From isanbard at gmail.com  Mon Aug 25 00:33:05 2008
From: isanbard at gmail.com (Bill Wendling)
Date: Sun, 24 Aug 2008 22:33:05 -0700
Subject: [llvm-commits] [llvm] r55292 - in /llvm/trunk:
	lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/fold-call-2.ll
In-Reply-To: <43E9ED7E-44AA-46F5-BE8A-698A8B97762F@apple.com>
References: <200808241919.m7OJJuZf013766@zion.cs.uiuc.edu>
	<F73AEC1C-1C03-4176-ABBB-705C8E4EC42A@gmail.com>
	<43E9ED7E-44AA-46F5-BE8A-698A8B97762F@apple.com>
Message-ID: <420CC131-B52A-491D-BAB6-E4A724FD296E@gmail.com>

Here you go.

-bw

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On Aug 24, 2008, at 9:04 PM, Evan Cheng wrote:

> Strangness. I was able to do a Apple style build with the patch. Any
> chance you can get me a bc file?
>
> Evan
>
> On Aug 24, 2008, at 2:45 PM, Bill Wendling wrote:
>
>> Evan,
>>
>> I think that this patch was causing a bootstrap failure:
>>
>> /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/ 
>> xgcc
>> -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./ 
>> gcc/ -
>> B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/ 
>> i386-
>> apple-darwin9.4.0/bin/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/
>> build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/ -isystem /Volumes/
>> Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-
>> darwin9.4.0/include -isystem /Volumes/Sandbox/Buildbot/llvm/full- 
>> llvm/
>> build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include -c -
>> DHAVE_CONFIG_H -O2 -g -O2   -m64 -I. -I../../../../llvm-gcc.src/
>> libiberty/../include  -W -Wall -pedantic -Wwrite-strings -Wstrict-
>> prototypes -Wc++-compat ../../../../llvm-gcc.src/libiberty/make-temp-
>> file.c -o make-temp-file.o
>> Assertion failed: (Node2Index[SU->NodeNum] > Node2Index[I->Dep-
>>> NodeNum] && "Wrong topological sorting"), function
>> InitDAGTopologicalSorting, file /Volumes/Sandbox/Buildbot/llvm/full-
>> llvm/build/llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp,
>> line 508.
>> ../../../../llvm-gcc.src/libiberty/hashtab.c:955: internal compiler
>> error: Abort trap
>> Please submit a full bug report,
>> with preprocessed source if appropriate.
>> See <URL:http://developer.apple.com/bugreporter> for instructions.
>> make[4]: *** [hashtab.o] Error 1
>> make[4]: *** Waiting for unfinished jobs....
>> make[3]: *** [multi-do] Error 1
>> make[2]: *** [all] Error 2
>> make[1]: *** [all-target-libiberty] Error 2
>> make: *** [all] Error 2
>>
>> I temporarily reverted it.
>>
>> -bw
>>
>> On Aug 24, 2008, at 12:19 PM, Evan Cheng wrote:
>>
>>> Author: evancheng
>>> Date: Sun Aug 24 14:19:55 2008
>>> New Revision: 55292
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=55292&view=rev
>>> Log:
>>> Move callseq_start above the call address load to allow load to be
>>> folded into the call node.
>>>
>>> Added:
>>>  llvm/trunk/test/CodeGen/X86/fold-call-2.ll
>>> Modified:
>>>  llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>>>
>>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=55292&r1=55291&r2=55292&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> = 
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
>>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Aug 24
>>> 14:19:55 2008
>>> @@ -1457,12 +1457,12 @@
>>>
>>> SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG  
>>> &DAG) {
>>> MachineFunction &MF = DAG.getMachineFunction();
>>> -  SDValue Chain     = Op.getOperand(0);
>>> +  SDValue Chain       = Op.getOperand(0);
>>> unsigned CC         = cast<ConstantSDNode>(Op.getOperand(1))-
>>>> getValue();
>>> bool isVarArg       = cast<ConstantSDNode>(Op.getOperand(2))-
>>>> getValue() != 0;
>>> bool IsTailCall     = cast<ConstantSDNode>(Op.getOperand(3))-
>>>> getValue() != 0
>>>                       && CC == CallingConv::Fast &&
>>> PerformTailCallOpt;
>>> -  SDValue Callee    = Op.getOperand(4);
>>> +  SDValue Callee      = Op.getOperand(4);
>>> bool Is64Bit        = Subtarget->is64Bit();
>>> bool IsStructRet    = CallIsStructReturn(Op);
>>>
>>> @@ -1499,6 +1499,11 @@
>>>     MF.getInfo<X86MachineFunctionInfo>()-
>>>> setTCReturnAddrDelta(FPDiff);
>>> }
>>>
>>> +  // If the address is a load, i.e. indirect function call, move
>>> callseq_start
>>> +  // above the load. This makes it possible for the load to fold
>>> into the call.
>>> +  if (Callee.Val == Chain.Val && ISD::isNormalLoad(Callee.Val) &&
>>> +      Chain.hasOneUse() && Callee.hasOneUse())
>>> +    Chain = Chain.getOperand(0);
>>> Chain = DAG.getCALLSEQ_START(Chain,
>>> DAG.getIntPtrConstant(NumBytes));
>>>
>>> SDValue RetAddrFrIdx;
>>>
>>> Added: llvm/trunk/test/CodeGen/X86/fold-call-2.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-call-2.ll?rev=55292&view=auto
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> = 
>>> ====================================================================
>>> --- llvm/trunk/test/CodeGen/X86/fold-call-2.ll (added)
>>> +++ llvm/trunk/test/CodeGen/X86/fold-call-2.ll Sun Aug 24 14:19:55
>>> 2008
>>> @@ -0,0 +1,10 @@
>>> +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | grep mov |
>>> count 1
>>> +
>>> + at f = external global void ()*		; <void ()**> [#uses=1]
>>> +
>>> +define i32 @main() nounwind {
>>> +entry:
>>> +	load void ()** @f, align 8		; <void ()*>:0 [#uses=1]
>>> +	tail call void %0( ) nounwind
>>> +	ret i32 0
>>> +}
>>>
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From ggreif at gmail.com  Mon Aug 25 11:27:00 2008
From: ggreif at gmail.com (Gabor Greif)
Date: Mon, 25 Aug 2008 16:27:00 -0000
Subject: [llvm-commits] [llvm] r55314 -
	/llvm/branches/ggreif/parallelized-test/lib/llvm.exp
Message-ID: <200808251627.m7PGR0lY001163@zion.cs.uiuc.edu>

Author: ggreif
Date: Mon Aug 25 11:26:59 2008
New Revision: 55314

URL: http://llvm.org/viewvc/llvm-project?rev=55314&view=rev
Log:
merge r52172:r54474 from trunk

Modified:
    llvm/branches/ggreif/parallelized-test/lib/llvm.exp

Modified: llvm/branches/ggreif/parallelized-test/lib/llvm.exp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/parallelized-test/lib/llvm.exp?rev=55314&r1=55313&r2=55314&view=diff

==============================================================================
--- llvm/branches/ggreif/parallelized-test/lib/llvm.exp (original)
+++ llvm/branches/ggreif/parallelized-test/lib/llvm.exp Mon Aug 25 11:26:59 2008
@@ -57,9 +57,9 @@
   #replace %prcontext with prcontext.tcl (Must replace before %p)
   regsub -all {%prcontext} $new_line $prcontext new_line
   #replace %llvmgcc with actual path to llvmgcc
-  regsub -all {%llvmgcc} $new_line "$llvmgcc -emit-llvm" new_line
+  regsub -all {%llvmgcc} $new_line "$llvmgcc -emit-llvm -w" new_line
   #replace %llvmgxx with actual path to llvmg++
-  regsub -all {%llvmgxx} $new_line "$llvmgxx -emit-llvm" new_line
+  regsub -all {%llvmgxx} $new_line "$llvmgxx -emit-llvm -w" new_line
   #replace %compile_cxx with C++ compilation command
   regsub -all {%compile_cxx} $new_line "$compile_cxx" new_line
   #replace %compile_c with C compilation command
@@ -313,9 +313,9 @@
     ada     { set file gnat1 }
     c       { set file cc1 }
     c++     { set file cc1plus }
-    objc    { set file cc1 }
-    objc++  { set file cc1 }
-    fortran { set file fcc1 }
+    objc    { set file cc1obj }
+    objc++  { set file cc1objplus }
+    fortran { set file f951 }
     default { return 0 }
   }
   foreach supported_lang [split "$llvmgcc_langs" ,] {




From sabre at nondot.org  Mon Aug 25 12:03:16 2008
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 25 Aug 2008 17:03:16 -0000
Subject: [llvm-commits] [llvm] r55315 - /llvm/trunk/lib/VMCore/AsmWriter.cpp
Message-ID: <200808251703.m7PH3HPL002639@zion.cs.uiuc.edu>

Author: lattner
Date: Mon Aug 25 12:03:15 2008
New Revision: 55315

URL: http://llvm.org/viewvc/llvm-project?rev=55315&view=rev
Log:
Fix pasto (values -> types) noticed by Josh Conner

Modified:
    llvm/trunk/lib/VMCore/AsmWriter.cpp

Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=55315&r1=55314&r2=55315&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/trunk/lib/VMCore/AsmWriter.cpp Mon Aug 25 12:03:15 2008
@@ -1788,15 +1788,13 @@
   print(OS, AAW);
 }
 
-// Value::dump - allow easy printing of  Values from the debugger.
-// Located here because so much of the needed functionality is here.
+// Value::dump - allow easy printing of Values from the debugger.
 void Value::dump() const { print(errs()); errs() << '\n'; errs().flush(); }
 
-// Type::dump - allow easy printing of  Values from the debugger.
-// Located here because so much of the needed functionality is here.
+// Type::dump - allow easy printing of Types from the debugger.
 void Type::dump() const { print(errs()); errs() << '\n'; errs().flush(); }
 
-// Module::dump() - Allow printing from debugger
+// Module::dump() - Allow printing of Modules from the debugger.
 void Module::dump() const { print(errs(), 0); errs().flush(); }
 
 




From isanbard at gmail.com  Mon Aug 25 13:20:53 2008
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 25 Aug 2008 18:20:53 -0000
Subject: [llvm-commits] [llvm] r55317 - in /llvm/trunk/lib/Target/X86:
 X86InstrFormats.td X86InstrMMX.td
Message-ID: <200808251820.m7PIKraY005150@zion.cs.uiuc.edu>

Author: void
Date: Mon Aug 25 13:20:52 2008
New Revision: 55317

URL: http://llvm.org/viewvc/llvm-project?rev=55317&view=rev
Log:
MOVQ2DQ and MOVQ2DQ use SSE2. We should conditionalize the use of these
instructions on having SSE2.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrFormats.td
    llvm/trunk/lib/Target/X86/X86InstrMMX.td

Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=55317&r1=55316&r2=55317&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Mon Aug 25 13:20:52 2008
@@ -157,16 +157,20 @@
 
 // SSE2 Instruction Templates:
 // 
-//   SDI   - SSE2 instructions with XD prefix.
-//   SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
-//   PDI   - SSE2 instructions with TB and OpSize prefixes.
-//   PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
+//   SDI    - SSE2 instructions with XD prefix.
+//   SDIi8  - SSE2 instructions with ImmT == Imm8 and XD prefix.
+//   SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
+//   PDI    - SSE2 instructions with TB and OpSize prefixes.
+//   PDIi8  - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
 
 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
       : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
             list<dag> pattern>
       : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
+class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
+             list<dag> pattern>
+      : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
       : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,

Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=55317&r1=55316&r2=55317&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Mon Aug 25 13:20:52 2008
@@ -173,15 +173,15 @@
                         "movq\t{$src, $dst|$dst, $src}",
                         [(store (v1i64 VR64:$src), addr:$dst)]>;
 
-def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
+def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
                           "movdq2q\t{$src, $dst|$dst, $src}",
                           [(set VR64:$dst,
                             (v1i64 (bitconvert
                             (i64 (vector_extract (v2i64 VR128:$src),
                                   (iPTR 0))))))]>;
 
-def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
-                          "movq2dq\t{$src, $dst|$dst, $src}",
+def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
+                           "movq2dq\t{$src, $dst|$dst, $src}",
           [(set VR128:$dst,
                 (v2i64 (vector_shuffle immAllZerosV,
                         (v2i64 (scalar_to_vector (i64 (bitconvert VR64:$src)))),




From isanbard at gmail.com  Mon Aug 25 13:32:39 2008
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 25 Aug 2008 18:32:39 -0000
Subject: [llvm-commits] [llvm] r55318 - in /llvm/trunk/lib/Target/X86:
 X86InstrFormats.td X86InstrMMX.td
Message-ID: <200808251832.m7PIWdiQ005650@zion.cs.uiuc.edu>

Author: void
Date: Mon Aug 25 13:32:39 2008
New Revision: 55318

URL: http://llvm.org/viewvc/llvm-project?rev=55318&view=rev
Log:
Nevermind. This broke the bootstrap (?!).

Modified:
    llvm/trunk/lib/Target/X86/X86InstrFormats.td
    llvm/trunk/lib/Target/X86/X86InstrMMX.td

Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=55318&r1=55317&r2=55318&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Mon Aug 25 13:32:39 2008
@@ -157,20 +157,16 @@
 
 // SSE2 Instruction Templates:
 // 
-//   SDI    - SSE2 instructions with XD prefix.
-//   SDIi8  - SSE2 instructions with ImmT == Imm8 and XD prefix.
-//   SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
-//   PDI    - SSE2 instructions with TB and OpSize prefixes.
-//   PDIi8  - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
+//   SDI   - SSE2 instructions with XD prefix.
+//   SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
+//   PDI   - SSE2 instructions with TB and OpSize prefixes.
+//   PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
 
 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
       : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
             list<dag> pattern>
       : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
-class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
-             list<dag> pattern>
-      : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
       : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,

Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=55318&r1=55317&r2=55318&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Mon Aug 25 13:32:39 2008
@@ -173,15 +173,15 @@
                         "movq\t{$src, $dst|$dst, $src}",
                         [(store (v1i64 VR64:$src), addr:$dst)]>;
 
-def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
+def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
                           "movdq2q\t{$src, $dst|$dst, $src}",
                           [(set VR64:$dst,
                             (v1i64 (bitconvert
                             (i64 (vector_extract (v2i64 VR128:$src),
                                   (iPTR 0))))))]>;
 
-def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
-                           "movq2dq\t{$src, $dst|$dst, $src}",
+def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
+                          "movq2dq\t{$src, $dst|$dst, $src}",
           [(set VR128:$dst,
                 (v2i64 (vector_shuffle immAllZerosV,
                         (v2i64 (scalar_to_vector (i64 (bitconvert VR64:$src)))),




From dalej at apple.com  Mon Aug 25 13:53:26 2008
From: dalej at apple.com (Dale Johannesen)
Date: Mon, 25 Aug 2008 18:53:26 -0000
Subject: [llvm-commits] [llvm] r55319 -
	/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
Message-ID: <200808251853.m7PIrRWR006543@zion.cs.uiuc.edu>

Author: johannes
Date: Mon Aug 25 13:53:26 2008
New Revision: 55319

URL: http://llvm.org/viewvc/llvm-project?rev=55319&view=rev
Log:
It's important for the cmp-and-swap to balance
loads and stores but it's even more important for
it to store the right value.:(


Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=55319&r1=55318&r2=55319&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Aug 25 13:53:26 2008
@@ -4040,38 +4040,56 @@
     unsigned oldval = MI->getOperand(3).getReg();
     unsigned newval = MI->getOperand(4).getReg();
 
-    MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
     MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
-    F->insert(It, loopMBB);
+    F->insert(It, loop1MBB);
+    F->insert(It, loop2MBB);
+    F->insert(It, midMBB);
     F->insert(It, exitMBB);
     exitMBB->transferSuccessors(BB);
 
     //  thisMBB:
     //   ...
     //   fallthrough --> loopMBB
-    BB->addSuccessor(loopMBB);
+    BB->addSuccessor(loop1MBB);
 
-    //  loopMBB:
+    // loop1MBB:
     //   l[wd]arx dest, ptr
-    //   cmp[wd] CR1, dest, oldval
+    //   cmp[wd] dest, oldval
+    //   bne- midMBB
+    // loop2MBB:
     //   st[wd]cx. newval, ptr
-    //   bne- CR1, exitMBB
     //   bne- loopMBB
-    //   fallthrough --> exitMBB
-    BB = loopMBB;
+    //   b exitBB
+    // midMBB:
+    //   st[wd]cx. dest, ptr
+    // exitBB:
+    BB = loop1MBB;
     BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
       .addReg(ptrA).addReg(ptrB);
-    BuildMI(BB, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR1)
+    BuildMI(BB, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
       .addReg(oldval).addReg(dest);
+    BuildMI(BB, TII->get(PPC::BCC))
+      .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
+    BB->addSuccessor(loop2MBB);
+    BB->addSuccessor(midMBB);
+
+    BB = loop2MBB;
     BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
       .addReg(newval).addReg(ptrA).addReg(ptrB);
     BuildMI(BB, TII->get(PPC::BCC))
-      .addImm(PPC::PRED_NE).addReg(PPC::CR1).addMBB(exitMBB);
-    BuildMI(BB, TII->get(PPC::BCC))
-      .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);    
-    BB->addSuccessor(loopMBB);
+      .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
+    BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB);
+    BB->addSuccessor(loop1MBB);
     BB->addSuccessor(exitMBB);
     
+    BB = midMBB;
+    BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
+      .addReg(dest).addReg(ptrA).addReg(ptrB);
+    BB->addSuccessor(exitMBB);
+
     //  exitMBB:
     //   ...
     BB = exitMBB;




From dalej at apple.com  Mon Aug 25 13:53:59 2008
From: dalej at apple.com (Dale Johannesen)
Date: Mon, 25 Aug 2008 18:53:59 -0000
Subject: [llvm-commits] [llvm] r55320 - in /llvm/trunk/test/CodeGen/PowerPC:
	atomic-1.ll atomic-2.ll
Message-ID: <200808251853.m7PIrxoR006569@zion.cs.uiuc.edu>

Author: johannes
Date: Mon Aug 25 13:53:58 2008
New Revision: 55320

URL: http://llvm.org/viewvc/llvm-project?rev=55320&view=rev
Log:
Adjust grep's for new code sequence.


Modified:
    llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll
    llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll

Modified: llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll?rev=55320&r1=55319&r2=55320&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll Mon Aug 25 13:53:58 2008
@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc -march=ppc32 | grep lwarx  | count 3
-; RUN: llvm-as < %s | llc -march=ppc32 | grep stwcx. | count 3
+; RUN: llvm-as < %s | llc -march=ppc32 | grep stwcx. | count 4
 
 define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind  {
 	%tmp = call i32 @llvm.atomic.load.add.i32( i32* %mem, i32 %val )

Modified: llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll?rev=55320&r1=55319&r2=55320&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll Mon Aug 25 13:53:58 2008
@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc -march=ppc64 | grep ldarx  | count 3
-; RUN: llvm-as < %s | llc -march=ppc64 | grep stdcx. | count 3
+; RUN: llvm-as < %s | llc -march=ppc64 | grep stdcx. | count 4
 
 define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind  {
 	%tmp = call i64 @llvm.atomic.load.add.i64( i64* %mem, i64 %val )




From gohman at apple.com  Mon Aug 25 14:47:50 2008
From: gohman at apple.com (Dan Gohman)
Date: Mon, 25 Aug 2008 12:47:50 -0700
Subject: [llvm-commits] [llvm] r55301 -
	/llvm/trunk/lib/VMCore/AsmWriter.cpp
In-Reply-To: <200808250455.m7P4tlYn030553@zion.cs.uiuc.edu>
References: <200808250455.m7P4tlYn030553@zion.cs.uiuc.edu>
Message-ID: <3A24A57D-5611-4273-86CD-F420C77CB634@apple.com>



On Aug 24, 2008, at 9:55 PM, Chris Lattner wrote:
> // Value::dump - allow easy printing of  Values from the debugger.
> // Located here because so much of the needed functionality is here.
> -void Value::dump() const { print(errs()); errs() << '\n'; }
> +void Value::dump() const { print(errs()); errs() << '\n';  
> errs().flush(); }
>
> // Type::dump - allow easy printing of  Values from the debugger.
> // Located here because so much of the needed functionality is here.
> -void Type::dump() const { print(errs()); errs() << '\n'; }
> +void Type::dump() const { print(errs()); errs() << '\n';  
> errs().flush(); }
>
> // Module::dump() - Allow printing from debugger
> -void Module::dump() const { print(errs(), 0); }
> +void Module::dump() const { print(errs(), 0); errs().flush(); }

It's surprising that this is necessary. For comparison, stderr is
unbuffered by default. Wouldn't it be better to make errs() return
a non-buffered stream?

Dan



From gohman at apple.com  Mon Aug 25 14:51:08 2008
From: gohman at apple.com (Dan Gohman)
Date: Mon, 25 Aug 2008 12:51:08 -0700
Subject: [llvm-commits] [llvm] r55292 - in /llvm/trunk:
	lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/fold-call-2.ll
In-Reply-To: <200808241919.m7OJJuZf013766@zion.cs.uiuc.edu>
References: <200808241919.m7OJJuZf013766@zion.cs.uiuc.edu>
Message-ID: <33103040-5633-4BCD-A250-56C247FB7282@apple.com>


On Aug 24, 2008, at 12:19 PM, Evan Cheng wrote:

> Author: evancheng
> Date: Sun Aug 24 14:19:55 2008
> New Revision: 55292
>
> URL: http://llvm.org/viewvc/llvm-project?rev=55292&view=rev
> Log:
> Move callseq_start above the call address load to allow load to be  
> folded into the call node.

What happens if the callseq_start involves a non-trivial stack
pointer adjustment and the load's address is spilled and needs
to be reloaded? Could this change cause the reload to happen
from the wrong stack location?

Dan



From resistor at mac.com  Mon Aug 25 15:20:33 2008
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Aug 2008 20:20:33 -0000
Subject: [llvm-commits] [llvm] r55325 - in /llvm/trunk:
 include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp
 test/CodeGen/X86/fast-isel.ll utils/TableGen/FastISelEmitter.cpp
Message-ID: <200808252020.m7PKKXKK010461@zion.cs.uiuc.edu>

Author: resistor
Date: Mon Aug 25 15:20:32 2008
New Revision: 55325

URL: http://llvm.org/viewvc/llvm-project?rev=55325&view=rev
Log:
Add support for fast isel of (integer) immediate materialization pattens, and use them to support
bitcast of constants in fast isel.

Modified:
    llvm/trunk/include/llvm/CodeGen/FastISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
    llvm/trunk/test/CodeGen/X86/fast-isel.ll
    llvm/trunk/utils/TableGen/FastISelEmitter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=55325&r1=55324&r2=55325&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Mon Aug 25 15:20:32 2008
@@ -81,11 +81,6 @@
                                ISD::NodeType Opcode,
                                unsigned Op0, unsigned Op1);
 
-  /// FastEmit_i - This method is called by target-independent code
-  /// to request that an instruction with the given type which materialize
-  /// the specified immediate value.
-  virtual unsigned FastEmit_i(MVT::SimpleValueType VT, uint64_t Imm);
-
   /// FastEmit_ri - This method is called by target-independent code
   /// to request that an instruction with the given type, opcode, and
   /// register and immediate operands be emitted.
@@ -110,6 +105,13 @@
                         ISD::NodeType Opcode,
                         unsigned Op0, uint64_t Imm,
                         MVT::SimpleValueType ImmType);
+  
+  /// FastEmit_i - This method is called by target-independent code
+  /// to request that an instruction with the given type, opcode, and
+  /// immediate operand be emitted.
+  virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
+                              ISD::NodeType Opcode,
+                              uint64_t Imm);
 
   /// FastEmitInst_ - Emit a MachineInstr with no operands and a
   /// result register in the given register class.
@@ -144,6 +146,12 @@
   unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
                             const TargetRegisterClass *RC,
                             unsigned Op0, unsigned Op1, uint64_t Imm);
+  
+  /// FastEmitInst_i - Emit a MachineInstr with a single immediate
+  /// operand, and a result register in the given register class.
+  unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
+                          const TargetRegisterClass *RC,
+                          uint64_t Imm);
 
 private:
   unsigned createResultReg(const TargetRegisterClass *RC);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55325&r1=55324&r2=55325&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Aug 25 15:20:32 2008
@@ -221,6 +221,22 @@
     case Instruction::PHI:
       // PHI nodes are already emitted.
       break;
+      
+    case Instruction::BitCast:
+      // BitCast consists of either an immediate to register move
+      // or a register to register move.
+      if (ConstantInt* CI = dyn_cast<ConstantInt>(I->getOperand(0))) {
+        if (I->getType()->isInteger()) {
+          MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/false);
+          ValueMap[I] = FastEmit_i(VT.getSimpleVT(), ISD::Constant,
+                                   CI->getZExtValue());
+          break;
+        } else
+          // TODO: Support vector and fp constants.
+          return I;
+      } else
+        // TODO: Support non-constant bitcasts.
+        return I;
 
     default:
       // Unhandled instruction. Halt "fast" selection and bail.
@@ -256,7 +272,8 @@
   return 0;
 }
 
-unsigned FastISel::FastEmit_i(MVT::SimpleValueType, uint64_t /*Imm*/) {
+unsigned FastISel::FastEmit_i(MVT::SimpleValueType, ISD::NodeType,
+                              uint64_t /*Imm*/) {
   return 0;
 }
 
@@ -284,7 +301,7 @@
     ResultReg = FastEmit_ri(VT, Opcode, Op0, Imm);
   if (ResultReg != 0)
     return ResultReg;
-  unsigned MaterialReg = FastEmit_i(ImmType, Imm);
+  unsigned MaterialReg = FastEmit_i(ImmType, ISD::Constant, Imm);
   if (MaterialReg == 0)
     return 0;
   return FastEmit_rr(VT, Opcode, Op0, MaterialReg);
@@ -342,3 +359,13 @@
   BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
   return ResultReg;
 }
+
+unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
+                                  const TargetRegisterClass *RC,
+                                  uint64_t Imm) {
+  unsigned ResultReg = createResultReg(RC);
+  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
+  
+  BuildMI(MBB, II, ResultReg).addImm(Imm);
+  return ResultReg;
+}
\ No newline at end of file

Modified: llvm/trunk/test/CodeGen/X86/fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel.ll?rev=55325&r1=55324&r2=55325&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel.ll Mon Aug 25 15:20:32 2008
@@ -41,3 +41,8 @@
   ret double %t2
 }
 
+define i32 @cast(){
+entry:
+	%tmp2 = bitcast i32 0 to i32
+	ret i32 %tmp2
+}

Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=55325&r1=55324&r2=55325&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Mon Aug 25 15:20:32 2008
@@ -64,6 +64,12 @@
                   const CodeGenTarget &Target,
                   MVT::SimpleValueType VT,
                   const CodeGenRegisterClass *DstRC) {
+    if (!InstPatNode->isLeaf() &&
+        InstPatNode->getOperator()->getName() == "imm") {
+      Operands.push_back("i");
+      return true;
+    }
+    
     for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
       TreePatternNode *Op = InstPatNode->getChild(i);
       // For now, filter out any operand with a predicate.
@@ -219,9 +225,6 @@
     // an Operand or an immediate, like MOV32ri.
     if (InstPatOp->isSubClassOf("Operand"))
       continue;
-    if (InstPatOp->getName() == "imm" ||
-        InstPatOp->getName() == "fpimm")
-      continue;
 
     // For now, filter out any instructions with predicates.
     if (!InstPatNode->getPredicateFn().empty())




From kremenek at apple.com  Mon Aug 25 15:46:11 2008
From: kremenek at apple.com (Ted Kremenek)
Date: Mon, 25 Aug 2008 20:46:11 -0000
Subject: [llvm-commits] [llvm] r55329 - /llvm/tags/checker/checker-82/
Message-ID: <200808252046.m7PKkBjh011254@zion.cs.uiuc.edu>

Author: kremenek
Date: Mon Aug 25 15:46:11 2008
New Revision: 55329

URL: http://llvm.org/viewvc/llvm-project?rev=55329&view=rev
Log:
Tagging checker-82.

Added:
    llvm/tags/checker/checker-82/
      - copied from r55328, llvm/trunk/



From kremenek at apple.com  Mon Aug 25 15:54:58 2008
From: kremenek at apple.com (Ted Kremenek)
Date: Mon, 25 Aug 2008 20:54:58 -0000
Subject: [llvm-commits] [llvm] r55332 - /llvm/tags/checker/checker-82/
Message-ID: <200808252054.m7PKswbf011621@zion.cs.uiuc.edu>

Author: kremenek
Date: Mon Aug 25 15:54:58 2008
New Revision: 55332

URL: http://llvm.org/viewvc/llvm-project?rev=55332&view=rev
Log:
Removing checker-82.

Removed:
    llvm/tags/checker/checker-82/



From kremenek at apple.com  Mon Aug 25 15:55:37 2008
From: kremenek at apple.com (Ted Kremenek)
Date: Mon, 25 Aug 2008 20:55:37 -0000
Subject: [llvm-commits] [llvm] r55334 - /llvm/tags/checker/checker-82/
Message-ID: <200808252055.m7PKtbJK011683@zion.cs.uiuc.edu>

Author: kremenek
Date: Mon Aug 25 15:55:37 2008
New Revision: 55334

URL: http://llvm.org/viewvc/llvm-project?rev=55334&view=rev
Log:
Tagging checker-82.

Added:
    llvm/tags/checker/checker-82/
      - copied from r55333, llvm/trunk/



From dalej at apple.com  Mon Aug 25 16:09:52 2008
From: dalej at apple.com (Dale Johannesen)
Date: Mon, 25 Aug 2008 21:09:52 -0000
Subject: [llvm-commits] [llvm] r55336 - in /llvm/trunk/lib/Target/PowerPC:
 PPCISelLowering.cpp PPCISelLowering.h PPCInstr64Bit.td PPCInstrInfo.td
Message-ID: <200808252109.m7PL9qZP012093@zion.cs.uiuc.edu>

Author: johannes
Date: Mon Aug 25 16:09:52 2008
New Revision: 55336

URL: http://llvm.org/viewvc/llvm-project?rev=55336&view=rev
Log:
Remove PPC-specific lowering for atomics; the
generic stuff works fine.

Mark rewritten cmp-and-swap as not using CR1.


Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
    llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=55336&r1=55335&r2=55336&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Aug 25 16:09:52 2008
@@ -203,15 +203,6 @@
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64  , Custom);
 
-  setOperationAction(ISD::ATOMIC_LOAD_ADD   , MVT::i32  , Custom);
-  setOperationAction(ISD::ATOMIC_CMP_SWAP   , MVT::i32  , Custom);
-  setOperationAction(ISD::ATOMIC_SWAP       , MVT::i32  , Custom);
-  if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
-    setOperationAction(ISD::ATOMIC_LOAD_ADD , MVT::i64  , Custom);
-    setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i64  , Custom);
-    setOperationAction(ISD::ATOMIC_SWAP     , MVT::i64  , Custom);
-  }
-
   // We want to custom lower some of our intrinsics.
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
   
@@ -405,9 +396,6 @@
   case PPCISD::VCMPo:           return "PPCISD::VCMPo";
   case PPCISD::LBRX:            return "PPCISD::LBRX";
   case PPCISD::STBRX:           return "PPCISD::STBRX";
-  case PPCISD::ATOMIC_LOAD_ADD: return "PPCISD::ATOMIC_LOAD_ADD";
-  case PPCISD::ATOMIC_CMP_SWAP: return "PPCISD::ATOMIC_CMP_SWAP";
-  case PPCISD::ATOMIC_SWAP:     return "PPCISD::ATOMIC_SWAP";
   case PPCISD::LARX:            return "PPCISD::LARX";
   case PPCISD::STCX:            return "PPCISD::STCX";
   case PPCISD::COND_BRANCH:     return "PPCISD::COND_BRANCH";
@@ -2722,53 +2710,6 @@
   return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
 }
 
-SDValue PPCTargetLowering::LowerAtomicLOAD_ADD(SDValue Op, SelectionDAG &DAG) {
-  MVT VT = Op.Val->getValueType(0);
-  SDValue Chain   = Op.getOperand(0);
-  SDValue Ptr     = Op.getOperand(1);
-  SDValue Incr    = Op.getOperand(2);
-
-  SDVTList VTs = DAG.getVTList(VT, MVT::Other);
-  SDValue Ops[] = {
-    Chain,
-    Ptr,
-    Incr,
-  };
-  return DAG.getNode(PPCISD::ATOMIC_LOAD_ADD, VTs, Ops, 3);
-}
-
-SDValue PPCTargetLowering::LowerAtomicCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
-  MVT VT = Op.Val->getValueType(0);
-  SDValue Chain   = Op.getOperand(0);
-  SDValue Ptr     = Op.getOperand(1);
-  SDValue NewVal  = Op.getOperand(2);
-  SDValue OldVal  = Op.getOperand(3);
-
-  SDVTList VTs = DAG.getVTList(VT, MVT::Other);
-  SDValue Ops[] = {
-    Chain,
-    Ptr,
-    OldVal,
-    NewVal,
-  };
-  return DAG.getNode(PPCISD::ATOMIC_CMP_SWAP, VTs, Ops, 4);
-}
-
-SDValue PPCTargetLowering::LowerAtomicSWAP(SDValue Op, SelectionDAG &DAG) {
-  MVT VT = Op.Val->getValueType(0);
-  SDValue Chain   = Op.getOperand(0);
-  SDValue Ptr     = Op.getOperand(1);
-  SDValue NewVal  = Op.getOperand(2);
-
-  SDVTList VTs = DAG.getVTList(VT, MVT::Other);
-  SDValue Ops[] = {
-    Chain,
-    Ptr,
-    NewVal,
-  };
-  return DAG.getNode(PPCISD::ATOMIC_SWAP, VTs, Ops, 3);
-}
-
 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
 /// possible.
 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
@@ -3876,10 +3817,6 @@
   case ISD::DYNAMIC_STACKALLOC:
     return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
 
-  case ISD::ATOMIC_LOAD_ADD:    return LowerAtomicLOAD_ADD(Op, DAG);
-  case ISD::ATOMIC_CMP_SWAP:    return LowerAtomicCMP_SWAP(Op, DAG);
-  case ISD::ATOMIC_SWAP:        return LowerAtomicSWAP(Op, DAG);
-    
   case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
   case ISD::FP_TO_SINT:         return LowerFP_TO_SINT(Op, DAG);
   case ISD::SINT_TO_FP:         return LowerSINT_TO_FP(Op, DAG);

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=55336&r1=55335&r2=55336&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Mon Aug 25 16:09:52 2008
@@ -152,11 +152,6 @@
       /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
       MTFSF,
 
-      /// ATOMIC_LOAD_ADD, ATOMIC_CMP_SWAP, ATOMIC_SWAP - These
-      /// correspond to the llvm.atomic.load.add, llvm.atomic.cmp.swap
-      /// and llvm.atomic.swap intrinsics.
-      ATOMIC_LOAD_ADD, ATOMIC_CMP_SWAP, ATOMIC_SWAP,
-
       /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
       /// reserve indexed. This is used to implement atomic operations.
       LARX,
@@ -363,9 +358,6 @@
     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
                                       const PPCSubtarget &Subtarget);
     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
-    SDValue LowerAtomicLOAD_ADD(SDValue Op, SelectionDAG &DAG);
-    SDValue LowerAtomicCMP_SWAP(SDValue Op, SelectionDAG &DAG);
-    SDValue LowerAtomicSWAP(SDValue Op, SelectionDAG &DAG);
     SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG);
     SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
     SDValue LowerFP_ROUND_INREG(SDValue Op, SelectionDAG &DAG);

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=55336&r1=55335&r2=55336&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Mon Aug 25 16:09:52 2008
@@ -122,18 +122,16 @@
     def ATOMIC_LOAD_ADD_I64 : Pseudo<
       (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
       "${:comment} ATOMIC_LOAD_ADD_I64 PSEUDO!",
-      [(set G8RC:$dst, (PPCatomic_load_add xoaddr:$ptr, G8RC:$incr))]>;
-    def ATOMIC_SWAP_I64 : Pseudo<
-      (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new),
-      "${:comment} ATOMIC_SWAP_I64 PSEUDO!",
-      [(set G8RC:$dst, (PPCatomic_swap xoaddr:$ptr, G8RC:$new))]>;
-  }
-  let Uses = [CR0, CR1] in {
+      [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>;
     def ATOMIC_CMP_SWAP_I64 : Pseudo<
       (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new),
       "${:comment} ATOMIC_CMP_SWAP_I64 PSEUDO!",
       [(set G8RC:$dst, 
-                    (PPCatomic_cmp_swap xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
+                    (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
+    def ATOMIC_SWAP_I64 : Pseudo<
+      (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new),
+      "${:comment} ATOMIC_SWAP_I64 PSEUDO!",
+      [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>;
   }
 }
 

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=55336&r1=55335&r2=55336&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Mon Aug 25 16:09:52 2008
@@ -42,16 +42,6 @@
   SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
 ]>;
 
-def SDT_PPCatomic_load_add : SDTypeProfile<1, 2, [
-  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>
-]>;
-def SDT_PPCatomic_cmp_swap : SDTypeProfile<1, 3, [
-  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>, SDTCisInt<3>
-]>;
-def SDT_PPCatomic_swap : SDTypeProfile<1, 2, [
-  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>
-]>;
-
 def SDT_PPClarx : SDTypeProfile<1, 1, [
   SDTCisInt<0>, SDTCisPtrTy<1>
 ]>;
@@ -149,17 +139,6 @@
 def PPCstbrx      : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
                            [SDNPHasChain, SDNPMayStore]>;
 
-// Atomic operations
-def PPCatomic_load_add : SDNode<"PPCISD::ATOMIC_LOAD_ADD",
-                                SDT_PPCatomic_load_add,
-                                [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
-def PPCatomic_cmp_swap : SDNode<"PPCISD::ATOMIC_CMP_SWAP",
-                                SDT_PPCatomic_cmp_swap,
-                                [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
-def PPCatomic_swap : SDNode<"PPCISD::ATOMIC_SWAP",
-                            SDT_PPCatomic_swap,
-                            [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
-
 // Instructions to support atomic operations
 def PPClarx      : SDNode<"PPCISD::LARX", SDT_PPClarx,
                           [SDNPHasChain, SDNPMayLoad]>;
@@ -552,18 +531,16 @@
     def ATOMIC_LOAD_ADD_I32 : Pseudo<
       (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
       "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
-      [(set GPRC:$dst, (PPCatomic_load_add xoaddr:$ptr, GPRC:$incr))]>;
-    def ATOMIC_SWAP_I32 : Pseudo<
-      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
-      "${:comment} ATOMIC_SWAP_I32 PSEUDO!",
-      [(set GPRC:$dst, (PPCatomic_swap xoaddr:$ptr, GPRC:$new))]>;
-  }
-  let Uses = [CR0, CR1] in {
+      [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
     def ATOMIC_CMP_SWAP_I32 : Pseudo<
       (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
       "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
       [(set GPRC:$dst, 
-                    (PPCatomic_cmp_swap xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
+                    (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
+    def ATOMIC_SWAP_I32 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
+      "${:comment} ATOMIC_SWAP_I32 PSEUDO!",
+      [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
   }
 }
 




From evan.cheng at apple.com  Mon Aug 25 16:27:19 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 25 Aug 2008 21:27:19 -0000
Subject: [llvm-commits] [llvm] r55338 - in /llvm/trunk:
 lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp
 test/CodeGen/X86/fold-call-2.ll
Message-ID: <200808252127.m7PLRJ0a012663@zion.cs.uiuc.edu>

Author: evancheng
Date: Mon Aug 25 16:27:18 2008
New Revision: 55338

URL: http://llvm.org/viewvc/llvm-project?rev=55338&view=rev
Log:
Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/fold-call-2.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=55338&r1=55337&r2=55338&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Aug 25 16:27:18 2008
@@ -373,12 +373,12 @@
 /// load's chain result.
 static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
                                  SDValue Store, SDValue TF) {
-  std::vector<SDValue> Ops;
+  SmallVector<SDValue, 4> Ops;
   for (unsigned i = 0, e = TF.Val->getNumOperands(); i != e; ++i)
-    if (Load.Val == TF.Val->getOperand(i).Val)
-      Ops.push_back(Load.Val->getOperand(0));
+    if (Load.Val == TF.getOperand(i).Val)
+      Ops.push_back(Load.getOperand(0));
     else
-      Ops.push_back(TF.Val->getOperand(i));
+      Ops.push_back(TF.getOperand(i));
   CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
   CurDAG->UpdateNodeOperands(Load, TF, Load.getOperand(1), Load.getOperand(2));
   CurDAG->UpdateNodeOperands(Store, Load.getValue(1), Store.getOperand(1),
@@ -411,6 +411,49 @@
   return false;
 }
 
+/// MoveBelowCallSeqStart - Replace CALLSEQ_START operand with load's chain
+/// operand and move load below the call's chain operand.
+static void MoveBelowCallSeqStart(SelectionDAG *CurDAG, SDValue Load,
+                           SDValue Call, SDValue Chain) {
+  SmallVector<SDValue, 8> Ops;
+  for (unsigned i = 0, e = Chain.Val->getNumOperands(); i != e; ++i)
+    if (Load.Val == Chain.getOperand(i).Val)
+      Ops.push_back(Load.getOperand(0));
+    else
+      Ops.push_back(Chain.getOperand(i));
+  CurDAG->UpdateNodeOperands(Chain, &Ops[0], Ops.size());
+  CurDAG->UpdateNodeOperands(Load, Call.getOperand(0),
+                             Load.getOperand(1), Load.getOperand(2));
+  Ops.clear();
+  Ops.push_back(SDValue(Load.Val, 1));
+  for (unsigned i = 1, e = Call.Val->getNumOperands(); i != e; ++i)
+    Ops.push_back(Call.getOperand(i));
+  CurDAG->UpdateNodeOperands(Call, &Ops[0], Ops.size());
+}
+
+/// isCalleeLoad - Return true if call address is a load and it can be
+/// moved below CALLSEQ_START and the chains leading up to the call.
+/// Return the CALLSEQ_START by reference as a second output.
+static bool isCalleeLoad(SDValue Callee, SDValue &Chain) {
+  if (Callee.Val == Chain.Val || !Callee.hasOneUse())
+    return false;
+  LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.Val);
+  if (!LD ||
+      LD->isVolatile() ||
+      LD->getAddressingMode() != ISD::UNINDEXED ||
+      LD->getExtensionType() != ISD::NON_EXTLOAD)
+    return false;
+
+  // Now let's find the callseq_start.
+  while (Chain.getOpcode() != ISD::CALLSEQ_START) {
+    if (!Chain.hasOneUse())
+      return false;
+    Chain = Chain.getOperand(0);
+  }
+  return Chain.getOperand(0).Val == Callee.Val;
+}
+
+
 /// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
 /// This is only run if not in -fast mode (aka -O0).
 /// This allows the instruction selector to pick more read-modify-write
@@ -454,9 +497,39 @@
 void X86DAGToDAGISel::PreprocessForRMW() {
   for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
          E = CurDAG->allnodes_end(); I != E; ++I) {
+    if (I->getOpcode() == X86ISD::CALL) {
+      /// Also try moving call address load from outside callseq_start to just
+      /// before the call to allow it to be folded.
+      ///
+      ///     [Load chain]
+      ///         ^
+      ///         |
+      ///       [Load]
+      ///       ^    ^
+      ///       |    |
+      ///      /      \--
+      ///     /          |
+      ///[CALLSEQ_START] |
+      ///     ^          |
+      ///     |          |
+      /// [LOAD/C2Reg]   |
+      ///     |          |
+      ///      \        /
+      ///       \      /
+      ///       [CALL]
+      SDValue Chain = I->getOperand(0);
+      SDValue Load  = I->getOperand(1);
+      if (!isCalleeLoad(Load, Chain))
+        continue;
+      MoveBelowCallSeqStart(CurDAG, Load, SDValue(I, 0), Chain);
+      ++NumLoadMoved;
+      continue;
+    }
+
     if (!ISD::isNON_TRUNCStore(I))
       continue;
     SDValue Chain = I->getOperand(0);
+
     if (Chain.Val->getOpcode() != ISD::TokenFactor)
       continue;
 
@@ -471,35 +544,35 @@
     SDValue Load;
     unsigned Opcode = N1.Val->getOpcode();
     switch (Opcode) {
-      case ISD::ADD:
-      case ISD::MUL:
-      case ISD::AND:
-      case ISD::OR:
-      case ISD::XOR:
-      case ISD::ADDC:
-      case ISD::ADDE:
-      case ISD::VECTOR_SHUFFLE: {
-        SDValue N10 = N1.getOperand(0);
-        SDValue N11 = N1.getOperand(1);
-        RModW = isRMWLoad(N10, Chain, N2, Load);
-        if (!RModW)
-          RModW = isRMWLoad(N11, Chain, N2, Load);
-        break;
-      }
-      case ISD::SUB:
-      case ISD::SHL:
-      case ISD::SRA:
-      case ISD::SRL:
-      case ISD::ROTL:
-      case ISD::ROTR:
-      case ISD::SUBC:
-      case ISD::SUBE:
-      case X86ISD::SHLD:
-      case X86ISD::SHRD: {
-        SDValue N10 = N1.getOperand(0);
-        RModW = isRMWLoad(N10, Chain, N2, Load);
-        break;
-      }
+    case ISD::ADD:
+    case ISD::MUL:
+    case ISD::AND:
+    case ISD::OR:
+    case ISD::XOR:
+    case ISD::ADDC:
+    case ISD::ADDE:
+    case ISD::VECTOR_SHUFFLE: {
+      SDValue N10 = N1.getOperand(0);
+      SDValue N11 = N1.getOperand(1);
+      RModW = isRMWLoad(N10, Chain, N2, Load);
+      if (!RModW)
+        RModW = isRMWLoad(N11, Chain, N2, Load);
+      break;
+    }
+    case ISD::SUB:
+    case ISD::SHL:
+    case ISD::SRA:
+    case ISD::SRL:
+    case ISD::ROTL:
+    case ISD::ROTR:
+    case ISD::SUBC:
+    case ISD::SUBE:
+    case X86ISD::SHLD:
+    case X86ISD::SHRD: {
+      SDValue N10 = N1.getOperand(0);
+      RModW = isRMWLoad(N10, Chain, N2, Load);
+      break;
+    }
     }
 
     if (RModW) {

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=55338&r1=55337&r2=55338&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Aug 25 16:27:18 2008
@@ -1457,12 +1457,12 @@
 
 SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
   MachineFunction &MF = DAG.getMachineFunction();
-  SDValue Chain     = Op.getOperand(0);
+  SDValue Chain       = Op.getOperand(0);
   unsigned CC         = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
   bool isVarArg       = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
   bool IsTailCall     = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0
                         && CC == CallingConv::Fast && PerformTailCallOpt;
-  SDValue Callee    = Op.getOperand(4);
+  SDValue Callee      = Op.getOperand(4);
   bool Is64Bit        = Subtarget->is64Bit();
   bool IsStructRet    = CallIsStructReturn(Op);
 

Modified: llvm/trunk/test/CodeGen/X86/fold-call-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-call-2.ll?rev=55338&r1=55337&r2=55338&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/fold-call-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fold-call-2.ll Mon Aug 25 16:27:18 2008
@@ -1,5 +1,4 @@
 ; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | grep mov | count 1
-; XFAIL: *
 
 @f = external global void ()*		; <void ()**> [#uses=1]
 




From resistor at mac.com  Mon Aug 25 16:32:34 2008
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Aug 2008 21:32:34 -0000
Subject: [llvm-commits] [llvm] r55340 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808252132.m7PLWY6b012844@zion.cs.uiuc.edu>

Author: resistor
Date: Mon Aug 25 16:32:34 2008
New Revision: 55340

URL: http://llvm.org/viewvc/llvm-project?rev=55340&view=rev
Log:
Expand bitcast support in fast isel to support bitcasts of non-constant values by emitting reg-reg copies.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55340&r1=55339&r2=55340&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Aug 25 16:32:34 2008
@@ -234,8 +234,36 @@
         } else
           // TODO: Support vector and fp constants.
           return I;
+      } else if (!isa<Constant>(I->getOperand(0))) {
+        // Bitcasts of non-constant values become reg-reg copies.
+        MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
+        MVT DstVT = MVT::getMVT(I->getOperand(0)->getType());
+        
+        if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
+            DstVT == MVT::Other || !DstVT.isSimple() ||
+            !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
+          // Unhandled type. Halt "fast" selection and bail.
+          return I;
+        if (!TLI.isConvertLegal(SrcVT, DstVT))
+          // Illegal conversion.  Halt "fast" selection and bail.
+          return I:
+        
+        // Otherwise, insert a register-to-register copy.
+        TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
+        TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
+        unsigned Op0 = ValueMap[I->getOperand(0)];
+        unsigned ResultReg = createResultReg(DstClass);
+        
+        if (Op0 == 0)
+          // Unhandled operand. Halt "fast" selection and bail.
+          return false;
+        
+        TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Op0, DstClass, SrcClass);
+        ValueMap[I] = ResultReg;
+        
+        break;
       } else
-        // TODO: Support non-constant bitcasts.
+        // Casting a non-integral constant?
         return I;
 
     default:




From evan.cheng at apple.com  Mon Aug 25 16:57:40 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 25 Aug 2008 14:57:40 -0700
Subject: [llvm-commits] [llvm] r55292 - in /llvm/trunk:
	lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/fold-call-2.ll
In-Reply-To: <33103040-5633-4BCD-A250-56C247FB7282@apple.com>
References: <200808241919.m7OJJuZf013766@zion.cs.uiuc.edu>
	<33103040-5633-4BCD-A250-56C247FB7282@apple.com>
Message-ID: <25F309AF-A954-43A1-AC17-B659C2381DAD@apple.com>

callseq_start is completely eliminated unless there is an alloca, but  
in that case FP is used to do reload. I think we are safe. Can you  
think of an unsafe situation?

Evan

On Aug 25, 2008, at 12:51 PM, Dan Gohman wrote:

>
> On Aug 24, 2008, at 12:19 PM, Evan Cheng wrote:
>
>> Author: evancheng
>> Date: Sun Aug 24 14:19:55 2008
>> New Revision: 55292
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=55292&view=rev
>> Log:
>> Move callseq_start above the call address load to allow load to be
>> folded into the call node.
>
> What happens if the callseq_start involves a non-trivial stack
> pointer adjustment and the load's address is spilled and needs
> to be reloaded? Could this change cause the reload to happen
> from the wrong stack location?
>
> Dan
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From evan.cheng at apple.com  Mon Aug 25 16:58:43 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 25 Aug 2008 21:58:43 -0000
Subject: [llvm-commits] [llvm] r55341 -
	/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
Message-ID: <200808252158.m7PLwhRj013596@zion.cs.uiuc.edu>

Author: evancheng
Date: Mon Aug 25 16:58:43 2008
New Revision: 55341

URL: http://llvm.org/viewvc/llvm-project?rev=55341&view=rev
Log:
80 col. violations.

Modified:
    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=55341&r1=55340&r2=55341&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon Aug 25 16:58:43 2008
@@ -343,8 +343,8 @@
 
       MachineInstr *New = 0;
       if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
-        New=BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
-          .addReg(StackPtr).addImm(Amount);
+        New = BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
+                      StackPtr).addReg(StackPtr).addImm(Amount);
       } else {
         assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
         // factor out the amount the callee already popped.
@@ -354,7 +354,8 @@
           unsigned Opc = (Amount < 128) ?
             (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
             (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
-          New = BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
+          New = BuildMI(MF, TII.get(Opc), StackPtr)
+            .addReg(StackPtr).addImm(Amount);
         }
       }
 




From evan.cheng at apple.com  Mon Aug 25 17:02:00 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 25 Aug 2008 15:02:00 -0700
Subject: [llvm-commits] [llvm] r55325 - in /llvm/trunk:
	include/llvm/CodeGen/FastISel.h
	lib/CodeGen/SelectionDAG/FastISel.cpp test/CodeGen/X86/fast-isel.ll
	utils/TableGen/FastISelEmitter.cpp
In-Reply-To: <200808252020.m7PKKXKK010461@zion.cs.uiuc.edu>
References: <200808252020.m7PKKXKK010461@zion.cs.uiuc.edu>
Message-ID: <122D532C-66CE-4A22-89BD-37C7B5AD9F7B@apple.com>


On Aug 25, 2008, at 1:20 PM, Owen Anderson wrote:

>
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55325&r1=55324&r2=55325&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Aug 25  
> 15:20:32 2008
> @@ -221,6 +221,22 @@
>     case Instruction::PHI:
>       // PHI nodes are already emitted.
>       break;
> +
> +    case Instruction::BitCast:
> +      // BitCast consists of either an immediate to register move
> +      // or a register to register move.
> +      if (ConstantInt* CI = dyn_cast<ConstantInt>(I- 
> >getOperand(0))) {
> +        if (I->getType()->isInteger()) {
> +          MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/ 
> false);
> +          ValueMap[I] = FastEmit_i(VT.getSimpleVT(), ISD::Constant,
> +                                   CI->getZExtValue());
> +          break;
> +        } else
> +          // TODO: Support vector and fp constants.
> +          return I;
> +      } else
> +        // TODO: Support non-constant bitcasts.
> +        return I;

Stylistic nitpick. If you invert the if conditions, you can eliminate  
nesting:

ConstantInt *CI = dyn_cast<>...
if (!CI)
   return I;
if (!I->getType()->isInteger())
   return I;

>
>
>     default:
>       // Unhandled instruction. Halt "fast" selection and bail.
> @@ -256,7 +272,8 @@
>   return 0;
> }
>
> -unsigned FastISel::FastEmit_i(MVT::SimpleValueType, uint64_t / 
> *Imm*/) {
> +unsigned FastISel::FastEmit_i(MVT::SimpleValueType, ISD::NodeType,
> +                              uint64_t /*Imm*/) {
>   return 0;
> }
>
> @@ -284,7 +301,7 @@
>     ResultReg = FastEmit_ri(VT, Opcode, Op0, Imm);
>   if (ResultReg != 0)
>     return ResultReg;
> -  unsigned MaterialReg = FastEmit_i(ImmType, Imm);
> +  unsigned MaterialReg = FastEmit_i(ImmType, ISD::Constant, Imm);

If NodeType is not yet used. Please add an assert.

>
>   if (MaterialReg == 0)
>     return 0;
>   return FastEmit_rr(VT, Opcode, Op0, MaterialReg);
> @@ -342,3 +359,13 @@
>   BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
>   return ResultReg;
> }
> +
> +unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
> +                                  const TargetRegisterClass *RC,
> +                                  uint64_t Imm) {
> +  unsigned ResultReg = createResultReg(RC);
> +  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
> +
> +  BuildMI(MBB, II, ResultReg).addImm(Imm);
> +  return ResultReg;
> +}

>
> \ No newline at end of file

Plz fix this.

Thanks,

Evan

>
>
> Modified: llvm/trunk/test/CodeGen/X86/fast-isel.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel.ll?rev=55325&r1=55324&r2=55325&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/fast-isel.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/fast-isel.ll Mon Aug 25 15:20:32 2008
> @@ -41,3 +41,8 @@
>   ret double %t2
> }
>
> +define i32 @cast(){
> +entry:
> +	%tmp2 = bitcast i32 0 to i32
> +	ret i32 %tmp2
> +}
>
> Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=55325&r1=55324&r2=55325&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Mon Aug 25  
> 15:20:32 2008
> @@ -64,6 +64,12 @@
>                   const CodeGenTarget &Target,
>                   MVT::SimpleValueType VT,
>                   const CodeGenRegisterClass *DstRC) {
> +    if (!InstPatNode->isLeaf() &&
> +        InstPatNode->getOperator()->getName() == "imm") {
> +      Operands.push_back("i");
> +      return true;
> +    }
> +
>     for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; + 
> +i) {
>       TreePatternNode *Op = InstPatNode->getChild(i);
>       // For now, filter out any operand with a predicate.
> @@ -219,9 +225,6 @@
>     // an Operand or an immediate, like MOV32ri.
>     if (InstPatOp->isSubClassOf("Operand"))
>       continue;
> -    if (InstPatOp->getName() == "imm" ||
> -        InstPatOp->getName() == "fpimm")
> -      continue;
>
>     // For now, filter out any instructions with predicates.
>     if (!InstPatNode->getPredicateFn().empty())
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From evan.cheng at apple.com  Mon Aug 25 17:20:39 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 25 Aug 2008 22:20:39 -0000
Subject: [llvm-commits] [llvm] r55342 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808252220.m7PMKdg4014197@zion.cs.uiuc.edu>

Author: evancheng
Date: Mon Aug 25 17:20:39 2008
New Revision: 55342

URL: http://llvm.org/viewvc/llvm-project?rev=55342&view=rev
Log:
Unbreak build.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55342&r1=55341&r2=55342&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Aug 25 17:20:39 2008
@@ -246,7 +246,7 @@
           return I;
         if (!TLI.isConvertLegal(SrcVT, DstVT))
           // Illegal conversion.  Halt "fast" selection and bail.
-          return I:
+          return I;
         
         // Otherwise, insert a register-to-register copy.
         TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
@@ -396,4 +396,4 @@
   
   BuildMI(MBB, II, ResultReg).addImm(Imm);
   return ResultReg;
-}
\ No newline at end of file
+}




From dalej at apple.com  Mon Aug 25 17:34:38 2008
From: dalej at apple.com (Dale Johannesen)
Date: Mon, 25 Aug 2008 22:34:38 -0000
Subject: [llvm-commits] [llvm] r55343 - in /llvm/trunk/lib/Target:
 PowerPC/PPCISelLowering.cpp PowerPC/PPCISelLowering.h
 PowerPC/PPCInstr64Bit.td PowerPC/PPCInstrInfo.td TargetSelectionDAG.td
Message-ID: <200808252234.m7PMYcVq014588@zion.cs.uiuc.edu>

Author: johannes
Date: Mon Aug 25 17:34:37 2008
New Revision: 55343

URL: http://llvm.org/viewvc/llvm-project?rev=55343&view=rev
Log:
Implement 32 & 64 bit versions of PPC atomic
binary primitives.


Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
    llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
    llvm/trunk/lib/Target/TargetSelectionDAG.td

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=55343&r1=55342&r2=55343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Aug 25 17:34:37 2008
@@ -3861,6 +3861,60 @@
 //===----------------------------------------------------------------------===//
 
 MachineBasicBlock *
+PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
+                                    bool is64bit, unsigned BinOpcode) {
+  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
+
+  const BasicBlock *LLVM_BB = BB->getBasicBlock();
+  MachineFunction *F = BB->getParent();
+  MachineFunction::iterator It = BB;
+  ++It;
+
+  unsigned dest = MI->getOperand(0).getReg();
+  unsigned ptrA = MI->getOperand(1).getReg();
+  unsigned ptrB = MI->getOperand(2).getReg();
+  unsigned incr = MI->getOperand(3).getReg();
+
+  MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
+  F->insert(It, loopMBB);
+  F->insert(It, exitMBB);
+  exitMBB->transferSuccessors(BB);
+
+  MachineRegisterInfo &RegInfo = F->getRegInfo();
+  unsigned TmpReg = RegInfo.createVirtualRegister(
+    is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass :
+              (const TargetRegisterClass *) &PPC::G8RCRegClass);
+
+  //  thisMBB:
+  //   ...
+  //   fallthrough --> loopMBB
+  BB->addSuccessor(loopMBB);
+
+  //  loopMBB:
+  //   l[wd]arx dest, ptr
+  //   add r0, dest, incr
+  //   st[wd]cx. r0, ptr
+  //   bne- loopMBB
+  //   fallthrough --> exitMBB
+  BB = loopMBB;
+  BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
+    .addReg(ptrA).addReg(ptrB);
+  BuildMI(BB, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
+  BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
+    .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
+  BuildMI(BB, TII->get(PPC::BCC))
+    .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);    
+  BB->addSuccessor(loopMBB);
+  BB->addSuccessor(exitMBB);
+
+  //  exitMBB:
+  //   ...
+  BB = exitMBB;
+  return BB;
+}
+
+MachineBasicBlock *
 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
                                                MachineBasicBlock *BB) {
   const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
@@ -3920,53 +3974,30 @@
       .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
       .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
   }
-  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32 ||
-           MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) {
-    bool is64bit = MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64;
-
-    unsigned dest = MI->getOperand(0).getReg();
-    unsigned ptrA = MI->getOperand(1).getReg();
-    unsigned ptrB = MI->getOperand(2).getReg();
-    unsigned incr = MI->getOperand(3).getReg();
-
-    MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
-    MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
-    F->insert(It, loopMBB);
-    F->insert(It, exitMBB);
-    exitMBB->transferSuccessors(BB);
-
-    MachineRegisterInfo &RegInfo = F->getRegInfo();
-    unsigned TmpReg = RegInfo.createVirtualRegister(
-      is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass :
-                (const TargetRegisterClass *) &PPC::G8RCRegClass);
-
-    //  thisMBB:
-    //   ...
-    //   fallthrough --> loopMBB
-    BB->addSuccessor(loopMBB);
-
-    //  loopMBB:
-    //   l[wd]arx dest, ptr
-    //   add r0, dest, incr
-    //   st[wd]cx. r0, ptr
-    //   bne- loopMBB
-    //   fallthrough --> exitMBB
-    BB = loopMBB;
-    BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
-      .addReg(ptrA).addReg(ptrB);
-    BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), TmpReg)
-      .addReg(incr).addReg(dest);
-    BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
-      .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
-    BuildMI(BB, TII->get(PPC::BCC))
-      .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);    
-    BB->addSuccessor(loopMBB);
-    BB->addSuccessor(exitMBB);
-    
-    //  exitMBB:
-    //   ...
-    BB = exitMBB;
-  }
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
+    BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
+    BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
+    BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
+    BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
+    BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
+    BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
+    BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
+    BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
+    BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
+    BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
+    BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
+    BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
   else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
            MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
     bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=55343&r1=55342&r2=55343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Mon Aug 25 17:34:37 2008
@@ -282,6 +282,9 @@
 
     virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
                                                         MachineBasicBlock *MBB);
+    MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 
+                                        MachineBasicBlock *MBB, bool is64Bit,
+                                        unsigned BinOpcode);
     
     ConstraintType getConstraintType(const std::string &Constraint) const;
     std::pair<unsigned, const TargetRegisterClass*> 

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=55343&r1=55342&r2=55343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Mon Aug 25 17:34:37 2008
@@ -123,11 +123,33 @@
       (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
       "${:comment} ATOMIC_LOAD_ADD_I64 PSEUDO!",
       [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>;
+    def ATOMIC_LOAD_SUB_I64 : Pseudo<
+      (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
+      "${:comment} ATOMIC_LOAD_SUB_I64 PSEUDO!",
+      [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>;
+    def ATOMIC_LOAD_OR_I64 : Pseudo<
+      (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
+      "${:comment} ATOMIC_LOAD_OR_I64 PSEUDO!",
+      [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>;
+    def ATOMIC_LOAD_XOR_I64 : Pseudo<
+      (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
+      "${:comment} ATOMIC_LOAD_XOR_I64 PSEUDO!",
+      [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>;
+    def ATOMIC_LOAD_AND_I64 : Pseudo<
+      (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
+      "${:comment} ATOMIC_LOAD_AND_I64 PSEUDO!",
+      [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>;
+    def ATOMIC_LOAD_NAND_I64 : Pseudo<
+      (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
+      "${:comment} ATOMIC_LOAD_NAND_I64 PSEUDO!",
+      [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>;
+
     def ATOMIC_CMP_SWAP_I64 : Pseudo<
       (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new),
       "${:comment} ATOMIC_CMP_SWAP_I64 PSEUDO!",
       [(set G8RC:$dst, 
                     (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
+
     def ATOMIC_SWAP_I64 : Pseudo<
       (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new),
       "${:comment} ATOMIC_SWAP_I64 PSEUDO!",
@@ -313,7 +335,6 @@
 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
                      "subf $rT, $rA, $rB", IntGeneral,
                      [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
-
 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
                       "subfc $rT, $rA, $rB", IntGeneral,
                       [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>,

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=55343&r1=55342&r2=55343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Mon Aug 25 17:34:37 2008
@@ -532,11 +532,33 @@
       (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
       "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
       [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
+    def ATOMIC_LOAD_SUB_I32 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
+      "${:comment} ATOMIC_LOAD_SUB_I32 PSEUDO!",
+      [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>;
+    def ATOMIC_LOAD_AND_I32 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
+      "${:comment} ATOMIC_LOAD_AND_I32 PSEUDO!",
+      [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>;
+    def ATOMIC_LOAD_OR_I32 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
+      "${:comment} ATOMIC_LOAD_OR_I32 PSEUDO!",
+      [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>;
+    def ATOMIC_LOAD_XOR_I32 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
+      "${:comment} ATOMIC_LOAD_XOR_I32 PSEUDO!",
+      [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>;
+    def ATOMIC_LOAD_NAND_I32 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
+      "${:comment} ATOMIC_LOAD_NAND_I32 PSEUDO!",
+      [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
+
     def ATOMIC_CMP_SWAP_I32 : Pseudo<
       (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
       "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
       [(set GPRC:$dst, 
                     (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
+
     def ATOMIC_SWAP_I32 : Pseudo<
       (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
       "${:comment} ATOMIC_SWAP_I32 PSEUDO!",

Modified: llvm/trunk/lib/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetSelectionDAG.td?rev=55343&r1=55342&r2=55343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/lib/Target/TargetSelectionDAG.td Mon Aug 25 17:34:37 2008
@@ -767,6 +767,111 @@
   return V->getValueType(0) == MVT::i64;
 }]>;
 
+def atomic_load_sub_8 : PatFrag<(ops node:$ptr, node:$inc),
+                    (atomic_load_sub node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i8;
+}]>;
+def atomic_load_sub_16 : PatFrag<(ops node:$ptr, node:$inc), 
+                    (atomic_load_sub node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i16;
+}]>;
+def atomic_load_sub_32 : PatFrag<(ops node:$ptr, node:$inc), 
+                    (atomic_load_sub node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i32;
+}]>;
+def atomic_load_sub_64 : PatFrag<(ops node:$ptr, node:$inc), 
+                    (atomic_load_sub node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i64;
+}]>;
+
+def atomic_load_and_8 : PatFrag<(ops node:$ptr, node:$inc),
+                    (atomic_load_and node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i8;
+}]>;
+def atomic_load_and_16 : PatFrag<(ops node:$ptr, node:$inc), 
+                    (atomic_load_and node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i16;
+}]>;
+def atomic_load_and_32 : PatFrag<(ops node:$ptr, node:$inc), 
+                    (atomic_load_and node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i32;
+}]>;
+def atomic_load_and_64 : PatFrag<(ops node:$ptr, node:$inc), 
+                    (atomic_load_and node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i64;
+}]>;
+
+def atomic_load_or_8 : PatFrag<(ops node:$ptr, node:$inc),
+                    (atomic_load_or node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i8;
+}]>;
+def atomic_load_or_16 : PatFrag<(ops node:$ptr, node:$inc), 
+                    (atomic_load_or node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i16;
+}]>;
+def atomic_load_or_32 : PatFrag<(ops node:$ptr, node:$inc), 
+                    (atomic_load_or node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i32;
+}]>;
+def atomic_load_or_64 : PatFrag<(ops node:$ptr, node:$inc), 
+                    (atomic_load_or node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i64;
+}]>;
+
+def atomic_load_xor_8 : PatFrag<(ops node:$ptr, node:$inc),
+                    (atomic_load_xor node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i8;
+}]>;
+def atomic_load_xor_16 : PatFrag<(ops node:$ptr, node:$inc), 
+                    (atomic_load_xor node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i16;
+}]>;
+def atomic_load_xor_32 : PatFrag<(ops node:$ptr, node:$inc), 
+                    (atomic_load_xor node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i32;
+}]>;
+def atomic_load_xor_64 : PatFrag<(ops node:$ptr, node:$inc), 
+                    (atomic_load_xor node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i64;
+}]>;
+
+def atomic_load_nand_8 : PatFrag<(ops node:$ptr, node:$inc),
+                    (atomic_load_nand node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i8;
+}]>;
+def atomic_load_nand_16 : PatFrag<(ops node:$ptr, node:$inc), 
+                    (atomic_load_nand node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i16;
+}]>;
+def atomic_load_nand_32 : PatFrag<(ops node:$ptr, node:$inc), 
+                    (atomic_load_nand node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i32;
+}]>;
+def atomic_load_nand_64 : PatFrag<(ops node:$ptr, node:$inc), 
+                    (atomic_load_nand node:$ptr, node:$inc), [{
+  AtomicSDNode* V = cast<AtomicSDNode>(N);
+  return V->getValueType(0) == MVT::i64;
+}]>;
+
 def atomic_swap_8 : PatFrag<(ops node:$ptr, node:$inc),
                     (atomic_swap node:$ptr, node:$inc), [{
   AtomicSDNode* V = cast<AtomicSDNode>(N);




From resistor at mac.com  Mon Aug 25 18:43:11 2008
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Aug 2008 23:43:11 -0000
Subject: [llvm-commits] [llvm] r55344 -
	/llvm/trunk/utils/TableGen/FastISelEmitter.cpp
Message-ID: <200808252343.m7PNhBj7016494@zion.cs.uiuc.edu>

Author: resistor
Date: Mon Aug 25 18:43:09 2008
New Revision: 55344

URL: http://llvm.org/viewvc/llvm-project?rev=55344&view=rev
Log:
Deepen the map structure tablegen uses to compute FastISel patterns, in preparation for having patterns
with return types that differ from their input types.  This is not yet used.

Modified:
    llvm/trunk/utils/TableGen/FastISelEmitter.cpp

Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=55344&r1=55343&r2=55344&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Mon Aug 25 18:43:09 2008
@@ -182,10 +182,11 @@
   OS << "\n";
   
   typedef std::map<std::string, InstructionMemo> PredMap;
-  typedef std::map<MVT::SimpleValueType, PredMap> TypePredMap;
-  typedef std::map<std::string, TypePredMap> OpcodeTypePredMap;
-  typedef std::map<OperandsSignature, OpcodeTypePredMap> OperandsOpcodeTypePredMap;
-  OperandsOpcodeTypePredMap SimplePatterns;
+  typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
+  typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
+  typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
+  typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> OperandsOpcodeTypeRetPredMap;
+  OperandsOpcodeTypeRetPredMap SimplePatterns;
 
   // Scan through all the patterns and record the simple ones.
   for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
@@ -243,24 +244,24 @@
       Pattern.getDstPattern()->getOperator()->getName(),
       DstRC
     };
-    assert(!SimplePatterns[Operands][OpcodeName][VT].count(PredicateCheck) &&
+    assert(!SimplePatterns[Operands][OpcodeName][VT][VT].count(PredicateCheck) &&
            "Duplicate pattern!");
-    SimplePatterns[Operands][OpcodeName][VT][PredicateCheck] = Memo;
+    SimplePatterns[Operands][OpcodeName][VT][VT][PredicateCheck] = Memo;
   }
 
   // Declare the target FastISel class.
   OS << "class FastISel : public llvm::FastISel {\n";
-  for (OperandsOpcodeTypePredMap::const_iterator OI = SimplePatterns.begin(),
+  for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
        OE = SimplePatterns.end(); OI != OE; ++OI) {
     const OperandsSignature &Operands = OI->first;
-    const OpcodeTypePredMap &OTM = OI->second;
+    const OpcodeTypeRetPredMap &OTM = OI->second;
 
-    for (OpcodeTypePredMap::const_iterator I = OTM.begin(), E = OTM.end();
+    for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
          I != E; ++I) {
       const std::string &Opcode = I->first;
-      const TypePredMap &TM = I->second;
+      const TypeRetPredMap &TM = I->second;
 
-      for (TypePredMap::const_iterator TI = TM.begin(), TE = TM.end();
+      for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
            TI != TE; ++TI) {
         MVT::SimpleValueType VT = TI->first;
 
@@ -312,63 +313,69 @@
   OS << "\n";
 
   // Now emit code for all the patterns that we collected.
-  for (OperandsOpcodeTypePredMap::const_iterator OI = SimplePatterns.begin(),
+  for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
        OE = SimplePatterns.end(); OI != OE; ++OI) {
     const OperandsSignature &Operands = OI->first;
-    const OpcodeTypePredMap &OTM = OI->second;
+    const OpcodeTypeRetPredMap &OTM = OI->second;
 
-    for (OpcodeTypePredMap::const_iterator I = OTM.begin(), E = OTM.end();
+    for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
          I != E; ++I) {
       const std::string &Opcode = I->first;
-      const TypePredMap &TM = I->second;
+      const TypeRetPredMap &TM = I->second;
 
       OS << "// FastEmit functions for " << Opcode << ".\n";
       OS << "\n";
 
       // Emit one function for each opcode,type pair.
-      for (TypePredMap::const_iterator TI = TM.begin(), TE = TM.end();
+      for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
            TI != TE; ++TI) {
         MVT::SimpleValueType VT = TI->first;
-        const PredMap &PM = TI->second;
-        bool HasPred = false;
+        const RetPredMap &RM = TI->second;
 
-        OS << "unsigned FastISel::FastEmit_"
-           << getLegalCName(Opcode)
-           << "_" << getLegalCName(getName(VT)) << "_";
-        Operands.PrintManglingSuffix(OS);
-        OS << "(";
-        Operands.PrintParameters(OS);
-        OS << ") {\n";
-
-        // Emit code for each possible instruction. There may be
-        // multiple if there are subtarget concerns.
-        for (PredMap::const_iterator PI = PM.begin(), PE = PM.end();
-             PI != PE; ++PI) {
-          std::string PredicateCheck = PI->first;
-          const InstructionMemo &Memo = PI->second;
+        for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
+             RI != RE; ++RI) {
+          const PredMap &PM = RI->second;
+          bool HasPred = false;
+
+          OS << "unsigned FastISel::FastEmit_"
+             << getLegalCName(Opcode)
+             << "_" << getLegalCName(getName(VT)) << "_";
+          Operands.PrintManglingSuffix(OS);
+          OS << "(";
+          Operands.PrintParameters(OS);
+          OS << ") {\n";
+
+          // Emit code for each possible instruction. There may be
+          // multiple if there are subtarget concerns.
+          for (PredMap::const_iterator PI = PM.begin(), PE = PM.end();
+               PI != PE; ++PI) {
+            std::string PredicateCheck = PI->first;
+            const InstructionMemo &Memo = PI->second;
   
-          if (PredicateCheck.empty()) {
-            assert(!HasPred && "Multiple instructions match, at least one has "
-                               "a predicate and at least one doesn't!");
-          } else {
-            OS << "  if (" + PredicateCheck + ")\n";
-            OS << "  ";
-            HasPred = true;
+            if (PredicateCheck.empty()) {
+              assert(!HasPred &&
+                     "Multiple instructions match, at least one has "
+                     "a predicate and at least one doesn't!");
+            } else {
+              OS << "  if (" + PredicateCheck + ")\n";
+              OS << "  ";
+              HasPred = true;
+            }
+            OS << "  return FastEmitInst_";
+            Operands.PrintManglingSuffix(OS);
+            OS << "(" << InstNS << Memo.Name << ", ";
+            OS << InstNS << Memo.RC->getName() << "RegisterClass";
+            if (!Operands.empty())
+              OS << ", ";
+            Operands.PrintArguments(OS);
+            OS << ");\n";
           }
-          OS << "  return FastEmitInst_";
-          Operands.PrintManglingSuffix(OS);
-          OS << "(" << InstNS << Memo.Name << ", ";
-          OS << InstNS << Memo.RC->getName() << "RegisterClass";
-          if (!Operands.empty())
-            OS << ", ";
-          Operands.PrintArguments(OS);
-          OS << ");\n";
+          // Return 0 if none of the predicates were satisfied.
+          if (HasPred)
+            OS << "  return 0;\n";
+          OS << "}\n";
+          OS << "\n";
         }
-        // Return 0 if none of the predicates were satisfied.
-        if (HasPred)
-          OS << "  return 0;\n";
-        OS << "}\n";
-        OS << "\n";
       }
 
       // Emit one function for the opcode that demultiplexes based on the type.
@@ -381,7 +388,7 @@
       Operands.PrintParameters(OS);
       OS << ") {\n";
       OS << "  switch (VT) {\n";
-      for (TypePredMap::const_iterator TI = TM.begin(), TE = TM.end();
+      for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
            TI != TE; ++TI) {
         MVT::SimpleValueType VT = TI->first;
         std::string TypeName = getName(VT);
@@ -411,7 +418,7 @@
     Operands.PrintParameters(OS);
     OS << ") {\n";
     OS << "  switch (Opcode) {\n";
-    for (OpcodeTypePredMap::const_iterator I = OTM.begin(), E = OTM.end();
+    for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
          I != E; ++I) {
       const std::string &Opcode = I->first;
 




From resistor at mac.com  Mon Aug 25 18:58:22 2008
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Aug 2008 23:58:22 -0000
Subject: [llvm-commits] [llvm] r55345 - in /llvm/trunk:
 include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp
 utils/TableGen/FastISelEmitter.cpp
Message-ID: <200808252358.m7PNwNWB016902@zion.cs.uiuc.edu>

Author: resistor
Date: Mon Aug 25 18:58:18 2008
New Revision: 55345

URL: http://llvm.org/viewvc/llvm-project?rev=55345&view=rev
Log:
Add a RetVT parameter to emitted FastISel methods, so that we will be able to pass the desired return
type down.  This is not currently used.

Modified:
    llvm/trunk/include/llvm/CodeGen/FastISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
    llvm/trunk/utils/TableGen/FastISelEmitter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=55345&r1=55344&r2=55345&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Mon Aug 25 18:58:18 2008
@@ -64,6 +64,7 @@
   /// to request that an instruction with the given type and opcode
   /// be emitted.
   virtual unsigned FastEmit_(MVT::SimpleValueType VT,
+                             MVT::SimpleValueType RetVT,
                              ISD::NodeType Opcode);
 
   /// FastEmit_r - This method is called by target-independent code
@@ -71,6 +72,7 @@
   /// register operand be emitted.
   ///
   virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
+                              MVT::SimpleValueType RetVT,
                               ISD::NodeType Opcode, unsigned Op0);
 
   /// FastEmit_rr - This method is called by target-independent code
@@ -78,6 +80,7 @@
   /// register operands be emitted.
   ///
   virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
+                               MVT::SimpleValueType RetVT,
                                ISD::NodeType Opcode,
                                unsigned Op0, unsigned Op1);
 
@@ -86,6 +89,7 @@
   /// register and immediate operands be emitted.
   ///
   virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
+                               MVT::SimpleValueType RetVT,
                                ISD::NodeType Opcode,
                                unsigned Op0, uint64_t Imm);
 
@@ -94,6 +98,7 @@
   /// register and immediate operands be emitted.
   ///
   virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
+                                MVT::SimpleValueType RetVT,
                                 ISD::NodeType Opcode,
                                 unsigned Op0, unsigned Op1, uint64_t Imm);
 
@@ -110,6 +115,7 @@
   /// to request that an instruction with the given type, opcode, and
   /// immediate operand be emitted.
   virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
+                              MVT::SimpleValueType RetVT,
                               ISD::NodeType Opcode,
                               uint64_t Imm);
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55345&r1=55344&r2=55345&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Aug 25 18:58:18 2008
@@ -55,7 +55,8 @@
     // Unhandled operand. Halt "fast" selection and bail.
     return false;
 
-  unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), ISDOpcode, Op0, Op1);
+  unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
+                                   ISDOpcode, Op0, Op1);
   if (ResultReg == 0)
     // Target-specific code wasn't able to find a machine opcode for
     // the given ISD opcode and type. Halt "fast" selection and bail.
@@ -117,9 +118,9 @@
       // it.
       MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
       if (IdxVT.bitsLT(VT))
-        IdxN = FastEmit_r(VT, ISD::SIGN_EXTEND, IdxN);
+        IdxN = FastEmit_r(VT, VT, ISD::SIGN_EXTEND, IdxN);
       else if (IdxVT.bitsGT(VT))
-        IdxN = FastEmit_r(VT, ISD::TRUNCATE, IdxN);
+        IdxN = FastEmit_r(VT, VT, ISD::TRUNCATE, IdxN);
       if (IdxN == 0)
         // Unhandled operand. Halt "fast" selection and bail.
         return false;
@@ -129,7 +130,7 @@
       if (IdxN == 0)
         // Unhandled operand. Halt "fast" selection and bail.
         return false;
-      N = FastEmit_rr(VT, ISD::ADD, N, IdxN);
+      N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
       if (N == 0)
         // Unhandled operand. Halt "fast" selection and bail.
         return false;
@@ -228,7 +229,8 @@
       if (ConstantInt* CI = dyn_cast<ConstantInt>(I->getOperand(0))) {
         if (I->getType()->isInteger()) {
           MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/false);
-          ValueMap[I] = FastEmit_i(VT.getSimpleVT(), ISD::Constant,
+          ValueMap[I] = FastEmit_i(VT.getSimpleVT(), VT.getSimpleVT(),
+                                   ISD::Constant,
                                    CI->getZExtValue());
           break;
         } else
@@ -286,31 +288,34 @@
 
 FastISel::~FastISel() {}
 
-unsigned FastISel::FastEmit_(MVT::SimpleValueType, ISD::NodeType) {
+unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, ISD::NodeType) {
   return 0;
 }
 
-unsigned FastISel::FastEmit_r(MVT::SimpleValueType, ISD::NodeType,
-                              unsigned /*Op0*/) {
+unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
+                              ISD::NodeType, unsigned /*Op0*/) {
   return 0;
 }
 
-unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
-                               unsigned /*Op0*/, unsigned /*Op0*/) {
+unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType, 
+                               ISD::NodeType, unsigned /*Op0*/,
+                               unsigned /*Op0*/) {
   return 0;
 }
 
-unsigned FastISel::FastEmit_i(MVT::SimpleValueType, ISD::NodeType,
-                              uint64_t /*Imm*/) {
+unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
+                              ISD::NodeType, uint64_t /*Imm*/) {
   return 0;
 }
 
-unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, ISD::NodeType,
-                               unsigned /*Op0*/, uint64_t /*Imm*/) {
+unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
+                               ISD::NodeType, unsigned /*Op0*/,
+                               uint64_t /*Imm*/) {
   return 0;
 }
 
-unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, ISD::NodeType,
+unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
+                                ISD::NodeType,
                                 unsigned /*Op0*/, unsigned /*Op1*/,
                                 uint64_t /*Imm*/) {
   return 0;
@@ -326,13 +331,13 @@
   unsigned ResultReg = 0;
   // First check if immediate type is legal. If not, we can't use the ri form.
   if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
-    ResultReg = FastEmit_ri(VT, Opcode, Op0, Imm);
+    ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
   if (ResultReg != 0)
     return ResultReg;
-  unsigned MaterialReg = FastEmit_i(ImmType, ISD::Constant, Imm);
+  unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
   if (MaterialReg == 0)
     return 0;
-  return FastEmit_rr(VT, Opcode, Op0, MaterialReg);
+  return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
 }
 
 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {

Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=55345&r1=55344&r2=55345&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Mon Aug 25 18:58:18 2008
@@ -268,14 +268,16 @@
         OS << "  unsigned FastEmit_" << getLegalCName(Opcode)
            << "_" << getLegalCName(getName(VT)) << "_";
         Operands.PrintManglingSuffix(OS);
-        OS << "(";
+        OS << "(MVT::SimpleValueType RetVT";
+        if (!Operands.empty())
+          OS << ", ";
         Operands.PrintParameters(OS);
         OS << ");\n";
       }
 
       OS << "  unsigned FastEmit_" << getLegalCName(Opcode) << "_";
       Operands.PrintManglingSuffix(OS);
-      OS << "(MVT::SimpleValueType VT";
+      OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT";
       if (!Operands.empty())
         OS << ", ";
       Operands.PrintParameters(OS);
@@ -284,7 +286,7 @@
 
     OS << "  unsigned FastEmit_";
     Operands.PrintManglingSuffix(OS);
-    OS << "(MVT::SimpleValueType VT, ISD::NodeType Opcode";
+    OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT, ISD::NodeType Opcode";
     if (!Operands.empty())
       OS << ", ";
     Operands.PrintParameters(OS);
@@ -341,7 +343,9 @@
              << getLegalCName(Opcode)
              << "_" << getLegalCName(getName(VT)) << "_";
           Operands.PrintManglingSuffix(OS);
-          OS << "(";
+          OS << "(MVT::SimpleValueType RetVT";
+          if (!Operands.empty())
+            OS << ", ";
           Operands.PrintParameters(OS);
           OS << ") {\n";
 
@@ -382,7 +386,7 @@
       OS << "unsigned FastISel::FastEmit_"
          << getLegalCName(Opcode) << "_";
       Operands.PrintManglingSuffix(OS);
-      OS << "(MVT::SimpleValueType VT";
+      OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT";
       if (!Operands.empty())
         OS << ", ";
       Operands.PrintParameters(OS);
@@ -395,7 +399,9 @@
         OS << "  case " << TypeName << ": return FastEmit_"
            << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
         Operands.PrintManglingSuffix(OS);
-        OS << "(";
+        OS << "(RetVT";
+        if (!Operands.empty())
+          OS << ", ";
         Operands.PrintArguments(OS);
         OS << ");\n";
       }
@@ -412,7 +418,7 @@
     // on opcode and type.
     OS << "unsigned FastISel::FastEmit_";
     Operands.PrintManglingSuffix(OS);
-    OS << "(MVT::SimpleValueType VT, ISD::NodeType Opcode";
+    OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT, ISD::NodeType Opcode";
     if (!Operands.empty())
       OS << ", ";
     Operands.PrintParameters(OS);
@@ -425,7 +431,7 @@
       OS << "  case " << Opcode << ": return FastEmit_"
          << getLegalCName(Opcode) << "_";
       Operands.PrintManglingSuffix(OS);
-      OS << "(VT";
+      OS << "(VT, RetVT";
       if (!Operands.empty())
         OS << ", ";
       Operands.PrintArguments(OS);




From gohman at apple.com  Mon Aug 25 19:36:19 2008
From: gohman at apple.com (Dan Gohman)
Date: Mon, 25 Aug 2008 17:36:19 -0700
Subject: [llvm-commits] [llvm] r55292 - in /llvm/trunk:
	lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/fold-call-2.ll
In-Reply-To: <25F309AF-A954-43A1-AC17-B659C2381DAD@apple.com>
References: <200808241919.m7OJJuZf013766@zion.cs.uiuc.edu>
	<33103040-5633-4BCD-A250-56C247FB7282@apple.com>
	<25F309AF-A954-43A1-AC17-B659C2381DAD@apple.com>
Message-ID: <4C3161E0-245F-4579-A14C-6928BEEAA906@apple.com>

Not offhand. Is callseq_start a no-op on all targets, when
there's no alloca?

BTW, this there's an X86/README.txt entry on this that
you can remove, the one beginning
"Another instruction selector deficiency".

Dan

On Aug 25, 2008, at 2:57 PM, Evan Cheng wrote:

> callseq_start is completely eliminated unless there is an alloca, but
> in that case FP is used to do reload. I think we are safe. Can you
> think of an unsafe situation?
>
> Evan
>
> On Aug 25, 2008, at 12:51 PM, Dan Gohman wrote:
>
>>
>> On Aug 24, 2008, at 12:19 PM, Evan Cheng wrote:
>>
>>> Author: evancheng
>>> Date: Sun Aug 24 14:19:55 2008
>>> New Revision: 55292
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=55292&view=rev
>>> Log:
>>> Move callseq_start above the call address load to allow load to be
>>> folded into the call node.
>>
>> What happens if the callseq_start involves a non-trivial stack
>> pointer adjustment and the load's address is spilled and needs
>> to be reloaded? Could this change cause the reload to happen
>> from the wrong stack location?
>>
>> Dan
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From resistor at mac.com  Mon Aug 25 19:42:26 2008
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Aug 2008 00:42:26 -0000
Subject: [llvm-commits] [llvm] r55347 -
	/llvm/trunk/utils/TableGen/FastISelEmitter.cpp
Message-ID: <200808260042.m7Q0gQWd018174@zion.cs.uiuc.edu>

Author: resistor
Date: Mon Aug 25 19:42:26 2008
New Revision: 55347

URL: http://llvm.org/viewvc/llvm-project?rev=55347&view=rev
Log:
Enhance TableGen to emit code for FastISel of opcodes with variadic return types without slowing down opcodes that are not variadic.  No such opcodes are currently generated, but in theory it should be a matter of just hitting the switch.

Modified:
    llvm/trunk/utils/TableGen/FastISelEmitter.cpp

Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=55347&r1=55346&r2=55347&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Mon Aug 25 19:42:26 2008
@@ -264,7 +264,21 @@
       for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
            TI != TE; ++TI) {
         MVT::SimpleValueType VT = TI->first;
-
+        const RetPredMap &RM = TI->second;
+        
+        if (RM.size() != 1)
+          for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
+               RI != RE; ++RI) {
+            MVT::SimpleValueType RetVT = RI->first;
+            OS << "  unsigned FastEmit_" << getLegalCName(Opcode)
+               << "_" << getLegalCName(getName(VT)) << "_"
+               << getLegalCName(getName(RetVT)) << "_";
+            Operands.PrintManglingSuffix(OS);
+            OS << "(";
+            Operands.PrintParameters(OS);
+            OS << ");\n";
+          }
+        
         OS << "  unsigned FastEmit_" << getLegalCName(Opcode)
            << "_" << getLegalCName(getName(VT)) << "_";
         Operands.PrintManglingSuffix(OS);
@@ -333,29 +347,98 @@
            TI != TE; ++TI) {
         MVT::SimpleValueType VT = TI->first;
         const RetPredMap &RM = TI->second;
-
-        for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
-             RI != RE; ++RI) {
-          const PredMap &PM = RI->second;
-          bool HasPred = false;
-
+        if (RM.size() != 1) {
+          for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
+               RI != RE; ++RI) {
+            MVT::SimpleValueType RetVT = RI->first;
+            const PredMap &PM = RI->second;
+            bool HasPred = false;
+
+            OS << "unsigned FastISel::FastEmit_"
+               << getLegalCName(Opcode)
+               << "_" << getLegalCName(getName(VT))
+               << "_" << getLegalCName(getName(RetVT)) << "_";
+            Operands.PrintManglingSuffix(OS);
+            OS << "(";
+            Operands.PrintParameters(OS);
+            OS << ") {\n";
+
+            // Emit code for each possible instruction. There may be
+            // multiple if there are subtarget concerns.
+            for (PredMap::const_iterator PI = PM.begin(), PE = PM.end();
+                 PI != PE; ++PI) {
+              std::string PredicateCheck = PI->first;
+              const InstructionMemo &Memo = PI->second;
+  
+              if (PredicateCheck.empty()) {
+                assert(!HasPred &&
+                       "Multiple instructions match, at least one has "
+                       "a predicate and at least one doesn't!");
+              } else {
+                OS << "  if (" + PredicateCheck + ")\n";
+                OS << "  ";
+                HasPred = true;
+              }
+              OS << "  return FastEmitInst_";
+              Operands.PrintManglingSuffix(OS);
+              OS << "(" << InstNS << Memo.Name << ", ";
+              OS << InstNS << Memo.RC->getName() << "RegisterClass";
+              if (!Operands.empty())
+                OS << ", ";
+              Operands.PrintArguments(OS);
+              OS << ");\n";
+            }
+            // Return 0 if none of the predicates were satisfied.
+            if (HasPred)
+              OS << "  return 0;\n";
+            OS << "}\n";
+            OS << "\n";
+          }
+          
+          // Emit one function for the type that demultiplexes on return type.
+          OS << "unsigned FastISel::FastEmit_"
+             << getLegalCName(Opcode) << "_"
+             << getLegalCName(getName(VT));
+          Operands.PrintManglingSuffix(OS);
+          OS << "(MVT::SimpleValueType RetVT";
+          if (!Operands.empty())
+            OS << ", ";
+          Operands.PrintParameters(OS);
+          OS << ") {\nswitch (RetVT) {\n";
+          for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
+               RI != RE; ++RI) {
+            MVT::SimpleValueType RetVT = RI->first;
+            OS << "  case " << getName(RetVT) << ": return FastEmit_"
+               << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT))
+               << "_" << getLegalCName(getName(RetVT)) << "_";
+            Operands.PrintManglingSuffix(OS);
+            OS << "(";
+            Operands.PrintArguments(OS);
+            OS << ");\n";
+          }
+          OS << "  default: return 0;\n}\n}\n\n";
+          
+        } else {
+          // Non-variadic return type.
           OS << "unsigned FastISel::FastEmit_"
-             << getLegalCName(Opcode)
-             << "_" << getLegalCName(getName(VT)) << "_";
+             << getLegalCName(Opcode) << "_"
+             << getLegalCName(getName(VT)) << "_";
           Operands.PrintManglingSuffix(OS);
           OS << "(MVT::SimpleValueType RetVT";
           if (!Operands.empty())
             OS << ", ";
           Operands.PrintParameters(OS);
           OS << ") {\n";
-
+          
+          const PredMap &PM = RM.begin()->second;
+          bool HasPred = false;
+          
           // Emit code for each possible instruction. There may be
           // multiple if there are subtarget concerns.
-          for (PredMap::const_iterator PI = PM.begin(), PE = PM.end();
-               PI != PE; ++PI) {
+          for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE; ++PI) {
             std::string PredicateCheck = PI->first;
             const InstructionMemo &Memo = PI->second;
-  
+
             if (PredicateCheck.empty()) {
               assert(!HasPred &&
                      "Multiple instructions match, at least one has "
@@ -374,6 +457,7 @@
             Operands.PrintArguments(OS);
             OS << ");\n";
           }
+          
           // Return 0 if none of the predicates were satisfied.
           if (HasPred)
             OS << "  return 0;\n";




From evan.cheng at apple.com  Mon Aug 25 20:11:49 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 25 Aug 2008 18:11:49 -0700
Subject: [llvm-commits] [llvm] r55292 - in /llvm/trunk:
	lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/fold-call-2.ll
In-Reply-To: <4C3161E0-245F-4579-A14C-6928BEEAA906@apple.com>
References: <200808241919.m7OJJuZf013766@zion.cs.uiuc.edu>
	<33103040-5633-4BCD-A250-56C247FB7282@apple.com>
	<25F309AF-A954-43A1-AC17-B659C2381DAD@apple.com>
	<4C3161E0-245F-4579-A14C-6928BEEAA906@apple.com>
Message-ID: <656B1F52-3DFE-432E-85B5-349B5DF63D4B@apple.com>


On Aug 25, 2008, at 5:36 PM, Dan Gohman wrote:

> Not offhand. Is callseq_start a no-op on all targets, when
> there's no alloca?

That's the case on x86 for sure. I need to check other target code to  
know for sure, but I think it's frequently true.

>
>
> BTW, this there's an X86/README.txt entry on this that
> you can remove, the one beginning
> "Another instruction selector deficiency".

Ok! Thanks.

Evan

>
>
> Dan
>
> On Aug 25, 2008, at 2:57 PM, Evan Cheng wrote:
>
>> callseq_start is completely eliminated unless there is an alloca, but
>> in that case FP is used to do reload. I think we are safe. Can you
>> think of an unsafe situation?
>>
>> Evan
>>
>> On Aug 25, 2008, at 12:51 PM, Dan Gohman wrote:
>>
>>>
>>> On Aug 24, 2008, at 12:19 PM, Evan Cheng wrote:
>>>
>>>> Author: evancheng
>>>> Date: Sun Aug 24 14:19:55 2008
>>>> New Revision: 55292
>>>>
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=55292&view=rev
>>>> Log:
>>>> Move callseq_start above the call address load to allow load to be
>>>> folded into the call node.
>>>
>>> What happens if the callseq_start involves a non-trivial stack
>>> pointer adjustment and the load's address is spilled and needs
>>> to be reloaded? Could this change cause the reload to happen
>>> from the wrong stack location?
>>>
>>> Dan
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From evan.cheng at apple.com  Mon Aug 25 20:13:45 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 26 Aug 2008 01:13:45 -0000
Subject: [llvm-commits] [llvm] r55348 - /llvm/trunk/lib/Target/X86/README.txt
Message-ID: <200808260113.m7Q1DjXi019031@zion.cs.uiuc.edu>

Author: evancheng
Date: Mon Aug 25 20:13:44 2008
New Revision: 55348

URL: http://llvm.org/viewvc/llvm-project?rev=55348&view=rev
Log:
This is done.

Modified:
    llvm/trunk/lib/Target/X86/README.txt

Modified: llvm/trunk/lib/Target/X86/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README.txt?rev=55348&r1=55347&r2=55348&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/README.txt (original)
+++ llvm/trunk/lib/Target/X86/README.txt Mon Aug 25 20:13:44 2008
@@ -379,27 +379,6 @@
 
 //===---------------------------------------------------------------------===//
 
-Another instruction selector deficiency:
-
-void %bar() {
-	%tmp = load int (int)** %foo
-	%tmp = tail call int %tmp( int 3 )
-	ret void
-}
-
-_bar:
-	subl $12, %esp
-	movl L_foo$non_lazy_ptr, %eax
-	movl (%eax), %eax
-	call *%eax
-	addl $12, %esp
-	ret
-
-The current isel scheme will not allow the load to be folded in the call since
-the load's chain result is read by the callseq_start.
-
-//===---------------------------------------------------------------------===//
-
 For this:
 
 int test(int a)




From resistor at mac.com  Mon Aug 25 20:22:59 2008
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Aug 2008 01:22:59 -0000
Subject: [llvm-commits] [llvm] r55349 -
	/llvm/trunk/utils/TableGen/FastISelEmitter.cpp
Message-ID: <200808260122.m7Q1Mx44019311@zion.cs.uiuc.edu>

Author: resistor
Date: Mon Aug 25 20:22:59 2008
New Revision: 55349

URL: http://llvm.org/viewvc/llvm-project?rev=55349&view=rev
Log:
Throw the switch to allow FastISel to emit instructions whose return types different from their inputs.  Next step: adding lowering pattens in FastISel that actually use these newly available opcodes.

Modified:
    llvm/trunk/utils/TableGen/FastISelEmitter.cpp

Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=55349&r1=55348&r2=55349&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Mon Aug 25 20:22:59 2008
@@ -62,14 +62,15 @@
   ///
   bool initialize(TreePatternNode *InstPatNode,
                   const CodeGenTarget &Target,
-                  MVT::SimpleValueType VT,
-                  const CodeGenRegisterClass *DstRC) {
+                  MVT::SimpleValueType VT) {
     if (!InstPatNode->isLeaf() &&
         InstPatNode->getOperator()->getName() == "imm") {
       Operands.push_back("i");
       return true;
     }
     
+    const CodeGenRegisterClass *DstRC = 0;
+    
     for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
       TreePatternNode *Op = InstPatNode->getChild(i);
       // For now, filter out any operand with a predicate.
@@ -105,8 +106,11 @@
       if (!RC)
         return false;
       // For now, all the operands must have the same register class.
-      if (DstRC != RC)
-        return false;
+      if (DstRC) {
+        if (DstRC != RC)
+          return false;
+      } else
+        DstRC = RC;
       Operands.push_back("r");
     }
     return true;
@@ -220,7 +224,10 @@
 
     Record *InstPatOp = InstPatNode->getOperator();
     std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
-    MVT::SimpleValueType VT = InstPatNode->getTypeNum(0);
+    MVT::SimpleValueType RetVT = InstPatNode->getTypeNum(0);
+    MVT::SimpleValueType VT = RetVT;
+    if (InstPatNode->getNumChildren())
+      VT = InstPatNode->getChild(0)->getTypeNum(0);
 
     // For now, filter out instructions which just set a register to
     // an Operand or an immediate, like MOV32ri.
@@ -233,7 +240,7 @@
 
     // Check all the operands.
     OperandsSignature Operands;
-    if (!Operands.initialize(InstPatNode, Target, VT, DstRC))
+    if (!Operands.initialize(InstPatNode, Target, VT))
       continue;
 
     // Get the predicate that guards this pattern.
@@ -244,9 +251,9 @@
       Pattern.getDstPattern()->getOperator()->getName(),
       DstRC
     };
-    assert(!SimplePatterns[Operands][OpcodeName][VT][VT].count(PredicateCheck) &&
+    assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) &&
            "Duplicate pattern!");
-    SimplePatterns[Operands][OpcodeName][VT][VT][PredicateCheck] = Memo;
+    SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
   }
 
   // Declare the target FastISel class.
@@ -398,7 +405,7 @@
           // Emit one function for the type that demultiplexes on return type.
           OS << "unsigned FastISel::FastEmit_"
              << getLegalCName(Opcode) << "_"
-             << getLegalCName(getName(VT));
+             << getLegalCName(getName(VT)) << "_";
           Operands.PrintManglingSuffix(OS);
           OS << "(MVT::SimpleValueType RetVT";
           if (!Operands.empty())




From gohman at apple.com  Mon Aug 25 20:38:29 2008
From: gohman at apple.com (Dan Gohman)
Date: Tue, 26 Aug 2008 01:38:29 -0000
Subject: [llvm-commits] [llvm] r55350 -
	/llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp
Message-ID: <200808260138.m7Q1cTtt019759@zion.cs.uiuc.edu>

Author: djg
Date: Mon Aug 25 20:38:29 2008
New Revision: 55350

URL: http://llvm.org/viewvc/llvm-project?rev=55350&view=rev
Log:
Avoid a warning about isTargetNullPtr being unused in release builds.

Modified:
    llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp

Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp?rev=55350&r1=55349&r2=55350&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp Mon Aug 25 20:38:29 2008
@@ -267,6 +267,7 @@
   }
 }
 
+#ifndef NDEBUG
 /// isTargetNullPtr - Return whether the target pointer stored at Loc is null.
 static bool isTargetNullPtr(ExecutionEngine *EE, void *Loc) {
   unsigned PtrSize = EE->getTargetData()->getPointerSize();
@@ -275,6 +276,7 @@
       return false;
   return true;
 }
+#endif
 
 /// runFunctionAsMain - This is a helper function which wraps runFunction to
 /// handle the common task of starting up main with the specified argc, argv,




From gohman at apple.com  Mon Aug 25 20:44:34 2008
From: gohman at apple.com (Dan Gohman)
Date: Tue, 26 Aug 2008 01:44:34 -0000
Subject: [llvm-commits] [llvm] r55351 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Message-ID: <200808260144.m7Q1iY0b019999@zion.cs.uiuc.edu>

Author: djg
Date: Mon Aug 25 20:44:34 2008
New Revision: 55351

URL: http://llvm.org/viewvc/llvm-project?rev=55351&view=rev
Log:
Actually recycle SDNode allocations. SelectionDAG is using
RecyclingAllocator, but this change is needed for the nodes
to actually be recycled. This cuts SelectionDAG's memory
usage high-water-mark in half in some cases.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=55351&r1=55350&r2=55351&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Aug 25 20:44:34 2008
@@ -523,7 +523,7 @@
     N->NumOperands = 0;
     
     // Finally, remove N itself.
-    AllNodes.remove(N);
+    NodeAllocator.Deallocate(AllNodes.remove(N));
   }
 }
 
@@ -551,7 +551,8 @@
   if (N->OperandsNeedDelete)
     delete[] N->OperandList;
   
-  AllNodes.remove(N);
+  assert(N != AllNodes.begin());
+  NodeAllocator.Deallocate(AllNodes.remove(N));
 }
 
 /// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that
@@ -777,11 +778,14 @@
 }
 
 void SelectionDAG::allnodes_clear() {
+  assert(&*AllNodes.begin() == &EntryNode);
+  AllNodes.remove(AllNodes.begin());
   while (!AllNodes.empty()) {
     SDNode *N = AllNodes.remove(AllNodes.begin());
     N->SetNextInBucket(0);
     if (N->OperandsNeedDelete)
       delete [] N->OperandList;
+    NodeAllocator.Deallocate(N);
   }
 }
 




From clattner at apple.com  Mon Aug 25 23:15:11 2008
From: clattner at apple.com (Chris Lattner)
Date: Mon, 25 Aug 2008 21:15:11 -0700
Subject: [llvm-commits] [llvm] r55301
	-	/llvm/trunk/lib/VMCore/AsmWriter.cpp
In-Reply-To: <3A24A57D-5611-4273-86CD-F420C77CB634@apple.com>
References: <200808250455.m7P4tlYn030553@zion.cs.uiuc.edu>
	<3A24A57D-5611-4273-86CD-F420C77CB634@apple.com>
Message-ID: <59612744-AFBB-45A7-83F2-97E2B56E9632@apple.com>

On Aug 25, 2008, at 12:47 PM, Dan Gohman wrote:
>> // Module::dump() - Allow printing from debugger
>> -void Module::dump() const { print(errs(), 0); }
>> +void Module::dump() const { print(errs(), 0); errs().flush(); }
>
> It's surprising that this is necessary. For comparison, stderr is
> unbuffered by default. Wouldn't it be better to make errs() return
> a non-buffered stream?

There's no such thing with raw_streams.

-Chris


From clattner at apple.com  Mon Aug 25 23:18:38 2008
From: clattner at apple.com (Chris Lattner)
Date: Mon, 25 Aug 2008 21:18:38 -0700
Subject: [llvm-commits] [llvm] r55349 -
	/llvm/trunk/utils/TableGen/FastISelEmitter.cpp
In-Reply-To: <200808260122.m7Q1Mx44019311@zion.cs.uiuc.edu>
References: <200808260122.m7Q1Mx44019311@zion.cs.uiuc.edu>
Message-ID: <70019B97-95E5-404D-8501-39A2C0A7F0D0@apple.com>


On Aug 25, 2008, at 6:22 PM, Owen Anderson wrote:

> Author: resistor
> Date: Mon Aug 25 20:22:59 2008
> New Revision: 55349
>
> URL: http://llvm.org/viewvc/llvm-project?rev=55349&view=rev
> Log:
> Throw the switch to allow FastISel to emit instructions whose return  
> types different from their inputs.  Next step: adding lowering  
> pattens in FastISel that actually use these newly available opcodes.

Random question: what patterns would use this?

-Chris


From sabre at nondot.org  Tue Aug 26 01:07:48 2008
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 26 Aug 2008 06:07:48 -0000
Subject: [llvm-commits] [llvm] r55355 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200808260607.m7Q67mIu027632@zion.cs.uiuc.edu>

Author: lattner
Date: Tue Aug 26 01:07:47 2008
New Revision: 55355

URL: http://llvm.org/viewvc/llvm-project?rev=55355&view=rev
Log:
typo fix.


Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=55355&r1=55354&r2=55355&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Aug 26 01:07:47 2008
@@ -4231,7 +4231,7 @@
     if (!SawEarlyClobber &&
         OpInfo.Type == InlineAsm::isClobber &&
         OpInfo.ConstraintType == TargetLowering::C_Register) {
-      // Note that we want to ignore things that we don't trick here, like
+      // Note that we want to ignore things that we don't track here, like
       // dirflag, fpsr, flags, etc.
       std::pair<unsigned, const TargetRegisterClass*> PhysReg = 
         TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,




From sabre at nondot.org  Tue Aug 26 01:19:02 2008
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 26 Aug 2008 06:19:02 -0000
Subject: [llvm-commits] [llvm] r55358 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp
 test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
Message-ID: <200808260619.m7Q6J3xp028048@zion.cs.uiuc.edu>

Author: lattner
Date: Tue Aug 26 01:19:02 2008
New Revision: 55358

URL: http://llvm.org/viewvc/llvm-project?rev=55358&view=rev
Log:
If an xmm register is referenced explicitly in an inline asm, make sure to 
assign it to a version of the xmm register with the regclass that matches its
type.  This fixes PR2715, a bug handling some crazy xpcom case in mozilla.

Added:
    llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=55358&r1=55357&r2=55358&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 26 01:19:02 2008
@@ -7221,56 +7221,68 @@
   // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp".  If we
   // really want an 8-bit or 32-bit register, map to the appropriate register
   // class and return the appropriate register.
-  if (Res.second != X86::GR16RegisterClass)
-    return Res;
-
-  if (VT == MVT::i8) {
-    unsigned DestReg = 0;
-    switch (Res.first) {
-    default: break;
-    case X86::AX: DestReg = X86::AL; break;
-    case X86::DX: DestReg = X86::DL; break;
-    case X86::CX: DestReg = X86::CL; break;
-    case X86::BX: DestReg = X86::BL; break;
-    }
-    if (DestReg) {
-      Res.first = DestReg;
-      Res.second = Res.second = X86::GR8RegisterClass;
-    }
-  } else if (VT == MVT::i32) {
-    unsigned DestReg = 0;
-    switch (Res.first) {
-    default: break;
-    case X86::AX: DestReg = X86::EAX; break;
-    case X86::DX: DestReg = X86::EDX; break;
-    case X86::CX: DestReg = X86::ECX; break;
-    case X86::BX: DestReg = X86::EBX; break;
-    case X86::SI: DestReg = X86::ESI; break;
-    case X86::DI: DestReg = X86::EDI; break;
-    case X86::BP: DestReg = X86::EBP; break;
-    case X86::SP: DestReg = X86::ESP; break;
-    }
-    if (DestReg) {
-      Res.first = DestReg;
-      Res.second = Res.second = X86::GR32RegisterClass;
-    }
-  } else if (VT == MVT::i64) {
-    unsigned DestReg = 0;
-    switch (Res.first) {
-    default: break;
-    case X86::AX: DestReg = X86::RAX; break;
-    case X86::DX: DestReg = X86::RDX; break;
-    case X86::CX: DestReg = X86::RCX; break;
-    case X86::BX: DestReg = X86::RBX; break;
-    case X86::SI: DestReg = X86::RSI; break;
-    case X86::DI: DestReg = X86::RDI; break;
-    case X86::BP: DestReg = X86::RBP; break;
-    case X86::SP: DestReg = X86::RSP; break;
-    }
-    if (DestReg) {
-      Res.first = DestReg;
-      Res.second = Res.second = X86::GR64RegisterClass;
-    }
+  if (Res.second == X86::GR16RegisterClass) {
+    if (VT == MVT::i8) {
+      unsigned DestReg = 0;
+      switch (Res.first) {
+      default: break;
+      case X86::AX: DestReg = X86::AL; break;
+      case X86::DX: DestReg = X86::DL; break;
+      case X86::CX: DestReg = X86::CL; break;
+      case X86::BX: DestReg = X86::BL; break;
+      }
+      if (DestReg) {
+        Res.first = DestReg;
+        Res.second = Res.second = X86::GR8RegisterClass;
+      }
+    } else if (VT == MVT::i32) {
+      unsigned DestReg = 0;
+      switch (Res.first) {
+      default: break;
+      case X86::AX: DestReg = X86::EAX; break;
+      case X86::DX: DestReg = X86::EDX; break;
+      case X86::CX: DestReg = X86::ECX; break;
+      case X86::BX: DestReg = X86::EBX; break;
+      case X86::SI: DestReg = X86::ESI; break;
+      case X86::DI: DestReg = X86::EDI; break;
+      case X86::BP: DestReg = X86::EBP; break;
+      case X86::SP: DestReg = X86::ESP; break;
+      }
+      if (DestReg) {
+        Res.first = DestReg;
+        Res.second = Res.second = X86::GR32RegisterClass;
+      }
+    } else if (VT == MVT::i64) {
+      unsigned DestReg = 0;
+      switch (Res.first) {
+      default: break;
+      case X86::AX: DestReg = X86::RAX; break;
+      case X86::DX: DestReg = X86::RDX; break;
+      case X86::CX: DestReg = X86::RCX; break;
+      case X86::BX: DestReg = X86::RBX; break;
+      case X86::SI: DestReg = X86::RSI; break;
+      case X86::DI: DestReg = X86::RDI; break;
+      case X86::BP: DestReg = X86::RBP; break;
+      case X86::SP: DestReg = X86::RSP; break;
+      }
+      if (DestReg) {
+        Res.first = DestReg;
+        Res.second = Res.second = X86::GR64RegisterClass;
+      }
+    }
+  } else if (Res.second == X86::FR32RegisterClass ||
+             Res.second == X86::FR64RegisterClass ||
+             Res.second == X86::VR128RegisterClass) {
+    // Handle references to XMM physical registers that got mapped into the
+    // wrong class.  This can happen with constraints like {xmm0} where the
+    // target independent register mapper will just pick the first match it can
+    // find, ignoring the required type.
+    if (VT == MVT::f32)
+      Res.second = X86::FR32RegisterClass;
+    else if (VT == MVT::f64)
+      Res.second = X86::FR64RegisterClass;
+    else if (X86::VR128RegisterClass->hasType(VT))
+      Res.second = X86::VR128RegisterClass;
   }
 
   return Res;

Added: llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll?rev=55358&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll Tue Aug 26 01:19:02 2008
@@ -0,0 +1,16 @@
+; RUN: llvm-as < %s | llc -mcpu=yonah
+; PR2715
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+	%struct.XPTTypeDescriptorPrefix = type { i8 }
+	%struct.nsISupports = type { i32 (...)** }
+	%struct.nsXPTCMiniVariant = type { %"struct.nsXPTCMiniVariant::._39" }
+	%"struct.nsXPTCMiniVariant::._39" = type { i64 }
+	%struct.nsXPTCVariant = type { %struct.nsXPTCMiniVariant, i8*, %struct.nsXPTType, i8 }
+	%struct.nsXPTType = type { %struct.XPTTypeDescriptorPrefix }
+
+define i32 @XPTC_InvokeByIndex(%struct.nsISupports* %that, i32 %methodIndex, i32 %paramCount, %struct.nsXPTCVariant* %params) nounwind {
+entry:
+	call void asm sideeffect "", "{xmm0},{xmm1},{xmm2},{xmm3},{xmm4},{xmm5},{xmm6},{xmm7},~{dirflag},~{fpsr},~{flags}"( double undef, double undef, double undef, double 1.0, double undef, double 0.0, double undef, double 0.0 ) nounwind
+	ret i32 0
+}




From evan.cheng at apple.com  Tue Aug 26 01:30:15 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 25 Aug 2008 23:30:15 -0700
Subject: [llvm-commits] [llvm] r55318 - in /llvm/trunk/lib/Target/X86:
	X86InstrFormats.td X86InstrMMX.td
In-Reply-To: <200808251832.m7PIWdiQ005650@zion.cs.uiuc.edu>
References: <200808251832.m7PIWdiQ005650@zion.cs.uiuc.edu>
Message-ID: <80B61887-0703-49E2-82AC-9841CDEFF41F@apple.com>

Are you sure? That seems highly unlikely.

Evan

On Aug 25, 2008, at 11:32 AM, Bill Wendling wrote:

> Author: void
> Date: Mon Aug 25 13:32:39 2008
> New Revision: 55318
>
> URL: http://llvm.org/viewvc/llvm-project?rev=55318&view=rev
> Log:
> Nevermind. This broke the bootstrap (?!).
>
> Modified:
>    llvm/trunk/lib/Target/X86/X86InstrFormats.td
>    llvm/trunk/lib/Target/X86/X86InstrMMX.td
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=55318&r1=55317&r2=55318&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Mon Aug 25 13:32:39  
> 2008
> @@ -157,20 +157,16 @@
>
> // SSE2 Instruction Templates:
> //
> -//   SDI    - SSE2 instructions with XD prefix.
> -//   SDIi8  - SSE2 instructions with ImmT == Imm8 and XD prefix.
> -//   SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
> -//   PDI    - SSE2 instructions with TB and OpSize prefixes.
> -//   PDIi8  - SSE2 instructions with ImmT == Imm8 and TB and OpSize  
> prefixes.
> +//   SDI   - SSE2 instructions with XD prefix.
> +//   SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
> +//   PDI   - SSE2 instructions with TB and OpSize prefixes.
> +//   PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize  
> prefixes.
>
> class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,  
> list<dag> pattern>
>       : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
> class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
>             list<dag> pattern>
>       : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
> -class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
> -             list<dag> pattern>
> -      : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
> class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,  
> list<dag> pattern>
>       : I<o, F, outs, ins, asm, pattern>, TB, OpSize,  
> Requires<[HasSSE2]>;
> class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=55318&r1=55317&r2=55318&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Mon Aug 25 13:32:39 2008
> @@ -173,15 +173,15 @@
>                         "movq\t{$src, $dst|$dst, $src}",
>                         [(store (v1i64 VR64:$src), addr:$dst)]>;
>
> -def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMDestMem, (outs VR64:$dst), (ins  
> VR128:$src),
> +def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (outs VR64:$dst), (ins  
> VR128:$src),
>                           "movdq2q\t{$src, $dst|$dst, $src}",
>                           [(set VR64:$dst,
>                             (v1i64 (bitconvert
>                             (i64 (vector_extract (v2i64 VR128:$src),
>                                   (iPTR 0))))))]>;
>
> -def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMDestMem, (outs VR128:$dst),  
> (ins VR64:$src),
> -                           "movq2dq\t{$src, $dst|$dst, $src}",
> +def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (outs VR128:$dst), (ins  
> VR64:$src),
> +                          "movq2dq\t{$src, $dst|$dst, $src}",
>           [(set VR128:$dst,
>                 (v2i64 (vector_shuffle immAllZerosV,
>                         (v2i64 (scalar_to_vector (i64 (bitconvert  
> VR64:$src)))),
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From sabre at nondot.org  Tue Aug 26 01:43:25 2008
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 26 Aug 2008 06:43:25 -0000
Subject: [llvm-commits] [llvm] r55359 - in /llvm/trunk/utils/TableGen:
 Record.h RegisterInfoEmitter.cpp SubtargetEmitter.cpp
Message-ID: <200808260643.m7Q6hPqh028935@zion.cs.uiuc.edu>

Author: lattner
Date: Tue Aug 26 01:43:25 2008
New Revision: 55359

URL: http://llvm.org/viewvc/llvm-project?rev=55359&view=rev
Log:
Stabilize 'getDwarfRegNumFull' output to not depend on random memory 
orders, part of PR2590

Modified:
    llvm/trunk/utils/TableGen/Record.h
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
    llvm/trunk/utils/TableGen/SubtargetEmitter.cpp

Modified: llvm/trunk/utils/TableGen/Record.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.h?rev=55359&r1=55358&r2=55359&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/Record.h (original)
+++ llvm/trunk/utils/TableGen/Record.h Tue Aug 26 01:43:25 2008
@@ -1175,6 +1175,23 @@
   void dump() const;
 };
 
+/// LessRecord - Sorting predicate to sort record pointers by name.
+///
+struct LessRecord {
+  bool operator()(const Record *Rec1, const Record *Rec2) const {
+    return Rec1->getName() < Rec2->getName();
+  }
+};
+
+/// LessRecord - Sorting predicate to sort record pointers by their name field.
+///
+struct LessRecordFieldName {
+  bool operator()(const Record *Rec1, const Record *Rec2) const {
+    return Rec1->getValueAsString("Name") < Rec2->getValueAsString("Name");
+  }
+};
+
+  
 std::ostream &operator<<(std::ostream &OS, const RecordKeeper &RK);
 
 extern RecordKeeper Records;

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=55359&r1=55358&r2=55359&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Tue Aug 26 01:43:25 2008
@@ -422,7 +422,8 @@
   std::map<Record*, std::set<Record*> > RegisterSuperRegs;
   std::map<Record*, std::set<Record*> > RegisterAliases;
   std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors;
-  std::map<Record*, std::vector<int> > DwarfRegNums;
+  typedef std::map<Record*, std::vector<int>, LessRecord> DwarfRegNumsMapTy;
+  DwarfRegNumsMapTy DwarfRegNums;
   
   const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
 
@@ -693,8 +694,8 @@
   }
 
   // Now we know maximal length of number list. Append -1's, where needed
-  for (std::map<Record*, std::vector<int> >::iterator 
-        I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
+  for (DwarfRegNumsMapTy::iterator 
+       I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
     for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
       I->second.push_back(-1);
 
@@ -712,8 +713,11 @@
        << "    default:\n"
        << "      assert(0 && \"Invalid RegNum\");\n"
        << "      return -1;\n";
+    
+    // Sort by name to get a stable order.
+    
 
-    for (std::map<Record*, std::vector<int> >::iterator 
+    for (DwarfRegNumsMapTy::iterator 
            I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
       int RegNo = I->second[i];
       if (RegNo != -2)

Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=55359&r1=55358&r2=55359&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Tue Aug 26 01:43:25 2008
@@ -20,24 +20,6 @@
 using namespace llvm;
 
 //
-// Record sort by name function.
-//
-struct LessRecord {
-  bool operator()(const Record *Rec1, const Record *Rec2) const {
-    return Rec1->getName() < Rec2->getName();
-  }
-};
-
-//
-// Record sort by field "Name" function.
-//
-struct LessRecordFieldName {
-  bool operator()(const Record *Rec1, const Record *Rec2) const {
-    return Rec1->getValueAsString("Name") < Rec2->getValueAsString("Name");
-  }
-};
-
-//
 // Enumeration - Emit the specified class as an enumeration.
 //
 void SubtargetEmitter::Enumeration(std::ostream &OS,




From sabre at nondot.org  Tue Aug 26 01:49:06 2008
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 26 Aug 2008 06:49:06 -0000
Subject: [llvm-commits] [llvm] r55360 -
	/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
Message-ID: <200808260649.m7Q6n605029115@zion.cs.uiuc.edu>

Author: lattner
Date: Tue Aug 26 01:49:06 2008
New Revision: 55360

URL: http://llvm.org/viewvc/llvm-project?rev=55360&view=rev
Log:
stablize SubRegsSet printing, part of PR2590

Modified:
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=55360&r1=55359&r2=55360&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Tue Aug 26 01:49:06 2008
@@ -114,7 +114,8 @@
 }
 
 static void addSuperReg(Record *R, Record *S,
-                        std::map<Record*, std::set<Record*> > &SubRegs,
+                        std::map<Record*, std::set<Record*>,
+                                 LessRecord> &SubRegs,
                         std::map<Record*, std::set<Record*> > &SuperRegs,
                         std::map<Record*, std::set<Record*> > &Aliases) {
   if (R == S) {
@@ -135,7 +136,8 @@
 }
 
 static void addSubSuperReg(Record *R, Record *S,
-                           std::map<Record*, std::set<Record*> > &SubRegs,
+                           std::map<Record*, std::set<Record*>,
+                                    LessRecord> &SubRegs,
                            std::map<Record*, std::set<Record*> > &SuperRegs,
                            std::map<Record*, std::set<Record*> > &Aliases) {
   if (R == S) {
@@ -158,10 +160,10 @@
 
 class RegisterSorter {
 private:
-  std::map<Record*, std::set<Record*> > &RegisterSubRegs;
+  std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
 
 public:
-  RegisterSorter(std::map<Record*, std::set<Record*> > &RS)
+  RegisterSorter(std::map<Record*, std::set<Record*>, LessRecord> &RS)
     : RegisterSubRegs(RS) {};
 
   bool operator()(Record *RegA, Record *RegB) {
@@ -418,7 +420,7 @@
   OS << "  };\n";
 
   // Emit register sub-registers / super-registers, aliases...
-  std::map<Record*, std::set<Record*> > RegisterSubRegs;
+  std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs;
   std::map<Record*, std::set<Record*> > RegisterSuperRegs;
   std::map<Record*, std::set<Record*> > RegisterAliases;
   std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors;
@@ -563,7 +565,7 @@
   OS << "  const unsigned Empty_SubRegsSet[] = { 0 };\n";
   // Loop over all of the registers which have sub-registers, emitting the
   // sub-registers list to memory.
-  for (std::map<Record*, std::set<Record*> >::iterator
+  for (std::map<Record*, std::set<Record*>, LessRecord>::iterator
          I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
     OS << "  const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
     std::vector<Record*> SubRegsVector;




From sabre at nondot.org  Tue Aug 26 01:50:47 2008
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 26 Aug 2008 06:50:47 -0000
Subject: [llvm-commits] [llvm] r55361 -
	/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
Message-ID: <200808260650.m7Q6olTx029175@zion.cs.uiuc.edu>

Author: lattner
Date: Tue Aug 26 01:50:46 2008
New Revision: 55361

URL: http://llvm.org/viewvc/llvm-project?rev=55361&view=rev
Log:
stabilize more printing, this doesn't cause a problem
in the example attached to PR2590, but is a problem in general.

Modified:
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=55361&r1=55360&r2=55361&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Tue Aug 26 01:50:46 2008
@@ -114,10 +114,9 @@
 }
 
 static void addSuperReg(Record *R, Record *S,
-                        std::map<Record*, std::set<Record*>,
-                                 LessRecord> &SubRegs,
-                        std::map<Record*, std::set<Record*> > &SuperRegs,
-                        std::map<Record*, std::set<Record*> > &Aliases) {
+                  std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
+                  std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
+                  std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
   if (R == S) {
     cerr << "Error: recursive sub-register relationship between"
          << " register " << getQualifiedName(R)
@@ -136,10 +135,9 @@
 }
 
 static void addSubSuperReg(Record *R, Record *S,
-                           std::map<Record*, std::set<Record*>,
-                                    LessRecord> &SubRegs,
-                           std::map<Record*, std::set<Record*> > &SuperRegs,
-                           std::map<Record*, std::set<Record*> > &Aliases) {
+                   std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
+                   std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
+                   std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
   if (R == S) {
     cerr << "Error: recursive sub-register relationship between"
          << " register " << getQualifiedName(R)
@@ -421,8 +419,8 @@
 
   // Emit register sub-registers / super-registers, aliases...
   std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs;
-  std::map<Record*, std::set<Record*> > RegisterSuperRegs;
-  std::map<Record*, std::set<Record*> > RegisterAliases;
+  std::map<Record*, std::set<Record*>, LessRecord> RegisterSuperRegs;
+  std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases;
   std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors;
   typedef std::map<Record*, std::vector<int>, LessRecord> DwarfRegNumsMapTy;
   DwarfRegNumsMapTy DwarfRegNums;




From sabre at nondot.org  Tue Aug 26 02:01:28 2008
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 26 Aug 2008 07:01:28 -0000
Subject: [llvm-commits] [llvm] r55363 -
	/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
Message-ID: <200808260701.m7Q71Sig029557@zion.cs.uiuc.edu>

Author: lattner
Date: Tue Aug 26 02:01:28 2008
New Revision: 55363

URL: http://llvm.org/viewvc/llvm-project?rev=55363&view=rev
Log:
code simplification, no functionality change.

Modified:
    llvm/trunk/utils/TableGen/DAGISelEmitter.cpp

Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=55363&r1=55362&r2=55363&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Tue Aug 26 02:01:28 2008
@@ -1653,17 +1653,7 @@
     for (unsigned i = 0, e = PatternsOfOp.size(); i != e; ++i) {
       const PatternToMatch *Pat = PatternsOfOp[i];
       TreePatternNode *SrcPat = Pat->getSrcPattern();
-      MVT::SimpleValueType VT = SrcPat->getTypeNum(0);
-      std::map<MVT::SimpleValueType,
-               std::vector<const PatternToMatch*> >::iterator TI = 
-        PatternsByType.find(VT);
-      if (TI != PatternsByType.end())
-        TI->second.push_back(Pat);
-      else {
-        std::vector<const PatternToMatch*> PVec;
-        PVec.push_back(Pat);
-        PatternsByType.insert(std::make_pair(VT, PVec));
-      }
+      PatternsByType[SrcPat->getTypeNum(0)].push_back(Pat);
     }
 
     for (std::map<MVT::SimpleValueType,




From kremenek at apple.com  Tue Aug 26 11:34:10 2008
From: kremenek at apple.com (Ted Kremenek)
Date: Tue, 26 Aug 2008 16:34:10 -0000
Subject: [llvm-commits] [llvm] r55370 -
	/llvm/trunk/include/llvm/Support/raw_ostream.h
Message-ID: <200808261634.m7QGYDKn028988@zion.cs.uiuc.edu>

Author: kremenek
Date: Tue Aug 26 11:34:01 2008
New Revision: 55370

URL: http://llvm.org/viewvc/llvm-project?rev=55370&view=rev
Log:
Added "str()" method to raw_string_ostream.
str() mirrors the same method in std::ostringstream.
str() flushes the buffered stream contents to string and returns a reference to the string.

Modified:
    llvm/trunk/include/llvm/Support/raw_ostream.h

Modified: llvm/trunk/include/llvm/Support/raw_ostream.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/raw_ostream.h?rev=55370&r1=55369&r2=55370&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Support/raw_ostream.h (original)
+++ llvm/trunk/include/llvm/Support/raw_ostream.h Tue Aug 26 11:34:01 2008
@@ -219,6 +219,13 @@
   raw_string_ostream(std::string &O) : OS(O) {}
   ~raw_string_ostream();
   
+  /// str - Flushes the stream contents to the target string and returns
+  ///  the strings reference.
+  std::string& str() {
+    flush();
+    return OS;
+  }
+  
   /// flush_impl - The is the piece of the class that is implemented by
   /// subclasses.  This outputs the currently buffered data and resets the
   /// buffer to empty.




From kremenek at apple.com  Tue Aug 26 11:41:20 2008
From: kremenek at apple.com (Ted Kremenek)
Date: Tue, 26 Aug 2008 16:41:20 -0000
Subject: [llvm-commits] [llvm] r55371 -
	/llvm/trunk/include/llvm/Support/raw_ostream.h
Message-ID: <200808261641.m7QGfKBF029173@zion.cs.uiuc.edu>

Author: kremenek
Date: Tue Aug 26 11:41:15 2008
New Revision: 55371

URL: http://llvm.org/viewvc/llvm-project?rev=55371&view=rev
Log:
Grammar fix.

Modified:
    llvm/trunk/include/llvm/Support/raw_ostream.h

Modified: llvm/trunk/include/llvm/Support/raw_ostream.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/raw_ostream.h?rev=55371&r1=55370&r2=55371&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Support/raw_ostream.h (original)
+++ llvm/trunk/include/llvm/Support/raw_ostream.h Tue Aug 26 11:41:15 2008
@@ -220,7 +220,7 @@
   ~raw_string_ostream();
   
   /// str - Flushes the stream contents to the target string and returns
-  ///  the strings reference.
+  ///  the string's reference.
   std::string& str() {
     flush();
     return OS;




From resistor at mac.com  Tue Aug 26 12:44:43 2008
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Aug 2008 17:44:43 -0000
Subject: [llvm-commits] [llvm] r55373 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808261744.m7QHihBY031198@zion.cs.uiuc.edu>

Author: resistor
Date: Tue Aug 26 12:44:42 2008
New Revision: 55373

URL: http://llvm.org/viewvc/llvm-project?rev=55373&view=rev
Log:
Add support for fast isel of non-constant fptosi instructions.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55373&r1=55372&r2=55373&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Aug 26 12:44:42 2008
@@ -229,9 +229,13 @@
       if (ConstantInt* CI = dyn_cast<ConstantInt>(I->getOperand(0))) {
         if (I->getType()->isInteger()) {
           MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/false);
-          ValueMap[I] = FastEmit_i(VT.getSimpleVT(), VT.getSimpleVT(),
-                                   ISD::Constant,
-                                   CI->getZExtValue());
+          unsigned result = FastEmit_i(VT.getSimpleVT(), VT.getSimpleVT(),
+                                       ISD::Constant,
+                                       CI->getZExtValue());
+          if (!result)
+            return I;
+          
+          ValueMap[I] = result;
           break;
         } else
           // TODO: Support vector and fp constants.
@@ -239,7 +243,7 @@
       } else if (!isa<Constant>(I->getOperand(0))) {
         // Bitcasts of non-constant values become reg-reg copies.
         MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
-        MVT DstVT = MVT::getMVT(I->getOperand(0)->getType());
+        MVT DstVT = MVT::getMVT(I->getType());
         
         if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
             DstVT == MVT::Other || !DstVT.isSimple() ||
@@ -265,7 +269,41 @@
         
         break;
       } else
-        // Casting a non-integral constant?
+        // TODO: Casting a non-integral constant?
+        return I;
+
+    case Instruction::FPToSI:
+      if (!isa<ConstantFP>(I->getOperand(0))) {
+        MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
+        MVT DstVT = MVT::getMVT(I->getType());
+        
+        if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
+            DstVT == MVT::Other || !DstVT.isSimple() ||
+            !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
+          // Unhandled type. Halt "fast" selection and bail.
+          return I;
+        if (TLI.getOperationAction(ISD::FP_TO_SINT, SrcVT) !=   
+            TargetLowering::Legal)
+          // Unhandled opcode on this type.  Halt "fast" seleciton and bail.
+          return I;
+        
+        unsigned InputReg = ValueMap[I->getOperand(0)];
+        if (!InputReg)
+          // Unhandled operand.  Halt "fast" selection and bail.
+          return I;
+        
+        unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
+                                        DstVT.getSimpleVT(),
+                                        ISD::FP_TO_SINT,
+                                        InputReg);
+        if (!ResultReg)
+          return I;
+        
+        ValueMap[I] = ResultReg;
+        break;
+      } else
+        // TODO: Materialize the FP constant and then convert,
+        // or attempt constant folding.
         return I;
 
     default:




From ggreif at gmail.com  Tue Aug 26 12:44:41 2008
From: ggreif at gmail.com (Gabor Greif)
Date: Tue, 26 Aug 2008 17:44:41 -0000
Subject: [llvm-commits] [llvm] r55372 -
	/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
Message-ID: <200808261744.m7QHifUw031184@zion.cs.uiuc.edu>

Author: ggreif
Date: Tue Aug 26 12:44:40 2008
New Revision: 55372

URL: http://llvm.org/viewvc/llvm-project?rev=55372&view=rev
Log:
fix doxygen comment

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=55372&r1=55371&r2=55372&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Tue Aug 26 12:44:40 2008
@@ -866,7 +866,7 @@
   ///
   inline bool use_empty() const;
 
-  /// use_empty - Return true if there is exactly one node using value
+  /// hasOneUse - Return true if there is exactly one node using value
   /// ResNo of node Val.
   ///
   inline bool hasOneUse() const;




From dpatel at apple.com  Tue Aug 26 12:58:03 2008
From: dpatel at apple.com (Devang Patel)
Date: Tue, 26 Aug 2008 17:58:03 -0000
Subject: [llvm-commits] [llvm] r55374 - in /llvm/trunk:
 lib/Transforms/Scalar/LoopStrengthReduce.cpp
 test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll
Message-ID: <200808261758.m7QHw5FM031611@zion.cs.uiuc.edu>

Author: dpatel
Date: Tue Aug 26 12:57:54 2008
New Revision: 55374

URL: http://llvm.org/viewvc/llvm-project?rev=55374&view=rev
Log:
If IV is used in a int-to-float cast inside the loop then try to eliminate the cast operation.

Modified:
    llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
    llvm/trunk/test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll

Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=55374&r1=55373&r2=55374&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Tue Aug 26 12:57:54 2008
@@ -45,6 +45,7 @@
 STATISTIC(NumInserted,    "Number of PHIs inserted");
 STATISTIC(NumVariable,    "Number of PHIs with variable strides");
 STATISTIC(NumEliminated , "Number of strides eliminated");
+STATISTIC(NumShadow , "Number of Shadow IVs optimized");
 
 namespace {
 
@@ -164,6 +165,7 @@
       AU.addRequired<DominatorTree>();
       AU.addRequired<TargetData>();
       AU.addRequired<ScalarEvolution>();
+      AU.addPreserved<ScalarEvolution>();
     }
     
     /// getCastedVersionOf - Return the specified value casted to uintptr_t.
@@ -177,8 +179,13 @@
                                   IVStrideUse* &CondUse,
                                   const SCEVHandle* &CondStride);
     void OptimizeIndvars(Loop *L);
+
+    /// OptimizeShadowIV - If IV is used in a int-to-float cast
+    /// inside the loop then try to eliminate the cast opeation.
+    void OptimizeShadowIV(Loop *L);
+
     bool FindIVUserForCond(ICmpInst *Cond, IVStrideUse *&CondUse,
-                       const SCEVHandle *&CondStride);
+                           const SCEVHandle *&CondStride);
     bool RequiresTypeConversion(const Type *Ty, const Type *NewTy);
     unsigned CheckForIVReuse(bool, bool, const SCEVHandle&,
                              IVExpr&, const Type*,
@@ -1689,12 +1696,122 @@
   return Cond;
 }
 
+/// OptimizeShadowIV - If IV is used in a int-to-float cast
+/// inside the loop then try to eliminate the cast opeation.
+void LoopStrengthReduce::OptimizeShadowIV(Loop *L) {
+
+  SCEVHandle IterationCount = SE->getIterationCount(L);
+  if (isa<SCEVCouldNotCompute>(IterationCount))
+    return;
+
+  for (unsigned Stride = 0, e = StrideOrder.size(); Stride != e;
+       ++Stride) {
+    std::map<SCEVHandle, IVUsersOfOneStride>::iterator SI = 
+      IVUsesByStride.find(StrideOrder[Stride]);
+    assert(SI != IVUsesByStride.end() && "Stride doesn't exist!");
+    if (!isa<SCEVConstant>(SI->first))
+      continue;
+
+    for (std::vector<IVStrideUse>::iterator UI = SI->second.Users.begin(),
+           E = SI->second.Users.end(); UI != E; /* empty */) {
+      std::vector<IVStrideUse>::iterator CandidateUI = UI;
+      UI++;
+      Instruction *ShadowUse = CandidateUI->User;
+      const Type *DestTy = NULL;
+
+      /* If shadow use is a int->float cast then insert a second IV
+         to elminate this cast.
+
+           for (unsigned i = 0; i < n; ++i) 
+             foo((double)i);
+
+         is trnasformed into
+
+           double d = 0.0;
+           for (unsigned i = 0; i < n; ++i, ++d) 
+             foo(d);
+      */
+      UIToFPInst *UCast = dyn_cast<UIToFPInst>(CandidateUI->User);
+      if (UCast) 
+        DestTy = UCast->getDestTy();
+      else {
+        SIToFPInst *SCast = dyn_cast<SIToFPInst>(CandidateUI->User);
+        if (!SCast) continue;
+        DestTy = SCast->getDestTy();
+      }
+      
+      PHINode *PH = dyn_cast<PHINode>(ShadowUse->getOperand(0));
+      if (!PH) continue;
+      if (PH->getNumIncomingValues() != 2) continue;
+
+      const Type *SrcTy = PH->getType();
+      int Mantissa = DestTy->getFPMantissaWidth();
+      if (Mantissa == -1) continue; 
+      if ((int)TD->getTypeSizeInBits(SrcTy) > Mantissa)
+        continue;
+
+      unsigned Entry, Latch;
+      if (PH->getIncomingBlock(0) == L->getLoopPreheader()) {
+        Entry = 0;
+        Latch = 1;
+      } else {
+        Entry = 1;
+        Latch = 0;
+      }
+        
+      ConstantInt *Init = dyn_cast<ConstantInt>(PH->getIncomingValue(Entry));
+      if (!Init) continue;
+      ConstantFP *NewInit = ConstantFP::get(DestTy, Init->getZExtValue());
+
+      BinaryOperator *Incr = 
+        dyn_cast<BinaryOperator>(PH->getIncomingValue(Latch));
+      if (!Incr) continue;
+      if (Incr->getOpcode() != Instruction::Add
+          && Incr->getOpcode() != Instruction::Sub)
+        continue;
+
+      /* Initialize new IV, double d = 0.0 in above example. */
+      ConstantInt *C = NULL;
+      if (Incr->getOperand(0) == PH)
+        C = dyn_cast<ConstantInt>(Incr->getOperand(1));
+      else if (Incr->getOperand(1) == PH)
+        C = dyn_cast<ConstantInt>(Incr->getOperand(0));
+      else
+        continue;
+
+      if (!C) continue;
+
+      /* Add new PHINode. */
+      PHINode *NewPH = PHINode::Create(DestTy, "IV.S.", PH);
+
+      /* create new icnrement. '++d' in above example. */
+      ConstantFP *CFP = ConstantFP::get(DestTy, C->getZExtValue());
+      BinaryOperator *NewIncr = 
+        BinaryOperator::Create(Incr->getOpcode(),
+                               NewPH, CFP, "IV.S.next.", Incr);
+
+      NewPH->addIncoming(NewInit, PH->getIncomingBlock(Entry));
+      NewPH->addIncoming(NewIncr, PH->getIncomingBlock(Latch));
+
+      /* Remove cast operation */
+      SE->deleteValueFromRecords(ShadowUse);
+      ShadowUse->replaceAllUsesWith(NewPH);
+      ShadowUse->eraseFromParent();
+      SI->second.Users.erase(CandidateUI);
+      NumShadow++;
+      break;
+    }
+  }
+}
+
 // OptimizeIndvars - Now that IVUsesByStride is set up with all of the indvar
 // uses in the loop, look to see if we can eliminate some, in favor of using
 // common indvars for the different uses.
 void LoopStrengthReduce::OptimizeIndvars(Loop *L) {
   // TODO: implement optzns here.
 
+  OptimizeShadowIV(L);
+
   // Finally, get the terminating condition for the loop if possible.  If we
   // can, we want to change it to use a post-incremented version of its
   // induction variable, to allow coalescing the live ranges for the IV into
@@ -1852,6 +1969,5 @@
     }
     DeleteTriviallyDeadInstructions(DeadInsts);
   }
-
   return Changed;
 }

Modified: llvm/trunk/test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll?rev=55374&r1=55373&r2=55374&view=diff

==============================================================================
--- llvm/trunk/test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll (original)
+++ llvm/trunk/test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll Tue Aug 26 12:57:54 2008
@@ -1,5 +1,4 @@
 ; RUN: llvm-as < %s | opt -loop-reduce | llvm-dis | grep "phi double" | count 1
-; XFAIL: *
 
 define void @foobar(i32 %n) nounwind {
 entry:




From resistor at mac.com  Tue Aug 26 13:03:31 2008
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Aug 2008 18:03:31 -0000
Subject: [llvm-commits] [llvm] r55375 - in /llvm/trunk: include/llvm/Target/
 lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/
 lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/
 lib/Target/Sparc/ lib/Target/X86/
Message-ID: <200808261803.m7QI3VUV031817@zion.cs.uiuc.edu>

Author: resistor
Date: Tue Aug 26 13:03:31 2008
New Revision: 55375

URL: http://llvm.org/viewvc/llvm-project?rev=55375&view=rev
Log:
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.

Modified:
    llvm/trunk/include/llvm/Target/TargetInstrInfo.h
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.h
    llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp
    llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h
    llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
    llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h
    llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp
    llvm/trunk/lib/Target/IA64/IA64InstrInfo.h
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h
    llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
    llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.h

Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=55375&r1=55374&r2=55375&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Tue Aug 26 13:03:31 2008
@@ -221,7 +221,7 @@
   }
   
   /// copyRegToReg - Add a copy between a pair of registers
-  virtual void copyRegToReg(MachineBasicBlock &MBB,
+  virtual bool copyRegToReg(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
                             unsigned DestReg, unsigned SrcReg,
                             const TargetRegisterClass *DestRC,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55375&r1=55374&r2=55375&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Aug 26 13:03:31 2008
@@ -250,9 +250,6 @@
             !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
           // Unhandled type. Halt "fast" selection and bail.
           return I;
-        if (!TLI.isConvertLegal(SrcVT, DstVT))
-          // Illegal conversion.  Halt "fast" selection and bail.
-          return I;
         
         // Otherwise, insert a register-to-register copy.
         TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
@@ -264,9 +261,12 @@
           // Unhandled operand. Halt "fast" selection and bail.
           return false;
         
-        TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Op0, DstClass, SrcClass);
-        ValueMap[I] = ResultReg;
+        bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+                                             Op0, DstClass, SrcClass);
+        if (!InsertedCopy)
+          return I;
         
+        ValueMap[I] = ResultReg;
         break;
       } else
         // TODO: Casting a non-integral constant?

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=55375&r1=55374&r2=55375&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Tue Aug 26 13:03:31 2008
@@ -459,14 +459,14 @@
   return 2;
 }
 
-void ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+bool ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator I,
                                    unsigned DestReg, unsigned SrcReg,
                                    const TargetRegisterClass *DestRC,
                                    const TargetRegisterClass *SrcRC) const {
   if (DestRC != SrcRC) {
-    cerr << "Not yet supported!";
-    abort();
+    // Not yet supported!
+    return false;
   }
 
   if (DestRC == ARM::GPRRegisterClass) {
@@ -484,7 +484,9 @@
     AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYD), DestReg)
                    .addReg(SrcReg));
   else
-    abort();
+    return false;
+  
+  return true;
 }
 
 static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=55375&r1=55374&r2=55375&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Tue Aug 26 13:03:31 2008
@@ -163,7 +163,7 @@
   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                                 MachineBasicBlock *FBB,
                             const SmallVectorImpl<MachineOperand> &Cond) const;
-  virtual void copyRegToReg(MachineBasicBlock &MBB,
+  virtual bool copyRegToReg(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator I,
                             unsigned DestReg, unsigned SrcReg,
                             const TargetRegisterClass *DestRC,

Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=55375&r1=55374&r2=55375&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Tue Aug 26 13:03:31 2008
@@ -133,15 +133,15 @@
   return 2;
 }
 
-void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator MI,
                                      unsigned DestReg, unsigned SrcReg,
                                      const TargetRegisterClass *DestRC,
                                      const TargetRegisterClass *SrcRC) const {
   //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
   if (DestRC != SrcRC) {
-    cerr << "Not yet supported!";
-    abort();
+    // Not yet supported!
+    return false;
   }
 
   if (DestRC == Alpha::GPRCRegisterClass) {
@@ -151,9 +151,11 @@
   } else if (DestRC == Alpha::F8RCRegisterClass) {
     BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
   } else {
-    cerr << "Attempt to copy register that is not GPR or FPR";
-    abort();
+    // Attempt to copy register that is not GPR or FPR
+    return false;
   }
+  
+  return true;
 }
 
 void

Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h?rev=55375&r1=55374&r2=55375&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h Tue Aug 26 13:03:31 2008
@@ -42,7 +42,7 @@
   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                             MachineBasicBlock *FBB,
                             const SmallVectorImpl<MachineOperand> &Cond) const;
-  virtual void copyRegToReg(MachineBasicBlock &MBB,
+  virtual bool copyRegToReg(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
                             unsigned DestReg, unsigned SrcReg,
                             const TargetRegisterClass *DestRC,

Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=55375&r1=55374&r2=55375&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Tue Aug 26 13:03:31 2008
@@ -180,7 +180,7 @@
   return 0;
 }
 
-void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MI,
                                    unsigned DestReg, unsigned SrcReg,
                                    const TargetRegisterClass *DestRC,
@@ -218,9 +218,11 @@
     BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg)
       .addReg(SrcReg);
   } else {
-    cerr << "Attempt to copy unknown/unsupported register class!\n";
-    abort();
+    // Attempt to copy unknown/unsupported register class!
+    return false;
   }
+  
+  return true;
 }
 
 void

Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h?rev=55375&r1=55374&r2=55375&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h Tue Aug 26 13:03:31 2008
@@ -46,7 +46,7 @@
     unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
     unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
     
-    virtual void copyRegToReg(MachineBasicBlock &MBB,
+    virtual bool copyRegToReg(MachineBasicBlock &MBB,
                               MachineBasicBlock::iterator MI,
                               unsigned DestReg, unsigned SrcReg,
                               const TargetRegisterClass *DestRC,

Modified: llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp?rev=55375&r1=55374&r2=55375&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp Tue Aug 26 13:03:31 2008
@@ -57,14 +57,14 @@
   return 1;
 }
 
-void IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+bool IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MI,
                                    unsigned DestReg, unsigned SrcReg,
                                    const TargetRegisterClass *DestRC,
                                    const TargetRegisterClass *SrcRC) const {
   if (DestRC != SrcRC) {
-    cerr << "Not yet supported!";
-    abort();
+    // Not yet supported!
+    return false;
   }
 
   if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
@@ -73,6 +73,8 @@
       .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
   else // otherwise, MOV works (for both gen. regs and FP regs)
     BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg);
+  
+  return true;
 }
 
 void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,

Modified: llvm/trunk/lib/Target/IA64/IA64InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64InstrInfo.h?rev=55375&r1=55374&r2=55375&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64InstrInfo.h (original)
+++ llvm/trunk/lib/Target/IA64/IA64InstrInfo.h Tue Aug 26 13:03:31 2008
@@ -40,7 +40,7 @@
   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                                 MachineBasicBlock *FBB,
                             const SmallVectorImpl<MachineOperand> &Cond) const;
-  virtual void copyRegToReg(MachineBasicBlock &MBB,
+  virtual bool copyRegToReg(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
                             unsigned DestReg, unsigned SrcReg,
                             const TargetRegisterClass *DestRC,

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=55375&r1=55374&r2=55375&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Tue Aug 26 13:03:31 2008
@@ -118,7 +118,7 @@
   BuildMI(MBB, MI, get(Mips::NOP));
 }
 
-void MipsInstrInfo::
+bool MipsInstrInfo::
 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
              unsigned DestReg, unsigned SrcReg,
              const TargetRegisterClass *DestRC,
@@ -141,10 +141,10 @@
       BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg);
     else if ((SrcRC == Mips::CCRRegisterClass) && 
              (SrcReg == Mips::FCR31))
-      return; // This register is used implicitly, no copy needed.
+      return true; // This register is used implicitly, no copy needed.
     else if ((DestRC == Mips::CCRRegisterClass) && 
              (DestReg == Mips::FCR31))
-      return; // This register is used implicitly, no copy needed.
+      return true; // This register is used implicitly, no copy needed.
     else if ((DestRC == Mips::HILORegisterClass) &&
              (SrcRC == Mips::CPURegsRegisterClass)) {
       unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
@@ -154,9 +154,10 @@
       unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
       BuildMI(MBB, I, get(Opc), DestReg);
     } else
-      assert (0 && "DestRC != SrcRC, Can't copy this register");
+      // DestRC != SrcRC, Can't copy this register
+      return false;
 
-    return;
+    return true;
   }
 
   if (DestRC == Mips::CPURegsRegisterClass)
@@ -169,7 +170,10 @@
   else if (DestRC == Mips::AFGR64RegisterClass)
     BuildMI(MBB, I, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
   else
-    assert (0 && "Can't copy this register");
+    // Can't copy this register
+    return false;
+  
+  return true;
 }
 
 void MipsInstrInfo::

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=55375&r1=55374&r2=55375&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Tue Aug 26 13:03:31 2008
@@ -169,7 +169,7 @@
   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                                 MachineBasicBlock *FBB,
                             const SmallVectorImpl<MachineOperand> &Cond) const;
-  virtual void copyRegToReg(MachineBasicBlock &MBB, 
+  virtual bool copyRegToReg(MachineBasicBlock &MBB, 
                             MachineBasicBlock::iterator I,
                             unsigned DestReg, unsigned SrcReg,
                             const TargetRegisterClass *DestRC,

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=55375&r1=55374&r2=55375&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Tue Aug 26 13:03:31 2008
@@ -315,14 +315,14 @@
   return 2;
 }
 
-void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MI,
                                    unsigned DestReg, unsigned SrcReg,
                                    const TargetRegisterClass *DestRC,
                                    const TargetRegisterClass *SrcRC) const {
   if (DestRC != SrcRC) {
-    cerr << "Not yet supported!";
-    abort();
+    // Not yet supported!
+    return false;
   }
 
   if (DestRC == PPC::GPRCRegisterClass) {
@@ -340,9 +340,11 @@
   } else if (DestRC == PPC::CRBITRCRegisterClass) {
     BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
   } else {
-    cerr << "Attempt to copy register that is not GPR or FPR";
-    abort();
+    // Attempt to copy register that is not GPR or FPR
+    return false;
   }
+  
+  return true;
 }
 
 bool

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=55375&r1=55374&r2=55375&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Tue Aug 26 13:03:31 2008
@@ -112,7 +112,7 @@
   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                                 MachineBasicBlock *FBB,
                             const SmallVectorImpl<MachineOperand> &Cond) const;
-  virtual void copyRegToReg(MachineBasicBlock &MBB,
+  virtual bool copyRegToReg(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
                             unsigned DestReg, unsigned SrcReg,
                             const TargetRegisterClass *DestRC,

Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=55375&r1=55374&r2=55375&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Tue Aug 26 13:03:31 2008
@@ -109,14 +109,14 @@
   return 1;
 }
 
-void SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+bool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator I,
                                      unsigned DestReg, unsigned SrcReg,
                                      const TargetRegisterClass *DestRC,
                                      const TargetRegisterClass *SrcRC) const {
   if (DestRC != SrcRC) {
-    cerr << "Not yet supported!";
-    abort();
+    // Not yet supported!
+    return false;
   }
 
   if (DestRC == SP::IntRegsRegisterClass)
@@ -127,7 +127,10 @@
     BuildMI(MBB, I, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
       .addReg(SrcReg);
   else
-    assert (0 && "Can't copy this register");
+    // Can't copy this register
+    return false;
+
+  return true;
 }
 
 void SparcInstrInfo::

Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h?rev=55375&r1=55374&r2=55375&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h Tue Aug 26 13:03:31 2008
@@ -68,7 +68,7 @@
                                 MachineBasicBlock *FBB,
                             const SmallVectorImpl<MachineOperand> &Cond) const;
 
-  virtual void copyRegToReg(MachineBasicBlock &MBB,
+  virtual bool copyRegToReg(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator I,
                             unsigned DestReg, unsigned SrcReg,
                             const TargetRegisterClass *DestRC,

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=55375&r1=55374&r2=55375&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Aug 26 13:03:31 2008
@@ -1592,7 +1592,7 @@
   return 2;
 }
 
-void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator MI,
                                 unsigned DestReg, unsigned SrcReg,
                                 const TargetRegisterClass *DestRC,
@@ -1626,11 +1626,10 @@
     } else if (DestRC == &X86::VR64RegClass) {
       Opc = X86::MMX_MOVQ64rr;
     } else {
-      assert(0 && "Unknown regclass");
-      abort();
+      return false;
     }
     BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
-    return;
+    return true;
   }
   
   // Moving EFLAGS to / from another register requires a push and a pop.
@@ -1639,30 +1638,31 @@
     if (DestRC == &X86::GR64RegClass) {
       BuildMI(MBB, MI, get(X86::PUSHFQ));
       BuildMI(MBB, MI, get(X86::POP64r), DestReg);
-      return;
+      return true;
     } else if (DestRC == &X86::GR32RegClass) {
       BuildMI(MBB, MI, get(X86::PUSHFD));
       BuildMI(MBB, MI, get(X86::POP32r), DestReg);
-      return;
+      return true;
     }
   } else if (DestRC == &X86::CCRRegClass) {
     assert(DestReg == X86::EFLAGS);
     if (SrcRC == &X86::GR64RegClass) {
       BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
       BuildMI(MBB, MI, get(X86::POPFQ));
-      return;
+      return true;
     } else if (SrcRC == &X86::GR32RegClass) {
       BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
       BuildMI(MBB, MI, get(X86::POPFD));
-      return;
+      return true;
     }
   }
   
   // Moving from ST(0) turns into FpGET_ST0_32 etc.
   if (SrcRC == &X86::RSTRegClass) {
     // Copying from ST(0)/ST(1).
-    assert((SrcReg == X86::ST0 || SrcReg == X86::ST1) &&
-           "Can only copy from ST(0)/ST(1) right now");
+    if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
+      // Can only copy from ST(0)/ST(1) right now
+      return false;
     bool isST0 = SrcReg == X86::ST0;
     unsigned Opc;
     if (DestRC == &X86::RFP32RegClass)
@@ -1674,13 +1674,15 @@
       Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
     }
     BuildMI(MBB, MI, get(Opc), DestReg);
-    return;
+    return true;
   }
 
   // Moving to ST(0) turns into FpSET_ST0_32 etc.
   if (DestRC == &X86::RSTRegClass) {
     // Copying to ST(0).  FIXME: handle ST(1) also
-    assert(DestReg == X86::ST0 && "Can only copy to TOS right now");
+    if (DestReg != X86::ST0)
+      // Can only copy to TOS right now
+      return false;
     unsigned Opc;
     if (SrcRC == &X86::RFP32RegClass)
       Opc = X86::FpSET_ST0_32;
@@ -1691,11 +1693,11 @@
       Opc = X86::FpSET_ST0_80;
     }
     BuildMI(MBB, MI, get(Opc)).addReg(SrcReg);
-    return;
+    return true;
   }
   
-  assert(0 && "Not yet supported!");
-  abort();
+  // Not yet supported!
+  return false;
 }
 
 static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=55375&r1=55374&r2=55375&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Tue Aug 26 13:03:31 2008
@@ -311,7 +311,7 @@
   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                                 MachineBasicBlock *FBB,
                             const SmallVectorImpl<MachineOperand> &Cond) const;
-  virtual void copyRegToReg(MachineBasicBlock &MBB,
+  virtual bool copyRegToReg(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
                             unsigned DestReg, unsigned SrcReg,
                             const TargetRegisterClass *DestRC,




From resistor at mac.com  Tue Aug 26 13:50:01 2008
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Aug 2008 18:50:01 -0000
Subject: [llvm-commits] [llvm] r55376 -
	/llvm/trunk/utils/TableGen/FastISelEmitter.cpp
Message-ID: <200808261850.m7QIo2NE000833@zion.cs.uiuc.edu>

Author: resistor
Date: Tue Aug 26 13:50:00 2008
New Revision: 55376

URL: http://llvm.org/viewvc/llvm-project?rev=55376&view=rev
Log:
We need to check that the return type is correct, even in cases where we don't
have a return type that differs from the operand types.

Modified:
    llvm/trunk/utils/TableGen/FastISelEmitter.cpp

Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=55376&r1=55375&r2=55376&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Tue Aug 26 13:50:00 2008
@@ -437,6 +437,9 @@
           Operands.PrintParameters(OS);
           OS << ") {\n";
           
+          OS << "  if (RetVT != " << getName(RM.begin()->first)
+             << ")\n    return 0;\n";
+          
           const PredMap &PM = RM.begin()->second;
           bool HasPred = false;
           




From resistor at mac.com  Tue Aug 26 13:50:40 2008
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Aug 2008 18:50:40 -0000
Subject: [llvm-commits] [llvm] r55377 -
	/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Message-ID: <200808261850.m7QIoffI000861@zion.cs.uiuc.edu>

Author: resistor
Date: Tue Aug 26 13:50:40 2008
New Revision: 55377

URL: http://llvm.org/viewvc/llvm-project?rev=55377&view=rev
Log:
These assertions should be return false's instead, allowing the client to detect the failure.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=55377&r1=55376&r2=55377&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Aug 26 13:50:40 2008
@@ -1634,7 +1634,8 @@
   
   // Moving EFLAGS to / from another register requires a push and a pop.
   if (SrcRC == &X86::CCRRegClass) {
-    assert(SrcReg == X86::EFLAGS);
+    if (SrcReg != X86::EFLAGS)
+      return false;
     if (DestRC == &X86::GR64RegClass) {
       BuildMI(MBB, MI, get(X86::PUSHFQ));
       BuildMI(MBB, MI, get(X86::POP64r), DestReg);
@@ -1645,7 +1646,8 @@
       return true;
     }
   } else if (DestRC == &X86::CCRRegClass) {
-    assert(DestReg == X86::EFLAGS);
+    if (DestReg != X86::EFLAGS)
+      return false;
     if (SrcRC == &X86::GR64RegClass) {
       BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
       BuildMI(MBB, MI, get(X86::POPFQ));
@@ -1670,7 +1672,8 @@
     else if (DestRC == &X86::RFP64RegClass)
       Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
     else {
-      assert(DestRC == &X86::RFP80RegClass);
+      if (DestRC != &X86::RFP80RegClass)
+        return false;
       Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
     }
     BuildMI(MBB, MI, get(Opc), DestReg);
@@ -1689,7 +1692,8 @@
     else if (SrcRC == &X86::RFP64RegClass)
       Opc = X86::FpSET_ST0_64;
     else {
-      assert(SrcRC == &X86::RFP80RegClass);
+      if (SrcRC != &X86::RFP80RegClass)
+        return false;
       Opc = X86::FpSET_ST0_80;
     }
     BuildMI(MBB, MI, get(Opc)).addReg(SrcReg);




From resistor at mac.com  Tue Aug 26 13:51:24 2008
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Aug 2008 18:51:24 -0000
Subject: [llvm-commits] [llvm] r55378 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808261851.m7QIpPYj000890@zion.cs.uiuc.edu>

Author: resistor
Date: Tue Aug 26 13:51:24 2008
New Revision: 55378

URL: http://llvm.org/viewvc/llvm-project?rev=55378&view=rev
Log:
Use a combination of copyRegToReg and ISD::BIT_CONVERT when doing fast isel of bitcasts,
allowing it to support the full range of conversions people might ask for in a correct manner.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55378&r1=55377&r2=55378&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Aug 26 13:51:24 2008
@@ -251,19 +251,30 @@
           // Unhandled type. Halt "fast" selection and bail.
           return I;
         
-        // Otherwise, insert a register-to-register copy.
-        TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
-        TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
         unsigned Op0 = ValueMap[I->getOperand(0)];
-        unsigned ResultReg = createResultReg(DstClass);
-        
         if (Op0 == 0)
           // Unhandled operand. Halt "fast" selection and bail.
           return false;
         
-        bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
-                                             Op0, DstClass, SrcClass);
-        if (!InsertedCopy)
+        // First, try to perform the bitcast by inserting a reg-reg copy.
+        unsigned ResultReg = 0;
+        if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
+          TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
+          TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
+          ResultReg = createResultReg(DstClass);
+          
+          bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+                                               Op0, DstClass, SrcClass);
+          if (!InsertedCopy)
+            ResultReg = 0;
+        }
+        
+        // If the reg-reg copy failed, select a BIT_CONVERT opcode.
+        if (!ResultReg)
+          ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
+                                 ISD::BIT_CONVERT, Op0);
+        
+        if (!ResultReg)
           return I;
         
         ValueMap[I] = ResultReg;




From cedric.venet at laposte.net  Tue Aug 26 14:49:04 2008
From: cedric.venet at laposte.net (Cedric Venet)
Date: Tue, 26 Aug 2008 19:49:04 -0000
Subject: [llvm-commits] [llvm] r55380 - in /llvm/trunk:
 include/llvm/Target/TargetInstrInfo.h
 utils/TableGen/RegisterInfoEmitter.cpp
Message-ID: <200808261949.m7QJn4Fg004180@zion.cs.uiuc.edu>

Author: venet
Date: Tue Aug 26 14:49:04 2008
New Revision: 55380

URL: http://llvm.org/viewvc/llvm-project?rev=55380&view=rev
Log:
- small bug corrected: incorrect iterator type.
- fix to please VS: add a return after an assert.

Modified:
    llvm/trunk/include/llvm/Target/TargetInstrInfo.h
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=55380&r1=55379&r2=55380&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Tue Aug 26 14:49:04 2008
@@ -227,6 +227,7 @@
                             const TargetRegisterClass *DestRC,
                             const TargetRegisterClass *SrcRC) const {
     assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
+    return false;
   }
   
   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=55380&r1=55379&r2=55380&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Tue Aug 26 14:49:04 2008
@@ -547,7 +547,7 @@
   OS << "  const unsigned Empty_AliasSet[] = { 0 };\n";
   // Loop over all of the registers which have aliases, emitting the alias list
   // to memory.
-  for (std::map<Record*, std::set<Record*> >::iterator
+  for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
          I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
     OS << "  const unsigned " << I->first->getName() << "_AliasSet[] = { ";
     for (std::set<Record*>::iterator ASI = I->second.begin(),
@@ -584,7 +584,7 @@
   OS << "  const unsigned Empty_SuperRegsSet[] = { 0 };\n";
   // Loop over all of the registers which have super-registers, emitting the
   // super-registers list to memory.
-  for (std::map<Record*, std::set<Record*> >::iterator
+  for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
          I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
     OS << "  const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
 




From isanbard at gmail.com  Tue Aug 26 15:03:24 2008
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 26 Aug 2008 13:03:24 -0700
Subject: [llvm-commits] [llvm] r55318 - in /llvm/trunk/lib/Target/X86:
	X86InstrFormats.td X86InstrMMX.td
In-Reply-To: <80B61887-0703-49E2-82AC-9841CDEFF41F@apple.com>
References: <200808251832.m7PIWdiQ005650@zion.cs.uiuc.edu>
	<80B61887-0703-49E2-82AC-9841CDEFF41F@apple.com>
Message-ID: <16e5fdf90808261303n34964729qa1934f14f1f26cba@mail.gmail.com>

Pretty sure. When I applied it, it ICEd saying "illegal instruction".
Removing it made it go away.

My guess is that it used this instruction because it was marked as
"HasSSE2", but it shouldn't have because it does MMX stuff.

-bw

On Mon, Aug 25, 2008 at 11:30 PM, Evan Cheng <evan.cheng at apple.com> wrote:
> Are you sure? That seems highly unlikely.
>
> Evan
>
> On Aug 25, 2008, at 11:32 AM, Bill Wendling wrote:
>
>> Author: void
>> Date: Mon Aug 25 13:32:39 2008
>> New Revision: 55318
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=55318&view=rev
>> Log:
>> Nevermind. This broke the bootstrap (?!).
>>
>> Modified:
>>    llvm/trunk/lib/Target/X86/X86InstrFormats.td
>>    llvm/trunk/lib/Target/X86/X86InstrMMX.td
>>
>> Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=55318&r1=55317&r2=55318&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> ======================================================================
>> --- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
>> +++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Mon Aug 25 13:32:39
>> 2008
>> @@ -157,20 +157,16 @@
>>
>> // SSE2 Instruction Templates:
>> //
>> -//   SDI    - SSE2 instructions with XD prefix.
>> -//   SDIi8  - SSE2 instructions with ImmT == Imm8 and XD prefix.
>> -//   SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
>> -//   PDI    - SSE2 instructions with TB and OpSize prefixes.
>> -//   PDIi8  - SSE2 instructions with ImmT == Imm8 and TB and OpSize
>> prefixes.
>> +//   SDI   - SSE2 instructions with XD prefix.
>> +//   SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
>> +//   PDI   - SSE2 instructions with TB and OpSize prefixes.
>> +//   PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize
>> prefixes.
>>
>> class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
>> list<dag> pattern>
>>       : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
>> class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
>>             list<dag> pattern>
>>       : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
>> -class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
>> -             list<dag> pattern>
>> -      : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
>> class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
>> list<dag> pattern>
>>       : I<o, F, outs, ins, asm, pattern>, TB, OpSize,
>> Requires<[HasSSE2]>;
>> class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
>>
>> Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=55318&r1=55317&r2=55318&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> ======================================================================
>> --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
>> +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Mon Aug 25 13:32:39 2008
>> @@ -173,15 +173,15 @@
>>                         "movq\t{$src, $dst|$dst, $src}",
>>                         [(store (v1i64 VR64:$src), addr:$dst)]>;
>>
>> -def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMDestMem, (outs VR64:$dst), (ins
>> VR128:$src),
>> +def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (outs VR64:$dst), (ins
>> VR128:$src),
>>                           "movdq2q\t{$src, $dst|$dst, $src}",
>>                           [(set VR64:$dst,
>>                             (v1i64 (bitconvert
>>                             (i64 (vector_extract (v2i64 VR128:$src),
>>                                   (iPTR 0))))))]>;
>>
>> -def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMDestMem, (outs VR128:$dst),
>> (ins VR64:$src),
>> -                           "movq2dq\t{$src, $dst|$dst, $src}",
>> +def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (outs VR128:$dst), (ins
>> VR64:$src),
>> +                          "movq2dq\t{$src, $dst|$dst, $src}",
>>           [(set VR128:$dst,
>>                 (v2i64 (vector_shuffle immAllZerosV,
>>                         (v2i64 (scalar_to_vector (i64 (bitconvert
>> VR64:$src)))),
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From resistor at mac.com  Tue Aug 26 15:37:00 2008
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Aug 2008 20:37:00 -0000
Subject: [llvm-commits] [llvm] r55381 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808262037.m7QKb0Ze005775@zion.cs.uiuc.edu>

Author: resistor
Date: Tue Aug 26 15:37:00 2008
New Revision: 55381

URL: http://llvm.org/viewvc/llvm-project?rev=55381&view=rev
Log:
Add support for fast isel of sitofp, and remove some unnecessary and imprecise legality checks.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55381&r1=55380&r2=55381&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Aug 26 15:37:00 2008
@@ -293,10 +293,6 @@
             !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
           // Unhandled type. Halt "fast" selection and bail.
           return I;
-        if (TLI.getOperationAction(ISD::FP_TO_SINT, SrcVT) !=   
-            TargetLowering::Legal)
-          // Unhandled opcode on this type.  Halt "fast" seleciton and bail.
-          return I;
         
         unsigned InputReg = ValueMap[I->getOperand(0)];
         if (!InputReg)
@@ -317,6 +313,34 @@
         // or attempt constant folding.
         return I;
 
+    case Instruction::SIToFP:
+      if (!isa<ConstantInt>(I->getOperand(0))) {
+        MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
+        MVT DstVT = MVT::getMVT(I->getType());
+        
+        if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
+            DstVT == MVT::Other || !DstVT.isSimple() ||
+            !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
+          // Unhandled type. Halt "fast" selection and bail.
+          return I;
+        
+        unsigned InputReg = ValueMap[I->getOperand(0)];
+        if (!InputReg)
+          // Unhandled operan.  Halt "fast" selection and bail.
+          return I;
+        
+        unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
+                                        DstVT.getSimpleVT(),
+                                        ISD::SINT_TO_FP,
+                                        InputReg);
+        if (!ResultReg)
+          return I;
+        
+        ValueMap[I] = ResultReg;
+        break;
+      } else
+        // TODO: Materialize constant and convert to FP.
+        return I;
     default:
       // Unhandled instruction. Halt "fast" selection and bail.
       return I;




From gohman at apple.com  Tue Aug 26 15:43:00 2008
From: gohman at apple.com (Dan Gohman)
Date: Tue, 26 Aug 2008 20:43:00 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r55382 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Message-ID: <200808262043.m7QKh0L2005959@zion.cs.uiuc.edu>

Author: djg
Date: Tue Aug 26 15:43:00 2008
New Revision: 55382

URL: http://llvm.org/viewvc/llvm-project?rev=55382&view=rev
Log:
Don't create a non-aggregate return value when returning an
aggregate when only a single member. That's no longer valid,
now that we're using first-class aggregates instead of 
multiple-return-values.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=55382&r1=55381&r2=55382&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Aug 26 15:43:00 2008
@@ -817,9 +817,10 @@
   if (TheDebugInfo) TheDebugInfo->EmitRegionEnd(Fn, Builder.GetInsertBlock());
   if (RetVals.empty())
     Builder.CreateRetVoid();
-  else if (RetVals.size() == 1)
+  else if (!Fn->getReturnType()->isAggregateType()) {
+    assert(RetVals.size() == 1 && "Non-aggregate return has multiple values!");
     Builder.CreateRet(RetVals[0]);
-  else
+  } else
     Builder.CreateAggregateRet(&RetVals[0], RetVals.size());
 
   // Emit pending exception handling code.




From gohman at apple.com  Tue Aug 26 15:52:40 2008
From: gohman at apple.com (Dan Gohman)
Date: Tue, 26 Aug 2008 20:52:40 -0000
Subject: [llvm-commits] [llvm] r55383 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808262052.m7QKqecH006267@zion.cs.uiuc.edu>

Author: djg
Date: Tue Aug 26 15:52:40 2008
New Revision: 55383

URL: http://llvm.org/viewvc/llvm-project?rev=55383&view=rev
Log:
Don't select binary instructions with illegal types.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55383&r1=55382&r2=55383&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Aug 26 15:52:40 2008
@@ -30,6 +30,12 @@
   if (VT == MVT::Other || !VT.isSimple())
     // Unhandled type. Halt "fast" selection and bail.
     return false;
+  // We only handle legal types. For example, on x86-32 the instruction
+  // selector contains all of the 64-bit instructions from x86-64,
+  // under the assumption that i64 won't be used if the target doesn't
+  // support it.
+  if (!TLI.isTypeLegal(VT))
+    return false;
 
   unsigned Op0 = ValueMap[I->getOperand(0)];
   if (Op0 == 0)




From gohman at apple.com  Tue Aug 26 15:57:08 2008
From: gohman at apple.com (Dan Gohman)
Date: Tue, 26 Aug 2008 20:57:08 -0000
Subject: [llvm-commits] [llvm] r55384 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808262057.m7QKv9Bd006403@zion.cs.uiuc.edu>

Author: djg
Date: Tue Aug 26 15:57:08 2008
New Revision: 55384

URL: http://llvm.org/viewvc/llvm-project?rev=55384&view=rev
Log:
Make FastISel use the correct argument type when casting GEP indices.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55384&r1=55383&r2=55384&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Aug 26 15:57:08 2008
@@ -124,18 +124,19 @@
       // it.
       MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
       if (IdxVT.bitsLT(VT))
-        IdxN = FastEmit_r(VT, VT, ISD::SIGN_EXTEND, IdxN);
+        IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN);
       else if (IdxVT.bitsGT(VT))
-        IdxN = FastEmit_r(VT, VT, ISD::TRUNCATE, IdxN);
+        IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN);
       if (IdxN == 0)
         // Unhandled operand. Halt "fast" selection and bail.
         return false;
 
-      if (ElementSize != 1)
+      if (ElementSize != 1) {
         IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
-      if (IdxN == 0)
-        // Unhandled operand. Halt "fast" selection and bail.
-        return false;
+        if (IdxN == 0)
+          // Unhandled operand. Halt "fast" selection and bail.
+          return false;
+      }
       N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
       if (N == 0)
         // Unhandled operand. Halt "fast" selection and bail.




From gohman at apple.com  Tue Aug 26 16:21:20 2008
From: gohman at apple.com (Dan Gohman)
Date: Tue, 26 Aug 2008 21:21:20 -0000
Subject: [llvm-commits] [llvm] r55385 - in /llvm/trunk/utils/TableGen:
 FastISelEmitter.cpp FastISelEmitter.h
Message-ID: <200808262121.m7QLLKA0007139@zion.cs.uiuc.edu>

Author: djg
Date: Tue Aug 26 16:21:20 2008
New Revision: 55385

URL: http://llvm.org/viewvc/llvm-project?rev=55385&view=rev
Log:
Refactor a bunch of FastISelEmitter code into a helper class, and
put each major step in a separate function. This makes the high
level sequence of events easier to follow.

Modified:
    llvm/trunk/utils/TableGen/FastISelEmitter.cpp
    llvm/trunk/utils/TableGen/FastISelEmitter.h

Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=55385&r1=55384&r2=55385&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Tue Aug 26 16:21:20 2008
@@ -161,6 +161,25 @@
   const CodeGenRegisterClass *RC;
 };
 
+class FastISelMap {
+  typedef std::map<std::string, InstructionMemo> PredMap;
+  typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
+  typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
+  typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
+  typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> OperandsOpcodeTypeRetPredMap;
+
+  OperandsOpcodeTypeRetPredMap SimplePatterns;
+
+  std::string InstNS;
+
+public:
+  explicit FastISelMap(std::string InstNS);
+
+  void CollectPatterns(CodeGenDAGPatterns &CGP);
+  void PrintClass(std::ostream &OS);
+  void PrintFunctionDefinitions(std::ostream &OS);
+};
+
 }
 
 static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
@@ -174,23 +193,16 @@
   return OpName;
 }
 
-void FastISelEmitter::run(std::ostream &OS) {
-  EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
-                       Target.getName() + " target", OS);
+FastISelMap::FastISelMap(std::string instns)
+  : InstNS(instns) {
+}
 
-  OS << "#include \"llvm/CodeGen/FastISel.h\"\n";
-  OS << "\n";
-  OS << "namespace llvm {\n";
-  OS << "\n";
-  OS << "namespace " << InstNS.substr(0, InstNS.size() - 2) << " {\n";
-  OS << "\n";
-  
-  typedef std::map<std::string, InstructionMemo> PredMap;
-  typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
-  typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
-  typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
-  typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> OperandsOpcodeTypeRetPredMap;
-  OperandsOpcodeTypeRetPredMap SimplePatterns;
+void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
+  const CodeGenTarget &Target = CGP.getTargetInfo();
+
+  // Determine the target's namespace name.
+  InstNS = Target.getInstNamespace() + "::";
+  assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
 
   // Scan through all the patterns and record the simple ones.
   for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
@@ -255,7 +267,9 @@
            "Duplicate pattern!");
     SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
   }
+}
 
+void FastISelMap::PrintClass(std::ostream &OS) {
   // Declare the target FastISel class.
   OS << "class FastISel : public llvm::FastISel {\n";
   for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
@@ -328,13 +342,9 @@
      << "Subtarget>()) {}\n";
   OS << "};\n";
   OS << "\n";
+}
 
-  // Define the target FastISel creation function.
-  OS << "llvm::FastISel *createFastISel(MachineFunction &mf) {\n";
-  OS << "  return new FastISel(mf);\n";
-  OS << "}\n";
-  OS << "\n";
-
+void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
   // Now emit code for all the patterns that we collected.
   for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
        OE = SimplePatterns.end(); OI != OE; ++OI) {
@@ -536,6 +546,35 @@
     OS << "}\n";
     OS << "\n";
   }
+}
+
+void FastISelEmitter::run(std::ostream &OS) {
+  const CodeGenTarget &Target = CGP.getTargetInfo();
+
+  // Determine the target's namespace name.
+  std::string InstNS = Target.getInstNamespace() + "::";
+  assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
+
+  EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
+                       Target.getName() + " target", OS);
+
+  OS << "#include \"llvm/CodeGen/FastISel.h\"\n";
+  OS << "\n";
+  OS << "namespace llvm {\n";
+  OS << "\n";
+  OS << "namespace " << InstNS.substr(0, InstNS.size() - 2) << " {\n";
+  OS << "\n";
+  
+  FastISelMap F(InstNS);
+  F.CollectPatterns(CGP);
+  F.PrintClass(OS);
+  F.PrintFunctionDefinitions(OS);
+
+  // Define the target FastISel creation function.
+  OS << "llvm::FastISel *createFastISel(MachineFunction &mf) {\n";
+  OS << "  return new FastISel(mf);\n";
+  OS << "}\n";
+  OS << "\n";
 
   OS << "} // namespace X86\n";
   OS << "\n";
@@ -544,9 +583,6 @@
 
 FastISelEmitter::FastISelEmitter(RecordKeeper &R)
   : Records(R),
-    CGP(R),
-    Target(CGP.getTargetInfo()),
-    InstNS(Target.getInstNamespace() + "::") {
-
-  assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
+    CGP(R) {
 }
+

Modified: llvm/trunk/utils/TableGen/FastISelEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.h?rev=55385&r1=55384&r2=55385&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/FastISelEmitter.h (original)
+++ llvm/trunk/utils/TableGen/FastISelEmitter.h Tue Aug 26 16:21:20 2008
@@ -27,8 +27,6 @@
 class FastISelEmitter : public TableGenBackend {
   RecordKeeper &Records;
   CodeGenDAGPatterns CGP;
-  const CodeGenTarget &Target;
-  const std::string InstNS;
 public:
   explicit FastISelEmitter(RecordKeeper &R);
 




From gohman at apple.com  Tue Aug 26 16:28:54 2008
From: gohman at apple.com (Dan Gohman)
Date: Tue, 26 Aug 2008 21:28:54 -0000
Subject: [llvm-commits] [llvm] r55387 - in /llvm/trunk:
 include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808262128.m7QLSsRJ007408@zion.cs.uiuc.edu>

Author: djg
Date: Tue Aug 26 16:28:54 2008
New Revision: 55387

URL: http://llvm.org/viewvc/llvm-project?rev=55387&view=rev
Log:
Refactor the bitcast code into its own function.

Modified:
    llvm/trunk/include/llvm/CodeGen/FastISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=55387&r1=55386&r2=55387&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Tue Aug 26 16:28:54 2008
@@ -167,6 +167,9 @@
 
   bool SelectGetElementPtr(Instruction *I,
                            DenseMap<const Value*, unsigned> &ValueMap);
+
+  bool SelectBitCast(Instruction *I,
+                     DenseMap<const Value*, unsigned> &ValueMap);
 };
 
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55387&r1=55386&r2=55387&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Aug 26 16:28:54 2008
@@ -149,6 +149,72 @@
   return true;
 }
 
+bool FastISel::SelectBitCast(Instruction *I,
+                             DenseMap<const Value*, unsigned> &ValueMap) {
+  // BitCast consists of either an immediate to register move
+  // or a register to register move.
+  if (ConstantInt* CI = dyn_cast<ConstantInt>(I->getOperand(0))) {
+    if (I->getType()->isInteger()) {
+      MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/false);
+      unsigned result = FastEmit_i(VT.getSimpleVT(), VT.getSimpleVT(),
+                                   ISD::Constant,
+                                   CI->getZExtValue());
+      if (!result)
+        return false;
+      
+      ValueMap[I] = result;
+      return true;
+    }
+
+    // TODO: Support vector and fp constants.
+    return false;
+  }
+
+  if (!isa<Constant>(I->getOperand(0))) {
+    // Bitcasts of non-constant values become reg-reg copies.
+    MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
+    MVT DstVT = MVT::getMVT(I->getType());
+    
+    if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
+        DstVT == MVT::Other || !DstVT.isSimple() ||
+        !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
+      // Unhandled type. Halt "fast" selection and bail.
+      return false;
+    
+    unsigned Op0 = ValueMap[I->getOperand(0)];
+    if (Op0 == 0)
+      // Unhandled operand. Halt "fast" selection and bail.
+      return false;
+    
+    // First, try to perform the bitcast by inserting a reg-reg copy.
+    unsigned ResultReg = 0;
+    if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
+      TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
+      TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
+      ResultReg = createResultReg(DstClass);
+      
+      bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+                                           Op0, DstClass, SrcClass);
+      if (!InsertedCopy)
+        ResultReg = 0;
+    }
+    
+    // If the reg-reg copy failed, select a BIT_CONVERT opcode.
+    if (!ResultReg)
+      ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
+                             ISD::BIT_CONVERT, Op0);
+    
+    if (!ResultReg)
+      return false;
+    
+    ValueMap[I] = ResultReg;
+    return true;
+  }
+
+  // TODO: Casting a non-integral constant?
+  return false;
+}
+
 BasicBlock::iterator
 FastISel::SelectInstructions(BasicBlock::iterator Begin,
                              BasicBlock::iterator End,
@@ -231,64 +297,8 @@
       break;
       
     case Instruction::BitCast:
-      // BitCast consists of either an immediate to register move
-      // or a register to register move.
-      if (ConstantInt* CI = dyn_cast<ConstantInt>(I->getOperand(0))) {
-        if (I->getType()->isInteger()) {
-          MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/false);
-          unsigned result = FastEmit_i(VT.getSimpleVT(), VT.getSimpleVT(),
-                                       ISD::Constant,
-                                       CI->getZExtValue());
-          if (!result)
-            return I;
-          
-          ValueMap[I] = result;
-          break;
-        } else
-          // TODO: Support vector and fp constants.
-          return I;
-      } else if (!isa<Constant>(I->getOperand(0))) {
-        // Bitcasts of non-constant values become reg-reg copies.
-        MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
-        MVT DstVT = MVT::getMVT(I->getType());
-        
-        if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
-            DstVT == MVT::Other || !DstVT.isSimple() ||
-            !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
-          // Unhandled type. Halt "fast" selection and bail.
-          return I;
-        
-        unsigned Op0 = ValueMap[I->getOperand(0)];
-        if (Op0 == 0)
-          // Unhandled operand. Halt "fast" selection and bail.
-          return false;
-        
-        // First, try to perform the bitcast by inserting a reg-reg copy.
-        unsigned ResultReg = 0;
-        if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
-          TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
-          TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
-          ResultReg = createResultReg(DstClass);
-          
-          bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
-                                               Op0, DstClass, SrcClass);
-          if (!InsertedCopy)
-            ResultReg = 0;
-        }
-        
-        // If the reg-reg copy failed, select a BIT_CONVERT opcode.
-        if (!ResultReg)
-          ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
-                                 ISD::BIT_CONVERT, Op0);
-        
-        if (!ResultReg)
-          return I;
-        
-        ValueMap[I] = ResultReg;
-        break;
-      } else
-        // TODO: Casting a non-integral constant?
-        return I;
+      if (!SelectBitCast(I, ValueMap)) return I;
+      break;
 
     case Instruction::FPToSI:
       if (!isa<ConstantFP>(I->getOperand(0))) {
@@ -348,6 +358,7 @@
       } else
         // TODO: Materialize constant and convert to FP.
         return I;
+
     default:
       // Unhandled instruction. Halt "fast" selection and bail.
       return I;




From evan.cheng at apple.com  Tue Aug 26 16:29:29 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 26 Aug 2008 14:29:29 -0700
Subject: [llvm-commits] [llvm] r55318 - in /llvm/trunk/lib/Target/X86:
	X86InstrFormats.td X86InstrMMX.td
In-Reply-To: <16e5fdf90808261303n34964729qa1934f14f1f26cba@mail.gmail.com>
References: <200808251832.m7PIWdiQ005650@zion.cs.uiuc.edu>
	<80B61887-0703-49E2-82AC-9841CDEFF41F@apple.com>
	<16e5fdf90808261303n34964729qa1934f14f1f26cba@mail.gmail.com>
Message-ID: <82DE1E04-9B9A-4BE3-AD0F-8A19D10A875E@apple.com>


On Aug 26, 2008, at 1:03 PM, Bill Wendling wrote:

> Pretty sure. When I applied it, it ICEd saying "illegal instruction".
> Removing it made it go away.
>
> My guess is that it used this instruction because it was marked as
> "HasSSE2", but it shouldn't have because it does MMX stuff.

Hmm... That's strange. The pattern is matching something that produces  
v1i16. The predicate doesn't change what gets matched. Is it possible  
to reproduce it and figure out what is miscompiled? I suspect the bug  
is elsewhere but it's being exposed by the change.

Evan

>
>
> -bw
>
> On Mon, Aug 25, 2008 at 11:30 PM, Evan Cheng <evan.cheng at apple.com>  
> wrote:
>> Are you sure? That seems highly unlikely.
>>
>> Evan
>>
>> On Aug 25, 2008, at 11:32 AM, Bill Wendling wrote:
>>
>>> Author: void
>>> Date: Mon Aug 25 13:32:39 2008
>>> New Revision: 55318
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=55318&view=rev
>>> Log:
>>> Nevermind. This broke the bootstrap (?!).
>>>
>>> Modified:
>>>   llvm/trunk/lib/Target/X86/X86InstrFormats.td
>>>   llvm/trunk/lib/Target/X86/X86InstrMMX.td
>>>
>>> Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=55318&r1=55317&r2=55318&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> = 
>>> = 
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
>>> +++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Mon Aug 25 13:32:39
>>> 2008
>>> @@ -157,20 +157,16 @@
>>>
>>> // SSE2 Instruction Templates:
>>> //
>>> -//   SDI    - SSE2 instructions with XD prefix.
>>> -//   SDIi8  - SSE2 instructions with ImmT == Imm8 and XD prefix.
>>> -//   SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
>>> -//   PDI    - SSE2 instructions with TB and OpSize prefixes.
>>> -//   PDIi8  - SSE2 instructions with ImmT == Imm8 and TB and OpSize
>>> prefixes.
>>> +//   SDI   - SSE2 instructions with XD prefix.
>>> +//   SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
>>> +//   PDI   - SSE2 instructions with TB and OpSize prefixes.
>>> +//   PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize
>>> prefixes.
>>>
>>> class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
>>> list<dag> pattern>
>>>      : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
>>> class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
>>>            list<dag> pattern>
>>>      : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
>>> -class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
>>> -             list<dag> pattern>
>>> -      : Ii8<o, F, outs, ins, asm, pattern>, XS,  
>>> Requires<[HasSSE2]>;
>>> class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
>>> list<dag> pattern>
>>>      : I<o, F, outs, ins, asm, pattern>, TB, OpSize,
>>> Requires<[HasSSE2]>;
>>> class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
>>>
>>> Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=55318&r1=55317&r2=55318&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> = 
>>> = 
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
>>> +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Mon Aug 25 13:32:39  
>>> 2008
>>> @@ -173,15 +173,15 @@
>>>                        "movq\t{$src, $dst|$dst, $src}",
>>>                        [(store (v1i64 VR64:$src), addr:$dst)]>;
>>>
>>> -def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMDestMem, (outs VR64:$dst), (ins
>>> VR128:$src),
>>> +def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (outs VR64:$dst), (ins
>>> VR128:$src),
>>>                          "movdq2q\t{$src, $dst|$dst, $src}",
>>>                          [(set VR64:$dst,
>>>                            (v1i64 (bitconvert
>>>                            (i64 (vector_extract (v2i64 VR128:$src),
>>>                                  (iPTR 0))))))]>;
>>>
>>> -def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMDestMem, (outs VR128:$dst),
>>> (ins VR64:$src),
>>> -                           "movq2dq\t{$src, $dst|$dst, $src}",
>>> +def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (outs VR128:$dst), (ins
>>> VR64:$src),
>>> +                          "movq2dq\t{$src, $dst|$dst, $src}",
>>>          [(set VR128:$dst,
>>>                (v2i64 (vector_shuffle immAllZerosV,
>>>                        (v2i64 (scalar_to_vector (i64 (bitconvert
>>> VR64:$src)))),
>>>
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From gohman at apple.com  Tue Aug 26 16:42:18 2008
From: gohman at apple.com (Dan Gohman)
Date: Tue, 26 Aug 2008 21:42:18 -0000
Subject: [llvm-commits] [llvm] r55389 - in
 /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp SelectionDAG.cpp
Message-ID: <200808262142.m7QLgJBb007889@zion.cs.uiuc.edu>

Author: djg
Date: Tue Aug 26 16:42:18 2008
New Revision: 55389

URL: http://llvm.org/viewvc/llvm-project?rev=55389&view=rev
Log:
Optimize SelectionDAG's topological sort to use one pass instead
of two, and to not need a scratch std::vector. Also, use the
SelectionDAG's topological sort in LegalizeDAG instead of having
a separate implementation.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=55389&r1=55388&r2=55389&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Aug 26 16:42:18 2008
@@ -270,45 +270,6 @@
          "Too many value types for ValueTypeActions to hold!");
 }
 
-/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
-/// contains all of a nodes operands before it contains the node.
-static void ComputeTopDownOrdering(SelectionDAG &DAG,
-                                   SmallVector<SDNode*, 64> &Order) {
-
-  DenseMap<SDNode*, unsigned> Visited;
-  std::vector<SDNode*> Worklist;
-  Worklist.reserve(128);
-  
-  // Compute ordering from all of the leaves in the graphs, those (like the
-  // entry node) that have no operands.
-  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
-       E = DAG.allnodes_end(); I != E; ++I) {
-    if (I->getNumOperands() == 0) {
-      Visited[I] = 0 - 1U;
-      Worklist.push_back(I);
-    }
-  }
-  
-  while (!Worklist.empty()) {
-    SDNode *N = Worklist.back();
-    Worklist.pop_back();
-    
-    if (++Visited[N] != N->getNumOperands())
-      continue;  // Haven't visited all operands yet
-    
-    Order.push_back(N);
-
-    // Now that we have N in, add anything that uses it if all of their operands
-    // are now done.
-    Worklist.insert(Worklist.end(), N->use_begin(), N->use_end());
-  }
-
-  assert(Order.size() == Visited.size() &&
-         Order.size() == DAG.allnodes_size() &&
-         "Error: DAG is cyclic!");
-}
-
-
 void SelectionDAGLegalize::LegalizeDAG() {
   LastCALLSEQ_END = DAG.getEntryNode();
   IsLegalizingCall = false;
@@ -319,11 +280,11 @@
   // practice however, this causes us to run out of stack space on large basic
   // blocks.  To avoid this problem, compute an ordering of the nodes where each
   // node is only legalized after all of its operands are legalized.
-  SmallVector<SDNode*, 64> Order;
-  ComputeTopDownOrdering(DAG, Order);
-  
-  for (unsigned i = 0, e = Order.size(); i != e; ++i)
-    HandleOp(SDValue(Order[i], 0));
+  std::vector<SDNode *> TopOrder;
+  unsigned N = DAG.AssignTopologicalOrder(TopOrder);
+  for (unsigned i = N; i != 0; --i)
+    HandleOp(SDValue(TopOrder[i-1], 0));
+  TopOrder.clear();
 
   // Finally, it's possible the root changed.  Get the new root.
   SDValue OldRoot = DAG.getRoot();

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=55389&r1=55388&r2=55389&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Aug 26 16:42:18 2008
@@ -4427,40 +4427,35 @@
 /// of the SDNodes* in assigned order by reference.
 unsigned SelectionDAG::AssignTopologicalOrder(std::vector<SDNode*> &TopOrder) {
   unsigned DAGSize = AllNodes.size();
-  std::vector<unsigned> InDegree(DAGSize);
   std::vector<SDNode*> Sources;
 
-  // Use a two pass approach to avoid using a std::map which is slow.
-  unsigned Id = 0;
   for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I){
     SDNode *N = I;
-    N->setNodeId(Id++);
     unsigned Degree = N->use_size();
-    InDegree[N->getNodeId()] = Degree;
+    // Temporarily use the Node Id as scratch space for the degree count.
+    N->setNodeId(Degree);
     if (Degree == 0)
       Sources.push_back(N);
   }
 
   TopOrder.clear();
   TopOrder.reserve(DAGSize);
+  int Id = 0;
   while (!Sources.empty()) {
     SDNode *N = Sources.back();
     Sources.pop_back();
     TopOrder.push_back(N);
+    N->setNodeId(Id++);
     for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) {
       SDNode *P = I->getVal();
-      unsigned Degree = --InDegree[P->getNodeId()];
+      unsigned Degree = P->getNodeId();
+      --Degree;
+      P->setNodeId(Degree);
       if (Degree == 0)
         Sources.push_back(P);
     }
   }
 
-  // Second pass, assign the actual topological order as node ids.
-  Id = 0;
-  for (std::vector<SDNode*>::iterator TI = TopOrder.begin(),TE = TopOrder.end();
-       TI != TE; ++TI)
-    (*TI)->setNodeId(Id++);
-
   return Id;
 }
 




From resistor at mac.com  Tue Aug 26 17:07:42 2008
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Aug 2008 22:07:42 -0000
Subject: [llvm-commits] [llvm] r55391 -
	/llvm/trunk/lib/Transforms/Scalar/GVN.cpp
Message-ID: <200808262207.m7QM7gBK008704@zion.cs.uiuc.edu>

Author: resistor
Date: Tue Aug 26 17:07:42 2008
New Revision: 55391

URL: http://llvm.org/viewvc/llvm-project?rev=55391&view=rev
Log:
Put a heuristic in place to prevent GVN from falling into bad cases with massively complicated CFGs.
This speeds up a particular testcase from 12+ hours to 5 seconds with little perceptible loss of quality.

Modified:
    llvm/trunk/lib/Transforms/Scalar/GVN.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=55391&r1=55390&r2=55391&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Tue Aug 26 17:07:42 2008
@@ -862,6 +862,12 @@
   DenseMap<BasicBlock*, Value*> deps;
   MD.getNonLocalDependency(L, deps);
   
+  // If we had to process more than one hundred blocks to find the
+  // dependencies, this load isn't worth worrying about.  Optimizing
+  // it will be too expensive.
+  if (deps.size() > 100)
+    return false;
+  
   DenseMap<BasicBlock*, Value*> repl;
   
   // Filter out useless results (non-locals, etc)




From viridia at gmail.com  Tue Aug 26 17:23:34 2008
From: viridia at gmail.com (Talin)
Date: Tue, 26 Aug 2008 15:23:34 -0700
Subject: [llvm-commits] DebugInfoBuilder - revised
Message-ID: <d1b71f830808261523t198e87ffw18a04ed616ebae08@mail.gmail.com>

Here's the latest version of the patch.

(Sorry for not replying to the previous message, it seems to have gotten
deleted from my mail prog.)
-- 
-- Talin
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From resistor at mac.com  Tue Aug 26 17:34:28 2008
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Aug 2008 22:34:28 -0000
Subject: [llvm-commits] [llvm] r55393 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808262234.m7QMYS3J009642@zion.cs.uiuc.edu>

Author: resistor
Date: Tue Aug 26 17:34:28 2008
New Revision: 55393

URL: http://llvm.org/viewvc/llvm-project?rev=55393&view=rev
Log:
Add support for fptosi of constants in fast isel.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55393&r1=55392&r2=55393&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Aug 26 17:34:28 2008
@@ -355,9 +355,35 @@
         
         ValueMap[I] = ResultReg;
         break;
-      } else
-        // TODO: Materialize constant and convert to FP.
-        return I;
+      } else {
+        // Materialize constant and convert to FP.
+        // TODO: Attempt constant folding?
+        ConstantInt* CI = cast<ConstantInt>(I->getOperand(0));
+        MVT SrcVT = MVT::getMVT(CI->getType());
+        MVT DstVT = MVT::getMVT(I->getType());
+        
+        if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
+            DstVT == MVT::Other || !DstVT.isSimple() ||
+            !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
+          // Unhandled type. Halt "fast" selection and bail.
+          return I;
+        
+        unsigned ResultReg1 = FastEmit_i(SrcVT.getSimpleVT(),
+                                         SrcVT.getSimpleVT(),
+                                         ISD::Constant, CI->getZExtValue());
+        if (!ResultReg1)
+          return I;
+        
+        unsigned ResultReg2 = FastEmit_r(SrcVT.getSimpleVT(),
+                                         DstVT.getSimpleVT(),
+                                         ISD::SINT_TO_FP,
+                                         ResultReg1);
+        if (!ResultReg2)
+          return I;
+        
+        ValueMap[I] = ResultReg2;
+        break;
+      }
 
     default:
       // Unhandled instruction. Halt "fast" selection and bail.




From ggreif at gmail.com  Tue Aug 26 17:36:50 2008
From: ggreif at gmail.com (Gabor Greif)
Date: Tue, 26 Aug 2008 22:36:50 -0000
Subject: [llvm-commits] [llvm] r55394 - in /llvm/trunk:
 include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/
 lib/Target/CellSPU/ lib/Target/Mips/ lib/Target/PIC16/ lib/Target/PowerPC/
 lib/Target/X86/ utils/TableGen/
Message-ID: <200808262236.m7QMapCf009736@zion.cs.uiuc.edu>

Author: ggreif
Date: Tue Aug 26 17:36:50 2008
New Revision: 55394

URL: http://llvm.org/viewvc/llvm-project?rev=55394&view=rev
Log:
disallow direct access to SDValue::ResNo, provide a getter instead

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/utils/TableGen/DAGISelEmitter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=55394&r1=55393&r2=55394&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Tue Aug 26 17:36:50 2008
@@ -811,11 +811,15 @@
 class SDValue {
 public:
   SDNode *Val;        // The node defining the value we are using.
+private:
   unsigned ResNo;     // Which return value of the node we are using.
-
+public:
   SDValue() : Val(0), ResNo(0) {}
   SDValue(SDNode *val, unsigned resno) : Val(val), ResNo(resno) {}
 
+  /// get the index which selects a specific result in the SDNode
+  unsigned getResNo() const { return ResNo; }
+
   bool operator==(const SDValue &O) const {
     return Val == O.Val && ResNo == O.ResNo;
   }
@@ -882,7 +886,7 @@
   }
   static unsigned getHashValue(const SDValue &Val) {
     return ((unsigned)((uintptr_t)Val.Val >> 4) ^
-            (unsigned)((uintptr_t)Val.Val >> 9)) + Val.ResNo;
+            (unsigned)((uintptr_t)Val.Val >> 9)) + Val.getResNo();
   }
   static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
     return LHS == RHS;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=55394&r1=55393&r2=55394&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Aug 26 17:36:50 2008
@@ -2730,7 +2730,7 @@
       SDNode *User = *UI;
       for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
         SDValue UseOp = User->getOperand(i);
-        if (UseOp.Val == N && UseOp.ResNo == 0) {
+        if (UseOp.Val == N && UseOp.getResNo() == 0) {
           BothLiveOut = true;
           break;
         }
@@ -3366,7 +3366,7 @@
   SDValue Elt = N->getOperand(i);
   if (Elt.getOpcode() != ISD::MERGE_VALUES)
     return Elt.Val;
-  return Elt.getOperand(Elt.ResNo).Val;
+  return Elt.getOperand(Elt.getResNo()).Val;
 }
 
 /// CombineConsecutiveLoads - build_pair (load, load) -> load

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=55394&r1=55393&r2=55394&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Aug 26 17:36:50 2008
@@ -821,7 +821,7 @@
 
       for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
         AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
-      return Result.getValue(Op.ResNo);
+      return Result.getValue(Op.getResNo());
     }
     // Otherwise this is an unhandled builtin node.  splat.
 #ifndef NDEBUG
@@ -901,7 +901,7 @@
     Tmp2 = LegalizeOp(Result.getValue(1));
     AddLegalizedOperand(Op.getValue(0), Tmp1);
     AddLegalizedOperand(Op.getValue(1), Tmp2);
-    return Op.ResNo ? Tmp2 : Tmp1;
+    return Op.getResNo() ? Tmp2 : Tmp1;
   case ISD::EHSELECTION: {
     Tmp1 = LegalizeOp(Node->getOperand(0));
     Tmp2 = LegalizeOp(Node->getOperand(1));
@@ -935,7 +935,7 @@
     Tmp2 = LegalizeOp(Result.getValue(1));
     AddLegalizedOperand(Op.getValue(0), Tmp1);
     AddLegalizedOperand(Op.getValue(1), Tmp2);
-    return Op.ResNo ? Tmp2 : Tmp1;
+    return Op.getResNo() ? Tmp2 : Tmp1;
   case ISD::EH_RETURN: {
     MVT VT = Node->getValueType(0);
     // The only "good" option for this node is to custom lower it.
@@ -959,7 +959,7 @@
     break;
   case ISD::MERGE_VALUES:
     // Legalize eliminates MERGE_VALUES nodes.
-    Result = Node->getOperand(Op.ResNo);
+    Result = Node->getOperand(Op.getResNo());
     break;
   case ISD::CopyFromReg:
     Tmp1 = LegalizeOp(Node->getOperand(0));
@@ -980,7 +980,7 @@
     // legalized both of them.
     AddLegalizedOperand(Op.getValue(0), Result);
     AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
-    return Result.getValue(Op.ResNo);
+    return Result.getValue(Op.getResNo());
   case ISD::UNDEF: {
     MVT VT = Op.getValueType();
     switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
@@ -1025,7 +1025,7 @@
     // legalized both of them.
     AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
     AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
-    return Result.getValue(Op.ResNo);
+    return Result.getValue(Op.getResNo());
   }    
 
   case ISD::DBG_STOPPOINT:
@@ -1199,7 +1199,7 @@
     }
     AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
     AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
-    return Result.getValue(Op.ResNo);
+    return Result.getValue(Op.getResNo());
   }
   case ISD::ATOMIC_LOAD_ADD:
   case ISD::ATOMIC_LOAD_SUB:
@@ -1232,7 +1232,7 @@
     }
     AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
     AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
-    return Result.getValue(Op.ResNo);
+    return Result.getValue(Op.getResNo());
   }
   case ISD::Constant: {
     ConstantSDNode *CN = cast<ConstantSDNode>(Node);
@@ -1331,7 +1331,7 @@
       if (Tmp3.Val->getValueType(i) == MVT::Flag)
         continue;
       Tmp1 = LegalizeOp(Tmp3.getValue(i));
-      if (Op.ResNo == i)
+      if (Op.getResNo() == i)
         Tmp2 = Tmp1;
       AddLegalizedOperand(SDValue(Node, i), Tmp1);
     }
@@ -1625,7 +1625,7 @@
     AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
     if (Node->getNumValues() == 2)
       AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
-    return Result.getValue(Op.ResNo);
+    return Result.getValue(Op.getResNo());
   case ISD::DYNAMIC_STACKALLOC: {
     MVT VT = Node->getValueType(0);
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
@@ -1684,7 +1684,7 @@
     // legalized both of them.
     AddLegalizedOperand(SDValue(Node, 0), Tmp1);
     AddLegalizedOperand(SDValue(Node, 1), Tmp2);
-    return Op.ResNo ? Tmp2 : Tmp1;
+    return Op.getResNo() ? Tmp2 : Tmp1;
   }
   case ISD::INLINEASM: {
     SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
@@ -1720,7 +1720,7 @@
     // INLINE asm returns a chain and flag, make sure to add both to the map.
     AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
     AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
-    return Result.getValue(Op.ResNo);
+    return Result.getValue(Op.getResNo());
   }
   case ISD::BR:
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
@@ -1935,7 +1935,7 @@
       // legalized both of them.
       AddLegalizedOperand(SDValue(Node, 0), Tmp3);
       AddLegalizedOperand(SDValue(Node, 1), Tmp4);
-      return Op.ResNo ? Tmp4 : Tmp3;
+      return Op.getResNo() ? Tmp4 : Tmp3;
     } else {
       MVT SrcVT = LD->getMemoryVT();
       unsigned SrcWidth = SrcVT.getSizeInBits();
@@ -2124,7 +2124,7 @@
       // both of them.
       AddLegalizedOperand(SDValue(Node, 0), Tmp1);
       AddLegalizedOperand(SDValue(Node, 1), Tmp2);
-      return Op.ResNo ? Tmp2 : Tmp1;
+      return Op.getResNo() ? Tmp2 : Tmp1;
     }
   }
   case ISD::EXTRACT_ELEMENT: {
@@ -2215,7 +2215,7 @@
           Result = LegalizeOp(Result);
         } else {
           SDNode *InVal = Tmp2.Val;
-          int InIx = Tmp2.ResNo;
+          int InIx = Tmp2.getResNo();
           unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
           MVT EVT = InVal->getValueType(InIx).getVectorElementType();
           
@@ -2411,7 +2411,7 @@
         // in the high half of the vector.
         if (ST->getValue().getValueType().isVector()) {
           SDNode *InVal = ST->getValue().Val;
-          int InIx = ST->getValue().ResNo;
+          int InIx = ST->getValue().getResNo();
           MVT InVT = InVal->getValueType(InIx);
           unsigned NumElems = InVT.getVectorNumElements();
           MVT EVT = InVT.getVectorElementType();
@@ -2619,7 +2619,7 @@
     // legalized both of them.
     AddLegalizedOperand(SDValue(Node, 0), Tmp1);
     AddLegalizedOperand(SDValue(Node, 1), Tmp2);
-    return Op.ResNo ? Tmp2 : Tmp1;
+    return Op.getResNo() ? Tmp2 : Tmp1;
 
   case ISD::STACKRESTORE:
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
@@ -2875,7 +2875,7 @@
         for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
           Tmp2 = LegalizeOp(Tmp1.getValue(i));
           AddLegalizedOperand(SDValue(Node, i), Tmp2);
-          if (i == Op.ResNo)
+          if (i == Op.getResNo())
             RetVal = Tmp2;
         }
         assert(RetVal.Val && "Illegal result number");
@@ -2888,7 +2888,7 @@
     // legalized all of them.
     for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
       AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
-    return Result.getValue(Op.ResNo);
+    return Result.getValue(Op.getResNo());
   }
 
     // Binary operators
@@ -3278,7 +3278,7 @@
     // legalized both of them.
     AddLegalizedOperand(SDValue(Node, 0), Result);
     AddLegalizedOperand(SDValue(Node, 1), Tmp1);
-    return Op.ResNo ? Tmp1 : Result;
+    return Op.getResNo() ? Tmp1 : Result;
   }
     
   case ISD::VACOPY: 
@@ -3574,7 +3574,7 @@
       // The input has to be a vector type, we have to either scalarize it, pack
       // it, or convert it based on whether the input vector type is legal.
       SDNode *InVal = Node->getOperand(0).Val;
-      int InIx = Node->getOperand(0).ResNo;
+      int InIx = Node->getOperand(0).getResNo();
       unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
       MVT EVT = InVal->getValueType(InIx).getVectorElementType();
     
@@ -3876,7 +3876,7 @@
     Result = LegalizeOp(Result);
     AddLegalizedOperand(SDValue(Node, 0), Result);
     AddLegalizedOperand(SDValue(Node, 1), Tmp1);
-    return Op.ResNo ? Tmp1 : Result;
+    return Op.getResNo() ? Tmp1 : Result;
   }
   case ISD::FLT_ROUNDS_: {
     MVT VT = Node->getValueType(0);
@@ -5808,7 +5808,7 @@
       break;
     }
     // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
-    assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
+    assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
            Op.getValue(1).getValueType() == MVT::Other &&
            "unhandled MERGE_VALUES");
     ExpandOp(Op.getOperand(0), Lo, Hi);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=55394&r1=55393&r2=55394&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Tue Aug 26 17:36:50 2008
@@ -62,7 +62,7 @@
   if (TargetRegisterInfo::isVirtualRegister(Reg))
     return;
 
-  unsigned ResNo = User->getOperand(2).ResNo;
+  unsigned ResNo = User->getOperand(2).getResNo();
   if (Def->isMachineOpcode()) {
     const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
     if (ResNo >= II.getNumDefs() &&
@@ -430,7 +430,7 @@
     bool Match = true;
     if (User->getOpcode() == ISD::CopyToReg && 
         User->getOperand(2).Val == Node &&
-        User->getOperand(2).ResNo == ResNo) {
+        User->getOperand(2).getResNo() == ResNo) {
       unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
       if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
         VRBase = DestReg;
@@ -440,9 +440,9 @@
     } else {
       for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
         SDValue Op = User->getOperand(i);
-        if (Op.Val != Node || Op.ResNo != ResNo)
+        if (Op.Val != Node || Op.getResNo() != ResNo)
           continue;
-        MVT VT = Node->getValueType(Op.ResNo);
+        MVT VT = Node->getValueType(Op.getResNo());
         if (VT != MVT::Other && VT != MVT::Flag)
           Match = false;
       }
@@ -490,7 +490,7 @@
   SDNode *User = *Node->use_begin();
   if (User->getOpcode() == ISD::CopyToReg && 
       User->getOperand(2).Val == Node &&
-      User->getOperand(2).ResNo == ResNo) {
+      User->getOperand(2).getResNo() == ResNo) {
     unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
     if (TargetRegisterInfo::isVirtualRegister(Reg))
       return Reg;
@@ -514,7 +514,7 @@
       SDNode *User = *UI;
       if (User->getOpcode() == ISD::CopyToReg && 
           User->getOperand(2).Val == Node &&
-          User->getOperand(2).ResNo == i) {
+          User->getOperand(2).getResNo() == i) {
         unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
         if (TargetRegisterInfo::isVirtualRegister(Reg)) {
           VRBase = Reg;
@@ -547,7 +547,7 @@
   if (Op.isMachineOpcode() &&
       Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
     // Add an IMPLICIT_DEF instruction before every use.
-    unsigned VReg = getDstOfOnlyCopyToRegUse(Op.Val, Op.ResNo);
+    unsigned VReg = getDstOfOnlyCopyToRegUse(Op.Val, Op.getResNo());
     // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
     // does not include operand register class info.
     if (!VReg) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=55394&r1=55393&r2=55394&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Aug 26 17:36:50 2008
@@ -652,7 +652,7 @@
   }
   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
     const SDValue &Op = N->getOperand(i);
-    MVT VT = Op.Val->getValueType(Op.ResNo);
+    MVT VT = Op.Val->getValueType(Op.getResNo());
     if (VT == MVT::Flag)
       return NULL;
   }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=55394&r1=55393&r2=55394&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Aug 26 17:36:50 2008
@@ -327,7 +327,7 @@
                               const SDValue *Ops, unsigned NumOps) {
   for (; NumOps; --NumOps, ++Ops) {
     ID.AddPointer(Ops->Val);
-    ID.AddInteger(Ops->ResNo);
+    ID.AddInteger(Ops->getResNo());
   }
 }
 
@@ -337,7 +337,7 @@
                               const SDUse *Ops, unsigned NumOps) {
   for (; NumOps; --NumOps, ++Ops) {
     ID.AddPointer(Ops->getVal());
-    ID.AddInteger(Ops->getSDValue().ResNo);
+    ID.AddInteger(Ops->getSDValue().getResNo());
   }
 }
 
@@ -3666,7 +3666,7 @@
   // See if the modified node already exists.
   void *InsertPos = 0;
   if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos))
-    return SDValue(Existing, InN.ResNo);
+    return SDValue(Existing, InN.getResNo());
   
   // Nope it doesn't.  Remove the node from its current place in the maps.
   if (InsertPos)
@@ -3695,7 +3695,7 @@
   // See if the modified node already exists.
   void *InsertPos = 0;
   if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos))
-    return SDValue(Existing, InN.ResNo);
+    return SDValue(Existing, InN.getResNo());
   
   // Nope it doesn't.  Remove the node from its current place in the maps.
   if (InsertPos)
@@ -3761,7 +3761,7 @@
   // See if the modified node already exists.
   void *InsertPos = 0;
   if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos))
-    return SDValue(Existing, InN.ResNo);
+    return SDValue(Existing, InN.getResNo());
   
   // Nope it doesn't.  Remove the node from its current place in the maps.
   if (InsertPos)
@@ -4161,7 +4161,7 @@
 void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To,
                                       DAGUpdateListener *UpdateListener) {
   SDNode *From = FromN.Val;
-  assert(From->getNumValues() == 1 && FromN.ResNo == 0 && 
+  assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 
          "Cannot replace with this method!");
   assert(From != To.Val && "Cannot replace uses of with self");
 
@@ -4267,7 +4267,7 @@
     for (SDNode::op_iterator I = U->op_begin(), E = U->op_end();
          I != E; ++I, ++operandNum)
       if (I->getVal() == From) {
-        const SDValue &ToOp = To[I->getSDValue().ResNo];
+        const SDValue &ToOp = To[I->getSDValue().getResNo()];
         From->removeUser(operandNum, U);
         *I = ToOp;
         I->setUser(U);
@@ -4573,7 +4573,7 @@
 
   // TODO: Only iterate over uses of a given value of the node
   for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) {
-    if (UI.getUse().getSDValue().ResNo == Value) {
+    if (UI.getUse().getSDValue().getResNo() == Value) {
       if (NUses == 0)
         return false;
       --NUses;
@@ -4591,7 +4591,7 @@
   assert(Value < getNumValues() && "Bad value!");
 
   for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI)
-    if (UI.getUse().getSDValue().ResNo == Value)
+    if (UI.getUse().getSDValue().getResNo() == Value)
       return true;
 
   return false;
@@ -5000,7 +5000,7 @@
   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     if (i) OS << ", ";
     OS << (void*)getOperand(i).Val;
-    if (unsigned RN = getOperand(i).ResNo)
+    if (unsigned RN = getOperand(i).getResNo())
       OS << ":" << RN;
   }
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=55394&r1=55393&r2=55394&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Aug 26 17:36:50 2008
@@ -1306,7 +1306,7 @@
       else if (F->paramHasAttr(0, ParamAttr::ZExt))
         ExtendKind = ISD::ZERO_EXTEND;
 
-      getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.ResNo + j),
+      getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.getResNo() + j),
                      &Parts[0], NumParts, PartVT, ExtendKind);
 
       for (unsigned i = 0; i < NumParts; ++i) {
@@ -2736,15 +2736,15 @@
   // Copy the beginning value(s) from the original aggregate.
   for (; i != LinearIndex; ++i)
     Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
-                SDValue(Agg.Val, Agg.ResNo + i);
+                SDValue(Agg.Val, Agg.getResNo() + i);
   // Copy values from the inserted value(s).
   for (; i != LinearIndex + NumValValues; ++i)
     Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
-                SDValue(Val.Val, Val.ResNo + i - LinearIndex);
+                SDValue(Val.Val, Val.getResNo() + i - LinearIndex);
   // Copy remaining value(s) from the original aggregate.
   for (; i != NumAggValues; ++i)
     Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
-                SDValue(Agg.Val, Agg.ResNo + i);
+                SDValue(Agg.Val, Agg.getResNo() + i);
 
   setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
                                   &Values[0], NumAggValues));
@@ -2769,8 +2769,8 @@
   // Copy out the selected value(s).
   for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
     Values[i - LinearIndex] =
-      OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) :
-                   SDValue(Agg.Val, Agg.ResNo + i);
+      OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.getResNo() + i)) :
+                   SDValue(Agg.Val, Agg.getResNo() + i);
 
   setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
                                   &Values[0], NumValValues));
@@ -2965,7 +2965,7 @@
   bool isVolatile = I.isVolatile();
   unsigned Alignment = I.getAlignment();
   for (unsigned i = 0; i != NumValues; ++i)
-    Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.ResNo + i),
+    Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.getResNo() + i),
                              DAG.getNode(ISD::ADD, PtrVT, Ptr,
                                          DAG.getConstant(Offsets[i], PtrVT)),
                              PtrV, Offsets[i],
@@ -3810,7 +3810,7 @@
     unsigned NumParts = TLI->getNumRegisters(ValueVT);
     MVT RegisterVT = RegVTs[Value];
 
-    getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
+    getCopyToParts(DAG, Val.getValue(Val.getResNo() + Value),
                    &Parts[Part], NumParts, RegisterVT);
     Part += NumParts;
   }
@@ -4763,7 +4763,7 @@
          Value != NumValues; ++Value) {
       MVT VT = ValueVTs[Value];
       const Type *ArgTy = VT.getTypeForMVT();
-      SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.ResNo + Value);
+      SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.getResNo() + Value);
       ISD::ArgFlagsTy Flags;
       unsigned OriginalAlignment =
         getTargetData()->getABITypeAlignment(ArgTy);
@@ -5017,8 +5017,8 @@
       (Op.getOpcode() == ISD::LOAD &&
        IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
       (Op.getOpcode() == ISD::MERGE_VALUES &&
-       Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD &&
-       IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo).
+       Op.getOperand(Op.getResNo()).getOpcode() == ISD::LOAD &&
+       IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.getResNo()).
                                        getOperand(1))))
     return true;
   return false;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=55394&r1=55393&r2=55394&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Tue Aug 26 17:36:50 2008
@@ -59,7 +59,7 @@
     static EdgeIter getEdgeTarget(const void *Node, EdgeIter I) {
       SDNode *TargetNode = *I;
       SDNodeIterator NI = SDNodeIterator::begin(TargetNode);
-      std::advance(NI, I.getNode()->getOperand(I.getOperand()).ResNo);
+      std::advance(NI, I.getNode()->getOperand(I.getOperand()).getResNo());
       return NI;
     }
 
@@ -110,7 +110,7 @@
                                        GraphWriter<SelectionDAG*> &GW) {
       GW.emitSimpleNode(0, "plaintext=circle", "GraphRoot");
       if (G->getRoot().Val)
-        GW.emitEdge(0, -1, G->getRoot().Val, G->getRoot().ResNo,
+        GW.emitEdge(0, -1, G->getRoot().Val, G->getRoot().getResNo(),
                     "color=blue,style=dashed");
     }
   };

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=55394&r1=55393&r2=55394&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Aug 26 17:36:50 2008
@@ -733,7 +733,7 @@
       InFlag = SDValue(ResNode, 1);
       ReplaceUses(SDValue(Op.Val, 1), InFlag);
     }
-    ReplaceUses(SDValue(Op.Val, 0), SDValue(Chain.Val, Chain.ResNo));
+    ReplaceUses(SDValue(Op.Val, 0), SDValue(Chain.Val, Chain.getResNo()));
     return NULL;
   }
   case ARMISD::CMOV: {

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=55394&r1=55393&r2=55394&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Aug 26 17:36:50 2008
@@ -646,7 +646,7 @@
 
   ResultVals.push_back(Chain);
   SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size());
-  return Res.getValue(Op.ResNo);
+  return Res.getValue(Op.getResNo());
 }
 
 static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {

Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=55394&r1=55393&r2=55394&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Tue Aug 26 17:36:50 2008
@@ -1292,7 +1292,7 @@
   // Otherwise, merge everything together with a MERGE_VALUES node.
   ResultVals[NumResults++] = Chain;
   SDValue Res = DAG.getMergeValues(ResultVals, NumResults);
-  return Res.getValue(Op.ResNo);
+  return Res.getValue(Op.getResNo());
 }
 
 static SDValue

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=55394&r1=55393&r2=55394&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Aug 26 17:36:50 2008
@@ -750,7 +750,7 @@
 
   // Handle result values, copying them out of physregs into vregs that we
   // return.
-  return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
+  return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.getResNo());
 }
 
 /// LowerCallResult - Lower the result values of an ISD::CALL into the
@@ -926,7 +926,7 @@
 
   // Return the new list of results.
   return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
-                            ArgValues.size()).getValue(Op.ResNo);
+                            ArgValues.size()).getValue(Op.getResNo());
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=55394&r1=55393&r2=55394&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Tue Aug 26 17:36:50 2008
@@ -544,7 +544,7 @@
   ArgValues.push_back(Root);
 
   return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
-                            ArgValues.size()).getValue(Op.ResNo);
+                            ArgValues.size()).getValue(Op.getResNo());
 }
 
 

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=55394&r1=55393&r2=55394&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Aug 26 17:36:50 2008
@@ -2511,7 +2511,7 @@
            "Flag must be set. Depend on flag being set in LowerRET");
     Chain = DAG.getNode(PPCISD::TAILCALL,
                         Op.Val->getVTList(), &Ops[0], Ops.size());
-    return SDValue(Chain.Val, Op.ResNo);
+    return SDValue(Chain.Val, Op.getResNo());
   }
 
   Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
@@ -2548,7 +2548,7 @@
   ResultVals.push_back(Chain);
   SDValue Res = DAG.getMergeValues(Op.Val->getVTList(), &ResultVals[0],
                                      ResultVals.size());
-  return Res.getValue(Op.ResNo);
+  return Res.getValue(Op.getResNo());
 }
 
 SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG, 

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=55394&r1=55393&r2=55394&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Aug 26 17:36:50 2008
@@ -253,7 +253,7 @@
     SDNode *User = *I;
     for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
       SDValue Op = User->getOperand(i);
-      if (Op.Val == N && Op.ResNo == FlagResNo)
+      if (Op.Val == N && Op.getResNo() == FlagResNo)
         return User;
     }
   }
@@ -888,7 +888,7 @@
   case ISD::SMUL_LOHI:
   case ISD::UMUL_LOHI:
     // A mul_lohi where we need the low part can be folded as a plain multiply.
-    if (N.ResNo != 0) break;
+    if (N.getResNo() != 0) break;
     // FALL THROUGH
   case ISD::MUL:
     // X*[3,5,9] -> X+X*[2,4,8]

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=55394&r1=55393&r2=55394&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 26 17:36:50 2008
@@ -1396,7 +1396,7 @@
 
   // Return the new list of results.
   return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
-                            ArgValues.size()).getValue(Op.ResNo);
+                            ArgValues.size()).getValue(Op.getResNo());
 }
 
 SDValue
@@ -1760,7 +1760,7 @@
     Chain = DAG.getNode(X86ISD::TAILCALL,
                         Op.Val->getVTList(), &Ops[0], Ops.size());
       
-    return SDValue(Chain.Val, Op.ResNo);
+    return SDValue(Chain.Val, Op.getResNo());
   }
 
   Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
@@ -1787,7 +1787,7 @@
 
   // Handle result values, copying them out of physregs into vregs that we
   // return.
-  return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
+  return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.getResNo());
 }
 
 

Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=55394&r1=55393&r2=55394&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Tue Aug 26 17:36:50 2008
@@ -1190,7 +1190,7 @@
         ReplaceFroms.push_back("SDValue(N.Val, " +
                                utostr(NumPatResults) + ")");
         ReplaceTos.push_back("SDValue(" + ChainName + ".Val, " +
-                             ChainName + ".ResNo" + ")");
+                             ChainName + ".getResNo()" + ")");
         ChainAssignmentNeeded |= NodeHasChain;
       }
 
@@ -1203,7 +1203,7 @@
           ReplaceFroms.push_back("SDValue(N.Val, " +
                                  utostr(NumPatResults+1) +
                                  ")");
-          ReplaceTos.push_back("SDValue(ResNode, N.ResNo-1)");
+          ReplaceTos.push_back("SDValue(ResNode, N.getResNo()-1)");
         }
         ReplaceFroms.push_back("SDValue(N.Val, " +
                                utostr(NumPatResults) + ")");




From resistor at mac.com  Tue Aug 26 18:14:49 2008
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Aug 2008 23:14:49 -0000
Subject: [llvm-commits] [llvm] r55396 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808262314.m7QNEn9x010939@zion.cs.uiuc.edu>

Author: resistor
Date: Tue Aug 26 18:14:49 2008
New Revision: 55396

URL: http://llvm.org/viewvc/llvm-project?rev=55396&view=rev
Log:
Add support for fast isel of zext.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55396&r1=55395&r2=55396&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Aug 26 18:14:49 2008
@@ -330,6 +330,35 @@
         // or attempt constant folding.
         return I;
 
+    case Instruction::ZExt:
+      if (!isa<ConstantInt>(I->getOperand(0))) {
+        MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
+        MVT DstVT = MVT::getMVT(I->getType());
+        
+        if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
+            DstVT == MVT::Other || !DstVT.isSimple() ||
+            !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
+          // Unhandled type. Halt "fast" selection and bail.
+          return I;
+        
+        unsigned InputReg = ValueMap[I->getOperand(0)];
+        if (!InputReg)
+          // Unhandled operand.  Halt "fast" selection and bail.
+          return I;
+        
+        unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
+                                        DstVT.getSimpleVT(),
+                                        ISD::ZERO_EXTEND,
+                                        InputReg);
+        if (!ResultReg)
+          return I;
+        
+        ValueMap[I] = ResultReg;
+        break;
+      } else
+        // TODO: Support constant operands
+        return I;
+
     case Instruction::SIToFP:
       if (!isa<ConstantInt>(I->getOperand(0))) {
         MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());




From lattner at cs.uiuc.edu  Tue Aug 26 18:17:46 2008
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 26 Aug 2008 18:17:46 -0500
Subject: [llvm-commits] CVS: llvm-www/RandomBoxes/003-Stacker.html
Message-ID: <200808262317.m7QNHkkk011128@zion.cs.uiuc.edu>



Changes in directory llvm-www/RandomBoxes:

003-Stacker.html (r1.1) removed
---
Log message:

stacker is no longer "neat" :)


---
Diffs of the changes:  (+0 -0)

 0 files changed





From gohman at apple.com  Tue Aug 26 18:19:24 2008
From: gohman at apple.com (Dan Gohman)
Date: Tue, 26 Aug 2008 23:19:24 -0000
Subject: [llvm-commits] [llvm] r55397 -
	/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h
Message-ID: <200808262319.m7QNJOFX011186@zion.cs.uiuc.edu>

Author: djg
Date: Tue Aug 26 18:19:23 2008
New Revision: 55397

URL: http://llvm.org/viewvc/llvm-project?rev=55397&view=rev
Log:
Add a MachineInstrBuilder method for adding floating-point
immediate operands.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h

Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=55397&r1=55396&r2=55397&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Tue Aug 26 18:19:23 2008
@@ -52,6 +52,11 @@
     return *this;
   }
 
+  const MachineInstrBuilder &addFPImm(ConstantFP *Val) const {
+    MI->addOperand(MachineOperand::CreateFPImm(Val));
+    return *this;
+  }
+
   const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB) const {
     MI->addOperand(MachineOperand::CreateMBB(MBB));
     return *this;




From resistor at mac.com  Tue Aug 26 18:46:32 2008
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Aug 2008 23:46:32 -0000
Subject: [llvm-commits] [llvm] r55398 - in /llvm/trunk:
 include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808262346.m7QNkXIR012345@zion.cs.uiuc.edu>

Author: resistor
Date: Tue Aug 26 18:46:32 2008
New Revision: 55398

URL: http://llvm.org/viewvc/llvm-project?rev=55398&view=rev
Log:
Factor out a large amoutn of the cast handling code in fast isel into helper methods.
This simultaneously makes the code simpler and adds support for sext as well.

Modified:
    llvm/trunk/include/llvm/CodeGen/FastISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=55398&r1=55397&r2=55398&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Tue Aug 26 18:46:32 2008
@@ -170,6 +170,14 @@
 
   bool SelectBitCast(Instruction *I,
                      DenseMap<const Value*, unsigned> &ValueMap);
+  
+  bool SelectCast(Instruction *I, ISD::NodeType Opcode,
+                  DenseMap<const Value*, unsigned> &ValueMap);
+  
+  bool SelectConstantCast(Instruction *I, ISD::NodeType Opcode,
+                          DenseMap<const Value*, unsigned> &ValueMap);
+  bool SelectConstantFPCast(Instruction *I, ISD::NodeType Opcode,
+                            DenseMap<const Value*, unsigned> &ValueMap);
 };
 
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55398&r1=55397&r2=55398&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Aug 26 18:46:32 2008
@@ -149,6 +149,70 @@
   return true;
 }
 
+bool FastISel::SelectCast(Instruction *I, ISD::NodeType Opcode,
+                          DenseMap<const Value*, unsigned> &ValueMap) {
+  MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
+  MVT DstVT = MVT::getMVT(I->getType());
+    
+  if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
+      DstVT == MVT::Other || !DstVT.isSimple() ||
+      !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
+    // Unhandled type. Halt "fast" selection and bail.
+    return false;
+    
+  unsigned InputReg = ValueMap[I->getOperand(0)];
+  if (!InputReg)
+    // Unhandled operand.  Halt "fast" selection and bail.
+    return false;
+    
+  unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
+                                  DstVT.getSimpleVT(),
+                                  Opcode,
+                                  InputReg);
+  if (!ResultReg)
+    return false;
+    
+  ValueMap[I] = ResultReg;
+  return true;
+}
+
+bool FastISel::SelectConstantCast(Instruction* I, ISD::NodeType Opcode,
+                                  DenseMap<const Value*, unsigned> &ValueMap) {
+  // Materialize constant and convert.
+  ConstantInt* CI = cast<ConstantInt>(I->getOperand(0));
+  MVT SrcVT = MVT::getMVT(CI->getType());
+  MVT DstVT = MVT::getMVT(I->getType());
+  
+  if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
+      DstVT == MVT::Other || !DstVT.isSimple() ||
+      !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
+    // Unhandled type. Halt "fast" selection and bail.
+    return false;
+  
+  unsigned ResultReg1 = FastEmit_i(SrcVT.getSimpleVT(),
+                                   SrcVT.getSimpleVT(),
+                                   ISD::Constant, CI->getZExtValue());
+  if (!ResultReg1)
+    return false;
+  
+  unsigned ResultReg2 = FastEmit_r(SrcVT.getSimpleVT(),
+                                   DstVT.getSimpleVT(),
+                                   Opcode,
+                                   ResultReg1);
+  if (!ResultReg2)
+    return false;
+  
+  ValueMap[I] = ResultReg2;
+  return true;
+}
+
+bool FastISel::SelectConstantFPCast(Instruction* I, ISD::NodeType Opcode,
+                                  DenseMap<const Value*, unsigned> &ValueMap) {
+  // TODO: Implement casting of FP constants by materialization
+  // followed by conversion.
+  return false;
+}
+
 bool FastISel::SelectBitCast(Instruction *I,
                              DenseMap<const Value*, unsigned> &ValueMap) {
   // BitCast consists of either an immediate to register move
@@ -297,122 +361,32 @@
       break;
       
     case Instruction::BitCast:
-      if (!SelectBitCast(I, ValueMap)) return I;
-      break;
+      if (!SelectBitCast(I, ValueMap)) return I; break;
 
     case Instruction::FPToSI:
       if (!isa<ConstantFP>(I->getOperand(0))) {
-        MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
-        MVT DstVT = MVT::getMVT(I->getType());
-        
-        if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
-            DstVT == MVT::Other || !DstVT.isSimple() ||
-            !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
-          // Unhandled type. Halt "fast" selection and bail.
-          return I;
-        
-        unsigned InputReg = ValueMap[I->getOperand(0)];
-        if (!InputReg)
-          // Unhandled operand.  Halt "fast" selection and bail.
-          return I;
-        
-        unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
-                                        DstVT.getSimpleVT(),
-                                        ISD::FP_TO_SINT,
-                                        InputReg);
-        if (!ResultReg)
-          return I;
-        
-        ValueMap[I] = ResultReg;
-        break;
+        if (!SelectCast(I, ISD::FP_TO_SINT, ValueMap)) return I; 
       } else
-        // TODO: Materialize the FP constant and then convert,
-        // or attempt constant folding.
-        return I;
-
+        if (!SelectConstantFPCast(I, ISD::FP_TO_SINT, ValueMap)) return I;
+      break;
     case Instruction::ZExt:
       if (!isa<ConstantInt>(I->getOperand(0))) {
-        MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
-        MVT DstVT = MVT::getMVT(I->getType());
-        
-        if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
-            DstVT == MVT::Other || !DstVT.isSimple() ||
-            !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
-          // Unhandled type. Halt "fast" selection and bail.
-          return I;
-        
-        unsigned InputReg = ValueMap[I->getOperand(0)];
-        if (!InputReg)
-          // Unhandled operand.  Halt "fast" selection and bail.
-          return I;
-        
-        unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
-                                        DstVT.getSimpleVT(),
-                                        ISD::ZERO_EXTEND,
-                                        InputReg);
-        if (!ResultReg)
-          return I;
-        
-        ValueMap[I] = ResultReg;
-        break;
+        if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
       } else
-        // TODO: Support constant operands
-        return I;
-
+        if (!SelectConstantCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
+      break;
+    case Instruction::SExt:
+      if (!isa<ConstantInt>(I->getOperand(0))) {
+        if (!SelectCast(I, ISD::SIGN_EXTEND, ValueMap)) return I;
+      } else
+        if (!SelectConstantCast(I, ISD::SIGN_EXTEND, ValueMap)) return I;
+      break;
     case Instruction::SIToFP:
       if (!isa<ConstantInt>(I->getOperand(0))) {
-        MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
-        MVT DstVT = MVT::getMVT(I->getType());
-        
-        if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
-            DstVT == MVT::Other || !DstVT.isSimple() ||
-            !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
-          // Unhandled type. Halt "fast" selection and bail.
-          return I;
-        
-        unsigned InputReg = ValueMap[I->getOperand(0)];
-        if (!InputReg)
-          // Unhandled operan.  Halt "fast" selection and bail.
-          return I;
-        
-        unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
-                                        DstVT.getSimpleVT(),
-                                        ISD::SINT_TO_FP,
-                                        InputReg);
-        if (!ResultReg)
-          return I;
-        
-        ValueMap[I] = ResultReg;
-        break;
-      } else {
-        // Materialize constant and convert to FP.
-        // TODO: Attempt constant folding?
-        ConstantInt* CI = cast<ConstantInt>(I->getOperand(0));
-        MVT SrcVT = MVT::getMVT(CI->getType());
-        MVT DstVT = MVT::getMVT(I->getType());
-        
-        if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
-            DstVT == MVT::Other || !DstVT.isSimple() ||
-            !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
-          // Unhandled type. Halt "fast" selection and bail.
-          return I;
-        
-        unsigned ResultReg1 = FastEmit_i(SrcVT.getSimpleVT(),
-                                         SrcVT.getSimpleVT(),
-                                         ISD::Constant, CI->getZExtValue());
-        if (!ResultReg1)
-          return I;
-        
-        unsigned ResultReg2 = FastEmit_r(SrcVT.getSimpleVT(),
-                                         DstVT.getSimpleVT(),
-                                         ISD::SINT_TO_FP,
-                                         ResultReg1);
-        if (!ResultReg2)
-          return I;
-        
-        ValueMap[I] = ResultReg2;
-        break;
-      }
+        if (!SelectCast(I, ISD::SINT_TO_FP, ValueMap)) return I;
+      } else
+        if (!SelectConstantCast(I, ISD::SINT_TO_FP, ValueMap)) return I;
+      break;
 
     default:
       // Unhandled instruction. Halt "fast" selection and bail.




From resistor at mac.com  Tue Aug 26 19:31:02 2008
From: resistor at mac.com (Owen Anderson)
Date: Wed, 27 Aug 2008 00:31:02 -0000
Subject: [llvm-commits] [llvm] r55399 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808270031.m7R0V2vM013908@zion.cs.uiuc.edu>

Author: resistor
Date: Tue Aug 26 19:31:01 2008
New Revision: 55399

URL: http://llvm.org/viewvc/llvm-project?rev=55399&view=rev
Log:
Add support for fast isel of inttoptr and ptrtoint in the cases where truncation is not needed.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55399&r1=55398&r2=55399&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Aug 26 19:31:01 2008
@@ -388,6 +388,25 @@
         if (!SelectConstantCast(I, ISD::SINT_TO_FP, ValueMap)) return I;
       break;
 
+    case Instruction::IntToPtr: // Deliberate fall-through.
+    case Instruction::PtrToInt: {
+      MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
+      MVT DstVT = TLI.getValueType(I->getType());
+      if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
+        ValueMap[I] = ValueMap[I->getOperand(0)];
+        break;
+      } else if (DstVT.bitsGT(SrcVT)) {
+        if (!isa<ConstantInt>(I->getOperand(0))) {
+          if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
+        } else
+          if (!SelectConstantCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
+        break;
+      } else {
+        // TODO: Handle SrcVT > DstVT, where truncation is needed.
+        return I;
+      }
+    }
+    
     default:
       // Unhandled instruction. Halt "fast" selection and bail.
       return I;




From resistor at mac.com  Tue Aug 26 19:35:37 2008
From: resistor at mac.com (Owen Anderson)
Date: Wed, 27 Aug 2008 00:35:37 -0000
Subject: [llvm-commits] [llvm] r55400 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808270035.m7R0Zba9014029@zion.cs.uiuc.edu>

Author: resistor
Date: Tue Aug 26 19:35:37 2008
New Revision: 55400

URL: http://llvm.org/viewvc/llvm-project?rev=55400&view=rev
Log:
Fix handling of inttoptr and ptrtoint when unhandled operands are present.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55400&r1=55399&r2=55400&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Aug 26 19:35:37 2008
@@ -393,8 +393,12 @@
       MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
       MVT DstVT = TLI.getValueType(I->getType());
       if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
-        ValueMap[I] = ValueMap[I->getOperand(0)];
-        break;
+        if (ValueMap[I->getOperand(0)]) {
+          ValueMap[I] = ValueMap[I->getOperand(0)];
+          break;
+        } else
+          // Unhandled operand
+          return I;
       } else if (DstVT.bitsGT(SrcVT)) {
         if (!isa<ConstantInt>(I->getOperand(0))) {
           if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;




From gohman at apple.com  Tue Aug 26 20:09:56 2008
From: gohman at apple.com (Dan Gohman)
Date: Wed, 27 Aug 2008 01:09:56 -0000
Subject: [llvm-commits] [llvm] r55401 - in /llvm/trunk:
 include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp
 test/CodeGen/X86/fast-isel.ll utils/TableGen/FastISelEmitter.cpp
Message-ID: <200808270109.m7R19v1V015283@zion.cs.uiuc.edu>

Author: djg
Date: Tue Aug 26 20:09:54 2008
New Revision: 55401

URL: http://llvm.org/viewvc/llvm-project?rev=55401&view=rev
Log:
Basic FastISel support for floating-point constants.

Modified:
    llvm/trunk/include/llvm/CodeGen/FastISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
    llvm/trunk/test/CodeGen/X86/fast-isel.ll
    llvm/trunk/utils/TableGen/FastISelEmitter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=55401&r1=55400&r2=55401&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Tue Aug 26 20:09:54 2008
@@ -20,6 +20,7 @@
 
 namespace llvm {
 
+class ConstantFP;
 class MachineBasicBlock;
 class MachineFunction;
 class MachineRegisterInfo;
@@ -93,6 +94,15 @@
                                ISD::NodeType Opcode,
                                unsigned Op0, uint64_t Imm);
 
+  /// FastEmit_rf - This method is called by target-independent code
+  /// to request that an instruction with the given type, opcode, and
+  /// register and floating-point immediate operands be emitted.
+  ///
+  virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
+                               MVT::SimpleValueType RetVT,
+                               ISD::NodeType Opcode,
+                               unsigned Op0, ConstantFP *FPImm);
+
   /// FastEmit_rri - This method is called by target-independent code
   /// to request that an instruction with the given type, opcode, and
   /// register and immediate operands be emitted.
@@ -111,6 +121,15 @@
                         unsigned Op0, uint64_t Imm,
                         MVT::SimpleValueType ImmType);
   
+  /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
+  /// to emit an instruction with an immediate operand using FastEmit_rf.
+  /// If that fails, it materializes the immediate into a register and try
+  /// FastEmit_rr instead.
+  unsigned FastEmit_rf_(MVT::SimpleValueType VT,
+                        ISD::NodeType Opcode,
+                        unsigned Op0, ConstantFP *FPImm,
+                        MVT::SimpleValueType ImmType);
+  
   /// FastEmit_i - This method is called by target-independent code
   /// to request that an instruction with the given type, opcode, and
   /// immediate operand be emitted.
@@ -119,6 +138,14 @@
                               ISD::NodeType Opcode,
                               uint64_t Imm);
 
+  /// FastEmit_f - This method is called by target-independent code
+  /// to request that an instruction with the given type, opcode, and
+  /// floating-point immediate operand be emitted.
+  virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
+                              MVT::SimpleValueType RetVT,
+                              ISD::NodeType Opcode,
+                              ConstantFP *FPImm);
+
   /// FastEmitInst_ - Emit a MachineInstr with no operands and a
   /// result register in the given register class.
   ///
@@ -146,6 +173,13 @@
                            const TargetRegisterClass *RC,
                            unsigned Op0, uint64_t Imm);
 
+  /// FastEmitInst_rf - Emit a MachineInstr with two register operands
+  /// and a result register in the given register class.
+  ///
+  unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
+                           const TargetRegisterClass *RC,
+                           unsigned Op0, ConstantFP *FPImm);
+
   /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
   /// an immediate, and a result register in the given register class.
   ///

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55401&r1=55400&r2=55401&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Aug 26 20:09:54 2008
@@ -56,6 +56,20 @@
     return true;
   }
 
+  // Check if the second operand is a constant float.
+  if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
+    unsigned ResultReg = FastEmit_rf_(VT.getSimpleVT(), ISDOpcode, Op0,
+                                      CF, VT.getSimpleVT());
+    if (ResultReg == 0)
+      // Target-specific code wasn't able to find a machine opcode for
+      // the given ISD opcode and type. Halt "fast" selection and bail.
+      return false;
+
+    // We successfully emitted code for the given LLVM Instruction.
+    ValueMap[I] = ResultReg;
+    return true;
+  }
+
   unsigned Op1 = ValueMap[I->getOperand(1)];
   if (Op1 == 0)
     // Unhandled operand. Halt "fast" selection and bail.
@@ -451,12 +465,23 @@
   return 0;
 }
 
+unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
+                              ISD::NodeType, ConstantFP * /*FPImm*/) {
+  return 0;
+}
+
 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
                                ISD::NodeType, unsigned /*Op0*/,
                                uint64_t /*Imm*/) {
   return 0;
 }
 
+unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
+                               ISD::NodeType, unsigned /*Op0*/,
+                               ConstantFP * /*FPImm*/) {
+  return 0;
+}
+
 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
                                 ISD::NodeType,
                                 unsigned /*Op0*/, unsigned /*Op1*/,
@@ -483,6 +508,45 @@
   return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
 }
 
+/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
+/// to emit an instruction with a floating-point immediate operand using
+/// FastEmit_rf. If that fails, it materializes the immediate into a register
+/// and try FastEmit_rr instead.
+unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
+                                unsigned Op0, ConstantFP *FPImm,
+                                MVT::SimpleValueType ImmType) {
+  unsigned ResultReg = 0;
+  // First check if immediate type is legal. If not, we can't use the rf form.
+  if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
+    ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
+  if (ResultReg != 0)
+    return ResultReg;
+
+  // Materialize the constant in a register.
+  unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
+  if (MaterialReg == 0) {
+    const APFloat &Flt = FPImm->getValueAPF();
+    MVT IntVT = TLI.getPointerTy();
+
+    uint64_t x[2];
+    uint32_t IntBitWidth = IntVT.getSizeInBits();
+    if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
+                             APFloat::rmTowardZero) != APFloat::opOK)
+      return 0;
+    APInt IntVal(IntBitWidth, 2, x);
+
+    unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
+                                     ISD::Constant, IntVal.getZExtValue());
+    if (IntegerReg == 0)
+      return 0;
+    MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
+                             ISD::SINT_TO_FP, IntegerReg);
+    if (MaterialReg == 0)
+      return 0;
+  }
+  return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
+}
+
 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
   return MRI.createVirtualRegister(RC);
 }
@@ -526,6 +590,16 @@
   return ResultReg;
 }
 
+unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
+                                   const TargetRegisterClass *RC,
+                                   unsigned Op0, ConstantFP *FPImm) {
+  unsigned ResultReg = createResultReg(RC);
+  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
+
+  BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
+  return ResultReg;
+}
+
 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
                                     const TargetRegisterClass *RC,
                                     unsigned Op0, unsigned Op1, uint64_t Imm) {

Modified: llvm/trunk/test/CodeGen/X86/fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel.ll?rev=55401&r1=55400&r2=55401&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel.ll Tue Aug 26 20:09:54 2008
@@ -35,10 +35,11 @@
   %t0 = add double %r, %s
   %t1 = mul double %t0, %s
   %t2 = sub double %t1, %s
+  %t3 = add double %t2, 707.0
   br label %exit
 
 exit:
-  ret double %t2
+  ret double %t3
 }
 
 define i32 @cast(){

Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=55401&r1=55400&r2=55401&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Tue Aug 26 20:09:54 2008
@@ -68,6 +68,11 @@
       Operands.push_back("i");
       return true;
     }
+    if (!InstPatNode->isLeaf() &&
+        InstPatNode->getOperator()->getName() == "fpimm") {
+      Operands.push_back("f");
+      return true;
+    }
     
     const CodeGenRegisterClass *DstRC = 0;
     
@@ -87,6 +92,10 @@
           Operands.push_back("i");
           return true;
         }
+        if (Op->getOperator()->getName() == "fpimm") {
+          Operands.push_back("f");
+          return true;
+        }
         // For now, ignore fpimm and other non-leaf nodes.
         return false;
       }
@@ -122,6 +131,8 @@
         OS << "unsigned Op" << i;
       } else if (Operands[i] == "i") {
         OS << "uint64_t imm" << i;
+      } else if (Operands[i] == "f") {
+        OS << "ConstantFP *f" << i;
       } else {
         assert("Unknown operand kind!");
         abort();
@@ -137,6 +148,8 @@
         OS << "Op" << i;
       } else if (Operands[i] == "i") {
         OS << "imm" << i;
+      } else if (Operands[i] == "f") {
+        OS << "f" << i;
       } else {
         assert("Unknown operand kind!");
         abort();




From nicholas at mxc.ca  Tue Aug 26 21:48:39 2008
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 26 Aug 2008 19:48:39 -0700
Subject: [llvm-commits] [llvm] r55374 - in /llvm/trunk:
 lib/Transforms/Scalar/LoopStrengthReduce.cpp
 test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll
In-Reply-To: <200808261758.m7QHw5FM031611@zion.cs.uiuc.edu>
References: <200808261758.m7QHw5FM031611@zion.cs.uiuc.edu>
Message-ID: <48B4C087.1080807@mxc.ca>

Devang Patel wrote:
> Author: dpatel
> Date: Tue Aug 26 12:57:54 2008
> New Revision: 55374
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=55374&view=rev
> Log:
> If IV is used in a int-to-float cast inside the loop then try to eliminate the cast operation.
> 
> Modified:
>     llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
>     llvm/trunk/test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll
> 
> Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=55374&r1=55373&r2=55374&view=diff
> 
> ==============================================================================
> --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
> +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Tue Aug 26 12:57:54 2008
> @@ -45,6 +45,7 @@
>  STATISTIC(NumInserted,    "Number of PHIs inserted");
>  STATISTIC(NumVariable,    "Number of PHIs with variable strides");
>  STATISTIC(NumEliminated , "Number of strides eliminated");
> +STATISTIC(NumShadow , "Number of Shadow IVs optimized");

Please fix the whitespace; no space before the comma, the " should line up.

>  
>  namespace {
>  
> @@ -164,6 +165,7 @@
>        AU.addRequired<DominatorTree>();
>        AU.addRequired<TargetData>();
>        AU.addRequired<ScalarEvolution>();
> +      AU.addPreserved<ScalarEvolution>();

Good catch!

>      }
>      
>      /// getCastedVersionOf - Return the specified value casted to uintptr_t.
> @@ -177,8 +179,13 @@
>                                    IVStrideUse* &CondUse,
>                                    const SCEVHandle* &CondStride);
>      void OptimizeIndvars(Loop *L);
> +
> +    /// OptimizeShadowIV - If IV is used in a int-to-float cast
> +    /// inside the loop then try to eliminate the cast opeation.
> +    void OptimizeShadowIV(Loop *L);
> +
>      bool FindIVUserForCond(ICmpInst *Cond, IVStrideUse *&CondUse,
> -                       const SCEVHandle *&CondStride);
> +                           const SCEVHandle *&CondStride);
>      bool RequiresTypeConversion(const Type *Ty, const Type *NewTy);
>      unsigned CheckForIVReuse(bool, bool, const SCEVHandle&,
>                               IVExpr&, const Type*,
> @@ -1689,12 +1696,122 @@
>    return Cond;
>  }
>  
> +/// OptimizeShadowIV - If IV is used in a int-to-float cast
> +/// inside the loop then try to eliminate the cast opeation.
> +void LoopStrengthReduce::OptimizeShadowIV(Loop *L) {
> +
> +  SCEVHandle IterationCount = SE->getIterationCount(L);
> +  if (isa<SCEVCouldNotCompute>(IterationCount))
> +    return;
> +
> +  for (unsigned Stride = 0, e = StrideOrder.size(); Stride != e;
> +       ++Stride) {
> +    std::map<SCEVHandle, IVUsersOfOneStride>::iterator SI = 
> +      IVUsesByStride.find(StrideOrder[Stride]);
> +    assert(SI != IVUsesByStride.end() && "Stride doesn't exist!");
> +    if (!isa<SCEVConstant>(SI->first))
> +      continue;
> +
> +    for (std::vector<IVStrideUse>::iterator UI = SI->second.Users.begin(),
> +           E = SI->second.Users.end(); UI != E; /* empty */) {
> +      std::vector<IVStrideUse>::iterator CandidateUI = UI;
> +      UI++;

++UI;

> +      Instruction *ShadowUse = CandidateUI->User;
> +      const Type *DestTy = NULL;
> +
> +      /* If shadow use is a int->float cast then insert a second IV
> +         to elminate this cast.

typo: eliminate

> +
> +           for (unsigned i = 0; i < n; ++i) 
> +             foo((double)i);
> +
> +         is trnasformed into

typo: eliminate

> +
> +           double d = 0.0;
> +           for (unsigned i = 0; i < n; ++i, ++d) 
> +             foo(d);
> +      */

I have a problem with this. Suppose you get:

   for (unsigned i = x; i != 5, ++i)
     foo((double)i);

and SCEV claims the trip count is 10, regardless of what x is equal to. 
Your double would saturate while the integer would wrap around.

The fix for this is to test that the loop condition isn't an equality test.

> +      UIToFPInst *UCast = dyn_cast<UIToFPInst>(CandidateUI->User);
> +      if (UCast) 
> +        DestTy = UCast->getDestTy();
> +      else {
> +        SIToFPInst *SCast = dyn_cast<SIToFPInst>(CandidateUI->User);
> +        if (!SCast) continue;
> +        DestTy = SCast->getDestTy();
> +      }

How about:

          if (UIToFPInst *UCast =
              dyn_cast<UIToFPInst>(CandidateUI->User)) {
            DestTy = ...
          } else if (SIToFPInst *SCast =
                     dyn_cast<SIToFPInst>(CandidateUI->User)) {
            DestTy = ..
          }
          if (!DestTy) continue;

?

> +      
> +      PHINode *PH = dyn_cast<PHINode>(ShadowUse->getOperand(0));
> +      if (!PH) continue;
> +      if (PH->getNumIncomingValues() != 2) continue;
> +
> +      const Type *SrcTy = PH->getType();
> +      int Mantissa = DestTy->getFPMantissaWidth();
> +      if (Mantissa == -1) continue; 
> +      if ((int)TD->getTypeSizeInBits(SrcTy) > Mantissa)
> +        continue;
> +
> +      unsigned Entry, Latch;
> +      if (PH->getIncomingBlock(0) == L->getLoopPreheader()) {
> +        Entry = 0;
> +        Latch = 1;
> +      } else {
> +        Entry = 1;
> +        Latch = 0;
> +      }
> +        
> +      ConstantInt *Init = dyn_cast<ConstantInt>(PH->getIncomingValue(Entry));
> +      if (!Init) continue;
> +      ConstantFP *NewInit = ConstantFP::get(DestTy, Init->getZExtValue());
> +
> +      BinaryOperator *Incr = 
> +        dyn_cast<BinaryOperator>(PH->getIncomingValue(Latch));
> +      if (!Incr) continue;
> +      if (Incr->getOpcode() != Instruction::Add
> +          && Incr->getOpcode() != Instruction::Sub)
> +        continue;
> +
> +      /* Initialize new IV, double d = 0.0 in above example. */
> +      ConstantInt *C = NULL;
> +      if (Incr->getOperand(0) == PH)
> +        C = dyn_cast<ConstantInt>(Incr->getOperand(1));
> +      else if (Incr->getOperand(1) == PH)
> +        C = dyn_cast<ConstantInt>(Incr->getOperand(0));
> +      else
> +        continue;
> +
> +      if (!C) continue;
> +
> +      /* Add new PHINode. */
> +      PHINode *NewPH = PHINode::Create(DestTy, "IV.S.", PH);
> +
> +      /* create new icnrement. '++d' in above example. */

typo: increment

Nick

> +      ConstantFP *CFP = ConstantFP::get(DestTy, C->getZExtValue());
> +      BinaryOperator *NewIncr = 
> +        BinaryOperator::Create(Incr->getOpcode(),
> +                               NewPH, CFP, "IV.S.next.", Incr);
> +
> +      NewPH->addIncoming(NewInit, PH->getIncomingBlock(Entry));
> +      NewPH->addIncoming(NewIncr, PH->getIncomingBlock(Latch));
> +
> +      /* Remove cast operation */
> +      SE->deleteValueFromRecords(ShadowUse);
> +      ShadowUse->replaceAllUsesWith(NewPH);
> +      ShadowUse->eraseFromParent();
> +      SI->second.Users.erase(CandidateUI);
> +      NumShadow++;
> +      break;
> +    }
> +  }
> +}
> +
>  // OptimizeIndvars - Now that IVUsesByStride is set up with all of the indvar
>  // uses in the loop, look to see if we can eliminate some, in favor of using
>  // common indvars for the different uses.
>  void LoopStrengthReduce::OptimizeIndvars(Loop *L) {
>    // TODO: implement optzns here.
>  
> +  OptimizeShadowIV(L);
> +
>    // Finally, get the terminating condition for the loop if possible.  If we
>    // can, we want to change it to use a post-incremented version of its
>    // induction variable, to allow coalescing the live ranges for the IV into
> @@ -1852,6 +1969,5 @@
>      }
>      DeleteTriviallyDeadInstructions(DeadInsts);
>    }
> -
>    return Changed;
>  }
> 
> Modified: llvm/trunk/test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll?rev=55374&r1=55373&r2=55374&view=diff
> 
> ==============================================================================
> --- llvm/trunk/test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll (original)
> +++ llvm/trunk/test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll Tue Aug 26 12:57:54 2008
> @@ -1,5 +1,4 @@
>  ; RUN: llvm-as < %s | opt -loop-reduce | llvm-dis | grep "phi double" | count 1
> -; XFAIL: *
>  
>  define void @foobar(i32 %n) nounwind {
>  entry:
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 



From nicholas at mxc.ca  Tue Aug 26 22:00:53 2008
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 26 Aug 2008 20:00:53 -0700
Subject: [llvm-commits] [llvm] r55374 - in /llvm/trunk:
 lib/Transforms/Scalar/LoopStrengthReduce.cpp
 test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll
In-Reply-To: <48B4C087.1080807@mxc.ca>
References: <200808261758.m7QHw5FM031611@zion.cs.uiuc.edu>
	<48B4C087.1080807@mxc.ca>
Message-ID: <48B4C365.90702@mxc.ca>

Let me try this again, with added sanity this time :-)

Nick Lewycky wrote:
> 
>> +
>> +           for (unsigned i = 0; i < n; ++i) 
>> +             foo((double)i);
>> +
>> +         is trnasformed into
> 
> typo: eliminate

uh huh. typo: transformed

>> +
>> +           double d = 0.0;
>> +           for (unsigned i = 0; i < n; ++i, ++d) 
>> +             foo(d);
>> +      */
> 
> I have a problem with this. Suppose you get:
> 
>    for (unsigned i = x; i != 5, ++i)
>      foo((double)i);
> 
> and SCEV claims the trip count is 10, regardless of what x is equal to. 

Which is, of course, impossible. But suppose it were:
   for (unsigned i = x; i != y; ++i)

then it's possible. Also, 10 would get unrolled, but just work with me 
here. :-)

Nick


From evan.cheng at apple.com  Wed Aug 27 01:43:06 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 26 Aug 2008 23:43:06 -0700
Subject: [llvm-commits] Enable exceptions in JIT for Darwin
In-Reply-To: <48B12811.9090001@lip6.fr>
References: <48AAE0EF.6000808@lip6.fr>
	<18991E51-BD03-4704-ADC7-42215304046B@apple.com>
	<48AD253A.8030205@lip6.fr>
	<20698121-E9E0-4D8E-A622-0151729E3AB3@apple.com>
	<48B12811.9090001@lip6.fr>
Message-ID: <5C479C04-882C-40FA-AE5C-44C236339E39@apple.com>


On Aug 24, 2008, at 2:21 AM, Nicolas Geoffray wrote:

> Hi Evan,
>
> Evan Cheng wrote:
>>
>> +  // Allocate a new LibgccObject to represent this frame.
>> Deallocation of this
>> +  // object may be impossible: libgcc does not seem to deallocate  
>> it,
>> even with
>> +  // __deregister_frame. Deallocating it manually may also cause
>> libgcc to
>> +  // crash.
>> +  struct LibgccObject* ob = (struct LibgccObject*)
>> +    malloc(sizeof(struct LibgccObject));
>>
>> Are you sure you can't deallocate it when the JIT is teared down?
>>
>
> Not really sure. I can add a table of LibgccObject* to the LLVM JIT,  
> and
> deallocate them when the JIT is destroyed. However, libgcc will  
> probably
> dislike this if exceptions still occur after the JIT is destroyed. It
> may be feasible to remove the exception tables from libgcc's linked
> list, but libgcc may cache the tables some places I don't know.
>
> A deep understanding of how things work in libgcc is needed :). And I
> double-checked, my comment is actually wrong, the __deregister_frame
> function does deallocate the objects. However, it does not work with  
> the
> darwin code for libgcc...

After looking into this a bit, I think this is ok.

Nick, do you know anything about this?

Thanks,

Evan

>
>
> Nicolas
>
>
>> Evan
>>
>>
>> On Aug 21, 2008, at 1:20 AM, Nicolas Geoffray wrote:
>>
>>> Hi Evan,
>>>
>>> New patch with new un-gcc documentation :)
>>>
>>> Thanks for reviewing!
>>>
>>> Nicolas
>>>
>>> Evan Cheng wrote:
>>>> Hi Nicolas,
>>>>
>>>> Comments in line.
>>>>
>>>> On Aug 19, 2008, at 8:04 AM, Nicolas Geoffray wrote:
>>>>
>>>>
>>>>> Dear all,
>>>>>
>>>>> Here's a patch that enables exception handling on Darwin with the
>>>>> JIT. It's really ugly, it's a workaround to work with libgcc which
>>>>> is doing crazy stuff when unwinding the stack. The
>>>>> __register_frame  function was sufficient enough for Linux, but
>>>>> unfortunately, the  code for darwin erases by default the
>>>>> registered frames. In a  perfect world, I think libgcc should be
>>>>> modified....
>>>>>
>>>>>
>>>>> I'd be totally OK if you don't want this patch in, as it's an ugly
>>>>> workaround. I can move the patch to vmkit, and that would be fine
>>>>> by  me. However, this makes lli work out of the box with  
>>>>> exceptions
>>>>> and  darwin, so it's still an improvement.
>>>>>
>>>>> Nicolas
>>>>> Index: lib/ExecutionEngine/JIT/JIT.cpp
>>>>> = 
>>>>> ==================================================================
>>>>> --- lib/ExecutionEngine/JIT/JIT.cpp (revision 54920)
>>>>> +++ lib/ExecutionEngine/JIT/JIT.cpp (working copy)
>>>>> @@ -64,10 +64,73 @@
>>>>> }
>>>>> }
>>>>>
>>>>> +
>>>>> #if defined (__GNUC__)
>>>>> extern "C" void __register_frame(void*);
>>>>> -#endif
>>>>>
>>>>> +#if defined (__APPLE__)
>>>>> +struct object {
>>>>> +  void *pc_begin;
>>>>> +  void *tbase;
>>>>> +  void *dbase;
>>>>> +  void* real_begin;
>>>>> +
>>>>> +    union {
>>>>> +    struct {
>>>>> +      unsigned long sorted : 1;
>>>>> +      unsigned long from_array : 1;
>>>>> +      unsigned long mixed_encoding : 1;
>>>>> +      unsigned long encoding : 8;
>>>>> +      unsigned long count : 21;
>>>>> +    } b;
>>>>> +    size_t i;
>>>>> +  } s;
>>>>>
>>>>
>>>> Please pick more descriptive names than object, etc. Also, please
>>>> try  to match the naming convention used in the file. Some
>>>> documentation is  definitely welcome. :-)
>>>>
>>>>> +
>>>>> +  // Be pessimistic, include this field even if GCC
>>>>> +  // may not have it.
>>>>> +  char *fde_end;
>>>>> +
>>>>> +  struct object *next;
>>>>> +};
>>>>> +
>>>>> +extern "C" void _keymgr_set_and_unlock_processwide_ptr (int,  
>>>>> void *);
>>>>> +extern "C" void *_keymgr_get_and_lock_processwide_ptr (int);
>>>>> +#define KEYMGR_GCC3_DW2_OBJ_LIST        302     /* Dwarf2 object
>>>>> list  */
>>>>> +
>>>>> +struct km_object_info {
>>>>> +  struct object* seen_objects;
>>>>> +  struct object* unseen_objects;
>>>>> +  unsigned spare[2];
>>>>> +};
>>>>> +
>>>>> +extern "C" void darwin_register_frame(void* begin) {
>>>>> +  struct km_object_info* the_obj_info = (struct km_object_info*)
>>>>> +    _keymgr_get_and_lock_processwide_ptr  
>>>>> (KEYMGR_GCC3_DW2_OBJ_LIST);
>>>>> +
>>>>> +  struct object* ob = (struct object*)malloc(sizeof(struct  
>>>>> object));
>>>>>
>>>>
>>>> Who frees this?
>>>>
>>>>
>>>>> +  ob->pc_begin = (void *)-1;
>>>>> +  ob->tbase = 0;
>>>>> +  ob->dbase = 0;
>>>>> +  ob->real_begin = begin;
>>>>> +  ob->s.i = 0;
>>>>> +  //ob->s.b.encoding = DW_EH_PE_omit;
>>>>>
>>>>
>>>> Why is this commented out?
>>>>
>>>>
>>>>> +  ob->s.b.encoding = 0xff;
>>>>> +
>>>>> +  // Put the info on both places, as libgcc uses the first or the
>>>>> +  // the second field.
>>>>> +  ob->fde_end = (char*)the_obj_info->unseen_objects;
>>>>> +  ob->next = (struct object*)the_obj_info->unseen_objects;
>>>>>
>>>>
>>>> Are the casting necessary? Why not just define the types correctly.
>>>>
>>>>
>>>>> +
>>>>> +  the_obj_info->unseen_objects = ob;
>>>>> +
>>>>> +  _keymgr_set_and_unlock_processwide_ptr  
>>>>> (KEYMGR_GCC3_DW2_OBJ_LIST,
>>>>> +                                          the_obj_info);
>>>>> +
>>>>> +}
>>>>>
>>>>
>>>> Function level documentation please.
>>>>
>>>> Thanks!
>>>>
>>>> Evan
>>>>
>>>>
>>>>> +
>>>>> +#endif // __APPLE__
>>>>> +#endif // __GNUC__
>>>>> +
>>>>> /// createJIT - This is the factory method for creating a JIT for
>>>>> the current
>>>>> /// machine, it does not fall back to the interpreter.  This takes
>>>>> ownership
>>>>> /// of the module provider.
>>>>> @@ -108,8 +171,20 @@
>>>>>
>>>>> // Register routine for informing unwinding runtime about new EH
>>>>> frames
>>>>> #if defined(__GNUC__)
>>>>> +#if defined(__APPLE__)
>>>>> +  struct km_object_info* the_obj_info = (struct km_object_info*)
>>>>> +    _keymgr_get_and_lock_processwide_ptr  
>>>>> (KEYMGR_GCC3_DW2_OBJ_LIST);
>>>>> +
>>>>> +  if (!the_obj_info) {
>>>>> +    the_obj_info = (km_object_info*)malloc(sizeof(struct
>>>>> km_object_info));
>>>>> +    _keymgr_set_and_unlock_processwide_ptr  
>>>>> (KEYMGR_GCC3_DW2_OBJ_LIST,
>>>>> +                                            the_obj_info);
>>>>> +  }
>>>>> +  InstallExceptionTableRegister(darwin_register_frame);
>>>>> +#else
>>>>> InstallExceptionTableRegister(__register_frame);
>>>>> -#endif
>>>>> +#endif // __APPLE__
>>>>> +#endif // __GNUC__
>>>>>
>>>>>
>>>>> // Initialize passes.
>>>>> PM.doInitialization();
>>>>> _______________________________________________
>>>>> llvm-commits mailing list
>>>>> llvm-commits at cs.uiuc.edu <mailto:llvm-commits at cs.uiuc.edu>
>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>>
>>>>
>>>> _______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu <mailto:llvm-commits at cs.uiuc.edu>
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>
>>>
>>> Index: lib/ExecutionEngine/JIT/JIT.cpp
>>> ===================================================================
>>> --- lib/ExecutionEngine/JIT/JIT.cpp (revision 54988)
>>> +++ lib/ExecutionEngine/JIT/JIT.cpp (working copy)
>>> @@ -64,10 +64,128 @@
>>>  }
>>> }
>>>
>>> +
>>> #if defined (__GNUC__)
>>> +
>>> +// libgcc defines the __register_frame function to dynamically
>>> register new
>>> +// dwarf frames for exception handling. This functionality is not
>>> portable
>>> +// across compilers and is only provided by GCC. We use the
>>> __register_frame
>>> +// function here so that code generated by the JIT cooperates with
>>> the unwinding
>>> +// runtime of libgcc. When JITting with exception handling  
>>> enable, LLVM
>>> +// generates dwarf frames and registers it to libgcc with
>>> __register_frame.
>>> +//
>>> +// The __register_frame function works with Linux.
>>> +//
>>> +// Unfortunately, this functionality seems to be in libgcc after  
>>> the
>>> unwinding
>>> +// library of libgcc for darwin was written. The code for darwin
>>> overwrites the
>>> +// value updated by __register_frame with a value fetched with  
>>> "keymgr".
>>> +// "keymgr" is an obsolete functionality, which should be rewritten
>>> some day.
>>> +// In the meantime, since "keymgr" is on all libgccs shipped with
>>> apple-gcc, we
>>> +// need a workaround in LLVM which uses the "keymgr" to dynamically
>>> modify the
>>> +// values of an opaque key, used by libgcc to find dwarf tables.
>>> +
>>> extern "C" void __register_frame(void*);
>>> -#endif
>>>
>>> +#if defined (__APPLE__)
>>> +
>>> +namespace {
>>> +
>>> +// LibgccObject - This is the structure defined in libgcc. There is
>>> no #include
>>> +// provided for this structure, so we also define it here. libgcc
>>> calls it
>>> +// "struct object". The structure is undocumented in libgcc.
>>> +struct LibgccObject {
>>> +  void *unused1;
>>> +  void *unused2;
>>> +  void *unused3;
>>> +
>>> +  /// frame - Pointer to the exception table.
>>> +  void *frame;
>>> +
>>> +  /// encoding -  The encoding of the object?
>>> +  union {
>>> +    struct {
>>> +      unsigned long sorted : 1;
>>> +      unsigned long from_array : 1;
>>> +      unsigned long mixed_encoding : 1;
>>> +      unsigned long encoding : 8;
>>> +      unsigned long count : 21;
>>> +    } b;
>>> +    size_t i;
>>> +  } encoding;
>>> +
>>> +  /// fde_end - libgcc defines this field only if some macro is
>>> defined. We
>>> +  /// include this field even if it may not there, to make libgcc  
>>> happy.
>>> +  char *fde_end;
>>> +
>>> +  /// next - At least we know it's a chained list!
>>> +  struct LibgccObject *next;
>>> +};
>>> +
>>> +// "kemgr" stuff. Apparently, all frame tables are stored there.
>>> +extern "C" void _keymgr_set_and_unlock_processwide_ptr(int, void  
>>> *);
>>> +extern "C" void *_keymgr_get_and_lock_processwide_ptr(int);
>>> +#define KEYMGR_GCC3_DW2_OBJ_LIST        302     /* Dwarf2 object
>>> list  */
>>> +
>>> +/// LibgccObjectInfo - libgcc defines this struct as  
>>> km_object_info. It
>>> +/// probably contains all dwarf tables that are loaded.
>>> +struct LibgccObjectInfo {
>>> +
>>> +  /// seenObjects - LibgccObjects already parsed by the unwinding
>>> runtime.
>>> +  ///
>>> +  struct LibgccObject* seenObjects;
>>> +
>>> +  /// unseenObjects - LibgccObjects not parsed yet by the unwinding
>>> runtime.
>>> +  ///
>>> +  struct LibgccObject* unseenObjects;
>>> +
>>> +  unsigned unused[2];
>>> +};
>>> +
>>> +// for DW_EH_PE_omit
>>> +#include "llvm/Support/Dwarf.h"
>>> +
>>> +/// darwin_register_frame - Since __register_frame does not work
>>> with darwin's
>>> +/// libgcc,we provide our own function, which "tricks" libgcc by
>>> modifying the
>>> +/// "Dwarf2 object list" key.
>>> +void DarwinRegisterFrame(void* FrameBegin) {
>>> +  // Get the key.
>>> +  struct LibgccObjectInfo* LOI = (struct LibgccObjectInfo*)
>>> +    _keymgr_get_and_lock_processwide_ptr(KEYMGR_GCC3_DW2_OBJ_LIST);
>>> +
>>> +  // Allocate a new LibgccObject to represent this frame.
>>> Deallocation of this
>>> +  // object may be impossible: libgcc does not seem to deallocate
>>> it, even with
>>> +  // __deregister_frame. Deallocating it manually may also cause
>>> libgcc to
>>> +  // crash.
>>> +  struct LibgccObject* ob = (struct LibgccObject*)
>>> +    malloc(sizeof(struct LibgccObject));
>>> +
>>> +  // Do like libgcc for the values of the field.
>>> +  ob->unused1 = (void *)-1;
>>> +  ob->unused2 = 0;
>>> +  ob->unused3 = 0;
>>> +  ob->frame = FrameBegin;
>>> +  ob->encoding.i = 0;
>>> +  ob->encoding.b.encoding = llvm::dwarf::DW_EH_PE_omit;
>>> +
>>> +  // Put the info on both places, as libgcc uses the first or the
>>> the second
>>> +  // field. Note that we rely on having two pointers here. If
>>> fde_end was a
>>> +  // char, things would get complicated.
>>> +  ob->fde_end = (char*)LOI->unseenObjects;
>>> +  ob->next = LOI->unseenObjects;
>>> +
>>> +  // Update the key's unseenObjects list.
>>> +  LOI->unseenObjects = ob;
>>> +
>>> +  // Finally update the "key". Apparently, libgcc requires it.
>>> +  _keymgr_set_and_unlock_processwide_ptr(KEYMGR_GCC3_DW2_OBJ_LIST,
>>> +                                         LOI);
>>> +
>>> +}
>>> +
>>> +}
>>> +#endif // __APPLE__
>>> +#endif // __GNUC__
>>> +
>>> /// createJIT - This is the factory method for creating a JIT for  
>>> the
>>> current
>>> /// machine, it does not fall back to the interpreter.  This takes
>>> ownership
>>> /// of the module provider.
>>> @@ -108,8 +226,23 @@
>>>
>>>  // Register routine for informing unwinding runtime about new EH  
>>> frames
>>> #if defined(__GNUC__)
>>> +#if defined(__APPLE__)
>>> +  struct LibgccObjectInfo* LOI = (struct LibgccObjectInfo*)
>>> +    _keymgr_get_and_lock_processwide_ptr(KEYMGR_GCC3_DW2_OBJ_LIST);
>>> +
>>> +  // The key is created on demand, and libgcc creates it the first
>>> time an
>>> +  // exception occurs. Since we need the key to register frames, we
>>> create
>>> +  // it now.
>>> +  if (!LOI) {
>>> +    LOI = (LibgccObjectInfo*)malloc(sizeof(struct  
>>> LibgccObjectInfo));
>>> +     
>>> _keymgr_set_and_unlock_processwide_ptr(KEYMGR_GCC3_DW2_OBJ_LIST,
>>> +                                           LOI);
>>> +  }
>>> +  InstallExceptionTableRegister(DarwinRegisterFrame);
>>> +#else
>>>  InstallExceptionTableRegister(__register_frame);
>>> -#endif
>>> +#endif // __APPLE__
>>> +#endif // __GNUC__
>>>
>>>  // Initialize passes.
>>>  PM.doInitialization();
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu <mailto:llvm-commits at cs.uiuc.edu>
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>> ------------------------------------------------------------------------
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From evan.cheng at apple.com  Wed Aug 27 01:50:13 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 26 Aug 2008 23:50:13 -0700
Subject: [llvm-commits] [llvm] r55374 - in /llvm/trunk:
	lib/Transforms/Scalar/LoopStrengthReduce.cpp
	test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll
In-Reply-To: <200808261758.m7QHw5FM031611@zion.cs.uiuc.edu>
References: <200808261758.m7QHw5FM031611@zion.cs.uiuc.edu>
Message-ID: <C371F941-5CDC-48E6-97EB-93F5C9A558E4@apple.com>

Hi Devang,

Please avoid the transformation is the int-to-float type is not  
natively supported.

Thanks,

Evan

On Aug 26, 2008, at 10:58 AM, Devang Patel wrote:

> Author: dpatel
> Date: Tue Aug 26 12:57:54 2008
> New Revision: 55374
>
> URL: http://llvm.org/viewvc/llvm-project?rev=55374&view=rev
> Log:
> If IV is used in a int-to-float cast inside the loop then try to  
> eliminate the cast operation.
>
> Modified:
>    llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
>    llvm/trunk/test/Transforms/LoopStrengthReduce/2008-08-14- 
> ShadowIV.ll
>
> Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=55374&r1=55373&r2=55374&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
> +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Tue Aug  
> 26 12:57:54 2008
> @@ -45,6 +45,7 @@
> STATISTIC(NumInserted,    "Number of PHIs inserted");
> STATISTIC(NumVariable,    "Number of PHIs with variable strides");
> STATISTIC(NumEliminated , "Number of strides eliminated");
> +STATISTIC(NumShadow , "Number of Shadow IVs optimized");
>
> namespace {
>
> @@ -164,6 +165,7 @@
>       AU.addRequired<DominatorTree>();
>       AU.addRequired<TargetData>();
>       AU.addRequired<ScalarEvolution>();
> +      AU.addPreserved<ScalarEvolution>();
>     }
>
>     /// getCastedVersionOf - Return the specified value casted to  
> uintptr_t.
> @@ -177,8 +179,13 @@
>                                   IVStrideUse* &CondUse,
>                                   const SCEVHandle* &CondStride);
>     void OptimizeIndvars(Loop *L);
> +
> +    /// OptimizeShadowIV - If IV is used in a int-to-float cast
> +    /// inside the loop then try to eliminate the cast opeation.
> +    void OptimizeShadowIV(Loop *L);
> +
>     bool FindIVUserForCond(ICmpInst *Cond, IVStrideUse *&CondUse,
> -                       const SCEVHandle *&CondStride);
> +                           const SCEVHandle *&CondStride);
>     bool RequiresTypeConversion(const Type *Ty, const Type *NewTy);
>     unsigned CheckForIVReuse(bool, bool, const SCEVHandle&,
>                              IVExpr&, const Type*,
> @@ -1689,12 +1696,122 @@
>   return Cond;
> }
>
> +/// OptimizeShadowIV - If IV is used in a int-to-float cast
> +/// inside the loop then try to eliminate the cast opeation.
> +void LoopStrengthReduce::OptimizeShadowIV(Loop *L) {
> +
> +  SCEVHandle IterationCount = SE->getIterationCount(L);
> +  if (isa<SCEVCouldNotCompute>(IterationCount))
> +    return;
> +
> +  for (unsigned Stride = 0, e = StrideOrder.size(); Stride != e;
> +       ++Stride) {
> +    std::map<SCEVHandle, IVUsersOfOneStride>::iterator SI =
> +      IVUsesByStride.find(StrideOrder[Stride]);
> +    assert(SI != IVUsesByStride.end() && "Stride doesn't exist!");
> +    if (!isa<SCEVConstant>(SI->first))
> +      continue;
> +
> +    for (std::vector<IVStrideUse>::iterator UI = SI- 
> >second.Users.begin(),
> +           E = SI->second.Users.end(); UI != E; /* empty */) {
> +      std::vector<IVStrideUse>::iterator CandidateUI = UI;
> +      UI++;
> +      Instruction *ShadowUse = CandidateUI->User;
> +      const Type *DestTy = NULL;
> +
> +      /* If shadow use is a int->float cast then insert a second IV
> +         to elminate this cast.
> +
> +           for (unsigned i = 0; i < n; ++i)
> +             foo((double)i);
> +
> +         is trnasformed into
> +
> +           double d = 0.0;
> +           for (unsigned i = 0; i < n; ++i, ++d)
> +             foo(d);
> +      */
> +      UIToFPInst *UCast = dyn_cast<UIToFPInst>(CandidateUI->User);
> +      if (UCast)
> +        DestTy = UCast->getDestTy();
> +      else {
> +        SIToFPInst *SCast = dyn_cast<SIToFPInst>(CandidateUI->User);
> +        if (!SCast) continue;
> +        DestTy = SCast->getDestTy();
> +      }
> +
> +      PHINode *PH = dyn_cast<PHINode>(ShadowUse->getOperand(0));
> +      if (!PH) continue;
> +      if (PH->getNumIncomingValues() != 2) continue;
> +
> +      const Type *SrcTy = PH->getType();
> +      int Mantissa = DestTy->getFPMantissaWidth();
> +      if (Mantissa == -1) continue;
> +      if ((int)TD->getTypeSizeInBits(SrcTy) > Mantissa)
> +        continue;
> +
> +      unsigned Entry, Latch;
> +      if (PH->getIncomingBlock(0) == L->getLoopPreheader()) {
> +        Entry = 0;
> +        Latch = 1;
> +      } else {
> +        Entry = 1;
> +        Latch = 0;
> +      }
> +
> +      ConstantInt *Init = dyn_cast<ConstantInt>(PH- 
> >getIncomingValue(Entry));
> +      if (!Init) continue;
> +      ConstantFP *NewInit = ConstantFP::get(DestTy, Init- 
> >getZExtValue());
> +
> +      BinaryOperator *Incr =
> +        dyn_cast<BinaryOperator>(PH->getIncomingValue(Latch));
> +      if (!Incr) continue;
> +      if (Incr->getOpcode() != Instruction::Add
> +          && Incr->getOpcode() != Instruction::Sub)
> +        continue;
> +
> +      /* Initialize new IV, double d = 0.0 in above example. */
> +      ConstantInt *C = NULL;
> +      if (Incr->getOperand(0) == PH)
> +        C = dyn_cast<ConstantInt>(Incr->getOperand(1));
> +      else if (Incr->getOperand(1) == PH)
> +        C = dyn_cast<ConstantInt>(Incr->getOperand(0));
> +      else
> +        continue;
> +
> +      if (!C) continue;
> +
> +      /* Add new PHINode. */
> +      PHINode *NewPH = PHINode::Create(DestTy, "IV.S.", PH);
> +
> +      /* create new icnrement. '++d' in above example. */
> +      ConstantFP *CFP = ConstantFP::get(DestTy, C->getZExtValue());
> +      BinaryOperator *NewIncr =
> +        BinaryOperator::Create(Incr->getOpcode(),
> +                               NewPH, CFP, "IV.S.next.", Incr);
> +
> +      NewPH->addIncoming(NewInit, PH->getIncomingBlock(Entry));
> +      NewPH->addIncoming(NewIncr, PH->getIncomingBlock(Latch));
> +
> +      /* Remove cast operation */
> +      SE->deleteValueFromRecords(ShadowUse);
> +      ShadowUse->replaceAllUsesWith(NewPH);
> +      ShadowUse->eraseFromParent();
> +      SI->second.Users.erase(CandidateUI);
> +      NumShadow++;
> +      break;
> +    }
> +  }
> +}
> +
> // OptimizeIndvars - Now that IVUsesByStride is set up with all of  
> the indvar
> // uses in the loop, look to see if we can eliminate some, in favor  
> of using
> // common indvars for the different uses.
> void LoopStrengthReduce::OptimizeIndvars(Loop *L) {
>   // TODO: implement optzns here.
>
> +  OptimizeShadowIV(L);
> +
>   // Finally, get the terminating condition for the loop if  
> possible.  If we
>   // can, we want to change it to use a post-incremented version of  
> its
>   // induction variable, to allow coalescing the live ranges for the  
> IV into
> @@ -1852,6 +1969,5 @@
>     }
>     DeleteTriviallyDeadInstructions(DeadInsts);
>   }
> -
>   return Changed;
> }
>
> Modified: llvm/trunk/test/Transforms/LoopStrengthReduce/2008-08-14- 
> ShadowIV.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll?rev=55374&r1=55373&r2=55374&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/Transforms/LoopStrengthReduce/2008-08-14- 
> ShadowIV.ll (original)
> +++ llvm/trunk/test/Transforms/LoopStrengthReduce/2008-08-14- 
> ShadowIV.ll Tue Aug 26 12:57:54 2008
> @@ -1,5 +1,4 @@
> ; RUN: llvm-as < %s | opt -loop-reduce | llvm-dis | grep "phi  
> double" | count 1
> -; XFAIL: *
>
> define void @foobar(i32 %n) nounwind {
> entry:
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From evan.cheng at apple.com  Wed Aug 27 01:51:15 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 27 Aug 2008 06:51:15 -0000
Subject: [llvm-commits] [llvm] r55409 - in /llvm/trunk:
 include/llvm/Support/DebugInfoBuilder.h lib/VMCore/DebugInfoBuilder.cpp
Message-ID: <200808270651.m7R6pFf1026223@zion.cs.uiuc.edu>

Author: evancheng
Date: Wed Aug 27 01:51:14 2008
New Revision: 55409

URL: http://llvm.org/viewvc/llvm-project?rev=55409&view=rev
Log:
Add DebugInfoBuilder. Patch by Talin!

Added:
    llvm/trunk/include/llvm/Support/DebugInfoBuilder.h
    llvm/trunk/lib/VMCore/DebugInfoBuilder.cpp

Added: llvm/trunk/include/llvm/Support/DebugInfoBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/DebugInfoBuilder.h?rev=55409&view=auto

==============================================================================
--- llvm/trunk/include/llvm/Support/DebugInfoBuilder.h (added)
+++ llvm/trunk/include/llvm/Support/DebugInfoBuilder.h Wed Aug 27 01:51:14 2008
@@ -0,0 +1,151 @@
+//===-- llvm/Support/DebugInfoBuilder.h - -----------------------*- C++ -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+//
+// This file contains the declaration of the DebugInfoBuilder class, which is
+// a helper class used to construct source level debugging information.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_SUPPORT_DEBUGINFOBUILDER_H
+#define LLVM_SUPPORT_DEBUGINFOBUILDER_H
+
+#include <llvm/Module.h>
+#include <string>
+
+namespace llvm {
+    
+class Type;
+class IntegerType;
+class FloatType;
+class StructType;
+class PointerType;
+class Module;
+class GlobalVariable;
+class Constant;
+
+namespace sys {
+    class Path;
+}
+
+/// Helper class used to construct source-level debugging information.
+///
+/// The helper contains a notion of "current context", which is a
+/// DWARF descriptor object representing the scope (module, class,
+/// function, etc.) that currently encloses the definitions being
+/// emitted.
+///
+/// Initially, you should call setModule() to specify the target
+/// module. Descriptors which are generated will be inserted into
+/// this module. This also generates the initial set of anchor
+/// descriptors, if they have not already been created for the module.
+///
+/// Next, you should call createCompileUnitDescriptor() to create
+/// the descriptor for the current compilation unit. This method
+/// sets the current context to the newly created descriptor.
+///
+/// Once that has been done, you can then create descriptors for
+/// global definitions (functions, variables, etc.). You can use
+/// setContext() to modify the current context. setContext() returns
+/// a reference to the previous context, allowing easy restoration
+/// of the previous context.
+class DebugInfoBuilder {
+private:
+    Module * module;
+    PointerType * anyPtrType;    // Pointer to empty struct
+    StructType * anchorType;
+    GlobalVariable * compileUnit;
+    GlobalVariable * context;
+    GlobalVariable * compileUnitAnchor;
+    GlobalVariable * globalVariableAnchor;
+    GlobalVariable * subprogramAnchor;
+    GlobalVariable * compileUnitDescriptor;
+
+    // Create an anchor with the specified tag.
+    GlobalVariable * createAnchor(unsigned anchorTag, const char * anchorName);
+
+    // Calculate alignement for primitive types.
+    unsigned getBasicAlignment(unsigned sizeInBits);
+
+    // Calculate the size of the specified LLVM type.
+    Constant * getSize(const Type * type);
+
+    // Calculate the alignment of the specified LLVM type.
+    Constant * getAlignment(const Type * type);
+
+public:
+    /// Constructor
+    DebugInfoBuilder();
+
+    /// Return the type defined by llvm.dbg.anchor.type
+    StructType * getAnchorType() const { return anchorType; }
+    
+    /// Set the reference to the module where we will insert debugging
+    /// information. Also defines the debug info types for the module and
+    /// creates the initial anchors. Also changes the current context to the
+    // global context for that module.
+    void setModule(Module * m);
+    
+    /// Emit a compile unit descriptor. This should be done once for each
+    /// module before any other debug descriptors are created. This also
+    /// changes the current context to the global context for the compile unit.
+    GlobalVariable * createCompileUnitDescriptor(
+        unsigned langId,
+        const sys::Path & srcPath,
+        const std::string & producer);
+
+    /// Set a new context, returning the previous context. The context is the
+    /// debug descriptor representing the current scope (module, function,
+    /// class, etc.)
+    GlobalVariable * setContext(GlobalVariable * ctx) {
+        GlobalVariable * prev = context;
+        context = ctx;
+        return prev;
+    }
+    
+    /// Emit a subprogram descriptor in the current context.
+    GlobalVariable * createSubProgramDescriptor(
+        const std::string & name,       // Name of the subprogram
+        const std::string & qualName,   // Fully-qualified name
+        unsigned line,                  // Line number
+        GlobalVariable * typeDesc,      // Type descriptor
+        bool isInternalScoped,          // True if internal to module.
+        bool isDefined);                // True if defined in this module.
+
+    /// Create a type descriptor for a primitive type.
+    GlobalVariable * createBasicTypeDescriptor(
+        std::string & name,
+        unsigned line,
+        unsigned sizeInBits,
+        unsigned alignmentInBits,
+        unsigned offsetInBits,
+        unsigned typeEncoding);
+
+    /// Create a type descriptor for an integer type
+    GlobalVariable * createIntegerTypeDescriptor(
+        std::string & name, const IntegerType * type, bool isSigned);
+
+    /// Create a type descriptor for an character type
+    GlobalVariable * createCharacterTypeDescriptor(
+        std::string & name, const IntegerType * type, bool isSigned);
+
+    /// Create a type descriptor for an floating-point type
+    GlobalVariable * createFloatTypeDescriptor(std::string & name,
+        const Type * type);
+
+    /// Create a type descriptor for a pointer type.
+    GlobalVariable * createPointerTypeDescriptor(
+        std::string & name,             // Name of the type
+        GlobalVariable * referenceType, // Descriptor for what is pointed to
+        const PointerType * type,       // LLVM type of the pointer
+        unsigned line);                 // Line number of definition (0 if none)
+};
+
+}
+
+#endif

Added: llvm/trunk/lib/VMCore/DebugInfoBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/DebugInfoBuilder.cpp?rev=55409&view=auto

==============================================================================
--- llvm/trunk/lib/VMCore/DebugInfoBuilder.cpp (added)
+++ llvm/trunk/lib/VMCore/DebugInfoBuilder.cpp Wed Aug 27 01:51:14 2008
@@ -0,0 +1,272 @@
+//===-- llvm/VMCore/DebugInfoBuilder.cpp - ----------------------*- C++ -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+//
+// This file contains the definition of the DebugInfoBuilder class, which is
+// a helper class used to construct source level debugging information.
+//
+//===----------------------------------------------------------------------===//
+
+#include <llvm/Support/DebugInfoBuilder.h>
+#include <llvm/DerivedTypes.h>
+#include <llvm/Constants.h>
+#include <llvm/GlobalVariable.h>
+#include <llvm/Module.h>
+#include <llvm/Support/Dwarf.h>
+#include <llvm/System/Path.h>
+
+namespace llvm {
+    
+//===----------------------------------------------------------------------===//
+// Debug version -- copied from MachineModuleInfo (for now), in order to avoid
+// creating a dependency on CodeGen. These declarations really should be moved
+// to a better place where modules can get at them without being dependent on
+// CodeGen.
+enum {
+  LLVMDebugVersion = (6 << 16),         // Current version of debug information.
+  LLVMDebugVersion5 = (5 << 16),        // Constant for version 5.
+  LLVMDebugVersion4 = (4 << 16),        // Constant for version 4.
+  LLVMDebugVersionMask = 0xffff0000     // Mask for version number.
+};
+
+const char ANCHOR_TYPE_NAME[] = "llvm.dbg.anchor.type";
+const char COMPILE_UNIT_ANCHOR_NAME[] = "llvm.dbg.compile_units";
+const char GLOBAL_VAR_ANCHOR_NAME[] = "llvm.dbg.global_variables";
+const char SUBPROGRAM_ANCHOR_NAME[] = "llvm.dbg.subprograms";
+const char COMPILE_UNIT_TYPE_NAME[] = "llvm.dbg.compile_unit.type";
+const char COMPILE_UNIT_NAME[] = "llvm.dbg.compile_unit";
+const char SUBPROGRAM_NAME[] = "llvm.dbg.subprogram";
+const char BASICTYPE_NAME[] = "llvm.dbg.basictype";
+const char DERIVEDTYPE_NAME[] = "llvm.dbg.derivedtype";
+
+DebugInfoBuilder::DebugInfoBuilder() {
+    anyPtrType = PointerType::getUnqual(StructType::get(NULL, NULL));
+    anchorType = StructType::get(Type::Int32Ty, Type::Int32Ty, NULL);
+}
+
+GlobalVariable * DebugInfoBuilder::createAnchor(unsigned anchorTag,
+    const char * anchorName) {
+
+    std::vector<Constant *> values;
+    values.push_back(ConstantInt::get(Type::Int32Ty, LLVMDebugVersion));
+    values.push_back(ConstantInt::get(Type::Int32Ty, anchorTag));
+    
+    return new GlobalVariable(anchorType, true, GlobalValue::LinkOnceLinkage,
+        ConstantStruct::get(anchorType, values), anchorName, module);
+}
+
+// Calculate the size of the specified LLVM type.
+Constant * DebugInfoBuilder::getSize(const Type * type) {
+    Constant * one = ConstantInt::get(Type::Int32Ty, 1);
+    return ConstantExpr::getPtrToInt(
+        ConstantExpr::getGetElementPtr(
+            ConstantPointerNull::get(PointerType::getUnqual(type)),
+            &one, 1), Type::Int32Ty);
+}
+    
+Constant * DebugInfoBuilder::getAlignment(const Type * type) {
+    // Calculates the alignment of T using "sizeof({i8, T}) - sizeof(T)"
+    return ConstantExpr::getSub(
+        getSize(StructType::get(Type::Int8Ty, type, NULL)),
+        getSize(type));
+}
+    
+void DebugInfoBuilder::setModule(Module * m) {
+    module = m;
+    module->addTypeName(ANCHOR_TYPE_NAME, anchorType);
+    
+    compileUnitAnchor = module->getGlobalVariable(COMPILE_UNIT_ANCHOR_NAME);
+    if (compileUnitAnchor == NULL) {
+        compileUnitAnchor =
+            createAnchor(dwarf::DW_TAG_compile_unit, COMPILE_UNIT_ANCHOR_NAME);
+    }
+
+    globalVariableAnchor = module->getGlobalVariable(GLOBAL_VAR_ANCHOR_NAME);
+    if (globalVariableAnchor == NULL) {
+        globalVariableAnchor =
+            createAnchor(dwarf::DW_TAG_compile_unit, GLOBAL_VAR_ANCHOR_NAME);
+    }
+
+    subprogramAnchor = module->getGlobalVariable(SUBPROGRAM_ANCHOR_NAME);
+    if (subprogramAnchor == NULL) {
+        subprogramAnchor =
+            createAnchor(dwarf::DW_TAG_compile_unit, SUBPROGRAM_ANCHOR_NAME);
+    }
+    
+    compileUnit = module->getGlobalVariable(COMPILE_UNIT_NAME);
+    setContext(compileUnit);
+}
+    
+GlobalVariable * DebugInfoBuilder::createCompileUnitDescriptor(unsigned langId,
+    const sys::Path & srcPath, const std::string & producer) {
+
+    if (compileUnit == NULL) {
+        std::vector<Constant *> values;
+        values.push_back(ConstantInt::get(
+            Type::Int32Ty, LLVMDebugVersion + dwarf::DW_TAG_compile_unit));
+        values.push_back(
+            ConstantExpr::getBitCast(compileUnitAnchor, anyPtrType));
+        values.push_back(ConstantInt::get(Type::Int32Ty, langId));
+        values.push_back(ConstantArray::get(srcPath.getLast()));
+        values.push_back(ConstantArray::get(srcPath.getDirname() + "/"));
+        values.push_back(ConstantArray::get(producer));
+    
+        Constant * structVal = ConstantStruct::get(values, false);
+        compileUnit = new GlobalVariable(structVal->getType(), true,
+            GlobalValue::InternalLinkage, structVal, COMPILE_UNIT_NAME, module);
+    }
+
+    setContext(compileUnit);
+    return compileUnit;
+}
+
+GlobalVariable * DebugInfoBuilder::createSubProgramDescriptor(
+    const std::string & name,
+    const std::string & qualifiedName,
+    unsigned line,
+    GlobalVariable * typeDesc,
+    bool isInternal,
+    bool isDefined) {
+        
+    assert(compileUnit != NULL);
+    assert(subprogramAnchor != NULL);
+        
+    std::vector<Constant *> values;
+    values.push_back(ConstantInt::get(
+        Type::Int32Ty, LLVMDebugVersion + dwarf::DW_TAG_subprogram));
+    values.push_back(ConstantExpr::getBitCast(subprogramAnchor, anyPtrType));
+    values.push_back(ConstantExpr::getBitCast(context, anyPtrType));
+    values.push_back(ConstantArray::get(name));
+    values.push_back(ConstantArray::get(qualifiedName));
+    values.push_back(ConstantArray::get(qualifiedName));
+    values.push_back(ConstantExpr::getBitCast(compileUnit, anyPtrType));
+    values.push_back(ConstantInt::get(Type::Int32Ty, line));
+    values.push_back(typeDesc ?
+        ConstantExpr::getBitCast(typeDesc, anyPtrType) :
+        ConstantPointerNull::get(anyPtrType));
+    values.push_back(ConstantInt::get(Type::Int1Ty, isInternal));
+    values.push_back(ConstantInt::get(Type::Int1Ty, isDefined));
+    
+    Constant * structVal = ConstantStruct::get(values, false);
+    return new GlobalVariable(structVal->getType(), true,
+        GlobalValue::InternalLinkage, structVal, SUBPROGRAM_NAME, module);
+}
+
+GlobalVariable * DebugInfoBuilder::createBasicTypeDescriptor(
+    std::string & name,
+    unsigned line,
+    unsigned sizeInBits,
+    unsigned alignmentInBits,
+    unsigned offsetInBits,
+    unsigned typeEncoding) {
+
+    std::vector<Constant *> values;
+    values.push_back(ConstantInt::get(
+        Type::Int32Ty, LLVMDebugVersion + dwarf::DW_TAG_base_type));
+    values.push_back(ConstantExpr::getBitCast(context, anyPtrType));
+    values.push_back(ConstantArray::get(name));
+    values.push_back(ConstantExpr::getBitCast(compileUnit, anyPtrType));
+    values.push_back(ConstantInt::get(Type::Int32Ty, line));
+    values.push_back(ConstantInt::get(Type::Int32Ty, sizeInBits));
+    values.push_back(ConstantInt::get(Type::Int32Ty, alignmentInBits));
+    values.push_back(ConstantInt::get(Type::Int32Ty, offsetInBits));
+    values.push_back(ConstantInt::get(Type::Int32Ty, typeEncoding));
+
+    Constant * structVal = ConstantStruct::get(values, false);
+    return new GlobalVariable(structVal->getType(), true,
+        GlobalValue::InternalLinkage, structVal, BASICTYPE_NAME, module);
+}
+
+GlobalVariable * DebugInfoBuilder::createIntegerTypeDescriptor(
+    std::string & name, const IntegerType * type, bool isSigned) {
+
+    std::vector<Constant *> values;
+    values.push_back(ConstantInt::get(
+        Type::Int32Ty, LLVMDebugVersion + dwarf::DW_TAG_base_type));
+    values.push_back(ConstantPointerNull::get(anyPtrType));
+    values.push_back(ConstantArray::get(name));
+    values.push_back(ConstantPointerNull::get(anyPtrType));
+    values.push_back(ConstantInt::get(Type::Int32Ty, 0));
+    values.push_back(ConstantInt::get(Type::Int32Ty, type->getBitWidth()));
+    values.push_back(getAlignment(type));
+    values.push_back(ConstantInt::get(Type::Int32Ty, 0));
+    values.push_back(ConstantInt::get(Type::Int32Ty,
+        isSigned ? dwarf::DW_ATE_signed_char : dwarf::DW_ATE_unsigned_char));
+
+    Constant * structVal = ConstantStruct::get(values, false);
+    return new GlobalVariable(structVal->getType(), true,
+        GlobalValue::InternalLinkage, structVal, BASICTYPE_NAME, module);
+}
+
+GlobalVariable * DebugInfoBuilder::createCharacterTypeDescriptor(
+    std::string & name, const IntegerType * type, bool isSigned) {
+
+    std::vector<Constant *> values;
+    values.push_back(ConstantInt::get(
+        Type::Int32Ty, LLVMDebugVersion + dwarf::DW_TAG_base_type));
+    values.push_back(ConstantPointerNull::get(anyPtrType));
+    values.push_back(ConstantArray::get(name));
+    values.push_back(ConstantPointerNull::get(anyPtrType));
+    values.push_back(ConstantInt::get(Type::Int32Ty, 0));
+    values.push_back(ConstantInt::get(Type::Int32Ty, type->getBitWidth()));
+    values.push_back(getAlignment(type));
+    values.push_back(ConstantInt::get(Type::Int32Ty, 0/*offsetInBits*/));
+    values.push_back(ConstantInt::get(Type::Int32Ty,
+        isSigned ? dwarf::DW_ATE_signed_char : dwarf::DW_ATE_unsigned_char));
+
+    Constant * structVal = ConstantStruct::get(values, false);
+    return new GlobalVariable(structVal->getType(), true,
+        GlobalValue::InternalLinkage, structVal, BASICTYPE_NAME, module);
+}
+
+GlobalVariable * DebugInfoBuilder::createFloatTypeDescriptor(
+    std::string & name, const Type * type) {
+
+    std::vector<Constant *> values;
+    values.push_back(ConstantInt::get(
+        Type::Int32Ty, LLVMDebugVersion + dwarf::DW_TAG_base_type));
+    values.push_back(ConstantPointerNull::get(anyPtrType));
+    values.push_back(ConstantArray::get(name));
+    values.push_back(ConstantPointerNull::get(anyPtrType));
+    values.push_back(ConstantInt::get(Type::Int32Ty, 0));
+    values.push_back(getSize(type));
+    values.push_back(getAlignment(type));
+    values.push_back(ConstantInt::get(Type::Int32Ty, 0/*offsetInBits*/));
+    values.push_back(ConstantInt::get(Type::Int32Ty, dwarf::DW_ATE_float));
+
+    Constant * structVal = ConstantStruct::get(values, false);
+    return new GlobalVariable(structVal->getType(), true,
+        GlobalValue::InternalLinkage, structVal, BASICTYPE_NAME, module);
+}
+
+GlobalVariable * DebugInfoBuilder::createPointerTypeDescriptor(
+    std::string & name,
+    GlobalVariable * referenceType,
+    const PointerType * type,
+    unsigned line) {
+
+    std::vector<Constant *> values;
+    values.push_back(ConstantInt::get(
+        Type::Int32Ty, dwarf::DW_TAG_pointer_type + LLVMDebugVersion));
+    values.push_back(
+        context ? ConstantExpr::getBitCast(context, anyPtrType) : NULL);
+    values.push_back(ConstantArray::get(name));
+    values.push_back(
+        compileUnit ? ConstantExpr::getBitCast(compileUnit, anyPtrType) : NULL);
+    values.push_back(ConstantInt::get(Type::Int32Ty, line));
+    values.push_back(getSize(type));
+    values.push_back(getAlignment(type));
+    values.push_back(ConstantInt::get(Type::Int32Ty, 0));
+    values.push_back(referenceType);
+
+    Constant * structVal = ConstantStruct::get(values, false);
+    return new GlobalVariable(structVal->getType(), true,
+        GlobalValue::InternalLinkage, structVal, DERIVEDTYPE_NAME, module);
+}
+
+}




From evan.cheng at apple.com  Wed Aug 27 01:51:24 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 26 Aug 2008 23:51:24 -0700
Subject: [llvm-commits] DebugInfoBuilder - revised
In-Reply-To: <d1b71f830808261523t198e87ffw18a04ed616ebae08@mail.gmail.com>
References: <d1b71f830808261523t198e87ffw18a04ed616ebae08@mail.gmail.com>
Message-ID: <D0E6C16B-3D6B-4EC4-803D-E86C0819BB3C@apple.com>

Committed. Thanks!

Evan
On Aug 26, 2008, at 3:23 PM, Talin wrote:

> Here's the latest version of the patch.
>
> (Sorry for not replying to the previous message, it seems to have  
> gotten deleted from my mail prog.)
>
> -- 
> -- Talin
> <DIB.patch>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From gohman at apple.com  Wed Aug 27 09:44:58 2008
From: gohman at apple.com (Dan Gohman)
Date: Wed, 27 Aug 2008 14:44:58 -0000
Subject: [llvm-commits] [llvm] r55413 - /llvm/trunk/lib/VMCore/Verifier.cpp
Message-ID: <200808271444.m7REixHp023492@zion.cs.uiuc.edu>

Author: djg
Date: Wed Aug 27 09:44:57 2008
New Revision: 55413

URL: http://llvm.org/viewvc/llvm-project?rev=55413&view=rev
Log:
Update wording, as aggregates are now first-class.

Modified:
    llvm/trunk/lib/VMCore/Verifier.cpp

Modified: llvm/trunk/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=55413&r1=55412&r2=55413&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/Verifier.cpp (original)
+++ llvm/trunk/lib/VMCore/Verifier.cpp Wed Aug 27 09:44:57 2008
@@ -505,10 +505,9 @@
     Assert2(I->getType() == FT->getParamType(i),
             "Argument value does not match function argument type!",
             I, FT->getParamType(i));
-    // Make sure no aggregates are passed by value.
     Assert1(I->getType()->isFirstClassType(),
-            "Functions cannot take aggregates as arguments by value!", I);
-   }
+            "Function arguments must have first-class types!", I);
+  }
 
   if (F.isDeclaration()) {
     Assert1(F.hasExternalLinkage() || F.hasDLLImportLinkage() ||




From gohman at apple.com  Wed Aug 27 09:48:06 2008
From: gohman at apple.com (Dan Gohman)
Date: Wed, 27 Aug 2008 14:48:06 -0000
Subject: [llvm-commits] [llvm] r55414 - in /llvm/trunk:
 lib/VMCore/Verifier.cpp test/Verifier/byval-2.ll
Message-ID: <200808271448.m7REm6IJ023628@zion.cs.uiuc.edu>

Author: djg
Date: Wed Aug 27 09:48:06 2008
New Revision: 55414

URL: http://llvm.org/viewvc/llvm-project?rev=55414&view=rev
Log:
Diagnose uses of unsized types with the byval attribute in the
verifier. See PR2711 for details.

Modified:
    llvm/trunk/lib/VMCore/Verifier.cpp
    llvm/trunk/test/Verifier/byval-2.ll

Modified: llvm/trunk/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=55414&r1=55413&r2=55414&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/Verifier.cpp (original)
+++ llvm/trunk/lib/VMCore/Verifier.cpp Wed Aug 27 09:48:06 2008
@@ -421,6 +421,17 @@
   ParameterAttributes TypeI = Attrs & ParamAttr::typeIncompatible(Ty);
   Assert1(!TypeI, "Wrong type for attribute " +
           ParamAttr::getAsString(TypeI), V);
+
+  ParameterAttributes ByValI = Attrs & ParamAttr::ByVal;
+  if (const PointerType *PTy = dyn_cast<PointerType>(Ty)) {
+    Assert1(!ByValI || PTy->getElementType()->isSized(),
+            "Attribute " + ParamAttr::getAsString(ByValI) +
+            " does not support unsized types!", V);
+  } else {
+    Assert1(!ByValI,
+            "Attribute " + ParamAttr::getAsString(ByValI) +
+            " only applies to parameters with pointer type!", V);
+  }
 }
 
 // VerifyFunctionAttrs - Check parameter attributes against a function type.

Modified: llvm/trunk/test/Verifier/byval-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Verifier/byval-2.ll?rev=55414&r1=55413&r2=55414&view=diff

==============================================================================
--- llvm/trunk/test/Verifier/byval-2.ll (original)
+++ llvm/trunk/test/Verifier/byval-2.ll Wed Aug 27 09:48:06 2008
@@ -1,3 +1,4 @@
-; RUN: llvm-as %s -o /dev/null -f
+; RUN: not llvm-as < %s >& /dev/null
+; PR2711
 	%s = type opaque
 declare void @h(%s* byval %num)




From gohman at apple.com  Wed Aug 27 10:24:44 2008
From: gohman at apple.com (Dan Gohman)
Date: Wed, 27 Aug 2008 15:24:44 -0000
Subject: [llvm-commits] [llvm] r55415 -
	/llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h
Message-ID: <200808271524.m7RFOjId024882@zion.cs.uiuc.edu>

Author: djg
Date: Wed Aug 27 10:24:43 2008
New Revision: 55415

URL: http://llvm.org/viewvc/llvm-project?rev=55415&view=rev
Log:
Unbreak PseudoSourceValue::print. This fixes -print-machine-instrs
and various other things.

Modified:
    llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h

Modified: llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h?rev=55415&r1=55414&r2=55415&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h (original)
+++ llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h Wed Aug 27 10:24:43 2008
@@ -28,7 +28,7 @@
   public:
     PseudoSourceValue();
 
-    void print(raw_ostream &OS) const;
+    virtual void print(raw_ostream &OS) const;
 
     /// isConstant - Test whether this PseudoSourceValue has a constant value.
     ///




From gohman at apple.com  Wed Aug 27 11:18:28 2008
From: gohman at apple.com (Dan Gohman)
Date: Wed, 27 Aug 2008 16:18:28 -0000
Subject: [llvm-commits] [llvm] r55418 -
	/llvm/trunk/utils/TableGen/FastISelEmitter.cpp
Message-ID: <200808271618.m7RGITlE027015@zion.cs.uiuc.edu>

Author: djg
Date: Wed Aug 27 11:18:22 2008
New Revision: 55418

URL: http://llvm.org/viewvc/llvm-project?rev=55418&view=rev
Log:
Update a comment to reflect recent changes.

Modified:
    llvm/trunk/utils/TableGen/FastISelEmitter.cpp

Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=55418&r1=55417&r2=55418&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Wed Aug 27 11:18:22 2008
@@ -96,7 +96,7 @@
           Operands.push_back("f");
           return true;
         }
-        // For now, ignore fpimm and other non-leaf nodes.
+        // For now, ignore other non-leaf nodes.
         return false;
       }
       DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());




From gohman at apple.com  Wed Aug 27 11:19:44 2008
From: gohman at apple.com (Dan Gohman)
Date: Wed, 27 Aug 2008 16:19:44 -0000
Subject: [llvm-commits] [llvm] r55419 -
	/llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp
Message-ID: <200808271619.m7RGJi75027082@zion.cs.uiuc.edu>

Author: djg
Date: Wed Aug 27 11:19:44 2008
New Revision: 55419

URL: http://llvm.org/viewvc/llvm-project?rev=55419&view=rev
Log:
Remove the std::ostream form of PseudoSourceValue's print,
which isn't needed anymore.

Modified:
    llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp

Modified: llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp?rev=55419&r1=55418&r2=55419&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp (original)
+++ llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp Wed Aug 27 11:19:44 2008
@@ -57,9 +57,6 @@
 
     virtual bool isConstant(const MachineFrameInfo *MFI) const;
 
-    virtual void print(std::ostream &OS) const {
-      OS << "FixedStack" << FI;
-    }
     virtual void print(raw_ostream &OS) const {
       OS << "FixedStack" << FI;
     }




From gohman at apple.com  Wed Aug 27 11:27:26 2008
From: gohman at apple.com (Dan Gohman)
Date: Wed, 27 Aug 2008 16:27:26 -0000
Subject: [llvm-commits] [llvm] r55420 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
Message-ID: <200808271627.m7RGRQqu027398@zion.cs.uiuc.edu>

Author: djg
Date: Wed Aug 27 11:27:25 2008
New Revision: 55420

URL: http://llvm.org/viewvc/llvm-project?rev=55420&view=rev
Log:
Optimize ScheduleDAG's ComputeDepths and ComputeHeights to not need
a scratch std::vector.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=55420&r1=55419&r2=55420&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Wed Aug 27 11:27:25 2008
@@ -250,17 +250,15 @@
 /// paths in the DAG
 void ScheduleDAG::CalculateDepths() {
   unsigned DAGSize = SUnits.size();
-  std::vector<unsigned> InDegree(DAGSize);
   std::vector<SUnit*> WorkList;
   WorkList.reserve(DAGSize);
 
   // Initialize the data structures
   for (unsigned i = 0, e = DAGSize; i != e; ++i) {
     SUnit *SU = &SUnits[i];
-    int NodeNum = SU->NodeNum;
     unsigned Degree = SU->Preds.size();
-    InDegree[NodeNum] = Degree;
-    SU->Depth = 0;
+    // Temporarily use the Depth field as scratch space for the degree count.
+    SU->Depth = Degree;
 
     // Is it a node without dependencies?
     if (Degree == 0) {
@@ -274,7 +272,7 @@
   while (!WorkList.empty()) {
     SUnit *SU = WorkList.back();
     WorkList.pop_back();
-    unsigned &SUDepth  = SU->Depth;
+    unsigned SUDepth = 0;
 
     // Use dynamic programming:
     // When current node is being processed, all of its dependencies
@@ -288,11 +286,13 @@
       }
     }
 
-    // Update InDegrees of all nodes depending on current SUnit
+    SU->Depth = SUDepth;
+
+    // Update degrees of all nodes depending on current SUnit
     for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
          I != E; ++I) {
       SUnit *SU = I->Dep;
-      if (!--InDegree[SU->NodeNum])
+      if (!--SU->Depth)
         // If all dependencies of the node are processed already,
         // then the longest path for the node can be computed now
         WorkList.push_back(SU);
@@ -304,17 +304,15 @@
 /// paths in the DAG
 void ScheduleDAG::CalculateHeights() {
   unsigned DAGSize = SUnits.size();
-  std::vector<unsigned> InDegree(DAGSize);
   std::vector<SUnit*> WorkList;
   WorkList.reserve(DAGSize);
 
   // Initialize the data structures
   for (unsigned i = 0, e = DAGSize; i != e; ++i) {
     SUnit *SU = &SUnits[i];
-    int NodeNum = SU->NodeNum;
     unsigned Degree = SU->Succs.size();
-    InDegree[NodeNum] = Degree;
-    SU->Height = 0;
+    // Temporarily use the Height field as scratch space for the degree count.
+    SU->Height = Degree;
 
     // Is it a node without dependencies?
     if (Degree == 0) {
@@ -329,7 +327,7 @@
   while (!WorkList.empty()) {
     SUnit *SU = WorkList.back();
     WorkList.pop_back();
-    unsigned &SUHeight  = SU->Height;
+    unsigned SUHeight = 0;
 
     // Use dynamic programming:
     // When current node is being processed, all of its dependencies
@@ -343,11 +341,13 @@
       }
     }
 
-    // Update InDegrees of all nodes depending on current SUnit
+    SU->Height = SUHeight;
+
+    // Update degrees of all nodes depending on current SUnit
     for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
          I != E; ++I) {
       SUnit *SU = I->Dep;
-      if (!--InDegree[SU->NodeNum])
+      if (!--SU->Height)
         // If all dependencies of the node are processed already,
         // then the longest path for the node can be computed now
         WorkList.push_back(SU);




From gohman at apple.com  Wed Aug 27 11:29:48 2008
From: gohman at apple.com (Dan Gohman)
Date: Wed, 27 Aug 2008 16:29:48 -0000
Subject: [llvm-commits] [llvm] r55421 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Message-ID: <200808271629.m7RGTmFO027475@zion.cs.uiuc.edu>

Author: djg
Date: Wed Aug 27 11:29:48 2008
New Revision: 55421

URL: http://llvm.org/viewvc/llvm-project?rev=55421&view=rev
Log:
Optimize ScheduleDAGRRList's topological sort to use one pass instead
of two, and to not need a scratch std::vector. Also, compute the ordering
immediately in the result array, instead of in another scratch std::vector
that is copied to the result array.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=55421&r1=55420&r2=55421&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Aug 27 11:29:48 2008
@@ -448,18 +448,19 @@
 /// immediately after X in Index2Node.
 void ScheduleDAGRRList::InitDAGTopologicalSorting() {
   unsigned DAGSize = SUnits.size();
-  std::vector<unsigned> InDegree(DAGSize);
   std::vector<SUnit*> WorkList;
   WorkList.reserve(DAGSize);
-  std::vector<SUnit*> TopOrder;
-  TopOrder.reserve(DAGSize);
+
+  Index2Node.resize(DAGSize);
+  Node2Index.resize(DAGSize);
 
   // Initialize the data structures.
   for (unsigned i = 0, e = DAGSize; i != e; ++i) {
     SUnit *SU = &SUnits[i];
     int NodeNum = SU->NodeNum;
     unsigned Degree = SU->Succs.size();
-    InDegree[NodeNum] = Degree;
+    // Temporarily use the Node2Index array as scratch space for degree counts.
+    Node2Index[NodeNum] = Degree;
 
     // Is it a node without dependencies?
     if (Degree == 0) {
@@ -469,35 +470,23 @@
     }
   }  
 
+  int Id = DAGSize;
   while (!WorkList.empty()) {
     SUnit *SU = WorkList.back();
     WorkList.pop_back();
-    TopOrder.push_back(SU);
+    Allocate(SU->NodeNum, --Id);
     for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
          I != E; ++I) {
       SUnit *SU = I->Dep;
-      if (!--InDegree[SU->NodeNum])
+      if (!--Node2Index[SU->NodeNum])
         // If all dependencies of the node are processed already,
         // then the node can be computed now.
         WorkList.push_back(SU);
     }
   }
 
-  // Second pass, assign the actual topological order as node ids.
-  int Id = 0;
-
-  Index2Node.clear();
-  Node2Index.clear();
-  Index2Node.resize(DAGSize);
-  Node2Index.resize(DAGSize);
   Visited.resize(DAGSize);
 
-  for (std::vector<SUnit*>::reverse_iterator TI = TopOrder.rbegin(),
-       TE = TopOrder.rend();TI != TE; ++TI) {
-    Allocate((*TI)->NodeNum, Id);
-    Id++;
-  }
-
 #ifndef NDEBUG
   // Check correctness of the ordering
   for (unsigned i = 0, e = DAGSize; i != e; ++i) {




From gohman at apple.com  Wed Aug 27 12:33:15 2008
From: gohman at apple.com (Dan Gohman)
Date: Wed, 27 Aug 2008 17:33:15 -0000
Subject: [llvm-commits] [llvm] r55422 -
	/llvm/trunk/lib/Target/X86/X86Instr64bit.td
Message-ID: <200808271733.m7RHXG9S029554@zion.cs.uiuc.edu>

Author: djg
Date: Wed Aug 27 12:33:15 2008
New Revision: 55422

URL: http://llvm.org/viewvc/llvm-project?rev=55422&view=rev
Log:
Reinstate the x86-64 portion of r55190. When doing extloads into
64-bit registers from 16-bit and smaller memory locations, prefer
instructions that define the entire 64-bit register, to avoid
partial-register updates.

Modified:
    llvm/trunk/lib/Target/X86/X86Instr64bit.td

Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=55422&r1=55421&r2=55422&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Wed Aug 27 12:33:15 2008
@@ -1254,15 +1254,14 @@
 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
 
 // extload
-def : Pat<(extloadi64i1 addr:$src),
-          (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV8rm addr:$src),
-                         x86_subreg_8bit)>;
-def : Pat<(extloadi64i8 addr:$src),
-          (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV8rm addr:$src),
-                         x86_subreg_8bit)>;
-def : Pat<(extloadi64i16 addr:$src),
-          (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV16rm addr:$src),
-                         x86_subreg_16bit)>;
+// When extloading from 16-bit and smaller memory locations into 64-bit registers,
+// use zero-extending loads so that the entire 64-bit register is defined, avoiding
+// partial-register updates.
+def : Pat<(extloadi64i1 addr:$src),  (MOVZX64rm8  addr:$src)>;
+def : Pat<(extloadi64i8 addr:$src),  (MOVZX64rm8  addr:$src)>;
+def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
+// For other extloads, use subregs, since the high contents of the register are
+// defined after an extload.
 def : Pat<(extloadi64i32 addr:$src),
           (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src),
                          x86_subreg_32bit)>;




From sabre at nondot.org  Wed Aug 27 12:36:58 2008
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 27 Aug 2008 17:36:58 -0000
Subject: [llvm-commits] [llvm] r55423 - /llvm/trunk/lib/VMCore/Verifier.cpp
Message-ID: <200808271736.m7RHaweK029669@zion.cs.uiuc.edu>

Author: lattner
Date: Wed Aug 27 12:36:58 2008
New Revision: 55423

URL: http://llvm.org/viewvc/llvm-project?rev=55423&view=rev
Log:
Minor cleanup.

Modified:
    llvm/trunk/lib/VMCore/Verifier.cpp

Modified: llvm/trunk/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=55423&r1=55422&r2=55423&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/Verifier.cpp (original)
+++ llvm/trunk/lib/VMCore/Verifier.cpp Wed Aug 27 12:36:58 2008
@@ -198,23 +198,22 @@
     /// this condition, do so.
     ///
     bool abortIfBroken() {
-      if (Broken) {
-        msgs << "Broken module found, ";
-        switch (action) {
-          case AbortProcessAction:
-            msgs << "compilation aborted!\n";
-            cerr << msgs.str();
-            abort();
-          case PrintMessageAction:
-            msgs << "verification continues.\n";
-            cerr << msgs.str();
-            return false;
-          case ReturnStatusAction:
-            msgs << "compilation terminated.\n";
-            return Broken;
-        }
+      if (!Broken) return false;
+      msgs << "Broken module found, ";
+      switch (action) {
+      default: assert(0 && "Unknown action");
+      case AbortProcessAction:
+        msgs << "compilation aborted!\n";
+        cerr << msgs.str();
+        abort();
+      case PrintMessageAction:
+        msgs << "verification continues.\n";
+        cerr << msgs.str();
+        return false;
+      case ReturnStatusAction:
+        msgs << "compilation terminated.\n";
+        return Broken;
       }
-      return false;
     }
 
 




From dpatel at apple.com  Wed Aug 27 12:43:07 2008
From: dpatel at apple.com (Devang Patel)
Date: Wed, 27 Aug 2008 10:43:07 -0700
Subject: [llvm-commits] [llvm] r55374 - in /llvm/trunk:
	lib/Transforms/Scalar/LoopStrengthReduce.cpp
	test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll
In-Reply-To: <C371F941-5CDC-48E6-97EB-93F5C9A558E4@apple.com>
References: <200808261758.m7QHw5FM031611@zion.cs.uiuc.edu>
	<C371F941-5CDC-48E6-97EB-93F5C9A558E4@apple.com>
Message-ID: <538A5D08-9390-4190-8FF4-4C62895B3418@apple.com>


On Aug 26, 2008, at 11:50 PM, Evan Cheng wrote:

> Hi Devang,
>
> Please avoid the transformation is the int-to-float type is not
> natively supported.

As soon as I figure out the right way to check lack of native floating  
point operations, I'll add the check to avoid this transformation in  
such cases. Any hints ?
Thanks,
-
Devang


From dpatel at apple.com  Wed Aug 27 12:50:18 2008
From: dpatel at apple.com (Devang Patel)
Date: Wed, 27 Aug 2008 17:50:18 -0000
Subject: [llvm-commits] [llvm] r55424 -
	/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Message-ID: <200808271750.m7RHoIc0030230@zion.cs.uiuc.edu>

Author: dpatel
Date: Wed Aug 27 12:50:18 2008
New Revision: 55424

URL: http://llvm.org/viewvc/llvm-project?rev=55424&view=rev
Log:
Fix typos and whitespaces. Other cosmetic changes based on feedback.

Modified:
    llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=55424&r1=55423&r2=55424&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Wed Aug 27 12:50:18 2008
@@ -44,8 +44,8 @@
 STATISTIC(NumReduced ,    "Number of GEPs strength reduced");
 STATISTIC(NumInserted,    "Number of PHIs inserted");
 STATISTIC(NumVariable,    "Number of PHIs with variable strides");
-STATISTIC(NumEliminated , "Number of strides eliminated");
-STATISTIC(NumShadow , "Number of Shadow IVs optimized");
+STATISTIC(NumEliminated,  "Number of strides eliminated");
+STATISTIC(NumShadow,      "Number of Shadow IVs optimized");
 
 namespace {
 
@@ -1715,30 +1715,27 @@
     for (std::vector<IVStrideUse>::iterator UI = SI->second.Users.begin(),
            E = SI->second.Users.end(); UI != E; /* empty */) {
       std::vector<IVStrideUse>::iterator CandidateUI = UI;
-      UI++;
+      ++UI;
       Instruction *ShadowUse = CandidateUI->User;
       const Type *DestTy = NULL;
 
       /* If shadow use is a int->float cast then insert a second IV
-         to elminate this cast.
+         to eliminate this cast.
 
            for (unsigned i = 0; i < n; ++i) 
              foo((double)i);
 
-         is trnasformed into
+         is transformed into
 
            double d = 0.0;
            for (unsigned i = 0; i < n; ++i, ++d) 
              foo(d);
       */
-      UIToFPInst *UCast = dyn_cast<UIToFPInst>(CandidateUI->User);
-      if (UCast) 
+      if (UIToFPInst *UCast = dyn_cast<UIToFPInst>(CandidateUI->User))
         DestTy = UCast->getDestTy();
-      else {
-        SIToFPInst *SCast = dyn_cast<SIToFPInst>(CandidateUI->User);
-        if (!SCast) continue;
+      else if (SIToFPInst *SCast = dyn_cast<SIToFPInst>(CandidateUI->User))
         DestTy = SCast->getDestTy();
-      }
+    if (!DestTy) continue;
       
       PHINode *PH = dyn_cast<PHINode>(ShadowUse->getOperand(0));
       if (!PH) continue;
@@ -1784,7 +1781,7 @@
       /* Add new PHINode. */
       PHINode *NewPH = PHINode::Create(DestTy, "IV.S.", PH);
 
-      /* create new icnrement. '++d' in above example. */
+      /* create new increment. '++d' in above example. */
       ConstantFP *CFP = ConstantFP::get(DestTy, C->getZExtValue());
       BinaryOperator *NewIncr = 
         BinaryOperator::Create(Incr->getOpcode(),




From gohman at apple.com  Wed Aug 27 13:01:42 2008
From: gohman at apple.com (Dan Gohman)
Date: Wed, 27 Aug 2008 18:01:42 -0000
Subject: [llvm-commits] [llvm] r55425 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808271801.m7RI1gU5030566@zion.cs.uiuc.edu>

Author: djg
Date: Wed Aug 27 13:01:42 2008
New Revision: 55425

URL: http://llvm.org/viewvc/llvm-project?rev=55425&view=rev
Log:
Add a comment about the current floating-point constant code in FastISel.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55425&r1=55424&r2=55425&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Wed Aug 27 13:01:42 2008
@@ -525,6 +525,12 @@
   // Materialize the constant in a register.
   unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
   if (MaterialReg == 0) {
+    // If the target doesn't have a way to directly enter a floating-point
+    // value into a register, use an alternate approach.
+    // TODO: The current approach only supports floating-point constants
+    // that can be constructed by conversion from integer values. This should
+    // be replaced by code that creates a load from a constant-pool entry,
+    // which will require some target-specific work.
     const APFloat &Flt = FPImm->getValueAPF();
     MVT IntVT = TLI.getPointerTy();
 




From gohman at apple.com  Wed Aug 27 13:10:19 2008
From: gohman at apple.com (Dan Gohman)
Date: Wed, 27 Aug 2008 18:10:19 -0000
Subject: [llvm-commits] [llvm] r55426 - in /llvm/trunk:
 include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808271810.m7RIAJKN030869@zion.cs.uiuc.edu>

Author: djg
Date: Wed Aug 27 13:10:19 2008
New Revision: 55426

URL: http://llvm.org/viewvc/llvm-project?rev=55426&view=rev
Log:
Add a new FastISel method, getRegForValue, which takes care of
the details of materializing constants and other values into
registers, and make use of it in several places.

Modified:
    llvm/trunk/include/llvm/CodeGen/FastISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=55426&r1=55425&r2=55426&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Wed Aug 27 13:10:19 2008
@@ -194,6 +194,9 @@
                           uint64_t Imm);
 
 private:
+  unsigned getRegForValue(Value *V,
+                          DenseMap<const Value*, unsigned> &ValueMap);
+
   unsigned createResultReg(const TargetRegisterClass *RC);
 
   bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
@@ -207,11 +210,6 @@
   
   bool SelectCast(Instruction *I, ISD::NodeType Opcode,
                   DenseMap<const Value*, unsigned> &ValueMap);
-  
-  bool SelectConstantCast(Instruction *I, ISD::NodeType Opcode,
-                          DenseMap<const Value*, unsigned> &ValueMap);
-  bool SelectConstantFPCast(Instruction *I, ISD::NodeType Opcode,
-                            DenseMap<const Value*, unsigned> &ValueMap);
 };
 
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55426&r1=55425&r2=55426&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Wed Aug 27 13:10:19 2008
@@ -21,6 +21,43 @@
 #include "llvm/Target/TargetMachine.h"
 using namespace llvm;
 
+unsigned FastISel::getRegForValue(Value *V, DenseMap<const Value*, unsigned> &ValueMap) {
+  unsigned &Reg = ValueMap[V];
+  if (Reg != 0)
+    return Reg;
+
+  MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
+  if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
+    if (CI->getValue().getActiveBits() > 64)
+      return 0;
+    Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
+  } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
+    Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
+
+    if (!Reg) {
+      const APFloat &Flt = CF->getValueAPF();
+      MVT IntVT = TLI.getPointerTy();
+
+      uint64_t x[2];
+      uint32_t IntBitWidth = IntVT.getSizeInBits();
+      if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
+                               APFloat::rmTowardZero) != APFloat::opOK)
+        return 0;
+      APInt IntVal(IntBitWidth, 2, x);
+
+      unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
+                                       ISD::Constant, IntVal.getZExtValue());
+      if (IntegerReg == 0)
+        return 0;
+      Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
+      if (Reg == 0)
+        return 0;
+    }
+  }
+
+  return Reg;
+}
+
 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
 /// which has an opcode which directly corresponds to the given ISD opcode.
 ///
@@ -37,44 +74,39 @@
   if (!TLI.isTypeLegal(VT))
     return false;
 
-  unsigned Op0 = ValueMap[I->getOperand(0)];
+  unsigned Op0 = getRegForValue(I->getOperand(0), ValueMap);
   if (Op0 == 0)
     // Unhandled operand. Halt "fast" selection and bail.
     return false;
 
   // Check if the second operand is a constant and handle it appropriately.
   if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
-    unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
-                                      CI->getZExtValue(), VT.getSimpleVT());
-    if (ResultReg == 0)
-      // Target-specific code wasn't able to find a machine opcode for
-      // the given ISD opcode and type. Halt "fast" selection and bail.
-      return false;
-
-    // We successfully emitted code for the given LLVM Instruction.
-    ValueMap[I] = ResultReg;
-    return true;
+    unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
+                                     ISDOpcode, Op0, CI->getZExtValue());
+    if (ResultReg != 0) {
+      // We successfully emitted code for the given LLVM Instruction.
+      ValueMap[I] = ResultReg;
+      return true;
+    }
   }
 
   // Check if the second operand is a constant float.
   if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
-    unsigned ResultReg = FastEmit_rf_(VT.getSimpleVT(), ISDOpcode, Op0,
-                                      CF, VT.getSimpleVT());
-    if (ResultReg == 0)
-      // Target-specific code wasn't able to find a machine opcode for
-      // the given ISD opcode and type. Halt "fast" selection and bail.
-      return false;
-
-    // We successfully emitted code for the given LLVM Instruction.
-    ValueMap[I] = ResultReg;
-    return true;
+    unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
+                                     ISDOpcode, Op0, CF);
+    if (ResultReg != 0) {
+      // We successfully emitted code for the given LLVM Instruction.
+      ValueMap[I] = ResultReg;
+      return true;
+    }
   }
 
-  unsigned Op1 = ValueMap[I->getOperand(1)];
+  unsigned Op1 = getRegForValue(I->getOperand(1), ValueMap);
   if (Op1 == 0)
     // Unhandled operand. Halt "fast" selection and bail.
     return false;
 
+  // Now we have both operands in registers. Emit the instruction.
   unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
                                    ISDOpcode, Op0, Op1);
   if (ResultReg == 0)
@@ -89,7 +121,7 @@
 
 bool FastISel::SelectGetElementPtr(Instruction *I,
                                    DenseMap<const Value*, unsigned> &ValueMap) {
-  unsigned N = ValueMap[I->getOperand(0)];
+  unsigned N = getRegForValue(I->getOperand(0), ValueMap);
   if (N == 0)
     // Unhandled operand. Halt "fast" selection and bail.
     return false;
@@ -129,7 +161,7 @@
       
       // N = N + Idx * ElementSize;
       uint64_t ElementSize = TD.getABITypeSize(Ty);
-      unsigned IdxN = ValueMap[Idx];
+      unsigned IdxN = getRegForValue(Idx, ValueMap);
       if (IdxN == 0)
         // Unhandled operand. Halt "fast" selection and bail.
         return false;
@@ -174,7 +206,7 @@
     // Unhandled type. Halt "fast" selection and bail.
     return false;
     
-  unsigned InputReg = ValueMap[I->getOperand(0)];
+  unsigned InputReg = getRegForValue(I->getOperand(0), ValueMap);
   if (!InputReg)
     // Unhandled operand.  Halt "fast" selection and bail.
     return false;
@@ -190,11 +222,16 @@
   return true;
 }
 
-bool FastISel::SelectConstantCast(Instruction* I, ISD::NodeType Opcode,
-                                  DenseMap<const Value*, unsigned> &ValueMap) {
-  // Materialize constant and convert.
-  ConstantInt* CI = cast<ConstantInt>(I->getOperand(0));
-  MVT SrcVT = MVT::getMVT(CI->getType());
+bool FastISel::SelectBitCast(Instruction *I,
+                             DenseMap<const Value*, unsigned> &ValueMap) {
+  // If the bitcast doesn't change the type, just use the operand value.
+  if (I->getType() == I->getOperand(0)->getType()) {
+    ValueMap[I] = getRegForValue(I->getOperand(0), ValueMap);
+    return true;
+  }
+
+  // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
+  MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
   MVT DstVT = MVT::getMVT(I->getType());
   
   if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
@@ -203,96 +240,36 @@
     // Unhandled type. Halt "fast" selection and bail.
     return false;
   
-  unsigned ResultReg1 = FastEmit_i(SrcVT.getSimpleVT(),
-                                   SrcVT.getSimpleVT(),
-                                   ISD::Constant, CI->getZExtValue());
-  if (!ResultReg1)
+  unsigned Op0 = getRegForValue(I->getOperand(0), ValueMap);
+  if (Op0 == 0)
+    // Unhandled operand. Halt "fast" selection and bail.
     return false;
   
-  unsigned ResultReg2 = FastEmit_r(SrcVT.getSimpleVT(),
-                                   DstVT.getSimpleVT(),
-                                   Opcode,
-                                   ResultReg1);
-  if (!ResultReg2)
+  // First, try to perform the bitcast by inserting a reg-reg copy.
+  unsigned ResultReg = 0;
+  if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
+    TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
+    TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
+    ResultReg = createResultReg(DstClass);
+    
+    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+                                         Op0, DstClass, SrcClass);
+    if (!InsertedCopy)
+      ResultReg = 0;
+  }
+  
+  // If the reg-reg copy failed, select a BIT_CONVERT opcode.
+  if (!ResultReg)
+    ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
+                           ISD::BIT_CONVERT, Op0);
+  
+  if (!ResultReg)
     return false;
   
-  ValueMap[I] = ResultReg2;
+  ValueMap[I] = ResultReg;
   return true;
 }
 
-bool FastISel::SelectConstantFPCast(Instruction* I, ISD::NodeType Opcode,
-                                  DenseMap<const Value*, unsigned> &ValueMap) {
-  // TODO: Implement casting of FP constants by materialization
-  // followed by conversion.
-  return false;
-}
-
-bool FastISel::SelectBitCast(Instruction *I,
-                             DenseMap<const Value*, unsigned> &ValueMap) {
-  // BitCast consists of either an immediate to register move
-  // or a register to register move.
-  if (ConstantInt* CI = dyn_cast<ConstantInt>(I->getOperand(0))) {
-    if (I->getType()->isInteger()) {
-      MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/false);
-      unsigned result = FastEmit_i(VT.getSimpleVT(), VT.getSimpleVT(),
-                                   ISD::Constant,
-                                   CI->getZExtValue());
-      if (!result)
-        return false;
-      
-      ValueMap[I] = result;
-      return true;
-    }
-
-    // TODO: Support vector and fp constants.
-    return false;
-  }
-
-  if (!isa<Constant>(I->getOperand(0))) {
-    // Bitcasts of non-constant values become reg-reg copies.
-    MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
-    MVT DstVT = MVT::getMVT(I->getType());
-    
-    if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
-        DstVT == MVT::Other || !DstVT.isSimple() ||
-        !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
-      // Unhandled type. Halt "fast" selection and bail.
-      return false;
-    
-    unsigned Op0 = ValueMap[I->getOperand(0)];
-    if (Op0 == 0)
-      // Unhandled operand. Halt "fast" selection and bail.
-      return false;
-    
-    // First, try to perform the bitcast by inserting a reg-reg copy.
-    unsigned ResultReg = 0;
-    if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
-      TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
-      TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
-      ResultReg = createResultReg(DstClass);
-      
-      bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
-                                           Op0, DstClass, SrcClass);
-      if (!InsertedCopy)
-        ResultReg = 0;
-    }
-    
-    // If the reg-reg copy failed, select a BIT_CONVERT opcode.
-    if (!ResultReg)
-      ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
-                             ISD::BIT_CONVERT, Op0);
-    
-    if (!ResultReg)
-      return false;
-    
-    ValueMap[I] = ResultReg;
-    return true;
-  }
-
-  // TODO: Casting a non-integral constant?
-  return false;
-}
-
 BasicBlock::iterator
 FastISel::SelectInstructions(BasicBlock::iterator Begin,
                              BasicBlock::iterator End,
@@ -378,28 +355,16 @@
       if (!SelectBitCast(I, ValueMap)) return I; break;
 
     case Instruction::FPToSI:
-      if (!isa<ConstantFP>(I->getOperand(0))) {
-        if (!SelectCast(I, ISD::FP_TO_SINT, ValueMap)) return I; 
-      } else
-        if (!SelectConstantFPCast(I, ISD::FP_TO_SINT, ValueMap)) return I;
+      if (!SelectCast(I, ISD::FP_TO_SINT, ValueMap)) return I; 
       break;
     case Instruction::ZExt:
-      if (!isa<ConstantInt>(I->getOperand(0))) {
-        if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
-      } else
-        if (!SelectConstantCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
+      if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
       break;
     case Instruction::SExt:
-      if (!isa<ConstantInt>(I->getOperand(0))) {
-        if (!SelectCast(I, ISD::SIGN_EXTEND, ValueMap)) return I;
-      } else
-        if (!SelectConstantCast(I, ISD::SIGN_EXTEND, ValueMap)) return I;
+      if (!SelectCast(I, ISD::SIGN_EXTEND, ValueMap)) return I;
       break;
     case Instruction::SIToFP:
-      if (!isa<ConstantInt>(I->getOperand(0))) {
-        if (!SelectCast(I, ISD::SINT_TO_FP, ValueMap)) return I;
-      } else
-        if (!SelectConstantCast(I, ISD::SINT_TO_FP, ValueMap)) return I;
+      if (!SelectCast(I, ISD::SINT_TO_FP, ValueMap)) return I;
       break;
 
     case Instruction::IntToPtr: // Deliberate fall-through.
@@ -414,10 +379,7 @@
           // Unhandled operand
           return I;
       } else if (DstVT.bitsGT(SrcVT)) {
-        if (!isa<ConstantInt>(I->getOperand(0))) {
-          if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
-        } else
-          if (!SelectConstantCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
+        if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
         break;
       } else {
         // TODO: Handle SrcVT > DstVT, where truncation is needed.




From gohman at apple.com  Wed Aug 27 13:15:05 2008
From: gohman at apple.com (Dan Gohman)
Date: Wed, 27 Aug 2008 18:15:05 -0000
Subject: [llvm-commits] [llvm] r55427 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808271815.m7RIF51b031186@zion.cs.uiuc.edu>

Author: djg
Date: Wed Aug 27 13:15:05 2008
New Revision: 55427

URL: http://llvm.org/viewvc/llvm-project?rev=55427&view=rev
Log:
Don't check TLI.getOperationAction. The FastISel way is to
just try to do the action and let the tablegen-generated code
determine if there is target-support for an operation.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55427&r1=55426&r2=55427&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Wed Aug 27 13:15:05 2008
@@ -458,10 +458,8 @@
 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
                                 unsigned Op0, uint64_t Imm,
                                 MVT::SimpleValueType ImmType) {
-  unsigned ResultReg = 0;
   // First check if immediate type is legal. If not, we can't use the ri form.
-  if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
-    ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
+  unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
   if (ResultReg != 0)
     return ResultReg;
   unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
@@ -477,10 +475,8 @@
 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
                                 unsigned Op0, ConstantFP *FPImm,
                                 MVT::SimpleValueType ImmType) {
-  unsigned ResultReg = 0;
   // First check if immediate type is legal. If not, we can't use the rf form.
-  if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
-    ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
+  unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
   if (ResultReg != 0)
     return ResultReg;
 




From evan.cheng at apple.com  Wed Aug 27 13:20:31 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 27 Aug 2008 11:20:31 -0700
Subject: [llvm-commits] [llvm] r55374 - in /llvm/trunk:
	lib/Transforms/Scalar/LoopStrengthReduce.cpp
	test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll
In-Reply-To: <538A5D08-9390-4190-8FF4-4C62895B3418@apple.com>
References: <200808261758.m7QHw5FM031611@zion.cs.uiuc.edu>
	<C371F941-5CDC-48E6-97EB-93F5C9A558E4@apple.com>
	<538A5D08-9390-4190-8FF4-4C62895B3418@apple.com>
Message-ID: <1717E167-BBBD-4FA1-922D-DBED0896F5E3@apple.com>

TargetLowering::getTypeAction probably would do.

Evan

On Aug 27, 2008, at 10:43 AM, Devang Patel wrote:

>
> On Aug 26, 2008, at 11:50 PM, Evan Cheng wrote:
>
>> Hi Devang,
>>
>> Please avoid the transformation is the int-to-float type is not
>> natively supported.
>
> As soon as I figure out the right way to check lack of native floating
> point operations, I'll add the check to avoid this transformation in
> such cases. Any hints ?
> Thanks,
> -
> Devang
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From dpatel at apple.com  Wed Aug 27 14:20:11 2008
From: dpatel at apple.com (Devang Patel)
Date: Wed, 27 Aug 2008 12:20:11 -0700
Subject: [llvm-commits] [llvm] r55374 - in /llvm/trunk:
	lib/Transforms/Scalar/LoopStrengthReduce.cpp
	test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll
In-Reply-To: <1717E167-BBBD-4FA1-922D-DBED0896F5E3@apple.com>
References: <200808261758.m7QHw5FM031611@zion.cs.uiuc.edu>
	<C371F941-5CDC-48E6-97EB-93F5C9A558E4@apple.com>
	<538A5D08-9390-4190-8FF4-4C62895B3418@apple.com>
	<1717E167-BBBD-4FA1-922D-DBED0896F5E3@apple.com>
Message-ID: <E418B5FF-400E-4C48-8908-130170414D86@apple.com>


On Aug 27, 2008, at 11:20 AM, Evan Cheng wrote:

> TargetLowering::getTypeAction probably would do.

I found TargetLowering::isTypeLegal() however, TargetLowering is not  
set when loop-reduce is used through 'opt'. I'll try to find some way.

Thanks for TargetLowering hint.
-
Devang


From dpatel at apple.com  Wed Aug 27 15:00:29 2008
From: dpatel at apple.com (Devang Patel)
Date: Wed, 27 Aug 2008 20:00:29 -0000
Subject: [llvm-commits] [llvm] r55429 - /llvm/trunk/tools/opt/opt.cpp
Message-ID: <200808272000.m7RK0TW0002496@zion.cs.uiuc.edu>

Author: dpatel
Date: Wed Aug 27 15:00:27 2008
New Revision: 55429

URL: http://llvm.org/viewvc/llvm-project?rev=55429&view=rev
Log:
Add facility to create a target.

Modified:
    llvm/trunk/tools/opt/opt.cpp

Modified: llvm/trunk/tools/opt/opt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/opt.cpp?rev=55429&r1=55428&r2=55429&view=diff

==============================================================================
--- llvm/trunk/tools/opt/opt.cpp (original)
+++ llvm/trunk/tools/opt/opt.cpp Wed Aug 27 15:00:27 2008
@@ -22,6 +22,8 @@
 #include "llvm/Analysis/CallGraph.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetMachineRegistry.h"
+#include "llvm/Target/SubtargetFeature.h"
 #include "llvm/Support/PassNameParser.h"
 #include "llvm/System/Signals.h"
 #include "llvm/Support/ManagedStatic.h"
@@ -93,6 +95,22 @@
 static cl::opt<bool>
 AnalyzeOnly("analyze", cl::desc("Only perform analysis, no optimization"));
 
+static cl::opt<const TargetMachineRegistry::entry*, false,
+               TargetMachineRegistry::Parser>
+MArch("march", cl::desc("Architecture to generate code for:"));
+
+static cl::opt<std::string>
+MCPU("mcpu", 
+  cl::desc("Target a specific cpu type (-mcpu=help for details)"),
+  cl::value_desc("cpu-name"),
+  cl::init(""));
+
+static cl::list<std::string>
+MAttrs("mattr", 
+  cl::CommaSeparated,
+  cl::desc("Target specific attributes (-mattr=help for details)"),
+  cl::value_desc("a1,+a2,-a3,..."));
+
 // ---------- Define Printers for module and function passes ------------
 namespace {
 
@@ -308,6 +326,36 @@
 //===----------------------------------------------------------------------===//
 // main for opt
 //
+
+TargetMachine *getTargetMachine(Module &Mod) {
+
+  if (MArch == 0) {
+    std::string Err;
+    MArch = 
+      TargetMachineRegistry::getClosestStaticTargetForModule(Mod, Err);
+    if (MArch == 0) {
+      std::cerr << "Error auto-selecting target for module '"
+                << Err << "'.  Please use the -march option to explicitly "
+                << "pick a target.\n";
+      return NULL;
+    }
+  }
+  
+  // Package up features to be passed to target/subtarget
+  std::string FeaturesStr;
+  if (MCPU.size() || MAttrs.size()) {
+    SubtargetFeatures Features;
+    Features.setCPU(MCPU);
+    for (unsigned i = 0; i != MAttrs.size(); ++i)
+      Features.AddFeature(MAttrs[i]);
+    FeaturesStr = Features.getString();
+  }
+  
+  TargetMachine *Target = MArch->CtorFn(Mod, FeaturesStr);
+  assert(Target && "Could not allocate target machine!");
+  return Target;
+}
+
 int main(int argc, char **argv) {
   llvm_shutdown_obj X;  // Call llvm_shutdown() on exit.
   try {
@@ -315,10 +363,6 @@
       "llvm .bc -> .bc modular optimizer and analysis printer\n");
     sys::PrintStackTraceOnErrorSignal();
 
-    // Allocate a full target machine description only if necessary.
-    // FIXME: The choice of target should be controllable on the command line.
-    std::auto_ptr<TargetMachine> target;
-
     std::string ErrorMessage;
 
     // Load the input module...




From evan.cheng at apple.com  Wed Aug 27 15:33:52 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 27 Aug 2008 20:33:52 -0000
Subject: [llvm-commits] [llvm] r55430 - in /llvm/trunk:
 include/llvm/CodeGen/MachineInstr.h lib/CodeGen/MachineInstr.cpp
 lib/CodeGen/TwoAddressInstructionPass.cpp
Message-ID: <200808272033.m7RKXq1Y003513@zion.cs.uiuc.edu>

Author: evancheng
Date: Wed Aug 27 15:33:50 2008
New Revision: 55430

URL: http://llvm.org/viewvc/llvm-project?rev=55430&view=rev
Log:
Refactor isSafeToReMat out of 2addr pass.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineInstr.h
    llvm/trunk/lib/CodeGen/MachineInstr.cpp
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=55430&r1=55429&r2=55430&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Wed Aug 27 15:33:50 2008
@@ -250,6 +250,8 @@
   /// the instruction's location and its intended destination.
   bool isSafeToMove(const TargetInstrInfo *TII, bool &SawStore);
 
+  bool isSafeToReMat(const TargetInstrInfo *TII, unsigned DstReg);
+
   //
   // Debugging support
   //

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=55430&r1=55429&r2=55430&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Wed Aug 27 15:33:50 2008
@@ -711,6 +711,31 @@
   return true;
 }
 
+/// isSafeToReMat - Return true if it's safe to rematerialize the specified
+/// instruction which defined the specified register instead of copying it.
+bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, unsigned DstReg) {
+  if (!TID->isAsCheapAsAMove())
+    return false;
+  bool SawStore = false;
+  if (!isSafeToMove(TII, SawStore))
+    return false;
+  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
+    MachineOperand &MO = getOperand(i);
+    if (!MO.isRegister())
+      continue;
+    // FIXME: For now, do not remat any instruction with register operands.
+    // Later on, we can loosen the restriction is the register operands have
+    // not been modified between the def and use. Note, this is different from
+    // MachineSink because the code in no longer in two-address form (at least
+    // partially).
+    if (MO.isUse())
+      return false;
+    else if (!MO.isDead() && MO.getReg() != DstReg)
+      return false;
+  }
+  return true;
+}
+
 void MachineInstr::dump() const {
   cerr << "  " << *this;
 }

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=55430&r1=55429&r2=55430&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Wed Aug 27 15:33:50 2008
@@ -64,7 +64,6 @@
                               unsigned Reg,
                               MachineBasicBlock::iterator OldPos);
 
-    bool isSafeToReMat(unsigned DstReg, MachineInstr *MI);
     bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
                              MachineInstr *MI, MachineInstr *DefMI,
                              MachineBasicBlock *MBB, unsigned Loc,
@@ -195,33 +194,6 @@
   return true;
 }
 
-/// isSafeToReMat - Return true if it's safe to rematerialize the specified
-/// instruction which defined the specified register instead of copying it.
-bool
-TwoAddressInstructionPass::isSafeToReMat(unsigned DstReg, MachineInstr *MI) {
-  const TargetInstrDesc &TID = MI->getDesc();
-  if (!TID.isAsCheapAsAMove())
-    return false;
-  bool SawStore = false;
-  if (!MI->isSafeToMove(TII, SawStore))
-    return false;
-  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
-    MachineOperand &MO = MI->getOperand(i);
-    if (!MO.isRegister())
-      continue;
-    // FIXME: For now, do not remat any instruction with register operands.
-    // Later on, we can loosen the restriction is the register operands have
-    // not been modified between the def and use. Note, this is different from
-    // MachineSink because the code in no longer in two-address form (at least
-    // partially).
-    if (MO.isUse())
-      return false;
-    else if (!MO.isDead() && MO.getReg() != DstReg)
-      return false;
-  }
-  return true;
-}
-
 /// isTwoAddrUse - Return true if the specified MI is using the specified
 /// register as a two-address operand.
 static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
@@ -431,7 +403,7 @@
           // If it's safe and profitable, remat the definition instead of
           // copying it.
           if (DefMI &&
-              isSafeToReMat(regB, DefMI) &&
+              DefMI->isSafeToReMat(TII, regB) &&
               isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist,DistanceMap)){
             DEBUG(cerr << "2addr: REMATTING : " << *DefMI << "\n");
             TII->reMaterialize(*mbbi, mi, regA, DefMI);




From gohman at apple.com  Wed Aug 27 15:41:38 2008
From: gohman at apple.com (Dan Gohman)
Date: Wed, 27 Aug 2008 20:41:38 -0000
Subject: [llvm-commits] [llvm] r55431 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808272041.m7RKfc0s003799@zion.cs.uiuc.edu>

Author: djg
Date: Wed Aug 27 15:41:38 2008
New Revision: 55431

URL: http://llvm.org/viewvc/llvm-project?rev=55431&view=rev
Log:
Fix FastISel's bitcast code for the case where getRegForValue fails.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55431&r1=55430&r2=55431&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Wed Aug 27 15:41:38 2008
@@ -226,7 +226,10 @@
                              DenseMap<const Value*, unsigned> &ValueMap) {
   // If the bitcast doesn't change the type, just use the operand value.
   if (I->getType() == I->getOperand(0)->getType()) {
-    ValueMap[I] = getRegForValue(I->getOperand(0), ValueMap);
+    unsigned Reg = getRegForValue(I->getOperand(0), ValueMap);
+    if (Reg == 0)
+      return false;
+    ValueMap[I] = Reg;
     return true;
   }
 




From clattner at apple.com  Wed Aug 27 15:42:53 2008
From: clattner at apple.com (Chris Lattner)
Date: Wed, 27 Aug 2008 13:42:53 -0700
Subject: [llvm-commits] [llvm] r55374 - in /llvm/trunk:
	lib/Transforms/Scalar/LoopStrengthReduce.cpp
	test/Transforms/LoopStrengthReduce/2008-08-14-ShadowIV.ll
In-Reply-To: <E418B5FF-400E-4C48-8908-130170414D86@apple.com>
References: <200808261758.m7QHw5FM031611@zion.cs.uiuc.edu>
	<C371F941-5CDC-48E6-97EB-93F5C9A558E4@apple.com>
	<538A5D08-9390-4190-8FF4-4C62895B3418@apple.com>
	<1717E167-BBBD-4FA1-922D-DBED0896F5E3@apple.com>
	<E418B5FF-400E-4C48-8908-130170414D86@apple.com>
Message-ID: <1C845E0D-3B6D-44AB-9962-D40CE827B1A1@apple.com>


On Aug 27, 2008, at 12:20 PM, Devang Patel wrote:

>
> On Aug 27, 2008, at 11:20 AM, Evan Cheng wrote:
>
>> TargetLowering::getTypeAction probably would do.
>
> I found TargetLowering::isTypeLegal() however, TargetLowering is not
> set when loop-reduce is used through 'opt'. I'll try to find some way.

This is "normal".  LSR is heavily parameterized on the target CPU  
info, and this is only available when LSR is run from LLC.  Making LSR  
runnable through opt is mostly useful to allow writing regtests for  
it, it isn't a practical way to run it if you care about code quality.

-Chris



From dpatel at apple.com  Wed Aug 27 15:51:50 2008
From: dpatel at apple.com (Devang Patel)
Date: Wed, 27 Aug 2008 20:51:50 -0000
Subject: [llvm-commits] [llvm] r55432 - /llvm/trunk/tools/opt/opt.cpp
Message-ID: <200808272051.m7RKpoxD004282@zion.cs.uiuc.edu>

Author: dpatel
Date: Wed Aug 27 15:51:49 2008
New Revision: 55432

URL: http://llvm.org/viewvc/llvm-project?rev=55432&view=rev
Log:
Backout 55429

Modified:
    llvm/trunk/tools/opt/opt.cpp

Modified: llvm/trunk/tools/opt/opt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/opt.cpp?rev=55432&r1=55431&r2=55432&view=diff

==============================================================================
--- llvm/trunk/tools/opt/opt.cpp (original)
+++ llvm/trunk/tools/opt/opt.cpp Wed Aug 27 15:51:49 2008
@@ -22,8 +22,6 @@
 #include "llvm/Analysis/CallGraph.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetMachineRegistry.h"
-#include "llvm/Target/SubtargetFeature.h"
 #include "llvm/Support/PassNameParser.h"
 #include "llvm/System/Signals.h"
 #include "llvm/Support/ManagedStatic.h"
@@ -95,22 +93,6 @@
 static cl::opt<bool>
 AnalyzeOnly("analyze", cl::desc("Only perform analysis, no optimization"));
 
-static cl::opt<const TargetMachineRegistry::entry*, false,
-               TargetMachineRegistry::Parser>
-MArch("march", cl::desc("Architecture to generate code for:"));
-
-static cl::opt<std::string>
-MCPU("mcpu", 
-  cl::desc("Target a specific cpu type (-mcpu=help for details)"),
-  cl::value_desc("cpu-name"),
-  cl::init(""));
-
-static cl::list<std::string>
-MAttrs("mattr", 
-  cl::CommaSeparated,
-  cl::desc("Target specific attributes (-mattr=help for details)"),
-  cl::value_desc("a1,+a2,-a3,..."));
-
 // ---------- Define Printers for module and function passes ------------
 namespace {
 
@@ -326,36 +308,6 @@
 //===----------------------------------------------------------------------===//
 // main for opt
 //
-
-TargetMachine *getTargetMachine(Module &Mod) {
-
-  if (MArch == 0) {
-    std::string Err;
-    MArch = 
-      TargetMachineRegistry::getClosestStaticTargetForModule(Mod, Err);
-    if (MArch == 0) {
-      std::cerr << "Error auto-selecting target for module '"
-                << Err << "'.  Please use the -march option to explicitly "
-                << "pick a target.\n";
-      return NULL;
-    }
-  }
-  
-  // Package up features to be passed to target/subtarget
-  std::string FeaturesStr;
-  if (MCPU.size() || MAttrs.size()) {
-    SubtargetFeatures Features;
-    Features.setCPU(MCPU);
-    for (unsigned i = 0; i != MAttrs.size(); ++i)
-      Features.AddFeature(MAttrs[i]);
-    FeaturesStr = Features.getString();
-  }
-  
-  TargetMachine *Target = MArch->CtorFn(Mod, FeaturesStr);
-  assert(Target && "Could not allocate target machine!");
-  return Target;
-}
-
 int main(int argc, char **argv) {
   llvm_shutdown_obj X;  // Call llvm_shutdown() on exit.
   try {
@@ -363,6 +315,10 @@
       "llvm .bc -> .bc modular optimizer and analysis printer\n");
     sys::PrintStackTraceOnErrorSignal();
 
+    // Allocate a full target machine description only if necessary.
+    // FIXME: The choice of target should be controllable on the command line.
+    std::auto_ptr<TargetMachine> target;
+
     std::string ErrorMessage;
 
     // Load the input module...




From dpatel at apple.com  Wed Aug 27 15:55:23 2008
From: dpatel at apple.com (Devang Patel)
Date: Wed, 27 Aug 2008 20:55:23 -0000
Subject: [llvm-commits] [llvm] r55433 -
	/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Message-ID: <200808272055.m7RKtNP4004451@zion.cs.uiuc.edu>

Author: dpatel
Date: Wed Aug 27 15:55:23 2008
New Revision: 55433

URL: http://llvm.org/viewvc/llvm-project?rev=55433&view=rev
Log:
Do not apply the transformation if the target does not support DestTy natively.

Modified:
    llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=55433&r1=55432&r2=55433&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Wed Aug 27 15:55:23 2008
@@ -1735,8 +1735,15 @@
         DestTy = UCast->getDestTy();
       else if (SIToFPInst *SCast = dyn_cast<SIToFPInst>(CandidateUI->User))
         DestTy = SCast->getDestTy();
-    if (!DestTy) continue;
-      
+      if (!DestTy) continue;
+
+      if (TLI) {
+        /* If target does not support DestTy natively then do not apply
+           this transformation. */
+        MVT DVT = TLI->getValueType(DestTy);
+        if (!TLI->isTypeLegal(DVT)) continue;
+      }
+
       PHINode *PH = dyn_cast<PHINode>(ShadowUse->getOperand(0));
       if (!PH) continue;
       if (PH->getNumIncomingValues() != 2) continue;




From evan.cheng at apple.com  Wed Aug 27 15:58:54 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 27 Aug 2008 20:58:54 -0000
Subject: [llvm-commits] [llvm] r55434 - in /llvm/trunk/lib/CodeGen:
 MachineInstr.cpp TwoAddressInstructionPass.cpp
Message-ID: <200808272058.m7RKwsTk004600@zion.cs.uiuc.edu>

Author: evancheng
Date: Wed Aug 27 15:58:54 2008
New Revision: 55434

URL: http://llvm.org/viewvc/llvm-project?rev=55434&view=rev
Log:
Move the check whether it's worth remating to caller.

Modified:
    llvm/trunk/lib/CodeGen/MachineInstr.cpp
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=55434&r1=55433&r2=55434&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Wed Aug 27 15:58:54 2008
@@ -714,8 +714,6 @@
 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
 /// instruction which defined the specified register instead of copying it.
 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, unsigned DstReg) {
-  if (!TID->isAsCheapAsAMove())
-    return false;
   bool SawStore = false;
   if (!isSafeToMove(TII, SawStore))
     return false;
@@ -726,7 +724,7 @@
     // FIXME: For now, do not remat any instruction with register operands.
     // Later on, we can loosen the restriction is the register operands have
     // not been modified between the def and use. Note, this is different from
-    // MachineSink because the code in no longer in two-address form (at least
+    // MachineSink because the code is no longer in two-address form (at least
     // partially).
     if (MO.isUse())
       return false;

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=55434&r1=55433&r2=55434&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Wed Aug 27 15:58:54 2008
@@ -403,6 +403,7 @@
           // If it's safe and profitable, remat the definition instead of
           // copying it.
           if (DefMI &&
+              DefMI->getDesc().isAsCheapAsAMove() &&
               DefMI->isSafeToReMat(TII, regB) &&
               isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist,DistanceMap)){
             DEBUG(cerr << "2addr: REMATTING : " << *DefMI << "\n");




From isanbard at gmail.com  Wed Aug 27 16:10:14 2008
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 27 Aug 2008 21:10:14 -0000
Subject: [llvm-commits] [llvm] r55435 -
	/llvm/trunk/lib/VMCore/DebugInfoBuilder.cpp
Message-ID: <200808272110.m7RLAF9p004998@zion.cs.uiuc.edu>

Author: void
Date: Wed Aug 27 16:10:13 2008
New Revision: 55435

URL: http://llvm.org/viewvc/llvm-project?rev=55435&view=rev
Log:
Put file scoped constants in an anonymous namespace. Use the "using namespace
llvm" for consistency.

Modified:
    llvm/trunk/lib/VMCore/DebugInfoBuilder.cpp

Modified: llvm/trunk/lib/VMCore/DebugInfoBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/DebugInfoBuilder.cpp?rev=55435&r1=55434&r2=55435&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/DebugInfoBuilder.cpp (original)
+++ llvm/trunk/lib/VMCore/DebugInfoBuilder.cpp Wed Aug 27 16:10:13 2008
@@ -20,7 +20,9 @@
 #include <llvm/Support/Dwarf.h>
 #include <llvm/System/Path.h>
 
-namespace llvm {
+using namespace llvm;
+
+namespace {
     
 //===----------------------------------------------------------------------===//
 // Debug version -- copied from MachineModuleInfo (for now), in order to avoid
@@ -44,6 +46,8 @@
 const char BASICTYPE_NAME[] = "llvm.dbg.basictype";
 const char DERIVEDTYPE_NAME[] = "llvm.dbg.derivedtype";
 
+} // end anonymous namespace
+
 DebugInfoBuilder::DebugInfoBuilder() {
     anyPtrType = PointerType::getUnqual(StructType::get(NULL, NULL));
     anchorType = StructType::get(Type::Int32Ty, Type::Int32Ty, NULL);
@@ -268,5 +272,3 @@
     return new GlobalVariable(structVal->getType(), true,
         GlobalValue::InternalLinkage, structVal, DERIVEDTYPE_NAME, module);
 }
-
-}




From isanbard at gmail.com  Wed Aug 27 16:32:04 2008
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 27 Aug 2008 21:32:04 -0000
Subject: [llvm-commits] [llvm] r55436 - in /llvm/trunk/lib/Target/X86:
 X86InstrFormats.td X86InstrMMX.td
Message-ID: <200808272132.m7RLW50u005673@zion.cs.uiuc.edu>

Author: void
Date: Wed Aug 27 16:32:04 2008
New Revision: 55436

URL: http://llvm.org/viewvc/llvm-project?rev=55436&view=rev
Log:
Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use the
SSE2 registers as well as the MMX registers.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrFormats.td
    llvm/trunk/lib/Target/X86/X86InstrMMX.td

Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=55436&r1=55435&r2=55436&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Wed Aug 27 16:32:04 2008
@@ -157,16 +157,20 @@
 
 // SSE2 Instruction Templates:
 // 
-//   SDI   - SSE2 instructions with XD prefix.
-//   SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
-//   PDI   - SSE2 instructions with TB and OpSize prefixes.
-//   PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
+//   SDI    - SSE2 instructions with XD prefix.
+//   SDIi8  - SSE2 instructions with ImmT == Imm8 and XD prefix.
+//   SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
+//   PDI    - SSE2 instructions with TB and OpSize prefixes.
+//   PDIi8  - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
 
 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
       : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
             list<dag> pattern>
       : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
+class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
+             list<dag> pattern>
+      : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
       : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,

Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=55436&r1=55435&r2=55436&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Wed Aug 27 16:32:04 2008
@@ -173,15 +173,15 @@
                         "movq\t{$src, $dst|$dst, $src}",
                         [(store (v1i64 VR64:$src), addr:$dst)]>;
 
-def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
+def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
                           "movdq2q\t{$src, $dst|$dst, $src}",
                           [(set VR64:$dst,
                             (v1i64 (bitconvert
                             (i64 (vector_extract (v2i64 VR128:$src),
                                   (iPTR 0))))))]>;
 
-def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
-                          "movq2dq\t{$src, $dst|$dst, $src}",
+def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
+                           "movq2dq\t{$src, $dst|$dst, $src}",
           [(set VR128:$dst,
                 (v2i64 (vector_shuffle immAllZerosV,
                         (v2i64 (scalar_to_vector (i64 (bitconvert VR64:$src)))),




From isanbard at gmail.com  Wed Aug 27 16:32:39 2008
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 27 Aug 2008 14:32:39 -0700
Subject: [llvm-commits] [llvm] r55318 - in /llvm/trunk/lib/Target/X86:
	X86InstrFormats.td X86InstrMMX.td
In-Reply-To: <82DE1E04-9B9A-4BE3-AD0F-8A19D10A875E@apple.com>
References: <200808251832.m7PIWdiQ005650@zion.cs.uiuc.edu>
	<80B61887-0703-49E2-82AC-9841CDEFF41F@apple.com>
	<16e5fdf90808261303n34964729qa1934f14f1f26cba@mail.gmail.com>
	<82DE1E04-9B9A-4BE3-AD0F-8A19D10A875E@apple.com>
Message-ID: <C4B964C6-BE78-40E3-A0AE-8BB8C8AFF69A@gmail.com>

On Aug 26, 2008, at 2:29 PM, Evan Cheng wrote:

> On Aug 26, 2008, at 1:03 PM, Bill Wendling wrote:
>
>> Pretty sure. When I applied it, it ICEd saying "illegal instruction".
>> Removing it made it go away.
>>
>> My guess is that it used this instruction because it was marked as
>> "HasSSE2", but it shouldn't have because it does MMX stuff.
>
> Hmm... That's strange. The pattern is matching something that produces
> v1i16. The predicate doesn't change what gets matched. Is it possible
> to reproduce it and figure out what is miscompiled? I suspect the bug
> is elsewhere but it's being exposed by the change.
>
I did several tests and it looks like it's no longer failing. I'm at a  
loss as to why it failed before. I'm recommitting the patch.

-bw




From gabor at mac.com  Wed Aug 27 17:20:09 2008
From: gabor at mac.com (Gabor Greif)
Date: Thu, 28 Aug 2008 00:20:09 +0200
Subject: [llvm-commits] [PATCH] SDNode refactoring
Message-ID: <F7CCF048-F36D-4A97-BA7A-D44348F57D32@mac.com>

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-------------- next part --------------



Hi all,

here comes a big patch that cleans up the vocabulary and
abstraction boundaries of SDNode usage.

It starts at the headers, passes thru TableGen and modifies many
.cpp files.

To the most part it is just tedious text replacement. But there
are some details that are worth noting.

Here are the highlights:


1) SDUse::getVal used to return SDNode*& which is actually
used in some contexts. This breaks abstraction.
Current solution, make SDUse::getVal return SDNode*
and satisfy those clients, who actually want to mutate the SDNode*
with a new interface SDUse::getSDValue() which returns SDValue&.

Analogously, provide SDValue::setNode to set SDValue::Val.
This accompanies the new SDValue::getVal(), which is a pure getter.


2) get rid of the anachronistic names in SDValue
Val -> Node
getNode (new)
setNode (new)

Please note that there is still some confusion in SDUse (getVal)
but I revisit that in a next patch.


3) This patch does not (intentionally) change the semantics.
All deja tests still pass.


4) I expect some 80-col violations. These are best taken care in
a patch directly after checking in.


And finally here is the most important changes. I excerpt
them here, with inline comments.

> Index: include/llvm/CodeGen/SelectionDAGNodes.h
> ===================================================================
> --- include/llvm/CodeGen/SelectionDAGNodes.h    (Revision 55428)
> +++ include/llvm/CodeGen/SelectionDAGNodes.h    (Arbeitskopie)
> @@ -809,29 +809,33 @@
>  /// of information is represented with the SDValue value type.
>  ///
>  class SDValue {
> -public:
> -  SDNode *Val;        // The node defining the value we are using.
> -private:
> +  SDNode *Node;       // The node defining the value we are using.



"Val" is named "Node" now and it becomes private.

>    unsigned ResNo;     // Which return value of the node we are using.
>  public:
> -  SDValue() : Val(0), ResNo(0) {}
> -  SDValue(SDNode *val, unsigned resno) : Val(val), ResNo(resno) {}
> +  SDValue() : Node(0), ResNo(0) {}
> +  SDValue(SDNode *node, unsigned resno) : Node(node), ResNo(resno) {}
>
>    /// get the index which selects a specific result in the SDNode
>    unsigned getResNo() const { return ResNo; }
>
> +  /// get the SDNode which holds the desired result
> +  SDNode *getNode() const { return Node; }
> +
> +  /// set the SDNode
> +  void setNode(SDNode *N) { Node = N; }
> +


These are the new accessors.


>    bool operator==(const SDValue &O) const {
> -    return Val == O.Val && ResNo == O.ResNo;
> +    return Node == O.Node && ResNo == O.ResNo;
>    }
>    bool operator!=(const SDValue &O) const {
>      return !operator==(O);
>    }
>    bool operator<(const SDValue &O) const {
> -    return Val < O.Val || (Val == O.Val && ResNo < O.ResNo);
> +    return Node < O.Node || (Node == O.Node && ResNo < O.ResNo);
>    }
>
>    SDValue getValue(unsigned R) const {
> -    return SDValue(Val, R);
> +    return SDValue(Node, R);
>    }
>
>    // isOperandOf - Return true if this node is an operand of N.
> @@ -866,12 +870,12 @@
>                                        unsigned Depth = 2) const;
>
>    /// use_empty - Return true if there are no nodes using value ResNo
> -  /// of node Val.
> +  /// of Node.
>    ///
>    inline bool use_empty() const;
>
>    /// hasOneUse - Return true if there is exactly one node using  
> value
> -  /// ResNo of node Val.
> +  /// ResNo of Node.
>    ///
>    inline bool hasOneUse() const;
>  };
> @@ -885,8 +889,8 @@
>      return SDValue((SDNode*)-1, 0);
>    }
>    static unsigned getHashValue(const SDValue &Val) {
> -    return ((unsigned)((uintptr_t)Val.Val >> 4) ^
> -            (unsigned)((uintptr_t)Val.Val >> 9)) + Val.getResNo();
> +    return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
> +            (unsigned)((uintptr_t)Val.getNode() >> 9)) +  
> Val.getResNo();
>    }
>    static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
>      return LHS == RHS;
> @@ -899,13 +903,13 @@
>  template<> struct simplify_type<SDValue> {
>    typedef SDNode* SimpleType;
>    static SimpleType getSimplifiedValue(const SDValue &Val) {
> -    return static_cast<SimpleType>(Val.Val);
> +    return static_cast<SimpleType>(Val.getNode());
>    }
>  };
>  template<> struct simplify_type<const SDValue> {
>    typedef SDNode* SimpleType;
>    static SimpleType getSimplifiedValue(const SDValue &Val) {
> -    return static_cast<SimpleType>(Val.Val);
> +    return static_cast<SimpleType>(Val.getNode());
>    }
>  };
>
> @@ -949,8 +953,9 @@
>
>    const SDValue& getSDValue() const { return Operand; }
>
> -  SDNode *&getVal() { return Operand.Val; }
> -  SDNode *const &getVal() const { return Operand.Val; }
> +  SDValue &getSDValue() { return Operand; }




This getter is new. Used by type legalizer, to update
node inside of SDValue.



>
> +  SDNode *getVal() { return Operand.getNode(); }



This is a regular getter now. No reference backdoor.

>
> +  SDNode *getVal() const { return Operand.getNode(); } // FIXME:  
> const correct?



Ditto. I'll take care of the constness issue in an upcoming patch.

>    bool operator==(const SDValue &O) const {
>      return Operand == O;
> @@ -1295,7 +1300,7 @@
>      for (unsigned i = 0; i != NumOps; ++i) {
>        OperandList[i] = Ops[i];
>        OperandList[i].setUser(this);
> -      Ops[i].Val->addUse(OperandList[i]);
> +      Ops[i].getNode()->addUse(OperandList[i]);
>      }
>
>      ValueList = VTs.VTs;
> @@ -1365,34 +1370,34 @@
>  // Define inline functions from the SDValue class.
>
>  inline unsigned SDValue::getOpcode() const {
> -  return Val->getOpcode();
> +  return Node->getOpcode();
>  }
>  inline MVT SDValue::getValueType() const {
> -  return Val->getValueType(ResNo);
> +  return Node->getValueType(ResNo);
>  }
>  inline unsigned SDValue::getNumOperands() const {
> -  return Val->getNumOperands();
> +  return Node->getNumOperands();
>  }
>  inline const SDValue &SDValue::getOperand(unsigned i) const {
> -  return Val->getOperand(i);
> +  return Node->getOperand(i);
>  }
>  inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
> -  return Val->getConstantOperandVal(i);
> +  return Node->getConstantOperandVal(i);
>  }
>  inline bool SDValue::isTargetOpcode() const {
> -  return Val->isTargetOpcode();
> +  return Node->isTargetOpcode();
>  }
>  inline bool SDValue::isMachineOpcode() const {
> -  return Val->isMachineOpcode();
> +  return Node->isMachineOpcode();
>  }
>  inline unsigned SDValue::getMachineOpcode() const {
> -  return Val->getMachineOpcode();
> +  return Node->getMachineOpcode();
>  }
>  inline bool SDValue::use_empty() const {
> -  return !Val->hasAnyUseOfValue(ResNo);
> +  return !Node->hasAnyUseOfValue(ResNo);
>  }
>  inline bool SDValue::hasOneUse() const {
> -  return Val->hasNUsesOfValue(1, ResNo);
> +  return Node->hasNUsesOfValue(1, ResNo);
>  }
>
>  /// UnarySDNode - This class is used for single-operand SDNodes.   
> This is solely
> @@ -2212,7 +2217,7 @@
>    }
>
>    pointer operator*() const {
> -    return Node->getOperand(Operand).Val;
> +    return Node->getOperand(Operand).getNode();
>    }
>    pointer operator->() const { return operator*(); }




OK, there are some notable changes in the rest of the patch,
I extract here only the semantically relevant ones:

> ===================================================================
> --- lib/CodeGen/SelectionDAG/LegalizeTypes.h    (Revision 55428)
> +++ lib/CodeGen/SelectionDAG/LegalizeTypes.h    (Arbeitskopie)
> @@ -157,7 +157,8 @@
>    /// for the specified node, adding it to the worklist if ready.
>    void ReanalyzeNode(SDNode *N) {
>      N->setNodeId(NewNode);
> -    AnalyzeNewNode(N);
> +    SDValue V(N, 0);
> +    AnalyzeNewNode(V); // FIXME: ignore the change?
>    }


This does not change the semantics, as the
formerly potentially changed N now is
changed in V. I doubt that this is desired,
suspecting a leak. I would like to hear
Duncan's word on this.


>  private:
> -  void AnalyzeNewNode(SDNode *&N);
> +  void AnalyzeNewNode(SDValue &Val);


The main change in the type legalizer. Change
SDValue::Node instead of the naked reference.

> ===================================================================
> --- lib/CodeGen/SelectionDAG/LegalizeTypes.cpp  (Revision 55428)
> +++ lib/CodeGen/SelectionDAG/LegalizeTypes.cpp  (Arbeitskopie)
>
> @@ -267,11 +268,14 @@
>
>    // Some operands changed - update the node.
>    if (!NewOps.empty())
> -    N = DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0],  
> NewOps.size()).Val;
> +    Val.setNode(DAG.UpdateNodeOperands(SDValue(N, 0),
> +                                      &NewOps[0],
> +                                      NewOps.size()).getNode());
>
> -  N->setNodeId(N->getNumOperands()-NumProcessed);
> -  if (N->getNodeId() == ReadyToProcess)
> -    Worklist.push_back(N);
> +  SDNode * const Nu(Val.getNode());
> +  Nu->setNodeId(Nu->getNumOperands()-NumProcessed);
> +  if (Nu->getNodeId() == ReadyToProcess)
> +    Worklist.push_back(Nu);
>  }


This is the place where the SDValue mutation occurs.
Note that it must use the setNode() setter.




> @@ -313,8 +317,8 @@
>    if (From == To) return;
>
>    // If expansion produced new nodes, make sure they are properly  
> marked.
> -  ExpungeNode(From.Val);
> -  AnalyzeNewNode(To.Val); // Expunges To.
> +  ExpungeNode(From.getNode());
> +  AnalyzeNewNode(To); // Expunges To.

Duncan, this could be probably formulated more
elegantly. I am not knowledgeable on ExpungeNode.


>
>    // Anything that used the old node should now use the new one.   
> Note that this
>    // can potentially cause recursive merging.
> @@ -333,8 +337,11 @@
>
>    // If expansion produced new nodes, make sure they are properly  
> marked.
>    ExpungeNode(From);
> -  AnalyzeNewNode(To); // Expunges To.
>
> +  SDValue ToNode(To, 0);
> +  AnalyzeNewNode(ToNode); // Expunges To.
> +  To = ToNode.getNode();
> +
>    assert(From->getNumValues() == To->getNumValues() &&
>           "Node results don't match");



Here I had to introduce a temporary, to adhere to the
new interface.



> --- lib/Target/PowerPC/PPCISelLowering.cpp      (Revision 55428)
> +++ lib/Target/PowerPC/PPCISelLowering.cpp      (Arbeitskopie)
>
> @@ -2475,14 +2475,14 @@
>      NodeTys.push_back(MVT::Flag);
>      Ops.push_back(Chain);
>      CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
> -    Callee.Val = 0;
> +    Callee.setNode(0);

One of the seldom places where the Node gets set to NULL.
There is another change of this kind in the patch.


>      // Add CTR register as callee so a bctr can be emitted later.
>      if (isTailCall)
>        Ops.push_back(DAG.getRegister(PPC::CTR, getPointerTy()));
>    }



The rest of the patch should be purely syntactic (or repetion of the  
above).

Thanks for any feedback!

Cheers,

	Gabor

From kremenek at apple.com  Wed Aug 27 17:31:52 2008
From: kremenek at apple.com (Ted Kremenek)
Date: Wed, 27 Aug 2008 22:31:52 -0000
Subject: [llvm-commits] [llvm] r55443 - /llvm/tags/checker/checker-83/
Message-ID: <200808272231.m7RMVrGd008183@zion.cs.uiuc.edu>

Author: kremenek
Date: Wed Aug 27 17:31:52 2008
New Revision: 55443

URL: http://llvm.org/viewvc/llvm-project?rev=55443&view=rev
Log:
Tagging checker-83.

Added:
    llvm/tags/checker/checker-83/
      - copied from r55442, llvm/trunk/



From resistor at mac.com  Wed Aug 27 13:58:30 2008
From: resistor at mac.com (Owen Anderson)
Date: Wed, 27 Aug 2008 18:58:30 -0000
Subject: [llvm-commits] [llvm] r55428 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808271858.m7RIwUkA000377@zion.cs.uiuc.edu>

Author: resistor
Date: Wed Aug 27 13:58:30 2008
New Revision: 55428

URL: http://llvm.org/viewvc/llvm-project?rev=55428&view=rev
Log:
Use TargetLowering to get the types in fast isel, which handles pointer types correctly for our purposes.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55428&r1=55427&r2=55428&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Wed Aug 27 13:58:30 2008
@@ -197,8 +197,8 @@
 
 bool FastISel::SelectCast(Instruction *I, ISD::NodeType Opcode,
                           DenseMap<const Value*, unsigned> &ValueMap) {
-  MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
-  MVT DstVT = MVT::getMVT(I->getType());
+  MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
+  MVT DstVT = TLI.getValueType(I->getType());
     
   if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
       DstVT == MVT::Other || !DstVT.isSimple() ||
@@ -231,8 +231,8 @@
   }
 
   // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
-  MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
-  MVT DstVT = MVT::getMVT(I->getType());
+  MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
+  MVT DstVT = TLI.getValueType(I->getType());
   
   if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
       DstVT == MVT::Other || !DstVT.isSimple() ||




From resistor at mac.com  Wed Aug 27 17:30:03 2008
From: resistor at mac.com (Owen Anderson)
Date: Wed, 27 Aug 2008 22:30:03 -0000
Subject: [llvm-commits] [llvm] r55439 - in /llvm/trunk:
 include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808272230.m7RMU3Tn008077@zion.cs.uiuc.edu>

Author: resistor
Date: Wed Aug 27 17:30:02 2008
New Revision: 55439

URL: http://llvm.org/viewvc/llvm-project?rev=55439&view=rev
Log:
Add a helper method that will be used to support EXTRACT_SUBREG for selecting trunc's in fast-isel.

Modified:
    llvm/trunk/include/llvm/CodeGen/FastISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=55439&r1=55438&r2=55439&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Wed Aug 27 17:30:02 2008
@@ -193,6 +193,11 @@
                           const TargetRegisterClass *RC,
                           uint64_t Imm);
 
+  /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
+  /// from a specified index of a superregister.
+  unsigned FastEmitInst_extractsubreg(const TargetRegisterClass *RC,
+                                      unsigned Op0, uint32_t Idx);
+
 private:
   unsigned getRegForValue(Value *V,
                           DenseMap<const Value*, unsigned> &ValueMap);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55439&r1=55438&r2=55439&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Wed Aug 27 17:30:02 2008
@@ -586,3 +586,14 @@
   BuildMI(MBB, II, ResultReg).addImm(Imm);
   return ResultReg;
 }
+
+unsigned FastISel::FastEmitInst_extractsubreg(const TargetRegisterClass *RC,
+                                              unsigned Op0, uint32_t Idx) {
+  const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1);
+  
+  unsigned ResultReg = createResultReg(SRC);
+  const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
+  
+  BuildMI(MBB, II, ResultReg).addReg(Op0);
+  return ResultReg;
+}




From gohman at apple.com  Wed Aug 27 18:52:12 2008
From: gohman at apple.com (Dan Gohman)
Date: Wed, 27 Aug 2008 23:52:12 -0000
Subject: [llvm-commits] [llvm] r55450 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAG.h include/llvm/CodeGen/SelectionDAGISel.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200808272352.m7RNqDWE010999@zion.cs.uiuc.edu>

Author: djg
Date: Wed Aug 27 18:52:12 2008
New Revision: 55450

URL: http://llvm.org/viewvc/llvm-project?rev=55450&view=rev
Log:
Reorganize the lifetimes of the major objects SelectionDAGISel
works with.

SelectionDAG, FunctionLoweringInfo, and SelectionDAGLowering
objects now get created once per SelectionDAGISel instance, and
can be reused across blocks and across functions. Previously,
they were created and destroyed each time they were needed.

This reorganization simplifies the handling of PHI nodes, and
also SwitchCases, JumpTables, and BitTestBlocks. This
simplification has the side effect of fixing a bug in FastISel
where successor PHI nodes weren't being updated correctly.

This is also a step towards making the transition from FastISel
into and out of SelectionDAG faster, and also making
plain SelectionDAG faster on code with lots of little blocks.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=55450&r1=55449&r2=55450&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Aug 27 18:52:12 2008
@@ -66,7 +66,7 @@
 ///
 class SelectionDAG {
   TargetLowering &TLI;
-  MachineFunction &MF;
+  MachineFunction *MF;
   FunctionLoweringInfo &FLI;
   MachineModuleInfo *MMI;
 
@@ -103,16 +103,20 @@
   void VerifyNode(SDNode *N);
 
 public:
-  SelectionDAG(TargetLowering &tli, MachineFunction &mf, 
-               FunctionLoweringInfo &fli, MachineModuleInfo *mmi);
+  SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli);
   ~SelectionDAG();
 
-  /// reset - Clear state and free memory necessary to make this
+  /// init - Prepare this SelectionDAG to process code in the given
+  /// MachineFunction.
+  ///
+  void init(MachineFunction &mf, MachineModuleInfo *mmi);
+
+  /// clear - Clear state and free memory necessary to make this
   /// SelectionDAG ready to process a new block.
   ///
-  void reset();
+  void clear();
 
-  MachineFunction &getMachineFunction() const { return MF; }
+  MachineFunction &getMachineFunction() const { return *MF; }
   const TargetMachine &getTarget() const;
   TargetLowering &getTargetLoweringInfo() const { return TLI; }
   FunctionLoweringInfo &getFunctionLoweringInfo() const { return FLI; }

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=55450&r1=55449&r2=55450&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Wed Aug 27 18:52:12 2008
@@ -39,7 +39,9 @@
 public:
   TargetLowering &TLI;
   MachineRegisterInfo *RegInfo;
+  FunctionLoweringInfo *FuncInfo;
   SelectionDAG *CurDAG;
+  SelectionDAGLowering *SDL;
   MachineBasicBlock *BB;
   AliasAnalysis *AA;
   GCFunctionInfo *GFI;
@@ -47,8 +49,8 @@
   std::vector<SDNode*> TopOrder;
   static char ID;
 
-  explicit SelectionDAGISel(TargetLowering &tli, bool fast = false) : 
-    FunctionPass((intptr_t)&ID), TLI(tli), GFI(), Fast(fast), DAGSize(0) {}
+  explicit SelectionDAGISel(TargetLowering &tli, bool fast = false);
+  virtual ~SelectionDAGISel();
   
   TargetLowering &getTargetLowering() { return TLI; }
 
@@ -87,80 +89,6 @@
   /// to use for this target when scheduling the DAG.
   virtual HazardRecognizer *CreateTargetHazardRecognizer();
   
-  /// CaseBlock - This structure is used to communicate between SDLowering and
-  /// SDISel for the code generation of additional basic blocks needed by multi-
-  /// case switch statements.
-  struct CaseBlock {
-    CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
-              MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
-              MachineBasicBlock *me)
-      : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
-        TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
-    // CC - the condition code to use for the case block's setcc node
-    ISD::CondCode CC;
-    // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
-    // Emit by default LHS op RHS. MHS is used for range comparisons:
-    // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
-    Value *CmpLHS, *CmpMHS, *CmpRHS;
-    // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
-    MachineBasicBlock *TrueBB, *FalseBB;
-    // ThisBB - the block into which to emit the code for the setcc and branches
-    MachineBasicBlock *ThisBB;
-  };
-  struct JumpTable {
-    JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
-              MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
-    
-    /// Reg - the virtual register containing the index of the jump table entry
-    //. to jump to.
-    unsigned Reg;
-    /// JTI - the JumpTableIndex for this jump table in the function.
-    unsigned JTI;
-    /// MBB - the MBB into which to emit the code for the indirect jump.
-    MachineBasicBlock *MBB;
-    /// Default - the MBB of the default bb, which is a successor of the range
-    /// check MBB.  This is when updating PHI nodes in successors.
-    MachineBasicBlock *Default;
-  };
-  struct JumpTableHeader {
-    JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
-                    bool E = false):
-      First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
-    uint64_t First;
-    uint64_t Last;
-    Value *SValue;
-    MachineBasicBlock *HeaderBB;
-    bool Emitted;
-  };
-  typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
-
-  struct BitTestCase {
-    BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
-      Mask(M), ThisBB(T), TargetBB(Tr) { }
-    uint64_t Mask;
-    MachineBasicBlock* ThisBB;
-    MachineBasicBlock* TargetBB;
-  };
-  
-  typedef SmallVector<BitTestCase, 3> BitTestInfo;
-
-  struct BitTestBlock {
-    BitTestBlock(uint64_t F, uint64_t R, Value* SV,
-                 unsigned Rg, bool E,
-                 MachineBasicBlock* P, MachineBasicBlock* D,
-                 const BitTestInfo& C):
-      First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
-      Parent(P), Default(D), Cases(C) { }
-    uint64_t First;
-    uint64_t Range;
-    Value  *SValue;
-    unsigned Reg;
-    bool Emitted;
-    MachineBasicBlock *Parent;
-    MachineBasicBlock *Default;
-    BitTestInfo Cases;
-  };
-  
 protected:
   /// DAGSize - Size of DAG being instruction selected.
   ///
@@ -177,40 +105,23 @@
                     int64_t DesiredMaskS) const;
   
 private:
-  void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
-                            FunctionLoweringInfo &FuncInfo);
-  void FinishBasicBlock(FunctionLoweringInfo &FuncInfo,
-             std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate);
+  void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF);
+  void FinishBasicBlock();
 
   void SelectBasicBlock(BasicBlock *LLVMBB,
                         BasicBlock::iterator Begin,
                         BasicBlock::iterator End,
-                        bool DoArgs,
-             std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
-                        FunctionLoweringInfo &FuncInfo);
+                        bool DoArgs);
   void CodeGenAndEmitDAG();
-  void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL);
+  void LowerArguments(BasicBlock *BB);
   
   void ComputeLiveOutVRegInfo();
 
-  void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB,
-                                       FunctionLoweringInfo &FuncInfo,
-             std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
-                                       SelectionDAGLowering &SDL);
+  void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
 
   /// Pick a safe ordering for instructions for each target node in the
   /// graph.
   ScheduleDAG *Schedule();
-
-  /// SwitchCases - Vector of CaseBlock structures used to communicate
-  /// SwitchInst code generation information.
-  std::vector<CaseBlock> SwitchCases;
-
-  /// JTCases - Vector of JumpTable structures which holds necessary information
-  /// for emitting a jump tables during SwitchInst code generation.
-  std::vector<JumpTableBlock> JTCases;
-
-  std::vector<BitTestBlock> BitTestCases;
 };
 
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=55450&r1=55449&r2=55450&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Aug 27 18:52:12 2008
@@ -765,14 +765,18 @@
   return TLI.getTargetData()->getABITypeAlignment(Ty);
 }
 
-SelectionDAG::SelectionDAG(TargetLowering &tli, MachineFunction &mf,
-                           FunctionLoweringInfo &fli, MachineModuleInfo *mmi)
-  : TLI(tli), MF(mf), FLI(fli), MMI(mmi),
-    EntryNode(ISD::EntryToken, getVTList(MVT::Other)), 
+SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli)
+  : TLI(tli), FLI(fli),
+    EntryNode(ISD::EntryToken, getVTList(MVT::Other)),
     Root(getEntryNode()) {
   AllNodes.push_back(&EntryNode);
 }
 
+void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi) {
+  MF = &mf;
+  MMI = mmi;
+}
+
 SelectionDAG::~SelectionDAG() {
   allnodes_clear();
 }
@@ -789,7 +793,7 @@
   }
 }
 
-void SelectionDAG::reset() {
+void SelectionDAG::clear() {
   allnodes_clear();
   OperandAllocator.Reset();
   CSEMap.clear();

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=55450&r1=55449&r2=55450&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Aug 27 18:52:12 2008
@@ -313,11 +313,16 @@
   class FunctionLoweringInfo {
   public:
     TargetLowering &TLI;
-    Function &Fn;
-    MachineFunction &MF;
-    MachineRegisterInfo &RegInfo;
-
-    FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
+    Function *Fn;
+    MachineFunction *MF;
+    MachineRegisterInfo *RegInfo;
+
+    explicit FunctionLoweringInfo(TargetLowering &TLI);
+
+    /// set - Initialize this FunctionLoweringInfo with the given Function
+    /// and its associated MachineFunction.
+    ///
+    void set(Function &Fn, MachineFunction &MF);
 
     /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
     DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
@@ -338,7 +343,7 @@
 #endif
 
     unsigned MakeReg(MVT VT) {
-      return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
+      return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
     }
     
     /// isExportedInst - Return true if the specified value is an instruction
@@ -364,6 +369,20 @@
     /// LiveOutRegInfo - Information about live out vregs, indexed by their
     /// register number offset by 'FirstVirtualRegister'.
     std::vector<LiveOutInfo> LiveOutRegInfo;
+
+    /// clear - Clear out all the function-specific state. This returns this
+    /// FunctionLoweringInfo to an empty state, ready to be used for a
+    /// different function.
+    void clear() {
+      MBBMap.clear();
+      ValueMap.clear();
+      StaticAllocaMap.clear();
+#ifndef NDEBUG
+      CatchInfoLost.clear();
+      CatchInfoFound.clear();
+#endif
+      LiveOutRegInfo.clear();
+    }
   };
 }
 
@@ -406,13 +425,18 @@
   return true;
 }
 
-FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
-                                           Function &fn, MachineFunction &mf)
-    : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
+FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
+  : TLI(tli) {
+}
+
+void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf) {
+   Fn = &fn;
+   MF = &mf;
+   RegInfo = &MF->getRegInfo();
 
   // Create a vreg for each argument register that is not dead and is used
   // outside of the entry block for the function.
-  for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
+  for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
        AI != E; ++AI)
     if (!isOnlyUsedInEntryBlock(AI))
       InitializeRegForValue(AI);
@@ -420,7 +444,7 @@
   // Initialize the mapping of values to registers.  This is only set up for
   // instruction values that are used outside of the block that defines
   // them.
-  Function::iterator BB = Fn.begin(), EB = Fn.end();
+  Function::iterator BB = Fn->begin(), EB = Fn->end();
   for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
     if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
       if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
@@ -433,7 +457,7 @@
         TySize *= CUI->getZExtValue();   // Get total allocated size.
         if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
         StaticAllocaMap[AI] =
-          MF.getFrameInfo()->CreateStackObject(TySize, Align);
+          MF->getFrameInfo()->CreateStackObject(TySize, Align);
       }
 
   for (; BB != EB; ++BB)
@@ -446,10 +470,10 @@
   // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
   // also creates the initial PHI MachineInstrs, though none of the input
   // operands are populated.
-  for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
+  for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
     MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
     MBBMap[BB] = MBB;
-    MF.push_back(MBB);
+    MF->push_back(MBB);
 
     // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
     // appropriate.
@@ -499,6 +523,84 @@
   return FirstReg;
 }
 
+namespace {
+
+/// CaseBlock - This structure is used to communicate between SDLowering and
+/// SDISel for the code generation of additional basic blocks needed by multi-
+/// case switch statements.
+struct CaseBlock {
+  CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
+            MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
+            MachineBasicBlock *me)
+    : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
+      TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
+  // CC - the condition code to use for the case block's setcc node
+  ISD::CondCode CC;
+  // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
+  // Emit by default LHS op RHS. MHS is used for range comparisons:
+  // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
+  Value *CmpLHS, *CmpMHS, *CmpRHS;
+  // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
+  MachineBasicBlock *TrueBB, *FalseBB;
+  // ThisBB - the block into which to emit the code for the setcc and branches
+  MachineBasicBlock *ThisBB;
+};
+struct JumpTable {
+  JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
+            MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
+  
+  /// Reg - the virtual register containing the index of the jump table entry
+  //. to jump to.
+  unsigned Reg;
+  /// JTI - the JumpTableIndex for this jump table in the function.
+  unsigned JTI;
+  /// MBB - the MBB into which to emit the code for the indirect jump.
+  MachineBasicBlock *MBB;
+  /// Default - the MBB of the default bb, which is a successor of the range
+  /// check MBB.  This is when updating PHI nodes in successors.
+  MachineBasicBlock *Default;
+};
+struct JumpTableHeader {
+  JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
+                  bool E = false):
+    First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
+  uint64_t First;
+  uint64_t Last;
+  Value *SValue;
+  MachineBasicBlock *HeaderBB;
+  bool Emitted;
+};
+typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
+
+struct BitTestCase {
+  BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
+    Mask(M), ThisBB(T), TargetBB(Tr) { }
+  uint64_t Mask;
+  MachineBasicBlock* ThisBB;
+  MachineBasicBlock* TargetBB;
+};
+
+typedef SmallVector<BitTestCase, 3> BitTestInfo;
+
+struct BitTestBlock {
+  BitTestBlock(uint64_t F, uint64_t R, Value* SV,
+               unsigned Rg, bool E,
+               MachineBasicBlock* P, MachineBasicBlock* D,
+               const BitTestInfo& C):
+    First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
+    Parent(P), Default(D), Cases(C) { }
+  uint64_t First;
+  uint64_t Range;
+  Value  *SValue;
+  unsigned Reg;
+  bool Emitted;
+  MachineBasicBlock *Parent;
+  MachineBasicBlock *Default;
+  BitTestInfo Cases;
+};
+
+} // end anonymous namespace
+
 //===----------------------------------------------------------------------===//
 /// SelectionDAGLowering - This is the common target-independent lowering
 /// implementation that is parameterized by a TargetLowering object.
@@ -521,7 +623,7 @@
   /// instruction, but they have no other ordering requirements. We bunch them
   /// up and the emit a single tokenfactor for them just before terminator
   /// instructions.
-  std::vector<SDValue> PendingExports;
+  SmallVector<SDValue, 8> PendingExports;
 
   /// Case - A struct to record the Value for a switch case, and the
   /// case's target basic block.
@@ -599,16 +701,24 @@
   TargetLowering &TLI;
   SelectionDAG &DAG;
   const TargetData *TD;
-  AliasAnalysis &AA;
+  AliasAnalysis *AA;
 
   /// SwitchCases - Vector of CaseBlock structures used to communicate
   /// SwitchInst code generation information.
-  std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
+  std::vector<CaseBlock> SwitchCases;
   /// JTCases - Vector of JumpTable structures used to communicate
   /// SwitchInst code generation information.
-  std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
-  std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
+  std::vector<JumpTableBlock> JTCases;
+  /// BitTestCases - Vector of BitTestBlock structures used to communicate
+  /// SwitchInst code generation information.
+  std::vector<BitTestBlock> BitTestCases;
   
+  std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
+
+  // Emit PHI-node-operand constants only once even if used by multiple
+  // PHI nodes.
+  DenseMap<Constant*, unsigned> ConstantsOut;
+
   /// FuncInfo - Information about the function as a whole.
   ///
   FunctionLoweringInfo &FuncInfo;
@@ -617,11 +727,27 @@
   GCFunctionInfo *GFI;
 
   SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
-                       AliasAnalysis &aa,
-                       FunctionLoweringInfo &funcinfo,
-                       GCFunctionInfo *gfi)
-    : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
-      FuncInfo(funcinfo), GFI(gfi) {
+                       FunctionLoweringInfo &funcinfo)
+    : TLI(tli), DAG(dag), FuncInfo(funcinfo) {
+  }
+
+  void init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
+    AA = &aa;
+    GFI = gfi;
+    TD = DAG.getTarget().getTargetData();
+  }
+
+  /// clear - Clear out the curret SelectionDAG and the associated
+  /// state and prepare this SelectionDAGLowering object to be used
+  /// for a new block. This doesn't clear out information about
+  /// additional blocks that are needed to complete switch lowering
+  /// or PHI node updating; that information is cleared out as it is
+  /// consumed.
+  void clear() {
+    NodeMap.clear();
+    PendingLoads.clear();
+    PendingExports.clear();
+    DAG.clear();
   }
 
   /// getRoot - Return the current virtual root of the Selection DAG,
@@ -741,14 +867,13 @@
                                 CaseRecVector& WorkList,
                                 Value* SV,
                                 MachineBasicBlock* Default);  
-  void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
-  void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
+  void visitSwitchCase(CaseBlock &CB);
+  void visitBitTestHeader(BitTestBlock &B);
   void visitBitTestCase(MachineBasicBlock* NextMBB,
                         unsigned Reg,
-                        SelectionDAGISel::BitTestCase &B);
-  void visitJumpTable(SelectionDAGISel::JumpTable &JT);
-  void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
-                            SelectionDAGISel::JumpTableHeader &JTH);
+                        BitTestCase &B);
+  void visitJumpTable(JumpTable &JT);
+  void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH);
   
   // These all get lowered before this pass.
   void visitInvoke(InvokeInst &I);
@@ -1437,15 +1562,15 @@
         assert(0 && "Unknown compare instruction");
       }
       
-      SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 
-                                     BOp->getOperand(1), NULL, TBB, FBB, CurBB);
+      CaseBlock CB(Condition, BOp->getOperand(0), 
+                   BOp->getOperand(1), NULL, TBB, FBB, CurBB);
       SwitchCases.push_back(CB);
       return;
     }
     
     // Create a CaseBlock record representing this branch.
-    SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
-                                   NULL, TBB, FBB, CurBB);
+    CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
+                 NULL, TBB, FBB, CurBB);
     SwitchCases.push_back(CB);
     return;
   }
@@ -1494,7 +1619,7 @@
 /// If we should emit this as a bunch of and/or'd together conditions, return
 /// false.
 static bool 
-ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
+ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
   if (Cases.size() != 2) return true;
   
   // If this is two comparisons of the same values or'd or and'd together, they
@@ -1583,8 +1708,8 @@
   }
   
   // Create a CaseBlock record representing this branch.
-  SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
-                                 NULL, Succ0MBB, Succ1MBB, CurMBB);
+  CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
+               NULL, Succ0MBB, Succ1MBB, CurMBB);
   // Use visitSwitchCase to actually insert the fast branch sequence for this
   // cond branch.
   visitSwitchCase(CB);
@@ -1592,7 +1717,7 @@
 
 /// visitSwitchCase - Emits the necessary code to represent a single node in
 /// the binary search tree resulting from lowering a switch instruction.
-void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
+void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
   SDValue Cond;
   SDValue CondLHS = getValue(CB.CmpLHS);
   
@@ -1664,7 +1789,7 @@
 }
 
 /// visitJumpTable - Emit JumpTable node in the current MBB
-void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
+void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
   // Emit the code for the jump table
   assert(JT.Reg != -1U && "Should lower JT Header first!");
   MVT PTy = TLI.getPointerTy();
@@ -1677,8 +1802,8 @@
 
 /// visitJumpTableHeader - This function emits necessary code to produce index
 /// in the JumpTable from switch case.
-void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
-                                         SelectionDAGISel::JumpTableHeader &JTH) {
+void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
+                                                JumpTableHeader &JTH) {
   // Subtract the lowest switch case value from the value being switched on
   // and conditional branch to default mbb if the result is greater than the
   // difference between smallest and largest cases.
@@ -1729,7 +1854,7 @@
 
 /// visitBitTestHeader - This function emits necessary code to produce value
 /// suitable for "bit tests"
-void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
+void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
   // Subtract the minimum value
   SDValue SwitchOp = getValue(B.SValue);
   MVT VT = SwitchOp.getValueType();
@@ -1783,7 +1908,7 @@
 /// visitBitTestCase - this function produces one "bit test"
 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
                                             unsigned Reg,
-                                            SelectionDAGISel::BitTestCase &B) {
+                                            BitTestCase &B) {
   // Emit bit tests and jumps
   SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg, 
                                            TLI.getPointerTy());
@@ -1911,8 +2036,7 @@
       CC = ISD::SETLE;
       LHS = I->Low; MHS = SV; RHS = I->High;
     }
-    SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
-                                   I->BB, FallThrough, CurBlock);
+    CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
     
     // If emitting the first comparison, just call visitSwitchCase to emit the
     // code into the current block.  Otherwise, push the CaseBlock onto the
@@ -2019,13 +2143,12 @@
   
   // Set the jump table information so that we can codegen it as a second
   // MachineBasicBlock
-  SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
-  SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
-                                        (CR.CaseBB == CurMBB));
+  JumpTable JT(-1U, JTI, JumpTableBB, Default);
+  JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
   if (CR.CaseBB == CurMBB)
     visitJumpTableHeader(JT, JTH);
         
-  JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
+  JTCases.push_back(JumpTableBlock(JTH, JT));
 
   return true;
 }
@@ -2139,8 +2262,7 @@
   // Create a CaseBlock record representing a conditional branch to
   // the LHS node if the value being switched on SV is less than C. 
   // Otherwise, branch to LHS.
-  SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
-                                 TrueBB, FalseBB, CR.CaseBB);
+  CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
 
   if (CR.CaseBB == CurMBB)
     visitSwitchCase(CB);
@@ -2241,7 +2363,7 @@
   }
   std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
   
-  SelectionDAGISel::BitTestInfo BTC;
+  BitTestInfo BTC;
 
   // Figure out which block is immediately after the current one.
   MachineFunction::iterator BBI = CR.CaseBB;
@@ -2256,14 +2378,14 @@
 
     MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
     CurMF->insert(BBI, CaseBB);
-    BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
-                                                CaseBB,
-                                                CasesBits[i].BB));
+    BTC.push_back(BitTestCase(CasesBits[i].Mask,
+                              CaseBB,
+                              CasesBits[i].BB));
   }
   
-  SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
-                                     -1U, (CR.CaseBB == CurMBB),
-                                     CR.CaseBB, Default, BTC);
+  BitTestBlock BTB(lowBound, range, SV,
+                   -1U, (CR.CaseBB == CurMBB),
+                   CR.CaseBB, Default, BTC);
 
   if (CR.CaseBB == CurMBB)
     visitBitTestHeader(BTB);
@@ -2906,7 +3028,7 @@
   if (I.isVolatile())
     // Serialize volatile loads with other side effects.
     Root = getRoot();
-  else if (AA.pointsToConstantMemory(SV)) {
+  else if (AA->pointsToConstantMemory(SV)) {
     // Do not serialize (non-volatile) loads of constant memory with anything.
     Root = DAG.getEntryNode();
     ConstantMemory = true;
@@ -3188,7 +3310,7 @@
     uint64_t Size = -1ULL;
     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
       Size = C->getValue();
-    if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
+    if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
         AliasAnalysis::NoAlias) {
       DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
                                 I.getOperand(1), 0, I.getOperand(2), 0));
@@ -4885,6 +5007,22 @@
 // SelectionDAGISel code
 //===----------------------------------------------------------------------===//
 
+SelectionDAGISel::SelectionDAGISel(TargetLowering &tli, bool fast) :
+  FunctionPass((intptr_t)&ID), TLI(tli),
+  FuncInfo(new FunctionLoweringInfo(TLI)),
+  CurDAG(new SelectionDAG(TLI, *FuncInfo)),
+  SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo)),
+  GFI(),
+  Fast(fast),
+  DAGSize(0)
+{}
+
+SelectionDAGISel::~SelectionDAGISel() {
+  delete SDL;
+  delete CurDAG;
+  delete FuncInfo;
+}
+
 unsigned SelectionDAGISel::MakeReg(MVT VT) {
   return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
 }
@@ -4907,28 +5045,32 @@
   RegInfo = &MF.getRegInfo();
   DOUT << "\n\n\n=== " << Fn.getName() << "\n";
 
-  FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
+  FuncInfo->set(Fn, MF);
+  CurDAG->init(MF, getAnalysisToUpdate<MachineModuleInfo>());
+  SDL->init(GFI, *AA);
 
   for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
     if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
       // Mark landing pad.
-      FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
+      FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
 
-  SelectAllBasicBlocks(Fn, MF, FuncInfo);
+  SelectAllBasicBlocks(Fn, MF);
 
   // Add function live-ins to entry block live-in set.
   BasicBlock *EntryBB = &Fn.getEntryBlock();
-  BB = FuncInfo.MBBMap[EntryBB];
+  BB = FuncInfo->MBBMap[EntryBB];
   if (!RegInfo->livein_empty())
     for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
            E = RegInfo->livein_end(); I != E; ++I)
       BB->addLiveIn(I->first);
 
 #ifndef NDEBUG
-  assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
+  assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
          "Not all catch info was assigned to a landing pad!");
 #endif
 
+  FuncInfo->clear();
+
   return true;
 }
 
@@ -4946,13 +5088,12 @@
 }
 
 void SelectionDAGISel::
-LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
+LowerArguments(BasicBlock *LLVMBB) {
   // If this is the entry block, emit arguments.
   Function &F = *LLVMBB->getParent();
-  FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
-  SDValue OldRoot = SDL.DAG.getRoot();
+  SDValue OldRoot = SDL->DAG.getRoot();
   SmallVector<SDValue, 16> Args;
-  TLI.LowerArguments(F, SDL.DAG, Args);
+  TLI.LowerArguments(F, SDL->DAG, Args);
 
   unsigned a = 0;
   for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
@@ -4961,12 +5102,12 @@
     ComputeValueVTs(TLI, AI->getType(), ValueVTs);
     unsigned NumValues = ValueVTs.size();
     if (!AI->use_empty()) {
-      SDL.setValue(AI, SDL.DAG.getMergeValues(&Args[a], NumValues));
+      SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues));
       // If this argument is live outside of the entry block, insert a copy from
       // whereever we got it to the vreg that other BB's will reference it as.
-      DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
-      if (VMI != FuncInfo.ValueMap.end()) {
-        SDL.CopyValueToVirtualRegister(AI, VMI->second);
+      DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo->ValueMap.find(AI);
+      if (VMI != FuncInfo->ValueMap.end()) {
+        SDL->CopyValueToVirtualRegister(AI, VMI->second);
       }
     }
     a += NumValues;
@@ -4974,7 +5115,7 @@
 
   // Finally, if the target has anything special to do, allow it to do so.
   // FIXME: this should insert code into the DAG!
-  EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
+  EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
 }
 
 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
@@ -5107,31 +5248,21 @@
 /// the end.
 ///
 void
-SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB,
-                                                 FunctionLoweringInfo &FuncInfo,
-             std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
-                                                  SelectionDAGLowering &SDL) {
+SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
   TerminatorInst *TI = LLVMBB->getTerminator();
 
-  // Emit constants only once even if used by multiple PHI nodes.
-  std::map<Constant*, unsigned> ConstantsOut;
-  
-  BitVector SuccsHandled;
-  if (TI->getNumSuccessors())
-    SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
-    
+  SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
+
   // Check successor nodes' PHI nodes that expect a constant to be available
   // from this block.
   for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
     BasicBlock *SuccBB = TI->getSuccessor(succ);
     if (!isa<PHINode>(SuccBB->begin())) continue;
-    MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
+    MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
     
     // If this terminator has multiple identical successors (common for
     // switches), only handle each succ once.
-    unsigned SuccMBBNo = SuccMBB->getNumber();
-    if (SuccsHandled[SuccMBBNo]) continue;
-    SuccsHandled[SuccMBBNo] = true;
+    if (!SuccsHandled.insert(SuccMBB)) continue;
     
     MachineBasicBlock::iterator MBBI = SuccMBB->begin();
     PHINode *PN;
@@ -5143,25 +5274,25 @@
          (PN = dyn_cast<PHINode>(I)); ++I) {
       // Ignore dead phi's.
       if (PN->use_empty()) continue;
-      
+
       unsigned Reg;
       Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
-      
+
       if (Constant *C = dyn_cast<Constant>(PHIOp)) {
-        unsigned &RegOut = ConstantsOut[C];
+        unsigned &RegOut = SDL->ConstantsOut[C];
         if (RegOut == 0) {
-          RegOut = FuncInfo.CreateRegForValue(C);
-          SDL.CopyValueToVirtualRegister(C, RegOut);
+          RegOut = FuncInfo->CreateRegForValue(C);
+          SDL->CopyValueToVirtualRegister(C, RegOut);
         }
         Reg = RegOut;
       } else {
-        Reg = FuncInfo.ValueMap[PHIOp];
+        Reg = FuncInfo->ValueMap[PHIOp];
         if (Reg == 0) {
           assert(isa<AllocaInst>(PHIOp) &&
-                 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
+                 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
                  "Didn't codegen value into a register!??");
-          Reg = FuncInfo.CreateRegForValue(PHIOp);
-          SDL.CopyValueToVirtualRegister(PHIOp, Reg);
+          Reg = FuncInfo->CreateRegForValue(PHIOp);
+          SDL->CopyValueToVirtualRegister(PHIOp, Reg);
         }
       }
 
@@ -5173,39 +5304,26 @@
         MVT VT = ValueVTs[vti];
         unsigned NumRegisters = TLI.getNumRegisters(VT);
         for (unsigned i = 0, e = NumRegisters; i != e; ++i)
-          PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
+          SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
         Reg += NumRegisters;
       }
     }
   }
-  ConstantsOut.clear();
+  SDL->ConstantsOut.clear();
 
   // Lower the terminator after the copies are emitted.
-  SDL.visit(*LLVMBB->getTerminator());
-
-  // Copy over any CaseBlock records that may now exist due to SwitchInst
-  // lowering, as well as any jump table information.
-  SwitchCases.clear();
-  SwitchCases = SDL.SwitchCases;
-  JTCases.clear();
-  JTCases = SDL.JTCases;
-  BitTestCases.clear();
-  BitTestCases = SDL.BitTestCases;
+  SDL->visit(*LLVMBB->getTerminator());
 }
 
 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
                                         BasicBlock::iterator Begin,
                                         BasicBlock::iterator End,
-                                        bool DoArgs,
-       std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
-                                        FunctionLoweringInfo &FuncInfo) {
-  SelectionDAGLowering SDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
-
+                                        bool DoArgs) {
   // Lower any arguments needed in this block if this is the entry block.
   if (DoArgs)
-    LowerArguments(LLVMBB, SDL);
+    LowerArguments(LLVMBB);
 
-  SDL.setCurrentBasicBlock(BB);
+  SDL->setCurrentBasicBlock(BB);
 
   MachineModuleInfo *MMI = CurDAG->getMachineModuleInfo();
 
@@ -5245,30 +5363,30 @@
 
       if (I == E)
         // No catch info found - try to extract some from the successor.
-        copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
+        copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
     }
   }
 
   // Lower all of the non-terminator instructions.
   for (BasicBlock::iterator I = Begin; I != End; ++I)
     if (!isa<TerminatorInst>(I))
-      SDL.visit(*I);
+      SDL->visit(*I);
 
   // Ensure that all instructions which are used outside of their defining
   // blocks are available as virtual registers.  Invoke is handled elsewhere.
   for (BasicBlock::iterator I = Begin; I != End; ++I)
     if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
-      DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
-      if (VMI != FuncInfo.ValueMap.end())
-        SDL.CopyValueToVirtualRegister(I, VMI->second);
+      DenseMap<const Value*,unsigned>::iterator VMI =FuncInfo->ValueMap.find(I);
+      if (VMI != FuncInfo->ValueMap.end())
+        SDL->CopyValueToVirtualRegister(I, VMI->second);
     }
 
   // Handle PHI nodes in successor blocks.
   if (Begin != End && End == LLVMBB->end())
-    HandlePHINodesInSuccessorBlocks(LLVMBB, FuncInfo, PHINodesToUpdate, SDL);
+    HandlePHINodesInSuccessorBlocks(LLVMBB);
     
   // Make sure the root of the DAG is up-to-date.
-  CurDAG->setRoot(SDL.getControlRoot());
+  CurDAG->setRoot(SDL->getControlRoot());
 
   // Check whether calls in this block are real tail calls. Fix up CALL nodes
   // with correct tailcall attribute so that the target can rely on the tailcall
@@ -5278,7 +5396,7 @@
 
   // Final step, emit the lowered DAG as machine code.
   CodeGenAndEmitDAG();
-  CurDAG->reset();
+  SDL->clear();
 }
 
 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
@@ -5457,18 +5575,10 @@
   DEBUG(BB->dump());
 }  
 
-void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
-                                            FunctionLoweringInfo &FuncInfo) {
-  // Define the SelectionDAG here so that memory allocation is reused for
-  // each basic block.
-  SelectionDAG DAG(TLI, MF, FuncInfo, 
-                   getAnalysisToUpdate<MachineModuleInfo>());
-  CurDAG = &DAG;
-
-  std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
+void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF) {
   for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
     BasicBlock *LLVMBB = &*I;
-    BB = FuncInfo.MBBMap[LLVMBB];
+    BB = FuncInfo->MBBMap[LLVMBB];
 
     BasicBlock::iterator Begin = LLVMBB->begin();
     BasicBlock::iterator End = LLVMBB->end();
@@ -5477,10 +5587,10 @@
     // Before doing SelectionDAG ISel, see if FastISel has been requested.
     // FastISel doesn't support EH landing pads, which require special handling.
     if (EnableFastISel && !BB->isLandingPad()) {
-      if (FastISel *F = TLI.createFastISel(FuncInfo.MF)) {
+      if (FastISel *F = TLI.createFastISel(*FuncInfo->MF)) {
         while (Begin != End) {
-          Begin = F->SelectInstructions(Begin, End, FuncInfo.ValueMap,
-                                        FuncInfo.MBBMap, BB);
+          Begin = F->SelectInstructions(Begin, End, FuncInfo->ValueMap,
+                                        FuncInfo->MBBMap, BB);
 
           if (Begin == End)
             // The "fast" selector selected the entire block, so we're done.
@@ -5490,13 +5600,12 @@
           if (isa<CallInst>(Begin) || isa<LoadInst>(Begin) ||
               isa<StoreInst>(Begin)) {
             if (Begin->getType() != Type::VoidTy) {
-              unsigned &R = FuncInfo.ValueMap[Begin];
+              unsigned &R = FuncInfo->ValueMap[Begin];
               if (!R)
-                R = FuncInfo.CreateRegForValue(Begin);
+                R = FuncInfo->CreateRegForValue(Begin);
             }
 
-            SelectBasicBlock(LLVMBB, Begin, next(Begin), DoArgs,
-                             PHINodesToUpdate, FuncInfo);
+            SelectBasicBlock(LLVMBB, Begin, next(Begin), DoArgs);
 
             ++Begin;
             DoArgs = false;
@@ -5522,18 +5631,14 @@
     }
 
     if (Begin != End || DoArgs)
-      SelectBasicBlock(LLVMBB, Begin, End, DoArgs, PHINodesToUpdate, FuncInfo);
+      SelectBasicBlock(LLVMBB, Begin, End, DoArgs);
 
-    FinishBasicBlock(FuncInfo, PHINodesToUpdate);
-    PHINodesToUpdate.clear();
+    FinishBasicBlock();
   }
-
-  CurDAG = 0;
 }
 
 void
-SelectionDAGISel::FinishBasicBlock(FunctionLoweringInfo &FuncInfo,
-             std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate) {
+SelectionDAGISel::FinishBasicBlock() {
 
   // Perform target specific isel post processing.
   InstructionSelectPostProcessing();
@@ -5542,146 +5647,148 @@
   DEBUG(BB->dump());
 
   DOUT << "Total amount of phi nodes to update: "
-       << PHINodesToUpdate.size() << "\n";
-  DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
-          DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
-               << ", " << PHINodesToUpdate[i].second << ")\n";);
+       << SDL->PHINodesToUpdate.size() << "\n";
+  DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i)
+          DOUT << "Node " << i << " : (" << SDL->PHINodesToUpdate[i].first
+               << ", " << SDL->PHINodesToUpdate[i].second << ")\n";);
   
   // Next, now that we know what the last MBB the LLVM BB expanded is, update
   // PHI nodes in successors.
-  if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
-    for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
-      MachineInstr *PHI = PHINodesToUpdate[i].first;
+  if (SDL->SwitchCases.empty() &&
+      SDL->JTCases.empty() &&
+      SDL->BitTestCases.empty()) {
+    for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
+      MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
       assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
              "This is not a machine PHI node that we are updating!");
-      PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
+      PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
                                                 false));
       PHI->addOperand(MachineOperand::CreateMBB(BB));
     }
+    SDL->PHINodesToUpdate.clear();
     return;
   }
 
-  for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
+  for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) {
     // Lower header first, if it wasn't already lowered
-    if (!BitTestCases[i].Emitted) {
-      SelectionDAGLowering HSDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
+    if (!SDL->BitTestCases[i].Emitted) {
       // Set the current basic block to the mbb we wish to insert the code into
-      BB = BitTestCases[i].Parent;
-      HSDL.setCurrentBasicBlock(BB);
+      BB = SDL->BitTestCases[i].Parent;
+      SDL->setCurrentBasicBlock(BB);
       // Emit the code
-      HSDL.visitBitTestHeader(BitTestCases[i]);
-      CurDAG->setRoot(HSDL.getRoot());
+      SDL->visitBitTestHeader(SDL->BitTestCases[i]);
+      CurDAG->setRoot(SDL->getRoot());
       CodeGenAndEmitDAG();
-      CurDAG->reset();
+      SDL->clear();
     }    
 
-    for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
-      SelectionDAGLowering BSDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
+    for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) {
       // Set the current basic block to the mbb we wish to insert the code into
-      BB = BitTestCases[i].Cases[j].ThisBB;
-      BSDL.setCurrentBasicBlock(BB);
+      BB = SDL->BitTestCases[i].Cases[j].ThisBB;
+      SDL->setCurrentBasicBlock(BB);
       // Emit the code
       if (j+1 != ej)
-        BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
-                              BitTestCases[i].Reg,
-                              BitTestCases[i].Cases[j]);
+        SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB,
+                              SDL->BitTestCases[i].Reg,
+                              SDL->BitTestCases[i].Cases[j]);
       else
-        BSDL.visitBitTestCase(BitTestCases[i].Default,
-                              BitTestCases[i].Reg,
-                              BitTestCases[i].Cases[j]);
+        SDL->visitBitTestCase(SDL->BitTestCases[i].Default,
+                              SDL->BitTestCases[i].Reg,
+                              SDL->BitTestCases[i].Cases[j]);
         
         
-      CurDAG->setRoot(BSDL.getRoot());
+      CurDAG->setRoot(SDL->getRoot());
       CodeGenAndEmitDAG();
-      CurDAG->reset();
+      SDL->clear();
     }
 
     // Update PHI Nodes
-    for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
-      MachineInstr *PHI = PHINodesToUpdate[pi].first;
+    for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
+      MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
       MachineBasicBlock *PHIBB = PHI->getParent();
       assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
              "This is not a machine PHI node that we are updating!");
       // This is "default" BB. We have two jumps to it. From "header" BB and
       // from last "case" BB.
-      if (PHIBB == BitTestCases[i].Default) {
-        PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
+      if (PHIBB == SDL->BitTestCases[i].Default) {
+        PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
                                                   false));
-        PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
-        PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
+        PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent));
+        PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
                                                   false));
-        PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
+        PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases.
                                                   back().ThisBB));
       }
       // One of "cases" BB.
-      for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
-        MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
+      for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size();
+           j != ej; ++j) {
+        MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB;
         if (cBB->succ_end() !=
             std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
-          PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
+          PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
                                                     false));
           PHI->addOperand(MachineOperand::CreateMBB(cBB));
         }
       }
     }
   }
+  SDL->BitTestCases.clear();
 
   // If the JumpTable record is filled in, then we need to emit a jump table.
   // Updating the PHI nodes is tricky in this case, since we need to determine
   // whether the PHI is a successor of the range check MBB or the jump table MBB
-  for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
+  for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) {
     // Lower header first, if it wasn't already lowered
-    if (!JTCases[i].first.Emitted) {
-      SelectionDAGLowering HSDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
+    if (!SDL->JTCases[i].first.Emitted) {
       // Set the current basic block to the mbb we wish to insert the code into
-      BB = JTCases[i].first.HeaderBB;
-      HSDL.setCurrentBasicBlock(BB);
+      BB = SDL->JTCases[i].first.HeaderBB;
+      SDL->setCurrentBasicBlock(BB);
       // Emit the code
-      HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
-      CurDAG->setRoot(HSDL.getRoot());
+      SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first);
+      CurDAG->setRoot(SDL->getRoot());
       CodeGenAndEmitDAG();
-      CurDAG->reset();
+      SDL->clear();
     }
     
-    SelectionDAGLowering JSDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
     // Set the current basic block to the mbb we wish to insert the code into
-    BB = JTCases[i].second.MBB;
-    JSDL.setCurrentBasicBlock(BB);
+    BB = SDL->JTCases[i].second.MBB;
+    SDL->setCurrentBasicBlock(BB);
     // Emit the code
-    JSDL.visitJumpTable(JTCases[i].second);
-    CurDAG->setRoot(JSDL.getRoot());
+    SDL->visitJumpTable(SDL->JTCases[i].second);
+    CurDAG->setRoot(SDL->getRoot());
     CodeGenAndEmitDAG();
-    CurDAG->reset();
+    SDL->clear();
     
     // Update PHI Nodes
-    for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
-      MachineInstr *PHI = PHINodesToUpdate[pi].first;
+    for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
+      MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
       MachineBasicBlock *PHIBB = PHI->getParent();
       assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
              "This is not a machine PHI node that we are updating!");
       // "default" BB. We can go there only from header BB.
-      if (PHIBB == JTCases[i].second.Default) {
-        PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
+      if (PHIBB == SDL->JTCases[i].second.Default) {
+        PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
                                                   false));
-        PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
+        PHI->addOperand(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB));
       }
       // JT BB. Just iterate over successors here
       if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
-        PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
+        PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
                                                   false));
         PHI->addOperand(MachineOperand::CreateMBB(BB));
       }
     }
   }
+  SDL->JTCases.clear();
   
   // If the switch block involved a branch to one of the actual successors, we
   // need to update PHI nodes in that block.
-  for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
-    MachineInstr *PHI = PHINodesToUpdate[i].first;
+  for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
+    MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
     assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
            "This is not a machine PHI node that we are updating!");
     if (BB->isSuccessor(PHI->getParent())) {
-      PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
+      PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
                                                 false));
       PHI->addOperand(MachineOperand::CreateMBB(BB));
     }
@@ -5689,48 +5796,50 @@
   
   // If we generated any switch lowering information, build and codegen any
   // additional DAGs necessary.
-  for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
-    SelectionDAGLowering SDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
-    
+  for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) {
     // Set the current basic block to the mbb we wish to insert the code into
-    BB = SwitchCases[i].ThisBB;
-    SDL.setCurrentBasicBlock(BB);
+    BB = SDL->SwitchCases[i].ThisBB;
+    SDL->setCurrentBasicBlock(BB);
     
     // Emit the code
-    SDL.visitSwitchCase(SwitchCases[i]);
-    CurDAG->setRoot(SDL.getRoot());
+    SDL->visitSwitchCase(SDL->SwitchCases[i]);
+    CurDAG->setRoot(SDL->getRoot());
     CodeGenAndEmitDAG();
-    CurDAG->reset();
+    SDL->clear();
     
     // Handle any PHI nodes in successors of this chunk, as if we were coming
     // from the original BB before switch expansion.  Note that PHI nodes can
     // occur multiple times in PHINodesToUpdate.  We have to be very careful to
     // handle them the right number of times.
-    while ((BB = SwitchCases[i].TrueBB)) {  // Handle LHS and RHS.
+    while ((BB = SDL->SwitchCases[i].TrueBB)) {  // Handle LHS and RHS.
       for (MachineBasicBlock::iterator Phi = BB->begin();
            Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
         // This value for this PHI node is recorded in PHINodesToUpdate, get it.
         for (unsigned pn = 0; ; ++pn) {
-          assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
-          if (PHINodesToUpdate[pn].first == Phi) {
-            Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
+          assert(pn != SDL->PHINodesToUpdate.size() &&
+                 "Didn't find PHI entry!");
+          if (SDL->PHINodesToUpdate[pn].first == Phi) {
+            Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn].
                                                       second, false));
-            Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
+            Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB));
             break;
           }
         }
       }
       
       // Don't process RHS if same block as LHS.
-      if (BB == SwitchCases[i].FalseBB)
-        SwitchCases[i].FalseBB = 0;
+      if (BB == SDL->SwitchCases[i].FalseBB)
+        SDL->SwitchCases[i].FalseBB = 0;
       
       // If we haven't handled the RHS, do so now.  Otherwise, we're done.
-      SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
-      SwitchCases[i].FalseBB = 0;
+      SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB;
+      SDL->SwitchCases[i].FalseBB = 0;
     }
-    assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
+    assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0);
   }
+  SDL->SwitchCases.clear();
+
+  SDL->PHINodesToUpdate.clear();
 }
 
 




From gohman at apple.com  Wed Aug 27 19:20:08 2008
From: gohman at apple.com (Dan Gohman)
Date: Thu, 28 Aug 2008 00:20:08 -0000
Subject: [llvm-commits] [llvm] r55451 - /llvm/trunk/include/llvm/Argument.h
Message-ID: <200808280020.m7S0K8PL011781@zion.cs.uiuc.edu>

Author: djg
Date: Wed Aug 27 19:20:07 2008
New Revision: 55451

URL: http://llvm.org/viewvc/llvm-project?rev=55451&view=rev
Log:
Fix a missing #include. Patch by Andrew John Hughes.

Modified:
    llvm/trunk/include/llvm/Argument.h

Modified: llvm/trunk/include/llvm/Argument.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Argument.h?rev=55451&r1=55450&r2=55451&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Argument.h (original)
+++ llvm/trunk/include/llvm/Argument.h Wed Aug 27 19:20:07 2008
@@ -16,6 +16,7 @@
 
 #include "llvm/Value.h"
 #include "llvm/ParameterAttributes.h"
+#include "llvm/ADT/ilist_node.h"
 
 namespace llvm {
 




From kremenek at apple.com  Wed Aug 27 20:19:16 2008
From: kremenek at apple.com (Ted Kremenek)
Date: Thu, 28 Aug 2008 01:19:16 -0000
Subject: [llvm-commits] [llvm] r55453 - /llvm/tags/checker/checker-84/
Message-ID: <200808280119.m7S1JGnq013543@zion.cs.uiuc.edu>

Author: kremenek
Date: Wed Aug 27 20:19:15 2008
New Revision: 55453

URL: http://llvm.org/viewvc/llvm-project?rev=55453&view=rev
Log:
Tagging checker-84.

Added:
    llvm/tags/checker/checker-84/
      - copied from r55452, llvm/trunk/



From dalej at apple.com  Wed Aug 27 20:51:09 2008
From: dalej at apple.com (Dale Johannesen)
Date: Thu, 28 Aug 2008 01:51:09 -0000
Subject: [llvm-commits] [llvm] r55456 -
	/llvm/trunk/test/CodeGen/X86/fast-isel.ll
Message-ID: <200808280151.m7S1p9SQ014491@zion.cs.uiuc.edu>

Author: johannes
Date: Wed Aug 27 20:51:09 2008
New Revision: 55456

URL: http://llvm.org/viewvc/llvm-project?rev=55456&view=rev
Log:
This test crashes on non-x86 host; make SSE explicit.
Feel free to fix a better way!


Modified:
    llvm/trunk/test/CodeGen/X86/fast-isel.ll

Modified: llvm/trunk/test/CodeGen/X86/fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel.ll?rev=55456&r1=55455&r2=55456&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel.ll Wed Aug 27 20:51:09 2008
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast-isel -march=x86
+; RUN: llvm-as < %s | llc -fast-isel -march=x86 -mattr=sse2
 
 ; This tests very minimal fast-isel functionality.
 




From dalej at apple.com  Wed Aug 27 21:44:50 2008
From: dalej at apple.com (Dale Johannesen)
Date: Thu, 28 Aug 2008 02:44:50 -0000
Subject: [llvm-commits] [llvm] r55457 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAGNodes.h
 include/llvm/Target/TargetLowering.h
 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
 lib/Target/TargetSelectionDAG.td lib/Target/X86/X86ISelLowering.cpp
 lib/Target/X86/X86Instr64bit.td lib/Target/X86/X86InstrInfo.td
Message-ID: <200808280244.m7S2ioDI016151@zion.cs.uiuc.edu>

Author: johannes
Date: Wed Aug 27 21:44:49 2008
New Revision: 55457

URL: http://llvm.org/viewvc/llvm-project?rev=55457&view=rev
Log:
Split the ATOMIC NodeType's to include the size, e.g.
ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.

This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad.  This is the alternative.


Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
    llvm/trunk/include/llvm/Target/TargetLowering.h
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/trunk/lib/Target/TargetSelectionDAG.td
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86Instr64bit.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=55457&r1=55456&r2=55457&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Aug 27 21:44:49 2008
@@ -58,6 +58,8 @@
 /// ISD namespace - This namespace contains an enum which represents all of the
 /// SelectionDAG node types and value types.
 ///
+/// If you add new elements here you should increase OpActionsCapacity in
+/// TargetLowering.h by the number of new elements.
 namespace ISD {
 
   //===--------------------------------------------------------------------===//
@@ -589,38 +591,64 @@
     // this corresponds to the atomic.lcs intrinsic.
     // cmp is compared to *ptr, and if equal, swap is stored in *ptr.
     // the return is always the original value in *ptr
-    ATOMIC_CMP_SWAP,
-
-    // Val, OUTCHAIN = ATOMIC_LOAD_ADD(INCHAIN, ptr, amt)
-    // this corresponds to the atomic.las intrinsic.
-    // *ptr + amt is stored to *ptr atomically.
-    // the return is always the original value in *ptr
-    ATOMIC_LOAD_ADD,
+    ATOMIC_CMP_SWAP_8,
+    ATOMIC_CMP_SWAP_16,
+    ATOMIC_CMP_SWAP_32,
+    ATOMIC_CMP_SWAP_64,
 
     // Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)
     // this corresponds to the atomic.swap intrinsic.
     // amt is stored to *ptr atomically.
     // the return is always the original value in *ptr
-    ATOMIC_SWAP,
+    ATOMIC_SWAP_8,
+    ATOMIC_SWAP_16,
+    ATOMIC_SWAP_32,
+    ATOMIC_SWAP_64,
 
-    // Val, OUTCHAIN = ATOMIC_LOAD_SUB(INCHAIN, ptr, amt)
-    // this corresponds to the atomic.lss intrinsic.
-    // *ptr - amt is stored to *ptr atomically.
-    // the return is always the original value in *ptr
-    ATOMIC_LOAD_SUB,
-    
     // Val, OUTCHAIN = ATOMIC_L[OpName]S(INCHAIN, ptr, amt)
     // this corresponds to the atomic.[OpName] intrinsic.
     // op(*ptr, amt) is stored to *ptr atomically.
     // the return is always the original value in *ptr
-    ATOMIC_LOAD_AND,
-    ATOMIC_LOAD_OR,
-    ATOMIC_LOAD_XOR,
-    ATOMIC_LOAD_NAND,
-    ATOMIC_LOAD_MIN,
-    ATOMIC_LOAD_MAX,
-    ATOMIC_LOAD_UMIN,
-    ATOMIC_LOAD_UMAX,
+    ATOMIC_LOAD_ADD_8,
+    ATOMIC_LOAD_SUB_8,
+    ATOMIC_LOAD_AND_8,
+    ATOMIC_LOAD_OR_8,
+    ATOMIC_LOAD_XOR_8,
+    ATOMIC_LOAD_NAND_8,
+    ATOMIC_LOAD_MIN_8,
+    ATOMIC_LOAD_MAX_8,
+    ATOMIC_LOAD_UMIN_8,
+    ATOMIC_LOAD_UMAX_8,
+    ATOMIC_LOAD_ADD_16,
+    ATOMIC_LOAD_SUB_16,
+    ATOMIC_LOAD_AND_16,
+    ATOMIC_LOAD_OR_16,
+    ATOMIC_LOAD_XOR_16,
+    ATOMIC_LOAD_NAND_16,
+    ATOMIC_LOAD_MIN_16,
+    ATOMIC_LOAD_MAX_16,
+    ATOMIC_LOAD_UMIN_16,
+    ATOMIC_LOAD_UMAX_16,
+    ATOMIC_LOAD_ADD_32,
+    ATOMIC_LOAD_SUB_32,
+    ATOMIC_LOAD_AND_32,
+    ATOMIC_LOAD_OR_32,
+    ATOMIC_LOAD_XOR_32,
+    ATOMIC_LOAD_NAND_32,
+    ATOMIC_LOAD_MIN_32,
+    ATOMIC_LOAD_MAX_32,
+    ATOMIC_LOAD_UMIN_32,
+    ATOMIC_LOAD_UMAX_32,
+    ATOMIC_LOAD_ADD_64,
+    ATOMIC_LOAD_SUB_64,
+    ATOMIC_LOAD_AND_64,
+    ATOMIC_LOAD_OR_64,
+    ATOMIC_LOAD_XOR_64,
+    ATOMIC_LOAD_NAND_64,
+    ATOMIC_LOAD_MIN_64,
+    ATOMIC_LOAD_MAX_64,
+    ATOMIC_LOAD_UMIN_64,
+    ATOMIC_LOAD_UMAX_64,
     
     // BUILTIN_OP_END - This must be the last enum value in this list.
     BUILTIN_OP_END
@@ -1512,20 +1540,59 @@
   // Methods to support isa and dyn_cast
   static bool classof(const MemSDNode *) { return true; }
   static bool classof(const SDNode *N) {
-    return N->getOpcode() == ISD::LOAD  ||
-           N->getOpcode() == ISD::STORE ||
-           N->getOpcode() == ISD::ATOMIC_CMP_SWAP  ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_ADD  ||
-           N->getOpcode() == ISD::ATOMIC_SWAP      ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_SUB  ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_AND  ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_OR   ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_XOR  ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_MIN  ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_MAX  ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_UMAX;
+    return N->getOpcode() == ISD::LOAD                ||
+           N->getOpcode() == ISD::STORE               ||
+           N->getOpcode() == ISD::ATOMIC_CMP_SWAP_8   ||
+           N->getOpcode() == ISD::ATOMIC_SWAP_8       ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_ADD_8   ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_SUB_8   ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_AND_8   ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_OR_8    ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_XOR_8   ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_NAND_8  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_MIN_8   ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_MAX_8   ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_UMIN_8  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_UMAX_8  ||
+
+           N->getOpcode() == ISD::ATOMIC_CMP_SWAP_16  ||
+           N->getOpcode() == ISD::ATOMIC_SWAP_16      ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_ADD_16  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_SUB_16  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_AND_16  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_OR_16   ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_XOR_16  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_NAND_16 ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_MIN_16  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_MAX_16  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_UMIN_16 ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_UMAX_16 ||
+
+           N->getOpcode() == ISD::ATOMIC_CMP_SWAP_32  ||
+           N->getOpcode() == ISD::ATOMIC_SWAP_32      ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_ADD_32  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_SUB_32  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_AND_32  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_OR_32   ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_XOR_32  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_NAND_32 ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_MIN_32  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_MAX_32  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_UMIN_32 ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_UMAX_32 ||
+
+           N->getOpcode() == ISD::ATOMIC_CMP_SWAP_64  ||
+           N->getOpcode() == ISD::ATOMIC_SWAP_64      ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_ADD_64  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_SUB_64  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_AND_64  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_OR_64   ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_XOR_64  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_NAND_64 ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_MIN_64  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_MAX_64  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_UMIN_64 ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_UMAX_64;
   }  
 };
 
@@ -1567,23 +1634,65 @@
   const SDValue &getBasePtr() const { return getOperand(1); }
   const SDValue &getVal() const { return getOperand(2); }
 
-  bool isCompareAndSwap() const { return getOpcode() == ISD::ATOMIC_CMP_SWAP; }
+  bool isCompareAndSwap() const { 
+    unsigned Op = getOpcode(); 
+    return Op == ISD::ATOMIC_CMP_SWAP_8 ||
+           Op == ISD::ATOMIC_CMP_SWAP_16 ||
+           Op == ISD::ATOMIC_CMP_SWAP_32 ||
+           Op == ISD::ATOMIC_CMP_SWAP_64;
+  }
 
   // Methods to support isa and dyn_cast
   static bool classof(const AtomicSDNode *) { return true; }
   static bool classof(const SDNode *N) {
-    return N->getOpcode() == ISD::ATOMIC_CMP_SWAP  ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_ADD  ||
-           N->getOpcode() == ISD::ATOMIC_SWAP      ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_SUB  ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_AND  ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_OR   ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_XOR  ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_MIN  ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_MAX  ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_UMAX;
+    return N->getOpcode() == ISD::ATOMIC_CMP_SWAP_8   ||
+           N->getOpcode() == ISD::ATOMIC_SWAP_8       ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_ADD_8   ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_SUB_8   ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_AND_8   ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_OR_8    ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_XOR_8   ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_NAND_8  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_MIN_8   ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_MAX_8   ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_UMIN_8  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_UMAX_8  ||
+           N->getOpcode() == ISD::ATOMIC_CMP_SWAP_16  ||
+           N->getOpcode() == ISD::ATOMIC_SWAP_16      ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_ADD_16  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_SUB_16  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_AND_16  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_OR_16   ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_XOR_16  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_NAND_16 ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_MIN_16  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_MAX_16  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_UMIN_16 ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_UMAX_16 ||
+           N->getOpcode() == ISD::ATOMIC_CMP_SWAP_32  ||
+           N->getOpcode() == ISD::ATOMIC_SWAP_32      ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_ADD_32  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_SUB_32  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_AND_32  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_OR_32   ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_XOR_32  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_NAND_32 ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_MIN_32  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_MAX_32  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_UMIN_32 ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_UMAX_32 ||
+           N->getOpcode() == ISD::ATOMIC_CMP_SWAP_64  ||
+           N->getOpcode() == ISD::ATOMIC_SWAP_64      ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_ADD_64  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_SUB_64  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_AND_64  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_OR_64   ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_XOR_64  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_NAND_64 ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_MIN_64  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_MAX_64  ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_UMIN_64 ||
+           N->getOpcode() == ISD::ATOMIC_LOAD_UMAX_64;
   }
 };
 

Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=55457&r1=55456&r2=55457&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Wed Aug 27 21:44:49 2008
@@ -1386,7 +1386,7 @@
   MVT TransformToType[MVT::LAST_VALUETYPE];
 
   // Defines the capacity of the TargetLowering::OpActions table
-  static const int OpActionsCapacity = 176;
+  static const int OpActionsCapacity = 212;
 
   /// OpActions - For each operation and each value type, keep a LegalizeAction
   /// that indicates how instruction selection should deal with the operation.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=55457&r1=55456&r2=55457&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Aug 27 21:44:49 2008
@@ -1181,7 +1181,10 @@
     break;
   }
 
-  case ISD::ATOMIC_CMP_SWAP: {
+  case ISD::ATOMIC_CMP_SWAP_8:
+  case ISD::ATOMIC_CMP_SWAP_16:
+  case ISD::ATOMIC_CMP_SWAP_32:
+  case ISD::ATOMIC_CMP_SWAP_64: {
     unsigned int num_operands = 4;
     assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
     SDValue Ops[4];
@@ -1201,17 +1204,50 @@
     AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
     return Result.getValue(Op.getResNo());
   }
-  case ISD::ATOMIC_LOAD_ADD:
-  case ISD::ATOMIC_LOAD_SUB:
-  case ISD::ATOMIC_LOAD_AND:
-  case ISD::ATOMIC_LOAD_OR:
-  case ISD::ATOMIC_LOAD_XOR:
-  case ISD::ATOMIC_LOAD_NAND:
-  case ISD::ATOMIC_LOAD_MIN:
-  case ISD::ATOMIC_LOAD_MAX:
-  case ISD::ATOMIC_LOAD_UMIN:
-  case ISD::ATOMIC_LOAD_UMAX:
-  case ISD::ATOMIC_SWAP: {
+  case ISD::ATOMIC_LOAD_ADD_8:
+  case ISD::ATOMIC_LOAD_SUB_8:
+  case ISD::ATOMIC_LOAD_AND_8:
+  case ISD::ATOMIC_LOAD_OR_8:
+  case ISD::ATOMIC_LOAD_XOR_8:
+  case ISD::ATOMIC_LOAD_NAND_8:
+  case ISD::ATOMIC_LOAD_MIN_8:
+  case ISD::ATOMIC_LOAD_MAX_8:
+  case ISD::ATOMIC_LOAD_UMIN_8:
+  case ISD::ATOMIC_LOAD_UMAX_8:
+  case ISD::ATOMIC_SWAP_8: 
+  case ISD::ATOMIC_LOAD_ADD_16:
+  case ISD::ATOMIC_LOAD_SUB_16:
+  case ISD::ATOMIC_LOAD_AND_16:
+  case ISD::ATOMIC_LOAD_OR_16:
+  case ISD::ATOMIC_LOAD_XOR_16:
+  case ISD::ATOMIC_LOAD_NAND_16:
+  case ISD::ATOMIC_LOAD_MIN_16:
+  case ISD::ATOMIC_LOAD_MAX_16:
+  case ISD::ATOMIC_LOAD_UMIN_16:
+  case ISD::ATOMIC_LOAD_UMAX_16:
+  case ISD::ATOMIC_SWAP_16:
+  case ISD::ATOMIC_LOAD_ADD_32:
+  case ISD::ATOMIC_LOAD_SUB_32:
+  case ISD::ATOMIC_LOAD_AND_32:
+  case ISD::ATOMIC_LOAD_OR_32:
+  case ISD::ATOMIC_LOAD_XOR_32:
+  case ISD::ATOMIC_LOAD_NAND_32:
+  case ISD::ATOMIC_LOAD_MIN_32:
+  case ISD::ATOMIC_LOAD_MAX_32:
+  case ISD::ATOMIC_LOAD_UMIN_32:
+  case ISD::ATOMIC_LOAD_UMAX_32:
+  case ISD::ATOMIC_SWAP_32:
+  case ISD::ATOMIC_LOAD_ADD_64:
+  case ISD::ATOMIC_LOAD_SUB_64:
+  case ISD::ATOMIC_LOAD_AND_64:
+  case ISD::ATOMIC_LOAD_OR_64:
+  case ISD::ATOMIC_LOAD_XOR_64:
+  case ISD::ATOMIC_LOAD_NAND_64:
+  case ISD::ATOMIC_LOAD_MIN_64:
+  case ISD::ATOMIC_LOAD_MAX_64:
+  case ISD::ATOMIC_LOAD_UMIN_64:
+  case ISD::ATOMIC_LOAD_UMAX_64:
+  case ISD::ATOMIC_SWAP_64: {
     unsigned int num_operands = 3;
     assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
     SDValue Ops[3];
@@ -4155,7 +4191,10 @@
     break;
   }
     
-  case ISD::ATOMIC_CMP_SWAP: {
+  case ISD::ATOMIC_CMP_SWAP_8:
+  case ISD::ATOMIC_CMP_SWAP_16:
+  case ISD::ATOMIC_CMP_SWAP_32:
+  case ISD::ATOMIC_CMP_SWAP_64: {
     AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
     Tmp2 = PromoteOp(Node->getOperand(2));
     Tmp3 = PromoteOp(Node->getOperand(3));
@@ -4167,17 +4206,50 @@
     AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
     break;
   }
-  case ISD::ATOMIC_LOAD_ADD:
-  case ISD::ATOMIC_LOAD_SUB:
-  case ISD::ATOMIC_LOAD_AND:
-  case ISD::ATOMIC_LOAD_OR:
-  case ISD::ATOMIC_LOAD_XOR:
-  case ISD::ATOMIC_LOAD_NAND:
-  case ISD::ATOMIC_LOAD_MIN:
-  case ISD::ATOMIC_LOAD_MAX:
-  case ISD::ATOMIC_LOAD_UMIN:
-  case ISD::ATOMIC_LOAD_UMAX:
-  case ISD::ATOMIC_SWAP: {
+  case ISD::ATOMIC_LOAD_ADD_8:
+  case ISD::ATOMIC_LOAD_SUB_8:
+  case ISD::ATOMIC_LOAD_AND_8:
+  case ISD::ATOMIC_LOAD_OR_8:
+  case ISD::ATOMIC_LOAD_XOR_8:
+  case ISD::ATOMIC_LOAD_NAND_8:
+  case ISD::ATOMIC_LOAD_MIN_8:
+  case ISD::ATOMIC_LOAD_MAX_8:
+  case ISD::ATOMIC_LOAD_UMIN_8:
+  case ISD::ATOMIC_LOAD_UMAX_8:
+  case ISD::ATOMIC_SWAP_8: 
+  case ISD::ATOMIC_LOAD_ADD_16:
+  case ISD::ATOMIC_LOAD_SUB_16:
+  case ISD::ATOMIC_LOAD_AND_16:
+  case ISD::ATOMIC_LOAD_OR_16:
+  case ISD::ATOMIC_LOAD_XOR_16:
+  case ISD::ATOMIC_LOAD_NAND_16:
+  case ISD::ATOMIC_LOAD_MIN_16:
+  case ISD::ATOMIC_LOAD_MAX_16:
+  case ISD::ATOMIC_LOAD_UMIN_16:
+  case ISD::ATOMIC_LOAD_UMAX_16:
+  case ISD::ATOMIC_SWAP_16:
+  case ISD::ATOMIC_LOAD_ADD_32:
+  case ISD::ATOMIC_LOAD_SUB_32:
+  case ISD::ATOMIC_LOAD_AND_32:
+  case ISD::ATOMIC_LOAD_OR_32:
+  case ISD::ATOMIC_LOAD_XOR_32:
+  case ISD::ATOMIC_LOAD_NAND_32:
+  case ISD::ATOMIC_LOAD_MIN_32:
+  case ISD::ATOMIC_LOAD_MAX_32:
+  case ISD::ATOMIC_LOAD_UMIN_32:
+  case ISD::ATOMIC_LOAD_UMAX_32:
+  case ISD::ATOMIC_SWAP_32:
+  case ISD::ATOMIC_LOAD_ADD_64:
+  case ISD::ATOMIC_LOAD_SUB_64:
+  case ISD::ATOMIC_LOAD_AND_64:
+  case ISD::ATOMIC_LOAD_OR_64:
+  case ISD::ATOMIC_LOAD_XOR_64:
+  case ISD::ATOMIC_LOAD_NAND_64:
+  case ISD::ATOMIC_LOAD_MIN_64:
+  case ISD::ATOMIC_LOAD_MAX_64:
+  case ISD::ATOMIC_LOAD_UMIN_64:
+  case ISD::ATOMIC_LOAD_UMAX_64:
+  case ISD::ATOMIC_SWAP_64: {
     AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
     Tmp2 = PromoteOp(Node->getOperand(2));
     Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(), 
@@ -6092,7 +6164,11 @@
     break;
   }
 
-  case ISD::ATOMIC_CMP_SWAP: {
+  // FIXME: should the LOAD_BIN and SWAP atomics get here too?  Probably.
+  case ISD::ATOMIC_CMP_SWAP_8:
+  case ISD::ATOMIC_CMP_SWAP_16:
+  case ISD::ATOMIC_CMP_SWAP_32:
+  case ISD::ATOMIC_CMP_SWAP_64: {
     SDValue Tmp = TLI.LowerOperation(Op, DAG);
     assert(Tmp.Val && "Node must be custom expanded!");
     ExpandOp(Tmp.getValue(0), Lo, Hi);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=55457&r1=55456&r2=55457&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Aug 27 21:44:49 2008
@@ -439,18 +439,54 @@
     ID.AddInteger(ST->getRawFlags());
     break;
   }
-  case ISD::ATOMIC_CMP_SWAP:
-  case ISD::ATOMIC_LOAD_ADD:
-  case ISD::ATOMIC_SWAP:
-  case ISD::ATOMIC_LOAD_SUB:
-  case ISD::ATOMIC_LOAD_AND:
-  case ISD::ATOMIC_LOAD_OR:
-  case ISD::ATOMIC_LOAD_XOR:
-  case ISD::ATOMIC_LOAD_NAND:
-  case ISD::ATOMIC_LOAD_MIN:
-  case ISD::ATOMIC_LOAD_MAX:
-  case ISD::ATOMIC_LOAD_UMIN:
-  case ISD::ATOMIC_LOAD_UMAX: {
+  case ISD::ATOMIC_CMP_SWAP_8:
+  case ISD::ATOMIC_SWAP_8:
+  case ISD::ATOMIC_LOAD_ADD_8:
+  case ISD::ATOMIC_LOAD_SUB_8:
+  case ISD::ATOMIC_LOAD_AND_8:
+  case ISD::ATOMIC_LOAD_OR_8:
+  case ISD::ATOMIC_LOAD_XOR_8:
+  case ISD::ATOMIC_LOAD_NAND_8:
+  case ISD::ATOMIC_LOAD_MIN_8:
+  case ISD::ATOMIC_LOAD_MAX_8:
+  case ISD::ATOMIC_LOAD_UMIN_8:
+  case ISD::ATOMIC_LOAD_UMAX_8: 
+  case ISD::ATOMIC_CMP_SWAP_16:
+  case ISD::ATOMIC_SWAP_16:
+  case ISD::ATOMIC_LOAD_ADD_16:
+  case ISD::ATOMIC_LOAD_SUB_16:
+  case ISD::ATOMIC_LOAD_AND_16:
+  case ISD::ATOMIC_LOAD_OR_16:
+  case ISD::ATOMIC_LOAD_XOR_16:
+  case ISD::ATOMIC_LOAD_NAND_16:
+  case ISD::ATOMIC_LOAD_MIN_16:
+  case ISD::ATOMIC_LOAD_MAX_16:
+  case ISD::ATOMIC_LOAD_UMIN_16:
+  case ISD::ATOMIC_LOAD_UMAX_16: 
+  case ISD::ATOMIC_CMP_SWAP_32:
+  case ISD::ATOMIC_SWAP_32:
+  case ISD::ATOMIC_LOAD_ADD_32:
+  case ISD::ATOMIC_LOAD_SUB_32:
+  case ISD::ATOMIC_LOAD_AND_32:
+  case ISD::ATOMIC_LOAD_OR_32:
+  case ISD::ATOMIC_LOAD_XOR_32:
+  case ISD::ATOMIC_LOAD_NAND_32:
+  case ISD::ATOMIC_LOAD_MIN_32:
+  case ISD::ATOMIC_LOAD_MAX_32:
+  case ISD::ATOMIC_LOAD_UMIN_32:
+  case ISD::ATOMIC_LOAD_UMAX_32: 
+  case ISD::ATOMIC_CMP_SWAP_64:
+  case ISD::ATOMIC_SWAP_64:
+  case ISD::ATOMIC_LOAD_ADD_64:
+  case ISD::ATOMIC_LOAD_SUB_64:
+  case ISD::ATOMIC_LOAD_AND_64:
+  case ISD::ATOMIC_LOAD_OR_64:
+  case ISD::ATOMIC_LOAD_XOR_64:
+  case ISD::ATOMIC_LOAD_NAND_64:
+  case ISD::ATOMIC_LOAD_MIN_64:
+  case ISD::ATOMIC_LOAD_MAX_64:
+  case ISD::ATOMIC_LOAD_UMIN_64:
+  case ISD::ATOMIC_LOAD_UMAX_64: {
     const AtomicSDNode *AT = cast<AtomicSDNode>(N);
     ID.AddInteger(AT->getRawFlags());
     break;
@@ -3149,7 +3185,10 @@
                                 SDValue Ptr, SDValue Cmp, 
                                 SDValue Swp, const Value* PtrVal,
                                 unsigned Alignment) {
-  assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op");
+  assert((Opcode == ISD::ATOMIC_CMP_SWAP_8  ||
+          Opcode == ISD::ATOMIC_CMP_SWAP_16 ||
+          Opcode == ISD::ATOMIC_CMP_SWAP_32 ||
+          Opcode == ISD::ATOMIC_CMP_SWAP_64) && "Invalid Atomic Op");
   assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types");
 
   MVT VT = Cmp.getValueType();
@@ -3175,13 +3214,50 @@
                                 SDValue Ptr, SDValue Val, 
                                 const Value* PtrVal,
                                 unsigned Alignment) {
-  assert((   Opcode == ISD::ATOMIC_LOAD_ADD || Opcode == ISD::ATOMIC_LOAD_SUB
-          || Opcode == ISD::ATOMIC_SWAP || Opcode == ISD::ATOMIC_LOAD_AND
-          || Opcode == ISD::ATOMIC_LOAD_OR || Opcode == ISD::ATOMIC_LOAD_XOR
-          || Opcode == ISD::ATOMIC_LOAD_NAND 
-          || Opcode == ISD::ATOMIC_LOAD_MIN || Opcode == ISD::ATOMIC_LOAD_MAX
-          || Opcode == ISD::ATOMIC_LOAD_UMIN || Opcode == ISD::ATOMIC_LOAD_UMAX) 
-         && "Invalid Atomic Op");
+  assert((Opcode == ISD::ATOMIC_LOAD_ADD_8 ||
+          Opcode == ISD::ATOMIC_LOAD_SUB_8 ||
+          Opcode == ISD::ATOMIC_LOAD_AND_8 ||
+          Opcode == ISD::ATOMIC_LOAD_OR_8 ||
+          Opcode == ISD::ATOMIC_LOAD_XOR_8 ||
+          Opcode == ISD::ATOMIC_LOAD_NAND_8 ||
+          Opcode == ISD::ATOMIC_LOAD_MIN_8 || 
+          Opcode == ISD::ATOMIC_LOAD_MAX_8 ||
+          Opcode == ISD::ATOMIC_LOAD_UMIN_8 || 
+          Opcode == ISD::ATOMIC_LOAD_UMAX_8 ||
+          Opcode == ISD::ATOMIC_SWAP_8 || 
+          Opcode == ISD::ATOMIC_LOAD_ADD_16 ||
+          Opcode == ISD::ATOMIC_LOAD_SUB_16 ||
+          Opcode == ISD::ATOMIC_LOAD_AND_16 ||
+          Opcode == ISD::ATOMIC_LOAD_OR_16 ||
+          Opcode == ISD::ATOMIC_LOAD_XOR_16 ||
+          Opcode == ISD::ATOMIC_LOAD_NAND_16 ||
+          Opcode == ISD::ATOMIC_LOAD_MIN_16 || 
+          Opcode == ISD::ATOMIC_LOAD_MAX_16 ||
+          Opcode == ISD::ATOMIC_LOAD_UMIN_16 || 
+          Opcode == ISD::ATOMIC_LOAD_UMAX_16 ||
+          Opcode == ISD::ATOMIC_SWAP_16 || 
+          Opcode == ISD::ATOMIC_LOAD_ADD_32 ||
+          Opcode == ISD::ATOMIC_LOAD_SUB_32 ||
+          Opcode == ISD::ATOMIC_LOAD_AND_32 ||
+          Opcode == ISD::ATOMIC_LOAD_OR_32 ||
+          Opcode == ISD::ATOMIC_LOAD_XOR_32 ||
+          Opcode == ISD::ATOMIC_LOAD_NAND_32 ||
+          Opcode == ISD::ATOMIC_LOAD_MIN_32 || 
+          Opcode == ISD::ATOMIC_LOAD_MAX_32 ||
+          Opcode == ISD::ATOMIC_LOAD_UMIN_32 || 
+          Opcode == ISD::ATOMIC_LOAD_UMAX_32 ||
+          Opcode == ISD::ATOMIC_SWAP_32 || 
+          Opcode == ISD::ATOMIC_LOAD_ADD_64 ||
+          Opcode == ISD::ATOMIC_LOAD_SUB_64 ||
+          Opcode == ISD::ATOMIC_LOAD_AND_64 ||
+          Opcode == ISD::ATOMIC_LOAD_OR_64 ||
+          Opcode == ISD::ATOMIC_LOAD_XOR_64 ||
+          Opcode == ISD::ATOMIC_LOAD_NAND_64 ||
+          Opcode == ISD::ATOMIC_LOAD_MIN_64 || 
+          Opcode == ISD::ATOMIC_LOAD_MAX_64 ||
+          Opcode == ISD::ATOMIC_LOAD_UMIN_64 || 
+          Opcode == ISD::ATOMIC_LOAD_UMAX_64 ||
+          Opcode == ISD::ATOMIC_SWAP_64)        && "Invalid Atomic Op");
 
   MVT VT = Val.getValueType();
 
@@ -4721,18 +4797,54 @@
 #endif
   case ISD::PREFETCH:      return "Prefetch";
   case ISD::MEMBARRIER:    return "MemBarrier";
-  case ISD::ATOMIC_CMP_SWAP:  return "AtomicCmpSwap";
-  case ISD::ATOMIC_LOAD_ADD:  return "AtomicLoadAdd";
-  case ISD::ATOMIC_LOAD_SUB:  return "AtomicLoadSub";
-  case ISD::ATOMIC_LOAD_AND:  return "AtomicLoadAnd";
-  case ISD::ATOMIC_LOAD_OR:   return "AtomicLoadOr";
-  case ISD::ATOMIC_LOAD_XOR:  return "AtomicLoadXor";
-  case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand";
-  case ISD::ATOMIC_LOAD_MIN:  return "AtomicLoadMin";
-  case ISD::ATOMIC_LOAD_MAX:  return "AtomicLoadMax";
-  case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin";
-  case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax";
-  case ISD::ATOMIC_SWAP:   return "AtomicSWAP";
+  case ISD::ATOMIC_CMP_SWAP_8:  return "AtomicCmpSwap8";
+  case ISD::ATOMIC_SWAP_8:      return "AtomicSwap8";
+  case ISD::ATOMIC_LOAD_ADD_8:  return "AtomicLoadAdd8";
+  case ISD::ATOMIC_LOAD_SUB_8:  return "AtomicLoadSub8";
+  case ISD::ATOMIC_LOAD_AND_8:  return "AtomicLoadAnd8";
+  case ISD::ATOMIC_LOAD_OR_8:   return "AtomicLoadOr8";
+  case ISD::ATOMIC_LOAD_XOR_8:  return "AtomicLoadXor8";
+  case ISD::ATOMIC_LOAD_NAND_8: return "AtomicLoadNand8";
+  case ISD::ATOMIC_LOAD_MIN_8:  return "AtomicLoadMin8";
+  case ISD::ATOMIC_LOAD_MAX_8:  return "AtomicLoadMax8";
+  case ISD::ATOMIC_LOAD_UMIN_8: return "AtomicLoadUMin8";
+  case ISD::ATOMIC_LOAD_UMAX_8: return "AtomicLoadUMax8";
+  case ISD::ATOMIC_CMP_SWAP_16:  return "AtomicCmpSwap16";
+  case ISD::ATOMIC_SWAP_16:      return "AtomicSwap16";
+  case ISD::ATOMIC_LOAD_ADD_16:  return "AtomicLoadAdd16";
+  case ISD::ATOMIC_LOAD_SUB_16:  return "AtomicLoadSub16";
+  case ISD::ATOMIC_LOAD_AND_16:  return "AtomicLoadAnd16";
+  case ISD::ATOMIC_LOAD_OR_16:   return "AtomicLoadOr16";
+  case ISD::ATOMIC_LOAD_XOR_16:  return "AtomicLoadXor16";
+  case ISD::ATOMIC_LOAD_NAND_16: return "AtomicLoadNand16";
+  case ISD::ATOMIC_LOAD_MIN_16:  return "AtomicLoadMin16";
+  case ISD::ATOMIC_LOAD_MAX_16:  return "AtomicLoadMax16";
+  case ISD::ATOMIC_LOAD_UMIN_16: return "AtomicLoadUMin16";
+  case ISD::ATOMIC_LOAD_UMAX_16: return "AtomicLoadUMax16";
+  case ISD::ATOMIC_CMP_SWAP_32:  return "AtomicCmpSwap32";
+  case ISD::ATOMIC_SWAP_32:      return "AtomicSwap32";
+  case ISD::ATOMIC_LOAD_ADD_32:  return "AtomicLoadAdd32";
+  case ISD::ATOMIC_LOAD_SUB_32:  return "AtomicLoadSub32";
+  case ISD::ATOMIC_LOAD_AND_32:  return "AtomicLoadAnd32";
+  case ISD::ATOMIC_LOAD_OR_32:   return "AtomicLoadOr32";
+  case ISD::ATOMIC_LOAD_XOR_32:  return "AtomicLoadXor32";
+  case ISD::ATOMIC_LOAD_NAND_32: return "AtomicLoadNand32";
+  case ISD::ATOMIC_LOAD_MIN_32:  return "AtomicLoadMin32";
+  case ISD::ATOMIC_LOAD_MAX_32:  return "AtomicLoadMax32";
+  case ISD::ATOMIC_LOAD_UMIN_32: return "AtomicLoadUMin32";
+  case ISD::ATOMIC_LOAD_UMAX_32: return "AtomicLoadUMax32";
+  case ISD::ATOMIC_CMP_SWAP_64:  return "AtomicCmpSwap64";
+  case ISD::ATOMIC_SWAP_64:      return "AtomicSwap64";
+  case ISD::ATOMIC_LOAD_ADD_64:  return "AtomicLoadAdd64";
+  case ISD::ATOMIC_LOAD_SUB_64:  return "AtomicLoadSub64";
+  case ISD::ATOMIC_LOAD_AND_64:  return "AtomicLoadAnd64";
+  case ISD::ATOMIC_LOAD_OR_64:   return "AtomicLoadOr64";
+  case ISD::ATOMIC_LOAD_XOR_64:  return "AtomicLoadXor64";
+  case ISD::ATOMIC_LOAD_NAND_64: return "AtomicLoadNand64";
+  case ISD::ATOMIC_LOAD_MIN_64:  return "AtomicLoadMin64";
+  case ISD::ATOMIC_LOAD_MAX_64:  return "AtomicLoadMax64";
+  case ISD::ATOMIC_LOAD_UMIN_64: return "AtomicLoadUMin64";
+  case ISD::ATOMIC_LOAD_UMAX_64: return "AtomicLoadUMax64";
   case ISD::PCMARKER:      return "PCMarker";
   case ISD::READCYCLECOUNTER: return "ReadCycleCounter";
   case ISD::SRCVALUE:      return "SrcValue";

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=55457&r1=55456&r2=55457&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Aug 27 21:44:49 2008
@@ -3664,37 +3664,198 @@
   }
   case Intrinsic::atomic_cmp_swap: {
     SDValue Root = getRoot();   
-    SDValue L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, Root, 
-                                getValue(I.getOperand(1)), 
-                                getValue(I.getOperand(2)),
-                                getValue(I.getOperand(3)),
-                                I.getOperand(1));
+    SDValue L;
+    switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
+      case MVT::i8:
+        L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_8, Root, 
+                          getValue(I.getOperand(1)), 
+                          getValue(I.getOperand(2)),
+                          getValue(I.getOperand(3)),
+                          I.getOperand(1));
+        break;
+      case MVT::i16:
+        L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_16, Root, 
+                          getValue(I.getOperand(1)), 
+                          getValue(I.getOperand(2)),
+                          getValue(I.getOperand(3)),
+                          I.getOperand(1));
+        break;
+      case MVT::i32:
+        L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_32, Root, 
+                          getValue(I.getOperand(1)), 
+                          getValue(I.getOperand(2)),
+                          getValue(I.getOperand(3)),
+                          I.getOperand(1));
+        break;
+      case MVT::i64:
+        L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_64, Root, 
+                          getValue(I.getOperand(1)), 
+                          getValue(I.getOperand(2)),
+                          getValue(I.getOperand(3)),
+                          I.getOperand(1));
+        break;
+      default:
+       assert(0 && "Invalid atomic type");
+       abort();
+    }
     setValue(&I, L);
     DAG.setRoot(L.getValue(1));
     return 0;
   }
   case Intrinsic::atomic_load_add:
-    return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
+    switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
+      case MVT::i8:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_8);
+      case MVT::i16:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_16);
+      case MVT::i32:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_32);
+      case MVT::i64:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_64);
+      default:
+       assert(0 && "Invalid atomic type");
+       abort();
+    }
   case Intrinsic::atomic_load_sub:
-    return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
-  case Intrinsic::atomic_load_and:
-    return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
+    switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
+      case MVT::i8:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_8);
+      case MVT::i16:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_16);
+      case MVT::i32:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_32);
+      case MVT::i64:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_64);
+      default:
+       assert(0 && "Invalid atomic type");
+       abort();
+    }
   case Intrinsic::atomic_load_or:
-    return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
+    switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
+      case MVT::i8:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_8);
+      case MVT::i16:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_16);
+      case MVT::i32:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_32);
+      case MVT::i64:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_64);
+      default:
+       assert(0 && "Invalid atomic type");
+       abort();
+    }
   case Intrinsic::atomic_load_xor:
-    return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
+    switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
+      case MVT::i8:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_8);
+      case MVT::i16:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_16);
+      case MVT::i32:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_32);
+      case MVT::i64:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_64);
+      default:
+       assert(0 && "Invalid atomic type");
+       abort();
+    }
+  case Intrinsic::atomic_load_and:
+    switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
+      case MVT::i8:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_8);
+      case MVT::i16:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_16);
+      case MVT::i32:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_32);
+      case MVT::i64:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_64);
+      default:
+       assert(0 && "Invalid atomic type");
+       abort();
+    }
   case Intrinsic::atomic_load_nand:
-    return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
-  case Intrinsic::atomic_load_min:
-    return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
+    switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
+      case MVT::i8:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_8);
+      case MVT::i16:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_16);
+      case MVT::i32:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_32);
+      case MVT::i64:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_64);
+      default:
+       assert(0 && "Invalid atomic type");
+       abort();
+    }
   case Intrinsic::atomic_load_max:
-    return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
+    switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
+      case MVT::i8:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_8);
+      case MVT::i16:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_16);
+      case MVT::i32:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_32);
+      case MVT::i64:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_64);
+      default:
+       assert(0 && "Invalid atomic type");
+       abort();
+    }
+  case Intrinsic::atomic_load_min:
+    switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
+      case MVT::i8:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_8);
+      case MVT::i16:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_16);
+      case MVT::i32:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_32);
+      case MVT::i64:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_64);
+      default:
+       assert(0 && "Invalid atomic type");
+       abort();
+    }
   case Intrinsic::atomic_load_umin:
-    return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
+    switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
+      case MVT::i8:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_8);
+      case MVT::i16:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_16);
+      case MVT::i32:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_32);
+      case MVT::i64:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_64);
+      default:
+       assert(0 && "Invalid atomic type");
+       abort();
+    }
   case Intrinsic::atomic_load_umax:
-      return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);                                              
+    switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
+      case MVT::i8:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_8);
+      case MVT::i16:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_16);
+      case MVT::i32:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_32);
+      case MVT::i64:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_64);
+      default:
+       assert(0 && "Invalid atomic type");
+       abort();
+    }
   case Intrinsic::atomic_swap:
-    return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
+    switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
+      case MVT::i8:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_8);
+      case MVT::i16:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_16);
+      case MVT::i32:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_32);
+      case MVT::i64:
+        return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_64);
+      default:
+       assert(0 && "Invalid atomic type");
+       abort();
+    }
   }
 }
 

Modified: llvm/trunk/lib/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetSelectionDAG.td?rev=55457&r1=55456&r2=55457&view=diff

==============================================================================
--- llvm/trunk/lib/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/lib/Target/TargetSelectionDAG.td Wed Aug 27 21:44:49 2008
@@ -358,30 +358,101 @@
 def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
                         [SDNPHasChain, SDNPSideEffect]>;
 
-// Do not use atomic_* directly, use atomic_*_size (see below)
-def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , STDAtomic3,
+def atomic_cmp_swap_8 : SDNode<"ISD::ATOMIC_CMP_SWAP_8" , STDAtomic3,
                     [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , STDAtomic2,
+def atomic_load_add_8 : SDNode<"ISD::ATOMIC_LOAD_ADD_8" , STDAtomic2,
                     [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_swap     : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2,
+def atomic_swap_8     : SDNode<"ISD::ATOMIC_SWAP_8", STDAtomic2,
                     [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , STDAtomic2,
+def atomic_load_sub_8 : SDNode<"ISD::ATOMIC_LOAD_SUB_8" , STDAtomic2,
                     [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , STDAtomic2,
+def atomic_load_and_8 : SDNode<"ISD::ATOMIC_LOAD_AND_8" , STDAtomic2,
                     [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_or  : SDNode<"ISD::ATOMIC_LOAD_OR" , STDAtomic2,
+def atomic_load_or_8  : SDNode<"ISD::ATOMIC_LOAD_OR_8" , STDAtomic2,
                     [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , STDAtomic2,
+def atomic_load_xor_8 : SDNode<"ISD::ATOMIC_LOAD_XOR_8" , STDAtomic2,
                     [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", STDAtomic2,
+def atomic_load_nand_8: SDNode<"ISD::ATOMIC_LOAD_NAND_8", STDAtomic2,
                     [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", STDAtomic2,
+def atomic_load_min_8 : SDNode<"ISD::ATOMIC_LOAD_MIN_8", STDAtomic2,
                     [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", STDAtomic2,
+def atomic_load_max_8 : SDNode<"ISD::ATOMIC_LOAD_MAX_8", STDAtomic2,
                     [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", STDAtomic2,
+def atomic_load_umin_8 : SDNode<"ISD::ATOMIC_LOAD_UMIN_8", STDAtomic2,
                     [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", STDAtomic2,
+def atomic_load_umax_8 : SDNode<"ISD::ATOMIC_LOAD_UMAX_8", STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_cmp_swap_16 : SDNode<"ISD::ATOMIC_CMP_SWAP_16" , STDAtomic3,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_add_16 : SDNode<"ISD::ATOMIC_LOAD_ADD_16" , STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_swap_16     : SDNode<"ISD::ATOMIC_SWAP_16", STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_sub_16 : SDNode<"ISD::ATOMIC_LOAD_SUB_16" , STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_and_16 : SDNode<"ISD::ATOMIC_LOAD_AND_16" , STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_or_16  : SDNode<"ISD::ATOMIC_LOAD_OR_16" , STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_xor_16 : SDNode<"ISD::ATOMIC_LOAD_XOR_16" , STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_nand_16: SDNode<"ISD::ATOMIC_LOAD_NAND_16", STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_min_16 : SDNode<"ISD::ATOMIC_LOAD_MIN_16", STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_max_16 : SDNode<"ISD::ATOMIC_LOAD_MAX_16", STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_umin_16 : SDNode<"ISD::ATOMIC_LOAD_UMIN_16", STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_umax_16 : SDNode<"ISD::ATOMIC_LOAD_UMAX_16", STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_cmp_swap_32 : SDNode<"ISD::ATOMIC_CMP_SWAP_32" , STDAtomic3,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_add_32 : SDNode<"ISD::ATOMIC_LOAD_ADD_32" , STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_swap_32     : SDNode<"ISD::ATOMIC_SWAP_32", STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_sub_32 : SDNode<"ISD::ATOMIC_LOAD_SUB_32" , STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_and_32 : SDNode<"ISD::ATOMIC_LOAD_AND_32" , STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_or_32  : SDNode<"ISD::ATOMIC_LOAD_OR_32" , STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_xor_32 : SDNode<"ISD::ATOMIC_LOAD_XOR_32" , STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_nand_32: SDNode<"ISD::ATOMIC_LOAD_NAND_32", STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_min_32 : SDNode<"ISD::ATOMIC_LOAD_MIN_32", STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_max_32 : SDNode<"ISD::ATOMIC_LOAD_MAX_32", STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_umin_32 : SDNode<"ISD::ATOMIC_LOAD_UMIN_32", STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_umax_32 : SDNode<"ISD::ATOMIC_LOAD_UMAX_32", STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_cmp_swap_64 : SDNode<"ISD::ATOMIC_CMP_SWAP_64" , STDAtomic3,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_add_64 : SDNode<"ISD::ATOMIC_LOAD_ADD_64" , STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_swap_64     : SDNode<"ISD::ATOMIC_SWAP_64", STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_sub_64 : SDNode<"ISD::ATOMIC_LOAD_SUB_64" , STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_and_64 : SDNode<"ISD::ATOMIC_LOAD_AND_64" , STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_or_64  : SDNode<"ISD::ATOMIC_LOAD_OR_64" , STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_xor_64 : SDNode<"ISD::ATOMIC_LOAD_XOR_64" , STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_nand_64: SDNode<"ISD::ATOMIC_LOAD_NAND_64", STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_min_64 : SDNode<"ISD::ATOMIC_LOAD_MIN_64", STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_max_64 : SDNode<"ISD::ATOMIC_LOAD_MAX_64", STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_umin_64 : SDNode<"ISD::ATOMIC_LOAD_UMIN_64", STDAtomic2,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_umax_64 : SDNode<"ISD::ATOMIC_LOAD_UMAX_64", STDAtomic2,
                     [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
 
 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
@@ -724,177 +795,6 @@
          ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
 }]>;
 
-// Atomic patterns
-def atomic_cmp_swap_8 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
-                    (atomic_cmp_swap node:$ptr, node:$cmp, node:$swp), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i8;
-}]>;
-def atomic_cmp_swap_16 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp), 
-                    (atomic_cmp_swap node:$ptr, node:$cmp, node:$swp), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i16;
-}]>;
-def atomic_cmp_swap_32 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp), 
-                    (atomic_cmp_swap node:$ptr, node:$cmp, node:$swp), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i32;
-}]>;
-def atomic_cmp_swap_64 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp), 
-                    (atomic_cmp_swap node:$ptr, node:$cmp, node:$swp), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i64;
-}]>;
-
-def atomic_load_add_8 : PatFrag<(ops node:$ptr, node:$inc),
-                    (atomic_load_add node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i8;
-}]>;
-def atomic_load_add_16 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_load_add node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i16;
-}]>;
-def atomic_load_add_32 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_load_add node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i32;
-}]>;
-def atomic_load_add_64 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_load_add node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i64;
-}]>;
-
-def atomic_load_sub_8 : PatFrag<(ops node:$ptr, node:$inc),
-                    (atomic_load_sub node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i8;
-}]>;
-def atomic_load_sub_16 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_load_sub node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i16;
-}]>;
-def atomic_load_sub_32 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_load_sub node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i32;
-}]>;
-def atomic_load_sub_64 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_load_sub node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i64;
-}]>;
-
-def atomic_load_and_8 : PatFrag<(ops node:$ptr, node:$inc),
-                    (atomic_load_and node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i8;
-}]>;
-def atomic_load_and_16 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_load_and node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i16;
-}]>;
-def atomic_load_and_32 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_load_and node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i32;
-}]>;
-def atomic_load_and_64 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_load_and node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i64;
-}]>;
-
-def atomic_load_or_8 : PatFrag<(ops node:$ptr, node:$inc),
-                    (atomic_load_or node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i8;
-}]>;
-def atomic_load_or_16 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_load_or node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i16;
-}]>;
-def atomic_load_or_32 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_load_or node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i32;
-}]>;
-def atomic_load_or_64 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_load_or node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i64;
-}]>;
-
-def atomic_load_xor_8 : PatFrag<(ops node:$ptr, node:$inc),
-                    (atomic_load_xor node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i8;
-}]>;
-def atomic_load_xor_16 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_load_xor node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i16;
-}]>;
-def atomic_load_xor_32 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_load_xor node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i32;
-}]>;
-def atomic_load_xor_64 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_load_xor node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i64;
-}]>;
-
-def atomic_load_nand_8 : PatFrag<(ops node:$ptr, node:$inc),
-                    (atomic_load_nand node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i8;
-}]>;
-def atomic_load_nand_16 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_load_nand node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i16;
-}]>;
-def atomic_load_nand_32 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_load_nand node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i32;
-}]>;
-def atomic_load_nand_64 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_load_nand node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i64;
-}]>;
-
-def atomic_swap_8 : PatFrag<(ops node:$ptr, node:$inc),
-                    (atomic_swap node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i8;
-}]>;
-def atomic_swap_16 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_swap node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i16;
-}]>;
-def atomic_swap_32 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_swap node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i32;
-}]>;
-def atomic_swap_64 : PatFrag<(ops node:$ptr, node:$inc), 
-                    (atomic_swap node:$ptr, node:$inc), [{
-  AtomicSDNode* V = cast<AtomicSDNode>(N);
-  return V->getValueType(0) == MVT::i64;
-}]>;
-
-
-
 // setcc convenience fragments.
 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
                      (setcc node:$lhs, node:$rhs, SETOEQ)>;

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=55457&r1=55456&r2=55457&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Aug 27 21:44:49 2008
@@ -293,15 +293,15 @@
     setOperationAction(ISD::MEMBARRIER    , MVT::Other, Expand);
 
   // Expand certain atomics
-  setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i8, Custom);
-  setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i16, Custom);
-  setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i32, Custom);
-  setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i64, Custom);
-
-  setOperationAction(ISD::ATOMIC_LOAD_SUB , MVT::i8, Expand);
-  setOperationAction(ISD::ATOMIC_LOAD_SUB , MVT::i16, Expand);
-  setOperationAction(ISD::ATOMIC_LOAD_SUB , MVT::i32, Expand);
-  setOperationAction(ISD::ATOMIC_LOAD_SUB , MVT::i64, Expand);
+  setOperationAction(ISD::ATOMIC_CMP_SWAP_8 , MVT::i8, Custom);
+  setOperationAction(ISD::ATOMIC_CMP_SWAP_16, MVT::i16, Custom);
+  setOperationAction(ISD::ATOMIC_CMP_SWAP_32, MVT::i32, Custom);
+  setOperationAction(ISD::ATOMIC_CMP_SWAP_64, MVT::i64, Custom);
+
+  setOperationAction(ISD::ATOMIC_LOAD_SUB_8, MVT::i8, Expand);
+  setOperationAction(ISD::ATOMIC_LOAD_SUB_16, MVT::i16, Expand);
+  setOperationAction(ISD::ATOMIC_LOAD_SUB_32, MVT::i32, Expand);
+  setOperationAction(ISD::ATOMIC_LOAD_SUB_64, MVT::i64, Expand);
 
   // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
   setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
@@ -5914,8 +5914,11 @@
   MVT T = Op->getValueType(0);
   SDValue negOp = DAG.getNode(ISD::SUB, T,
                                 DAG.getConstant(0, T), Op->getOperand(2));
-  return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, Op->getOperand(0),
-                       Op->getOperand(1), negOp,
+  return DAG.getAtomic((T==MVT::i8 ? ISD::ATOMIC_LOAD_ADD_8:
+                        T==MVT::i16 ? ISD::ATOMIC_LOAD_ADD_16:
+                        T==MVT::i32 ? ISD::ATOMIC_LOAD_ADD_32:
+                        T==MVT::i64 ? ISD::ATOMIC_LOAD_ADD_64: 0),
+                       Op->getOperand(0), Op->getOperand(1), negOp,
                        cast<AtomicSDNode>(Op)->getSrcValue(),
                        cast<AtomicSDNode>(Op)->getAlignment()).Val;
 }
@@ -5925,7 +5928,10 @@
 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
   switch (Op.getOpcode()) {
   default: assert(0 && "Should not custom lower this!");
-  case ISD::ATOMIC_CMP_SWAP:    return LowerCMP_SWAP(Op,DAG);
+  case ISD::ATOMIC_CMP_SWAP_8:  return LowerCMP_SWAP(Op,DAG);
+  case ISD::ATOMIC_CMP_SWAP_16: return LowerCMP_SWAP(Op,DAG);
+  case ISD::ATOMIC_CMP_SWAP_32: return LowerCMP_SWAP(Op,DAG);
+  case ISD::ATOMIC_CMP_SWAP_64: return LowerCMP_SWAP(Op,DAG);
   case ISD::BUILD_VECTOR:       return LowerBUILD_VECTOR(Op, DAG);
   case ISD::VECTOR_SHUFFLE:     return LowerVECTOR_SHUFFLE(Op, DAG);
   case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
@@ -5979,8 +5985,11 @@
   default: assert(0 && "Should not custom lower this!");
   case ISD::FP_TO_SINT:         return ExpandFP_TO_SINT(N, DAG);
   case ISD::READCYCLECOUNTER:   return ExpandREADCYCLECOUNTER(N, DAG);
-  case ISD::ATOMIC_CMP_SWAP:    return ExpandATOMIC_CMP_SWAP(N, DAG);
-  case ISD::ATOMIC_LOAD_SUB:    return ExpandATOMIC_LOAD_SUB(N,DAG);
+  case ISD::ATOMIC_CMP_SWAP_64: return ExpandATOMIC_CMP_SWAP(N, DAG);
+  case ISD::ATOMIC_LOAD_SUB_8:  return ExpandATOMIC_LOAD_SUB(N,DAG);
+  case ISD::ATOMIC_LOAD_SUB_16: return ExpandATOMIC_LOAD_SUB(N,DAG);
+  case ISD::ATOMIC_LOAD_SUB_32: return ExpandATOMIC_LOAD_SUB(N,DAG);
+  case ISD::ATOMIC_LOAD_SUB_64: return ExpandATOMIC_LOAD_SUB(N,DAG);
   }
 }
 

Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=55457&r1=55456&r2=55457&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Wed Aug 27 21:44:49 2008
@@ -1153,28 +1153,28 @@
                   usesCustomDAGSchedInserter = 1 in {
 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
                "#ATOMAND64 PSUEDO!", 
-               [(set GR64:$dst, (atomic_load_and addr:$ptr, GR64:$val))]>;
+               [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
                "#ATOMOR64 PSUEDO!", 
-               [(set GR64:$dst, (atomic_load_or addr:$ptr, GR64:$val))]>;
+               [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
                "#ATOMXOR64 PSUEDO!", 
-               [(set GR64:$dst, (atomic_load_xor addr:$ptr, GR64:$val))]>;
+               [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
                "#ATOMNAND64 PSUEDO!", 
-               [(set GR64:$dst, (atomic_load_nand addr:$ptr, GR64:$val))]>;
+               [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
                "#ATOMMIN64 PSUEDO!", 
-               [(set GR64:$dst, (atomic_load_min addr:$ptr, GR64:$val))]>;
+               [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
                "#ATOMMAX64 PSUEDO!", 
-               [(set GR64:$dst, (atomic_load_max addr:$ptr, GR64:$val))]>;
+               [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
                "#ATOMUMIN64 PSUEDO!", 
-               [(set GR64:$dst, (atomic_load_umin addr:$ptr, GR64:$val))]>;
+               [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
                "#ATOMUMAX64 PSUEDO!", 
-               [(set GR64:$dst, (atomic_load_umax addr:$ptr, GR64:$val))]>;
+               [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=55457&r1=55456&r2=55457&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Aug 27 21:44:49 2008
@@ -2637,66 +2637,66 @@
                   usesCustomDAGSchedInserter = 1 in {
 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
                "#ATOMAND32 PSUEDO!", 
-               [(set GR32:$dst, (atomic_load_and addr:$ptr, GR32:$val))]>;
+               [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
                "#ATOMOR32 PSUEDO!", 
-               [(set GR32:$dst, (atomic_load_or addr:$ptr, GR32:$val))]>;
+               [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
                "#ATOMXOR32 PSUEDO!", 
-               [(set GR32:$dst, (atomic_load_xor addr:$ptr, GR32:$val))]>;
+               [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
                "#ATOMNAND32 PSUEDO!", 
-               [(set GR32:$dst, (atomic_load_nand addr:$ptr, GR32:$val))]>;
+               [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
                "#ATOMMIN32 PSUEDO!", 
-               [(set GR32:$dst, (atomic_load_min addr:$ptr, GR32:$val))]>;
+               [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
                "#ATOMMAX32 PSUEDO!", 
-               [(set GR32:$dst, (atomic_load_max addr:$ptr, GR32:$val))]>;
+               [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
                "#ATOMUMIN32 PSUEDO!", 
-               [(set GR32:$dst, (atomic_load_umin addr:$ptr, GR32:$val))]>;
+               [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
                "#ATOMUMAX32 PSUEDO!", 
-               [(set GR32:$dst, (atomic_load_umax addr:$ptr, GR32:$val))]>;
+               [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
 
 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
                "#ATOMAND16 PSUEDO!", 
-               [(set GR16:$dst, (atomic_load_and addr:$ptr, GR16:$val))]>;
+               [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
                "#ATOMOR16 PSUEDO!", 
-               [(set GR16:$dst, (atomic_load_or addr:$ptr, GR16:$val))]>;
+               [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
                "#ATOMXOR16 PSUEDO!", 
-               [(set GR16:$dst, (atomic_load_xor addr:$ptr, GR16:$val))]>;
+               [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
                "#ATOMNAND16 PSUEDO!", 
-               [(set GR16:$dst, (atomic_load_nand addr:$ptr, GR16:$val))]>;
+               [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
                "#ATOMMIN16 PSUEDO!", 
-               [(set GR16:$dst, (atomic_load_min addr:$ptr, GR16:$val))]>;
+               [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
                "#ATOMMAX16 PSUEDO!", 
-               [(set GR16:$dst, (atomic_load_max addr:$ptr, GR16:$val))]>;
+               [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
                "#ATOMUMIN16 PSUEDO!", 
-               [(set GR16:$dst, (atomic_load_umin addr:$ptr, GR16:$val))]>;
+               [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
                "#ATOMUMAX16 PSUEDO!", 
-               [(set GR16:$dst, (atomic_load_umax addr:$ptr, GR16:$val))]>;
+               [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
 
 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
                "#ATOMAND8 PSUEDO!", 
-               [(set GR8:$dst, (atomic_load_and addr:$ptr, GR8:$val))]>;
+               [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
                "#ATOMOR8 PSUEDO!", 
-               [(set GR8:$dst, (atomic_load_or addr:$ptr, GR8:$val))]>;
+               [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
                "#ATOMXOR8 PSUEDO!", 
-               [(set GR8:$dst, (atomic_load_xor addr:$ptr, GR8:$val))]>;
+               [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
                "#ATOMNAND8 PSUEDO!", 
-               [(set GR8:$dst, (atomic_load_nand addr:$ptr, GR8:$val))]>;
+               [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
 }
 
 //===----------------------------------------------------------------------===//




From sabre at nondot.org  Wed Aug 27 22:33:05 2008
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 28 Aug 2008 03:33:05 -0000
Subject: [llvm-commits] [llvm] r55458 -
	/llvm/trunk/lib/Analysis/IntervalPartition.cpp
Message-ID: <200808280333.m7S3X5tL018162@zion.cs.uiuc.edu>

Author: lattner
Date: Wed Aug 27 22:33:03 2008
New Revision: 55458

URL: http://llvm.org/viewvc/llvm-project?rev=55458&view=rev
Log:
Clear the intervals list in "destroy", patch by 
Prakash Prabhu!


Modified:
    llvm/trunk/lib/Analysis/IntervalPartition.cpp

Modified: llvm/trunk/lib/Analysis/IntervalPartition.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IntervalPartition.cpp?rev=55458&r1=55457&r2=55458&view=diff

==============================================================================
--- llvm/trunk/lib/Analysis/IntervalPartition.cpp (original)
+++ llvm/trunk/lib/Analysis/IntervalPartition.cpp Wed Aug 27 22:33:03 2008
@@ -28,6 +28,7 @@
   for (unsigned i = 0, e = Intervals.size(); i != e; ++i)
     delete Intervals[i];
   IntervalMap.clear();
+  Intervals.clear();
   RootInterval = 0;
 }
 




From sabre at nondot.org  Wed Aug 27 23:02:44 2008
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 28 Aug 2008 04:02:44 -0000
Subject: [llvm-commits] [llvm] r55460 - /llvm/trunk/lib/VMCore/Verifier.cpp
Message-ID: <200808280402.m7S42jbV019226@zion.cs.uiuc.edu>

Author: lattner
Date: Wed Aug 27 23:02:44 2008
New Revision: 55460

URL: http://llvm.org/viewvc/llvm-project?rev=55460&view=rev
Log:
Make the verifier reject instructions which have null pointers 
for operands: rdar://6179606.  no testcase, because I can't write
a .ll file that is this broken ;-)

Modified:
    llvm/trunk/lib/VMCore/Verifier.cpp

Modified: llvm/trunk/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=55460&r1=55459&r2=55460&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/Verifier.cpp (original)
+++ llvm/trunk/lib/VMCore/Verifier.cpp Wed Aug 27 23:02:44 2008
@@ -224,6 +224,10 @@
     void visitGlobalAlias(GlobalAlias &GA);
     void visitFunction(Function &F);
     void visitBasicBlock(BasicBlock &BB);
+    using InstVisitor<Verifier>::visit;
+       
+    void visit(Instruction &I);
+       
     void visitTruncInst(TruncInst &I);
     void visitZExtInst(ZExtInst &I);
     void visitSExtInst(SExtInst &I);
@@ -326,6 +330,13 @@
   do { if (!(C)) { CheckFailed(M, V1, V2, V3, V4); return; } } while (0)
 
 
+void Verifier::visit(Instruction &I) {
+  for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i)
+    Assert1(I.getOperand(i) != 0, "Operand is null", &I);
+  InstVisitor<Verifier>::visit(I);
+}
+
+
 void Verifier::visitGlobalValue(GlobalValue &GV) {
   Assert1(!GV.isDeclaration() ||
           GV.hasExternalLinkage() ||




From evan.cheng at apple.com  Thu Aug 28 02:41:35 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 28 Aug 2008 07:41:35 -0000
Subject: [llvm-commits] [test-suite] r55464 -
	/test-suite/trunk/Makefile.programs
Message-ID: <200808280741.m7S7fZVq029225@zion.cs.uiuc.edu>

Author: evancheng
Date: Thu Aug 28 02:41:34 2008
New Revision: 55464

URL: http://llvm.org/viewvc/llvm-project?rev=55464&view=rev
Log:
-two-addr-remat has been removed.

Modified:
    test-suite/trunk/Makefile.programs

Modified: test-suite/trunk/Makefile.programs
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=55464&r1=55463&r2=55464&view=diff

==============================================================================
--- test-suite/trunk/Makefile.programs (original)
+++ test-suite/trunk/Makefile.programs Thu Aug 28 02:41:34 2008
@@ -221,7 +221,6 @@
 ifeq ($(ARCH),x86)
 LLCBETAOPTION := -machine-licm
 #-new-spilling-heuristic
-#-two-addr-remat
 #-enable-value-prop
 #-enable-sinking
 #-schedule-livein-copies




From evan.cheng at apple.com  Thu Aug 28 02:52:25 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 28 Aug 2008 07:52:25 -0000
Subject: [llvm-commits] [llvm] r55466 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <200808280752.m7S7qPUG001130@zion.cs.uiuc.edu>

Author: evancheng
Date: Thu Aug 28 02:52:25 2008
New Revision: 55466

URL: http://llvm.org/viewvc/llvm-project?rev=55466&view=rev
Log:
FsFLD0S{S|D} and V_SETALLONES are as cheap as moves.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=55466&r1=55465&r2=55466&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Aug 28 02:52:25 2008
@@ -458,7 +458,7 @@
 // start with 'Fs'.
 
 // Alias instructions that map fld0 to pxor for sse.
-let isReMaterializable = 1 in
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
                  "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
                Requires<[HasSSE1]>, TB, OpSize;
@@ -1192,7 +1192,7 @@
 // start with 'Fs'.
 
 // Alias instructions that map fld0 to pxor for sse.
-let isReMaterializable = 1 in
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
                  "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
                Requires<[HasSSE2]>, TB, OpSize;
@@ -2241,7 +2241,7 @@
            (i8 1)), (MFENCE)>;
 
 // Alias instructions that map zero vector to pxor / xorp* for sse.
-let isReMaterializable = 1 in
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
   def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
                          "pcmpeqd\t$dst, $dst",
                          [(set VR128:$dst, (v4i32 immAllOnesV))]>;




From evan.cheng at apple.com  Thu Aug 28 02:53:52 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 28 Aug 2008 07:53:52 -0000
Subject: [llvm-commits] [llvm] r55467 - in /llvm/trunk:
 lib/CodeGen/SimpleRegisterCoalescing.cpp
 lib/CodeGen/SimpleRegisterCoalescing.h
 test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll
 test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
Message-ID: <200808280753.m7S7rqGH001920@zion.cs.uiuc.edu>

Author: evancheng
Date: Thu Aug 28 02:53:51 2008
New Revision: 55467

URL: http://llvm.org/viewvc/llvm-project?rev=55467&view=rev
Log:
If a copy isn't coalesced, but its src is defined by trivial computation. Re-materialize the src to replace the copy.

Modified:
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h
    llvm/trunk/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll
    llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=55467&r1=55466&r2=55467&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Thu Aug 28 02:53:51 2008
@@ -38,6 +38,7 @@
 STATISTIC(numSubJoins , "Number of subclass joins performed");
 STATISTIC(numCommutes , "Number of instruction commuting performed");
 STATISTIC(numExtends  , "Number of copies extended");
+STATISTIC(NumReMats   , "Number of instructions re-materialized");
 STATISTIC(numPeep     , "Number of identity moves eliminated after coalescing");
 STATISTIC(numAborts   , "Number of times interval joining aborted");
 
@@ -426,6 +427,43 @@
   return true;
 }
 
+/// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
+/// computation, replace the copy by rematerialize the definition.
+bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
+                                                       unsigned DstReg,
+                                                       MachineInstr *CopyMI) {
+  unsigned CopyIdx = li_->getUseIndex(li_->getInstructionIndex(CopyMI));
+  LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
+  if (SrcLR == SrcInt.end()) // Should never happen!
+    return false;
+  VNInfo *ValNo = SrcLR->valno;
+  // If other defs can reach uses of this def, then it's not safe to perform
+  // the optimization.
+  if (ValNo->def == ~0U || ValNo->def == ~1U || ValNo->hasPHIKill)
+    return false;
+  MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
+  const TargetInstrDesc &TID = DefMI->getDesc();
+  if (!TID.isAsCheapAsAMove())
+    return false;
+  bool SawStore = false;
+  if (!DefMI->isSafeToMove(tii_, SawStore))
+    return false;
+
+  unsigned DefIdx = li_->getDefIndex(CopyIdx);
+  const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
+  DLR->valno->copy = NULL;
+
+  MachineBasicBlock::iterator MII = CopyMI;
+  MachineBasicBlock *MBB = CopyMI->getParent();
+  tii_->reMaterialize(*MBB, MII, DstReg, DefMI);
+  MachineInstr *NewMI = prior(MII);
+  li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
+  CopyMI->eraseFromParent();
+  ReMatCopies.insert(CopyMI);
+  ++NumReMats;
+  return true;
+}
+
 /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
 ///
 bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
@@ -475,6 +513,17 @@
       unsigned UseDstReg = DstReg;
       if (OldSubIdx)
           UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
+
+      unsigned CopySrcReg, CopyDstReg;
+      if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg) &&
+          CopySrcReg != CopyDstReg &&
+          CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
+        // If the use is a copy and it won't be coalesced away, and its source
+        // is defined by a trivial computation, try to rematerialize it instead.
+        if (ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,UseMI))
+          continue;
+      }
+
       O.setReg(UseDstReg);
       O.setSubReg(0);
     } else {
@@ -865,7 +914,7 @@
   MachineInstr *CopyMI = TheCopy.MI;
 
   Again = false;
-  if (JoinedCopies.count(CopyMI))
+  if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
     return false; // Already done.
 
   DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
@@ -1108,6 +1157,12 @@
 
   if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) {
     // Coalescing failed.
+
+    // If definition of source is defined by trivial computation, try
+    // rematerializing it.
+    if (!isExtSubReg && !isInsSubReg &&
+        ReMaterializeTrivialDef(SrcInt, DstInt.reg, CopyMI))
+      return true;
     
     // If we can eliminate the copy without merging the live ranges, do so now.
     if (!isExtSubReg && !isInsSubReg &&
@@ -1211,9 +1266,6 @@
   if (TargetRegisterInfo::isVirtualRegister(DstReg))
     RemoveUnnecessaryKills(DstReg, *ResDstInt);
 
-  // SrcReg is guarateed to be the register whose live interval that is
-  // being merged.
-  li_->removeInterval(SrcReg);
   if (isInsSubReg)
     // Avoid:
     // r1024 = op
@@ -1223,6 +1275,10 @@
     RemoveDeadImpDef(DstReg, *ResDstInt);
   UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
 
+  // SrcReg is guarateed to be the register whose live interval that is
+  // being merged.
+  li_->removeInterval(SrcReg);
+
   if (isEmpty) {
     // Now the copy is being coalesced away, the val# previously defined
     // by the copy is being defined by an IMPLICIT_DEF which defines a zero
@@ -2018,6 +2074,7 @@
 
 void SimpleRegisterCoalescing::releaseMemory() {
   JoinedCopies.clear();
+  ReMatCopies.clear();
 }
 
 static bool isZeroLengthInterval(LiveInterval *li) {

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h?rev=55467&r1=55466&r2=55467&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Thu Aug 28 02:53:51 2008
@@ -96,6 +96,10 @@
     ///
     SmallPtrSet<MachineInstr*, 32> JoinedCopies;
 
+    /// ReMatCopies - Keep track of copies eliminated due to remat.
+    ///
+    SmallPtrSet<MachineInstr*, 32> ReMatCopies;
+
   public:
     static char ID; // Pass identifcation, replacement for typeid
     SimpleRegisterCoalescing() : MachineFunctionPass((intptr_t)&ID) {}
@@ -194,6 +198,9 @@
     bool RemoveCopyByCommutingDef(LiveInterval &IntA, LiveInterval &IntB,
                                   MachineInstr *CopyMI);
 
+    bool ReMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg,
+                                 MachineInstr *CopyMI);
+
     /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def,
     /// turn the copy into an implicit def.
     bool TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,

Modified: llvm/trunk/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll?rev=55467&r1=55466&r2=55467&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll Thu Aug 28 02:53:51 2008
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | not grep movd
+; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movd | count 1
 ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movq
 ; PR2677
 

Modified: llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll?rev=55467&r1=55466&r2=55467&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll Thu Aug 28 02:53:51 2008
@@ -1,5 +1,7 @@
-; RUN: llvm-as < %s | llc -mcpu=yonah
+; RUN: llvm-as < %s | llc -mcpu=yonah | grep pxor | count 2
+; RUN: llvm-as < %s | llc -mcpu=yonah | not grep movapd
 ; PR2715
+
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-unknown-linux-gnu"
 	%struct.XPTTypeDescriptorPrefix = type { i8 }




From rafael.espindola at gmail.com  Thu Aug 28 09:24:48 2008
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Thu, 28 Aug 2008 14:24:48 -0000
Subject: [llvm-commits] [llvm] r55471 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200808281424.m7SEOnDC025340@zion.cs.uiuc.edu>

Author: rafael
Date: Thu Aug 28 09:24:45 2008
New Revision: 55471

URL: http://llvm.org/viewvc/llvm-project?rev=55471&view=rev
Log:
Correctly resize the Parts array.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=55471&r1=55470&r2=55471&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Aug 28 09:24:45 2008
@@ -4014,7 +4014,7 @@
     unsigned NumRegs = TLI->getNumRegisters(ValueVT);
     MVT RegisterVT = RegVTs[Value];
 
-    Parts.resize(NumRegs);
+    Parts.resize(Part + NumRegs);
     for (unsigned i = 0; i != NumRegs; ++i) {
       SDValue P;
       if (Flag == 0)




From espindola at google.com  Thu Aug 28 11:18:57 2008
From: espindola at google.com (Rafael Espindola)
Date: Thu, 28 Aug 2008 17:18:57 +0100
Subject: [llvm-commits] [patch] add bound checks to SmallVector
Message-ID: <38a0d8450808280918s29a70eefv76a5ee087925c7f@mail.gmail.com>

This patch adds bound checks to SmallVector. I am using it to try to
find memory corruption bugs. Have fixed one so far. Is this to
expensive for a debug build?

Cheers,
-- 
Rafael Avila de Espindola

Google | Gordon House | Barrow Street | Dublin 4 | Ireland
Registered in Dublin, Ireland | Registration Number: 368047
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From gohman at apple.com  Thu Aug 28 12:22:54 2008
From: gohman at apple.com (Dan Gohman)
Date: Thu, 28 Aug 2008 17:22:54 -0000
Subject: [llvm-commits] [llvm] r55475 - in /llvm/trunk:
 lib/CodeGen/SimpleRegisterCoalescing.cpp
 lib/CodeGen/SimpleRegisterCoalescing.h
 test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll
 test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
Message-ID: <200808281722.m7SHMthK031178@zion.cs.uiuc.edu>

Author: djg
Date: Thu Aug 28 12:22:54 2008
New Revision: 55475

URL: http://llvm.org/viewvc/llvm-project?rev=55475&view=rev
Log:
Revert r55467; it causes regressions in UnitTests/Vector/divides,
Benchmarks/sim/sim, and others on x86-64.

Modified:
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h
    llvm/trunk/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll
    llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=55475&r1=55474&r2=55475&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Thu Aug 28 12:22:54 2008
@@ -38,7 +38,6 @@
 STATISTIC(numSubJoins , "Number of subclass joins performed");
 STATISTIC(numCommutes , "Number of instruction commuting performed");
 STATISTIC(numExtends  , "Number of copies extended");
-STATISTIC(NumReMats   , "Number of instructions re-materialized");
 STATISTIC(numPeep     , "Number of identity moves eliminated after coalescing");
 STATISTIC(numAborts   , "Number of times interval joining aborted");
 
@@ -427,43 +426,6 @@
   return true;
 }
 
-/// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
-/// computation, replace the copy by rematerialize the definition.
-bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
-                                                       unsigned DstReg,
-                                                       MachineInstr *CopyMI) {
-  unsigned CopyIdx = li_->getUseIndex(li_->getInstructionIndex(CopyMI));
-  LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
-  if (SrcLR == SrcInt.end()) // Should never happen!
-    return false;
-  VNInfo *ValNo = SrcLR->valno;
-  // If other defs can reach uses of this def, then it's not safe to perform
-  // the optimization.
-  if (ValNo->def == ~0U || ValNo->def == ~1U || ValNo->hasPHIKill)
-    return false;
-  MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
-  const TargetInstrDesc &TID = DefMI->getDesc();
-  if (!TID.isAsCheapAsAMove())
-    return false;
-  bool SawStore = false;
-  if (!DefMI->isSafeToMove(tii_, SawStore))
-    return false;
-
-  unsigned DefIdx = li_->getDefIndex(CopyIdx);
-  const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
-  DLR->valno->copy = NULL;
-
-  MachineBasicBlock::iterator MII = CopyMI;
-  MachineBasicBlock *MBB = CopyMI->getParent();
-  tii_->reMaterialize(*MBB, MII, DstReg, DefMI);
-  MachineInstr *NewMI = prior(MII);
-  li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
-  CopyMI->eraseFromParent();
-  ReMatCopies.insert(CopyMI);
-  ++NumReMats;
-  return true;
-}
-
 /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
 ///
 bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
@@ -513,17 +475,6 @@
       unsigned UseDstReg = DstReg;
       if (OldSubIdx)
           UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
-
-      unsigned CopySrcReg, CopyDstReg;
-      if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg) &&
-          CopySrcReg != CopyDstReg &&
-          CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
-        // If the use is a copy and it won't be coalesced away, and its source
-        // is defined by a trivial computation, try to rematerialize it instead.
-        if (ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,UseMI))
-          continue;
-      }
-
       O.setReg(UseDstReg);
       O.setSubReg(0);
     } else {
@@ -914,7 +865,7 @@
   MachineInstr *CopyMI = TheCopy.MI;
 
   Again = false;
-  if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
+  if (JoinedCopies.count(CopyMI))
     return false; // Already done.
 
   DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
@@ -1157,12 +1108,6 @@
 
   if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) {
     // Coalescing failed.
-
-    // If definition of source is defined by trivial computation, try
-    // rematerializing it.
-    if (!isExtSubReg && !isInsSubReg &&
-        ReMaterializeTrivialDef(SrcInt, DstInt.reg, CopyMI))
-      return true;
     
     // If we can eliminate the copy without merging the live ranges, do so now.
     if (!isExtSubReg && !isInsSubReg &&
@@ -1266,6 +1211,9 @@
   if (TargetRegisterInfo::isVirtualRegister(DstReg))
     RemoveUnnecessaryKills(DstReg, *ResDstInt);
 
+  // SrcReg is guarateed to be the register whose live interval that is
+  // being merged.
+  li_->removeInterval(SrcReg);
   if (isInsSubReg)
     // Avoid:
     // r1024 = op
@@ -1275,10 +1223,6 @@
     RemoveDeadImpDef(DstReg, *ResDstInt);
   UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
 
-  // SrcReg is guarateed to be the register whose live interval that is
-  // being merged.
-  li_->removeInterval(SrcReg);
-
   if (isEmpty) {
     // Now the copy is being coalesced away, the val# previously defined
     // by the copy is being defined by an IMPLICIT_DEF which defines a zero
@@ -2074,7 +2018,6 @@
 
 void SimpleRegisterCoalescing::releaseMemory() {
   JoinedCopies.clear();
-  ReMatCopies.clear();
 }
 
 static bool isZeroLengthInterval(LiveInterval *li) {

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h?rev=55475&r1=55474&r2=55475&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Thu Aug 28 12:22:54 2008
@@ -96,10 +96,6 @@
     ///
     SmallPtrSet<MachineInstr*, 32> JoinedCopies;
 
-    /// ReMatCopies - Keep track of copies eliminated due to remat.
-    ///
-    SmallPtrSet<MachineInstr*, 32> ReMatCopies;
-
   public:
     static char ID; // Pass identifcation, replacement for typeid
     SimpleRegisterCoalescing() : MachineFunctionPass((intptr_t)&ID) {}
@@ -198,9 +194,6 @@
     bool RemoveCopyByCommutingDef(LiveInterval &IntA, LiveInterval &IntB,
                                   MachineInstr *CopyMI);
 
-    bool ReMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg,
-                                 MachineInstr *CopyMI);
-
     /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def,
     /// turn the copy into an implicit def.
     bool TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,

Modified: llvm/trunk/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll?rev=55475&r1=55474&r2=55475&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll Thu Aug 28 12:22:54 2008
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movd | count 1
+; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | not grep movd
 ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movq
 ; PR2677
 

Modified: llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll?rev=55475&r1=55474&r2=55475&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll Thu Aug 28 12:22:54 2008
@@ -1,7 +1,5 @@
-; RUN: llvm-as < %s | llc -mcpu=yonah | grep pxor | count 2
-; RUN: llvm-as < %s | llc -mcpu=yonah | not grep movapd
+; RUN: llvm-as < %s | llc -mcpu=yonah
 ; PR2715
-
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-unknown-linux-gnu"
 	%struct.XPTTypeDescriptorPrefix = type { i8 }




From gohman at apple.com  Thu Aug 28 12:24:41 2008
From: gohman at apple.com (Dan Gohman)
Date: Thu, 28 Aug 2008 10:24:41 -0700
Subject: [llvm-commits] [llvm] r55467 - in /llvm/trunk:
	lib/CodeGen/SimpleRegisterCoalescing.cpp
	lib/CodeGen/SimpleRegisterCoalescing.h
	test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll
	test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
In-Reply-To: <200808280753.m7S7rqGH001920@zion.cs.uiuc.edu>
References: <200808280753.m7S7rqGH001920@zion.cs.uiuc.edu>
Message-ID: <F306A6C8-B1FA-4E8F-BED7-9D801C73F0EC@apple.com>

Hi Evan,

I reverted this patch because it broke UnitTests/Vector/divides,
Benchmarks/sim/sim, and others on x86-64. Please investigate.

Thanks,

Dan

On Aug 28, 2008, at 12:53 AM, Evan Cheng wrote:

> Author: evancheng
> Date: Thu Aug 28 02:53:51 2008
> New Revision: 55467
>
> URL: http://llvm.org/viewvc/llvm-project?rev=55467&view=rev
> Log:
> If a copy isn't coalesced, but its src is defined by trivial  
> computation. Re-materialize the src to replace the copy.
>
> Modified:
>    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
>    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h
>    llvm/trunk/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll
>    llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
>
> Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=55467&r1=55466&r2=55467&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Thu Aug 28  
> 02:53:51 2008
> @@ -38,6 +38,7 @@
> STATISTIC(numSubJoins , "Number of subclass joins performed");
> STATISTIC(numCommutes , "Number of instruction commuting performed");
> STATISTIC(numExtends  , "Number of copies extended");
> +STATISTIC(NumReMats   , "Number of instructions re-materialized");
> STATISTIC(numPeep     , "Number of identity moves eliminated after  
> coalescing");
> STATISTIC(numAborts   , "Number of times interval joining aborted");
>
> @@ -426,6 +427,43 @@
>   return true;
> }
>
> +/// ReMaterializeTrivialDef - If the source of a copy is defined by  
> a trivial
> +/// computation, replace the copy by rematerialize the definition.
> +bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval  
> &SrcInt,
> +                                                       unsigned  
> DstReg,
> +                                                       MachineInstr  
> *CopyMI) {
> +  unsigned CopyIdx = li_->getUseIndex(li_- 
> >getInstructionIndex(CopyMI));
> +  LiveInterval::iterator SrcLR =  
> SrcInt.FindLiveRangeContaining(CopyIdx);
> +  if (SrcLR == SrcInt.end()) // Should never happen!
> +    return false;
> +  VNInfo *ValNo = SrcLR->valno;
> +  // If other defs can reach uses of this def, then it's not safe  
> to perform
> +  // the optimization.
> +  if (ValNo->def == ~0U || ValNo->def == ~1U || ValNo->hasPHIKill)
> +    return false;
> +  MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
> +  const TargetInstrDesc &TID = DefMI->getDesc();
> +  if (!TID.isAsCheapAsAMove())
> +    return false;
> +  bool SawStore = false;
> +  if (!DefMI->isSafeToMove(tii_, SawStore))
> +    return false;
> +
> +  unsigned DefIdx = li_->getDefIndex(CopyIdx);
> +  const LiveRange *DLR= li_- 
> >getInterval(DstReg).getLiveRangeContaining(DefIdx);
> +  DLR->valno->copy = NULL;
> +
> +  MachineBasicBlock::iterator MII = CopyMI;
> +  MachineBasicBlock *MBB = CopyMI->getParent();
> +  tii_->reMaterialize(*MBB, MII, DstReg, DefMI);
> +  MachineInstr *NewMI = prior(MII);
> +  li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
> +  CopyMI->eraseFromParent();
> +  ReMatCopies.insert(CopyMI);
> +  ++NumReMats;
> +  return true;
> +}
> +
> /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
> ///
> bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
> @@ -475,6 +513,17 @@
>       unsigned UseDstReg = DstReg;
>       if (OldSubIdx)
>           UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
> +
> +      unsigned CopySrcReg, CopyDstReg;
> +      if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg) &&
> +          CopySrcReg != CopyDstReg &&
> +          CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
> +        // If the use is a copy and it won't be coalesced away, and  
> its source
> +        // is defined by a trivial computation, try to  
> rematerialize it instead.
> +        if (ReMaterializeTrivialDef(li_->getInterval(SrcReg),  
> CopyDstReg,UseMI))
> +          continue;
> +      }
> +
>       O.setReg(UseDstReg);
>       O.setSubReg(0);
>     } else {
> @@ -865,7 +914,7 @@
>   MachineInstr *CopyMI = TheCopy.MI;
>
>   Again = false;
> -  if (JoinedCopies.count(CopyMI))
> +  if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
>     return false; // Already done.
>
>   DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
> @@ -1108,6 +1157,12 @@
>
>   if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) {
>     // Coalescing failed.
> +
> +    // If definition of source is defined by trivial computation, try
> +    // rematerializing it.
> +    if (!isExtSubReg && !isInsSubReg &&
> +        ReMaterializeTrivialDef(SrcInt, DstInt.reg, CopyMI))
> +      return true;
>
>     // If we can eliminate the copy without merging the live ranges,  
> do so now.
>     if (!isExtSubReg && !isInsSubReg &&
> @@ -1211,9 +1266,6 @@
>   if (TargetRegisterInfo::isVirtualRegister(DstReg))
>     RemoveUnnecessaryKills(DstReg, *ResDstInt);
>
> -  // SrcReg is guarateed to be the register whose live interval  
> that is
> -  // being merged.
> -  li_->removeInterval(SrcReg);
>   if (isInsSubReg)
>     // Avoid:
>     // r1024 = op
> @@ -1223,6 +1275,10 @@
>     RemoveDeadImpDef(DstReg, *ResDstInt);
>   UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
>
> +  // SrcReg is guarateed to be the register whose live interval  
> that is
> +  // being merged.
> +  li_->removeInterval(SrcReg);
> +
>   if (isEmpty) {
>     // Now the copy is being coalesced away, the val# previously  
> defined
>     // by the copy is being defined by an IMPLICIT_DEF which defines  
> a zero
> @@ -2018,6 +2074,7 @@
>
> void SimpleRegisterCoalescing::releaseMemory() {
>   JoinedCopies.clear();
> +  ReMatCopies.clear();
> }
>
> static bool isZeroLengthInterval(LiveInterval *li) {
>
> Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h?rev=55467&r1=55466&r2=55467&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h (original)
> +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Thu Aug 28  
> 02:53:51 2008
> @@ -96,6 +96,10 @@
>     ///
>     SmallPtrSet<MachineInstr*, 32> JoinedCopies;
>
> +    /// ReMatCopies - Keep track of copies eliminated due to remat.
> +    ///
> +    SmallPtrSet<MachineInstr*, 32> ReMatCopies;
> +
>   public:
>     static char ID; // Pass identifcation, replacement for typeid
>     SimpleRegisterCoalescing() : MachineFunctionPass((intptr_t)&ID) {}
> @@ -194,6 +198,9 @@
>     bool RemoveCopyByCommutingDef(LiveInterval &IntA, LiveInterval  
> &IntB,
>                                   MachineInstr *CopyMI);
>
> +    bool ReMaterializeTrivialDef(LiveInterval &SrcInt, unsigned  
> DstReg,
> +                                 MachineInstr *CopyMI);
> +
>     /// TurnCopyIntoImpDef - If source of the specified copy is an  
> implicit def,
>     /// turn the copy into an implicit def.
>     bool TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
>
> Modified: llvm/trunk/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll?rev=55467&r1=55466&r2=55467&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll Thu Aug  
> 28 02:53:51 2008
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | not grep  
> movd
> +; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movd  
> | count 1
> ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movq
> ; PR2677
>
>
> Modified: llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll?rev=55467&r1=55466&r2=55467&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll  
> (original)
> +++ llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll Thu  
> Aug 28 02:53:51 2008
> @@ -1,5 +1,7 @@
> -; RUN: llvm-as < %s | llc -mcpu=yonah
> +; RUN: llvm-as < %s | llc -mcpu=yonah | grep pxor | count 2
> +; RUN: llvm-as < %s | llc -mcpu=yonah | not grep movapd
> ; PR2715
> +
> target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32- 
> i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64- 
> s0:64:64-f80:128:128"
> target triple = "x86_64-unknown-linux-gnu"
> 	%struct.XPTTypeDescriptorPrefix = type { i8 }
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From gohman at apple.com  Thu Aug 28 12:30:03 2008
From: gohman at apple.com (Dan Gohman)
Date: Thu, 28 Aug 2008 10:30:03 -0700
Subject: [llvm-commits] [llvm] r55471 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
In-Reply-To: <200808281424.m7SEOnDC025340@zion.cs.uiuc.edu>
References: <200808281424.m7SEOnDC025340@zion.cs.uiuc.edu>
Message-ID: <CD847517-4475-48FD-9E5F-B4C1886BB7C5@apple.com>


On Aug 28, 2008, at 7:24 AM, Rafael Espindola wrote:
>
> -    Parts.resize(NumRegs);
> +    Parts.resize(Part + NumRegs);

Hi Rafael,

Good catch! One minor comment, the Parts vector still only needs
NumRegs entries here, so could you instead change the places
where Parts is used to use indices [0,NumRegs) instead of
[Parts,NumRegs+Parts)?

Thanks,

Dan



From gohman at apple.com  Thu Aug 28 12:35:44 2008
From: gohman at apple.com (Dan Gohman)
Date: Thu, 28 Aug 2008 10:35:44 -0700
Subject: [llvm-commits] [patch] add bound checks to SmallVector
In-Reply-To: <38a0d8450808280918s29a70eefv76a5ee087925c7f@mail.gmail.com>
References: <38a0d8450808280918s29a70eefv76a5ee087925c7f@mail.gmail.com>
Message-ID: <8A6B72C7-A574-4BF3-A2FF-2C9D5F480615@apple.com>

Hi Rafael,

I suspect it's not too expensive for a debug build, but it would
be nice if you could run a few experiments to verify this. If it
does end up being significant, it would still be appropriate to
add to ENABLE_EXPENSIVE_CHECKS=1 builds at least.

Dan

On Aug 28, 2008, at 9:18 AM, Rafael Espindola wrote:

> This patch adds bound checks to SmallVector. I am using it to try to
> find memory corruption bugs. Have fixed one so far. Is this to
> expensive for a debug build?
>
> Cheers,
> -- 
> Rafael Avila de Espindola
>
> Google | Gordon House | Barrow Street | Dublin 4 | Ireland
> Registered in Dublin, Ireland | Registration Number: 368047
> <assert.patch>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From resistor at mac.com  Thu Aug 28 12:47:37 2008
From: resistor at mac.com (Owen Anderson)
Date: Thu, 28 Aug 2008 17:47:37 -0000
Subject: [llvm-commits] [llvm] r55476 - in /llvm/trunk:
 include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808281747.m7SHlbNY032015@zion.cs.uiuc.edu>

Author: resistor
Date: Thu Aug 28 12:47:37 2008
New Revision: 55476

URL: http://llvm.org/viewvc/llvm-project?rev=55476&view=rev
Log:
FastEmitInst_extractsubreg doesn't need to be passed the register class.  It can get it from MachineRegisterInfo instead.

Modified:
    llvm/trunk/include/llvm/CodeGen/FastISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=55476&r1=55475&r2=55476&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Thu Aug 28 12:47:37 2008
@@ -195,8 +195,7 @@
 
   /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
   /// from a specified index of a superregister.
-  unsigned FastEmitInst_extractsubreg(const TargetRegisterClass *RC,
-                                      unsigned Op0, uint32_t Idx);
+  unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
 
 private:
   unsigned getRegForValue(Value *V,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55476&r1=55475&r2=55476&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Aug 28 12:47:37 2008
@@ -587,8 +587,8 @@
   return ResultReg;
 }
 
-unsigned FastISel::FastEmitInst_extractsubreg(const TargetRegisterClass *RC,
-                                              unsigned Op0, uint32_t Idx) {
+unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) {
+  const TargetRegisterClass* RC = MRI.getRegClass(Op0);
   const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1);
   
   unsigned ResultReg = createResultReg(SRC);




From dalej at apple.com  Thu Aug 28 12:53:09 2008
From: dalej at apple.com (Dale Johannesen)
Date: Thu, 28 Aug 2008 17:53:09 -0000
Subject: [llvm-commits] [llvm] r55478 - in /llvm/trunk/lib/Target/PowerPC:
 PPCISelLowering.cpp PPCISelLowering.h PPCInstrInfo.td
Message-ID: <200808281753.m7SHr9Wl032230@zion.cs.uiuc.edu>

Author: johannes
Date: Thu Aug 28 12:53:09 2008
New Revision: 55478

URL: http://llvm.org/viewvc/llvm-project?rev=55478&view=rev
Log:
Implement partial-word binary atomics on ppc.


Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=55478&r1=55477&r2=55478&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Aug 28 12:53:09 2008
@@ -3915,6 +3915,126 @@
 }
 
 MachineBasicBlock *
+PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, 
+                                            MachineBasicBlock *BB,
+                                            bool is8bit,    // operation
+                                            unsigned BinOpcode) {
+  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
+  // In 64 bit mode we have to use 64 bits for addresses, even though the
+  // lwarx/stwcx are 32 bits.  With the 32-bit atomics we can use address
+  // registers without caring whether they're 32 or 64, but here we're
+  // doing actual arithmetic on the addresses.
+  bool is64bit = PPCSubTarget.isPPC64();
+
+  const BasicBlock *LLVM_BB = BB->getBasicBlock();
+  MachineFunction *F = BB->getParent();
+  MachineFunction::iterator It = BB;
+  ++It;
+
+  unsigned dest = MI->getOperand(0).getReg();
+  unsigned ptrA = MI->getOperand(1).getReg();
+  unsigned ptrB = MI->getOperand(2).getReg();
+  unsigned incr = MI->getOperand(3).getReg();
+
+  MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
+  F->insert(It, loopMBB);
+  F->insert(It, exitMBB);
+  exitMBB->transferSuccessors(BB);
+
+  MachineRegisterInfo &RegInfo = F->getRegInfo();
+  const TargetRegisterClass *RC = 
+    is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass :
+              (const TargetRegisterClass *) &PPC::G8RCRegClass;
+  unsigned TmpReg = RegInfo.createVirtualRegister(RC);
+  unsigned PtrReg = RegInfo.createVirtualRegister(RC);
+  unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
+  unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
+  unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
+  unsigned MaskReg = RegInfo.createVirtualRegister(RC);
+  unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
+  unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
+  unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
+  unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
+  unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
+  unsigned Ptr1Reg;
+
+  //  thisMBB:
+  //   ...
+  //   fallthrough --> loopMBB
+  BB->addSuccessor(loopMBB);
+
+  // The 4-byte load must be aligned, while a char or short may be
+  // anywhere in the word.  Hence all this nasty bookkeeping code.
+  //   add ptr1, ptrA, ptrB [copy if ptrA==0]
+  //   rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
+  //   xor shift, shift1, 24 [16]
+  //   rlwinm ptr, ptr1, 0, 0, 29
+  //   slw incr2, incr, shift
+  //   li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
+  //   slw mask, mask2, shift
+  //  loopMBB:
+  //   l[wd]arx dest, ptr
+  //   add tmp, dest, incr2
+  //   andc tmp2, dest, mask
+  //   and tmp3, tmp, mask
+  //   or tmp4, tmp3, tmp2
+  //   st[wd]cx. tmp4, ptr
+  //   bne- loopMBB
+  //   fallthrough --> exitMBB
+
+  if (ptrA!=PPC::R0) {
+    Ptr1Reg = RegInfo.createVirtualRegister(RC);
+    BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
+      .addReg(ptrA).addReg(ptrB);
+  } else {
+    Ptr1Reg = ptrB;
+  }
+  BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
+      .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
+  BuildMI(BB, TII->get(is64bit ? PPC::XOR8 : PPC::XOR), ShiftReg)
+      .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
+  if (is64bit)
+    BuildMI(BB, TII->get(PPC::RLDICR), PtrReg)
+      .addReg(Ptr1Reg).addImm(0).addImm(61);
+  else
+    BuildMI(BB, TII->get(PPC::RLWINM), PtrReg)
+      .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
+  BuildMI(BB, TII->get(PPC::SLW), Incr2Reg)
+      .addReg(incr).addReg(ShiftReg);
+  if (is8bit)
+    BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255);
+  else {
+    BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0);
+    BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535);
+  }
+  BuildMI(BB, TII->get(PPC::SLW), MaskReg)
+      .addReg(Mask2Reg).addReg(ShiftReg);
+
+  BB = loopMBB;
+  BuildMI(BB, TII->get(PPC::LWARX), dest)
+    .addReg(PPC::R0).addReg(PtrReg);
+  BuildMI(BB, TII->get(BinOpcode), TmpReg).addReg(Incr2Reg).addReg(dest);
+  BuildMI(BB, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
+    .addReg(dest).addReg(MaskReg);
+  BuildMI(BB, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
+    .addReg(TmpReg).addReg(MaskReg);
+  BuildMI(BB, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
+    .addReg(Tmp3Reg).addReg(Tmp2Reg);
+  BuildMI(BB, TII->get(PPC::STWCX))
+    .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
+  BuildMI(BB, TII->get(PPC::BCC))
+    .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);    
+  BB->addSuccessor(loopMBB);
+  BB->addSuccessor(exitMBB);
+
+  //  exitMBB:
+  //   ...
+  BB = exitMBB;
+  return BB;
+}
+
+MachineBasicBlock *
 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
                                                MachineBasicBlock *BB) {
   const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
@@ -3974,30 +4094,60 @@
       .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
       .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
   }
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
+    BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
+    BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
   else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
     BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
   else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
     BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
+
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
+    BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
+    BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
   else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
     BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
   else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
     BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
+
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
+    BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
+    BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
   else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
     BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
   else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
     BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
+
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
+    BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
+    BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
   else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
     BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
   else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
     BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
+
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
+    BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
+    BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
   else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
     BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
   else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
     BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
+
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
+    BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
+  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
+    BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
   else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
     BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
   else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
     BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
+
   else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
            MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
     bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=55478&r1=55477&r2=55478&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Thu Aug 28 12:53:09 2008
@@ -285,6 +285,9 @@
     MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 
                                         MachineBasicBlock *MBB, bool is64Bit,
                                         unsigned BinOpcode);
+    MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI, 
+                                                MachineBasicBlock *MBB, 
+                                                bool is8bit, unsigned Opcode);
     
     ConstraintType getConstraintType(const std::string &Constraint) const;
     std::pair<unsigned, const TargetRegisterClass*> 

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=55478&r1=55477&r2=55478&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Thu Aug 28 12:53:09 2008
@@ -528,6 +528,54 @@
 // Atomic operations
 let usesCustomDAGSchedInserter = 1 in {
   let Uses = [CR0] in {
+    def ATOMIC_LOAD_ADD_I8 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
+      "${:comment} ATOMIC_LOAD_ADD_I8 PSEUDO!",
+      [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;
+    def ATOMIC_LOAD_SUB_I8 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
+      "${:comment} ATOMIC_LOAD_SUB_I8 PSEUDO!",
+      [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>;
+    def ATOMIC_LOAD_AND_I8 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
+      "${:comment} ATOMIC_LOAD_AND_I8 PSEUDO!",
+      [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>;
+    def ATOMIC_LOAD_OR_I8 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
+      "${:comment} ATOMIC_LOAD_OR_I8 PSEUDO!",
+      [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>;
+    def ATOMIC_LOAD_XOR_I8 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
+      "${:comment} ATOMIC_LOAD_XOR_I8 PSEUDO!",
+      [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>;
+    def ATOMIC_LOAD_NAND_I8 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
+      "${:comment} ATOMIC_LOAD_NAND_I8 PSEUDO!",
+      [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>;
+    def ATOMIC_LOAD_ADD_I16 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
+      "${:comment} ATOMIC_LOAD_ADD_I16 PSEUDO!",
+      [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>;
+    def ATOMIC_LOAD_SUB_I16 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
+      "${:comment} ATOMIC_LOAD_SUB_I16 PSEUDO!",
+      [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>;
+    def ATOMIC_LOAD_AND_I16 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
+      "${:comment} ATOMIC_LOAD_AND_I16 PSEUDO!",
+      [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>;
+    def ATOMIC_LOAD_OR_I16 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
+      "${:comment} ATOMIC_LOAD_OR_I16 PSEUDO!",
+      [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>;
+    def ATOMIC_LOAD_XOR_I16 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
+      "${:comment} ATOMIC_LOAD_XOR_I16 PSEUDO!",
+      [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>;
+    def ATOMIC_LOAD_NAND_I16 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
+      "${:comment} ATOMIC_LOAD_NAND_I16 PSEUDO!",
+      [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>;
     def ATOMIC_LOAD_ADD_I32 : Pseudo<
       (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
       "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
@@ -553,12 +601,30 @@
       "${:comment} ATOMIC_LOAD_NAND_I32 PSEUDO!",
       [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
 
+    def ATOMIC_CMP_SWAP_I8 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
+      "${:comment} ATOMIC_CMP_SWAP_I8 PSEUDO!",
+      [(set GPRC:$dst, 
+                    (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
+    def ATOMIC_CMP_SWAP_I16 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
+      "${:comment} ATOMIC_CMP_SWAP_I16 PSEUDO!",
+      [(set GPRC:$dst, 
+                    (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
     def ATOMIC_CMP_SWAP_I32 : Pseudo<
       (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
       "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
       [(set GPRC:$dst, 
                     (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
 
+    def ATOMIC_SWAP_I8 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
+      "${:comment} ATOMIC_SWAP_I8 PSEUDO!",
+      [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>;
+    def ATOMIC_SWAP_I16 : Pseudo<
+      (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
+      "${:comment} ATOMIC_SWAP_I16 PSEUDO!",
+      [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>;
     def ATOMIC_SWAP_I32 : Pseudo<
       (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
       "${:comment} ATOMIC_SWAP_I32 PSEUDO!",




From gohman at apple.com  Thu Aug 28 12:53:08 2008
From: gohman at apple.com (Dan Gohman)
Date: Thu, 28 Aug 2008 10:53:08 -0700
Subject: [llvm-commits] [PATCH] SDNode refactoring
In-Reply-To: <F7CCF048-F36D-4A97-BA7A-D44348F57D32@mac.com>
References: <F7CCF048-F36D-4A97-BA7A-D44348F57D32@mac.com>
Message-ID: <C92C08C5-A959-47BB-B103-1AA97B8FC552@apple.com>

Hi Gabor,

Overall this looks good to me. Comments below.

On Aug 27, 2008, at 3:20 PM, Gabor Greif wrote:

> <SDNode-refactor4-55428.diff>
>
>
> Hi all,
>
> here comes a big patch that cleans up the vocabulary and
> abstraction boundaries of SDNode usage.
>
> It starts at the headers, passes thru TableGen and modifies many
> .cpp files.
>
> To the most part it is just tedious text replacement. But there
> are some details that are worth noting.
>
> Here are the highlights:
>
>
> 1) SDUse::getVal used to return SDNode*& which is actually
> used in some contexts. This breaks abstraction.
> Current solution, make SDUse::getVal return SDNode*
> and satisfy those clients, who actually want to mutate the SDNode*
> with a new interface SDUse::getSDValue() which returns SDValue&.
>
> Analogously, provide SDValue::setNode to set SDValue::Val.
> This accompanies the new SDValue::getVal(), which is a pure getter.

Looks good to me.

>
>
>
> 2) get rid of the anachronistic names in SDValue
> Val -> Node

Yay!

>
> getNode (new)
> setNode (new)

>
>
> Please note that there is still some confusion in SDUse (getVal)
> but I revisit that in a next patch.

Ok.

>
>
>
> 3) This patch does not (intentionally) change the semantics.
> All deja tests still pass.

Even though this patch doesn't change any functionality, it's a
big diff, so it would be good to run more tests than just dejagnu.

>
>
> 4) I expect some 80-col violations. These are best taken care in
> a patch directly after checking in.

Ok.

>
>
>
> And finally here is the most important changes. I excerpt
> them here, with inline comments.
>
>> Index: include/llvm/CodeGen/SelectionDAGNodes.h
>> ===================================================================
>> --- include/llvm/CodeGen/SelectionDAGNodes.h    (Revision 55428)
>> +++ include/llvm/CodeGen/SelectionDAGNodes.h    (Arbeitskopie)
>> @@ -809,29 +809,33 @@
>> /// of information is represented with the SDValue value type.
>> ///
>> class SDValue {
>> -public:
>> -  SDNode *Val;        // The node defining the value we are using.
>> -private:
>> +  SDNode *Node;       // The node defining the value we are using.
>
>
>
> "Val" is named "Node" now and it becomes private.
>
>>   unsigned ResNo;     // Which return value of the node we are using.
>> public:
>> -  SDValue() : Val(0), ResNo(0) {}
>> -  SDValue(SDNode *val, unsigned resno) : Val(val), ResNo(resno) {}
>> +  SDValue() : Node(0), ResNo(0) {}
>> +  SDValue(SDNode *node, unsigned resno) : Node(node), ResNo(resno)  
>> {}
>>
>>   /// get the index which selects a specific result in the SDNode
>>   unsigned getResNo() const { return ResNo; }
>>
>> +  /// get the SDNode which holds the desired result
>> +  SDNode *getNode() const { return Node; }
>> +
>> +  /// set the SDNode
>> +  void setNode(SDNode *N) { Node = N; }
>> +
>
>
> These are the new accessors.
>
>
>>   bool operator==(const SDValue &O) const {
>> -    return Val == O.Val && ResNo == O.ResNo;
>> +    return Node == O.Node && ResNo == O.ResNo;
>>   }
>>   bool operator!=(const SDValue &O) const {
>>     return !operator==(O);
>>   }
>>   bool operator<(const SDValue &O) const {
>> -    return Val < O.Val || (Val == O.Val && ResNo < O.ResNo);
>> +    return Node < O.Node || (Node == O.Node && ResNo < O.ResNo);
>>   }
>>
>>   SDValue getValue(unsigned R) const {
>> -    return SDValue(Val, R);
>> +    return SDValue(Node, R);
>>   }
>>
>>   // isOperandOf - Return true if this node is an operand of N.
>> @@ -866,12 +870,12 @@
>>                                       unsigned Depth = 2) const;
>>
>>   /// use_empty - Return true if there are no nodes using value ResNo
>> -  /// of node Val.
>> +  /// of Node.
>>   ///
>>   inline bool use_empty() const;
>>
>>   /// hasOneUse - Return true if there is exactly one node using  
>> value
>> -  /// ResNo of node Val.
>> +  /// ResNo of Node.
>>   ///
>>   inline bool hasOneUse() const;
>> };
>> @@ -885,8 +889,8 @@
>>     return SDValue((SDNode*)-1, 0);
>>   }
>>   static unsigned getHashValue(const SDValue &Val) {
>> -    return ((unsigned)((uintptr_t)Val.Val >> 4) ^
>> -            (unsigned)((uintptr_t)Val.Val >> 9)) + Val.getResNo();
>> +    return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
>> +            (unsigned)((uintptr_t)Val.getNode() >> 9)) +  
>> Val.getResNo();
>>   }
>>   static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
>>     return LHS == RHS;
>> @@ -899,13 +903,13 @@
>> template<> struct simplify_type<SDValue> {
>>   typedef SDNode* SimpleType;
>>   static SimpleType getSimplifiedValue(const SDValue &Val) {
>> -    return static_cast<SimpleType>(Val.Val);
>> +    return static_cast<SimpleType>(Val.getNode());
>>   }
>> };
>> template<> struct simplify_type<const SDValue> {
>>   typedef SDNode* SimpleType;
>>   static SimpleType getSimplifiedValue(const SDValue &Val) {
>> -    return static_cast<SimpleType>(Val.Val);
>> +    return static_cast<SimpleType>(Val.getNode());
>>   }
>> };
>>
>> @@ -949,8 +953,9 @@
>>
>>   const SDValue& getSDValue() const { return Operand; }
>>
>> -  SDNode *&getVal() { return Operand.Val; }
>> -  SDNode *const &getVal() const { return Operand.Val; }
>> +  SDValue &getSDValue() { return Operand; }
>
>
>
>
> This getter is new. Used by type legalizer, to update
> node inside of SDValue.

>
>
>
>
>>
>> +  SDNode *getVal() { return Operand.getNode(); }
>
>
>
> This is a regular getter now. No reference backdoor.
>
>>
>> +  SDNode *getVal() const { return Operand.getNode(); } // FIXME:  
>> const correct?
>
>
>
> Ditto. I'll take care of the constness issue in an upcoming patch.
>

What is the constness issue? Do you intend for SDUse's getVal() const to
return a const SDNode* ? I don't think that's needed. I think the
current const overload is there to protect the reference to the pointer,
which this patch eliminates anyway.

As you say, it would be good to get Duncan's input on the LegalizeTypes
changes.

Thanks,

Dan




From resistor at mac.com  Thu Aug 28 13:06:12 2008
From: resistor at mac.com (Owen Anderson)
Date: Thu, 28 Aug 2008 18:06:12 -0000
Subject: [llvm-commits] [llvm] r55480 -
	/llvm/trunk/utils/TableGen/FastISelEmitter.cpp
Message-ID: <200808281806.m7SI6C28000468@zion.cs.uiuc.edu>

Author: resistor
Date: Thu Aug 28 13:06:12 2008
New Revision: 55480

URL: http://llvm.org/viewvc/llvm-project?rev=55480&view=rev
Log:
Add support for fast-isel of opcodes that require use of extract_subreg.  Because of how extract_subreg is treated, it requires special case handling.

Modified:
    llvm/trunk/utils/TableGen/FastISelEmitter.cpp

Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=55480&r1=55479&r2=55480&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Thu Aug 28 13:06:12 2008
@@ -172,6 +172,7 @@
 struct InstructionMemo {
   std::string Name;
   const CodeGenRegisterClass *RC;
+  unsigned char SubRegNo;
 };
 
 class FastISelMap {
@@ -235,12 +236,19 @@
 
     // For now, ignore instructions where the first operand is not an
     // output register.
-    Record *Op0Rec = II.OperandList[0].Rec;
-    if (!Op0Rec->isSubClassOf("RegisterClass"))
-      continue;
-    const CodeGenRegisterClass *DstRC = &Target.getRegisterClass(Op0Rec);
-    if (!DstRC)
-      continue;
+    const CodeGenRegisterClass *DstRC = 0;
+    unsigned SubRegNo = ~0;
+    if (Op->getName() != "EXTRACT_SUBREG") {
+      Record *Op0Rec = II.OperandList[0].Rec;
+      if (!Op0Rec->isSubClassOf("RegisterClass"))
+        continue;
+      DstRC = &Target.getRegisterClass(Op0Rec);
+      if (!DstRC)
+        continue;
+    } else {
+      SubRegNo = static_cast<IntInit*>(
+                 Dst->getChild(1)->getLeafValue())->getValue();
+    }
 
     // Inspect the pattern.
     TreePatternNode *InstPatNode = Pattern.getSrcPattern();
@@ -274,7 +282,8 @@
     // Ok, we found a pattern that we can handle. Remember it.
     InstructionMemo Memo = {
       Pattern.getDstPattern()->getOperator()->getName(),
-      DstRC
+      DstRC,
+      SubRegNo
     };
     assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) &&
            "Duplicate pattern!");
@@ -410,13 +419,19 @@
                 HasPred = true;
               }
               OS << "  return FastEmitInst_";
-              Operands.PrintManglingSuffix(OS);
-              OS << "(" << InstNS << Memo.Name << ", ";
-              OS << InstNS << Memo.RC->getName() << "RegisterClass";
-              if (!Operands.empty())
-                OS << ", ";
-              Operands.PrintArguments(OS);
-              OS << ");\n";
+              if (Memo.SubRegNo == (unsigned char)~0) {
+                Operands.PrintManglingSuffix(OS);
+                OS << "(" << InstNS << Memo.Name << ", ";
+                OS << InstNS << Memo.RC->getName() << "RegisterClass";
+                if (!Operands.empty())
+                  OS << ", ";
+                Operands.PrintArguments(OS);
+                OS << ");\n";
+              } else {
+                OS << "extractsubreg(Op0, ";
+                OS << (unsigned)Memo.SubRegNo;
+                OS << ");\n";
+              }
             }
             // Return 0 if none of the predicates were satisfied.
             if (HasPred)
@@ -482,13 +497,20 @@
               HasPred = true;
             }
             OS << "  return FastEmitInst_";
-            Operands.PrintManglingSuffix(OS);
-            OS << "(" << InstNS << Memo.Name << ", ";
-            OS << InstNS << Memo.RC->getName() << "RegisterClass";
-            if (!Operands.empty())
-              OS << ", ";
-            Operands.PrintArguments(OS);
-            OS << ");\n";
+            
+            if (Memo.SubRegNo == (unsigned char)~0) {
+              Operands.PrintManglingSuffix(OS);
+              OS << "(" << InstNS << Memo.Name << ", ";
+              OS << InstNS << Memo.RC->getName() << "RegisterClass";
+              if (!Operands.empty())
+                OS << ", ";
+              Operands.PrintArguments(OS);
+              OS << ");\n";
+            } else {
+              OS << "extractsubreg(Op0, ";
+              OS << (unsigned)Memo.SubRegNo;
+              OS << ");\n";
+            }
           }
           
           // Return 0 if none of the predicates were satisfied.




From dalej at apple.com  Thu Aug 28 13:14:01 2008
From: dalej at apple.com (Dale Johannesen)
Date: Thu, 28 Aug 2008 18:14:01 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r55481 -
 /llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/i386-unaligned-movaps.c
Message-ID: <200808281814.m7SIE1VP000730@zion.cs.uiuc.edu>

Author: johannes
Date: Thu Aug 28 13:14:01 2008
New Revision: 55481

URL: http://llvm.org/viewvc/llvm-project?rev=55481&view=rev
Log:
Expand some arrays and initialize values to avoid wild loads and stores.


Modified:
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/i386-unaligned-movaps.c

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/i386-unaligned-movaps.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/i386-unaligned-movaps.c?rev=55481&r1=55480&r2=55481&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/i386-unaligned-movaps.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/i386-unaligned-movaps.c Thu Aug 28 13:14:01 2008
@@ -36,7 +36,13 @@
 
 int main ()
 {
-  float a[4], b[4], c[4], d[4], e[4];
+  float a[4], b[4], c[6], d[4], e[5];
+  int i;
+  for (i=0; i<4; i++)
+    a[i] = b[i] = c[i] = d[i] = e[i] = i;
+  c[4] = 4;
+  c[5] = 5;
+  e[4] = 4;
   signal (SIGILL, sig_ill_handler);
   foo (2, 2, a, b, c, d, e);
   return 0;




From gohman at apple.com  Thu Aug 28 13:14:06 2008
From: gohman at apple.com (Dan Gohman)
Date: Thu, 28 Aug 2008 11:14:06 -0700
Subject: [llvm-commits] [llvm] r55457 - in /llvm/trunk:
	include/llvm/CodeGen/SelectionDAGNodes.h
	include/llvm/Target/TargetLowering.h
	lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	lib/CodeGen/SelectionDAG/SelectionDAG.cpp
	lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
	lib/Target/TargetSelectionDAG.td lib/Target/X86/X86ISelLowering.cpp
	lib/Target/X86/X86Instr64bit.td lib/Target/X86/X86InstrInfo.td
In-Reply-To: <200808280244.m7S2ioDI016151@zion.cs.uiuc.edu>
References: <200808280244.m7S2ioDI016151@zion.cs.uiuc.edu>
Message-ID: <3D1FD3C4-4F1D-423E-BBF1-3D184394890A@apple.com>


On Aug 27, 2008, at 7:44 PM, Dale Johannesen wrote:

> Author: johannes
> Date: Wed Aug 27 21:44:49 2008
> New Revision: 55457
>
> URL: http://llvm.org/viewvc/llvm-project?rev=55457&view=rev
> Log:
> Split the ATOMIC NodeType's to include the size, e.g.
> ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
> Increased the Hardcoded Constant OpActionsCapacity to match.
> Large but boring; no functional change.
>
> This is to support partial-word atomics on ppc; i8 is
> not a valid type there, so by the time we get to lowering, the
> ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
> The information can be added to the AtomicSDNode, but that is the
> largest SDNode; I don't fully understand the SDNode allocation,
> but it is sensitive to the largest node size, so increasing
> that must be bad.  This is the alternative.


Hi Dale,

I'd like to see if we can find an alternative to this alternative :-).
Here's one idea:

MemSDNode has a MemoryVT member. This is used for truncating
stores and extending loads to indicate the type of the actual
memory access. We don't have extending or truncating atomics,
so I believe it's redundant in AtomicSDNode.

Perhaps MemoryVT could be moved out of MemSDNode and into
LSBaseSDNode? That would allow a new MVT member to be added
to AtomicSDNode without an overall size increase.

What do you think?

Thanks,

Dan



From resistor at mac.com  Thu Aug 28 13:26:01 2008
From: resistor at mac.com (Owen Anderson)
Date: Thu, 28 Aug 2008 18:26:01 -0000
Subject: [llvm-commits] [llvm] r55482 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808281826.m7SIQ1hP001142@zion.cs.uiuc.edu>

Author: resistor
Date: Thu Aug 28 13:26:01 2008
New Revision: 55482

URL: http://llvm.org/viewvc/llvm-project?rev=55482&view=rev
Log:
Hook up support for fast-isel of trunc instructions, using the newly working support for EXTRACT_SUBREG.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55482&r1=55481&r2=55482&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Aug 28 13:26:01 2008
@@ -366,6 +366,9 @@
     case Instruction::SExt:
       if (!SelectCast(I, ISD::SIGN_EXTEND, ValueMap)) return I;
       break;
+    case Instruction::Trunc:
+      if (!SelectCast(I, ISD::TRUNCATE, ValueMap)) return I;
+      break;
     case Instruction::SIToFP:
       if (!SelectCast(I, ISD::SINT_TO_FP, ValueMap)) return I;
       break;
@@ -594,6 +597,6 @@
   unsigned ResultReg = createResultReg(SRC);
   const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
   
-  BuildMI(MBB, II, ResultReg).addReg(Op0);
+  BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx);
   return ResultReg;
 }




From rafael.espindola at gmail.com  Thu Aug 28 13:29:58 2008
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Thu, 28 Aug 2008 18:29:58 -0000
Subject: [llvm-commits] [llvm] r55483 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200808281829.m7SITwMG001267@zion.cs.uiuc.edu>

Author: rafael
Date: Thu Aug 28 13:29:58 2008
New Revision: 55483

URL: http://llvm.org/viewvc/llvm-project?rev=55483&view=rev
Log:
Reduce the size of the Parts vector.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=55483&r1=55482&r2=55483&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Aug 28 13:29:58 2008
@@ -4014,7 +4014,7 @@
     unsigned NumRegs = TLI->getNumRegisters(ValueVT);
     MVT RegisterVT = RegVTs[Value];
 
-    Parts.resize(Part + NumRegs);
+    Parts.resize(NumRegs);
     for (unsigned i = 0; i != NumRegs; ++i) {
       SDValue P;
       if (Flag == 0)
@@ -4067,12 +4067,13 @@
         }
       }
       
-      Parts[Part+i] = P;
+      Parts[i] = P;
     }
   
-    Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT,
+    Values[Value] = getCopyFromParts(DAG, Parts.begin(), NumRegs, RegisterVT,
                                      ValueVT);
     Part += NumRegs;
+    Parts.clear();
   }
 
   return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),




From isanbard at gmail.com  Thu Aug 28 13:29:59 2008
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 28 Aug 2008 18:29:59 -0000
Subject: [llvm-commits] [llvm] r55484 - /llvm/tags/Apple/llvmCore-2067/
Message-ID: <200808281829.m7SITxPT001278@zion.cs.uiuc.edu>

Author: void
Date: Thu Aug 28 13:29:59 2008
New Revision: 55484

URL: http://llvm.org/viewvc/llvm-project?rev=55484&view=rev
Log:
Creating llvmCore-2067 branch

Added:
    llvm/tags/Apple/llvmCore-2067/
      - copied from r55482, llvm/trunk/



From isanbard at gmail.com  Thu Aug 28 13:30:07 2008
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 28 Aug 2008 18:30:07 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r55485 -
	/llvm-gcc-4.2/tags/Apple/llvmgcc42-2067/
Message-ID: <200808281830.m7SIU7O6001307@zion.cs.uiuc.edu>

Author: void
Date: Thu Aug 28 13:30:07 2008
New Revision: 55485

URL: http://llvm.org/viewvc/llvm-project?rev=55485&view=rev
Log:
Creating llvmgcc42-2067 branch

Added:
    llvm-gcc-4.2/tags/Apple/llvmgcc42-2067/
      - copied from r55484, llvm-gcc-4.2/trunk/



From isanbard at gmail.com  Thu Aug 28 13:31:57 2008
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 28 Aug 2008 11:31:57 -0700
Subject: [llvm-commits] [llvm] r55450 - in /llvm/trunk:
	include/llvm/CodeGen/SelectionDAG.h
	include/llvm/CodeGen/SelectionDAGISel.h
	lib/CodeGen/SelectionDAG/SelectionDAG.cpp
	lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
In-Reply-To: <200808272352.m7RNqDWE010999@zion.cs.uiuc.edu>
References: <200808272352.m7RNqDWE010999@zion.cs.uiuc.edu>
Message-ID: <16e5fdf90808281131y629b4cabve76ade3f248c7724@mail.gmail.com>

Dan,

This patch is causing these warnings during the build:

/Volumes/Gir/devel/llvm/llvm.src/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:610:
warning: 'llvm::SelectionDAGLowering' has a field
'llvm::SelectionDAGLowering::SwitchCases' whose type uses the
anonymous namespace
/Volumes/Gir/devel/llvm/llvm.src/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:610:
warning: 'llvm::SelectionDAGLowering' has a field
'llvm::SelectionDAGLowering::JTCases' whose type uses the anonymous
namespace
/Volumes/Gir/devel/llvm/llvm.src/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:610:
warning: 'llvm::SelectionDAGLowering' has a field
'llvm::SelectionDAGLowering::BitTestCases' whose type uses the
anonymous namespace

Could you please investigate these and fix them?

Thanks!
-bw

On Wed, Aug 27, 2008 at 4:52 PM, Dan Gohman <gohman at apple.com> wrote:
> Author: djg
> Date: Wed Aug 27 18:52:12 2008
> New Revision: 55450
>
> URL: http://llvm.org/viewvc/llvm-project?rev=55450&view=rev
> Log:
> Reorganize the lifetimes of the major objects SelectionDAGISel
> works with.
>
> SelectionDAG, FunctionLoweringInfo, and SelectionDAGLowering
> objects now get created once per SelectionDAGISel instance, and
> can be reused across blocks and across functions. Previously,
> they were created and destroyed each time they were needed.
>
> This reorganization simplifies the handling of PHI nodes, and
> also SwitchCases, JumpTables, and BitTestBlocks. This
> simplification has the side effect of fixing a bug in FastISel
> where successor PHI nodes weren't being updated correctly.
>
> This is also a step towards making the transition from FastISel
> into and out of SelectionDAG faster, and also making
> plain SelectionDAG faster on code with lots of little blocks.
>
> Modified:
>    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>    llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=55450&r1=55449&r2=55450&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Aug 27 18:52:12 2008
> @@ -66,7 +66,7 @@
>  ///
>  class SelectionDAG {
>   TargetLowering &TLI;
> -  MachineFunction &MF;
> +  MachineFunction *MF;
>   FunctionLoweringInfo &FLI;
>   MachineModuleInfo *MMI;
>
> @@ -103,16 +103,20 @@
>   void VerifyNode(SDNode *N);
>
>  public:
> -  SelectionDAG(TargetLowering &tli, MachineFunction &mf,
> -               FunctionLoweringInfo &fli, MachineModuleInfo *mmi);
> +  SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli);
>   ~SelectionDAG();
>
> -  /// reset - Clear state and free memory necessary to make this
> +  /// init - Prepare this SelectionDAG to process code in the given
> +  /// MachineFunction.
> +  ///
> +  void init(MachineFunction &mf, MachineModuleInfo *mmi);
> +
> +  /// clear - Clear state and free memory necessary to make this
>   /// SelectionDAG ready to process a new block.
>   ///
> -  void reset();
> +  void clear();
>
> -  MachineFunction &getMachineFunction() const { return MF; }
> +  MachineFunction &getMachineFunction() const { return *MF; }
>   const TargetMachine &getTarget() const;
>   TargetLowering &getTargetLoweringInfo() const { return TLI; }
>   FunctionLoweringInfo &getFunctionLoweringInfo() const { return FLI; }
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=55450&r1=55449&r2=55450&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Wed Aug 27 18:52:12 2008
> @@ -39,7 +39,9 @@
>  public:
>   TargetLowering &TLI;
>   MachineRegisterInfo *RegInfo;
> +  FunctionLoweringInfo *FuncInfo;
>   SelectionDAG *CurDAG;
> +  SelectionDAGLowering *SDL;
>   MachineBasicBlock *BB;
>   AliasAnalysis *AA;
>   GCFunctionInfo *GFI;
> @@ -47,8 +49,8 @@
>   std::vector<SDNode*> TopOrder;
>   static char ID;
>
> -  explicit SelectionDAGISel(TargetLowering &tli, bool fast = false) :
> -    FunctionPass((intptr_t)&ID), TLI(tli), GFI(), Fast(fast), DAGSize(0) {}
> +  explicit SelectionDAGISel(TargetLowering &tli, bool fast = false);
> +  virtual ~SelectionDAGISel();
>
>   TargetLowering &getTargetLowering() { return TLI; }
>
> @@ -87,80 +89,6 @@
>   /// to use for this target when scheduling the DAG.
>   virtual HazardRecognizer *CreateTargetHazardRecognizer();
>
> -  /// CaseBlock - This structure is used to communicate between SDLowering and
> -  /// SDISel for the code generation of additional basic blocks needed by multi-
> -  /// case switch statements.
> -  struct CaseBlock {
> -    CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
> -              MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
> -              MachineBasicBlock *me)
> -      : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
> -        TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
> -    // CC - the condition code to use for the case block's setcc node
> -    ISD::CondCode CC;
> -    // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
> -    // Emit by default LHS op RHS. MHS is used for range comparisons:
> -    // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
> -    Value *CmpLHS, *CmpMHS, *CmpRHS;
> -    // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
> -    MachineBasicBlock *TrueBB, *FalseBB;
> -    // ThisBB - the block into which to emit the code for the setcc and branches
> -    MachineBasicBlock *ThisBB;
> -  };
> -  struct JumpTable {
> -    JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
> -              MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
> -
> -    /// Reg - the virtual register containing the index of the jump table entry
> -    //. to jump to.
> -    unsigned Reg;
> -    /// JTI - the JumpTableIndex for this jump table in the function.
> -    unsigned JTI;
> -    /// MBB - the MBB into which to emit the code for the indirect jump.
> -    MachineBasicBlock *MBB;
> -    /// Default - the MBB of the default bb, which is a successor of the range
> -    /// check MBB.  This is when updating PHI nodes in successors.
> -    MachineBasicBlock *Default;
> -  };
> -  struct JumpTableHeader {
> -    JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
> -                    bool E = false):
> -      First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
> -    uint64_t First;
> -    uint64_t Last;
> -    Value *SValue;
> -    MachineBasicBlock *HeaderBB;
> -    bool Emitted;
> -  };
> -  typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
> -
> -  struct BitTestCase {
> -    BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
> -      Mask(M), ThisBB(T), TargetBB(Tr) { }
> -    uint64_t Mask;
> -    MachineBasicBlock* ThisBB;
> -    MachineBasicBlock* TargetBB;
> -  };
> -
> -  typedef SmallVector<BitTestCase, 3> BitTestInfo;
> -
> -  struct BitTestBlock {
> -    BitTestBlock(uint64_t F, uint64_t R, Value* SV,
> -                 unsigned Rg, bool E,
> -                 MachineBasicBlock* P, MachineBasicBlock* D,
> -                 const BitTestInfo& C):
> -      First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
> -      Parent(P), Default(D), Cases(C) { }
> -    uint64_t First;
> -    uint64_t Range;
> -    Value  *SValue;
> -    unsigned Reg;
> -    bool Emitted;
> -    MachineBasicBlock *Parent;
> -    MachineBasicBlock *Default;
> -    BitTestInfo Cases;
> -  };
> -
>  protected:
>   /// DAGSize - Size of DAG being instruction selected.
>   ///
> @@ -177,40 +105,23 @@
>                     int64_t DesiredMaskS) const;
>
>  private:
> -  void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
> -                            FunctionLoweringInfo &FuncInfo);
> -  void FinishBasicBlock(FunctionLoweringInfo &FuncInfo,
> -             std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate);
> +  void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF);
> +  void FinishBasicBlock();
>
>   void SelectBasicBlock(BasicBlock *LLVMBB,
>                         BasicBlock::iterator Begin,
>                         BasicBlock::iterator End,
> -                        bool DoArgs,
> -             std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
> -                        FunctionLoweringInfo &FuncInfo);
> +                        bool DoArgs);
>   void CodeGenAndEmitDAG();
> -  void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL);
> +  void LowerArguments(BasicBlock *BB);
>
>   void ComputeLiveOutVRegInfo();
>
> -  void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB,
> -                                       FunctionLoweringInfo &FuncInfo,
> -             std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
> -                                       SelectionDAGLowering &SDL);
> +  void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
>
>   /// Pick a safe ordering for instructions for each target node in the
>   /// graph.
>   ScheduleDAG *Schedule();
> -
> -  /// SwitchCases - Vector of CaseBlock structures used to communicate
> -  /// SwitchInst code generation information.
> -  std::vector<CaseBlock> SwitchCases;
> -
> -  /// JTCases - Vector of JumpTable structures which holds necessary information
> -  /// for emitting a jump tables during SwitchInst code generation.
> -  std::vector<JumpTableBlock> JTCases;
> -
> -  std::vector<BitTestBlock> BitTestCases;
>  };
>
>  }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=55450&r1=55449&r2=55450&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Aug 27 18:52:12 2008
> @@ -765,14 +765,18 @@
>   return TLI.getTargetData()->getABITypeAlignment(Ty);
>  }
>
> -SelectionDAG::SelectionDAG(TargetLowering &tli, MachineFunction &mf,
> -                           FunctionLoweringInfo &fli, MachineModuleInfo *mmi)
> -  : TLI(tli), MF(mf), FLI(fli), MMI(mmi),
> -    EntryNode(ISD::EntryToken, getVTList(MVT::Other)),
> +SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli)
> +  : TLI(tli), FLI(fli),
> +    EntryNode(ISD::EntryToken, getVTList(MVT::Other)),
>     Root(getEntryNode()) {
>   AllNodes.push_back(&EntryNode);
>  }
>
> +void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi) {
> +  MF = &mf;
> +  MMI = mmi;
> +}
> +
>  SelectionDAG::~SelectionDAG() {
>   allnodes_clear();
>  }
> @@ -789,7 +793,7 @@
>   }
>  }
>
> -void SelectionDAG::reset() {
> +void SelectionDAG::clear() {
>   allnodes_clear();
>   OperandAllocator.Reset();
>   CSEMap.clear();
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=55450&r1=55449&r2=55450&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Aug 27 18:52:12 2008
> @@ -313,11 +313,16 @@
>   class FunctionLoweringInfo {
>   public:
>     TargetLowering &TLI;
> -    Function &Fn;
> -    MachineFunction &MF;
> -    MachineRegisterInfo &RegInfo;
> -
> -    FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
> +    Function *Fn;
> +    MachineFunction *MF;
> +    MachineRegisterInfo *RegInfo;
> +
> +    explicit FunctionLoweringInfo(TargetLowering &TLI);
> +
> +    /// set - Initialize this FunctionLoweringInfo with the given Function
> +    /// and its associated MachineFunction.
> +    ///
> +    void set(Function &Fn, MachineFunction &MF);
>
>     /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
>     DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
> @@ -338,7 +343,7 @@
>  #endif
>
>     unsigned MakeReg(MVT VT) {
> -      return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
> +      return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
>     }
>
>     /// isExportedInst - Return true if the specified value is an instruction
> @@ -364,6 +369,20 @@
>     /// LiveOutRegInfo - Information about live out vregs, indexed by their
>     /// register number offset by 'FirstVirtualRegister'.
>     std::vector<LiveOutInfo> LiveOutRegInfo;
> +
> +    /// clear - Clear out all the function-specific state. This returns this
> +    /// FunctionLoweringInfo to an empty state, ready to be used for a
> +    /// different function.
> +    void clear() {
> +      MBBMap.clear();
> +      ValueMap.clear();
> +      StaticAllocaMap.clear();
> +#ifndef NDEBUG
> +      CatchInfoLost.clear();
> +      CatchInfoFound.clear();
> +#endif
> +      LiveOutRegInfo.clear();
> +    }
>   };
>  }
>
> @@ -406,13 +425,18 @@
>   return true;
>  }
>
> -FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
> -                                           Function &fn, MachineFunction &mf)
> -    : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
> +FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
> +  : TLI(tli) {
> +}
> +
> +void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf) {
> +   Fn = &fn;
> +   MF = &mf;
> +   RegInfo = &MF->getRegInfo();
>
>   // Create a vreg for each argument register that is not dead and is used
>   // outside of the entry block for the function.
> -  for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
> +  for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
>        AI != E; ++AI)
>     if (!isOnlyUsedInEntryBlock(AI))
>       InitializeRegForValue(AI);
> @@ -420,7 +444,7 @@
>   // Initialize the mapping of values to registers.  This is only set up for
>   // instruction values that are used outside of the block that defines
>   // them.
> -  Function::iterator BB = Fn.begin(), EB = Fn.end();
> +  Function::iterator BB = Fn->begin(), EB = Fn->end();
>   for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
>     if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
>       if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
> @@ -433,7 +457,7 @@
>         TySize *= CUI->getZExtValue();   // Get total allocated size.
>         if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
>         StaticAllocaMap[AI] =
> -          MF.getFrameInfo()->CreateStackObject(TySize, Align);
> +          MF->getFrameInfo()->CreateStackObject(TySize, Align);
>       }
>
>   for (; BB != EB; ++BB)
> @@ -446,10 +470,10 @@
>   // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
>   // also creates the initial PHI MachineInstrs, though none of the input
>   // operands are populated.
> -  for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
> +  for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
>     MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
>     MBBMap[BB] = MBB;
> -    MF.push_back(MBB);
> +    MF->push_back(MBB);
>
>     // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
>     // appropriate.
> @@ -499,6 +523,84 @@
>   return FirstReg;
>  }
>
> +namespace {
> +
> +/// CaseBlock - This structure is used to communicate between SDLowering and
> +/// SDISel for the code generation of additional basic blocks needed by multi-
> +/// case switch statements.
> +struct CaseBlock {
> +  CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
> +            MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
> +            MachineBasicBlock *me)
> +    : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
> +      TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
> +  // CC - the condition code to use for the case block's setcc node
> +  ISD::CondCode CC;
> +  // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
> +  // Emit by default LHS op RHS. MHS is used for range comparisons:
> +  // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
> +  Value *CmpLHS, *CmpMHS, *CmpRHS;
> +  // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
> +  MachineBasicBlock *TrueBB, *FalseBB;
> +  // ThisBB - the block into which to emit the code for the setcc and branches
> +  MachineBasicBlock *ThisBB;
> +};
> +struct JumpTable {
> +  JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
> +            MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
> +
> +  /// Reg - the virtual register containing the index of the jump table entry
> +  //. to jump to.
> +  unsigned Reg;
> +  /// JTI - the JumpTableIndex for this jump table in the function.
> +  unsigned JTI;
> +  /// MBB - the MBB into which to emit the code for the indirect jump.
> +  MachineBasicBlock *MBB;
> +  /// Default - the MBB of the default bb, which is a successor of the range
> +  /// check MBB.  This is when updating PHI nodes in successors.
> +  MachineBasicBlock *Default;
> +};
> +struct JumpTableHeader {
> +  JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
> +                  bool E = false):
> +    First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
> +  uint64_t First;
> +  uint64_t Last;
> +  Value *SValue;
> +  MachineBasicBlock *HeaderBB;
> +  bool Emitted;
> +};
> +typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
> +
> +struct BitTestCase {
> +  BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
> +    Mask(M), ThisBB(T), TargetBB(Tr) { }
> +  uint64_t Mask;
> +  MachineBasicBlock* ThisBB;
> +  MachineBasicBlock* TargetBB;
> +};
> +
> +typedef SmallVector<BitTestCase, 3> BitTestInfo;
> +
> +struct BitTestBlock {
> +  BitTestBlock(uint64_t F, uint64_t R, Value* SV,
> +               unsigned Rg, bool E,
> +               MachineBasicBlock* P, MachineBasicBlock* D,
> +               const BitTestInfo& C):
> +    First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
> +    Parent(P), Default(D), Cases(C) { }
> +  uint64_t First;
> +  uint64_t Range;
> +  Value  *SValue;
> +  unsigned Reg;
> +  bool Emitted;
> +  MachineBasicBlock *Parent;
> +  MachineBasicBlock *Default;
> +  BitTestInfo Cases;
> +};
> +
> +} // end anonymous namespace
> +
>  //===----------------------------------------------------------------------===//
>  /// SelectionDAGLowering - This is the common target-independent lowering
>  /// implementation that is parameterized by a TargetLowering object.
> @@ -521,7 +623,7 @@
>   /// instruction, but they have no other ordering requirements. We bunch them
>   /// up and the emit a single tokenfactor for them just before terminator
>   /// instructions.
> -  std::vector<SDValue> PendingExports;
> +  SmallVector<SDValue, 8> PendingExports;
>
>   /// Case - A struct to record the Value for a switch case, and the
>   /// case's target basic block.
> @@ -599,16 +701,24 @@
>   TargetLowering &TLI;
>   SelectionDAG &DAG;
>   const TargetData *TD;
> -  AliasAnalysis &AA;
> +  AliasAnalysis *AA;
>
>   /// SwitchCases - Vector of CaseBlock structures used to communicate
>   /// SwitchInst code generation information.
> -  std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
> +  std::vector<CaseBlock> SwitchCases;
>   /// JTCases - Vector of JumpTable structures used to communicate
>   /// SwitchInst code generation information.
> -  std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
> -  std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
> +  std::vector<JumpTableBlock> JTCases;
> +  /// BitTestCases - Vector of BitTestBlock structures used to communicate
> +  /// SwitchInst code generation information.
> +  std::vector<BitTestBlock> BitTestCases;
>
> +  std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
> +
> +  // Emit PHI-node-operand constants only once even if used by multiple
> +  // PHI nodes.
> +  DenseMap<Constant*, unsigned> ConstantsOut;
> +
>   /// FuncInfo - Information about the function as a whole.
>   ///
>   FunctionLoweringInfo &FuncInfo;
> @@ -617,11 +727,27 @@
>   GCFunctionInfo *GFI;
>
>   SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
> -                       AliasAnalysis &aa,
> -                       FunctionLoweringInfo &funcinfo,
> -                       GCFunctionInfo *gfi)
> -    : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
> -      FuncInfo(funcinfo), GFI(gfi) {
> +                       FunctionLoweringInfo &funcinfo)
> +    : TLI(tli), DAG(dag), FuncInfo(funcinfo) {
> +  }
> +
> +  void init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
> +    AA = &aa;
> +    GFI = gfi;
> +    TD = DAG.getTarget().getTargetData();
> +  }
> +
> +  /// clear - Clear out the curret SelectionDAG and the associated
> +  /// state and prepare this SelectionDAGLowering object to be used
> +  /// for a new block. This doesn't clear out information about
> +  /// additional blocks that are needed to complete switch lowering
> +  /// or PHI node updating; that information is cleared out as it is
> +  /// consumed.
> +  void clear() {
> +    NodeMap.clear();
> +    PendingLoads.clear();
> +    PendingExports.clear();
> +    DAG.clear();
>   }
>
>   /// getRoot - Return the current virtual root of the Selection DAG,
> @@ -741,14 +867,13 @@
>                                 CaseRecVector& WorkList,
>                                 Value* SV,
>                                 MachineBasicBlock* Default);
> -  void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
> -  void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
> +  void visitSwitchCase(CaseBlock &CB);
> +  void visitBitTestHeader(BitTestBlock &B);
>   void visitBitTestCase(MachineBasicBlock* NextMBB,
>                         unsigned Reg,
> -                        SelectionDAGISel::BitTestCase &B);
> -  void visitJumpTable(SelectionDAGISel::JumpTable &JT);
> -  void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
> -                            SelectionDAGISel::JumpTableHeader &JTH);
> +                        BitTestCase &B);
> +  void visitJumpTable(JumpTable &JT);
> +  void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH);
>
>   // These all get lowered before this pass.
>   void visitInvoke(InvokeInst &I);
> @@ -1437,15 +1562,15 @@
>         assert(0 && "Unknown compare instruction");
>       }
>
> -      SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
> -                                     BOp->getOperand(1), NULL, TBB, FBB, CurBB);
> +      CaseBlock CB(Condition, BOp->getOperand(0),
> +                   BOp->getOperand(1), NULL, TBB, FBB, CurBB);
>       SwitchCases.push_back(CB);
>       return;
>     }
>
>     // Create a CaseBlock record representing this branch.
> -    SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
> -                                   NULL, TBB, FBB, CurBB);
> +    CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
> +                 NULL, TBB, FBB, CurBB);
>     SwitchCases.push_back(CB);
>     return;
>   }
> @@ -1494,7 +1619,7 @@
>  /// If we should emit this as a bunch of and/or'd together conditions, return
>  /// false.
>  static bool
> -ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
> +ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
>   if (Cases.size() != 2) return true;
>
>   // If this is two comparisons of the same values or'd or and'd together, they
> @@ -1583,8 +1708,8 @@
>   }
>
>   // Create a CaseBlock record representing this branch.
> -  SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
> -                                 NULL, Succ0MBB, Succ1MBB, CurMBB);
> +  CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
> +               NULL, Succ0MBB, Succ1MBB, CurMBB);
>   // Use visitSwitchCase to actually insert the fast branch sequence for this
>   // cond branch.
>   visitSwitchCase(CB);
> @@ -1592,7 +1717,7 @@
>
>  /// visitSwitchCase - Emits the necessary code to represent a single node in
>  /// the binary search tree resulting from lowering a switch instruction.
> -void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
> +void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
>   SDValue Cond;
>   SDValue CondLHS = getValue(CB.CmpLHS);
>
> @@ -1664,7 +1789,7 @@
>  }
>
>  /// visitJumpTable - Emit JumpTable node in the current MBB
> -void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
> +void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
>   // Emit the code for the jump table
>   assert(JT.Reg != -1U && "Should lower JT Header first!");
>   MVT PTy = TLI.getPointerTy();
> @@ -1677,8 +1802,8 @@
>
>  /// visitJumpTableHeader - This function emits necessary code to produce index
>  /// in the JumpTable from switch case.
> -void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
> -                                         SelectionDAGISel::JumpTableHeader &JTH) {
> +void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
> +                                                JumpTableHeader &JTH) {
>   // Subtract the lowest switch case value from the value being switched on
>   // and conditional branch to default mbb if the result is greater than the
>   // difference between smallest and largest cases.
> @@ -1729,7 +1854,7 @@
>
>  /// visitBitTestHeader - This function emits necessary code to produce value
>  /// suitable for "bit tests"
> -void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
> +void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
>   // Subtract the minimum value
>   SDValue SwitchOp = getValue(B.SValue);
>   MVT VT = SwitchOp.getValueType();
> @@ -1783,7 +1908,7 @@
>  /// visitBitTestCase - this function produces one "bit test"
>  void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
>                                             unsigned Reg,
> -                                            SelectionDAGISel::BitTestCase &B) {
> +                                            BitTestCase &B) {
>   // Emit bit tests and jumps
>   SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
>                                            TLI.getPointerTy());
> @@ -1911,8 +2036,7 @@
>       CC = ISD::SETLE;
>       LHS = I->Low; MHS = SV; RHS = I->High;
>     }
> -    SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
> -                                   I->BB, FallThrough, CurBlock);
> +    CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
>
>     // If emitting the first comparison, just call visitSwitchCase to emit the
>     // code into the current block.  Otherwise, push the CaseBlock onto the
> @@ -2019,13 +2143,12 @@
>
>   // Set the jump table information so that we can codegen it as a second
>   // MachineBasicBlock
> -  SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
> -  SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
> -                                        (CR.CaseBB == CurMBB));
> +  JumpTable JT(-1U, JTI, JumpTableBB, Default);
> +  JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
>   if (CR.CaseBB == CurMBB)
>     visitJumpTableHeader(JT, JTH);
>
> -  JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
> +  JTCases.push_back(JumpTableBlock(JTH, JT));
>
>   return true;
>  }
> @@ -2139,8 +2262,7 @@
>   // Create a CaseBlock record representing a conditional branch to
>   // the LHS node if the value being switched on SV is less than C.
>   // Otherwise, branch to LHS.
> -  SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
> -                                 TrueBB, FalseBB, CR.CaseBB);
> +  CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
>
>   if (CR.CaseBB == CurMBB)
>     visitSwitchCase(CB);
> @@ -2241,7 +2363,7 @@
>   }
>   std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
>
> -  SelectionDAGISel::BitTestInfo BTC;
> +  BitTestInfo BTC;
>
>   // Figure out which block is immediately after the current one.
>   MachineFunction::iterator BBI = CR.CaseBB;
> @@ -2256,14 +2378,14 @@
>
>     MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
>     CurMF->insert(BBI, CaseBB);
> -    BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
> -                                                CaseBB,
> -                                                CasesBits[i].BB));
> +    BTC.push_back(BitTestCase(CasesBits[i].Mask,
> +                              CaseBB,
> +                              CasesBits[i].BB));
>   }
>
> -  SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
> -                                     -1U, (CR.CaseBB == CurMBB),
> -                                     CR.CaseBB, Default, BTC);
> +  BitTestBlock BTB(lowBound, range, SV,
> +                   -1U, (CR.CaseBB == CurMBB),
> +                   CR.CaseBB, Default, BTC);
>
>   if (CR.CaseBB == CurMBB)
>     visitBitTestHeader(BTB);
> @@ -2906,7 +3028,7 @@
>   if (I.isVolatile())
>     // Serialize volatile loads with other side effects.
>     Root = getRoot();
> -  else if (AA.pointsToConstantMemory(SV)) {
> +  else if (AA->pointsToConstantMemory(SV)) {
>     // Do not serialize (non-volatile) loads of constant memory with anything.
>     Root = DAG.getEntryNode();
>     ConstantMemory = true;
> @@ -3188,7 +3310,7 @@
>     uint64_t Size = -1ULL;
>     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
>       Size = C->getValue();
> -    if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
> +    if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
>         AliasAnalysis::NoAlias) {
>       DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
>                                 I.getOperand(1), 0, I.getOperand(2), 0));
> @@ -4885,6 +5007,22 @@
>  // SelectionDAGISel code
>  //===----------------------------------------------------------------------===//
>
> +SelectionDAGISel::SelectionDAGISel(TargetLowering &tli, bool fast) :
> +  FunctionPass((intptr_t)&ID), TLI(tli),
> +  FuncInfo(new FunctionLoweringInfo(TLI)),
> +  CurDAG(new SelectionDAG(TLI, *FuncInfo)),
> +  SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo)),
> +  GFI(),
> +  Fast(fast),
> +  DAGSize(0)
> +{}
> +
> +SelectionDAGISel::~SelectionDAGISel() {
> +  delete SDL;
> +  delete CurDAG;
> +  delete FuncInfo;
> +}
> +
>  unsigned SelectionDAGISel::MakeReg(MVT VT) {
>   return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
>  }
> @@ -4907,28 +5045,32 @@
>   RegInfo = &MF.getRegInfo();
>   DOUT << "\n\n\n=== " << Fn.getName() << "\n";
>
> -  FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
> +  FuncInfo->set(Fn, MF);
> +  CurDAG->init(MF, getAnalysisToUpdate<MachineModuleInfo>());
> +  SDL->init(GFI, *AA);
>
>   for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
>     if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
>       // Mark landing pad.
> -      FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
> +      FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
>
> -  SelectAllBasicBlocks(Fn, MF, FuncInfo);
> +  SelectAllBasicBlocks(Fn, MF);
>
>   // Add function live-ins to entry block live-in set.
>   BasicBlock *EntryBB = &Fn.getEntryBlock();
> -  BB = FuncInfo.MBBMap[EntryBB];
> +  BB = FuncInfo->MBBMap[EntryBB];
>   if (!RegInfo->livein_empty())
>     for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
>            E = RegInfo->livein_end(); I != E; ++I)
>       BB->addLiveIn(I->first);
>
>  #ifndef NDEBUG
> -  assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
> +  assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
>          "Not all catch info was assigned to a landing pad!");
>  #endif
>
> +  FuncInfo->clear();
> +
>   return true;
>  }
>
> @@ -4946,13 +5088,12 @@
>  }
>
>  void SelectionDAGISel::
> -LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
> +LowerArguments(BasicBlock *LLVMBB) {
>   // If this is the entry block, emit arguments.
>   Function &F = *LLVMBB->getParent();
> -  FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
> -  SDValue OldRoot = SDL.DAG.getRoot();
> +  SDValue OldRoot = SDL->DAG.getRoot();
>   SmallVector<SDValue, 16> Args;
> -  TLI.LowerArguments(F, SDL.DAG, Args);
> +  TLI.LowerArguments(F, SDL->DAG, Args);
>
>   unsigned a = 0;
>   for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
> @@ -4961,12 +5102,12 @@
>     ComputeValueVTs(TLI, AI->getType(), ValueVTs);
>     unsigned NumValues = ValueVTs.size();
>     if (!AI->use_empty()) {
> -      SDL.setValue(AI, SDL.DAG.getMergeValues(&Args[a], NumValues));
> +      SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues));
>       // If this argument is live outside of the entry block, insert a copy from
>       // whereever we got it to the vreg that other BB's will reference it as.
> -      DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
> -      if (VMI != FuncInfo.ValueMap.end()) {
> -        SDL.CopyValueToVirtualRegister(AI, VMI->second);
> +      DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo->ValueMap.find(AI);
> +      if (VMI != FuncInfo->ValueMap.end()) {
> +        SDL->CopyValueToVirtualRegister(AI, VMI->second);
>       }
>     }
>     a += NumValues;
> @@ -4974,7 +5115,7 @@
>
>   // Finally, if the target has anything special to do, allow it to do so.
>   // FIXME: this should insert code into the DAG!
> -  EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
> +  EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
>  }
>
>  static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
> @@ -5107,31 +5248,21 @@
>  /// the end.
>  ///
>  void
> -SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB,
> -                                                 FunctionLoweringInfo &FuncInfo,
> -             std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
> -                                                  SelectionDAGLowering &SDL) {
> +SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
>   TerminatorInst *TI = LLVMBB->getTerminator();
>
> -  // Emit constants only once even if used by multiple PHI nodes.
> -  std::map<Constant*, unsigned> ConstantsOut;
> -
> -  BitVector SuccsHandled;
> -  if (TI->getNumSuccessors())
> -    SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
> -
> +  SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
> +
>   // Check successor nodes' PHI nodes that expect a constant to be available
>   // from this block.
>   for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
>     BasicBlock *SuccBB = TI->getSuccessor(succ);
>     if (!isa<PHINode>(SuccBB->begin())) continue;
> -    MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
> +    MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
>
>     // If this terminator has multiple identical successors (common for
>     // switches), only handle each succ once.
> -    unsigned SuccMBBNo = SuccMBB->getNumber();
> -    if (SuccsHandled[SuccMBBNo]) continue;
> -    SuccsHandled[SuccMBBNo] = true;
> +    if (!SuccsHandled.insert(SuccMBB)) continue;
>
>     MachineBasicBlock::iterator MBBI = SuccMBB->begin();
>     PHINode *PN;
> @@ -5143,25 +5274,25 @@
>          (PN = dyn_cast<PHINode>(I)); ++I) {
>       // Ignore dead phi's.
>       if (PN->use_empty()) continue;
> -
> +
>       unsigned Reg;
>       Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
> -
> +
>       if (Constant *C = dyn_cast<Constant>(PHIOp)) {
> -        unsigned &RegOut = ConstantsOut[C];
> +        unsigned &RegOut = SDL->ConstantsOut[C];
>         if (RegOut == 0) {
> -          RegOut = FuncInfo.CreateRegForValue(C);
> -          SDL.CopyValueToVirtualRegister(C, RegOut);
> +          RegOut = FuncInfo->CreateRegForValue(C);
> +          SDL->CopyValueToVirtualRegister(C, RegOut);
>         }
>         Reg = RegOut;
>       } else {
> -        Reg = FuncInfo.ValueMap[PHIOp];
> +        Reg = FuncInfo->ValueMap[PHIOp];
>         if (Reg == 0) {
>           assert(isa<AllocaInst>(PHIOp) &&
> -                 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
> +                 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
>                  "Didn't codegen value into a register!??");
> -          Reg = FuncInfo.CreateRegForValue(PHIOp);
> -          SDL.CopyValueToVirtualRegister(PHIOp, Reg);
> +          Reg = FuncInfo->CreateRegForValue(PHIOp);
> +          SDL->CopyValueToVirtualRegister(PHIOp, Reg);
>         }
>       }
>
> @@ -5173,39 +5304,26 @@
>         MVT VT = ValueVTs[vti];
>         unsigned NumRegisters = TLI.getNumRegisters(VT);
>         for (unsigned i = 0, e = NumRegisters; i != e; ++i)
> -          PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
> +          SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
>         Reg += NumRegisters;
>       }
>     }
>   }
> -  ConstantsOut.clear();
> +  SDL->ConstantsOut.clear();
>
>   // Lower the terminator after the copies are emitted.
> -  SDL.visit(*LLVMBB->getTerminator());
> -
> -  // Copy over any CaseBlock records that may now exist due to SwitchInst
> -  // lowering, as well as any jump table information.
> -  SwitchCases.clear();
> -  SwitchCases = SDL.SwitchCases;
> -  JTCases.clear();
> -  JTCases = SDL.JTCases;
> -  BitTestCases.clear();
> -  BitTestCases = SDL.BitTestCases;
> +  SDL->visit(*LLVMBB->getTerminator());
>  }
>
>  void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
>                                         BasicBlock::iterator Begin,
>                                         BasicBlock::iterator End,
> -                                        bool DoArgs,
> -       std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
> -                                        FunctionLoweringInfo &FuncInfo) {
> -  SelectionDAGLowering SDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
> -
> +                                        bool DoArgs) {
>   // Lower any arguments needed in this block if this is the entry block.
>   if (DoArgs)
> -    LowerArguments(LLVMBB, SDL);
> +    LowerArguments(LLVMBB);
>
> -  SDL.setCurrentBasicBlock(BB);
> +  SDL->setCurrentBasicBlock(BB);
>
>   MachineModuleInfo *MMI = CurDAG->getMachineModuleInfo();
>
> @@ -5245,30 +5363,30 @@
>
>       if (I == E)
>         // No catch info found - try to extract some from the successor.
> -        copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
> +        copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
>     }
>   }
>
>   // Lower all of the non-terminator instructions.
>   for (BasicBlock::iterator I = Begin; I != End; ++I)
>     if (!isa<TerminatorInst>(I))
> -      SDL.visit(*I);
> +      SDL->visit(*I);
>
>   // Ensure that all instructions which are used outside of their defining
>   // blocks are available as virtual registers.  Invoke is handled elsewhere.
>   for (BasicBlock::iterator I = Begin; I != End; ++I)
>     if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
> -      DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
> -      if (VMI != FuncInfo.ValueMap.end())
> -        SDL.CopyValueToVirtualRegister(I, VMI->second);
> +      DenseMap<const Value*,unsigned>::iterator VMI =FuncInfo->ValueMap.find(I);
> +      if (VMI != FuncInfo->ValueMap.end())
> +        SDL->CopyValueToVirtualRegister(I, VMI->second);
>     }
>
>   // Handle PHI nodes in successor blocks.
>   if (Begin != End && End == LLVMBB->end())
> -    HandlePHINodesInSuccessorBlocks(LLVMBB, FuncInfo, PHINodesToUpdate, SDL);
> +    HandlePHINodesInSuccessorBlocks(LLVMBB);
>
>   // Make sure the root of the DAG is up-to-date.
> -  CurDAG->setRoot(SDL.getControlRoot());
> +  CurDAG->setRoot(SDL->getControlRoot());
>
>   // Check whether calls in this block are real tail calls. Fix up CALL nodes
>   // with correct tailcall attribute so that the target can rely on the tailcall
> @@ -5278,7 +5396,7 @@
>
>   // Final step, emit the lowered DAG as machine code.
>   CodeGenAndEmitDAG();
> -  CurDAG->reset();
> +  SDL->clear();
>  }
>
>  void SelectionDAGISel::ComputeLiveOutVRegInfo() {
> @@ -5457,18 +5575,10 @@
>   DEBUG(BB->dump());
>  }
>
> -void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
> -                                            FunctionLoweringInfo &FuncInfo) {
> -  // Define the SelectionDAG here so that memory allocation is reused for
> -  // each basic block.
> -  SelectionDAG DAG(TLI, MF, FuncInfo,
> -                   getAnalysisToUpdate<MachineModuleInfo>());
> -  CurDAG = &DAG;
> -
> -  std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
> +void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF) {
>   for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
>     BasicBlock *LLVMBB = &*I;
> -    BB = FuncInfo.MBBMap[LLVMBB];
> +    BB = FuncInfo->MBBMap[LLVMBB];
>
>     BasicBlock::iterator Begin = LLVMBB->begin();
>     BasicBlock::iterator End = LLVMBB->end();
> @@ -5477,10 +5587,10 @@
>     // Before doing SelectionDAG ISel, see if FastISel has been requested.
>     // FastISel doesn't support EH landing pads, which require special handling.
>     if (EnableFastISel && !BB->isLandingPad()) {
> -      if (FastISel *F = TLI.createFastISel(FuncInfo.MF)) {
> +      if (FastISel *F = TLI.createFastISel(*FuncInfo->MF)) {
>         while (Begin != End) {
> -          Begin = F->SelectInstructions(Begin, End, FuncInfo.ValueMap,
> -                                        FuncInfo.MBBMap, BB);
> +          Begin = F->SelectInstructions(Begin, End, FuncInfo->ValueMap,
> +                                        FuncInfo->MBBMap, BB);
>
>           if (Begin == End)
>             // The "fast" selector selected the entire block, so we're done.
> @@ -5490,13 +5600,12 @@
>           if (isa<CallInst>(Begin) || isa<LoadInst>(Begin) ||
>               isa<StoreInst>(Begin)) {
>             if (Begin->getType() != Type::VoidTy) {
> -              unsigned &R = FuncInfo.ValueMap[Begin];
> +              unsigned &R = FuncInfo->ValueMap[Begin];
>               if (!R)
> -                R = FuncInfo.CreateRegForValue(Begin);
> +                R = FuncInfo->CreateRegForValue(Begin);
>             }
>
> -            SelectBasicBlock(LLVMBB, Begin, next(Begin), DoArgs,
> -                             PHINodesToUpdate, FuncInfo);
> +            SelectBasicBlock(LLVMBB, Begin, next(Begin), DoArgs);
>
>             ++Begin;
>             DoArgs = false;
> @@ -5522,18 +5631,14 @@
>     }
>
>     if (Begin != End || DoArgs)
> -      SelectBasicBlock(LLVMBB, Begin, End, DoArgs, PHINodesToUpdate, FuncInfo);
> +      SelectBasicBlock(LLVMBB, Begin, End, DoArgs);
>
> -    FinishBasicBlock(FuncInfo, PHINodesToUpdate);
> -    PHINodesToUpdate.clear();
> +    FinishBasicBlock();
>   }
> -
> -  CurDAG = 0;
>  }
>
>  void
> -SelectionDAGISel::FinishBasicBlock(FunctionLoweringInfo &FuncInfo,
> -             std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate) {
> +SelectionDAGISel::FinishBasicBlock() {
>
>   // Perform target specific isel post processing.
>   InstructionSelectPostProcessing();
> @@ -5542,146 +5647,148 @@
>   DEBUG(BB->dump());
>
>   DOUT << "Total amount of phi nodes to update: "
> -       << PHINodesToUpdate.size() << "\n";
> -  DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
> -          DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
> -               << ", " << PHINodesToUpdate[i].second << ")\n";);
> +       << SDL->PHINodesToUpdate.size() << "\n";
> +  DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i)
> +          DOUT << "Node " << i << " : (" << SDL->PHINodesToUpdate[i].first
> +               << ", " << SDL->PHINodesToUpdate[i].second << ")\n";);
>
>   // Next, now that we know what the last MBB the LLVM BB expanded is, update
>   // PHI nodes in successors.
> -  if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
> -    for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
> -      MachineInstr *PHI = PHINodesToUpdate[i].first;
> +  if (SDL->SwitchCases.empty() &&
> +      SDL->JTCases.empty() &&
> +      SDL->BitTestCases.empty()) {
> +    for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
> +      MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
>       assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
>              "This is not a machine PHI node that we are updating!");
> -      PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
> +      PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
>                                                 false));
>       PHI->addOperand(MachineOperand::CreateMBB(BB));
>     }
> +    SDL->PHINodesToUpdate.clear();
>     return;
>   }
>
> -  for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
> +  for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) {
>     // Lower header first, if it wasn't already lowered
> -    if (!BitTestCases[i].Emitted) {
> -      SelectionDAGLowering HSDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
> +    if (!SDL->BitTestCases[i].Emitted) {
>       // Set the current basic block to the mbb we wish to insert the code into
> -      BB = BitTestCases[i].Parent;
> -      HSDL.setCurrentBasicBlock(BB);
> +      BB = SDL->BitTestCases[i].Parent;
> +      SDL->setCurrentBasicBlock(BB);
>       // Emit the code
> -      HSDL.visitBitTestHeader(BitTestCases[i]);
> -      CurDAG->setRoot(HSDL.getRoot());
> +      SDL->visitBitTestHeader(SDL->BitTestCases[i]);
> +      CurDAG->setRoot(SDL->getRoot());
>       CodeGenAndEmitDAG();
> -      CurDAG->reset();
> +      SDL->clear();
>     }
>
> -    for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
> -      SelectionDAGLowering BSDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
> +    for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) {
>       // Set the current basic block to the mbb we wish to insert the code into
> -      BB = BitTestCases[i].Cases[j].ThisBB;
> -      BSDL.setCurrentBasicBlock(BB);
> +      BB = SDL->BitTestCases[i].Cases[j].ThisBB;
> +      SDL->setCurrentBasicBlock(BB);
>       // Emit the code
>       if (j+1 != ej)
> -        BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
> -                              BitTestCases[i].Reg,
> -                              BitTestCases[i].Cases[j]);
> +        SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB,
> +                              SDL->BitTestCases[i].Reg,
> +                              SDL->BitTestCases[i].Cases[j]);
>       else
> -        BSDL.visitBitTestCase(BitTestCases[i].Default,
> -                              BitTestCases[i].Reg,
> -                              BitTestCases[i].Cases[j]);
> +        SDL->visitBitTestCase(SDL->BitTestCases[i].Default,
> +                              SDL->BitTestCases[i].Reg,
> +                              SDL->BitTestCases[i].Cases[j]);
>
>
> -      CurDAG->setRoot(BSDL.getRoot());
> +      CurDAG->setRoot(SDL->getRoot());
>       CodeGenAndEmitDAG();
> -      CurDAG->reset();
> +      SDL->clear();
>     }
>
>     // Update PHI Nodes
> -    for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
> -      MachineInstr *PHI = PHINodesToUpdate[pi].first;
> +    for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
> +      MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
>       MachineBasicBlock *PHIBB = PHI->getParent();
>       assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
>              "This is not a machine PHI node that we are updating!");
>       // This is "default" BB. We have two jumps to it. From "header" BB and
>       // from last "case" BB.
> -      if (PHIBB == BitTestCases[i].Default) {
> -        PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
> +      if (PHIBB == SDL->BitTestCases[i].Default) {
> +        PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
>                                                   false));
> -        PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
> -        PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
> +        PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent));
> +        PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
>                                                   false));
> -        PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
> +        PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases.
>                                                   back().ThisBB));
>       }
>       // One of "cases" BB.
> -      for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
> -        MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
> +      for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size();
> +           j != ej; ++j) {
> +        MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB;
>         if (cBB->succ_end() !=
>             std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
> -          PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
> +          PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
>                                                     false));
>           PHI->addOperand(MachineOperand::CreateMBB(cBB));
>         }
>       }
>     }
>   }
> +  SDL->BitTestCases.clear();
>
>   // If the JumpTable record is filled in, then we need to emit a jump table.
>   // Updating the PHI nodes is tricky in this case, since we need to determine
>   // whether the PHI is a successor of the range check MBB or the jump table MBB
> -  for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
> +  for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) {
>     // Lower header first, if it wasn't already lowered
> -    if (!JTCases[i].first.Emitted) {
> -      SelectionDAGLowering HSDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
> +    if (!SDL->JTCases[i].first.Emitted) {
>       // Set the current basic block to the mbb we wish to insert the code into
> -      BB = JTCases[i].first.HeaderBB;
> -      HSDL.setCurrentBasicBlock(BB);
> +      BB = SDL->JTCases[i].first.HeaderBB;
> +      SDL->setCurrentBasicBlock(BB);
>       // Emit the code
> -      HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
> -      CurDAG->setRoot(HSDL.getRoot());
> +      SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first);
> +      CurDAG->setRoot(SDL->getRoot());
>       CodeGenAndEmitDAG();
> -      CurDAG->reset();
> +      SDL->clear();
>     }
>
> -    SelectionDAGLowering JSDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
>     // Set the current basic block to the mbb we wish to insert the code into
> -    BB = JTCases[i].second.MBB;
> -    JSDL.setCurrentBasicBlock(BB);
> +    BB = SDL->JTCases[i].second.MBB;
> +    SDL->setCurrentBasicBlock(BB);
>     // Emit the code
> -    JSDL.visitJumpTable(JTCases[i].second);
> -    CurDAG->setRoot(JSDL.getRoot());
> +    SDL->visitJumpTable(SDL->JTCases[i].second);
> +    CurDAG->setRoot(SDL->getRoot());
>     CodeGenAndEmitDAG();
> -    CurDAG->reset();
> +    SDL->clear();
>
>     // Update PHI Nodes
> -    for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
> -      MachineInstr *PHI = PHINodesToUpdate[pi].first;
> +    for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
> +      MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
>       MachineBasicBlock *PHIBB = PHI->getParent();
>       assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
>              "This is not a machine PHI node that we are updating!");
>       // "default" BB. We can go there only from header BB.
> -      if (PHIBB == JTCases[i].second.Default) {
> -        PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
> +      if (PHIBB == SDL->JTCases[i].second.Default) {
> +        PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
>                                                   false));
> -        PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
> +        PHI->addOperand(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB));
>       }
>       // JT BB. Just iterate over successors here
>       if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
> -        PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
> +        PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
>                                                   false));
>         PHI->addOperand(MachineOperand::CreateMBB(BB));
>       }
>     }
>   }
> +  SDL->JTCases.clear();
>
>   // If the switch block involved a branch to one of the actual successors, we
>   // need to update PHI nodes in that block.
> -  for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
> -    MachineInstr *PHI = PHINodesToUpdate[i].first;
> +  for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
> +    MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
>     assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
>            "This is not a machine PHI node that we are updating!");
>     if (BB->isSuccessor(PHI->getParent())) {
> -      PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
> +      PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
>                                                 false));
>       PHI->addOperand(MachineOperand::CreateMBB(BB));
>     }
> @@ -5689,48 +5796,50 @@
>
>   // If we generated any switch lowering information, build and codegen any
>   // additional DAGs necessary.
> -  for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
> -    SelectionDAGLowering SDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
> -
> +  for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) {
>     // Set the current basic block to the mbb we wish to insert the code into
> -    BB = SwitchCases[i].ThisBB;
> -    SDL.setCurrentBasicBlock(BB);
> +    BB = SDL->SwitchCases[i].ThisBB;
> +    SDL->setCurrentBasicBlock(BB);
>
>     // Emit the code
> -    SDL.visitSwitchCase(SwitchCases[i]);
> -    CurDAG->setRoot(SDL.getRoot());
> +    SDL->visitSwitchCase(SDL->SwitchCases[i]);
> +    CurDAG->setRoot(SDL->getRoot());
>     CodeGenAndEmitDAG();
> -    CurDAG->reset();
> +    SDL->clear();
>
>     // Handle any PHI nodes in successors of this chunk, as if we were coming
>     // from the original BB before switch expansion.  Note that PHI nodes can
>     // occur multiple times in PHINodesToUpdate.  We have to be very careful to
>     // handle them the right number of times.
> -    while ((BB = SwitchCases[i].TrueBB)) {  // Handle LHS and RHS.
> +    while ((BB = SDL->SwitchCases[i].TrueBB)) {  // Handle LHS and RHS.
>       for (MachineBasicBlock::iterator Phi = BB->begin();
>            Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
>         // This value for this PHI node is recorded in PHINodesToUpdate, get it.
>         for (unsigned pn = 0; ; ++pn) {
> -          assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
> -          if (PHINodesToUpdate[pn].first == Phi) {
> -            Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
> +          assert(pn != SDL->PHINodesToUpdate.size() &&
> +                 "Didn't find PHI entry!");
> +          if (SDL->PHINodesToUpdate[pn].first == Phi) {
> +            Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn].
>                                                       second, false));
> -            Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
> +            Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB));
>             break;
>           }
>         }
>       }
>
>       // Don't process RHS if same block as LHS.
> -      if (BB == SwitchCases[i].FalseBB)
> -        SwitchCases[i].FalseBB = 0;
> +      if (BB == SDL->SwitchCases[i].FalseBB)
> +        SDL->SwitchCases[i].FalseBB = 0;
>
>       // If we haven't handled the RHS, do so now.  Otherwise, we're done.
> -      SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
> -      SwitchCases[i].FalseBB = 0;
> +      SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB;
> +      SDL->SwitchCases[i].FalseBB = 0;
>     }
> -    assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
> +    assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0);
>   }
> +  SDL->SwitchCases.clear();
> +
> +  SDL->PHINodesToUpdate.clear();
>  }
>
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From rafael.espindola at gmail.com  Thu Aug 28 13:32:53 2008
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Thu, 28 Aug 2008 18:32:53 -0000
Subject: [llvm-commits] [llvm] r55486 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <200808281832.m7SIWrQf001396@zion.cs.uiuc.edu>

Author: rafael
Date: Thu Aug 28 13:32:53 2008
New Revision: 55486

URL: http://llvm.org/viewvc/llvm-project?rev=55486&view=rev
Log:
Use resize instead of reserve. Reserve doesn't change size().

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=55486&r1=55485&r2=55486&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Aug 28 13:32:53 2008
@@ -3686,7 +3686,7 @@
   MVT MaskVT = PermMask.getValueType();
   MVT MaskEVT = MaskVT.getVectorElementType();
   SmallVector<std::pair<int, int>, 8> Locs;
-  Locs.reserve(4);
+  Locs.resize(4);
   SmallVector<SDValue, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT));
   unsigned NumHi = 0;
   unsigned NumLo = 0;




From isanbard at gmail.com  Thu Aug 28 13:37:32 2008
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 28 Aug 2008 18:37:32 -0000
Subject: [llvm-commits] [llvm] r55489 - /llvm/tags/Apple/llvmCore-2067/
Message-ID: <200808281837.m7SIbWq9001565@zion.cs.uiuc.edu>

Author: void
Date: Thu Aug 28 13:37:32 2008
New Revision: 55489

URL: http://llvm.org/viewvc/llvm-project?rev=55489&view=rev
Log:
Redoing tags

Removed:
    llvm/tags/Apple/llvmCore-2067/



From isanbard at gmail.com  Thu Aug 28 13:37:43 2008
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 28 Aug 2008 18:37:43 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r55490 -
	/llvm-gcc-4.2/tags/Apple/llvmgcc42-2067/
Message-ID: <200808281837.m7SIbiTG001582@zion.cs.uiuc.edu>

Author: void
Date: Thu Aug 28 13:37:43 2008
New Revision: 55490

URL: http://llvm.org/viewvc/llvm-project?rev=55490&view=rev
Log:
Redoing tags

Removed:
    llvm-gcc-4.2/tags/Apple/llvmgcc42-2067/



From isanbard at gmail.com  Thu Aug 28 13:38:58 2008
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 28 Aug 2008 18:38:58 -0000
Subject: [llvm-commits] [llvm] r55491 - /llvm/tags/Apple/llvmCore-2067/
Message-ID: <200808281838.m7SIcwC3001631@zion.cs.uiuc.edu>

Author: void
Date: Thu Aug 28 13:38:58 2008
New Revision: 55491

URL: http://llvm.org/viewvc/llvm-project?rev=55491&view=rev
Log:
Creating llvmCore-2067 branch

Added:
    llvm/tags/Apple/llvmCore-2067/
      - copied from r55490, llvm/trunk/



From isanbard at gmail.com  Thu Aug 28 13:39:05 2008
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 28 Aug 2008 18:39:05 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r55492 -
	/llvm-gcc-4.2/tags/Apple/llvmgcc42-2067/
Message-ID: <200808281839.m7SId5XP001649@zion.cs.uiuc.edu>

Author: void
Date: Thu Aug 28 13:39:04 2008
New Revision: 55492

URL: http://llvm.org/viewvc/llvm-project?rev=55492&view=rev
Log:
Creating llvmgcc42-2067 branch

Added:
    llvm-gcc-4.2/tags/Apple/llvmgcc42-2067/
      - copied from r55491, llvm-gcc-4.2/trunk/



From dalej at apple.com  Thu Aug 28 15:14:20 2008
From: dalej at apple.com (Dale Johannesen)
Date: Thu, 28 Aug 2008 13:14:20 -0700
Subject: [llvm-commits] [llvm] r55457 - in /llvm/trunk:
	include/llvm/CodeGen/SelectionDAGNodes.h	include/llvm/Target/TargetLowering.h
	lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	lib/CodeGen/SelectionDAG/SelectionDAG.cpp
	lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	lib/Target/TargetSelectionDAG.td
	lib/Target/X86/X86ISelLowering.cpp	lib/Target/X86/X86Instr64bit.td
	lib/Target/X86/X86InstrInfo.td
In-Reply-To: <3D1FD3C4-4F1D-423E-BBF1-3D184394890A@apple.com>
References: <200808280244.m7S2ioDI016151@zion.cs.uiuc.edu>
	<3D1FD3C4-4F1D-423E-BBF1-3D184394890A@apple.com>
Message-ID: <764F54DD-8DFF-40E2-821D-1308B8B3606E@apple.com>


On Aug 28, 2008, at 11:14 AMPDT, Dan Gohman wrote:
> On Aug 27, 2008, at 7:44 PM, Dale Johannesen wrote:
>
>> Author: johannes
>> Date: Wed Aug 27 21:44:49 2008
>> New Revision: 55457
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=55457&view=rev
>> Log:
>> Split the ATOMIC NodeType's to include the size, e.g.
>> ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
>> Increased the Hardcoded Constant OpActionsCapacity to match.
>> Large but boring; no functional change.
>>
>> This is to support partial-word atomics on ppc; i8 is
>> not a valid type there, so by the time we get to lowering, the
>> ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
>> The information can be added to the AtomicSDNode, but that is the
>> largest SDNode; I don't fully understand the SDNode allocation,
>> but it is sensitive to the largest node size, so increasing
>> that must be bad.  This is the alternative.
>
>
> Hi Dale,
>
> I'd like to see if we can find an alternative to this alternative :-).
> Here's one idea:
>
> MemSDNode has a MemoryVT member. This is used for truncating
> stores and extending loads to indicate the type of the actual
> memory access. We don't have extending or truncating atomics,
> so I believe it's redundant in AtomicSDNode.
>
> Perhaps MemoryVT could be moved out of MemSDNode and into
> LSBaseSDNode? That would allow a new MVT member to be added
> to AtomicSDNode without an overall size increase.

Maybe, but MemoryVT kind of belongs in the MemSDNode, doesn't it?




From gohman at apple.com  Thu Aug 28 15:28:56 2008
From: gohman at apple.com (Dan Gohman)
Date: Thu, 28 Aug 2008 20:28:56 -0000
Subject: [llvm-commits] [llvm] r55496 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAGISel.h
 lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200808282028.m7SKSuN3005672@zion.cs.uiuc.edu>

Author: djg
Date: Thu Aug 28 15:28:56 2008
New Revision: 55496

URL: http://llvm.org/viewvc/llvm-project?rev=55496&view=rev
Log:
Fix a FastISel bug where the instructions from lowering the arguments
were being emitted after the first instructions of the entry block.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=55496&r1=55495&r2=55496&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Thu Aug 28 15:28:56 2008
@@ -110,8 +110,7 @@
 
   void SelectBasicBlock(BasicBlock *LLVMBB,
                         BasicBlock::iterator Begin,
-                        BasicBlock::iterator End,
-                        bool DoArgs);
+                        BasicBlock::iterator End);
   void CodeGenAndEmitDAG();
   void LowerArguments(BasicBlock *BB);
   

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=55496&r1=55495&r2=55496&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Aug 28 15:28:56 2008
@@ -5479,12 +5479,7 @@
 
 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
                                         BasicBlock::iterator Begin,
-                                        BasicBlock::iterator End,
-                                        bool DoArgs) {
-  // Lower any arguments needed in this block if this is the entry block.
-  if (DoArgs)
-    LowerArguments(LLVMBB);
-
+                                        BasicBlock::iterator End) {
   SDL->setCurrentBasicBlock(BB);
 
   MachineModuleInfo *MMI = CurDAG->getMachineModuleInfo();
@@ -5744,12 +5739,23 @@
 
     BasicBlock::iterator Begin = LLVMBB->begin();
     BasicBlock::iterator End = LLVMBB->end();
-    bool DoArgs = LLVMBB == &Fn.getEntryBlock();
+
+    // Lower any arguments needed in this block if this is the entry block.
+    if (LLVMBB == &Fn.getEntryBlock())
+      LowerArguments(LLVMBB);
 
     // Before doing SelectionDAG ISel, see if FastISel has been requested.
     // FastISel doesn't support EH landing pads, which require special handling.
     if (EnableFastISel && !BB->isLandingPad()) {
       if (FastISel *F = TLI.createFastISel(*FuncInfo->MF)) {
+        // Emit code for any incoming arguments. This must happen before
+        // beginning FastISel on the entry block.
+        if (LLVMBB == &Fn.getEntryBlock()) {
+          CurDAG->setRoot(SDL->getControlRoot());
+          CodeGenAndEmitDAG();
+          SDL->clear();
+        }
+        // Do FastISel on as many instructions as possible.
         while (Begin != End) {
           Begin = F->SelectInstructions(Begin, End, FuncInfo->ValueMap,
                                         FuncInfo->MBBMap, BB);
@@ -5767,10 +5773,8 @@
                 R = FuncInfo->CreateRegForValue(Begin);
             }
 
-            SelectBasicBlock(LLVMBB, Begin, next(Begin), DoArgs);
-
+            SelectBasicBlock(LLVMBB, Begin, next(Begin));
             ++Begin;
-            DoArgs = false;
             continue;
           }
 
@@ -5792,8 +5796,8 @@
       }
     }
 
-    if (Begin != End || DoArgs)
-      SelectBasicBlock(LLVMBB, Begin, End, DoArgs);
+    if (Begin != End)
+      SelectBasicBlock(LLVMBB, Begin, End);
 
     FinishBasicBlock();
   }




From gohman at apple.com  Thu Aug 28 15:38:18 2008
From: gohman at apple.com (Dan Gohman)
Date: Thu, 28 Aug 2008 20:38:18 -0000
Subject: [llvm-commits] [llvm] r55497 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200808282038.m7SKcIHR006014@zion.cs.uiuc.edu>

Author: djg
Date: Thu Aug 28 15:38:18 2008
New Revision: 55497

URL: http://llvm.org/viewvc/llvm-project?rev=55497&view=rev
Log:
Move CaseBlock, JumpTable, and BitTestBlock to be members of
SelectionDAGLowering instead of being in an anonymous namespace.
This fixes warnings about SelectionDAGLowering having fields
using anonymous namespaces.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=55497&r1=55496&r2=55497&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Aug 28 15:38:18 2008
@@ -523,84 +523,6 @@
   return FirstReg;
 }
 
-namespace {
-
-/// CaseBlock - This structure is used to communicate between SDLowering and
-/// SDISel for the code generation of additional basic blocks needed by multi-
-/// case switch statements.
-struct CaseBlock {
-  CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
-            MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
-            MachineBasicBlock *me)
-    : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
-      TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
-  // CC - the condition code to use for the case block's setcc node
-  ISD::CondCode CC;
-  // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
-  // Emit by default LHS op RHS. MHS is used for range comparisons:
-  // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
-  Value *CmpLHS, *CmpMHS, *CmpRHS;
-  // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
-  MachineBasicBlock *TrueBB, *FalseBB;
-  // ThisBB - the block into which to emit the code for the setcc and branches
-  MachineBasicBlock *ThisBB;
-};
-struct JumpTable {
-  JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
-            MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
-  
-  /// Reg - the virtual register containing the index of the jump table entry
-  //. to jump to.
-  unsigned Reg;
-  /// JTI - the JumpTableIndex for this jump table in the function.
-  unsigned JTI;
-  /// MBB - the MBB into which to emit the code for the indirect jump.
-  MachineBasicBlock *MBB;
-  /// Default - the MBB of the default bb, which is a successor of the range
-  /// check MBB.  This is when updating PHI nodes in successors.
-  MachineBasicBlock *Default;
-};
-struct JumpTableHeader {
-  JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
-                  bool E = false):
-    First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
-  uint64_t First;
-  uint64_t Last;
-  Value *SValue;
-  MachineBasicBlock *HeaderBB;
-  bool Emitted;
-};
-typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
-
-struct BitTestCase {
-  BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
-    Mask(M), ThisBB(T), TargetBB(Tr) { }
-  uint64_t Mask;
-  MachineBasicBlock* ThisBB;
-  MachineBasicBlock* TargetBB;
-};
-
-typedef SmallVector<BitTestCase, 3> BitTestInfo;
-
-struct BitTestBlock {
-  BitTestBlock(uint64_t F, uint64_t R, Value* SV,
-               unsigned Rg, bool E,
-               MachineBasicBlock* P, MachineBasicBlock* D,
-               const BitTestInfo& C):
-    First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
-    Parent(P), Default(D), Cases(C) { }
-  uint64_t First;
-  uint64_t Range;
-  Value  *SValue;
-  unsigned Reg;
-  bool Emitted;
-  MachineBasicBlock *Parent;
-  MachineBasicBlock *Default;
-  BitTestInfo Cases;
-};
-
-} // end anonymous namespace
-
 //===----------------------------------------------------------------------===//
 /// SelectionDAGLowering - This is the common target-independent lowering
 /// implementation that is parameterized by a TargetLowering object.
@@ -694,6 +616,80 @@
 
   unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
   
+  /// CaseBlock - This structure is used to communicate between SDLowering and
+  /// SDISel for the code generation of additional basic blocks needed by multi-
+  /// case switch statements.
+  struct CaseBlock {
+    CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
+              MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
+              MachineBasicBlock *me)
+      : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
+        TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
+    // CC - the condition code to use for the case block's setcc node
+    ISD::CondCode CC;
+    // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
+    // Emit by default LHS op RHS. MHS is used for range comparisons:
+    // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
+    Value *CmpLHS, *CmpMHS, *CmpRHS;
+    // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
+    MachineBasicBlock *TrueBB, *FalseBB;
+    // ThisBB - the block into which to emit the code for the setcc and branches
+    MachineBasicBlock *ThisBB;
+  };
+  struct JumpTable {
+    JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
+              MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
+  
+    /// Reg - the virtual register containing the index of the jump table entry
+    //. to jump to.
+    unsigned Reg;
+    /// JTI - the JumpTableIndex for this jump table in the function.
+    unsigned JTI;
+    /// MBB - the MBB into which to emit the code for the indirect jump.
+    MachineBasicBlock *MBB;
+    /// Default - the MBB of the default bb, which is a successor of the range
+    /// check MBB.  This is when updating PHI nodes in successors.
+    MachineBasicBlock *Default;
+  };
+  struct JumpTableHeader {
+    JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
+                    bool E = false):
+      First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
+    uint64_t First;
+    uint64_t Last;
+    Value *SValue;
+    MachineBasicBlock *HeaderBB;
+    bool Emitted;
+  };
+  typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
+
+  struct BitTestCase {
+    BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
+      Mask(M), ThisBB(T), TargetBB(Tr) { }
+    uint64_t Mask;
+    MachineBasicBlock* ThisBB;
+    MachineBasicBlock* TargetBB;
+  };
+
+  typedef SmallVector<BitTestCase, 3> BitTestInfo;
+
+  struct BitTestBlock {
+    BitTestBlock(uint64_t F, uint64_t R, Value* SV,
+                 unsigned Rg, bool E,
+                 MachineBasicBlock* P, MachineBasicBlock* D,
+                 const BitTestInfo& C):
+      First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
+      Parent(P), Default(D), Cases(C) { }
+    uint64_t First;
+    uint64_t Range;
+    Value  *SValue;
+    unsigned Reg;
+    bool Emitted;
+    MachineBasicBlock *Parent;
+    MachineBasicBlock *Default;
+    BitTestInfo Cases;
+  };
+
 public:
   // TLI - This is information that describes the available target features we
   // need for lowering.  This indicates when operations are unavailable,
@@ -839,6 +835,7 @@
   void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
                             MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
                             unsigned Opc);
+  bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
   bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
   void ExportFromCurrentBlock(Value *V);
   void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall,
@@ -1618,8 +1615,8 @@
 /// If the set of cases should be emitted as a series of branches, return true.
 /// If we should emit this as a bunch of and/or'd together conditions, return
 /// false.
-static bool 
-ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
+bool 
+SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
   if (Cases.size() != 2) return true;
   
   // If this is two comparisons of the same values or'd or and'd together, they




From gohman at apple.com  Thu Aug 28 16:01:56 2008
From: gohman at apple.com (Dan Gohman)
Date: Thu, 28 Aug 2008 21:01:56 -0000
Subject: [llvm-commits] [llvm] r55498 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 test/CodeGen/X86/alloca-align-rounding.ll
Message-ID: <200808282101.m7SL1uLN006828@zion.cs.uiuc.edu>

Author: djg
Date: Thu Aug 28 16:01:56 2008
New Revision: 55498

URL: http://llvm.org/viewvc/llvm-project?rev=55498&view=rev
Log:
Optimize DAGCombiner's worklist processing. Previously it started
its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.

This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/alloca-align-rounding.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=55498&r1=55497&r2=55498&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Aug 28 16:01:56 2008
@@ -53,12 +53,31 @@
     bool AfterLegalize;
     bool Fast;
 
+    // Create a dummy node (which is not added to allnodes), that adds a reference
+    // to the root node, preventing it from being deleted, and tracking any
+    // changes of the root.
+    HandleSDNode Dummy;
+  
     // Worklist of all of the nodes that need to be simplified.
-    std::vector<SDNode*> WorkList;
+    SmallVector<SDNode*, 8> WorkList;
+
+    // The current position of our iteration through the allnodes list.
+    SelectionDAG::allnodes_iterator CurNode;
 
     // AA - Used for DAG load/store alias analysis.
     AliasAnalysis &AA;
 
+    /// AdvanceCurNode - Update CurNode to point to the next node to process.
+    ///
+    void AdvanceCurNode() {
+      // We start at the end of the list and work towards the front. Setting
+      // CurNode to DAG.allnodes_end() indicates that we're done.
+      if (CurNode == DAG.allnodes_begin())
+        CurNode = DAG.allnodes_end();
+      else
+        --CurNode;
+    }
+
     /// AddUsersToWorkList - When an instruction is simplified, add all users of
     /// the instruction to the work lists because they might get more simplified
     /// now.
@@ -86,6 +105,10 @@
     void removeFromWorkList(SDNode *N) {
       WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
                      WorkList.end());
+      // If the next node we were planning to process is deleted,
+      // skip past it.
+      if (N == CurNode)
+        AdvanceCurNode();
     }
     
     SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
@@ -243,10 +266,14 @@
         TLI(D.getTargetLoweringInfo()),
         AfterLegalize(false),
         Fast(fast),
+        Dummy(D.getRoot()),
         AA(A) {}
     
     /// Run - runs the dag combiner on all nodes in the work list
     void Run(bool RunningAfterLegalize); 
+
+    /// ProcessNode - runs the dag combiner on a node
+    void ProcessNode(SDNode *N);
   };
 }
 
@@ -575,91 +602,89 @@
 //  Main DAG Combiner implementation
 //===----------------------------------------------------------------------===//
 
+void DAGCombiner::ProcessNode(SDNode *N) {
+  // If N has no uses, it is dead.  Make sure to revisit all N's operands once
+  // N is deleted from the DAG, since they too may now be dead or may have a
+  // reduced number of uses, allowing other xforms.
+  if (N->use_empty() && N != &Dummy) {
+    for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
+      AddToWorkList(N->getOperand(i).Val);
+    
+    DAG.DeleteNode(N);
+    return;
+  }
+    
+  SDValue RV = combine(N);
+  
+  if (RV.Val == 0)
+    return;
+  
+  ++NodesCombined;
+  
+  // If we get back the same node we passed in, rather than a new node or
+  // zero, we know that the node must have defined multiple values and
+  // CombineTo was used.  Since CombineTo takes care of the worklist 
+  // mechanics for us, we have no work to do in this case.
+  if (RV.Val == N)
+    return;
+  
+  assert(N->getOpcode() != ISD::DELETED_NODE &&
+         RV.Val->getOpcode() != ISD::DELETED_NODE &&
+         "Node was deleted but visit returned new node!");
+
+  DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
+  DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
+  DOUT << '\n';
+
+  if (N->getNumValues() == RV.Val->getNumValues())
+    DAG.ReplaceAllUsesWith(N, RV.Val);
+  else {
+    assert(N->getValueType(0) == RV.getValueType() &&
+           N->getNumValues() == 1 && "Type mismatch");
+    SDValue OpV = RV;
+    DAG.ReplaceAllUsesWith(N, &OpV);
+  }
+
+  // Delete the old node.
+  removeFromWorkList(N);
+  DAG.DeleteNode(N);
+
+  // Push the new node and any users onto the worklist
+  AddToWorkList(RV.Val);
+  AddUsersToWorkList(RV.Val);
+}
+
 void DAGCombiner::Run(bool RunningAfterLegalize) {
   // set the instance variable, so that the various visit routines may use it.
   AfterLegalize = RunningAfterLegalize;
 
-  // Add all the dag nodes to the worklist.
-  WorkList.reserve(DAG.allnodes_size());
-  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
-       E = DAG.allnodes_end(); I != E; ++I)
-    WorkList.push_back(I);
-  
-  // Create a dummy node (which is not added to allnodes), that adds a reference
-  // to the root node, preventing it from being deleted, and tracking any
-  // changes of the root.
-  HandleSDNode Dummy(DAG.getRoot());
-  
   // The root of the dag may dangle to deleted nodes until the dag combiner is
   // done.  Set it to null to avoid confusion.
   DAG.setRoot(SDValue());
   
-  // while the worklist isn't empty, inspect the node on the end of it and
-  // try and combine it.
-  while (!WorkList.empty()) {
-    SDNode *N = WorkList.back();
-    WorkList.pop_back();
-    
-    // If N has no uses, it is dead.  Make sure to revisit all N's operands once
-    // N is deleted from the DAG, since they too may now be dead or may have a
-    // reduced number of uses, allowing other xforms.
-    if (N->use_empty() && N != &Dummy) {
-      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-        AddToWorkList(N->getOperand(i).Val);
-      
-      DAG.DeleteNode(N);
-      continue;
+  // Process all the original dag nodes. We process starting from the
+  // end of the list and working forward, which is in roughly topological
+  // order. Starting at the end and working forward means we won't
+  // accidentally revisit nodes created during the dagcombine process.
+  CurNode = prior(DAG.allnodes_end());
+  do {
+    SDNode *N = &*CurNode;
+    AdvanceCurNode();
+    ProcessNode(N);
+    // Processing the node may have resulted in nodes being added to the
+    // worklist, because the were newly created or because one of their 
+    // operands changed or some other reason they should be revisited.
+    // While the worklist isn't empty, inspect the node on the end of it
+    // and try and combine it.
+    while (!WorkList.empty()) {
+      SDNode *N = WorkList.back();
+      WorkList.pop_back();
+      if (N == CurNode)
+        AdvanceCurNode();
+      ProcessNode(N);
     }
-    
-    SDValue RV = combine(N);
-    
-    if (RV.Val == 0)
-      continue;
-    
-    ++NodesCombined;
-    
-    // If we get back the same node we passed in, rather than a new node or
-    // zero, we know that the node must have defined multiple values and
-    // CombineTo was used.  Since CombineTo takes care of the worklist 
-    // mechanics for us, we have no work to do in this case.
-    if (RV.Val == N)
-      continue;
-    
-    assert(N->getOpcode() != ISD::DELETED_NODE &&
-           RV.Val->getOpcode() != ISD::DELETED_NODE &&
-           "Node was deleted but visit returned new node!");
+  } while (CurNode != DAG.allnodes_end());
 
-    DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
-    DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
-    DOUT << '\n';
-    WorkListRemover DeadNodes(*this);
-    if (N->getNumValues() == RV.Val->getNumValues())
-      DAG.ReplaceAllUsesWith(N, RV.Val, &DeadNodes);
-    else {
-      assert(N->getValueType(0) == RV.getValueType() &&
-             N->getNumValues() == 1 && "Type mismatch");
-      SDValue OpV = RV;
-      DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
-    }
-      
-    // Push the new node and any users onto the worklist
-    AddToWorkList(RV.Val);
-    AddUsersToWorkList(RV.Val);
-    
-    // Add any uses of the old node to the worklist in case this node is the
-    // last one that uses them.  They may become dead after this node is
-    // deleted.
-    for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-      AddToWorkList(N->getOperand(i).Val);
-      
-    // Nodes can be reintroduced into the worklist.  Make sure we do not
-    // process a node that has been replaced.
-    removeFromWorkList(N);
-    
-    // Finally, since the node is now dead, remove it from the graph.
-    DAG.DeleteNode(N);
-  }
-  
   // If the root changed (e.g. it was a dead load, update the root).
   DAG.setRoot(Dummy.getValue());
 }

Modified: llvm/trunk/test/CodeGen/X86/alloca-align-rounding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/alloca-align-rounding.ll?rev=55498&r1=55497&r2=55498&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/alloca-align-rounding.ll (original)
+++ llvm/trunk/test/CodeGen/X86/alloca-align-rounding.ll Thu Aug 28 16:01:56 2008
@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-apple-darwin | grep and | count 1
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=i686-pc-linux | grep and | count 3
+; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=i686-pc-linux | grep and | count 1
 
 declare void @bar(<2 x i64>* %n)
 




From wangmp at apple.com  Thu Aug 28 16:04:05 2008
From: wangmp at apple.com (Mon P Wang)
Date: Thu, 28 Aug 2008 21:04:05 -0000
Subject: [llvm-commits] [llvm] r55499 - in /llvm/trunk:
 lib/Target/PowerPC/PPCISelLowering.cpp test/CodeGen/PowerPC/fnegsel.ll
Message-ID: <200808282104.m7SL45PP006904@zion.cs.uiuc.edu>

Author: wangmp
Date: Thu Aug 28 16:04:05 2008
New Revision: 55499

URL: http://llvm.org/viewvc/llvm-project?rev=55499&view=rev
Log:
In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/test/CodeGen/PowerPC/fnegsel.ll

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=55499&r1=55498&r2=55499&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Aug 28 16:04:05 2008
@@ -2734,20 +2734,16 @@
     switch (CC) {
     default: break;       // SETUO etc aren't handled by fsel.
     case ISD::SETULT:
-    case ISD::SETOLT:
     case ISD::SETLT:
       std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
-    case ISD::SETUGE:
     case ISD::SETOGE:
     case ISD::SETGE:
       if (LHS.getValueType() == MVT::f32)   // Comparison is always 64-bits
         LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
       return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
     case ISD::SETUGT:
-    case ISD::SETOGT:
     case ISD::SETGT:
       std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
-    case ISD::SETULE:
     case ISD::SETOLE:
     case ISD::SETLE:
       if (LHS.getValueType() == MVT::f32)   // Comparison is always 64-bits
@@ -2760,13 +2756,11 @@
   switch (CC) {
   default: break;       // SETUO etc aren't handled by fsel.
   case ISD::SETULT:
-  case ISD::SETOLT:
   case ISD::SETLT:
     Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
     if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
       Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
       return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
-  case ISD::SETUGE:
   case ISD::SETOGE:
   case ISD::SETGE:
     Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
@@ -2774,13 +2768,11 @@
       Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
       return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
   case ISD::SETUGT:
-  case ISD::SETOGT:
   case ISD::SETGT:
     Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
     if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
       Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
       return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
-  case ISD::SETULE:
   case ISD::SETOLE:
   case ISD::SETLE:
     Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);

Modified: llvm/trunk/test/CodeGen/PowerPC/fnegsel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fnegsel.ll?rev=55499&r1=55498&r2=55499&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/fnegsel.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/fnegsel.ll Thu Aug 28 16:04:05 2008
@@ -2,7 +2,7 @@
 
 define double @test_FNEG_sel(double %A, double %B, double %C) {
         %D = sub double -0.000000e+00, %A               ; <double> [#uses=1]
-        %Cond = fcmp ogt double %D, -0.000000e+00               ; <i1> [#uses=1]
+        %Cond = fcmp ugt double %D, -0.000000e+00               ; <i1> [#uses=1]
         %E = select i1 %Cond, double %B, double %C              ; <double> [#uses=1]
         ret double %E
 }




From ggreif at gmail.com  Thu Aug 28 16:10:35 2008
From: ggreif at gmail.com (Gabor Greif)
Date: Thu, 28 Aug 2008 14:10:35 -0700 (PDT)
Subject: [llvm-commits] [PATCH] SDValue (was: SDNode) refactoring
In-Reply-To: <C92C08C5-A959-47BB-B103-1AA97B8FC552@apple.com>
References: <F7CCF048-F36D-4A97-BA7A-D44348F57D32@mac.com> 
	<C92C08C5-A959-47BB-B103-1AA97B8FC552@apple.com>
Message-ID: <7207b287-883d-4fdb-b0ac-c60bf0548982@i76g2000hsf.googlegroups.com>

On Aug 28, 7:53?pm, Dan Gohman <goh... at apple.com> wrote:
> Hi Gabor,
>
> Overall this looks good to me. Comments below.

Great! Thanks for looking into this!

>
> On Aug 27, 2008, at 3:20 PM, Gabor Greif wrote:
>
>
>
> > <SDNode-refactor4-55428.diff>
>
> > Hi all,
>
> > here comes a big patch that cleans up the vocabulary and
> > abstraction boundaries of SDNode usage.
>
> > It starts at the headers, passes thru TableGen and modifies many
> > .cpp files.
>
> > To the most part it is just tedious text replacement. But there
> > are some details that are worth noting.
>
> > Here are the highlights:
>
> > 1) SDUse::getVal used to return SDNode*& which is actually
> > used in some contexts. This breaks abstraction.
> > Current solution, make SDUse::getVal return SDNode*
> > and satisfy those clients, who actually want to mutate the SDNode*
> > with a new interface SDUse::getSDValue() which returns SDValue&.
>
> > Analogously, provide SDValue::setNode to set SDValue::Val.
> > This accompanies the new SDValue::getVal(), which is a pure getter.
>
> Looks good to me.
>
>
>
> > 2) get rid of the anachronistic names in SDValue
> > Val -> Node
>
> Yay!
>
>
>
> > getNode (new)
> > setNode (new)
>
> > Please note that there is still some confusion in SDUse (getVal)
> > but I revisit that in a next patch.
>
> Ok.
>
>
>
> > 3) This patch does not (intentionally) change the semantics.
> > All deja tests still pass.
>
> Even though this patch doesn't change any functionality, it's a
> big diff, so it would be good to run more tests than just dejagnu.
>

I have just ran SingleSource, looked good. At the moment I am into
MultiSource.
I'll check in if all is right.

>
>
> > 4) I expect some 80-col violations. These are best taken care in
> > a patch directly after checking in.
>
> Ok.
>
>
>
>
>
> > And finally here is the most important changes. I excerpt
> > them here, with inline comments.
>
> >> Index: include/llvm/CodeGen/SelectionDAGNodes.h
> >> ===================================================================
> >> --- include/llvm/CodeGen/SelectionDAGNodes.h ? ?(Revision 55428)
> >> +++ include/llvm/CodeGen/SelectionDAGNodes.h ? ?(Arbeitskopie)
> >> @@ -809,29 +809,33 @@
> >> /// of information is represented with the SDValue value type.
> >> ///
> >> class SDValue {
> >> -public:
> >> - ?SDNode *Val; ? ? ? ?// The node defining the value we are using.
> >> -private:
> >> + ?SDNode *Node; ? ? ? // The node defining the value we are using.
>
> > "Val" is named "Node" now and it becomes private.
>
> >> ? unsigned ResNo; ? ? // Which return value of the node we are using.
> >> public:
> >> - ?SDValue() : Val(0), ResNo(0) {}
> >> - ?SDValue(SDNode *val, unsigned resno) : Val(val), ResNo(resno) {}
> >> + ?SDValue() : Node(0), ResNo(0) {}
> >> + ?SDValue(SDNode *node, unsigned resno) : Node(node), ResNo(resno) ?
> >> {}
>
> >> ? /// get the index which selects a specific result in the SDNode
> >> ? unsigned getResNo() const { return ResNo; }
>
> >> + ?/// get the SDNode which holds the desired result
> >> + ?SDNode *getNode() const { return Node; }
> >> +
> >> + ?/// set the SDNode
> >> + ?void setNode(SDNode *N) { Node = N; }
> >> +
>
> > These are the new accessors.
>
> >> ? bool operator==(const SDValue &O) const {
> >> - ? ?return Val == O.Val && ResNo == O.ResNo;
> >> + ? ?return Node == O.Node && ResNo == O.ResNo;
> >> ? }
> >> ? bool operator!=(const SDValue &O) const {
> >> ? ? return !operator==(O);
> >> ? }
> >> ? bool operator<(const SDValue &O) const {
> >> - ? ?return Val < O.Val || (Val == O.Val && ResNo < O.ResNo);
> >> + ? ?return Node < O.Node || (Node == O.Node && ResNo < O.ResNo);
> >> ? }
>
> >> ? SDValue getValue(unsigned R) const {
> >> - ? ?return SDValue(Val, R);
> >> + ? ?return SDValue(Node, R);
> >> ? }
>
> >> ? // isOperandOf - Return true if this node is an operand of N.
> >> @@ -866,12 +870,12 @@
> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned Depth = 2) const;
>
> >> ? /// use_empty - Return true if there are no nodes using value ResNo
> >> - ?/// of node Val.
> >> + ?/// of Node.
> >> ? ///
> >> ? inline bool use_empty() const;
>
> >> ? /// hasOneUse - Return true if there is exactly one node using ?
> >> value
> >> - ?/// ResNo of node Val.
> >> + ?/// ResNo of Node.
> >> ? ///
> >> ? inline bool hasOneUse() const;
> >> };
> >> @@ -885,8 +889,8 @@
> >> ? ? return SDValue((SDNode*)-1, 0);
> >> ? }
> >> ? static unsigned getHashValue(const SDValue &Val) {
> >> - ? ?return ((unsigned)((uintptr_t)Val.Val >> 4) ^
> >> - ? ? ? ? ? ?(unsigned)((uintptr_t)Val.Val >> 9)) + Val.getResNo();
> >> + ? ?return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
> >> + ? ? ? ? ? ?(unsigned)((uintptr_t)Val.getNode() >> 9)) + ?
> >> Val.getResNo();
> >> ? }
> >> ? static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
> >> ? ? return LHS == RHS;
> >> @@ -899,13 +903,13 @@
> >> template<> struct simplify_type<SDValue> {
> >> ? typedef SDNode* SimpleType;
> >> ? static SimpleType getSimplifiedValue(const SDValue &Val) {
> >> - ? ?return static_cast<SimpleType>(Val.Val);
> >> + ? ?return static_cast<SimpleType>(Val.getNode());
> >> ? }
> >> };
> >> template<> struct simplify_type<const SDValue> {
> >> ? typedef SDNode* SimpleType;
> >> ? static SimpleType getSimplifiedValue(const SDValue &Val) {
> >> - ? ?return static_cast<SimpleType>(Val.Val);
> >> + ? ?return static_cast<SimpleType>(Val.getNode());
> >> ? }
> >> };
>
> >> @@ -949,8 +953,9 @@
>
> >> ? const SDValue& getSDValue() const { return Operand; }
>
> >> - ?SDNode *&getVal() { return Operand.Val; }
> >> - ?SDNode *const &getVal() const { return Operand.Val; }
> >> + ?SDValue &getSDValue() { return Operand; }
>
> > This getter is new. Used by type legalizer, to update
> > node inside of SDValue.
>
> >> + ?SDNode *getVal() { return Operand.getNode(); }
>
> > This is a regular getter now. No reference backdoor.
>
> >> + ?SDNode *getVal() const { return Operand.getNode(); } // FIXME: ?
> >> const correct?
>
> > Ditto. I'll take care of the constness issue in an upcoming patch.
>
> What is the constness issue? Do you intend for SDUse's getVal() const to
> return a const SDNode* ? I don't think that's needed. I think the
> current const overload is there to protect the reference to the pointer,
> which this patch eliminates anyway.

The constness should extend to the parts of an object. I shall
investigate and if there are hurdles I won't pursue it.
Anyway, different issue.

>
> As you say, it would be good to get Duncan's input on the LegalizeTypes
> changes.

I have slept over it and do not think that there is any
problem that I have newly introduced. The parts that make
me doubtful already existed before my patch.
I shall consult Duncan when he arrives from vacation.

Thanks again,

    Gabor

>
> Thanks,
>
> Dan
>
> _______________________________________________
> llvm-commits mailing list
> llvm-comm... at cs.uiuc.eduhttp://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From gohman at apple.com  Thu Aug 28 16:19:08 2008
From: gohman at apple.com (Dan Gohman)
Date: Thu, 28 Aug 2008 21:19:08 -0000
Subject: [llvm-commits] [llvm] r55500 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200808282119.m7SLJ8Xe007370@zion.cs.uiuc.edu>

Author: djg
Date: Thu Aug 28 16:19:07 2008
New Revision: 55500

URL: http://llvm.org/viewvc/llvm-project?rev=55500&view=rev
Log:
Implement null and undef values for FastISel.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55500&r1=55499&r2=55500&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Aug 28 16:19:07 2008
@@ -31,6 +31,8 @@
     if (CI->getValue().getActiveBits() > 64)
       return 0;
     Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
+  } else if (isa<ConstantPointerNull>(V)) {
+    Reg = FastEmit_i(VT, VT, ISD::Constant, 0);
   } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
     Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
 
@@ -53,6 +55,9 @@
       if (Reg == 0)
         return 0;
     }
+  } else if (isa<UndefValue>(V)) {
+    Reg = createResultReg(TLI.getRegClassFor(VT));
+    BuildMI(MBB, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
   }
 
   return Reg;




From kremenek at apple.com  Thu Aug 28 16:29:04 2008
From: kremenek at apple.com (Ted Kremenek)
Date: Thu, 28 Aug 2008 21:29:04 -0000
Subject: [llvm-commits] [llvm] r55502 - /llvm/tags/checker/checker-85/
Message-ID: <200808282129.m7SLT4GW007945@zion.cs.uiuc.edu>

Author: kremenek
Date: Thu Aug 28 16:29:04 2008
New Revision: 55502

URL: http://llvm.org/viewvc/llvm-project?rev=55502&view=rev
Log:
Tagging checker-85.

Added:
    llvm/tags/checker/checker-85/
      - copied from r55501, llvm/trunk/



From ggreif at gmail.com  Thu Aug 28 16:40:38 2008
From: ggreif at gmail.com (Gabor Greif)
Date: Thu, 28 Aug 2008 21:40:38 -0000
Subject: [llvm-commits] [llvm] r55504 - in /llvm/trunk:
 include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/
 lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/
 lib/Target/Mips/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/
 lib/Target/X86/ utils/TableGen/
Message-ID: <200808282140.m7SLeelK008466@zion.cs.uiuc.edu>

Author: ggreif
Date: Thu Aug 28 16:40:38 2008
New Revision: 55504

URL: http://llvm.org/viewvc/llvm-project?rev=55504&view=rev
Log:
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics

Modified:
    llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
    llvm/trunk/include/llvm/Target/TargetLowering.h
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
    llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
    llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
    llvm/trunk/lib/Target/CellSPU/SPUOperands.td
    llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
    llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/utils/TableGen/DAGISelEmitter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h (original)
+++ llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h Thu Aug 28 16:40:38 2008
@@ -37,7 +37,7 @@
   else if (Chain->getNumOperands() > 0) {
     SDValue C0 = Chain->getOperand(0);
     if (C0.getValueType() == MVT::Other)
-      return C0.Val != Op && IsChainCompatible(C0.Val, Op);
+      return C0.getNode() != Op && IsChainCompatible(C0.getNode(), Op);
   }
   return true;
 }
@@ -76,9 +76,9 @@
 /// AddToISelQueue - adds a node to the instruction 
 /// selection queue.
 void AddToISelQueue(SDValue N) DISABLE_INLINE {
-  int Id = N.Val->getNodeId();
+  int Id = N.getNode()->getNodeId();
   if (Id != -1 && !isQueued(Id)) {
-    ISelQueue.push_back(N.Val);
+    ISelQueue.push_back(N.getNode());
     std::push_heap(ISelQueue.begin(), ISelQueue.end(), isel_sort());
     setQueued(Id);
   }
@@ -120,7 +120,7 @@
 void ReplaceUses(SDValue F, SDValue T) DISABLE_INLINE {
   ISelQueueUpdater ISQU(ISelQueue);
   CurDAG->ReplaceAllUsesOfValueWith(F, T, &ISQU);
-  setSelected(F.Val->getNodeId());
+  setSelected(F.getNode()->getNodeId());
   UpdateQueue(ISQU);
 }
 
@@ -131,7 +131,7 @@
   ISelQueueUpdater ISQU(ISelQueue);
   CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num, &ISQU);
   for (unsigned i = 0; i != Num; ++i)
-    setSelected(F[i].Val->getNodeId());
+    setSelected(F[i].getNode()->getNodeId());
   UpdateQueue(ISQU);
 }
 
@@ -165,7 +165,7 @@
   // a reference to the root node, preventing it from being deleted,
   // and tracking any changes of the root.
   HandleSDNode Dummy(CurDAG->getRoot());
-  ISelQueue.push_back(CurDAG->getRoot().Val);
+  ISelQueue.push_back(CurDAG->getRoot().getNode());
 
   // Select pending nodes from the instruction selection queue
   // until no more nodes are left for selection.

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Thu Aug 28 16:40:38 2008
@@ -170,7 +170,7 @@
   /// setRoot - Set the current root tag of the SelectionDAG.
   ///
   const SDValue &setRoot(SDValue N) {
-    assert((!N.Val || N.getValueType() == MVT::Other) &&
+    assert((!N.getNode() || N.getValueType() == MVT::Other) &&
            "DAG root value is not a chain!");
     return Root = N;
   }
@@ -295,7 +295,7 @@
                          SDValue Flag) {
     const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
     SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag };
-    return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.Val ? 4 : 3);
+    return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.getNode() ? 4 : 3);
   }
 
   // Similar to last getCopyToReg() except parameter Reg is a SDValue
@@ -303,7 +303,7 @@
                          SDValue Flag) {
     const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
     SDValue Ops[] = { Chain, Reg, N, Flag };
-    return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.Val ? 4 : 3);
+    return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.getNode() ? 4 : 3);
   }
   
   SDValue getCopyFromReg(SDValue Chain, unsigned Reg, MVT VT) {
@@ -319,7 +319,7 @@
                            SDValue Flag) {
     const MVT *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag);
     SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag };
-    return getNode(ISD::CopyFromReg, VTs, 3, Ops, Flag.Val ? 3 : 2);
+    return getNode(ISD::CopyFromReg, VTs, 3, Ops, Flag.getNode() ? 3 : 2);
   }
 
   SDValue getCondCode(ISD::CondCode Cond);
@@ -347,7 +347,7 @@
     Ops.push_back(Op2);
     Ops.push_back(InFlag);
     return getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0],
-                   (unsigned)Ops.size() - (InFlag.Val == 0 ? 1 : 0));
+                   (unsigned)Ops.size() - (InFlag.getNode() == 0 ? 1 : 0));
   }
 
   /// getNode - Gets or creates the specified node.

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Aug 28 16:40:38 2008
@@ -837,29 +837,33 @@
 /// of information is represented with the SDValue value type.
 ///
 class SDValue {
-public:
-  SDNode *Val;        // The node defining the value we are using.
-private:
+  SDNode *Node;       // The node defining the value we are using.
   unsigned ResNo;     // Which return value of the node we are using.
 public:
-  SDValue() : Val(0), ResNo(0) {}
-  SDValue(SDNode *val, unsigned resno) : Val(val), ResNo(resno) {}
+  SDValue() : Node(0), ResNo(0) {}
+  SDValue(SDNode *node, unsigned resno) : Node(node), ResNo(resno) {}
 
   /// get the index which selects a specific result in the SDNode
   unsigned getResNo() const { return ResNo; }
 
+  /// get the SDNode which holds the desired result
+  SDNode *getNode() const { return Node; }
+
+  /// set the SDNode
+  void setNode(SDNode *N) { Node = N; }
+
   bool operator==(const SDValue &O) const {
-    return Val == O.Val && ResNo == O.ResNo;
+    return Node == O.Node && ResNo == O.ResNo;
   }
   bool operator!=(const SDValue &O) const {
     return !operator==(O);
   }
   bool operator<(const SDValue &O) const {
-    return Val < O.Val || (Val == O.Val && ResNo < O.ResNo);
+    return Node < O.Node || (Node == O.Node && ResNo < O.ResNo);
   }
 
   SDValue getValue(unsigned R) const {
-    return SDValue(Val, R);
+    return SDValue(Node, R);
   }
 
   // isOperandOf - Return true if this node is an operand of N.
@@ -894,12 +898,12 @@
                                       unsigned Depth = 2) const;
   
   /// use_empty - Return true if there are no nodes using value ResNo
-  /// of node Val.
+  /// of Node.
   ///
   inline bool use_empty() const;
 
   /// hasOneUse - Return true if there is exactly one node using value
-  /// ResNo of node Val.
+  /// ResNo of Node.
   ///
   inline bool hasOneUse() const;
 };
@@ -913,8 +917,8 @@
     return SDValue((SDNode*)-1, 0);
   }
   static unsigned getHashValue(const SDValue &Val) {
-    return ((unsigned)((uintptr_t)Val.Val >> 4) ^
-            (unsigned)((uintptr_t)Val.Val >> 9)) + Val.getResNo();
+    return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
+            (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
   }
   static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
     return LHS == RHS;
@@ -927,13 +931,13 @@
 template<> struct simplify_type<SDValue> {
   typedef SDNode* SimpleType;
   static SimpleType getSimplifiedValue(const SDValue &Val) {
-    return static_cast<SimpleType>(Val.Val);
+    return static_cast<SimpleType>(Val.getNode());
   }
 };
 template<> struct simplify_type<const SDValue> {
   typedef SDNode* SimpleType;
   static SimpleType getSimplifiedValue(const SDValue &Val) {
-    return static_cast<SimpleType>(Val.Val);
+    return static_cast<SimpleType>(Val.getNode());
   }
 };
 
@@ -977,8 +981,9 @@
 
   const SDValue& getSDValue() const { return Operand; }
 
-  SDNode *&getVal() { return Operand.Val; }
-  SDNode *const &getVal() const { return Operand.Val; }
+  SDValue &getSDValue() { return Operand; }
+  SDNode *getVal() { return Operand.getNode(); }
+  SDNode *getVal() const { return Operand.getNode(); } // FIXME: const correct?
 
   bool operator==(const SDValue &O) const {
     return Operand == O;
@@ -1323,7 +1328,7 @@
     for (unsigned i = 0; i != NumOps; ++i) {
       OperandList[i] = Ops[i];
       OperandList[i].setUser(this);
-      Ops[i].Val->addUse(OperandList[i]);
+      Ops[i].getNode()->addUse(OperandList[i]);
     }
     
     ValueList = VTs.VTs;
@@ -1393,34 +1398,34 @@
 // Define inline functions from the SDValue class.
 
 inline unsigned SDValue::getOpcode() const {
-  return Val->getOpcode();
+  return Node->getOpcode();
 }
 inline MVT SDValue::getValueType() const {
-  return Val->getValueType(ResNo);
+  return Node->getValueType(ResNo);
 }
 inline unsigned SDValue::getNumOperands() const {
-  return Val->getNumOperands();
+  return Node->getNumOperands();
 }
 inline const SDValue &SDValue::getOperand(unsigned i) const {
-  return Val->getOperand(i);
+  return Node->getOperand(i);
 }
 inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
-  return Val->getConstantOperandVal(i);
+  return Node->getConstantOperandVal(i);
 }
 inline bool SDValue::isTargetOpcode() const {
-  return Val->isTargetOpcode();
+  return Node->isTargetOpcode();
 }
 inline bool SDValue::isMachineOpcode() const {
-  return Val->isMachineOpcode();
+  return Node->isMachineOpcode();
 }
 inline unsigned SDValue::getMachineOpcode() const {
-  return Val->getMachineOpcode();
+  return Node->getMachineOpcode();
 }
 inline bool SDValue::use_empty() const {
-  return !Val->hasAnyUseOfValue(ResNo);
+  return !Node->hasAnyUseOfValue(ResNo);
 }
 inline bool SDValue::hasOneUse() const {
-  return Val->hasNUsesOfValue(1, ResNo);
+  return Node->hasNUsesOfValue(1, ResNo);
 }
 
 /// UnarySDNode - This class is used for single-operand SDNodes.  This is solely
@@ -2321,7 +2326,7 @@
   }
 
   pointer operator*() const {
-    return Node->getOperand(Operand).Val;
+    return Node->getOperand(Operand).getNode();
   }
   pointer operator->() const { return operator*(); }
 

Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Thu Aug 28 16:40:38 2008
@@ -1086,11 +1086,11 @@
   static bool CheckTailCallReturnConstraints(SDValue Call, SDValue Ret) {
     unsigned NumOps = Ret.getNumOperands();
     if ((NumOps == 1 &&
-       (Ret.getOperand(0) == SDValue(Call.Val,1) ||
-        Ret.getOperand(0) == SDValue(Call.Val,0))) ||
+       (Ret.getOperand(0) == SDValue(Call.getNode(),1) ||
+        Ret.getOperand(0) == SDValue(Call.getNode(),0))) ||
       (NumOps > 1 &&
-       Ret.getOperand(0) == SDValue(Call.Val,Call.Val->getNumValues()-1) &&
-       Ret.getOperand(1) == SDValue(Call.Val,0)))
+       Ret.getOperand(0) == SDValue(Call.getNode(),Call.getNode()->getNumValues()-1) &&
+       Ret.getOperand(1) == SDValue(Call.getNode(),0)))
       return true;
     return false;
   }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Aug 28 16:40:38 2008
@@ -148,8 +148,8 @@
     // Visitation implementation - Implement dag node combining for different
     // node types.  The semantics are as follows:
     // Return Value:
-    //   SDValue.Val == 0   - No change was made
-    //   SDValue.Val == N   - N was replaced, is dead, and is already handled.
+    //   SDValue.getNode() == 0   - No change was made
+    //   SDValue.getNode() == N   - N was replaced, is dead, and is already handled.
     //   otherwise            - N should be replaced by the returned Operand.
     //
     SDValue visitTokenFactor(SDNode *N);
@@ -491,7 +491,7 @@
 // free when it is profitable to do so.
 static bool isOneUseSetCC(SDValue N) {
   SDValue N0, N1, N2;
-  if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
+  if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
     return true;
   return false;
 }
@@ -503,11 +503,11 @@
   if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
     if (isa<ConstantSDNode>(N1)) {
       SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
-      AddToWorkList(OpNode.Val);
+      AddToWorkList(OpNode.getNode());
       return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
     } else if (N0.hasOneUse()) {
       SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
-      AddToWorkList(OpNode.Val);
+      AddToWorkList(OpNode.getNode());
       return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
     }
   }
@@ -516,11 +516,11 @@
   if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
     if (isa<ConstantSDNode>(N0)) {
       SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
-      AddToWorkList(OpNode.Val);
+      AddToWorkList(OpNode.getNode());
       return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
     } else if (N1.hasOneUse()) {
       SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
-      AddToWorkList(OpNode.Val);
+      AddToWorkList(OpNode.getNode());
       return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
     }
   }
@@ -532,7 +532,7 @@
   assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
   ++NodesCombined;
   DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
-  DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
+  DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG));
   DOUT << " and " << NumTo-1 << " other values\n";
   WorkListRemover DeadNodes(*this);
   DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
@@ -540,8 +540,8 @@
   if (AddTo) {
     // Push the new nodes and any users onto the worklist
     for (unsigned i = 0, e = NumTo; i != e; ++i) {
-      AddToWorkList(To[i].Val);
-      AddUsersToWorkList(To[i].Val);
+      AddToWorkList(To[i].getNode());
+      AddUsersToWorkList(To[i].getNode());
     }
   }
   
@@ -564,12 +564,12 @@
     return false;
   
   // Revisit the node.
-  AddToWorkList(Op.Val);
+  AddToWorkList(Op.getNode());
   
   // Replace the old value with the new one.
   ++NodesCombined;
-  DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
-  DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
+  DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG));
+  DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
   DOUT << '\n';
   
   // Replace all uses.  If any nodes become isomorphic to other nodes and 
@@ -578,22 +578,22 @@
   DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
   
   // Push the new node and any (possibly new) users onto the worklist.
-  AddToWorkList(TLO.New.Val);
-  AddUsersToWorkList(TLO.New.Val);
+  AddToWorkList(TLO.New.getNode());
+  AddUsersToWorkList(TLO.New.getNode());
   
   // Finally, if the node is now dead, remove it from the graph.  The node
   // may not be dead if the replacement process recursively simplified to
   // something else needing this node.
-  if (TLO.Old.Val->use_empty()) {
-    removeFromWorkList(TLO.Old.Val);
+  if (TLO.Old.getNode()->use_empty()) {
+    removeFromWorkList(TLO.Old.getNode());
     
     // If the operands of this node are only used by the node, they will now
     // be dead.  Make sure to visit them first to delete dead nodes early.
-    for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i)
-      if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
-        AddToWorkList(TLO.Old.Val->getOperand(i).Val);
+    for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
+      if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
+        AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
     
-    DAG.DeleteNode(TLO.Old.Val);
+    DAG.DeleteNode(TLO.Old.getNode());
   }
   return true;
 }
@@ -608,7 +608,7 @@
   // reduced number of uses, allowing other xforms.
   if (N->use_empty() && N != &Dummy) {
     for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-      AddToWorkList(N->getOperand(i).Val);
+      AddToWorkList(N->getOperand(i).getNode());
     
     DAG.DeleteNode(N);
     return;
@@ -616,7 +616,7 @@
     
   SDValue RV = combine(N);
   
-  if (RV.Val == 0)
+  if (RV.getNode() == 0)
     return;
   
   ++NodesCombined;
@@ -625,19 +625,19 @@
   // zero, we know that the node must have defined multiple values and
   // CombineTo was used.  Since CombineTo takes care of the worklist 
   // mechanics for us, we have no work to do in this case.
-  if (RV.Val == N)
+  if (RV.getNode() == N)
     return;
   
   assert(N->getOpcode() != ISD::DELETED_NODE &&
-         RV.Val->getOpcode() != ISD::DELETED_NODE &&
+         RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
          "Node was deleted but visit returned new node!");
 
   DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
-  DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
+  DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG));
   DOUT << '\n';
 
-  if (N->getNumValues() == RV.Val->getNumValues())
-    DAG.ReplaceAllUsesWith(N, RV.Val);
+  if (N->getNumValues() == RV.getNode()->getNumValues())
+    DAG.ReplaceAllUsesWith(N, RV.getNode());
   else {
     assert(N->getValueType(0) == RV.getValueType() &&
            N->getNumValues() == 1 && "Type mismatch");
@@ -650,8 +650,8 @@
   DAG.DeleteNode(N);
 
   // Push the new node and any users onto the worklist
-  AddToWorkList(RV.Val);
-  AddUsersToWorkList(RV.Val);
+  AddToWorkList(RV.getNode());
+  AddUsersToWorkList(RV.getNode());
 }
 
 void DAGCombiner::Run(bool RunningAfterLegalize) {
@@ -761,7 +761,7 @@
   SDValue RV = visit(N);
 
   // If nothing happened, try a target-specific DAG combine.
-  if (RV.Val == 0) {
+  if (RV.getNode() == 0) {
     assert(N->getOpcode() != ISD::DELETED_NODE &&
            "Node was deleted but visit returned NULL!");
 
@@ -778,7 +778,7 @@
 
   // If N is a commutative binary node, try commuting it to enable more 
   // sdisel CSE.
-  if (RV.Val == 0 && 
+  if (RV.getNode() == 0 && 
       SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
       N->getNumValues() == 1) {
     SDValue N0 = N->getOperand(0);
@@ -815,9 +815,9 @@
   // If N has two operands, where one has an input chain equal to the other,
   // the 'other' chain is redundant.
   if (N->getNumOperands() == 2) {
-    if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
+    if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
       return N->getOperand(0);
-    if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
+    if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
       return N->getOperand(1);
   }
   
@@ -847,11 +847,11 @@
         
       case ISD::TokenFactor:
         if ((CombinerAA || Op.hasOneUse()) &&
-            std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
+            std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
           // Queue up for processing.
-          TFs.push_back(Op.Val);
+          TFs.push_back(Op.getNode());
           // Clean up in case the token factor is removed.
-          AddToWorkList(Op.Val);
+          AddToWorkList(Op.getNode());
           Changed = true;
           break;
         }
@@ -859,7 +859,7 @@
         
       default:
         // Only add if it isn't already in the list.
-        if (SeenOps.insert(Op.Val))
+        if (SeenOps.insert(Op.getNode()))
           Ops.push_back(Op);
         else
           Changed = true;
@@ -905,7 +905,7 @@
   SDValue N00 = N0.getOperand(0);
   SDValue N01 = N0.getOperand(1);
   ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
-  if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
+  if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
       isa<ConstantSDNode>(N00.getOperand(1))) {
     N0 = DAG.getNode(ISD::ADD, VT,
                      DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
@@ -975,7 +975,7 @@
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (add x, undef) -> undef
@@ -1001,7 +1001,7 @@
                          N0.getOperand(1));
   // reassociate add
   SDValue RADD = ReassociateOps(ISD::ADD, N0, N1);
-  if (RADD.Val != 0)
+  if (RADD.getNode() != 0)
     return RADD;
   // fold ((0-A) + B) -> B-A
   if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
@@ -1036,23 +1036,23 @@
   }
 
   // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
-  if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
+  if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
     SDValue Result = combineShlAddConstant(N0, N1, DAG);
-    if (Result.Val) return Result;
+    if (Result.getNode()) return Result;
   }
-  if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
+  if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
     SDValue Result = combineShlAddConstant(N1, N0, DAG);
-    if (Result.Val) return Result;
+    if (Result.getNode()) return Result;
   }
 
   // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
-  if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
+  if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
     SDValue Result = combineSelectAndUse(N, N0, N1, DAG);
-    if (Result.Val) return Result;
+    if (Result.getNode()) return Result;
   }
-  if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
+  if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
     SDValue Result = combineSelectAndUse(N, N1, N0, DAG);
-    if (Result.Val) return Result;
+    if (Result.getNode()) return Result;
   }
 
   return SDValue();
@@ -1121,14 +1121,14 @@
 SDValue DAGCombiner::visitSUB(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
-  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
+  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
+  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
   MVT VT = N0.getValueType();
   
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (sub x, x) -> 0
@@ -1148,9 +1148,9 @@
   if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
     return N0.getOperand(0);
   // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
-  if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
+  if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
     SDValue Result = combineSelectAndUse(N, N1, N0, DAG);
-    if (Result.Val) return Result;
+    if (Result.getNode()) return Result;
   }
   // If either operand of a sub is undef, the result is undef
   if (N0.getOpcode() == ISD::UNDEF)
@@ -1171,7 +1171,7 @@
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (mul x, undef) -> 0
@@ -1208,7 +1208,7 @@
   if (N1C && N0.getOpcode() == ISD::SHL && 
       isa<ConstantSDNode>(N0.getOperand(1))) {
     SDValue C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
-    AddToWorkList(C3.Val);
+    AddToWorkList(C3.getNode());
     return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
   }
   
@@ -1218,19 +1218,19 @@
     SDValue Sh(0,0), Y(0,0);
     // Check for both (mul (shl X, C), Y)  and  (mul Y, (shl X, C)).
     if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
-        N0.Val->hasOneUse()) {
+        N0.getNode()->hasOneUse()) {
       Sh = N0; Y = N1;
     } else if (N1.getOpcode() == ISD::SHL && 
-               isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
+               isa<ConstantSDNode>(N1.getOperand(1)) && N1.getNode()->hasOneUse()) {
       Sh = N1; Y = N0;
     }
-    if (Sh.Val) {
+    if (Sh.getNode()) {
       SDValue Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
       return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
     }
   }
   // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
-  if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 
+  if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 
       isa<ConstantSDNode>(N0.getOperand(1))) {
     return DAG.getNode(ISD::ADD, VT, 
                        DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
@@ -1239,7 +1239,7 @@
   
   // reassociate mul
   SDValue RMUL = ReassociateOps(ISD::MUL, N0, N1);
-  if (RMUL.Val != 0)
+  if (RMUL.getNode() != 0)
     return RMUL;
 
   return SDValue();
@@ -1248,14 +1248,14 @@
 SDValue DAGCombiner::visitSDIV(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
-  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
+  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
+  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
   MVT VT = N->getValueType(0);
 
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (sdiv c1, c2) -> c1/c2
@@ -1288,21 +1288,21 @@
     SDValue SGN = DAG.getNode(ISD::SRA, VT, N0,
                                 DAG.getConstant(VT.getSizeInBits()-1,
                                                 TLI.getShiftAmountTy()));
-    AddToWorkList(SGN.Val);
+    AddToWorkList(SGN.getNode());
     // Add (N0 < 0) ? abs2 - 1 : 0;
     SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN,
                                 DAG.getConstant(VT.getSizeInBits()-lg2,
                                                 TLI.getShiftAmountTy()));
     SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
-    AddToWorkList(SRL.Val);
-    AddToWorkList(ADD.Val);    // Divide by pow2
+    AddToWorkList(SRL.getNode());
+    AddToWorkList(ADD.getNode());    // Divide by pow2
     SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD,
                                 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
     // If we're dividing by a positive value, we're done.  Otherwise, we must
     // negate the result.
     if (pow2 > 0)
       return SRA;
-    AddToWorkList(SRA.Val);
+    AddToWorkList(SRA.getNode());
     return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
   }
   // if integer divide is expensive and we satisfy the requirements, emit an
@@ -1310,7 +1310,7 @@
   if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 
       !TLI.isIntDivCheap()) {
     SDValue Op = BuildSDIV(N);
-    if (Op.Val) return Op;
+    if (Op.getNode()) return Op;
   }
 
   // undef / X -> 0
@@ -1326,14 +1326,14 @@
 SDValue DAGCombiner::visitUDIV(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
-  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
+  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
+  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
   MVT VT = N->getValueType(0);
   
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (udiv c1, c2) -> c1/c2
@@ -1353,7 +1353,7 @@
                                     DAG.getConstant(SHC->getAPIntValue()
                                                                     .logBase2(),
                                                     ADDVT));
-        AddToWorkList(Add.Val);
+        AddToWorkList(Add.getNode());
         return DAG.getNode(ISD::SRL, VT, N0, Add);
       }
     }
@@ -1361,7 +1361,7 @@
   // fold (udiv x, c) -> alternate
   if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
     SDValue Op = BuildUDIV(N);
-    if (Op.Val) return Op;
+    if (Op.getNode()) return Op;
   }
 
   // undef / X -> 0
@@ -1395,12 +1395,12 @@
   // X%C to the equivalent of X-X/C*C.
   if (N1C && !N1C->isNullValue()) {
     SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
-    AddToWorkList(Div.Val);
-    SDValue OptimizedDiv = combine(Div.Val);
-    if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
+    AddToWorkList(Div.getNode());
+    SDValue OptimizedDiv = combine(Div.getNode());
+    if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
       SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
       SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
-      AddToWorkList(Mul.Val);
+      AddToWorkList(Mul.getNode());
       return Sub;
     }
   }
@@ -1437,7 +1437,7 @@
           DAG.getNode(ISD::ADD, VT, N1,
                  DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
                                  VT));
-        AddToWorkList(Add.Val);
+        AddToWorkList(Add.getNode());
         return DAG.getNode(ISD::AND, VT, N0, Add);
       }
     }
@@ -1447,11 +1447,11 @@
   // X%C to the equivalent of X-X/C*C.
   if (N1C && !N1C->isNullValue()) {
     SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
-    SDValue OptimizedDiv = combine(Div.Val);
-    if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
+    SDValue OptimizedDiv = combine(Div.getNode());
+    if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
       SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
       SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
-      AddToWorkList(Mul.Val);
+      AddToWorkList(Mul.getNode());
       return Sub;
     }
   }
@@ -1540,9 +1540,9 @@
   if (LoExists) {
     SDValue Lo = DAG.getNode(LoOp, N->getValueType(0),
                                N->op_begin(), N->getNumOperands());
-    AddToWorkList(Lo.Val);
-    SDValue LoOpt = combine(Lo.Val);
-    if (LoOpt.Val && LoOpt.Val != Lo.Val &&
+    AddToWorkList(Lo.getNode());
+    SDValue LoOpt = combine(Lo.getNode());
+    if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
         (!AfterLegalize ||
          TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
       return CombineTo(N, LoOpt, LoOpt);
@@ -1551,9 +1551,9 @@
   if (HiExists) {
     SDValue Hi = DAG.getNode(HiOp, N->getValueType(1),
                                N->op_begin(), N->getNumOperands());
-    AddToWorkList(Hi.Val);
-    SDValue HiOpt = combine(Hi.Val);
-    if (HiOpt.Val && HiOpt != Hi &&
+    AddToWorkList(Hi.getNode());
+    SDValue HiOpt = combine(Hi.getNode());
+    if (HiOpt.getNode() && HiOpt != Hi &&
         (!AfterLegalize ||
          TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
       return CombineTo(N, HiOpt, HiOpt);
@@ -1563,28 +1563,28 @@
 
 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
   SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
-  if (Res.Val) return Res;
+  if (Res.getNode()) return Res;
 
   return SDValue();
 }
 
 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
   SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
-  if (Res.Val) return Res;
+  if (Res.getNode()) return Res;
 
   return SDValue();
 }
 
 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
   SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
-  if (Res.Val) return Res;
+  if (Res.getNode()) return Res;
   
   return SDValue();
 }
 
 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
   SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
-  if (Res.Val) return Res;
+  if (Res.getNode()) return Res;
   
   return SDValue();
 }
@@ -1607,7 +1607,7 @@
     SDValue ORNode = DAG.getNode(N->getOpcode(), 
                                    N0.getOperand(0).getValueType(),
                                    N0.getOperand(0), N1.getOperand(0));
-    AddToWorkList(ORNode.Val);
+    AddToWorkList(ORNode.getNode());
     return DAG.getNode(N0.getOpcode(), VT, ORNode);
   }
   
@@ -1621,7 +1621,7 @@
     SDValue ORNode = DAG.getNode(N->getOpcode(),
                                    N0.getOperand(0).getValueType(),
                                    N0.getOperand(0), N1.getOperand(0));
-    AddToWorkList(ORNode.Val);
+    AddToWorkList(ORNode.getNode());
     return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
   }
   
@@ -1640,7 +1640,7 @@
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (and x, undef) -> 0
@@ -1661,7 +1661,7 @@
     return DAG.getConstant(0, VT);
   // reassociate and
   SDValue RAND = ReassociateOps(ISD::AND, N0, N1);
-  if (RAND.Val != 0)
+  if (RAND.getNode() != 0)
     return RAND;
   // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
   if (N1C && N0.getOpcode() == ISD::OR)
@@ -1683,7 +1683,7 @@
       // We actually want to replace all uses of the any_extend with the
       // zero_extend, to avoid duplicating things.  This will later cause this
       // AND to be folded.
-      CombineTo(N0.Val, Zext);
+      CombineTo(N0.getNode(), Zext);
       return SDValue(N, 0);   // Return N so it doesn't get rechecked!
     }
   }
@@ -1697,19 +1697,19 @@
       // fold (X == 0) & (Y == 0) -> (X|Y == 0)
       if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
         SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
-        AddToWorkList(ORNode.Val);
+        AddToWorkList(ORNode.getNode());
         return DAG.getSetCC(VT, ORNode, LR, Op1);
       }
       // fold (X == -1) & (Y == -1) -> (X&Y == -1)
       if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
         SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
-        AddToWorkList(ANDNode.Val);
+        AddToWorkList(ANDNode.getNode());
         return DAG.getSetCC(VT, ANDNode, LR, Op1);
       }
       // fold (X >  -1) & (Y >  -1) -> (X|Y > -1)
       if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
         SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
-        AddToWorkList(ORNode.Val);
+        AddToWorkList(ORNode.getNode());
         return DAG.getSetCC(VT, ORNode, LR, Op1);
       }
     }
@@ -1729,7 +1729,7 @@
   // Simplify: and (op x...), (op y...)  -> (op (and x, y))
   if (N0.getOpcode() == N1.getOpcode()) {
     SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
-    if (Tmp.Val) return Tmp;
+    if (Tmp.getNode()) return Tmp;
   }
   
   // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
@@ -1738,7 +1738,7 @@
       SimplifyDemandedBits(SDValue(N, 0)))
     return SDValue(N, 0);
   // fold (zext_inreg (extload x)) -> (zextload x)
-  if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
+  if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     MVT EVT = LN0->getMemoryVT();
     // If we zero all the possible extended bits, then we can turn this into
@@ -1754,12 +1754,12 @@
                                          LN0->isVolatile(), 
                                          LN0->getAlignment());
       AddToWorkList(N);
-      CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
+      CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
       return SDValue(N, 0);   // Return N so it doesn't get rechecked!
     }
   }
   // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
-  if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
+  if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
       N0.hasOneUse()) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     MVT EVT = LN0->getMemoryVT();
@@ -1776,7 +1776,7 @@
                                          LN0->isVolatile(), 
                                          LN0->getAlignment());
       AddToWorkList(N);
-      CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
+      CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
       return SDValue(N, 0);   // Return N so it doesn't get rechecked!
     }
   }
@@ -1813,13 +1813,13 @@
                                DAG.getConstant(PtrOff, PtrType));
           Alignment = MinAlign(Alignment, PtrOff);
         }
-        AddToWorkList(NewPtr.Val);
+        AddToWorkList(NewPtr.getNode());
         SDValue Load =
           DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
                          LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
                          LN0->isVolatile(), Alignment);
         AddToWorkList(N);
-        CombineTo(N0.Val, Load, Load.getValue(1));
+        CombineTo(N0.getNode(), Load, Load.getValue(1));
         return SDValue(N, 0);   // Return N so it doesn't get rechecked!
       }
     }
@@ -1839,7 +1839,7 @@
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (or x, undef) -> -1
@@ -1862,10 +1862,10 @@
     return N1;
   // reassociate or
   SDValue ROR = ReassociateOps(ISD::OR, N0, N1);
-  if (ROR.Val != 0)
+  if (ROR.getNode() != 0)
     return ROR;
   // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
-  if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
+  if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
              isa<ConstantSDNode>(N0.getOperand(1))) {
     ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
     return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
@@ -1885,7 +1885,7 @@
       if (cast<ConstantSDNode>(LR)->isNullValue() && 
           (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
         SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
-        AddToWorkList(ORNode.Val);
+        AddToWorkList(ORNode.getNode());
         return DAG.getSetCC(VT, ORNode, LR, Op1);
       }
       // fold (X != -1) | (Y != -1) -> (X&Y != -1)
@@ -1893,7 +1893,7 @@
       if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 
           (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
         SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
-        AddToWorkList(ANDNode.Val);
+        AddToWorkList(ANDNode.getNode());
         return DAG.getSetCC(VT, ANDNode, LR, Op1);
       }
     }
@@ -1913,7 +1913,7 @@
   // Simplify: or (op x...), (op y...)  -> (op (or x, y))
   if (N0.getOpcode() == N1.getOpcode()) {
     SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
-    if (Tmp.Val) return Tmp;
+    if (Tmp.getNode()) return Tmp;
   }
   
   // (X & C1) | (Y & C2)  -> (X|Y) & C3  if possible.
@@ -1922,7 +1922,7 @@
       N0.getOperand(1).getOpcode() == ISD::Constant &&
       N1.getOperand(1).getOpcode() == ISD::Constant &&
       // Don't increase # computations.
-      (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
+      (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
     // We can only do this xform if we know that bits from X that are set in C2
     // but not in C1 are already zero.  Likewise for Y.
     const APInt &LHSMask =
@@ -2023,14 +2023,14 @@
       Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
     
     // If there is an AND of either shifted operand, apply it to the result.
-    if (LHSMask.Val || RHSMask.Val) {
+    if (LHSMask.getNode() || RHSMask.getNode()) {
       APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
       
-      if (LHSMask.Val) {
+      if (LHSMask.getNode()) {
         APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
         Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
       }
-      if (RHSMask.Val) {
+      if (RHSMask.getNode()) {
         APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
         Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
       }
@@ -2038,12 +2038,12 @@
       Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
     }
     
-    return Rot.Val;
+    return Rot.getNode();
   }
   
   // If there is a mask here, and we have a variable shift, we can't be sure
   // that we're masking out the right stuff.
-  if (LHSMask.Val || RHSMask.Val)
+  if (LHSMask.getNode() || RHSMask.getNode())
     return 0;
   
   // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
@@ -2054,9 +2054,9 @@
           dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
       if (SUBC->getAPIntValue() == OpSizeInBits) {
         if (HasROTL)
-          return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
+          return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode();
         else
-          return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
+          return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode();
       }
     }
   }
@@ -2069,9 +2069,9 @@
           dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
       if (SUBC->getAPIntValue() == OpSizeInBits) {
         if (HasROTL)
-          return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
+          return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode();
         else
-          return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
+          return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode();
       }
     }
   }
@@ -2094,9 +2094,9 @@
       if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
         if (SUBC->getAPIntValue() == OpSizeInBits) {
           if (HasROTL)
-            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
+            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode();
           else
-            return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
+            return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode();
         }
       }
     } else if (LExtOp0.getOpcode() == ISD::SUB &&
@@ -2108,9 +2108,9 @@
       if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
         if (SUBC->getAPIntValue() == OpSizeInBits) {
           if (HasROTL)
-            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val;
+            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).getNode();
           else
-            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
+            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode();
         }
       }
     }
@@ -2131,7 +2131,7 @@
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
@@ -2153,7 +2153,7 @@
     return N0;
   // reassociate xor
   SDValue RXOR = ReassociateOps(ISD::XOR, N0, N1);
-  if (RXOR.Val != 0)
+  if (RXOR.getNode() != 0)
     return RXOR;
   // fold !(x cc y) -> (x !cc y)
   if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
@@ -2169,11 +2169,11 @@
   }
   // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
   if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
-      N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
+      N0.getNode()->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
     SDValue V = N0.getOperand(0);
     V = DAG.getNode(ISD::XOR, V.getValueType(), V, 
                     DAG.getConstant(1, V.getValueType()));
-    AddToWorkList(V.Val);
+    AddToWorkList(V.getNode());
     return DAG.getNode(ISD::ZERO_EXTEND, VT, V);
   }
   
@@ -2185,7 +2185,7 @@
       unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
       LHS = DAG.getNode(ISD::XOR, VT, LHS, N1);  // RHS = ~LHS
       RHS = DAG.getNode(ISD::XOR, VT, RHS, N1);  // RHS = ~RHS
-      AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
+      AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
       return DAG.getNode(NewOpcode, VT, LHS, RHS);
     }
   }
@@ -2197,7 +2197,7 @@
       unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
       LHS = DAG.getNode(ISD::XOR, VT, LHS, N1);  // RHS = ~LHS
       RHS = DAG.getNode(ISD::XOR, VT, RHS, N1);  // RHS = ~RHS
-      AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
+      AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
       return DAG.getNode(NewOpcode, VT, LHS, RHS);
     }
   }
@@ -2229,7 +2229,7 @@
   // Simplify: xor (op x...), (op y...)  -> (op (xor x, y))
   if (N0.getOpcode() == N1.getOpcode()) {
     SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
-    if (Tmp.Val) return Tmp;
+    if (Tmp.getNode()) return Tmp;
   }
   
   // Simplify the expression using non-local knowledge.
@@ -2243,7 +2243,7 @@
 /// visitShiftByConstant - Handle transforms common to the three shifts, when
 /// the shift amount is a constant.
 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
-  SDNode *LHS = N->getOperand(0).Val;
+  SDNode *LHS = N->getOperand(0).getNode();
   if (!LHS->hasOneUse()) return SDValue();
   
   // We want to pull some binops through shifts, so that we have (and (shift))
@@ -2278,7 +2278,7 @@
   //
   //void foo(int *X, int i) { X[i & 1235] = 1; }
   //int bar(int *X, int i) { return X[i & 255]; }
-  SDNode *BinOpLHSVal = LHS->getOperand(0).Val;
+  SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
   if ((BinOpLHSVal->getOpcode() != ISD::SHL && 
        BinOpLHSVal->getOpcode() != ISD::SRA &&
        BinOpLHSVal->getOpcode() != ISD::SRL) ||
@@ -2502,7 +2502,7 @@
       return DAG.getNode(ISD::UNDEF, VT);
 
     SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
-    AddToWorkList(SmallShift.Val);
+    AddToWorkList(SmallShift.getNode());
     return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
   }
   
@@ -2540,7 +2540,7 @@
       if (ShAmt) {
         Op = DAG.getNode(ISD::SRL, VT, Op,
                          DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
-        AddToWorkList(Op.Val);
+        AddToWorkList(Op.getNode());
       }
       return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
     }
@@ -2612,7 +2612,7 @@
     SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
     if (VT == VT0)
       return XORNode;
-    AddToWorkList(XORNode.Val);
+    AddToWorkList(XORNode.getNode());
     if (VT.bitsGT(VT0))
       return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
     return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
@@ -2620,13 +2620,13 @@
   // fold select C, 0, X -> ~C & X
   if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
     SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
-    AddToWorkList(XORNode.Val);
+    AddToWorkList(XORNode.getNode());
     return DAG.getNode(ISD::AND, VT, XORNode, N2);
   }
   // fold select C, X, 1 -> ~C | X
   if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
     SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
-    AddToWorkList(XORNode.Val);
+    AddToWorkList(XORNode.getNode());
     return DAG.getNode(ISD::OR, VT, XORNode, N1);
   }
   // fold select C, X, 0 -> C & X
@@ -2673,9 +2673,9 @@
   
   // Determine if the condition we're dealing with is constant
   SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
-  if (SCC.Val) AddToWorkList(SCC.Val);
+  if (SCC.getNode()) AddToWorkList(SCC.getNode());
 
-  if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
+  if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
     if (!SCCC->isNullValue())
       return N2;    // cond always true -> true val
     else
@@ -2683,7 +2683,7 @@
   }
   
   // Fold to a simpler select_cc
-  if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
+  if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
     return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 
                        SCC.getOperand(0), SCC.getOperand(1), N2, N3, 
                        SCC.getOperand(2));
@@ -2711,7 +2711,7 @@
                                     TargetLowering &TLI) {
   bool HasCopyToRegUses = false;
   bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
-  for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end();
+  for (SDNode::use_iterator UI = N0.getNode()->use_begin(), UE = N0.getNode()->use_end();
        UI != UE; ++UI) {
     SDNode *User = *UI;
     if (User == N)
@@ -2755,7 +2755,7 @@
       SDNode *User = *UI;
       for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
         SDValue UseOp = User->getOperand(i);
-        if (UseOp.Val == N && UseOp.getResNo() == 0) {
+        if (UseOp.getNode() == N && UseOp.getResNo() == 0) {
           BothLiveOut = true;
           break;
         }
@@ -2785,10 +2785,10 @@
   if (N0.getOpcode() == ISD::TRUNCATE) {
     // fold (sext (truncate (load x))) -> (sext (smaller load x))
     // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
-    SDValue NarrowLoad = ReduceLoadWidth(N0.Val);
-    if (NarrowLoad.Val) {
-      if (NarrowLoad.Val != N0.Val)
-        CombineTo(N0.Val, NarrowLoad);
+    SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
+    if (NarrowLoad.getNode()) {
+      if (NarrowLoad.getNode() != N0.getNode())
+        CombineTo(N0.getNode(), NarrowLoad);
       return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
     }
 
@@ -2830,7 +2830,7 @@
   }
   
   // fold (sext (load x)) -> (sext (truncate (sextload x)))
-  if (ISD::isNON_EXTLoad(N0.Val) &&
+  if (ISD::isNON_EXTLoad(N0.getNode()) &&
       ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
        TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))) {
     bool DoXform = true;
@@ -2847,7 +2847,7 @@
                                          LN0->getAlignment());
       CombineTo(N, ExtLoad);
       SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
-      CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
+      CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
       // Extend SetCC uses if necessary.
       for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
         SDNode *SetCC = SetCCs[i];
@@ -2869,8 +2869,8 @@
 
   // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
   // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
-  if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
-      ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
+  if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
+      ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     MVT EVT = LN0->getMemoryVT();
     if ((!AfterLegalize && !LN0->isVolatile()) ||
@@ -2881,7 +2881,7 @@
                                          LN0->isVolatile(), 
                                          LN0->getAlignment());
       CombineTo(N, ExtLoad);
-      CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
+      CombineTo(N0.getNode(), DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
                 ExtLoad.getValue(1));
       return SDValue(N, 0);   // Return N so it doesn't get rechecked!
     }
@@ -2893,7 +2893,7 @@
       SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
                        DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
                        cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
-    if (SCC.Val) return SCC;
+    if (SCC.getNode()) return SCC;
   }
   
   // fold (sext x) -> (zext x) if the sign bit is known zero.
@@ -2919,10 +2919,10 @@
   // fold (zext (truncate (load x))) -> (zext (smaller load x))
   // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
   if (N0.getOpcode() == ISD::TRUNCATE) {
-    SDValue NarrowLoad = ReduceLoadWidth(N0.Val);
-    if (NarrowLoad.Val) {
-      if (NarrowLoad.Val != N0.Val)
-        CombineTo(N0.Val, NarrowLoad);
+    SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
+    if (NarrowLoad.getNode()) {
+      if (NarrowLoad.getNode() != N0.getNode())
+        CombineTo(N0.getNode(), NarrowLoad);
       return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
     }
   }
@@ -2955,7 +2955,7 @@
   }
   
   // fold (zext (load x)) -> (zext (truncate (zextload x)))
-  if (ISD::isNON_EXTLoad(N0.Val) &&
+  if (ISD::isNON_EXTLoad(N0.getNode()) &&
       ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
        TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
     bool DoXform = true;
@@ -2972,7 +2972,7 @@
                                          LN0->getAlignment());
       CombineTo(N, ExtLoad);
       SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
-      CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
+      CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
       // Extend SetCC uses if necessary.
       for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
         SDNode *SetCC = SetCCs[i];
@@ -2994,8 +2994,8 @@
 
   // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
   // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
-  if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
-      ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
+  if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
+      ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     MVT EVT = LN0->getMemoryVT();
     if ((!AfterLegalize && !LN0->isVolatile()) ||
@@ -3006,7 +3006,7 @@
                                          LN0->isVolatile(),
                                          LN0->getAlignment());
       CombineTo(N, ExtLoad);
-      CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
+      CombineTo(N0.getNode(), DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
                 ExtLoad.getValue(1));
       return SDValue(N, 0);   // Return N so it doesn't get rechecked!
     }
@@ -3018,7 +3018,7 @@
       SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
                        DAG.getConstant(1, VT), DAG.getConstant(0, VT),
                        cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
-    if (SCC.Val) return SCC;
+    if (SCC.getNode()) return SCC;
   }
   
   return SDValue();
@@ -3042,10 +3042,10 @@
   // fold (aext (truncate (load x))) -> (aext (smaller load x))
   // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
   if (N0.getOpcode() == ISD::TRUNCATE) {
-    SDValue NarrowLoad = ReduceLoadWidth(N0.Val);
-    if (NarrowLoad.Val) {
-      if (NarrowLoad.Val != N0.Val)
-        CombineTo(N0.Val, NarrowLoad);
+    SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
+    if (NarrowLoad.getNode()) {
+      if (NarrowLoad.getNode() != N0.getNode())
+        CombineTo(N0.getNode(), NarrowLoad);
       return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
     }
   }
@@ -3076,7 +3076,7 @@
   }
   
   // fold (aext (load x)) -> (aext (truncate (extload x)))
-  if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
+  if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
       ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
        TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
@@ -3088,7 +3088,7 @@
                                        LN0->getAlignment());
     CombineTo(N, ExtLoad);
     // Redirect any chain users to the new load.
-    DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), SDValue(ExtLoad.Val, 1));
+    DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), SDValue(ExtLoad.getNode(), 1));
     // If any node needs the original loaded value, recompute it.
     if (!LN0->use_empty())
       CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
@@ -3100,7 +3100,7 @@
   // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
   // fold (aext ( extload x)) -> (aext (truncate (extload  x)))
   if (N0.getOpcode() == ISD::LOAD &&
-      !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
+      !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
       N0.hasOneUse()) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     MVT EVT = LN0->getMemoryVT();
@@ -3111,7 +3111,7 @@
                                        LN0->isVolatile(), 
                                        LN0->getAlignment());
     CombineTo(N, ExtLoad);
-    CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
+    CombineTo(N0.getNode(), DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
               ExtLoad.getValue(1));
     return SDValue(N, 0);   // Return N so it doesn't get rechecked!
   }
@@ -3122,7 +3122,7 @@
       SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
                        DAG.getConstant(1, VT), DAG.getConstant(0, VT),
                        cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
-    if (SCC.Val)
+    if (SCC.getNode())
       return SCC;
   }
   
@@ -3145,14 +3145,14 @@
     break;
   case ISD::SRL:
     // Only look at single-use SRLs.
-    if (!V.Val->hasOneUse())
+    if (!V.getNode()->hasOneUse())
       break;
     if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
       // See if we can recursively simplify the LHS.
       unsigned Amt = RHSC->getValue();
       APInt NewMask = Mask << Amt;
       SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
-      if (SimplifyLHS.Val) {
+      if (SimplifyLHS.getNode()) {
         return DAG.getNode(ISD::SRL, V.getValueType(), 
                            SimplifyLHS, V.getOperand(1));
       }
@@ -3221,7 +3221,7 @@
     unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
     SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
                                    DAG.getConstant(PtrOff, PtrType));
-    AddToWorkList(NewPtr.Val);
+    AddToWorkList(NewPtr.getNode());
     SDValue Load = (ExtType == ISD::NON_EXTLOAD)
       ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
                     LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
@@ -3234,9 +3234,9 @@
       WorkListRemover DeadNodes(*this);
       DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
                                     &DeadNodes);
-      CombineTo(N->getOperand(0).Val, Load);
+      CombineTo(N->getOperand(0).getNode(), Load);
     } else
-      CombineTo(N0.Val, Load, Load.getValue(1));
+      CombineTo(N0.getNode(), Load, Load.getValue(1));
     if (ShAmt) {
       if (Opc == ISD::SIGN_EXTEND_INREG)
         return DAG.getNode(Opc, VT, Load, N->getOperand(1));
@@ -3293,7 +3293,7 @@
   // fold (sext_in_reg (load x)) -> (smaller sextload x)
   // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
   SDValue NarrowLoad = ReduceLoadWidth(N);
-  if (NarrowLoad.Val)
+  if (NarrowLoad.getNode())
     return NarrowLoad;
 
   // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
@@ -3311,8 +3311,8 @@
   }
 
   // fold (sext_inreg (extload x)) -> (sextload x)
-  if (ISD::isEXTLoad(N0.Val) && 
-      ISD::isUNINDEXEDLoad(N0.Val) &&
+  if (ISD::isEXTLoad(N0.getNode()) && 
+      ISD::isUNINDEXEDLoad(N0.getNode()) &&
       EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
       ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
        TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
@@ -3323,11 +3323,11 @@
                                        LN0->isVolatile(), 
                                        LN0->getAlignment());
     CombineTo(N, ExtLoad);
-    CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
+    CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
     return SDValue(N, 0);   // Return N so it doesn't get rechecked!
   }
   // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
-  if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
+  if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
       N0.hasOneUse() &&
       EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
       ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
@@ -3339,7 +3339,7 @@
                                        LN0->isVolatile(), 
                                        LN0->getAlignment());
     CombineTo(N, ExtLoad);
-    CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
+    CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
     return SDValue(N, 0);   // Return N so it doesn't get rechecked!
   }
   return SDValue();
@@ -3379,7 +3379,7 @@
   SDValue Shorter =
     GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
                                              VT.getSizeInBits()));
-  if (Shorter.Val)
+  if (Shorter.getNode())
     return DAG.getNode(ISD::TRUNCATE, VT, Shorter);
 
   // fold (truncate (load x)) -> (smaller load x)
@@ -3390,8 +3390,8 @@
 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
   SDValue Elt = N->getOperand(i);
   if (Elt.getOpcode() != ISD::MERGE_VALUES)
-    return Elt.Val;
-  return Elt.getOperand(Elt.getResNo()).Val;
+    return Elt.getNode();
+  return Elt.getOperand(Elt.getResNo()).getNode();
 }
 
 /// CombineConsecutiveLoads - build_pair (load, load) -> load
@@ -3434,7 +3434,7 @@
   // on the bitconvert.
   // First check to see if this is all constant.
   if (!AfterLegalize &&
-      N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
+      N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
       VT.isVector()) {
     bool isSimple = true;
     for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
@@ -3449,14 +3449,14 @@
     assert(!DestEltVT.isVector() &&
            "Element type of vector ValueType must not be vector!");
     if (isSimple) {
-      return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT);
+      return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT);
     }
   }
   
   // If the input is a constant, let getNode() fold it.
   if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
     SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
-    if (Res.Val != N) return Res;
+    if (Res.getNode() != N) return Res;
   }
   
   if (N0.getOpcode() == ISD::BIT_CONVERT)  // conv(conv(x,t1),t2) -> conv(x,t2)
@@ -3464,7 +3464,7 @@
 
   // fold (conv (load x)) -> (load (conv*)x)
   // If the resultant load doesn't need a higher alignment than the original!
-  if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() &&
+  if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
       // Do not change the width of a volatile load.
       !cast<LoadSDNode>(N0)->isVolatile() &&
       (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) {
@@ -3477,7 +3477,7 @@
                                    LN0->getSrcValue(), LN0->getSrcValueOffset(),
                                    LN0->isVolatile(), OrigAlign);
       AddToWorkList(N);
-      CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
+      CombineTo(N0.getNode(), DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
                 Load.getValue(1));
       return Load;
     }
@@ -3487,9 +3487,9 @@
   // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit)
   // This often reduces constant pool loads.
   if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
-      N0.Val->hasOneUse() && VT.isInteger() && !VT.isVector()) {
+      N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
     SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
-    AddToWorkList(NewConv.Val);
+    AddToWorkList(NewConv.getNode());
     
     APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
     if (N0.getOpcode() == ISD::FNEG)
@@ -3501,45 +3501,45 @@
   // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign'
   // Note that we don't handle copysign(x,cst) because this can always be folded
   // to an fneg or fabs.
-  if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() &&
+  if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
       isa<ConstantFPSDNode>(N0.getOperand(0)) &&
       VT.isInteger() && !VT.isVector()) {
     unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
     SDValue X = DAG.getNode(ISD::BIT_CONVERT,
                               MVT::getIntegerVT(OrigXWidth),
                               N0.getOperand(1));
-    AddToWorkList(X.Val);
+    AddToWorkList(X.getNode());
 
     // If X has a different width than the result/lhs, sext it or truncate it.
     unsigned VTWidth = VT.getSizeInBits();
     if (OrigXWidth < VTWidth) {
       X = DAG.getNode(ISD::SIGN_EXTEND, VT, X);
-      AddToWorkList(X.Val);
+      AddToWorkList(X.getNode());
     } else if (OrigXWidth > VTWidth) {
       // To get the sign bit in the right place, we have to shift it right
       // before truncating.
       X = DAG.getNode(ISD::SRL, X.getValueType(), X, 
                       DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
-      AddToWorkList(X.Val);
+      AddToWorkList(X.getNode());
       X = DAG.getNode(ISD::TRUNCATE, VT, X);
-      AddToWorkList(X.Val);
+      AddToWorkList(X.getNode());
     }
     
     APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
     X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT));
-    AddToWorkList(X.Val);
+    AddToWorkList(X.getNode());
 
     SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
     Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT));
-    AddToWorkList(Cst.Val);
+    AddToWorkList(Cst.getNode());
 
     return DAG.getNode(ISD::OR, VT, X, Cst);
   }
 
   // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 
   if (N0.getOpcode() == ISD::BUILD_PAIR) {
-    SDValue CombineLD = CombineConsecutiveLoads(N0.Val, VT);
-    if (CombineLD.Val)
+    SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
+    if (CombineLD.getNode())
       return CombineLD;
   }
   
@@ -3570,7 +3570,7 @@
     SmallVector<SDValue, 8> Ops;
     for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
       Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
-      AddToWorkList(Ops.back().Val);
+      AddToWorkList(Ops.back().getNode());
     }
     MVT VT = MVT::getVectorVT(DstEltVT,
                               BV->getValueType(0).getVectorNumElements());
@@ -3585,7 +3585,7 @@
     // same sizes.
     assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
     MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits());
-    BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
+    BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
     SrcEltVT = IntVT;
   }
   
@@ -3594,7 +3594,7 @@
   if (DstEltVT.isFloatingPoint()) {
     assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
     MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits());
-    SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val;
+    SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
     
     // Next, convert to FP elements of the same size.
     return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
@@ -3674,7 +3674,7 @@
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (fadd c1, c2) -> c1+c2
@@ -3694,7 +3694,7 @@
   
   // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
   if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
-      N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
+      N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
     return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
                        DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
   
@@ -3711,7 +3711,7 @@
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (fsub c1, c2) -> c1-c2
@@ -3741,7 +3741,7 @@
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (fmul c1, c2) -> c1*c2
@@ -3771,7 +3771,7 @@
   
   // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
   if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
-      N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
+      N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
     return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
                        DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
   
@@ -3788,7 +3788,7 @@
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (fdiv c1, c2) -> c1/c2
@@ -3955,15 +3955,15 @@
   if (N0.getOpcode() == ISD::FP_ROUND) {
     // This is a value preserving truncation if both round's are.
     bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
-                   N0.Val->getConstantOperandVal(1) == 1;
+                   N0.getNode()->getConstantOperandVal(1) == 1;
     return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0),
                        DAG.getIntPtrConstant(IsTrunc));
   }
   
   // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
-  if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
+  if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
     SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1);
-    AddToWorkList(Tmp.Val);
+    AddToWorkList(Tmp.getNode());
     return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
   }
   
@@ -4000,7 +4000,7 @@
 
   // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
   // value of X.
-  if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){
+  if (N0.getOpcode() == ISD::FP_ROUND && N0.getNode()->getConstantOperandVal(1) == 1){
     SDValue In = N0.getOperand(0);
     if (In.getValueType() == VT) return In;
     if (VT.bitsLT(In.getValueType()))
@@ -4009,7 +4009,7 @@
   }
       
   // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
-  if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
+  if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
       ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
        TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
@@ -4020,7 +4020,7 @@
                                        LN0->isVolatile(), 
                                        LN0->getAlignment());
     CombineTo(N, ExtLoad);
-    CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad,
+    CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad,
                                   DAG.getIntPtrConstant(1)),
               ExtLoad.getValue(1));
     return SDValue(N, 0);   // Return N so it doesn't get rechecked!
@@ -4037,7 +4037,7 @@
 
   // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
   // constant pool values.
-  if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() &&
+  if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
       N0.getOperand(0).getValueType().isInteger() &&
       !N0.getOperand(0).getValueType().isVector()) {
     SDValue Int = N0.getOperand(0);
@@ -4045,7 +4045,7 @@
     if (IntVT.isInteger() && !IntVT.isVector()) {
       Int = DAG.getNode(ISD::XOR, IntVT, Int, 
                         DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT));
-      AddToWorkList(Int.Val);
+      AddToWorkList(Int.getNode());
       return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
     }
   }
@@ -4071,7 +4071,7 @@
   
   // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
   // constant pool values.
-  if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() &&
+  if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
       N0.getOperand(0).getValueType().isInteger() &&
       !N0.getOperand(0).getValueType().isVector()) {
     SDValue Int = N0.getOperand(0);
@@ -4079,7 +4079,7 @@
     if (IntVT.isInteger() && !IntVT.isVector()) {
       Int = DAG.getNode(ISD::AND, IntVT, Int, 
                         DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT));
-      AddToWorkList(Int.Val);
+      AddToWorkList(Int.getNode());
       return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
     }
   }
@@ -4117,9 +4117,9 @@
   
   // Use SimplifySetCC to simplify SETCC's.
   SDValue Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
-  if (Simp.Val) AddToWorkList(Simp.Val);
+  if (Simp.getNode()) AddToWorkList(Simp.getNode());
 
-  ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
+  ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode());
 
   // fold br_cc true, dest -> br dest (unconditional branch)
   if (SCCC && !SCCC->isNullValue())
@@ -4130,7 +4130,7 @@
     return N->getOperand(0);
 
   // fold to a simpler setcc
-  if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
+  if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
     return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 
                        Simp.getOperand(2), Simp.getOperand(0),
                        Simp.getOperand(1), N->getOperand(4));
@@ -4174,7 +4174,7 @@
   // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
   // out.  There is no reason to make this a preinc/predec.
   if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
-      Ptr.Val->hasOneUse())
+      Ptr.getNode()->hasOneUse())
     return false;
 
   // Ask the target to do addressing mode selection.
@@ -4204,14 +4204,14 @@
   // Check #2.
   if (!isLoad) {
     SDValue Val = cast<StoreSDNode>(N)->getValue();
-    if (Val == BasePtr || BasePtr.Val->isPredecessorOf(Val.Val))
+    if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
       return false;
   }
 
   // Now check for #3 and #4.
   bool RealUse = false;
-  for (SDNode::use_iterator I = Ptr.Val->use_begin(),
-         E = Ptr.Val->use_end(); I != E; ++I) {
+  for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
+         E = Ptr.getNode()->use_end(); I != E; ++I) {
     SDNode *Use = *I;
     if (Use == N)
       continue;
@@ -4235,7 +4235,7 @@
   ++PreIndexedNodes;
   ++NodesCombined;
   DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
-  DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
+  DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
   DOUT << '\n';
   WorkListRemover DeadNodes(*this);
   if (isLoad) {
@@ -4254,8 +4254,8 @@
   // Replace the uses of Ptr with uses of the updated base value.
   DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
                                 &DeadNodes);
-  removeFromWorkList(Ptr.Val);
-  DAG.DeleteNode(Ptr.Val);
+  removeFromWorkList(Ptr.getNode());
+  DAG.DeleteNode(Ptr.getNode());
 
   return true;
 }
@@ -4292,11 +4292,11 @@
   } else
     return false;
 
-  if (Ptr.Val->hasOneUse())
+  if (Ptr.getNode()->hasOneUse())
     return false;
   
-  for (SDNode::use_iterator I = Ptr.Val->use_begin(),
-         E = Ptr.Val->use_end(); I != E; ++I) {
+  for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
+         E = Ptr.getNode()->use_end(); I != E; ++I) {
     SDNode *Op = *I;
     if (Op == N ||
         (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
@@ -4323,10 +4323,10 @@
 
       // Check for #1.
       bool TryNext = false;
-      for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
-             EE = BasePtr.Val->use_end(); II != EE; ++II) {
+      for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
+             EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
         SDNode *Use = *II;
-        if (Use == Ptr.Val)
+        if (Use == Ptr.getNode())
           continue;
 
         // If all the uses are load / store addresses, then don't do the
@@ -4337,9 +4337,9 @@
                  EEE = Use->use_end(); III != EEE; ++III) {
             SDNode *UseUse = *III;
             if (!((UseUse->getOpcode() == ISD::LOAD &&
-                   cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
+                   cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
                   (UseUse->getOpcode() == ISD::STORE &&
-                   cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)))
+                   cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
               RealUse = true;
           }
 
@@ -4360,7 +4360,7 @@
         ++PostIndexedNodes;
         ++NodesCombined;
         DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
-        DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
+        DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
         DOUT << '\n';
         WorkListRemover DeadNodes(*this);
         if (isLoad) {
@@ -4463,7 +4463,7 @@
         // Now we replace use of chain2 with chain1.  This makes the second load
         // isomorphic to the one we are deleting, and thus makes this load live.
         DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
-        DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG));
+        DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG));
         DOUT << "\n";
         WorkListRemover DeadNodes(*this);
         DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
@@ -4479,7 +4479,7 @@
       if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
         SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0));
         DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
-        DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG));
+        DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG));
         DOUT << " and 2 other values\n";
         WorkListRemover DeadNodes(*this);
         DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
@@ -4500,7 +4500,7 @@
   // TODO: Handle TRUNCSTORE/LOADEXT
   if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
       !LD->isVolatile()) {
-    if (ISD::isNON_TRUNCStore(Chain.Val)) {
+    if (ISD::isNON_TRUNCStore(Chain.getNode())) {
       StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
       if (PrevST->getBasePtr() == Ptr &&
           PrevST->getValue().getValueType() == N->getValueType(0))
@@ -4684,8 +4684,8 @@
       GetDemandedBits(Value,
                  APInt::getLowBitsSet(Value.getValueSizeInBits(),
                                       ST->getMemoryVT().getSizeInBits()));
-    AddToWorkList(Value.Val);
-    if (Shorter.Val)
+    AddToWorkList(Value.getNode());
+    if (Shorter.getNode())
       return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(),
                                ST->getSrcValueOffset(), ST->getMemoryVT(),
                                ST->isVolatile(), ST->getAlignment());
@@ -4715,7 +4715,7 @@
   // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
   // truncating store.  We can do this even if this is already a truncstore.
   if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
-      && Value.Val->hasOneUse() && ST->isUnindexed() &&
+      && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
       TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
                             ST->getMemoryVT())) {
     return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
@@ -4735,7 +4735,7 @@
   // vector with the inserted element.
   if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
     unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
-    SmallVector<SDValue, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
+    SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), InVec.getNode()->op_end());
     if (Elt < Ops.size())
       Ops[Elt] = InVal;
     return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
@@ -4773,11 +4773,11 @@
     }
 
     LoadSDNode *LN0 = NULL;
-    if (ISD::isNormalLoad(InVec.Val))
+    if (ISD::isNormalLoad(InVec.getNode()))
       LN0 = cast<LoadSDNode>(InVec);
     else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
              InVec.getOperand(0).getValueType() == EVT &&
-             ISD::isNormalLoad(InVec.getOperand(0).Val)) {
+             ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
       LN0 = cast<LoadSDNode>(InVec.getOperand(0));
     } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) {
       // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
@@ -4789,7 +4789,7 @@
       InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
       if (InVec.getOpcode() == ISD::BIT_CONVERT)
         InVec = InVec.getOperand(0);
-      if (ISD::isNormalLoad(InVec.Val)) {
+      if (ISD::isNormalLoad(InVec.getNode())) {
         LN0 = cast<LoadSDNode>(InVec);
         Elt = (Idx < NumElems) ? Idx : Idx - NumElems;
       }
@@ -4859,9 +4859,9 @@
     if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
       continue;
     
-    if (VecIn1.Val == 0) {
+    if (VecIn1.getNode() == 0) {
       VecIn1 = ExtractedFromVec;
-    } else if (VecIn2.Val == 0) {
+    } else if (VecIn2.getNode() == 0) {
       VecIn2 = ExtractedFromVec;
     } else {
       // Too many inputs.
@@ -4871,7 +4871,7 @@
   }
   
   // If everything is good, we can make a shuffle operation.
-  if (VecIn1.Val) {
+  if (VecIn1.getNode()) {
     SmallVector<SDValue, 8> BuildVecIndices;
     for (unsigned i = 0; i != NumInScalars; ++i) {
       if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
@@ -4898,7 +4898,7 @@
     // Return the new VECTOR_SHUFFLE node.
     SDValue Ops[5];
     Ops[0] = VecIn1;
-    if (VecIn2.Val) {
+    if (VecIn2.getNode()) {
       Ops[1] = VecIn2;
     } else {
       // Use an undef build_vector as input for the second operand.
@@ -4907,7 +4907,7 @@
                                                EltType));
       Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
                            &UnOps[0], UnOps.size());
-      AddToWorkList(Ops[1].Val);
+      AddToWorkList(Ops[1].getNode());
     }
     Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
                          &BuildVecIndices[0], BuildVecIndices.size());
@@ -4989,7 +4989,7 @@
   // If it is a splat, check if the argument vector is a build_vector with
   // all scalar elements the same.
   if (isSplat) {
-    SDNode *V = N0.Val;
+    SDNode *V = N0.getNode();
 
     // If this is a bit convert that changes the element type of the vector but
     // not the number of vector elements, look through it.  Be careful not to
@@ -4998,7 +4998,7 @@
       SDValue ConvInput = V->getOperand(0);
       if (ConvInput.getValueType().isVector() &&
           ConvInput.getValueType().getVectorNumElements() == NumElts)
-        V = ConvInput.Val;
+        V = ConvInput.getNode();
     }
 
     if (V->getOpcode() == ISD::BUILD_VECTOR) {
@@ -5013,7 +5013,7 @@
           }
         }
         // Splat of <u, u, u, u>, return <u, u, u, u>
-        if (!Base.Val)
+        if (!Base.getNode())
           return N0;
         for (unsigned i = 0; i != NumElems; ++i) {
           if (V->getOperand(i) != Base) {
@@ -5047,7 +5047,7 @@
     }
     ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
                            &MappedOps[0], MappedOps.size());
-    AddToWorkList(ShufMask.Val);
+    AddToWorkList(ShufMask.getNode());
     return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
                        N0,
                        DAG.getNode(ISD::UNDEF, N->getValueType(0)),
@@ -5093,7 +5093,7 @@
       std::vector<SDValue> Ops;
       LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
       Ops.push_back(LHS);
-      AddToWorkList(LHS.Val);
+      AddToWorkList(LHS.getNode());
       std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT));
       Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
                                 &ZeroOps[0], ZeroOps.size()));
@@ -5123,7 +5123,7 @@
   SDValue LHS = N->getOperand(0);
   SDValue RHS = N->getOperand(1);
   SDValue Shuffle = XformToShuffleWithZero(N);
-  if (Shuffle.Val) return Shuffle;
+  if (Shuffle.getNode()) return Shuffle;
 
   // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
   // this operation.
@@ -5145,13 +5145,13 @@
       if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
           N->getOpcode() == ISD::FDIV) {
         if ((RHSOp.getOpcode() == ISD::Constant &&
-             cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
+             cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
             (RHSOp.getOpcode() == ISD::ConstantFP &&
-             cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero()))
+             cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
           break;
       }
       Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp));
-      AddToWorkList(Ops.back().Val);
+      AddToWorkList(Ops.back().getNode());
       assert((Ops.back().getOpcode() == ISD::UNDEF ||
               Ops.back().getOpcode() == ISD::Constant ||
               Ops.back().getOpcode() == ISD::ConstantFP) &&
@@ -5175,14 +5175,14 @@
   // If we got a simplified select_cc node back from SimplifySelectCC, then
   // break it down into a new SETCC node, and a new SELECT node, and then return
   // the SELECT node, since we were called with a SELECT node.
-  if (SCC.Val) {
+  if (SCC.getNode()) {
     // Check to see if we got a select_cc back (to turn into setcc/select).
     // Otherwise, just return whatever node we got back, like fabs.
     if (SCC.getOpcode() == ISD::SELECT_CC) {
       SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
                                     SCC.getOperand(0), SCC.getOperand(1), 
                                     SCC.getOperand(4));
-      AddToWorkList(SETCC.Val);
+      AddToWorkList(SETCC.getNode());
       return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
                          SCC.getOperand(3), SETCC);
     }
@@ -5226,8 +5226,8 @@
         if (TheSelect->getOpcode() == ISD::SELECT) {
           // Check that the condition doesn't reach either load.  If so, folding
           // this will induce a cycle into the DAG.
-          if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) &&
-              !RLD->isPredecessorOf(TheSelect->getOperand(0).Val)) {
+          if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
+              !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) {
             Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
                                TheSelect->getOperand(0), LLD->getBasePtr(),
                                RLD->getBasePtr());
@@ -5235,10 +5235,10 @@
         } else {
           // Check that the condition doesn't reach either load.  If so, folding
           // this will induce a cycle into the DAG.
-          if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) &&
-              !RLD->isPredecessorOf(TheSelect->getOperand(0).Val) &&
-              !LLD->isPredecessorOf(TheSelect->getOperand(1).Val) &&
-              !RLD->isPredecessorOf(TheSelect->getOperand(1).Val)) {
+          if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
+              !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
+              !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) &&
+              !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) {
             Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
                              TheSelect->getOperand(0),
                              TheSelect->getOperand(1), 
@@ -5247,7 +5247,7 @@
           }
         }
         
-        if (Addr.Val) {
+        if (Addr.getNode()) {
           SDValue Load;
           if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
             Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
@@ -5269,8 +5269,8 @@
         
           // Users of the old loads now use the new load's chain.  We know the
           // old-load value is dead now.
-          CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
-          CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
+          CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
+          CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
           return true;
         }
       }
@@ -5285,14 +5285,14 @@
                                       ISD::CondCode CC, bool NotExtCompare) {
   
   MVT VT = N2.getValueType();
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
-  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
-  ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
+  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
+  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
+  ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
 
   // Determine if the condition we're dealing with is constant
   SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
-  if (SCC.Val) AddToWorkList(SCC.Val);
-  ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
+  if (SCC.getNode()) AddToWorkList(SCC.getNode());
+  ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
 
   // fold select_cc true, x, y -> x
   if (SCCC && !SCCC->isNullValue())
@@ -5336,20 +5336,20 @@
         ShCtV = XType.getSizeInBits()-ShCtV-1;
         SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
         SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
-        AddToWorkList(Shift.Val);
+        AddToWorkList(Shift.getNode());
         if (XType.bitsGT(AType)) {
           Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
-          AddToWorkList(Shift.Val);
+          AddToWorkList(Shift.getNode());
         }
         return DAG.getNode(ISD::AND, AType, Shift, N2);
       }
       SDValue Shift = DAG.getNode(ISD::SRA, XType, N0,
                                     DAG.getConstant(XType.getSizeInBits()-1,
                                                     TLI.getShiftAmountTy()));
-      AddToWorkList(Shift.Val);
+      AddToWorkList(Shift.getNode());
       if (XType.bitsGT(AType)) {
         Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
-        AddToWorkList(Shift.Val);
+        AddToWorkList(Shift.getNode());
       }
       return DAG.getNode(ISD::AND, AType, Shift, N2);
     }
@@ -5379,8 +5379,8 @@
       SCC  = DAG.getSetCC(MVT::i1, N0, N1, CC);
       Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
     }
-    AddToWorkList(SCC.Val);
-    AddToWorkList(Temp.Val);
+    AddToWorkList(SCC.getNode());
+    AddToWorkList(Temp.getNode());
     
     if (N2C->getAPIntValue() == 1)
       return Temp;
@@ -5442,8 +5442,8 @@
                                   DAG.getConstant(XType.getSizeInBits()-1,
                                                   TLI.getShiftAmountTy()));
     SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
-    AddToWorkList(Shift.Val);
-    AddToWorkList(Add.Val);
+    AddToWorkList(Shift.getNode());
+    AddToWorkList(Add.getNode());
     return DAG.getNode(ISD::XOR, XType, Add, Shift);
   }
   // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
@@ -5457,8 +5457,8 @@
                                       DAG.getConstant(XType.getSizeInBits()-1,
                                                       TLI.getShiftAmountTy()));
         SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
-        AddToWorkList(Shift.Val);
-        AddToWorkList(Add.Val);
+        AddToWorkList(Shift.getNode());
+        AddToWorkList(Add.getNode());
         return DAG.getNode(ISD::XOR, XType, Add, Shift);
       }
     }
@@ -5612,8 +5612,8 @@
     Chains.pop_back();
     
      // Don't bother if we've been before.
-    if (Visited.find(Chain.Val) != Visited.end()) continue;
-    Visited.insert(Chain.Val);
+    if (Visited.find(Chain.getNode()) != Visited.end()) continue;
+    Visited.insert(Chain.getNode());
   
     switch (Chain.getOpcode()) {
     case ISD::EntryToken:
@@ -5627,7 +5627,7 @@
       int64_t OpSize;
       const Value *OpSrcValue;
       int OpSrcValueOffset;
-      bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
+      bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
                                     OpSrcValue, OpSrcValueOffset);
       
       // If chain is alias then stop here.
@@ -5639,7 +5639,7 @@
         // Look further up the chain.
         Chains.push_back(Chain.getOperand(0));      
         // Clean up old chain.
-        AddToWorkList(Chain.Val);
+        AddToWorkList(Chain.getNode());
       }
       break;
     }
@@ -5652,7 +5652,7 @@
       for (unsigned n = Chain.getNumOperands(); n;)
         Chains.push_back(Chain.getOperand(--n));
       // Eliminate the token factor if we can.
-      AddToWorkList(Chain.Val);
+      AddToWorkList(Chain.getNode());
       break;
       
     default:
@@ -5684,7 +5684,7 @@
                                    &Aliases[0], Aliases.size());
 
   // Make sure the old chain gets cleaned up.
-  if (NewChain != OldChain) AddToWorkList(OldChain.Val);
+  if (NewChain != OldChain) AddToWorkList(OldChain.getNode());
   
   return NewChain;
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Aug 28 16:40:38 2008
@@ -260,7 +260,7 @@
     break;
   }
   }
-  return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
+  return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
 }
 
 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
@@ -350,7 +350,7 @@
   
   assert(Node->getOperand(0).getValueType() == MVT::Other &&
          "Node doesn't have a token chain argument!");
-  return FindCallStartFromCallEnd(Node->getOperand(0).Val);
+  return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
 }
 
 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
@@ -387,7 +387,7 @@
   bool OperandsLeadToDest = false;
   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
     OperandsLeadToDest |=     // If an operand leads to Dest, so do we.
-      LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
+      LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
 
   if (OperandsLeadToDest) {
     NodesLeadingTo.insert(N);
@@ -667,7 +667,7 @@
   MVT VT = Op.getValueType();
   assert(isTypeLegal(VT) &&
          "Caller should expand or promote operands that are not legal!");
-  assert(Op.Val->getNumValues() == 1 &&
+  assert(Op.getNode()->getNumValues() == 1 &&
          "Can't unroll a vector with multiple results!");
   unsigned NE = VT.getVectorNumElements();
   MVT EltVT = VT.getVectorElementType();
@@ -733,7 +733,7 @@
   MVT PtrVT = TLI.getPointerTy();
   SDValue StackPtr = DAG.CreateStackTemporary(VT);
 
-  int SPFI = cast<FrameIndexSDNode>(StackPtr.Val)->getIndex();
+  int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
 
   // Store the vector.
   SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
@@ -764,7 +764,7 @@
   
   assert(isTypeLegal(Op.getValueType()) &&
          "Caller should expand or promote operands that are not legal!");
-  SDNode *Node = Op.Val;
+  SDNode *Node = Op.getNode();
 
   // If this operation defines any values that cannot be represented in a
   // register on this target, make sure to expand or promote them.
@@ -839,7 +839,7 @@
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Op, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       // FALLTHROUGH if the target doesn't want to lower this op after all.
     case TargetLowering::Legal:
       break;
@@ -850,7 +850,7 @@
     // The only option for these nodes is to custom lower them.  If the target
     // does not custom lower them, then return zero.
     Tmp1 = TLI.LowerOperation(Op, DAG);
-    if (Tmp1.Val) 
+    if (Tmp1.getNode()) 
       Result = Tmp1;
     else
       Result = DAG.getConstant(0, TLI.getPointerTy());
@@ -861,7 +861,7 @@
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Custom:
       Result = TLI.LowerOperation(Op, DAG);
-      if (Result.Val) break;
+      if (Result.getNode()) break;
       // Fall Thru
     case TargetLowering::Legal:
       Result = DAG.getConstant(0, VT);
@@ -881,7 +881,7 @@
       break;
     case TargetLowering::Custom:
       Result = TLI.LowerOperation(Op, DAG);
-      if (Result.Val) break;
+      if (Result.getNode()) break;
       // Fall Thru
     case TargetLowering::Legal: {
       SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
@@ -890,9 +890,9 @@
     }
     }
     }
-    if (Result.Val->getNumValues() == 1) break;
+    if (Result.getNode()->getNumValues() == 1) break;
 
-    assert(Result.Val->getNumValues() == 2 &&
+    assert(Result.getNode()->getNumValues() == 2 &&
            "Cannot return more than two values!");
 
     // Since we produced two values, make sure to remember that we
@@ -915,7 +915,7 @@
       break;
     case TargetLowering::Custom:
       Result = TLI.LowerOperation(Op, DAG);
-      if (Result.Val) break;
+      if (Result.getNode()) break;
       // Fall Thru
     case TargetLowering::Legal: {
       SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
@@ -924,9 +924,9 @@
     }
     }
     }
-    if (Result.Val->getNumValues() == 1) break;
+    if (Result.getNode()->getNumValues() == 1) break;
 
-    assert(Result.Val->getNumValues() == 2 &&
+    assert(Result.getNode()->getNumValues() == 2 &&
            "Cannot return more than two values!");
 
     // Since we produced two values, make sure to remember that we
@@ -943,7 +943,7 @@
     default: assert(0 && "This action is not supported at all!");
     case TargetLowering::Custom:
       Result = TLI.LowerOperation(Op, DAG);
-      if (Result.Val) break;
+      if (Result.getNode()) break;
       // Fall Thru
     case TargetLowering::Legal:
       // Target does not know, how to lower this, lower to noop
@@ -1012,13 +1012,13 @@
     if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 
         TargetLowering::Custom) {
       Tmp3 = TLI.LowerOperation(Result, DAG);
-      if (Tmp3.Val) Result = Tmp3;
+      if (Tmp3.getNode()) Result = Tmp3;
     }
 
-    if (Result.Val->getNumValues() == 1) break;
+    if (Result.getNode()->getNumValues() == 1) break;
 
     // Must have return value and chain result.
-    assert(Result.Val->getNumValues() == 2 &&
+    assert(Result.getNode()->getNumValues() == 2 &&
            "Cannot return more than two values!");
 
     // Since loads produce two values, make sure to remember that we 
@@ -1261,7 +1261,7 @@
       Result = TLI.LowerOperation(Result, DAG);
       break;
     case TargetLowering::Expand:
-      Result = SDValue(TLI.ReplaceNodeResults(Op.Val, DAG),0);
+      Result = SDValue(TLI.ReplaceNodeResults(Op.getNode(), DAG),0);
       break;
     case TargetLowering::Legal:
       break;
@@ -1280,7 +1280,7 @@
 
     if (opAction == TargetLowering::Custom) {
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val)
+      if (Tmp1.getNode())
         Result = Tmp1;
     }
     break;
@@ -1298,7 +1298,7 @@
       break;
     case TargetLowering::Custom:
       Tmp3 = TLI.LowerOperation(Result, DAG);
-      if (Tmp3.Val) {
+      if (Tmp3.getNode()) {
         Result = Tmp3;
         break;
       }
@@ -1344,27 +1344,27 @@
   case ISD::CALL:
     // The only option for this is to custom lower it.
     Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
-    assert(Tmp3.Val && "Target didn't custom lower this node!");
+    assert(Tmp3.getNode() && "Target didn't custom lower this node!");
     // A call within a calling sequence must be legalized to something
     // other than the normal CALLSEQ_END.  Violating this gets Legalize
     // into an infinite loop.
     assert ((!IsLegalizingCall ||
              Node->getOpcode() != ISD::CALL ||
-             Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) &&
+             Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
             "Nested CALLSEQ_START..CALLSEQ_END not supported.");
 
     // The number of incoming and outgoing values should match; unless the final
     // outgoing value is a flag.
-    assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
-            (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
-             Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
+    assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
+            (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
+             Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
                MVT::Flag)) &&
            "Lowering call/formal_arguments produced unexpected # results!");
     
     // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
     // remember that we legalized all of them, so it doesn't get relegalized.
-    for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
-      if (Tmp3.Val->getValueType(i) == MVT::Flag)
+    for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
+      if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
         continue;
       Tmp1 = LegalizeOp(Tmp3.getValue(i));
       if (Op.getResNo() == i)
@@ -1394,13 +1394,13 @@
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Custom:
       Tmp3 = TLI.LowerOperation(Result, DAG);
-      if (Tmp3.Val) {
+      if (Tmp3.getNode()) {
         Result = Tmp3;
         break;
       }
       // FALLTHROUGH
     case TargetLowering::Expand:
-      Result = ExpandBUILD_VECTOR(Result.Val);
+      Result = ExpandBUILD_VECTOR(Result.getNode());
       break;
     }
     break;
@@ -1425,7 +1425,7 @@
       break;
     case TargetLowering::Custom:
       Tmp4 = TLI.LowerOperation(Result, DAG);
-      if (Tmp4.Val) {
+      if (Tmp4.getNode()) {
         Result = Tmp4;
         break;
       }
@@ -1485,7 +1485,7 @@
       break;
     case TargetLowering::Custom:
       Tmp3 = TLI.LowerOperation(Result, DAG);
-      if (Tmp3.Val) {
+      if (Tmp3.getNode()) {
         Result = Tmp3;
         break;
       }
@@ -1509,7 +1509,7 @@
       break;
     case TargetLowering::Custom:
       Tmp3 = TLI.LowerOperation(Result, DAG);
-      if (Tmp3.Val) {
+      if (Tmp3.getNode()) {
         Result = Tmp3;
         break;
       }
@@ -1550,7 +1550,7 @@
       
       // Convert the shuffle mask to the right # elements.
       Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
-      assert(Tmp3.Val && "Shuffle not legal?");
+      assert(Tmp3.getNode() && "Shuffle not legal?");
       Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
       Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
       break;
@@ -1580,7 +1580,7 @@
     // are inserted *before* the CALLSEQ_START.
     {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
     for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
-      LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
+      LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
                                    NodesLeadingTo);
     }
 
@@ -1624,7 +1624,7 @@
   case ISD::CALLSEQ_END:
     // If the CALLSEQ_START node hasn't been legalized first, legalize it.  This
     // will cause this node to be legalized as well as handling libcalls right.
-    if (LastCALLSEQ_END.Val != Node) {
+    if (LastCALLSEQ_END.getNode() != Node) {
       LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
       DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
       assert(I != LegalizedNodes.end() &&
@@ -1708,7 +1708,7 @@
     }
     case TargetLowering::Custom:
       Tmp3 = TLI.LowerOperation(Tmp1, DAG);
-      if (Tmp3.Val) {
+      if (Tmp3.getNode()) {
         Tmp1 = LegalizeOp(Tmp3);
         Tmp2 = LegalizeOp(Tmp3.getValue(1));
       }
@@ -1797,7 +1797,7 @@
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       break;
     case TargetLowering::Expand: {
       SDValue Chain = Result.getOperand(0);
@@ -1866,7 +1866,7 @@
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       break;
     case TargetLowering::Expand:
       // Expand brcond's setcc into its constituent parts and create a BR_CC
@@ -1899,7 +1899,7 @@
     // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
     // the LHS is a legal SETCC itself.  In this case, we need to compare
     // the result against zero to select between true and false values.
-    if (Tmp3.Val == 0) {
+    if (Tmp3.getNode() == 0) {
       Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
       Tmp4 = DAG.getCondCode(ISD::SETNE);
     }
@@ -1912,7 +1912,7 @@
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp4 = TLI.LowerOperation(Result, DAG);
-      if (Tmp4.Val) Result = Tmp4;
+      if (Tmp4.getNode()) Result = Tmp4;
       break;
     }
     break;
@@ -1937,7 +1937,7 @@
           unsigned ABIAlignment = TLI.getTargetData()->
             getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
           if (LD->getAlignment() < ABIAlignment){
-            Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
+            Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
                                          TLI);
             Tmp3 = Result.getOperand(0);
             Tmp4 = Result.getOperand(1);
@@ -1948,7 +1948,7 @@
         break;
       case TargetLowering::Custom:
         Tmp1 = TLI.LowerOperation(Tmp3, DAG);
-        if (Tmp1.Val) {
+        if (Tmp1.getNode()) {
           Tmp3 = LegalizeOp(Tmp1);
           Tmp4 = LegalizeOp(Tmp1.getValue(1));
         }
@@ -2105,7 +2105,7 @@
 
           if (isCustom) {
             Tmp3 = TLI.LowerOperation(Result, DAG);
-            if (Tmp3.Val) {
+            if (Tmp3.getNode()) {
               Tmp1 = LegalizeOp(Tmp3);
               Tmp2 = LegalizeOp(Tmp3.getValue(1));
             }
@@ -2116,7 +2116,7 @@
               unsigned ABIAlignment = TLI.getTargetData()->
                 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
               if (LD->getAlignment() < ABIAlignment){
-                Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
+                Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
                                              TLI);
                 Tmp1 = Result.getOperand(0);
                 Tmp2 = Result.getOperand(1);
@@ -2244,13 +2244,13 @@
           if (TLI.isBigEndian())
             std::swap(Lo, Hi);
           
-          if (Hi.Val)
+          if (Hi.getNode())
             Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
           else
             Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
           Result = LegalizeOp(Result);
         } else {
-          SDNode *InVal = Tmp2.Val;
+          SDNode *InVal = Tmp2.getNode();
           int InIx = Tmp2.getResNo();
           unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
           MVT EVT = InVal->getValueType(InIx).getVectorElementType();
@@ -2310,7 +2310,7 @@
           ExpandOp(Node->getOperand(i), Lo, Hi);
           NewValues.push_back(Lo);
           NewValues.push_back(Node->getOperand(i+1));
-          if (Hi.Val) {
+          if (Hi.getNode()) {
             NewValues.push_back(Hi);
             NewValues.push_back(Node->getOperand(i+1));
           }
@@ -2335,7 +2335,7 @@
       case TargetLowering::Legal: break;
       case TargetLowering::Custom:
         Tmp1 = TLI.LowerOperation(Result, DAG);
-        if (Tmp1.Val) Result = Tmp1;
+        if (Tmp1.getNode()) Result = Tmp1;
         break;
       }
     }
@@ -2411,13 +2411,13 @@
             unsigned ABIAlignment = TLI.getTargetData()->
               getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
             if (ST->getAlignment() < ABIAlignment)
-              Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
+              Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
                                             TLI);
           }
           break;
         case TargetLowering::Custom:
           Tmp1 = TLI.LowerOperation(Result, DAG);
-          if (Tmp1.Val) Result = Tmp1;
+          if (Tmp1.getNode()) Result = Tmp1;
           break;
         case TargetLowering::Promote:
           assert(VT.isVector() && "Unknown legal promote case!");
@@ -2446,7 +2446,7 @@
         // the product of the element size in bytes, and the number of elements
         // in the high half of the vector.
         if (ST->getValue().getValueType().isVector()) {
-          SDNode *InVal = ST->getValue().Val;
+          SDNode *InVal = ST->getValue().getNode();
           int InIx = ST->getValue().getResNo();
           MVT InVT = InVal->getValueType(InIx);
           unsigned NumElems = InVT.getVectorNumElements();
@@ -2473,12 +2473,12 @@
             break;
           } else {
             SplitVectorOp(ST->getValue(), Lo, Hi);
-            IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() *
+            IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
                             EVT.getSizeInBits()/8;
           }
         } else {
           ExpandOp(ST->getValue(), Lo, Hi);
-          IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0;
+          IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
 
           if (TLI.isBigEndian())
             std::swap(Lo, Hi);
@@ -2487,7 +2487,7 @@
         Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
                           SVOffset, isVolatile, Alignment);
 
-        if (Hi.Val == NULL) {
+        if (Hi.getNode() == NULL) {
           // Must be int <-> float one-to-one expansion.
           Result = Lo;
           break;
@@ -2598,7 +2598,7 @@
             unsigned ABIAlignment = TLI.getTargetData()->
               getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
             if (ST->getAlignment() < ABIAlignment)
-              Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
+              Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
                                             TLI);
           }
           break;
@@ -2632,7 +2632,7 @@
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp3 = TLI.LowerOperation(Result, DAG);
-      if (Tmp3.Val) {
+      if (Tmp3.getNode()) {
         Tmp1 = LegalizeOp(Tmp3);
         Tmp2 = LegalizeOp(Tmp3.getValue(1));
       }
@@ -2667,7 +2667,7 @@
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       break;
     case TargetLowering::Expand:
       // Expand to CopyToReg if the target set 
@@ -2730,7 +2730,7 @@
     case TargetLowering::Legal: break;
     case TargetLowering::Custom: {
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       break;
     }
     case TargetLowering::Expand:
@@ -2784,7 +2784,7 @@
     // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
     // the LHS is a legal SETCC itself.  In this case, we need to compare
     // the result against zero to select between true and false values.
-    if (Tmp2.Val == 0) {
+    if (Tmp2.getNode() == 0) {
       Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
       CC = DAG.getCondCode(ISD::SETNE);
     }
@@ -2796,7 +2796,7 @@
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       break;
     }
     break;
@@ -2810,7 +2810,7 @@
     // If we had to Expand the SetCC operands into a SELECT node, then it may 
     // not always be possible to return a true LHS & RHS.  In this case, just 
     // return the value we legalized, returned in the LHS
-    if (Tmp2.Val == 0) {
+    if (Tmp2.getNode() == 0) {
       Result = Tmp1;
       break;
     }
@@ -2824,7 +2824,7 @@
       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
       if (isCustom) {
         Tmp4 = TLI.LowerOperation(Result, DAG);
-        if (Tmp4.Val) Result = Tmp4;
+        if (Tmp4.getNode()) Result = Tmp4;
       }
       break;
     case TargetLowering::Promote: {
@@ -2882,7 +2882,7 @@
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       break;
     }
     break;
@@ -2906,7 +2906,7 @@
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) {
+      if (Tmp1.getNode()) {
         SDValue Tmp2, RetVal(0, 0);
         for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
           Tmp2 = LegalizeOp(Tmp1.getValue(i));
@@ -2914,7 +2914,7 @@
           if (i == Op.getResNo())
             RetVal = Tmp2;
         }
-        assert(RetVal.Val && "Illegal result number");
+        assert(RetVal.getNode() && "Illegal result number");
         return RetVal;
       }
       break;
@@ -2974,7 +2974,7 @@
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) {
+      if (Tmp1.getNode()) {
         Result = Tmp1;
         break;
       }
@@ -3004,28 +3004,28 @@
           OpToUse = ISD::UMUL_LOHI;
         }
         if (OpToUse) {
-          Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
+          Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0);
           break;
         }
       }
       if (Node->getOpcode() == ISD::MULHS &&
           TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
-        Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
+        Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 1);
         break;
       }
       if (Node->getOpcode() == ISD::MULHU && 
           TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
-        Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
+        Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 1);
         break;
       }
       if (Node->getOpcode() == ISD::SDIV &&
           TLI.isOperationLegal(ISD::SDIVREM, VT)) {
-        Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
+        Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 0);
         break;
       }
       if (Node->getOpcode() == ISD::UDIV &&
           TLI.isOperationLegal(ISD::UDIVREM, VT)) {
-        Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
+        Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 0);
         break;
       }
 
@@ -3113,7 +3113,7 @@
     default: assert(0 && "Operation not supported");
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       break;
     case TargetLowering::Legal: break;
     case TargetLowering::Expand: {
@@ -3216,7 +3216,7 @@
       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
       if (isCustom) {
         Tmp1 = TLI.LowerOperation(Result, DAG);
-        if (Tmp1.Val) Result = Tmp1;
+        if (Tmp1.getNode()) Result = Tmp1;
       }
       break;
     case TargetLowering::Expand: {
@@ -3228,12 +3228,12 @@
       SDVTList VTs = DAG.getVTList(VT, VT);
       if (Node->getOpcode() == ISD::SREM &&
           TLI.isOperationLegal(ISD::SDIVREM, VT)) {
-        Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
+        Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
         break;
       }
       if (Node->getOpcode() == ISD::UREM &&
           TLI.isOperationLegal(ISD::UDIVREM, VT)) {
-        Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
+        Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
         break;
       }
 
@@ -3288,7 +3288,7 @@
 
       if (isCustom) {
         Tmp2 = TLI.LowerOperation(Result, DAG);
-        if (Tmp2.Val) {
+        if (Tmp2.getNode()) {
           Result = LegalizeOp(Tmp2);
           Tmp1 = LegalizeOp(Tmp2.getValue(1));
         }
@@ -3332,7 +3332,7 @@
                                       Node->getOperand(3), Node->getOperand(4));
       if (isCustom) {
         Tmp1 = TLI.LowerOperation(Result, DAG);
-        if (Tmp1.Val) Result = Tmp1;
+        if (Tmp1.getNode()) Result = Tmp1;
       }
       break;
     case TargetLowering::Expand:
@@ -3359,7 +3359,7 @@
       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
       if (isCustom) {
         Tmp1 = TLI.LowerOperation(Tmp1, DAG);
-        if (Tmp1.Val) Result = Tmp1;
+        if (Tmp1.getNode()) Result = Tmp1;
       }
       break;
     case TargetLowering::Expand:
@@ -3379,7 +3379,7 @@
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       break;
     }
     break;
@@ -3397,7 +3397,7 @@
       break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       break;
     case TargetLowering::Promote:
       assert(0 && "Do not know how to promote ROTL/ROTR");
@@ -3444,7 +3444,7 @@
       if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
           TargetLowering::Custom) {
         Tmp1 = TLI.LowerOperation(Result, DAG);
-        if (Tmp1.Val) {
+        if (Tmp1.getNode()) {
           Result = Tmp1;
         }
       }
@@ -3505,7 +3505,7 @@
       Result = DAG.UpdateNodeOperands(Result, Tmp1);
       if (isCustom) {
         Tmp1 = TLI.LowerOperation(Result, DAG);
-        if (Tmp1.Val) Result = Tmp1;
+        if (Tmp1.getNode()) Result = Tmp1;
       }
       break;
     case TargetLowering::Expand:
@@ -3609,7 +3609,7 @@
     } else if (Op.getOperand(0).getValueType().isVector()) {
       // The input has to be a vector type, we have to either scalarize it, pack
       // it, or convert it based on whether the input vector type is legal.
-      SDNode *InVal = Node->getOperand(0).Val;
+      SDNode *InVal = Node->getOperand(0).getNode();
       int InIx = Node->getOperand(0).getResNo();
       unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
       MVT EVT = InVal->getValueType(InIx).getVectorElementType();
@@ -3690,7 +3690,7 @@
         Result = DAG.UpdateNodeOperands(Result, Tmp1);
         if (isCustom) {
           Tmp1 = TLI.LowerOperation(Result, DAG);
-          if (Tmp1.Val) Result = Tmp1;
+          if (Tmp1.getNode()) Result = Tmp1;
         }
         break;
       case TargetLowering::Promote:
@@ -3832,7 +3832,7 @@
       if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
           TargetLowering::Custom) {
         Tmp1 = TLI.LowerOperation(Result, DAG);
-        if (Tmp1.Val) Result = Tmp1;
+        if (Tmp1.getNode()) Result = Tmp1;
       }
       break;
     case Promote:
@@ -3904,7 +3904,7 @@
     Result = DAG.UpdateNodeOperands(Result, Ops, 6);
     // The only option for this node is to custom lower it.
     Result = TLI.LowerOperation(Result, DAG);
-    assert(Result.Val && "Should always custom lower!");
+    assert(Result.getNode() && "Should always custom lower!");
 
     // Since trampoline produces two values, make sure to remember that we
     // legalized both of them.
@@ -3920,7 +3920,7 @@
     default: assert(0 && "This action not supported for this op yet!");
     case TargetLowering::Custom:
       Result = TLI.LowerOperation(Op, DAG);
-      if (Result.Val) break;
+      if (Result.getNode()) break;
       // Fall Thru
     case TargetLowering::Legal:
       // If this operation is not supported, lower it to constant 1
@@ -3939,7 +3939,7 @@
       break;
     case TargetLowering::Custom:
       Result = TLI.LowerOperation(Op, DAG);
-      if (Result.Val) break;
+      if (Result.getNode()) break;
       // Fall Thru
     case TargetLowering::Expand:
       // If this operation is not supported, lower it to 'abort()' call
@@ -3984,7 +3984,7 @@
 
   SDValue Tmp1, Tmp2, Tmp3;
   SDValue Result;
-  SDNode *Node = Op.Val;
+  SDNode *Node = Op.getNode();
 
   DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
   if (I != PromotedNodes.end()) return I->second;
@@ -4461,7 +4461,7 @@
     break;
   }
 
-  assert(Result.Val && "Didn't set a result!");
+  assert(Result.getNode() && "Didn't set a result!");
 
   // Make sure the result is itself legal.
   Result = LegalizeOp(Result);
@@ -4491,7 +4491,7 @@
     Vec = LegalizeOp(Vec);
     Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
     SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
-    if (Tmp3.Val)
+    if (Tmp3.getNode())
       return Tmp3;
     break;
   }
@@ -4697,14 +4697,14 @@
 
       SDValue Dummy;
       SDValue Ops[2] = { LHS, RHS };
-      Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).Val,
+      Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(),
                            false /*sign irrelevant*/, Dummy);
       Tmp2 = DAG.getConstant(0, MVT::i32);
       CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
       if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
         Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
                            CC);
-        LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).Val,
+        LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
                             false /*sign irrelevant*/, Dummy);
         Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
                            DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
@@ -4791,16 +4791,16 @@
       TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
       Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
                                LowCC, false, DagCombineInfo);
-      if (!Tmp1.Val)
+      if (!Tmp1.getNode())
         Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
       Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
                                CCCode, false, DagCombineInfo);
-      if (!Tmp2.Val)
+      if (!Tmp2.getNode())
         Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
                            RHSHi,CC);
       
-      ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
-      ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
+      ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
+      ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
       if ((Tmp1C && Tmp1C->isNullValue()) ||
           (Tmp2C && Tmp2C->isNullValue() &&
            (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
@@ -4816,7 +4816,7 @@
       } else {
         Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
                                    ISD::SETEQ, false, DagCombineInfo);
-        if (!Result.Val)
+        if (!Result.getNode())
           Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
                               ISD::SETEQ);
         Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
@@ -4958,7 +4958,7 @@
                        PseudoSourceValue::getConstantPool(), 0);
   }
   
-  if (SplatValue.Val) {   // Splat of one value?
+  if (SplatValue.getNode()) {   // Splat of one value?
     // Build the shuffle constant vector: <0, 0, 0, 0>
     MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
     SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
@@ -5095,7 +5095,7 @@
   unsigned NVTBits = NVT.getSizeInBits();
 
   // Handle the case when Amt is an immediate.
-  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
+  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
     unsigned Cst = CN->getValue();
     // Expand the incoming operand to be shifted, so that we have its parts
     SDValue InL, InH;
@@ -5292,14 +5292,14 @@
       // FALLTHROUGH
     case TargetLowering::Legal:
       Tmp1 = LegalizeOp(Op);
-      if (Result.Val)
+      if (Result.getNode())
         Result = DAG.UpdateNodeOperands(Result, Tmp1);
       else
         Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
                              DestTy, Tmp1);
       if (isCustom) {
         Tmp1 = TLI.LowerOperation(Result, DAG);
-        if (Tmp1.Val) Result = Tmp1;
+        if (Tmp1.getNode()) Result = Tmp1;
       }
       break;
     case TargetLowering::Expand:
@@ -5322,7 +5322,7 @@
       Tmp1 = DAG.getZeroExtendInReg(Tmp1,
                                     Op.getValueType());
     }
-    if (Result.Val)
+    if (Result.getNode())
       Result = DAG.UpdateNodeOperands(Result, Tmp1);
     else
       Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
@@ -5427,7 +5427,7 @@
   case TargetLowering::Custom: {
     SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
                                                   Source), DAG);
-    if (NV.Val)
+    if (NV.getNode())
       return LegalizeOp(NV);
     break;   // The target decided this was legal after all
   }
@@ -5448,8 +5448,8 @@
 
   Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
   SDValue HiPart;
-  SDValue Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart);
-  if (Result.getValueType() != DestTy && HiPart.Val)
+  SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
+  if (Result.getValueType() != DestTy && HiPart.getNode())
     Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
   return Result;
 }
@@ -5665,8 +5665,8 @@
   // the target lowering hooks to expand it.  Just keep the low part of the
   // expanded operation, we know that we're truncating anyway.
   if (getTypeAction(NewOutTy) == Expand) {
-    Operation = SDValue(TLI.ReplaceNodeResults(Operation.Val, DAG), 0);
-    assert(Operation.Val && "Didn't return anything");
+    Operation = SDValue(TLI.ReplaceNodeResults(Operation.getNode(), DAG), 0);
+    assert(Operation.getNode() && "Didn't return anything");
   }
 
   // Truncate the result of the extended FP_TO_*INT operation to the desired
@@ -5794,7 +5794,7 @@
 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
   MVT VT = Op.getValueType();
   MVT NVT = TLI.getTypeToTransformTo(VT);
-  SDNode *Node = Op.Val;
+  SDNode *Node = Op.getNode();
   assert(getTypeAction(VT) == Expand && "Not an expanded type!");
   assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
          VT.isVector()) && "Cannot expand to FP value or to larger int value!");
@@ -5820,9 +5820,9 @@
       Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
       SDValue Result = TLI.LowerOperation(
         DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
-      assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
-      Lo = Result.Val->getOperand(0);
-      Hi = Result.Val->getOperand(1);
+      assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
+      Lo = Result.getNode()->getOperand(0);
+      Hi = Result.getNode()->getOperand(1);
       break;
     }
     // fall through
@@ -6145,7 +6145,7 @@
     }
 
     // Turn this into a load/store pair by default.
-    if (Tmp.Val == 0)
+    if (Tmp.getNode() == 0)
       Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
     
     ExpandOp(Tmp, Lo, Hi);
@@ -6157,7 +6157,7 @@
                  TargetLowering::Custom &&
            "Must custom expand ReadCycleCounter");
     SDValue Tmp = TLI.LowerOperation(Op, DAG);
-    assert(Tmp.Val && "Node must be custom expanded!");
+    assert(Tmp.getNode() && "Node must be custom expanded!");
     ExpandOp(Tmp.getValue(0), Lo, Hi);
     AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
                         LegalizeOp(Tmp.getValue(1)));
@@ -6170,7 +6170,7 @@
   case ISD::ATOMIC_CMP_SWAP_32:
   case ISD::ATOMIC_CMP_SWAP_64: {
     SDValue Tmp = TLI.LowerOperation(Op, DAG);
-    assert(Tmp.Val && "Node must be custom expanded!");
+    assert(Tmp.getNode() && "Node must be custom expanded!");
     ExpandOp(Tmp.getValue(0), Lo, Hi);
     AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
                         LegalizeOp(Tmp.getValue(1)));
@@ -6194,7 +6194,7 @@
 
       // Now that the custom expander is done, expand the result, which is still
       // VT.
-      if (Op.Val) {
+      if (Op.getNode()) {
         ExpandOp(Op, Lo, Hi);
         break;
       }
@@ -6219,7 +6219,7 @@
       Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
 
       // Now that the custom expander is done, expand the result.
-      if (Op.Val) {
+      if (Op.getNode()) {
         ExpandOp(Op, Lo, Hi);
         break;
       }
@@ -6238,7 +6238,7 @@
     if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
       SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
       Op = TLI.LowerOperation(Op, DAG);
-      if (Op.Val) {
+      if (Op.getNode()) {
         // Now that the custom expander is done, expand the result, which is
         // still VT.
         ExpandOp(Op, Lo, Hi);
@@ -6288,7 +6288,7 @@
     if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
       SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
       Op = TLI.LowerOperation(Op, DAG);
-      if (Op.Val) {
+      if (Op.getNode()) {
         // Now that the custom expander is done, expand the result, which is
         // still VT.
         ExpandOp(Op, Lo, Hi);
@@ -6320,7 +6320,7 @@
     if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
       SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
       Op = TLI.LowerOperation(Op, DAG);
-      if (Op.Val) {
+      if (Op.getNode()) {
         // Now that the custom expander is done, expand the result, which is
         // still VT.
         ExpandOp(Op, Lo, Hi);
@@ -6352,7 +6352,7 @@
     if (TLI.getOperationAction(Node->getOpcode(), VT) ==
             TargetLowering::Custom) {
       SDValue Result = TLI.LowerOperation(Op, DAG);
-      if (Result.Val) {
+      if (Result.getNode()) {
         ExpandOp(Result, Lo, Hi);
         break;
       }
@@ -6425,7 +6425,7 @@
     // If the target wants to custom expand this, let them.
     if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
       SDValue New = TLI.LowerOperation(Op, DAG);
-      if (New.Val) {
+      if (New.getNode()) {
         ExpandOp(New, Lo, Hi);
         break;
       }
@@ -6450,7 +6450,7 @@
         if (HasUMUL_LOHI) {
           // We can emit a umul_lohi.
           Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
-          Hi = SDValue(Lo.Val, 1);
+          Hi = SDValue(Lo.getNode(), 1);
           break;
         }
         if (HasMULHU) {
@@ -6465,7 +6465,7 @@
         if (HasSMUL_LOHI) {
           // We can emit a smul_lohi.
           Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
-          Hi = SDValue(Lo.Val, 1);
+          Hi = SDValue(Lo.getNode(), 1);
           break;
         }
         if (HasMULHS) {
@@ -6678,7 +6678,7 @@
         ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
                       DAG.getValueType(SrcVT))
         : DAG.getZeroExtendInReg(Tmp, SrcVT);
-      Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
+      Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
       SrcVT = Node->getOperand(0).getValueType();
     }
 
@@ -6739,7 +6739,7 @@
   // is a type that requires multi-step expansion.
   if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
     Lo = LegalizeOp(Lo);
-    if (Hi.Val)
+    if (Hi.getNode())
       // Don't legalize the high part if it is expanded to a single node.
       Hi = LegalizeOp(Hi);
   }
@@ -6755,7 +6755,7 @@
 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
                                          SDValue &Hi) {
   assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
-  SDNode *Node = Op.Val;
+  SDNode *Node = Op.getNode();
   unsigned NumElements = Op.getValueType().getVectorNumElements();
   assert(NumElements > 1 && "Cannot split a single element vector!");
 
@@ -7033,7 +7033,7 @@
       unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
                                             Op.getValueType().getTypeForMVT());
       SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
-      int FI = cast<FrameIndexSDNode>(Ptr.Val)->getIndex();
+      int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
 
       SDValue St = DAG.getStore(DAG.getEntryNode(),
                                   InOp, Ptr,
@@ -7061,7 +7061,7 @@
 /// scalar (e.g. f32) value.
 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
   assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
-  SDNode *Node = Op.Val;
+  SDNode *Node = Op.getNode();
   MVT NewVT = Op.getValueType().getVectorElementType();
   assert(Op.getValueType().getVectorNumElements() == 1);
   

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Thu Aug 28 16:40:38 2008
@@ -76,7 +76,7 @@
   }
 
   // If R is null, the sub-method took care of registering the result.
-  if (R.Val)
+  if (R.getNode())
     SetSoftenedFloat(SDValue(N, ResNo), R);
 }
 
@@ -311,11 +311,11 @@
   }
 
   // If the result is null, the sub-method took care of registering results etc.
-  if (!Res.Val) return false;
+  if (!Res.getNode()) return false;
 
   // If the result is N, the sub-method updated N in place.  Check to see if any
   // operands are new, and if so, mark them.
-  if (Res.Val == N) {
+  if (Res.getNode() == N) {
     // Mark N as new and remark N and its operands.  This allows us to correctly
     // revisit N if it needs another step of promotion and allows us to visit
     // any new operands to N.
@@ -438,7 +438,7 @@
 
   // If SoftenSetCCOperands returned a scalar, we need to compare the result
   // against zero to select between true and false values.
-  if (NewRHS.Val == 0) {
+  if (NewRHS.getNode() == 0) {
     NewRHS = DAG.getConstant(0, NewLHS.getValueType());
     CCCode = ISD::SETNE;
   }
@@ -472,7 +472,7 @@
 
   // If SoftenSetCCOperands returned a scalar, we need to compare the result
   // against zero to select between true and false values.
-  if (NewRHS.Val == 0) {
+  if (NewRHS.getNode() == 0) {
     NewRHS = DAG.getConstant(0, NewLHS.getValueType());
     CCCode = ISD::SETNE;
   }
@@ -489,7 +489,7 @@
   SoftenSetCCOperands(NewLHS, NewRHS, CCCode);
 
   // If SoftenSetCCOperands returned a scalar, use it.
-  if (NewRHS.Val == 0) {
+  if (NewRHS.getNode() == 0) {
     assert(NewLHS.getValueType() == N->getValueType(0) &&
            "Unexpected setcc expansion!");
     return NewLHS;
@@ -577,7 +577,7 @@
   }
 
   // If Lo/Hi is null, the sub-method took care of registering results etc.
-  if (Lo.Val)
+  if (Lo.getNode())
     SetExpandedFloat(SDValue(N, ResNo), Lo, Hi);
 }
 
@@ -603,7 +603,7 @@
                                             RTLIB::ADD_PPCF128),
                                N->getValueType(0), Ops, 2,
                                false);
-  assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!");
+  assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!");
   Lo = Call.getOperand(0); Hi = Call.getOperand(1);
 }
 
@@ -630,7 +630,7 @@
                                             RTLIB::DIV_PPCF128),
                                N->getValueType(0), Ops, 2,
                                false);
-  assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!");
+  assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!");
   Lo = Call.getOperand(0); Hi = Call.getOperand(1);
 }
 
@@ -644,7 +644,7 @@
                                             RTLIB::MUL_PPCF128),
                                N->getValueType(0), Ops, 2,
                                false);
-  assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!");
+  assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!");
   Lo = Call.getOperand(0); Hi = Call.getOperand(1);
 }
 
@@ -672,7 +672,7 @@
                                             RTLIB::SUB_PPCF128),
                                N->getValueType(0), Ops, 2,
                                false);
-  assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!");
+  assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!");
   Lo = Call.getOperand(0); Hi = Call.getOperand(1);
 }
 
@@ -734,7 +734,7 @@
     assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
 
     Hi = MakeLibCall(LC, VT, &Src, 1, true);
-    assert(Hi.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!");
+    assert(Hi.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!");
     Lo = Hi.getOperand(0); Hi = Hi.getOperand(1);
   }
 
@@ -790,7 +790,7 @@
       == TargetLowering::Custom)
     Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
 
-  if (Res.Val == 0) {
+  if (Res.getNode() == 0) {
     switch (N->getOpcode()) {
     default:
   #ifndef NDEBUG
@@ -816,10 +816,10 @@
   }
 
   // If the result is null, the sub-method took care of registering results etc.
-  if (!Res.Val) return false;
+  if (!Res.getNode()) return false;
   // If the result is N, the sub-method updated N in place.  Check to see if any
   // operands are new, and if so, mark them.
-  if (Res.Val == N) {
+  if (Res.getNode() == N) {
     // Mark N as new and remark N and its operands.  This allows us to correctly
     // revisit N if it needs another step of expansion and allows us to visit
     // any new operands to N.
@@ -869,7 +869,7 @@
 
   // If ExpandSetCCOperands returned a scalar, we need to compare the result
   // against zero to select between true and false values.
-  if (NewRHS.Val == 0) {
+  if (NewRHS.getNode() == 0) {
     NewRHS = DAG.getConstant(0, NewLHS.getValueType());
     CCCode = ISD::SETNE;
   }
@@ -910,7 +910,7 @@
 
   // If ExpandSetCCOperands returned a scalar, we need to compare the result
   // against zero to select between true and false values.
-  if (NewRHS.Val == 0) {
+  if (NewRHS.getNode() == 0) {
     NewRHS = DAG.getConstant(0, NewLHS.getValueType());
     CCCode = ISD::SETNE;
   }
@@ -927,7 +927,7 @@
   FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode);
 
   // If ExpandSetCCOperands returned a scalar, use it.
-  if (NewRHS.Val == 0) {
+  if (NewRHS.getNode() == 0) {
     assert(NewLHS.getValueType() == N->getValueType(0) &&
            "Unexpected setcc expansion!");
     return NewLHS;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Thu Aug 28 16:40:38 2008
@@ -99,7 +99,7 @@
   }
 
   // If Result is null, the sub-method took care of registering the result.
-  if (Result.Val)
+  if (Result.getNode())
     SetPromotedInteger(SDValue(N, ResNo), Result);
 }
 
@@ -167,7 +167,7 @@
   // Otherwise, lower the bit-convert to a store/load from the stack, then
   // promote the load.
   SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0));
-  return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.Val));
+  return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.getNode()));
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
@@ -494,7 +494,7 @@
       == TargetLowering::Custom)
     Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
 
-  if (Res.Val == 0) {
+  if (Res.getNode() == 0) {
     switch (N->getOpcode()) {
       default:
   #ifndef NDEBUG
@@ -529,9 +529,9 @@
   }
 
   // If the result is null, the sub-method took care of registering results etc.
-  if (!Res.Val) return false;
+  if (!Res.getNode()) return false;
   // If the result is N, the sub-method updated N in place.
-  if (Res.Val == N) {
+  if (Res.getNode() == N) {
     // Mark N as new and remark N and its operands.  This allows us to correctly
     // revisit N if it needs another step of promotion and allows us to visit
     // any new operands to N.
@@ -885,7 +885,7 @@
   }
 
   // If Lo/Hi is null, the sub-method took care of registering results etc.
-  if (Lo.Val)
+  if (Lo.getNode())
     SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
 }
 
@@ -1395,7 +1395,7 @@
       if (HasUMUL_LOHI) {
         // We can emit a umul_lohi.
         Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
-        Hi = SDValue(Lo.Val, 1);
+        Hi = SDValue(Lo.getNode(), 1);
         return;
       }
       if (HasMULHU) {
@@ -1410,7 +1410,7 @@
       if (HasSMUL_LOHI) {
         // We can emit a smul_lohi.
         Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
-        Hi = SDValue(Lo.Val, 1);
+        Hi = SDValue(Lo.getNode(), 1);
         return;
       }
       if (HasMULHS) {
@@ -1706,7 +1706,7 @@
       == TargetLowering::Custom)
     Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
 
-  if (Res.Val == 0) {
+  if (Res.getNode() == 0) {
     switch (N->getOpcode()) {
     default:
   #ifndef NDEBUG
@@ -1732,10 +1732,10 @@
   }
 
   // If the result is null, the sub-method took care of registering results etc.
-  if (!Res.Val) return false;
+  if (!Res.getNode()) return false;
   // If the result is N, the sub-method updated N in place.  Check to see if any
   // operands are new, and if so, mark them.
-  if (Res.Val == N) {
+  if (Res.getNode() == N) {
     // Mark N as new and remark N and its operands.  This allows us to correctly
     // revisit N if it needs another step of expansion and allows us to visit
     // any new operands to N.
@@ -1814,16 +1814,16 @@
   SDValue Tmp1, Tmp2;
   Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
                            false, DagCombineInfo);
-  if (!Tmp1.Val)
+  if (!Tmp1.getNode())
     Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
   Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
                            CCCode, false, DagCombineInfo);
-  if (!Tmp2.Val)
+  if (!Tmp2.getNode())
     Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
                        DAG.getCondCode(CCCode));
 
-  ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
-  ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
+  ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
+  ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
   if ((Tmp1C && Tmp1C->isNullValue()) ||
       (Tmp2C && Tmp2C->isNullValue() &&
        (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
@@ -1841,7 +1841,7 @@
 
   NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
                              ISD::SETEQ, false, DagCombineInfo);
-  if (!NewLHS.Val)
+  if (!NewLHS.getNode())
     NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
                           ISD::SETEQ);
   NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
@@ -1856,7 +1856,7 @@
 
   // If ExpandSetCCOperands returned a scalar, we need to compare the result
   // against zero to select between true and false values.
-  if (NewRHS.Val == 0) {
+  if (NewRHS.getNode() == 0) {
     NewRHS = DAG.getConstant(0, NewLHS.getValueType());
     CCCode = ISD::SETNE;
   }
@@ -1874,7 +1874,7 @@
 
   // If ExpandSetCCOperands returned a scalar, we need to compare the result
   // against zero to select between true and false values.
-  if (NewRHS.Val == 0) {
+  if (NewRHS.getNode() == 0) {
     NewRHS = DAG.getConstant(0, NewLHS.getValueType());
     CCCode = ISD::SETNE;
   }
@@ -1891,7 +1891,7 @@
   IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
 
   // If ExpandSetCCOperands returned a scalar, use it.
-  if (NewRHS.Val == 0) {
+  if (NewRHS.getNode() == 0) {
     assert(NewLHS.getValueType() == N->getValueType(0) &&
            "Unexpected setcc expansion!");
     return NewLHS;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Thu Aug 28 16:40:38 2008
@@ -92,7 +92,7 @@
     bool NeedsRevisit = false;
     unsigned i;
     for (i = 0; i != NumOperands; ++i) {
-      if (IgnoreNodeResults(N->getOperand(i).Val))
+      if (IgnoreNodeResults(N->getOperand(i).getNode()))
         continue;
 
       MVT OpVT = N->getOperand(i).getValueType();
@@ -194,7 +194,7 @@
 
     // Check that all operand types are legal.
     for (unsigned i = 0, NumOps = I->getNumOperands(); i < NumOps; ++i)
-      if (!IgnoreNodeResults(I->getOperand(i).Val) &&
+      if (!IgnoreNodeResults(I->getOperand(i).getNode()) &&
           !isTypeLegal(I->getOperand(i).getValueType())) {
         cerr << "Operand type " << i << " illegal!\n";
         Failed = true;
@@ -221,7 +221,8 @@
 /// AnalyzeNewNode - The specified node is the root of a subtree of potentially
 /// new nodes.  Correct any processed operands (this may change the node) and
 /// calculate the NodeId.
-void DAGTypeLegalizer::AnalyzeNewNode(SDNode *&N) {
+void DAGTypeLegalizer::AnalyzeNewNode(SDValue &Val) {
+  SDNode * const N(Val.getNode());
   // If this was an existing node that is already done, we're done.
   if (N->getNodeId() != NewNode)
     return;
@@ -246,12 +247,12 @@
     SDValue OrigOp = N->getOperand(i);
     SDValue Op = OrigOp;
 
-    if (Op.Val->getNodeId() == Processed)
+    if (Op.getNode()->getNodeId() == Processed)
       RemapNode(Op);
 
-    if (Op.Val->getNodeId() == NewNode)
-      AnalyzeNewNode(Op.Val);
-    else if (Op.Val->getNodeId() == Processed)
+    if (Op.getNode()->getNodeId() == NewNode)
+      AnalyzeNewNode(Op);
+    else if (Op.getNode()->getNodeId() == Processed)
       ++NumProcessed;
 
     if (!NewOps.empty()) {
@@ -267,11 +268,14 @@
 
   // Some operands changed - update the node.
   if (!NewOps.empty())
-    N = DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0], NewOps.size()).Val;
-
-  N->setNodeId(N->getNumOperands()-NumProcessed);
-  if (N->getNodeId() == ReadyToProcess)
-    Worklist.push_back(N);
+    Val.setNode(DAG.UpdateNodeOperands(SDValue(N, 0),
+				       &NewOps[0],
+				       NewOps.size()).getNode());
+
+  SDNode * const Nu(Val.getNode());
+  Nu->setNodeId(Nu->getNumOperands()-NumProcessed);
+  if (Nu->getNodeId() == ReadyToProcess)
+    Worklist.push_back(Nu);
 }
 
 namespace {
@@ -313,8 +317,8 @@
   if (From == To) return;
 
   // If expansion produced new nodes, make sure they are properly marked.
-  ExpungeNode(From.Val);
-  AnalyzeNewNode(To.Val); // Expunges To.
+  ExpungeNode(From.getNode());
+  AnalyzeNewNode(To); // Expunges To.
 
   // Anything that used the old node should now use the new one.  Note that this
   // can potentially cause recursive merging.
@@ -333,7 +337,10 @@
 
   // If expansion produced new nodes, make sure they are properly marked.
   ExpungeNode(From);
-  AnalyzeNewNode(To); // Expunges To.
+
+  SDValue ToNode(To, 0);
+  AnalyzeNewNode(ToNode); // Expunges To.
+  To = ToNode.getNode();
 
   assert(From->getNumValues() == To->getNumValues() &&
          "Node results don't match");
@@ -394,39 +401,39 @@
 
   for (DenseMap<SDValue, SDValue>::iterator I = PromotedIntegers.begin(),
        E = PromotedIntegers.end(); I != E; ++I) {
-    assert(I->first.Val != N);
+    assert(I->first.getNode() != N);
     RemapNode(I->second);
   }
 
   for (DenseMap<SDValue, SDValue>::iterator I = SoftenedFloats.begin(),
        E = SoftenedFloats.end(); I != E; ++I) {
-    assert(I->first.Val != N);
+    assert(I->first.getNode() != N);
     RemapNode(I->second);
   }
 
   for (DenseMap<SDValue, SDValue>::iterator I = ScalarizedVectors.begin(),
        E = ScalarizedVectors.end(); I != E; ++I) {
-    assert(I->first.Val != N);
+    assert(I->first.getNode() != N);
     RemapNode(I->second);
   }
 
   for (DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator
        I = ExpandedIntegers.begin(), E = ExpandedIntegers.end(); I != E; ++I){
-    assert(I->first.Val != N);
+    assert(I->first.getNode() != N);
     RemapNode(I->second.first);
     RemapNode(I->second.second);
   }
 
   for (DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator
        I = ExpandedFloats.begin(), E = ExpandedFloats.end(); I != E; ++I) {
-    assert(I->first.Val != N);
+    assert(I->first.getNode() != N);
     RemapNode(I->second.first);
     RemapNode(I->second.second);
   }
 
   for (DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator
        I = SplitVectors.begin(), E = SplitVectors.end(); I != E; ++I) {
-    assert(I->first.Val != N);
+    assert(I->first.getNode() != N);
     RemapNode(I->second.first);
     RemapNode(I->second.second);
   }
@@ -440,26 +447,26 @@
 }
 
 void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) {
-  AnalyzeNewNode(Result.Val);
+  AnalyzeNewNode(Result);
 
   SDValue &OpEntry = PromotedIntegers[Op];
-  assert(OpEntry.Val == 0 && "Node is already promoted!");
+  assert(OpEntry.getNode() == 0 && "Node is already promoted!");
   OpEntry = Result;
 }
 
 void DAGTypeLegalizer::SetSoftenedFloat(SDValue Op, SDValue Result) {
-  AnalyzeNewNode(Result.Val);
+  AnalyzeNewNode(Result);
 
   SDValue &OpEntry = SoftenedFloats[Op];
-  assert(OpEntry.Val == 0 && "Node is already converted to integer!");
+  assert(OpEntry.getNode() == 0 && "Node is already converted to integer!");
   OpEntry = Result;
 }
 
 void DAGTypeLegalizer::SetScalarizedVector(SDValue Op, SDValue Result) {
-  AnalyzeNewNode(Result.Val);
+  AnalyzeNewNode(Result);
 
   SDValue &OpEntry = ScalarizedVectors[Op];
-  assert(OpEntry.Val == 0 && "Node is already scalarized!");
+  assert(OpEntry.getNode() == 0 && "Node is already scalarized!");
   OpEntry = Result;
 }
 
@@ -468,7 +475,7 @@
   std::pair<SDValue, SDValue> &Entry = ExpandedIntegers[Op];
   RemapNode(Entry.first);
   RemapNode(Entry.second);
-  assert(Entry.first.Val && "Operand isn't expanded");
+  assert(Entry.first.getNode() && "Operand isn't expanded");
   Lo = Entry.first;
   Hi = Entry.second;
 }
@@ -476,12 +483,12 @@
 void DAGTypeLegalizer::SetExpandedInteger(SDValue Op, SDValue Lo,
                                           SDValue Hi) {
   // Lo/Hi may have been newly allocated, if so, add nodeid's as relevant.
-  AnalyzeNewNode(Lo.Val);
-  AnalyzeNewNode(Hi.Val);
+  AnalyzeNewNode(Lo);
+  AnalyzeNewNode(Hi);
 
   // Remember that this is the result of the node.
   std::pair<SDValue, SDValue> &Entry = ExpandedIntegers[Op];
-  assert(Entry.first.Val == 0 && "Node already expanded");
+  assert(Entry.first.getNode() == 0 && "Node already expanded");
   Entry.first = Lo;
   Entry.second = Hi;
 }
@@ -491,7 +498,7 @@
   std::pair<SDValue, SDValue> &Entry = ExpandedFloats[Op];
   RemapNode(Entry.first);
   RemapNode(Entry.second);
-  assert(Entry.first.Val && "Operand isn't expanded");
+  assert(Entry.first.getNode() && "Operand isn't expanded");
   Lo = Entry.first;
   Hi = Entry.second;
 }
@@ -499,12 +506,12 @@
 void DAGTypeLegalizer::SetExpandedFloat(SDValue Op, SDValue Lo,
                                         SDValue Hi) {
   // Lo/Hi may have been newly allocated, if so, add nodeid's as relevant.
-  AnalyzeNewNode(Lo.Val);
-  AnalyzeNewNode(Hi.Val);
+  AnalyzeNewNode(Lo);
+  AnalyzeNewNode(Hi);
 
   // Remember that this is the result of the node.
   std::pair<SDValue, SDValue> &Entry = ExpandedFloats[Op];
-  assert(Entry.first.Val == 0 && "Node already expanded");
+  assert(Entry.first.getNode() == 0 && "Node already expanded");
   Entry.first = Lo;
   Entry.second = Hi;
 }
@@ -514,7 +521,7 @@
   std::pair<SDValue, SDValue> &Entry = SplitVectors[Op];
   RemapNode(Entry.first);
   RemapNode(Entry.second);
-  assert(Entry.first.Val && "Operand isn't split");
+  assert(Entry.first.getNode() && "Operand isn't split");
   Lo = Entry.first;
   Hi = Entry.second;
 }
@@ -522,12 +529,12 @@
 void DAGTypeLegalizer::SetSplitVector(SDValue Op, SDValue Lo,
                                       SDValue Hi) {
   // Lo/Hi may have been newly allocated, if so, add nodeid's as relevant.
-  AnalyzeNewNode(Lo.Val);
-  AnalyzeNewNode(Hi.Val);
+  AnalyzeNewNode(Lo);
+  AnalyzeNewNode(Hi);
 
   // Remember that this is the result of the node.
   std::pair<SDValue, SDValue> &Entry = SplitVectors[Op];
-  assert(Entry.first.Val == 0 && "Node already split");
+  assert(Entry.first.getNode() == 0 && "Node already split");
   Entry.first = Lo;
   Entry.second = Hi;
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Thu Aug 28 16:40:38 2008
@@ -157,7 +157,8 @@
   /// for the specified node, adding it to the worklist if ready.
   void ReanalyzeNode(SDNode *N) {
     N->setNodeId(NewNode);
-    AnalyzeNewNode(N);
+    SDValue V(N, 0);
+    AnalyzeNewNode(V); // FIXME: ignore the change?
   }
 
   void NoteDeletion(SDNode *Old, SDNode *New) {
@@ -168,7 +169,7 @@
   }
 
 private:
-  void AnalyzeNewNode(SDNode *&N);
+  void AnalyzeNewNode(SDValue &Val);
 
   void ReplaceValueWith(SDValue From, SDValue To);
   void ReplaceNodeWith(SDNode *From, SDNode *To);
@@ -197,7 +198,7 @@
   SDValue GetPromotedInteger(SDValue Op) {
     SDValue &PromotedOp = PromotedIntegers[Op];
     RemapNode(PromotedOp);
-    assert(PromotedOp.Val && "Operand wasn't promoted?");
+    assert(PromotedOp.getNode() && "Operand wasn't promoted?");
     return PromotedOp;
   }
   void SetPromotedInteger(SDValue Op, SDValue Result);
@@ -324,7 +325,7 @@
   SDValue GetSoftenedFloat(SDValue Op) {
     SDValue &SoftenedOp = SoftenedFloats[Op];
     RemapNode(SoftenedOp);
-    assert(SoftenedOp.Val && "Operand wasn't converted to integer?");
+    assert(SoftenedOp.getNode() && "Operand wasn't converted to integer?");
     return SoftenedOp;
   }
   void SetSoftenedFloat(SDValue Op, SDValue Result);
@@ -403,7 +404,7 @@
   SDValue GetScalarizedVector(SDValue Op) {
     SDValue &ScalarizedOp = ScalarizedVectors[Op];
     RemapNode(ScalarizedOp);
-    assert(ScalarizedOp.Val && "Operand wasn't scalarized?");
+    assert(ScalarizedOp.getNode() && "Operand wasn't scalarized?");
     return ScalarizedOp;
   }
   void SetScalarizedVector(SDValue Op, SDValue Result);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Thu Aug 28 16:40:38 2008
@@ -75,7 +75,7 @@
 
   // Lower the bit-convert to a store/load from the stack, then expand the load.
   SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0));
-  ExpandRes_NormalLoad(Op.Val, Lo, Hi);
+  ExpandRes_NormalLoad(Op.getNode(), Lo, Hi);
 }
 
 void DAGTypeLegalizer::ExpandRes_BUILD_PAIR(SDNode *N, SDValue &Lo,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Thu Aug 28 16:40:38 2008
@@ -88,7 +88,7 @@
   }
 
   // If R is null, the sub-method took care of registering the result.
-  if (R.Val)
+  if (R.getNode())
     SetScalarizedVector(SDValue(N, ResNo), R);
 }
 
@@ -184,7 +184,7 @@
         cerr << "\n");
   SDValue Res = SDValue();
 
-  if (Res.Val == 0) {
+  if (Res.getNode() == 0) {
     switch (N->getOpcode()) {
     default:
 #ifndef NDEBUG
@@ -206,11 +206,11 @@
   }
 
   // If the result is null, the sub-method took care of registering results etc.
-  if (!Res.Val) return false;
+  if (!Res.getNode()) return false;
 
   // If the result is N, the sub-method updated N in place.  Check to see if any
   // operands are new, and if so, mark them.
-  if (Res.Val == N) {
+  if (Res.getNode() == N) {
     // Mark N as new and remark N and its operands.  This allows us to correctly
     // revisit N if it needs another step of promotion and allows us to visit
     // any new operands to N.
@@ -332,7 +332,7 @@
   }
 
   // If Lo/Hi is null, the sub-method took care of registering results etc.
-  if (Lo.Val)
+  if (Lo.getNode())
     SetSplitVector(SDValue(N, ResNo), Lo, Hi);
 }
 
@@ -475,7 +475,7 @@
   SDValue Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0);
 
   // Split it.
-  SplitVecRes_LOAD(cast<LoadSDNode>(Load.Val), Lo, Hi);
+  SplitVecRes_LOAD(cast<LoadSDNode>(Load.getNode()), Lo, Hi);
 }
 
 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
@@ -595,7 +595,7 @@
   DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
   SDValue Res = SDValue();
 
-  if (Res.Val == 0) {
+  if (Res.getNode() == 0) {
     switch (N->getOpcode()) {
     default:
 #ifndef NDEBUG
@@ -615,11 +615,11 @@
   }
 
   // If the result is null, the sub-method took care of registering results etc.
-  if (!Res.Val) return false;
+  if (!Res.getNode()) return false;
 
   // If the result is N, the sub-method updated N in place.  Check to see if any
   // operands are new, and if so, mark them.
-  if (Res.Val == N) {
+  if (Res.getNode() == N) {
     // Mark N as new and remark N and its operands.  This allows us to correctly
     // revisit N if it needs another step of promotion and allows us to visit
     // any new operands to N.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Thu Aug 28 16:40:38 2008
@@ -122,7 +122,7 @@
     if (N->getNumOperands() &&
         N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
       do {
-        N = N->getOperand(N->getNumOperands()-1).Val;
+        N = N->getOperand(N->getNumOperands()-1).getNode();
         NodeSUnit->FlaggedNodes.push_back(N);
         assert(N->getNodeId() == -1 && "Node already inserted!");
         N->setNodeId(NodeSUnit->NodeNum);
@@ -192,7 +192,7 @@
         SU->hasPhysRegDefs = true;
       
       for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
-        SDNode *OpN = N->getOperand(i).Val;
+        SDNode *OpN = N->getOperand(i).getNode();
         if (isPassiveNode(OpN)) continue;   // Not scheduled.
         SUnit *OpSU = &SUnits[OpN->getNodeId()];
         assert(OpSU && "Node has no SUnit!");
@@ -373,7 +373,7 @@
 /// actual operands that will go into the resulting MachineInstr.
 unsigned ScheduleDAG::CountOperands(SDNode *Node) {
   unsigned N = ComputeMemOperandsEnd(Node);
-  while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).Val))
+  while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).getNode()))
     --N; // Ignore MEMOPERAND nodes
   return N;
 }
@@ -429,7 +429,7 @@
     SDNode *User = *UI;
     bool Match = true;
     if (User->getOpcode() == ISD::CopyToReg && 
-        User->getOperand(2).Val == Node &&
+        User->getOperand(2).getNode() == Node &&
         User->getOperand(2).getResNo() == ResNo) {
       unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
       if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
@@ -440,7 +440,7 @@
     } else {
       for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
         SDValue Op = User->getOperand(i);
-        if (Op.Val != Node || Op.getResNo() != ResNo)
+        if (Op.getNode() != Node || Op.getResNo() != ResNo)
           continue;
         MVT VT = Node->getValueType(Op.getResNo());
         if (VT != MVT::Other && VT != MVT::Flag)
@@ -489,7 +489,7 @@
 
   SDNode *User = *Node->use_begin();
   if (User->getOpcode() == ISD::CopyToReg && 
-      User->getOperand(2).Val == Node &&
+      User->getOperand(2).getNode() == Node &&
       User->getOperand(2).getResNo() == ResNo) {
     unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
     if (TargetRegisterInfo::isVirtualRegister(Reg))
@@ -513,7 +513,7 @@
          UI != E; ++UI) {
       SDNode *User = *UI;
       if (User->getOpcode() == ISD::CopyToReg && 
-          User->getOperand(2).Val == Node &&
+          User->getOperand(2).getNode() == Node &&
           User->getOperand(2).getResNo() == i) {
         unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
         if (TargetRegisterInfo::isVirtualRegister(Reg)) {
@@ -547,7 +547,7 @@
   if (Op.isMachineOpcode() &&
       Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
     // Add an IMPLICIT_DEF instruction before every use.
-    unsigned VReg = getDstOfOnlyCopyToRegUse(Op.Val, Op.getResNo());
+    unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
     // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
     // does not include operand register class info.
     if (!VReg) {
@@ -600,7 +600,7 @@
       if (RC && VRC != RC) {
         cerr << "Register class of operand and regclass of use don't agree!\n";
         cerr << "Operand = " << IIOpNum << "\n";
-        cerr << "Op->Val = "; Op.Val->dump(&DAG); cerr << "\n";
+        cerr << "Op->Val = "; Op.getNode()->dump(&DAG); cerr << "\n";
         cerr << "MI = "; MI->print(cerr);
         cerr << "VReg = " << VReg << "\n";
         cerr << "VReg RegClass     size = " << VRC->getSize()
@@ -712,7 +712,7 @@
        UI != E; ++UI) {
     SDNode *User = *UI;
     if (User->getOpcode() == ISD::CopyToReg && 
-        User->getOperand(2).Val == Node) {
+        User->getOperand(2).getNode() == Node) {
       unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
       if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
         VRBase = DestReg;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu Aug 28 16:40:38 2008
@@ -224,7 +224,7 @@
         if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1)
           continue;
 
-        SDNode *OpN = SU->Node->getOperand(j).Val;
+        SDNode *OpN = SU->Node->getOperand(j).getNode();
         SUnit *OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()];
         if (OpSU && OperandSeen.count(OpSU) == 1) {
           // Ok, so SU is not the last use of OpSU, but SU is two-address so
@@ -233,7 +233,7 @@
           bool DoCommute = true;
           for (unsigned k = 0; k < NumOps; ++k) {
             if (k != j) {
-              OpN = SU->Node->getOperand(k).Val;
+              OpN = SU->Node->getOperand(k).getNode();
               OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()];
               if (OpSU && OperandSeen.count(OpSU) == 1) {
                 DoCommute = false;
@@ -641,7 +641,7 @@
   }
   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
     const SDValue &Op = N->getOperand(i);
-    MVT VT = Op.Val->getValueType(Op.getResNo());
+    MVT VT = Op.getNode()->getValueType(Op.getResNo());
     if (VT == MVT::Flag)
       return NULL;
   }
@@ -930,7 +930,7 @@
   unsigned CurCycle = 0;
   // Add root to Available queue.
   if (!SUnits.empty()) {
-    SUnit *RootSU = &SUnits[DAG.getRoot().Val->getNodeId()];
+    SUnit *RootSU = &SUnits[DAG.getRoot().getNode()->getNodeId()];
     assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!");
     RootSU->isAvailable = true;
     AvailableQueue->push(RootSU);
@@ -1668,7 +1668,7 @@
     unsigned NumOps = TID.getNumOperands() - NumRes;
     for (unsigned i = 0; i != NumOps; ++i) {
       if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) {
-        SDNode *DU = SU->Node->getOperand(i).Val;
+        SDNode *DU = SU->Node->getOperand(i).getNode();
         if (DU->getNodeId() != -1 &&
             Op->OrigNode == &(*SUnits)[DU->getNodeId()])
           return true;
@@ -1742,7 +1742,7 @@
     unsigned NumOps = TID.getNumOperands() - NumRes;
     for (unsigned j = 0; j != NumOps; ++j) {
       if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) != -1) {
-        SDNode *DU = SU->Node->getOperand(j).Val;
+        SDNode *DU = SU->Node->getOperand(j).getNode();
         if (DU->getNodeId() == -1)
           continue;
         const SUnit *DUSU = &(*SUnits)[DU->getNodeId()];

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Aug 28 16:40:38 2008
@@ -96,7 +96,7 @@
 bool ISD::isBuildVectorAllOnes(const SDNode *N) {
   // Look through a bit convert.
   if (N->getOpcode() == ISD::BIT_CONVERT)
-    N = N->getOperand(0).Val;
+    N = N->getOperand(0).getNode();
   
   if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
   
@@ -137,7 +137,7 @@
 bool ISD::isBuildVectorAllZeros(const SDNode *N) {
   // Look through a bit convert.
   if (N->getOpcode() == ISD::BIT_CONVERT)
-    N = N->getOperand(0).Val;
+    N = N->getOperand(0).getNode();
   
   if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
   
@@ -326,7 +326,7 @@
 static void AddNodeIDOperands(FoldingSetNodeID &ID,
                               const SDValue *Ops, unsigned NumOps) {
   for (; NumOps; --NumOps, ++Ops) {
-    ID.AddPointer(Ops->Val);
+    ID.AddPointer(Ops->getNode());
     ID.AddInteger(Ops->getResNo());
   }
 }
@@ -1230,9 +1230,9 @@
     break;
   }
   
-  if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val)) {
+  if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) {
     const APInt &C2 = N2C->getAPIntValue();
-    if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
+    if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
       const APInt &C1 = N1C->getAPIntValue();
       
       switch (Cond) {
@@ -1250,8 +1250,8 @@
       }
     }
   }
-  if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
-    if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) {
+  if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
+    if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) {
       // No compile time operations on this type yet.
       if (N1C->getValueType(0) == MVT::ppcf128)
         return SDValue();
@@ -1572,7 +1572,7 @@
     return;
   }
   case ISD::LOAD: {
-    if (ISD::isZEXTLoad(Op.Val)) {
+    if (ISD::isZEXTLoad(Op.getNode())) {
       LoadSDNode *LD = cast<LoadSDNode>(Op);
       MVT VT = LD->getMemoryVT();
       unsigned MemBits = VT.getSizeInBits();
@@ -2024,7 +2024,7 @@
   if (V.getOpcode() == ISD::BUILD_VECTOR)
     return V.getOperand(Index);
   if (V.getOpcode() == ISD::VECTOR_SHUFFLE)
-    return getShuffleScalarElt(V.Val, Index);
+    return getShuffleScalarElt(V.getNode(), Index);
   return SDValue();
 }
 
@@ -2050,7 +2050,7 @@
 
 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) {
   // Constant fold unary operations with an integer constant operand.
-  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) {
+  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) {
     const APInt &Val = C->getAPIntValue();
     unsigned BitWidth = VT.getSizeInBits();
     switch (Opcode) {
@@ -2091,7 +2091,7 @@
   }
 
   // Constant fold unary operations with a floating point constant operand.
-  if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.Val)) {
+  if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) {
     APFloat V = C->getValueAPF();    // make copy
     if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) {
       switch (Opcode) {
@@ -2130,7 +2130,7 @@
     }
   }
 
-  unsigned OpOpcode = Operand.Val->getOpcode();
+  unsigned OpOpcode = Operand.getNode()->getOpcode();
   switch (Opcode) {
   case ISD::TokenFactor:
   case ISD::CONCAT_VECTORS:
@@ -2150,7 +2150,7 @@
     assert(Operand.getValueType().bitsLT(VT)
            && "Invalid sext node, dst < src!");
     if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
-      return getNode(OpOpcode, VT, Operand.Val->getOperand(0));
+      return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0));
     break;
   case ISD::ZERO_EXTEND:
     assert(VT.isInteger() && Operand.getValueType().isInteger() &&
@@ -2159,7 +2159,7 @@
     assert(Operand.getValueType().bitsLT(VT)
            && "Invalid zext node, dst < src!");
     if (OpOpcode == ISD::ZERO_EXTEND)   // (zext (zext x)) -> (zext x)
-      return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0));
+      return getNode(ISD::ZERO_EXTEND, VT, Operand.getNode()->getOperand(0));
     break;
   case ISD::ANY_EXTEND:
     assert(VT.isInteger() && Operand.getValueType().isInteger() &&
@@ -2169,7 +2169,7 @@
            && "Invalid anyext node, dst < src!");
     if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND)
       // (ext (zext x)) -> (zext x)  and  (ext (sext x)) -> (sext x)
-      return getNode(OpOpcode, VT, Operand.Val->getOperand(0));
+      return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0));
     break;
   case ISD::TRUNCATE:
     assert(VT.isInteger() && Operand.getValueType().isInteger() &&
@@ -2178,16 +2178,16 @@
     assert(Operand.getValueType().bitsGT(VT)
            && "Invalid truncate node, src < dst!");
     if (OpOpcode == ISD::TRUNCATE)
-      return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0));
+      return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0));
     else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
              OpOpcode == ISD::ANY_EXTEND) {
       // If the source is smaller than the dest, we still need an extend.
-      if (Operand.Val->getOperand(0).getValueType().bitsLT(VT))
-        return getNode(OpOpcode, VT, Operand.Val->getOperand(0));
-      else if (Operand.Val->getOperand(0).getValueType().bitsGT(VT))
-        return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0));
+      if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT))
+        return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0));
+      else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT))
+        return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0));
       else
-        return Operand.Val->getOperand(0);
+        return Operand.getNode()->getOperand(0);
     }
     break;
   case ISD::BIT_CONVERT:
@@ -2215,14 +2215,14 @@
     break;
   case ISD::FNEG:
     if (OpOpcode == ISD::FSUB)   // -(X-Y) -> (Y-X)
-      return getNode(ISD::FSUB, VT, Operand.Val->getOperand(1),
-                     Operand.Val->getOperand(0));
+      return getNode(ISD::FSUB, VT, Operand.getNode()->getOperand(1),
+                     Operand.getNode()->getOperand(0));
     if (OpOpcode == ISD::FNEG)  // --X -> X
-      return Operand.Val->getOperand(0);
+      return Operand.getNode()->getOperand(0);
     break;
   case ISD::FABS:
     if (OpOpcode == ISD::FNEG)  // abs(-X) -> abs(X)
-      return getNode(ISD::FABS, VT, Operand.Val->getOperand(0));
+      return getNode(ISD::FABS, VT, Operand.getNode()->getOperand(0));
     break;
   }
 
@@ -2252,8 +2252,8 @@
 
 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
                               SDValue N1, SDValue N2) {
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
-  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
+  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
+  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
   switch (Opcode) {
   default: break;
   case ISD::TokenFactor:
@@ -2268,8 +2268,8 @@
     // one big BUILD_VECTOR.
     if (N1.getOpcode() == ISD::BUILD_VECTOR &&
         N2.getOpcode() == ISD::BUILD_VECTOR) {
-      SmallVector<SDValue, 16> Elts(N1.Val->op_begin(), N1.Val->op_end());
-      Elts.insert(Elts.end(), N2.Val->op_begin(), N2.Val->op_end());
+      SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end());
+      Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end());
       return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size());
     }
     break;
@@ -2471,8 +2471,8 @@
   }
 
   // Constant fold FP operations.
-  ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val);
-  ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val);
+  ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode());
+  ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode());
   if (N1CFP) {
     if (!N2CFP && isCommutativeBinOp(Opcode)) {
       // Cannonicalize constant to RHS if commutative
@@ -2615,8 +2615,8 @@
 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
                               SDValue N1, SDValue N2, SDValue N3) {
   // Perform various simplifications.
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
-  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
+  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
+  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
   switch (Opcode) {
   case ISD::CONCAT_VECTORS:
     // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to
@@ -2624,16 +2624,16 @@
     if (N1.getOpcode() == ISD::BUILD_VECTOR &&
         N2.getOpcode() == ISD::BUILD_VECTOR &&
         N3.getOpcode() == ISD::BUILD_VECTOR) {
-      SmallVector<SDValue, 16> Elts(N1.Val->op_begin(), N1.Val->op_end());
-      Elts.insert(Elts.end(), N2.Val->op_begin(), N2.Val->op_end());
-      Elts.insert(Elts.end(), N3.Val->op_begin(), N3.Val->op_end());
+      SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end());
+      Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end());
+      Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end());
       return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size());
     }
     break;
   case ISD::SETCC: {
     // Use FoldSetCC to simplify SETCC's.
     SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get());
-    if (Simp.Val) return Simp;
+    if (Simp.getNode()) return Simp;
     break;
   }
   case ISD::SELECT:
@@ -3049,7 +3049,7 @@
     SDValue Result =
       getMemcpyLoadsAndStores(*this, Chain, Dst, Src, ConstantSize->getValue(),
                               Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff);
-    if (Result.Val)
+    if (Result.getNode())
       return Result;
   }
 
@@ -3059,7 +3059,7 @@
     TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align,
                                 AlwaysInline,
                                 DstSV, DstSVOff, SrcSV, SrcSVOff);
-  if (Result.Val)
+  if (Result.getNode())
     return Result;
 
   // If we really need inline code and the target declined to provide it,
@@ -3103,7 +3103,7 @@
     SDValue Result =
       getMemmoveLoadsAndStores(*this, Chain, Dst, Src, ConstantSize->getValue(),
                                Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff);
-    if (Result.Val)
+    if (Result.getNode())
       return Result;
   }
 
@@ -3112,7 +3112,7 @@
   SDValue Result =
     TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align,
                                  DstSV, DstSVOff, SrcSV, SrcSVOff);
-  if (Result.Val)
+  if (Result.getNode())
     return Result;
 
   // Emit a library call.
@@ -3146,7 +3146,7 @@
     SDValue Result =
       getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getValue(), Align,
                       DstSV, DstSVOff);
-    if (Result.Val)
+    if (Result.getNode())
       return Result;
   }
 
@@ -3155,7 +3155,7 @@
   SDValue Result =
     TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align,
                                 DstSV, DstSVOff);
-  if (Result.Val)
+  if (Result.getNode())
     return Result;
 
   // Emit a library call.
@@ -3737,7 +3737,7 @@
 /// input node is returned.  As a degenerate case, if you specify the same
 /// input operands as the node already has, the input node is returned.
 SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) {
-  SDNode *N = InN.Val;
+  SDNode *N = InN.getNode();
   assert(N->getNumOperands() == 1 && "Update with wrong number of operands");
   
   // Check to see if there is no change.
@@ -3756,7 +3756,7 @@
   N->OperandList[0].getVal()->removeUser(0, N);
   N->OperandList[0] = Op;
   N->OperandList[0].setUser(N);
-  Op.Val->addUser(0, N);
+  Op.getNode()->addUser(0, N);
   
   // If this gets put into a CSE map, add it.
   if (InsertPos) CSEMap.InsertNode(N, InsertPos);
@@ -3765,7 +3765,7 @@
 
 SDValue SelectionDAG::
 UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) {
-  SDNode *N = InN.Val;
+  SDNode *N = InN.getNode();
   assert(N->getNumOperands() == 2 && "Update with wrong number of operands");
   
   // Check to see if there is no change.
@@ -3786,13 +3786,13 @@
     N->OperandList[0].getVal()->removeUser(0, N);
     N->OperandList[0] = Op1;
     N->OperandList[0].setUser(N);
-    Op1.Val->addUser(0, N);
+    Op1.getNode()->addUser(0, N);
   }
   if (N->OperandList[1] != Op2) {
     N->OperandList[1].getVal()->removeUser(1, N);
     N->OperandList[1] = Op2;
     N->OperandList[1].setUser(N);
-    Op2.Val->addUser(1, N);
+    Op2.getNode()->addUser(1, N);
   }
   
   // If this gets put into a CSE map, add it.
@@ -3822,7 +3822,7 @@
 
 SDValue SelectionDAG::
 UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) {
-  SDNode *N = InN.Val;
+  SDNode *N = InN.getNode();
   assert(N->getNumOperands() == NumOps &&
          "Update with wrong number of operands");
   
@@ -3853,7 +3853,7 @@
       N->OperandList[i].getVal()->removeUser(i, N);
       N->OperandList[i] = Ops[i];
       N->OperandList[i].setUser(N);
-      Ops[i].Val->addUser(i, N);
+      Ops[i].getNode()->addUser(i, N);
     }
   }
 
@@ -4134,70 +4134,70 @@
 /// node of the specified opcode and operands, it returns that node instead of
 /// the current one.
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) {
-  return getNode(~Opcode, VT).Val;
+  return getNode(~Opcode, VT).getNode();
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) {
-  return getNode(~Opcode, VT, Op1).Val;
+  return getNode(~Opcode, VT, Op1).getNode();
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
                                     SDValue Op1, SDValue Op2) {
-  return getNode(~Opcode, VT, Op1, Op2).Val;
+  return getNode(~Opcode, VT, Op1, Op2).getNode();
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
                                     SDValue Op1, SDValue Op2,
                                     SDValue Op3) {
-  return getNode(~Opcode, VT, Op1, Op2, Op3).Val;
+  return getNode(~Opcode, VT, Op1, Op2, Op3).getNode();
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
                                     const SDValue *Ops, unsigned NumOps) {
-  return getNode(~Opcode, VT, Ops, NumOps).Val;
+  return getNode(~Opcode, VT, Ops, NumOps).getNode();
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2);
   SDValue Op;
-  return getNode(~Opcode, VTs, 2, &Op, 0).Val;
+  return getNode(~Opcode, VTs, 2, &Op, 0).getNode();
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
                                     MVT VT2, SDValue Op1) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2);
-  return getNode(~Opcode, VTs, 2, &Op1, 1).Val;
+  return getNode(~Opcode, VTs, 2, &Op1, 1).getNode();
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
                                     MVT VT2, SDValue Op1,
                                     SDValue Op2) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2);
   SDValue Ops[] = { Op1, Op2 };
-  return getNode(~Opcode, VTs, 2, Ops, 2).Val;
+  return getNode(~Opcode, VTs, 2, Ops, 2).getNode();
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
                                     MVT VT2, SDValue Op1,
                                     SDValue Op2, SDValue Op3) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2);
   SDValue Ops[] = { Op1, Op2, Op3 };
-  return getNode(~Opcode, VTs, 2, Ops, 3).Val;
+  return getNode(~Opcode, VTs, 2, Ops, 3).getNode();
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
                                     const SDValue *Ops, unsigned NumOps) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2);
-  return getNode(~Opcode, VTs, 2, Ops, NumOps).Val;
+  return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode();
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
                                     SDValue Op1, SDValue Op2) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
   SDValue Ops[] = { Op1, Op2 };
-  return getNode(~Opcode, VTs, 3, Ops, 2).Val;
+  return getNode(~Opcode, VTs, 3, Ops, 2).getNode();
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
                                     SDValue Op1, SDValue Op2,
                                     SDValue Op3) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
   SDValue Ops[] = { Op1, Op2, Op3 };
-  return getNode(~Opcode, VTs, 3, Ops, 3).Val;
+  return getNode(~Opcode, VTs, 3, Ops, 3).getNode();
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
                                     const SDValue *Ops, unsigned NumOps) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
-  return getNode(~Opcode, VTs, 3, Ops, NumOps).Val;
+  return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
                                     MVT VT2, MVT VT3, MVT VT4,
@@ -4208,14 +4208,14 @@
   VTList.push_back(VT3);
   VTList.push_back(VT4);
   const MVT *VTs = getNodeValueTypes(VTList);
-  return getNode(~Opcode, VTs, 4, Ops, NumOps).Val;
+  return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode();
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
                                     const std::vector<MVT> &ResultTys,
                                     const SDValue *Ops, unsigned NumOps) {
   const MVT *VTs = getNodeValueTypes(ResultTys);
   return getNode(~Opcode, VTs, ResultTys.size(),
-                 Ops, NumOps).Val;
+                 Ops, NumOps).getNode();
 }
 
 /// getNodeIfExists - Get the specified node if it's already available, or
@@ -4240,10 +4240,10 @@
 ///
 void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To,
                                       DAGUpdateListener *UpdateListener) {
-  SDNode *From = FromN.Val;
+  SDNode *From = FromN.getNode();
   assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 
          "Cannot replace with this method!");
-  assert(From != To.Val && "Cannot replace uses of with self");
+  assert(From != To.getNode() && "Cannot replace uses of with self");
 
   while (!From->use_empty()) {
     SDNode::use_iterator UI = From->use_begin();
@@ -4258,7 +4258,7 @@
         From->removeUser(operandNum, U);
         *I = To;
         I->setUser(U);
-        To.Val->addUser(operandNum, U);
+        To.getNode()->addUser(operandNum, U);
       }    
 
     // Now that we have modified U, add it back to the CSE maps.  If it already
@@ -4305,7 +4305,7 @@
          I != E; ++I, ++operandNum)
       if (I->getVal() == From) {
         From->removeUser(operandNum, U);
-        I->getVal() = To;
+        I->getSDValue().setNode(To);
         To->addUser(operandNum, U);
       }
 
@@ -4351,7 +4351,7 @@
         From->removeUser(operandNum, U);
         *I = ToOp;
         I->setUser(U);
-        ToOp.Val->addUser(operandNum, U);
+        ToOp.getNode()->addUser(operandNum, U);
       }
 
     // Now that we have modified U, add it back to the CSE maps.  If it already
@@ -4372,7 +4372,7 @@
 }
 
 /// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving
-/// uses of other values produced by From.Val alone.  The Deleted vector is
+/// uses of other values produced by From.getVal() alone.  The Deleted vector is
 /// handled the same way as for ReplaceAllUsesWith.
 void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To,
                                              DAGUpdateListener *UpdateListener){
@@ -4380,14 +4380,14 @@
   if (From == To) return;
 
   // Handle the simple, trivial, case efficiently.
-  if (From.Val->getNumValues() == 1) {
+  if (From.getNode()->getNumValues() == 1) {
     ReplaceAllUsesWith(From, To, UpdateListener);
     return;
   }
 
-  // Get all of the users of From.Val.  We want these in a nice,
+  // Get all of the users of From.getNode().  We want these in a nice,
   // deterministically ordered and uniqued set, so we use a SmallSetVector.
-  SmallSetVector<SDNode*, 16> Users(From.Val->use_begin(), From.Val->use_end());
+  SmallSetVector<SDNode*, 16> Users(From.getNode()->use_begin(), From.getNode()->use_end());
 
   while (!Users.empty()) {
     // We know that this user uses some value of From.  If it is the right
@@ -4410,10 +4410,10 @@
     // Update all operands that match "From" in case there are multiple uses.
     for (; Op != E; ++Op) {
       if (*Op == From) {
-        From.Val->removeUser(Op-User->op_begin(), User);
+        From.getNode()->removeUser(Op-User->op_begin(), User);
         *Op = To;
         Op->setUser(User);
-        To.Val->addUser(Op-User->op_begin(), User);
+        To.getNode()->addUser(Op-User->op_begin(), User);
       }
     }
                
@@ -4437,7 +4437,7 @@
 }
 
 /// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving
-/// uses of other values produced by From.Val alone.  The same value may
+/// uses of other values produced by From.getVal() alone.  The same value may
 /// appear in both the From and To list.  The Deleted vector is
 /// handled the same way as for ReplaceAllUsesWith.
 void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From,
@@ -4450,8 +4450,8 @@
 
   SmallVector<std::pair<SDNode *, unsigned>, 16> Users;
   for (unsigned i = 0; i != Num; ++i)
-    for (SDNode::use_iterator UI = From[i].Val->use_begin(), 
-         E = From[i].Val->use_end(); UI != E; ++UI)
+    for (SDNode::use_iterator UI = From[i].getNode()->use_begin(), 
+         E = From[i].getNode()->use_end(); UI != E; ++UI)
       Users.push_back(std::make_pair(*UI, i));
 
   while (!Users.empty()) {
@@ -4476,10 +4476,10 @@
     // Update all operands that match "From" in case there are multiple uses.
     for (; Op != E; ++Op) {
       if (*Op == From[i]) {
-        From[i].Val->removeUser(Op-User->op_begin(), User);
+        From[i].getNode()->removeUser(Op-User->op_begin(), User);
         *Op = To[i];
         Op->setUser(User);
-        To[i].Val->addUser(Op-User->op_begin(), User);
+        To[i].getNode()->addUser(Op-User->op_begin(), User);
       }
     }
                
@@ -4617,7 +4617,7 @@
   
   // Check if the memory reference references a frame index
   const FrameIndexSDNode *FI = 
-  dyn_cast<const FrameIndexSDNode>(getBasePtr().Val);
+  dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode());
   if (!getSrcValue() && FI)
     return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()),
                              Flags, 0, Size, getAlignment());
@@ -4746,7 +4746,7 @@
     return;
 
   for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) {
-    SDNode *Op = N->getOperand(i).Val;
+    SDNode *Op = N->getOperand(i).getNode();
     if (Op == P) {
       found = true;
       return;
@@ -5115,13 +5115,13 @@
   OS << " ";
   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     if (i) OS << ", ";
-    OS << (void*)getOperand(i).Val;
+    OS << (void*)getOperand(i).getNode();
     if (unsigned RN = getOperand(i).getResNo())
       OS << ":" << RN;
   }
 
   if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) {
-    SDNode *Mask = getOperand(2).Val;
+    SDNode *Mask = getOperand(2).getNode();
     OS << "<";
     for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) {
       if (i) OS << ",";
@@ -5262,11 +5262,11 @@
 
 static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) {
   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-    if (N->getOperand(i).Val->hasOneUse())
-      DumpNodes(N->getOperand(i).Val, indent+2, G);
+    if (N->getOperand(i).getNode()->hasOneUse())
+      DumpNodes(N->getOperand(i).getNode(), indent+2, G);
     else
       cerr << "\n" << std::string(indent+2, ' ')
-           << (void*)N->getOperand(i).Val << ": <multiple use>";
+           << (void*)N->getOperand(i).getNode() << ": <multiple use>";
 
 
   cerr << "\n" << std::string(indent, ' ');
@@ -5279,11 +5279,11 @@
   for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end();
        I != E; ++I) {
     const SDNode *N = I;
-    if (!N->hasOneUse() && N != getRoot().Val)
+    if (!N->hasOneUse() && N != getRoot().getNode())
       DumpNodes(N, 2, this);
   }
 
-  if (getRoot().Val) DumpNodes(getRoot().Val, 2, this);
+  if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this);
 
   cerr << "\n\n";
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Aug 28 16:40:38 2008
@@ -784,8 +784,8 @@
     if (Root.getOpcode() != ISD::EntryToken) {
       unsigned i = 0, e = PendingExports.size();
       for (; i != e; ++i) {
-        assert(PendingExports[i].Val->getNumOperands() > 1);
-        if (PendingExports[i].Val->getOperand(0) == Root)
+        assert(PendingExports[i].getNode()->getNumOperands() > 1);
+        if (PendingExports[i].getNode()->getOperand(0) == Root)
           break;  // Don't add the root if we already indirectly depend on it.
       }
         
@@ -824,7 +824,7 @@
 
   void setValue(const Value *V, SDValue NewN) {
     SDValue &N = NodeMap[V];
-    assert(N.Val == 0 && "Already set a value for this node!");
+    assert(N.getNode() == 0 && "Already set a value for this node!");
     N = NewN;
   }
   
@@ -1286,7 +1286,7 @@
 
 SDValue SelectionDAGLowering::getValue(const Value *V) {
   SDValue &N = NodeMap[V];
-  if (N.Val) return N;
+  if (N.getNode()) return N;
   
   if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
     MVT VT = TLI.getValueType(V->getType(), true);
@@ -1310,7 +1310,7 @@
     if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
       visit(CE->getOpcode(), *CE);
       SDValue N1 = NodeMap[V];
-      assert(N1.Val && "visit didn't populate the ValueMap!");
+      assert(N1.getNode() && "visit didn't populate the ValueMap!");
       return N1;
     }
     
@@ -1318,7 +1318,7 @@
       SmallVector<SDValue, 4> Constants;
       for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
            OI != OE; ++OI) {
-        SDNode *Val = getValue(*OI).Val;
+        SDNode *Val = getValue(*OI).getNode();
         for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
           Constants.push_back(SDValue(Val, i));
       }
@@ -1428,7 +1428,7 @@
       else if (F->paramHasAttr(0, ParamAttr::ZExt))
         ExtendKind = ISD::ZERO_EXTEND;
 
-      getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.getResNo() + j),
+      getCopyToParts(DAG, SDValue(RetOp.getNode(), RetOp.getResNo() + j),
                      &Parts[0], NumParts, PartVT, ExtendKind);
 
       for (unsigned i = 0; i < NumParts; ++i) {
@@ -2855,15 +2855,15 @@
   // Copy the beginning value(s) from the original aggregate.
   for (; i != LinearIndex; ++i)
     Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
-                SDValue(Agg.Val, Agg.getResNo() + i);
+                SDValue(Agg.getNode(), Agg.getResNo() + i);
   // Copy values from the inserted value(s).
   for (; i != LinearIndex + NumValValues; ++i)
     Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
-                SDValue(Val.Val, Val.getResNo() + i - LinearIndex);
+                SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
   // Copy remaining value(s) from the original aggregate.
   for (; i != NumAggValues; ++i)
     Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
-                SDValue(Agg.Val, Agg.getResNo() + i);
+                SDValue(Agg.getNode(), Agg.getResNo() + i);
 
   setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
                                   &Values[0], NumAggValues));
@@ -2888,8 +2888,8 @@
   // Copy out the selected value(s).
   for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
     Values[i - LinearIndex] =
-      OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.getResNo() + i)) :
-                   SDValue(Agg.Val, Agg.getResNo() + i);
+      OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.getNode()->getValueType(Agg.getResNo() + i)) :
+                   SDValue(Agg.getNode(), Agg.getResNo() + i);
 
   setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
                                   &Values[0], NumValValues));
@@ -3084,7 +3084,7 @@
   bool isVolatile = I.isVolatile();
   unsigned Alignment = I.getAlignment();
   for (unsigned i = 0; i != NumValues; ++i)
-    Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.getResNo() + i),
+    Chains[i] = DAG.getStore(Root, SDValue(Src.getNode(), Src.getResNo() + i),
                              DAG.getNode(ISD::ADD, PtrVT, Ptr,
                                          DAG.getConstant(Offsets[i], PtrVT)),
                              PtrV, Offsets[i],
@@ -3154,7 +3154,7 @@
                          &Ops[0], Ops.size());
 
   if (HasChain) {
-    SDValue Chain = Result.getValue(Result.Val->getNumValues()-1);
+    SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
     if (OnlyLoad)
       PendingLoads.push_back(Chain);
     else
@@ -3621,7 +3621,7 @@
       Value *Alloca = I.getOperand(1);
       Constant *TypeMap = cast<Constant>(I.getOperand(2));
       
-      FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
+      FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
       GFI->addStackRoot(FI->getIndex(), TypeMap);
     }
     return 0;
@@ -4751,7 +4751,7 @@
   
   // Finish up input operands.
   AsmNodeOperands[0] = Chain;
-  if (Flag.Val) AsmNodeOperands.push_back(Flag);
+  if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
   
   Chain = DAG.getNode(ISD::INLINEASM, 
                       DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
@@ -4770,7 +4770,7 @@
     // bit_convert.
     if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
       for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
-        if (Val.Val->getValueType(i).isVector())
+        if (Val.getNode()->getValueType(i).isVector())
           Val = DAG.getNode(ISD::BIT_CONVERT,
                             TLI.getValueType(ResSTy->getElementType(i)), Val);
       }
@@ -4963,7 +4963,7 @@
   // Create the node.
   SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
                                DAG.getVTList(&RetVals[0], RetVals.size()),
-                               &Ops[0], Ops.size()).Val;
+                               &Ops[0], Ops.size()).getNode();
   
   // Prelower FORMAL_ARGUMENTS.  This isn't required for functionality, but
   // allows exposing the loads that may be part of the argument access to the
@@ -4972,18 +4972,18 @@
   
   // The number of results should match up, except that the lowered one may have
   // an extra flag result.
-  assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
-          (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
+  assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
+          (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
            TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
          && "Lowering produced unexpected number of results!");
 
   // The FORMAL_ARGUMENTS node itself is likely no longer needed.
-  if (Result != TmpRes.Val && Result->use_empty()) {
+  if (Result != TmpRes.getNode() && Result->use_empty()) {
     HandleSDNode Dummy(DAG.getRoot());
     DAG.RemoveDeadNode(Result);
   }
 
-  Result = TmpRes.Val;
+  Result = TmpRes.getNode();
   
   unsigned NumArgRegs = Result->getNumValues() - 1;
   DAG.setRoot(SDValue(Result, NumArgRegs));
@@ -5044,7 +5044,7 @@
          Value != NumValues; ++Value) {
       MVT VT = ValueVTs[Value];
       const Type *ArgTy = VT.getTypeForMVT();
-      SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.getResNo() + Value);
+      SDValue Op = SDValue(Args[i].Node.getNode(), Args[i].Node.getResNo() + Value);
       ISD::ArgFlagsTy Flags;
       unsigned OriginalAlignment =
         getTargetData()->getABITypeAlignment(ArgTy);
@@ -5333,7 +5333,7 @@
 
   // Find RET node.
   if (Terminator.getOpcode() == ISD::RET) {
-    Ret = Terminator.Val;
+    Ret = Terminator.getNode();
   }
  
   // Fix tail call attribute of CALL nodes.
@@ -5355,8 +5355,8 @@
         // Not eligible. Mark CALL node as non tail call.
         SmallVector<SDValue, 32> Ops;
         unsigned idx=0;
-        for(SDNode::op_iterator I =OpCall.Val->op_begin(),
-              E = OpCall.Val->op_end(); I != E; I++, idx++) {
+        for(SDNode::op_iterator I =OpCall.getNode()->op_begin(),
+              E = OpCall.getNode()->op_end(); I != E; I++, idx++) {
           if (idx!=3)
             Ops.push_back(*I);
           else
@@ -5369,8 +5369,8 @@
         SmallVector<SDValue, 32> Ops;
         SDValue Chain = OpCall.getOperand(0), InFlag;
         unsigned idx=0;
-        for(SDNode::op_iterator I = OpCall.Val->op_begin(),
-              E = OpCall.Val->op_end(); I != E; I++, idx++) {
+        for(SDNode::op_iterator I = OpCall.getNode()->op_begin(),
+              E = OpCall.getNode()->op_end(); I != E; I++, idx++) {
           SDValue Arg = *I;
           if (idx > 4 && (idx % 2)) {
             bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
@@ -5557,7 +5557,7 @@
   SmallPtrSet<SDNode*, 128> VisitedNodes;
   SmallVector<SDNode*, 128> Worklist;
   
-  Worklist.push_back(CurDAG->getRoot().Val);
+  Worklist.push_back(CurDAG->getRoot().getNode());
   
   APInt Mask;
   APInt KnownZero;
@@ -5574,7 +5574,7 @@
     // Otherwise, add all chain operands to the worklist.
     for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
       if (N->getOperand(i).getValueType() == MVT::Other)
-        Worklist.push_back(N->getOperand(i).Val);
+        Worklist.push_back(N->getOperand(i).getNode());
     
     // If this is a CopyToReg with a vreg dest, process it.
     if (N->getOpcode() != ISD::CopyToReg)

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Thu Aug 28 16:40:38 2008
@@ -109,8 +109,8 @@
     static void addCustomGraphFeatures(SelectionDAG *G,
                                        GraphWriter<SelectionDAG*> &GW) {
       GW.emitSimpleNode(0, "plaintext=circle", "GraphRoot");
-      if (G->getRoot().Val)
-        GW.emitEdge(0, -1, G->getRoot().Val, G->getRoot().getResNo(),
+      if (G->getRoot().getNode())
+        GW.emitEdge(0, -1, G->getRoot().getNode(), G->getRoot().getResNo(),
                     "color=blue,style=dashed");
     }
   };
@@ -356,7 +356,7 @@
     static void addCustomGraphFeatures(ScheduleDAG *G,
                                        GraphWriter<ScheduleDAG*> &GW) {
       GW.emitSimpleNode(0, "plaintext=circle", "GraphRoot");
-      const SDNode *N = G->DAG.getRoot().Val;
+      const SDNode *N = G->DAG.getRoot().getNode();
       if (N && N->getNodeId() != -1)
         GW.emitEdge(0, -1, &G->SUnits[N->getNodeId()], -1,
                     "color=blue,style=dashed");

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Aug 28 16:40:38 2008
@@ -674,7 +674,7 @@
   KnownZero = KnownOne = APInt(BitWidth, 0);
 
   // Other users may use these bits.
-  if (!Op.Val->hasOneUse()) { 
+  if (!Op.getNode()->hasOneUse()) { 
     if (Depth != 0) {
       // If not at the root, Just compute the KnownZero/KnownOne bits to 
       // simplify things downstream.
@@ -1131,7 +1131,7 @@
     
     // If the input is only used by this truncate, see if we can shrink it based
     // on the known demanded bits.
-    if (Op.getOperand(0).Val->hasOneUse()) {
+    if (Op.getOperand(0).getNode()->hasOneUse()) {
       SDValue In = Op.getOperand(0);
       unsigned InBitWidth = In.getValueSizeInBits();
       switch (In.getOpcode()) {
@@ -1259,9 +1259,9 @@
   case ISD::SETTRUE2:  return DAG.getConstant(1, VT);
   }
 
-  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
+  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
     const APInt &C1 = N1C->getAPIntValue();
-    if (isa<ConstantSDNode>(N0.Val)) {
+    if (isa<ConstantSDNode>(N0.getNode())) {
       return DAG.FoldSetCC(VT, N0, N1, Cond);
     } else {
       // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
@@ -1356,7 +1356,7 @@
                                DAG.getConstant(Imm, Op0Ty));
         }
         if (!DCI.isCalledByLegalizer())
-          DCI.AddToWorklist(ZextOp.Val);
+          DCI.AddToWorklist(ZextOp.getNode());
         // Otherwise, make this a use of a zext.
         return DAG.getSetCC(VT, ZextOp, 
                             DAG.getConstant(C1 & APInt::getLowBitsSet(
@@ -1493,16 +1493,16 @@
           }
         }
     }
-  } else if (isa<ConstantSDNode>(N0.Val)) {
+  } else if (isa<ConstantSDNode>(N0.getNode())) {
       // Ensure that the constant occurs on the RHS.
     return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
   }
 
-  if (isa<ConstantFPSDNode>(N0.Val)) {
+  if (isa<ConstantFPSDNode>(N0.getNode())) {
     // Constant fold or commute setcc.
     SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond);    
-    if (O.Val) return O;
-  } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.Val)) {
+    if (O.getNode()) return O;
+  } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
     // If the RHS of an FP comparison is a constant, simplify it away in
     // some cases.
     if (CFP->getValueAPF().isNaN()) {
@@ -1564,7 +1564,7 @@
       if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
         if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
           // Turn (X+C1) == C2 --> X == C2-C1
-          if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
+          if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
             return DAG.getSetCC(VT, N0.getOperand(0),
                               DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
                                 N0.getValueType()), Cond);
@@ -1585,7 +1585,7 @@
         
         // Turn (C1-X) == C2 --> X == C1-C2
         if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
-          if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
+          if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
             return
               DAG.getSetCC(VT, N0.getOperand(1),
                            DAG.getConstant(SUBC->getAPIntValue() -
@@ -1604,14 +1604,14 @@
         if (DAG.isCommutativeBinOp(N0.getOpcode()))
           return DAG.getSetCC(VT, N0.getOperand(0),
                           DAG.getConstant(0, N0.getValueType()), Cond);
-        else if (N0.Val->hasOneUse()) {
+        else if (N0.getNode()->hasOneUse()) {
           assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
           // (Z-X) == X  --> Z == X<<1
           SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(),
                                      N1, 
                                      DAG.getConstant(1, getShiftAmountTy()));
           if (!DCI.isCalledByLegalizer())
-            DCI.AddToWorklist(SH.Val);
+            DCI.AddToWorklist(SH.getNode());
           return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
         }
       }
@@ -1627,13 +1627,13 @@
         if (DAG.isCommutativeBinOp(N1.getOpcode())) {
           return DAG.getSetCC(VT, N1.getOperand(0),
                           DAG.getConstant(0, N1.getValueType()), Cond);
-        } else if (N1.Val->hasOneUse()) {
+        } else if (N1.getNode()->hasOneUse()) {
           assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
           // X == (Z-X)  --> X<<1 == Z
           SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 
                                      DAG.getConstant(1, getShiftAmountTy()));
           if (!DCI.isCalledByLegalizer())
-            DCI.AddToWorklist(SH.Val);
+            DCI.AddToWorklist(SH.getNode());
           return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
         }
       }
@@ -1649,7 +1649,7 @@
       Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
       N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
       if (!DCI.isCalledByLegalizer())
-        DCI.AddToWorklist(Temp.Val);
+        DCI.AddToWorklist(Temp.getNode());
       break;
     case ISD::SETNE:  // X != Y   -->  (X^Y)
       N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
@@ -1659,21 +1659,21 @@
       Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
       N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
       if (!DCI.isCalledByLegalizer())
-        DCI.AddToWorklist(Temp.Val);
+        DCI.AddToWorklist(Temp.getNode());
       break;
     case ISD::SETLT:  // X <s Y   --> X == 1 & Y == 0  -->  Y^1 & X
     case ISD::SETUGT: // X >u Y   --> X == 1 & Y == 0  -->  Y^1 & X
       Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
       N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
       if (!DCI.isCalledByLegalizer())
-        DCI.AddToWorklist(Temp.Val);
+        DCI.AddToWorklist(Temp.getNode());
       break;
     case ISD::SETULE: // X <=u Y  --> X == 0 | Y == 1  -->  X^1 | Y
     case ISD::SETGE:  // X >=s Y  --> X == 0 | Y == 1  -->  X^1 | Y
       Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
       N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
       if (!DCI.isCalledByLegalizer())
-        DCI.AddToWorklist(Temp.Val);
+        DCI.AddToWorklist(Temp.getNode());
       break;
     case ISD::SETUGE: // X >=u Y  --> X == 1 | Y == 0  -->  Y^1 | X
     case ISD::SETLE:  // X <=s Y  --> X == 1 | Y == 0  -->  Y^1 | X
@@ -1683,7 +1683,7 @@
     }
     if (VT != MVT::i1) {
       if (!DCI.isCalledByLegalizer())
-        DCI.AddToWorklist(N0.Val);
+        DCI.AddToWorklist(N0.getNode());
       // FIXME: If running after legalize, we probably can't do this.
       N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
     }
@@ -1708,13 +1708,13 @@
   if (N->getOpcode() == ISD::ADD) {
     SDValue N1 = N->getOperand(0);
     SDValue N2 = N->getOperand(1);
-    if (isGAPlusOffset(N1.Val, GA, Offset)) {
+    if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
       ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
       if (V) {
         Offset += V->getSignExtended();
         return true;
       }
-    } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
+    } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
       ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
       if (V) {
         Offset += V->getSignExtended();
@@ -1732,7 +1732,7 @@
 bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base,
                                        unsigned Bytes, int Dist,
                                        const MachineFrameInfo *MFI) const {
-  if (LD->getOperand(0).Val != Base->getOperand(0).Val)
+  if (LD->getOperand(0).getNode() != Base->getOperand(0).getNode())
     return false;
   MVT VT = LD->getValueType(0);
   if (VT.getSizeInBits() / 8 != Bytes)
@@ -1755,8 +1755,8 @@
   GlobalValue *GV2 = NULL;
   int64_t Offset1 = 0;
   int64_t Offset2 = 0;
-  bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
-  bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
+  bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1);
+  bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
   if (isGA1 && isGA2 && GV1 == GV2)
     return Offset1 == (Offset2 + Dist*Bytes);
   return false;
@@ -1979,7 +1979,7 @@
     // For example, on X86 we might have an 'rI' constraint.  If the operand
     // is an integer in the range [0..31] we want to use I (saving a load
     // of a register), otherwise we must use 'r'.
-    if (CType == TargetLowering::C_Other && Op.Val) {
+    if (CType == TargetLowering::C_Other && Op.getNode()) {
       assert(OpInfo.Codes[i].size() == 1 &&
              "Unhandled multi-letter 'other' constraint");
       std::vector<SDValue> ResultOps;
@@ -2273,34 +2273,34 @@
   else if (isOperationLegal(ISD::SMUL_LOHI, VT))
     Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT),
                               N->getOperand(0),
-                              DAG.getConstant(magics.m, VT)).Val, 1);
+                              DAG.getConstant(magics.m, VT)).getNode(), 1);
   else
     return SDValue();       // No mulhs or equvialent
   // If d > 0 and m < 0, add the numerator
   if (d > 0 && magics.m < 0) { 
     Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
     if (Created)
-      Created->push_back(Q.Val);
+      Created->push_back(Q.getNode());
   }
   // If d < 0 and m > 0, subtract the numerator.
   if (d < 0 && magics.m > 0) {
     Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
     if (Created)
-      Created->push_back(Q.Val);
+      Created->push_back(Q.getNode());
   }
   // Shift right algebraic if shift value is nonzero
   if (magics.s > 0) {
     Q = DAG.getNode(ISD::SRA, VT, Q, 
                     DAG.getConstant(magics.s, getShiftAmountTy()));
     if (Created)
-      Created->push_back(Q.Val);
+      Created->push_back(Q.getNode());
   }
   // Extract the sign bit and add it to the quotient
   SDValue T =
     DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
                                                  getShiftAmountTy()));
   if (Created)
-    Created->push_back(T.Val);
+    Created->push_back(T.getNode());
   return DAG.getNode(ISD::ADD, VT, Q, T);
 }
 
@@ -2327,11 +2327,11 @@
   else if (isOperationLegal(ISD::UMUL_LOHI, VT))
     Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT),
                               N->getOperand(0),
-                              DAG.getConstant(magics.m, VT)).Val, 1);
+                              DAG.getConstant(magics.m, VT)).getNode(), 1);
   else
     return SDValue();       // No mulhu or equvialent
   if (Created)
-    Created->push_back(Q.Val);
+    Created->push_back(Q.getNode());
 
   if (magics.a == 0) {
     return DAG.getNode(ISD::SRL, VT, Q, 
@@ -2339,14 +2339,14 @@
   } else {
     SDValue NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
     if (Created)
-      Created->push_back(NPQ.Val);
+      Created->push_back(NPQ.getNode());
     NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 
                       DAG.getConstant(1, getShiftAmountTy()));
     if (Created)
-      Created->push_back(NPQ.Val);
+      Created->push_back(NPQ.getNode());
     NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
     if (Created)
-      Created->push_back(NPQ.Val);
+      Created->push_back(NPQ.getNode());
     return DAG.getNode(ISD::SRL, VT, NPQ, 
                        DAG.getConstant(magics.s-1, getShiftAmountTy()));
   }

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Aug 28 16:40:38 2008
@@ -529,7 +529,7 @@
 
 
 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
-  SDNode *N = Op.Val;
+  SDNode *N = Op.getNode();
 
   if (N->isMachineOpcode())
     return NULL;   // Already selected.
@@ -729,11 +729,11 @@
     SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
     SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other, MVT::Flag, Ops, 5);
     Chain = SDValue(ResNode, 0);
-    if (Op.Val->getNumValues() == 2) {
+    if (Op.getNode()->getNumValues() == 2) {
       InFlag = SDValue(ResNode, 1);
-      ReplaceUses(SDValue(Op.Val, 1), InFlag);
+      ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
     }
-    ReplaceUses(SDValue(Op.Val, 0), SDValue(Chain.Val, Chain.getResNo()));
+    ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
     return NULL;
   }
   case ARMISD::CMOV: {
@@ -763,7 +763,7 @@
       SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
                                cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
       SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
-      return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCs, MVT::i32, Ops, 7);
+      return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs, MVT::i32, Ops, 7);
     }
 
     // Pattern: (ARMcmov:i32 GPR:i32:$false,
@@ -774,16 +774,16 @@
     // Pattern complexity = 10  cost = 1  size = 0
     if (VT == MVT::i32 &&
         N3.getOpcode() == ISD::Constant &&
-        Predicate_so_imm(N3.Val)) {
+        Predicate_so_imm(N3.getNode())) {
       AddToISelQueue(N0);
       AddToISelQueue(InFlag);
       SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
                                cast<ConstantSDNode>(N1)->getValue()), MVT::i32);
-      Tmp1 = Transform_so_imm_XFORM(Tmp1.Val);
+      Tmp1 = Transform_so_imm_XFORM(Tmp1.getNode());
       SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
                                cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
       SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
-      return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCi, MVT::i32, Ops, 5);
+      return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCi, MVT::i32, Ops, 5);
     }
 
     // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
@@ -815,7 +815,7 @@
       Opc = ARM::FCPYDcc;
       break; 
     }
-    return CurDAG->SelectNodeTo(Op.Val, Opc, VT, Ops, 5);
+    return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
   }
   case ARMISD::CNEG: {
     MVT VT = Op.getValueType();
@@ -844,7 +844,7 @@
       Opc = ARM::FNEGDcc;
       break; 
     }
-    return CurDAG->SelectNodeTo(Op.Val, Opc, VT, Ops, 5);
+    return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
   }
   }
   return SelectCode(Op);

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Aug 28 16:40:38 2008
@@ -400,7 +400,7 @@
 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
 /// nodes.
 SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
-  MVT RetVT= Op.Val->getValueType(0);
+  MVT RetVT= Op.getNode()->getValueType(0);
   SDValue Chain    = Op.getOperand(0);
   unsigned CallConv  = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
   assert((CallConv == CallingConv::C ||
@@ -597,7 +597,7 @@
     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
                                   RegsToPass[i].second.getValueType()));
 
-  if (InFlag.Val)
+  if (InFlag.getNode())
     Ops.push_back(InFlag);
   // Returns a chain and a flag for retval copy to use.
   Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag),
@@ -621,7 +621,7 @@
   case MVT::i32:
     Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
     ResultVals.push_back(Chain.getValue(0));
-    if (Op.Val->getValueType(1) == MVT::i32) {
+    if (Op.getNode()->getValueType(1) == MVT::i32) {
       // Returns a i64 value.
       Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32,
                                  Chain.getValue(2)).getValue(1);
@@ -981,7 +981,7 @@
   unsigned ArgOffset = 0;   // Frame mechanisms handle retaddr slot
   unsigned NumGPRs = 0;     // GPRs used for parameter passing.
 
-  unsigned NumArgs = Op.Val->getNumValues()-1;
+  unsigned NumArgs = Op.getNode()->getNumValues()-1;
   for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
     ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo,
                                              NumGPRs, ArgOffset));
@@ -1029,7 +1029,7 @@
   ArgValues.push_back(Root);
 
   // Return the new list of results.
-  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
+  return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
                             ArgValues.size());
 }
 
@@ -1037,7 +1037,7 @@
 static bool isFloatingPointZero(SDValue Op) {
   if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
     return CFP->getValueAPF().isPosZero();
-  else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
+  else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
     // Maybe this has already been legalized into the constant pool?
     if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
       SDValue WrapperOp = Op.getOperand(1).getOperand(0);
@@ -1058,7 +1058,7 @@
 /// the given operands.
 static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
                            SDValue &ARMCC, SelectionDAG &DAG, bool isThumb) {
-  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) {
+  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
     unsigned C = RHSC->getValue();
     if (!isLegalCmpImmediate(C, isThumb)) {
       // Constant does not fit, try adjusting it by one?
@@ -1362,7 +1362,7 @@
                               &Op, 1);
   
   // Merge the pieces into a single i64 value.
-  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)).Val;
+  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)).getNode();
 }
 
 static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
@@ -1393,7 +1393,7 @@
   Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
   
   // Merge the pieces into a single i64 value.
- return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).Val;
+ return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).getNode();
 }
 
 
@@ -1424,9 +1424,9 @@
       
       
   // FIXME: Remove these when LegalizeDAGTypes lands.
-  case ISD::BIT_CONVERT:   return SDValue(ExpandBIT_CONVERT(Op.Val, DAG), 0);
+  case ISD::BIT_CONVERT:   return SDValue(ExpandBIT_CONVERT(Op.getNode(), DAG), 0);
   case ISD::SRL:
-  case ISD::SRA:           return SDValue(ExpandSRx(Op.Val, DAG,Subtarget),0);
+  case ISD::SRA:           return SDValue(ExpandSRx(Op.getNode(), DAG,Subtarget),0);
   }
   return SDValue();
 }
@@ -1734,7 +1734,7 @@
     return false;
 
   bool isInc;
-  bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad, Base, Offset,
+  bool isLegal = getIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, Offset,
                                         isInc, DAG);
   if (isLegal) {
     AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;

Modified: llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Thu Aug 28 16:40:38 2008
@@ -75,7 +75,7 @@
           Result |= 1 << i;
           if (((Constant >> 8*i) & 0xFF) == 0xFF) {
             // If the entire byte is set, zapnot the byte.
-          } else if (LHS.Val == 0) {
+          } else if (LHS.getNode() == 0) {
             // Otherwise, if the mask was previously validated, we know its okay
             // to zapnot this entire byte even though all the bits aren't set.
           } else {
@@ -242,7 +242,7 @@
 // Select - Convert the specified operand from a target-independent to a
 // target-specific node if it hasn't already been changed.
 SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
-  SDNode *N = Op.Val;
+  SDNode *N = Op.getNode();
   if (N->isMachineOpcode()) {
     return NULL;   // Already selected.
   }
@@ -345,7 +345,7 @@
   }
 
   case ISD::SETCC:
-    if (N->getOperand(0).Val->getValueType(0).isFloatingPoint()) {
+    if (N->getOperand(0).getNode()->getValueType(0).isFloatingPoint()) {
       ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
 
       unsigned Opc = Alpha::WTF;
@@ -460,7 +460,7 @@
 void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
   //TODO: add flag stuff to prevent nondeturministic breakage!
 
-  SDNode *N = Op.Val;
+  SDNode *N = Op.getNode();
   SDValue Chain = N->getOperand(0);
   SDValue Addr = N->getOperand(1);
   SDValue InFlag(0,0);  // Null incoming flag value.

Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Thu Aug 28 16:40:38 2008
@@ -215,7 +215,7 @@
   unsigned args_float[] = {
     Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
   
-  for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
+  for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e; ++ArgNo) {
     SDValue argt;
     MVT ObjectVT = Op.getValue(ArgNo).getValueType();
     SDValue ArgVal;
@@ -255,7 +255,7 @@
   // If the functions takes variable number of arguments, copy all regs to stack
   bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
   if (isVarArg) {
-    VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
+    VarArgsOffset = (Op.getNode()->getNumValues()-1) * 8;
     std::vector<SDValue> LS;
     for (int i = 0; i < 6; ++i) {
       if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
@@ -281,7 +281,7 @@
   ArgValues.push_back(Root);
 
   // Return the new list of results.
-  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
+  return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
                             ArgValues.size());
 }
 
@@ -491,10 +491,10 @@
   case ISD::SREM:
     //Expand only on constant case
     if (Op.getOperand(1).getOpcode() == ISD::Constant) {
-      MVT VT = Op.Val->getValueType(0);
-      SDValue Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
-        BuildUDIV(Op.Val, DAG, NULL) :
-        BuildSDIV(Op.Val, DAG, NULL);
+      MVT VT = Op.getNode()->getValueType(0);
+      SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ?
+        BuildUDIV(Op.getNode(), DAG, NULL) :
+        BuildSDIV(Op.getNode(), DAG, NULL);
       Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
       Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
       return Tmp1;
@@ -504,8 +504,8 @@
   case ISD::UDIV:
     if (Op.getValueType().isInteger()) {
       if (Op.getOperand(1).getOpcode() == ISD::Constant)
-        return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL) 
-          : BuildUDIV(Op.Val, DAG, NULL);
+        return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.getNode(), DAG, NULL) 
+          : BuildUDIV(Op.getNode(), DAG, NULL);
       const char* opstr = 0;
       switch (Op.getOpcode()) {
       case ISD::UREM: opstr = "__remqu"; break;
@@ -522,7 +522,7 @@
 
   case ISD::VAARG: {
     SDValue Chain, DataPtr;
-    LowerVAARG(Op.Val, Chain, DataPtr, DAG);
+    LowerVAARG(Op.getNode(), Chain, DataPtr, DAG);
 
     SDValue Result;
     if (Op.getValueType() == MVT::i32)
@@ -578,7 +578,7 @@
 
   SDValue Chain, DataPtr;
   LowerVAARG(N, Chain, DataPtr, DAG);
-  return DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL, 0).Val;
+  return DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL, 0).getNode();
 }
 
 

Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Thu Aug 28 16:40:38 2008
@@ -579,7 +579,7 @@
  */
 SDNode *
 SPUDAGToDAGISel::Select(SDValue Op) {
-  SDNode *N = Op.Val;
+  SDNode *N = Op.getNode();
   unsigned Opc = N->getOpcode();
   int n_ops = -1;
   unsigned NewOpc;
@@ -669,9 +669,9 @@
       MVT VT = Op.getValueType();
 
       DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = ");
-      DEBUG(Op.getOperand(0).Val->dump(CurDAG));
+      DEBUG(Op.getOperand(0).getNode()->dump(CurDAG));
       DEBUG(cerr << "\nOp1 = ");
-      DEBUG(Op.getOperand(1).Val->dump(CurDAG));
+      DEBUG(Op.getOperand(1).getNode()->dump(CurDAG));
       DEBUG(cerr << "\n");
 
       if (Op1.getOpcode() == ISD::Constant) {

Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Thu Aug 28 16:40:38 2008
@@ -503,7 +503,7 @@
   SDValue chain = LSN->getChain();
 
   if (basePtr.getOpcode() == ISD::ADD) {
-    SDValue Op1 = basePtr.Val->getOperand(1);
+    SDValue Op1 = basePtr.getNode()->getOperand(1);
 
     if (Op1.getOpcode() == ISD::Constant || Op1.getOpcode() == ISD::TargetConstant) {
       const ConstantSDNode *CN = cast<ConstantSDNode>(basePtr.getOperand(1));
@@ -579,7 +579,7 @@
   LoadSDNode *LN = cast<LoadSDNode>(Op);
   SDValue the_chain = LN->getChain();
   MVT VT = LN->getMemoryVT();
-  MVT OpVT = Op.Val->getValueType(0);
+  MVT OpVT = Op.getNode()->getValueType(0);
   ISD::LoadExtType ExtType = LN->getExtensionType();
   unsigned alignment = LN->getAlignment();
   SDValue Ops[8];
@@ -591,7 +591,7 @@
     SDValue result =
       AlignedLoad(Op, DAG, ST, LN,alignment, offset, rotamt, VT, was16aligned);
 
-    if (result.Val == 0)
+    if (result.getNode() == 0)
       return result;
 
     the_chain = result.getValue(1);
@@ -708,7 +708,7 @@
       AlignedLoad(Op, DAG, ST, SN, alignment,
                   chunk_offset, slot_offset, VT, was16aligned);
 
-    if (alignLoadVec.Val == 0)
+    if (alignLoadVec.getNode() == 0)
       return alignLoadVec;
 
     LoadSDNode *LN = cast<LoadSDNode>(alignLoadVec);
@@ -736,7 +736,7 @@
     // Otherwise generate a D-form address with the slot offset relative
     // to the stack pointer, which is always aligned.
     DEBUG(cerr << "CellSPU LowerSTORE: basePtr = ");
-    DEBUG(basePtr.Val->dump(&DAG));
+    DEBUG(basePtr.getNode()->dump(&DAG));
     DEBUG(cerr << "\n");
 
     if (basePtr.getOpcode() == SPUISD::IndirectAddr ||
@@ -859,7 +859,7 @@
 static SDValue
 LowerConstant(SDValue Op, SelectionDAG &DAG) {
   MVT VT = Op.getValueType();
-  ConstantSDNode *CN = cast<ConstantSDNode>(Op.Val);
+  ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode());
 
   if (VT == MVT::i64) {
     SDValue T = DAG.getConstant(CN->getValue(), MVT::i64);
@@ -880,7 +880,7 @@
 static SDValue
 LowerConstantFP(SDValue Op, SelectionDAG &DAG) {
   MVT VT = Op.getValueType();
-  ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.Val);
+  ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.getNode());
 
   assert((FP != 0) &&
          "LowerConstantFP: Node is not ConstantFPSDNode");
@@ -932,7 +932,7 @@
   MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
 
   // Add DAG nodes to load the arguments or copy them out of registers.
-  for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
+  for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e; ++ArgNo) {
     SDValue ArgVal;
     bool needsLoad = false;
     MVT ObjectVT = Op.getValue(ArgNo).getValueType();
@@ -1061,7 +1061,7 @@
   ArgValues.push_back(Root);
 
   // Return the new list of results.
-  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
+  return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
                             ArgValues.size());
 }
 
@@ -1076,7 +1076,7 @@
       (Addr << 14 >> 14) != Addr)
     return 0;  // Top 14 bits have to be sext of immediate.
 
-  return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
+  return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).getNode();
 }
 
 static
@@ -1226,7 +1226,7 @@
     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
                                   RegsToPass[i].second.getValueType()));
 
-  if (InFlag.Val)
+  if (InFlag.getNode())
     Ops.push_back(InFlag);
   // Returns a chain and a flag for retval copy to use.
   Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag),
@@ -1237,18 +1237,18 @@
                              DAG.getConstant(NumStackBytes, PtrVT),
                              DAG.getConstant(0, PtrVT),
                              InFlag);
-  if (Op.Val->getValueType(0) != MVT::Other)
+  if (Op.getNode()->getValueType(0) != MVT::Other)
     InFlag = Chain.getValue(1);
 
   SDValue ResultVals[3];
   unsigned NumResults = 0;
 
   // If the call has results, copy the values out of the ret val registers.
-  switch (Op.Val->getValueType(0).getSimpleVT()) {
+  switch (Op.getNode()->getValueType(0).getSimpleVT()) {
   default: assert(0 && "Unexpected ret value!");
   case MVT::Other: break;
   case MVT::i32:
-    if (Op.Val->getValueType(1) == MVT::i32) {
+    if (Op.getNode()->getValueType(1) == MVT::i32) {
       Chain = DAG.getCopyFromReg(Chain, SPU::R4, MVT::i32, InFlag).getValue(1);
       ResultVals[0] = Chain.getValue(0);
       Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i32,
@@ -1268,7 +1268,7 @@
     break;
   case MVT::f32:
   case MVT::f64:
-    Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.Val->getValueType(0),
+    Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.getNode()->getValueType(0),
                                InFlag).getValue(1);
     ResultVals[0] = Chain.getValue(0);
     NumResults = 1;
@@ -1278,7 +1278,7 @@
   case MVT::v4i32:
   case MVT::v8i16:
   case MVT::v16i8:
-    Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.Val->getValueType(0),
+    Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.getNode()->getValueType(0),
                                    InFlag).getValue(1);
     ResultVals[0] = Chain.getValue(0);
     NumResults = 1;
@@ -1301,7 +1301,7 @@
   unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
   bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
   CCState CCInfo(CC, isVarArg, TM, RVLocs);
-  CCInfo.AnalyzeReturn(Op.Val, RetCC_SPU);
+  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SPU);
 
   // If this is the first return lowered for this function, add the regs to the
   // liveout set for the function.
@@ -1321,7 +1321,7 @@
     Flag = Chain.getValue(1);
   }
 
-  if (Flag.Val)
+  if (Flag.getNode())
     return DAG.getNode(SPUISD::RET_FLAG, MVT::Other, Chain, Flag);
   else
     return DAG.getNode(SPUISD::RET_FLAG, MVT::Other, Chain);
@@ -1339,13 +1339,13 @@
   // Check to see if this buildvec has a single non-undef value in its elements.
   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
     if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
-    if (OpVal.Val == 0)
+    if (OpVal.getNode() == 0)
       OpVal = N->getOperand(i);
     else if (OpVal != N->getOperand(i))
       return 0;
   }
 
-  if (OpVal.Val != 0) {
+  if (OpVal.getNode() != 0) {
     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
       return CN;
     }
@@ -1599,7 +1599,7 @@
   uint64_t UndefBits[2];
   uint64_t SplatBits, SplatUndef;
   int SplatSize;
-  if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)
+  if (GetConstantBuildVectorBits(Op.getNode(), VectorBits, UndefBits)
       || !isConstantSplat(VectorBits, UndefBits,
                           VT.getVectorElementType().getSizeInBits(),
                           SplatBits, SplatUndef, SplatSize))
@@ -1842,11 +1842,11 @@
 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
   SDValue Op0 = Op.getOperand(0);                     // Op0 = the scalar
 
-  if (Op0.Val->getOpcode() == ISD::Constant) {
+  if (Op0.getNode()->getOpcode() == ISD::Constant) {
     // For a constant, build the appropriate constant vector, which will
     // eventually simplify to a vector register load.
 
-    ConstantSDNode *CN = cast<ConstantSDNode>(Op0.Val);
+    ConstantSDNode *CN = cast<ConstantSDNode>(Op0.getNode());
     SmallVector<SDValue, 16> ConstVecValues;
     MVT VT;
     size_t n_copies;
@@ -2447,25 +2447,25 @@
 
   ConstVec = Op.getOperand(0);
   Arg = Op.getOperand(1);
-  if (ConstVec.Val->getOpcode() != ISD::BUILD_VECTOR) {
-    if (ConstVec.Val->getOpcode() == ISD::BIT_CONVERT) {
+  if (ConstVec.getNode()->getOpcode() != ISD::BUILD_VECTOR) {
+    if (ConstVec.getNode()->getOpcode() == ISD::BIT_CONVERT) {
       ConstVec = ConstVec.getOperand(0);
     } else {
       ConstVec = Op.getOperand(1);
       Arg = Op.getOperand(0);
-      if (ConstVec.Val->getOpcode() == ISD::BIT_CONVERT) {
+      if (ConstVec.getNode()->getOpcode() == ISD::BIT_CONVERT) {
         ConstVec = ConstVec.getOperand(0);
       }
     }
   }
 
-  if (ConstVec.Val->getOpcode() == ISD::BUILD_VECTOR) {
+  if (ConstVec.getNode()->getOpcode() == ISD::BUILD_VECTOR) {
     uint64_t VectorBits[2];
     uint64_t UndefBits[2];
     uint64_t SplatBits, SplatUndef;
     int SplatSize;
 
-    if (!GetConstantBuildVectorBits(ConstVec.Val, VectorBits, UndefBits)
+    if (!GetConstantBuildVectorBits(ConstVec.getNode(), VectorBits, UndefBits)
         && isConstantSplat(VectorBits, UndefBits,
                            VT.getVectorElementType().getSizeInBits(),
                            SplatBits, SplatUndef, SplatSize)) {
@@ -2477,7 +2477,7 @@
       for (size_t i = 0; i < tcVecSize; ++i)
         tcVec[i] = tc;
 
-      return DAG.getNode(Op.Val->getOpcode(), VT, Arg,
+      return DAG.getNode(Op.getNode()->getOpcode(), VT, Arg,
                          DAG.getNode(ISD::BUILD_VECTOR, VT, tcVec, tcVecSize));
     }
   }
@@ -2632,8 +2632,8 @@
   default: {
     cerr << "SPUTargetLowering::LowerOperation(): need to lower this!\n";
     cerr << "Op.getOpcode() = " << Opc << "\n";
-    cerr << "*Op.Val:\n";
-    Op.Val->dump();
+    cerr << "*Op.getNode():\n";
+    Op.getNode()->dump();
     abort();
   }
   case ISD::LOAD:
@@ -2796,7 +2796,7 @@
       DEBUG(cerr << "Replace: ");
       DEBUG(N->dump(&DAG));
       DEBUG(cerr << "\nWith:    ");
-      DEBUG(Op0.Val->dump(&DAG));
+      DEBUG(Op0.getNode()->dump(&DAG));
       DEBUG(cerr << "\n");
 
       return Op0;
@@ -2813,7 +2813,7 @@
         DEBUG(cerr << "Replace: ");
         DEBUG(N->dump(&DAG));
         DEBUG(cerr << "\nWith:    ");
-        DEBUG(Op0.Val->dump(&DAG));
+        DEBUG(Op0.getNode()->dump(&DAG));
         DEBUG(cerr << "\n");
 
         return Op0;
@@ -2871,11 +2871,11 @@
   }
   // Otherwise, return unchanged.
 #if 1
-  if (Result.Val) {
+  if (Result.getNode()) {
     DEBUG(cerr << "\nReplace.SPU: ");
     DEBUG(N->dump(&DAG));
     DEBUG(cerr << "\nWith:        ");
-    DEBUG(Result.Val->dump(&DAG));
+    DEBUG(Result.getNode()->dump(&DAG));
     DEBUG(cerr << "\n");
   }
 #endif

Modified: llvm/trunk/lib/Target/CellSPU/SPUOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUOperands.td?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUOperands.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUOperands.td Thu Aug 28 16:40:38 2008
@@ -24,13 +24,13 @@
          && "LO16_vec got something other than a BUILD_VECTOR");
 
   // Get first constant operand...
-  for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) {
+  for (unsigned i = 0, e = N->getNumOperands(); OpVal.getNode() == 0 && i != e; ++i) {
     if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
-    if (OpVal.Val == 0)
+    if (OpVal.getNode() == 0)
       OpVal = N->getOperand(i);
   }
   
-  assert(OpVal.Val != 0 && "LO16_vec did not locate a <defined> node");
+  assert(OpVal.getNode() != 0 && "LO16_vec did not locate a <defined> node");
   ConstantSDNode *CN = cast<ConstantSDNode>(OpVal);
   return getI32Imm((unsigned)CN->getValue() & 0xffff);
 }]>;
@@ -49,13 +49,13 @@
          && "HI16_vec got something other than a BUILD_VECTOR");
   
   // Get first constant operand...
-  for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) {
+  for (unsigned i = 0, e = N->getNumOperands(); OpVal.getNode() == 0 && i != e; ++i) {
     if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
-    if (OpVal.Val == 0)
+    if (OpVal.getNode() == 0)
       OpVal = N->getOperand(i);
   }
   
-  assert(OpVal.Val != 0 && "HI16_vec did not locate a <defined> node");
+  assert(OpVal.getNode() != 0 && "HI16_vec did not locate a <defined> node");
   ConstantSDNode *CN = cast<ConstantSDNode>(OpVal);
   return getI32Imm((unsigned)CN->getValue() >> 16);
 }]>;
@@ -244,7 +244,7 @@
 // incoming constant being a 16-bit quantity, where the upper and lower bytes
 // are EXACTLY the same (e.g., 0x2a2a)
 def v16i8SExt8Imm: PatLeaf<(build_vector), [{
-  return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
+  return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
 }], v16i8SExt8Imm_xform>;
 
 // v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit
@@ -259,7 +259,7 @@
 // incoming constant being a 16-bit quantity, where the upper and lower bytes
 // are EXACTLY the same (e.g., 0x2a2a)
 def v16i8U8Imm: PatLeaf<(build_vector), [{
-  return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
+  return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
 }], v16i8U8Imm_xform>;
 
 // v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign extended
@@ -271,7 +271,7 @@
 // v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate constant
 // load, works in conjunction with its transform function.
 def v8i16SExt8Imm: PatLeaf<(build_vector), [{
-  return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).Val != 0;
+  return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).getNode() != 0;
 }], v8i16SExt8Imm_xform>;
 
 // v8i16SExt10Imm_xform function: convert build_vector to 16-bit sign extended
@@ -283,7 +283,7 @@
 // v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate constant
 // load, works in conjunction with its transform function.
 def v8i16SExt10Imm: PatLeaf<(build_vector), [{
-  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
+  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
 }], v8i16SExt10Imm_xform>;
 
 // v8i16Uns10Imm_xform function: convert build_vector to 16-bit unsigned
@@ -295,7 +295,7 @@
 // v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate constant
 // load, works in conjunction with its transform function.
 def v8i16Uns10Imm: PatLeaf<(build_vector), [{
-  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
+  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
 }], v8i16Uns10Imm_xform>;
 
 // v8i16SExt16Imm_xform function: convert build_vector to 16-bit sign extended
@@ -307,7 +307,7 @@
 // v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate constant
 // load, works in conjunction with its transform function.
 def v8i16SExt16Imm: PatLeaf<(build_vector), [{
-  return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).Val != 0;
+  return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).getNode() != 0;
 }], v8i16Uns16Imm_xform>;
 
 // v4i32SExt10Imm_xform function: convert build_vector to 10-bit sign extended
@@ -319,7 +319,7 @@
 // v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate constant
 // load, works in conjunction with its transform function.
 def v4i32SExt10Imm: PatLeaf<(build_vector), [{
-  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
+  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
 }], v4i32SExt10Imm_xform>;
 
 // v4i32Uns10Imm_xform function: convert build_vector to 10-bit unsigned
@@ -331,7 +331,7 @@
 // v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate constant
 // load, works in conjunction with its transform function.
 def v4i32Uns10Imm: PatLeaf<(build_vector), [{
-  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
+  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
 }], v4i32Uns10Imm_xform>;
 
 // v4i32SExt16Imm_xform function: convert build_vector to 16-bit sign extended
@@ -343,7 +343,7 @@
 // v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate constant
 // load, works in conjunction with its transform function.
 def v4i32SExt16Imm: PatLeaf<(build_vector), [{
-  return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).Val != 0;
+  return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).getNode() != 0;
 }], v4i32SExt16Imm_xform>;
 
 // v4i32Uns18Imm_xform function: convert build_vector to 18-bit unsigned
@@ -355,7 +355,7 @@
 // v4i32Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
 // works in conjunction with its transform function.
 def v4i32Uns18Imm: PatLeaf<(build_vector), [{
-  return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).Val != 0;
+  return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).getNode() != 0;
 }], v4i32Uns18Imm_xform>;
 
 // ILHUvec_get_imm xform function: convert build_vector to ILHUvec imm constant
@@ -366,7 +366,7 @@
 
 /// immILHUvec: Predicate test for a ILHU constant vector.
 def immILHUvec: PatLeaf<(build_vector), [{
-  return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).Val != 0;
+  return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).getNode() != 0;
 }], ILHUvec_get_imm>;
 
 // Catch-all for any other i32 vector constants
@@ -375,7 +375,7 @@
 }]>;
 
 def v4i32Imm: PatLeaf<(build_vector), [{
-  return SPU::get_v4i32_imm(N, *CurDAG).Val != 0;
+  return SPU::get_v4i32_imm(N, *CurDAG).getNode() != 0;
 }], v4i32_get_imm>;
 
 // v2i64SExt10Imm_xform function: convert build_vector to 10-bit sign extended
@@ -387,7 +387,7 @@
 // v2i64SExt10Imm: Predicate test for 10-bit sign extended immediate constant
 // load, works in conjunction with its transform function.
 def v2i64SExt10Imm: PatLeaf<(build_vector), [{
-  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).Val != 0;
+  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).getNode() != 0;
 }], v2i64SExt10Imm_xform>;
 
 // v2i64SExt16Imm_xform function: convert build_vector to 16-bit sign extended
@@ -399,7 +399,7 @@
 // v2i64SExt16Imm: Predicate test for 16-bit sign extended immediate constant
 // load, works in conjunction with its transform function.
 def v2i64SExt16Imm: PatLeaf<(build_vector), [{
-  return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).Val != 0;
+  return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).getNode() != 0;
 }], v2i64SExt16Imm_xform>;
 
 // v2i64Uns18Imm_xform function: convert build_vector to 18-bit unsigned
@@ -411,12 +411,12 @@
 // v2i64Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
 // works in conjunction with its transform function.
 def v2i64Uns18Imm: PatLeaf<(build_vector), [{
-  return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).Val != 0;
+  return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).getNode() != 0;
 }], v2i64Uns18Imm_xform>;
 
 /// immILHUvec: Predicate test for a ILHU constant vector.
 def immILHUvec_i64: PatLeaf<(build_vector), [{
-  return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).Val != 0;
+  return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).getNode() != 0;
 }], ILHUvec_get_imm>;
 
 // Catch-all for any other i32 vector constants
@@ -425,7 +425,7 @@
 }]>;
 
 def v2i64Imm: PatLeaf<(build_vector), [{
-  return SPU::get_v2i64_imm(N, *CurDAG).Val != 0;
+  return SPU::get_v2i64_imm(N, *CurDAG).getNode() != 0;
 }], v2i64_get_imm>;
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp Thu Aug 28 16:40:38 2008
@@ -105,7 +105,7 @@
 }
 
 SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) {
-  SDNode *N = Op.Val;
+  SDNode *N = Op.getNode();
   SDValue Chain = N->getOperand(0);
   SDValue Tmp1 = N->getOperand(0);
   SDValue Tmp2 = N->getOperand(1);
@@ -304,7 +304,7 @@
 // Select - Convert the specified operand from a target-independent to a
 // target-specific node if it hasn't already been changed.
 SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
-  SDNode *N = Op.Val;
+  SDNode *N = Op.getNode();
   if (N->isMachineOpcode())
     return NULL;   // Already selected.
 
@@ -367,7 +367,7 @@
   }
  
    // Finally, once everything is setup, emit the call itself
-   if(InFlag.Val)
+   if (InFlag.getNode())
      Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
                                              CallOperand, InFlag), 0);
    else // there might be no arguments

Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp Thu Aug 28 16:40:38 2008
@@ -387,8 +387,8 @@
         break;
       }
       
-      if(ValToStore.Val) {
-        if(!StackPtr.Val) {
+      if(ValToStore.getNode()) {
+        if(!StackPtr.getNode()) {
           StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
         }
         SDValue PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
@@ -397,7 +397,7 @@
         ArgOffset += ObjSize;
       }
 
-      if(ValToConvert.Val) {
+      if(ValToConvert.getNode()) {
         Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert)); 
       }
     }
@@ -471,7 +471,7 @@
   CallOperands.push_back(Callee);
 
   // emit the call itself
-  if (InFlag.Val)
+  if (InFlag.getNode())
     CallOperands.push_back(InFlag);
   else
     assert(0 && "this should never happen!\n");

Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Thu Aug 28 16:40:38 2008
@@ -193,7 +193,7 @@
 SDNode* MipsDAGToDAGISel::
 Select(SDValue N) 
 {
-  SDNode *Node = N.Val;
+  SDNode *Node = N.getNode();
   unsigned Opcode = Node->getOpcode();
 
   // Dump information about the Node being selected
@@ -252,7 +252,7 @@
       SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT, 
                                                SDValue(Carry,0), RHS);
 
-      return CurDAG->SelectNodeTo(N.Val, MOp, VT, MVT::Flag, 
+      return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, MVT::Flag, 
                                   LHS, SDValue(AddCarry,0));
     }
 
@@ -391,8 +391,8 @@
 
   #ifndef NDEBUG
   DOUT << std::string(Indent-2, ' ') << "=> ";
-  if (ResNode == NULL || ResNode == N.Val)
-    DEBUG(N.Val->dump(CurDAG));
+  if (ResNode == NULL || ResNode == N.getNode())
+    DEBUG(N.getNode()->dump(CurDAG));
   else
     DEBUG(ResNode->dump(CurDAG));
   DOUT << "\n";

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Aug 28 16:40:38 2008
@@ -602,7 +602,7 @@
     MFI->CreateFixedObject(VTsize, (VTsize*3));
   }
 
-  CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
+  CCInfo.AnalyzeCallOperands(Op.getNode(), CC_Mips);
   
   // Get a count of how many bytes are to be pushed on the stack.
   unsigned NumBytes = CCInfo.getNextStackOffset();
@@ -706,7 +706,7 @@
     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
                                   RegsToPass[i].second.getValueType()));
 
-  if (InFlag.Val)
+  if (InFlag.getNode())
     Ops.push_back(InFlag);
 
   Chain  = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
@@ -750,7 +750,7 @@
 
   // Handle result values, copying them out of physregs into vregs that we
   // return.
-  return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.getResNo());
+  return SDValue(LowerCallResult(Chain, InFlag, Op.getNode(), CC, DAG), Op.getResNo());
 }
 
 /// LowerCallResult - Lower the result values of an ISD::CALL into the
@@ -783,7 +783,7 @@
 
   // Merge everything together with a MERGE_VALUES node.
   return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
-                            ResultVals.size()).Val;
+                            ResultVals.size()).getNode();
 }
 
 //===----------------------------------------------------------------------===//
@@ -814,7 +814,7 @@
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
 
-  CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
+  CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_Mips);
   SmallVector<SDValue, 16> ArgValues;
   SDValue StackPtr;
 
@@ -865,7 +865,7 @@
       // To meet ABI, when VARARGS are passed on registers, the registers
       // must have their values written to the caller stack frame. 
       if ((isVarArg) && (Subtarget->isABI_O32())) {
-        if (StackPtr.Val == 0)
+        if (StackPtr.getNode() == 0)
           StackPtr = DAG.getRegister(StackReg, getPointerTy());
      
         // The stack pointer offset is relative to the caller stack frame. 
@@ -925,7 +925,7 @@
   ArgValues.push_back(Root);
 
   // Return the new list of results.
-  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
+  return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
                             ArgValues.size()).getValue(Op.getResNo());
 }
 
@@ -946,7 +946,7 @@
   CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
 
   // Analize return values of ISD::RET
-  CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
+  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Mips);
 
   // If this is the first return lowered for this function, add 
   // the regs to the liveout set for the function.
@@ -992,7 +992,7 @@
   }
 
   // Return on Mips is always a "jr $ra"
-  if (Flag.Val)
+  if (Flag.getNode())
     return DAG.getNode(MipsISD::Ret, MVT::Other, 
                        Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
   else // Return Void

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp Thu Aug 28 16:40:38 2008
@@ -168,11 +168,11 @@
     if (LD) {
       fsr = LD->getBasePtr();
     }
-    else if (isa<RegisterSDNode>(N.Val)) { 
+    else if (isa<RegisterSDNode>(N.getNode())) { 
       //FIXME an attempt to retrieve the register number
       //but does not work
       DOUT << "this is a register\n";
-      Reg = dyn_cast<RegisterSDNode>(N.Val);
+      Reg = dyn_cast<RegisterSDNode>(N.getNode());
       fsr = CurDAG->getRegister(Reg->getReg(),MVT::i16);  
     }
     else {
@@ -198,7 +198,7 @@
     return true;
   }
   else if (N.getOpcode() == PIC16ISD::Package) {
-    CurDAG->setGraphColor(Op.Val, "blue");
+    CurDAG->setGraphColor(Op.getNode(), "blue");
     CurDAG->viewGraph();
   }
 
@@ -227,7 +227,7 @@
 /// expanded, promoted and normal instructions.
 SDNode* PIC16DAGToDAGISel::Select(SDValue N) 
 {
-  SDNode *Node = N.Val;
+  SDNode *Node = N.getNode();
   unsigned Opcode = Node->getOpcode();
 
   // Dump information about the Node being selected
@@ -262,8 +262,8 @@
 
 #ifndef NDEBUG
   DOUT << std::string(Indent-2, ' ') << "=> ";
-  if (ResNode == NULL || ResNode == N.Val)
-    DEBUG(N.Val->dump(CurDAG));
+  if (ResNode == NULL || ResNode == N.getNode())
+    DEBUG(N.getNode()->dump(CurDAG));
   else
     DEBUG(ResNode->dump(CurDAG));
   DOUT << "\n";

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Thu Aug 28 16:40:38 2008
@@ -334,7 +334,7 @@
   LoadSDNode *LD  = cast<LoadSDNode>(N);
   SDValue Ptr   = LD->getBasePtr();
   if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
-    if (ISD::isNON_TRUNCStore(Chain.Val)) {
+    if (ISD::isNON_TRUNCStore(Chain.getNode())) {
       StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
       if (PrevST->getBasePtr() == Ptr &&
           PrevST->getValue().getValueType() == N->getValueType(0))
@@ -352,7 +352,7 @@
   Outs[1] = DAG.getLoad(MVT::i8, Chain, toWorklist, NULL, 0);
   // FIXME: Add to worklist may not be needed. 
   // It is meant to merge sequences of add with constant into one. 
-  DCI.AddToWorklist(toWorklist.Val);   
+  DCI.AddToWorklist(toWorklist.getNode());   
   
   // Create the tokenfactors and carry it on to the build_pair node
   OutChains[0] = Outs[0].getValue(1);
@@ -443,7 +443,7 @@
       changed = true;
       // LowerLOAD returns a Package node or it may combine and return 
       // anything else.
-      SDValue lowered = LowerLOAD(InOp[i].Val, DAG, DCI);
+      SDValue lowered = LowerLOAD(InOp[i].getNode(), DAG, DCI);
 
       // So If LowerLOAD returns something other than Package, 
       // then just call ADD again.
@@ -462,7 +462,7 @@
       changed = true;
       // Must call LowerADDSUB recursively here,
       // LowerADDSUB returns a Package node.
-      SDValue lowered = LowerADDSUB(InOp[i].Val, DAG, DCI);
+      SDValue lowered = LowerADDSUB(InOp[i].getNode(), DAG, DCI);
 
       LoOps[i] = lowered.getOperand(0);
       HiOps[i] = lowered.getOperand(1);
@@ -543,7 +543,7 @@
   // FIXME: Just copy right now.
   ArgValues.push_back(Root);
 
-  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
+  return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
                             ArgValues.size()).getValue(Op.getResNo());
 }
 
@@ -622,7 +622,7 @@
       if ((Src.getOpcode() == ISD::ANY_EXTEND) ||
           (Src.getOpcode() == ISD::SIGN_EXTEND) || 
           (Src.getOpcode() == ISD::ZERO_EXTEND)) {
-        Src = Src.Val->getOperand(0);
+        Src = Src.getNode()->getOperand(0);
         Stores[0] = DAG.getStore(Chain, Src, Dest, NULL,0);
         return Stores[0];
       }
@@ -721,10 +721,10 @@
           // We want to merge sequence of add with constant to one add and a 
           // constant, so add the ADD node to worklist to have llvm do that 
           // automatically.
-          DCI.AddToWorklist(toWorkList.Val); 
+          DCI.AddToWorklist(toWorkList.getNode()); 
 
           // We don't need the Package so add to worklist so llvm deletes it
-          DCI.AddToWorklist(Src.Val);
+          DCI.AddToWorklist(Src.getNode());
           retVal = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], 2);
         }
 

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Aug 28 16:40:38 2008
@@ -294,7 +294,7 @@
       BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
     }
   }
-  return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()).Val;
+  return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()).getNode();
 }
 
 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
@@ -313,7 +313,7 @@
 }
 
 static bool isIntS16Immediate(SDValue Op, short &Imm) {
-  return isIntS16Immediate(Op.Val, Imm);
+  return isIntS16Immediate(Op.getNode(), Imm);
 }
 
 
@@ -340,7 +340,7 @@
 // isInt32Immediate - This method tests to see if a constant operand.
 // If so Imm will receive the 32 bit value.
 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
-  return isInt32Immediate(N.Val, Imm);
+  return isInt32Immediate(N.getNode(), Imm);
 }
 
 
@@ -348,7 +348,7 @@
 // opcode and that it has a immediate integer right operand.
 // If so Imm will receive the 32 bit value.
 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
-  return N->getOpcode() == Opc && isInt32Immediate(N->getOperand(1).Val, Imm);
+  return N->getOpcode() == Opc && isInt32Immediate(N->getOperand(1).getNode(), Imm);
 }
 
 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
@@ -384,7 +384,7 @@
   unsigned Indeterminant = ~0;  // bit mask marking indeterminant results
   unsigned Opcode = N->getOpcode();
   if (N->getNumOperands() != 2 ||
-      !isInt32Immediate(N->getOperand(1).Val, Shift) || (Shift > 31))
+      !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
     return false;
   
   if (Opcode == ISD::SHL) {
@@ -540,7 +540,7 @@
   } else if (LHS.getValueType() == MVT::i64) {
     uint64_t Imm;
     if (CC == ISD::SETEQ || CC == ISD::SETNE) {
-      if (isInt64Immediate(RHS.Val, Imm)) {
+      if (isInt64Immediate(RHS.getNode(), Imm)) {
         // SETEQ/SETNE comparison with 16-bit immediate, fold it.
         if (isUInt16(Imm))
           return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
@@ -568,7 +568,7 @@
       }
       Opc = PPC::CMPLD;
     } else if (ISD::isUnsignedIntSetCC(CC)) {
-      if (isInt64Immediate(RHS.Val, Imm) && isUInt16(Imm))
+      if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm))
         return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
                                                getI64Imm(Imm & 0xFFFF)), 0);
       Opc = PPC::CMPLD;
@@ -653,7 +653,7 @@
 }
 
 SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
-  SDNode *N = Op.Val;
+  SDNode *N = Op.getNode();
   unsigned Imm;
   ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
   if (isInt32Immediate(N->getOperand(1), Imm)) {
@@ -773,7 +773,7 @@
 // Select - Convert the specified operand from a target-independent to a
 // target-specific node if it hasn't already been changed.
 SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
-  SDNode *N = Op.Val;
+  SDNode *N = Op.getNode();
   if (N->isMachineOpcode())
     return NULL;   // Already selected.
 
@@ -974,7 +974,7 @@
     // If this is an and of a value rotated between 0 and 31 bits and then and'd
     // with a mask, emit rlwinm
     if (isInt32Immediate(N->getOperand(1), Imm) &&
-        isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
+        isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
       SDValue Val = N->getOperand(0).getOperand(0);
       AddToISelQueue(Val);
       SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
@@ -1025,7 +1025,7 @@
     break;
   case ISD::SHL: {
     unsigned Imm, SH, MB, ME;
-    if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
+    if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
         isRotateAndMask(N, Imm, true, SH, MB, ME)) {
       AddToISelQueue(N->getOperand(0).getOperand(0));
       SDValue Ops[] = { N->getOperand(0).getOperand(0),
@@ -1038,7 +1038,7 @@
   }
   case ISD::SRL: {
     unsigned Imm, SH, MB, ME;
-    if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
+    if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
         isRotateAndMask(N, Imm, true, SH, MB, ME)) { 
       AddToISelQueue(N->getOperand(0).getOperand(0));
       SDValue Ops[] = { N->getOperand(0).getOperand(0),

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Aug 28 16:40:38 2008
@@ -423,7 +423,7 @@
 static bool isFloatingPointZero(SDValue Op) {
   if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
     return CFP->getValueAPF().isZero();
-  else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
+  else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
     // Maybe this has already been legalized into the constant pool?
     if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
       if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
@@ -625,7 +625,7 @@
       if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
 
           
-      if (UniquedVals[i&(Multiple-1)].Val == 0)
+      if (UniquedVals[i&(Multiple-1)].getNode() == 0)
         UniquedVals[i&(Multiple-1)] = N->getOperand(i);
       else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
         return SDValue();  // no match.
@@ -640,21 +640,21 @@
     bool LeadingZero = true;
     bool LeadingOnes = true;
     for (unsigned i = 0; i != Multiple-1; ++i) {
-      if (UniquedVals[i].Val == 0) continue;  // Must have been undefs.
+      if (UniquedVals[i].getNode() == 0) continue;  // Must have been undefs.
       
       LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
       LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
     }
     // Finally, check the least significant entry.
     if (LeadingZero) {
-      if (UniquedVals[Multiple-1].Val == 0)
+      if (UniquedVals[Multiple-1].getNode() == 0)
         return DAG.getTargetConstant(0, MVT::i32);  // 0,0,0,undef
       int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
       if (Val < 16)
         return DAG.getTargetConstant(Val, MVT::i32);  // 0,0,0,4 -> vspltisw(4)
     }
     if (LeadingOnes) {
-      if (UniquedVals[Multiple-1].Val == 0)
+      if (UniquedVals[Multiple-1].getNode() == 0)
         return DAG.getTargetConstant(~0U, MVT::i32);  // -1,-1,-1,undef
       int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
       if (Val >= -16)                            // -1,-1,-1,-2 -> vspltisw(-2)
@@ -667,13 +667,13 @@
   // Check to see if this buildvec has a single non-undef value in its elements.
   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
     if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
-    if (OpVal.Val == 0)
+    if (OpVal.getNode() == 0)
       OpVal = N->getOperand(i);
     else if (OpVal != N->getOperand(i))
       return SDValue();
   }
   
-  if (OpVal.Val == 0) return SDValue();  // All UNDEF: use implicit def.
+  if (OpVal.getNode() == 0) return SDValue();  // All UNDEF: use implicit def.
   
   unsigned ValSizeInBytes = 0;
   uint64_t Value = 0;
@@ -735,7 +735,7 @@
     return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
 }
 static bool isIntS16Immediate(SDValue Op, short &Imm) {
-  return isIntS16Immediate(Op.Val, Imm);
+  return isIntS16Immediate(Op.getNode(), Imm);
 }
 
 
@@ -1389,7 +1389,7 @@
   // to handle Elf here.
   unsigned VecArgOffset = ArgOffset;
   if (!isVarArg && !isPPC64) {
-    for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; 
+    for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e; 
          ++ArgNo) {
       MVT ObjectVT = Op.getValue(ArgNo).getValueType();
       unsigned ObjSize = ObjectVT.getSizeInBits()/8;
@@ -1439,7 +1439,7 @@
 
   SmallVector<SDValue, 8> MemOps;
   unsigned nAltivecParamsAtEnd = 0;
-  for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
+  for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e; ++ArgNo) {
     SDValue ArgVal;
     bool needsLoad = false;
     MVT ObjectVT = Op.getValue(ArgNo).getValueType();
@@ -1765,7 +1765,7 @@
   ArgValues.push_back(Root);
  
   // Return the new list of results.
-  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
+  return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
                             ArgValues.size());
 }
 
@@ -1906,7 +1906,7 @@
     return 0;  // Top 6 bits have to be sext of immediate.
   
   return DAG.getConstant((int)C->getValue() >> 2,
-                         DAG.getTargetLoweringInfo().getPointerTy()).Val;
+                         DAG.getTargetLoweringInfo().getPointerTy()).getNode();
 }
 
 namespace {
@@ -2001,10 +2001,10 @@
     MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
     LROpOut = getReturnAddrFrameIndex(DAG);
     LROpOut = DAG.getLoad(VT, Chain, LROpOut, NULL, 0);
-    Chain = SDValue(LROpOut.Val, 1);
+    Chain = SDValue(LROpOut.getNode(), 1);
     FPOpOut = getFramePointerFrameIndex(DAG);
     FPOpOut = DAG.getLoad(VT, Chain, FPOpOut, NULL, 0);
-    Chain = SDValue(FPOpOut.Val, 1);
+    Chain = SDValue(FPOpOut.getNode(), 1);
   }
   return Chain;
 }
@@ -2193,12 +2193,12 @@
           SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
           SDValue AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const);
           SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
-                                CallSeqStart.Val->getOperand(0), 
+                                CallSeqStart.getNode()->getOperand(0), 
                                 Flags, DAG, Size);
           // This must go outside the CALLSEQ_START..END.
           SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
-                               CallSeqStart.Val->getOperand(1));
-          DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
+                               CallSeqStart.getNode()->getOperand(1));
+          DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
           Chain = CallSeqStart = NewCallSeqStart;
           ArgOffset += PtrByteSize;
         }
@@ -2208,12 +2208,12 @@
       // code assumes it is there, even if it could be put entirely into
       // registers.  (This is not what the doc says.)
       SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
-                            CallSeqStart.Val->getOperand(0), 
+                            CallSeqStart.getNode()->getOperand(0), 
                             Flags, DAG, Size);
       // This must go outside the CALLSEQ_START..END.
       SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
-                           CallSeqStart.Val->getOperand(1));
-      DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
+                           CallSeqStart.getNode()->getOperand(1));
+      DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
       Chain = CallSeqStart = NewCallSeqStart;
       // And copy the pieces of it that fit into registers.
       for (unsigned j=0; j<Size; j+=PtrByteSize) {
@@ -2432,7 +2432,7 @@
     CallSeqOps.push_back(Chain);
     CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes));
     CallSeqOps.push_back(DAG.getIntPtrConstant(0));
-    if (InFlag.Val)
+    if (InFlag.getNode())
       CallSeqOps.push_back(InFlag);
     Chain = DAG.getNode(ISD::CALLSEQ_END, CallSeqNodeTys, &CallSeqOps[0],
                         CallSeqOps.size());
@@ -2460,7 +2460,7 @@
     // Otherwise, this is an indirect call.  We have to use a MTCTR/BCTRL pair
     // to do the call, we can't use PPCISD::CALL.
     SDValue MTCTROps[] = {Chain, Callee, InFlag};
-    Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
+    Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.getNode()!=0));
     InFlag = Chain.getValue(1);
     
     // Copy the callee address into R12/X12 on darwin.
@@ -2475,14 +2475,14 @@
     NodeTys.push_back(MVT::Flag);
     Ops.push_back(Chain);
     CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
-    Callee.Val = 0;
+    Callee.setNode(0);
     // Add CTR register as callee so a bctr can be emitted later.
     if (isTailCall)
       Ops.push_back(DAG.getRegister(PPC::CTR, getPointerTy()));
   }
 
   // If this is a direct call, pass the chain and the callee.
-  if (Callee.Val) {
+  if (Callee.getNode()) {
     Ops.push_back(Chain);
     Ops.push_back(Callee);
   }
@@ -2502,16 +2502,16 @@
   int BytesCalleePops =
     (CC==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0;
 
-  if (InFlag.Val)
+  if (InFlag.getNode())
     Ops.push_back(InFlag);
 
   // Emit tail call.
   if (isTailCall) {
-    assert(InFlag.Val &&
+    assert(InFlag.getNode() &&
            "Flag must be set. Depend on flag being set in LowerRET");
     Chain = DAG.getNode(PPCISD::TAILCALL,
-                        Op.Val->getVTList(), &Ops[0], Ops.size());
-    return SDValue(Chain.Val, Op.getResNo());
+                        Op.getNode()->getVTList(), &Ops[0], Ops.size());
+    return SDValue(Chain.getNode(), Op.getResNo());
   }
 
   Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
@@ -2521,14 +2521,14 @@
                              DAG.getConstant(NumBytes, PtrVT),
                              DAG.getConstant(BytesCalleePops, PtrVT),
                              InFlag);
-  if (Op.Val->getValueType(0) != MVT::Other)
+  if (Op.getNode()->getValueType(0) != MVT::Other)
     InFlag = Chain.getValue(1);
 
   SmallVector<SDValue, 16> ResultVals;
   SmallVector<CCValAssign, 16> RVLocs;
   unsigned CallerCC = DAG.getMachineFunction().getFunction()->getCallingConv();
   CCState CCInfo(CallerCC, isVarArg, TM, RVLocs);
-  CCInfo.AnalyzeCallResult(Op.Val, RetCC_PPC);
+  CCInfo.AnalyzeCallResult(Op.getNode(), RetCC_PPC);
   
   // Copy all of the result registers out of their specified physreg.
   for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
@@ -2546,7 +2546,7 @@
   
   // Otherwise, merge everything together with a MERGE_VALUES node.
   ResultVals.push_back(Chain);
-  SDValue Res = DAG.getMergeValues(Op.Val->getVTList(), &ResultVals[0],
+  SDValue Res = DAG.getMergeValues(Op.getNode()->getVTList(), &ResultVals[0],
                                      ResultVals.size());
   return Res.getValue(Op.getResNo());
 }
@@ -2557,7 +2557,7 @@
   unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
   bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
   CCState CCInfo(CC, isVarArg, TM, RVLocs);
-  CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
+  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_PPC);
   
   // If this is the first return lowered for this function, add the regs to the
   // liveout set for the function.
@@ -2607,7 +2607,7 @@
     Flag = Chain.getValue(1);
   }
 
-  if (Flag.Val)
+  if (Flag.getNode())
     return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
   else
     return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
@@ -2818,11 +2818,11 @@
 SDValue PPCTargetLowering::LowerFP_ROUND_INREG(SDValue Op, 
                                                  SelectionDAG &DAG) {
   assert(Op.getValueType() == MVT::ppcf128);
-  SDNode *Node = Op.Val;
+  SDNode *Node = Op.getNode();
   assert(Node->getOperand(0).getValueType() == MVT::ppcf128);
-  assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR);
-  SDValue Lo = Node->getOperand(0).Val->getOperand(0);
-  SDValue Hi = Node->getOperand(0).Val->getOperand(1);
+  assert(Node->getOperand(0).getNode()->getOpcode() == ISD::BUILD_PAIR);
+  SDValue Lo = Node->getOperand(0).getNode()->getOperand(0);
+  SDValue Hi = Node->getOperand(0).getNode()->getOperand(1);
 
   // This sequence changes FPSCR to do round-to-zero, adds the two halves
   // of the long double, and puts FPSCR back the way it was.  We do not
@@ -3237,7 +3237,7 @@
   // zero. 
   uint64_t VectorBits[2];
   uint64_t UndefBits[2];
-  if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
+  if (GetConstantBuildVectorBits(Op.getNode(), VectorBits, UndefBits))
     return SDValue();   // Not a constant vector.
   
   // If this is a splat (repetition) of a value across the whole vector, return
@@ -3483,18 +3483,18 @@
   // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
   // selected by the instruction selector.
   if (V2.getOpcode() == ISD::UNDEF) {
-    if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
-        PPC::isSplatShuffleMask(PermMask.Val, 2) ||
-        PPC::isSplatShuffleMask(PermMask.Val, 4) ||
-        PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
-        PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
-        PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
-        PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
-        PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
-        PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
-        PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
-        PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
-        PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
+    if (PPC::isSplatShuffleMask(PermMask.getNode(), 1) ||
+        PPC::isSplatShuffleMask(PermMask.getNode(), 2) ||
+        PPC::isSplatShuffleMask(PermMask.getNode(), 4) ||
+        PPC::isVPKUWUMShuffleMask(PermMask.getNode(), true) ||
+        PPC::isVPKUHUMShuffleMask(PermMask.getNode(), true) ||
+        PPC::isVSLDOIShuffleMask(PermMask.getNode(), true) != -1 ||
+        PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, true) ||
+        PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, true) ||
+        PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, true) ||
+        PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, true) ||
+        PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, true) ||
+        PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, true)) {
       return Op;
     }
   }
@@ -3502,15 +3502,15 @@
   // Altivec has a variety of "shuffle immediates" that take two vector inputs
   // and produce a fixed permutation.  If any of these match, do not lower to
   // VPERM.
-  if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
-      PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
-      PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
-      PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
-      PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
-      PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
-      PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
-      PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
-      PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
+  if (PPC::isVPKUWUMShuffleMask(PermMask.getNode(), false) ||
+      PPC::isVPKUHUMShuffleMask(PermMask.getNode(), false) ||
+      PPC::isVSLDOIShuffleMask(PermMask.getNode(), false) != -1 ||
+      PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, false) ||
+      PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, false) ||
+      PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, false) ||
+      PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, false) ||
+      PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, false) ||
+      PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, false))
     return Op;
   
   // Check to see if this is a shuffle of 4-byte values.  If so, we can use our
@@ -3842,7 +3842,7 @@
     // Use MERGE_VALUES to drop the chain result value and get a node with one
     // result.  This requires turning off getMergeValues simplification, since
     // otherwise it will give us Res back.
-    return DAG.getMergeValues(&Res, 1, false).Val;
+    return DAG.getMergeValues(&Res, 1, false).getNode();
   }
   }
 }
@@ -4292,17 +4292,17 @@
           SDValue Val = N->getOperand(0).getOperand(0);
           if (Val.getValueType() == MVT::f32) {
             Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
-            DCI.AddToWorklist(Val.Val);
+            DCI.AddToWorklist(Val.getNode());
           }
             
           Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
-          DCI.AddToWorklist(Val.Val);
+          DCI.AddToWorklist(Val.getNode());
           Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
-          DCI.AddToWorklist(Val.Val);
+          DCI.AddToWorklist(Val.getNode());
           if (N->getValueType(0) == MVT::f32) {
             Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val, 
                               DAG.getIntPtrConstant(0));
-            DCI.AddToWorklist(Val.Val);
+            DCI.AddToWorklist(Val.getNode());
           }
           return Val;
         } else if (N->getOperand(0).getValueType() == MVT::i32) {
@@ -4322,20 +4322,20 @@
       SDValue Val = N->getOperand(1).getOperand(0);
       if (Val.getValueType() == MVT::f32) {
         Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
-        DCI.AddToWorklist(Val.Val);
+        DCI.AddToWorklist(Val.getNode());
       }
       Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
-      DCI.AddToWorklist(Val.Val);
+      DCI.AddToWorklist(Val.getNode());
 
       Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
                         N->getOperand(2), N->getOperand(3));
-      DCI.AddToWorklist(Val.Val);
+      DCI.AddToWorklist(Val.getNode());
       return Val;
     }
     
     // Turn STORE (BSWAP) -> sthbrx/stwbrx.
     if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
-        N->getOperand(1).Val->hasOneUse() &&
+        N->getOperand(1).getNode()->hasOneUse() &&
         (N->getOperand(1).getValueType() == MVT::i32 ||
          N->getOperand(1).getValueType() == MVT::i16)) {
       SDValue BSwapOp = N->getOperand(1).getOperand(0);
@@ -4350,7 +4350,7 @@
     break;
   case ISD::BSWAP:
     // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
-    if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
+    if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
         N->getOperand(0).hasOneUse() &&
         (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
       SDValue Load = N->getOperand(0);
@@ -4379,7 +4379,7 @@
 
       // Next, combine the load away, we give it a bogus result value but a real
       // chain result.  The result value is dead because the bswap is dead.
-      DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
+      DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
       
       // Return N so it doesn't get rechecked!
       return SDValue(N, 0);
@@ -4398,7 +4398,7 @@
       // Scan all of the users of the LHS, looking for VCMPo's that match.
       SDNode *VCMPoNode = 0;
       
-      SDNode *LHSN = N->getOperand(0).Val;
+      SDNode *LHSN = N->getOperand(0).getNode();
       for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
            UI != E; ++UI)
         if (UI->getOpcode() == PPCISD::VCMPo &&
@@ -4650,7 +4650,7 @@
   }
   }
   
-  if (Result.Val) {
+  if (Result.getNode()) {
     Ops.push_back(Result);
     return;
   }

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td Thu Aug 28 16:40:38 2008
@@ -113,7 +113,7 @@
   return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
 }]>;
 def vecspltisb : PatLeaf<(build_vector), [{
-  return PPC::get_VSPLTI_elt(N, 1, *CurDAG).Val != 0;
+  return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0;
 }], VSPLTISB_get_imm>;
 
 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
@@ -121,7 +121,7 @@
   return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
 }]>;
 def vecspltish : PatLeaf<(build_vector), [{
-  return PPC::get_VSPLTI_elt(N, 2, *CurDAG).Val != 0;
+  return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0;
 }], VSPLTISH_get_imm>;
 
 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
@@ -129,7 +129,7 @@
   return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
 }]>;
 def vecspltisw : PatLeaf<(build_vector), [{
-  return PPC::get_VSPLTI_elt(N, 4, *CurDAG).Val != 0;
+  return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0;
 }], VSPLTISW_get_imm>;
 
 def V_immneg0 : PatLeaf<(build_vector), [{

Modified: llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp Thu Aug 28 16:40:38 2008
@@ -120,7 +120,7 @@
   
   if (Addr.getOpcode() == ISD::ADD) {
     if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
-        Predicate_simm13(Addr.getOperand(1).Val))
+        Predicate_simm13(Addr.getOperand(1).getNode()))
       return false;  // Let the reg+imm pattern catch this!
     if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
         Addr.getOperand(1).getOpcode() == SPISD::Lo)
@@ -136,7 +136,7 @@
 }
 
 SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
-  SDNode *N = Op.Val;
+  SDNode *N = Op.getNode();
   if (N->isMachineOpcode())
     return NULL;   // Already selected.
 

Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Thu Aug 28 16:40:38 2008
@@ -40,7 +40,7 @@
   CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs);
   
   // Analize return values of ISD::RET
-  CCInfo.AnalyzeReturn(Op.Val, RetCC_Sparc32);
+  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Sparc32);
   
   // If this is the first return lowered for this function, add the regs to the
   // liveout set for the function.
@@ -66,7 +66,7 @@
     Flag = Chain.getValue(1);
   }
   
-  if (Flag.Val)
+  if (Flag.getNode())
     return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain, Flag);
   return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain);
 }
@@ -233,7 +233,7 @@
   // Analyze operands of the call, assigning locations to each operand.
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), ArgLocs);
-  CCInfo.AnalyzeCallOperands(Op.Val, CC_Sparc32);
+  CCInfo.AnalyzeCallOperands(Op.getNode(), CC_Sparc32);
   
   // Get the size of the outgoing arguments stack space requirement.
   unsigned ArgsSize = CCInfo.getNextStackOffset();
@@ -374,7 +374,7 @@
       break;
     }
     
-    if (ValToStore.Val) {
+    if (ValToStore.getNode()) {
       SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
       SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
       PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
@@ -416,7 +416,7 @@
   NodeTys.push_back(MVT::Other);   // Returns a chain
   NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
   SDValue Ops[] = { Chain, Callee, InFlag };
-  Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
+  Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.getNode() ? 3 : 2);
   InFlag = Chain.getValue(1);
   
   Chain = DAG.getCALLSEQ_END(Chain,
@@ -428,7 +428,7 @@
   SmallVector<CCValAssign, 16> RVLocs;
   CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs);
   
-  RVInfo.AnalyzeCallResult(Op.Val, RetCC_Sparc32);
+  RVInfo.AnalyzeCallResult(Op.getNode(), RetCC_Sparc32);
   SmallVector<SDValue, 8> ResultVals;
   
   // Copy all of the result registers out of their specified physreg.
@@ -448,7 +448,7 @@
   ResultVals.push_back(Chain);
 
   // Merge everything together with a MERGE_VALUES node.
-  return DAG.getMergeValues(Op.Val->getVTList(), &ResultVals[0],
+  return DAG.getMergeValues(Op.getNode()->getVTList(), &ResultVals[0],
                             ResultVals.size());
 }
 
@@ -803,7 +803,7 @@
 }
 
 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
-  SDNode *Node = Op.Val;
+  SDNode *Node = Op.getNode();
   MVT VT = Node->getValueType(0);
   SDValue InChain = Node->getOperand(0);
   SDValue VAListPtr = Node->getOperand(1);

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Aug 28 16:40:38 2008
@@ -80,11 +80,11 @@
     }
     void dump() {
       cerr << "X86ISelAddressMode " << this << "\n";
-      cerr << "Base.Reg "; if (Base.Reg.Val!=0) Base.Reg.Val->dump(); 
+      cerr << "Base.Reg "; if (Base.Reg.getNode()!=0) Base.Reg.getNode()->dump(); 
                            else cerr << "nul";
       cerr << " Base.FrameIndex " << Base.FrameIndex << "\n";
       cerr << "isRIPRel " << isRIPRel << " Scale" << Scale << "\n";
-      cerr << "IndexReg "; if (IndexReg.Val!=0) IndexReg.Val->dump();
+      cerr << "IndexReg "; if (IndexReg.getNode()!=0) IndexReg.getNode()->dump();
                           else cerr << "nul"; 
       cerr << " Disp " << Disp << "\n";
       cerr << "GV "; if (GV) GV->dump(); 
@@ -253,7 +253,7 @@
     SDNode *User = *I;
     for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
       SDValue Op = User->getOperand(i);
-      if (Op.Val == N && Op.getResNo() == FlagResNo)
+      if (Op.getNode() == N && Op.getResNo() == FlagResNo)
         return User;
     }
   }
@@ -272,7 +272,7 @@
     return;
   
   for (unsigned i = 0, e = Use->getNumOperands(); !found && i != e; ++i) {
-    SDNode *N = Use->getOperand(i).Val;
+    SDNode *N = Use->getOperand(i).getNode();
     if (N == Skip)
       continue;
     if (N == Def) {
@@ -374,8 +374,8 @@
 static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
                                  SDValue Store, SDValue TF) {
   SmallVector<SDValue, 4> Ops;
-  for (unsigned i = 0, e = TF.Val->getNumOperands(); i != e; ++i)
-    if (Load.Val == TF.getOperand(i).Val)
+  for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i)
+    if (Load.getNode() == TF.getOperand(i).getNode())
       Ops.push_back(Load.getOperand(0));
     else
       Ops.push_back(TF.getOperand(i));
@@ -404,7 +404,7 @@
 
   if (N.hasOneUse() &&
       N.getOperand(1) == Address &&
-      N.Val->isOperandOf(Chain.Val)) {
+      N.getNode()->isOperandOf(Chain.getNode())) {
     Load = N;
     return true;
   }
@@ -416,8 +416,8 @@
 static void MoveBelowCallSeqStart(SelectionDAG *CurDAG, SDValue Load,
                            SDValue Call, SDValue Chain) {
   SmallVector<SDValue, 8> Ops;
-  for (unsigned i = 0, e = Chain.Val->getNumOperands(); i != e; ++i)
-    if (Load.Val == Chain.getOperand(i).Val)
+  for (unsigned i = 0, e = Chain.getNode()->getNumOperands(); i != e; ++i)
+    if (Load.getNode() == Chain.getOperand(i).getNode())
       Ops.push_back(Load.getOperand(0));
     else
       Ops.push_back(Chain.getOperand(i));
@@ -425,8 +425,8 @@
   CurDAG->UpdateNodeOperands(Load, Call.getOperand(0),
                              Load.getOperand(1), Load.getOperand(2));
   Ops.clear();
-  Ops.push_back(SDValue(Load.Val, 1));
-  for (unsigned i = 1, e = Call.Val->getNumOperands(); i != e; ++i)
+  Ops.push_back(SDValue(Load.getNode(), 1));
+  for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i)
     Ops.push_back(Call.getOperand(i));
   CurDAG->UpdateNodeOperands(Call, &Ops[0], Ops.size());
 }
@@ -435,9 +435,9 @@
 /// moved below CALLSEQ_START and the chains leading up to the call.
 /// Return the CALLSEQ_START by reference as a second output.
 static bool isCalleeLoad(SDValue Callee, SDValue &Chain) {
-  if (Callee.Val == Chain.Val || !Callee.hasOneUse())
+  if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
     return false;
-  LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.Val);
+  LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
   if (!LD ||
       LD->isVolatile() ||
       LD->getAddressingMode() != ISD::UNINDEXED ||
@@ -450,7 +450,7 @@
       return false;
     Chain = Chain.getOperand(0);
   }
-  return Chain.getOperand(0).Val == Callee.Val;
+  return Chain.getOperand(0).getNode() == Callee.getNode();
 }
 
 
@@ -530,7 +530,7 @@
       continue;
     SDValue Chain = I->getOperand(0);
 
-    if (Chain.Val->getOpcode() != ISD::TokenFactor)
+    if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
       continue;
 
     SDValue N1 = I->getOperand(1);
@@ -542,7 +542,7 @@
 
     bool RModW = false;
     SDValue Load;
-    unsigned Opcode = N1.Val->getOpcode();
+    unsigned Opcode = N1.getNode()->getOpcode();
     switch (Opcode) {
     case ISD::ADD:
     case ISD::MUL:
@@ -786,7 +786,7 @@
     return true;
   }
 
-  int id = N.Val->getNodeId();
+  int id = N.getNode()->getNodeId();
   bool AlreadySelected = isSelected(id); // Already selected, not yet replaced.
 
   switch (N.getOpcode()) {
@@ -808,14 +808,14 @@
     // Under X86-64 non-small code model, GV (and friends) are 64-bits.
     // Also, base and index reg must be 0 in order to use rip as base.
     if (is64Bit && (TM.getCodeModel() != CodeModel::Small ||
-                    AM.Base.Reg.Val || AM.IndexReg.Val))
+                    AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
       break;
     if (AM.GV != 0 || AM.CP != 0 || AM.ES != 0 || AM.JT != -1)
       break;
     // If value is available in a register both base and index components have
     // been picked, we can't fit the result available in the register in the
     // addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
-    if (!AlreadySelected || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
+    if (!AlreadySelected || (AM.Base.Reg.getNode() && AM.IndexReg.getNode())) {
       SDValue N0 = N.getOperand(0);
       if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
         GlobalValue *GV = G->getGlobal();
@@ -847,7 +847,7 @@
   }
 
   case ISD::FrameIndex:
-    if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
+    if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.getNode() == 0) {
       AM.BaseType = X86ISelAddressMode::FrameIndexBase;
       AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
       return false;
@@ -855,23 +855,23 @@
     break;
 
   case ISD::SHL:
-    if (AlreadySelected || AM.IndexReg.Val != 0 || AM.Scale != 1 || AM.isRIPRel)
+    if (AlreadySelected || AM.IndexReg.getNode() != 0 || AM.Scale != 1 || AM.isRIPRel)
       break;
       
-    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
+    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
       unsigned Val = CN->getValue();
       if (Val == 1 || Val == 2 || Val == 3) {
         AM.Scale = 1 << Val;
-        SDValue ShVal = N.Val->getOperand(0);
+        SDValue ShVal = N.getNode()->getOperand(0);
 
         // Okay, we know that we have a scale by now.  However, if the scaled
         // value is an add of something and a constant, we can fold the
         // constant into the disp field here.
-        if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
-            isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
-          AM.IndexReg = ShVal.Val->getOperand(0);
+        if (ShVal.getNode()->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
+            isa<ConstantSDNode>(ShVal.getNode()->getOperand(1))) {
+          AM.IndexReg = ShVal.getNode()->getOperand(0);
           ConstantSDNode *AddVal =
-            cast<ConstantSDNode>(ShVal.Val->getOperand(1));
+            cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
           uint64_t Disp = AM.Disp + (AddVal->getValue() << Val);
           if (isInt32(Disp))
             AM.Disp = Disp;
@@ -894,31 +894,31 @@
     // X*[3,5,9] -> X+X*[2,4,8]
     if (!AlreadySelected &&
         AM.BaseType == X86ISelAddressMode::RegBase &&
-        AM.Base.Reg.Val == 0 &&
-        AM.IndexReg.Val == 0 &&
+        AM.Base.Reg.getNode() == 0 &&
+        AM.IndexReg.getNode() == 0 &&
         !AM.isRIPRel) {
-      if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1)))
+      if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
         if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
           AM.Scale = unsigned(CN->getValue())-1;
 
-          SDValue MulVal = N.Val->getOperand(0);
+          SDValue MulVal = N.getNode()->getOperand(0);
           SDValue Reg;
 
           // Okay, we know that we have a scale by now.  However, if the scaled
           // value is an add of something and a constant, we can fold the
           // constant into the disp field here.
-          if (MulVal.Val->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
-              isa<ConstantSDNode>(MulVal.Val->getOperand(1))) {
-            Reg = MulVal.Val->getOperand(0);
+          if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
+              isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
+            Reg = MulVal.getNode()->getOperand(0);
             ConstantSDNode *AddVal =
-              cast<ConstantSDNode>(MulVal.Val->getOperand(1));
+              cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
             uint64_t Disp = AM.Disp + AddVal->getValue() * CN->getValue();
             if (isInt32(Disp))
               AM.Disp = Disp;
             else
-              Reg = N.Val->getOperand(0);
+              Reg = N.getNode()->getOperand(0);
           } else {
-            Reg = N.Val->getOperand(0);
+            Reg = N.getNode()->getOperand(0);
           }
 
           AM.IndexReg = AM.Base.Reg = Reg;
@@ -930,12 +930,12 @@
   case ISD::ADD:
     if (!AlreadySelected) {
       X86ISelAddressMode Backup = AM;
-      if (!MatchAddress(N.Val->getOperand(0), AM, false, Depth+1) &&
-          !MatchAddress(N.Val->getOperand(1), AM, false, Depth+1))
+      if (!MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1) &&
+          !MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1))
         return false;
       AM = Backup;
-      if (!MatchAddress(N.Val->getOperand(1), AM, false, Depth+1) &&
-          !MatchAddress(N.Val->getOperand(0), AM, false, Depth+1))
+      if (!MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1) &&
+          !MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1))
         return false;
       AM = Backup;
     }
@@ -970,7 +970,7 @@
     if (Shift.getOpcode() != ISD::SHL) break;
     
     // Scale must not be used already.
-    if (AM.IndexReg.Val != 0 || AM.Scale != 1) break;
+    if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
 
     // Not when RIP is used as the base.
     if (AM.isRIPRel) break;
@@ -995,8 +995,8 @@
                                            SDValue(C2, 0), SDValue(C1, 0));
     SDValue NewAND = CurDAG->getNode(ISD::AND, N.getValueType(),
                                        Shift.getOperand(0), NewANDMask);
-    NewANDMask.Val->setNodeId(Shift.Val->getNodeId());
-    NewAND.Val->setNodeId(N.Val->getNodeId());
+    NewANDMask.getNode()->setNodeId(Shift.getNode()->getNodeId());
+    NewAND.getNode()->setNodeId(N.getNode()->getNodeId());
     
     AM.Scale = 1 << ShiftCst;
     AM.IndexReg = NewAND;
@@ -1012,9 +1012,9 @@
 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM,
                                        bool isRoot, unsigned Depth) {
   // Is the base register already occupied?
-  if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
+  if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
     // If so, check to see if the scale index register is set.
-    if (AM.IndexReg.Val == 0 && !AM.isRIPRel) {
+    if (AM.IndexReg.getNode() == 0 && !AM.isRIPRel) {
       AM.IndexReg = N;
       AM.Scale = 1;
       return false;
@@ -1042,11 +1042,11 @@
 
   MVT VT = N.getValueType();
   if (AM.BaseType == X86ISelAddressMode::RegBase) {
-    if (!AM.Base.Reg.Val)
+    if (!AM.Base.Reg.getNode())
       AM.Base.Reg = CurDAG->getRegister(0, VT);
   }
 
-  if (!AM.IndexReg.Val)
+  if (!AM.IndexReg.getNode())
     AM.IndexReg = CurDAG->getRegister(0, VT);
 
   getAddressOperands(AM, Base, Scale, Index, Disp);
@@ -1073,10 +1073,10 @@
                                           SDValue &OutChain) {
   if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
     InChain = N.getOperand(0).getValue(1);
-    if (ISD::isNON_EXTLoad(InChain.Val) &&
+    if (ISD::isNON_EXTLoad(InChain.getNode()) &&
         InChain.getValue(0).hasOneUse() &&
         N.hasOneUse() &&
-        CanBeFoldedBy(N.Val, Pred.Val, Op.Val)) {
+        CanBeFoldedBy(N.getNode(), Pred.getNode(), Op.getNode())) {
       LoadSDNode *LD = cast<LoadSDNode>(InChain);
       if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
         return false;
@@ -1087,11 +1087,11 @@
 
   // Also handle the case where we explicitly require zeros in the top
   // elements.  This is a vector shuffle from the zero vector.
-  if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.Val->hasOneUse() &&
+  if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
       // Check to see if the top elements are all zeros (or bitcast of zeros).
       N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR && 
-      N.getOperand(0).Val->hasOneUse() &&
-      ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).Val) &&
+      N.getOperand(0).getNode()->hasOneUse() &&
+      ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
       N.getOperand(0).getOperand(0).hasOneUse()) {
     // Okay, this is a zero extending load.  Fold it.
     LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
@@ -1117,14 +1117,14 @@
   MVT VT = N.getValueType();
   unsigned Complexity = 0;
   if (AM.BaseType == X86ISelAddressMode::RegBase)
-    if (AM.Base.Reg.Val)
+    if (AM.Base.Reg.getNode())
       Complexity = 1;
     else
       AM.Base.Reg = CurDAG->getRegister(0, VT);
   else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
     Complexity = 4;
 
-  if (AM.IndexReg.Val)
+  if (AM.IndexReg.getNode())
     Complexity++;
   else
     AM.IndexReg = CurDAG->getRegister(0, VT);
@@ -1148,7 +1148,7 @@
       Complexity += 2;
   }
 
-  if (AM.Disp && (AM.Base.Reg.Val || AM.IndexReg.Val))
+  if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
     Complexity++;
 
   if (Complexity > 2) {
@@ -1161,9 +1161,9 @@
 bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
                                   SDValue &Base, SDValue &Scale,
                                   SDValue &Index, SDValue &Disp) {
-  if (ISD::isNON_EXTLoad(N.Val) &&
+  if (ISD::isNON_EXTLoad(N.getNode()) &&
       N.hasOneUse() &&
-      CanBeFoldedBy(N.Val, P.Val, P.Val))
+      CanBeFoldedBy(N.getNode(), P.getNode(), P.getNode()))
     return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp);
   return false;
 }
@@ -1198,14 +1198,14 @@
     }
     
   }
-  return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val;
+  return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
 }
 
 static SDNode *FindCallStartFromCall(SDNode *Node) {
   if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
     assert(Node->getOperand(0).getValueType() == MVT::Other &&
          "Node doesn't have a token chain argument!");
-  return FindCallStartFromCall(Node->getOperand(0).Val);
+  return FindCallStartFromCall(Node->getOperand(0).getNode());
 }
 
 /// getTruncateTo8Bit - return an SDNode that implements a subreg based
@@ -1239,7 +1239,7 @@
 
 
 SDNode *X86DAGToDAGISel::Select(SDValue N) {
-  SDNode *Node = N.Val;
+  SDNode *Node = N.getNode();
   MVT NVT = Node->getValueType(0);
   unsigned Opc, MOpc;
   unsigned Opcode = Node->getOpcode();
@@ -1277,7 +1277,7 @@
       MVT PtrVT = TLI.getPointerTy();
       SDValue N0 = N.getOperand(0);
       SDValue N1 = N.getOperand(1);
-      if (N.Val->getValueType(0) == PtrVT &&
+      if (N.getNode()->getValueType(0) == PtrVT &&
           N0.getOpcode() == X86ISD::Wrapper &&
           N1.getOpcode() == ISD::Constant) {
         unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getValue();
@@ -1294,13 +1294,13 @@
                                             CP->getOffset()+Offset);
         }
 
-        if (C.Val) {
+        if (C.getNode()) {
           if (Subtarget->is64Bit()) {
             SDValue Ops[] = { CurDAG->getRegister(0, PtrVT), getI8Imm(1),
                                 CurDAG->getRegister(0, PtrVT), C };
-            return CurDAG->SelectNodeTo(N.Val, X86::LEA64r, MVT::i64, Ops, 4);
+            return CurDAG->SelectNodeTo(N.getNode(), X86::LEA64r, MVT::i64, Ops, 4);
           } else
-            return CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, PtrVT, C);
+            return CurDAG->SelectNodeTo(N.getNode(), X86::MOV32ri, PtrVT, C);
         }
       }
 
@@ -1379,7 +1379,7 @@
         ReplaceUses(N.getValue(0), Result);
 #ifndef NDEBUG
         DOUT << std::string(Indent-2, ' ') << "=> ";
-        DEBUG(Result.Val->dump(CurDAG));
+        DEBUG(Result.getNode()->dump(CurDAG));
         DOUT << "\n";
 #endif
       }
@@ -1406,7 +1406,7 @@
         ReplaceUses(N.getValue(1), Result);
 #ifndef NDEBUG
         DOUT << std::string(Indent-2, ' ') << "=> ";
-        DEBUG(Result.Val->dump(CurDAG));
+        DEBUG(Result.getNode()->dump(CurDAG));
         DOUT << "\n";
 #endif
       }
@@ -1538,7 +1538,7 @@
         ReplaceUses(N.getValue(0), Result);
 #ifndef NDEBUG
         DOUT << std::string(Indent-2, ' ') << "=> ";
-        DEBUG(Result.Val->dump(CurDAG));
+        DEBUG(Result.getNode()->dump(CurDAG));
         DOUT << "\n";
 #endif
       }
@@ -1565,7 +1565,7 @@
         ReplaceUses(N.getValue(1), Result);
 #ifndef NDEBUG
         DOUT << std::string(Indent-2, ' ') << "=> ";
-        DEBUG(Result.Val->dump(CurDAG));
+        DEBUG(Result.getNode()->dump(CurDAG));
         DOUT << "\n";
 #endif
       }
@@ -1599,7 +1599,7 @@
       
 #ifndef NDEBUG
         DOUT << std::string(Indent-2, ' ') << "=> ";
-        DEBUG(TruncOp.Val->dump(CurDAG));
+        DEBUG(TruncOp.getNode()->dump(CurDAG));
         DOUT << "\n";
         DOUT << std::string(Indent-2, ' ') << "=> ";
         DEBUG(ResNode->dump(CurDAG));
@@ -1659,8 +1659,8 @@
 
 #ifndef NDEBUG
   DOUT << std::string(Indent-2, ' ') << "=> ";
-  if (ResNode == NULL || ResNode == N.Val)
-    DEBUG(N.Val->dump(CurDAG));
+  if (ResNode == NULL || ResNode == N.getNode())
+    DEBUG(N.getNode()->dump(CurDAG));
   else
     DEBUG(ResNode->dump(CurDAG));
   DOUT << "\n";

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Aug 28 16:40:38 2008
@@ -852,7 +852,7 @@
   unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
   bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
   CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
-  CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
+  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
     
   // If this is the first return lowered for this function, add the regs to the
   // liveout set for the function.
@@ -944,7 +944,7 @@
   RetOps[0] = Chain;  // Update chain.
 
   // Add the flag if we have it.
-  if (Flag.Val)
+  if (Flag.getNode())
     RetOps.push_back(Flag);
   
   return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size());
@@ -1000,7 +1000,7 @@
   // Merge everything together with a MERGE_VALUES node.
   ResultVals.push_back(Chain);
   return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
-                            ResultVals.size()).Val;
+                            ResultVals.size()).getNode();
 }
 
 
@@ -1038,7 +1038,7 @@
 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
 /// return semantics.
 static bool ArgsAreStructReturn(SDValue Op) {
-  unsigned NumArgs = Op.Val->getNumValues() - 1;
+  unsigned NumArgs = Op.getNode()->getNumValues() - 1;
   if (!NumArgs)
     return false;
 
@@ -1182,7 +1182,7 @@
   // Assign locations to all of the incoming arguments.
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
-  CCInfo.AnalyzeFormalArguments(Op.Val, CCAssignFnForNode(Op));
+  CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(Op));
   
   SmallVector<SDValue, 8> ArgValues;
   unsigned LastVal = ~0U;
@@ -1395,7 +1395,7 @@
   FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
 
   // Return the new list of results.
-  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
+  return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
                             ArgValues.size()).getValue(Op.getResNo());
 }
 
@@ -1433,7 +1433,7 @@
   OutRetAddr = getReturnAddressFrameIndex(DAG);
   // Load the "old" Return address.
   OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0);
-  return SDValue(OutRetAddr.Val, 1);
+  return SDValue(OutRetAddr.getNode(), 1);
 }
 
 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
@@ -1472,7 +1472,7 @@
   // Analyze operands of the call, assigning locations to each operand.
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
-  CCInfo.AnalyzeCallOperands(Op.Val, CCAssignFnForNode(Op));
+  CCInfo.AnalyzeCallOperands(Op.getNode(), CCAssignFnForNode(Op));
   
   // Get a count of how many bytes are to be pushed on the stack.
   unsigned NumBytes = CCInfo.getNextStackOffset();
@@ -1562,7 +1562,7 @@
     } else {
       if (!IsTailCall || (IsTailCall && isByVal)) {
         assert(VA.isMemLoc());
-        if (StackPtr.Val == 0)
+        if (StackPtr.getNode() == 0)
           StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
         
         MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain,
@@ -1658,7 +1658,7 @@
         if (Flags.isByVal()) {
           // Copy relative to framepointer.
           SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
-          if (StackPtr.Val == 0)
+          if (StackPtr.getNode() == 0)
             StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
           Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
 
@@ -1719,7 +1719,7 @@
     Ops.push_back(Chain);
     Ops.push_back(DAG.getIntPtrConstant(NumBytes));
     Ops.push_back(DAG.getIntPtrConstant(0));
-    if (InFlag.Val)
+    if (InFlag.getNode())
       Ops.push_back(InFlag);
     Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
     InFlag = Chain.getValue(1);
@@ -1751,16 +1751,16 @@
   if (Is64Bit && isVarArg)
     Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
 
-  if (InFlag.Val)
+  if (InFlag.getNode())
     Ops.push_back(InFlag);
 
   if (IsTailCall) {
-    assert(InFlag.Val && 
+    assert(InFlag.getNode() && 
            "Flag must be set. Depend on flag being set in LowerRET");
     Chain = DAG.getNode(X86ISD::TAILCALL,
-                        Op.Val->getVTList(), &Ops[0], Ops.size());
+                        Op.getNode()->getVTList(), &Ops[0], Ops.size());
       
-    return SDValue(Chain.Val, Op.getResNo());
+    return SDValue(Chain.getNode(), Op.getResNo());
   }
 
   Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
@@ -1787,7 +1787,7 @@
 
   // Handle result values, copying them out of physregs into vregs that we
   // return.
-  return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.getResNo());
+  return SDValue(LowerCallResult(Chain, InFlag, Op.getNode(), CC, DAG), Op.getResNo());
 }
 
 
@@ -2457,7 +2457,7 @@
     }
   }
 
-  if (!ElementBase.Val)
+  if (!ElementBase.getNode())
     return false;
 
   for (; i != NumElems; ++i) {
@@ -2661,7 +2661,7 @@
 /// required.
 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
   if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
-    N = N->getOperand(0).Val;
+    N = N->getOperand(0).getNode();
     if (ISD::isNON_EXTLoad(N)) {
       if (LD)
         *LD = cast<LoadSDNode>(N);
@@ -2758,18 +2758,18 @@
     
     unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
     if (Idx < NumElems) {
-      unsigned Opc = V1.Val->getOpcode();
-      if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.Val))
+      unsigned Opc = V1.getNode()->getOpcode();
+      if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
         continue;
       if (Opc != ISD::BUILD_VECTOR ||
-          !isZeroNode(V1.Val->getOperand(Idx)))
+          !isZeroNode(V1.getNode()->getOperand(Idx)))
         return false;
     } else if (Idx >= NumElems) {
-      unsigned Opc = V2.Val->getOpcode();
-      if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.Val))
+      unsigned Opc = V2.getNode()->getOpcode();
+      if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
         continue;
       if (Opc != ISD::BUILD_VECTOR ||
-          !isZeroNode(V2.Val->getOperand(Idx - NumElems)))
+          !isZeroNode(V2.getNode()->getOperand(Idx - NumElems)))
         return false;
     }
   }
@@ -2958,8 +2958,8 @@
       ++NumZeros;
       continue;
     }
-    SDValue Elt = DAG.getShuffleScalarElt(Op.Val, Index);
-    if (Elt.Val && isZeroNode(Elt))
+    SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index);
+    if (Elt.getNode() && isZeroNode(Elt))
       ++NumZeros;
     else
       break;
@@ -3043,7 +3043,7 @@
       } else
         ThisElt = LastElt;
 
-      if (ThisElt.Val)
+      if (ThisElt.getNode())
         V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
                         DAG.getIntPtrConstant(i/2));
     }
@@ -3097,14 +3097,14 @@
 SDValue
 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
   // All zero's are handled with pxor, all one's are handled with pcmpeqd.
-  if (ISD::isBuildVectorAllZeros(Op.Val) || ISD::isBuildVectorAllOnes(Op.Val)) {
+  if (ISD::isBuildVectorAllZeros(Op.getNode()) || ISD::isBuildVectorAllOnes(Op.getNode())) {
     // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
     // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
     // eliminated on x86-32 hosts.
     if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
       return Op;
 
-    if (ISD::isBuildVectorAllOnes(Op.Val))
+    if (ISD::isBuildVectorAllOnes(Op.getNode()))
       return getOnesVector(Op.getValueType(), DAG);
     return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG);
   }
@@ -3252,13 +3252,13 @@
   if (EVTBits == 8 && NumElems == 16) {
     SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
                                         *this);
-    if (V.Val) return V;
+    if (V.getNode()) return V;
   }
 
   if (EVTBits == 16 && NumElems == 8) {
     SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
                                         *this);
-    if (V.Val) return V;
+    if (V.getNode()) return V;
   }
 
   // If element VT is == 32 bits, turn it into a number of shuffles.
@@ -3344,8 +3344,8 @@
   MVT MaskVT = MVT::getIntVectorWithNumElements(8);
   MVT MaskEVT = MaskVT.getVectorElementType();
   MVT PtrVT = TLI.getPointerTy();
-  SmallVector<SDValue, 8> MaskElts(PermMask.Val->op_begin(),
-                                   PermMask.Val->op_end());
+  SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(),
+                                   PermMask.getNode()->op_end());
 
   // First record which half of which vector the low elements come from.
   SmallVector<unsigned, 4> LowQuad(4);
@@ -3653,7 +3653,7 @@
                               const X86Subtarget *Subtarget) {
   if (VT == MVT::v2f64 || VT == MVT::v4f32) {
     LoadSDNode *LD = NULL;
-    if (!isScalarLoadToVector(SrcOp.Val, &LD))
+    if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
       LD = dyn_cast<LoadSDNode>(SrcOp);
     if (!LD) {
       // movssrr and movsdrr do not clear top bits. Try to use movd, movq
@@ -3850,18 +3850,18 @@
   bool V1IsSplat = false;
   bool V2IsSplat = false;
 
-  if (isUndefShuffle(Op.Val))
+  if (isUndefShuffle(Op.getNode()))
     return DAG.getNode(ISD::UNDEF, VT);
 
-  if (isZeroShuffle(Op.Val))
+  if (isZeroShuffle(Op.getNode()))
     return getZeroVector(VT, Subtarget->hasSSE2(), DAG);
 
-  if (isIdentityMask(PermMask.Val))
+  if (isIdentityMask(PermMask.getNode()))
     return V1;
-  else if (isIdentityMask(PermMask.Val, true))
+  else if (isIdentityMask(PermMask.getNode(), true))
     return V2;
 
-  if (isSplatMask(PermMask.Val)) {
+  if (isSplatMask(PermMask.getNode())) {
     if (isMMX || NumElems < 4) return Op;
     // Promote it to a v4{if}32 splat.
     return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
@@ -3871,27 +3871,27 @@
   // do it!
   if (VT == MVT::v8i16 || VT == MVT::v16i8) {
     SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
-    if (NewOp.Val)
+    if (NewOp.getNode())
       return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
   } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
     // FIXME: Figure out a cleaner way to do this.
     // Try to make use of movq to zero out the top part.
-    if (ISD::isBuildVectorAllZeros(V2.Val)) {
+    if (ISD::isBuildVectorAllZeros(V2.getNode())) {
       SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
                                                  DAG, *this);
-      if (NewOp.Val) {
+      if (NewOp.getNode()) {
         SDValue NewV1 = NewOp.getOperand(0);
         SDValue NewV2 = NewOp.getOperand(1);
         SDValue NewMask = NewOp.getOperand(2);
-        if (isCommutedMOVL(NewMask.Val, true, false)) {
+        if (isCommutedMOVL(NewMask.getNode(), true, false)) {
           NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
           return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget);
         }
       }
-    } else if (ISD::isBuildVectorAllZeros(V1.Val)) {
+    } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
       SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
                                                 DAG, *this);
-      if (NewOp.Val && X86::isMOVLMask(NewOp.getOperand(2).Val))
+      if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode()))
         return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
                              DAG, Subtarget);
     }
@@ -3910,24 +3910,24 @@
     return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
   }
 
-  if (X86::isMOVLMask(PermMask.Val)) {
+  if (X86::isMOVLMask(PermMask.getNode())) {
     if (V1IsUndef)
       return V2;
-    if (ISD::isBuildVectorAllZeros(V1.Val))
+    if (ISD::isBuildVectorAllZeros(V1.getNode()))
       return getVZextMovL(VT, VT, V2, DAG, Subtarget);
     if (!isMMX)
       return Op;
   }
 
-  if (!isMMX && (X86::isMOVSHDUPMask(PermMask.Val) ||
-                 X86::isMOVSLDUPMask(PermMask.Val) ||
-                 X86::isMOVHLPSMask(PermMask.Val) ||
-                 X86::isMOVHPMask(PermMask.Val) ||
-                 X86::isMOVLPMask(PermMask.Val)))
+  if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) ||
+                 X86::isMOVSLDUPMask(PermMask.getNode()) ||
+                 X86::isMOVHLPSMask(PermMask.getNode()) ||
+                 X86::isMOVHPMask(PermMask.getNode()) ||
+                 X86::isMOVLPMask(PermMask.getNode())))
     return Op;
 
-  if (ShouldXformToMOVHLPS(PermMask.Val) ||
-      ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
+  if (ShouldXformToMOVHLPS(PermMask.getNode()) ||
+      ShouldXformToMOVLP(V1.getNode(), V2.getNode(), PermMask.getNode()))
     return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
 
   if (isShift) {
@@ -3940,8 +3940,8 @@
   bool Commuted = false;
   // FIXME: This should also accept a bitcast of a splat?  Be careful, not
   // 1,1,1,1 -> v8i16 though.
-  V1IsSplat = isSplatVector(V1.Val);
-  V2IsSplat = isSplatVector(V2.Val);
+  V1IsSplat = isSplatVector(V1.getNode());
+  V2IsSplat = isSplatVector(V2.getNode());
   
   // Canonicalize the splat or undef, if present, to be on the RHS.
   if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
@@ -3952,7 +3952,7 @@
   }
 
   // FIXME: Figure out a cleaner way to do this.
-  if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
+  if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) {
     if (V2IsUndef) return V1;
     Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
     if (V2IsSplat) {
@@ -3960,16 +3960,16 @@
       // to any V2 element. The instruction selectior won't like this. Get
       // a corrected mask and commute to form a proper MOVS{S|D}.
       SDValue NewMask = getMOVLMask(NumElems, DAG);
-      if (NewMask.Val != PermMask.Val)
+      if (NewMask.getNode() != PermMask.getNode())
         Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
     }
     return Op;
   }
 
-  if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
-      X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
-      X86::isUNPCKLMask(PermMask.Val) ||
-      X86::isUNPCKHMask(PermMask.Val))
+  if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
+      X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
+      X86::isUNPCKLMask(PermMask.getNode()) ||
+      X86::isUNPCKHMask(PermMask.getNode()))
     return Op;
 
   if (V2IsSplat) {
@@ -3977,11 +3977,11 @@
     // element then try to match unpck{h|l} again. If match, return a
     // new vector_shuffle with the corrected mask.
     SDValue NewMask = NormalizeMask(PermMask, DAG);
-    if (NewMask.Val != PermMask.Val) {
-      if (X86::isUNPCKLMask(PermMask.Val, true)) {
+    if (NewMask.getNode() != PermMask.getNode()) {
+      if (X86::isUNPCKLMask(PermMask.getNode(), true)) {
         SDValue NewMask = getUnpacklMask(NumElems, DAG);
         return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
-      } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
+      } else if (X86::isUNPCKHMask(PermMask.getNode(), true)) {
         SDValue NewMask = getUnpackhMask(NumElems, DAG);
         return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
       }
@@ -3989,23 +3989,23 @@
   }
 
   // Normalize the node to match x86 shuffle ops if needed
-  if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
+  if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.getNode()))
       Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
 
   if (Commuted) {
     // Commute is back and try unpck* again.
     Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
-    if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
-        X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
-        X86::isUNPCKLMask(PermMask.Val) ||
-        X86::isUNPCKHMask(PermMask.Val))
+    if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
+        X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
+        X86::isUNPCKLMask(PermMask.getNode()) ||
+        X86::isUNPCKHMask(PermMask.getNode()))
       return Op;
   }
 
   // Try PSHUF* first, then SHUFP*.
   // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically
   // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
-  if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.Val)) {
+  if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) {
     if (V2.getOpcode() != ISD::UNDEF)
       return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
                          DAG.getNode(ISD::UNDEF, VT), PermMask);
@@ -4014,9 +4014,9 @@
 
   if (!isMMX) {
     if (Subtarget->hasSSE2() &&
-        (X86::isPSHUFDMask(PermMask.Val) ||
-         X86::isPSHUFHWMask(PermMask.Val) ||
-         X86::isPSHUFLWMask(PermMask.Val))) {
+        (X86::isPSHUFDMask(PermMask.getNode()) ||
+         X86::isPSHUFHWMask(PermMask.getNode()) ||
+         X86::isPSHUFLWMask(PermMask.getNode()))) {
       MVT RVT = VT;
       if (VT == MVT::v4f32) {
         RVT = MVT::v4i32;
@@ -4032,15 +4032,15 @@
     }
 
     // Binary or unary shufps.
-    if (X86::isSHUFPMask(PermMask.Val) ||
-        (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.Val)))
+    if (X86::isSHUFPMask(PermMask.getNode()) ||
+        (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.getNode())))
       return Op;
   }
 
   // Handle v8i16 specifically since SSE can do byte extraction and insertion.
   if (VT == MVT::v8i16) {
     SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
-    if (NewOp.Val)
+    if (NewOp.getNode())
       return NewOp;
   }
 
@@ -4073,7 +4073,7 @@
     // result has a single use which is a store or a bitcast to i32.
     if (!Op.hasOneUse())
       return SDValue();
-    SDNode *User = *Op.Val->use_begin();
+    SDNode *User = *Op.getNode()->use_begin();
     if (User->getOpcode() != ISD::STORE &&
         (User->getOpcode() != ISD::BIT_CONVERT ||
          User->getValueType(0) != MVT::i32))
@@ -4094,7 +4094,7 @@
 
   if (Subtarget->hasSSE41()) {
     SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
-    if (Res.Val)
+    if (Res.getNode())
       return Res;
   }
 
@@ -4599,7 +4599,7 @@
 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
   std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG);
   SDValue FIST = Vals.first, StackSlot = Vals.second;
-  if (FIST.Val == 0) return SDValue();
+  if (FIST.getNode() == 0) return SDValue();
   
   // Load the result.
   return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
@@ -4608,7 +4608,7 @@
 SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) {
   std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG);
   SDValue FIST = Vals.first, StackSlot = Vals.second;
-  if (FIST.Val == 0) return 0;
+  if (FIST.getNode() == 0) return 0;
 
   MVT VT = N->getValueType(0);
 
@@ -4618,7 +4618,7 @@
   // Use MERGE_VALUES to drop the chain result value and get a node with one
   // result.  This requires turning off getMergeValues simplification, since
   // otherwise it will give us Res back.
-  return DAG.getMergeValues(&Res, 1, false).Val;
+  return DAG.getMergeValues(&Res, 1, false).getNode();
 }
 
 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
@@ -5258,7 +5258,7 @@
       DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
     };
     
-    return DAG.getMergeValues(Ops, 2).Val;
+    return DAG.getMergeValues(Ops, 2).getNode();
   }
   
   SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
@@ -5270,7 +5270,7 @@
 
   // Use a MERGE_VALUES to return the value and chain.
   Ops[1] = edx.getValue(1);
-  return DAG.getMergeValues(Ops, 2).Val;
+  return DAG.getMergeValues(Ops, 2).getNode();
 }
 
 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
@@ -5857,7 +5857,7 @@
     if (Subtarget->is64Bit()) {
       Reg = X86::RAX; size = 8;
     } else //Should go away when LowerType stuff lands
-      return SDValue(ExpandATOMIC_CMP_SWAP(Op.Val, DAG), 0);
+      return SDValue(ExpandATOMIC_CMP_SWAP(Op.getNode(), DAG), 0);
     break;
   };
   SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
@@ -5907,7 +5907,7 @@
   SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
   SDValue ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
   SDValue Vals[2] = { ResultVal, cpOutH.getValue(1) };
-  return DAG.getMergeValues(Vals, 2).Val;
+  return DAG.getMergeValues(Vals, 2).getNode();
 }
 
 SDNode* X86TargetLowering::ExpandATOMIC_LOAD_SUB(SDNode* Op, SelectionDAG &DAG) {
@@ -5920,7 +5920,7 @@
                         T==MVT::i64 ? ISD::ATOMIC_LOAD_ADD_64: 0),
                        Op->getOperand(0), Op->getOperand(1), negOp,
                        cast<AtomicSDNode>(Op)->getSrcValue(),
-                       cast<AtomicSDNode>(Op)->getAlignment()).Val;
+                       cast<AtomicSDNode>(Op)->getAlignment()).getNode();
 }
 
 /// LowerOperation - Provide custom lowering hooks for some operations.
@@ -5974,7 +5974,7 @@
       
   // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
   case ISD::READCYCLECOUNTER:
-    return SDValue(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0);
+    return SDValue(ExpandREADCYCLECOUNTER(Op.getNode(), DAG), 0);
   }
 }
 
@@ -6135,15 +6135,15 @@
 X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const {
   // Only do shuffles on 128-bit vector types for now.
   if (VT.getSizeInBits() == 64) return false;
-  return (Mask.Val->getNumOperands() <= 4 ||
-          isIdentityMask(Mask.Val) ||
-          isIdentityMask(Mask.Val, true) ||
-          isSplatMask(Mask.Val)  ||
-          isPSHUFHW_PSHUFLWMask(Mask.Val) ||
-          X86::isUNPCKLMask(Mask.Val) ||
-          X86::isUNPCKHMask(Mask.Val) ||
-          X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
-          X86::isUNPCKH_v_undef_Mask(Mask.Val));
+  return (Mask.getNode()->getNumOperands() <= 4 ||
+          isIdentityMask(Mask.getNode()) ||
+          isIdentityMask(Mask.getNode(), true) ||
+          isSplatMask(Mask.getNode())  ||
+          isPSHUFHW_PSHUFLWMask(Mask.getNode()) ||
+          X86::isUNPCKLMask(Mask.getNode()) ||
+          X86::isUNPCKHMask(Mask.getNode()) ||
+          X86::isUNPCKL_v_undef_Mask(Mask.getNode()) ||
+          X86::isUNPCKH_v_undef_Mask(Mask.getNode()));
 }
 
 bool
@@ -6695,11 +6695,11 @@
     }
 
     SDValue Elt = DAG.getShuffleScalarElt(N, i);
-    if (!Elt.Val ||
-        (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.Val)))
+    if (!Elt.getNode() ||
+        (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
       return false;
     if (!Base) {
-      Base = Elt.Val;
+      Base = Elt.getNode();
       if (Base->getOpcode() == ISD::UNDEF)
         return false;
       continue;
@@ -6707,7 +6707,7 @@
     if (Elt.getOpcode() == ISD::UNDEF)
       continue;
 
-    if (!TLI.isConsecutiveLoad(Elt.Val, Base,
+    if (!TLI.isConsecutiveLoad(Elt.getNode(), Base,
                                EVT.getSizeInBits()/8, i, MFI))
       return false;
   }
@@ -6731,7 +6731,7 @@
     return SDValue();
 
   LoadSDNode *LD = cast<LoadSDNode>(Base);
-  if (isBaseAlignmentOfN(16, Base->getOperand(1).Val, TLI))
+  if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI))
     return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
                        LD->getSrcValueOffset(), LD->isVolatile());
   return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
@@ -6762,11 +6762,11 @@
     return SDValue();
 
   // Value must be a load.
-  SDNode *Base = N->getOperand(0).Val;
+  SDNode *Base = N->getOperand(0).getNode();
   if (!isa<LoadSDNode>(Base)) {
     if (Base->getOpcode() != ISD::BIT_CONVERT)
       return SDValue();
-    Base = Base->getOperand(0).Val;
+    Base = Base->getOperand(0).getNode();
     if (!isa<LoadSDNode>(Base))
       return SDValue();
   }
@@ -6866,11 +6866,11 @@
       isa<LoadSDNode>(St->getValue()) &&
       !cast<LoadSDNode>(St->getValue())->isVolatile() &&
       St->getChain().hasOneUse() && !St->isVolatile()) {
-    SDNode* LdVal = St->getValue().Val;
+    SDNode* LdVal = St->getValue().getNode();
     LoadSDNode *Ld = 0;
     int TokenFactorIndex = -1;
     SmallVector<SDValue, 8> Ops;
-    SDNode* ChainVal = St->getChain().Val;
+    SDNode* ChainVal = St->getChain().getNode();
     // Must be a store of a load.  We currently handle two cases:  the load
     // is a direct child, and it's under an intervening TokenFactor.  It is
     // possible to dig deeper under nested TokenFactors.
@@ -6879,7 +6879,7 @@
     else if (St->getValue().hasOneUse() &&
              ChainVal->getOpcode() == ISD::TokenFactor) {
       for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
-        if (ChainVal->getOperand(i).Val == LdVal) {
+        if (ChainVal->getOperand(i).getNode() == LdVal) {
           TokenFactorIndex = i;
           Ld = cast<LoadSDNode>(St->getValue());
         } else
@@ -7108,7 +7108,7 @@
   }
   }
   
-  if (Result.Val) {
+  if (Result.getNode()) {
     Ops.push_back(Result);
     return;
   }

Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=55504&r1=55503&r2=55504&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Thu Aug 28 16:40:38 2008
@@ -506,17 +506,17 @@
 
           if (NeedCheck) {
             std::string ParentName(RootName.begin(), RootName.end()-1);
-            emitCheck("CanBeFoldedBy(" + RootName + ".Val, " + ParentName +
-                      ".Val, N.Val)");
+            emitCheck("CanBeFoldedBy(" + RootName + ".getNode(), " + ParentName +
+                      ".getNode(), N.getNode())");
           }
         }
       }
 
       if (NodeHasChain) {
         if (FoundChain) {
-          emitCheck("(" + ChainName + ".Val == " + RootName + ".Val || "
-                    "IsChainCompatible(" + ChainName + ".Val, " +
-                    RootName + ".Val))");
+          emitCheck("(" + ChainName + ".getNode() == " + RootName + ".getNode() || "
+                    "IsChainCompatible(" + ChainName + ".getNode(), " +
+                    RootName + ".getNode()))");
           OrigChains.push_back(std::make_pair(ChainName, RootName));
         } else
           FoundChain = true;
@@ -543,7 +543,7 @@
 
     // If there is a node predicate for this, emit the call.
     if (!N->getPredicateFn().empty())
-      emitCheck(N->getPredicateFn() + "(" + RootName + ".Val)");
+      emitCheck(N->getPredicateFn() + "(" + RootName + ".getNode())");
 
     
     // If this is an 'and R, 1234' where the operation is AND/OR and the RHS is
@@ -720,7 +720,7 @@
         // If there is a node predicate for this, emit the call.
         if (!Child->getPredicateFn().empty())
           emitCheck(Child->getPredicateFn() + "(" + RootName +
-                    ".Val)");
+                    ".getNode())");
       } else if (IntInit *II =
                  dynamic_cast<IntInit*>(Child->getLeafValue())) {
         emitCheck("isa<ConstantSDNode>(" + RootName + ")");
@@ -951,8 +951,8 @@
         // case, the TokenFactor can have more operands.
         emitCode("SmallVector<SDValue, 8> InChains;");
         for (unsigned i = 0, e = OrigChains.size(); i < e; ++i) {
-          emitCode("if (" + OrigChains[i].first + ".Val != " +
-                   OrigChains[i].second + ".Val) {");
+          emitCode("if (" + OrigChains[i].first + ".getNode() != " +
+                   OrigChains[i].second + ".getNode()) {");
           emitCode("  AddToISelQueue(" + OrigChains[i].first + ");");
           emitCode("  InChains.push_back(" + OrigChains[i].first + ");");
           emitCode("}");
@@ -1164,7 +1164,7 @@
         std::string Code;
         for (unsigned j = 0, e = FoldedChains.size(); j < e; j++) {
           ReplaceFroms.push_back("SDValue(" +
-                                 FoldedChains[j].first + ".Val, " +
+                                 FoldedChains[j].first + ".getNode(), " +
                                  utostr(FoldedChains[j].second) +
                                  ")");
           ReplaceTos.push_back("SDValue(ResNode, " +
@@ -1174,12 +1174,12 @@
 
       if (NodeHasOutFlag) {
         if (FoldedFlag.first != "") {
-          ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + ".Val, " +
+          ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + ".getNode(), " +
                                  utostr(FoldedFlag.second) + ")");
           ReplaceTos.push_back("InFlag");
         } else {
           assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP));
-          ReplaceFroms.push_back("SDValue(N.Val, " +
+          ReplaceFroms.push_back("SDValue(N.getNode(), " +
                                  utostr(NumPatResults + (unsigned)InputHasChain)
                                  + ")");
           ReplaceTos.push_back("InFlag");
@@ -1187,9 +1187,9 @@
       }
 
       if (!ReplaceFroms.empty() && InputHasChain) {
-        ReplaceFroms.push_back("SDValue(N.Val, " +
+        ReplaceFroms.push_back("SDValue(N.getNode(), " +
                                utostr(NumPatResults) + ")");
-        ReplaceTos.push_back("SDValue(" + ChainName + ".Val, " +
+        ReplaceTos.push_back("SDValue(" + ChainName + ".getNode(), " +
                              ChainName + ".getResNo()" + ")");
         ChainAssignmentNeeded |= NodeHasChain;
       }
@@ -1200,12 +1200,12 @@
       } else if (InputHasChain && !NodeHasChain) {
         // One of the inner node produces a chain.
         if (NodeHasOutFlag) {
-          ReplaceFroms.push_back("SDValue(N.Val, " +
+          ReplaceFroms.push_back("SDValue(N.getNode(), " +
                                  utostr(NumPatResults+1) +
                                  ")");
           ReplaceTos.push_back("SDValue(ResNode, N.getResNo()-1)");
         }
-        ReplaceFroms.push_back("SDValue(N.Val, " +
+        ReplaceFroms.push_back("SDValue(N.getNode(), " +
                                utostr(NumPatResults) + ")");
         ReplaceTos.push_back(ChainName);
       }
@@ -1216,7 +1216,7 @@
         std::string ChainAssign;
         if (!isRoot)
           ChainAssign = ChainName + " = SDValue(" + NodeName +
-                        ".Val, " + utostr(NumResults+NumDstRegs) + ");";
+                        ".getNode(), " + utostr(NumResults+NumDstRegs) + ");";
         else
           ChainAssign = ChainName + " = SDValue(" + NodeName +
                         ", " + utostr(NumResults+NumDstRegs) + ");";
@@ -1251,7 +1251,7 @@
       if (!isRoot || (InputHasChain && !NodeHasChain)) {
         Code = "CurDAG->getTargetNode(" + Code;
       } else {
-        Code = "CurDAG->SelectNodeTo(N.Val, " + Code;
+        Code = "CurDAG->SelectNodeTo(N.getNode(), " + Code;
       }
       if (isRoot) {
         if (After.empty())
@@ -1274,10 +1274,10 @@
                        ResNodeDecled, true);
       unsigned ResNo = TmpNo++;
       emitCode("SDValue Tmp" + utostr(ResNo) + " = Transform_" + Op->getName()
-               + "(" + Ops.back() + ".Val);");
+               + "(" + Ops.back() + ".getNode());");
       NodeOps.push_back("Tmp" + utostr(ResNo));
       if (isRoot)
-        emitCode("return Tmp" + utostr(ResNo) + ".Val;");
+        emitCode("return Tmp" + utostr(ResNo) + ".getNode();");
       return NodeOps;
     } else {
       N->dump();
@@ -1298,7 +1298,7 @@
       Pat->setTypes(Other->getExtTypes());
       // The top level node type is checked outside of the select function.
       if (!isRoot)
-        emitCheck(Prefix + ".Val->getValueType(0) == " +
+        emitCheck(Prefix + ".getNode()->getValueType(0) == " +
                   getName(Pat->getTypeNum(0)));
       return true;
     }
@@ -1360,7 +1360,7 @@
               std::string Decl = (!ResNodeDecled) ? "SDNode *" : "";
               emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" + ChainName +
                        ", " + getQualifiedName(RR) +
-                       ", " +  RootName + utostr(OpNo) + ", InFlag).Val;");
+                       ", " +  RootName + utostr(OpNo) + ", InFlag).getNode();");
               ResNodeDecled = true;
               emitCode(ChainName + " = SDValue(ResNode, 0);");
               emitCode("InFlag = SDValue(ResNode, 1);");
@@ -1836,7 +1836,7 @@
         if (OpName != "ISD::INTRINSIC_W_CHAIN" &&
             OpName != "ISD::INTRINSIC_WO_CHAIN" &&
             OpName != "ISD::INTRINSIC_VOID") {
-          OS << "  N.Val->dump(CurDAG);\n";
+          OS << "  N.getNode()->dump(CurDAG);\n";
         } else {
           OS << "  unsigned iid = cast<ConstantSDNode>(N.getOperand("
             "N.getOperand(0).getValueType() == MVT::Other))->getValue();\n"
@@ -1853,7 +1853,7 @@
   
   // Emit boilerplate.
   OS << "SDNode *Select_INLINEASM(SDValue N) {\n"
-     << "  std::vector<SDValue> Ops(N.Val->op_begin(), N.Val->op_end());\n"
+     << "  std::vector<SDValue> Ops(N.getNode()->op_begin(), N.getNode()->op_end());\n"
      << "  SelectInlineAsmMemoryOperands(Ops);\n\n"
     
      << "  // Ensure that the asm operands are themselves selected.\n"
@@ -1865,11 +1865,11 @@
      << "  VTs.push_back(MVT::Flag);\n"
      << "  SDValue New = CurDAG->getNode(ISD::INLINEASM, VTs, &Ops[0], "
                  "Ops.size());\n"
-     << "  return New.Val;\n"
+     << "  return New.getNode();\n"
      << "}\n\n";
 
   OS << "SDNode *Select_UNDEF(const SDValue &N) {\n"
-     << "  return CurDAG->SelectNodeTo(N.Val, TargetInstrInfo::IMPLICIT_DEF,\n"
+     << "  return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::IMPLICIT_DEF,\n"
      << "                              N.getValueType());\n"
      << "}\n\n";
 
@@ -1878,7 +1878,7 @@
      << "  unsigned C = cast<LabelSDNode>(N)->getLabelID();\n"
      << "  SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
      << "  AddToISelQueue(Chain);\n"
-     << "  return CurDAG->SelectNodeTo(N.Val, TargetInstrInfo::DBG_LABEL,\n"
+     << "  return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::DBG_LABEL,\n"
      << "                              MVT::Other, Tmp, Chain);\n"
      << "}\n\n";
 
@@ -1887,7 +1887,7 @@
      << "  unsigned C = cast<LabelSDNode>(N)->getLabelID();\n"
      << "  SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
      << "  AddToISelQueue(Chain);\n"
-     << "  return CurDAG->SelectNodeTo(N.Val, TargetInstrInfo::EH_LABEL,\n"
+     << "  return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::EH_LABEL,\n"
      << "                              MVT::Other, Tmp, Chain);\n"
      << "}\n\n";
 
@@ -1897,7 +1897,7 @@
      << "  SDValue N2 = N.getOperand(2);\n"
      << "  if (!isa<FrameIndexSDNode>(N1) || !isa<GlobalAddressSDNode>(N2)) {\n"
      << "    cerr << \"Cannot yet select llvm.dbg.declare: \";\n"
-     << "    N.Val->dump(CurDAG);\n"
+     << "    N.getNode()->dump(CurDAG);\n"
      << "    abort();\n"
      << "  }\n"
      << "  int FI = cast<FrameIndexSDNode>(N1)->getIndex();\n"
@@ -1907,7 +1907,7 @@
      << "  SDValue Tmp2 = "
      << "CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());\n"
      << "  AddToISelQueue(Chain);\n"
-     << "  return CurDAG->SelectNodeTo(N.Val, TargetInstrInfo::DECLARE,\n"
+     << "  return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::DECLARE,\n"
      << "                              MVT::Other, Tmp1, Tmp2, Chain);\n"
      << "}\n\n";
 
@@ -1917,7 +1917,7 @@
      << "  unsigned C = cast<ConstantSDNode>(N1)->getValue();\n"
      << "  SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
      << "  AddToISelQueue(N0);\n"
-     << "  return CurDAG->SelectNodeTo(N.Val, TargetInstrInfo::EXTRACT_SUBREG,\n"
+     << "  return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::EXTRACT_SUBREG,\n"
      << "                              N.getValueType(), N0, Tmp);\n"
      << "}\n\n";
 
@@ -1929,7 +1929,7 @@
      << "  SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
      << "  AddToISelQueue(N1);\n"
      << "  AddToISelQueue(N0);\n"
-     << "  return CurDAG->SelectNodeTo(N.Val, TargetInstrInfo::INSERT_SUBREG,\n"
+     << "  return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::INSERT_SUBREG,\n"
      << "                              N.getValueType(), N0, N1, Tmp);\n"
      << "}\n\n";
 
@@ -1938,7 +1938,7 @@
      << "  if (N.isMachineOpcode()) {\n"
      << "    return NULL;   // Already selected.\n"
      << "  }\n\n"
-     << "  MVT::SimpleValueType NVT = N.Val->getValueType(0).getSimpleVT();\n"
+     << "  MVT::SimpleValueType NVT = N.getNode()->getValueType(0).getSimpleVT();\n"
      << "  switch (N.getOpcode()) {\n"
      << "  default: break;\n"
      << "  case ISD::EntryToken:       // These leaves remain the same.\n"
@@ -2033,7 +2033,7 @@
      << "  if (N.getOpcode() != ISD::INTRINSIC_W_CHAIN &&\n"
      << "      N.getOpcode() != ISD::INTRINSIC_WO_CHAIN &&\n"
      << "      N.getOpcode() != ISD::INTRINSIC_VOID) {\n"
-     << "    N.Val->dump(CurDAG);\n"
+     << "    N.getNode()->dump(CurDAG);\n"
      << "  } else {\n"
      << "    unsigned iid = cast<ConstantSDNode>(N.getOperand("
                "N.getOperand(0).getValueType() == MVT::Other))->getValue();\n"




From ggreif at gmail.com  Thu Aug 28 17:32:40 2008
From: ggreif at gmail.com (Gabor Greif)
Date: Thu, 28 Aug 2008 22:32:40 -0000
Subject: [llvm-commits] [llvm] r55506 - /llvm/trunk/Makefile.rules
Message-ID: <200808282232.m7SMWehT010010@zion.cs.uiuc.edu>

Author: ggreif
Date: Thu Aug 28 17:32:39 2008
New Revision: 55506

URL: http://llvm.org/viewvc/llvm-project?rev=55506&view=rev
Log:
fix the output dumbness I have introduced some time ago

Modified:
    llvm/trunk/Makefile.rules

Modified: llvm/trunk/Makefile.rules
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=55506&r1=55505&r2=55506&view=diff

==============================================================================
--- llvm/trunk/Makefile.rules (original)
+++ llvm/trunk/Makefile.rules Thu Aug 28 17:32:39 2008
@@ -1750,13 +1750,13 @@
 	@echo searching for overlength lines in files: $(Sources)
 	@echo
 	@echo
-	@egrep -n '.{81}' $(Sources) /dev/null
+	egrep -n '.{81}' $(Sources) /dev/null
 
 check-for-tabs:
 	@echo searching for tabs in files: $(Sources)
 	@echo
 	@echo
-	@egrep -n '	' $(Sources) /dev/null
+	egrep -n '	' $(Sources) /dev/null
 
 check-footprint:
 	@ls -l $(LibDir) | awk '\




From nicolas.geoffray at lip6.fr  Thu Aug 28 17:34:49 2008
From: nicolas.geoffray at lip6.fr (Nicolas Geoffray)
Date: Thu, 28 Aug 2008 22:34:49 -0000
Subject: [llvm-commits] [llvm] r55507 -
	/llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp
Message-ID: <200808282234.m7SMYobp010080@zion.cs.uiuc.edu>

Author: geoffray
Date: Thu Aug 28 17:34:49 2008
New Revision: 55507

URL: http://llvm.org/viewvc/llvm-project?rev=55507&view=rev
Log:
Add support for JIT exceptions on Darwin. Since we're dealing with libgcc,
whose darwin code was written after the ability to dynamically register frames,
we need to do special hacks to make things work.


Modified:
    llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp

Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp?rev=55507&r1=55506&r2=55507&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp Thu Aug 28 17:34:49 2008
@@ -64,9 +64,127 @@
   }
 }
 
+
 #if defined (__GNUC__)
+ 
+// libgcc defines the __register_frame function to dynamically register new
+// dwarf frames for exception handling. This functionality is not portable
+// across compilers and is only provided by GCC. We use the __register_frame
+// function here so that code generated by the JIT cooperates with the unwinding
+// runtime of libgcc. When JITting with exception handling enable, LLVM
+// generates dwarf frames and registers it to libgcc with __register_frame.
+//
+// The __register_frame function works with Linux.
+//
+// Unfortunately, this functionality seems to be in libgcc after the unwinding
+// library of libgcc for darwin was written. The code for darwin overwrites the
+// value updated by __register_frame with a value fetched with "keymgr".
+// "keymgr" is an obsolete functionality, which should be rewritten some day.
+// In the meantime, since "keymgr" is on all libgccs shipped with apple-gcc, we
+// need a workaround in LLVM which uses the "keymgr" to dynamically modify the
+// values of an opaque key, used by libgcc to find dwarf tables.
+
 extern "C" void __register_frame(void*);
-#endif
+
+#if defined (__APPLE__)
+
+namespace {
+
+// LibgccObject - This is the structure defined in libgcc. There is no #include
+// provided for this structure, so we also define it here. libgcc calls it
+// "struct object". The structure is undocumented in libgcc.
+struct LibgccObject {
+  void *unused1;
+  void *unused2;
+  void *unused3;
+  
+  /// frame - Pointer to the exception table.
+  void *frame;
+  
+  /// encoding -  The encoding of the object?
+  union {
+    struct {
+      unsigned long sorted : 1;
+      unsigned long from_array : 1;
+      unsigned long mixed_encoding : 1;
+      unsigned long encoding : 8;
+      unsigned long count : 21; 
+    } b;
+    size_t i;
+  } encoding;
+  
+  /// fde_end - libgcc defines this field only if some macro is defined. We
+  /// include this field even if it may not there, to make libgcc happy.
+  char *fde_end;
+  
+  /// next - At least we know it's a chained list!
+  struct LibgccObject *next;
+};
+
+// "kemgr" stuff. Apparently, all frame tables are stored there.
+extern "C" void _keymgr_set_and_unlock_processwide_ptr(int, void *);
+extern "C" void *_keymgr_get_and_lock_processwide_ptr(int);
+#define KEYMGR_GCC3_DW2_OBJ_LIST        302     /* Dwarf2 object list  */
+
+/// LibgccObjectInfo - libgcc defines this struct as km_object_info. It
+/// probably contains all dwarf tables that are loaded.
+struct LibgccObjectInfo {
+
+  /// seenObjects - LibgccObjects already parsed by the unwinding runtime.
+  ///
+  struct LibgccObject* seenObjects;
+
+  /// unseenObjects - LibgccObjects not parsed yet by the unwinding runtime.
+  ///
+  struct LibgccObject* unseenObjects;
+  
+  unsigned unused[2];
+};
+
+// for DW_EH_PE_omit
+#include "llvm/Support/Dwarf.h"
+
+/// darwin_register_frame - Since __register_frame does not work with darwin's
+/// libgcc,we provide our own function, which "tricks" libgcc by modifying the
+/// "Dwarf2 object list" key.
+void DarwinRegisterFrame(void* FrameBegin) {
+  // Get the key.
+  struct LibgccObjectInfo* LOI = (struct LibgccObjectInfo*)
+    _keymgr_get_and_lock_processwide_ptr(KEYMGR_GCC3_DW2_OBJ_LIST);
+  
+  // Allocate a new LibgccObject to represent this frame. Deallocation of this
+  // object may be impossible: since darwin code in libgcc was written after
+  // the ability to dynamically register frames, things may crash if we
+  // deallocate it.
+  struct LibgccObject* ob = (struct LibgccObject*)
+    malloc(sizeof(struct LibgccObject));
+  
+  // Do like libgcc for the values of the field.
+  ob->unused1 = (void *)-1;
+  ob->unused2 = 0;
+  ob->unused3 = 0;
+  ob->frame = FrameBegin;
+  ob->encoding.i = 0; 
+  ob->encoding.b.encoding = llvm::dwarf::DW_EH_PE_omit;
+  
+  // Put the info on both places, as libgcc uses the first or the the second
+  // field. Note that we rely on having two pointers here. If fde_end was a
+  // char, things would get complicated.
+  ob->fde_end = (char*)LOI->unseenObjects;
+  ob->next = LOI->unseenObjects;
+  
+  // Update the key's unseenObjects list.
+  LOI->unseenObjects = ob;
+  
+  // Finally update the "key". Apparently, libgcc requires it. 
+  _keymgr_set_and_unlock_processwide_ptr(KEYMGR_GCC3_DW2_OBJ_LIST,
+                                         LOI);
+
+}
+
+}
+#endif // __APPLE__
+#endif // __GNUC__
 
 /// createJIT - This is the factory method for creating a JIT for the current
 /// machine, it does not fall back to the interpreter.  This takes ownership
@@ -108,8 +226,23 @@
   
   // Register routine for informing unwinding runtime about new EH frames
 #if defined(__GNUC__)
+#if defined(__APPLE__)
+  struct LibgccObjectInfo* LOI = (struct LibgccObjectInfo*)
+    _keymgr_get_and_lock_processwide_ptr(KEYMGR_GCC3_DW2_OBJ_LIST);
+  
+  // The key is created on demand, and libgcc creates it the first time an
+  // exception occurs. Since we need the key to register frames, we create
+  // it now.
+  if (!LOI) {
+    LOI = (LibgccObjectInfo*)malloc(sizeof(struct LibgccObjectInfo)); 
+    _keymgr_set_and_unlock_processwide_ptr(KEYMGR_GCC3_DW2_OBJ_LIST,
+                                           LOI);
+  }
+  InstallExceptionTableRegister(DarwinRegisterFrame);
+#else
   InstallExceptionTableRegister(__register_frame);
-#endif
+#endif // __APPLE__
+#endif // __GNUC__
   
   // Initialize passes.
   PM.doInitialization();




From wangmp at apple.com  Thu Aug 28 17:36:34 2008
From: wangmp at apple.com (Mon Ping Wang)
Date: Thu, 28 Aug 2008 15:36:34 -0700
Subject: [llvm-commits] [llvm] r55457 - in /llvm/trunk:
	include/llvm/CodeGen/SelectionDAGNodes.h	include/llvm/Target/TargetLowering.h
	lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	lib/CodeGen/SelectionDAG/SelectionDAG.cpp
	lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	lib/Target/TargetSelectionDAG.td
	lib/Target/X86/X86ISelLowering.cpp	lib/Target/X86/X86Instr64bit.td
	lib/Target/X86/X86InstrInfo.td
In-Reply-To: <764F54DD-8DFF-40E2-821D-1308B8B3606E@apple.com>
References: <200808280244.m7S2ioDI016151@zion.cs.uiuc.edu>
	<3D1FD3C4-4F1D-423E-BBF1-3D184394890A@apple.com>
	<764F54DD-8DFF-40E2-821D-1308B8B3606E@apple.com>
Message-ID: <3682B07E-6F50-48AF-863C-8E1FA968B1CB@apple.com>

Hi,

On the PPC, what does a normal write to i8 look like? Is it  
represented as LOAD to an i8 MemoryVT?
Does it make sense when doing an ATOMIC_LOAD_ADD_8 to be  
ATOMIC_LOAD_ADD to a MemoryVT of i8 or is that senseless?

If the MemoryVT is meant only to be used the LOAD/STORES, it seems  
natural to move it down to LSBaseSDNode.  I moved it into MemSDNode  
because I thought that any memory access should have a MemoryVT  
associated with it.

-- Mon Ping

On Aug 28, 2008, at 1:14 PM, Dale Johannesen wrote:

>
> On Aug 28, 2008, at 11:14 AMPDT, Dan Gohman wrote:
>> On Aug 27, 2008, at 7:44 PM, Dale Johannesen wrote:
>>
>>> Author: johannes
>>> Date: Wed Aug 27 21:44:49 2008
>>> New Revision: 55457
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=55457&view=rev
>>> Log:
>>> Split the ATOMIC NodeType's to include the size, e.g.
>>> ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
>>> Increased the Hardcoded Constant OpActionsCapacity to match.
>>> Large but boring; no functional change.
>>>
>>> This is to support partial-word atomics on ppc; i8 is
>>> not a valid type there, so by the time we get to lowering, the
>>> ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
>>> The information can be added to the AtomicSDNode, but that is the
>>> largest SDNode; I don't fully understand the SDNode allocation,
>>> but it is sensitive to the largest node size, so increasing
>>> that must be bad.  This is the alternative.
>>
>>
>> Hi Dale,
>>
>> I'd like to see if we can find an alternative to this  
>> alternative :-).
>> Here's one idea:
>>
>> MemSDNode has a MemoryVT member. This is used for truncating
>> stores and extending loads to indicate the type of the actual
>> memory access. We don't have extending or truncating atomics,
>> so I believe it's redundant in AtomicSDNode.
>>
>> Perhaps MemoryVT could be moved out of MemSDNode and into
>> LSBaseSDNode? That would allow a new MVT member to be added
>> to AtomicSDNode without an overall size increase.
>
> Maybe, but MemoryVT kind of belongs in the MemSDNode, doesn't it?
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From sabre at nondot.org  Thu Aug 28 17:56:53 2008
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 28 Aug 2008 22:56:53 -0000
Subject: [llvm-commits] [llvm] r55508 - in /llvm/trunk:
 include/llvm/Analysis/IntervalPartition.h
 lib/Analysis/IntervalPartition.cpp
Message-ID: <200808282256.m7SMurSM010803@zion.cs.uiuc.edu>

Author: lattner
Date: Thu Aug 28 17:56:53 2008
New Revision: 55508

URL: http://llvm.org/viewvc/llvm-project?rev=55508&view=rev
Log:
rename destroy -> releaseMemory to properly hook into passmgr.


Modified:
    llvm/trunk/include/llvm/Analysis/IntervalPartition.h
    llvm/trunk/lib/Analysis/IntervalPartition.cpp

Modified: llvm/trunk/include/llvm/Analysis/IntervalPartition.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/IntervalPartition.h?rev=55508&r1=55507&r2=55508&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Analysis/IntervalPartition.h (original)
+++ llvm/trunk/include/llvm/Analysis/IntervalPartition.h Thu Aug 28 17:56:53 2008
@@ -59,9 +59,6 @@
   //
   IntervalPartition(IntervalPartition &I, bool);
 
-  // Destructor - Free memory
-  ~IntervalPartition() { destroy(); }
-
   // print - Show contents in human readable format...
   virtual void print(std::ostream &O, const Module* = 0) const;
   void print(std::ostream *O, const Module* M = 0) const {
@@ -92,10 +89,10 @@
   // Interface to Intervals vector...
   const std::vector<Interval*> &getIntervals() const { return Intervals; }
 
-private:
-  // destroy - Reset state back to before function was analyzed
-  void destroy();
+  // releaseMemory - Reset state back to before function was analyzed
+  void releaseMemory();
 
+private:
   // addIntervalToPartition - Add an interval to the internal list of intervals,
   // and then add mappings from all of the basic blocks in the interval to the
   // interval itself (in the IntervalMap).

Modified: llvm/trunk/lib/Analysis/IntervalPartition.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IntervalPartition.cpp?rev=55508&r1=55507&r2=55508&view=diff

==============================================================================
--- llvm/trunk/lib/Analysis/IntervalPartition.cpp (original)
+++ llvm/trunk/lib/Analysis/IntervalPartition.cpp Thu Aug 28 17:56:53 2008
@@ -23,8 +23,8 @@
 // IntervalPartition Implementation
 //===----------------------------------------------------------------------===//
 
-// destroy - Reset state back to before function was analyzed
-void IntervalPartition::destroy() {
+// releaseMemory - Reset state back to before function was analyzed
+void IntervalPartition::releaseMemory() {
   for (unsigned i = 0, e = Intervals.size(); i != e; ++i)
     delete Intervals[i];
   IntervalMap.clear();




From ggreif at gmail.com  Thu Aug 28 18:15:28 2008
From: ggreif at gmail.com (Gabor Greif)
Date: Thu, 28 Aug 2008 23:15:28 -0000
Subject: [llvm-commits] [llvm] r55509 - /llvm/trunk/utils/visit-violations
Message-ID: <200808282315.m7SNFSxM011339@zion.cs.uiuc.edu>

Author: ggreif
Date: Thu Aug 28 18:15:28 2008
New Revision: 55509

URL: http://llvm.org/viewvc/llvm-project?rev=55509&view=rev
Log:
just a brain dump for a small tool
that brings us to 80-col violations
or tabs.

Usage:
  visit-violations <file>

At the moment it outputs editor invocations.

Added:
    llvm/trunk/utils/visit-violations   (with props)

Added: llvm/trunk/utils/visit-violations
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/visit-violations?rev=55509&view=auto

==============================================================================
--- llvm/trunk/utils/visit-violations (added)
+++ llvm/trunk/utils/visit-violations Thu Aug 28 18:15:28 2008
@@ -0,0 +1,5 @@
+#!/usr/bin/env tcsh
+
+make check-line-length Sources="$1" \
+| awk -F : '/:[0-9]*:/ {print "emacs", "+" $2, $1}' \
+| sort -r

Propchange: llvm/trunk/utils/visit-violations

------------------------------------------------------------------------------
    svn:executable = *




From isanbard at gmail.com  Thu Aug 28 18:16:38 2008
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 28 Aug 2008 23:16:38 -0000
Subject: [llvm-commits] [llvm] r55510 - /llvm/trunk/CREDITS.TXT
Message-ID: <200808282316.m7SNGcL8011377@zion.cs.uiuc.edu>

Author: void
Date: Thu Aug 28 18:16:37 2008
New Revision: 55510

URL: http://llvm.org/viewvc/llvm-project?rev=55510&view=rev
Log:
Add another description to my entry.

Modified:
    llvm/trunk/CREDITS.TXT

Modified: llvm/trunk/CREDITS.TXT
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CREDITS.TXT?rev=55510&r1=55509&r2=55510&view=diff

==============================================================================
--- llvm/trunk/CREDITS.TXT (original)
+++ llvm/trunk/CREDITS.TXT Thu Aug 28 18:16:37 2008
@@ -266,6 +266,7 @@
 
 N: Bill Wendling
 E: isanbard at gmail.com
+D: Machine LICM
 D: Darwin exception handling
 D: MMX & SSSE3 instructions
 D: SPEC2006 support




From ggreif at gmail.com  Thu Aug 28 18:19:52 2008
From: ggreif at gmail.com (Gabor Greif)
Date: Thu, 28 Aug 2008 23:19:52 -0000
Subject: [llvm-commits] [llvm] r55511 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <200808282319.m7SNJqSn011480@zion.cs.uiuc.edu>

Author: ggreif
Date: Thu Aug 28 18:19:51 2008
New Revision: 55511

URL: http://llvm.org/viewvc/llvm-project?rev=55511&view=rev
Log:
remove tabs, fix > 80 cols

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=55511&r1=55510&r2=55511&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Aug 28 18:19:51 2008
@@ -512,9 +512,9 @@
     setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
     setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
     setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
-    setOperationAction(ISD::VECTOR_SHUFFLE,     (MVT::SimpleValueType)VT, Expand);
-    setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::SimpleValueType)VT, Expand);
-    setOperationAction(ISD::INSERT_VECTOR_ELT,  (MVT::SimpleValueType)VT, Expand);
+    setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
+    setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
+    setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
     setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
     setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
     setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
@@ -1787,7 +1787,8 @@
 
   // Handle result values, copying them out of physregs into vregs that we
   // return.
-  return SDValue(LowerCallResult(Chain, InFlag, Op.getNode(), CC, DAG), Op.getResNo());
+  return SDValue(LowerCallResult(Chain, InFlag, Op.getNode(), CC, DAG),
+                 Op.getResNo());
 }
 
 
@@ -3091,13 +3092,14 @@
   SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp);
   return DAG.getNode(ISD::BIT_CONVERT, VT,
                      DAG.getNode(Opc, ShVT, SrcOp,
-                              DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
+                             DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
 }
 
 SDValue
 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
   // All zero's are handled with pxor, all one's are handled with pcmpeqd.
-  if (ISD::isBuildVectorAllZeros(Op.getNode()) || ISD::isBuildVectorAllOnes(Op.getNode())) {
+  if (ISD::isBuildVectorAllZeros(Op.getNode())
+      || ISD::isBuildVectorAllOnes(Op.getNode())) {
     // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
     // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
     // eliminated on x86-32 hosts.
@@ -3668,7 +3670,8 @@
         return DAG.getNode(ISD::BIT_CONVERT, VT,
                            DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
                                        DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT,
-                                                   SrcOp.getOperand(0).getOperand(0))));
+                                                   SrcOp.getOperand(0)
+                                                          .getOperand(0))));
       }
     }
   }
@@ -5874,7 +5877,8 @@
   return cpOut;
 }
 
-SDNode* X86TargetLowering::ExpandATOMIC_CMP_SWAP(SDNode* Op, SelectionDAG &DAG) {
+SDNode* X86TargetLowering::ExpandATOMIC_CMP_SWAP(SDNode* Op,
+                                                 SelectionDAG &DAG) {
   MVT T = Op->getValueType(0);
   assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
   SDValue cpInL, cpInH;
@@ -5910,7 +5914,8 @@
   return DAG.getMergeValues(Vals, 2).getNode();
 }
 
-SDNode* X86TargetLowering::ExpandATOMIC_LOAD_SUB(SDNode* Op, SelectionDAG &DAG) {
+SDNode* X86TargetLowering::ExpandATOMIC_LOAD_SUB(SDNode* Op,
+                                                 SelectionDAG &DAG) {
   MVT T = Op->getValueType(0);
   SDValue negOp = DAG.getNode(ISD::SUB, T,
                                 DAG.getConstant(0, T), Op->getOperand(2));
@@ -6933,7 +6938,8 @@
                           St->getSrcValue(), St->getSrcValueOffset(),
                           St->isVolatile(), St->getAlignment());
       SDValue HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
-                                    St->getSrcValue(), St->getSrcValueOffset()+4,
+                                    St->getSrcValue(),
+                                    St->getSrcValueOffset() + 4,
                                     St->isVolatile(), 
                                     MinAlign(St->getAlignment(), 4));
       return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);




From gohman at apple.com  Thu Aug 28 18:21:35 2008
From: gohman at apple.com (Dan Gohman)
Date: Thu, 28 Aug 2008 23:21:35 -0000
Subject: [llvm-commits] [llvm] r55512 - in /llvm/trunk:
 include/llvm/CodeGen/FastISel.h
 lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
 lib/Target/X86/X86FastISel.cpp utils/TableGen/FastISelEmitter.cpp
Message-ID: <200808282321.m7SNLZmS011561@zion.cs.uiuc.edu>

Author: djg
Date: Thu Aug 28 18:21:34 2008
New Revision: 55512

URL: http://llvm.org/viewvc/llvm-project?rev=55512&view=rev
Log:
Add a target callback for FastISel.

Modified:
    llvm/trunk/include/llvm/CodeGen/FastISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/trunk/lib/Target/X86/X86FastISel.cpp
    llvm/trunk/utils/TableGen/FastISelEmitter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=55512&r1=55511&r2=55512&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Thu Aug 28 18:21:34 2008
@@ -52,10 +52,21 @@
   /// the generated MachineInstrs.
   BasicBlock::iterator
   SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
-                     DenseMap<const Value*, unsigned> &ValueMap,
-                     DenseMap<const BasicBlock*, MachineBasicBlock *> &MBBMap,
+                     DenseMap<const Value *, unsigned> &ValueMap,
+                     DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap,
                      MachineBasicBlock *MBB);
 
+  /// TargetSelectInstruction - This method is called by target-independent
+  /// code when the normal FastISel process fails to select an instruction.
+  /// This gives targets a chance to emit code for anything that doesn't
+  /// fit into FastISel's framework. It returns true if it was successful.
+  ///
+  virtual bool
+  TargetSelectInstruction(Instruction *I,
+                          DenseMap<const Value *, unsigned> &ValueMap,
+                      DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap,
+                          MachineBasicBlock *MBB) = 0;
+
   virtual ~FastISel();
 
 protected:

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=55512&r1=55511&r2=55512&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Aug 28 18:21:34 2008
@@ -5757,10 +5757,15 @@
           Begin = F->SelectInstructions(Begin, End, FuncInfo->ValueMap,
                                         FuncInfo->MBBMap, BB);
 
+          // If the "fast" selector selected the entire block, we're done.
           if (Begin == End)
-            // The "fast" selector selected the entire block, so we're done.
             break;
 
+          // Next, try calling the target to attempt to handle the instruction.
+          if (F->TargetSelectInstruction(Begin, FuncInfo->ValueMap,
+                                         FuncInfo->MBBMap, BB))
+            continue;
+
           // Handle certain instructions as single-LLVM-Instruction blocks.
           if (isa<CallInst>(Begin) || isa<LoadInst>(Begin) ||
               isa<StoreInst>(Begin)) {
@@ -5783,7 +5788,7 @@
             // The "fast" selector couldn't handle something and bailed.
             // For the purpose of debugging, just abort.
 #ifndef NDEBUG
-              Begin->dump();
+            Begin->dump();
 #endif
             assert(0 && "FastISel didn't select the entire block");
           }

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=55512&r1=55511&r2=55512&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Thu Aug 28 18:21:34 2008
@@ -19,3 +19,23 @@
 #include "X86FastISel.h"
 #include "X86TargetMachine.h"
 #include "X86GenFastISel.inc"
+
+namespace llvm {
+
+namespace X86 {
+
+bool
+FastISel::TargetSelectInstruction(Instruction *I,
+                                  DenseMap<const Value *, unsigned> &ValueMap,
+                      DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap,
+                                  MachineBasicBlock *MBB)  {
+  switch (I->getOpcode()) {
+  default: break;
+  }
+
+  return false;
+}
+
+}
+
+}

Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=55512&r1=55511&r2=55512&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Thu Aug 28 18:21:34 2008
@@ -351,6 +351,14 @@
   }
   OS << "\n";
 
+  OS << "bool TargetSelectInstruction(Instruction *I,\n";
+  OS << "                             "
+        "DenseMap<const Value *, unsigned> &ValueMap,\n";
+  OS << "                             "
+        "DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap,\n";
+  OS << "                             "
+        "MachineBasicBlock *MBB);\n";
+
   // Declare the Subtarget member, which is used for predicate checks.
   OS << "  const " << InstNS.substr(0, InstNS.size() - 2)
      << "Subtarget *Subtarget;\n";




From daniel at zuster.org  Thu Aug 28 18:37:31 2008
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 28 Aug 2008 16:37:31 -0700
Subject: [llvm-commits] [PATCH] Add DenseMap::lookup
Message-ID: <6a8523d60808281637k10ddcd05v19d199dd534c6812@mail.gmail.com>

The attached patch adds DenseMap::lookup:
+  /// lookup - Return the entry for the specified key, or a default
+  /// value if no such entry exists.

This is useful for situations where you just want to get an entry from
the DenseMap if it exists. Code like:
--
  llvm::Function *Fn = MethodDefinitions[MD];
  if (!Fn)
    return 0;
--
is succinct but is wastefully adding entries into MethodDefinitions.

 - Daniel
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From evan.cheng at apple.com  Thu Aug 28 18:39:26 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 28 Aug 2008 23:39:26 -0000
Subject: [llvm-commits] [llvm] r55518 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td ARMInstrInfo.td
Message-ID: <200808282339.m7SNdQuO012179@zion.cs.uiuc.edu>

Author: evancheng
Date: Thu Aug 28 18:39:26 2008
New Revision: 55518

URL: http://llvm.org/viewvc/llvm-project?rev=55518&view=rev
Log:
Refactor ARM instruction format definitions into a separate file. No functionality changes.

Added:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Added: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=55518&view=auto

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (added)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Aug 28 18:39:26 2008
@@ -0,0 +1,228 @@
+//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//
+// ARM Instruction Format Definitions.
+//
+
+// Format specifies the encoding used by the instruction.  This is part of the
+// ad-hoc solution used to emit machine instruction encodings by our machine
+// code emitter.
+class Format<bits<5> val> {
+  bits<5> Value = val;
+}
+
+def Pseudo      : Format<1>;
+def MulFrm      : Format<2>;
+def MulSMLAW    : Format<3>;
+def MulSMULW    : Format<4>;
+def MulSMLA     : Format<5>;
+def MulSMUL     : Format<6>;
+def Branch      : Format<7>;
+def BranchMisc  : Format<8>;
+
+def DPRdIm      : Format<9>;
+def DPRdReg     : Format<10>;
+def DPRdSoReg   : Format<11>;
+def DPRdMisc    : Format<12>;
+def DPRnIm      : Format<13>;
+def DPRnReg     : Format<14>;
+def DPRnSoReg   : Format<15>;
+def DPRIm       : Format<16>;
+def DPRReg      : Format<17>;
+def DPRSoReg    : Format<18>;
+def DPRImS      : Format<19>;
+def DPRRegS     : Format<20>;
+def DPRSoRegS   : Format<21>;
+
+def LdFrm       : Format<22>;
+def StFrm       : Format<23>;
+
+def ArithMisc   : Format<24>;
+def ThumbFrm    : Format<25>;
+def VFPFrm      : Format<26>;
+
+
+
+//===----------------------------------------------------------------------===//
+
+// ARM Instruction templates.
+//
+
+class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
+              Format f, string cstr>
+  : Instruction {
+  let Namespace = "ARM";
+
+  bits<4> Opcode = opcod;
+  AddrMode AM = am;
+  bits<4> AddrModeBits = AM.Value;
+  
+  SizeFlagVal SZ = sz;
+  bits<3> SizeFlag = SZ.Value;
+
+  IndexMode IM = im;
+  bits<2> IndexModeBits = IM.Value;
+  
+  Format F = f;
+  bits<5> Form = F.Value;
+  
+  let Constraints = cstr;
+}
+
+class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
+  : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
+  let OutOperandList = oops;
+  let InOperandList = iops;
+  let AsmString   = asm;
+  let Pattern = pattern;
+}
+
+// Almost all ARM instructions are predicable.
+class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
+        IndexMode im, Format f, string opc, string asm, string cstr,
+        list<dag> pattern>
+  : InstARM<opcod, am, sz, im, f, cstr> {
+  let OutOperandList = oops;
+  let InOperandList = !con(iops, (ops pred:$p));
+  let AsmString   = !strconcat(opc, !strconcat("${p}", asm));
+  let Pattern = pattern;
+  list<Predicate> Predicates = [IsARM];
+}
+
+// Same as I except it can optionally modify CPSR. Note it's modeled as
+// an input operand since by default it's a zero register. It will
+// become an implicit def once it's "flipped".
+class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
+         IndexMode im, Format f, string opc, string asm, string cstr,
+         list<dag> pattern>
+  : InstARM<opcod, am, sz, im, f, cstr> {
+  let OutOperandList = oops;
+  let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
+  let AsmString   = !strconcat(opc, !strconcat("${p}${s}", asm));
+  let Pattern = pattern;
+  list<Predicate> Predicates = [IsARM];
+}
+
+class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+         string asm, list<dag> pattern>
+  : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
+      asm,"",pattern>;
+class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+          string asm, list<dag> pattern>
+  : sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
+       asm,"",pattern>;
+class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+          string asm, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
+      asm, "", pattern>;
+class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+           string asm, list<dag> pattern>
+  : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
+       asm, "", pattern>;
+class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+          string asm, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
+      asm, "", pattern>;
+class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+          string asm, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
+      asm, "", pattern>;
+class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+          string asm, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
+      asm, "", pattern>;
+class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+            string asm, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
+      asm, "", pattern>;
+
+// Pre-indexed ops
+class AI2pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+            string asm, string cstr, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
+      asm, cstr, pattern>;
+class AI3pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+            string asm, string cstr, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
+      asm, cstr, pattern>;
+
+// Post-indexed ops
+class AI2po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+            string asm, string cstr, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
+      asm, cstr,pattern>;
+class AI3po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+            string asm, string cstr, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
+      asm, cstr,pattern>;
+
+
+// Special cases.
+class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
+         IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
+  : InstARM<opcod, am, sz, im, f, cstr> {
+  let OutOperandList = oops;
+  let InOperandList = iops;
+  let AsmString   = asm;
+  let Pattern = pattern;
+  list<Predicate> Predicates = [IsARM];
+}
+
+class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+          list<dag> pattern>
+  : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
+       "", pattern>;
+class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+           list<dag> pattern>
+  : XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
+       "", pattern>;
+class AXI2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+           list<dag> pattern>
+  : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
+       "", pattern>;
+class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+           list<dag> pattern>
+  : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
+       "", pattern>;
+class AXI4<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+           list<dag> pattern>
+  : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
+       "", pattern>;
+
+class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+            list<dag> pattern>
+  : XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
+       "", pattern>;
+
+// BR_JT instructions
+class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
+  : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
+       asm, "", pattern>;
+class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
+  : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
+       asm, "", pattern>;
+class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
+  : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
+       asm, "", pattern>;
+
+
+//===----------------------------------------------------------------------===//
+
+// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
+class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
+  list<Predicate> Predicates = [IsARM];
+}
+class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
+  list<Predicate> Predicates = [IsARM, HasV5TE];
+}
+class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
+  list<Predicate> Predicates = [IsARM, HasV6];
+}

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=55518&r1=55517&r2=55518&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Aug 28 18:39:26 2008
@@ -155,7 +155,8 @@
   return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
 }]>;
 
-
+class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
+class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
 
 //===----------------------------------------------------------------------===//
 // Operand Definitions.
@@ -330,176 +331,12 @@
 def IndexModePost : IndexMode<2>;
 
 //===----------------------------------------------------------------------===//
-// ARM Instruction Format Definitions.
-//
-
-// Format specifies the encoding used by the instruction.  This is part of the
-// ad-hoc solution used to emit machine instruction encodings by our machine
-// code emitter.
-class Format<bits<5> val> {
-  bits<5> Value = val;
-}
-
-def Pseudo      : Format<1>;
-def MulFrm      : Format<2>;
-def MulSMLAW    : Format<3>;
-def MulSMULW    : Format<4>;
-def MulSMLA     : Format<5>;
-def MulSMUL     : Format<6>;
-def Branch      : Format<7>;
-def BranchMisc  : Format<8>;
-
-def DPRdIm      : Format<9>;
-def DPRdReg     : Format<10>;
-def DPRdSoReg   : Format<11>;
-def DPRdMisc    : Format<12>;
-def DPRnIm      : Format<13>;
-def DPRnReg     : Format<14>;
-def DPRnSoReg   : Format<15>;
-def DPRIm       : Format<16>;
-def DPRReg      : Format<17>;
-def DPRSoReg    : Format<18>;
-def DPRImS      : Format<19>;
-def DPRRegS     : Format<20>;
-def DPRSoRegS   : Format<21>;
-
-def LdFrm       : Format<22>;
-def StFrm       : Format<23>;
-
-def ArithMisc   : Format<24>;
-def ThumbFrm    : Format<25>;
-def VFPFrm      : Format<26>;
-
 
+include "ARMInstrFormats.td"
 
 //===----------------------------------------------------------------------===//
-
-// ARM Instruction templates.
-//
-
-// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
-class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
-  list<Predicate> Predicates = [IsARM];
-}
-class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
-  list<Predicate> Predicates = [IsARM, HasV5TE];
-}
-class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
-  list<Predicate> Predicates = [IsARM, HasV6];
-}
-
-class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
-              Format f, string cstr>
-  : Instruction {
-  let Namespace = "ARM";
-
-  bits<4> Opcode = opcod;
-  AddrMode AM = am;
-  bits<4> AddrModeBits = AM.Value;
-  
-  SizeFlagVal SZ = sz;
-  bits<3> SizeFlag = SZ.Value;
-
-  IndexMode IM = im;
-  bits<2> IndexModeBits = IM.Value;
-  
-  Format F = f;
-  bits<5> Form = F.Value;
-  
-  let Constraints = cstr;
-}
-
-class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
-  : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
-  let OutOperandList = oops;
-  let InOperandList = iops;
-  let AsmString   = asm;
-  let Pattern = pattern;
-}
-
-// Almost all ARM instructions are predicable.
-class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
-        IndexMode im, Format f, string opc, string asm, string cstr,
-        list<dag> pattern>
-  : InstARM<opcod, am, sz, im, f, cstr> {
-  let OutOperandList = oops;
-  let InOperandList = !con(iops, (ops pred:$p));
-  let AsmString   = !strconcat(opc, !strconcat("${p}", asm));
-  let Pattern = pattern;
-  list<Predicate> Predicates = [IsARM];
-}
-
-// Same as I except it can optionally modify CPSR. Note it's modeled as
-// an input operand since by default it's a zero register. It will
-// become an implicit def once it's "flipped".
-class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
-         IndexMode im, Format f, string opc, string asm, string cstr,
-         list<dag> pattern>
-  : InstARM<opcod, am, sz, im, f, cstr> {
-  let OutOperandList = oops;
-  let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
-  let AsmString   = !strconcat(opc, !strconcat("${p}${s}", asm));
-  let Pattern = pattern;
-  list<Predicate> Predicates = [IsARM];
-}
-
-class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
-         string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
-      asm,"",pattern>;
-class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
-          string asm, list<dag> pattern>
-  : sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
-       asm,"",pattern>;
-class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
-          string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
-      asm, "", pattern>;
-class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
-           string asm, list<dag> pattern>
-  : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
-       asm, "", pattern>;
-class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
-          string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
-      asm, "", pattern>;
-class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
-          string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
-      asm, "", pattern>;
-class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
-          string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
-      asm, "", pattern>;
-class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
-            string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
-      asm, "", pattern>;
-
-// Pre-indexed ops
-class AI2pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
-            string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
-      asm, cstr, pattern>;
-class AI3pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
-            string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
-      asm, cstr, pattern>;
-
-// Post-indexed ops
-class AI2po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
-            string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
-      asm, cstr,pattern>;
-class AI3po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
-            string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
-      asm, cstr,pattern>;
-
-
-class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
-class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
-
+// Multiclass helpers...
+//
 
 /// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
 /// binop that produces a value.
@@ -574,54 +411,6 @@
                   Requires<[IsARM, HasV6]>;
 }
 
-// Special cases.
-class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
-         IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
-  : InstARM<opcod, am, sz, im, f, cstr> {
-  let OutOperandList = oops;
-  let InOperandList = iops;
-  let AsmString   = asm;
-  let Pattern = pattern;
-  list<Predicate> Predicates = [IsARM];
-}
-
-class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
-          list<dag> pattern>
-  : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
-       "", pattern>;
-class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
-           list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
-       "", pattern>;
-class AXI2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
-           list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
-       "", pattern>;
-class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm,
-           list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
-       "", pattern>;
-class AXI4<bits<4> opcod, dag oops, dag iops, Format f, string asm,
-           list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
-       "", pattern>;
-
-class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
-            list<dag> pattern>
-  : XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
-       "", pattern>;
-
-// BR_JT instructions
-class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
-       asm, "", pattern>;
-class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
-       asm, "", pattern>;
-class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
-       asm, "", pattern>;
-
 /// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
 /// setting carry bit. But it can optionally set CPSR.
 let Uses = [CPSR] in {




From clattner at apple.com  Thu Aug 28 18:43:27 2008
From: clattner at apple.com (Chris Lattner)
Date: Thu, 28 Aug 2008 16:43:27 -0700
Subject: [llvm-commits] [PATCH] Add DenseMap::lookup
In-Reply-To: <6a8523d60808281637k10ddcd05v19d199dd534c6812@mail.gmail.com>
References: <6a8523d60808281637k10ddcd05v19d199dd534c6812@mail.gmail.com>
Message-ID: <38C7195D-B685-4BCE-ADB6-7123E4AF1E16@apple.com>


On Aug 28, 2008, at 4:37 PM, Daniel Dunbar wrote:

> The attached patch adds DenseMap::lookup:
> +  /// lookup - Return the entry for the specified key, or a default
> +  /// value if no such entry exists.

lgtm, plz commit.

-Chris



From evan.cheng at apple.com  Thu Aug 28 18:48:31 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 28 Aug 2008 23:48:31 -0000
Subject: [llvm-commits] [llvm] r55521 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrInfo.cpp
 lib/Target/X86/X86InstrInfo.h test/CodeGen/X86/cmp2.ll
 test/CodeGen/X86/long-setcc.ll
Message-ID: <200808282348.m7SNmVF6012462@zion.cs.uiuc.edu>

Author: evancheng
Date: Thu Aug 28 18:48:31 2008
New Revision: 55521

URL: http://llvm.org/viewvc/llvm-project?rev=55521&view=rev
Log:
Swap fp comparison operands and change predicate to allow load folding.

Added:
    llvm/trunk/test/CodeGen/X86/cmp2.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.h
    llvm/trunk/test/CodeGen/X86/long-setcc.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=55521&r1=55520&r2=55521&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Aug 28 18:48:31 2008
@@ -1909,7 +1909,6 @@
 }
 
 
-
 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
 /// specific condition code. It returns a false if it cannot do a direct
 /// translation. X86CC is the translated CondCode.  LHS/RHS are modified as
@@ -1936,7 +1935,10 @@
         return true;
       }
     }
+  }
 
+  bool Flip = false;
+  if (!isFP) {
     switch (SetCCOpcode) {
     default: break;
     case ISD::SETEQ:  X86CC = X86::COND_E;  break;
@@ -1957,7 +1959,6 @@
     //  0 | 0 | 1 | X < Y
     //  1 | 0 | 0 | X == Y
     //  1 | 1 | 1 | unordered
-    bool Flip = false;
     switch (SetCCOpcode) {
     default: break;
     case ISD::SETUEQ:
@@ -1979,11 +1980,24 @@
     case ISD::SETUO: X86CC = X86::COND_P;  break;
     case ISD::SETO:  X86CC = X86::COND_NP; break;
     }
-    if (Flip)
+  }
+
+  if (X86CC == X86::COND_INVALID)
+    return false;
+
+  if (Flip)
+    std::swap(LHS, RHS);
+
+  if (isFP) {
+    bool LHSCanFold = ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse();
+    bool RHSCanFold = ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse();
+    if (LHSCanFold && !RHSCanFold) {
+      X86CC = X86::GetSwappedBranchCondition(static_cast<X86::CondCode>(X86CC));
       std::swap(LHS, RHS);
+    }
   }
 
-  return X86CC != X86::COND_INVALID;
+  return true;
 }
 
 /// hasFPCMov - is there a floating point cmov for the specific X86 condition

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=55521&r1=55520&r2=55521&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Aug 28 18:48:31 2008
@@ -1433,6 +1433,30 @@
   }
 }
 
+/// GetSwappedBranchCondition - Return the branch condition that would be
+/// the result of exchanging the two operands of a comparison without
+/// changing the result produced.
+/// e.g. COND_E to COND_E, COND_G -> COND_L
+X86::CondCode X86::GetSwappedBranchCondition(X86::CondCode CC) {
+  switch (CC) {
+  default: assert(0 && "Illegal condition code!");
+  case X86::COND_E:  return X86::COND_E;
+  case X86::COND_NE: return X86::COND_NE;
+  case X86::COND_L:  return X86::COND_G;
+  case X86::COND_LE: return X86::COND_GE;
+  case X86::COND_G:  return X86::COND_L;
+  case X86::COND_GE: return X86::COND_LE;
+  case X86::COND_B:  return X86::COND_A;
+  case X86::COND_BE: return X86::COND_AE;
+  case X86::COND_A:  return X86::COND_B;
+  case X86::COND_AE: return X86::COND_BE;
+  case X86::COND_P:  return X86::COND_P;
+  case X86::COND_NP: return X86::COND_NP;
+  case X86::COND_O:  return X86::COND_O;
+  case X86::COND_NO: return X86::COND_NO;
+  }
+}
+
 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
   const TargetInstrDesc &TID = MI->getDesc();
   if (!TID.isTerminator()) return false;
@@ -2373,7 +2397,8 @@
 bool X86InstrInfo::
 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
-  Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm()));
+  X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
+  Cond[0].setImm(GetOppositeBranchCondition(CC));
   return false;
 }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=55521&r1=55520&r2=55521&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Thu Aug 28 18:48:31 2008
@@ -54,6 +54,11 @@
   /// e.g. turning COND_E to COND_NE.
   CondCode GetOppositeBranchCondition(X86::CondCode CC);
 
+  /// GetSwappedBranchCondition - Return the branch condition that would be
+  /// the result of exchanging the two operands of a comparison without
+  /// changing the result produced.
+  /// e.g. COND_E to COND_E, COND_G -> COND_L
+  CondCode GetSwappedBranchCondition(X86::CondCode CC);
 }
   
 /// X86II - This namespace holds all of the target specific flags that

Added: llvm/trunk/test/CodeGen/X86/cmp2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmp2.ll?rev=55521&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/cmp2.ll (added)
+++ llvm/trunk/test/CodeGen/X86/cmp2.ll Thu Aug 28 18:48:31 2008
@@ -0,0 +1,18 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep ucomisd | grep CPI | count 2
+
+define i32 @test(double %A) nounwind  {
+ entry:
+ %tmp2 = fcmp ogt double %A, 1.500000e+02; <i1> [#uses=1]
+ %tmp5 = fcmp olt double %A, 7.500000e+01; <i1> [#uses=1]
+ %bothcond = or i1 %tmp2, %tmp5; <i1> [#uses=1]
+ br i1 %bothcond, label %bb8, label %bb12
+
+ bb8:; preds = %entry
+ %tmp9 = tail call i32 (...)* @foo( ) nounwind ; <i32> [#uses=1]
+ ret i32 %tmp9
+
+ bb12:; preds = %entry
+ ret i32 32
+}
+
+declare i32 @foo(...)

Modified: llvm/trunk/test/CodeGen/X86/long-setcc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/long-setcc.ll?rev=55521&r1=55520&r2=55521&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/long-setcc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/long-setcc.ll Thu Aug 28 18:48:31 2008
@@ -2,17 +2,17 @@
 ; RUN: llvm-as < %s | llc -march=x86 | grep shr | count 1
 ; RUN: llvm-as < %s | llc -march=x86 | grep xor | count 1
 
-define i1 @t1(i64 %x) {
+define i1 @t1(i64 %x) nounwind {
 	%B = icmp slt i64 %x, 0
 	ret i1 %B
 }
 
-define i1 @t2(i64 %x) {
+define i1 @t2(i64 %x) nounwind {
 	%tmp = icmp ult i64 %x, 4294967296
 	ret i1 %tmp
 }
 
-define i1 @t3(i32 %x) {
+define i1 @t3(i32 %x) nounwind {
 	%tmp = icmp ugt i32 %x, -1
 	ret i1 %tmp
 }




From gohman at apple.com  Thu Aug 28 19:48:35 2008
From: gohman at apple.com (Dan Gohman)
Date: Thu, 28 Aug 2008 17:48:35 -0700
Subject: [llvm-commits] [llvm] r55457 - in /llvm/trunk:
	include/llvm/CodeGen/SelectionDAGNodes.h	include/llvm/Target/TargetLowering.h
	lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	lib/CodeGen/SelectionDAG/SelectionDAG.cpp
	lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	lib/Target/TargetSelectionDAG.td
	lib/Target/X86/X86ISelLowering.cpp	lib/Target/X86/X86Instr64bit.td
	lib/Target/X86/X86InstrInfo.td
In-Reply-To: <764F54DD-8DFF-40E2-821D-1308B8B3606E@apple.com>
References: <200808280244.m7S2ioDI016151@zion.cs.uiuc.edu>
	<3D1FD3C4-4F1D-423E-BBF1-3D184394890A@apple.com>
	<764F54DD-8DFF-40E2-821D-1308B8B3606E@apple.com>
Message-ID: <AE3860E4-F22B-4251-89C6-F8D79FD72C47@apple.com>


On Aug 28, 2008, at 1:14 PM, Dale Johannesen wrote:

>
> On Aug 28, 2008, at 11:14 AMPDT, Dan Gohman wrote:
>>
>>
>> MemSDNode has a MemoryVT member. This is used for truncating
>> stores and extending loads to indicate the type of the actual
>> memory access. We don't have extending or truncating atomics,
>> so I believe it's redundant in AtomicSDNode.
>>
>> Perhaps MemoryVT could be moved out of MemSDNode and into
>> LSBaseSDNode? That would allow a new MVT member to be added
>> to AtomicSDNode without an overall size increase.
>
> Maybe, but MemoryVT kind of belongs in the MemSDNode, doesn't it?

Not necessarily. The purpose of MemoryVT is to provide the type
when it differs from what the load or store would normally have,
in the case of an extending load or truncating store.

Dan



From daniel at zuster.org  Thu Aug 28 19:48:45 2008
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 29 Aug 2008 00:48:45 -0000
Subject: [llvm-commits] [llvm] r55523 -
	/llvm/trunk/include/llvm/ADT/DenseMap.h
Message-ID: <200808290048.m7T0mjpH014353@zion.cs.uiuc.edu>

Author: ddunbar
Date: Thu Aug 28 19:48:44 2008
New Revision: 55523

URL: http://llvm.org/viewvc/llvm-project?rev=55523&view=rev
Log:
Add DenseMap::lookup:
  /// lookup - Return the entry for the specified key, or a default
  /// constructed value if no such entry exists.

Modified:
    llvm/trunk/include/llvm/ADT/DenseMap.h

Modified: llvm/trunk/include/llvm/ADT/DenseMap.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/DenseMap.h?rev=55523&r1=55522&r2=55523&view=diff

==============================================================================
--- llvm/trunk/include/llvm/ADT/DenseMap.h (original)
+++ llvm/trunk/include/llvm/ADT/DenseMap.h Thu Aug 28 19:48:44 2008
@@ -189,6 +189,15 @@
     return end();
   }
   
+  /// lookup - Return the entry for the specified key, or a default
+  /// constructed value if no such entry exists.
+  ValueT lookup(const KeyT &Val) const {
+    BucketT *TheBucket;
+    if (LookupBucketFor(Val, TheBucket))
+      return TheBucket->second;
+    return ValueT();
+  }
+
   std::pair<iterator, bool> insert(const std::pair<KeyT, ValueT> &KV) {
     BucketT *TheBucket;
     if (LookupBucketFor(KV.first, TheBucket))




From evan.cheng at apple.com  Fri Aug 29 01:41:12 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 29 Aug 2008 06:41:12 -0000
Subject: [llvm-commits] [llvm] r55528 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td ARMInstrThumb.td
Message-ID: <200808290641.m7T6fDgJ024849@zion.cs.uiuc.edu>

Author: evancheng
Date: Fri Aug 29 01:41:12 2008
New Revision: 55528

URL: http://llvm.org/viewvc/llvm-project?rev=55528&view=rev
Log:
More refactoring.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=55528&r1=55527&r2=55528&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Aug 29 01:41:12 2008
@@ -226,3 +226,58 @@
 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
   list<Predicate> Predicates = [IsARM, HasV6];
 }
+
+//===----------------------------------------------------------------------===//
+//
+// Thumb Instruction Format Definitions.
+//
+
+
+// TI - Thumb instruction.
+
+class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
+             string asm, string cstr, list<dag> pattern>
+  // FIXME: Set all opcodes to 0 for now.
+  : InstARM<0, am, sz, IndexModeNone, ThumbFrm, cstr> {
+  let OutOperandList = outs;
+  let InOperandList = ins;
+  let AsmString   = asm;
+  let Pattern = pattern;
+  list<Predicate> Predicates = [IsThumb];
+}
+
+class TI<dag outs, dag ins, string asm, list<dag> pattern>
+  : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
+class TI1<dag outs, dag ins, string asm, list<dag> pattern>
+  : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
+class TI2<dag outs, dag ins, string asm, list<dag> pattern>
+  : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
+class TI4<dag outs, dag ins, string asm, list<dag> pattern>
+  : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
+class TIs<dag outs, dag ins, string asm, list<dag> pattern>
+  : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
+
+// Two-address instructions
+class TIt<dag outs, dag ins, string asm, list<dag> pattern>
+  : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
+
+// BL, BLX(1) are translated by assembler into two instructions
+class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
+  : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
+
+// BR_JT instructions
+class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
+  : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
+
+
+//===----------------------------------------------------------------------===//
+
+
+// ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
+class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
+  list<Predicate> Predicates = [IsThumb];
+}
+
+class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
+  list<Predicate> Predicates = [IsThumb, HasV5T];
+}

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=55528&r1=55527&r2=55528&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 29 01:41:12 2008
@@ -18,51 +18,6 @@
 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
                       [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
 
-// TI - Thumb instruction.
-
-// ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
-class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
-  list<Predicate> Predicates = [IsThumb];
-}
-
-class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
-  list<Predicate> Predicates = [IsThumb, HasV5T];
-}
-
-class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
-             string asm, string cstr, list<dag> pattern>
-  // FIXME: Set all opcodes to 0 for now.
-  : InstARM<0, am, sz, IndexModeNone, ThumbFrm, cstr> {
-  let OutOperandList = outs;
-  let InOperandList = ins;
-  let AsmString   = asm;
-  let Pattern = pattern;
-  list<Predicate> Predicates = [IsThumb];
-}
-
-class TI<dag outs, dag ins, string asm, list<dag> pattern>
-  : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
-class TI1<dag outs, dag ins, string asm, list<dag> pattern>
-  : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
-class TI2<dag outs, dag ins, string asm, list<dag> pattern>
-  : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
-class TI4<dag outs, dag ins, string asm, list<dag> pattern>
-  : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
-class TIs<dag outs, dag ins, string asm, list<dag> pattern>
-  : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
-
-// Two-address instructions
-class TIt<dag outs, dag ins, string asm, list<dag> pattern>
-  : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
-
-// BL, BLX(1) are translated by assembler into two instructions
-class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
-  : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
-
-// BR_JT instructions
-class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
-  : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
-
 def imm_neg_XFORM : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(-(int)N->getValue(), MVT::i32);
 }]>;




From daniel at zuster.org  Fri Aug 29 02:30:15 2008
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 29 Aug 2008 07:30:15 -0000
Subject: [llvm-commits] [llvm] r55529 - in /llvm/trunk/include/llvm:
 Function.h GlobalAlias.h GlobalValue.h GlobalVariable.h
Message-ID: <200808290730.m7T7UGv3026422@zion.cs.uiuc.edu>

Author: ddunbar
Date: Fri Aug 29 02:30:15 2008
New Revision: 55529

URL: http://llvm.org/viewvc/llvm-project?rev=55529&view=rev
Log:
Add GlobalValue::{removeFromParent,eraseFromParent}

Modified:
    llvm/trunk/include/llvm/Function.h
    llvm/trunk/include/llvm/GlobalAlias.h
    llvm/trunk/include/llvm/GlobalValue.h
    llvm/trunk/include/llvm/GlobalVariable.h

Modified: llvm/trunk/include/llvm/Function.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Function.h?rev=55529&r1=55528&r2=55529&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Function.h (original)
+++ llvm/trunk/include/llvm/Function.h Fri Aug 29 02:30:15 2008
@@ -228,12 +228,12 @@
   /// removeFromParent - This method unlinks 'this' from the containing module,
   /// but does not delete it.
   ///
-  void removeFromParent();
+  virtual void removeFromParent();
 
   /// eraseFromParent - This method unlinks 'this' from the containing module
   /// and deletes it.
   ///
-  void eraseFromParent();
+  virtual void eraseFromParent();
 
 
   /// Get the underlying elements of the Function... the basic block list is

Modified: llvm/trunk/include/llvm/GlobalAlias.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/GlobalAlias.h?rev=55529&r1=55528&r2=55529&view=diff

==============================================================================
--- llvm/trunk/include/llvm/GlobalAlias.h (original)
+++ llvm/trunk/include/llvm/GlobalAlias.h Fri Aug 29 02:30:15 2008
@@ -55,12 +55,12 @@
   /// removeFromParent - This method unlinks 'this' from the containing module,
   /// but does not delete it.
   ///
-  void removeFromParent();
+  virtual void removeFromParent();
 
   /// eraseFromParent - This method unlinks 'this' from the containing module
   /// and deletes it.
   ///
-  void eraseFromParent();
+  virtual void eraseFromParent();
 
   /// set/getAliasee - These methods retrive and set alias target.
   void setAliasee(Constant* GV);

Modified: llvm/trunk/include/llvm/GlobalValue.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/GlobalValue.h?rev=55529&r1=55528&r2=55529&view=diff

==============================================================================
--- llvm/trunk/include/llvm/GlobalValue.h (original)
+++ llvm/trunk/include/llvm/GlobalValue.h Fri Aug 29 02:30:15 2008
@@ -142,6 +142,14 @@
   /// value is outside of the current translation unit...
   virtual bool isDeclaration() const = 0;
 
+  /// removeFromParent - This method unlinks 'this' from the containing module,
+  /// but does not delete it.
+  virtual void removeFromParent() = 0;
+
+  /// eraseFromParent - This method unlinks 'this' from the containing module
+  /// and deletes it.
+  virtual void eraseFromParent() = 0;
+
   /// getParent - Get the module that this global value is contained inside
   /// of...
   inline Module *getParent() { return Parent; }

Modified: llvm/trunk/include/llvm/GlobalVariable.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/GlobalVariable.h?rev=55529&r1=55528&r2=55529&view=diff

==============================================================================
--- llvm/trunk/include/llvm/GlobalVariable.h (original)
+++ llvm/trunk/include/llvm/GlobalVariable.h Fri Aug 29 02:30:15 2008
@@ -122,12 +122,12 @@
   /// removeFromParent - This method unlinks 'this' from the containing module,
   /// but does not delete it.
   ///
-  void removeFromParent();
+  virtual void removeFromParent();
 
   /// eraseFromParent - This method unlinks 'this' from the containing module
   /// and deletes it.
   ///
-  void eraseFromParent();
+  virtual void eraseFromParent();
 
   /// Override Constant's implementation of this method so we can
   /// replace constant initializers.




From evan.cheng at apple.com  Fri Aug 29 02:36:25 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 29 Aug 2008 07:36:25 -0000
Subject: [llvm-commits] [llvm] r55530 -
	/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Message-ID: <200808290736.m7T7aPTM027872@zion.cs.uiuc.edu>

Author: evancheng
Date: Fri Aug 29 02:36:24 2008
New Revision: 55530

URL: http://llvm.org/viewvc/llvm-project?rev=55530&view=rev
Log:
MVN is addrmode1.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=55530&r1=55529&r2=55530&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Aug 29 02:36:24 2008
@@ -338,7 +338,7 @@
 // Multiclass helpers...
 //
 
-/// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
+/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
 /// binop that produces a value.
 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
   def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
@@ -873,13 +873,13 @@
 defm EOR   : AsI1_bin_irs<0x1, "eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
 defm BIC   : AsI1_bin_irs<0xE, "bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
 
-def  MVNr  : AsI<0xE, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
-                 "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
-def  MVNs  : AsI<0xE, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
-                 "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
+def  MVNr  : AsI1<0xE, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
+                  "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
+def  MVNs  : AsI1<0xE, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
+                  "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
 let isReMaterializable = 1 in
-def  MVNi  : AsI<0xE, (outs GPR:$dst), (ins so_imm:$imm), DPRdIm,
-                 "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
+def  MVNi  : AsI1<0xE, (outs GPR:$dst), (ins so_imm:$imm), DPRdIm,
+                  "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
 
 def : ARMPat<(and   GPR:$src, so_imm_not:$imm),
              (BICri GPR:$src, so_imm_not:$imm)>;




From evan.cheng at apple.com  Fri Aug 29 02:40:52 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 29 Aug 2008 07:40:52 -0000
Subject: [llvm-commits] [llvm] r55531 -
	/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
Message-ID: <200808290740.m7T7eq7X029498@zion.cs.uiuc.edu>

Author: evancheng
Date: Fri Aug 29 02:40:52 2008
New Revision: 55531

URL: http://llvm.org/viewvc/llvm-project?rev=55531&view=rev
Log:
addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=55531&r1=55530&r2=55531&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Aug 29 02:40:52 2008
@@ -50,7 +50,6 @@
 def VFPFrm      : Format<26>;
 
 
-
 //===----------------------------------------------------------------------===//
 
 // ARM Instruction templates.
@@ -59,6 +58,8 @@
 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
               Format f, string cstr>
   : Instruction {
+  field bits<32> Inst;
+
   let Namespace = "ARM";
 
   bits<4> Opcode = opcod;
@@ -122,11 +123,17 @@
 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
   : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
-      asm, "", pattern>;
+      asm, "", pattern> {
+  let Inst{5-6}  = 0;
+  let Inst{7-10} = opcod;
+}
 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
            string asm, list<dag> pattern>
   : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
-       asm, "", pattern>;
+       asm, "", pattern> {
+  let Inst{5-6}  = 0;
+  let Inst{7-10} = opcod;
+}
 class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
   : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,




From evan.cheng at apple.com  Fri Aug 29 02:42:03 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 29 Aug 2008 07:42:03 -0000
Subject: [llvm-commits] [llvm] r55533 - /llvm/trunk/lib/Target/ARM/Makefile
Message-ID: <200808290742.m7T7g3nx029980@zion.cs.uiuc.edu>

Author: evancheng
Date: Fri Aug 29 02:42:03 2008
New Revision: 55533

URL: http://llvm.org/viewvc/llvm-project?rev=55533&view=rev
Log:
TableGen'ing instruction encodings.

Modified:
    llvm/trunk/lib/Target/ARM/Makefile

Modified: llvm/trunk/lib/Target/ARM/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Makefile?rev=55533&r1=55532&r2=55533&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/Makefile (original)
+++ llvm/trunk/lib/Target/ARM/Makefile Fri Aug 29 02:42:03 2008
@@ -15,7 +15,8 @@
 BUILT_SOURCES = ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc \
                 ARMGenRegisterInfo.inc ARMGenInstrNames.inc \
                 ARMGenInstrInfo.inc ARMGenAsmWriter.inc \
-                ARMGenDAGISel.inc ARMGenSubtarget.inc
+                ARMGenDAGISel.inc ARMGenSubtarget.inc \
+                ARMGenCodeEmitter.inc
 
 DIRS = AsmPrinter
 




From daniel at zuster.org  Fri Aug 29 02:43:51 2008
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 29 Aug 2008 00:43:51 -0700
Subject: [llvm-commits] [PATCH] Add -fvisibility-inlines-hidden
Message-ID: <6a8523d60808290043v53d17f44tbc613570c01be6dd@mail.gmail.com>

The attached patch adds the configure magic to turn on
-fvisibility-inlines-hidden
by default if the compiler supports it. The patch doesn't contain the
configure changes,
you will have to regenerate it yourself to test.

I really have no idea how to use autoconf so feedback appreciated.

 - Daniel
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From baldrick at free.fr  Thu Aug 28 14:50:00 2008
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 28 Aug 2008 21:50:00 +0200
Subject: [llvm-commits] [llvm-gcc-4.2] r55184 - in
	/llvm-gcc-4.2/trunk/gcc: passes.c tree-ssa-ccp.c
In-Reply-To: <200808221707.m7MH7Wr5027215@zion.cs.uiuc.edu>
References: <200808221707.m7MH7Wr5027215@zion.cs.uiuc.edu>
Message-ID: <200808282150.00830.baldrick@free.fr>

Hi Rafael, you forgot the "LLVM local" markers here:

> ==============================================================================
> --- llvm-gcc-4.2/trunk/gcc/tree-ssa-ccp.c (original)
> +++ llvm-gcc-4.2/trunk/gcc/tree-ssa-ccp.c Fri Aug 22 12:07:31 2008
> @@ -2544,6 +2544,11 @@
>  	      continue;
>  	    }
>  	  fcode = DECL_FUNCTION_CODE (callee);
> +	  if (fcode != BUILT_IN_CONSTANT_P)
> +	    {
> +	      bsi_next (&i);
> +	      continue;
> +	    }
>  
>  	  result = ccp_fold_builtin (*stmtp, call);
>  	  if (!result)
> @@ -2621,12 +2626,10 @@
>    NULL,					/* next */
>    0,					/* static_pass_number */
>    0,					/* tv_id */
> -  PROP_cfg | PROP_ssa | PROP_alias,	/* properties_required */
> +  PROP_cfg,	/* properties_required */
>    0,					/* properties_provided */
>    0,					/* properties_destroyed */
>    0,					/* todo_flags_start */
> -  TODO_dump_func
> -    | TODO_verify_ssa
> -    | TODO_update_ssa,			/* todo_flags_finish */
> +  TODO_dump_func,			/* todo_flags_finish */
>    0					/* letter */
>  };

Ciao,

Duncan.


From baldrick at free.fr  Fri Aug 29 10:14:27 2008
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 29 Aug 2008 17:14:27 +0200
Subject: [llvm-commits] [llvm] r55457 - in /llvm/trunk:
	include/llvm/CodeGen/SelectionDAGNodes.h
	include/llvm/Target/TargetLowering.h
	lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	lib/CodeGen/SelectionDAG/SelectionDAG.cpp
	lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
	lib/Target/TargetSelectionDAG.td lib/Target/X86/X86ISelLowering.cpp
	lib/Target/X86/X86Instr64bit.td lib/Target/X86/X86InstrInfo.td
In-Reply-To: <3D1FD3C4-4F1D-423E-BBF1-3D184394890A@apple.com>
References: <200808280244.m7S2ioDI016151@zion.cs.uiuc.edu>
	<3D1FD3C4-4F1D-423E-BBF1-3D184394890A@apple.com>
Message-ID: <200808291714.27366.baldrick@free.fr>

> MemSDNode has a MemoryVT member. This is used for truncating
> stores and extending loads to indicate the type of the actual
> memory access. We don't have extending or truncating atomics,
> so I believe it's redundant in AtomicSDNode.

On the other hand, having ATOMIC_LOAD_ADD that acts on an i8
seems quite analogous to an extending load to me.  So rather
than introducing new names ATOMIC_LOAD_ADD_{8,16,32,64}, how
about using MemoryVT to indicate the size of the partial word
being acted on (i.e. i8, i16, i32, i64) instead?

Ciao,

Duncan.


From baldrick at free.fr  Fri Aug 29 10:19:00 2008
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 29 Aug 2008 17:19:00 +0200
Subject: [llvm-commits]
 =?iso-8859-1?q?=5Bllvm=5D_r55457_-_in_/llvm/trunk?=
 =?iso-8859-1?q?=3A_include/llvm/CodeGen/SelectionDAGNodes=2Eh=09include/l?=
 =?iso-8859-1?q?lvm/Target/TargetLowering=2Eh_lib/CodeGen/SelectionDAG/Leg?=
 =?iso-8859-1?q?alizeDAG=2Ecpp_lib/CodeGen/SelectionDAG/SelectionDAG=2Ecpp?=
 =?iso-8859-1?q?_lib/CodeGen/SelectionDAG/SelectionDAGISel=2Ecpp=09lib/Tar?=
 =?iso-8859-1?q?get/TargetSelectionDAG=2Etd_lib/Target/X86/X86ISelLowering?=
 =?iso-8859-1?q?=2Ecpp=09lib/Target/X86/X86Instr64bit=2Etd_lib/Target/X86/?=
 =?iso-8859-1?q?X86InstrInfo=2Etd?=
In-Reply-To: <AE3860E4-F22B-4251-89C6-F8D79FD72C47@apple.com>
References: <200808280244.m7S2ioDI016151@zion.cs.uiuc.edu>
	<764F54DD-8DFF-40E2-821D-1308B8B3606E@apple.com>
	<AE3860E4-F22B-4251-89C6-F8D79FD72C47@apple.com>
Message-ID: <200808291719.00403.baldrick@free.fr>

> Not necessarily. The purpose of MemoryVT is to provide the type
> when it differs from what the load or store would normally have,
> in the case of an extending load or truncating store.

This occurs exactly when the type being loaded is not legal for
the target.  For example, suppose in the IR you load an i8, but
codegen on a target for which i8 is not legal (but i32 is).  This
gets turned into an extending load with MemoryVT equal to i8 and
result type equal to i32.  It seems quite similar to the situation
of doing an atomic operation on an i8 in the IR: it would get
legalized into an extending operation with MemoryVT equal to i8
and (assuming the operation returned an i8 value) returning an i32.

Ciao,

Duncan.


From sabre at nondot.org  Fri Aug 29 12:12:15 2008
From: sabre at nondot.org (Chris Lattner)
Date: Fri, 29 Aug 2008 17:12:15 -0000
Subject: [llvm-commits] [llvm] r55539 - in /llvm/trunk:
 lib/AsmParser/llvmAsmParser.y test/Assembler/numbered-values.ll
Message-ID: <200808291712.m7THCFi4028107@zion.cs.uiuc.edu>

Author: lattner
Date: Fri Aug 29 12:12:13 2008
New Revision: 55539

URL: http://llvm.org/viewvc/llvm-project?rev=55539&view=rev
Log:
Add support for parsing .ll files that have numbers in front of
nameless values, such as:

%3 = add i32 4, 2

This fixes the first half of PR2480


Added:
    llvm/trunk/test/Assembler/numbered-values.ll
Modified:
    llvm/trunk/lib/AsmParser/llvmAsmParser.y

Modified: llvm/trunk/lib/AsmParser/llvmAsmParser.y
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/llvmAsmParser.y?rev=55539&r1=55538&r2=55539&view=diff

==============================================================================
--- llvm/trunk/lib/AsmParser/llvmAsmParser.y (original)
+++ llvm/trunk/lib/AsmParser/llvmAsmParser.y Fri Aug 29 12:12:13 2008
@@ -249,10 +249,12 @@
 //               Code to handle definitions of all the types
 //===----------------------------------------------------------------------===//
 
-static void InsertValue(Value *V, ValueList &ValueTab = CurFun.Values) {
+/// InsertValue - Insert a value into the value table.  If it is named, this
+/// returns -1, otherwise it returns the slot number for the value.
+static int InsertValue(Value *V, ValueList &ValueTab = CurFun.Values) {
   // Things that have names or are void typed don't get slot numbers
   if (V->hasName() || (V->getType() == Type::VoidTy))
-    return;
+    return -1;
 
   // In the case of function values, we have to allow for the forward reference
   // of basic blocks, which are included in the numbering. Consequently, we keep
@@ -262,10 +264,11 @@
     if (ValueTab.size() <= CurFun.NextValNum)
       ValueTab.resize(CurFun.NextValNum+1);
     ValueTab[CurFun.NextValNum++] = V;
-    return;
+    return CurFun.NextValNum-1;
   } 
   // For all other lists, its okay to just tack it on the back of the vector.
   ValueTab.push_back(V);
+  return ValueTab.size()-1;
 }
 
 static const Type *getTypeVal(const ValID &D, bool DoNotImprovise = false) {
@@ -1084,7 +1087,7 @@
 %token CC_TOK CCC_TOK FASTCC_TOK COLDCC_TOK X86_STDCALLCC_TOK X86_FASTCALLCC_TOK
 %token X86_SSECALLCC_TOK
 %token DATALAYOUT
-%type <UIntVal> OptCallingConv
+%type <UIntVal> OptCallingConv LocalNumber
 %type <ParamAttrs> OptParamAttrs ParamAttr 
 %type <ParamAttrs> OptFuncAttrs  FuncAttr
 
@@ -1177,6 +1180,12 @@
     CHECK_FOR_ERROR
   };
 
+LocalNumber : LOCALVAL_ID '=' {
+  $$ = $1;
+  CHECK_FOR_ERROR
+};
+
+
 GlobalName : GLOBALVAR | ATSTRINGCONSTANT ;
 
 OptGlobalAssign : GlobalAssign
@@ -2673,7 +2682,7 @@
 // Basic blocks are terminated by branching instructions: 
 // br, br/cc, switch, ret
 //
-BasicBlock : InstructionList OptLocalAssign BBTerminatorInst  {
+BasicBlock : InstructionList OptLocalAssign BBTerminatorInst {
     setValueName($3, $2);
     CHECK_FOR_ERROR
     InsertValue($3);
@@ -2682,6 +2691,19 @@
     CHECK_FOR_ERROR
   };
 
+BasicBlock : InstructionList LocalNumber BBTerminatorInst {
+  CHECK_FOR_ERROR
+  int ValNum = InsertValue($3);
+  if (ValNum != (int)$2)
+    GEN_ERROR("Result value number %" + utostr($2) +
+              " is incorrect, expected %" + utostr((unsigned)ValNum));
+  
+  $1->getInstList().push_back($3);
+  $$ = $1;
+  CHECK_FOR_ERROR
+};
+
+
 InstructionList : InstructionList Inst {
     if (CastInst *CI1 = dyn_cast<CastInst>($2))
       if (CastInst *CI2 = dyn_cast<CastInst>(CI1->getOperand(0)))
@@ -2901,6 +2923,18 @@
     CHECK_FOR_ERROR
   };
 
+Inst : LocalNumber InstVal {
+    CHECK_FOR_ERROR
+    int ValNum = InsertValue($2);
+  
+    if (ValNum != (int)$1)
+      GEN_ERROR("Result value number %" + utostr($1) +
+                " is incorrect, expected %" + utostr((unsigned)ValNum));
+
+    $$ = $2;
+    CHECK_FOR_ERROR
+  };
+
 
 PHIList : Types '[' ValueRef ',' ValueRef ']' {    // Used for PHI nodes
     if (!UpRefs.empty())

Added: llvm/trunk/test/Assembler/numbered-values.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/numbered-values.ll?rev=55539&view=auto

==============================================================================
--- llvm/trunk/test/Assembler/numbered-values.ll (added)
+++ llvm/trunk/test/Assembler/numbered-values.ll Fri Aug 29 12:12:13 2008
@@ -0,0 +1,16 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis
+; PR2480
+
+define i32 @test(i32 %X) nounwind {
+entry:
+	%X_addr = alloca i32		; <i32*> [#uses=2]
+	%retval = alloca i32		; <i32*> [#uses=2]
+	%0 = alloca i32		; <i32*>:0 [#uses=2]
+	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
+	store i32 %X, i32* %X_addr
+	%1 = load i32* %X_addr, align 4		; <i32>:1 [#uses=1]
+	mul i32 %1, 4		; <i32>:2 [#uses=1]
+	%3 = add i32 %2, 123		; <i32>:3 [#uses=1]
+	store i32 %3, i32* %0, align 4
+	ret i32 %3
+}




From sabre at nondot.org  Fri Aug 29 12:18:27 2008
From: sabre at nondot.org (Chris Lattner)
Date: Fri, 29 Aug 2008 17:18:27 -0000
Subject: [llvm-commits] [llvm] r55540 -
	/llvm/trunk/test/CodeGen/Alpha/mul5.ll
Message-ID: <200808291718.m7THIRw4028273@zion.cs.uiuc.edu>

Author: lattner
Date: Fri Aug 29 12:18:26 2008
New Revision: 55540

URL: http://llvm.org/viewvc/llvm-project?rev=55540&view=rev
Log:
allow this to pass.

Modified:
    llvm/trunk/test/CodeGen/Alpha/mul5.ll

Modified: llvm/trunk/test/CodeGen/Alpha/mul5.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Alpha/mul5.ll?rev=55540&r1=55539&r2=55540&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Alpha/mul5.ll (original)
+++ llvm/trunk/test/CodeGen/Alpha/mul5.ll Fri Aug 29 12:18:26 2008
@@ -1,7 +1,5 @@
 ; Make sure this testcase does not use mulq
-; RUN: llvm-as < %s | llc -march=alpha | \
-; RUN:   not grep -i mul
-; XFAIL: *
+; RUN: llvm-as < %s | llc -march=alpha | not grep -i mul
 
 define i64 @foo1(i64 %x) {
 entry:
@@ -21,24 +19,6 @@
         ret i64 %tmp.1
 }
 
-define i64 @foo4ln(i64 %x) {
-entry:
-        %tmp.1 = mul i64 %x, 508                ; <i64> [#uses=1]
-        ret i64 %tmp.1
-}
-
-define i64 @foo4ln_more(i64 %x) {
-entry:
-        %tmp.1 = mul i64 %x, 252                ; <i64> [#uses=1]
-        ret i64 %tmp.1
-}
-
-define i64 @foo1n(i64 %x) {
-entry:
-        %tmp.1 = mul i64 %x, 511                ; <i64> [#uses=1]
-        ret i64 %tmp.1
-}
-
 define i64 @foo8l(i64 %x) {
 entry:
         %tmp.1 = mul i64 %x, 768                ; <i64> [#uses=1]




From sabre at nondot.org  Fri Aug 29 12:19:30 2008
From: sabre at nondot.org (Chris Lattner)
Date: Fri, 29 Aug 2008 17:19:30 -0000
Subject: [llvm-commits] [llvm] r55541 - /llvm/trunk/lib/VMCore/AsmWriter.cpp
Message-ID: <200808291719.m7THJUEf028328@zion.cs.uiuc.edu>

Author: lattner
Date: Fri Aug 29 12:19:30 2008
New Revision: 55541

URL: http://llvm.org/viewvc/llvm-project?rev=55541&view=rev
Log:
Asmprint nameless instructions as:

%4 = add ...

instead of:

add ...    ; 4

This makes opt -print-cfg output actually usable and makes .ll files
generally easier to read.  This fixes PR2480

Modified:
    llvm/trunk/lib/VMCore/AsmWriter.cpp

Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=55541&r1=55540&r2=55541&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/trunk/lib/VMCore/AsmWriter.cpp Fri Aug 29 12:19:30 2008
@@ -1486,7 +1486,7 @@
     printType(V.getType());
     Out << '>';
 
-    if (!V.hasName()) {
+    if (!V.hasName() && !isa<Instruction>(V)) {
       int SlotNum;
       if (const GlobalValue *GV = dyn_cast<GlobalValue>(&V))
         SlotNum = Machine.getGlobalSlot(GV);
@@ -1511,6 +1511,13 @@
   if (I.hasName()) {
     PrintLLVMName(Out, &I);
     Out << " = ";
+  } else if (I.getType() != Type::VoidTy) {
+    // Print out the def slot taken.
+    int SlotNum = Machine.getLocalSlot(&I);
+    if (SlotNum == -1)
+      Out << "<badref> = ";
+    else
+      Out << '%' << SlotNum << " = ";
   }
 
   // If this is a volatile load or store, print out the volatile marker.




From sabre at nondot.org  Fri Aug 29 12:20:18 2008
From: sabre at nondot.org (Chris Lattner)
Date: Fri, 29 Aug 2008 17:20:18 -0000
Subject: [llvm-commits] [llvm] r55542 - in /llvm/trunk/lib/AsmParser:
 llvmAsmParser.cpp.cvs llvmAsmParser.h.cvs llvmAsmParser.y.cvs
Message-ID: <200808291720.m7THKJDc028400@zion.cs.uiuc.edu>

Author: lattner
Date: Fri Aug 29 12:20:18 2008
New Revision: 55542

URL: http://llvm.org/viewvc/llvm-project?rev=55542&view=rev
Log:
regenerate

Modified:
    llvm/trunk/lib/AsmParser/llvmAsmParser.cpp.cvs
    llvm/trunk/lib/AsmParser/llvmAsmParser.h.cvs
    llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs

Modified: llvm/trunk/lib/AsmParser/llvmAsmParser.cpp.cvs
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/llvmAsmParser.cpp.cvs?rev=55542&r1=55541&r2=55542&view=diff

==============================================================================
--- llvm/trunk/lib/AsmParser/llvmAsmParser.cpp.cvs (original)
+++ llvm/trunk/lib/AsmParser/llvmAsmParser.cpp.cvs Fri Aug 29 12:20:18 2008
@@ -390,7 +390,7 @@
 
 
 /* Copy the first part of user declarations.  */
-#line 14 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 14 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
 
 #include "ParserInternals.h"
 #include "llvm/CallingConv.h"
@@ -629,10 +629,12 @@
 //               Code to handle definitions of all the types
 //===----------------------------------------------------------------------===//
 
-static void InsertValue(Value *V, ValueList &ValueTab = CurFun.Values) {
+/// InsertValue - Insert a value into the value table.  If it is named, this
+/// returns -1, otherwise it returns the slot number for the value.
+static int InsertValue(Value *V, ValueList &ValueTab = CurFun.Values) {
   // Things that have names or are void typed don't get slot numbers
   if (V->hasName() || (V->getType() == Type::VoidTy))
-    return;
+    return -1;
 
   // In the case of function values, we have to allow for the forward reference
   // of basic blocks, which are included in the numbering. Consequently, we keep
@@ -642,10 +644,11 @@
     if (ValueTab.size() <= CurFun.NextValNum)
       ValueTab.resize(CurFun.NextValNum+1);
     ValueTab[CurFun.NextValNum++] = V;
-    return;
+    return CurFun.NextValNum-1;
   } 
   // For all other lists, its okay to just tack it on the back of the vector.
   ValueTab.push_back(V);
+  return ValueTab.size()-1;
 }
 
 static const Type *getTypeVal(const ValID &D, bool DoNotImprovise = false) {
@@ -1364,7 +1367,7 @@
 
 #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
 typedef union YYSTYPE
-#line 967 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 970 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
 {
   llvm::Module                           *ModuleVal;
   llvm::Function                         *FunctionVal;
@@ -1413,7 +1416,7 @@
   llvm::FCmpInst::Predicate         FPredicate;
 }
 /* Line 193 of yacc.c.  */
-#line 1417 "llvmAsmParser.tab.c"
+#line 1420 "llvmAsmParser.tab.c"
 	YYSTYPE;
 # define yystype YYSTYPE /* obsolescent; will be withdrawn */
 # define YYSTYPE_IS_DECLARED 1
@@ -1426,7 +1429,7 @@
 
 
 /* Line 216 of yacc.c.  */
-#line 1430 "llvmAsmParser.tab.c"
+#line 1433 "llvmAsmParser.tab.c"
 
 #ifdef short
 # undef short
@@ -1641,16 +1644,16 @@
 /* YYFINAL -- State number of the termination state.  */
 #define YYFINAL  44
 /* YYLAST -- Last index in YYTABLE.  */
-#define YYLAST   2381
+#define YYLAST   2386
 
 /* YYNTOKENS -- Number of terminals.  */
 #define YYNTOKENS  171
 /* YYNNTS -- Number of nonterminals.  */
-#define YYNNTS  86
+#define YYNNTS  87
 /* YYNRULES -- Number of rules.  */
-#define YYNRULES  343
+#define YYNRULES  346
 /* YYNRULES -- Number of states.  */
-#define YYNSTATES  702
+#define YYNSTATES  707
 
 /* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX.  */
 #define YYUNDEFTOK  2
@@ -1718,40 +1721,40 @@
       79,    81,    83,    85,    87,    89,    91,    93,    95,    97,
       99,   101,   103,   105,   107,   109,   111,   113,   115,   117,
      119,   121,   123,   125,   127,   129,   130,   135,   136,   139,
-     140,   142,   144,   146,   147,   150,   152,   154,   156,   158,
-     160,   162,   164,   166,   168,   169,   171,   173,   175,   176,
-     178,   180,   181,   183,   185,   187,   189,   190,   192,   194,
-     195,   197,   199,   201,   203,   205,   207,   210,   212,   214,
-     216,   218,   220,   222,   224,   226,   228,   231,   232,   235,
-     237,   239,   241,   243,   245,   247,   248,   251,   252,   255,
-     256,   259,   260,   264,   267,   268,   270,   271,   275,   277,
-     280,   282,   284,   286,   288,   290,   292,   294,   296,   298,
-     302,   304,   307,   313,   319,   325,   331,   335,   338,   344,
-     349,   352,   354,   356,   358,   362,   364,   368,   370,   371,
-     373,   377,   382,   386,   390,   395,   400,   404,   411,   417,
+     140,   143,   145,   147,   149,   150,   153,   155,   157,   159,
+     161,   163,   165,   167,   169,   171,   172,   174,   176,   178,
+     179,   181,   183,   184,   186,   188,   190,   192,   193,   195,
+     197,   198,   200,   202,   204,   206,   208,   210,   213,   215,
+     217,   219,   221,   223,   225,   227,   229,   231,   234,   235,
+     238,   240,   242,   244,   246,   248,   250,   251,   254,   255,
+     258,   259,   262,   263,   267,   270,   271,   273,   274,   278,
+     280,   283,   285,   287,   289,   291,   293,   295,   297,   299,
+     301,   305,   307,   310,   316,   322,   328,   334,   338,   341,
+     347,   352,   355,   357,   359,   361,   365,   367,   371,   373,
+     374,   376,   380,   385,   389,   393,   398,   403,   407,   414,
      420,   423,   426,   429,   432,   435,   438,   441,   444,   447,
-     450,   453,   460,   466,   475,   482,   489,   497,   505,   513,
-     521,   528,   537,   546,   552,   560,   564,   566,   568,   570,
-     572,   573,   576,   583,   585,   586,   588,   591,   592,   596,
-     597,   601,   605,   609,   613,   614,   623,   624,   634,   635,
-     645,   651,   654,   658,   660,   664,   668,   672,   676,   678,
-     679,   685,   689,   691,   695,   697,   698,   709,   711,   713,
-     718,   720,   722,   725,   729,   730,   732,   734,   736,   738,
-     740,   742,   744,   746,   748,   750,   752,   756,   760,   763,
-     766,   770,   773,   779,   784,   786,   792,   794,   796,   798,
-     800,   802,   804,   807,   809,   813,   816,   819,   823,   826,
-     827,   829,   832,   835,   839,   849,   859,   868,   883,   885,
-     887,   894,   900,   903,   910,   918,   923,   928,   935,   942,
-     943,   944,   948,   951,   955,   958,   960,   966,   972,   979,
-     986,   993,  1000,  1005,  1012,  1017,  1022,  1029,  1036,  1039,
-    1048,  1050,  1052,  1053,  1057,  1064,  1068,  1075,  1078,  1084,
-    1092,  1098,  1103,  1108
+     450,   453,   456,   463,   469,   478,   485,   492,   500,   508,
+     516,   524,   531,   540,   549,   555,   563,   567,   569,   571,
+     573,   575,   576,   579,   586,   588,   589,   591,   594,   595,
+     599,   600,   604,   608,   612,   616,   617,   626,   627,   637,
+     638,   648,   654,   657,   661,   663,   667,   671,   675,   679,
+     681,   682,   688,   692,   694,   698,   700,   701,   712,   714,
+     716,   721,   723,   725,   728,   732,   733,   735,   737,   739,
+     741,   743,   745,   747,   749,   751,   753,   755,   759,   763,
+     766,   769,   773,   776,   782,   787,   789,   795,   797,   799,
+     801,   803,   805,   807,   810,   812,   816,   819,   822,   826,
+     830,   833,   834,   836,   839,   842,   846,   856,   866,   875,
+     890,   892,   894,   901,   907,   910,   913,   920,   928,   933,
+     938,   945,   952,   953,   954,   958,   961,   965,   968,   970,
+     976,   982,   989,   996,  1003,  1010,  1015,  1022,  1027,  1032,
+    1039,  1046,  1049,  1058,  1060,  1062,  1063,  1067,  1074,  1078,
+    1085,  1088,  1094,  1102,  1108,  1113,  1118
 };
 
 /* YYRHS -- A `-1'-separated list of the rules' RHS.  */
 static const yytype_int16 yyrhs[] =
 {
-     217,     0,    -1,    76,    -1,    77,    -1,    78,    -1,    79,
+     218,     0,    -1,    76,    -1,    77,    -1,    78,    -1,    79,
       -1,    80,    -1,    81,    -1,    82,    -1,    83,    -1,    84,
       -1,    88,    -1,    89,    -1,    90,    -1,    85,    -1,    86,
       -1,    87,    -1,   121,    -1,   122,    -1,   123,    -1,   124,
@@ -1765,144 +1768,145 @@
       -1,    12,    -1,    13,    -1,    16,    -1,    15,    -1,    14,
       -1,    19,    -1,    22,    -1,    24,    -1,   179,    -1,    -1,
       55,   157,     4,   158,    -1,    -1,   179,   159,    -1,    -1,
-      20,    -1,    23,    -1,   185,    -1,    -1,   183,   159,    -1,
-      42,    -1,    44,    -1,    43,    -1,    45,    -1,    47,    -1,
-      49,    -1,    46,    -1,    48,    -1,    51,    -1,    -1,   154,
-      -1,   155,    -1,   156,    -1,    -1,    46,    -1,    48,    -1,
-      -1,    42,    -1,    43,    -1,    44,    -1,    47,    -1,    -1,
-      44,    -1,    42,    -1,    -1,    63,    -1,    64,    -1,    65,
-      -1,    66,    -1,    67,    -1,    68,    -1,    62,     4,    -1,
-     143,    -1,   122,    -1,   142,    -1,   123,    -1,   145,    -1,
-     146,    -1,   148,    -1,   149,    -1,   150,    -1,    54,     4,
-      -1,    -1,   194,   193,    -1,   144,    -1,   147,    -1,   143,
-      -1,   142,    -1,   151,    -1,   152,    -1,    -1,   196,   195,
-      -1,    -1,   153,    22,    -1,    -1,    54,     4,    -1,    -1,
-     160,    54,     4,    -1,    34,    22,    -1,    -1,   200,    -1,
-      -1,   160,   203,   202,    -1,   200,    -1,    54,     4,    -1,
-      11,    -1,    12,    -1,    13,    -1,    16,    -1,    15,    -1,
-      14,    -1,    17,    -1,    50,    -1,   204,    -1,   205,   181,
-     161,    -1,   239,    -1,   162,     4,    -1,   205,   157,   209,
-     158,   196,    -1,    10,   157,   209,   158,   196,    -1,   163,
-       4,   164,   205,   165,    -1,   166,     4,   164,   205,   167,
-      -1,   168,   210,   169,    -1,   168,   169,    -1,   166,   168,
-     210,   169,   167,    -1,   166,   168,   169,   167,    -1,   205,
-     194,    -1,   205,    -1,    10,    -1,   206,    -1,   208,   160,
-     206,    -1,   208,    -1,   208,   160,    39,    -1,    39,    -1,
-      -1,   205,    -1,   210,   160,   205,    -1,   205,   163,   213,
-     165,    -1,   205,   163,   165,    -1,   205,   170,    22,    -1,
-     205,   166,   213,   167,    -1,   205,   168,   213,   169,    -1,
-     205,   168,   169,    -1,   205,   166,   168,   213,   169,   167,
-      -1,   205,   166,   168,   169,   167,    -1,   205,    40,    -1,
-     205,    41,    -1,   205,   239,    -1,   205,   212,    -1,   205,
-      25,    -1,   177,     3,    -1,   177,     5,    -1,   177,     4,
-      -1,   177,     6,    -1,    11,    26,    -1,    11,    27,    -1,
-     178,     9,    -1,   174,   157,   211,    38,   205,   158,    -1,
-     120,   157,   211,   251,   158,    -1,   134,   157,   211,   160,
-     211,   160,   211,   158,    -1,   172,   157,   211,   160,   211,
-     158,    -1,   173,   157,   211,   160,   211,   158,    -1,    91,
-     175,   157,   211,   160,   211,   158,    -1,    92,   176,   157,
-     211,   160,   211,   158,    -1,    93,   175,   157,   211,   160,
-     211,   158,    -1,    94,   176,   157,   211,   160,   211,   158,
-      -1,   136,   157,   211,   160,   211,   158,    -1,   137,   157,
-     211,   160,   211,   160,   211,   158,    -1,   138,   157,   211,
-     160,   211,   160,   211,   158,    -1,   140,   157,   211,   252,
-     158,    -1,   141,   157,   211,   160,   211,   252,   158,    -1,
-     213,   160,   211,    -1,   211,    -1,    32,    -1,    33,    -1,
-      37,    -1,    -1,   207,   239,    -1,   126,   157,   216,    38,
-     205,   158,    -1,   218,    -1,    -1,   219,    -1,   218,   219,
-      -1,    -1,    31,   220,   235,    -1,    -1,    30,   221,   236,
-      -1,    60,    59,   225,    -1,   182,    18,   205,    -1,   182,
-      18,    10,    -1,    -1,   184,   188,   215,   214,   211,   181,
-     222,   202,    -1,    -1,   184,   186,   188,   215,   214,   211,
-     181,   223,   202,    -1,    -1,   184,   187,   188,   215,   214,
-     205,   181,   224,   202,    -1,   184,   188,    35,   191,   216,
-      -1,    52,   226,    -1,    56,   159,   227,    -1,    22,    -1,
-      53,   159,    22,    -1,    69,   159,    22,    -1,   163,   228,
-     165,    -1,   228,   160,    22,    -1,    22,    -1,    -1,   229,
-     160,   205,   194,   180,    -1,   205,   194,   180,    -1,   229,
-      -1,   229,   160,    39,    -1,    39,    -1,    -1,   192,   207,
-     183,   157,   230,   158,   196,   201,   198,   197,    -1,    28,
-      -1,   168,    -1,   190,   188,   231,   232,    -1,    29,    -1,
-     169,    -1,   243,   234,    -1,   189,   188,   231,    -1,    -1,
-      61,    -1,     3,    -1,     4,    -1,     5,    -1,     6,    -1,
-       9,    -1,    26,    -1,    27,    -1,    40,    -1,    41,    -1,
-      25,    -1,   166,   213,   167,    -1,   163,   213,   165,    -1,
-     163,   165,    -1,   170,    22,    -1,   168,   213,   169,    -1,
-     168,   169,    -1,   166,   168,   213,   169,   167,    -1,   166,
-     168,   169,   167,    -1,   212,    -1,    59,   237,    22,   160,
-      22,    -1,     7,    -1,     8,    -1,   179,    -1,   183,    -1,
-     239,    -1,   238,    -1,   205,   240,    -1,   241,    -1,   242,
-     160,   241,    -1,   243,   244,    -1,   233,   244,    -1,   245,
-     182,   246,    -1,   245,   248,    -1,    -1,    21,    -1,    70,
-     242,    -1,    70,    10,    -1,    71,    17,   240,    -1,    71,
-      11,   240,   160,    17,   240,   160,    17,   240,    -1,    72,
-     177,   240,   160,    17,   240,   163,   247,   165,    -1,    72,
-     177,   240,   160,    17,   240,   163,   165,    -1,    73,   192,
-     207,   240,   157,   250,   158,   196,    38,    17,   240,    74,
-      17,   240,    -1,    74,    -1,    75,    -1,   247,   177,   238,
-     160,    17,   240,    -1,   177,   238,   160,    17,   240,    -1,
-     182,   254,    -1,   205,   163,   240,   160,   240,   165,    -1,
-     249,   160,   163,   240,   160,   240,   165,    -1,   205,   194,
-     240,   194,    -1,    17,   194,   240,   194,    -1,   250,   160,
-     205,   194,   240,   194,    -1,   250,   160,    17,   194,   240,
-     194,    -1,    -1,    -1,   251,   160,   241,    -1,   160,     4,
-      -1,   252,   160,     4,    -1,    58,    57,    -1,    57,    -1,
-     172,   205,   240,   160,   240,    -1,   173,   205,   240,   160,
-     240,    -1,    91,   175,   205,   240,   160,   240,    -1,    92,
-     176,   205,   240,   160,   240,    -1,    93,   175,   205,   240,
-     160,   240,    -1,    94,   176,   205,   240,   160,   240,    -1,
-     174,   241,    38,   205,    -1,   134,   241,   160,   241,   160,
-     241,    -1,   135,   241,   160,   205,    -1,   136,   241,   160,
-     241,    -1,   137,   241,   160,   241,   160,   241,    -1,   138,
-     241,   160,   241,   160,   241,    -1,   133,   249,    -1,   253,
-     192,   207,   240,   157,   250,   158,   196,    -1,   256,    -1,
-      36,    -1,    -1,   115,   205,   199,    -1,   115,   205,   160,
-      11,   240,   199,    -1,   116,   205,   199,    -1,   116,   205,
-     160,    11,   240,   199,    -1,   117,   241,    -1,   255,   118,
-     205,   240,   199,    -1,   255,   119,   241,   160,   205,   240,
-     199,    -1,   139,   205,   240,   160,     4,    -1,   120,   205,
-     240,   251,    -1,   140,   205,   240,   252,    -1,   141,   205,
-     240,   160,   205,   240,   252,    -1
+       7,   159,    -1,    20,    -1,    23,    -1,   186,    -1,    -1,
+     184,   159,    -1,    42,    -1,    44,    -1,    43,    -1,    45,
+      -1,    47,    -1,    49,    -1,    46,    -1,    48,    -1,    51,
+      -1,    -1,   154,    -1,   155,    -1,   156,    -1,    -1,    46,
+      -1,    48,    -1,    -1,    42,    -1,    43,    -1,    44,    -1,
+      47,    -1,    -1,    44,    -1,    42,    -1,    -1,    63,    -1,
+      64,    -1,    65,    -1,    66,    -1,    67,    -1,    68,    -1,
+      62,     4,    -1,   143,    -1,   122,    -1,   142,    -1,   123,
+      -1,   145,    -1,   146,    -1,   148,    -1,   149,    -1,   150,
+      -1,    54,     4,    -1,    -1,   195,   194,    -1,   144,    -1,
+     147,    -1,   143,    -1,   142,    -1,   151,    -1,   152,    -1,
+      -1,   197,   196,    -1,    -1,   153,    22,    -1,    -1,    54,
+       4,    -1,    -1,   160,    54,     4,    -1,    34,    22,    -1,
+      -1,   201,    -1,    -1,   160,   204,   203,    -1,   201,    -1,
+      54,     4,    -1,    11,    -1,    12,    -1,    13,    -1,    16,
+      -1,    15,    -1,    14,    -1,    17,    -1,    50,    -1,   205,
+      -1,   206,   181,   161,    -1,   240,    -1,   162,     4,    -1,
+     206,   157,   210,   158,   197,    -1,    10,   157,   210,   158,
+     197,    -1,   163,     4,   164,   206,   165,    -1,   166,     4,
+     164,   206,   167,    -1,   168,   211,   169,    -1,   168,   169,
+      -1,   166,   168,   211,   169,   167,    -1,   166,   168,   169,
+     167,    -1,   206,   195,    -1,   206,    -1,    10,    -1,   207,
+      -1,   209,   160,   207,    -1,   209,    -1,   209,   160,    39,
+      -1,    39,    -1,    -1,   206,    -1,   211,   160,   206,    -1,
+     206,   163,   214,   165,    -1,   206,   163,   165,    -1,   206,
+     170,    22,    -1,   206,   166,   214,   167,    -1,   206,   168,
+     214,   169,    -1,   206,   168,   169,    -1,   206,   166,   168,
+     214,   169,   167,    -1,   206,   166,   168,   169,   167,    -1,
+     206,    40,    -1,   206,    41,    -1,   206,   240,    -1,   206,
+     213,    -1,   206,    25,    -1,   177,     3,    -1,   177,     5,
+      -1,   177,     4,    -1,   177,     6,    -1,    11,    26,    -1,
+      11,    27,    -1,   178,     9,    -1,   174,   157,   212,    38,
+     206,   158,    -1,   120,   157,   212,   252,   158,    -1,   134,
+     157,   212,   160,   212,   160,   212,   158,    -1,   172,   157,
+     212,   160,   212,   158,    -1,   173,   157,   212,   160,   212,
+     158,    -1,    91,   175,   157,   212,   160,   212,   158,    -1,
+      92,   176,   157,   212,   160,   212,   158,    -1,    93,   175,
+     157,   212,   160,   212,   158,    -1,    94,   176,   157,   212,
+     160,   212,   158,    -1,   136,   157,   212,   160,   212,   158,
+      -1,   137,   157,   212,   160,   212,   160,   212,   158,    -1,
+     138,   157,   212,   160,   212,   160,   212,   158,    -1,   140,
+     157,   212,   253,   158,    -1,   141,   157,   212,   160,   212,
+     253,   158,    -1,   214,   160,   212,    -1,   212,    -1,    32,
+      -1,    33,    -1,    37,    -1,    -1,   208,   240,    -1,   126,
+     157,   217,    38,   206,   158,    -1,   219,    -1,    -1,   220,
+      -1,   219,   220,    -1,    -1,    31,   221,   236,    -1,    -1,
+      30,   222,   237,    -1,    60,    59,   226,    -1,   182,    18,
+     206,    -1,   182,    18,    10,    -1,    -1,   185,   189,   216,
+     215,   212,   181,   223,   203,    -1,    -1,   185,   187,   189,
+     216,   215,   212,   181,   224,   203,    -1,    -1,   185,   188,
+     189,   216,   215,   206,   181,   225,   203,    -1,   185,   189,
+      35,   192,   217,    -1,    52,   227,    -1,    56,   159,   228,
+      -1,    22,    -1,    53,   159,    22,    -1,    69,   159,    22,
+      -1,   163,   229,   165,    -1,   229,   160,    22,    -1,    22,
+      -1,    -1,   230,   160,   206,   195,   180,    -1,   206,   195,
+     180,    -1,   230,    -1,   230,   160,    39,    -1,    39,    -1,
+      -1,   193,   208,   184,   157,   231,   158,   197,   202,   199,
+     198,    -1,    28,    -1,   168,    -1,   191,   189,   232,   233,
+      -1,    29,    -1,   169,    -1,   244,   235,    -1,   190,   189,
+     232,    -1,    -1,    61,    -1,     3,    -1,     4,    -1,     5,
+      -1,     6,    -1,     9,    -1,    26,    -1,    27,    -1,    40,
+      -1,    41,    -1,    25,    -1,   166,   214,   167,    -1,   163,
+     214,   165,    -1,   163,   165,    -1,   170,    22,    -1,   168,
+     214,   169,    -1,   168,   169,    -1,   166,   168,   214,   169,
+     167,    -1,   166,   168,   169,   167,    -1,   213,    -1,    59,
+     238,    22,   160,    22,    -1,     7,    -1,     8,    -1,   179,
+      -1,   184,    -1,   240,    -1,   239,    -1,   206,   241,    -1,
+     242,    -1,   243,   160,   242,    -1,   244,   245,    -1,   234,
+     245,    -1,   246,   182,   247,    -1,   246,   183,   247,    -1,
+     246,   249,    -1,    -1,    21,    -1,    70,   243,    -1,    70,
+      10,    -1,    71,    17,   241,    -1,    71,    11,   241,   160,
+      17,   241,   160,    17,   241,    -1,    72,   177,   241,   160,
+      17,   241,   163,   248,   165,    -1,    72,   177,   241,   160,
+      17,   241,   163,   165,    -1,    73,   193,   208,   241,   157,
+     251,   158,   197,    38,    17,   241,    74,    17,   241,    -1,
+      74,    -1,    75,    -1,   248,   177,   239,   160,    17,   241,
+      -1,   177,   239,   160,    17,   241,    -1,   182,   255,    -1,
+     183,   255,    -1,   206,   163,   241,   160,   241,   165,    -1,
+     250,   160,   163,   241,   160,   241,   165,    -1,   206,   195,
+     241,   195,    -1,    17,   195,   241,   195,    -1,   251,   160,
+     206,   195,   241,   195,    -1,   251,   160,    17,   195,   241,
+     195,    -1,    -1,    -1,   252,   160,   242,    -1,   160,     4,
+      -1,   253,   160,     4,    -1,    58,    57,    -1,    57,    -1,
+     172,   206,   241,   160,   241,    -1,   173,   206,   241,   160,
+     241,    -1,    91,   175,   206,   241,   160,   241,    -1,    92,
+     176,   206,   241,   160,   241,    -1,    93,   175,   206,   241,
+     160,   241,    -1,    94,   176,   206,   241,   160,   241,    -1,
+     174,   242,    38,   206,    -1,   134,   242,   160,   242,   160,
+     242,    -1,   135,   242,   160,   206,    -1,   136,   242,   160,
+     242,    -1,   137,   242,   160,   242,   160,   242,    -1,   138,
+     242,   160,   242,   160,   242,    -1,   133,   250,    -1,   254,
+     193,   208,   241,   157,   251,   158,   197,    -1,   257,    -1,
+      36,    -1,    -1,   115,   206,   200,    -1,   115,   206,   160,
+      11,   241,   200,    -1,   116,   206,   200,    -1,   116,   206,
+     160,    11,   241,   200,    -1,   117,   242,    -1,   256,   118,
+     206,   241,   200,    -1,   256,   119,   242,   160,   206,   241,
+     200,    -1,   139,   206,   241,   160,     4,    -1,   120,   206,
+     241,   252,    -1,   140,   206,   241,   253,    -1,   141,   206,
+     241,   160,   206,   241,   253,    -1
 };
 
 /* YYRLINE[YYN] -- source line where rule number YYN was defined.  */
 static const yytype_uint16 yyrline[] =
 {
-       0,  1133,  1133,  1133,  1133,  1133,  1133,  1133,  1133,  1133,
-    1133,  1134,  1134,  1134,  1134,  1134,  1134,  1135,  1135,  1135,
-    1135,  1135,  1135,  1136,  1136,  1136,  1136,  1136,  1136,  1139,
-    1139,  1140,  1140,  1141,  1141,  1142,  1142,  1143,  1143,  1147,
-    1147,  1148,  1148,  1149,  1149,  1150,  1150,  1151,  1151,  1152,
-    1152,  1153,  1153,  1154,  1155,  1160,  1161,  1161,  1161,  1161,
-    1161,  1163,  1163,  1163,  1164,  1164,  1166,  1167,  1171,  1175,
-    1180,  1180,  1182,  1183,  1188,  1194,  1195,  1196,  1197,  1198,
-    1199,  1203,  1204,  1205,  1209,  1210,  1211,  1212,  1216,  1217,
-    1218,  1222,  1223,  1224,  1225,  1226,  1230,  1231,  1232,  1235,
-    1236,  1237,  1238,  1239,  1240,  1241,  1242,  1249,  1250,  1251,
-    1252,  1253,  1254,  1255,  1256,  1257,  1258,  1262,  1263,  1268,
-    1269,  1270,  1271,  1272,  1273,  1276,  1277,  1282,  1283,  1290,
-    1291,  1297,  1298,  1307,  1315,  1316,  1321,  1322,  1323,  1328,
-    1341,  1341,  1341,  1341,  1341,  1341,  1341,  1344,  1348,  1352,
-    1359,  1364,  1372,  1401,  1426,  1431,  1441,  1451,  1455,  1465,
-    1472,  1481,  1488,  1493,  1498,  1505,  1506,  1513,  1520,  1528,
-    1534,  1546,  1574,  1590,  1617,  1645,  1671,  1691,  1717,  1737,
-    1749,  1756,  1822,  1832,  1842,  1848,  1858,  1864,  1874,  1880,
-    1886,  1899,  1911,  1932,  1940,  1946,  1957,  1962,  1967,  1972,
-    1977,  1983,  1989,  1995,  2003,  2014,  2018,  2026,  2026,  2029,
-    2029,  2032,  2044,  2065,  2070,  2078,  2079,  2083,  2083,  2087,
-    2087,  2090,  2093,  2117,  2129,  2128,  2140,  2139,  2149,  2148,
-    2159,  2199,  2202,  2208,  2218,  2222,  2227,  2229,  2234,  2239,
-    2248,  2258,  2269,  2273,  2282,  2291,  2296,  2425,  2425,  2427,
-    2436,  2436,  2438,  2443,  2455,  2459,  2464,  2468,  2472,  2477,
-    2482,  2486,  2490,  2494,  2498,  2502,  2506,  2528,  2550,  2556,
-    2569,  2581,  2586,  2598,  2604,  2608,  2618,  2622,  2626,  2631,
-    2638,  2638,  2644,  2653,  2658,  2663,  2667,  2676,  2685,  2694,
-    2698,  2706,  2726,  2730,  2735,  2746,  2765,  2774,  2860,  2864,
-    2871,  2882,  2895,  2905,  2916,  2926,  2937,  2945,  2955,  2962,
-    2965,  2966,  2974,  2980,  2989,  2993,  2998,  3014,  3031,  3045,
-    3059,  3073,  3087,  3099,  3107,  3114,  3120,  3126,  3132,  3147,
-    3237,  3242,  3246,  3253,  3260,  3270,  3277,  3287,  3295,  3309,
-    3326,  3340,  3355,  3370
+       0,  1136,  1136,  1136,  1136,  1136,  1136,  1136,  1136,  1136,
+    1136,  1137,  1137,  1137,  1137,  1137,  1137,  1138,  1138,  1138,
+    1138,  1138,  1138,  1139,  1139,  1139,  1139,  1139,  1139,  1142,
+    1142,  1143,  1143,  1144,  1144,  1145,  1145,  1146,  1146,  1150,
+    1150,  1151,  1151,  1152,  1152,  1153,  1153,  1154,  1154,  1155,
+    1155,  1156,  1156,  1157,  1158,  1163,  1164,  1164,  1164,  1164,
+    1164,  1166,  1166,  1166,  1167,  1167,  1169,  1170,  1174,  1178,
+    1183,  1189,  1189,  1191,  1192,  1197,  1203,  1204,  1205,  1206,
+    1207,  1208,  1212,  1213,  1214,  1218,  1219,  1220,  1221,  1225,
+    1226,  1227,  1231,  1232,  1233,  1234,  1235,  1239,  1240,  1241,
+    1244,  1245,  1246,  1247,  1248,  1249,  1250,  1251,  1258,  1259,
+    1260,  1261,  1262,  1263,  1264,  1265,  1266,  1267,  1271,  1272,
+    1277,  1278,  1279,  1280,  1281,  1282,  1285,  1286,  1291,  1292,
+    1299,  1300,  1306,  1307,  1316,  1324,  1325,  1330,  1331,  1332,
+    1337,  1350,  1350,  1350,  1350,  1350,  1350,  1350,  1353,  1357,
+    1361,  1368,  1373,  1381,  1410,  1435,  1440,  1450,  1460,  1464,
+    1474,  1481,  1490,  1497,  1502,  1507,  1514,  1515,  1522,  1529,
+    1537,  1543,  1555,  1583,  1599,  1626,  1654,  1680,  1700,  1726,
+    1746,  1758,  1765,  1831,  1841,  1851,  1857,  1867,  1873,  1883,
+    1889,  1895,  1908,  1920,  1941,  1949,  1955,  1966,  1971,  1976,
+    1981,  1986,  1992,  1998,  2004,  2012,  2023,  2027,  2035,  2035,
+    2038,  2038,  2041,  2053,  2074,  2079,  2087,  2088,  2092,  2092,
+    2096,  2096,  2099,  2102,  2126,  2138,  2137,  2149,  2148,  2158,
+    2157,  2168,  2208,  2211,  2217,  2227,  2231,  2236,  2238,  2243,
+    2248,  2257,  2267,  2278,  2282,  2291,  2300,  2305,  2434,  2434,
+    2436,  2445,  2445,  2447,  2452,  2464,  2468,  2473,  2477,  2481,
+    2486,  2491,  2495,  2499,  2503,  2507,  2511,  2515,  2537,  2559,
+    2565,  2578,  2590,  2595,  2607,  2613,  2617,  2627,  2631,  2635,
+    2640,  2647,  2647,  2653,  2662,  2667,  2672,  2676,  2685,  2694,
+    2707,  2716,  2720,  2728,  2748,  2752,  2757,  2768,  2787,  2796,
+    2882,  2886,  2893,  2904,  2917,  2926,  2939,  2950,  2960,  2971,
+    2979,  2989,  2996,  2999,  3000,  3008,  3014,  3023,  3027,  3032,
+    3048,  3065,  3079,  3093,  3107,  3121,  3133,  3141,  3148,  3154,
+    3160,  3166,  3181,  3271,  3276,  3280,  3287,  3294,  3304,  3311,
+    3321,  3329,  3343,  3360,  3374,  3389,  3404
 };
 #endif
 
@@ -1939,23 +1943,23 @@
   "'>'", "'{'", "'}'", "'c'", "$accept", "ArithmeticOps", "LogicalOps",
   "CastOps", "IPredicates", "FPredicates", "IntType", "FPType",
   "LocalName", "OptLocalName", "OptAddrSpace", "OptLocalAssign",
-  "GlobalName", "OptGlobalAssign", "GlobalAssign", "GVInternalLinkage",
-  "GVExternalLinkage", "GVVisibilityStyle", "FunctionDeclareLinkage",
-  "FunctionDefineLinkage", "AliasLinkage", "OptCallingConv", "ParamAttr",
-  "OptParamAttrs", "FuncAttr", "OptFuncAttrs", "OptGC", "OptAlign",
-  "OptCAlign", "SectionString", "OptSection", "GlobalVarAttributes",
-  "GlobalVarAttribute", "PrimType", "Types", "ArgType", "ResultTypes",
-  "ArgTypeList", "ArgTypeListI", "TypeListI", "ConstVal", "ConstExpr",
-  "ConstVector", "GlobalType", "ThreadLocal", "AliaseeRef", "Module",
-  "DefinitionList", "Definition", "@1", "@2", "@3", "@4", "@5", "AsmBlock",
-  "TargetDefinition", "LibrariesDefinition", "LibList", "ArgListH",
-  "ArgList", "FunctionHeaderH", "BEGIN", "FunctionHeader", "END",
-  "Function", "FunctionProto", "OptSideEffect", "ConstValueRef",
-  "SymbolicValueRef", "ValueRef", "ResolvedVal", "ReturnedVal",
-  "BasicBlockList", "BasicBlock", "InstructionList", "BBTerminatorInst",
-  "JumpTable", "Inst", "PHIList", "ParamList", "IndexList",
-  "ConstantIndexList", "OptTailCall", "InstVal", "OptVolatile",
-  "MemoryInst", 0
+  "LocalNumber", "GlobalName", "OptGlobalAssign", "GlobalAssign",
+  "GVInternalLinkage", "GVExternalLinkage", "GVVisibilityStyle",
+  "FunctionDeclareLinkage", "FunctionDefineLinkage", "AliasLinkage",
+  "OptCallingConv", "ParamAttr", "OptParamAttrs", "FuncAttr",
+  "OptFuncAttrs", "OptGC", "OptAlign", "OptCAlign", "SectionString",
+  "OptSection", "GlobalVarAttributes", "GlobalVarAttribute", "PrimType",
+  "Types", "ArgType", "ResultTypes", "ArgTypeList", "ArgTypeListI",
+  "TypeListI", "ConstVal", "ConstExpr", "ConstVector", "GlobalType",
+  "ThreadLocal", "AliaseeRef", "Module", "DefinitionList", "Definition",
+  "@1", "@2", "@3", "@4", "@5", "AsmBlock", "TargetDefinition",
+  "LibrariesDefinition", "LibList", "ArgListH", "ArgList",
+  "FunctionHeaderH", "BEGIN", "FunctionHeader", "END", "Function",
+  "FunctionProto", "OptSideEffect", "ConstValueRef", "SymbolicValueRef",
+  "ValueRef", "ResolvedVal", "ReturnedVal", "BasicBlockList", "BasicBlock",
+  "InstructionList", "BBTerminatorInst", "JumpTable", "Inst", "PHIList",
+  "ParamList", "IndexList", "ConstantIndexList", "OptTailCall", "InstVal",
+  "OptVolatile", "MemoryInst", 0
 };
 #endif
 
@@ -1995,34 +1999,34 @@
      176,   176,   176,   176,   176,   176,   176,   176,   176,   176,
      176,   176,   176,   176,   176,   177,   178,   178,   178,   178,
      178,   179,   179,   179,   180,   180,   181,   181,   182,   182,
-     183,   183,   184,   184,   185,   186,   186,   186,   186,   186,
-     186,   187,   187,   187,   188,   188,   188,   188,   189,   189,
-     189,   190,   190,   190,   190,   190,   191,   191,   191,   192,
-     192,   192,   192,   192,   192,   192,   192,   193,   193,   193,
-     193,   193,   193,   193,   193,   193,   193,   194,   194,   195,
-     195,   195,   195,   195,   195,   196,   196,   197,   197,   198,
-     198,   199,   199,   200,   201,   201,   202,   202,   203,   203,
-     204,   204,   204,   204,   204,   204,   204,   205,   205,   205,
-     205,   205,   205,   205,   205,   205,   205,   205,   205,   205,
-     206,   207,   207,   208,   208,   209,   209,   209,   209,   210,
-     210,   211,   211,   211,   211,   211,   211,   211,   211,   211,
-     211,   211,   211,   211,   211,   211,   211,   211,   211,   211,
-     211,   212,   212,   212,   212,   212,   212,   212,   212,   212,
-     212,   212,   212,   212,   212,   213,   213,   214,   214,   215,
-     215,   216,   216,   217,   217,   218,   218,   220,   219,   221,
-     219,   219,   219,   219,   222,   219,   223,   219,   224,   219,
-     219,   219,   219,   225,   226,   226,   227,   228,   228,   228,
-     229,   229,   230,   230,   230,   230,   231,   232,   232,   233,
-     234,   234,   235,   236,   237,   237,   238,   238,   238,   238,
-     238,   238,   238,   238,   238,   238,   238,   238,   238,   238,
-     238,   238,   238,   238,   238,   238,   239,   239,   239,   239,
-     240,   240,   241,   242,   242,   243,   243,   244,   245,   245,
-     245,   246,   246,   246,   246,   246,   246,   246,   246,   246,
-     247,   247,   248,   249,   249,   250,   250,   250,   250,   250,
-     251,   251,   252,   252,   253,   253,   254,   254,   254,   254,
-     254,   254,   254,   254,   254,   254,   254,   254,   254,   254,
-     254,   255,   255,   256,   256,   256,   256,   256,   256,   256,
-     256,   256,   256,   256
+     183,   184,   184,   185,   185,   186,   187,   187,   187,   187,
+     187,   187,   188,   188,   188,   189,   189,   189,   189,   190,
+     190,   190,   191,   191,   191,   191,   191,   192,   192,   192,
+     193,   193,   193,   193,   193,   193,   193,   193,   194,   194,
+     194,   194,   194,   194,   194,   194,   194,   194,   195,   195,
+     196,   196,   196,   196,   196,   196,   197,   197,   198,   198,
+     199,   199,   200,   200,   201,   202,   202,   203,   203,   204,
+     204,   205,   205,   205,   205,   205,   205,   205,   206,   206,
+     206,   206,   206,   206,   206,   206,   206,   206,   206,   206,
+     206,   207,   208,   208,   209,   209,   210,   210,   210,   210,
+     211,   211,   212,   212,   212,   212,   212,   212,   212,   212,
+     212,   212,   212,   212,   212,   212,   212,   212,   212,   212,
+     212,   212,   213,   213,   213,   213,   213,   213,   213,   213,
+     213,   213,   213,   213,   213,   213,   214,   214,   215,   215,
+     216,   216,   217,   217,   218,   218,   219,   219,   221,   220,
+     222,   220,   220,   220,   220,   223,   220,   224,   220,   225,
+     220,   220,   220,   220,   226,   227,   227,   228,   229,   229,
+     229,   230,   230,   231,   231,   231,   231,   232,   233,   233,
+     234,   235,   235,   236,   237,   238,   238,   239,   239,   239,
+     239,   239,   239,   239,   239,   239,   239,   239,   239,   239,
+     239,   239,   239,   239,   239,   239,   239,   240,   240,   240,
+     240,   241,   241,   242,   243,   243,   244,   244,   245,   245,
+     246,   246,   246,   247,   247,   247,   247,   247,   247,   247,
+     247,   247,   248,   248,   249,   249,   250,   250,   251,   251,
+     251,   251,   251,   252,   252,   253,   253,   254,   254,   255,
+     255,   255,   255,   255,   255,   255,   255,   255,   255,   255,
+     255,   255,   255,   255,   256,   256,   257,   257,   257,   257,
+     257,   257,   257,   257,   257,   257,   257
 };
 
 /* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN.  */
@@ -2035,34 +2039,34 @@
        1,     1,     1,     1,     1,     1,     1,     1,     1,     1,
        1,     1,     1,     1,     1,     1,     1,     1,     1,     1,
        1,     1,     1,     1,     1,     0,     4,     0,     2,     0,
-       1,     1,     1,     0,     2,     1,     1,     1,     1,     1,
-       1,     1,     1,     1,     0,     1,     1,     1,     0,     1,
-       1,     0,     1,     1,     1,     1,     0,     1,     1,     0,
-       1,     1,     1,     1,     1,     1,     2,     1,     1,     1,
-       1,     1,     1,     1,     1,     1,     2,     0,     2,     1,
-       1,     1,     1,     1,     1,     0,     2,     0,     2,     0,
-       2,     0,     3,     2,     0,     1,     0,     3,     1,     2,
-       1,     1,     1,     1,     1,     1,     1,     1,     1,     3,
-       1,     2,     5,     5,     5,     5,     3,     2,     5,     4,
-       2,     1,     1,     1,     3,     1,     3,     1,     0,     1,
-       3,     4,     3,     3,     4,     4,     3,     6,     5,     2,
+       2,     1,     1,     1,     0,     2,     1,     1,     1,     1,
+       1,     1,     1,     1,     1,     0,     1,     1,     1,     0,
+       1,     1,     0,     1,     1,     1,     1,     0,     1,     1,
+       0,     1,     1,     1,     1,     1,     1,     2,     1,     1,
+       1,     1,     1,     1,     1,     1,     1,     2,     0,     2,
+       1,     1,     1,     1,     1,     1,     0,     2,     0,     2,
+       0,     2,     0,     3,     2,     0,     1,     0,     3,     1,
+       2,     1,     1,     1,     1,     1,     1,     1,     1,     1,
+       3,     1,     2,     5,     5,     5,     5,     3,     2,     5,
+       4,     2,     1,     1,     1,     3,     1,     3,     1,     0,
+       1,     3,     4,     3,     3,     4,     4,     3,     6,     5,
        2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     6,     5,     8,     6,     6,     7,     7,     7,     7,
-       6,     8,     8,     5,     7,     3,     1,     1,     1,     1,
-       0,     2,     6,     1,     0,     1,     2,     0,     3,     0,
-       3,     3,     3,     3,     0,     8,     0,     9,     0,     9,
-       5,     2,     3,     1,     3,     3,     3,     3,     1,     0,
-       5,     3,     1,     3,     1,     0,    10,     1,     1,     4,
-       1,     1,     2,     3,     0,     1,     1,     1,     1,     1,
-       1,     1,     1,     1,     1,     1,     3,     3,     2,     2,
-       3,     2,     5,     4,     1,     5,     1,     1,     1,     1,
-       1,     1,     2,     1,     3,     2,     2,     3,     2,     0,
-       1,     2,     2,     3,     9,     9,     8,    14,     1,     1,
-       6,     5,     2,     6,     7,     4,     4,     6,     6,     0,
-       0,     3,     2,     3,     2,     1,     5,     5,     6,     6,
-       6,     6,     4,     6,     4,     4,     6,     6,     2,     8,
-       1,     1,     0,     3,     6,     3,     6,     2,     5,     7,
-       5,     4,     4,     7
+       2,     2,     6,     5,     8,     6,     6,     7,     7,     7,
+       7,     6,     8,     8,     5,     7,     3,     1,     1,     1,
+       1,     0,     2,     6,     1,     0,     1,     2,     0,     3,
+       0,     3,     3,     3,     3,     0,     8,     0,     9,     0,
+       9,     5,     2,     3,     1,     3,     3,     3,     3,     1,
+       0,     5,     3,     1,     3,     1,     0,    10,     1,     1,
+       4,     1,     1,     2,     3,     0,     1,     1,     1,     1,
+       1,     1,     1,     1,     1,     1,     1,     3,     3,     2,
+       2,     3,     2,     5,     4,     1,     5,     1,     1,     1,
+       1,     1,     1,     2,     1,     3,     2,     2,     3,     3,
+       2,     0,     1,     2,     2,     3,     9,     9,     8,    14,
+       1,     1,     6,     5,     2,     2,     6,     7,     4,     4,
+       6,     6,     0,     0,     3,     2,     3,     2,     1,     5,
+       5,     6,     6,     6,     6,     4,     6,     4,     4,     6,
+       6,     2,     8,     1,     1,     0,     3,     6,     3,     6,
+       2,     5,     7,     5,     4,     4,     7
 };
 
 /* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
@@ -2070,674 +2074,674 @@
    means the default is an error.  */
 static const yytype_uint16 yydefact[] =
 {
-      73,    61,    70,    62,    71,    63,   219,   217,     0,     0,
-       0,     0,     0,     0,    84,    72,     0,    73,   215,    88,
-      91,     0,     0,   231,     0,     0,    68,     0,    74,    75,
-      77,    76,    78,    81,    79,    82,    80,    83,    85,    86,
-      87,    84,    84,   210,     1,   216,    89,    90,    84,   220,
-      92,    93,    94,    95,    84,   289,   218,   289,     0,     0,
-     239,   232,   233,   221,   276,   277,   223,   140,   141,   142,
-     145,   144,   143,   146,   147,     0,     0,     0,     0,   278,
-     279,   148,   222,   150,   210,   210,    96,   209,     0,    99,
-      99,   290,   286,    69,   250,   251,   252,   285,   234,   235,
-     238,     0,   168,   151,     0,     0,     0,     0,   157,   169,
-       0,     0,   168,     0,     0,     0,    98,    97,     0,   207,
-     208,     0,     0,   100,   101,   102,   103,   104,   105,     0,
-     253,     0,   332,   288,     0,   236,   167,   117,   163,   165,
-       0,     0,     0,     0,     0,     0,   156,     0,     0,   149,
-       0,     0,   162,     0,   161,     0,   230,   140,   141,   142,
-     145,   144,   143,     0,     0,    67,    67,   106,     0,   247,
-     248,   249,   331,   315,     0,     0,     0,     0,    99,   298,
-     299,     2,     3,     4,     5,     6,     7,     8,     9,    10,
-      14,    15,    16,    11,    12,    13,     0,     0,     0,     0,
-       0,     0,     0,     0,    17,    18,    19,    20,    21,    22,
-      23,    24,    25,    26,    27,    28,     0,     0,     0,     0,
-       0,     0,     0,     0,     0,     0,     0,     0,   287,    99,
-     302,     0,   330,   237,   160,     0,   125,    67,    67,   159,
-       0,   170,     0,   125,    67,    67,     0,   211,   188,   189,
-     184,   186,   185,   187,   190,   183,   179,   180,     0,     0,
+      74,    61,    71,    62,    72,    63,   220,   218,     0,     0,
+       0,     0,     0,     0,    85,    73,     0,    74,   216,    89,
+      92,     0,     0,   232,     0,     0,    68,     0,    75,    76,
+      78,    77,    79,    82,    80,    83,    81,    84,    86,    87,
+      88,    85,    85,   211,     1,   217,    90,    91,    85,   221,
+      93,    94,    95,    96,    85,   291,   219,   291,     0,     0,
+     240,   233,   234,   222,   277,   278,   224,   141,   142,   143,
+     146,   145,   144,   147,   148,     0,     0,     0,     0,   279,
+     280,   149,   223,   151,   211,   211,    97,   210,     0,   100,
+     100,   292,   287,    69,   251,   252,   253,   286,   235,   236,
+     239,     0,   169,   152,     0,     0,     0,     0,   158,   170,
+       0,     0,   169,     0,     0,     0,    99,    98,     0,   208,
+     209,     0,     0,   101,   102,   103,   104,   105,   106,     0,
+     254,     0,     0,   335,   335,   290,     0,   237,   168,   118,
+     164,   166,     0,     0,     0,     0,     0,     0,   157,     0,
+       0,   150,     0,     0,   163,     0,   162,     0,   231,   141,
+     142,   143,   146,   145,   144,     0,     0,    67,    67,   107,
+       0,   248,   249,   250,    70,   334,   318,     0,     0,     0,
+       0,   100,   300,   301,     2,     3,     4,     5,     6,     7,
+       8,     9,    10,    14,    15,    16,    11,    12,    13,     0,
+       0,     0,     0,     0,     0,     0,     0,    17,    18,    19,
+      20,    21,    22,    23,    24,    25,    26,    27,    28,     0,
        0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,     0,     0,     0,   182,   181,   224,     0,
-     314,   292,    67,   283,   291,     0,     0,    55,     0,     0,
-      29,    30,    31,    32,    33,    34,    35,    36,    37,    38,
-       0,    53,    54,    49,    50,    51,    52,    39,    40,    41,
-      42,    43,    44,    45,    46,    47,    48,     0,     0,     0,
-     131,   131,   337,    67,    67,   328,     0,     0,     0,     0,
-       0,    67,    67,    67,    67,    67,     0,     0,     0,     0,
-       0,   108,   110,   109,   107,   111,   112,   113,   114,   115,
-     118,   166,   164,   153,   154,   155,   158,    66,   152,   226,
-     228,     0,     0,     0,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,   172,   206,     0,     0,     0,   176,     0,
-     173,     0,     0,     0,   136,   245,   256,   257,   258,   259,
-     260,   265,   261,   262,   263,   264,   254,     0,     0,     0,
-       0,   274,   281,   280,   282,     0,     0,   293,     0,     0,
-      67,    67,    67,    67,     0,   333,     0,   335,   310,     0,
+       0,   288,   100,   304,     0,   333,   289,   305,   238,   161,
+       0,   126,    67,    67,   160,     0,   171,     0,   126,    67,
+      67,     0,   212,   189,   190,   185,   187,   186,   188,   191,
+     184,   180,   181,     0,     0,     0,     0,     0,     0,     0,
        0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,    67,     0,   116,   122,   121,   119,   120,
-     123,   124,   126,   136,   136,     0,     0,     0,     0,     0,
-     310,     0,     0,     0,     0,     0,     0,     0,   171,   157,
-     169,     0,   174,   175,     0,     0,     0,     0,   225,   244,
-     117,   242,     0,   255,     0,   268,     0,     0,     0,   271,
-       0,   269,   284,     0,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,   341,     0,     0,     0,   324,   325,     0,
-       0,     0,     0,   342,     0,     0,     0,   322,     0,   131,
-       0,   227,   229,    67,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,     0,     0,   205,   178,     0,     0,     0,
-       0,     0,     0,   138,   136,    65,     0,   125,     0,   267,
-     157,     0,   266,   270,     0,     0,   309,     0,     0,     0,
-       0,   131,   132,   131,     0,     0,     0,     0,     0,     0,
-     340,   312,     0,    67,   316,   317,   309,     0,   338,    67,
-     212,     0,     0,     0,     0,   192,     0,     0,     0,     0,
-     203,     0,   177,     0,     0,    67,   133,   139,   137,    64,
-     241,   243,   117,   134,     0,   273,     0,     0,     0,   117,
-     117,     0,   318,   319,   320,   321,   334,   336,   311,     0,
-       0,   323,   326,   327,   313,     0,     0,   131,     0,     0,
-       0,     0,     0,   200,     0,     0,     0,   194,   195,   191,
-      65,   135,   129,   275,   272,     0,     0,     0,     0,   125,
-       0,   303,     0,   343,   125,   339,   196,   197,   198,   199,
-       0,     0,     0,   204,   240,     0,   127,     0,   296,     0,
-       0,   108,   110,   117,   117,     0,   117,   117,   304,   329,
-     193,   201,   202,   130,     0,   246,   294,     0,   295,     0,
-     306,   305,     0,     0,     0,   128,     0,     0,     0,   117,
-     117,     0,     0,     0,   308,   307,   301,     0,     0,   300,
-       0,   297
+       0,   183,   182,   225,     0,   317,   294,    67,   284,   293,
+       0,     0,    55,     0,     0,    29,    30,    31,    32,    33,
+      34,    35,    36,    37,    38,     0,    53,    54,    49,    50,
+      51,    52,    39,    40,    41,    42,    43,    44,    45,    46,
+      47,    48,     0,     0,     0,   132,   132,   340,    67,    67,
+     331,     0,     0,     0,     0,     0,    67,    67,    67,    67,
+      67,     0,     0,     0,     0,     0,   109,   111,   110,   108,
+     112,   113,   114,   115,   116,   119,   167,   165,   154,   155,
+     156,   159,    66,   153,   227,   229,     0,     0,     0,     0,
+       0,     0,     0,     0,     0,     0,     0,     0,   173,   207,
+       0,     0,     0,   177,     0,   174,     0,     0,     0,   137,
+     246,   257,   258,   259,   260,   261,   266,   262,   263,   264,
+     265,   255,     0,     0,     0,     0,   275,   282,   281,   283,
+       0,     0,   295,     0,     0,    67,    67,    67,    67,     0,
+     336,     0,   338,   313,     0,     0,     0,     0,     0,     0,
+       0,     0,     0,     0,     0,     0,     0,     0,    67,     0,
+     117,   123,   122,   120,   121,   124,   125,   127,   137,   137,
+       0,     0,     0,     0,     0,   313,     0,     0,     0,     0,
+       0,     0,     0,   172,   158,   170,     0,   175,   176,     0,
+       0,     0,     0,   226,   245,   118,   243,     0,   256,     0,
+     269,     0,     0,     0,   272,     0,   270,   285,     0,     0,
+       0,     0,     0,     0,     0,     0,     0,     0,   344,     0,
+       0,     0,   327,   328,     0,     0,     0,     0,   345,     0,
+       0,     0,   325,     0,   132,     0,   228,   230,    67,     0,
+       0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
+     206,   179,     0,     0,     0,     0,     0,     0,   139,   137,
+      65,     0,   126,     0,   268,   158,     0,   267,   271,     0,
+       0,   312,     0,     0,     0,     0,   132,   133,   132,     0,
+       0,     0,     0,     0,     0,   343,   315,     0,    67,   319,
+     320,   312,     0,   341,    67,   213,     0,     0,     0,     0,
+     193,     0,     0,     0,     0,   204,     0,   178,     0,     0,
+      67,   134,   140,   138,    64,   242,   244,   118,   135,     0,
+     274,     0,     0,     0,   118,   118,     0,   321,   322,   323,
+     324,   337,   339,   314,     0,     0,   326,   329,   330,   316,
+       0,     0,   132,     0,     0,     0,     0,     0,   201,     0,
+       0,     0,   195,   196,   192,    65,   136,   130,   276,   273,
+       0,     0,     0,     0,   126,     0,   306,     0,   346,   126,
+     342,   197,   198,   199,   200,     0,     0,     0,   205,   241,
+       0,   128,     0,   298,     0,     0,   109,   111,   118,   118,
+       0,   118,   118,   307,   332,   194,   202,   203,   131,     0,
+     247,   296,     0,   297,     0,   309,   308,     0,     0,     0,
+     129,     0,     0,     0,   118,   118,     0,     0,     0,   311,
+     310,   303,     0,     0,   302,     0,   299
 };
 
 /* YYDEFGOTO[NTERM-NUM].  */
 static const yytype_int16 yydefgoto[] =
 {
-      -1,   273,   274,   275,   300,   317,   163,   164,    79,   590,
-     113,    12,    80,    14,    15,    41,    42,    43,    48,    54,
-     118,   129,   350,   234,   442,   353,   675,   656,   415,   533,
-     632,   468,   534,    81,   165,   138,   155,   139,   140,   110,
-     374,   401,   375,   121,    88,   156,    16,    17,    18,    20,
-      19,   384,   443,   444,    63,    23,    61,   101,   471,   472,
-     130,   171,    55,    96,    56,    49,   474,   402,    83,   404,
-     283,   284,    57,    92,    93,   228,   660,   133,   325,   601,
-     493,   503,   229,   230,   231,   232
+      -1,   278,   279,   280,   305,   322,   165,   166,    79,   595,
+     113,    12,   134,    80,    14,    15,    41,    42,    43,    48,
+      54,   118,   129,   355,   239,   447,   358,   680,   661,   420,
+     538,   637,   473,   539,    81,   167,   140,   157,   141,   142,
+     110,   379,   406,   380,   121,    88,   158,    16,    17,    18,
+      20,    19,   389,   448,   449,    63,    23,    61,   101,   476,
+     477,   130,   173,    55,    96,    56,    49,   479,   407,    83,
+     409,   288,   289,    57,    92,    93,   231,   665,   135,   330,
+     606,   498,   508,   232,   233,   234,   235
 };
 
 /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
    STATE-NUM.  */
-#define YYPACT_NINF -623
+#define YYPACT_NINF -615
 static const yytype_int16 yypact[] =
 {
-     493,  -623,  -623,  -623,  -623,  -623,  -623,  -623,    18,  -104,
-      15,  -100,    70,   -57,    -3,  -623,   148,   542,  -623,   191,
-     228,   -29,     9,  -623,    44,   159,  -623,  1927,  -623,  -623,
-    -623,  -623,  -623,  -623,  -623,  -623,  -623,  -623,  -623,  -623,
-    -623,    33,    33,   222,  -623,  -623,  -623,  -623,    33,  -623,
-    -623,  -623,  -623,  -623,    33,   196,  -623,   -10,   201,   208,
-     218,  -623,  -623,  -623,  -623,  -623,    93,  -623,  -623,  -623,
-    -623,  -623,  -623,  -623,  -623,   256,   262,     2,   624,  -623,
-    -623,  -623,    10,  -623,   250,   250,   235,  -623,    78,   310,
-     310,  -623,  -623,   254,  -623,  -623,  -623,  -623,  -623,  -623,
-    -623,   -32,  1645,  -623,   125,   139,   806,    93,  -623,    10,
-    -109,   137,  1645,   153,    78,    78,  -623,  -623,  1686,  -623,
-    -623,  1945,   314,  -623,  -623,  -623,  -623,  -623,  -623,  1974,
-    -623,   -12,  2208,  -623,   301,  -623,  -623,    10,  -623,   167,
-     177,  1992,  1992,   170,  -107,  1992,  -623,   334,   193,  -623,
-    1945,  1992,    93,   197,    10,   205,  -623,    63,   346,   347,
-     348,   349,   355,   243,   357,  1509,   312,  -623,   122,  -623,
-    -623,  -623,  -623,  -623,   324,  2033,   129,   371,   310,  -623,
-    -623,  -623,  -623,  -623,  -623,  -623,  -623,  -623,  -623,  -623,
-    -623,  -623,  -623,  -623,  -623,  -623,   245,   548,   245,   548,
-    1992,  1992,  1992,  1992,  -623,  -623,  -623,  -623,  -623,  -623,
-    -623,  -623,  -623,  -623,  -623,  -623,  1992,  1992,  1992,  1992,
-    1992,  1992,  1992,  1992,  1992,  1992,  1992,  1992,  -623,   310,
-    -623,    39,  -623,  -623,   331,  1704,  -623,   -31,   -28,  -623,
-     216,    10,   226,  -623,   312,     8,  1686,  -623,  -623,  -623,
-    -623,  -623,  -623,  -623,  -623,  -623,  -623,  -623,   245,   548,
-     245,   548,   229,   230,   231,   232,   233,   234,   236,  1745,
-    2051,  1126,   370,   237,   246,   247,  -623,  -623,  -623,   251,
-    -623,    93,   908,  -623,   240,  1076,  1076,  -623,  1076,  1974,
-    -623,  -623,  -623,  -623,  -623,  -623,  -623,  -623,  -623,  -623,
-    1992,  -623,  -623,  -623,  -623,  -623,  -623,  -623,  -623,  -623,
-    -623,  -623,  -623,  -623,  -623,  -623,  -623,  1992,  1992,  1992,
-     -40,    22,  -623,   908,     6,   242,   249,   253,   257,   258,
-     260,   908,   908,   908,   908,   908,   369,  1974,  1992,  1992,
-     407,  -623,  -623,  -623,  -623,  -623,  -623,  -623,  -623,  -623,
-    -623,  -623,  -623,   158,  -623,  -623,  -623,  -623,   158,  -623,
-     153,   376,   259,   264,   265,   266,  1945,  1945,  1945,  1945,
-    1945,  1945,  1945,  -623,  -623,    66,  1170,  -111,  -623,   -88,
-    -623,  1945,  1945,  1945,   267,  1764,  -623,  -623,  -623,  -623,
-    -623,  -623,  -623,  -623,  -623,  -623,   363,  1808,  2107,  1403,
-     406,  -623,  -623,  -623,  -623,  1992,   269,  -623,   270,  1076,
-     908,   908,   908,   908,    25,  -623,    43,  -623,  -623,  1076,
-     268,  1992,  1992,  1992,  1992,  1992,   272,   277,   279,   280,
-     281,  1992,  1076,   908,   284,  -623,  -623,  -623,  -623,  -623,
-    -623,  -623,  -623,   267,   267,  1992,  1945,  1945,  1945,  1945,
-    -623,   285,   286,   287,   288,   277,   289,  1945,  -623,   283,
-    1357,   -87,  -623,  -623,   292,   295,   418,    16,  -623,  -623,
-      10,   297,   300,  -623,   439,  -623,    73,  1449,   -59,  -623,
-     -69,  -623,  -623,   446,   454,   315,   322,   332,   335,   336,
-    1076,   487,  1076,   338,   339,  1076,   340,    10,  -623,   341,
-     342,   490,   499,   354,  1992,  1076,  1076,    10,   361,   359,
-    1992,  -623,  -623,     3,   362,   365,   366,   367,   130,  1945,
-    1945,  1945,  1945,   146,  1945,  -623,  -623,   374,  1945,  1945,
-    1992,   507,   517,  -623,   267,   119,  1866,  -623,   377,  -623,
-     379,   -65,  -623,  -623,  1076,  1076,  2154,  1076,  1076,  1076,
-    1076,   359,  -623,   359,  1992,  1076,   383,  1992,  1992,  1992,
-    -623,  -623,   530,   908,  -623,  -623,  2154,   494,  -623,   908,
-    -623,  1945,  1945,  1945,  1945,  -623,   384,   389,   390,   391,
-    -623,   277,  -623,   394,   396,    28,  -623,  -623,  -623,  -623,
-    -623,  -623,    10,   -20,   533,  -623,   392,   403,   393,    23,
-      10,   161,  -623,  -623,  -623,  -623,  -623,  -623,  -623,   402,
-    1076,  -623,  -623,  -623,  -623,   277,   168,   359,   410,   411,
-     412,   413,  1945,  -623,  1945,  1945,   176,  -623,  -623,  -623,
-     119,  -623,   522,  -623,  -623,   561,    -1,   756,   756,  -623,
-    2213,  -623,   414,   354,  -623,  -623,  -623,  -623,  -623,  -623,
-     422,   423,   424,  -623,  -623,   584,   436,  1076,  -623,  1222,
-       1,   433,   434,  -623,  -623,   173,    23,    10,  -623,   158,
-    -623,  -623,  -623,  -623,   570,  -623,  -623,   435,  -623,  1222,
-     331,   331,   579,   756,   756,  -623,   580,   440,  1076,  -623,
-    -623,  1076,   582,   527,   331,   331,  -623,  1076,   588,  -623,
-    1076,  -623
+     498,  -615,  -615,  -615,  -615,  -615,  -615,  -615,     2,  -101,
+      46,   -19,   101,    -9,   227,  -615,   168,   547,  -615,    49,
+     266,    22,    25,  -615,    24,   170,  -615,  1932,  -615,  -615,
+    -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,
+    -615,   -81,   -81,   181,  -615,  -615,  -615,  -615,   -81,  -615,
+    -615,  -615,  -615,  -615,   -81,   205,  -615,   -10,   197,   212,
+     219,  -615,  -615,  -615,  -615,  -615,    97,  -615,  -615,  -615,
+    -615,  -615,  -615,  -615,  -615,   259,   263,     3,   629,  -615,
+    -615,  -615,   -12,  -615,   240,   240,   211,  -615,   142,   387,
+     387,  -615,  -615,    77,  -615,  -615,  -615,  -615,  -615,  -615,
+    -615,   -53,  1650,  -615,   120,   143,   811,    97,  -615,   -12,
+    -112,   173,  1650,   166,   142,   142,  -615,  -615,  1691,  -615,
+    -615,  1950,   335,  -615,  -615,  -615,  -615,  -615,  -615,  1979,
+    -615,    -8,   184,  2213,  2213,  -615,   325,  -615,  -615,   -12,
+    -615,   193,   196,  1997,  1997,   189,  -104,  1997,  -615,   355,
+     202,  -615,  1950,  1997,    97,   204,   -12,   242,  -615,    41,
+     353,   354,   361,   362,   366,   277,   368,  1514,   323,  -615,
+     141,  -615,  -615,  -615,  -615,  -615,  -615,   322,  2038,    72,
+     369,   387,  -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,
+    -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,   559,
+     285,   559,   285,  1997,  1997,  1997,  1997,  -615,  -615,  -615,
+    -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,  1997,
+    1997,  1997,  1997,  1997,  1997,  1997,  1997,  1997,  1997,  1997,
+    1997,  -615,   387,  -615,   104,  -615,  -615,  -615,  -615,   183,
+    1709,  -615,   -34,   -41,  -615,   238,   -12,   249,  -615,   323,
+     -29,  1691,  -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,
+    -615,  -615,  -615,   559,   285,   559,   285,   251,   252,   255,
+     256,   257,   261,   262,  1750,  2056,  1131,   394,   264,   265,
+     268,  -615,  -615,  -615,   269,  -615,    97,   913,  -615,   272,
+    1081,  1081,  -615,  1081,  1979,  -615,  -615,  -615,  -615,  -615,
+    -615,  -615,  -615,  -615,  -615,  1997,  -615,  -615,  -615,  -615,
+    -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,
+    -615,  -615,  1997,  1997,  1997,   -28,    67,  -615,   913,   -33,
+     273,   274,   275,   276,   282,   284,   913,   913,   913,   913,
+     913,   385,  1979,  1997,  1997,   423,  -615,  -615,  -615,  -615,
+    -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,   198,  -615,
+    -615,  -615,  -615,   198,  -615,   166,   390,   280,   288,   289,
+     300,  1950,  1950,  1950,  1950,  1950,  1950,  1950,  -615,  -615,
+     -52,  1175,  -107,  -615,   -79,  -615,  1950,  1950,  1950,   298,
+    1769,  -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,
+    -615,   398,  1813,  2112,  1408,   407,  -615,  -615,  -615,  -615,
+    1997,   301,  -615,   302,  1081,   913,   913,   913,   913,    18,
+    -615,    28,  -615,  -615,  1081,   297,  1997,  1997,  1997,  1997,
+    1997,   306,   308,   311,   316,   317,  1997,  1081,   913,   318,
+    -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,   298,   298,
+    1997,  1950,  1950,  1950,  1950,  -615,   319,   321,   324,   326,
+     308,   336,  1950,  -615,   315,  1362,   -58,  -615,  -615,   337,
+     339,   447,    15,  -615,  -615,   -12,   340,   343,  -615,   473,
+    -615,   -40,  1454,  -106,  -615,    -2,  -615,  -615,   486,   487,
+     348,   346,   347,   359,   363,  1081,   504,  1081,   364,   367,
+    1081,   370,   -12,  -615,   371,   372,   522,   530,   379,  1997,
+    1081,  1081,   -12,   389,   382,  1997,  -615,  -615,   -14,   388,
+     391,   392,   393,   134,  1950,  1950,  1950,  1950,   135,  1950,
+    -615,  -615,   397,  1950,  1950,  1997,   527,   551,  -615,   298,
+      40,  1871,  -615,   396,  -615,   401,    52,  -615,  -615,  1081,
+    1081,  2159,  1081,  1081,  1081,  1081,   382,  -615,   382,  1997,
+    1081,   399,  1997,  1997,  1997,  -615,  -615,   553,   913,  -615,
+    -615,  2159,   506,  -615,   913,  -615,  1950,  1950,  1950,  1950,
+    -615,   412,   403,   413,   414,  -615,   308,  -615,   417,   418,
+       8,  -615,  -615,  -615,  -615,  -615,  -615,   -12,     4,   557,
+    -615,   416,   420,   421,    -4,   -12,   161,  -615,  -615,  -615,
+    -615,  -615,  -615,  -615,   422,  1081,  -615,  -615,  -615,  -615,
+     308,   162,   382,   427,   428,   435,   436,  1950,  -615,  1950,
+    1950,   188,  -615,  -615,  -615,    40,  -615,   541,  -615,  -615,
+     564,     5,   761,   761,  -615,  2218,  -615,   431,   379,  -615,
+    -615,  -615,  -615,  -615,  -615,   439,   442,   443,  -615,  -615,
+     598,   451,  1081,  -615,  1227,     7,   448,   449,  -615,  -615,
+     100,    -4,   -12,  -615,   198,  -615,  -615,  -615,  -615,   588,
+    -615,  -615,   454,  -615,  1227,   183,   183,   600,   761,   761,
+    -615,   601,   455,  1081,  -615,  -615,  1081,   603,   549,   183,
+     183,  -615,  1081,   604,  -615,  1081,  -615
 };
 
 /* YYPGOTO[NTERM-NUM].  */
 static const yytype_int16 yypgoto[] =
 {
-    -623,   477,   478,   480,  -164,  -152,  -170,  -623,     0,   -17,
-    -146,   523,     4,  -623,  -623,  -623,  -623,    64,  -623,  -623,
-    -623,  -145,  -623,  -445,  -623,  -238,  -623,  -623,  -295,    26,
-    -623,  -421,  -623,  -623,   -26,   380,  -127,  -623,   506,   515,
-     -86,  -162,  -262,    89,   223,   378,  -623,  -623,   605,  -623,
-    -623,  -623,  -623,  -623,  -623,  -623,  -623,  -623,  -623,  -623,
-     535,  -623,  -623,  -623,  -623,  -623,  -623,  -622,   -80,   174,
-    -189,  -623,  -623,   566,  -623,  -623,  -623,  -623,  -623,    60,
-     178,  -437,  -623,  -623,  -623,  -623
+    -615,    96,   112,   190,  -165,  -160,  -178,  -615,     0,   -11,
+    -140,   533,  -615,     6,  -615,  -615,  -615,  -615,    37,  -615,
+    -615,  -615,  -144,  -615,  -463,  -615,  -238,  -615,  -615,  -323,
+      29,  -615,  -424,  -615,  -615,   -26,   410,  -125,  -615,   516,
+     523,   -86,  -162,  -267,   200,   267,   380,  -615,  -615,   613,
+    -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,  -615,
+    -615,   542,  -615,  -615,  -615,  -615,  -615,  -615,  -614,   -80,
+     174,  -190,  -615,  -615,   576,  -615,   500,  -615,  -615,  -615,
+      76,   209,  -447,  -615,   531,  -615,  -615
 };
 
 /* YYTABLE[YYPACT[STATE-NUM]].  What to do in state STATE-NUM.  If
    positive, shift that token.  If negative, reduce the rule which
    number is the opposite.  If zero, do what YYDEFACT says.
    If YYTABLE_NINF, syntax error.  */
-#define YYTABLE_NINF -215
+#define YYTABLE_NINF -216
 static const yytype_int16 yytable[] =
 {
-      11,    82,   168,   276,    13,   358,   105,   288,   377,   379,
-     287,    91,   287,   322,   531,   111,   169,    11,   523,    94,
-     278,    13,   511,   512,   111,   535,   417,   111,   326,   327,
-     328,   329,   330,   289,   318,   166,   490,   677,   336,    29,
-      30,    31,    32,    33,    34,    35,    36,   319,    37,   457,
-     531,   145,   109,   145,   492,    24,   462,   687,   111,    26,
-     146,   111,   240,   111,   244,   111,   -55,   -55,   -55,   -55,
-     532,    21,   457,   457,    25,   247,   137,   111,  -146,   491,
-     109,   463,   527,   111,   337,   277,   137,    22,    27,   248,
-     249,   457,   154,    11,   362,   457,   364,   491,   359,   360,
-     543,   457,    28,   154,   596,    84,    85,   363,   542,   365,
-     119,   120,    89,   588,   461,   237,   238,   112,    90,   241,
-     414,   -67,   436,   437,   438,   245,   112,   439,   134,   112,
-      58,   440,   441,   135,   354,   476,   478,   480,     1,   355,
-     285,     3,     2,     5,   626,     4,   286,   630,    44,   282,
-     434,    38,    39,    40,   637,   638,   170,   338,   339,    95,
-     112,   570,   409,   112,   658,   112,   678,   112,    59,   419,
-     106,   -67,   279,   340,   320,   321,   282,   323,   643,   112,
-    -146,    62,   416,   -67,  -146,   112,   629,    38,    39,    40,
-     324,   282,   282,   282,   282,   282,   331,   332,   333,   334,
-     335,   282,   403,   150,   151,   403,   403,    60,   403,   137,
-     432,   682,    64,    65,   568,   541,   482,    91,   680,   681,
-     154,   683,   684,    98,     1,     2,   457,     3,     4,     5,
-      99,   458,   496,   457,   498,   499,   500,    46,   539,    47,
-     100,   341,   342,   403,   694,   695,   250,   251,   252,   253,
-     102,   403,   403,   403,   403,   403,   606,    86,   607,    87,
-     103,   343,   344,   154,   345,   346,   104,   347,   348,   349,
-      50,    51,    52,     1,   410,    53,     3,   116,     5,   117,
-     450,   451,   452,   453,   454,   455,   456,    87,   575,   141,
-     554,   411,   412,   413,   147,   464,   465,   466,   276,   593,
-     436,   437,   438,   142,   580,   439,   562,   114,   115,   440,
-     441,   154,   433,   282,   149,   436,   437,   438,   167,   639,
-     439,   640,   645,   233,   440,   441,   644,   235,   640,   403,
-     403,   403,   403,   403,   653,   236,   562,   239,   242,   403,
-     290,   291,   292,   293,   294,   295,   296,   297,   298,   299,
-     460,   243,   403,   403,   246,   -56,   -57,   -60,   -59,   470,
-     514,   515,   516,   517,   -58,   608,   254,   111,   611,   612,
-     613,   525,   122,   123,   124,   125,   126,   127,   128,   282,
-     277,   280,   287,   356,   357,   340,   366,   367,   368,   369,
-     370,   371,   380,   372,   381,   282,   497,   282,   282,   282,
-     405,   665,   420,   382,   383,   507,   669,   431,   385,   421,
-     403,   435,   403,   422,   445,   403,   446,   423,   424,   513,
-     425,   447,   448,   449,   473,   403,   403,   467,   481,   483,
-     484,   495,   501,   576,   577,   578,   579,   502,   581,   504,
-     505,   506,   583,   584,   510,   519,   520,   521,   522,   524,
-     526,   460,   528,   341,   342,   529,   530,   536,   537,   406,
-     407,   538,   408,   544,   403,   403,   659,   403,   403,   403,
-     403,   545,   546,   343,   344,   403,   345,   346,   563,   347,
-     348,   349,   547,   403,   569,   618,   619,   620,   621,   403,
-     679,   552,   548,  -214,   560,   549,   550,   418,   554,   555,
-     557,   558,   559,   561,   585,   426,   427,   428,   429,   430,
-     592,   -69,     1,     2,   562,     3,     4,     5,   566,   567,
-     600,   587,   571,     6,     7,   572,   573,   574,   282,   586,
-     403,   282,   282,   282,   614,   589,   650,   594,   651,   652,
-     600,   582,  -213,   610,   622,     8,   595,   623,   491,     9,
-     624,   625,   627,    10,   628,   633,   636,   403,   403,   634,
-     -69,     1,     2,   635,     3,     4,     5,   641,   646,   647,
-     648,   649,     6,     7,   301,   302,   655,   403,   657,   668,
-     670,   671,   672,   485,   486,   487,   488,   489,   673,   674,
-     -18,   -19,   685,   494,     8,   686,   688,   691,     9,   697,
-     692,   698,    10,   403,   403,   700,   508,   509,   403,   225,
-     226,   403,   227,   654,   667,   352,   132,   403,   148,   631,
-     403,   144,    45,    97,   361,   131,   616,     0,   518,     0,
-     589,    64,    65,     0,   107,    67,    68,    69,    70,    71,
-      72,    73,     0,     1,     2,     0,     3,     4,     5,   303,
-     304,   305,   306,   307,   308,   309,   310,   311,   312,   313,
-     314,   315,   316,     0,   551,     0,   553,     0,     0,   556,
-       0,     0,     0,     0,    74,     0,     0,     0,     0,   564,
-     565,     0,     0,     0,     0,     0,     0,     0,     0,     0,
+      11,    82,   293,   422,   170,   281,    13,   105,   382,   384,
+     363,    91,   540,   528,   111,   327,   292,    11,   292,    94,
+     171,   111,   111,    13,   516,   517,   111,   111,   283,   495,
+     331,   332,   333,   334,   335,   168,   323,   294,   536,   497,
+     341,   111,   324,   111,   -55,   -55,   -55,   -55,   147,   536,
+     682,  -147,   109,   462,   462,    21,   147,   148,    24,     1,
+     467,   547,     3,   111,     5,   245,   249,   253,   254,   537,
+     692,    22,   496,    38,    39,    40,   139,   252,    84,    85,
+     109,   462,   496,   290,   132,    89,   139,   282,   342,   291,
+     468,    90,   156,    11,   345,    46,     1,    47,   367,     3,
+     369,     5,   462,   156,   368,    25,   370,   136,   462,   364,
+     365,   532,   137,   463,   466,   593,   112,   242,   243,    27,
+     462,   246,   111,   112,   112,   544,   360,   250,   112,   112,
+     424,   359,   419,   -67,   635,   481,   483,   485,   687,   631,
+      26,   642,   643,   112,   575,   112,   441,   442,   443,   -67,
+      28,   444,   287,  -147,   439,   445,   446,  -147,   462,    95,
+     172,     2,   346,   347,     4,   112,   634,   548,    44,   414,
+     663,   106,   683,   648,   119,   120,   284,   325,   326,   287,
+     328,    58,   348,   349,    59,   350,   351,    60,   352,   353,
+     354,   573,    62,   329,   287,   287,   287,   287,   287,   336,
+     337,   338,   339,   340,   287,   685,   686,   408,   688,   689,
+     408,   408,   462,   408,   139,   546,    86,   437,    87,    98,
+     487,   601,   343,   344,   112,   156,    91,   421,   -67,   228,
+     228,   699,   700,   611,    99,   612,   501,   345,   503,   504,
+     505,   100,   441,   442,   443,   229,   229,   444,   408,    64,
+      65,   445,   446,   116,   102,   117,   408,   408,   408,   408,
+     408,     1,     2,   103,     3,     4,     5,   104,   156,    29,
+      30,    31,    32,    33,    34,    35,    36,    87,    37,   415,
+     255,   256,   257,   258,   143,   455,   456,   457,   458,   459,
+     460,   461,   580,   585,   559,   567,   416,   417,   418,   650,
+     469,   470,   471,   281,   598,   346,   347,   144,    50,    51,
+      52,   306,   307,    53,   152,   153,   156,   438,   287,   644,
+     649,   645,   645,   230,   230,   348,   349,   151,   350,   351,
+     149,   352,   353,   354,   408,   408,   408,   408,   408,   169,
+     441,   442,   443,   174,   408,   444,   658,   238,   567,   445,
+     446,   114,   115,   240,   241,   465,   244,   408,   408,   247,
+     248,   251,   -56,   -57,   475,   519,   520,   521,   522,   613,
+     -60,   -59,   616,   617,   618,   -58,   530,   259,   111,   285,
+     292,    38,    39,    40,   287,   282,   308,   309,   310,   311,
+     312,   313,   314,   315,   316,   317,   318,   319,   320,   321,
+     287,   502,   287,   287,   287,   361,   670,   362,   371,   372,
+     512,   674,   373,   374,   375,   408,   385,   408,   376,   377,
+     408,   386,   387,   436,   518,   388,   390,   440,   450,   486,
+     408,   408,   410,   425,   426,   427,   428,   451,   581,   582,
+     583,   584,   429,   586,   430,   452,   453,   588,   589,   122,
+     123,   124,   125,   126,   127,   128,   465,   454,   472,   478,
+     500,   488,   489,   664,   411,   412,   506,   413,   507,   408,
+     408,   509,   408,   408,   408,   408,   510,   511,   515,   524,
+     408,   525,   531,   568,   526,   535,   527,   684,   408,   574,
+     623,   624,   625,   626,   408,   543,   529,   533,  -215,   534,
+     541,   542,   423,   549,   550,   551,   552,   553,   557,   590,
+     431,   432,   433,   434,   435,   597,   -69,     1,     2,   554,
+       3,     4,     5,   555,   559,   605,   565,   560,     6,     7,
+     562,   563,   564,   287,   566,   408,   287,   287,   287,   567,
+     594,   655,   572,   656,   657,   605,   571,  -214,   576,   591,
+       8,   577,   578,   579,     9,   592,   599,   619,    10,   615,
+     496,   628,   408,   408,   587,   -69,     1,     2,   600,     3,
+       4,     5,   627,   629,   630,   632,   633,     6,     7,   638,
+     640,   662,   408,   639,   641,   651,   652,   646,   490,   491,
+     492,   493,   494,   653,   654,   660,   673,   675,   499,     8,
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+       0,    74,     0,     0,     0,     0,     0,     0,     0,     0,
+       0,    75,    76,     0,     0,    77,     0,    78,     0,    64,
+      65,     0,    66,    67,    68,    69,    70,    71,    72,    73,
+       0,     1,     2,     0,     3,     4,     5,    64,    65,     0,
+     107,   159,   160,   161,   162,   163,   164,    73,     0,     1,
+       2,     0,     3,     4,     5,    75,    76,     0,   480,    77,
+       0,    78,    74,     0,     0,     0,    64,    65,     0,   154,
+      67,    68,    69,    70,    71,    72,    73,     0,     1,     2,
+      74,     3,     4,     5,    64,    65,     0,   107,    67,    68,
       69,    70,    71,    72,    73,     0,     1,     2,     0,     3,
-       4,     5,    64,    65,     0,   107,   157,   158,   159,   160,
-     161,   162,    73,     0,     1,     2,     0,     3,     4,     5,
-      75,    76,     0,   475,    77,     0,    78,    74,     0,     0,
-       0,    64,    65,     0,   152,    67,    68,    69,    70,    71,
-      72,    73,     0,     1,     2,    74,     3,     4,     5,    64,
-      65,     0,   107,    67,    68,    69,    70,    71,    72,    73,
+       4,     5,     0,     0,     0,     0,     0,     0,     0,    74,
+       0,     0,     0,    75,    76,     0,     0,    77,     0,    78,
+       0,     0,     0,     0,     0,    64,    65,    74,   286,    67,
+      68,    69,    70,    71,    72,    73,     0,     1,     2,     0,
+       3,     4,     5,    64,    65,     0,   107,   159,   160,   161,
+     162,   163,   164,    73,     0,     1,     2,     0,     3,     4,
+       5,     0,     0,     0,     0,     0,     0,     0,    74,     0,
+       0,     0,     0,     0,    75,    76,     0,     0,    77,     0,
+      78,     0,     0,     0,     0,     0,    74,     0,     0,     0,
+       0,     0,    75,    76,     0,     0,    77,     0,    78,    64,
+      65,     0,   107,   159,   160,   161,   162,   163,   164,    73,
        0,     1,     2,     0,     3,     4,     5,     0,     0,     0,
-       0,     0,     0,     0,    74,     0,     0,     0,    75,    76,
-       0,     0,    77,     0,    78,     0,     0,     0,     0,     0,
-      64,    65,    74,   281,    67,    68,    69,    70,    71,    72,
-      73,     0,     1,     2,     0,     3,     4,     5,    64,    65,
-       0,   107,   157,   158,   159,   160,   161,   162,    73,     0,
-       1,     2,     0,     3,     4,     5,     0,     0,     0,     0,
-       0,     0,     0,    74,     0,     0,     0,     0,     0,    75,
-      76,     0,     0,    77,     0,    78,     0,     0,     0,     0,
-       0,    74,     0,     0,     0,     0,     0,    75,    76,     0,
-       0,    77,     0,    78,    64,    65,     0,   107,   157,   158,
-     159,   160,   161,   162,    73,     0,     1,     2,     0,     3,
-       4,     5,     0,     0,     0,     0,    75,    76,     0,     0,
-      77,     0,    78,     0,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,     0,    75,    76,     0,    74,    77,     0,
-      78,    64,    65,     0,   107,    67,    68,    69,    70,    71,
-      72,   599,     0,     1,     2,     0,     3,     4,     5,     0,
+       0,    75,    76,     0,     0,    77,     0,    78,     0,     0,
+       0,     0,     0,     0,     0,     0,     0,     0,     0,    75,
+      76,     0,    74,    77,     0,    78,    64,    65,     0,   107,
+      67,    68,    69,    70,    71,    72,   604,     0,     1,     2,
+       0,     3,     4,     5,     0,     0,     0,     0,     0,     0,
        0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,     0,     0,    75,    76,     0,     0,    77,
-       0,    78,     0,     0,    74,     0,     0,     0,     0,     0,
-       0,     0,     0,    75,    76,     0,     0,    77,     0,   376,
-      64,    65,     0,   107,    67,    68,    69,    70,    71,    72,
-     666,     0,     1,     2,     0,     3,     4,     5,     0,     0,
-       0,     0,     0,     0,   172,     0,     0,     0,     0,     0,
+      75,    76,     0,     0,    77,     0,    78,     0,     0,    74,
+       0,     0,     0,     0,     0,     0,     0,     0,    75,    76,
+       0,     0,    77,     0,   381,    64,    65,     0,   107,    67,
+      68,    69,    70,    71,    72,   671,     0,     1,     2,     0,
+       3,     4,     5,     0,     0,     0,     0,     0,     0,   175,
        0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,    74,     0,   173,   174,     0,     0,    75,
-      76,     0,     0,    77,     0,   477,     0,     0,   175,   176,
-     177,   178,   179,   180,   181,   182,   183,   184,   185,   186,
-     187,   188,   189,   190,   191,   192,   193,   194,   195,   196,
-     197,   198,   199,     0,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,     0,     0,     0,    75,    76,     0,     0,
-      77,     0,    78,   200,   201,   202,     0,     0,   203,   204,
-     205,   206,   207,   208,   209,   210,   211,   212,   213,   214,
-     215,   216,   217,   218,   219,   220,   221,   222,   223,   224,
+       0,     0,     0,     0,     0,     0,     0,     0,    74,     0,
+     176,   177,     0,     0,    75,    76,     0,     0,    77,     0,
+     482,     0,     0,   178,   179,   180,   181,   182,   183,   184,
+     185,   186,   187,   188,   189,   190,   191,   192,   193,   194,
+     195,   196,   197,   198,   199,   200,   201,   202,     0,     0,
+       0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
+       0,    75,    76,     0,     0,    77,     0,    78,   203,   204,
+     205,     0,     0,   206,   207,   208,   209,   210,   211,   212,
+     213,   214,   215,   216,   217,   218,   219,   220,   221,   222,
+     223,   224,   225,   226,   227,     0,     0,     0,     0,     0,
        0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
        0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,     0,     0,    75,    76,     0,     0,    77,
-       0,    78
+      75,    76,     0,     0,    77,     0,    78
 };
 
 static const yytype_int16 yycheck[] =
 {
-       0,    27,   129,   165,     0,   243,     4,   177,   270,   271,
-      11,    21,    11,   202,    34,    55,    28,    17,   455,    29,
-     166,    17,   443,   444,    55,   470,   321,    55,   217,   218,
-     219,   220,   221,   178,   198,   121,    11,   659,   227,    42,
-      43,    44,    45,    46,    47,    48,    49,   199,    51,   160,
-      34,   160,    78,   160,    11,   159,   167,   679,    55,   159,
-     169,    55,   169,    55,   150,    55,     3,     4,     5,     6,
-      54,    53,   160,   160,    59,   155,   102,    55,    55,    54,
-     106,   169,   169,    55,   229,   165,   112,    69,    18,    26,
-      27,   160,   118,    93,   258,   160,   260,    54,   244,   245,
-     169,   160,   159,   129,   169,    41,    42,   259,   167,   261,
-      32,    33,    48,   534,   376,   141,   142,   157,    54,   145,
-     160,   161,   142,   143,   144,   151,   157,   147,   160,   157,
-     159,   151,   152,   165,   165,   397,   398,   399,    19,   167,
-      11,    22,    20,    24,   581,    23,    17,   592,     0,   175,
-     339,   154,   155,   156,   599,   600,   168,   118,   119,   169,
-     157,   158,   289,   157,   165,   157,   165,   157,   159,   163,
-     168,   161,   168,    54,   200,   201,   202,   203,   615,   157,
-     157,    22,   160,   161,   161,   157,   158,   154,   155,   156,
-     216,   217,   218,   219,   220,   221,   222,   223,   224,   225,
-     226,   227,   282,   114,   115,   285,   286,   163,   288,   235,
-     337,    38,     7,     8,   509,   477,   405,    21,   663,   664,
-     246,   666,   667,    22,    19,    20,   160,    22,    23,    24,
-      22,   165,   421,   160,   423,   424,   425,    46,   165,    48,
-      22,   122,   123,   323,   689,   690,     3,     4,     5,     6,
-     157,   331,   332,   333,   334,   335,   551,    35,   553,    37,
-       4,   142,   143,   289,   145,   146,     4,   148,   149,   150,
-      42,    43,    44,    19,   300,    47,    22,    42,    24,    44,
-     366,   367,   368,   369,   370,   371,   372,    37,   158,   164,
-     160,   317,   318,   319,   157,   381,   382,   383,   460,   537,
-     142,   143,   144,   164,   158,   147,   160,    84,    85,   151,
-     152,   337,   338,   339,   161,   142,   143,   144,     4,   158,
-     147,   160,   617,    22,   151,   152,   158,   160,   160,   409,
-     410,   411,   412,   413,   158,   158,   160,   167,     4,   419,
-      95,    96,    97,    98,    99,   100,   101,   102,   103,   104,
-     376,   158,   432,   433,   157,     9,     9,     9,     9,   385,
-     446,   447,   448,   449,     9,   554,     9,    55,   557,   558,
-     559,   457,    62,    63,    64,    65,    66,    67,    68,   405,
-     460,    57,    11,   167,   158,    54,   157,   157,   157,   157,
-     157,   157,    22,   157,   157,   421,   422,   423,   424,   425,
-     160,   639,   160,   157,   157,   431,   644,    38,   157,   160,
-     490,     4,   492,   160,    38,   495,   157,   160,   160,   445,
-     160,   157,   157,   157,    61,   505,   506,   160,    22,   160,
-     160,   163,   160,   519,   520,   521,   522,   160,   524,   160,
-     160,   160,   528,   529,   160,   160,   160,   160,   160,   160,
-     167,   477,   160,   122,   123,   160,    38,   160,   158,   285,
-     286,    22,   288,    17,   544,   545,   636,   547,   548,   549,
-     550,    17,   157,   142,   143,   555,   145,   146,   504,   148,
-     149,   150,   160,   563,   510,   571,   572,   573,   574,   569,
-     660,     4,   160,     0,     4,   160,   160,   323,   160,   160,
-     160,   160,   160,     4,   530,   331,   332,   333,   334,   335,
-     536,    18,    19,    20,   160,    22,    23,    24,   157,   160,
-     546,     4,   160,    30,    31,   160,   160,   160,   554,    22,
-     610,   557,   558,   559,     4,   535,   622,   160,   624,   625,
-     566,   167,     0,   160,   160,    52,   167,   158,    54,    56,
-     160,   160,   158,    60,   158,    22,   163,   637,   638,   167,
-      18,    19,    20,   160,    22,    23,    24,   165,   158,   158,
-     158,   158,    30,    31,    26,    27,    54,   657,    17,   165,
-     158,   158,   158,   409,   410,   411,   412,   413,     4,   153,
-     157,   157,    22,   419,    52,   160,    17,    17,    56,    17,
-     160,    74,    60,   683,   684,    17,   432,   433,   688,   132,
-     132,   691,   132,   630,   640,   235,    93,   697,   112,   593,
-     700,   106,    17,    57,   246,    90,   566,    -1,   450,    -1,
-     630,     7,     8,    -1,    10,    11,    12,    13,    14,    15,
-      16,    17,    -1,    19,    20,    -1,    22,    23,    24,   101,
-     102,   103,   104,   105,   106,   107,   108,   109,   110,   111,
-     112,   113,   114,    -1,   490,    -1,   492,    -1,    -1,   495,
-      -1,    -1,    -1,    -1,    50,    -1,    -1,    -1,    -1,   505,
-     506,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
+       0,    27,   180,   326,   129,   167,     0,     4,   275,   276,
+     248,    21,   475,   460,    55,   205,    11,    17,    11,    29,
+      28,    55,    55,    17,   448,   449,    55,    55,   168,    11,
+     220,   221,   222,   223,   224,   121,   201,   181,    34,    11,
+     230,    55,   202,    55,     3,     4,     5,     6,   160,    34,
+     664,    55,    78,   160,   160,    53,   160,   169,   159,    19,
+     167,   167,    22,    55,    24,   169,   152,    26,    27,    54,
+     684,    69,    54,   154,   155,   156,   102,   157,    41,    42,
+     106,   160,    54,    11,     7,    48,   112,   167,   232,    17,
+     169,    54,   118,    93,    54,    46,    19,    48,   263,    22,
+     265,    24,   160,   129,   264,    59,   266,   160,   160,   249,
+     250,   169,   165,   165,   381,   539,   157,   143,   144,    18,
+     160,   147,    55,   157,   157,   165,   167,   153,   157,   157,
+     163,   165,   160,   161,   597,   402,   403,   404,    38,   586,
+     159,   604,   605,   157,   158,   157,   142,   143,   144,   161,
+     159,   147,   178,   157,   344,   151,   152,   161,   160,   169,
+     168,    20,   122,   123,    23,   157,   158,   169,     0,   294,
+     165,   168,   165,   620,    32,    33,   170,   203,   204,   205,
+     206,   159,   142,   143,   159,   145,   146,   163,   148,   149,
+     150,   514,    22,   219,   220,   221,   222,   223,   224,   225,
+     226,   227,   228,   229,   230,   668,   669,   287,   671,   672,
+     290,   291,   160,   293,   240,   482,    35,   342,    37,    22,
+     410,   169,   118,   119,   157,   251,    21,   160,   161,   133,
+     134,   694,   695,   556,    22,   558,   426,    54,   428,   429,
+     430,    22,   142,   143,   144,   133,   134,   147,   328,     7,
+       8,   151,   152,    42,   157,    44,   336,   337,   338,   339,
+     340,    19,    20,     4,    22,    23,    24,     4,   294,    42,
+      43,    44,    45,    46,    47,    48,    49,    37,    51,   305,
+       3,     4,     5,     6,   164,   371,   372,   373,   374,   375,
+     376,   377,   158,   158,   160,   160,   322,   323,   324,   622,
+     386,   387,   388,   465,   542,   122,   123,   164,    42,    43,
+      44,    26,    27,    47,   114,   115,   342,   343,   344,   158,
+     158,   160,   160,   133,   134,   142,   143,   161,   145,   146,
+     157,   148,   149,   150,   414,   415,   416,   417,   418,     4,
+     142,   143,   144,   159,   424,   147,   158,    22,   160,   151,
+     152,    84,    85,   160,   158,   381,   167,   437,   438,     4,
+     158,   157,     9,     9,   390,   451,   452,   453,   454,   559,
+       9,     9,   562,   563,   564,     9,   462,     9,    55,    57,
+      11,   154,   155,   156,   410,   465,   101,   102,   103,   104,
+     105,   106,   107,   108,   109,   110,   111,   112,   113,   114,
+     426,   427,   428,   429,   430,   167,   644,   158,   157,   157,
+     436,   649,   157,   157,   157,   495,    22,   497,   157,   157,
+     500,   157,   157,    38,   450,   157,   157,     4,    38,    22,
+     510,   511,   160,   160,   160,   160,   160,   157,   524,   525,
+     526,   527,   160,   529,   160,   157,   157,   533,   534,    62,
+      63,    64,    65,    66,    67,    68,   482,   157,   160,    61,
+     163,   160,   160,   641,   290,   291,   160,   293,   160,   549,
+     550,   160,   552,   553,   554,   555,   160,   160,   160,   160,
+     560,   160,   167,   509,   160,    38,   160,   665,   568,   515,
+     576,   577,   578,   579,   574,    22,   160,   160,     0,   160,
+     160,   158,   328,    17,    17,   157,   160,   160,     4,   535,
+     336,   337,   338,   339,   340,   541,    18,    19,    20,   160,
+      22,    23,    24,   160,   160,   551,     4,   160,    30,    31,
+     160,   160,   160,   559,     4,   615,   562,   563,   564,   160,
+     540,   627,   160,   629,   630,   571,   157,     0,   160,    22,
+      52,   160,   160,   160,    56,     4,   160,     4,    60,   160,
+      54,   158,   642,   643,   167,    18,    19,    20,   167,    22,
+      23,    24,   160,   160,   160,   158,   158,    30,    31,    22,
+     160,    17,   662,   167,   163,   158,   158,   165,   414,   415,
+     416,   417,   418,   158,   158,    54,   165,   158,   424,    52,
+     158,   158,     4,    56,   153,   157,   157,    60,   688,   689,
+      22,   437,   438,   693,   160,   160,   696,    17,    17,   645,
+      17,    17,   702,    74,   635,   705,    93,   598,   112,   106,
+      17,   251,    90,    57,   134,   635,     7,     8,    -1,    10,
+      11,    12,    13,    14,    15,    16,    17,   571,    19,    20,
+     240,    22,    23,    24,    95,    96,    97,    98,    99,   100,
+     101,   102,   103,   104,   455,   134,    -1,    -1,    -1,   495,
+      -1,   497,    -1,    -1,   500,    -1,    -1,    -1,    -1,    50,
+      -1,    -1,    -1,    -1,   510,   511,    -1,    -1,    -1,    -1,
       -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
       -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
-      -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,   544,   545,
-      -1,   547,   548,   549,   550,    -1,    -1,    -1,    -1,   555,
-      -1,    -1,    -1,    -1,    -1,    -1,    -1,   563,    -1,    -1,
-      -1,    -1,    -1,   569,    -1,    -1,    -1,    -1,    -1,    -1,
-      -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,     3,
-       4,     5,     6,     7,     8,     9,    -1,    -1,    -1,    -1,
-      -1,    -1,    -1,    -1,    -1,    19,    20,    -1,    22,    23,
-      24,    25,    26,    27,   610,    -1,   162,   163,    -1,    -1,
-     166,    -1,   168,   169,    -1,    -1,    40,    41,    -1,    -1,
       -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
-      54,   637,   638,     7,     8,    59,    10,    11,    12,    13,
-      14,    15,    16,    17,    -1,    19,    20,    -1,    22,    23,
-      24,   657,    76,    77,    78,    79,    80,    81,    82,    83,
-      84,    85,    86,    87,    88,    89,    90,    91,    92,    93,
-      94,    -1,    -1,    -1,    -1,    -1,    50,   683,   684,    -1,
-      -1,    -1,   688,    -1,    -1,   691,    -1,    -1,    -1,    -1,
-      -1,   697,    -1,    -1,   700,    -1,   120,   121,   122,   123,
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+      -1,    -1,    -1,   162,   163,    -1,    -1,   166,    -1,   168,
+      -1,    -1,    -1,    -1,    -1,     7,     8,    50,    10,    11,
       12,    13,    14,    15,    16,    17,    -1,    19,    20,    -1,
-      22,    23,    24,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
-      -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,   162,   163,
-      -1,    -1,   166,    -1,   168,    -1,    -1,    -1,    50,    -1,
-      -1,    -1,    -1,    -1,    -1,    -1,   162,   163,    -1,    -1,
-     166,    -1,   168,     7,     8,    -1,    10,    11,    12,    13,
+      22,    23,    24,     7,     8,    -1,    10,    11,    12,    13,
       14,    15,    16,    17,    -1,    19,    20,    -1,    22,    23,
-      24,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
-      -1,    -1,    -1,    -1,    -1,    39,    -1,   162,   163,    -1,
-     165,   166,    -1,   168,    -1,    -1,    50,    -1,    -1,    -1,
-      -1,    -1,    -1,    -1,    -1,    -1,   162,   163,    -1,    -1,
-     166,    -1,   168,    -1,     7,     8,    -1,    10,    11,    12,
-      13,    14,    15,    16,    17,    -1,    19,    20,    -1,    22,
-      23,    24,     7,     8,    -1,    10,    11,    12,    13,    14,
-      15,    16,    17,    -1,    19,    20,    -1,    22,    23,    24,
-     162,   163,    -1,   165,   166,    -1,   168,    50,    -1,    -1,
-      -1,     7,     8,    -1,    10,    11,    12,    13,    14,    15,
-      16,    17,    -1,    19,    20,    50,    22,    23,    24,     7,
+      24,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    50,    -1,
+      -1,    -1,    -1,    -1,   162,   163,    -1,    -1,   166,    -1,
+     168,    -1,    -1,    -1,    -1,    -1,    50,    -1,    -1,    -1,
+      -1,    -1,   162,   163,    -1,    -1,   166,    -1,   168,     7,
        8,    -1,    10,    11,    12,    13,    14,    15,    16,    17,
       -1,    19,    20,    -1,    22,    23,    24,    -1,    -1,    -1,
-      -1,    -1,    -1,    -1,    50,    -1,    -1,    -1,   162,   163,
-      -1,    -1,   166,    -1,   168,    -1,    -1,    -1,    -1,    -1,
-       7,     8,    50,    10,    11,    12,    13,    14,    15,    16,
-      17,    -1,    19,    20,    -1,    22,    23,    24,     7,     8,
-      -1,    10,    11,    12,    13,    14,    15,    16,    17,    -1,
-      19,    20,    -1,    22,    23,    24,    -1,    -1,    -1,    -1,
-      -1,    -1,    -1,    50,    -1,    -1,    -1,    -1,    -1,   162,
-     163,    -1,    -1,   166,    -1,   168,    -1,    -1,    -1,    -1,
-      -1,    50,    -1,    -1,    -1,    -1,    -1,   162,   163,    -1,
-      -1,   166,    -1,   168,     7,     8,    -1,    10,    11,    12,
-      13,    14,    15,    16,    17,    -1,    19,    20,    -1,    22,
-      23,    24,    -1,    -1,    -1,    -1,   162,   163,    -1,    -1,
-     166,    -1,   168,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
-      -1,    -1,    -1,    -1,   162,   163,    -1,    50,   166,    -1,
-     168,     7,     8,    -1,    10,    11,    12,    13,    14,    15,
-      16,    17,    -1,    19,    20,    -1,    22,    23,    24,    -1,
+      -1,   162,   163,    -1,    -1,   166,    -1,   168,    -1,    -1,
+      -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,   162,
+     163,    -1,    50,   166,    -1,   168,     7,     8,    -1,    10,
+      11,    12,    13,    14,    15,    16,    17,    -1,    19,    20,
+      -1,    22,    23,    24,    -1,    -1,    -1,    -1,    -1,    -1,
       -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
-      -1,    -1,    -1,    -1,    -1,   162,   163,    -1,    -1,   166,
-      -1,   168,    -1,    -1,    50,    -1,    -1,    -1,    -1,    -1,
-      -1,    -1,    -1,   162,   163,    -1,    -1,   166,    -1,   168,
-       7,     8,    -1,    10,    11,    12,    13,    14,    15,    16,
-      17,    -1,    19,    20,    -1,    22,    23,    24,    -1,    -1,
-      -1,    -1,    -1,    -1,    36,    -1,    -1,    -1,    -1,    -1,
+     162,   163,    -1,    -1,   166,    -1,   168,    -1,    -1,    50,
+      -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,   162,   163,
+      -1,    -1,   166,    -1,   168,     7,     8,    -1,    10,    11,
+      12,    13,    14,    15,    16,    17,    -1,    19,    20,    -1,
+      22,    23,    24,    -1,    -1,    -1,    -1,    -1,    -1,    36,
       -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
-      -1,    -1,    -1,    50,    -1,    57,    58,    -1,    -1,   162,
-     163,    -1,    -1,   166,    -1,   168,    -1,    -1,    70,    71,
-      72,    73,    74,    75,    76,    77,    78,    79,    80,    81,
-      82,    83,    84,    85,    86,    87,    88,    89,    90,    91,
-      92,    93,    94,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
-      -1,    -1,    -1,    -1,    -1,    -1,   162,   163,    -1,    -1,
-     166,    -1,   168,   115,   116,   117,    -1,    -1,   120,   121,
-     122,   123,   124,   125,   126,   127,   128,   129,   130,   131,
-     132,   133,   134,   135,   136,   137,   138,   139,   140,   141,
+      -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    50,    -1,
+      57,    58,    -1,    -1,   162,   163,    -1,    -1,   166,    -1,
+     168,    -1,    -1,    70,    71,    72,    73,    74,    75,    76,
+      77,    78,    79,    80,    81,    82,    83,    84,    85,    86,
+      87,    88,    89,    90,    91,    92,    93,    94,    -1,    -1,
+      -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
+      -1,   162,   163,    -1,    -1,   166,    -1,   168,   115,   116,
+     117,    -1,    -1,   120,   121,   122,   123,   124,   125,   126,
+     127,   128,   129,   130,   131,   132,   133,   134,   135,   136,
+     137,   138,   139,   140,   141,    -1,    -1,    -1,    -1,    -1,
       -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
       -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
-      -1,    -1,    -1,    -1,    -1,   162,   163,    -1,    -1,   166,
-      -1,   168
+     162,   163,    -1,    -1,   166,    -1,   168
 };
 
 /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
@@ -2745,76 +2749,76 @@
 static const yytype_uint16 yystos[] =
 {
        0,    19,    20,    22,    23,    24,    30,    31,    52,    56,
-      60,   179,   182,   183,   184,   185,   217,   218,   219,   221,
-     220,    53,    69,   226,   159,    59,   159,    18,   159,    42,
+      60,   179,   182,   184,   185,   186,   218,   219,   220,   222,
+     221,    53,    69,   227,   159,    59,   159,    18,   159,    42,
       43,    44,    45,    46,    47,    48,    49,    51,   154,   155,
-     156,   186,   187,   188,     0,   219,    46,    48,   189,   236,
-      42,    43,    44,    47,   190,   233,   235,   243,   159,   159,
-     163,   227,    22,   225,     7,     8,    10,    11,    12,    13,
+     156,   187,   188,   189,     0,   220,    46,    48,   190,   237,
+      42,    43,    44,    47,   191,   234,   236,   244,   159,   159,
+     163,   228,    22,   226,     7,     8,    10,    11,    12,    13,
       14,    15,    16,    17,    50,   162,   163,   166,   168,   179,
-     183,   204,   205,   239,   188,   188,    35,    37,   215,   188,
-     188,    21,   244,   245,    29,   169,   234,   244,    22,    22,
-      22,   228,   157,     4,     4,     4,   168,    10,   169,   205,
-     210,    55,   157,   181,   215,   215,    42,    44,   191,    32,
-      33,   214,    62,    63,    64,    65,    66,    67,    68,   192,
-     231,   231,   182,   248,   160,   165,    39,   205,   206,   208,
-     209,   164,   164,   169,   210,   160,   169,   157,   209,   161,
-     214,   214,    10,   126,   205,   207,   216,    11,    12,    13,
-      14,    15,    16,   177,   178,   205,   211,     4,   207,    28,
-     168,   232,    36,    57,    58,    70,    71,    72,    73,    74,
-      75,    76,    77,    78,    79,    80,    81,    82,    83,    84,
-      85,    86,    87,    88,    89,    90,    91,    92,    93,    94,
-     115,   116,   117,   120,   121,   122,   123,   124,   125,   126,
-     127,   128,   129,   130,   131,   132,   133,   134,   135,   136,
-     137,   138,   139,   140,   141,   172,   173,   174,   246,   253,
-     254,   255,   256,    22,   194,   160,   158,   205,   205,   167,
-     169,   205,     4,   158,   211,   205,   157,   239,    26,    27,
-       3,     4,     5,     6,     9,    25,    40,    41,    91,    92,
-      93,    94,   120,   134,   136,   137,   138,   140,   141,   163,
-     166,   168,   170,   172,   173,   174,   212,   239,   181,   183,
-      57,    10,   205,   241,   242,    11,    17,    11,   177,   192,
-      95,    96,    97,    98,    99,   100,   101,   102,   103,   104,
-     175,    26,    27,   101,   102,   103,   104,   105,   106,   107,
-     108,   109,   110,   111,   112,   113,   114,   176,   175,   176,
-     205,   205,   241,   205,   205,   249,   241,   241,   241,   241,
-     241,   205,   205,   205,   205,   205,   241,   192,   118,   119,
-      54,   122,   123,   142,   143,   145,   146,   148,   149,   150,
-     193,    39,   206,   196,   165,   167,   167,   158,   196,   181,
-     181,   216,   175,   176,   175,   176,   157,   157,   157,   157,
-     157,   157,   157,   165,   211,   213,   168,   213,   169,   213,
-      22,   157,   157,   157,   222,   157,     3,     4,     5,     6,
-       9,    25,    26,    27,    40,    41,    59,   163,   166,   168,
-     170,   212,   238,   239,   240,   160,   240,   240,   240,   207,
-     205,   205,   205,   205,   160,   199,   160,   199,   240,   163,
-     160,   160,   160,   160,   160,   160,   240,   240,   240,   240,
-     240,    38,   207,   205,   241,     4,   142,   143,   144,   147,
-     151,   152,   195,   223,   224,    38,   157,   157,   157,   157,
-     211,   211,   211,   211,   211,   211,   211,   160,   165,   169,
-     205,   213,   167,   169,   211,   211,   211,   160,   202,    39,
-     205,   229,   230,    61,   237,   165,   213,   168,   213,   169,
-     213,    22,   241,   160,   160,   240,   240,   240,   240,   240,
-      11,    54,    11,   251,   240,   163,   241,   205,   241,   241,
-     241,   160,   160,   252,   160,   160,   160,   205,   240,   240,
-     160,   202,   202,   205,   211,   211,   211,   211,   251,   160,
-     160,   160,   160,   252,   160,   211,   167,   169,   160,   160,
-      38,    34,    54,   200,   203,   194,   160,   158,    22,   165,
-     169,   213,   167,   169,    17,    17,   157,   160,   160,   160,
-     160,   240,     4,   240,   160,   160,   240,   160,   160,   160,
-       4,     4,   160,   205,   240,   240,   157,   160,   199,   205,
-     158,   160,   160,   160,   160,   158,   211,   211,   211,   211,
-     158,   211,   167,   211,   211,   205,    22,     4,   202,   179,
-     180,    39,   205,   196,   160,   167,   169,   240,   240,    17,
-     205,   250,   240,   240,   240,   240,   199,   199,   241,   240,
-     160,   241,   241,   241,     4,   240,   250,   240,   211,   211,
-     211,   211,   160,   158,   160,   160,   252,   158,   158,   158,
-     194,   200,   201,    22,   167,   160,   163,   194,   194,   158,
-     160,   165,   240,   252,   158,   199,   158,   158,   158,   158,
-     211,   211,   211,   158,   180,    54,   198,    17,   165,   177,
-     247,   122,   123,   240,   240,   196,    17,   205,   165,   196,
-     158,   158,   158,     4,   153,   197,   240,   238,   165,   177,
-     194,   194,    38,   194,   194,    22,   160,   238,    17,   240,
-     240,    17,   160,   240,   194,   194,   240,    17,    74,   240,
-      17,   240
+     184,   205,   206,   240,   189,   189,    35,    37,   216,   189,
+     189,    21,   245,   246,    29,   169,   235,   245,    22,    22,
+      22,   229,   157,     4,     4,     4,   168,    10,   169,   206,
+     211,    55,   157,   181,   216,   216,    42,    44,   192,    32,
+      33,   215,    62,    63,    64,    65,    66,    67,    68,   193,
+     232,   232,     7,   182,   183,   249,   160,   165,    39,   206,
+     207,   209,   210,   164,   164,   169,   211,   160,   169,   157,
+     210,   161,   215,   215,    10,   126,   206,   208,   217,    11,
+      12,    13,    14,    15,    16,   177,   178,   206,   212,     4,
+     208,    28,   168,   233,   159,    36,    57,    58,    70,    71,
+      72,    73,    74,    75,    76,    77,    78,    79,    80,    81,
+      82,    83,    84,    85,    86,    87,    88,    89,    90,    91,
+      92,    93,    94,   115,   116,   117,   120,   121,   122,   123,
+     124,   125,   126,   127,   128,   129,   130,   131,   132,   133,
+     134,   135,   136,   137,   138,   139,   140,   141,   172,   173,
+     174,   247,   254,   255,   256,   257,   247,   255,    22,   195,
+     160,   158,   206,   206,   167,   169,   206,     4,   158,   212,
+     206,   157,   240,    26,    27,     3,     4,     5,     6,     9,
+      25,    40,    41,    91,    92,    93,    94,   120,   134,   136,
+     137,   138,   140,   141,   163,   166,   168,   170,   172,   173,
+     174,   213,   240,   181,   184,    57,    10,   206,   242,   243,
+      11,    17,    11,   177,   193,    95,    96,    97,    98,    99,
+     100,   101,   102,   103,   104,   175,    26,    27,   101,   102,
+     103,   104,   105,   106,   107,   108,   109,   110,   111,   112,
+     113,   114,   176,   175,   176,   206,   206,   242,   206,   206,
+     250,   242,   242,   242,   242,   242,   206,   206,   206,   206,
+     206,   242,   193,   118,   119,    54,   122,   123,   142,   143,
+     145,   146,   148,   149,   150,   194,    39,   207,   197,   165,
+     167,   167,   158,   197,   181,   181,   217,   175,   176,   175,
+     176,   157,   157,   157,   157,   157,   157,   157,   165,   212,
+     214,   168,   214,   169,   214,    22,   157,   157,   157,   223,
+     157,     3,     4,     5,     6,     9,    25,    26,    27,    40,
+      41,    59,   163,   166,   168,   170,   213,   239,   240,   241,
+     160,   241,   241,   241,   208,   206,   206,   206,   206,   160,
+     200,   160,   200,   241,   163,   160,   160,   160,   160,   160,
+     160,   241,   241,   241,   241,   241,    38,   208,   206,   242,
+       4,   142,   143,   144,   147,   151,   152,   196,   224,   225,
+      38,   157,   157,   157,   157,   212,   212,   212,   212,   212,
+     212,   212,   160,   165,   169,   206,   214,   167,   169,   212,
+     212,   212,   160,   203,    39,   206,   230,   231,    61,   238,
+     165,   214,   168,   214,   169,   214,    22,   242,   160,   160,
+     241,   241,   241,   241,   241,    11,    54,    11,   252,   241,
+     163,   242,   206,   242,   242,   242,   160,   160,   253,   160,
+     160,   160,   206,   241,   241,   160,   203,   203,   206,   212,
+     212,   212,   212,   252,   160,   160,   160,   160,   253,   160,
+     212,   167,   169,   160,   160,    38,    34,    54,   201,   204,
+     195,   160,   158,    22,   165,   169,   214,   167,   169,    17,
+      17,   157,   160,   160,   160,   160,   241,     4,   241,   160,
+     160,   241,   160,   160,   160,     4,     4,   160,   206,   241,
+     241,   157,   160,   200,   206,   158,   160,   160,   160,   160,
+     158,   212,   212,   212,   212,   158,   212,   167,   212,   212,
+     206,    22,     4,   203,   179,   180,    39,   206,   197,   160,
+     167,   169,   241,   241,    17,   206,   251,   241,   241,   241,
+     241,   200,   200,   242,   241,   160,   242,   242,   242,     4,
+     241,   251,   241,   212,   212,   212,   212,   160,   158,   160,
+     160,   253,   158,   158,   158,   195,   201,   202,    22,   167,
+     160,   163,   195,   195,   158,   160,   165,   241,   253,   158,
+     200,   158,   158,   158,   158,   212,   212,   212,   158,   180,
+      54,   199,    17,   165,   177,   248,   122,   123,   241,   241,
+     197,    17,   206,   165,   197,   158,   158,   158,     4,   153,
+     198,   241,   239,   165,   177,   195,   195,    38,   195,   195,
+      22,   160,   239,    17,   241,   241,    17,   160,   241,   195,
+     195,   241,    17,    74,   241,    17,   241
 };
 
 #define yyerrok		(yyerrstatus = 0)
@@ -3629,152 +3633,152 @@
   switch (yyn)
     {
         case 29:
-#line 1139 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1142 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.IPredicate) = ICmpInst::ICMP_EQ; ;}
     break;
 
   case 30:
-#line 1139 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1142 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.IPredicate) = ICmpInst::ICMP_NE; ;}
     break;
 
   case 31:
-#line 1140 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1143 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.IPredicate) = ICmpInst::ICMP_SLT; ;}
     break;
 
   case 32:
-#line 1140 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1143 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.IPredicate) = ICmpInst::ICMP_SGT; ;}
     break;
 
   case 33:
-#line 1141 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1144 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.IPredicate) = ICmpInst::ICMP_SLE; ;}
     break;
 
   case 34:
-#line 1141 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1144 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.IPredicate) = ICmpInst::ICMP_SGE; ;}
     break;
 
   case 35:
-#line 1142 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1145 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.IPredicate) = ICmpInst::ICMP_ULT; ;}
     break;
 
   case 36:
-#line 1142 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1145 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.IPredicate) = ICmpInst::ICMP_UGT; ;}
     break;
 
   case 37:
-#line 1143 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1146 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.IPredicate) = ICmpInst::ICMP_ULE; ;}
     break;
 
   case 38:
-#line 1143 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1146 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.IPredicate) = ICmpInst::ICMP_UGE; ;}
     break;
 
   case 39:
-#line 1147 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1150 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.FPredicate) = FCmpInst::FCMP_OEQ; ;}
     break;
 
   case 40:
-#line 1147 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1150 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.FPredicate) = FCmpInst::FCMP_ONE; ;}
     break;
 
   case 41:
-#line 1148 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1151 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.FPredicate) = FCmpInst::FCMP_OLT; ;}
     break;
 
   case 42:
-#line 1148 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1151 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.FPredicate) = FCmpInst::FCMP_OGT; ;}
     break;
 
   case 43:
-#line 1149 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1152 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.FPredicate) = FCmpInst::FCMP_OLE; ;}
     break;
 
   case 44:
-#line 1149 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1152 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.FPredicate) = FCmpInst::FCMP_OGE; ;}
     break;
 
   case 45:
-#line 1150 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1153 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.FPredicate) = FCmpInst::FCMP_ORD; ;}
     break;
 
   case 46:
-#line 1150 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1153 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.FPredicate) = FCmpInst::FCMP_UNO; ;}
     break;
 
   case 47:
-#line 1151 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1154 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.FPredicate) = FCmpInst::FCMP_UEQ; ;}
     break;
 
   case 48:
-#line 1151 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1154 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.FPredicate) = FCmpInst::FCMP_UNE; ;}
     break;
 
   case 49:
-#line 1152 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1155 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.FPredicate) = FCmpInst::FCMP_ULT; ;}
     break;
 
   case 50:
-#line 1152 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1155 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.FPredicate) = FCmpInst::FCMP_UGT; ;}
     break;
 
   case 51:
-#line 1153 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1156 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.FPredicate) = FCmpInst::FCMP_ULE; ;}
     break;
 
   case 52:
-#line 1153 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1156 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.FPredicate) = FCmpInst::FCMP_UGE; ;}
     break;
 
   case 53:
-#line 1154 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1157 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.FPredicate) = FCmpInst::FCMP_TRUE; ;}
     break;
 
   case 54:
-#line 1155 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1158 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.FPredicate) = FCmpInst::FCMP_FALSE; ;}
     break;
 
   case 65:
-#line 1164 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1167 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.StrVal) = 0; ;}
     break;
 
   case 66:
-#line 1166 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1169 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.UIntVal)=(yyvsp[(3) - (4)].UInt64Val); ;}
     break;
 
   case 67:
-#line 1167 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1170 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.UIntVal)=0; ;}
     break;
 
   case 68:
-#line 1171 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1174 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.StrVal) = (yyvsp[(1) - (2)].StrVal);
     CHECK_FOR_ERROR
@@ -3782,186 +3786,194 @@
     break;
 
   case 69:
-#line 1175 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1178 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.StrVal) = 0;
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 73:
-#line 1183 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 70:
+#line 1183 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
-    (yyval.StrVal) = 0;
-    CHECK_FOR_ERROR
-  ;}
+  (yyval.UIntVal) = (yyvsp[(1) - (2)].UIntVal);
+  CHECK_FOR_ERROR
+;}
     break;
 
   case 74:
-#line 1188 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1192 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
-    (yyval.StrVal) = (yyvsp[(1) - (2)].StrVal);
+    (yyval.StrVal) = 0;
     CHECK_FOR_ERROR
   ;}
     break;
 
   case 75:
-#line 1194 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::InternalLinkage; ;}
+#line 1197 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    {
+    (yyval.StrVal) = (yyvsp[(1) - (2)].StrVal);
+    CHECK_FOR_ERROR
+  ;}
     break;
 
   case 76:
-#line 1195 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::WeakLinkage; ;}
+#line 1203 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::InternalLinkage; ;}
     break;
 
   case 77:
-#line 1196 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::LinkOnceLinkage; ;}
+#line 1204 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::WeakLinkage; ;}
     break;
 
   case 78:
-#line 1197 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::AppendingLinkage; ;}
+#line 1205 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::LinkOnceLinkage; ;}
     break;
 
   case 79:
-#line 1198 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::DLLExportLinkage; ;}
+#line 1206 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::AppendingLinkage; ;}
     break;
 
   case 80:
-#line 1199 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::CommonLinkage; ;}
+#line 1207 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::DLLExportLinkage; ;}
     break;
 
   case 81:
-#line 1203 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::DLLImportLinkage; ;}
+#line 1208 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::CommonLinkage; ;}
     break;
 
   case 82:
-#line 1204 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::ExternalWeakLinkage; ;}
+#line 1212 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::DLLImportLinkage; ;}
     break;
 
   case 83:
-#line 1205 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::ExternalLinkage; ;}
+#line 1213 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::ExternalWeakLinkage; ;}
     break;
 
   case 84:
-#line 1209 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Visibility) = GlobalValue::DefaultVisibility;   ;}
+#line 1214 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::ExternalLinkage; ;}
     break;
 
   case 85:
-#line 1210 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1218 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.Visibility) = GlobalValue::DefaultVisibility;   ;}
     break;
 
   case 86:
-#line 1211 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Visibility) = GlobalValue::HiddenVisibility;    ;}
+#line 1219 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Visibility) = GlobalValue::DefaultVisibility;   ;}
     break;
 
   case 87:
-#line 1212 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Visibility) = GlobalValue::ProtectedVisibility; ;}
+#line 1220 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Visibility) = GlobalValue::HiddenVisibility;    ;}
     break;
 
   case 88:
-#line 1216 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::ExternalLinkage; ;}
+#line 1221 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Visibility) = GlobalValue::ProtectedVisibility; ;}
     break;
 
   case 89:
-#line 1217 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::DLLImportLinkage; ;}
+#line 1225 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::ExternalLinkage; ;}
     break;
 
   case 90:
-#line 1218 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::ExternalWeakLinkage; ;}
+#line 1226 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::DLLImportLinkage; ;}
     break;
 
   case 91:
-#line 1222 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::ExternalLinkage; ;}
+#line 1227 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::ExternalWeakLinkage; ;}
     break;
 
   case 92:
-#line 1223 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::InternalLinkage; ;}
+#line 1231 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::ExternalLinkage; ;}
     break;
 
   case 93:
-#line 1224 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::LinkOnceLinkage; ;}
+#line 1232 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::InternalLinkage; ;}
     break;
 
   case 94:
-#line 1225 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::WeakLinkage; ;}
+#line 1233 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::LinkOnceLinkage; ;}
     break;
 
   case 95:
-#line 1226 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::DLLExportLinkage; ;}
+#line 1234 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::WeakLinkage; ;}
     break;
 
   case 96:
-#line 1230 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::ExternalLinkage; ;}
+#line 1235 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::DLLExportLinkage; ;}
     break;
 
   case 97:
-#line 1231 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::WeakLinkage; ;}
+#line 1239 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::ExternalLinkage; ;}
     break;
 
   case 98:
-#line 1232 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.Linkage) = GlobalValue::InternalLinkage; ;}
+#line 1240 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::WeakLinkage; ;}
     break;
 
   case 99:
-#line 1235 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.UIntVal) = CallingConv::C; ;}
+#line 1241 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.Linkage) = GlobalValue::InternalLinkage; ;}
     break;
 
   case 100:
-#line 1236 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1244 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.UIntVal) = CallingConv::C; ;}
     break;
 
   case 101:
-#line 1237 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.UIntVal) = CallingConv::Fast; ;}
+#line 1245 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.UIntVal) = CallingConv::C; ;}
     break;
 
   case 102:
-#line 1238 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.UIntVal) = CallingConv::Cold; ;}
+#line 1246 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.UIntVal) = CallingConv::Fast; ;}
     break;
 
   case 103:
-#line 1239 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.UIntVal) = CallingConv::X86_StdCall; ;}
+#line 1247 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.UIntVal) = CallingConv::Cold; ;}
     break;
 
   case 104:
-#line 1240 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.UIntVal) = CallingConv::X86_FastCall; ;}
+#line 1248 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.UIntVal) = CallingConv::X86_StdCall; ;}
     break;
 
   case 105:
-#line 1241 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.UIntVal) = CallingConv::X86_SSECall; ;}
+#line 1249 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.UIntVal) = CallingConv::X86_FastCall; ;}
     break;
 
   case 106:
-#line 1242 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1250 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.UIntVal) = CallingConv::X86_SSECall; ;}
+    break;
+
+  case 107:
+#line 1251 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
                    if ((unsigned)(yyvsp[(2) - (2)].UInt64Val) != (yyvsp[(2) - (2)].UInt64Val))
                      GEN_ERROR("Calling conv too large");
@@ -3970,130 +3982,130 @@
                  ;}
     break;
 
-  case 107:
-#line 1249 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.ParamAttrs) = ParamAttr::ZExt;      ;}
-    break;
-
   case 108:
-#line 1250 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1258 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.ParamAttrs) = ParamAttr::ZExt;      ;}
     break;
 
   case 109:
-#line 1251 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.ParamAttrs) = ParamAttr::SExt;      ;}
+#line 1259 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.ParamAttrs) = ParamAttr::ZExt;      ;}
     break;
 
   case 110:
-#line 1252 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1260 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.ParamAttrs) = ParamAttr::SExt;      ;}
     break;
 
   case 111:
-#line 1253 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.ParamAttrs) = ParamAttr::InReg;     ;}
+#line 1261 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.ParamAttrs) = ParamAttr::SExt;      ;}
     break;
 
   case 112:
-#line 1254 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.ParamAttrs) = ParamAttr::StructRet; ;}
+#line 1262 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.ParamAttrs) = ParamAttr::InReg;     ;}
     break;
 
   case 113:
-#line 1255 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.ParamAttrs) = ParamAttr::NoAlias;   ;}
+#line 1263 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.ParamAttrs) = ParamAttr::StructRet; ;}
     break;
 
   case 114:
-#line 1256 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.ParamAttrs) = ParamAttr::ByVal;     ;}
+#line 1264 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.ParamAttrs) = ParamAttr::NoAlias;   ;}
     break;
 
   case 115:
-#line 1257 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
-    { (yyval.ParamAttrs) = ParamAttr::Nest;      ;}
+#line 1265 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.ParamAttrs) = ParamAttr::ByVal;     ;}
     break;
 
   case 116:
-#line 1258 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 1266 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    { (yyval.ParamAttrs) = ParamAttr::Nest;      ;}
+    break;
+
+  case 117:
+#line 1267 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.ParamAttrs) = 
                           ParamAttr::constructAlignmentFromInt((yyvsp[(2) - (2)].UInt64Val));    ;}
     break;
 
-  case 117:
-#line 1262 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 118:
+#line 1271 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.ParamAttrs) = ParamAttr::None; ;}
     break;
 
-  case 118:
-#line 1263 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 119:
+#line 1272 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
                 (yyval.ParamAttrs) = (yyvsp[(1) - (2)].ParamAttrs) | (yyvsp[(2) - (2)].ParamAttrs);
               ;}
     break;
 
-  case 119:
-#line 1268 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 120:
+#line 1277 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.ParamAttrs) = ParamAttr::NoReturn; ;}
     break;
 
-  case 120:
-#line 1269 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 121:
+#line 1278 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.ParamAttrs) = ParamAttr::NoUnwind; ;}
     break;
 
-  case 121:
-#line 1270 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 122:
+#line 1279 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.ParamAttrs) = ParamAttr::ZExt;     ;}
     break;
 
-  case 122:
-#line 1271 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 123:
+#line 1280 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.ParamAttrs) = ParamAttr::SExt;     ;}
     break;
 
-  case 123:
-#line 1272 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 124:
+#line 1281 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.ParamAttrs) = ParamAttr::ReadNone; ;}
     break;
 
-  case 124:
-#line 1273 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 125:
+#line 1282 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.ParamAttrs) = ParamAttr::ReadOnly; ;}
     break;
 
-  case 125:
-#line 1276 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 126:
+#line 1285 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.ParamAttrs) = ParamAttr::None; ;}
     break;
 
-  case 126:
-#line 1277 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 127:
+#line 1286 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
                 (yyval.ParamAttrs) = (yyvsp[(1) - (2)].ParamAttrs) | (yyvsp[(2) - (2)].ParamAttrs);
               ;}
     break;
 
-  case 127:
-#line 1282 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 128:
+#line 1291 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.StrVal) = 0; ;}
     break;
 
-  case 128:
-#line 1283 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 129:
+#line 1292 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
                 (yyval.StrVal) = (yyvsp[(2) - (2)].StrVal);
               ;}
     break;
 
-  case 129:
-#line 1290 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 130:
+#line 1299 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.UIntVal) = 0; ;}
     break;
 
-  case 130:
-#line 1291 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 131:
+#line 1300 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
   (yyval.UIntVal) = (yyvsp[(2) - (2)].UInt64Val);
   if ((yyval.UIntVal) != 0 && !isPowerOf2_32((yyval.UIntVal)))
@@ -4102,13 +4114,13 @@
 ;}
     break;
 
-  case 131:
-#line 1297 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 132:
+#line 1306 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.UIntVal) = 0; ;}
     break;
 
-  case 132:
-#line 1298 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 133:
+#line 1307 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
   (yyval.UIntVal) = (yyvsp[(3) - (3)].UInt64Val);
   if ((yyval.UIntVal) != 0 && !isPowerOf2_32((yyval.UIntVal)))
@@ -4117,8 +4129,8 @@
 ;}
     break;
 
-  case 133:
-#line 1307 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 134:
+#line 1316 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
   for (unsigned i = 0, e = (yyvsp[(2) - (2)].StrVal)->length(); i != e; ++i)
     if ((*(yyvsp[(2) - (2)].StrVal))[i] == '"' || (*(yyvsp[(2) - (2)].StrVal))[i] == '\\')
@@ -4128,28 +4140,28 @@
 ;}
     break;
 
-  case 134:
-#line 1315 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 135:
+#line 1324 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.StrVal) = 0; ;}
     break;
 
-  case 135:
-#line 1316 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 136:
+#line 1325 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.StrVal) = (yyvsp[(1) - (1)].StrVal); ;}
     break;
 
-  case 136:
-#line 1321 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 137:
+#line 1330 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {;}
     break;
 
-  case 137:
-#line 1322 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 138:
+#line 1331 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {;}
     break;
 
-  case 138:
-#line 1323 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 139:
+#line 1332 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     CurGV->setSection(*(yyvsp[(1) - (1)].StrVal));
     delete (yyvsp[(1) - (1)].StrVal);
@@ -4157,8 +4169,8 @@
   ;}
     break;
 
-  case 139:
-#line 1328 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 140:
+#line 1337 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if ((yyvsp[(2) - (2)].UInt64Val) != 0 && !isPowerOf2_32((yyvsp[(2) - (2)].UInt64Val)))
       GEN_ERROR("Alignment must be a power of two");
@@ -4167,24 +4179,24 @@
   ;}
     break;
 
-  case 147:
-#line 1344 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 148:
+#line 1353 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.TypeVal) = new PATypeHolder(OpaqueType::get());
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 148:
-#line 1348 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 149:
+#line 1357 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.TypeVal) = new PATypeHolder((yyvsp[(1) - (1)].PrimType));
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 149:
-#line 1352 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 150:
+#line 1361 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {                             // Pointer type?
     if (*(yyvsp[(1) - (3)].TypeVal) == Type::LabelTy)
       GEN_ERROR("Cannot form a pointer to a basic block");
@@ -4194,8 +4206,8 @@
   ;}
     break;
 
-  case 150:
-#line 1359 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 151:
+#line 1368 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {            // Named types are also simple types...
     const Type* tmp = getTypeVal((yyvsp[(1) - (1)].ValIDVal));
     CHECK_FOR_ERROR
@@ -4203,8 +4215,8 @@
   ;}
     break;
 
-  case 151:
-#line 1364 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 152:
+#line 1373 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {                   // Type UpReference
     if ((yyvsp[(2) - (2)].UInt64Val) > (uint64_t)~0U) GEN_ERROR("Value out of range");
     OpaqueType *OT = OpaqueType::get();        // Use temporary placeholder
@@ -4215,8 +4227,8 @@
   ;}
     break;
 
-  case 152:
-#line 1372 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 153:
+#line 1381 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     // Allow but ignore attributes on function types; this permits auto-upgrade.
     // FIXME: remove in LLVM 3.0.
@@ -4248,8 +4260,8 @@
   ;}
     break;
 
-  case 153:
-#line 1401 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 154:
+#line 1410 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     // Allow but ignore attributes on function types; this permits auto-upgrade.
     // FIXME: remove in LLVM 3.0.
@@ -4276,8 +4288,8 @@
   ;}
     break;
 
-  case 154:
-#line 1426 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 155:
+#line 1435 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {          // Sized array type?
     (yyval.TypeVal) = new PATypeHolder(HandleUpRefs(ArrayType::get(*(yyvsp[(4) - (5)].TypeVal), (yyvsp[(2) - (5)].UInt64Val))));
     delete (yyvsp[(4) - (5)].TypeVal);
@@ -4285,8 +4297,8 @@
   ;}
     break;
 
-  case 155:
-#line 1431 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 156:
+#line 1440 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {          // Vector type?
      const llvm::Type* ElemTy = (yyvsp[(4) - (5)].TypeVal)->get();
      if ((unsigned)(yyvsp[(2) - (5)].UInt64Val) != (yyvsp[(2) - (5)].UInt64Val))
@@ -4299,8 +4311,8 @@
   ;}
     break;
 
-  case 156:
-#line 1441 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 157:
+#line 1450 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {                        // Structure type?
     std::vector<const Type*> Elements;
     for (std::list<llvm::PATypeHolder>::iterator I = (yyvsp[(2) - (3)].TypeList)->begin(),
@@ -4313,16 +4325,16 @@
   ;}
     break;
 
-  case 157:
-#line 1451 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 158:
+#line 1460 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {                                  // Empty structure type?
     (yyval.TypeVal) = new PATypeHolder(StructType::get(std::vector<const Type*>()));
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 158:
-#line 1455 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 159:
+#line 1464 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     std::vector<const Type*> Elements;
     for (std::list<llvm::PATypeHolder>::iterator I = (yyvsp[(3) - (5)].TypeList)->begin(),
@@ -4335,16 +4347,16 @@
   ;}
     break;
 
-  case 159:
-#line 1465 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 160:
+#line 1474 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {                         // Empty structure type?
     (yyval.TypeVal) = new PATypeHolder(StructType::get(std::vector<const Type*>(), true));
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 160:
-#line 1472 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 161:
+#line 1481 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     // Allow but ignore attributes on function types; this permits auto-upgrade.
     // FIXME: remove in LLVM 3.0.
@@ -4353,8 +4365,8 @@
   ;}
     break;
 
-  case 161:
-#line 1481 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 162:
+#line 1490 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (1)].TypeVal))->getDescription());
@@ -4364,15 +4376,15 @@
   ;}
     break;
 
-  case 162:
-#line 1488 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 163:
+#line 1497 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.TypeVal) = new PATypeHolder(Type::VoidTy);
   ;}
     break;
 
-  case 163:
-#line 1493 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 164:
+#line 1502 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.TypeWithAttrsList) = new TypeWithAttrsList();
     (yyval.TypeWithAttrsList)->push_back((yyvsp[(1) - (1)].TypeWithAttrs));
@@ -4380,16 +4392,16 @@
   ;}
     break;
 
-  case 164:
-#line 1498 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 165:
+#line 1507 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     ((yyval.TypeWithAttrsList)=(yyvsp[(1) - (3)].TypeWithAttrsList))->push_back((yyvsp[(3) - (3)].TypeWithAttrs));
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 166:
-#line 1506 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 167:
+#line 1515 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.TypeWithAttrsList)=(yyvsp[(1) - (3)].TypeWithAttrsList);
     TypeWithAttrs TWA; TWA.Attrs = ParamAttr::None;
@@ -4399,8 +4411,8 @@
   ;}
     break;
 
-  case 167:
-#line 1513 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 168:
+#line 1522 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.TypeWithAttrsList) = new TypeWithAttrsList;
     TypeWithAttrs TWA; TWA.Attrs = ParamAttr::None;
@@ -4410,16 +4422,16 @@
   ;}
     break;
 
-  case 168:
-#line 1520 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 169:
+#line 1529 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.TypeWithAttrsList) = new TypeWithAttrsList();
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 169:
-#line 1528 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 170:
+#line 1537 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.TypeList) = new std::list<PATypeHolder>();
     (yyval.TypeList)->push_back(*(yyvsp[(1) - (1)].TypeVal)); 
@@ -4428,8 +4440,8 @@
   ;}
     break;
 
-  case 170:
-#line 1534 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 171:
+#line 1543 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     ((yyval.TypeList)=(yyvsp[(1) - (3)].TypeList))->push_back(*(yyvsp[(3) - (3)].TypeVal)); 
     delete (yyvsp[(3) - (3)].TypeVal);
@@ -4437,8 +4449,8 @@
   ;}
     break;
 
-  case 171:
-#line 1546 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 172:
+#line 1555 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { // Nonempty unsized arr
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (4)].TypeVal))->getDescription());
@@ -4469,8 +4481,8 @@
   ;}
     break;
 
-  case 172:
-#line 1574 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 173:
+#line 1583 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (3)].TypeVal))->getDescription());
@@ -4489,8 +4501,8 @@
   ;}
     break;
 
-  case 173:
-#line 1590 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 174:
+#line 1599 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (3)].TypeVal))->getDescription());
@@ -4520,8 +4532,8 @@
   ;}
     break;
 
-  case 174:
-#line 1617 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 175:
+#line 1626 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { // Nonempty unsized arr
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (4)].TypeVal))->getDescription());
@@ -4552,8 +4564,8 @@
   ;}
     break;
 
-  case 175:
-#line 1645 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 176:
+#line 1654 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     const StructType *STy = dyn_cast<StructType>((yyvsp[(1) - (4)].TypeVal)->get());
     if (STy == 0)
@@ -4582,8 +4594,8 @@
   ;}
     break;
 
-  case 176:
-#line 1671 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 177:
+#line 1680 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (3)].TypeVal))->getDescription());
@@ -4606,8 +4618,8 @@
   ;}
     break;
 
-  case 177:
-#line 1691 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 178:
+#line 1700 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     const StructType *STy = dyn_cast<StructType>((yyvsp[(1) - (6)].TypeVal)->get());
     if (STy == 0)
@@ -4636,8 +4648,8 @@
   ;}
     break;
 
-  case 178:
-#line 1717 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 179:
+#line 1726 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (5)].TypeVal))->getDescription());
@@ -4660,8 +4672,8 @@
   ;}
     break;
 
-  case 179:
-#line 1737 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 180:
+#line 1746 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (2)].TypeVal))->getDescription());
@@ -4676,8 +4688,8 @@
   ;}
     break;
 
-  case 180:
-#line 1749 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 181:
+#line 1758 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (2)].TypeVal))->getDescription());
@@ -4687,8 +4699,8 @@
   ;}
     break;
 
-  case 181:
-#line 1756 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 182:
+#line 1765 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (2)].TypeVal))->getDescription());
@@ -4757,8 +4769,8 @@
   ;}
     break;
 
-  case 182:
-#line 1822 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 183:
+#line 1831 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (2)].TypeVal))->getDescription());
@@ -4771,8 +4783,8 @@
   ;}
     break;
 
-  case 183:
-#line 1832 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 184:
+#line 1841 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (2)].TypeVal))->getDescription());
@@ -4785,8 +4797,8 @@
   ;}
     break;
 
-  case 184:
-#line 1842 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 185:
+#line 1851 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {      // integral constants
     if (!ConstantInt::isValueValidForType((yyvsp[(1) - (2)].PrimType), (yyvsp[(2) - (2)].SInt64Val)))
       GEN_ERROR("Constant value doesn't fit in type");
@@ -4795,8 +4807,8 @@
   ;}
     break;
 
-  case 185:
-#line 1848 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 186:
+#line 1857 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {      // arbitrary precision integer constants
     uint32_t BitWidth = cast<IntegerType>((yyvsp[(1) - (2)].PrimType))->getBitWidth();
     if ((yyvsp[(2) - (2)].APIntVal)->getBitWidth() > BitWidth) {
@@ -4809,8 +4821,8 @@
   ;}
     break;
 
-  case 186:
-#line 1858 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 187:
+#line 1867 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {      // integral constants
     if (!ConstantInt::isValueValidForType((yyvsp[(1) - (2)].PrimType), (yyvsp[(2) - (2)].UInt64Val)))
       GEN_ERROR("Constant value doesn't fit in type");
@@ -4819,8 +4831,8 @@
   ;}
     break;
 
-  case 187:
-#line 1864 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 188:
+#line 1873 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {      // arbitrary precision integer constants
     uint32_t BitWidth = cast<IntegerType>((yyvsp[(1) - (2)].PrimType))->getBitWidth();
     if ((yyvsp[(2) - (2)].APIntVal)->getBitWidth() > BitWidth) {
@@ -4833,8 +4845,8 @@
   ;}
     break;
 
-  case 188:
-#line 1874 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 189:
+#line 1883 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {                      // Boolean constants
     if (cast<IntegerType>((yyvsp[(1) - (2)].PrimType))->getBitWidth() != 1)
       GEN_ERROR("Constant true must have type i1");
@@ -4843,8 +4855,8 @@
   ;}
     break;
 
-  case 189:
-#line 1880 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 190:
+#line 1889 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {                     // Boolean constants
     if (cast<IntegerType>((yyvsp[(1) - (2)].PrimType))->getBitWidth() != 1)
       GEN_ERROR("Constant false must have type i1");
@@ -4853,8 +4865,8 @@
   ;}
     break;
 
-  case 190:
-#line 1886 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 191:
+#line 1895 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {                   // Floating point constants
     if (!ConstantFP::isValueValidForType((yyvsp[(1) - (2)].PrimType), *(yyvsp[(2) - (2)].FPVal)))
       GEN_ERROR("Floating point constant invalid for type");
@@ -4868,8 +4880,8 @@
   ;}
     break;
 
-  case 191:
-#line 1899 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 192:
+#line 1908 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(5) - (6)].TypeVal))->getDescription());
@@ -4884,8 +4896,8 @@
   ;}
     break;
 
-  case 192:
-#line 1911 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 193:
+#line 1920 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!isa<PointerType>((yyvsp[(3) - (5)].ConstVal)->getType()))
       GEN_ERROR("GetElementPtr requires a pointer operand");
@@ -4909,8 +4921,8 @@
   ;}
     break;
 
-  case 193:
-#line 1932 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 194:
+#line 1941 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if ((yyvsp[(3) - (8)].ConstVal)->getType() != Type::Int1Ty)
       GEN_ERROR("Select condition must be of boolean type");
@@ -4921,8 +4933,8 @@
   ;}
     break;
 
-  case 194:
-#line 1940 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 195:
+#line 1949 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if ((yyvsp[(3) - (6)].ConstVal)->getType() != (yyvsp[(5) - (6)].ConstVal)->getType())
       GEN_ERROR("Binary operator types must match");
@@ -4931,8 +4943,8 @@
   ;}
     break;
 
-  case 195:
-#line 1946 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 196:
+#line 1955 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if ((yyvsp[(3) - (6)].ConstVal)->getType() != (yyvsp[(5) - (6)].ConstVal)->getType())
       GEN_ERROR("Logical operator types must match");
@@ -4946,8 +4958,8 @@
   ;}
     break;
 
-  case 196:
-#line 1957 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 197:
+#line 1966 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if ((yyvsp[(4) - (7)].ConstVal)->getType() != (yyvsp[(6) - (7)].ConstVal)->getType())
       GEN_ERROR("icmp operand types must match");
@@ -4955,8 +4967,8 @@
   ;}
     break;
 
-  case 197:
-#line 1962 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 198:
+#line 1971 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if ((yyvsp[(4) - (7)].ConstVal)->getType() != (yyvsp[(6) - (7)].ConstVal)->getType())
       GEN_ERROR("fcmp operand types must match");
@@ -4964,8 +4976,8 @@
   ;}
     break;
 
-  case 198:
-#line 1967 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 199:
+#line 1976 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if ((yyvsp[(4) - (7)].ConstVal)->getType() != (yyvsp[(6) - (7)].ConstVal)->getType())
       GEN_ERROR("vicmp operand types must match");
@@ -4973,8 +4985,8 @@
   ;}
     break;
 
-  case 199:
-#line 1972 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 200:
+#line 1981 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if ((yyvsp[(4) - (7)].ConstVal)->getType() != (yyvsp[(6) - (7)].ConstVal)->getType())
       GEN_ERROR("vfcmp operand types must match");
@@ -4982,8 +4994,8 @@
   ;}
     break;
 
-  case 200:
-#line 1977 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 201:
+#line 1986 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!ExtractElementInst::isValidOperands((yyvsp[(3) - (6)].ConstVal), (yyvsp[(5) - (6)].ConstVal)))
       GEN_ERROR("Invalid extractelement operands");
@@ -4992,8 +5004,8 @@
   ;}
     break;
 
-  case 201:
-#line 1983 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 202:
+#line 1992 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!InsertElementInst::isValidOperands((yyvsp[(3) - (8)].ConstVal), (yyvsp[(5) - (8)].ConstVal), (yyvsp[(7) - (8)].ConstVal)))
       GEN_ERROR("Invalid insertelement operands");
@@ -5002,8 +5014,8 @@
   ;}
     break;
 
-  case 202:
-#line 1989 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 203:
+#line 1998 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!ShuffleVectorInst::isValidOperands((yyvsp[(3) - (8)].ConstVal), (yyvsp[(5) - (8)].ConstVal), (yyvsp[(7) - (8)].ConstVal)))
       GEN_ERROR("Invalid shufflevector operands");
@@ -5012,8 +5024,8 @@
   ;}
     break;
 
-  case 203:
-#line 1995 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 204:
+#line 2004 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!isa<StructType>((yyvsp[(3) - (5)].ConstVal)->getType()) && !isa<ArrayType>((yyvsp[(3) - (5)].ConstVal)->getType()))
       GEN_ERROR("ExtractValue requires an aggregate operand");
@@ -5024,8 +5036,8 @@
   ;}
     break;
 
-  case 204:
-#line 2003 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 205:
+#line 2012 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!isa<StructType>((yyvsp[(3) - (7)].ConstVal)->getType()) && !isa<ArrayType>((yyvsp[(3) - (7)].ConstVal)->getType()))
       GEN_ERROR("InsertValue requires an aggregate operand");
@@ -5036,16 +5048,16 @@
   ;}
     break;
 
-  case 205:
-#line 2014 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 206:
+#line 2023 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     ((yyval.ConstVector) = (yyvsp[(1) - (3)].ConstVector))->push_back((yyvsp[(3) - (3)].ConstVal));
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 206:
-#line 2018 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 207:
+#line 2027 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ConstVector) = new std::vector<Constant*>();
     (yyval.ConstVector)->push_back((yyvsp[(1) - (1)].ConstVal));
@@ -5053,28 +5065,28 @@
   ;}
     break;
 
-  case 207:
-#line 2026 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 208:
+#line 2035 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.BoolVal) = false; ;}
     break;
 
-  case 208:
-#line 2026 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 209:
+#line 2035 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.BoolVal) = true; ;}
     break;
 
-  case 209:
-#line 2029 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 210:
+#line 2038 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.BoolVal) = true; ;}
     break;
 
-  case 210:
-#line 2029 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 211:
+#line 2038 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.BoolVal) = false; ;}
     break;
 
-  case 211:
-#line 2032 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 212:
+#line 2041 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     const Type* VTy = (yyvsp[(1) - (2)].TypeVal)->get();
     Value *V = getVal(VTy, (yyvsp[(2) - (2)].ValIDVal));
@@ -5089,8 +5101,8 @@
    ;}
     break;
 
-  case 212:
-#line 2044 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 213:
+#line 2053 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     Constant *Val = (yyvsp[(3) - (6)].ConstVal);
     const Type *DestTy = (yyvsp[(5) - (6)].TypeVal)->get();
@@ -5105,8 +5117,8 @@
    ;}
     break;
 
-  case 213:
-#line 2065 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 214:
+#line 2074 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ModuleVal) = ParserResult = CurModule.CurrentModule;
     CurModule.ModuleDone();
@@ -5114,8 +5126,8 @@
   ;}
     break;
 
-  case 214:
-#line 2070 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 215:
+#line 2079 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ModuleVal) = ParserResult = CurModule.CurrentModule;
     CurModule.ModuleDone();
@@ -5123,40 +5135,40 @@
   ;}
     break;
 
-  case 217:
-#line 2083 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 218:
+#line 2092 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { CurFun.isDeclare = false; ;}
     break;
 
-  case 218:
-#line 2083 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 219:
+#line 2092 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     CurFun.FunctionDone();
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 219:
-#line 2087 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 220:
+#line 2096 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { CurFun.isDeclare = true; ;}
     break;
 
-  case 220:
-#line 2087 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 221:
+#line 2096 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 221:
-#line 2090 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 222:
+#line 2099 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 222:
-#line 2093 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 223:
+#line 2102 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (3)].TypeVal))->getDescription());
@@ -5183,8 +5195,8 @@
   ;}
     break;
 
-  case 223:
-#line 2117 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 224:
+#line 2126 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     ResolveTypeTo((yyvsp[(1) - (3)].StrVal), (yyvsp[(3) - (3)].PrimType));
 
@@ -5198,8 +5210,8 @@
   ;}
     break;
 
-  case 224:
-#line 2129 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 225:
+#line 2138 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { 
     /* "Externally Visible" Linkage */
     if ((yyvsp[(5) - (6)].ConstVal) == 0) 
@@ -5210,15 +5222,15 @@
   ;}
     break;
 
-  case 225:
-#line 2136 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 226:
+#line 2145 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     CurGV = 0;
   ;}
     break;
 
-  case 226:
-#line 2140 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 227:
+#line 2149 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if ((yyvsp[(6) - (7)].ConstVal) == 0) 
       GEN_ERROR("Global value initializer is not a constant");
@@ -5227,15 +5239,15 @@
   ;}
     break;
 
-  case 227:
-#line 2145 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 228:
+#line 2154 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     CurGV = 0;
   ;}
     break;
 
-  case 228:
-#line 2149 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 229:
+#line 2158 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(6) - (7)].TypeVal))->getDescription());
@@ -5245,16 +5257,16 @@
   ;}
     break;
 
-  case 229:
-#line 2155 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 230:
+#line 2164 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     CurGV = 0;
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 230:
-#line 2159 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 231:
+#line 2168 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     std::string Name;
     if ((yyvsp[(1) - (5)].StrVal)) {
@@ -5297,22 +5309,22 @@
   ;}
     break;
 
-  case 231:
-#line 2199 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 232:
+#line 2208 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { 
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 232:
-#line 2202 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 233:
+#line 2211 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 233:
-#line 2208 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 234:
+#line 2217 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
   const std::string &AsmSoFar = CurModule.CurrentModule->getModuleInlineAsm();
   if (AsmSoFar.empty())
@@ -5324,24 +5336,24 @@
 ;}
     break;
 
-  case 234:
-#line 2218 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 235:
+#line 2227 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     CurModule.CurrentModule->setTargetTriple(*(yyvsp[(3) - (3)].StrVal));
     delete (yyvsp[(3) - (3)].StrVal);
   ;}
     break;
 
-  case 235:
-#line 2222 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 236:
+#line 2231 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     CurModule.CurrentModule->setDataLayout(*(yyvsp[(3) - (3)].StrVal));
     delete (yyvsp[(3) - (3)].StrVal);
   ;}
     break;
 
-  case 237:
-#line 2229 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 238:
+#line 2238 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
           CurModule.CurrentModule->addLibrary(*(yyvsp[(3) - (3)].StrVal));
           delete (yyvsp[(3) - (3)].StrVal);
@@ -5349,8 +5361,8 @@
         ;}
     break;
 
-  case 238:
-#line 2234 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 239:
+#line 2243 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
           CurModule.CurrentModule->addLibrary(*(yyvsp[(1) - (1)].StrVal));
           delete (yyvsp[(1) - (1)].StrVal);
@@ -5358,15 +5370,15 @@
         ;}
     break;
 
-  case 239:
-#line 2239 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 240:
+#line 2248 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
           CHECK_FOR_ERROR
         ;}
     break;
 
-  case 240:
-#line 2248 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 241:
+#line 2257 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (5)].TypeVal))->getDescription());
@@ -5379,8 +5391,8 @@
   ;}
     break;
 
-  case 241:
-#line 2258 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 242:
+#line 2267 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (3)].TypeVal))->getDescription());
@@ -5393,16 +5405,16 @@
   ;}
     break;
 
-  case 242:
-#line 2269 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 243:
+#line 2278 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ArgList) = (yyvsp[(1) - (1)].ArgList);
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 243:
-#line 2273 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 244:
+#line 2282 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ArgList) = (yyvsp[(1) - (3)].ArgList);
     struct ArgListEntry E;
@@ -5414,8 +5426,8 @@
   ;}
     break;
 
-  case 244:
-#line 2282 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 245:
+#line 2291 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ArgList) = new ArgListType;
     struct ArgListEntry E;
@@ -5427,16 +5439,16 @@
   ;}
     break;
 
-  case 245:
-#line 2291 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 246:
+#line 2300 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ArgList) = 0;
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 246:
-#line 2297 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 247:
+#line 2306 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
   std::string FunctionName(*(yyvsp[(3) - (10)].StrVal));
   delete (yyvsp[(3) - (10)].StrVal);  // Free strdup'd memory!
@@ -5566,8 +5578,8 @@
 ;}
     break;
 
-  case 249:
-#line 2427 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 250:
+#line 2436 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
   (yyval.FunctionVal) = CurFun.CurrentFunction;
 
@@ -5578,16 +5590,16 @@
 ;}
     break;
 
-  case 252:
-#line 2438 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 253:
+#line 2447 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
   (yyval.FunctionVal) = (yyvsp[(1) - (2)].FunctionVal);
   CHECK_FOR_ERROR
 ;}
     break;
 
-  case 253:
-#line 2443 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 254:
+#line 2452 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     CurFun.CurrentFunction->setLinkage((yyvsp[(1) - (3)].Linkage));
     CurFun.CurrentFunction->setVisibility((yyvsp[(2) - (3)].Visibility));
@@ -5597,40 +5609,40 @@
   ;}
     break;
 
-  case 254:
-#line 2455 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 255:
+#line 2464 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.BoolVal) = false;
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 255:
-#line 2459 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 256:
+#line 2468 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.BoolVal) = true;
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 256:
-#line 2464 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 257:
+#line 2473 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {    // A reference to a direct constant
     (yyval.ValIDVal) = ValID::create((yyvsp[(1) - (1)].SInt64Val));
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 257:
-#line 2468 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 258:
+#line 2477 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ValIDVal) = ValID::create((yyvsp[(1) - (1)].UInt64Val));
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 258:
-#line 2472 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 259:
+#line 2481 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {      // arbitrary precision integer constants
     (yyval.ValIDVal) = ValID::create(*(yyvsp[(1) - (1)].APIntVal), true);
     delete (yyvsp[(1) - (1)].APIntVal);
@@ -5638,8 +5650,8 @@
   ;}
     break;
 
-  case 259:
-#line 2477 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 260:
+#line 2486 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {      // arbitrary precision integer constants
     (yyval.ValIDVal) = ValID::create(*(yyvsp[(1) - (1)].APIntVal), false);
     delete (yyvsp[(1) - (1)].APIntVal);
@@ -5647,56 +5659,56 @@
   ;}
     break;
 
-  case 260:
-#line 2482 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 261:
+#line 2491 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {                     // Perhaps it's an FP constant?
     (yyval.ValIDVal) = ValID::create((yyvsp[(1) - (1)].FPVal));
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 261:
-#line 2486 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 262:
+#line 2495 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ValIDVal) = ValID::create(ConstantInt::getTrue());
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 262:
-#line 2490 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 263:
+#line 2499 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ValIDVal) = ValID::create(ConstantInt::getFalse());
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 263:
-#line 2494 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 264:
+#line 2503 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ValIDVal) = ValID::createNull();
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 264:
-#line 2498 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 265:
+#line 2507 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ValIDVal) = ValID::createUndef();
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 265:
-#line 2502 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 266:
+#line 2511 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {     // A vector zero constant.
     (yyval.ValIDVal) = ValID::createZeroInit();
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 266:
-#line 2506 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 267:
+#line 2515 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { // Nonempty unsized packed vector
     const Type *ETy = (*(yyvsp[(2) - (3)].ConstVector))[0]->getType();
     unsigned NumElements = (yyvsp[(2) - (3)].ConstVector)->size(); 
@@ -5721,8 +5733,8 @@
   ;}
     break;
 
-  case 267:
-#line 2528 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 268:
+#line 2537 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { // Nonempty unsized arr
     const Type *ETy = (*(yyvsp[(2) - (3)].ConstVector))[0]->getType();
     uint64_t NumElements = (yyvsp[(2) - (3)].ConstVector)->size(); 
@@ -5747,8 +5759,8 @@
   ;}
     break;
 
-  case 268:
-#line 2550 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 269:
+#line 2559 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     // Use undef instead of an array because it's inconvenient to determine
     // the element type at this point, there being no elements to examine.
@@ -5757,8 +5769,8 @@
   ;}
     break;
 
-  case 269:
-#line 2556 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 270:
+#line 2565 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     uint64_t NumElements = (yyvsp[(2) - (2)].StrVal)->length();
     const Type *ETy = Type::Int8Ty;
@@ -5774,8 +5786,8 @@
   ;}
     break;
 
-  case 270:
-#line 2569 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 271:
+#line 2578 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     std::vector<const Type*> Elements((yyvsp[(2) - (3)].ConstVector)->size());
     for (unsigned i = 0, e = (yyvsp[(2) - (3)].ConstVector)->size(); i != e; ++i)
@@ -5790,8 +5802,8 @@
   ;}
     break;
 
-  case 271:
-#line 2581 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 272:
+#line 2590 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     const StructType *STy = StructType::get(std::vector<const Type*>());
     (yyval.ValIDVal) = ValID::create(ConstantStruct::get(STy, std::vector<Constant*>()));
@@ -5799,8 +5811,8 @@
   ;}
     break;
 
-  case 272:
-#line 2586 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 273:
+#line 2595 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     std::vector<const Type*> Elements((yyvsp[(3) - (5)].ConstVector)->size());
     for (unsigned i = 0, e = (yyvsp[(3) - (5)].ConstVector)->size(); i != e; ++i)
@@ -5815,8 +5827,8 @@
   ;}
     break;
 
-  case 273:
-#line 2598 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 274:
+#line 2607 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     const StructType *STy = StructType::get(std::vector<const Type*>(),
                                             /*isPacked=*/true);
@@ -5825,16 +5837,16 @@
   ;}
     break;
 
-  case 274:
-#line 2604 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 275:
+#line 2613 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ValIDVal) = ValID::create((yyvsp[(1) - (1)].ConstVal));
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 275:
-#line 2608 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 276:
+#line 2617 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ValIDVal) = ValID::createInlineAsm(*(yyvsp[(3) - (5)].StrVal), *(yyvsp[(5) - (5)].StrVal), (yyvsp[(2) - (5)].BoolVal));
     delete (yyvsp[(3) - (5)].StrVal);
@@ -5843,24 +5855,24 @@
   ;}
     break;
 
-  case 276:
-#line 2618 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 277:
+#line 2627 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {  // Is it an integer reference...?
     (yyval.ValIDVal) = ValID::createLocalID((yyvsp[(1) - (1)].UIntVal));
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 277:
-#line 2622 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 278:
+#line 2631 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ValIDVal) = ValID::createGlobalID((yyvsp[(1) - (1)].UIntVal));
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 278:
-#line 2626 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 279:
+#line 2635 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {                   // Is it a named reference...?
     (yyval.ValIDVal) = ValID::createLocalName(*(yyvsp[(1) - (1)].StrVal));
     delete (yyvsp[(1) - (1)].StrVal);
@@ -5868,8 +5880,8 @@
   ;}
     break;
 
-  case 279:
-#line 2631 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 280:
+#line 2640 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {                   // Is it a named reference...?
     (yyval.ValIDVal) = ValID::createGlobalName(*(yyvsp[(1) - (1)].StrVal));
     delete (yyvsp[(1) - (1)].StrVal);
@@ -5877,8 +5889,8 @@
   ;}
     break;
 
-  case 282:
-#line 2644 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 283:
+#line 2653 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (2)].TypeVal))->getDescription());
@@ -5888,8 +5900,8 @@
   ;}
     break;
 
-  case 283:
-#line 2653 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 284:
+#line 2662 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ValueList) = new std::vector<Value *>();
     (yyval.ValueList)->push_back((yyvsp[(1) - (1)].ValueVal)); 
@@ -5897,32 +5909,32 @@
   ;}
     break;
 
-  case 284:
-#line 2658 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 285:
+#line 2667 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     ((yyval.ValueList)=(yyvsp[(1) - (3)].ValueList))->push_back((yyvsp[(3) - (3)].ValueVal)); 
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 285:
-#line 2663 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 286:
+#line 2672 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.FunctionVal) = (yyvsp[(1) - (2)].FunctionVal);
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 286:
-#line 2667 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 287:
+#line 2676 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { // Do not allow functions with 0 basic blocks   
     (yyval.FunctionVal) = (yyvsp[(1) - (2)].FunctionVal);
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 287:
-#line 2676 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 288:
+#line 2685 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     setValueName((yyvsp[(3) - (3)].TermInstVal), (yyvsp[(2) - (3)].StrVal));
     CHECK_FOR_ERROR
@@ -5933,8 +5945,23 @@
   ;}
     break;
 
-  case 288:
-#line 2685 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 289:
+#line 2694 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    {
+  CHECK_FOR_ERROR
+  int ValNum = InsertValue((yyvsp[(3) - (3)].TermInstVal));
+  if (ValNum != (int)(yyvsp[(2) - (3)].UIntVal))
+    GEN_ERROR("Result value number %" + utostr((yyvsp[(2) - (3)].UIntVal)) +
+              " is incorrect, expected %" + utostr((unsigned)ValNum));
+  
+  (yyvsp[(1) - (3)].BasicBlockVal)->getInstList().push_back((yyvsp[(3) - (3)].TermInstVal));
+  (yyval.BasicBlockVal) = (yyvsp[(1) - (3)].BasicBlockVal);
+  CHECK_FOR_ERROR
+;}
+    break;
+
+  case 290:
+#line 2707 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (CastInst *CI1 = dyn_cast<CastInst>((yyvsp[(2) - (2)].InstVal)))
       if (CastInst *CI2 = dyn_cast<CastInst>(CI1->getOperand(0)))
@@ -5946,16 +5973,16 @@
   ;}
     break;
 
-  case 289:
-#line 2694 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 291:
+#line 2716 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {          // Empty space between instruction lists
     (yyval.BasicBlockVal) = defineBBVal(ValID::createLocalID(CurFun.NextValNum));
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 290:
-#line 2698 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 292:
+#line 2720 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {             // Labelled (named) basic block
     (yyval.BasicBlockVal) = defineBBVal(ValID::createLocalName(*(yyvsp[(1) - (1)].StrVal)));
     delete (yyvsp[(1) - (1)].StrVal);
@@ -5964,8 +5991,8 @@
   ;}
     break;
 
-  case 291:
-#line 2706 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 293:
+#line 2728 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { // Return with a result...
     ValueList &VL = *(yyvsp[(2) - (2)].ValueList);
     assert(!VL.empty() && "Invalid ret operands!");
@@ -5988,16 +6015,16 @@
   ;}
     break;
 
-  case 292:
-#line 2726 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 294:
+#line 2748 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {                                    // Return with no result...
     (yyval.TermInstVal) = ReturnInst::Create();
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 293:
-#line 2730 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 295:
+#line 2752 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {                           // Unconditional Branch...
     BasicBlock* tmpBB = getBBVal((yyvsp[(3) - (3)].ValIDVal));
     CHECK_FOR_ERROR
@@ -6005,8 +6032,8 @@
   ;}
     break;
 
-  case 294:
-#line 2735 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 296:
+#line 2757 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {  
     if (cast<IntegerType>((yyvsp[(2) - (9)].PrimType))->getBitWidth() != 1)
       GEN_ERROR("Branch condition must have type i1");
@@ -6020,8 +6047,8 @@
   ;}
     break;
 
-  case 295:
-#line 2746 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 297:
+#line 2768 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     Value* tmpVal = getVal((yyvsp[(2) - (9)].PrimType), (yyvsp[(3) - (9)].ValIDVal));
     CHECK_FOR_ERROR
@@ -6043,8 +6070,8 @@
   ;}
     break;
 
-  case 296:
-#line 2765 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 298:
+#line 2787 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     Value* tmpVal = getVal((yyvsp[(2) - (8)].PrimType), (yyvsp[(3) - (8)].ValIDVal));
     CHECK_FOR_ERROR
@@ -6056,8 +6083,8 @@
   ;}
     break;
 
-  case 297:
-#line 2775 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 299:
+#line 2797 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
 
     // Handle the short syntax
@@ -6145,24 +6172,24 @@
   ;}
     break;
 
-  case 298:
-#line 2860 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 300:
+#line 2882 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.TermInstVal) = new UnwindInst();
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 299:
-#line 2864 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 301:
+#line 2886 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.TermInstVal) = new UnreachableInst();
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 300:
-#line 2871 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 302:
+#line 2893 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.JumpTable) = (yyvsp[(1) - (6)].JumpTable);
     Constant *V = cast<Constant>(getExistingVal((yyvsp[(2) - (6)].PrimType), (yyvsp[(3) - (6)].ValIDVal)));
@@ -6176,8 +6203,8 @@
   ;}
     break;
 
-  case 301:
-#line 2882 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 303:
+#line 2904 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.JumpTable) = new std::vector<std::pair<Constant*, BasicBlock*> >();
     Constant *V = cast<Constant>(getExistingVal((yyvsp[(1) - (5)].PrimType), (yyvsp[(2) - (5)].ValIDVal)));
@@ -6192,8 +6219,8 @@
   ;}
     break;
 
-  case 302:
-#line 2895 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 304:
+#line 2917 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     // Is this definition named?? if so, assign the name...
     setValueName((yyvsp[(2) - (2)].InstVal), (yyvsp[(1) - (2)].StrVal));
@@ -6204,8 +6231,23 @@
   ;}
     break;
 
-  case 303:
-#line 2905 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 305:
+#line 2926 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
+    {
+    CHECK_FOR_ERROR
+    int ValNum = InsertValue((yyvsp[(2) - (2)].InstVal));
+  
+    if (ValNum != (int)(yyvsp[(1) - (2)].UIntVal))
+      GEN_ERROR("Result value number %" + utostr((yyvsp[(1) - (2)].UIntVal)) +
+                " is incorrect, expected %" + utostr((unsigned)ValNum));
+
+    (yyval.InstVal) = (yyvsp[(2) - (2)].InstVal);
+    CHECK_FOR_ERROR
+  ;}
+    break;
+
+  case 306:
+#line 2939 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {    // Used for PHI nodes
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (6)].TypeVal))->getDescription());
@@ -6219,8 +6261,8 @@
   ;}
     break;
 
-  case 304:
-#line 2916 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 307:
+#line 2950 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.PHIList) = (yyvsp[(1) - (7)].PHIList);
     Value* tmpVal = getVal((yyvsp[(1) - (7)].PHIList)->front().first->getType(), (yyvsp[(4) - (7)].ValIDVal));
@@ -6231,8 +6273,8 @@
   ;}
     break;
 
-  case 305:
-#line 2926 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 308:
+#line 2960 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     // FIXME: Remove trailing OptParamAttrs in LLVM 3.0, it was a mistake in 2.0
     if (!UpRefs.empty())
@@ -6246,8 +6288,8 @@
   ;}
     break;
 
-  case 306:
-#line 2937 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 309:
+#line 2971 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     // FIXME: Remove trailing OptParamAttrs in LLVM 3.0, it was a mistake in 2.0
     // Labels are only valid in ASMs
@@ -6258,8 +6300,8 @@
   ;}
     break;
 
-  case 307:
-#line 2945 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 310:
+#line 2979 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     // FIXME: Remove trailing OptParamAttrs in LLVM 3.0, it was a mistake in 2.0
     if (!UpRefs.empty())
@@ -6272,8 +6314,8 @@
   ;}
     break;
 
-  case 308:
-#line 2955 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 311:
+#line 2989 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     // FIXME: Remove trailing OptParamAttrs in LLVM 3.0, it was a mistake in 2.0
     (yyval.ParamList) = (yyvsp[(1) - (6)].ParamList);
@@ -6283,18 +6325,18 @@
   ;}
     break;
 
-  case 309:
-#line 2962 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 312:
+#line 2996 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.ParamList) = new ParamList(); ;}
     break;
 
-  case 310:
-#line 2965 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 313:
+#line 2999 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     { (yyval.ValueList) = new std::vector<Value*>(); ;}
     break;
 
-  case 311:
-#line 2966 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 314:
+#line 3000 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ValueList) = (yyvsp[(1) - (3)].ValueList);
     (yyval.ValueList)->push_back((yyvsp[(3) - (3)].ValueVal));
@@ -6302,8 +6344,8 @@
   ;}
     break;
 
-  case 312:
-#line 2974 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 315:
+#line 3008 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ConstantList) = new std::vector<unsigned>();
     if ((unsigned)(yyvsp[(2) - (2)].UInt64Val) != (yyvsp[(2) - (2)].UInt64Val))
@@ -6312,8 +6354,8 @@
   ;}
     break;
 
-  case 313:
-#line 2980 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 316:
+#line 3014 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.ConstantList) = (yyvsp[(1) - (3)].ConstantList);
     if ((unsigned)(yyvsp[(3) - (3)].UInt64Val) != (yyvsp[(3) - (3)].UInt64Val))
@@ -6323,24 +6365,24 @@
   ;}
     break;
 
-  case 314:
-#line 2989 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 317:
+#line 3023 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.BoolVal) = true;
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 315:
-#line 2993 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 318:
+#line 3027 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.BoolVal) = false;
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 316:
-#line 2998 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 319:
+#line 3032 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (5)].TypeVal))->getDescription());
@@ -6359,8 +6401,8 @@
   ;}
     break;
 
-  case 317:
-#line 3014 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 320:
+#line 3048 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (5)].TypeVal))->getDescription());
@@ -6380,8 +6422,8 @@
   ;}
     break;
 
-  case 318:
-#line 3031 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 321:
+#line 3065 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (6)].TypeVal))->getDescription());
@@ -6398,8 +6440,8 @@
   ;}
     break;
 
-  case 319:
-#line 3045 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 322:
+#line 3079 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (6)].TypeVal))->getDescription());
@@ -6416,8 +6458,8 @@
   ;}
     break;
 
-  case 320:
-#line 3059 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 323:
+#line 3093 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (6)].TypeVal))->getDescription());
@@ -6434,8 +6476,8 @@
   ;}
     break;
 
-  case 321:
-#line 3073 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 324:
+#line 3107 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (6)].TypeVal))->getDescription());
@@ -6452,8 +6494,8 @@
   ;}
     break;
 
-  case 322:
-#line 3087 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 325:
+#line 3121 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(4) - (4)].TypeVal))->getDescription());
@@ -6468,8 +6510,8 @@
   ;}
     break;
 
-  case 323:
-#line 3099 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 326:
+#line 3133 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if ((yyvsp[(2) - (6)].ValueVal)->getType() != Type::Int1Ty)
       GEN_ERROR("select condition must be boolean");
@@ -6480,8 +6522,8 @@
   ;}
     break;
 
-  case 324:
-#line 3107 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 327:
+#line 3141 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(4) - (4)].TypeVal))->getDescription());
@@ -6491,8 +6533,8 @@
   ;}
     break;
 
-  case 325:
-#line 3114 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 328:
+#line 3148 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!ExtractElementInst::isValidOperands((yyvsp[(2) - (4)].ValueVal), (yyvsp[(4) - (4)].ValueVal)))
       GEN_ERROR("Invalid extractelement operands");
@@ -6501,8 +6543,8 @@
   ;}
     break;
 
-  case 326:
-#line 3120 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 329:
+#line 3154 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!InsertElementInst::isValidOperands((yyvsp[(2) - (6)].ValueVal), (yyvsp[(4) - (6)].ValueVal), (yyvsp[(6) - (6)].ValueVal)))
       GEN_ERROR("Invalid insertelement operands");
@@ -6511,8 +6553,8 @@
   ;}
     break;
 
-  case 327:
-#line 3126 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 330:
+#line 3160 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!ShuffleVectorInst::isValidOperands((yyvsp[(2) - (6)].ValueVal), (yyvsp[(4) - (6)].ValueVal), (yyvsp[(6) - (6)].ValueVal)))
       GEN_ERROR("Invalid shufflevector operands");
@@ -6521,8 +6563,8 @@
   ;}
     break;
 
-  case 328:
-#line 3132 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 331:
+#line 3166 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     const Type *Ty = (yyvsp[(2) - (2)].PHIList)->front().first->getType();
     if (!Ty->isFirstClassType())
@@ -6540,8 +6582,8 @@
   ;}
     break;
 
-  case 329:
-#line 3148 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 332:
+#line 3182 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
 
     // Handle the short syntax
@@ -6633,32 +6675,32 @@
   ;}
     break;
 
-  case 330:
-#line 3237 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 333:
+#line 3271 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.InstVal) = (yyvsp[(1) - (1)].InstVal);
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 331:
-#line 3242 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 334:
+#line 3276 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.BoolVal) = true;
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 332:
-#line 3246 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 335:
+#line 3280 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     (yyval.BoolVal) = false;
     CHECK_FOR_ERROR
   ;}
     break;
 
-  case 333:
-#line 3253 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 336:
+#line 3287 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (3)].TypeVal))->getDescription());
@@ -6668,8 +6710,8 @@
   ;}
     break;
 
-  case 334:
-#line 3260 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 337:
+#line 3294 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (6)].TypeVal))->getDescription());
@@ -6682,8 +6724,8 @@
   ;}
     break;
 
-  case 335:
-#line 3270 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 338:
+#line 3304 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (3)].TypeVal))->getDescription());
@@ -6693,8 +6735,8 @@
   ;}
     break;
 
-  case 336:
-#line 3277 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 339:
+#line 3311 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (6)].TypeVal))->getDescription());
@@ -6707,8 +6749,8 @@
   ;}
     break;
 
-  case 337:
-#line 3287 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 340:
+#line 3321 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!isa<PointerType>((yyvsp[(2) - (2)].ValueVal)->getType()))
       GEN_ERROR("Trying to free nonpointer type " + 
@@ -6718,8 +6760,8 @@
   ;}
     break;
 
-  case 338:
-#line 3295 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 341:
+#line 3329 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (5)].TypeVal))->getDescription());
@@ -6736,8 +6778,8 @@
   ;}
     break;
 
-  case 339:
-#line 3309 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 342:
+#line 3343 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(5) - (7)].TypeVal))->getDescription());
@@ -6757,8 +6799,8 @@
   ;}
     break;
 
-  case 340:
-#line 3326 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 343:
+#line 3360 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (5)].TypeVal))->getDescription());
@@ -6775,8 +6817,8 @@
   ;}
     break;
 
-  case 341:
-#line 3340 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 344:
+#line 3374 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (4)].TypeVal))->getDescription());
@@ -6794,8 +6836,8 @@
   ;}
     break;
 
-  case 342:
-#line 3355 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 345:
+#line 3389 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (4)].TypeVal))->getDescription());
@@ -6813,8 +6855,8 @@
   ;}
     break;
 
-  case 343:
-#line 3370 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+  case 346:
+#line 3404 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
     {
     if (!UpRefs.empty())
       GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (7)].TypeVal))->getDescription());
@@ -6836,7 +6878,7 @@
 
 
 /* Line 1267 of yacc.c.  */
-#line 6840 "llvmAsmParser.tab.c"
+#line 6882 "llvmAsmParser.tab.c"
       default: break;
     }
   YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc);
@@ -7050,7 +7092,7 @@
 }
 
 
-#line 3389 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 3423 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
 
 
 // common code from the two 'RunVMAsmParser' functions

Modified: llvm/trunk/lib/AsmParser/llvmAsmParser.h.cvs
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/llvmAsmParser.h.cvs?rev=55542&r1=55541&r2=55542&view=diff

==============================================================================
--- llvm/trunk/lib/AsmParser/llvmAsmParser.h.cvs (original)
+++ llvm/trunk/lib/AsmParser/llvmAsmParser.h.cvs Fri Aug 29 12:20:18 2008
@@ -356,7 +356,7 @@
 
 #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
 typedef union YYSTYPE
-#line 967 "/Users/malichus/Source/LLVM/src/svn/llvm/lib/AsmParser/llvmAsmParser.y"
+#line 970 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y"
 {
   llvm::Module                           *ModuleVal;
   llvm::Function                         *FunctionVal;

Modified: llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs?rev=55542&r1=55541&r2=55542&view=diff

==============================================================================
--- llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs (original)
+++ llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs Fri Aug 29 12:20:18 2008
@@ -249,10 +249,12 @@
 //               Code to handle definitions of all the types
 //===----------------------------------------------------------------------===//
 
-static void InsertValue(Value *V, ValueList &ValueTab = CurFun.Values) {
+/// InsertValue - Insert a value into the value table.  If it is named, this
+/// returns -1, otherwise it returns the slot number for the value.
+static int InsertValue(Value *V, ValueList &ValueTab = CurFun.Values) {
   // Things that have names or are void typed don't get slot numbers
   if (V->hasName() || (V->getType() == Type::VoidTy))
-    return;
+    return -1;
 
   // In the case of function values, we have to allow for the forward reference
   // of basic blocks, which are included in the numbering. Consequently, we keep
@@ -262,10 +264,11 @@
     if (ValueTab.size() <= CurFun.NextValNum)
       ValueTab.resize(CurFun.NextValNum+1);
     ValueTab[CurFun.NextValNum++] = V;
-    return;
+    return CurFun.NextValNum-1;
   } 
   // For all other lists, its okay to just tack it on the back of the vector.
   ValueTab.push_back(V);
+  return ValueTab.size()-1;
 }
 
 static const Type *getTypeVal(const ValID &D, bool DoNotImprovise = false) {
@@ -1084,7 +1087,7 @@
 %token CC_TOK CCC_TOK FASTCC_TOK COLDCC_TOK X86_STDCALLCC_TOK X86_FASTCALLCC_TOK
 %token X86_SSECALLCC_TOK
 %token DATALAYOUT
-%type <UIntVal> OptCallingConv
+%type <UIntVal> OptCallingConv LocalNumber
 %type <ParamAttrs> OptParamAttrs ParamAttr 
 %type <ParamAttrs> OptFuncAttrs  FuncAttr
 
@@ -1177,6 +1180,12 @@
     CHECK_FOR_ERROR
   };
 
+LocalNumber : LOCALVAL_ID '=' {
+  $$ = $1;
+  CHECK_FOR_ERROR
+};
+
+
 GlobalName : GLOBALVAR | ATSTRINGCONSTANT ;
 
 OptGlobalAssign : GlobalAssign
@@ -2673,7 +2682,7 @@
 // Basic blocks are terminated by branching instructions: 
 // br, br/cc, switch, ret
 //
-BasicBlock : InstructionList OptLocalAssign BBTerminatorInst  {
+BasicBlock : InstructionList OptLocalAssign BBTerminatorInst {
     setValueName($3, $2);
     CHECK_FOR_ERROR
     InsertValue($3);
@@ -2682,6 +2691,19 @@
     CHECK_FOR_ERROR
   };
 
+BasicBlock : InstructionList LocalNumber BBTerminatorInst {
+  CHECK_FOR_ERROR
+  int ValNum = InsertValue($3);
+  if (ValNum != (int)$2)
+    GEN_ERROR("Result value number %" + utostr($2) +
+              " is incorrect, expected %" + utostr((unsigned)ValNum));
+  
+  $1->getInstList().push_back($3);
+  $$ = $1;
+  CHECK_FOR_ERROR
+};
+
+
 InstructionList : InstructionList Inst {
     if (CastInst *CI1 = dyn_cast<CastInst>($2))
       if (CastInst *CI2 = dyn_cast<CastInst>(CI1->getOperand(0)))
@@ -2901,6 +2923,18 @@
     CHECK_FOR_ERROR
   };
 
+Inst : LocalNumber InstVal {
+    CHECK_FOR_ERROR
+    int ValNum = InsertValue($2);
+  
+    if (ValNum != (int)$1)
+      GEN_ERROR("Result value number %" + utostr($1) +
+                " is incorrect, expected %" + utostr((unsigned)ValNum));
+
+    $$ = $2;
+    CHECK_FOR_ERROR
+  };
+
 
 PHIList : Types '[' ValueRef ',' ValueRef ']' {    // Used for PHI nodes
     if (!UpRefs.empty())




From resistor at mac.com  Fri Aug 29 12:45:57 2008
From: resistor at mac.com (Owen Anderson)
Date: Fri, 29 Aug 2008 17:45:57 -0000
Subject: [llvm-commits] [llvm] r55545 - in /llvm/trunk:
 lib/Target/X86/X86FastISel.cpp utils/TableGen/FastISelEmitter.cpp
Message-ID: <200808291745.m7THjvFw029223@zion.cs.uiuc.edu>

Author: resistor
Date: Fri Aug 29 12:45:56 2008
New Revision: 55545

URL: http://llvm.org/viewvc/llvm-project?rev=55545&view=rev
Log:
Add initial support for fast isel of instructions that have inputs pinned to physical registers.

Modified:
    llvm/trunk/lib/Target/X86/X86FastISel.cpp
    llvm/trunk/utils/TableGen/FastISelEmitter.cpp

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=55545&r1=55544&r2=55545&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Fri Aug 29 12:45:56 2008
@@ -18,6 +18,7 @@
 #include "X86ISelLowering.h"
 #include "X86FastISel.h"
 #include "X86TargetMachine.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "X86GenFastISel.inc"
 
 namespace llvm {

Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=55545&r1=55544&r2=55545&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Fri Aug 29 12:45:56 2008
@@ -44,6 +44,16 @@
 
 namespace {
 
+/// InstructionMemo - This class holds additional information about an
+/// instruction needed to emit code for it.
+///
+struct InstructionMemo {
+  std::string Name;
+  const CodeGenRegisterClass *RC;
+  unsigned char SubRegNo;
+  std::vector<std::string>* PhysRegs;
+};
+
 /// OperandsSignature - This class holds a description of a list of operand
 /// types. It has utility methods for emitting text based on the operands.
 ///
@@ -103,15 +113,17 @@
       if (!OpDI)
         return false;
       Record *OpLeafRec = OpDI->getDef();
-      // TODO: handle instructions which have physreg operands.
-      if (OpLeafRec->isSubClassOf("Register"))
-        return false;
       // For now, the only other thing we accept is register operands.
-      if (!OpLeafRec->isSubClassOf("RegisterClass"))
+      
+      const CodeGenRegisterClass *RC = 0;
+      if (OpLeafRec->isSubClassOf("RegisterClass"))
+        RC = &Target.getRegisterClass(OpLeafRec);
+      else if (OpLeafRec->isSubClassOf("Register"))
+        RC = Target.getRegisterClassForRegister(OpLeafRec);
+      else
         return false;
       // For now, require the register operands' register classes to all
       // be the same.
-      const CodeGenRegisterClass *RC = &Target.getRegisterClass(OpLeafRec);
       if (!RC)
         return false;
       // For now, all the operands must have the same register class.
@@ -142,6 +154,27 @@
     }
   }
 
+  void PrintArguments(std::ostream &OS,
+                      const std::vector<std::string>& PR) const {
+    assert(PR.size() == Operands.size());
+    for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
+      if (PR[i] != "") {
+        OS << PR[i];
+      } else if (Operands[i] == "r") {
+        OS << "Op" << i;
+      } else if (Operands[i] == "i") {
+        OS << "imm" << i;
+      } else if (Operands[i] == "f") {
+        OS << "f" << i;
+      } else {
+        assert("Unknown operand kind!");
+        abort();
+      }
+      if (i + 1 != e)
+        OS << ", ";
+    }
+  }
+
   void PrintArguments(std::ostream &OS) const {
     for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
       if (Operands[i] == "r") {
@@ -159,6 +192,7 @@
     }
   }
 
+
   void PrintManglingSuffix(std::ostream &OS) const {
     for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
       OS << Operands[i];
@@ -166,15 +200,6 @@
   }
 };
 
-/// InstructionMemo - This class holds additional information about an
-/// instruction needed to emit code for it.
-///
-struct InstructionMemo {
-  std::string Name;
-  const CodeGenRegisterClass *RC;
-  unsigned char SubRegNo;
-};
-
 class FastISelMap {
   typedef std::map<std::string, InstructionMemo> PredMap;
   typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
@@ -275,6 +300,41 @@
     OperandsSignature Operands;
     if (!Operands.initialize(InstPatNode, Target, VT))
       continue;
+    
+    std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
+    if (!InstPatNode->isLeaf() &&
+        (InstPatNode->getOperator()->getName() == "imm" ||
+         InstPatNode->getOperator()->getName() == "fpimmm"))
+      PhysRegInputs->push_back("");
+    else if (!InstPatNode->isLeaf()) {
+      for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
+        TreePatternNode *Op = InstPatNode->getChild(i);
+        if (!Op->isLeaf()) {
+          PhysRegInputs->push_back("");
+          continue;
+        }
+        
+        DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
+        Record *OpLeafRec = OpDI->getDef();
+        std::string PhysReg;
+        if (OpLeafRec->isSubClassOf("Register")) {
+          PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \
+                     "Namespace")->getValue())->getValue();
+          PhysReg += "::";
+          
+          std::vector<CodeGenRegister> Regs = Target.getRegisters();
+          for (unsigned i = 0; i < Regs.size(); ++i) {
+            if (Regs[i].TheDef == OpLeafRec) {
+              PhysReg += Regs[i].getName();
+              break;
+            }
+          }
+        }
+      
+        PhysRegInputs->push_back(PhysReg);
+      }
+    } else
+      PhysRegInputs->push_back("");
 
     // Get the predicate that guards this pattern.
     std::string PredicateCheck = Pattern.getPredicateCheck();
@@ -283,7 +343,8 @@
     InstructionMemo Memo = {
       Pattern.getDstPattern()->getOperator()->getName(),
       DstRC,
-      SubRegNo
+      SubRegNo,
+      PhysRegInputs
     };
     assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) &&
            "Duplicate pattern!");
@@ -422,10 +483,20 @@
                        "Multiple instructions match, at least one has "
                        "a predicate and at least one doesn't!");
               } else {
-                OS << "  if (" + PredicateCheck + ")\n";
+                OS << "  if (" + PredicateCheck + ") {\n";
                 OS << "  ";
                 HasPred = true;
               }
+              
+              for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
+                if ((*Memo.PhysRegs)[i] != "")
+                  OS << "  TII.copyRegToReg(*MBB, MBB->end(), "
+                     << (*Memo.PhysRegs)[i] << ", Op" << i << ", "
+                     << "TM.getRegisterInfo()->getPhysicalRegisterRegClass("
+                     << (*Memo.PhysRegs)[i] << "), "
+                     << "MRI.getRegClass(Op" << i << "));\n";
+              }
+              
               OS << "  return FastEmitInst_";
               if (Memo.SubRegNo == (unsigned char)~0) {
                 Operands.PrintManglingSuffix(OS);
@@ -433,13 +504,17 @@
                 OS << InstNS << Memo.RC->getName() << "RegisterClass";
                 if (!Operands.empty())
                   OS << ", ";
-                Operands.PrintArguments(OS);
+                Operands.PrintArguments(OS, *Memo.PhysRegs);
                 OS << ");\n";
               } else {
                 OS << "extractsubreg(Op0, ";
                 OS << (unsigned)Memo.SubRegNo;
                 OS << ");\n";
               }
+              
+              if (HasPred)
+                OS << "}\n";
+              
             }
             // Return 0 if none of the predicates were satisfied.
             if (HasPred)
@@ -500,10 +575,20 @@
                      "Multiple instructions match, at least one has "
                      "a predicate and at least one doesn't!");
             } else {
-              OS << "  if (" + PredicateCheck + ")\n";
+              OS << "  if (" + PredicateCheck + ") {\n";
               OS << "  ";
               HasPred = true;
             }
+            
+             for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
+                if ((*Memo.PhysRegs)[i] != "")
+                  OS << "  TII.copyRegToReg(*MBB, MBB->end(), "
+                     << (*Memo.PhysRegs)[i] << ", Op" << i << ", "
+                     << "TM.getRegisterInfo()->getPhysicalRegisterRegClass("
+                     << (*Memo.PhysRegs)[i] << "), "
+                     << "MRI.getRegClass(Op" << i << "));\n";
+              }
+            
             OS << "  return FastEmitInst_";
             
             if (Memo.SubRegNo == (unsigned char)~0) {
@@ -512,13 +597,16 @@
               OS << InstNS << Memo.RC->getName() << "RegisterClass";
               if (!Operands.empty())
                 OS << ", ";
-              Operands.PrintArguments(OS);
+              Operands.PrintArguments(OS, *Memo.PhysRegs);
               OS << ");\n";
             } else {
               OS << "extractsubreg(Op0, ";
               OS << (unsigned)Memo.SubRegNo;
               OS << ");\n";
             }
+            
+             if (HasPred)
+               OS << "  }\n";
           }
           
           // Return 0 if none of the predicates were satisfied.




From dalej at apple.com  Fri Aug 29 13:29:48 2008
From: dalej at apple.com (Dale Johannesen)
Date: Fri, 29 Aug 2008 18:29:48 -0000
Subject: [llvm-commits] [llvm] r55546 -
	/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
Message-ID: <200808291829.m7TITmYS030563@zion.cs.uiuc.edu>

Author: johannes
Date: Fri Aug 29 13:29:46 2008
New Revision: 55546

URL: http://llvm.org/viewvc/llvm-project?rev=55546&view=rev
Log:
Add partial word version of ATOMIC_SWAP.


Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=55546&r1=55545&r2=55546&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri Aug 29 13:29:46 2008
@@ -3855,6 +3855,7 @@
 MachineBasicBlock *
 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
                                     bool is64bit, unsigned BinOpcode) {
+  // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
   const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
 
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
@@ -3874,9 +3875,10 @@
   exitMBB->transferSuccessors(BB);
 
   MachineRegisterInfo &RegInfo = F->getRegInfo();
-  unsigned TmpReg = RegInfo.createVirtualRegister(
-    is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass :
-              (const TargetRegisterClass *) &PPC::G8RCRegClass);
+  unsigned TmpReg = (!BinOpcode) ? incr :
+    RegInfo.createVirtualRegister(
+       is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass :
+                 (const TargetRegisterClass *) &PPC::G8RCRegClass);
 
   //  thisMBB:
   //   ...
@@ -3892,7 +3894,8 @@
   BB = loopMBB;
   BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
     .addReg(ptrA).addReg(ptrB);
-  BuildMI(BB, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
+  if (BinOpcode)
+    BuildMI(BB, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
   BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
     .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
   BuildMI(BB, TII->get(PPC::BCC))
@@ -3911,6 +3914,7 @@
                                             MachineBasicBlock *BB,
                                             bool is8bit,    // operation
                                             unsigned BinOpcode) {
+  // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
   const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
   // In 64 bit mode we have to use 64 bits for addresses, even though the
   // lwarx/stwcx are 32 bits.  With the 32-bit atomics we can use address
@@ -3938,7 +3942,6 @@
   const TargetRegisterClass *RC = 
     is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass :
               (const TargetRegisterClass *) &PPC::G8RCRegClass;
-  unsigned TmpReg = RegInfo.createVirtualRegister(RC);
   unsigned PtrReg = RegInfo.createVirtualRegister(RC);
   unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
   unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
@@ -3949,7 +3952,9 @@
   unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
   unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
   unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
+  unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
   unsigned Ptr1Reg;
+  unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
 
   //  thisMBB:
   //   ...
@@ -3966,14 +3971,15 @@
   //   li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
   //   slw mask, mask2, shift
   //  loopMBB:
-  //   l[wd]arx dest, ptr
-  //   add tmp, dest, incr2
-  //   andc tmp2, dest, mask
+  //   l[wd]arx tmpDest, ptr
+  //   add tmp, tmpDest, incr2
+  //   andc tmp2, tmpDest, mask
   //   and tmp3, tmp, mask
   //   or tmp4, tmp3, tmp2
   //   st[wd]cx. tmp4, ptr
   //   bne- loopMBB
   //   fallthrough --> exitMBB
+  //   srw dest, tmpDest, shift
 
   if (ptrA!=PPC::R0) {
     Ptr1Reg = RegInfo.createVirtualRegister(RC);
@@ -4004,11 +4010,13 @@
       .addReg(Mask2Reg).addReg(ShiftReg);
 
   BB = loopMBB;
-  BuildMI(BB, TII->get(PPC::LWARX), dest)
+  BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg)
     .addReg(PPC::R0).addReg(PtrReg);
-  BuildMI(BB, TII->get(BinOpcode), TmpReg).addReg(Incr2Reg).addReg(dest);
+  if (BinOpcode)
+    BuildMI(BB, TII->get(BinOpcode), TmpReg)
+      .addReg(Incr2Reg).addReg(TmpDestReg);
   BuildMI(BB, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
-    .addReg(dest).addReg(MaskReg);
+    .addReg(TmpDestReg).addReg(MaskReg);
   BuildMI(BB, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
     .addReg(TmpReg).addReg(MaskReg);
   BuildMI(BB, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
@@ -4023,6 +4031,7 @@
   //  exitMBB:
   //   ...
   BB = exitMBB;
+  BuildMI(BB, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
   return BB;
 }
 
@@ -4140,6 +4149,15 @@
   else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
     BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
 
+  else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
+    BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
+  else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
+    BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
+  else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
+    BB = EmitAtomicBinary(MI, BB, false, 0);
+  else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
+    BB = EmitAtomicBinary(MI, BB, true, 0);
+
   else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
            MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
     bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
@@ -4204,45 +4222,6 @@
     //   ...
     BB = exitMBB;
   }
-  else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32 ||
-           MI->getOpcode() == PPC::ATOMIC_SWAP_I64) {
-    bool is64bit = MI->getOpcode() == PPC::ATOMIC_SWAP_I64;
-
-    unsigned dest   = MI->getOperand(0).getReg();
-    unsigned ptrA   = MI->getOperand(1).getReg();
-    unsigned ptrB   = MI->getOperand(2).getReg();
-    unsigned newval = MI->getOperand(3).getReg();
-
-    MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
-    MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
-    F->insert(It, loopMBB);
-    F->insert(It, exitMBB);
-    exitMBB->transferSuccessors(BB);
-
-    //  thisMBB:
-    //   ...
-    //   fallthrough --> loopMBB
-    BB->addSuccessor(loopMBB);
-
-    //  loopMBB:
-    //   l[wd]arx dest, ptr
-    //   st[wd]cx. newval, ptr
-    //   bne- loopMBB
-    //   fallthrough --> exitMBB
-    BB = loopMBB;
-    BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
-      .addReg(ptrA).addReg(ptrB);
-    BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
-      .addReg(newval).addReg(ptrA).addReg(ptrB);
-    BuildMI(BB, TII->get(PPC::BCC))
-      .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);    
-    BB->addSuccessor(loopMBB);
-    BB->addSuccessor(exitMBB);
-    
-    //  exitMBB:
-    //   ...
-    BB = exitMBB;
-  }
   else {
     assert(0 && "Unexpected instr type to insert");
   }




From evan.cheng at apple.com  Fri Aug 29 17:05:28 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 29 Aug 2008 15:05:28 -0700
Subject: [llvm-commits] [llvm] r55498 - in /llvm/trunk:
	lib/CodeGen/SelectionDAG/DAGCombiner.cpp
	test/CodeGen/X86/alloca-align-rounding.ll
In-Reply-To: <200808282101.m7SL1uLN006828@zion.cs.uiuc.edu>
References: <200808282101.m7SL1uLN006828@zion.cs.uiuc.edu>
Message-ID: <5162A06E-ED65-4D03-8C3A-2EF0901CF8D3@apple.com>

Hi Dan,

This patch broke llvm-gcc bootstrapping. I'm going to back it out for  
now.

Evan

On Aug 28, 2008, at 2:01 PM, Dan Gohman wrote:

> Author: djg
> Date: Thu Aug 28 16:01:56 2008
> New Revision: 55498
>
> URL: http://llvm.org/viewvc/llvm-project?rev=55498&view=rev
> Log:
> Optimize DAGCombiner's worklist processing. Previously it started
> its work by putting all nodes in the worklist, requiring a big
> dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
> list and maintains a worklist for nodes that are newly created or
> need to be revisited. This allows the worklist to stay small in most
> cases, so it can be a SmallVector.
>
> This has the side effect of making DAGCombine not miss a folding
> opportunity in alloca-align-rounding.ll.
>
> Modified:
>    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>    llvm/trunk/test/CodeGen/X86/alloca-align-rounding.ll
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=55498&r1=55497&r2=55498&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Aug 28  
> 16:01:56 2008
> @@ -53,12 +53,31 @@
>     bool AfterLegalize;
>     bool Fast;
>
> +    // Create a dummy node (which is not added to allnodes), that  
> adds a reference
> +    // to the root node, preventing it from being deleted, and  
> tracking any
> +    // changes of the root.
> +    HandleSDNode Dummy;
> +
>     // Worklist of all of the nodes that need to be simplified.
> -    std::vector<SDNode*> WorkList;
> +    SmallVector<SDNode*, 8> WorkList;
> +
> +    // The current position of our iteration through the allnodes  
> list.
> +    SelectionDAG::allnodes_iterator CurNode;
>
>     // AA - Used for DAG load/store alias analysis.
>     AliasAnalysis &AA;
>
> +    /// AdvanceCurNode - Update CurNode to point to the next node  
> to process.
> +    ///
> +    void AdvanceCurNode() {
> +      // We start at the end of the list and work towards the  
> front. Setting
> +      // CurNode to DAG.allnodes_end() indicates that we're done.
> +      if (CurNode == DAG.allnodes_begin())
> +        CurNode = DAG.allnodes_end();
> +      else
> +        --CurNode;
> +    }
> +
>     /// AddUsersToWorkList - When an instruction is simplified, add  
> all users of
>     /// the instruction to the work lists because they might get  
> more simplified
>     /// now.
> @@ -86,6 +105,10 @@
>     void removeFromWorkList(SDNode *N) {
>       WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
>                      WorkList.end());
> +      // If the next node we were planning to process is deleted,
> +      // skip past it.
> +      if (N == CurNode)
> +        AdvanceCurNode();
>     }
>
>     SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
> @@ -243,10 +266,14 @@
>         TLI(D.getTargetLoweringInfo()),
>         AfterLegalize(false),
>         Fast(fast),
> +        Dummy(D.getRoot()),
>         AA(A) {}
>
>     /// Run - runs the dag combiner on all nodes in the work list
>     void Run(bool RunningAfterLegalize);
> +
> +    /// ProcessNode - runs the dag combiner on a node
> +    void ProcessNode(SDNode *N);
>   };
> }
>
> @@ -575,91 +602,89 @@
> //  Main DAG Combiner implementation
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> +void DAGCombiner::ProcessNode(SDNode *N) {
> +  // If N has no uses, it is dead.  Make sure to revisit all N's  
> operands once
> +  // N is deleted from the DAG, since they too may now be dead or  
> may have a
> +  // reduced number of uses, allowing other xforms.
> +  if (N->use_empty() && N != &Dummy) {
> +    for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
> +      AddToWorkList(N->getOperand(i).Val);
> +
> +    DAG.DeleteNode(N);
> +    return;
> +  }
> +
> +  SDValue RV = combine(N);
> +
> +  if (RV.Val == 0)
> +    return;
> +
> +  ++NodesCombined;
> +
> +  // If we get back the same node we passed in, rather than a new  
> node or
> +  // zero, we know that the node must have defined multiple values  
> and
> +  // CombineTo was used.  Since CombineTo takes care of the worklist
> +  // mechanics for us, we have no work to do in this case.
> +  if (RV.Val == N)
> +    return;
> +
> +  assert(N->getOpcode() != ISD::DELETED_NODE &&
> +         RV.Val->getOpcode() != ISD::DELETED_NODE &&
> +         "Node was deleted but visit returned new node!");
> +
> +  DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
> +  DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
> +  DOUT << '\n';
> +
> +  if (N->getNumValues() == RV.Val->getNumValues())
> +    DAG.ReplaceAllUsesWith(N, RV.Val);
> +  else {
> +    assert(N->getValueType(0) == RV.getValueType() &&
> +           N->getNumValues() == 1 && "Type mismatch");
> +    SDValue OpV = RV;
> +    DAG.ReplaceAllUsesWith(N, &OpV);
> +  }
> +
> +  // Delete the old node.
> +  removeFromWorkList(N);
> +  DAG.DeleteNode(N);
> +
> +  // Push the new node and any users onto the worklist
> +  AddToWorkList(RV.Val);
> +  AddUsersToWorkList(RV.Val);
> +}
> +
> void DAGCombiner::Run(bool RunningAfterLegalize) {
>   // set the instance variable, so that the various visit routines  
> may use it.
>   AfterLegalize = RunningAfterLegalize;
>
> -  // Add all the dag nodes to the worklist.
> -  WorkList.reserve(DAG.allnodes_size());
> -  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
> -       E = DAG.allnodes_end(); I != E; ++I)
> -    WorkList.push_back(I);
> -
> -  // Create a dummy node (which is not added to allnodes), that  
> adds a reference
> -  // to the root node, preventing it from being deleted, and  
> tracking any
> -  // changes of the root.
> -  HandleSDNode Dummy(DAG.getRoot());
> -
>   // The root of the dag may dangle to deleted nodes until the dag  
> combiner is
>   // done.  Set it to null to avoid confusion.
>   DAG.setRoot(SDValue());
>
> -  // while the worklist isn't empty, inspect the node on the end of  
> it and
> -  // try and combine it.
> -  while (!WorkList.empty()) {
> -    SDNode *N = WorkList.back();
> -    WorkList.pop_back();
> -
> -    // If N has no uses, it is dead.  Make sure to revisit all N's  
> operands once
> -    // N is deleted from the DAG, since they too may now be dead or  
> may have a
> -    // reduced number of uses, allowing other xforms.
> -    if (N->use_empty() && N != &Dummy) {
> -      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
> -        AddToWorkList(N->getOperand(i).Val);
> -
> -      DAG.DeleteNode(N);
> -      continue;
> +  // Process all the original dag nodes. We process starting from the
> +  // end of the list and working forward, which is in roughly  
> topological
> +  // order. Starting at the end and working forward means we won't
> +  // accidentally revisit nodes created during the dagcombine  
> process.
> +  CurNode = prior(DAG.allnodes_end());
> +  do {
> +    SDNode *N = &*CurNode;
> +    AdvanceCurNode();
> +    ProcessNode(N);
> +    // Processing the node may have resulted in nodes being added  
> to the
> +    // worklist, because the were newly created or because one of  
> their
> +    // operands changed or some other reason they should be  
> revisited.
> +    // While the worklist isn't empty, inspect the node on the end  
> of it
> +    // and try and combine it.
> +    while (!WorkList.empty()) {
> +      SDNode *N = WorkList.back();
> +      WorkList.pop_back();
> +      if (N == CurNode)
> +        AdvanceCurNode();
> +      ProcessNode(N);
>     }
> -
> -    SDValue RV = combine(N);
> -
> -    if (RV.Val == 0)
> -      continue;
> -
> -    ++NodesCombined;
> -
> -    // If we get back the same node we passed in, rather than a new  
> node or
> -    // zero, we know that the node must have defined multiple  
> values and
> -    // CombineTo was used.  Since CombineTo takes care of the  
> worklist
> -    // mechanics for us, we have no work to do in this case.
> -    if (RV.Val == N)
> -      continue;
> -
> -    assert(N->getOpcode() != ISD::DELETED_NODE &&
> -           RV.Val->getOpcode() != ISD::DELETED_NODE &&
> -           "Node was deleted but visit returned new node!");
> +  } while (CurNode != DAG.allnodes_end());
>
> -    DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
> -    DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
> -    DOUT << '\n';
> -    WorkListRemover DeadNodes(*this);
> -    if (N->getNumValues() == RV.Val->getNumValues())
> -      DAG.ReplaceAllUsesWith(N, RV.Val, &DeadNodes);
> -    else {
> -      assert(N->getValueType(0) == RV.getValueType() &&
> -             N->getNumValues() == 1 && "Type mismatch");
> -      SDValue OpV = RV;
> -      DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
> -    }
> -
> -    // Push the new node and any users onto the worklist
> -    AddToWorkList(RV.Val);
> -    AddUsersToWorkList(RV.Val);
> -
> -    // Add any uses of the old node to the worklist in case this  
> node is the
> -    // last one that uses them.  They may become dead after this  
> node is
> -    // deleted.
> -    for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
> -      AddToWorkList(N->getOperand(i).Val);
> -
> -    // Nodes can be reintroduced into the worklist.  Make sure we  
> do not
> -    // process a node that has been replaced.
> -    removeFromWorkList(N);
> -
> -    // Finally, since the node is now dead, remove it from the graph.
> -    DAG.DeleteNode(N);
> -  }
> -
>   // If the root changed (e.g. it was a dead load, update the root).
>   DAG.setRoot(Dummy.getValue());
> }
>
> Modified: llvm/trunk/test/CodeGen/X86/alloca-align-rounding.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/alloca-align-rounding.ll?rev=55498&r1=55497&r2=55498&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/alloca-align-rounding.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/alloca-align-rounding.ll Thu Aug 28  
> 16:01:56 2008
> @@ -1,5 +1,5 @@
> ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-apple-darwin |  
> grep and | count 1
> -; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=i686-pc-linux |  
> grep and | count 3
> +; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=i686-pc-linux |  
> grep and | count 1
>
> declare void @bar(<2 x i64>* %n)
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From evan.cheng at apple.com  Fri Aug 29 17:07:24 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 29 Aug 2008 15:07:24 -0700
Subject: [llvm-commits] [llvm] r55504 - in /llvm/trunk:
	include/llvm/CodeGen/ include/llvm/Target/
	lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/
	lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/
	lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/
	lib/Target/X86/ utils/TableGen/
In-Reply-To: <200808282140.m7SLeelK008466@zion.cs.uiuc.edu>
References: <200808282140.m7SLeelK008466@zion.cs.uiuc.edu>
Message-ID: <E7D8C0EF-7C45-4A8B-BDE5-49A50912093E@apple.com>

Hi Gabor,

I am forced to back out this patch. I think it's fine but I can't  
cleanly back out 55498 without backing this out as well. Sorry about  
it. Can you re-commit the patch after getting DAG combiner to build  
again?

Thanks,

Evan

On Aug 28, 2008, at 2:40 PM, Gabor Greif wrote:

> Author: ggreif
> Date: Thu Aug 28 16:40:38 2008
> New Revision: 55504
>
> URL: http://llvm.org/viewvc/llvm-project?rev=55504&view=rev
> Log:
> erect abstraction boundaries for accessing SDValue members, rename  
> Val -> Node to reflect semantics
>
> Modified:
>    llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h
>    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
>    llvm/trunk/include/llvm/Target/TargetLowering.h
>    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
>    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
>    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
>    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>    llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
>    llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
>    llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
>    llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
>    llvm/trunk/lib/Target/CellSPU/SPUOperands.td
>    llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp
>    llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp
>    llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
>    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
>    llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
>    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
>    llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
>    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
>    llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
>    llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
>    llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
>    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>    llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h Thu Aug 28  
> 16:40:38 2008
> @@ -37,7 +37,7 @@
>   else if (Chain->getNumOperands() > 0) {
>     SDValue C0 = Chain->getOperand(0);
>     if (C0.getValueType() == MVT::Other)
> -      return C0.Val != Op && IsChainCompatible(C0.Val, Op);
> +      return C0.getNode() != Op && IsChainCompatible(C0.getNode(),  
> Op);
>   }
>   return true;
> }
> @@ -76,9 +76,9 @@
> /// AddToISelQueue - adds a node to the instruction
> /// selection queue.
> void AddToISelQueue(SDValue N) DISABLE_INLINE {
> -  int Id = N.Val->getNodeId();
> +  int Id = N.getNode()->getNodeId();
>   if (Id != -1 && !isQueued(Id)) {
> -    ISelQueue.push_back(N.Val);
> +    ISelQueue.push_back(N.getNode());
>     std::push_heap(ISelQueue.begin(), ISelQueue.end(), isel_sort());
>     setQueued(Id);
>   }
> @@ -120,7 +120,7 @@
> void ReplaceUses(SDValue F, SDValue T) DISABLE_INLINE {
>   ISelQueueUpdater ISQU(ISelQueue);
>   CurDAG->ReplaceAllUsesOfValueWith(F, T, &ISQU);
> -  setSelected(F.Val->getNodeId());
> +  setSelected(F.getNode()->getNodeId());
>   UpdateQueue(ISQU);
> }
>
> @@ -131,7 +131,7 @@
>   ISelQueueUpdater ISQU(ISelQueue);
>   CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num, &ISQU);
>   for (unsigned i = 0; i != Num; ++i)
> -    setSelected(F[i].Val->getNodeId());
> +    setSelected(F[i].getNode()->getNodeId());
>   UpdateQueue(ISQU);
> }
>
> @@ -165,7 +165,7 @@
>   // a reference to the root node, preventing it from being deleted,
>   // and tracking any changes of the root.
>   HandleSDNode Dummy(CurDAG->getRoot());
> -  ISelQueue.push_back(CurDAG->getRoot().Val);
> +  ISelQueue.push_back(CurDAG->getRoot().getNode());
>
>   // Select pending nodes from the instruction selection queue
>   // until no more nodes are left for selection.
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Thu Aug 28  
> 16:40:38 2008
> @@ -170,7 +170,7 @@
>   /// setRoot - Set the current root tag of the SelectionDAG.
>   ///
>   const SDValue &setRoot(SDValue N) {
> -    assert((!N.Val || N.getValueType() == MVT::Other) &&
> +    assert((!N.getNode() || N.getValueType() == MVT::Other) &&
>            "DAG root value is not a chain!");
>     return Root = N;
>   }
> @@ -295,7 +295,7 @@
>                          SDValue Flag) {
>     const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
>     SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N,  
> Flag };
> -    return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.Val ? 4 : 3);
> +    return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.getNode() ?  
> 4 : 3);
>   }
>
>   // Similar to last getCopyToReg() except parameter Reg is a SDValue
> @@ -303,7 +303,7 @@
>                          SDValue Flag) {
>     const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
>     SDValue Ops[] = { Chain, Reg, N, Flag };
> -    return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.Val ? 4 : 3);
> +    return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.getNode() ?  
> 4 : 3);
>   }
>
>   SDValue getCopyFromReg(SDValue Chain, unsigned Reg, MVT VT) {
> @@ -319,7 +319,7 @@
>                            SDValue Flag) {
>     const MVT *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag);
>     SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag };
> -    return getNode(ISD::CopyFromReg, VTs, 3, Ops, Flag.Val ? 3 : 2);
> +    return getNode(ISD::CopyFromReg, VTs, 3, Ops, Flag.getNode() ?  
> 3 : 2);
>   }
>
>   SDValue getCondCode(ISD::CondCode Cond);
> @@ -347,7 +347,7 @@
>     Ops.push_back(Op2);
>     Ops.push_back(InFlag);
>     return getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0],
> -                   (unsigned)Ops.size() - (InFlag.Val == 0 ? 1 : 0));
> +                   (unsigned)Ops.size() - (InFlag.getNode() == 0 ?  
> 1 : 0));
>   }
>
>   /// getNode - Gets or creates the specified node.
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Aug 28  
> 16:40:38 2008
> @@ -837,29 +837,33 @@
> /// of information is represented with the SDValue value type.
> ///
> class SDValue {
> -public:
> -  SDNode *Val;        // The node defining the value we are using.
> -private:
> +  SDNode *Node;       // The node defining the value we are using.
>   unsigned ResNo;     // Which return value of the node we are using.
> public:
> -  SDValue() : Val(0), ResNo(0) {}
> -  SDValue(SDNode *val, unsigned resno) : Val(val), ResNo(resno) {}
> +  SDValue() : Node(0), ResNo(0) {}
> +  SDValue(SDNode *node, unsigned resno) : Node(node), ResNo(resno) {}
>
>   /// get the index which selects a specific result in the SDNode
>   unsigned getResNo() const { return ResNo; }
>
> +  /// get the SDNode which holds the desired result
> +  SDNode *getNode() const { return Node; }
> +
> +  /// set the SDNode
> +  void setNode(SDNode *N) { Node = N; }
> +
>   bool operator==(const SDValue &O) const {
> -    return Val == O.Val && ResNo == O.ResNo;
> +    return Node == O.Node && ResNo == O.ResNo;
>   }
>   bool operator!=(const SDValue &O) const {
>     return !operator==(O);
>   }
>   bool operator<(const SDValue &O) const {
> -    return Val < O.Val || (Val == O.Val && ResNo < O.ResNo);
> +    return Node < O.Node || (Node == O.Node && ResNo < O.ResNo);
>   }
>
>   SDValue getValue(unsigned R) const {
> -    return SDValue(Val, R);
> +    return SDValue(Node, R);
>   }
>
>   // isOperandOf - Return true if this node is an operand of N.
> @@ -894,12 +898,12 @@
>                                       unsigned Depth = 2) const;
>
>   /// use_empty - Return true if there are no nodes using value ResNo
> -  /// of node Val.
> +  /// of Node.
>   ///
>   inline bool use_empty() const;
>
>   /// hasOneUse - Return true if there is exactly one node using value
> -  /// ResNo of node Val.
> +  /// ResNo of Node.
>   ///
>   inline bool hasOneUse() const;
> };
> @@ -913,8 +917,8 @@
>     return SDValue((SDNode*)-1, 0);
>   }
>   static unsigned getHashValue(const SDValue &Val) {
> -    return ((unsigned)((uintptr_t)Val.Val >> 4) ^
> -            (unsigned)((uintptr_t)Val.Val >> 9)) + Val.getResNo();
> +    return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
> +            (unsigned)((uintptr_t)Val.getNode() >> 9)) +  
> Val.getResNo();
>   }
>   static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
>     return LHS == RHS;
> @@ -927,13 +931,13 @@
> template<> struct simplify_type<SDValue> {
>   typedef SDNode* SimpleType;
>   static SimpleType getSimplifiedValue(const SDValue &Val) {
> -    return static_cast<SimpleType>(Val.Val);
> +    return static_cast<SimpleType>(Val.getNode());
>   }
> };
> template<> struct simplify_type<const SDValue> {
>   typedef SDNode* SimpleType;
>   static SimpleType getSimplifiedValue(const SDValue &Val) {
> -    return static_cast<SimpleType>(Val.Val);
> +    return static_cast<SimpleType>(Val.getNode());
>   }
> };
>
> @@ -977,8 +981,9 @@
>
>   const SDValue& getSDValue() const { return Operand; }
>
> -  SDNode *&getVal() { return Operand.Val; }
> -  SDNode *const &getVal() const { return Operand.Val; }
> +  SDValue &getSDValue() { return Operand; }
> +  SDNode *getVal() { return Operand.getNode(); }
> +  SDNode *getVal() const { return Operand.getNode(); } // FIXME:  
> const correct?
>
>   bool operator==(const SDValue &O) const {
>     return Operand == O;
> @@ -1323,7 +1328,7 @@
>     for (unsigned i = 0; i != NumOps; ++i) {
>       OperandList[i] = Ops[i];
>       OperandList[i].setUser(this);
> -      Ops[i].Val->addUse(OperandList[i]);
> +      Ops[i].getNode()->addUse(OperandList[i]);
>     }
>
>     ValueList = VTs.VTs;
> @@ -1393,34 +1398,34 @@
> // Define inline functions from the SDValue class.
>
> inline unsigned SDValue::getOpcode() const {
> -  return Val->getOpcode();
> +  return Node->getOpcode();
> }
> inline MVT SDValue::getValueType() const {
> -  return Val->getValueType(ResNo);
> +  return Node->getValueType(ResNo);
> }
> inline unsigned SDValue::getNumOperands() const {
> -  return Val->getNumOperands();
> +  return Node->getNumOperands();
> }
> inline const SDValue &SDValue::getOperand(unsigned i) const {
> -  return Val->getOperand(i);
> +  return Node->getOperand(i);
> }
> inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
> -  return Val->getConstantOperandVal(i);
> +  return Node->getConstantOperandVal(i);
> }
> inline bool SDValue::isTargetOpcode() const {
> -  return Val->isTargetOpcode();
> +  return Node->isTargetOpcode();
> }
> inline bool SDValue::isMachineOpcode() const {
> -  return Val->isMachineOpcode();
> +  return Node->isMachineOpcode();
> }
> inline unsigned SDValue::getMachineOpcode() const {
> -  return Val->getMachineOpcode();
> +  return Node->getMachineOpcode();
> }
> inline bool SDValue::use_empty() const {
> -  return !Val->hasAnyUseOfValue(ResNo);
> +  return !Node->hasAnyUseOfValue(ResNo);
> }
> inline bool SDValue::hasOneUse() const {
> -  return Val->hasNUsesOfValue(1, ResNo);
> +  return Node->hasNUsesOfValue(1, ResNo);
> }
>
> /// UnarySDNode - This class is used for single-operand SDNodes.   
> This is solely
> @@ -2321,7 +2326,7 @@
>   }
>
>   pointer operator*() const {
> -    return Node->getOperand(Operand).Val;
> +    return Node->getOperand(Operand).getNode();
>   }
>   pointer operator->() const { return operator*(); }
>
>
> Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetLowering.h Thu Aug 28  
> 16:40:38 2008
> @@ -1086,11 +1086,11 @@
>   static bool CheckTailCallReturnConstraints(SDValue Call, SDValue  
> Ret) {
>     unsigned NumOps = Ret.getNumOperands();
>     if ((NumOps == 1 &&
> -       (Ret.getOperand(0) == SDValue(Call.Val,1) ||
> -        Ret.getOperand(0) == SDValue(Call.Val,0))) ||
> +       (Ret.getOperand(0) == SDValue(Call.getNode(),1) ||
> +        Ret.getOperand(0) == SDValue(Call.getNode(),0))) ||
>       (NumOps > 1 &&
> -       Ret.getOperand(0) == SDValue(Call.Val,Call.Val- 
> >getNumValues()-1) &&
> -       Ret.getOperand(1) == SDValue(Call.Val,0)))
> +       Ret.getOperand(0) == SDValue(Call.getNode(),Call.getNode()- 
> >getNumValues()-1) &&
> +       Ret.getOperand(1) == SDValue(Call.getNode(),0)))
>       return true;
>     return false;
>   }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -148,8 +148,8 @@
>     // Visitation implementation - Implement dag node combining for  
> different
>     // node types.  The semantics are as follows:
>     // Return Value:
> -    //   SDValue.Val == 0   - No change was made
> -    //   SDValue.Val == N   - N was replaced, is dead, and is  
> already handled.
> +    //   SDValue.getNode() == 0   - No change was made
> +    //   SDValue.getNode() == N   - N was replaced, is dead, and is  
> already handled.
>     //   otherwise            - N should be replaced by the returned  
> Operand.
>     //
>     SDValue visitTokenFactor(SDNode *N);
> @@ -491,7 +491,7 @@
> // free when it is profitable to do so.
> static bool isOneUseSetCC(SDValue N) {
>   SDValue N0, N1, N2;
> -  if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
> +  if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
>     return true;
>   return false;
> }
> @@ -503,11 +503,11 @@
>   if (N0.getOpcode() == Opc &&  
> isa<ConstantSDNode>(N0.getOperand(1))) {
>     if (isa<ConstantSDNode>(N1)) {
>       SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
> -      AddToWorkList(OpNode.Val);
> +      AddToWorkList(OpNode.getNode());
>       return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
>     } else if (N0.hasOneUse()) {
>       SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
> -      AddToWorkList(OpNode.Val);
> +      AddToWorkList(OpNode.getNode());
>       return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
>     }
>   }
> @@ -516,11 +516,11 @@
>   if (N1.getOpcode() == Opc &&  
> isa<ConstantSDNode>(N1.getOperand(1))) {
>     if (isa<ConstantSDNode>(N0)) {
>       SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
> -      AddToWorkList(OpNode.Val);
> +      AddToWorkList(OpNode.getNode());
>       return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
>     } else if (N1.hasOneUse()) {
>       SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
> -      AddToWorkList(OpNode.Val);
> +      AddToWorkList(OpNode.getNode());
>       return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
>     }
>   }
> @@ -532,7 +532,7 @@
>   assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
>   ++NodesCombined;
>   DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
> -  DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
> +  DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG));
>   DOUT << " and " << NumTo-1 << " other values\n";
>   WorkListRemover DeadNodes(*this);
>   DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
> @@ -540,8 +540,8 @@
>   if (AddTo) {
>     // Push the new nodes and any users onto the worklist
>     for (unsigned i = 0, e = NumTo; i != e; ++i) {
> -      AddToWorkList(To[i].Val);
> -      AddUsersToWorkList(To[i].Val);
> +      AddToWorkList(To[i].getNode());
> +      AddUsersToWorkList(To[i].getNode());
>     }
>   }
>
> @@ -564,12 +564,12 @@
>     return false;
>
>   // Revisit the node.
> -  AddToWorkList(Op.Val);
> +  AddToWorkList(Op.getNode());
>
>   // Replace the old value with the new one.
>   ++NodesCombined;
> -  DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
> -  DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
> +  DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG));
> +  DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
>   DOUT << '\n';
>
>   // Replace all uses.  If any nodes become isomorphic to other  
> nodes and
> @@ -578,22 +578,22 @@
>   DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
>
>   // Push the new node and any (possibly new) users onto the worklist.
> -  AddToWorkList(TLO.New.Val);
> -  AddUsersToWorkList(TLO.New.Val);
> +  AddToWorkList(TLO.New.getNode());
> +  AddUsersToWorkList(TLO.New.getNode());
>
>   // Finally, if the node is now dead, remove it from the graph.   
> The node
>   // may not be dead if the replacement process recursively  
> simplified to
>   // something else needing this node.
> -  if (TLO.Old.Val->use_empty()) {
> -    removeFromWorkList(TLO.Old.Val);
> +  if (TLO.Old.getNode()->use_empty()) {
> +    removeFromWorkList(TLO.Old.getNode());
>
>     // If the operands of this node are only used by the node, they  
> will now
>     // be dead.  Make sure to visit them first to delete dead nodes  
> early.
> -    for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e;  
> ++i)
> -      if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
> -        AddToWorkList(TLO.Old.Val->getOperand(i).Val);
> +    for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();  
> i != e; ++i)
> +      if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
> +        AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
>
> -    DAG.DeleteNode(TLO.Old.Val);
> +    DAG.DeleteNode(TLO.Old.getNode());
>   }
>   return true;
> }
> @@ -608,7 +608,7 @@
>   // reduced number of uses, allowing other xforms.
>   if (N->use_empty() && N != &Dummy) {
>     for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
> -      AddToWorkList(N->getOperand(i).Val);
> +      AddToWorkList(N->getOperand(i).getNode());
>
>     DAG.DeleteNode(N);
>     return;
> @@ -616,7 +616,7 @@
>
>   SDValue RV = combine(N);
>
> -  if (RV.Val == 0)
> +  if (RV.getNode() == 0)
>     return;
>
>   ++NodesCombined;
> @@ -625,19 +625,19 @@
>   // zero, we know that the node must have defined multiple values and
>   // CombineTo was used.  Since CombineTo takes care of the worklist
>   // mechanics for us, we have no work to do in this case.
> -  if (RV.Val == N)
> +  if (RV.getNode() == N)
>     return;
>
>   assert(N->getOpcode() != ISD::DELETED_NODE &&
> -         RV.Val->getOpcode() != ISD::DELETED_NODE &&
> +         RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
>          "Node was deleted but visit returned new node!");
>
>   DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
> -  DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
> +  DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG));
>   DOUT << '\n';
>
> -  if (N->getNumValues() == RV.Val->getNumValues())
> -    DAG.ReplaceAllUsesWith(N, RV.Val);
> +  if (N->getNumValues() == RV.getNode()->getNumValues())
> +    DAG.ReplaceAllUsesWith(N, RV.getNode());
>   else {
>     assert(N->getValueType(0) == RV.getValueType() &&
>            N->getNumValues() == 1 && "Type mismatch");
> @@ -650,8 +650,8 @@
>   DAG.DeleteNode(N);
>
>   // Push the new node and any users onto the worklist
> -  AddToWorkList(RV.Val);
> -  AddUsersToWorkList(RV.Val);
> +  AddToWorkList(RV.getNode());
> +  AddUsersToWorkList(RV.getNode());
> }
>
> void DAGCombiner::Run(bool RunningAfterLegalize) {
> @@ -761,7 +761,7 @@
>   SDValue RV = visit(N);
>
>   // If nothing happened, try a target-specific DAG combine.
> -  if (RV.Val == 0) {
> +  if (RV.getNode() == 0) {
>     assert(N->getOpcode() != ISD::DELETED_NODE &&
>            "Node was deleted but visit returned NULL!");
>
> @@ -778,7 +778,7 @@
>
>   // If N is a commutative binary node, try commuting it to enable  
> more
>   // sdisel CSE.
> -  if (RV.Val == 0 &&
> +  if (RV.getNode() == 0 &&
>       SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
>       N->getNumValues() == 1) {
>     SDValue N0 = N->getOperand(0);
> @@ -815,9 +815,9 @@
>   // If N has two operands, where one has an input chain equal to  
> the other,
>   // the 'other' chain is redundant.
>   if (N->getNumOperands() == 2) {
> -    if (getInputChainForNode(N->getOperand(0).Val) == N- 
> >getOperand(1))
> +    if (getInputChainForNode(N->getOperand(0).getNode()) == N- 
> >getOperand(1))
>       return N->getOperand(0);
> -    if (getInputChainForNode(N->getOperand(1).Val) == N- 
> >getOperand(0))
> +    if (getInputChainForNode(N->getOperand(1).getNode()) == N- 
> >getOperand(0))
>       return N->getOperand(1);
>   }
>
> @@ -847,11 +847,11 @@
>
>       case ISD::TokenFactor:
>         if ((CombinerAA || Op.hasOneUse()) &&
> -            std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
> +            std::find(TFs.begin(), TFs.end(), Op.getNode()) ==  
> TFs.end()) {
>           // Queue up for processing.
> -          TFs.push_back(Op.Val);
> +          TFs.push_back(Op.getNode());
>           // Clean up in case the token factor is removed.
> -          AddToWorkList(Op.Val);
> +          AddToWorkList(Op.getNode());
>           Changed = true;
>           break;
>         }
> @@ -859,7 +859,7 @@
>
>       default:
>         // Only add if it isn't already in the list.
> -        if (SeenOps.insert(Op.Val))
> +        if (SeenOps.insert(Op.getNode()))
>           Ops.push_back(Op);
>         else
>           Changed = true;
> @@ -905,7 +905,7 @@
>   SDValue N00 = N0.getOperand(0);
>   SDValue N01 = N0.getOperand(1);
>   ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
> -  if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
> +  if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()- 
> >hasOneUse() &&
>       isa<ConstantSDNode>(N00.getOperand(1))) {
>     N0 = DAG.getNode(ISD::ADD, VT,
>                      DAG.getNode(ISD::SHL, VT, N00.getOperand(0),  
> N01),
> @@ -975,7 +975,7 @@
>   // fold vector ops
>   if (VT.isVector()) {
>     SDValue FoldedVOp = SimplifyVBinOp(N);
> -    if (FoldedVOp.Val) return FoldedVOp;
> +    if (FoldedVOp.getNode()) return FoldedVOp;
>   }
>
>   // fold (add x, undef) -> undef
> @@ -1001,7 +1001,7 @@
>                          N0.getOperand(1));
>   // reassociate add
>   SDValue RADD = ReassociateOps(ISD::ADD, N0, N1);
> -  if (RADD.Val != 0)
> +  if (RADD.getNode() != 0)
>     return RADD;
>   // fold ((0-A) + B) -> B-A
>   if (N0.getOpcode() == ISD::SUB &&  
> isa<ConstantSDNode>(N0.getOperand(0)) &&
> @@ -1036,23 +1036,23 @@
>   }
>
>   // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2),  
> c1<<c2), )
> -  if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
> +  if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
>     SDValue Result = combineShlAddConstant(N0, N1, DAG);
> -    if (Result.Val) return Result;
> +    if (Result.getNode()) return Result;
>   }
> -  if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
> +  if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
>     SDValue Result = combineShlAddConstant(N1, N0, DAG);
> -    if (Result.Val) return Result;
> +    if (Result.getNode()) return Result;
>   }
>
>   // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
> -  if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
> +  if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
>     SDValue Result = combineSelectAndUse(N, N0, N1, DAG);
> -    if (Result.Val) return Result;
> +    if (Result.getNode()) return Result;
>   }
> -  if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
> +  if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
>     SDValue Result = combineSelectAndUse(N, N1, N0, DAG);
> -    if (Result.Val) return Result;
> +    if (Result.getNode()) return Result;
>   }
>
>   return SDValue();
> @@ -1121,14 +1121,14 @@
> SDValue DAGCombiner::visitSUB(SDNode *N) {
>   SDValue N0 = N->getOperand(0);
>   SDValue N1 = N->getOperand(1);
> -  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
> -  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
> +  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
> +  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
>   MVT VT = N0.getValueType();
>
>   // fold vector ops
>   if (VT.isVector()) {
>     SDValue FoldedVOp = SimplifyVBinOp(N);
> -    if (FoldedVOp.Val) return FoldedVOp;
> +    if (FoldedVOp.getNode()) return FoldedVOp;
>   }
>
>   // fold (sub x, x) -> 0
> @@ -1148,9 +1148,9 @@
>   if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
>     return N0.getOperand(0);
>   // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
> -  if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
> +  if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
>     SDValue Result = combineSelectAndUse(N, N1, N0, DAG);
> -    if (Result.Val) return Result;
> +    if (Result.getNode()) return Result;
>   }
>   // If either operand of a sub is undef, the result is undef
>   if (N0.getOpcode() == ISD::UNDEF)
> @@ -1171,7 +1171,7 @@
>   // fold vector ops
>   if (VT.isVector()) {
>     SDValue FoldedVOp = SimplifyVBinOp(N);
> -    if (FoldedVOp.Val) return FoldedVOp;
> +    if (FoldedVOp.getNode()) return FoldedVOp;
>   }
>
>   // fold (mul x, undef) -> 0
> @@ -1208,7 +1208,7 @@
>   if (N1C && N0.getOpcode() == ISD::SHL &&
>       isa<ConstantSDNode>(N0.getOperand(1))) {
>     SDValue C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
> -    AddToWorkList(C3.Val);
> +    AddToWorkList(C3.getNode());
>     return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
>   }
>
> @@ -1218,19 +1218,19 @@
>     SDValue Sh(0,0), Y(0,0);
>     // Check for both (mul (shl X, C), Y)  and  (mul Y, (shl X, C)).
>     if (N0.getOpcode() == ISD::SHL &&  
> isa<ConstantSDNode>(N0.getOperand(1)) &&
> -        N0.Val->hasOneUse()) {
> +        N0.getNode()->hasOneUse()) {
>       Sh = N0; Y = N1;
>     } else if (N1.getOpcode() == ISD::SHL &&
> -               isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val- 
> >hasOneUse()) {
> +               isa<ConstantSDNode>(N1.getOperand(1)) &&  
> N1.getNode()->hasOneUse()) {
>       Sh = N1; Y = N0;
>     }
> -    if (Sh.Val) {
> +    if (Sh.getNode()) {
>       SDValue Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
>       return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
>     }
>   }
>   // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
> -  if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
> +  if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()- 
> >hasOneUse() &&
>       isa<ConstantSDNode>(N0.getOperand(1))) {
>     return DAG.getNode(ISD::ADD, VT,
>                        DAG.getNode(ISD::MUL, VT, N0.getOperand(0),  
> N1),
> @@ -1239,7 +1239,7 @@
>
>   // reassociate mul
>   SDValue RMUL = ReassociateOps(ISD::MUL, N0, N1);
> -  if (RMUL.Val != 0)
> +  if (RMUL.getNode() != 0)
>     return RMUL;
>
>   return SDValue();
> @@ -1248,14 +1248,14 @@
> SDValue DAGCombiner::visitSDIV(SDNode *N) {
>   SDValue N0 = N->getOperand(0);
>   SDValue N1 = N->getOperand(1);
> -  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
> -  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
> +  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
> +  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
>   MVT VT = N->getValueType(0);
>
>   // fold vector ops
>   if (VT.isVector()) {
>     SDValue FoldedVOp = SimplifyVBinOp(N);
> -    if (FoldedVOp.Val) return FoldedVOp;
> +    if (FoldedVOp.getNode()) return FoldedVOp;
>   }
>
>   // fold (sdiv c1, c2) -> c1/c2
> @@ -1288,21 +1288,21 @@
>     SDValue SGN = DAG.getNode(ISD::SRA, VT, N0,
>                                 DAG.getConstant(VT.getSizeInBits()-1,
>                                                  
> TLI.getShiftAmountTy()));
> -    AddToWorkList(SGN.Val);
> +    AddToWorkList(SGN.getNode());
>     // Add (N0 < 0) ? abs2 - 1 : 0;
>     SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN,
>                                 DAG.getConstant(VT.getSizeInBits()- 
> lg2,
>                                                  
> TLI.getShiftAmountTy()));
>     SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
> -    AddToWorkList(SRL.Val);
> -    AddToWorkList(ADD.Val);    // Divide by pow2
> +    AddToWorkList(SRL.getNode());
> +    AddToWorkList(ADD.getNode());    // Divide by pow2
>     SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD,
>                                 DAG.getConstant(lg2,  
> TLI.getShiftAmountTy()));
>     // If we're dividing by a positive value, we're done.   
> Otherwise, we must
>     // negate the result.
>     if (pow2 > 0)
>       return SRA;
> -    AddToWorkList(SRA.Val);
> +    AddToWorkList(SRA.getNode());
>     return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
>   }
>   // if integer divide is expensive and we satisfy the requirements,  
> emit an
> @@ -1310,7 +1310,7 @@
>   if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended()  
> > 1) &&
>       !TLI.isIntDivCheap()) {
>     SDValue Op = BuildSDIV(N);
> -    if (Op.Val) return Op;
> +    if (Op.getNode()) return Op;
>   }
>
>   // undef / X -> 0
> @@ -1326,14 +1326,14 @@
> SDValue DAGCombiner::visitUDIV(SDNode *N) {
>   SDValue N0 = N->getOperand(0);
>   SDValue N1 = N->getOperand(1);
> -  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
> -  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
> +  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
> +  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
>   MVT VT = N->getValueType(0);
>
>   // fold vector ops
>   if (VT.isVector()) {
>     SDValue FoldedVOp = SimplifyVBinOp(N);
> -    if (FoldedVOp.Val) return FoldedVOp;
> +    if (FoldedVOp.getNode()) return FoldedVOp;
>   }
>
>   // fold (udiv c1, c2) -> c1/c2
> @@ -1353,7 +1353,7 @@
>                                     DAG.getConstant(SHC- 
> >getAPIntValue()
>                                                                     .logBase2 
> (),
>                                                     ADDVT));
> -        AddToWorkList(Add.Val);
> +        AddToWorkList(Add.getNode());
>         return DAG.getNode(ISD::SRL, VT, N0, Add);
>       }
>     }
> @@ -1361,7 +1361,7 @@
>   // fold (udiv x, c) -> alternate
>   if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
>     SDValue Op = BuildUDIV(N);
> -    if (Op.Val) return Op;
> +    if (Op.getNode()) return Op;
>   }
>
>   // undef / X -> 0
> @@ -1395,12 +1395,12 @@
>   // X%C to the equivalent of X-X/C*C.
>   if (N1C && !N1C->isNullValue()) {
>     SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
> -    AddToWorkList(Div.Val);
> -    SDValue OptimizedDiv = combine(Div.Val);
> -    if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
> +    AddToWorkList(Div.getNode());
> +    SDValue OptimizedDiv = combine(Div.getNode());
> +    if (OptimizedDiv.getNode() && OptimizedDiv.getNode() !=  
> Div.getNode()) {
>       SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
>       SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
> -      AddToWorkList(Mul.Val);
> +      AddToWorkList(Mul.getNode());
>       return Sub;
>     }
>   }
> @@ -1437,7 +1437,7 @@
>           DAG.getNode(ISD::ADD, VT, N1,
>                   
> DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
>                                  VT));
> -        AddToWorkList(Add.Val);
> +        AddToWorkList(Add.getNode());
>         return DAG.getNode(ISD::AND, VT, N0, Add);
>       }
>     }
> @@ -1447,11 +1447,11 @@
>   // X%C to the equivalent of X-X/C*C.
>   if (N1C && !N1C->isNullValue()) {
>     SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
> -    SDValue OptimizedDiv = combine(Div.Val);
> -    if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
> +    SDValue OptimizedDiv = combine(Div.getNode());
> +    if (OptimizedDiv.getNode() && OptimizedDiv.getNode() !=  
> Div.getNode()) {
>       SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
>       SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
> -      AddToWorkList(Mul.Val);
> +      AddToWorkList(Mul.getNode());
>       return Sub;
>     }
>   }
> @@ -1540,9 +1540,9 @@
>   if (LoExists) {
>     SDValue Lo = DAG.getNode(LoOp, N->getValueType(0),
>                                N->op_begin(), N->getNumOperands());
> -    AddToWorkList(Lo.Val);
> -    SDValue LoOpt = combine(Lo.Val);
> -    if (LoOpt.Val && LoOpt.Val != Lo.Val &&
> +    AddToWorkList(Lo.getNode());
> +    SDValue LoOpt = combine(Lo.getNode());
> +    if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
>         (!AfterLegalize ||
>          TLI.isOperationLegal(LoOpt.getOpcode(),  
> LoOpt.getValueType())))
>       return CombineTo(N, LoOpt, LoOpt);
> @@ -1551,9 +1551,9 @@
>   if (HiExists) {
>     SDValue Hi = DAG.getNode(HiOp, N->getValueType(1),
>                                N->op_begin(), N->getNumOperands());
> -    AddToWorkList(Hi.Val);
> -    SDValue HiOpt = combine(Hi.Val);
> -    if (HiOpt.Val && HiOpt != Hi &&
> +    AddToWorkList(Hi.getNode());
> +    SDValue HiOpt = combine(Hi.getNode());
> +    if (HiOpt.getNode() && HiOpt != Hi &&
>         (!AfterLegalize ||
>          TLI.isOperationLegal(HiOpt.getOpcode(),  
> HiOpt.getValueType())))
>       return CombineTo(N, HiOpt, HiOpt);
> @@ -1563,28 +1563,28 @@
>
> SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
>   SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
> -  if (Res.Val) return Res;
> +  if (Res.getNode()) return Res;
>
>   return SDValue();
> }
>
> SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
>   SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
> -  if (Res.Val) return Res;
> +  if (Res.getNode()) return Res;
>
>   return SDValue();
> }
>
> SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
>   SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
> -  if (Res.Val) return Res;
> +  if (Res.getNode()) return Res;
>
>   return SDValue();
> }
>
> SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
>   SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
> -  if (Res.Val) return Res;
> +  if (Res.getNode()) return Res;
>
>   return SDValue();
> }
> @@ -1607,7 +1607,7 @@
>     SDValue ORNode = DAG.getNode(N->getOpcode(),
>                                    N0.getOperand(0).getValueType(),
>                                    N0.getOperand(0),  
> N1.getOperand(0));
> -    AddToWorkList(ORNode.Val);
> +    AddToWorkList(ORNode.getNode());
>     return DAG.getNode(N0.getOpcode(), VT, ORNode);
>   }
>
> @@ -1621,7 +1621,7 @@
>     SDValue ORNode = DAG.getNode(N->getOpcode(),
>                                    N0.getOperand(0).getValueType(),
>                                    N0.getOperand(0),  
> N1.getOperand(0));
> -    AddToWorkList(ORNode.Val);
> +    AddToWorkList(ORNode.getNode());
>     return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
>   }
>
> @@ -1640,7 +1640,7 @@
>   // fold vector ops
>   if (VT.isVector()) {
>     SDValue FoldedVOp = SimplifyVBinOp(N);
> -    if (FoldedVOp.Val) return FoldedVOp;
> +    if (FoldedVOp.getNode()) return FoldedVOp;
>   }
>
>   // fold (and x, undef) -> 0
> @@ -1661,7 +1661,7 @@
>     return DAG.getConstant(0, VT);
>   // reassociate and
>   SDValue RAND = ReassociateOps(ISD::AND, N0, N1);
> -  if (RAND.Val != 0)
> +  if (RAND.getNode() != 0)
>     return RAND;
>   // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
>   if (N1C && N0.getOpcode() == ISD::OR)
> @@ -1683,7 +1683,7 @@
>       // We actually want to replace all uses of the any_extend with  
> the
>       // zero_extend, to avoid duplicating things.  This will later  
> cause this
>       // AND to be folded.
> -      CombineTo(N0.Val, Zext);
> +      CombineTo(N0.getNode(), Zext);
>       return SDValue(N, 0);   // Return N so it doesn't get rechecked!
>     }
>   }
> @@ -1697,19 +1697,19 @@
>       // fold (X == 0) & (Y == 0) -> (X|Y == 0)
>       if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 ==  
> ISD::SETEQ) {
>         SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL,  
> RL);
> -        AddToWorkList(ORNode.Val);
> +        AddToWorkList(ORNode.getNode());
>         return DAG.getSetCC(VT, ORNode, LR, Op1);
>       }
>       // fold (X == -1) & (Y == -1) -> (X&Y == -1)
>       if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 ==  
> ISD::SETEQ) {
>         SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(),  
> LL, RL);
> -        AddToWorkList(ANDNode.Val);
> +        AddToWorkList(ANDNode.getNode());
>         return DAG.getSetCC(VT, ANDNode, LR, Op1);
>       }
>       // fold (X >  -1) & (Y >  -1) -> (X|Y > -1)
>       if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 ==  
> ISD::SETGT) {
>         SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL,  
> RL);
> -        AddToWorkList(ORNode.Val);
> +        AddToWorkList(ORNode.getNode());
>         return DAG.getSetCC(VT, ORNode, LR, Op1);
>       }
>     }
> @@ -1729,7 +1729,7 @@
>   // Simplify: and (op x...), (op y...)  -> (op (and x, y))
>   if (N0.getOpcode() == N1.getOpcode()) {
>     SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
> -    if (Tmp.Val) return Tmp;
> +    if (Tmp.getNode()) return Tmp;
>   }
>
>   // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
> @@ -1738,7 +1738,7 @@
>       SimplifyDemandedBits(SDValue(N, 0)))
>     return SDValue(N, 0);
>   // fold (zext_inreg (extload x)) -> (zextload x)
> -  if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
> +  if (ISD::isEXTLoad(N0.getNode()) &&  
> ISD::isUNINDEXEDLoad(N0.getNode())) {
>     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>     MVT EVT = LN0->getMemoryVT();
>     // If we zero all the possible extended bits, then we can turn  
> this into
> @@ -1754,12 +1754,12 @@
>                                          LN0->isVolatile(),
>                                          LN0->getAlignment());
>       AddToWorkList(N);
> -      CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
> +      CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
>       return SDValue(N, 0);   // Return N so it doesn't get rechecked!
>     }
>   }
>   // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one  
> use
> -  if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
> +  if (ISD::isSEXTLoad(N0.getNode()) &&  
> ISD::isUNINDEXEDLoad(N0.getNode()) &&
>       N0.hasOneUse()) {
>     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>     MVT EVT = LN0->getMemoryVT();
> @@ -1776,7 +1776,7 @@
>                                          LN0->isVolatile(),
>                                          LN0->getAlignment());
>       AddToWorkList(N);
> -      CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
> +      CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
>       return SDValue(N, 0);   // Return N so it doesn't get rechecked!
>     }
>   }
> @@ -1813,13 +1813,13 @@
>                                DAG.getConstant(PtrOff, PtrType));
>           Alignment = MinAlign(Alignment, PtrOff);
>         }
> -        AddToWorkList(NewPtr.Val);
> +        AddToWorkList(NewPtr.getNode());
>         SDValue Load =
>           DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
>                          LN0->getSrcValue(), LN0- 
> >getSrcValueOffset(), EVT,
>                          LN0->isVolatile(), Alignment);
>         AddToWorkList(N);
> -        CombineTo(N0.Val, Load, Load.getValue(1));
> +        CombineTo(N0.getNode(), Load, Load.getValue(1));
>         return SDValue(N, 0);   // Return N so it doesn't get  
> rechecked!
>       }
>     }
> @@ -1839,7 +1839,7 @@
>   // fold vector ops
>   if (VT.isVector()) {
>     SDValue FoldedVOp = SimplifyVBinOp(N);
> -    if (FoldedVOp.Val) return FoldedVOp;
> +    if (FoldedVOp.getNode()) return FoldedVOp;
>   }
>
>   // fold (or x, undef) -> -1
> @@ -1862,10 +1862,10 @@
>     return N1;
>   // reassociate or
>   SDValue ROR = ReassociateOps(ISD::OR, N0, N1);
> -  if (ROR.Val != 0)
> +  if (ROR.getNode() != 0)
>     return ROR;
>   // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
> -  if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
> +  if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()- 
> >hasOneUse() &&
>              isa<ConstantSDNode>(N0.getOperand(1))) {
>     ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
>     return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT,  
> N0.getOperand(0),
> @@ -1885,7 +1885,7 @@
>       if (cast<ConstantSDNode>(LR)->isNullValue() &&
>           (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
>         SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL,  
> RL);
> -        AddToWorkList(ORNode.Val);
> +        AddToWorkList(ORNode.getNode());
>         return DAG.getSetCC(VT, ORNode, LR, Op1);
>       }
>       // fold (X != -1) | (Y != -1) -> (X&Y != -1)
> @@ -1893,7 +1893,7 @@
>       if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
>           (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
>         SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(),  
> LL, RL);
> -        AddToWorkList(ANDNode.Val);
> +        AddToWorkList(ANDNode.getNode());
>         return DAG.getSetCC(VT, ANDNode, LR, Op1);
>       }
>     }
> @@ -1913,7 +1913,7 @@
>   // Simplify: or (op x...), (op y...)  -> (op (or x, y))
>   if (N0.getOpcode() == N1.getOpcode()) {
>     SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
> -    if (Tmp.Val) return Tmp;
> +    if (Tmp.getNode()) return Tmp;
>   }
>
>   // (X & C1) | (Y & C2)  -> (X|Y) & C3  if possible.
> @@ -1922,7 +1922,7 @@
>       N0.getOperand(1).getOpcode() == ISD::Constant &&
>       N1.getOperand(1).getOpcode() == ISD::Constant &&
>       // Don't increase # computations.
> -      (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
> +      (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
>     // We can only do this xform if we know that bits from X that  
> are set in C2
>     // but not in C1 are already zero.  Likewise for Y.
>     const APInt &LHSMask =
> @@ -2023,14 +2023,14 @@
>       Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
>
>     // If there is an AND of either shifted operand, apply it to the  
> result.
> -    if (LHSMask.Val || RHSMask.Val) {
> +    if (LHSMask.getNode() || RHSMask.getNode()) {
>       APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
>
> -      if (LHSMask.Val) {
> +      if (LHSMask.getNode()) {
>         APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
>         Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() |  
> RHSBits;
>       }
> -      if (RHSMask.Val) {
> +      if (RHSMask.getNode()) {
>         APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
>         Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() |  
> LHSBits;
>       }
> @@ -2038,12 +2038,12 @@
>       Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
>     }
>
> -    return Rot.Val;
> +    return Rot.getNode();
>   }
>
>   // If there is a mask here, and we have a variable shift, we can't  
> be sure
>   // that we're masking out the right stuff.
> -  if (LHSMask.Val || RHSMask.Val)
> +  if (LHSMask.getNode() || RHSMask.getNode())
>     return 0;
>
>   // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
> @@ -2054,9 +2054,9 @@
>           dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
>       if (SUBC->getAPIntValue() == OpSizeInBits) {
>         if (HasROTL)
> -          return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,  
> LHSShiftAmt).Val;
> +          return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,  
> LHSShiftAmt).getNode();
>         else
> -          return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,  
> RHSShiftAmt).Val;
> +          return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,  
> RHSShiftAmt).getNode();
>       }
>     }
>   }
> @@ -2069,9 +2069,9 @@
>           dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
>       if (SUBC->getAPIntValue() == OpSizeInBits) {
>         if (HasROTL)
> -          return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,  
> LHSShiftAmt).Val;
> +          return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,  
> LHSShiftAmt).getNode();
>         else
> -          return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,  
> RHSShiftAmt).Val;
> +          return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,  
> RHSShiftAmt).getNode();
>       }
>     }
>   }
> @@ -2094,9 +2094,9 @@
>       if (ConstantSDNode *SUBC =  
> cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
>         if (SUBC->getAPIntValue() == OpSizeInBits) {
>           if (HasROTL)
> -            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,  
> LHSShiftAmt).Val;
> +            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,  
> LHSShiftAmt).getNode();
>           else
> -            return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,  
> RHSShiftAmt).Val;
> +            return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,  
> RHSShiftAmt).getNode();
>         }
>       }
>     } else if (LExtOp0.getOpcode() == ISD::SUB &&
> @@ -2108,9 +2108,9 @@
>       if (ConstantSDNode *SUBC =  
> cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
>         if (SUBC->getAPIntValue() == OpSizeInBits) {
>           if (HasROTL)
> -            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,  
> RHSShiftAmt).Val;
> +            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,  
> RHSShiftAmt).getNode();
>           else
> -            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,  
> LHSShiftAmt).Val;
> +            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,  
> LHSShiftAmt).getNode();
>         }
>       }
>     }
> @@ -2131,7 +2131,7 @@
>   // fold vector ops
>   if (VT.isVector()) {
>     SDValue FoldedVOp = SimplifyVBinOp(N);
> -    if (FoldedVOp.Val) return FoldedVOp;
> +    if (FoldedVOp.getNode()) return FoldedVOp;
>   }
>
>   // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
> @@ -2153,7 +2153,7 @@
>     return N0;
>   // reassociate xor
>   SDValue RXOR = ReassociateOps(ISD::XOR, N0, N1);
> -  if (RXOR.Val != 0)
> +  if (RXOR.getNode() != 0)
>     return RXOR;
>   // fold !(x cc y) -> (x !cc y)
>   if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS,  
> RHS, CC)) {
> @@ -2169,11 +2169,11 @@
>   }
>   // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
>   if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() ==  
> ISD::ZERO_EXTEND &&
> -      N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0),  
> LHS, RHS, CC)){
> +      N0.getNode()->hasOneUse() &&  
> isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
>     SDValue V = N0.getOperand(0);
>     V = DAG.getNode(ISD::XOR, V.getValueType(), V,
>                     DAG.getConstant(1, V.getValueType()));
> -    AddToWorkList(V.Val);
> +    AddToWorkList(V.getNode());
>     return DAG.getNode(ISD::ZERO_EXTEND, VT, V);
>   }
>
> @@ -2185,7 +2185,7 @@
>       unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR :  
> ISD::AND;
>       LHS = DAG.getNode(ISD::XOR, VT, LHS, N1);  // RHS = ~LHS
>       RHS = DAG.getNode(ISD::XOR, VT, RHS, N1);  // RHS = ~RHS
> -      AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
> +      AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
>       return DAG.getNode(NewOpcode, VT, LHS, RHS);
>     }
>   }
> @@ -2197,7 +2197,7 @@
>       unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR :  
> ISD::AND;
>       LHS = DAG.getNode(ISD::XOR, VT, LHS, N1);  // RHS = ~LHS
>       RHS = DAG.getNode(ISD::XOR, VT, RHS, N1);  // RHS = ~RHS
> -      AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
> +      AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
>       return DAG.getNode(NewOpcode, VT, LHS, RHS);
>     }
>   }
> @@ -2229,7 +2229,7 @@
>   // Simplify: xor (op x...), (op y...)  -> (op (xor x, y))
>   if (N0.getOpcode() == N1.getOpcode()) {
>     SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
> -    if (Tmp.Val) return Tmp;
> +    if (Tmp.getNode()) return Tmp;
>   }
>
>   // Simplify the expression using non-local knowledge.
> @@ -2243,7 +2243,7 @@
> /// visitShiftByConstant - Handle transforms common to the three  
> shifts, when
> /// the shift amount is a constant.
> SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
> -  SDNode *LHS = N->getOperand(0).Val;
> +  SDNode *LHS = N->getOperand(0).getNode();
>   if (!LHS->hasOneUse()) return SDValue();
>
>   // We want to pull some binops through shifts, so that we have  
> (and (shift))
> @@ -2278,7 +2278,7 @@
>   //
>   //void foo(int *X, int i) { X[i & 1235] = 1; }
>   //int bar(int *X, int i) { return X[i & 255]; }
> -  SDNode *BinOpLHSVal = LHS->getOperand(0).Val;
> +  SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
>   if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
>        BinOpLHSVal->getOpcode() != ISD::SRA &&
>        BinOpLHSVal->getOpcode() != ISD::SRL) ||
> @@ -2502,7 +2502,7 @@
>       return DAG.getNode(ISD::UNDEF, VT);
>
>     SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT,  
> N0.getOperand(0), N1);
> -    AddToWorkList(SmallShift.Val);
> +    AddToWorkList(SmallShift.getNode());
>     return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
>   }
>
> @@ -2540,7 +2540,7 @@
>       if (ShAmt) {
>         Op = DAG.getNode(ISD::SRL, VT, Op,
>                          DAG.getConstant(ShAmt,  
> TLI.getShiftAmountTy()));
> -        AddToWorkList(Op.Val);
> +        AddToWorkList(Op.getNode());
>       }
>       return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
>     }
> @@ -2612,7 +2612,7 @@
>     SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0,  
> DAG.getConstant(1, VT0));
>     if (VT == VT0)
>       return XORNode;
> -    AddToWorkList(XORNode.Val);
> +    AddToWorkList(XORNode.getNode());
>     if (VT.bitsGT(VT0))
>       return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
>     return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
> @@ -2620,13 +2620,13 @@
>   // fold select C, 0, X -> ~C & X
>   if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
>     SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0,  
> DAG.getConstant(1, VT));
> -    AddToWorkList(XORNode.Val);
> +    AddToWorkList(XORNode.getNode());
>     return DAG.getNode(ISD::AND, VT, XORNode, N2);
>   }
>   // fold select C, X, 1 -> ~C | X
>   if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() ==  
> 1) {
>     SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0,  
> DAG.getConstant(1, VT));
> -    AddToWorkList(XORNode.Val);
> +    AddToWorkList(XORNode.getNode());
>     return DAG.getNode(ISD::OR, VT, XORNode, N1);
>   }
>   // fold select C, X, 0 -> C & X
> @@ -2673,9 +2673,9 @@
>
>   // Determine if the condition we're dealing with is constant
>   SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1,  
> CC, false);
> -  if (SCC.Val) AddToWorkList(SCC.Val);
> +  if (SCC.getNode()) AddToWorkList(SCC.getNode());
>
> -  if (ConstantSDNode *SCCC =  
> dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
> +  if (ConstantSDNode *SCCC =  
> dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
>     if (!SCCC->isNullValue())
>       return N2;    // cond always true -> true val
>     else
> @@ -2683,7 +2683,7 @@
>   }
>
>   // Fold to a simpler select_cc
> -  if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
> +  if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
>     return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
>                        SCC.getOperand(0), SCC.getOperand(1), N2, N3,
>                        SCC.getOperand(2));
> @@ -2711,7 +2711,7 @@
>                                     TargetLowering &TLI) {
>   bool HasCopyToRegUses = false;
>   bool isTruncFree = TLI.isTruncateFree(N->getValueType(0),  
> N0.getValueType());
> -  for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val- 
> >use_end();
> +  for (SDNode::use_iterator UI = N0.getNode()->use_begin(), UE =  
> N0.getNode()->use_end();
>        UI != UE; ++UI) {
>     SDNode *User = *UI;
>     if (User == N)
> @@ -2755,7 +2755,7 @@
>       SDNode *User = *UI;
>       for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
>         SDValue UseOp = User->getOperand(i);
> -        if (UseOp.Val == N && UseOp.getResNo() == 0) {
> +        if (UseOp.getNode() == N && UseOp.getResNo() == 0) {
>           BothLiveOut = true;
>           break;
>         }
> @@ -2785,10 +2785,10 @@
>   if (N0.getOpcode() == ISD::TRUNCATE) {
>     // fold (sext (truncate (load x))) -> (sext (smaller load x))
>     // fold (sext (truncate (srl (load x), c))) -> (sext (smaller  
> load (x+c/n)))
> -    SDValue NarrowLoad = ReduceLoadWidth(N0.Val);
> -    if (NarrowLoad.Val) {
> -      if (NarrowLoad.Val != N0.Val)
> -        CombineTo(N0.Val, NarrowLoad);
> +    SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
> +    if (NarrowLoad.getNode()) {
> +      if (NarrowLoad.getNode() != N0.getNode())
> +        CombineTo(N0.getNode(), NarrowLoad);
>       return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
>     }
>
> @@ -2830,7 +2830,7 @@
>   }
>
>   // fold (sext (load x)) -> (sext (truncate (sextload x)))
> -  if (ISD::isNON_EXTLoad(N0.Val) &&
> +  if (ISD::isNON_EXTLoad(N0.getNode()) &&
>       ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
>        TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))) {
>     bool DoXform = true;
> @@ -2847,7 +2847,7 @@
>                                          LN0->getAlignment());
>       CombineTo(N, ExtLoad);
>       SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(),  
> ExtLoad);
> -      CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
> +      CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
>       // Extend SetCC uses if necessary.
>       for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
>         SDNode *SetCC = SetCCs[i];
> @@ -2869,8 +2869,8 @@
>
>   // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
>   // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
> -  if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
> -      ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
> +  if ((ISD::isSEXTLoad(N0.getNode()) ||  
> ISD::isEXTLoad(N0.getNode())) &&
> +      ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
>     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>     MVT EVT = LN0->getMemoryVT();
>     if ((!AfterLegalize && !LN0->isVolatile()) ||
> @@ -2881,7 +2881,7 @@
>                                          LN0->isVolatile(),
>                                          LN0->getAlignment());
>       CombineTo(N, ExtLoad);
> -      CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE,  
> N0.getValueType(), ExtLoad),
> +      CombineTo(N0.getNode(), DAG.getNode(ISD::TRUNCATE,  
> N0.getValueType(), ExtLoad),
>                 ExtLoad.getValue(1));
>       return SDValue(N, 0);   // Return N so it doesn't get rechecked!
>     }
> @@ -2893,7 +2893,7 @@
>       SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
>                        DAG.getConstant(~0ULL, VT),  
> DAG.getConstant(0, VT),
>                        cast<CondCodeSDNode>(N0.getOperand(2))- 
> >get(), true);
> -    if (SCC.Val) return SCC;
> +    if (SCC.getNode()) return SCC;
>   }
>
>   // fold (sext x) -> (zext x) if the sign bit is known zero.
> @@ -2919,10 +2919,10 @@
>   // fold (zext (truncate (load x))) -> (zext (smaller load x))
>   // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x 
> +c/n)))
>   if (N0.getOpcode() == ISD::TRUNCATE) {
> -    SDValue NarrowLoad = ReduceLoadWidth(N0.Val);
> -    if (NarrowLoad.Val) {
> -      if (NarrowLoad.Val != N0.Val)
> -        CombineTo(N0.Val, NarrowLoad);
> +    SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
> +    if (NarrowLoad.getNode()) {
> +      if (NarrowLoad.getNode() != N0.getNode())
> +        CombineTo(N0.getNode(), NarrowLoad);
>       return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
>     }
>   }
> @@ -2955,7 +2955,7 @@
>   }
>
>   // fold (zext (load x)) -> (zext (truncate (zextload x)))
> -  if (ISD::isNON_EXTLoad(N0.Val) &&
> +  if (ISD::isNON_EXTLoad(N0.getNode()) &&
>       ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
>        TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
>     bool DoXform = true;
> @@ -2972,7 +2972,7 @@
>                                          LN0->getAlignment());
>       CombineTo(N, ExtLoad);
>       SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(),  
> ExtLoad);
> -      CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
> +      CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
>       // Extend SetCC uses if necessary.
>       for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
>         SDNode *SetCC = SetCCs[i];
> @@ -2994,8 +2994,8 @@
>
>   // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
>   // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
> -  if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
> -      ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
> +  if ((ISD::isZEXTLoad(N0.getNode()) ||  
> ISD::isEXTLoad(N0.getNode())) &&
> +      ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
>     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>     MVT EVT = LN0->getMemoryVT();
>     if ((!AfterLegalize && !LN0->isVolatile()) ||
> @@ -3006,7 +3006,7 @@
>                                          LN0->isVolatile(),
>                                          LN0->getAlignment());
>       CombineTo(N, ExtLoad);
> -      CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE,  
> N0.getValueType(), ExtLoad),
> +      CombineTo(N0.getNode(), DAG.getNode(ISD::TRUNCATE,  
> N0.getValueType(), ExtLoad),
>                 ExtLoad.getValue(1));
>       return SDValue(N, 0);   // Return N so it doesn't get rechecked!
>     }
> @@ -3018,7 +3018,7 @@
>       SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
>                        DAG.getConstant(1, VT), DAG.getConstant(0, VT),
>                        cast<CondCodeSDNode>(N0.getOperand(2))- 
> >get(), true);
> -    if (SCC.Val) return SCC;
> +    if (SCC.getNode()) return SCC;
>   }
>
>   return SDValue();
> @@ -3042,10 +3042,10 @@
>   // fold (aext (truncate (load x))) -> (aext (smaller load x))
>   // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x 
> +c/n)))
>   if (N0.getOpcode() == ISD::TRUNCATE) {
> -    SDValue NarrowLoad = ReduceLoadWidth(N0.Val);
> -    if (NarrowLoad.Val) {
> -      if (NarrowLoad.Val != N0.Val)
> -        CombineTo(N0.Val, NarrowLoad);
> +    SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
> +    if (NarrowLoad.getNode()) {
> +      if (NarrowLoad.getNode() != N0.getNode())
> +        CombineTo(N0.getNode(), NarrowLoad);
>       return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
>     }
>   }
> @@ -3076,7 +3076,7 @@
>   }
>
>   // fold (aext (load x)) -> (aext (truncate (extload x)))
> -  if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
> +  if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
>       ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
>        TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
>     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
> @@ -3088,7 +3088,7 @@
>                                        LN0->getAlignment());
>     CombineTo(N, ExtLoad);
>     // Redirect any chain users to the new load.
> -    DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1),  
> SDValue(ExtLoad.Val, 1));
> +    DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1),  
> SDValue(ExtLoad.getNode(), 1));
>     // If any node needs the original loaded value, recompute it.
>     if (!LN0->use_empty())
>       CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(),  
> ExtLoad),
> @@ -3100,7 +3100,7 @@
>   // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
>   // fold (aext ( extload x)) -> (aext (truncate (extload  x)))
>   if (N0.getOpcode() == ISD::LOAD &&
> -      !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
> +      !ISD::isNON_EXTLoad(N0.getNode()) &&  
> ISD::isUNINDEXEDLoad(N0.getNode()) &&
>       N0.hasOneUse()) {
>     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>     MVT EVT = LN0->getMemoryVT();
> @@ -3111,7 +3111,7 @@
>                                        LN0->isVolatile(),
>                                        LN0->getAlignment());
>     CombineTo(N, ExtLoad);
> -    CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(),  
> ExtLoad),
> +    CombineTo(N0.getNode(), DAG.getNode(ISD::TRUNCATE,  
> N0.getValueType(), ExtLoad),
>               ExtLoad.getValue(1));
>     return SDValue(N, 0);   // Return N so it doesn't get rechecked!
>   }
> @@ -3122,7 +3122,7 @@
>       SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
>                        DAG.getConstant(1, VT), DAG.getConstant(0, VT),
>                        cast<CondCodeSDNode>(N0.getOperand(2))- 
> >get(), true);
> -    if (SCC.Val)
> +    if (SCC.getNode())
>       return SCC;
>   }
>
> @@ -3145,14 +3145,14 @@
>     break;
>   case ISD::SRL:
>     // Only look at single-use SRLs.
> -    if (!V.Val->hasOneUse())
> +    if (!V.getNode()->hasOneUse())
>       break;
>     if (ConstantSDNode *RHSC =  
> dyn_cast<ConstantSDNode>(V.getOperand(1))) {
>       // See if we can recursively simplify the LHS.
>       unsigned Amt = RHSC->getValue();
>       APInt NewMask = Mask << Amt;
>       SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
> -      if (SimplifyLHS.Val) {
> +      if (SimplifyLHS.getNode()) {
>         return DAG.getNode(ISD::SRL, V.getValueType(),
>                            SimplifyLHS, V.getOperand(1));
>       }
> @@ -3221,7 +3221,7 @@
>     unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
>     SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
>                                    DAG.getConstant(PtrOff, PtrType));
> -    AddToWorkList(NewPtr.Val);
> +    AddToWorkList(NewPtr.getNode());
>     SDValue Load = (ExtType == ISD::NON_EXTLOAD)
>       ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
>                     LN0->getSrcValue(), LN0->getSrcValueOffset() +  
> PtrOff,
> @@ -3234,9 +3234,9 @@
>       WorkListRemover DeadNodes(*this);
>       DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
>                                     &DeadNodes);
> -      CombineTo(N->getOperand(0).Val, Load);
> +      CombineTo(N->getOperand(0).getNode(), Load);
>     } else
> -      CombineTo(N0.Val, Load, Load.getValue(1));
> +      CombineTo(N0.getNode(), Load, Load.getValue(1));
>     if (ShAmt) {
>       if (Opc == ISD::SIGN_EXTEND_INREG)
>         return DAG.getNode(Opc, VT, Load, N->getOperand(1));
> @@ -3293,7 +3293,7 @@
>   // fold (sext_in_reg (load x)) -> (smaller sextload x)
>   // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/ 
> evtbits))
>   SDValue NarrowLoad = ReduceLoadWidth(N);
> -  if (NarrowLoad.Val)
> +  if (NarrowLoad.getNode())
>     return NarrowLoad;
>
>   // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
> @@ -3311,8 +3311,8 @@
>   }
>
>   // fold (sext_inreg (extload x)) -> (sextload x)
> -  if (ISD::isEXTLoad(N0.Val) &&
> -      ISD::isUNINDEXEDLoad(N0.Val) &&
> +  if (ISD::isEXTLoad(N0.getNode()) &&
> +      ISD::isUNINDEXEDLoad(N0.getNode()) &&
>       EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
>       ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
>        TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
> @@ -3323,11 +3323,11 @@
>                                        LN0->isVolatile(),
>                                        LN0->getAlignment());
>     CombineTo(N, ExtLoad);
> -    CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
> +    CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
>     return SDValue(N, 0);   // Return N so it doesn't get rechecked!
>   }
>   // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one  
> use
> -  if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
> +  if (ISD::isZEXTLoad(N0.getNode()) &&  
> ISD::isUNINDEXEDLoad(N0.getNode()) &&
>       N0.hasOneUse() &&
>       EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
>       ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
> @@ -3339,7 +3339,7 @@
>                                        LN0->isVolatile(),
>                                        LN0->getAlignment());
>     CombineTo(N, ExtLoad);
> -    CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
> +    CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
>     return SDValue(N, 0);   // Return N so it doesn't get rechecked!
>   }
>   return SDValue();
> @@ -3379,7 +3379,7 @@
>   SDValue Shorter =
>     GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
>                                              VT.getSizeInBits()));
> -  if (Shorter.Val)
> +  if (Shorter.getNode())
>     return DAG.getNode(ISD::TRUNCATE, VT, Shorter);
>
>   // fold (truncate (load x)) -> (smaller load x)
> @@ -3390,8 +3390,8 @@
> static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
>   SDValue Elt = N->getOperand(i);
>   if (Elt.getOpcode() != ISD::MERGE_VALUES)
> -    return Elt.Val;
> -  return Elt.getOperand(Elt.getResNo()).Val;
> +    return Elt.getNode();
> +  return Elt.getOperand(Elt.getResNo()).getNode();
> }
>
> /// CombineConsecutiveLoads - build_pair (load, load) -> load
> @@ -3434,7 +3434,7 @@
>   // on the bitconvert.
>   // First check to see if this is all constant.
>   if (!AfterLegalize &&
> -      N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
> +      N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()- 
> >hasOneUse() &&
>       VT.isVector()) {
>     bool isSimple = true;
>     for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
> @@ -3449,14 +3449,14 @@
>     assert(!DestEltVT.isVector() &&
>            "Element type of vector ValueType must not be vector!");
>     if (isSimple) {
> -      return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val,  
> DestEltVT);
> +      return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(),  
> DestEltVT);
>     }
>   }
>
>   // If the input is a constant, let getNode() fold it.
>   if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
>     SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
> -    if (Res.Val != N) return Res;
> +    if (Res.getNode() != N) return Res;
>   }
>
>   if (N0.getOpcode() == ISD::BIT_CONVERT)  // conv(conv(x,t1),t2) ->  
> conv(x,t2)
> @@ -3464,7 +3464,7 @@
>
>   // fold (conv (load x)) -> (load (conv*)x)
>   // If the resultant load doesn't need a higher alignment than the  
> original!
> -  if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() &&
> +  if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
>       // Do not change the width of a volatile load.
>       !cast<LoadSDNode>(N0)->isVolatile() &&
>       (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) {
> @@ -3477,7 +3477,7 @@
>                                    LN0->getSrcValue(), LN0- 
> >getSrcValueOffset(),
>                                    LN0->isVolatile(), OrigAlign);
>       AddToWorkList(N);
> -      CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT,  
> N0.getValueType(), Load),
> +      CombineTo(N0.getNode(), DAG.getNode(ISD::BIT_CONVERT,  
> N0.getValueType(), Load),
>                 Load.getValue(1));
>       return Load;
>     }
> @@ -3487,9 +3487,9 @@
>   // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit)
>   // This often reduces constant pool loads.
>   if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
> -      N0.Val->hasOneUse() && VT.isInteger() && !VT.isVector()) {
> +      N0.getNode()->hasOneUse() && VT.isInteger() && ! 
> VT.isVector()) {
>     SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT,  
> N0.getOperand(0));
> -    AddToWorkList(NewConv.Val);
> +    AddToWorkList(NewConv.getNode());
>
>     APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
>     if (N0.getOpcode() == ISD::FNEG)
> @@ -3501,45 +3501,45 @@
>   // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign |  
> cst&~sign'
>   // Note that we don't handle copysign(x,cst) because this can  
> always be folded
>   // to an fneg or fabs.
> -  if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() &&
> +  if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()  
> &&
>       isa<ConstantFPSDNode>(N0.getOperand(0)) &&
>       VT.isInteger() && !VT.isVector()) {
>     unsigned OrigXWidth =  
> N0.getOperand(1).getValueType().getSizeInBits();
>     SDValue X = DAG.getNode(ISD::BIT_CONVERT,
>                               MVT::getIntegerVT(OrigXWidth),
>                               N0.getOperand(1));
> -    AddToWorkList(X.Val);
> +    AddToWorkList(X.getNode());
>
>     // If X has a different width than the result/lhs, sext it or  
> truncate it.
>     unsigned VTWidth = VT.getSizeInBits();
>     if (OrigXWidth < VTWidth) {
>       X = DAG.getNode(ISD::SIGN_EXTEND, VT, X);
> -      AddToWorkList(X.Val);
> +      AddToWorkList(X.getNode());
>     } else if (OrigXWidth > VTWidth) {
>       // To get the sign bit in the right place, we have to shift it  
> right
>       // before truncating.
>       X = DAG.getNode(ISD::SRL, X.getValueType(), X,
>                       DAG.getConstant(OrigXWidth-VTWidth,  
> X.getValueType()));
> -      AddToWorkList(X.Val);
> +      AddToWorkList(X.getNode());
>       X = DAG.getNode(ISD::TRUNCATE, VT, X);
> -      AddToWorkList(X.Val);
> +      AddToWorkList(X.getNode());
>     }
>
>     APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
>     X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT));
> -    AddToWorkList(X.Val);
> +    AddToWorkList(X.getNode());
>
>     SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
>     Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit,  
> VT));
> -    AddToWorkList(Cst.Val);
> +    AddToWorkList(Cst.getNode());
>
>     return DAG.getNode(ISD::OR, VT, X, Cst);
>   }
>
>   // bitconvert(build_pair(ld, ld)) -> ld iff load locations are  
> consecutive.
>   if (N0.getOpcode() == ISD::BUILD_PAIR) {
> -    SDValue CombineLD = CombineConsecutiveLoads(N0.Val, VT);
> -    if (CombineLD.Val)
> +    SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
> +    if (CombineLD.getNode())
>       return CombineLD;
>   }
>
> @@ -3570,7 +3570,7 @@
>     SmallVector<SDValue, 8> Ops;
>     for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
>       Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV- 
> >getOperand(i)));
> -      AddToWorkList(Ops.back().Val);
> +      AddToWorkList(Ops.back().getNode());
>     }
>     MVT VT = MVT::getVectorVT(DstEltVT,
>                               BV- 
> >getValueType(0).getVectorNumElements());
> @@ -3585,7 +3585,7 @@
>     // same sizes.
>     assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) &&  
> "Unknown FP VT!");
>     MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits());
> -    BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
> +    BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
>     SrcEltVT = IntVT;
>   }
>
> @@ -3594,7 +3594,7 @@
>   if (DstEltVT.isFloatingPoint()) {
>     assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) &&  
> "Unknown FP VT!");
>     MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits());
> -    SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV,  
> TmpVT).Val;
> +    SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV,  
> TmpVT).getNode();
>
>     // Next, convert to FP elements of the same size.
>     return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
> @@ -3674,7 +3674,7 @@
>   // fold vector ops
>   if (VT.isVector()) {
>     SDValue FoldedVOp = SimplifyVBinOp(N);
> -    if (FoldedVOp.Val) return FoldedVOp;
> +    if (FoldedVOp.getNode()) return FoldedVOp;
>   }
>
>   // fold (fadd c1, c2) -> c1+c2
> @@ -3694,7 +3694,7 @@
>
>   // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1,  
> c2))
>   if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
> -      N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
> +      N0.getNode()->hasOneUse() &&  
> isa<ConstantFPSDNode>(N0.getOperand(1)))
>     return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
>                        DAG.getNode(ISD::FADD, VT, N0.getOperand(1),  
> N1));
>
> @@ -3711,7 +3711,7 @@
>   // fold vector ops
>   if (VT.isVector()) {
>     SDValue FoldedVOp = SimplifyVBinOp(N);
> -    if (FoldedVOp.Val) return FoldedVOp;
> +    if (FoldedVOp.getNode()) return FoldedVOp;
>   }
>
>   // fold (fsub c1, c2) -> c1-c2
> @@ -3741,7 +3741,7 @@
>   // fold vector ops
>   if (VT.isVector()) {
>     SDValue FoldedVOp = SimplifyVBinOp(N);
> -    if (FoldedVOp.Val) return FoldedVOp;
> +    if (FoldedVOp.getNode()) return FoldedVOp;
>   }
>
>   // fold (fmul c1, c2) -> c1*c2
> @@ -3771,7 +3771,7 @@
>
>   // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1,  
> c2))
>   if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
> -      N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
> +      N0.getNode()->hasOneUse() &&  
> isa<ConstantFPSDNode>(N0.getOperand(1)))
>     return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
>                        DAG.getNode(ISD::FMUL, VT, N0.getOperand(1),  
> N1));
>
> @@ -3788,7 +3788,7 @@
>   // fold vector ops
>   if (VT.isVector()) {
>     SDValue FoldedVOp = SimplifyVBinOp(N);
> -    if (FoldedVOp.Val) return FoldedVOp;
> +    if (FoldedVOp.getNode()) return FoldedVOp;
>   }
>
>   // fold (fdiv c1, c2) -> c1/c2
> @@ -3955,15 +3955,15 @@
>   if (N0.getOpcode() == ISD::FP_ROUND) {
>     // This is a value preserving truncation if both round's are.
>     bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
> -                   N0.Val->getConstantOperandVal(1) == 1;
> +                   N0.getNode()->getConstantOperandVal(1) == 1;
>     return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0),
>                        DAG.getIntPtrConstant(IsTrunc));
>   }
>
>   // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
> -  if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
> +  if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()- 
> >hasOneUse()) {
>     SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0),  
> N1);
> -    AddToWorkList(Tmp.Val);
> +    AddToWorkList(Tmp.getNode());
>     return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
>   }
>
> @@ -4000,7 +4000,7 @@
>
>   // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't  
> affect the
>   // value of X.
> -  if (N0.getOpcode() == ISD::FP_ROUND && N0.Val- 
> >getConstantOperandVal(1) == 1){
> +  if (N0.getOpcode() == ISD::FP_ROUND && N0.getNode()- 
> >getConstantOperandVal(1) == 1){
>     SDValue In = N0.getOperand(0);
>     if (In.getValueType() == VT) return In;
>     if (VT.bitsLT(In.getValueType()))
> @@ -4009,7 +4009,7 @@
>   }
>
>   // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
> -  if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
> +  if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
>       ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
>        TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
>     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
> @@ -4020,7 +4020,7 @@
>                                        LN0->isVolatile(),
>                                        LN0->getAlignment());
>     CombineTo(N, ExtLoad);
> -    CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(),  
> ExtLoad,
> +    CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND,  
> N0.getValueType(), ExtLoad,
>                                   DAG.getIntPtrConstant(1)),
>               ExtLoad.getValue(1));
>     return SDValue(N, 0);   // Return N so it doesn't get rechecked!
> @@ -4037,7 +4037,7 @@
>
>   // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid  
> loading
>   // constant pool values.
> -  if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() &&
> +  if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()- 
> >hasOneUse() &&
>       N0.getOperand(0).getValueType().isInteger() &&
>       !N0.getOperand(0).getValueType().isVector()) {
>     SDValue Int = N0.getOperand(0);
> @@ -4045,7 +4045,7 @@
>     if (IntVT.isInteger() && !IntVT.isVector()) {
>       Int = DAG.getNode(ISD::XOR, IntVT, Int,
>                         DAG.getConstant(IntVT.getIntegerVTSignBit(),  
> IntVT));
> -      AddToWorkList(Int.Val);
> +      AddToWorkList(Int.getNode());
>       return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
>     }
>   }
> @@ -4071,7 +4071,7 @@
>
>   // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid  
> loading
>   // constant pool values.
> -  if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() &&
> +  if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()- 
> >hasOneUse() &&
>       N0.getOperand(0).getValueType().isInteger() &&
>       !N0.getOperand(0).getValueType().isVector()) {
>     SDValue Int = N0.getOperand(0);
> @@ -4079,7 +4079,7 @@
>     if (IntVT.isInteger() && !IntVT.isVector()) {
>       Int = DAG.getNode(ISD::AND, IntVT, Int,
>                          
> DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT));
> -      AddToWorkList(Int.Val);
> +      AddToWorkList(Int.getNode());
>       return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
>     }
>   }
> @@ -4117,9 +4117,9 @@
>
>   // Use SimplifySetCC to simplify SETCC's.
>   SDValue Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(),  
> false);
> -  if (Simp.Val) AddToWorkList(Simp.Val);
> +  if (Simp.getNode()) AddToWorkList(Simp.getNode());
>
> -  ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
> +  ConstantSDNode *SCCC =  
> dyn_cast_or_null<ConstantSDNode>(Simp.getNode());
>
>   // fold br_cc true, dest -> br dest (unconditional branch)
>   if (SCCC && !SCCC->isNullValue())
> @@ -4130,7 +4130,7 @@
>     return N->getOperand(0);
>
>   // fold to a simpler setcc
> -  if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
> +  if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
>     return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
>                        Simp.getOperand(2), Simp.getOperand(0),
>                        Simp.getOperand(1), N->getOperand(4));
> @@ -4174,7 +4174,7 @@
>   // If the pointer is not an add/sub, or if it doesn't have  
> multiple uses, bail
>   // out.  There is no reason to make this a preinc/predec.
>   if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
> -      Ptr.Val->hasOneUse())
> +      Ptr.getNode()->hasOneUse())
>     return false;
>
>   // Ask the target to do addressing mode selection.
> @@ -4204,14 +4204,14 @@
>   // Check #2.
>   if (!isLoad) {
>     SDValue Val = cast<StoreSDNode>(N)->getValue();
> -    if (Val == BasePtr || BasePtr.Val->isPredecessorOf(Val.Val))
> +    if (Val == BasePtr || BasePtr.getNode()- 
> >isPredecessorOf(Val.getNode()))
>       return false;
>   }
>
>   // Now check for #3 and #4.
>   bool RealUse = false;
> -  for (SDNode::use_iterator I = Ptr.Val->use_begin(),
> -         E = Ptr.Val->use_end(); I != E; ++I) {
> +  for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
> +         E = Ptr.getNode()->use_end(); I != E; ++I) {
>     SDNode *Use = *I;
>     if (Use == N)
>       continue;
> @@ -4235,7 +4235,7 @@
>   ++PreIndexedNodes;
>   ++NodesCombined;
>   DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
> -  DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
> +  DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
>   DOUT << '\n';
>   WorkListRemover DeadNodes(*this);
>   if (isLoad) {
> @@ -4254,8 +4254,8 @@
>   // Replace the uses of Ptr with uses of the updated base value.
>   DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
>                                 &DeadNodes);
> -  removeFromWorkList(Ptr.Val);
> -  DAG.DeleteNode(Ptr.Val);
> +  removeFromWorkList(Ptr.getNode());
> +  DAG.DeleteNode(Ptr.getNode());
>
>   return true;
> }
> @@ -4292,11 +4292,11 @@
>   } else
>     return false;
>
> -  if (Ptr.Val->hasOneUse())
> +  if (Ptr.getNode()->hasOneUse())
>     return false;
>
> -  for (SDNode::use_iterator I = Ptr.Val->use_begin(),
> -         E = Ptr.Val->use_end(); I != E; ++I) {
> +  for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
> +         E = Ptr.getNode()->use_end(); I != E; ++I) {
>     SDNode *Op = *I;
>     if (Op == N ||
>         (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
> @@ -4323,10 +4323,10 @@
>
>       // Check for #1.
>       bool TryNext = false;
> -      for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
> -             EE = BasePtr.Val->use_end(); II != EE; ++II) {
> +      for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
> +             EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
>         SDNode *Use = *II;
> -        if (Use == Ptr.Val)
> +        if (Use == Ptr.getNode())
>           continue;
>
>         // If all the uses are load / store addresses, then don't do  
> the
> @@ -4337,9 +4337,9 @@
>                  EEE = Use->use_end(); III != EEE; ++III) {
>             SDNode *UseUse = *III;
>             if (!((UseUse->getOpcode() == ISD::LOAD &&
> -                   cast<LoadSDNode>(UseUse)->getBasePtr().Val ==  
> Use) ||
> +                   cast<LoadSDNode>(UseUse)->getBasePtr().getNode()  
> == Use) ||
>                   (UseUse->getOpcode() == ISD::STORE &&
> -                   cast<StoreSDNode>(UseUse)->getBasePtr().Val ==  
> Use)))
> +                   cast<StoreSDNode>(UseUse)- 
> >getBasePtr().getNode() == Use)))
>               RealUse = true;
>           }
>
> @@ -4360,7 +4360,7 @@
>         ++PostIndexedNodes;
>         ++NodesCombined;
>         DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
> -        DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
> +        DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
>         DOUT << '\n';
>         WorkListRemover DeadNodes(*this);
>         if (isLoad) {
> @@ -4463,7 +4463,7 @@
>         // Now we replace use of chain2 with chain1.  This makes the  
> second load
>         // isomorphic to the one we are deleting, and thus makes  
> this load live.
>         DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
> -        DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG));
> +        DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG));
>         DOUT << "\n";
>         WorkListRemover DeadNodes(*this);
>         DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain,  
> &DeadNodes);
> @@ -4479,7 +4479,7 @@
>       if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
>         SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0));
>         DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
> -        DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG));
> +        DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG));
>         DOUT << " and 2 other values\n";
>         WorkListRemover DeadNodes(*this);
>         DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef,  
> &DeadNodes);
> @@ -4500,7 +4500,7 @@
>   // TODO: Handle TRUNCSTORE/LOADEXT
>   if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
>       !LD->isVolatile()) {
> -    if (ISD::isNON_TRUNCStore(Chain.Val)) {
> +    if (ISD::isNON_TRUNCStore(Chain.getNode())) {
>       StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
>       if (PrevST->getBasePtr() == Ptr &&
>           PrevST->getValue().getValueType() == N->getValueType(0))
> @@ -4684,8 +4684,8 @@
>       GetDemandedBits(Value,
>                  APInt::getLowBitsSet(Value.getValueSizeInBits(),
>                                       ST- 
> >getMemoryVT().getSizeInBits()));
> -    AddToWorkList(Value.Val);
> -    if (Shorter.Val)
> +    AddToWorkList(Value.getNode());
> +    if (Shorter.getNode())
>       return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(),
>                                ST->getSrcValueOffset(), ST- 
> >getMemoryVT(),
>                                ST->isVolatile(), ST->getAlignment());
> @@ -4715,7 +4715,7 @@
>   // If this is an FP_ROUND or TRUNC followed by a store, fold this  
> into a
>   // truncating store.  We can do this even if this is already a  
> truncstore.
>   if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() ==  
> ISD::TRUNCATE)
> -      && Value.Val->hasOneUse() && ST->isUnindexed() &&
> +      && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
>       TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
>                             ST->getMemoryVT())) {
>     return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST- 
> >getSrcValue(),
> @@ -4735,7 +4735,7 @@
>   // vector with the inserted element.
>   if (InVec.getOpcode() == ISD::BUILD_VECTOR &&  
> isa<ConstantSDNode>(EltNo)) {
>     unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
> -    SmallVector<SDValue, 8> Ops(InVec.Val->op_begin(), InVec.Val- 
> >op_end());
> +    SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),  
> InVec.getNode()->op_end());
>     if (Elt < Ops.size())
>       Ops[Elt] = InVal;
>     return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
> @@ -4773,11 +4773,11 @@
>     }
>
>     LoadSDNode *LN0 = NULL;
> -    if (ISD::isNormalLoad(InVec.Val))
> +    if (ISD::isNormalLoad(InVec.getNode()))
>       LN0 = cast<LoadSDNode>(InVec);
>     else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
>              InVec.getOperand(0).getValueType() == EVT &&
> -             ISD::isNormalLoad(InVec.getOperand(0).Val)) {
> +             ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
>       LN0 = cast<LoadSDNode>(InVec.getOperand(0));
>     } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) {
>       // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
> @@ -4789,7 +4789,7 @@
>       InVec = (Idx < NumElems) ? InVec.getOperand(0) :  
> InVec.getOperand(1);
>       if (InVec.getOpcode() == ISD::BIT_CONVERT)
>         InVec = InVec.getOperand(0);
> -      if (ISD::isNormalLoad(InVec.Val)) {
> +      if (ISD::isNormalLoad(InVec.getNode())) {
>         LN0 = cast<LoadSDNode>(InVec);
>         Elt = (Idx < NumElems) ? Idx : Idx - NumElems;
>       }
> @@ -4859,9 +4859,9 @@
>     if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
>       continue;
>
> -    if (VecIn1.Val == 0) {
> +    if (VecIn1.getNode() == 0) {
>       VecIn1 = ExtractedFromVec;
> -    } else if (VecIn2.Val == 0) {
> +    } else if (VecIn2.getNode() == 0) {
>       VecIn2 = ExtractedFromVec;
>     } else {
>       // Too many inputs.
> @@ -4871,7 +4871,7 @@
>   }
>
>   // If everything is good, we can make a shuffle operation.
> -  if (VecIn1.Val) {
> +  if (VecIn1.getNode()) {
>     SmallVector<SDValue, 8> BuildVecIndices;
>     for (unsigned i = 0; i != NumInScalars; ++i) {
>       if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
> @@ -4898,7 +4898,7 @@
>     // Return the new VECTOR_SHUFFLE node.
>     SDValue Ops[5];
>     Ops[0] = VecIn1;
> -    if (VecIn2.Val) {
> +    if (VecIn2.getNode()) {
>       Ops[1] = VecIn2;
>     } else {
>       // Use an undef build_vector as input for the second operand.
> @@ -4907,7 +4907,7 @@
>                                                EltType));
>       Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
>                            &UnOps[0], UnOps.size());
> -      AddToWorkList(Ops[1].Val);
> +      AddToWorkList(Ops[1].getNode());
>     }
>     Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
>                          &BuildVecIndices[0], BuildVecIndices.size());
> @@ -4989,7 +4989,7 @@
>   // If it is a splat, check if the argument vector is a  
> build_vector with
>   // all scalar elements the same.
>   if (isSplat) {
> -    SDNode *V = N0.Val;
> +    SDNode *V = N0.getNode();
>
>     // If this is a bit convert that changes the element type of the  
> vector but
>     // not the number of vector elements, look through it.  Be  
> careful not to
> @@ -4998,7 +4998,7 @@
>       SDValue ConvInput = V->getOperand(0);
>       if (ConvInput.getValueType().isVector() &&
>           ConvInput.getValueType().getVectorNumElements() == NumElts)
> -        V = ConvInput.Val;
> +        V = ConvInput.getNode();
>     }
>
>     if (V->getOpcode() == ISD::BUILD_VECTOR) {
> @@ -5013,7 +5013,7 @@
>           }
>         }
>         // Splat of <u, u, u, u>, return <u, u, u, u>
> -        if (!Base.Val)
> +        if (!Base.getNode())
>           return N0;
>         for (unsigned i = 0; i != NumElems; ++i) {
>           if (V->getOperand(i) != Base) {
> @@ -5047,7 +5047,7 @@
>     }
>     ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
>                            &MappedOps[0], MappedOps.size());
> -    AddToWorkList(ShufMask.Val);
> +    AddToWorkList(ShufMask.getNode());
>     return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
>                        N0,
>                        DAG.getNode(ISD::UNDEF, N->getValueType(0)),
> @@ -5093,7 +5093,7 @@
>       std::vector<SDValue> Ops;
>       LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
>       Ops.push_back(LHS);
> -      AddToWorkList(LHS.Val);
> +      AddToWorkList(LHS.getNode());
>       std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT));
>       Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
>                                 &ZeroOps[0], ZeroOps.size()));
> @@ -5123,7 +5123,7 @@
>   SDValue LHS = N->getOperand(0);
>   SDValue RHS = N->getOperand(1);
>   SDValue Shuffle = XformToShuffleWithZero(N);
> -  if (Shuffle.Val) return Shuffle;
> +  if (Shuffle.getNode()) return Shuffle;
>
>   // If the LHS and RHS are BUILD_VECTOR nodes, see if we can  
> constant fold
>   // this operation.
> @@ -5145,13 +5145,13 @@
>       if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV  
> ||
>           N->getOpcode() == ISD::FDIV) {
>         if ((RHSOp.getOpcode() == ISD::Constant &&
> -             cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
> +             cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
>             (RHSOp.getOpcode() == ISD::ConstantFP &&
> -             cast<ConstantFPSDNode>(RHSOp.Val)- 
> >getValueAPF().isZero()))
> +             cast<ConstantFPSDNode>(RHSOp.getNode())- 
> >getValueAPF().isZero()))
>           break;
>       }
>       Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp,  
> RHSOp));
> -      AddToWorkList(Ops.back().Val);
> +      AddToWorkList(Ops.back().getNode());
>       assert((Ops.back().getOpcode() == ISD::UNDEF ||
>               Ops.back().getOpcode() == ISD::Constant ||
>               Ops.back().getOpcode() == ISD::ConstantFP) &&
> @@ -5175,14 +5175,14 @@
>   // If we got a simplified select_cc node back from  
> SimplifySelectCC, then
>   // break it down into a new SETCC node, and a new SELECT node, and  
> then return
>   // the SELECT node, since we were called with a SELECT node.
> -  if (SCC.Val) {
> +  if (SCC.getNode()) {
>     // Check to see if we got a select_cc back (to turn into setcc/ 
> select).
>     // Otherwise, just return whatever node we got back, like fabs.
>     if (SCC.getOpcode() == ISD::SELECT_CC) {
>       SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
>                                     SCC.getOperand(0),  
> SCC.getOperand(1),
>                                     SCC.getOperand(4));
> -      AddToWorkList(SETCC.Val);
> +      AddToWorkList(SETCC.getNode());
>       return DAG.getNode(ISD::SELECT, SCC.getValueType(),  
> SCC.getOperand(2),
>                          SCC.getOperand(3), SETCC);
>     }
> @@ -5226,8 +5226,8 @@
>         if (TheSelect->getOpcode() == ISD::SELECT) {
>           // Check that the condition doesn't reach either load.  If  
> so, folding
>           // this will induce a cycle into the DAG.
> -          if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) &&
> -              !RLD->isPredecessorOf(TheSelect->getOperand(0).Val)) {
> +          if (!LLD->isPredecessorOf(TheSelect- 
> >getOperand(0).getNode()) &&
> +              !RLD->isPredecessorOf(TheSelect- 
> >getOperand(0).getNode())) {
>             Addr = DAG.getNode(ISD::SELECT, LLD- 
> >getBasePtr().getValueType(),
>                                TheSelect->getOperand(0), LLD- 
> >getBasePtr(),
>                                RLD->getBasePtr());
> @@ -5235,10 +5235,10 @@
>         } else {
>           // Check that the condition doesn't reach either load.  If  
> so, folding
>           // this will induce a cycle into the DAG.
> -          if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) &&
> -              !RLD->isPredecessorOf(TheSelect->getOperand(0).Val) &&
> -              !LLD->isPredecessorOf(TheSelect->getOperand(1).Val) &&
> -              !RLD->isPredecessorOf(TheSelect->getOperand(1).Val)) {
> +          if (!LLD->isPredecessorOf(TheSelect- 
> >getOperand(0).getNode()) &&
> +              !RLD->isPredecessorOf(TheSelect- 
> >getOperand(0).getNode()) &&
> +              !LLD->isPredecessorOf(TheSelect- 
> >getOperand(1).getNode()) &&
> +              !RLD->isPredecessorOf(TheSelect- 
> >getOperand(1).getNode())) {
>             Addr = DAG.getNode(ISD::SELECT_CC, LLD- 
> >getBasePtr().getValueType(),
>                              TheSelect->getOperand(0),
>                              TheSelect->getOperand(1),
> @@ -5247,7 +5247,7 @@
>           }
>         }
>
> -        if (Addr.Val) {
> +        if (Addr.getNode()) {
>           SDValue Load;
>           if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
>             Load = DAG.getLoad(TheSelect->getValueType(0), LLD- 
> >getChain(),
> @@ -5269,8 +5269,8 @@
>
>           // Users of the old loads now use the new load's chain.   
> We know the
>           // old-load value is dead now.
> -          CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
> -          CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
> +          CombineTo(LHS.getNode(), Load.getValue(0),  
> Load.getValue(1));
> +          CombineTo(RHS.getNode(), Load.getValue(0),  
> Load.getValue(1));
>           return true;
>         }
>       }
> @@ -5285,14 +5285,14 @@
>                                       ISD::CondCode CC, bool  
> NotExtCompare) {
>
>   MVT VT = N2.getValueType();
> -  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
> -  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
> -  ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
> +  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
> +  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
> +  ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
>
>   // Determine if the condition we're dealing with is constant
>   SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1,  
> CC, false);
> -  if (SCC.Val) AddToWorkList(SCC.Val);
> -  ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
> +  if (SCC.getNode()) AddToWorkList(SCC.getNode());
> +  ConstantSDNode *SCCC =  
> dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
>
>   // fold select_cc true, x, y -> x
>   if (SCCC && !SCCC->isNullValue())
> @@ -5336,20 +5336,20 @@
>         ShCtV = XType.getSizeInBits()-ShCtV-1;
>         SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
>         SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
> -        AddToWorkList(Shift.Val);
> +        AddToWorkList(Shift.getNode());
>         if (XType.bitsGT(AType)) {
>           Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
> -          AddToWorkList(Shift.Val);
> +          AddToWorkList(Shift.getNode());
>         }
>         return DAG.getNode(ISD::AND, AType, Shift, N2);
>       }
>       SDValue Shift = DAG.getNode(ISD::SRA, XType, N0,
>                                      
> DAG.getConstant(XType.getSizeInBits()-1,
>                                                      
> TLI.getShiftAmountTy()));
> -      AddToWorkList(Shift.Val);
> +      AddToWorkList(Shift.getNode());
>       if (XType.bitsGT(AType)) {
>         Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
> -        AddToWorkList(Shift.Val);
> +        AddToWorkList(Shift.getNode());
>       }
>       return DAG.getNode(ISD::AND, AType, Shift, N2);
>     }
> @@ -5379,8 +5379,8 @@
>       SCC  = DAG.getSetCC(MVT::i1, N0, N1, CC);
>       Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
>     }
> -    AddToWorkList(SCC.Val);
> -    AddToWorkList(Temp.Val);
> +    AddToWorkList(SCC.getNode());
> +    AddToWorkList(Temp.getNode());
>
>     if (N2C->getAPIntValue() == 1)
>       return Temp;
> @@ -5442,8 +5442,8 @@
>                                    
> DAG.getConstant(XType.getSizeInBits()-1,
>                                                    
> TLI.getShiftAmountTy()));
>     SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
> -    AddToWorkList(Shift.Val);
> -    AddToWorkList(Add.Val);
> +    AddToWorkList(Shift.getNode());
> +    AddToWorkList(Add.getNode());
>     return DAG.getNode(ISD::XOR, XType, Add, Shift);
>   }
>   // Check to see if this is an integer abs. select_cc setgt X, -1,  
> X, -X ->
> @@ -5457,8 +5457,8 @@
>                                        
> DAG.getConstant(XType.getSizeInBits()-1,
>                                                        
> TLI.getShiftAmountTy()));
>         SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
> -        AddToWorkList(Shift.Val);
> -        AddToWorkList(Add.Val);
> +        AddToWorkList(Shift.getNode());
> +        AddToWorkList(Add.getNode());
>         return DAG.getNode(ISD::XOR, XType, Add, Shift);
>       }
>     }
> @@ -5612,8 +5612,8 @@
>     Chains.pop_back();
>
>      // Don't bother if we've been before.
> -    if (Visited.find(Chain.Val) != Visited.end()) continue;
> -    Visited.insert(Chain.Val);
> +    if (Visited.find(Chain.getNode()) != Visited.end()) continue;
> +    Visited.insert(Chain.getNode());
>
>     switch (Chain.getOpcode()) {
>     case ISD::EntryToken:
> @@ -5627,7 +5627,7 @@
>       int64_t OpSize;
>       const Value *OpSrcValue;
>       int OpSrcValueOffset;
> -      bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
> +      bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
>                                     OpSrcValue, OpSrcValueOffset);
>
>       // If chain is alias then stop here.
> @@ -5639,7 +5639,7 @@
>         // Look further up the chain.
>         Chains.push_back(Chain.getOperand(0));
>         // Clean up old chain.
> -        AddToWorkList(Chain.Val);
> +        AddToWorkList(Chain.getNode());
>       }
>       break;
>     }
> @@ -5652,7 +5652,7 @@
>       for (unsigned n = Chain.getNumOperands(); n;)
>         Chains.push_back(Chain.getOperand(--n));
>       // Eliminate the token factor if we can.
> -      AddToWorkList(Chain.Val);
> +      AddToWorkList(Chain.getNode());
>       break;
>
>     default:
> @@ -5684,7 +5684,7 @@
>                                    &Aliases[0], Aliases.size());
>
>   // Make sure the old chain gets cleaned up.
> -  if (NewChain != OldChain) AddToWorkList(OldChain.Val);
> +  if (NewChain != OldChain) AddToWorkList(OldChain.getNode());
>
>   return NewChain;
> }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -260,7 +260,7 @@
>     break;
>   }
>   }
> -  return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
> +  return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
> }
>
> SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
> @@ -350,7 +350,7 @@
>
>   assert(Node->getOperand(0).getValueType() == MVT::Other &&
>          "Node doesn't have a token chain argument!");
> -  return FindCallStartFromCallEnd(Node->getOperand(0).Val);
> +  return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
> }
>
> /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N,  
> looking to
> @@ -387,7 +387,7 @@
>   bool OperandsLeadToDest = false;
>   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
>     OperandsLeadToDest |=     // If an operand leads to Dest, so do  
> we.
> -      LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest,  
> NodesLeadingTo);
> +      LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(),  
> Dest, NodesLeadingTo);
>
>   if (OperandsLeadToDest) {
>     NodesLeadingTo.insert(N);
> @@ -667,7 +667,7 @@
>   MVT VT = Op.getValueType();
>   assert(isTypeLegal(VT) &&
>          "Caller should expand or promote operands that are not  
> legal!");
> -  assert(Op.Val->getNumValues() == 1 &&
> +  assert(Op.getNode()->getNumValues() == 1 &&
>          "Can't unroll a vector with multiple results!");
>   unsigned NE = VT.getVectorNumElements();
>   MVT EltVT = VT.getVectorElementType();
> @@ -733,7 +733,7 @@
>   MVT PtrVT = TLI.getPointerTy();
>   SDValue StackPtr = DAG.CreateStackTemporary(VT);
>
> -  int SPFI = cast<FrameIndexSDNode>(StackPtr.Val)->getIndex();
> +  int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
>
>   // Store the vector.
>   SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
> @@ -764,7 +764,7 @@
>
>   assert(isTypeLegal(Op.getValueType()) &&
>          "Caller should expand or promote operands that are not  
> legal!");
> -  SDNode *Node = Op.Val;
> +  SDNode *Node = Op.getNode();
>
>   // If this operation defines any values that cannot be represented  
> in a
>   // register on this target, make sure to expand or promote them.
> @@ -839,7 +839,7 @@
>     default: assert(0 && "This action is not supported yet!");
>     case TargetLowering::Custom:
>       Tmp1 = TLI.LowerOperation(Op, DAG);
> -      if (Tmp1.Val) Result = Tmp1;
> +      if (Tmp1.getNode()) Result = Tmp1;
>       // FALLTHROUGH if the target doesn't want to lower this op  
> after all.
>     case TargetLowering::Legal:
>       break;
> @@ -850,7 +850,7 @@
>     // The only option for these nodes is to custom lower them.  If  
> the target
>     // does not custom lower them, then return zero.
>     Tmp1 = TLI.LowerOperation(Op, DAG);
> -    if (Tmp1.Val)
> +    if (Tmp1.getNode())
>       Result = Tmp1;
>     else
>       Result = DAG.getConstant(0, TLI.getPointerTy());
> @@ -861,7 +861,7 @@
>     default: assert(0 && "This action is not supported yet!");
>     case TargetLowering::Custom:
>       Result = TLI.LowerOperation(Op, DAG);
> -      if (Result.Val) break;
> +      if (Result.getNode()) break;
>       // Fall Thru
>     case TargetLowering::Legal:
>       Result = DAG.getConstant(0, VT);
> @@ -881,7 +881,7 @@
>       break;
>     case TargetLowering::Custom:
>       Result = TLI.LowerOperation(Op, DAG);
> -      if (Result.Val) break;
> +      if (Result.getNode()) break;
>       // Fall Thru
>     case TargetLowering::Legal: {
>       SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
> @@ -890,9 +890,9 @@
>     }
>     }
>     }
> -    if (Result.Val->getNumValues() == 1) break;
> +    if (Result.getNode()->getNumValues() == 1) break;
>
> -    assert(Result.Val->getNumValues() == 2 &&
> +    assert(Result.getNode()->getNumValues() == 2 &&
>            "Cannot return more than two values!");
>
>     // Since we produced two values, make sure to remember that we
> @@ -915,7 +915,7 @@
>       break;
>     case TargetLowering::Custom:
>       Result = TLI.LowerOperation(Op, DAG);
> -      if (Result.Val) break;
> +      if (Result.getNode()) break;
>       // Fall Thru
>     case TargetLowering::Legal: {
>       SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
> @@ -924,9 +924,9 @@
>     }
>     }
>     }
> -    if (Result.Val->getNumValues() == 1) break;
> +    if (Result.getNode()->getNumValues() == 1) break;
>
> -    assert(Result.Val->getNumValues() == 2 &&
> +    assert(Result.getNode()->getNumValues() == 2 &&
>            "Cannot return more than two values!");
>
>     // Since we produced two values, make sure to remember that we
> @@ -943,7 +943,7 @@
>     default: assert(0 && "This action is not supported at all!");
>     case TargetLowering::Custom:
>       Result = TLI.LowerOperation(Op, DAG);
> -      if (Result.Val) break;
> +      if (Result.getNode()) break;
>       // Fall Thru
>     case TargetLowering::Legal:
>       // Target does not know, how to lower this, lower to noop
> @@ -1012,13 +1012,13 @@
>     if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
>         TargetLowering::Custom) {
>       Tmp3 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp3.Val) Result = Tmp3;
> +      if (Tmp3.getNode()) Result = Tmp3;
>     }
>
> -    if (Result.Val->getNumValues() == 1) break;
> +    if (Result.getNode()->getNumValues() == 1) break;
>
>     // Must have return value and chain result.
> -    assert(Result.Val->getNumValues() == 2 &&
> +    assert(Result.getNode()->getNumValues() == 2 &&
>            "Cannot return more than two values!");
>
>     // Since loads produce two values, make sure to remember that we
> @@ -1261,7 +1261,7 @@
>       Result = TLI.LowerOperation(Result, DAG);
>       break;
>     case TargetLowering::Expand:
> -      Result = SDValue(TLI.ReplaceNodeResults(Op.Val, DAG),0);
> +      Result = SDValue(TLI.ReplaceNodeResults(Op.getNode(), DAG),0);
>       break;
>     case TargetLowering::Legal:
>       break;
> @@ -1280,7 +1280,7 @@
>
>     if (opAction == TargetLowering::Custom) {
>       Tmp1 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp1.Val)
> +      if (Tmp1.getNode())
>         Result = Tmp1;
>     }
>     break;
> @@ -1298,7 +1298,7 @@
>       break;
>     case TargetLowering::Custom:
>       Tmp3 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp3.Val) {
> +      if (Tmp3.getNode()) {
>         Result = Tmp3;
>         break;
>       }
> @@ -1344,27 +1344,27 @@
>   case ISD::CALL:
>     // The only option for this is to custom lower it.
>     Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
> -    assert(Tmp3.Val && "Target didn't custom lower this node!");
> +    assert(Tmp3.getNode() && "Target didn't custom lower this  
> node!");
>     // A call within a calling sequence must be legalized to something
>     // other than the normal CALLSEQ_END.  Violating this gets  
> Legalize
>     // into an infinite loop.
>     assert ((!IsLegalizingCall ||
>              Node->getOpcode() != ISD::CALL ||
> -             Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) &&
> +             Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
>             "Nested CALLSEQ_START..CALLSEQ_END not supported.");
>
>     // The number of incoming and outgoing values should match;  
> unless the final
>     // outgoing value is a flag.
> -    assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
> -            (Tmp3.Val->getNumValues() == Result.Val->getNumValues()  
> + 1 &&
> -             Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
> +    assert((Tmp3.getNode()->getNumValues() == Result.getNode()- 
> >getNumValues() ||
> +            (Tmp3.getNode()->getNumValues() == Result.getNode()- 
> >getNumValues() + 1 &&
> +             Tmp3.getNode()->getValueType(Tmp3.getNode()- 
> >getNumValues() - 1) ==
>                MVT::Flag)) &&
>            "Lowering call/formal_arguments produced unexpected #  
> results!");
>
>     // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values,  
> make sure to
>     // remember that we legalized all of them, so it doesn't get  
> relegalized.
> -    for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
> -      if (Tmp3.Val->getValueType(i) == MVT::Flag)
> +    for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i !=  
> e; ++i) {
> +      if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
>         continue;
>       Tmp1 = LegalizeOp(Tmp3.getValue(i));
>       if (Op.getResNo() == i)
> @@ -1394,13 +1394,13 @@
>     default: assert(0 && "This action is not supported yet!");
>     case TargetLowering::Custom:
>       Tmp3 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp3.Val) {
> +      if (Tmp3.getNode()) {
>         Result = Tmp3;
>         break;
>       }
>       // FALLTHROUGH
>     case TargetLowering::Expand:
> -      Result = ExpandBUILD_VECTOR(Result.Val);
> +      Result = ExpandBUILD_VECTOR(Result.getNode());
>       break;
>     }
>     break;
> @@ -1425,7 +1425,7 @@
>       break;
>     case TargetLowering::Custom:
>       Tmp4 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp4.Val) {
> +      if (Tmp4.getNode()) {
>         Result = Tmp4;
>         break;
>       }
> @@ -1485,7 +1485,7 @@
>       break;
>     case TargetLowering::Custom:
>       Tmp3 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp3.Val) {
> +      if (Tmp3.getNode()) {
>         Result = Tmp3;
>         break;
>       }
> @@ -1509,7 +1509,7 @@
>       break;
>     case TargetLowering::Custom:
>       Tmp3 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp3.Val) {
> +      if (Tmp3.getNode()) {
>         Result = Tmp3;
>         break;
>       }
> @@ -1550,7 +1550,7 @@
>
>       // Convert the shuffle mask to the right # elements.
>       Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
> -      assert(Tmp3.Val && "Shuffle not legal?");
> +      assert(Tmp3.getNode() && "Shuffle not legal?");
>       Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2,  
> Tmp3);
>       Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
>       break;
> @@ -1580,7 +1580,7 @@
>     // are inserted *before* the CALLSEQ_START.
>     {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
>     for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
> -      LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
> +      LegalizeAllNodesNotLeadingTo(CallEnd- 
> >getOperand(i).getNode(), Node,
>                                    NodesLeadingTo);
>     }
>
> @@ -1624,7 +1624,7 @@
>   case ISD::CALLSEQ_END:
>     // If the CALLSEQ_START node hasn't been legalized first,  
> legalize it.  This
>     // will cause this node to be legalized as well as handling  
> libcalls right.
> -    if (LastCALLSEQ_END.Val != Node) {
> +    if (LastCALLSEQ_END.getNode() != Node) {
>       LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
>       DenseMap<SDValue, SDValue>::iterator I =  
> LegalizedNodes.find(Op);
>       assert(I != LegalizedNodes.end() &&
> @@ -1708,7 +1708,7 @@
>     }
>     case TargetLowering::Custom:
>       Tmp3 = TLI.LowerOperation(Tmp1, DAG);
> -      if (Tmp3.Val) {
> +      if (Tmp3.getNode()) {
>         Tmp1 = LegalizeOp(Tmp3);
>         Tmp2 = LegalizeOp(Tmp3.getValue(1));
>       }
> @@ -1797,7 +1797,7 @@
>     case TargetLowering::Legal: break;
>     case TargetLowering::Custom:
>       Tmp1 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp1.Val) Result = Tmp1;
> +      if (Tmp1.getNode()) Result = Tmp1;
>       break;
>     case TargetLowering::Expand: {
>       SDValue Chain = Result.getOperand(0);
> @@ -1866,7 +1866,7 @@
>     case TargetLowering::Legal: break;
>     case TargetLowering::Custom:
>       Tmp1 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp1.Val) Result = Tmp1;
> +      if (Tmp1.getNode()) Result = Tmp1;
>       break;
>     case TargetLowering::Expand:
>       // Expand brcond's setcc into its constituent parts and create  
> a BR_CC
> @@ -1899,7 +1899,7 @@
>     // If we didn't get both a LHS and RHS back from  
> LegalizeSetCCOperands,
>     // the LHS is a legal SETCC itself.  In this case, we need to  
> compare
>     // the result against zero to select between true and false  
> values.
> -    if (Tmp3.Val == 0) {
> +    if (Tmp3.getNode() == 0) {
>       Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
>       Tmp4 = DAG.getCondCode(ISD::SETNE);
>     }
> @@ -1912,7 +1912,7 @@
>     case TargetLowering::Legal: break;
>     case TargetLowering::Custom:
>       Tmp4 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp4.Val) Result = Tmp4;
> +      if (Tmp4.getNode()) Result = Tmp4;
>       break;
>     }
>     break;
> @@ -1937,7 +1937,7 @@
>           unsigned ABIAlignment = TLI.getTargetData()->
>             getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
>           if (LD->getAlignment() < ABIAlignment){
> -            Result =  
> ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
> +            Result =  
> ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
>                                          TLI);
>             Tmp3 = Result.getOperand(0);
>             Tmp4 = Result.getOperand(1);
> @@ -1948,7 +1948,7 @@
>         break;
>       case TargetLowering::Custom:
>         Tmp1 = TLI.LowerOperation(Tmp3, DAG);
> -        if (Tmp1.Val) {
> +        if (Tmp1.getNode()) {
>           Tmp3 = LegalizeOp(Tmp1);
>           Tmp4 = LegalizeOp(Tmp1.getValue(1));
>         }
> @@ -2105,7 +2105,7 @@
>
>           if (isCustom) {
>             Tmp3 = TLI.LowerOperation(Result, DAG);
> -            if (Tmp3.Val) {
> +            if (Tmp3.getNode()) {
>               Tmp1 = LegalizeOp(Tmp3);
>               Tmp2 = LegalizeOp(Tmp3.getValue(1));
>             }
> @@ -2116,7 +2116,7 @@
>               unsigned ABIAlignment = TLI.getTargetData()->
>                 getABITypeAlignment(LD- 
> >getMemoryVT().getTypeForMVT());
>               if (LD->getAlignment() < ABIAlignment){
> -                Result =  
> ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
> +                Result =  
> ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
>                                              TLI);
>                 Tmp1 = Result.getOperand(0);
>                 Tmp2 = Result.getOperand(1);
> @@ -2244,13 +2244,13 @@
>           if (TLI.isBigEndian())
>             std::swap(Lo, Hi);
>
> -          if (Hi.Val)
> +          if (Hi.getNode())
>             Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo,  
> Tmp3, Hi,Tmp3);
>           else
>             Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo,  
> Tmp3);
>           Result = LegalizeOp(Result);
>         } else {
> -          SDNode *InVal = Tmp2.Val;
> +          SDNode *InVal = Tmp2.getNode();
>           int InIx = Tmp2.getResNo();
>           unsigned NumElems = InVal- 
> >getValueType(InIx).getVectorNumElements();
>           MVT EVT = InVal->getValueType(InIx).getVectorElementType();
> @@ -2310,7 +2310,7 @@
>           ExpandOp(Node->getOperand(i), Lo, Hi);
>           NewValues.push_back(Lo);
>           NewValues.push_back(Node->getOperand(i+1));
> -          if (Hi.Val) {
> +          if (Hi.getNode()) {
>             NewValues.push_back(Hi);
>             NewValues.push_back(Node->getOperand(i+1));
>           }
> @@ -2335,7 +2335,7 @@
>       case TargetLowering::Legal: break;
>       case TargetLowering::Custom:
>         Tmp1 = TLI.LowerOperation(Result, DAG);
> -        if (Tmp1.Val) Result = Tmp1;
> +        if (Tmp1.getNode()) Result = Tmp1;
>         break;
>       }
>     }
> @@ -2411,13 +2411,13 @@
>             unsigned ABIAlignment = TLI.getTargetData()->
>               getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
>             if (ST->getAlignment() < ABIAlignment)
> -              Result =  
> ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
> +              Result =  
> ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
>                                             TLI);
>           }
>           break;
>         case TargetLowering::Custom:
>           Tmp1 = TLI.LowerOperation(Result, DAG);
> -          if (Tmp1.Val) Result = Tmp1;
> +          if (Tmp1.getNode()) Result = Tmp1;
>           break;
>         case TargetLowering::Promote:
>           assert(VT.isVector() && "Unknown legal promote case!");
> @@ -2446,7 +2446,7 @@
>         // the product of the element size in bytes, and the number  
> of elements
>         // in the high half of the vector.
>         if (ST->getValue().getValueType().isVector()) {
> -          SDNode *InVal = ST->getValue().Val;
> +          SDNode *InVal = ST->getValue().getNode();
>           int InIx = ST->getValue().getResNo();
>           MVT InVT = InVal->getValueType(InIx);
>           unsigned NumElems = InVT.getVectorNumElements();
> @@ -2473,12 +2473,12 @@
>             break;
>           } else {
>             SplitVectorOp(ST->getValue(), Lo, Hi);
> -            IncrementSize = Lo.Val- 
> >getValueType(0).getVectorNumElements() *
> +            IncrementSize = Lo.getNode()- 
> >getValueType(0).getVectorNumElements() *
>                             EVT.getSizeInBits()/8;
>           }
>         } else {
>           ExpandOp(ST->getValue(), Lo, Hi);
> -          IncrementSize = Hi.Val ?  
> Hi.getValueType().getSizeInBits()/8 : 0;
> +          IncrementSize = Hi.getNode() ?  
> Hi.getValueType().getSizeInBits()/8 : 0;
>
>           if (TLI.isBigEndian())
>             std::swap(Lo, Hi);
> @@ -2487,7 +2487,7 @@
>         Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
>                           SVOffset, isVolatile, Alignment);
>
> -        if (Hi.Val == NULL) {
> +        if (Hi.getNode() == NULL) {
>           // Must be int <-> float one-to-one expansion.
>           Result = Lo;
>           break;
> @@ -2598,7 +2598,7 @@
>             unsigned ABIAlignment = TLI.getTargetData()->
>               getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
>             if (ST->getAlignment() < ABIAlignment)
> -              Result =  
> ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
> +              Result =  
> ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
>                                             TLI);
>           }
>           break;
> @@ -2632,7 +2632,7 @@
>     case TargetLowering::Legal: break;
>     case TargetLowering::Custom:
>       Tmp3 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp3.Val) {
> +      if (Tmp3.getNode()) {
>         Tmp1 = LegalizeOp(Tmp3);
>         Tmp2 = LegalizeOp(Tmp3.getValue(1));
>       }
> @@ -2667,7 +2667,7 @@
>     case TargetLowering::Legal: break;
>     case TargetLowering::Custom:
>       Tmp1 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp1.Val) Result = Tmp1;
> +      if (Tmp1.getNode()) Result = Tmp1;
>       break;
>     case TargetLowering::Expand:
>       // Expand to CopyToReg if the target set
> @@ -2730,7 +2730,7 @@
>     case TargetLowering::Legal: break;
>     case TargetLowering::Custom: {
>       Tmp1 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp1.Val) Result = Tmp1;
> +      if (Tmp1.getNode()) Result = Tmp1;
>       break;
>     }
>     case TargetLowering::Expand:
> @@ -2784,7 +2784,7 @@
>     // If we didn't get both a LHS and RHS back from  
> LegalizeSetCCOperands,
>     // the LHS is a legal SETCC itself.  In this case, we need to  
> compare
>     // the result against zero to select between true and false  
> values.
> -    if (Tmp2.Val == 0) {
> +    if (Tmp2.getNode() == 0) {
>       Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
>       CC = DAG.getCondCode(ISD::SETNE);
>     }
> @@ -2796,7 +2796,7 @@
>     case TargetLowering::Legal: break;
>     case TargetLowering::Custom:
>       Tmp1 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp1.Val) Result = Tmp1;
> +      if (Tmp1.getNode()) Result = Tmp1;
>       break;
>     }
>     break;
> @@ -2810,7 +2810,7 @@
>     // If we had to Expand the SetCC operands into a SELECT node,  
> then it may
>     // not always be possible to return a true LHS & RHS.  In this  
> case, just
>     // return the value we legalized, returned in the LHS
> -    if (Tmp2.Val == 0) {
> +    if (Tmp2.getNode() == 0) {
>       Result = Tmp1;
>       break;
>     }
> @@ -2824,7 +2824,7 @@
>       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
>       if (isCustom) {
>         Tmp4 = TLI.LowerOperation(Result, DAG);
> -        if (Tmp4.Val) Result = Tmp4;
> +        if (Tmp4.getNode()) Result = Tmp4;
>       }
>       break;
>     case TargetLowering::Promote: {
> @@ -2882,7 +2882,7 @@
>     case TargetLowering::Legal: break;
>     case TargetLowering::Custom:
>       Tmp1 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp1.Val) Result = Tmp1;
> +      if (Tmp1.getNode()) Result = Tmp1;
>       break;
>     }
>     break;
> @@ -2906,7 +2906,7 @@
>     case TargetLowering::Legal: break;
>     case TargetLowering::Custom:
>       Tmp1 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp1.Val) {
> +      if (Tmp1.getNode()) {
>         SDValue Tmp2, RetVal(0, 0);
>         for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
>           Tmp2 = LegalizeOp(Tmp1.getValue(i));
> @@ -2914,7 +2914,7 @@
>           if (i == Op.getResNo())
>             RetVal = Tmp2;
>         }
> -        assert(RetVal.Val && "Illegal result number");
> +        assert(RetVal.getNode() && "Illegal result number");
>         return RetVal;
>       }
>       break;
> @@ -2974,7 +2974,7 @@
>     case TargetLowering::Legal: break;
>     case TargetLowering::Custom:
>       Tmp1 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp1.Val) {
> +      if (Tmp1.getNode()) {
>         Result = Tmp1;
>         break;
>       }
> @@ -3004,28 +3004,28 @@
>           OpToUse = ISD::UMUL_LOHI;
>         }
>         if (OpToUse) {
> -          Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1,  
> Tmp2).Val, 0);
> +          Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1,  
> Tmp2).getNode(), 0);
>           break;
>         }
>       }
>       if (Node->getOpcode() == ISD::MULHS &&
>           TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
> -        Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1,  
> Tmp2).Val, 1);
> +        Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1,  
> Tmp2).getNode(), 1);
>         break;
>       }
>       if (Node->getOpcode() == ISD::MULHU &&
>           TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
> -        Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1,  
> Tmp2).Val, 1);
> +        Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1,  
> Tmp2).getNode(), 1);
>         break;
>       }
>       if (Node->getOpcode() == ISD::SDIV &&
>           TLI.isOperationLegal(ISD::SDIVREM, VT)) {
> -        Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1,  
> Tmp2).Val, 0);
> +        Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1,  
> Tmp2).getNode(), 0);
>         break;
>       }
>       if (Node->getOpcode() == ISD::UDIV &&
>           TLI.isOperationLegal(ISD::UDIVREM, VT)) {
> -        Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1,  
> Tmp2).Val, 0);
> +        Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1,  
> Tmp2).getNode(), 0);
>         break;
>       }
>
> @@ -3113,7 +3113,7 @@
>     default: assert(0 && "Operation not supported");
>     case TargetLowering::Custom:
>       Tmp1 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp1.Val) Result = Tmp1;
> +      if (Tmp1.getNode()) Result = Tmp1;
>       break;
>     case TargetLowering::Legal: break;
>     case TargetLowering::Expand: {
> @@ -3216,7 +3216,7 @@
>       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
>       if (isCustom) {
>         Tmp1 = TLI.LowerOperation(Result, DAG);
> -        if (Tmp1.Val) Result = Tmp1;
> +        if (Tmp1.getNode()) Result = Tmp1;
>       }
>       break;
>     case TargetLowering::Expand: {
> @@ -3228,12 +3228,12 @@
>       SDVTList VTs = DAG.getVTList(VT, VT);
>       if (Node->getOpcode() == ISD::SREM &&
>           TLI.isOperationLegal(ISD::SDIVREM, VT)) {
> -        Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1,  
> Tmp2).Val, 1);
> +        Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1,  
> Tmp2).getNode(), 1);
>         break;
>       }
>       if (Node->getOpcode() == ISD::UREM &&
>           TLI.isOperationLegal(ISD::UDIVREM, VT)) {
> -        Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1,  
> Tmp2).Val, 1);
> +        Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1,  
> Tmp2).getNode(), 1);
>         break;
>       }
>
> @@ -3288,7 +3288,7 @@
>
>       if (isCustom) {
>         Tmp2 = TLI.LowerOperation(Result, DAG);
> -        if (Tmp2.Val) {
> +        if (Tmp2.getNode()) {
>           Result = LegalizeOp(Tmp2);
>           Tmp1 = LegalizeOp(Tmp2.getValue(1));
>         }
> @@ -3332,7 +3332,7 @@
>                                       Node->getOperand(3), Node- 
> >getOperand(4));
>       if (isCustom) {
>         Tmp1 = TLI.LowerOperation(Result, DAG);
> -        if (Tmp1.Val) Result = Tmp1;
> +        if (Tmp1.getNode()) Result = Tmp1;
>       }
>       break;
>     case TargetLowering::Expand:
> @@ -3359,7 +3359,7 @@
>       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node- 
> >getOperand(2));
>       if (isCustom) {
>         Tmp1 = TLI.LowerOperation(Tmp1, DAG);
> -        if (Tmp1.Val) Result = Tmp1;
> +        if (Tmp1.getNode()) Result = Tmp1;
>       }
>       break;
>     case TargetLowering::Expand:
> @@ -3379,7 +3379,7 @@
>     case TargetLowering::Legal: break;
>     case TargetLowering::Custom:
>       Tmp1 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp1.Val) Result = Tmp1;
> +      if (Tmp1.getNode()) Result = Tmp1;
>       break;
>     }
>     break;
> @@ -3397,7 +3397,7 @@
>       break;
>     case TargetLowering::Custom:
>       Tmp1 = TLI.LowerOperation(Result, DAG);
> -      if (Tmp1.Val) Result = Tmp1;
> +      if (Tmp1.getNode()) Result = Tmp1;
>       break;
>     case TargetLowering::Promote:
>       assert(0 && "Do not know how to promote ROTL/ROTR");
> @@ -3444,7 +3444,7 @@
>       if (TLI.getOperationAction(Node->getOpcode(), Node- 
> >getValueType(0)) ==
>           TargetLowering::Custom) {
>         Tmp1 = TLI.LowerOperation(Result, DAG);
> -        if (Tmp1.Val) {
> +        if (Tmp1.getNode()) {
>           Result = Tmp1;
>         }
>       }
> @@ -3505,7 +3505,7 @@
>       Result = DAG.UpdateNodeOperands(Result, Tmp1);
>       if (isCustom) {
>         Tmp1 = TLI.LowerOperation(Result, DAG);
> -        if (Tmp1.Val) Result = Tmp1;
> +        if (Tmp1.getNode()) Result = Tmp1;
>       }
>       break;
>     case TargetLowering::Expand:
> @@ -3609,7 +3609,7 @@
>     } else if (Op.getOperand(0).getValueType().isVector()) {
>       // The input has to be a vector type, we have to either  
> scalarize it, pack
>       // it, or convert it based on whether the input vector type is  
> legal.
> -      SDNode *InVal = Node->getOperand(0).Val;
> +      SDNode *InVal = Node->getOperand(0).getNode();
>       int InIx = Node->getOperand(0).getResNo();
>       unsigned NumElems = InVal- 
> >getValueType(InIx).getVectorNumElements();
>       MVT EVT = InVal->getValueType(InIx).getVectorElementType();
> @@ -3690,7 +3690,7 @@
>         Result = DAG.UpdateNodeOperands(Result, Tmp1);
>         if (isCustom) {
>           Tmp1 = TLI.LowerOperation(Result, DAG);
> -          if (Tmp1.Val) Result = Tmp1;
> +          if (Tmp1.getNode()) Result = Tmp1;
>         }
>         break;
>       case TargetLowering::Promote:
> @@ -3832,7 +3832,7 @@
>       if (TLI.getOperationAction(Node->getOpcode(), Node- 
> >getValueType(0)) ==
>           TargetLowering::Custom) {
>         Tmp1 = TLI.LowerOperation(Result, DAG);
> -        if (Tmp1.Val) Result = Tmp1;
> +        if (Tmp1.getNode()) Result = Tmp1;
>       }
>       break;
>     case Promote:
> @@ -3904,7 +3904,7 @@
>     Result = DAG.UpdateNodeOperands(Result, Ops, 6);
>     // The only option for this node is to custom lower it.
>     Result = TLI.LowerOperation(Result, DAG);
> -    assert(Result.Val && "Should always custom lower!");
> +    assert(Result.getNode() && "Should always custom lower!");
>
>     // Since trampoline produces two values, make sure to remember  
> that we
>     // legalized both of them.
> @@ -3920,7 +3920,7 @@
>     default: assert(0 && "This action not supported for this op  
> yet!");
>     case TargetLowering::Custom:
>       Result = TLI.LowerOperation(Op, DAG);
> -      if (Result.Val) break;
> +      if (Result.getNode()) break;
>       // Fall Thru
>     case TargetLowering::Legal:
>       // If this operation is not supported, lower it to constant 1
> @@ -3939,7 +3939,7 @@
>       break;
>     case TargetLowering::Custom:
>       Result = TLI.LowerOperation(Op, DAG);
> -      if (Result.Val) break;
> +      if (Result.getNode()) break;
>       // Fall Thru
>     case TargetLowering::Expand:
>       // If this operation is not supported, lower it to 'abort()'  
> call
> @@ -3984,7 +3984,7 @@
>
>   SDValue Tmp1, Tmp2, Tmp3;
>   SDValue Result;
> -  SDNode *Node = Op.Val;
> +  SDNode *Node = Op.getNode();
>
>   DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
>   if (I != PromotedNodes.end()) return I->second;
> @@ -4461,7 +4461,7 @@
>     break;
>   }
>
> -  assert(Result.Val && "Didn't set a result!");
> +  assert(Result.getNode() && "Didn't set a result!");
>
>   // Make sure the result is itself legal.
>   Result = LegalizeOp(Result);
> @@ -4491,7 +4491,7 @@
>     Vec = LegalizeOp(Vec);
>     Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
>     SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
> -    if (Tmp3.Val)
> +    if (Tmp3.getNode())
>       return Tmp3;
>     break;
>   }
> @@ -4697,14 +4697,14 @@
>
>       SDValue Dummy;
>       SDValue Ops[2] = { LHS, RHS };
> -      Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).Val,
> +      Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(),
>                            false /*sign irrelevant*/, Dummy);
>       Tmp2 = DAG.getConstant(0, MVT::i32);
>       CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
>       if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
>         Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1),  
> Tmp1, Tmp2,
>                            CC);
> -        LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).Val,
> +        LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops,  
> 2).getNode(),
>                             false /*sign irrelevant*/, Dummy);
>         Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS),  
> LHS, Tmp2,
>                            DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
> @@ -4791,16 +4791,16 @@
>       TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false,  
> true, NULL);
>       Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo,  
> RHSLo,
>                                LowCC, false, DagCombineInfo);
> -      if (!Tmp1.Val)
> +      if (!Tmp1.getNode())
>         Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo,  
> RHSLo, LowCC);
>       Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi,  
> RHSHi,
>                                CCCode, false, DagCombineInfo);
> -      if (!Tmp2.Val)
> +      if (!Tmp2.getNode())
>         Tmp2 = DAG.getNode(ISD::SETCC,  
> TLI.getSetCCResultType(LHSHi), LHSHi,
>                            RHSHi,CC);
>
> -      ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
> -      ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
> +      ConstantSDNode *Tmp1C =  
> dyn_cast<ConstantSDNode>(Tmp1.getNode());
> +      ConstantSDNode *Tmp2C =  
> dyn_cast<ConstantSDNode>(Tmp2.getNode());
>       if ((Tmp1C && Tmp1C->isNullValue()) ||
>           (Tmp2C && Tmp2C->isNullValue() &&
>            (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
> @@ -4816,7 +4816,7 @@
>       } else {
>         Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi),  
> LHSHi, RHSHi,
>                                    ISD::SETEQ, false, DagCombineInfo);
> -        if (!Result.Val)
> +        if (!Result.getNode())
>           Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi,  
> RHSHi,
>                               ISD::SETEQ);
>         Result = LegalizeOp(DAG.getNode(ISD::SELECT,  
> Tmp1.getValueType(),
> @@ -4958,7 +4958,7 @@
>                        PseudoSourceValue::getConstantPool(), 0);
>   }
>
> -  if (SplatValue.Val) {   // Splat of one value?
> +  if (SplatValue.getNode()) {   // Splat of one value?
>     // Build the shuffle constant vector: <0, 0, 0, 0>
>     MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
>     SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
> @@ -5095,7 +5095,7 @@
>   unsigned NVTBits = NVT.getSizeInBits();
>
>   // Handle the case when Amt is an immediate.
> -  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
> +  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
>     unsigned Cst = CN->getValue();
>     // Expand the incoming operand to be shifted, so that we have  
> its parts
>     SDValue InL, InH;
> @@ -5292,14 +5292,14 @@
>       // FALLTHROUGH
>     case TargetLowering::Legal:
>       Tmp1 = LegalizeOp(Op);
> -      if (Result.Val)
> +      if (Result.getNode())
>         Result = DAG.UpdateNodeOperands(Result, Tmp1);
>       else
>         Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP :  
> ISD::UINT_TO_FP,
>                              DestTy, Tmp1);
>       if (isCustom) {
>         Tmp1 = TLI.LowerOperation(Result, DAG);
> -        if (Tmp1.Val) Result = Tmp1;
> +        if (Tmp1.getNode()) Result = Tmp1;
>       }
>       break;
>     case TargetLowering::Expand:
> @@ -5322,7 +5322,7 @@
>       Tmp1 = DAG.getZeroExtendInReg(Tmp1,
>                                     Op.getValueType());
>     }
> -    if (Result.Val)
> +    if (Result.getNode())
>       Result = DAG.UpdateNodeOperands(Result, Tmp1);
>     else
>       Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP :  
> ISD::UINT_TO_FP,
> @@ -5427,7 +5427,7 @@
>   case TargetLowering::Custom: {
>     SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP,  
> DestTy,
>                                                   Source), DAG);
> -    if (NV.Val)
> +    if (NV.getNode())
>       return LegalizeOp(NV);
>     break;   // The target decided this was legal after all
>   }
> @@ -5448,8 +5448,8 @@
>
>   Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
>   SDValue HiPart;
> -  SDValue Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart);
> -  if (Result.getValueType() != DestTy && HiPart.Val)
> +  SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned,  
> HiPart);
> +  if (Result.getValueType() != DestTy && HiPart.getNode())
>     Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
>   return Result;
> }
> @@ -5665,8 +5665,8 @@
>   // the target lowering hooks to expand it.  Just keep the low part  
> of the
>   // expanded operation, we know that we're truncating anyway.
>   if (getTypeAction(NewOutTy) == Expand) {
> -    Operation = SDValue(TLI.ReplaceNodeResults(Operation.Val, DAG),  
> 0);
> -    assert(Operation.Val && "Didn't return anything");
> +    Operation = SDValue(TLI.ReplaceNodeResults(Operation.getNode(),  
> DAG), 0);
> +    assert(Operation.getNode() && "Didn't return anything");
>   }
>
>   // Truncate the result of the extended FP_TO_*INT operation to the  
> desired
> @@ -5794,7 +5794,7 @@
> void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue  
> &Hi){
>   MVT VT = Op.getValueType();
>   MVT NVT = TLI.getTypeToTransformTo(VT);
> -  SDNode *Node = Op.Val;
> +  SDNode *Node = Op.getNode();
>   assert(getTypeAction(VT) == Expand && "Not an expanded type!");
>   assert(((NVT.isInteger() && NVT.bitsLT(VT)) ||  
> VT.isFloatingPoint() ||
>          VT.isVector()) && "Cannot expand to FP value or to larger  
> int value!");
> @@ -5820,9 +5820,9 @@
>       Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
>       SDValue Result = TLI.LowerOperation(
>         DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)),  
> DAG);
> -      assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
> -      Lo = Result.Val->getOperand(0);
> -      Hi = Result.Val->getOperand(1);
> +      assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
> +      Lo = Result.getNode()->getOperand(0);
> +      Hi = Result.getNode()->getOperand(1);
>       break;
>     }
>     // fall through
> @@ -6145,7 +6145,7 @@
>     }
>
>     // Turn this into a load/store pair by default.
> -    if (Tmp.Val == 0)
> +    if (Tmp.getNode() == 0)
>       Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
>
>     ExpandOp(Tmp, Lo, Hi);
> @@ -6157,7 +6157,7 @@
>                  TargetLowering::Custom &&
>            "Must custom expand ReadCycleCounter");
>     SDValue Tmp = TLI.LowerOperation(Op, DAG);
> -    assert(Tmp.Val && "Node must be custom expanded!");
> +    assert(Tmp.getNode() && "Node must be custom expanded!");
>     ExpandOp(Tmp.getValue(0), Lo, Hi);
>     AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized  
> the chain.
>                         LegalizeOp(Tmp.getValue(1)));
> @@ -6170,7 +6170,7 @@
>   case ISD::ATOMIC_CMP_SWAP_32:
>   case ISD::ATOMIC_CMP_SWAP_64: {
>     SDValue Tmp = TLI.LowerOperation(Op, DAG);
> -    assert(Tmp.Val && "Node must be custom expanded!");
> +    assert(Tmp.getNode() && "Node must be custom expanded!");
>     ExpandOp(Tmp.getValue(0), Lo, Hi);
>     AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized  
> the chain.
>                         LegalizeOp(Tmp.getValue(1)));
> @@ -6194,7 +6194,7 @@
>
>       // Now that the custom expander is done, expand the result,  
> which is still
>       // VT.
> -      if (Op.Val) {
> +      if (Op.getNode()) {
>         ExpandOp(Op, Lo, Hi);
>         break;
>       }
> @@ -6219,7 +6219,7 @@
>       Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op),  
> DAG);
>
>       // Now that the custom expander is done, expand the result.
> -      if (Op.Val) {
> +      if (Op.getNode()) {
>         ExpandOp(Op, Lo, Hi);
>         break;
>       }
> @@ -6238,7 +6238,7 @@
>     if (TLI.getOperationAction(ISD::SHL, VT) ==  
> TargetLowering::Custom) {
>       SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0),  
> ShiftAmt);
>       Op = TLI.LowerOperation(Op, DAG);
> -      if (Op.Val) {
> +      if (Op.getNode()) {
>         // Now that the custom expander is done, expand the result,  
> which is
>         // still VT.
>         ExpandOp(Op, Lo, Hi);
> @@ -6288,7 +6288,7 @@
>     if (TLI.getOperationAction(ISD::SRA, VT) ==  
> TargetLowering::Custom) {
>       SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0),  
> ShiftAmt);
>       Op = TLI.LowerOperation(Op, DAG);
> -      if (Op.Val) {
> +      if (Op.getNode()) {
>         // Now that the custom expander is done, expand the result,  
> which is
>         // still VT.
>         ExpandOp(Op, Lo, Hi);
> @@ -6320,7 +6320,7 @@
>     if (TLI.getOperationAction(ISD::SRL, VT) ==  
> TargetLowering::Custom) {
>       SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0),  
> ShiftAmt);
>       Op = TLI.LowerOperation(Op, DAG);
> -      if (Op.Val) {
> +      if (Op.getNode()) {
>         // Now that the custom expander is done, expand the result,  
> which is
>         // still VT.
>         ExpandOp(Op, Lo, Hi);
> @@ -6352,7 +6352,7 @@
>     if (TLI.getOperationAction(Node->getOpcode(), VT) ==
>             TargetLowering::Custom) {
>       SDValue Result = TLI.LowerOperation(Op, DAG);
> -      if (Result.Val) {
> +      if (Result.getNode()) {
>         ExpandOp(Result, Lo, Hi);
>         break;
>       }
> @@ -6425,7 +6425,7 @@
>     // If the target wants to custom expand this, let them.
>     if (TLI.getOperationAction(ISD::MUL, VT) ==  
> TargetLowering::Custom) {
>       SDValue New = TLI.LowerOperation(Op, DAG);
> -      if (New.Val) {
> +      if (New.getNode()) {
>         ExpandOp(New, Lo, Hi);
>         break;
>       }
> @@ -6450,7 +6450,7 @@
>         if (HasUMUL_LOHI) {
>           // We can emit a umul_lohi.
>           Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT),  
> LL, RL);
> -          Hi = SDValue(Lo.Val, 1);
> +          Hi = SDValue(Lo.getNode(), 1);
>           break;
>         }
>         if (HasMULHU) {
> @@ -6465,7 +6465,7 @@
>         if (HasSMUL_LOHI) {
>           // We can emit a smul_lohi.
>           Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT),  
> LL, RL);
> -          Hi = SDValue(Lo.Val, 1);
> +          Hi = SDValue(Lo.getNode(), 1);
>           break;
>         }
>         if (HasMULHS) {
> @@ -6678,7 +6678,7 @@
>         ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
>                       DAG.getValueType(SrcVT))
>         : DAG.getZeroExtendInReg(Tmp, SrcVT);
> -      Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
> +      Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
>       SrcVT = Node->getOperand(0).getValueType();
>     }
>
> @@ -6739,7 +6739,7 @@
>   // is a type that requires multi-step expansion.
>   if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
>     Lo = LegalizeOp(Lo);
> -    if (Hi.Val)
> +    if (Hi.getNode())
>       // Don't legalize the high part if it is expanded to a single  
> node.
>       Hi = LegalizeOp(Hi);
>   }
> @@ -6755,7 +6755,7 @@
> void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
>                                          SDValue &Hi) {
>   assert(Op.getValueType().isVector() && "Cannot split non-vector  
> type!");
> -  SDNode *Node = Op.Val;
> +  SDNode *Node = Op.getNode();
>   unsigned NumElements = Op.getValueType().getVectorNumElements();
>   assert(NumElements > 1 && "Cannot split a single element vector!");
>
> @@ -7033,7 +7033,7 @@
>       unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
>                                              
> Op.getValueType().getTypeForMVT());
>       SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(),  
> LdAlign);
> -      int FI = cast<FrameIndexSDNode>(Ptr.Val)->getIndex();
> +      int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
>
>       SDValue St = DAG.getStore(DAG.getEntryNode(),
>                                   InOp, Ptr,
> @@ -7061,7 +7061,7 @@
> /// scalar (e.g. f32) value.
> SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
>   assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp  
> invocation!");
> -  SDNode *Node = Op.Val;
> +  SDNode *Node = Op.getNode();
>   MVT NewVT = Op.getValueType().getVectorElementType();
>   assert(Op.getValueType().getVectorNumElements() == 1);
>
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Thu  
> Aug 28 16:40:38 2008
> @@ -76,7 +76,7 @@
>   }
>
>   // If R is null, the sub-method took care of registering the result.
> -  if (R.Val)
> +  if (R.getNode())
>     SetSoftenedFloat(SDValue(N, ResNo), R);
> }
>
> @@ -311,11 +311,11 @@
>   }
>
>   // If the result is null, the sub-method took care of registering  
> results etc.
> -  if (!Res.Val) return false;
> +  if (!Res.getNode()) return false;
>
>   // If the result is N, the sub-method updated N in place.  Check  
> to see if any
>   // operands are new, and if so, mark them.
> -  if (Res.Val == N) {
> +  if (Res.getNode() == N) {
>     // Mark N as new and remark N and its operands.  This allows us  
> to correctly
>     // revisit N if it needs another step of promotion and allows us  
> to visit
>     // any new operands to N.
> @@ -438,7 +438,7 @@
>
>   // If SoftenSetCCOperands returned a scalar, we need to compare  
> the result
>   // against zero to select between true and false values.
> -  if (NewRHS.Val == 0) {
> +  if (NewRHS.getNode() == 0) {
>     NewRHS = DAG.getConstant(0, NewLHS.getValueType());
>     CCCode = ISD::SETNE;
>   }
> @@ -472,7 +472,7 @@
>
>   // If SoftenSetCCOperands returned a scalar, we need to compare  
> the result
>   // against zero to select between true and false values.
> -  if (NewRHS.Val == 0) {
> +  if (NewRHS.getNode() == 0) {
>     NewRHS = DAG.getConstant(0, NewLHS.getValueType());
>     CCCode = ISD::SETNE;
>   }
> @@ -489,7 +489,7 @@
>   SoftenSetCCOperands(NewLHS, NewRHS, CCCode);
>
>   // If SoftenSetCCOperands returned a scalar, use it.
> -  if (NewRHS.Val == 0) {
> +  if (NewRHS.getNode() == 0) {
>     assert(NewLHS.getValueType() == N->getValueType(0) &&
>            "Unexpected setcc expansion!");
>     return NewLHS;
> @@ -577,7 +577,7 @@
>   }
>
>   // If Lo/Hi is null, the sub-method took care of registering  
> results etc.
> -  if (Lo.Val)
> +  if (Lo.getNode())
>     SetExpandedFloat(SDValue(N, ResNo), Lo, Hi);
> }
>
> @@ -603,7 +603,7 @@
>                                             RTLIB::ADD_PPCF128),
>                                N->getValueType(0), Ops, 2,
>                                false);
> -  assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered  
> wrongly!");
> +  assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call  
> lowered wrongly!");
>   Lo = Call.getOperand(0); Hi = Call.getOperand(1);
> }
>
> @@ -630,7 +630,7 @@
>                                             RTLIB::DIV_PPCF128),
>                                N->getValueType(0), Ops, 2,
>                                false);
> -  assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered  
> wrongly!");
> +  assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call  
> lowered wrongly!");
>   Lo = Call.getOperand(0); Hi = Call.getOperand(1);
> }
>
> @@ -644,7 +644,7 @@
>                                             RTLIB::MUL_PPCF128),
>                                N->getValueType(0), Ops, 2,
>                                false);
> -  assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered  
> wrongly!");
> +  assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call  
> lowered wrongly!");
>   Lo = Call.getOperand(0); Hi = Call.getOperand(1);
> }
>
> @@ -672,7 +672,7 @@
>                                             RTLIB::SUB_PPCF128),
>                                N->getValueType(0), Ops, 2,
>                                false);
> -  assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered  
> wrongly!");
> +  assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call  
> lowered wrongly!");
>   Lo = Call.getOperand(0); Hi = Call.getOperand(1);
> }
>
> @@ -734,7 +734,7 @@
>     assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
>
>     Hi = MakeLibCall(LC, VT, &Src, 1, true);
> -    assert(Hi.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered  
> wrongly!");
> +    assert(Hi.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call  
> lowered wrongly!");
>     Lo = Hi.getOperand(0); Hi = Hi.getOperand(1);
>   }
>
> @@ -790,7 +790,7 @@
>       == TargetLowering::Custom)
>     Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
>
> -  if (Res.Val == 0) {
> +  if (Res.getNode() == 0) {
>     switch (N->getOpcode()) {
>     default:
>   #ifndef NDEBUG
> @@ -816,10 +816,10 @@
>   }
>
>   // If the result is null, the sub-method took care of registering  
> results etc.
> -  if (!Res.Val) return false;
> +  if (!Res.getNode()) return false;
>   // If the result is N, the sub-method updated N in place.  Check  
> to see if any
>   // operands are new, and if so, mark them.
> -  if (Res.Val == N) {
> +  if (Res.getNode() == N) {
>     // Mark N as new and remark N and its operands.  This allows us  
> to correctly
>     // revisit N if it needs another step of expansion and allows us  
> to visit
>     // any new operands to N.
> @@ -869,7 +869,7 @@
>
>   // If ExpandSetCCOperands returned a scalar, we need to compare  
> the result
>   // against zero to select between true and false values.
> -  if (NewRHS.Val == 0) {
> +  if (NewRHS.getNode() == 0) {
>     NewRHS = DAG.getConstant(0, NewLHS.getValueType());
>     CCCode = ISD::SETNE;
>   }
> @@ -910,7 +910,7 @@
>
>   // If ExpandSetCCOperands returned a scalar, we need to compare  
> the result
>   // against zero to select between true and false values.
> -  if (NewRHS.Val == 0) {
> +  if (NewRHS.getNode() == 0) {
>     NewRHS = DAG.getConstant(0, NewLHS.getValueType());
>     CCCode = ISD::SETNE;
>   }
> @@ -927,7 +927,7 @@
>   FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode);
>
>   // If ExpandSetCCOperands returned a scalar, use it.
> -  if (NewRHS.Val == 0) {
> +  if (NewRHS.getNode() == 0) {
>     assert(NewLHS.getValueType() == N->getValueType(0) &&
>            "Unexpected setcc expansion!");
>     return NewLHS;
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Thu  
> Aug 28 16:40:38 2008
> @@ -99,7 +99,7 @@
>   }
>
>   // If Result is null, the sub-method took care of registering the  
> result.
> -  if (Result.Val)
> +  if (Result.getNode())
>     SetPromotedInteger(SDValue(N, ResNo), Result);
> }
>
> @@ -167,7 +167,7 @@
>   // Otherwise, lower the bit-convert to a store/load from the  
> stack, then
>   // promote the load.
>   SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0));
> -  return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.Val));
> +  return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.getNode()));
> }
>
> SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
> @@ -494,7 +494,7 @@
>       == TargetLowering::Custom)
>     Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
>
> -  if (Res.Val == 0) {
> +  if (Res.getNode() == 0) {
>     switch (N->getOpcode()) {
>       default:
>   #ifndef NDEBUG
> @@ -529,9 +529,9 @@
>   }
>
>   // If the result is null, the sub-method took care of registering  
> results etc.
> -  if (!Res.Val) return false;
> +  if (!Res.getNode()) return false;
>   // If the result is N, the sub-method updated N in place.
> -  if (Res.Val == N) {
> +  if (Res.getNode() == N) {
>     // Mark N as new and remark N and its operands.  This allows us  
> to correctly
>     // revisit N if it needs another step of promotion and allows us  
> to visit
>     // any new operands to N.
> @@ -885,7 +885,7 @@
>   }
>
>   // If Lo/Hi is null, the sub-method took care of registering  
> results etc.
> -  if (Lo.Val)
> +  if (Lo.getNode())
>     SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
> }
>
> @@ -1395,7 +1395,7 @@
>       if (HasUMUL_LOHI) {
>         // We can emit a umul_lohi.
>         Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT),  
> LL, RL);
> -        Hi = SDValue(Lo.Val, 1);
> +        Hi = SDValue(Lo.getNode(), 1);
>         return;
>       }
>       if (HasMULHU) {
> @@ -1410,7 +1410,7 @@
>       if (HasSMUL_LOHI) {
>         // We can emit a smul_lohi.
>         Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT),  
> LL, RL);
> -        Hi = SDValue(Lo.Val, 1);
> +        Hi = SDValue(Lo.getNode(), 1);
>         return;
>       }
>       if (HasMULHS) {
> @@ -1706,7 +1706,7 @@
>       == TargetLowering::Custom)
>     Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
>
> -  if (Res.Val == 0) {
> +  if (Res.getNode() == 0) {
>     switch (N->getOpcode()) {
>     default:
>   #ifndef NDEBUG
> @@ -1732,10 +1732,10 @@
>   }
>
>   // If the result is null, the sub-method took care of registering  
> results etc.
> -  if (!Res.Val) return false;
> +  if (!Res.getNode()) return false;
>   // If the result is N, the sub-method updated N in place.  Check  
> to see if any
>   // operands are new, and if so, mark them.
> -  if (Res.Val == N) {
> +  if (Res.getNode() == N) {
>     // Mark N as new and remark N and its operands.  This allows us  
> to correctly
>     // revisit N if it needs another step of expansion and allows us  
> to visit
>     // any new operands to N.
> @@ -1814,16 +1814,16 @@
>   SDValue Tmp1, Tmp2;
>   Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo,  
> RHSLo, LowCC,
>                            false, DagCombineInfo);
> -  if (!Tmp1.Val)
> +  if (!Tmp1.getNode())
>     Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,  
> LowCC);
>   Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi,  
> RHSHi,
>                            CCCode, false, DagCombineInfo);
> -  if (!Tmp2.Val)
> +  if (!Tmp2.getNode())
>     Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi),  
> LHSHi, RHSHi,
>                        DAG.getCondCode(CCCode));
>
> -  ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
> -  ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
> +  ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
> +  ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
>   if ((Tmp1C && Tmp1C->isNullValue()) ||
>       (Tmp2C && Tmp2C->isNullValue() &&
>        (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
> @@ -1841,7 +1841,7 @@
>
>   NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi,  
> RHSHi,
>                              ISD::SETEQ, false, DagCombineInfo);
> -  if (!NewLHS.Val)
> +  if (!NewLHS.getNode())
>     NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
>                           ISD::SETEQ);
>   NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
> @@ -1856,7 +1856,7 @@
>
>   // If ExpandSetCCOperands returned a scalar, we need to compare  
> the result
>   // against zero to select between true and false values.
> -  if (NewRHS.Val == 0) {
> +  if (NewRHS.getNode() == 0) {
>     NewRHS = DAG.getConstant(0, NewLHS.getValueType());
>     CCCode = ISD::SETNE;
>   }
> @@ -1874,7 +1874,7 @@
>
>   // If ExpandSetCCOperands returned a scalar, we need to compare  
> the result
>   // against zero to select between true and false values.
> -  if (NewRHS.Val == 0) {
> +  if (NewRHS.getNode() == 0) {
>     NewRHS = DAG.getConstant(0, NewLHS.getValueType());
>     CCCode = ISD::SETNE;
>   }
> @@ -1891,7 +1891,7 @@
>   IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
>
>   // If ExpandSetCCOperands returned a scalar, use it.
> -  if (NewRHS.Val == 0) {
> +  if (NewRHS.getNode() == 0) {
>     assert(NewLHS.getValueType() == N->getValueType(0) &&
>            "Unexpected setcc expansion!");
>     return NewLHS;
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -92,7 +92,7 @@
>     bool NeedsRevisit = false;
>     unsigned i;
>     for (i = 0; i != NumOperands; ++i) {
> -      if (IgnoreNodeResults(N->getOperand(i).Val))
> +      if (IgnoreNodeResults(N->getOperand(i).getNode()))
>         continue;
>
>       MVT OpVT = N->getOperand(i).getValueType();
> @@ -194,7 +194,7 @@
>
>     // Check that all operand types are legal.
>     for (unsigned i = 0, NumOps = I->getNumOperands(); i < NumOps; + 
> +i)
> -      if (!IgnoreNodeResults(I->getOperand(i).Val) &&
> +      if (!IgnoreNodeResults(I->getOperand(i).getNode()) &&
>           !isTypeLegal(I->getOperand(i).getValueType())) {
>         cerr << "Operand type " << i << " illegal!\n";
>         Failed = true;
> @@ -221,7 +221,8 @@
> /// AnalyzeNewNode - The specified node is the root of a subtree of  
> potentially
> /// new nodes.  Correct any processed operands (this may change the  
> node) and
> /// calculate the NodeId.
> -void DAGTypeLegalizer::AnalyzeNewNode(SDNode *&N) {
> +void DAGTypeLegalizer::AnalyzeNewNode(SDValue &Val) {
> +  SDNode * const N(Val.getNode());
>   // If this was an existing node that is already done, we're done.
>   if (N->getNodeId() != NewNode)
>     return;
> @@ -246,12 +247,12 @@
>     SDValue OrigOp = N->getOperand(i);
>     SDValue Op = OrigOp;
>
> -    if (Op.Val->getNodeId() == Processed)
> +    if (Op.getNode()->getNodeId() == Processed)
>       RemapNode(Op);
>
> -    if (Op.Val->getNodeId() == NewNode)
> -      AnalyzeNewNode(Op.Val);
> -    else if (Op.Val->getNodeId() == Processed)
> +    if (Op.getNode()->getNodeId() == NewNode)
> +      AnalyzeNewNode(Op);
> +    else if (Op.getNode()->getNodeId() == Processed)
>       ++NumProcessed;
>
>     if (!NewOps.empty()) {
> @@ -267,11 +268,14 @@
>
>   // Some operands changed - update the node.
>   if (!NewOps.empty())
> -    N = DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0],  
> NewOps.size()).Val;
> -
> -  N->setNodeId(N->getNumOperands()-NumProcessed);
> -  if (N->getNodeId() == ReadyToProcess)
> -    Worklist.push_back(N);
> +    Val.setNode(DAG.UpdateNodeOperands(SDValue(N, 0),
> +				       &NewOps[0],
> +				       NewOps.size()).getNode());
> +
> +  SDNode * const Nu(Val.getNode());
> +  Nu->setNodeId(Nu->getNumOperands()-NumProcessed);
> +  if (Nu->getNodeId() == ReadyToProcess)
> +    Worklist.push_back(Nu);
> }
>
> namespace {
> @@ -313,8 +317,8 @@
>   if (From == To) return;
>
>   // If expansion produced new nodes, make sure they are properly  
> marked.
> -  ExpungeNode(From.Val);
> -  AnalyzeNewNode(To.Val); // Expunges To.
> +  ExpungeNode(From.getNode());
> +  AnalyzeNewNode(To); // Expunges To.
>
>   // Anything that used the old node should now use the new one.   
> Note that this
>   // can potentially cause recursive merging.
> @@ -333,7 +337,10 @@
>
>   // If expansion produced new nodes, make sure they are properly  
> marked.
>   ExpungeNode(From);
> -  AnalyzeNewNode(To); // Expunges To.
> +
> +  SDValue ToNode(To, 0);
> +  AnalyzeNewNode(ToNode); // Expunges To.
> +  To = ToNode.getNode();
>
>   assert(From->getNumValues() == To->getNumValues() &&
>          "Node results don't match");
> @@ -394,39 +401,39 @@
>
>   for (DenseMap<SDValue, SDValue>::iterator I =  
> PromotedIntegers.begin(),
>        E = PromotedIntegers.end(); I != E; ++I) {
> -    assert(I->first.Val != N);
> +    assert(I->first.getNode() != N);
>     RemapNode(I->second);
>   }
>
>   for (DenseMap<SDValue, SDValue>::iterator I =  
> SoftenedFloats.begin(),
>        E = SoftenedFloats.end(); I != E; ++I) {
> -    assert(I->first.Val != N);
> +    assert(I->first.getNode() != N);
>     RemapNode(I->second);
>   }
>
>   for (DenseMap<SDValue, SDValue>::iterator I =  
> ScalarizedVectors.begin(),
>        E = ScalarizedVectors.end(); I != E; ++I) {
> -    assert(I->first.Val != N);
> +    assert(I->first.getNode() != N);
>     RemapNode(I->second);
>   }
>
>   for (DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator
>        I = ExpandedIntegers.begin(), E = ExpandedIntegers.end(); I ! 
> = E; ++I){
> -    assert(I->first.Val != N);
> +    assert(I->first.getNode() != N);
>     RemapNode(I->second.first);
>     RemapNode(I->second.second);
>   }
>
>   for (DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator
>        I = ExpandedFloats.begin(), E = ExpandedFloats.end(); I != E;  
> ++I) {
> -    assert(I->first.Val != N);
> +    assert(I->first.getNode() != N);
>     RemapNode(I->second.first);
>     RemapNode(I->second.second);
>   }
>
>   for (DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator
>        I = SplitVectors.begin(), E = SplitVectors.end(); I != E; + 
> +I) {
> -    assert(I->first.Val != N);
> +    assert(I->first.getNode() != N);
>     RemapNode(I->second.first);
>     RemapNode(I->second.second);
>   }
> @@ -440,26 +447,26 @@
> }
>
> void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue  
> Result) {
> -  AnalyzeNewNode(Result.Val);
> +  AnalyzeNewNode(Result);
>
>   SDValue &OpEntry = PromotedIntegers[Op];
> -  assert(OpEntry.Val == 0 && "Node is already promoted!");
> +  assert(OpEntry.getNode() == 0 && "Node is already promoted!");
>   OpEntry = Result;
> }
>
> void DAGTypeLegalizer::SetSoftenedFloat(SDValue Op, SDValue Result) {
> -  AnalyzeNewNode(Result.Val);
> +  AnalyzeNewNode(Result);
>
>   SDValue &OpEntry = SoftenedFloats[Op];
> -  assert(OpEntry.Val == 0 && "Node is already converted to  
> integer!");
> +  assert(OpEntry.getNode() == 0 && "Node is already converted to  
> integer!");
>   OpEntry = Result;
> }
>
> void DAGTypeLegalizer::SetScalarizedVector(SDValue Op, SDValue  
> Result) {
> -  AnalyzeNewNode(Result.Val);
> +  AnalyzeNewNode(Result);
>
>   SDValue &OpEntry = ScalarizedVectors[Op];
> -  assert(OpEntry.Val == 0 && "Node is already scalarized!");
> +  assert(OpEntry.getNode() == 0 && "Node is already scalarized!");
>   OpEntry = Result;
> }
>
> @@ -468,7 +475,7 @@
>   std::pair<SDValue, SDValue> &Entry = ExpandedIntegers[Op];
>   RemapNode(Entry.first);
>   RemapNode(Entry.second);
> -  assert(Entry.first.Val && "Operand isn't expanded");
> +  assert(Entry.first.getNode() && "Operand isn't expanded");
>   Lo = Entry.first;
>   Hi = Entry.second;
> }
> @@ -476,12 +483,12 @@
> void DAGTypeLegalizer::SetExpandedInteger(SDValue Op, SDValue Lo,
>                                           SDValue Hi) {
>   // Lo/Hi may have been newly allocated, if so, add nodeid's as  
> relevant.
> -  AnalyzeNewNode(Lo.Val);
> -  AnalyzeNewNode(Hi.Val);
> +  AnalyzeNewNode(Lo);
> +  AnalyzeNewNode(Hi);
>
>   // Remember that this is the result of the node.
>   std::pair<SDValue, SDValue> &Entry = ExpandedIntegers[Op];
> -  assert(Entry.first.Val == 0 && "Node already expanded");
> +  assert(Entry.first.getNode() == 0 && "Node already expanded");
>   Entry.first = Lo;
>   Entry.second = Hi;
> }
> @@ -491,7 +498,7 @@
>   std::pair<SDValue, SDValue> &Entry = ExpandedFloats[Op];
>   RemapNode(Entry.first);
>   RemapNode(Entry.second);
> -  assert(Entry.first.Val && "Operand isn't expanded");
> +  assert(Entry.first.getNode() && "Operand isn't expanded");
>   Lo = Entry.first;
>   Hi = Entry.second;
> }
> @@ -499,12 +506,12 @@
> void DAGTypeLegalizer::SetExpandedFloat(SDValue Op, SDValue Lo,
>                                         SDValue Hi) {
>   // Lo/Hi may have been newly allocated, if so, add nodeid's as  
> relevant.
> -  AnalyzeNewNode(Lo.Val);
> -  AnalyzeNewNode(Hi.Val);
> +  AnalyzeNewNode(Lo);
> +  AnalyzeNewNode(Hi);
>
>   // Remember that this is the result of the node.
>   std::pair<SDValue, SDValue> &Entry = ExpandedFloats[Op];
> -  assert(Entry.first.Val == 0 && "Node already expanded");
> +  assert(Entry.first.getNode() == 0 && "Node already expanded");
>   Entry.first = Lo;
>   Entry.second = Hi;
> }
> @@ -514,7 +521,7 @@
>   std::pair<SDValue, SDValue> &Entry = SplitVectors[Op];
>   RemapNode(Entry.first);
>   RemapNode(Entry.second);
> -  assert(Entry.first.Val && "Operand isn't split");
> +  assert(Entry.first.getNode() && "Operand isn't split");
>   Lo = Entry.first;
>   Hi = Entry.second;
> }
> @@ -522,12 +529,12 @@
> void DAGTypeLegalizer::SetSplitVector(SDValue Op, SDValue Lo,
>                                       SDValue Hi) {
>   // Lo/Hi may have been newly allocated, if so, add nodeid's as  
> relevant.
> -  AnalyzeNewNode(Lo.Val);
> -  AnalyzeNewNode(Hi.Val);
> +  AnalyzeNewNode(Lo);
> +  AnalyzeNewNode(Hi);
>
>   // Remember that this is the result of the node.
>   std::pair<SDValue, SDValue> &Entry = SplitVectors[Op];
> -  assert(Entry.first.Val == 0 && "Node already split");
> +  assert(Entry.first.getNode() == 0 && "Node already split");
>   Entry.first = Lo;
>   Entry.second = Hi;
> }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Thu Aug 28  
> 16:40:38 2008
> @@ -157,7 +157,8 @@
>   /// for the specified node, adding it to the worklist if ready.
>   void ReanalyzeNode(SDNode *N) {
>     N->setNodeId(NewNode);
> -    AnalyzeNewNode(N);
> +    SDValue V(N, 0);
> +    AnalyzeNewNode(V); // FIXME: ignore the change?
>   }
>
>   void NoteDeletion(SDNode *Old, SDNode *New) {
> @@ -168,7 +169,7 @@
>   }
>
> private:
> -  void AnalyzeNewNode(SDNode *&N);
> +  void AnalyzeNewNode(SDValue &Val);
>
>   void ReplaceValueWith(SDValue From, SDValue To);
>   void ReplaceNodeWith(SDNode *From, SDNode *To);
> @@ -197,7 +198,7 @@
>   SDValue GetPromotedInteger(SDValue Op) {
>     SDValue &PromotedOp = PromotedIntegers[Op];
>     RemapNode(PromotedOp);
> -    assert(PromotedOp.Val && "Operand wasn't promoted?");
> +    assert(PromotedOp.getNode() && "Operand wasn't promoted?");
>     return PromotedOp;
>   }
>   void SetPromotedInteger(SDValue Op, SDValue Result);
> @@ -324,7 +325,7 @@
>   SDValue GetSoftenedFloat(SDValue Op) {
>     SDValue &SoftenedOp = SoftenedFloats[Op];
>     RemapNode(SoftenedOp);
> -    assert(SoftenedOp.Val && "Operand wasn't converted to integer?");
> +    assert(SoftenedOp.getNode() && "Operand wasn't converted to  
> integer?");
>     return SoftenedOp;
>   }
>   void SetSoftenedFloat(SDValue Op, SDValue Result);
> @@ -403,7 +404,7 @@
>   SDValue GetScalarizedVector(SDValue Op) {
>     SDValue &ScalarizedOp = ScalarizedVectors[Op];
>     RemapNode(ScalarizedOp);
> -    assert(ScalarizedOp.Val && "Operand wasn't scalarized?");
> +    assert(ScalarizedOp.getNode() && "Operand wasn't scalarized?");
>     return ScalarizedOp;
>   }
>   void SetScalarizedVector(SDValue Op, SDValue Result);
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Thu  
> Aug 28 16:40:38 2008
> @@ -75,7 +75,7 @@
>
>   // Lower the bit-convert to a store/load from the stack, then  
> expand the load.
>   SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0));
> -  ExpandRes_NormalLoad(Op.Val, Lo, Hi);
> +  ExpandRes_NormalLoad(Op.getNode(), Lo, Hi);
> }
>
> void DAGTypeLegalizer::ExpandRes_BUILD_PAIR(SDNode *N, SDValue &Lo,
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Thu  
> Aug 28 16:40:38 2008
> @@ -88,7 +88,7 @@
>   }
>
>   // If R is null, the sub-method took care of registering the result.
> -  if (R.Val)
> +  if (R.getNode())
>     SetScalarizedVector(SDValue(N, ResNo), R);
> }
>
> @@ -184,7 +184,7 @@
>         cerr << "\n");
>   SDValue Res = SDValue();
>
> -  if (Res.Val == 0) {
> +  if (Res.getNode() == 0) {
>     switch (N->getOpcode()) {
>     default:
> #ifndef NDEBUG
> @@ -206,11 +206,11 @@
>   }
>
>   // If the result is null, the sub-method took care of registering  
> results etc.
> -  if (!Res.Val) return false;
> +  if (!Res.getNode()) return false;
>
>   // If the result is N, the sub-method updated N in place.  Check  
> to see if any
>   // operands are new, and if so, mark them.
> -  if (Res.Val == N) {
> +  if (Res.getNode() == N) {
>     // Mark N as new and remark N and its operands.  This allows us  
> to correctly
>     // revisit N if it needs another step of promotion and allows us  
> to visit
>     // any new operands to N.
> @@ -332,7 +332,7 @@
>   }
>
>   // If Lo/Hi is null, the sub-method took care of registering  
> results etc.
> -  if (Lo.Val)
> +  if (Lo.getNode())
>     SetSplitVector(SDValue(N, ResNo), Lo, Hi);
> }
>
> @@ -475,7 +475,7 @@
>   SDValue Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0);
>
>   // Split it.
> -  SplitVecRes_LOAD(cast<LoadSDNode>(Load.Val), Lo, Hi);
> +  SplitVecRes_LOAD(cast<LoadSDNode>(Load.getNode()), Lo, Hi);
> }
>
> void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
> @@ -595,7 +595,7 @@
>   DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
>   SDValue Res = SDValue();
>
> -  if (Res.Val == 0) {
> +  if (Res.getNode() == 0) {
>     switch (N->getOpcode()) {
>     default:
> #ifndef NDEBUG
> @@ -615,11 +615,11 @@
>   }
>
>   // If the result is null, the sub-method took care of registering  
> results etc.
> -  if (!Res.Val) return false;
> +  if (!Res.getNode()) return false;
>
>   // If the result is N, the sub-method updated N in place.  Check  
> to see if any
>   // operands are new, and if so, mark them.
> -  if (Res.Val == N) {
> +  if (Res.getNode() == N) {
>     // Mark N as new and remark N and its operands.  This allows us  
> to correctly
>     // revisit N if it needs another step of promotion and allows us  
> to visit
>     // any new operands to N.
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -122,7 +122,7 @@
>     if (N->getNumOperands() &&
>         N->getOperand(N->getNumOperands()-1).getValueType() ==  
> MVT::Flag) {
>       do {
> -        N = N->getOperand(N->getNumOperands()-1).Val;
> +        N = N->getOperand(N->getNumOperands()-1).getNode();
>         NodeSUnit->FlaggedNodes.push_back(N);
>         assert(N->getNodeId() == -1 && "Node already inserted!");
>         N->setNodeId(NodeSUnit->NodeNum);
> @@ -192,7 +192,7 @@
>         SU->hasPhysRegDefs = true;
>
>       for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
> -        SDNode *OpN = N->getOperand(i).Val;
> +        SDNode *OpN = N->getOperand(i).getNode();
>         if (isPassiveNode(OpN)) continue;   // Not scheduled.
>         SUnit *OpSU = &SUnits[OpN->getNodeId()];
>         assert(OpSU && "Node has no SUnit!");
> @@ -373,7 +373,7 @@
> /// actual operands that will go into the resulting MachineInstr.
> unsigned ScheduleDAG::CountOperands(SDNode *Node) {
>   unsigned N = ComputeMemOperandsEnd(Node);
> -  while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).Val))
> +  while (N && isa<MemOperandSDNode>(Node->getOperand(N -  
> 1).getNode()))
>     --N; // Ignore MEMOPERAND nodes
>   return N;
> }
> @@ -429,7 +429,7 @@
>     SDNode *User = *UI;
>     bool Match = true;
>     if (User->getOpcode() == ISD::CopyToReg &&
> -        User->getOperand(2).Val == Node &&
> +        User->getOperand(2).getNode() == Node &&
>         User->getOperand(2).getResNo() == ResNo) {
>       unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))- 
> >getReg();
>       if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
> @@ -440,7 +440,7 @@
>     } else {
>       for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
>         SDValue Op = User->getOperand(i);
> -        if (Op.Val != Node || Op.getResNo() != ResNo)
> +        if (Op.getNode() != Node || Op.getResNo() != ResNo)
>           continue;
>         MVT VT = Node->getValueType(Op.getResNo());
>         if (VT != MVT::Other && VT != MVT::Flag)
> @@ -489,7 +489,7 @@
>
>   SDNode *User = *Node->use_begin();
>   if (User->getOpcode() == ISD::CopyToReg &&
> -      User->getOperand(2).Val == Node &&
> +      User->getOperand(2).getNode() == Node &&
>       User->getOperand(2).getResNo() == ResNo) {
>     unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))- 
> >getReg();
>     if (TargetRegisterInfo::isVirtualRegister(Reg))
> @@ -513,7 +513,7 @@
>          UI != E; ++UI) {
>       SDNode *User = *UI;
>       if (User->getOpcode() == ISD::CopyToReg &&
> -          User->getOperand(2).Val == Node &&
> +          User->getOperand(2).getNode() == Node &&
>           User->getOperand(2).getResNo() == i) {
>         unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))- 
> >getReg();
>         if (TargetRegisterInfo::isVirtualRegister(Reg)) {
> @@ -547,7 +547,7 @@
>   if (Op.isMachineOpcode() &&
>       Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
>     // Add an IMPLICIT_DEF instruction before every use.
> -    unsigned VReg = getDstOfOnlyCopyToRegUse(Op.Val, Op.getResNo());
> +    unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(),  
> Op.getResNo());
>     // IMPLICIT_DEF can produce any type of result so its  
> TargetInstrDesc
>     // does not include operand register class info.
>     if (!VReg) {
> @@ -600,7 +600,7 @@
>       if (RC && VRC != RC) {
>         cerr << "Register class of operand and regclass of use don't  
> agree!\n";
>         cerr << "Operand = " << IIOpNum << "\n";
> -        cerr << "Op->Val = "; Op.Val->dump(&DAG); cerr << "\n";
> +        cerr << "Op->Val = "; Op.getNode()->dump(&DAG); cerr << "\n";
>         cerr << "MI = "; MI->print(cerr);
>         cerr << "VReg = " << VReg << "\n";
>         cerr << "VReg RegClass     size = " << VRC->getSize()
> @@ -712,7 +712,7 @@
>        UI != E; ++UI) {
>     SDNode *User = *UI;
>     if (User->getOpcode() == ISD::CopyToReg &&
> -        User->getOperand(2).Val == Node) {
> +        User->getOperand(2).getNode() == Node) {
>       unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))- 
> >getReg();
>       if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
>         VRBase = DestReg;
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu  
> Aug 28 16:40:38 2008
> @@ -224,7 +224,7 @@
>         if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1)
>           continue;
>
> -        SDNode *OpN = SU->Node->getOperand(j).Val;
> +        SDNode *OpN = SU->Node->getOperand(j).getNode();
>         SUnit *OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN- 
> >getNodeId()];
>         if (OpSU && OperandSeen.count(OpSU) == 1) {
>           // Ok, so SU is not the last use of OpSU, but SU is two- 
> address so
> @@ -233,7 +233,7 @@
>           bool DoCommute = true;
>           for (unsigned k = 0; k < NumOps; ++k) {
>             if (k != j) {
> -              OpN = SU->Node->getOperand(k).Val;
> +              OpN = SU->Node->getOperand(k).getNode();
>               OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN- 
> >getNodeId()];
>               if (OpSU && OperandSeen.count(OpSU) == 1) {
>                 DoCommute = false;
> @@ -641,7 +641,7 @@
>   }
>   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
>     const SDValue &Op = N->getOperand(i);
> -    MVT VT = Op.Val->getValueType(Op.getResNo());
> +    MVT VT = Op.getNode()->getValueType(Op.getResNo());
>     if (VT == MVT::Flag)
>       return NULL;
>   }
> @@ -930,7 +930,7 @@
>   unsigned CurCycle = 0;
>   // Add root to Available queue.
>   if (!SUnits.empty()) {
> -    SUnit *RootSU = &SUnits[DAG.getRoot().Val->getNodeId()];
> +    SUnit *RootSU = &SUnits[DAG.getRoot().getNode()->getNodeId()];
>     assert(RootSU->Succs.empty() && "Graph root shouldn't have  
> successors!");
>     RootSU->isAvailable = true;
>     AvailableQueue->push(RootSU);
> @@ -1668,7 +1668,7 @@
>     unsigned NumOps = TID.getNumOperands() - NumRes;
>     for (unsigned i = 0; i != NumOps; ++i) {
>       if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) {
> -        SDNode *DU = SU->Node->getOperand(i).Val;
> +        SDNode *DU = SU->Node->getOperand(i).getNode();
>         if (DU->getNodeId() != -1 &&
>             Op->OrigNode == &(*SUnits)[DU->getNodeId()])
>           return true;
> @@ -1742,7 +1742,7 @@
>     unsigned NumOps = TID.getNumOperands() - NumRes;
>     for (unsigned j = 0; j != NumOps; ++j) {
>       if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) != -1) {
> -        SDNode *DU = SU->Node->getOperand(j).Val;
> +        SDNode *DU = SU->Node->getOperand(j).getNode();
>         if (DU->getNodeId() == -1)
>           continue;
>         const SUnit *DUSU = &(*SUnits)[DU->getNodeId()];
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -96,7 +96,7 @@
> bool ISD::isBuildVectorAllOnes(const SDNode *N) {
>   // Look through a bit convert.
>   if (N->getOpcode() == ISD::BIT_CONVERT)
> -    N = N->getOperand(0).Val;
> +    N = N->getOperand(0).getNode();
>
>   if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
>
> @@ -137,7 +137,7 @@
> bool ISD::isBuildVectorAllZeros(const SDNode *N) {
>   // Look through a bit convert.
>   if (N->getOpcode() == ISD::BIT_CONVERT)
> -    N = N->getOperand(0).Val;
> +    N = N->getOperand(0).getNode();
>
>   if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
>
> @@ -326,7 +326,7 @@
> static void AddNodeIDOperands(FoldingSetNodeID &ID,
>                               const SDValue *Ops, unsigned NumOps) {
>   for (; NumOps; --NumOps, ++Ops) {
> -    ID.AddPointer(Ops->Val);
> +    ID.AddPointer(Ops->getNode());
>     ID.AddInteger(Ops->getResNo());
>   }
> }
> @@ -1230,9 +1230,9 @@
>     break;
>   }
>
> -  if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val)) {
> +  if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) {
>     const APInt &C2 = N2C->getAPIntValue();
> -    if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
> +    if (ConstantSDNode *N1C =  
> dyn_cast<ConstantSDNode>(N1.getNode())) {
>       const APInt &C1 = N1C->getAPIntValue();
>
>       switch (Cond) {
> @@ -1250,8 +1250,8 @@
>       }
>     }
>   }
> -  if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
> -    if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) {
> +  if (ConstantFPSDNode *N1C =  
> dyn_cast<ConstantFPSDNode>(N1.getNode())) {
> +    if (ConstantFPSDNode *N2C =  
> dyn_cast<ConstantFPSDNode>(N2.getNode())) {
>       // No compile time operations on this type yet.
>       if (N1C->getValueType(0) == MVT::ppcf128)
>         return SDValue();
> @@ -1572,7 +1572,7 @@
>     return;
>   }
>   case ISD::LOAD: {
> -    if (ISD::isZEXTLoad(Op.Val)) {
> +    if (ISD::isZEXTLoad(Op.getNode())) {
>       LoadSDNode *LD = cast<LoadSDNode>(Op);
>       MVT VT = LD->getMemoryVT();
>       unsigned MemBits = VT.getSizeInBits();
> @@ -2024,7 +2024,7 @@
>   if (V.getOpcode() == ISD::BUILD_VECTOR)
>     return V.getOperand(Index);
>   if (V.getOpcode() == ISD::VECTOR_SHUFFLE)
> -    return getShuffleScalarElt(V.Val, Index);
> +    return getShuffleScalarElt(V.getNode(), Index);
>   return SDValue();
> }
>
> @@ -2050,7 +2050,7 @@
>
> SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue  
> Operand) {
>   // Constant fold unary operations with an integer constant operand.
> -  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) {
> +  if (ConstantSDNode *C =  
> dyn_cast<ConstantSDNode>(Operand.getNode())) {
>     const APInt &Val = C->getAPIntValue();
>     unsigned BitWidth = VT.getSizeInBits();
>     switch (Opcode) {
> @@ -2091,7 +2091,7 @@
>   }
>
>   // Constant fold unary operations with a floating point constant  
> operand.
> -  if (ConstantFPSDNode *C =  
> dyn_cast<ConstantFPSDNode>(Operand.Val)) {
> +  if (ConstantFPSDNode *C =  
> dyn_cast<ConstantFPSDNode>(Operand.getNode())) {
>     APFloat V = C->getValueAPF();    // make copy
>     if (VT != MVT::ppcf128 && Operand.getValueType() !=  
> MVT::ppcf128) {
>       switch (Opcode) {
> @@ -2130,7 +2130,7 @@
>     }
>   }
>
> -  unsigned OpOpcode = Operand.Val->getOpcode();
> +  unsigned OpOpcode = Operand.getNode()->getOpcode();
>   switch (Opcode) {
>   case ISD::TokenFactor:
>   case ISD::CONCAT_VECTORS:
> @@ -2150,7 +2150,7 @@
>     assert(Operand.getValueType().bitsLT(VT)
>            && "Invalid sext node, dst < src!");
>     if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
> -      return getNode(OpOpcode, VT, Operand.Val->getOperand(0));
> +      return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0));
>     break;
>   case ISD::ZERO_EXTEND:
>     assert(VT.isInteger() && Operand.getValueType().isInteger() &&
> @@ -2159,7 +2159,7 @@
>     assert(Operand.getValueType().bitsLT(VT)
>            && "Invalid zext node, dst < src!");
>     if (OpOpcode == ISD::ZERO_EXTEND)   // (zext (zext x)) -> (zext x)
> -      return getNode(ISD::ZERO_EXTEND, VT, Operand.Val- 
> >getOperand(0));
> +      return getNode(ISD::ZERO_EXTEND, VT, Operand.getNode()- 
> >getOperand(0));
>     break;
>   case ISD::ANY_EXTEND:
>     assert(VT.isInteger() && Operand.getValueType().isInteger() &&
> @@ -2169,7 +2169,7 @@
>            && "Invalid anyext node, dst < src!");
>     if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND)
>       // (ext (zext x)) -> (zext x)  and  (ext (sext x)) -> (sext x)
> -      return getNode(OpOpcode, VT, Operand.Val->getOperand(0));
> +      return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0));
>     break;
>   case ISD::TRUNCATE:
>     assert(VT.isInteger() && Operand.getValueType().isInteger() &&
> @@ -2178,16 +2178,16 @@
>     assert(Operand.getValueType().bitsGT(VT)
>            && "Invalid truncate node, src < dst!");
>     if (OpOpcode == ISD::TRUNCATE)
> -      return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0));
> +      return getNode(ISD::TRUNCATE, VT, Operand.getNode()- 
> >getOperand(0));
>     else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode ==  
> ISD::SIGN_EXTEND ||
>              OpOpcode == ISD::ANY_EXTEND) {
>       // If the source is smaller than the dest, we still need an  
> extend.
> -      if (Operand.Val->getOperand(0).getValueType().bitsLT(VT))
> -        return getNode(OpOpcode, VT, Operand.Val->getOperand(0));
> -      else if (Operand.Val->getOperand(0).getValueType().bitsGT(VT))
> -        return getNode(ISD::TRUNCATE, VT, Operand.Val- 
> >getOperand(0));
> +      if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT))
> +        return getNode(OpOpcode, VT, Operand.getNode()- 
> >getOperand(0));
> +      else if (Operand.getNode()- 
> >getOperand(0).getValueType().bitsGT(VT))
> +        return getNode(ISD::TRUNCATE, VT, Operand.getNode()- 
> >getOperand(0));
>       else
> -        return Operand.Val->getOperand(0);
> +        return Operand.getNode()->getOperand(0);
>     }
>     break;
>   case ISD::BIT_CONVERT:
> @@ -2215,14 +2215,14 @@
>     break;
>   case ISD::FNEG:
>     if (OpOpcode == ISD::FSUB)   // -(X-Y) -> (Y-X)
> -      return getNode(ISD::FSUB, VT, Operand.Val->getOperand(1),
> -                     Operand.Val->getOperand(0));
> +      return getNode(ISD::FSUB, VT, Operand.getNode()->getOperand(1),
> +                     Operand.getNode()->getOperand(0));
>     if (OpOpcode == ISD::FNEG)  // --X -> X
> -      return Operand.Val->getOperand(0);
> +      return Operand.getNode()->getOperand(0);
>     break;
>   case ISD::FABS:
>     if (OpOpcode == ISD::FNEG)  // abs(-X) -> abs(X)
> -      return getNode(ISD::FABS, VT, Operand.Val->getOperand(0));
> +      return getNode(ISD::FABS, VT, Operand.getNode()- 
> >getOperand(0));
>     break;
>   }
>
> @@ -2252,8 +2252,8 @@
>
> SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
>                               SDValue N1, SDValue N2) {
> -  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
> -  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
> +  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
> +  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
>   switch (Opcode) {
>   default: break;
>   case ISD::TokenFactor:
> @@ -2268,8 +2268,8 @@
>     // one big BUILD_VECTOR.
>     if (N1.getOpcode() == ISD::BUILD_VECTOR &&
>         N2.getOpcode() == ISD::BUILD_VECTOR) {
> -      SmallVector<SDValue, 16> Elts(N1.Val->op_begin(), N1.Val- 
> >op_end());
> -      Elts.insert(Elts.end(), N2.Val->op_begin(), N2.Val->op_end());
> +      SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(),  
> N1.getNode()->op_end());
> +      Elts.insert(Elts.end(), N2.getNode()->op_begin(),  
> N2.getNode()->op_end());
>       return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size());
>     }
>     break;
> @@ -2471,8 +2471,8 @@
>   }
>
>   // Constant fold FP operations.
> -  ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val);
> -  ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val);
> +  ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode());
> +  ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode());
>   if (N1CFP) {
>     if (!N2CFP && isCommutativeBinOp(Opcode)) {
>       // Cannonicalize constant to RHS if commutative
> @@ -2615,8 +2615,8 @@
> SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
>                               SDValue N1, SDValue N2, SDValue N3) {
>   // Perform various simplifications.
> -  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
> -  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
> +  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
> +  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
>   switch (Opcode) {
>   case ISD::CONCAT_VECTORS:
>     // A CONCAT_VECTOR with all operands BUILD_VECTOR can be  
> simplified to
> @@ -2624,16 +2624,16 @@
>     if (N1.getOpcode() == ISD::BUILD_VECTOR &&
>         N2.getOpcode() == ISD::BUILD_VECTOR &&
>         N3.getOpcode() == ISD::BUILD_VECTOR) {
> -      SmallVector<SDValue, 16> Elts(N1.Val->op_begin(), N1.Val- 
> >op_end());
> -      Elts.insert(Elts.end(), N2.Val->op_begin(), N2.Val->op_end());
> -      Elts.insert(Elts.end(), N3.Val->op_begin(), N3.Val->op_end());
> +      SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(),  
> N1.getNode()->op_end());
> +      Elts.insert(Elts.end(), N2.getNode()->op_begin(),  
> N2.getNode()->op_end());
> +      Elts.insert(Elts.end(), N3.getNode()->op_begin(),  
> N3.getNode()->op_end());
>       return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size());
>     }
>     break;
>   case ISD::SETCC: {
>     // Use FoldSetCC to simplify SETCC's.
>     SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)- 
> >get());
> -    if (Simp.Val) return Simp;
> +    if (Simp.getNode()) return Simp;
>     break;
>   }
>   case ISD::SELECT:
> @@ -3049,7 +3049,7 @@
>     SDValue Result =
>       getMemcpyLoadsAndStores(*this, Chain, Dst, Src, ConstantSize- 
> >getValue(),
>                               Align, false, DstSV, DstSVOff, SrcSV,  
> SrcSVOff);
> -    if (Result.Val)
> +    if (Result.getNode())
>       return Result;
>   }
>
> @@ -3059,7 +3059,7 @@
>     TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align,
>                                 AlwaysInline,
>                                 DstSV, DstSVOff, SrcSV, SrcSVOff);
> -  if (Result.Val)
> +  if (Result.getNode())
>     return Result;
>
>   // If we really need inline code and the target declined to  
> provide it,
> @@ -3103,7 +3103,7 @@
>     SDValue Result =
>       getMemmoveLoadsAndStores(*this, Chain, Dst, Src, ConstantSize- 
> >getValue(),
>                                Align, false, DstSV, DstSVOff, SrcSV,  
> SrcSVOff);
> -    if (Result.Val)
> +    if (Result.getNode())
>       return Result;
>   }
>
> @@ -3112,7 +3112,7 @@
>   SDValue Result =
>     TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align,
>                                  DstSV, DstSVOff, SrcSV, SrcSVOff);
> -  if (Result.Val)
> +  if (Result.getNode())
>     return Result;
>
>   // Emit a library call.
> @@ -3146,7 +3146,7 @@
>     SDValue Result =
>       getMemsetStores(*this, Chain, Dst, Src, ConstantSize- 
> >getValue(), Align,
>                       DstSV, DstSVOff);
> -    if (Result.Val)
> +    if (Result.getNode())
>       return Result;
>   }
>
> @@ -3155,7 +3155,7 @@
>   SDValue Result =
>     TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align,
>                                 DstSV, DstSVOff);
> -  if (Result.Val)
> +  if (Result.getNode())
>     return Result;
>
>   // Emit a library call.
> @@ -3737,7 +3737,7 @@
> /// input node is returned.  As a degenerate case, if you specify  
> the same
> /// input operands as the node already has, the input node is  
> returned.
> SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) {
> -  SDNode *N = InN.Val;
> +  SDNode *N = InN.getNode();
>   assert(N->getNumOperands() == 1 && "Update with wrong number of  
> operands");
>
>   // Check to see if there is no change.
> @@ -3756,7 +3756,7 @@
>   N->OperandList[0].getVal()->removeUser(0, N);
>   N->OperandList[0] = Op;
>   N->OperandList[0].setUser(N);
> -  Op.Val->addUser(0, N);
> +  Op.getNode()->addUser(0, N);
>
>   // If this gets put into a CSE map, add it.
>   if (InsertPos) CSEMap.InsertNode(N, InsertPos);
> @@ -3765,7 +3765,7 @@
>
> SDValue SelectionDAG::
> UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) {
> -  SDNode *N = InN.Val;
> +  SDNode *N = InN.getNode();
>   assert(N->getNumOperands() == 2 && "Update with wrong number of  
> operands");
>
>   // Check to see if there is no change.
> @@ -3786,13 +3786,13 @@
>     N->OperandList[0].getVal()->removeUser(0, N);
>     N->OperandList[0] = Op1;
>     N->OperandList[0].setUser(N);
> -    Op1.Val->addUser(0, N);
> +    Op1.getNode()->addUser(0, N);
>   }
>   if (N->OperandList[1] != Op2) {
>     N->OperandList[1].getVal()->removeUser(1, N);
>     N->OperandList[1] = Op2;
>     N->OperandList[1].setUser(N);
> -    Op2.Val->addUser(1, N);
> +    Op2.getNode()->addUser(1, N);
>   }
>
>   // If this gets put into a CSE map, add it.
> @@ -3822,7 +3822,7 @@
>
> SDValue SelectionDAG::
> UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) {
> -  SDNode *N = InN.Val;
> +  SDNode *N = InN.getNode();
>   assert(N->getNumOperands() == NumOps &&
>          "Update with wrong number of operands");
>
> @@ -3853,7 +3853,7 @@
>       N->OperandList[i].getVal()->removeUser(i, N);
>       N->OperandList[i] = Ops[i];
>       N->OperandList[i].setUser(N);
> -      Ops[i].Val->addUser(i, N);
> +      Ops[i].getNode()->addUser(i, N);
>     }
>   }
>
> @@ -4134,70 +4134,70 @@
> /// node of the specified opcode and operands, it returns that node  
> instead of
> /// the current one.
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) {
> -  return getNode(~Opcode, VT).Val;
> +  return getNode(~Opcode, VT).getNode();
> }
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue  
> Op1) {
> -  return getNode(~Opcode, VT, Op1).Val;
> +  return getNode(~Opcode, VT, Op1).getNode();
> }
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
>                                     SDValue Op1, SDValue Op2) {
> -  return getNode(~Opcode, VT, Op1, Op2).Val;
> +  return getNode(~Opcode, VT, Op1, Op2).getNode();
> }
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
>                                     SDValue Op1, SDValue Op2,
>                                     SDValue Op3) {
> -  return getNode(~Opcode, VT, Op1, Op2, Op3).Val;
> +  return getNode(~Opcode, VT, Op1, Op2, Op3).getNode();
> }
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
> -  return getNode(~Opcode, VT, Ops, NumOps).Val;
> +  return getNode(~Opcode, VT, Ops, NumOps).getNode();
> }
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT  
> VT2) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2);
>   SDValue Op;
> -  return getNode(~Opcode, VTs, 2, &Op, 0).Val;
> +  return getNode(~Opcode, VTs, 2, &Op, 0).getNode();
> }
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>                                     MVT VT2, SDValue Op1) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2);
> -  return getNode(~Opcode, VTs, 2, &Op1, 1).Val;
> +  return getNode(~Opcode, VTs, 2, &Op1, 1).getNode();
> }
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>                                     MVT VT2, SDValue Op1,
>                                     SDValue Op2) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2);
>   SDValue Ops[] = { Op1, Op2 };
> -  return getNode(~Opcode, VTs, 2, Ops, 2).Val;
> +  return getNode(~Opcode, VTs, 2, Ops, 2).getNode();
> }
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>                                     MVT VT2, SDValue Op1,
>                                     SDValue Op2, SDValue Op3) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2);
>   SDValue Ops[] = { Op1, Op2, Op3 };
> -  return getNode(~Opcode, VTs, 2, Ops, 3).Val;
> +  return getNode(~Opcode, VTs, 2, Ops, 3).getNode();
> }
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2);
> -  return getNode(~Opcode, VTs, 2, Ops, NumOps).Val;
> +  return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode();
> }
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT  
> VT2, MVT VT3,
>                                     SDValue Op1, SDValue Op2) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
>   SDValue Ops[] = { Op1, Op2 };
> -  return getNode(~Opcode, VTs, 3, Ops, 2).Val;
> +  return getNode(~Opcode, VTs, 3, Ops, 2).getNode();
> }
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT  
> VT2, MVT VT3,
>                                     SDValue Op1, SDValue Op2,
>                                     SDValue Op3) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
>   SDValue Ops[] = { Op1, Op2, Op3 };
> -  return getNode(~Opcode, VTs, 3, Ops, 3).Val;
> +  return getNode(~Opcode, VTs, 3, Ops, 3).getNode();
> }
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT  
> VT2, MVT VT3,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
> -  return getNode(~Opcode, VTs, 3, Ops, NumOps).Val;
> +  return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
> }
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>                                     MVT VT2, MVT VT3, MVT VT4,
> @@ -4208,14 +4208,14 @@
>   VTList.push_back(VT3);
>   VTList.push_back(VT4);
>   const MVT *VTs = getNodeValueTypes(VTList);
> -  return getNode(~Opcode, VTs, 4, Ops, NumOps).Val;
> +  return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode();
> }
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
>                                     const std::vector<MVT> &ResultTys,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
>   const MVT *VTs = getNodeValueTypes(ResultTys);
>   return getNode(~Opcode, VTs, ResultTys.size(),
> -                 Ops, NumOps).Val;
> +                 Ops, NumOps).getNode();
> }
>
> /// getNodeIfExists - Get the specified node if it's already  
> available, or
> @@ -4240,10 +4240,10 @@
> ///
> void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To,
>                                       DAGUpdateListener  
> *UpdateListener) {
> -  SDNode *From = FromN.Val;
> +  SDNode *From = FromN.getNode();
>   assert(From->getNumValues() == 1 && FromN.getResNo() == 0 &&
>          "Cannot replace with this method!");
> -  assert(From != To.Val && "Cannot replace uses of with self");
> +  assert(From != To.getNode() && "Cannot replace uses of with self");
>
>   while (!From->use_empty()) {
>     SDNode::use_iterator UI = From->use_begin();
> @@ -4258,7 +4258,7 @@
>         From->removeUser(operandNum, U);
>         *I = To;
>         I->setUser(U);
> -        To.Val->addUser(operandNum, U);
> +        To.getNode()->addUser(operandNum, U);
>       }
>
>     // Now that we have modified U, add it back to the CSE maps.  If  
> it already
> @@ -4305,7 +4305,7 @@
>          I != E; ++I, ++operandNum)
>       if (I->getVal() == From) {
>         From->removeUser(operandNum, U);
> -        I->getVal() = To;
> +        I->getSDValue().setNode(To);
>         To->addUser(operandNum, U);
>       }
>
> @@ -4351,7 +4351,7 @@
>         From->removeUser(operandNum, U);
>         *I = ToOp;
>         I->setUser(U);
> -        ToOp.Val->addUser(operandNum, U);
> +        ToOp.getNode()->addUser(operandNum, U);
>       }
>
>     // Now that we have modified U, add it back to the CSE maps.  If  
> it already
> @@ -4372,7 +4372,7 @@
> }
>
> /// ReplaceAllUsesOfValueWith - Replace any uses of From with To,  
> leaving
> -/// uses of other values produced by From.Val alone.  The Deleted  
> vector is
> +/// uses of other values produced by From.getVal() alone.  The  
> Deleted vector is
> /// handled the same way as for ReplaceAllUsesWith.
> void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To,
>                                              DAGUpdateListener  
> *UpdateListener){
> @@ -4380,14 +4380,14 @@
>   if (From == To) return;
>
>   // Handle the simple, trivial, case efficiently.
> -  if (From.Val->getNumValues() == 1) {
> +  if (From.getNode()->getNumValues() == 1) {
>     ReplaceAllUsesWith(From, To, UpdateListener);
>     return;
>   }
>
> -  // Get all of the users of From.Val.  We want these in a nice,
> +  // Get all of the users of From.getNode().  We want these in a  
> nice,
>   // deterministically ordered and uniqued set, so we use a  
> SmallSetVector.
> -  SmallSetVector<SDNode*, 16> Users(From.Val->use_begin(), From.Val- 
> >use_end());
> +  SmallSetVector<SDNode*, 16> Users(From.getNode()->use_begin(),  
> From.getNode()->use_end());
>
>   while (!Users.empty()) {
>     // We know that this user uses some value of From.  If it is the  
> right
> @@ -4410,10 +4410,10 @@
>     // Update all operands that match "From" in case there are  
> multiple uses.
>     for (; Op != E; ++Op) {
>       if (*Op == From) {
> -        From.Val->removeUser(Op-User->op_begin(), User);
> +        From.getNode()->removeUser(Op-User->op_begin(), User);
>         *Op = To;
>         Op->setUser(User);
> -        To.Val->addUser(Op-User->op_begin(), User);
> +        To.getNode()->addUser(Op-User->op_begin(), User);
>       }
>     }
>
> @@ -4437,7 +4437,7 @@
> }
>
> /// ReplaceAllUsesOfValuesWith - Replace any uses of From with To,  
> leaving
> -/// uses of other values produced by From.Val alone.  The same  
> value may
> +/// uses of other values produced by From.getVal() alone.  The same  
> value may
> /// appear in both the From and To list.  The Deleted vector is
> /// handled the same way as for ReplaceAllUsesWith.
> void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From,
> @@ -4450,8 +4450,8 @@
>
>   SmallVector<std::pair<SDNode *, unsigned>, 16> Users;
>   for (unsigned i = 0; i != Num; ++i)
> -    for (SDNode::use_iterator UI = From[i].Val->use_begin(),
> -         E = From[i].Val->use_end(); UI != E; ++UI)
> +    for (SDNode::use_iterator UI = From[i].getNode()->use_begin(),
> +         E = From[i].getNode()->use_end(); UI != E; ++UI)
>       Users.push_back(std::make_pair(*UI, i));
>
>   while (!Users.empty()) {
> @@ -4476,10 +4476,10 @@
>     // Update all operands that match "From" in case there are  
> multiple uses.
>     for (; Op != E; ++Op) {
>       if (*Op == From[i]) {
> -        From[i].Val->removeUser(Op-User->op_begin(), User);
> +        From[i].getNode()->removeUser(Op-User->op_begin(), User);
>         *Op = To[i];
>         Op->setUser(User);
> -        To[i].Val->addUser(Op-User->op_begin(), User);
> +        To[i].getNode()->addUser(Op-User->op_begin(), User);
>       }
>     }
>
> @@ -4617,7 +4617,7 @@
>
>   // Check if the memory reference references a frame index
>   const FrameIndexSDNode *FI =
> -  dyn_cast<const FrameIndexSDNode>(getBasePtr().Val);
> +  dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode());
>   if (!getSrcValue() && FI)
>     return MachineMemOperand(PseudoSourceValue::getFixedStack(FI- 
> >getIndex()),
>                              Flags, 0, Size, getAlignment());
> @@ -4746,7 +4746,7 @@
>     return;
>
>   for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; + 
> +i) {
> -    SDNode *Op = N->getOperand(i).Val;
> +    SDNode *Op = N->getOperand(i).getNode();
>     if (Op == P) {
>       found = true;
>       return;
> @@ -5115,13 +5115,13 @@
>   OS << " ";
>   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
>     if (i) OS << ", ";
> -    OS << (void*)getOperand(i).Val;
> +    OS << (void*)getOperand(i).getNode();
>     if (unsigned RN = getOperand(i).getResNo())
>       OS << ":" << RN;
>   }
>
>   if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) {
> -    SDNode *Mask = getOperand(2).Val;
> +    SDNode *Mask = getOperand(2).getNode();
>     OS << "<";
>     for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) {
>       if (i) OS << ",";
> @@ -5262,11 +5262,11 @@
>
> static void DumpNodes(const SDNode *N, unsigned indent, const  
> SelectionDAG *G) {
>   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
> -    if (N->getOperand(i).Val->hasOneUse())
> -      DumpNodes(N->getOperand(i).Val, indent+2, G);
> +    if (N->getOperand(i).getNode()->hasOneUse())
> +      DumpNodes(N->getOperand(i).getNode(), indent+2, G);
>     else
>       cerr << "\n" << std::string(indent+2, ' ')
> -           << (void*)N->getOperand(i).Val << ": <multiple use>";
> +           << (void*)N->getOperand(i).getNode() << ": <multiple  
> use>";
>
>
>   cerr << "\n" << std::string(indent, ' ');
> @@ -5279,11 +5279,11 @@
>   for (allnodes_const_iterator I = allnodes_begin(), E =  
> allnodes_end();
>        I != E; ++I) {
>     const SDNode *N = I;
> -    if (!N->hasOneUse() && N != getRoot().Val)
> +    if (!N->hasOneUse() && N != getRoot().getNode())
>       DumpNodes(N, 2, this);
>   }
>
> -  if (getRoot().Val) DumpNodes(getRoot().Val, 2, this);
> +  if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this);
>
>   cerr << "\n\n";
> }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Aug  
> 28 16:40:38 2008
> @@ -784,8 +784,8 @@
>     if (Root.getOpcode() != ISD::EntryToken) {
>       unsigned i = 0, e = PendingExports.size();
>       for (; i != e; ++i) {
> -        assert(PendingExports[i].Val->getNumOperands() > 1);
> -        if (PendingExports[i].Val->getOperand(0) == Root)
> +        assert(PendingExports[i].getNode()->getNumOperands() > 1);
> +        if (PendingExports[i].getNode()->getOperand(0) == Root)
>           break;  // Don't add the root if we already indirectly  
> depend on it.
>       }
>
> @@ -824,7 +824,7 @@
>
>   void setValue(const Value *V, SDValue NewN) {
>     SDValue &N = NodeMap[V];
> -    assert(N.Val == 0 && "Already set a value for this node!");
> +    assert(N.getNode() == 0 && "Already set a value for this node!");
>     N = NewN;
>   }
>
> @@ -1286,7 +1286,7 @@
>
> SDValue SelectionDAGLowering::getValue(const Value *V) {
>   SDValue &N = NodeMap[V];
> -  if (N.Val) return N;
> +  if (N.getNode()) return N;
>
>   if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
>     MVT VT = TLI.getValueType(V->getType(), true);
> @@ -1310,7 +1310,7 @@
>     if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
>       visit(CE->getOpcode(), *CE);
>       SDValue N1 = NodeMap[V];
> -      assert(N1.Val && "visit didn't populate the ValueMap!");
> +      assert(N1.getNode() && "visit didn't populate the ValueMap!");
>       return N1;
>     }
>
> @@ -1318,7 +1318,7 @@
>       SmallVector<SDValue, 4> Constants;
>       for (User::const_op_iterator OI = C->op_begin(), OE = C- 
> >op_end();
>            OI != OE; ++OI) {
> -        SDNode *Val = getValue(*OI).Val;
> +        SDNode *Val = getValue(*OI).getNode();
>         for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
>           Constants.push_back(SDValue(Val, i));
>       }
> @@ -1428,7 +1428,7 @@
>       else if (F->paramHasAttr(0, ParamAttr::ZExt))
>         ExtendKind = ISD::ZERO_EXTEND;
>
> -      getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.getResNo() + j),
> +      getCopyToParts(DAG, SDValue(RetOp.getNode(), RetOp.getResNo()  
> + j),
>                      &Parts[0], NumParts, PartVT, ExtendKind);
>
>       for (unsigned i = 0; i < NumParts; ++i) {
> @@ -2855,15 +2855,15 @@
>   // Copy the beginning value(s) from the original aggregate.
>   for (; i != LinearIndex; ++i)
>     Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
> -                SDValue(Agg.Val, Agg.getResNo() + i);
> +                SDValue(Agg.getNode(), Agg.getResNo() + i);
>   // Copy values from the inserted value(s).
>   for (; i != LinearIndex + NumValValues; ++i)
>     Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
> -                SDValue(Val.Val, Val.getResNo() + i - LinearIndex);
> +                SDValue(Val.getNode(), Val.getResNo() + i -  
> LinearIndex);
>   // Copy remaining value(s) from the original aggregate.
>   for (; i != NumAggValues; ++i)
>     Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
> -                SDValue(Agg.Val, Agg.getResNo() + i);
> +                SDValue(Agg.getNode(), Agg.getResNo() + i);
>
>   setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0],  
> NumAggValues),
>                                   &Values[0], NumAggValues));
> @@ -2888,8 +2888,8 @@
>   // Copy out the selected value(s).
>   for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
>     Values[i - LinearIndex] =
> -      OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val- 
> >getValueType(Agg.getResNo() + i)) :
> -                   SDValue(Agg.Val, Agg.getResNo() + i);
> +      OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.getNode()- 
> >getValueType(Agg.getResNo() + i)) :
> +                   SDValue(Agg.getNode(), Agg.getResNo() + i);
>
>   setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0],  
> NumValValues),
>                                   &Values[0], NumValValues));
> @@ -3084,7 +3084,7 @@
>   bool isVolatile = I.isVolatile();
>   unsigned Alignment = I.getAlignment();
>   for (unsigned i = 0; i != NumValues; ++i)
> -    Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.getResNo()  
> + i),
> +    Chains[i] = DAG.getStore(Root, SDValue(Src.getNode(),  
> Src.getResNo() + i),
>                              DAG.getNode(ISD::ADD, PtrVT, Ptr,
>                                          DAG.getConstant(Offsets[i],  
> PtrVT)),
>                              PtrV, Offsets[i],
> @@ -3154,7 +3154,7 @@
>                          &Ops[0], Ops.size());
>
>   if (HasChain) {
> -    SDValue Chain = Result.getValue(Result.Val->getNumValues()-1);
> +    SDValue Chain = Result.getValue(Result.getNode()- 
> >getNumValues()-1);
>     if (OnlyLoad)
>       PendingLoads.push_back(Chain);
>     else
> @@ -3621,7 +3621,7 @@
>       Value *Alloca = I.getOperand(1);
>       Constant *TypeMap = cast<Constant>(I.getOperand(2));
>
> -      FrameIndexSDNode *FI =  
> cast<FrameIndexSDNode>(getValue(Alloca).Val);
> +      FrameIndexSDNode *FI =  
> cast<FrameIndexSDNode>(getValue(Alloca).getNode());
>       GFI->addStackRoot(FI->getIndex(), TypeMap);
>     }
>     return 0;
> @@ -4751,7 +4751,7 @@
>
>   // Finish up input operands.
>   AsmNodeOperands[0] = Chain;
> -  if (Flag.Val) AsmNodeOperands.push_back(Flag);
> +  if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
>
>   Chain = DAG.getNode(ISD::INLINEASM,
>                       DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
> @@ -4770,7 +4770,7 @@
>     // bit_convert.
>     if (const StructType *ResSTy =  
> dyn_cast<StructType>(CS.getType())) {
>       for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; + 
> +i) {
> -        if (Val.Val->getValueType(i).isVector())
> +        if (Val.getNode()->getValueType(i).isVector())
>           Val = DAG.getNode(ISD::BIT_CONVERT,
>                             TLI.getValueType(ResSTy- 
> >getElementType(i)), Val);
>       }
> @@ -4963,7 +4963,7 @@
>   // Create the node.
>   SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
>                                DAG.getVTList(&RetVals[0],  
> RetVals.size()),
> -                               &Ops[0], Ops.size()).Val;
> +                               &Ops[0], Ops.size()).getNode();
>
>   // Prelower FORMAL_ARGUMENTS.  This isn't required for  
> functionality, but
>   // allows exposing the loads that may be part of the argument  
> access to the
> @@ -4972,18 +4972,18 @@
>
>   // The number of results should match up, except that the lowered  
> one may have
>   // an extra flag result.
> -  assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
> -          (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
> +  assert((Result->getNumValues() == TmpRes.getNode()- 
> >getNumValues() ||
> +          (Result->getNumValues()+1 == TmpRes.getNode()- 
> >getNumValues() &&
>            TmpRes.getValue(Result->getNumValues()).getValueType() ==  
> MVT::Flag))
>          && "Lowering produced unexpected number of results!");
>
>   // The FORMAL_ARGUMENTS node itself is likely no longer needed.
> -  if (Result != TmpRes.Val && Result->use_empty()) {
> +  if (Result != TmpRes.getNode() && Result->use_empty()) {
>     HandleSDNode Dummy(DAG.getRoot());
>     DAG.RemoveDeadNode(Result);
>   }
>
> -  Result = TmpRes.Val;
> +  Result = TmpRes.getNode();
>
>   unsigned NumArgRegs = Result->getNumValues() - 1;
>   DAG.setRoot(SDValue(Result, NumArgRegs));
> @@ -5044,7 +5044,7 @@
>          Value != NumValues; ++Value) {
>       MVT VT = ValueVTs[Value];
>       const Type *ArgTy = VT.getTypeForMVT();
> -      SDValue Op = SDValue(Args[i].Node.Val,  
> Args[i].Node.getResNo() + Value);
> +      SDValue Op = SDValue(Args[i].Node.getNode(),  
> Args[i].Node.getResNo() + Value);
>       ISD::ArgFlagsTy Flags;
>       unsigned OriginalAlignment =
>         getTargetData()->getABITypeAlignment(ArgTy);
> @@ -5333,7 +5333,7 @@
>
>   // Find RET node.
>   if (Terminator.getOpcode() == ISD::RET) {
> -    Ret = Terminator.Val;
> +    Ret = Terminator.getNode();
>   }
>
>   // Fix tail call attribute of CALL nodes.
> @@ -5355,8 +5355,8 @@
>         // Not eligible. Mark CALL node as non tail call.
>         SmallVector<SDValue, 32> Ops;
>         unsigned idx=0;
> -        for(SDNode::op_iterator I =OpCall.Val->op_begin(),
> -              E = OpCall.Val->op_end(); I != E; I++, idx++) {
> +        for(SDNode::op_iterator I =OpCall.getNode()->op_begin(),
> +              E = OpCall.getNode()->op_end(); I != E; I++, idx++) {
>           if (idx!=3)
>             Ops.push_back(*I);
>           else
> @@ -5369,8 +5369,8 @@
>         SmallVector<SDValue, 32> Ops;
>         SDValue Chain = OpCall.getOperand(0), InFlag;
>         unsigned idx=0;
> -        for(SDNode::op_iterator I = OpCall.Val->op_begin(),
> -              E = OpCall.Val->op_end(); I != E; I++, idx++) {
> +        for(SDNode::op_iterator I = OpCall.getNode()->op_begin(),
> +              E = OpCall.getNode()->op_end(); I != E; I++, idx++) {
>           SDValue Arg = *I;
>           if (idx > 4 && (idx % 2)) {
>             bool isByVal =  
> cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
> @@ -5557,7 +5557,7 @@
>   SmallPtrSet<SDNode*, 128> VisitedNodes;
>   SmallVector<SDNode*, 128> Worklist;
>
> -  Worklist.push_back(CurDAG->getRoot().Val);
> +  Worklist.push_back(CurDAG->getRoot().getNode());
>
>   APInt Mask;
>   APInt KnownZero;
> @@ -5574,7 +5574,7 @@
>     // Otherwise, add all chain operands to the worklist.
>     for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
>       if (N->getOperand(i).getValueType() == MVT::Other)
> -        Worklist.push_back(N->getOperand(i).Val);
> +        Worklist.push_back(N->getOperand(i).getNode());
>
>     // If this is a CopyToReg with a vreg dest, process it.
>     if (N->getOpcode() != ISD::CopyToReg)
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Thu  
> Aug 28 16:40:38 2008
> @@ -109,8 +109,8 @@
>     static void addCustomGraphFeatures(SelectionDAG *G,
>                                        GraphWriter<SelectionDAG*>  
> &GW) {
>       GW.emitSimpleNode(0, "plaintext=circle", "GraphRoot");
> -      if (G->getRoot().Val)
> -        GW.emitEdge(0, -1, G->getRoot().Val, G->getRoot().getResNo(),
> +      if (G->getRoot().getNode())
> +        GW.emitEdge(0, -1, G->getRoot().getNode(), G- 
> >getRoot().getResNo(),
>                     "color=blue,style=dashed");
>     }
>   };
> @@ -356,7 +356,7 @@
>     static void addCustomGraphFeatures(ScheduleDAG *G,
>                                        GraphWriter<ScheduleDAG*>  
> &GW) {
>       GW.emitSimpleNode(0, "plaintext=circle", "GraphRoot");
> -      const SDNode *N = G->DAG.getRoot().Val;
> +      const SDNode *N = G->DAG.getRoot().getNode();
>       if (N && N->getNodeId() != -1)
>         GW.emitEdge(0, -1, &G->SUnits[N->getNodeId()], -1,
>                     "color=blue,style=dashed");
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Aug  
> 28 16:40:38 2008
> @@ -674,7 +674,7 @@
>   KnownZero = KnownOne = APInt(BitWidth, 0);
>
>   // Other users may use these bits.
> -  if (!Op.Val->hasOneUse()) {
> +  if (!Op.getNode()->hasOneUse()) {
>     if (Depth != 0) {
>       // If not at the root, Just compute the KnownZero/KnownOne  
> bits to
>       // simplify things downstream.
> @@ -1131,7 +1131,7 @@
>
>     // If the input is only used by this truncate, see if we can  
> shrink it based
>     // on the known demanded bits.
> -    if (Op.getOperand(0).Val->hasOneUse()) {
> +    if (Op.getOperand(0).getNode()->hasOneUse()) {
>       SDValue In = Op.getOperand(0);
>       unsigned InBitWidth = In.getValueSizeInBits();
>       switch (In.getOpcode()) {
> @@ -1259,9 +1259,9 @@
>   case ISD::SETTRUE2:  return DAG.getConstant(1, VT);
>   }
>
> -  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
> +  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
>     const APInt &C1 = N1C->getAPIntValue();
> -    if (isa<ConstantSDNode>(N0.Val)) {
> +    if (isa<ConstantSDNode>(N0.getNode())) {
>       return DAG.FoldSetCC(VT, N0, N1, Cond);
>     } else {
>       // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this  
> is an
> @@ -1356,7 +1356,7 @@
>                                DAG.getConstant(Imm, Op0Ty));
>         }
>         if (!DCI.isCalledByLegalizer())
> -          DCI.AddToWorklist(ZextOp.Val);
> +          DCI.AddToWorklist(ZextOp.getNode());
>         // Otherwise, make this a use of a zext.
>         return DAG.getSetCC(VT, ZextOp,
>                             DAG.getConstant(C1 & APInt::getLowBitsSet(
> @@ -1493,16 +1493,16 @@
>           }
>         }
>     }
> -  } else if (isa<ConstantSDNode>(N0.Val)) {
> +  } else if (isa<ConstantSDNode>(N0.getNode())) {
>       // Ensure that the constant occurs on the RHS.
>     return DAG.getSetCC(VT, N1, N0,  
> ISD::getSetCCSwappedOperands(Cond));
>   }
>
> -  if (isa<ConstantFPSDNode>(N0.Val)) {
> +  if (isa<ConstantFPSDNode>(N0.getNode())) {
>     // Constant fold or commute setcc.
>     SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond);
> -    if (O.Val) return O;
> -  } else if (ConstantFPSDNode *CFP =  
> dyn_cast<ConstantFPSDNode>(N1.Val)) {
> +    if (O.getNode()) return O;
> +  } else if (ConstantFPSDNode *CFP =  
> dyn_cast<ConstantFPSDNode>(N1.getNode())) {
>     // If the RHS of an FP comparison is a constant, simplify it  
> away in
>     // some cases.
>     if (CFP->getValueAPF().isNaN()) {
> @@ -1564,7 +1564,7 @@
>       if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
>         if (ConstantSDNode *LHSR =  
> dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
>           // Turn (X+C1) == C2 --> X == C2-C1
> -          if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
> +          if (N0.getOpcode() == ISD::ADD && N0.getNode()- 
> >hasOneUse()) {
>             return DAG.getSetCC(VT, N0.getOperand(0),
>                               DAG.getConstant(RHSC->getValue()-LHSR- 
> >getValue(),
>                                 N0.getValueType()), Cond);
> @@ -1585,7 +1585,7 @@
>
>         // Turn (C1-X) == C2 --> X == C1-C2
>         if (ConstantSDNode *SUBC =  
> dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
> -          if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
> +          if (N0.getOpcode() == ISD::SUB && N0.getNode()- 
> >hasOneUse()) {
>             return
>               DAG.getSetCC(VT, N0.getOperand(1),
>                            DAG.getConstant(SUBC->getAPIntValue() -
> @@ -1604,14 +1604,14 @@
>         if (DAG.isCommutativeBinOp(N0.getOpcode()))
>           return DAG.getSetCC(VT, N0.getOperand(0),
>                           DAG.getConstant(0, N0.getValueType()),  
> Cond);
> -        else if (N0.Val->hasOneUse()) {
> +        else if (N0.getNode()->hasOneUse()) {
>           assert(N0.getOpcode() == ISD::SUB && "Unexpected  
> operation!");
>           // (Z-X) == X  --> Z == X<<1
>           SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(),
>                                      N1,
>                                      DAG.getConstant(1,  
> getShiftAmountTy()));
>           if (!DCI.isCalledByLegalizer())
> -            DCI.AddToWorklist(SH.Val);
> +            DCI.AddToWorklist(SH.getNode());
>           return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
>         }
>       }
> @@ -1627,13 +1627,13 @@
>         if (DAG.isCommutativeBinOp(N1.getOpcode())) {
>           return DAG.getSetCC(VT, N1.getOperand(0),
>                           DAG.getConstant(0, N1.getValueType()),  
> Cond);
> -        } else if (N1.Val->hasOneUse()) {
> +        } else if (N1.getNode()->hasOneUse()) {
>           assert(N1.getOpcode() == ISD::SUB && "Unexpected  
> operation!");
>           // X == (Z-X)  --> X<<1 == Z
>           SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
>                                      DAG.getConstant(1,  
> getShiftAmountTy()));
>           if (!DCI.isCalledByLegalizer())
> -            DCI.AddToWorklist(SH.Val);
> +            DCI.AddToWorklist(SH.getNode());
>           return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
>         }
>       }
> @@ -1649,7 +1649,7 @@
>       Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
>       N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1,  
> MVT::i1));
>       if (!DCI.isCalledByLegalizer())
> -        DCI.AddToWorklist(Temp.Val);
> +        DCI.AddToWorklist(Temp.getNode());
>       break;
>     case ISD::SETNE:  // X != Y   -->  (X^Y)
>       N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
> @@ -1659,21 +1659,21 @@
>       Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1,  
> MVT::i1));
>       N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
>       if (!DCI.isCalledByLegalizer())
> -        DCI.AddToWorklist(Temp.Val);
> +        DCI.AddToWorklist(Temp.getNode());
>       break;
>     case ISD::SETLT:  // X <s Y   --> X == 1 & Y == 0  -->  Y^1 & X
>     case ISD::SETUGT: // X >u Y   --> X == 1 & Y == 0  -->  Y^1 & X
>       Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1,  
> MVT::i1));
>       N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
>       if (!DCI.isCalledByLegalizer())
> -        DCI.AddToWorklist(Temp.Val);
> +        DCI.AddToWorklist(Temp.getNode());
>       break;
>     case ISD::SETULE: // X <=u Y  --> X == 0 | Y == 1  -->  X^1 | Y
>     case ISD::SETGE:  // X >=s Y  --> X == 0 | Y == 1  -->  X^1 | Y
>       Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1,  
> MVT::i1));
>       N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
>       if (!DCI.isCalledByLegalizer())
> -        DCI.AddToWorklist(Temp.Val);
> +        DCI.AddToWorklist(Temp.getNode());
>       break;
>     case ISD::SETUGE: // X >=u Y  --> X == 1 | Y == 0  -->  Y^1 | X
>     case ISD::SETLE:  // X <=s Y  --> X == 1 | Y == 0  -->  Y^1 | X
> @@ -1683,7 +1683,7 @@
>     }
>     if (VT != MVT::i1) {
>       if (!DCI.isCalledByLegalizer())
> -        DCI.AddToWorklist(N0.Val);
> +        DCI.AddToWorklist(N0.getNode());
>       // FIXME: If running after legalize, we probably can't do this.
>       N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
>     }
> @@ -1708,13 +1708,13 @@
>   if (N->getOpcode() == ISD::ADD) {
>     SDValue N1 = N->getOperand(0);
>     SDValue N2 = N->getOperand(1);
> -    if (isGAPlusOffset(N1.Val, GA, Offset)) {
> +    if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
>       ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
>       if (V) {
>         Offset += V->getSignExtended();
>         return true;
>       }
> -    } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
> +    } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
>       ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
>       if (V) {
>         Offset += V->getSignExtended();
> @@ -1732,7 +1732,7 @@
> bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base,
>                                        unsigned Bytes, int Dist,
>                                        const MachineFrameInfo *MFI)  
> const {
> -  if (LD->getOperand(0).Val != Base->getOperand(0).Val)
> +  if (LD->getOperand(0).getNode() != Base->getOperand(0).getNode())
>     return false;
>   MVT VT = LD->getValueType(0);
>   if (VT.getSizeInBits() / 8 != Bytes)
> @@ -1755,8 +1755,8 @@
>   GlobalValue *GV2 = NULL;
>   int64_t Offset1 = 0;
>   int64_t Offset2 = 0;
> -  bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
> -  bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
> +  bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1);
> +  bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
>   if (isGA1 && isGA2 && GV1 == GV2)
>     return Offset1 == (Offset2 + Dist*Bytes);
>   return false;
> @@ -1979,7 +1979,7 @@
>     // For example, on X86 we might have an 'rI' constraint.  If the  
> operand
>     // is an integer in the range [0..31] we want to use I (saving a  
> load
>     // of a register), otherwise we must use 'r'.
> -    if (CType == TargetLowering::C_Other && Op.Val) {
> +    if (CType == TargetLowering::C_Other && Op.getNode()) {
>       assert(OpInfo.Codes[i].size() == 1 &&
>              "Unhandled multi-letter 'other' constraint");
>       std::vector<SDValue> ResultOps;
> @@ -2273,34 +2273,34 @@
>   else if (isOperationLegal(ISD::SMUL_LOHI, VT))
>     Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT),
>                               N->getOperand(0),
> -                              DAG.getConstant(magics.m, VT)).Val, 1);
> +                              DAG.getConstant(magics.m,  
> VT)).getNode(), 1);
>   else
>     return SDValue();       // No mulhs or equvialent
>   // If d > 0 and m < 0, add the numerator
>   if (d > 0 && magics.m < 0) {
>     Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
>     if (Created)
> -      Created->push_back(Q.Val);
> +      Created->push_back(Q.getNode());
>   }
>   // If d < 0 and m > 0, subtract the numerator.
>   if (d < 0 && magics.m > 0) {
>     Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
>     if (Created)
> -      Created->push_back(Q.Val);
> +      Created->push_back(Q.getNode());
>   }
>   // Shift right algebraic if shift value is nonzero
>   if (magics.s > 0) {
>     Q = DAG.getNode(ISD::SRA, VT, Q,
>                     DAG.getConstant(magics.s, getShiftAmountTy()));
>     if (Created)
> -      Created->push_back(Q.Val);
> +      Created->push_back(Q.getNode());
>   }
>   // Extract the sign bit and add it to the quotient
>   SDValue T =
>     DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
>                                                  getShiftAmountTy()));
>   if (Created)
> -    Created->push_back(T.Val);
> +    Created->push_back(T.getNode());
>   return DAG.getNode(ISD::ADD, VT, Q, T);
> }
>
> @@ -2327,11 +2327,11 @@
>   else if (isOperationLegal(ISD::UMUL_LOHI, VT))
>     Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT),
>                               N->getOperand(0),
> -                              DAG.getConstant(magics.m, VT)).Val, 1);
> +                              DAG.getConstant(magics.m,  
> VT)).getNode(), 1);
>   else
>     return SDValue();       // No mulhu or equvialent
>   if (Created)
> -    Created->push_back(Q.Val);
> +    Created->push_back(Q.getNode());
>
>   if (magics.a == 0) {
>     return DAG.getNode(ISD::SRL, VT, Q,
> @@ -2339,14 +2339,14 @@
>   } else {
>     SDValue NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
>     if (Created)
> -      Created->push_back(NPQ.Val);
> +      Created->push_back(NPQ.getNode());
>     NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
>                       DAG.getConstant(1, getShiftAmountTy()));
>     if (Created)
> -      Created->push_back(NPQ.Val);
> +      Created->push_back(NPQ.getNode());
>     NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
>     if (Created)
> -      Created->push_back(NPQ.Val);
> +      Created->push_back(NPQ.getNode());
>     return DAG.getNode(ISD::SRL, VT, NPQ,
>                        DAG.getConstant(magics.s-1,  
> getShiftAmountTy()));
>   }
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -529,7 +529,7 @@
>
>
> SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
> -  SDNode *N = Op.Val;
> +  SDNode *N = Op.getNode();
>
>   if (N->isMachineOpcode())
>     return NULL;   // Already selected.
> @@ -729,11 +729,11 @@
>     SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
>     SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other,  
> MVT::Flag, Ops, 5);
>     Chain = SDValue(ResNode, 0);
> -    if (Op.Val->getNumValues() == 2) {
> +    if (Op.getNode()->getNumValues() == 2) {
>       InFlag = SDValue(ResNode, 1);
> -      ReplaceUses(SDValue(Op.Val, 1), InFlag);
> +      ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
>     }
> -    ReplaceUses(SDValue(Op.Val, 0), SDValue(Chain.Val,  
> Chain.getResNo()));
> +    ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(),  
> Chain.getResNo()));
>     return NULL;
>   }
>   case ARMISD::CMOV: {
> @@ -763,7 +763,7 @@
>       SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
>                                cast<ConstantSDNode>(N2)- 
> >getValue()), MVT::i32);
>       SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3,  
> InFlag };
> -      return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCs, MVT::i32,  
> Ops, 7);
> +      return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs,  
> MVT::i32, Ops, 7);
>     }
>
>     // Pattern: (ARMcmov:i32 GPR:i32:$false,
> @@ -774,16 +774,16 @@
>     // Pattern complexity = 10  cost = 1  size = 0
>     if (VT == MVT::i32 &&
>         N3.getOpcode() == ISD::Constant &&
> -        Predicate_so_imm(N3.Val)) {
> +        Predicate_so_imm(N3.getNode())) {
>       AddToISelQueue(N0);
>       AddToISelQueue(InFlag);
>       SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
>                                cast<ConstantSDNode>(N1)- 
> >getValue()), MVT::i32);
> -      Tmp1 = Transform_so_imm_XFORM(Tmp1.Val);
> +      Tmp1 = Transform_so_imm_XFORM(Tmp1.getNode());
>       SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
>                                cast<ConstantSDNode>(N2)- 
> >getValue()), MVT::i32);
>       SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
> -      return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCi, MVT::i32,  
> Ops, 5);
> +      return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCi,  
> MVT::i32, Ops, 5);
>     }
>
>     // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true,  
> (imm:i32):$cc)
> @@ -815,7 +815,7 @@
>       Opc = ARM::FCPYDcc;
>       break;
>     }
> -    return CurDAG->SelectNodeTo(Op.Val, Opc, VT, Ops, 5);
> +    return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
>   }
>   case ARMISD::CNEG: {
>     MVT VT = Op.getValueType();
> @@ -844,7 +844,7 @@
>       Opc = ARM::FNEGDcc;
>       break;
>     }
> -    return CurDAG->SelectNodeTo(Op.Val, Opc, VT, Ops, 5);
> +    return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
>   }
>   }
>   return SelectCode(Op);
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -400,7 +400,7 @@
> /// ARMISD:CALL <- callseq_end chain. Also add input and output  
> parameter
> /// nodes.
> SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
> -  MVT RetVT= Op.Val->getValueType(0);
> +  MVT RetVT= Op.getNode()->getValueType(0);
>   SDValue Chain    = Op.getOperand(0);
>   unsigned CallConv  = cast<ConstantSDNode>(Op.getOperand(1))- 
> >getValue();
>   assert((CallConv == CallingConv::C ||
> @@ -597,7 +597,7 @@
>     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
>                                    
> RegsToPass[i].second.getValueType()));
>
> -  if (InFlag.Val)
> +  if (InFlag.getNode())
>     Ops.push_back(InFlag);
>   // Returns a chain and a flag for retval copy to use.
>   Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag),
> @@ -621,7 +621,7 @@
>   case MVT::i32:
>     Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32,  
> InFlag).getValue(1);
>     ResultVals.push_back(Chain.getValue(0));
> -    if (Op.Val->getValueType(1) == MVT::i32) {
> +    if (Op.getNode()->getValueType(1) == MVT::i32) {
>       // Returns a i64 value.
>       Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32,
>                                  Chain.getValue(2)).getValue(1);
> @@ -981,7 +981,7 @@
>   unsigned ArgOffset = 0;   // Frame mechanisms handle retaddr slot
>   unsigned NumGPRs = 0;     // GPRs used for parameter passing.
>
> -  unsigned NumArgs = Op.Val->getNumValues()-1;
> +  unsigned NumArgs = Op.getNode()->getNumValues()-1;
>   for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
>     ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo,
>                                              NumGPRs, ArgOffset));
> @@ -1029,7 +1029,7 @@
>   ArgValues.push_back(Root);
>
>   // Return the new list of results.
> -  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
> +  return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
>                             ArgValues.size());
> }
>
> @@ -1037,7 +1037,7 @@
> static bool isFloatingPointZero(SDValue Op) {
>   if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
>     return CFP->getValueAPF().isPosZero();
> -  else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
> +  else if (ISD::isEXTLoad(Op.getNode()) ||  
> ISD::isNON_EXTLoad(Op.getNode())) {
>     // Maybe this has already been legalized into the constant pool?
>     if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
>       SDValue WrapperOp = Op.getOperand(1).getOperand(0);
> @@ -1058,7 +1058,7 @@
> /// the given operands.
> static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
>                            SDValue &ARMCC, SelectionDAG &DAG, bool  
> isThumb) {
> -  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) {
> +  if (ConstantSDNode *RHSC =  
> dyn_cast<ConstantSDNode>(RHS.getNode())) {
>     unsigned C = RHSC->getValue();
>     if (!isLegalCmpImmediate(C, isThumb)) {
>       // Constant does not fit, try adjusting it by one?
> @@ -1362,7 +1362,7 @@
>                               &Op, 1);
>
>   // Merge the pieces into a single i64 value.
> -  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt,  
> Cvt.getValue(1)).Val;
> +  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt,  
> Cvt.getValue(1)).getNode();
> }
>
> static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const  
> ARMSubtarget *ST) {
> @@ -1393,7 +1393,7 @@
>   Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
>
>   // Merge the pieces into a single i64 value.
> - return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).Val;
> + return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).getNode();
> }
>
>
> @@ -1424,9 +1424,9 @@
>
>
>   // FIXME: Remove these when LegalizeDAGTypes lands.
> -  case ISD::BIT_CONVERT:   return SDValue(ExpandBIT_CONVERT(Op.Val,  
> DAG), 0);
> +  case ISD::BIT_CONVERT:   return  
> SDValue(ExpandBIT_CONVERT(Op.getNode(), DAG), 0);
>   case ISD::SRL:
> -  case ISD::SRA:           return SDValue(ExpandSRx(Op.Val,  
> DAG,Subtarget),0);
> +  case ISD::SRA:           return SDValue(ExpandSRx(Op.getNode(),  
> DAG,Subtarget),0);
>   }
>   return SDValue();
> }
> @@ -1734,7 +1734,7 @@
>     return false;
>
>   bool isInc;
> -  bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad,  
> Base, Offset,
> +  bool isLegal = getIndexedAddressParts(Ptr.getNode(), VT,  
> isSEXTLoad, Base, Offset,
>                                         isInc, DAG);
>   if (isLegal) {
>     AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -75,7 +75,7 @@
>           Result |= 1 << i;
>           if (((Constant >> 8*i) & 0xFF) == 0xFF) {
>             // If the entire byte is set, zapnot the byte.
> -          } else if (LHS.Val == 0) {
> +          } else if (LHS.getNode() == 0) {
>             // Otherwise, if the mask was previously validated, we  
> know its okay
>             // to zapnot this entire byte even though all the bits  
> aren't set.
>           } else {
> @@ -242,7 +242,7 @@
> // Select - Convert the specified operand from a target-independent  
> to a
> // target-specific node if it hasn't already been changed.
> SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
> -  SDNode *N = Op.Val;
> +  SDNode *N = Op.getNode();
>   if (N->isMachineOpcode()) {
>     return NULL;   // Already selected.
>   }
> @@ -345,7 +345,7 @@
>   }
>
>   case ISD::SETCC:
> -    if (N->getOperand(0).Val->getValueType(0).isFloatingPoint()) {
> +    if (N->getOperand(0).getNode()- 
> >getValueType(0).isFloatingPoint()) {
>       ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))- 
> >get();
>
>       unsigned Opc = Alpha::WTF;
> @@ -460,7 +460,7 @@
> void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
>   //TODO: add flag stuff to prevent nondeturministic breakage!
>
> -  SDNode *N = Op.Val;
> +  SDNode *N = Op.getNode();
>   SDValue Chain = N->getOperand(0);
>   SDValue Addr = N->getOperand(1);
>   SDValue InFlag(0,0);  // Null incoming flag value.
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -215,7 +215,7 @@
>   unsigned args_float[] = {
>     Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20,  
> Alpha::F21};
>
> -  for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo !=  
> e; ++ArgNo) {
> +  for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1;  
> ArgNo != e; ++ArgNo) {
>     SDValue argt;
>     MVT ObjectVT = Op.getValue(ArgNo).getValueType();
>     SDValue ArgVal;
> @@ -255,7 +255,7 @@
>   // If the functions takes variable number of arguments, copy all  
> regs to stack
>   bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))- 
> >getValue() != 0;
>   if (isVarArg) {
> -    VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
> +    VarArgsOffset = (Op.getNode()->getNumValues()-1) * 8;
>     std::vector<SDValue> LS;
>     for (int i = 0; i < 6; ++i) {
>       if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
> @@ -281,7 +281,7 @@
>   ArgValues.push_back(Root);
>
>   // Return the new list of results.
> -  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
> +  return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
>                             ArgValues.size());
> }
>
> @@ -491,10 +491,10 @@
>   case ISD::SREM:
>     //Expand only on constant case
>     if (Op.getOperand(1).getOpcode() == ISD::Constant) {
> -      MVT VT = Op.Val->getValueType(0);
> -      SDValue Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
> -        BuildUDIV(Op.Val, DAG, NULL) :
> -        BuildSDIV(Op.Val, DAG, NULL);
> +      MVT VT = Op.getNode()->getValueType(0);
> +      SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ?
> +        BuildUDIV(Op.getNode(), DAG, NULL) :
> +        BuildSDIV(Op.getNode(), DAG, NULL);
>       Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
>       Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
>       return Tmp1;
> @@ -504,8 +504,8 @@
>   case ISD::UDIV:
>     if (Op.getValueType().isInteger()) {
>       if (Op.getOperand(1).getOpcode() == ISD::Constant)
> -        return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG,  
> NULL)
> -          : BuildUDIV(Op.Val, DAG, NULL);
> +        return Op.getOpcode() == ISD::SDIV ?  
> BuildSDIV(Op.getNode(), DAG, NULL)
> +          : BuildUDIV(Op.getNode(), DAG, NULL);
>       const char* opstr = 0;
>       switch (Op.getOpcode()) {
>       case ISD::UREM: opstr = "__remqu"; break;
> @@ -522,7 +522,7 @@
>
>   case ISD::VAARG: {
>     SDValue Chain, DataPtr;
> -    LowerVAARG(Op.Val, Chain, DataPtr, DAG);
> +    LowerVAARG(Op.getNode(), Chain, DataPtr, DAG);
>
>     SDValue Result;
>     if (Op.getValueType() == MVT::i32)
> @@ -578,7 +578,7 @@
>
>   SDValue Chain, DataPtr;
>   LowerVAARG(N, Chain, DataPtr, DAG);
> -  return DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL,  
> 0).Val;
> +  return DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL,  
> 0).getNode();
> }
>
>
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -579,7 +579,7 @@
>  */
> SDNode *
> SPUDAGToDAGISel::Select(SDValue Op) {
> -  SDNode *N = Op.Val;
> +  SDNode *N = Op.getNode();
>   unsigned Opc = N->getOpcode();
>   int n_ops = -1;
>   unsigned NewOpc;
> @@ -669,9 +669,9 @@
>       MVT VT = Op.getValueType();
>
>       DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = ");
> -      DEBUG(Op.getOperand(0).Val->dump(CurDAG));
> +      DEBUG(Op.getOperand(0).getNode()->dump(CurDAG));
>       DEBUG(cerr << "\nOp1 = ");
> -      DEBUG(Op.getOperand(1).Val->dump(CurDAG));
> +      DEBUG(Op.getOperand(1).getNode()->dump(CurDAG));
>       DEBUG(cerr << "\n");
>
>       if (Op1.getOpcode() == ISD::Constant) {
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -503,7 +503,7 @@
>   SDValue chain = LSN->getChain();
>
>   if (basePtr.getOpcode() == ISD::ADD) {
> -    SDValue Op1 = basePtr.Val->getOperand(1);
> +    SDValue Op1 = basePtr.getNode()->getOperand(1);
>
>     if (Op1.getOpcode() == ISD::Constant || Op1.getOpcode() ==  
> ISD::TargetConstant) {
>       const ConstantSDNode *CN =  
> cast<ConstantSDNode>(basePtr.getOperand(1));
> @@ -579,7 +579,7 @@
>   LoadSDNode *LN = cast<LoadSDNode>(Op);
>   SDValue the_chain = LN->getChain();
>   MVT VT = LN->getMemoryVT();
> -  MVT OpVT = Op.Val->getValueType(0);
> +  MVT OpVT = Op.getNode()->getValueType(0);
>   ISD::LoadExtType ExtType = LN->getExtensionType();
>   unsigned alignment = LN->getAlignment();
>   SDValue Ops[8];
> @@ -591,7 +591,7 @@
>     SDValue result =
>       AlignedLoad(Op, DAG, ST, LN,alignment, offset, rotamt, VT,  
> was16aligned);
>
> -    if (result.Val == 0)
> +    if (result.getNode() == 0)
>       return result;
>
>     the_chain = result.getValue(1);
> @@ -708,7 +708,7 @@
>       AlignedLoad(Op, DAG, ST, SN, alignment,
>                   chunk_offset, slot_offset, VT, was16aligned);
>
> -    if (alignLoadVec.Val == 0)
> +    if (alignLoadVec.getNode() == 0)
>       return alignLoadVec;
>
>     LoadSDNode *LN = cast<LoadSDNode>(alignLoadVec);
> @@ -736,7 +736,7 @@
>     // Otherwise generate a D-form address with the slot offset  
> relative
>     // to the stack pointer, which is always aligned.
>     DEBUG(cerr << "CellSPU LowerSTORE: basePtr = ");
> -    DEBUG(basePtr.Val->dump(&DAG));
> +    DEBUG(basePtr.getNode()->dump(&DAG));
>     DEBUG(cerr << "\n");
>
>     if (basePtr.getOpcode() == SPUISD::IndirectAddr ||
> @@ -859,7 +859,7 @@
> static SDValue
> LowerConstant(SDValue Op, SelectionDAG &DAG) {
>   MVT VT = Op.getValueType();
> -  ConstantSDNode *CN = cast<ConstantSDNode>(Op.Val);
> +  ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode());
>
>   if (VT == MVT::i64) {
>     SDValue T = DAG.getConstant(CN->getValue(), MVT::i64);
> @@ -880,7 +880,7 @@
> static SDValue
> LowerConstantFP(SDValue Op, SelectionDAG &DAG) {
>   MVT VT = Op.getValueType();
> -  ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.Val);
> +  ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.getNode());
>
>   assert((FP != 0) &&
>          "LowerConstantFP: Node is not ConstantFPSDNode");
> @@ -932,7 +932,7 @@
>   MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
>
>   // Add DAG nodes to load the arguments or copy them out of  
> registers.
> -  for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo !=  
> e; ++ArgNo) {
> +  for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1;  
> ArgNo != e; ++ArgNo) {
>     SDValue ArgVal;
>     bool needsLoad = false;
>     MVT ObjectVT = Op.getValue(ArgNo).getValueType();
> @@ -1061,7 +1061,7 @@
>   ArgValues.push_back(Root);
>
>   // Return the new list of results.
> -  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
> +  return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
>                             ArgValues.size());
> }
>
> @@ -1076,7 +1076,7 @@
>       (Addr << 14 >> 14) != Addr)
>     return 0;  // Top 14 bits have to be sext of immediate.
>
> -  return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
> +  return DAG.getConstant((int)C->getValue() >> 2,  
> MVT::i32).getNode();
> }
>
> static
> @@ -1226,7 +1226,7 @@
>     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
>                                    
> RegsToPass[i].second.getValueType()));
>
> -  if (InFlag.Val)
> +  if (InFlag.getNode())
>     Ops.push_back(InFlag);
>   // Returns a chain and a flag for retval copy to use.
>   Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag),
> @@ -1237,18 +1237,18 @@
>                              DAG.getConstant(NumStackBytes, PtrVT),
>                              DAG.getConstant(0, PtrVT),
>                              InFlag);
> -  if (Op.Val->getValueType(0) != MVT::Other)
> +  if (Op.getNode()->getValueType(0) != MVT::Other)
>     InFlag = Chain.getValue(1);
>
>   SDValue ResultVals[3];
>   unsigned NumResults = 0;
>
>   // If the call has results, copy the values out of the ret val  
> registers.
> -  switch (Op.Val->getValueType(0).getSimpleVT()) {
> +  switch (Op.getNode()->getValueType(0).getSimpleVT()) {
>   default: assert(0 && "Unexpected ret value!");
>   case MVT::Other: break;
>   case MVT::i32:
> -    if (Op.Val->getValueType(1) == MVT::i32) {
> +    if (Op.getNode()->getValueType(1) == MVT::i32) {
>       Chain = DAG.getCopyFromReg(Chain, SPU::R4, MVT::i32,  
> InFlag).getValue(1);
>       ResultVals[0] = Chain.getValue(0);
>       Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i32,
> @@ -1268,7 +1268,7 @@
>     break;
>   case MVT::f32:
>   case MVT::f64:
> -    Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.Val- 
> >getValueType(0),
> +    Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.getNode()- 
> >getValueType(0),
>                                InFlag).getValue(1);
>     ResultVals[0] = Chain.getValue(0);
>     NumResults = 1;
> @@ -1278,7 +1278,7 @@
>   case MVT::v4i32:
>   case MVT::v8i16:
>   case MVT::v16i8:
> -    Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.Val- 
> >getValueType(0),
> +    Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.getNode()- 
> >getValueType(0),
>                                    InFlag).getValue(1);
>     ResultVals[0] = Chain.getValue(0);
>     NumResults = 1;
> @@ -1301,7 +1301,7 @@
>   unsigned CC = DAG.getMachineFunction().getFunction()- 
> >getCallingConv();
>   bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
>   CCState CCInfo(CC, isVarArg, TM, RVLocs);
> -  CCInfo.AnalyzeReturn(Op.Val, RetCC_SPU);
> +  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SPU);
>
>   // If this is the first return lowered for this function, add the  
> regs to the
>   // liveout set for the function.
> @@ -1321,7 +1321,7 @@
>     Flag = Chain.getValue(1);
>   }
>
> -  if (Flag.Val)
> +  if (Flag.getNode())
>     return DAG.getNode(SPUISD::RET_FLAG, MVT::Other, Chain, Flag);
>   else
>     return DAG.getNode(SPUISD::RET_FLAG, MVT::Other, Chain);
> @@ -1339,13 +1339,13 @@
>   // Check to see if this buildvec has a single non-undef value in  
> its elements.
>   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
>     if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
> -    if (OpVal.Val == 0)
> +    if (OpVal.getNode() == 0)
>       OpVal = N->getOperand(i);
>     else if (OpVal != N->getOperand(i))
>       return 0;
>   }
>
> -  if (OpVal.Val != 0) {
> +  if (OpVal.getNode() != 0) {
>     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
>       return CN;
>     }
> @@ -1599,7 +1599,7 @@
>   uint64_t UndefBits[2];
>   uint64_t SplatBits, SplatUndef;
>   int SplatSize;
> -  if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)
> +  if (GetConstantBuildVectorBits(Op.getNode(), VectorBits, UndefBits)
>       || !isConstantSplat(VectorBits, UndefBits,
>                           VT.getVectorElementType().getSizeInBits(),
>                           SplatBits, SplatUndef, SplatSize))
> @@ -1842,11 +1842,11 @@
> static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
>   SDValue Op0 = Op.getOperand(0);                     // Op0 = the  
> scalar
>
> -  if (Op0.Val->getOpcode() == ISD::Constant) {
> +  if (Op0.getNode()->getOpcode() == ISD::Constant) {
>     // For a constant, build the appropriate constant vector, which  
> will
>     // eventually simplify to a vector register load.
>
> -    ConstantSDNode *CN = cast<ConstantSDNode>(Op0.Val);
> +    ConstantSDNode *CN = cast<ConstantSDNode>(Op0.getNode());
>     SmallVector<SDValue, 16> ConstVecValues;
>     MVT VT;
>     size_t n_copies;
> @@ -2447,25 +2447,25 @@
>
>   ConstVec = Op.getOperand(0);
>   Arg = Op.getOperand(1);
> -  if (ConstVec.Val->getOpcode() != ISD::BUILD_VECTOR) {
> -    if (ConstVec.Val->getOpcode() == ISD::BIT_CONVERT) {
> +  if (ConstVec.getNode()->getOpcode() != ISD::BUILD_VECTOR) {
> +    if (ConstVec.getNode()->getOpcode() == ISD::BIT_CONVERT) {
>       ConstVec = ConstVec.getOperand(0);
>     } else {
>       ConstVec = Op.getOperand(1);
>       Arg = Op.getOperand(0);
> -      if (ConstVec.Val->getOpcode() == ISD::BIT_CONVERT) {
> +      if (ConstVec.getNode()->getOpcode() == ISD::BIT_CONVERT) {
>         ConstVec = ConstVec.getOperand(0);
>       }
>     }
>   }
>
> -  if (ConstVec.Val->getOpcode() == ISD::BUILD_VECTOR) {
> +  if (ConstVec.getNode()->getOpcode() == ISD::BUILD_VECTOR) {
>     uint64_t VectorBits[2];
>     uint64_t UndefBits[2];
>     uint64_t SplatBits, SplatUndef;
>     int SplatSize;
>
> -    if (!GetConstantBuildVectorBits(ConstVec.Val, VectorBits,  
> UndefBits)
> +    if (!GetConstantBuildVectorBits(ConstVec.getNode(), VectorBits,  
> UndefBits)
>         && isConstantSplat(VectorBits, UndefBits,
>                            VT.getVectorElementType().getSizeInBits(),
>                            SplatBits, SplatUndef, SplatSize)) {
> @@ -2477,7 +2477,7 @@
>       for (size_t i = 0; i < tcVecSize; ++i)
>         tcVec[i] = tc;
>
> -      return DAG.getNode(Op.Val->getOpcode(), VT, Arg,
> +      return DAG.getNode(Op.getNode()->getOpcode(), VT, Arg,
>                          DAG.getNode(ISD::BUILD_VECTOR, VT, tcVec,  
> tcVecSize));
>     }
>   }
> @@ -2632,8 +2632,8 @@
>   default: {
>     cerr << "SPUTargetLowering::LowerOperation(): need to lower this! 
> \n";
>     cerr << "Op.getOpcode() = " << Opc << "\n";
> -    cerr << "*Op.Val:\n";
> -    Op.Val->dump();
> +    cerr << "*Op.getNode():\n";
> +    Op.getNode()->dump();
>     abort();
>   }
>   case ISD::LOAD:
> @@ -2796,7 +2796,7 @@
>       DEBUG(cerr << "Replace: ");
>       DEBUG(N->dump(&DAG));
>       DEBUG(cerr << "\nWith:    ");
> -      DEBUG(Op0.Val->dump(&DAG));
> +      DEBUG(Op0.getNode()->dump(&DAG));
>       DEBUG(cerr << "\n");
>
>       return Op0;
> @@ -2813,7 +2813,7 @@
>         DEBUG(cerr << "Replace: ");
>         DEBUG(N->dump(&DAG));
>         DEBUG(cerr << "\nWith:    ");
> -        DEBUG(Op0.Val->dump(&DAG));
> +        DEBUG(Op0.getNode()->dump(&DAG));
>         DEBUG(cerr << "\n");
>
>         return Op0;
> @@ -2871,11 +2871,11 @@
>   }
>   // Otherwise, return unchanged.
> #if 1
> -  if (Result.Val) {
> +  if (Result.getNode()) {
>     DEBUG(cerr << "\nReplace.SPU: ");
>     DEBUG(N->dump(&DAG));
>     DEBUG(cerr << "\nWith:        ");
> -    DEBUG(Result.Val->dump(&DAG));
> +    DEBUG(Result.getNode()->dump(&DAG));
>     DEBUG(cerr << "\n");
>   }
> #endif
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPUOperands.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUOperands.td?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPUOperands.td (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPUOperands.td Thu Aug 28 16:40:38  
> 2008
> @@ -24,13 +24,13 @@
>          && "LO16_vec got something other than a BUILD_VECTOR");
>
>   // Get first constant operand...
> -  for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 &&  
> i != e; ++i) {
> +  for (unsigned i = 0, e = N->getNumOperands(); OpVal.getNode() ==  
> 0 && i != e; ++i) {
>     if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
> -    if (OpVal.Val == 0)
> +    if (OpVal.getNode() == 0)
>       OpVal = N->getOperand(i);
>   }
>
> -  assert(OpVal.Val != 0 && "LO16_vec did not locate a <defined>  
> node");
> +  assert(OpVal.getNode() != 0 && "LO16_vec did not locate a  
> <defined> node");
>   ConstantSDNode *CN = cast<ConstantSDNode>(OpVal);
>   return getI32Imm((unsigned)CN->getValue() & 0xffff);
> }]>;
> @@ -49,13 +49,13 @@
>          && "HI16_vec got something other than a BUILD_VECTOR");
>
>   // Get first constant operand...
> -  for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 &&  
> i != e; ++i) {
> +  for (unsigned i = 0, e = N->getNumOperands(); OpVal.getNode() ==  
> 0 && i != e; ++i) {
>     if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
> -    if (OpVal.Val == 0)
> +    if (OpVal.getNode() == 0)
>       OpVal = N->getOperand(i);
>   }
>
> -  assert(OpVal.Val != 0 && "HI16_vec did not locate a <defined>  
> node");
> +  assert(OpVal.getNode() != 0 && "HI16_vec did not locate a  
> <defined> node");
>   ConstantSDNode *CN = cast<ConstantSDNode>(OpVal);
>   return getI32Imm((unsigned)CN->getValue() >> 16);
> }]>;
> @@ -244,7 +244,7 @@
> // incoming constant being a 16-bit quantity, where the upper and  
> lower bytes
> // are EXACTLY the same (e.g., 0x2a2a)
> def v16i8SExt8Imm: PatLeaf<(build_vector), [{
> -  return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
> +  return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
> }], v16i8SExt8Imm_xform>;
>
> // v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit
> @@ -259,7 +259,7 @@
> // incoming constant being a 16-bit quantity, where the upper and  
> lower bytes
> // are EXACTLY the same (e.g., 0x2a2a)
> def v16i8U8Imm: PatLeaf<(build_vector), [{
> -  return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
> +  return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
> }], v16i8U8Imm_xform>;
>
> // v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign  
> extended
> @@ -271,7 +271,7 @@
> // v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate  
> constant
> // load, works in conjunction with its transform function.
> def v8i16SExt8Imm: PatLeaf<(build_vector), [{
> -  return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).Val != 0;
> +  return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).getNode() != 0;
> }], v8i16SExt8Imm_xform>;
>
> // v8i16SExt10Imm_xform function: convert build_vector to 16-bit  
> sign extended
> @@ -283,7 +283,7 @@
> // v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate  
> constant
> // load, works in conjunction with its transform function.
> def v8i16SExt10Imm: PatLeaf<(build_vector), [{
> -  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
> +  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
> }], v8i16SExt10Imm_xform>;
>
> // v8i16Uns10Imm_xform function: convert build_vector to 16-bit  
> unsigned
> @@ -295,7 +295,7 @@
> // v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate  
> constant
> // load, works in conjunction with its transform function.
> def v8i16Uns10Imm: PatLeaf<(build_vector), [{
> -  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
> +  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
> }], v8i16Uns10Imm_xform>;
>
> // v8i16SExt16Imm_xform function: convert build_vector to 16-bit  
> sign extended
> @@ -307,7 +307,7 @@
> // v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate  
> constant
> // load, works in conjunction with its transform function.
> def v8i16SExt16Imm: PatLeaf<(build_vector), [{
> -  return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).Val != 0;
> +  return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).getNode() != 0;
> }], v8i16Uns16Imm_xform>;
>
> // v4i32SExt10Imm_xform function: convert build_vector to 10-bit  
> sign extended
> @@ -319,7 +319,7 @@
> // v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate  
> constant
> // load, works in conjunction with its transform function.
> def v4i32SExt10Imm: PatLeaf<(build_vector), [{
> -  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
> +  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
> }], v4i32SExt10Imm_xform>;
>
> // v4i32Uns10Imm_xform function: convert build_vector to 10-bit  
> unsigned
> @@ -331,7 +331,7 @@
> // v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate  
> constant
> // load, works in conjunction with its transform function.
> def v4i32Uns10Imm: PatLeaf<(build_vector), [{
> -  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
> +  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
> }], v4i32Uns10Imm_xform>;
>
> // v4i32SExt16Imm_xform function: convert build_vector to 16-bit  
> sign extended
> @@ -343,7 +343,7 @@
> // v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate  
> constant
> // load, works in conjunction with its transform function.
> def v4i32SExt16Imm: PatLeaf<(build_vector), [{
> -  return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).Val != 0;
> +  return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).getNode() != 0;
> }], v4i32SExt16Imm_xform>;
>
> // v4i32Uns18Imm_xform function: convert build_vector to 18-bit  
> unsigned
> @@ -355,7 +355,7 @@
> // v4i32Uns18Imm: Predicate test for 18-bit unsigned immediate  
> constant load,
> // works in conjunction with its transform function.
> def v4i32Uns18Imm: PatLeaf<(build_vector), [{
> -  return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).Val != 0;
> +  return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).getNode() != 0;
> }], v4i32Uns18Imm_xform>;
>
> // ILHUvec_get_imm xform function: convert build_vector to ILHUvec  
> imm constant
> @@ -366,7 +366,7 @@
>
> /// immILHUvec: Predicate test for a ILHU constant vector.
> def immILHUvec: PatLeaf<(build_vector), [{
> -  return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).Val != 0;
> +  return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).getNode() != 0;
> }], ILHUvec_get_imm>;
>
> // Catch-all for any other i32 vector constants
> @@ -375,7 +375,7 @@
> }]>;
>
> def v4i32Imm: PatLeaf<(build_vector), [{
> -  return SPU::get_v4i32_imm(N, *CurDAG).Val != 0;
> +  return SPU::get_v4i32_imm(N, *CurDAG).getNode() != 0;
> }], v4i32_get_imm>;
>
> // v2i64SExt10Imm_xform function: convert build_vector to 10-bit  
> sign extended
> @@ -387,7 +387,7 @@
> // v2i64SExt10Imm: Predicate test for 10-bit sign extended immediate  
> constant
> // load, works in conjunction with its transform function.
> def v2i64SExt10Imm: PatLeaf<(build_vector), [{
> -  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).Val != 0;
> +  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).getNode() != 0;
> }], v2i64SExt10Imm_xform>;
>
> // v2i64SExt16Imm_xform function: convert build_vector to 16-bit  
> sign extended
> @@ -399,7 +399,7 @@
> // v2i64SExt16Imm: Predicate test for 16-bit sign extended immediate  
> constant
> // load, works in conjunction with its transform function.
> def v2i64SExt16Imm: PatLeaf<(build_vector), [{
> -  return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).Val != 0;
> +  return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).getNode() != 0;
> }], v2i64SExt16Imm_xform>;
>
> // v2i64Uns18Imm_xform function: convert build_vector to 18-bit  
> unsigned
> @@ -411,12 +411,12 @@
> // v2i64Uns18Imm: Predicate test for 18-bit unsigned immediate  
> constant load,
> // works in conjunction with its transform function.
> def v2i64Uns18Imm: PatLeaf<(build_vector), [{
> -  return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).Val != 0;
> +  return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).getNode() != 0;
> }], v2i64Uns18Imm_xform>;
>
> /// immILHUvec: Predicate test for a ILHU constant vector.
> def immILHUvec_i64: PatLeaf<(build_vector), [{
> -  return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).Val != 0;
> +  return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).getNode() != 0;
> }], ILHUvec_get_imm>;
>
> // Catch-all for any other i32 vector constants
> @@ -425,7 +425,7 @@
> }]>;
>
> def v2i64Imm: PatLeaf<(build_vector), [{
> -  return SPU::get_v2i64_imm(N, *CurDAG).Val != 0;
> +  return SPU::get_v2i64_imm(N, *CurDAG).getNode() != 0;
> }], v2i64_get_imm>;
>
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> Modified: llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -105,7 +105,7 @@
> }
>
> SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) {
> -  SDNode *N = Op.Val;
> +  SDNode *N = Op.getNode();
>   SDValue Chain = N->getOperand(0);
>   SDValue Tmp1 = N->getOperand(0);
>   SDValue Tmp2 = N->getOperand(1);
> @@ -304,7 +304,7 @@
> // Select - Convert the specified operand from a target-independent  
> to a
> // target-specific node if it hasn't already been changed.
> SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
> -  SDNode *N = Op.Val;
> +  SDNode *N = Op.getNode();
>   if (N->isMachineOpcode())
>     return NULL;   // Already selected.
>
> @@ -367,7 +367,7 @@
>   }
>
>    // Finally, once everything is setup, emit the call itself
> -   if(InFlag.Val)
> +   if (InFlag.getNode())
>      Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other,  
> MVT::Flag,
>                                              CallOperand, InFlag), 0);
>    else // there might be no arguments
>
> Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -387,8 +387,8 @@
>         break;
>       }
>
> -      if(ValToStore.Val) {
> -        if(!StackPtr.Val) {
> +      if(ValToStore.getNode()) {
> +        if(!StackPtr.getNode()) {
>           StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
>         }
>         SDValue PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
> @@ -397,7 +397,7 @@
>         ArgOffset += ObjSize;
>       }
>
> -      if(ValToConvert.Val) {
> +      if(ValToConvert.getNode()) {
>         Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64,  
> ValToConvert));
>       }
>     }
> @@ -471,7 +471,7 @@
>   CallOperands.push_back(Callee);
>
>   // emit the call itself
> -  if (InFlag.Val)
> +  if (InFlag.getNode())
>     CallOperands.push_back(InFlag);
>   else
>     assert(0 && "this should never happen!\n");
>
> Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -193,7 +193,7 @@
> SDNode* MipsDAGToDAGISel::
> Select(SDValue N)
> {
> -  SDNode *Node = N.Val;
> +  SDNode *Node = N.getNode();
>   unsigned Opcode = Node->getOpcode();
>
>   // Dump information about the Node being selected
> @@ -252,7 +252,7 @@
>       SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT,
>                                                SDValue(Carry,0), RHS);
>
> -      return CurDAG->SelectNodeTo(N.Val, MOp, VT, MVT::Flag,
> +      return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, MVT::Flag,
>                                   LHS, SDValue(AddCarry,0));
>     }
>
> @@ -391,8 +391,8 @@
>
>   #ifndef NDEBUG
>   DOUT << std::string(Indent-2, ' ') << "=> ";
> -  if (ResNode == NULL || ResNode == N.Val)
> -    DEBUG(N.Val->dump(CurDAG));
> +  if (ResNode == NULL || ResNode == N.getNode())
> +    DEBUG(N.getNode()->dump(CurDAG));
>   else
>     DEBUG(ResNode->dump(CurDAG));
>   DOUT << "\n";
>
> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -602,7 +602,7 @@
>     MFI->CreateFixedObject(VTsize, (VTsize*3));
>   }
>
> -  CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
> +  CCInfo.AnalyzeCallOperands(Op.getNode(), CC_Mips);
>
>   // Get a count of how many bytes are to be pushed on the stack.
>   unsigned NumBytes = CCInfo.getNextStackOffset();
> @@ -706,7 +706,7 @@
>     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
>                                    
> RegsToPass[i].second.getValueType()));
>
> -  if (InFlag.Val)
> +  if (InFlag.getNode())
>     Ops.push_back(InFlag);
>
>   Chain  = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0],  
> Ops.size());
> @@ -750,7 +750,7 @@
>
>   // Handle result values, copying them out of physregs into vregs  
> that we
>   // return.
> -  return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG),  
> Op.getResNo());
> +  return SDValue(LowerCallResult(Chain, InFlag, Op.getNode(), CC,  
> DAG), Op.getResNo());
> }
>
> /// LowerCallResult - Lower the result values of an ISD::CALL into the
> @@ -783,7 +783,7 @@
>
>   // Merge everything together with a MERGE_VALUES node.
>   return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
> -                            ResultVals.size()).Val;
> +                            ResultVals.size()).getNode();
> }
>
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
> @@ -814,7 +814,7 @@
>   SmallVector<CCValAssign, 16> ArgLocs;
>   CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
>
> -  CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
> +  CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_Mips);
>   SmallVector<SDValue, 16> ArgValues;
>   SDValue StackPtr;
>
> @@ -865,7 +865,7 @@
>       // To meet ABI, when VARARGS are passed on registers, the  
> registers
>       // must have their values written to the caller stack frame.
>       if ((isVarArg) && (Subtarget->isABI_O32())) {
> -        if (StackPtr.Val == 0)
> +        if (StackPtr.getNode() == 0)
>           StackPtr = DAG.getRegister(StackReg, getPointerTy());
>
>         // The stack pointer offset is relative to the caller stack  
> frame.
> @@ -925,7 +925,7 @@
>   ArgValues.push_back(Root);
>
>   // Return the new list of results.
> -  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
> +  return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
>                             ArgValues.size()).getValue(Op.getResNo());
> }
>
> @@ -946,7 +946,7 @@
>   CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
>
>   // Analize return values of ISD::RET
> -  CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
> +  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Mips);
>
>   // If this is the first return lowered for this function, add
>   // the regs to the liveout set for the function.
> @@ -992,7 +992,7 @@
>   }
>
>   // Return on Mips is always a "jr $ra"
> -  if (Flag.Val)
> +  if (Flag.getNode())
>     return DAG.getNode(MipsISD::Ret, MVT::Other,
>                        Chain, DAG.getRegister(Mips::RA, MVT::i32),  
> Flag);
>   else // Return Void
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -168,11 +168,11 @@
>     if (LD) {
>       fsr = LD->getBasePtr();
>     }
> -    else if (isa<RegisterSDNode>(N.Val)) {
> +    else if (isa<RegisterSDNode>(N.getNode())) {
>       //FIXME an attempt to retrieve the register number
>       //but does not work
>       DOUT << "this is a register\n";
> -      Reg = dyn_cast<RegisterSDNode>(N.Val);
> +      Reg = dyn_cast<RegisterSDNode>(N.getNode());
>       fsr = CurDAG->getRegister(Reg->getReg(),MVT::i16);
>     }
>     else {
> @@ -198,7 +198,7 @@
>     return true;
>   }
>   else if (N.getOpcode() == PIC16ISD::Package) {
> -    CurDAG->setGraphColor(Op.Val, "blue");
> +    CurDAG->setGraphColor(Op.getNode(), "blue");
>     CurDAG->viewGraph();
>   }
>
> @@ -227,7 +227,7 @@
> /// expanded, promoted and normal instructions.
> SDNode* PIC16DAGToDAGISel::Select(SDValue N)
> {
> -  SDNode *Node = N.Val;
> +  SDNode *Node = N.getNode();
>   unsigned Opcode = Node->getOpcode();
>
>   // Dump information about the Node being selected
> @@ -262,8 +262,8 @@
>
> #ifndef NDEBUG
>   DOUT << std::string(Indent-2, ' ') << "=> ";
> -  if (ResNode == NULL || ResNode == N.Val)
> -    DEBUG(N.Val->dump(CurDAG));
> +  if (ResNode == NULL || ResNode == N.getNode())
> +    DEBUG(N.getNode()->dump(CurDAG));
>   else
>     DEBUG(ResNode->dump(CurDAG));
>   DOUT << "\n";
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -334,7 +334,7 @@
>   LoadSDNode *LD  = cast<LoadSDNode>(N);
>   SDValue Ptr   = LD->getBasePtr();
>   if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
> -    if (ISD::isNON_TRUNCStore(Chain.Val)) {
> +    if (ISD::isNON_TRUNCStore(Chain.getNode())) {
>       StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
>       if (PrevST->getBasePtr() == Ptr &&
>           PrevST->getValue().getValueType() == N->getValueType(0))
> @@ -352,7 +352,7 @@
>   Outs[1] = DAG.getLoad(MVT::i8, Chain, toWorklist, NULL, 0);
>   // FIXME: Add to worklist may not be needed.
>   // It is meant to merge sequences of add with constant into one.
> -  DCI.AddToWorklist(toWorklist.Val);
> +  DCI.AddToWorklist(toWorklist.getNode());
>
>   // Create the tokenfactors and carry it on to the build_pair node
>   OutChains[0] = Outs[0].getValue(1);
> @@ -443,7 +443,7 @@
>       changed = true;
>       // LowerLOAD returns a Package node or it may combine and return
>       // anything else.
> -      SDValue lowered = LowerLOAD(InOp[i].Val, DAG, DCI);
> +      SDValue lowered = LowerLOAD(InOp[i].getNode(), DAG, DCI);
>
>       // So If LowerLOAD returns something other than Package,
>       // then just call ADD again.
> @@ -462,7 +462,7 @@
>       changed = true;
>       // Must call LowerADDSUB recursively here,
>       // LowerADDSUB returns a Package node.
> -      SDValue lowered = LowerADDSUB(InOp[i].Val, DAG, DCI);
> +      SDValue lowered = LowerADDSUB(InOp[i].getNode(), DAG, DCI);
>
>       LoOps[i] = lowered.getOperand(0);
>       HiOps[i] = lowered.getOperand(1);
> @@ -543,7 +543,7 @@
>   // FIXME: Just copy right now.
>   ArgValues.push_back(Root);
>
> -  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
> +  return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
>                             ArgValues.size()).getValue(Op.getResNo());
> }
>
> @@ -622,7 +622,7 @@
>       if ((Src.getOpcode() == ISD::ANY_EXTEND) ||
>           (Src.getOpcode() == ISD::SIGN_EXTEND) ||
>           (Src.getOpcode() == ISD::ZERO_EXTEND)) {
> -        Src = Src.Val->getOperand(0);
> +        Src = Src.getNode()->getOperand(0);
>         Stores[0] = DAG.getStore(Chain, Src, Dest, NULL,0);
>         return Stores[0];
>       }
> @@ -721,10 +721,10 @@
>           // We want to merge sequence of add with constant to one  
> add and a
>           // constant, so add the ADD node to worklist to have llvm  
> do that
>           // automatically.
> -          DCI.AddToWorklist(toWorkList.Val);
> +          DCI.AddToWorklist(toWorkList.getNode());
>
>           // We don't need the Package so add to worklist so llvm  
> deletes it
> -          DCI.AddToWorklist(Src.Val);
> +          DCI.AddToWorklist(Src.getNode());
>           retVal = DAG.getNode(ISD::TokenFactor, MVT::Other,  
> &Stores[0], 2);
>         }
>
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -294,7 +294,7 @@
>       BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
>     }
>   }
> -  return CurDAG->getRegister(GlobalBaseReg,  
> PPCLowering.getPointerTy()).Val;
> +  return CurDAG->getRegister(GlobalBaseReg,  
> PPCLowering.getPointerTy()).getNode();
> }
>
> /// isIntS16Immediate - This method tests to see if the node is  
> either a 32-bit
> @@ -313,7 +313,7 @@
> }
>
> static bool isIntS16Immediate(SDValue Op, short &Imm) {
> -  return isIntS16Immediate(Op.Val, Imm);
> +  return isIntS16Immediate(Op.getNode(), Imm);
> }
>
>
> @@ -340,7 +340,7 @@
> // isInt32Immediate - This method tests to see if a constant operand.
> // If so Imm will receive the 32 bit value.
> static bool isInt32Immediate(SDValue N, unsigned &Imm) {
> -  return isInt32Immediate(N.Val, Imm);
> +  return isInt32Immediate(N.getNode(), Imm);
> }
>
>
> @@ -348,7 +348,7 @@
> // opcode and that it has a immediate integer right operand.
> // If so Imm will receive the 32 bit value.
> static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned&  
> Imm) {
> -  return N->getOpcode() == Opc && isInt32Immediate(N- 
> >getOperand(1).Val, Imm);
> +  return N->getOpcode() == Opc && isInt32Immediate(N- 
> >getOperand(1).getNode(), Imm);
> }
>
> bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB,  
> unsigned &ME) {
> @@ -384,7 +384,7 @@
>   unsigned Indeterminant = ~0;  // bit mask marking indeterminant  
> results
>   unsigned Opcode = N->getOpcode();
>   if (N->getNumOperands() != 2 ||
> -      !isInt32Immediate(N->getOperand(1).Val, Shift) || (Shift > 31))
> +      !isInt32Immediate(N->getOperand(1).getNode(), Shift) ||  
> (Shift > 31))
>     return false;
>
>   if (Opcode == ISD::SHL) {
> @@ -540,7 +540,7 @@
>   } else if (LHS.getValueType() == MVT::i64) {
>     uint64_t Imm;
>     if (CC == ISD::SETEQ || CC == ISD::SETNE) {
> -      if (isInt64Immediate(RHS.Val, Imm)) {
> +      if (isInt64Immediate(RHS.getNode(), Imm)) {
>         // SETEQ/SETNE comparison with 16-bit immediate, fold it.
>         if (isUInt16(Imm))
>           return SDValue(CurDAG->getTargetNode(PPC::CMPLDI,  
> MVT::i64, LHS,
> @@ -568,7 +568,7 @@
>       }
>       Opc = PPC::CMPLD;
>     } else if (ISD::isUnsignedIntSetCC(CC)) {
> -      if (isInt64Immediate(RHS.Val, Imm) && isUInt16(Imm))
> +      if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm))
>         return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64,  
> LHS,
>                                                getI64Imm(Imm &  
> 0xFFFF)), 0);
>       Opc = PPC::CMPLD;
> @@ -653,7 +653,7 @@
> }
>
> SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
> -  SDNode *N = Op.Val;
> +  SDNode *N = Op.getNode();
>   unsigned Imm;
>   ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
>   if (isInt32Immediate(N->getOperand(1), Imm)) {
> @@ -773,7 +773,7 @@
> // Select - Convert the specified operand from a target-independent  
> to a
> // target-specific node if it hasn't already been changed.
> SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
> -  SDNode *N = Op.Val;
> +  SDNode *N = Op.getNode();
>   if (N->isMachineOpcode())
>     return NULL;   // Already selected.
>
> @@ -974,7 +974,7 @@
>     // If this is an and of a value rotated between 0 and 31 bits  
> and then and'd
>     // with a mask, emit rlwinm
>     if (isInt32Immediate(N->getOperand(1), Imm) &&
> -        isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB,  
> ME)) {
> +        isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH,  
> MB, ME)) {
>       SDValue Val = N->getOperand(0).getOperand(0);
>       AddToISelQueue(Val);
>       SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB),  
> getI32Imm(ME) };
> @@ -1025,7 +1025,7 @@
>     break;
>   case ISD::SHL: {
>     unsigned Imm, SH, MB, ME;
> -    if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
> +    if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND,  
> Imm) &&
>         isRotateAndMask(N, Imm, true, SH, MB, ME)) {
>       AddToISelQueue(N->getOperand(0).getOperand(0));
>       SDValue Ops[] = { N->getOperand(0).getOperand(0),
> @@ -1038,7 +1038,7 @@
>   }
>   case ISD::SRL: {
>     unsigned Imm, SH, MB, ME;
> -    if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
> +    if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND,  
> Imm) &&
>         isRotateAndMask(N, Imm, true, SH, MB, ME)) {
>       AddToISelQueue(N->getOperand(0).getOperand(0));
>       SDValue Ops[] = { N->getOperand(0).getOperand(0),
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -423,7 +423,7 @@
> static bool isFloatingPointZero(SDValue Op) {
>   if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
>     return CFP->getValueAPF().isZero();
> -  else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
> +  else if (ISD::isEXTLoad(Op.getNode()) ||  
> ISD::isNON_EXTLoad(Op.getNode())) {
>     // Maybe this has already been legalized into the constant pool?
>     if (ConstantPoolSDNode *CP =  
> dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
>       if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
> @@ -625,7 +625,7 @@
>       if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
>
>
> -      if (UniquedVals[i&(Multiple-1)].Val == 0)
> +      if (UniquedVals[i&(Multiple-1)].getNode() == 0)
>         UniquedVals[i&(Multiple-1)] = N->getOperand(i);
>       else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
>         return SDValue();  // no match.
> @@ -640,21 +640,21 @@
>     bool LeadingZero = true;
>     bool LeadingOnes = true;
>     for (unsigned i = 0; i != Multiple-1; ++i) {
> -      if (UniquedVals[i].Val == 0) continue;  // Must have been  
> undefs.
> +      if (UniquedVals[i].getNode() == 0) continue;  // Must have  
> been undefs.
>
>       LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])- 
> >isNullValue();
>       LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])- 
> >isAllOnesValue();
>     }
>     // Finally, check the least significant entry.
>     if (LeadingZero) {
> -      if (UniquedVals[Multiple-1].Val == 0)
> +      if (UniquedVals[Multiple-1].getNode() == 0)
>         return DAG.getTargetConstant(0, MVT::i32);  // 0,0,0,undef
>       int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])- 
> >getValue();
>       if (Val < 16)
>         return DAG.getTargetConstant(Val, MVT::i32);  // 0,0,0,4 ->  
> vspltisw(4)
>     }
>     if (LeadingOnes) {
> -      if (UniquedVals[Multiple-1].Val == 0)
> +      if (UniquedVals[Multiple-1].getNode() == 0)
>         return DAG.getTargetConstant(~0U, MVT::i32);  //  
> -1,-1,-1,undef
>       int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])- 
> >getSignExtended();
>       if (Val >= -16)                            // -1,-1,-1,-2 ->  
> vspltisw(-2)
> @@ -667,13 +667,13 @@
>   // Check to see if this buildvec has a single non-undef value in  
> its elements.
>   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
>     if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
> -    if (OpVal.Val == 0)
> +    if (OpVal.getNode() == 0)
>       OpVal = N->getOperand(i);
>     else if (OpVal != N->getOperand(i))
>       return SDValue();
>   }
>
> -  if (OpVal.Val == 0) return SDValue();  // All UNDEF: use implicit  
> def.
> +  if (OpVal.getNode() == 0) return SDValue();  // All UNDEF: use  
> implicit def.
>
>   unsigned ValSizeInBytes = 0;
>   uint64_t Value = 0;
> @@ -735,7 +735,7 @@
>     return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
> }
> static bool isIntS16Immediate(SDValue Op, short &Imm) {
> -  return isIntS16Immediate(Op.Val, Imm);
> +  return isIntS16Immediate(Op.getNode(), Imm);
> }
>
>
> @@ -1389,7 +1389,7 @@
>   // to handle Elf here.
>   unsigned VecArgOffset = ArgOffset;
>   if (!isVarArg && !isPPC64) {
> -    for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo !=  
> e;
> +    for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1;  
> ArgNo != e;
>          ++ArgNo) {
>       MVT ObjectVT = Op.getValue(ArgNo).getValueType();
>       unsigned ObjSize = ObjectVT.getSizeInBits()/8;
> @@ -1439,7 +1439,7 @@
>
>   SmallVector<SDValue, 8> MemOps;
>   unsigned nAltivecParamsAtEnd = 0;
> -  for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo !=  
> e; ++ArgNo) {
> +  for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1;  
> ArgNo != e; ++ArgNo) {
>     SDValue ArgVal;
>     bool needsLoad = false;
>     MVT ObjectVT = Op.getValue(ArgNo).getValueType();
> @@ -1765,7 +1765,7 @@
>   ArgValues.push_back(Root);
>
>   // Return the new list of results.
> -  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
> +  return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
>                             ArgValues.size());
> }
>
> @@ -1906,7 +1906,7 @@
>     return 0;  // Top 6 bits have to be sext of immediate.
>
>   return DAG.getConstant((int)C->getValue() >> 2,
> -                          
> DAG.getTargetLoweringInfo().getPointerTy()).Val;
> +                          
> DAG.getTargetLoweringInfo().getPointerTy()).getNode();
> }
>
> namespace {
> @@ -2001,10 +2001,10 @@
>     MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
>     LROpOut = getReturnAddrFrameIndex(DAG);
>     LROpOut = DAG.getLoad(VT, Chain, LROpOut, NULL, 0);
> -    Chain = SDValue(LROpOut.Val, 1);
> +    Chain = SDValue(LROpOut.getNode(), 1);
>     FPOpOut = getFramePointerFrameIndex(DAG);
>     FPOpOut = DAG.getLoad(VT, Chain, FPOpOut, NULL, 0);
> -    Chain = SDValue(FPOpOut.Val, 1);
> +    Chain = SDValue(FPOpOut.getNode(), 1);
>   }
>   return Chain;
> }
> @@ -2193,12 +2193,12 @@
>           SDValue Const = DAG.getConstant(4 - Size,  
> PtrOff.getValueType());
>           SDValue AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff,  
> Const);
>           SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
> -                                CallSeqStart.Val->getOperand(0),
> +                                CallSeqStart.getNode()- 
> >getOperand(0),
>                                 Flags, DAG, Size);
>           // This must go outside the CALLSEQ_START..END.
>           SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
> -                               CallSeqStart.Val->getOperand(1));
> -          DAG.ReplaceAllUsesWith(CallSeqStart.Val,  
> NewCallSeqStart.Val);
> +                               CallSeqStart.getNode()- 
> >getOperand(1));
> +          DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),  
> NewCallSeqStart.getNode());
>           Chain = CallSeqStart = NewCallSeqStart;
>           ArgOffset += PtrByteSize;
>         }
> @@ -2208,12 +2208,12 @@
>       // code assumes it is there, even if it could be put entirely  
> into
>       // registers.  (This is not what the doc says.)
>       SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
> -                            CallSeqStart.Val->getOperand(0),
> +                            CallSeqStart.getNode()->getOperand(0),
>                             Flags, DAG, Size);
>       // This must go outside the CALLSEQ_START..END.
>       SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
> -                           CallSeqStart.Val->getOperand(1));
> -      DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
> +                           CallSeqStart.getNode()->getOperand(1));
> +      DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),  
> NewCallSeqStart.getNode());
>       Chain = CallSeqStart = NewCallSeqStart;
>       // And copy the pieces of it that fit into registers.
>       for (unsigned j=0; j<Size; j+=PtrByteSize) {
> @@ -2432,7 +2432,7 @@
>     CallSeqOps.push_back(Chain);
>     CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes));
>     CallSeqOps.push_back(DAG.getIntPtrConstant(0));
> -    if (InFlag.Val)
> +    if (InFlag.getNode())
>       CallSeqOps.push_back(InFlag);
>     Chain = DAG.getNode(ISD::CALLSEQ_END, CallSeqNodeTys,  
> &CallSeqOps[0],
>                         CallSeqOps.size());
> @@ -2460,7 +2460,7 @@
>     // Otherwise, this is an indirect call.  We have to use a MTCTR/ 
> BCTRL pair
>     // to do the call, we can't use PPCISD::CALL.
>     SDValue MTCTROps[] = {Chain, Callee, InFlag};
> -    Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+ 
> (InFlag.Val!=0));
> +    Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+ 
> (InFlag.getNode()!=0));
>     InFlag = Chain.getValue(1);
>
>     // Copy the callee address into R12/X12 on darwin.
> @@ -2475,14 +2475,14 @@
>     NodeTys.push_back(MVT::Flag);
>     Ops.push_back(Chain);
>     CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
> -    Callee.Val = 0;
> +    Callee.setNode(0);
>     // Add CTR register as callee so a bctr can be emitted later.
>     if (isTailCall)
>       Ops.push_back(DAG.getRegister(PPC::CTR, getPointerTy()));
>   }
>
>   // If this is a direct call, pass the chain and the callee.
> -  if (Callee.Val) {
> +  if (Callee.getNode()) {
>     Ops.push_back(Chain);
>     Ops.push_back(Callee);
>   }
> @@ -2502,16 +2502,16 @@
>   int BytesCalleePops =
>     (CC==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0;
>
> -  if (InFlag.Val)
> +  if (InFlag.getNode())
>     Ops.push_back(InFlag);
>
>   // Emit tail call.
>   if (isTailCall) {
> -    assert(InFlag.Val &&
> +    assert(InFlag.getNode() &&
>            "Flag must be set. Depend on flag being set in LowerRET");
>     Chain = DAG.getNode(PPCISD::TAILCALL,
> -                        Op.Val->getVTList(), &Ops[0], Ops.size());
> -    return SDValue(Chain.Val, Op.getResNo());
> +                        Op.getNode()->getVTList(), &Ops[0],  
> Ops.size());
> +    return SDValue(Chain.getNode(), Op.getResNo());
>   }
>
>   Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
> @@ -2521,14 +2521,14 @@
>                              DAG.getConstant(NumBytes, PtrVT),
>                              DAG.getConstant(BytesCalleePops, PtrVT),
>                              InFlag);
> -  if (Op.Val->getValueType(0) != MVT::Other)
> +  if (Op.getNode()->getValueType(0) != MVT::Other)
>     InFlag = Chain.getValue(1);
>
>   SmallVector<SDValue, 16> ResultVals;
>   SmallVector<CCValAssign, 16> RVLocs;
>   unsigned CallerCC = DAG.getMachineFunction().getFunction()- 
> >getCallingConv();
>   CCState CCInfo(CallerCC, isVarArg, TM, RVLocs);
> -  CCInfo.AnalyzeCallResult(Op.Val, RetCC_PPC);
> +  CCInfo.AnalyzeCallResult(Op.getNode(), RetCC_PPC);
>
>   // Copy all of the result registers out of their specified physreg.
>   for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
> @@ -2546,7 +2546,7 @@
>
>   // Otherwise, merge everything together with a MERGE_VALUES node.
>   ResultVals.push_back(Chain);
> -  SDValue Res = DAG.getMergeValues(Op.Val->getVTList(),  
> &ResultVals[0],
> +  SDValue Res = DAG.getMergeValues(Op.getNode()->getVTList(),  
> &ResultVals[0],
>                                      ResultVals.size());
>   return Res.getValue(Op.getResNo());
> }
> @@ -2557,7 +2557,7 @@
>   unsigned CC = DAG.getMachineFunction().getFunction()- 
> >getCallingConv();
>   bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
>   CCState CCInfo(CC, isVarArg, TM, RVLocs);
> -  CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
> +  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_PPC);
>
>   // If this is the first return lowered for this function, add the  
> regs to the
>   // liveout set for the function.
> @@ -2607,7 +2607,7 @@
>     Flag = Chain.getValue(1);
>   }
>
> -  if (Flag.Val)
> +  if (Flag.getNode())
>     return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
>   else
>     return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
> @@ -2818,11 +2818,11 @@
> SDValue PPCTargetLowering::LowerFP_ROUND_INREG(SDValue Op,
>                                                  SelectionDAG &DAG) {
>   assert(Op.getValueType() == MVT::ppcf128);
> -  SDNode *Node = Op.Val;
> +  SDNode *Node = Op.getNode();
>   assert(Node->getOperand(0).getValueType() == MVT::ppcf128);
> -  assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR);
> -  SDValue Lo = Node->getOperand(0).Val->getOperand(0);
> -  SDValue Hi = Node->getOperand(0).Val->getOperand(1);
> +  assert(Node->getOperand(0).getNode()->getOpcode() ==  
> ISD::BUILD_PAIR);
> +  SDValue Lo = Node->getOperand(0).getNode()->getOperand(0);
> +  SDValue Hi = Node->getOperand(0).getNode()->getOperand(1);
>
>   // This sequence changes FPSCR to do round-to-zero, adds the two  
> halves
>   // of the long double, and puts FPSCR back the way it was.  We do  
> not
> @@ -3237,7 +3237,7 @@
>   // zero.
>   uint64_t VectorBits[2];
>   uint64_t UndefBits[2];
> -  if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
> +  if (GetConstantBuildVectorBits(Op.getNode(), VectorBits,  
> UndefBits))
>     return SDValue();   // Not a constant vector.
>
>   // If this is a splat (repetition) of a value across the whole  
> vector, return
> @@ -3483,18 +3483,18 @@
>   // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they  
> can be
>   // selected by the instruction selector.
>   if (V2.getOpcode() == ISD::UNDEF) {
> -    if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
> -        PPC::isSplatShuffleMask(PermMask.Val, 2) ||
> -        PPC::isSplatShuffleMask(PermMask.Val, 4) ||
> -        PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
> -        PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
> -        PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
> -        PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
> -        PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
> -        PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
> -        PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
> -        PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
> -        PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
> +    if (PPC::isSplatShuffleMask(PermMask.getNode(), 1) ||
> +        PPC::isSplatShuffleMask(PermMask.getNode(), 2) ||
> +        PPC::isSplatShuffleMask(PermMask.getNode(), 4) ||
> +        PPC::isVPKUWUMShuffleMask(PermMask.getNode(), true) ||
> +        PPC::isVPKUHUMShuffleMask(PermMask.getNode(), true) ||
> +        PPC::isVSLDOIShuffleMask(PermMask.getNode(), true) != -1 ||
> +        PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, true) ||
> +        PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, true) ||
> +        PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, true) ||
> +        PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, true) ||
> +        PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, true) ||
> +        PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, true)) {
>       return Op;
>     }
>   }
> @@ -3502,15 +3502,15 @@
>   // Altivec has a variety of "shuffle immediates" that take two  
> vector inputs
>   // and produce a fixed permutation.  If any of these match, do not  
> lower to
>   // VPERM.
> -  if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
> -      PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
> -      PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
> -      PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
> -      PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
> -      PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
> -      PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
> -      PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
> -      PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
> +  if (PPC::isVPKUWUMShuffleMask(PermMask.getNode(), false) ||
> +      PPC::isVPKUHUMShuffleMask(PermMask.getNode(), false) ||
> +      PPC::isVSLDOIShuffleMask(PermMask.getNode(), false) != -1 ||
> +      PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, false) ||
> +      PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, false) ||
> +      PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, false) ||
> +      PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, false) ||
> +      PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, false) ||
> +      PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, false))
>     return Op;
>
>   // Check to see if this is a shuffle of 4-byte values.  If so, we  
> can use our
> @@ -3842,7 +3842,7 @@
>     // Use MERGE_VALUES to drop the chain result value and get a  
> node with one
>     // result.  This requires turning off getMergeValues  
> simplification, since
>     // otherwise it will give us Res back.
> -    return DAG.getMergeValues(&Res, 1, false).Val;
> +    return DAG.getMergeValues(&Res, 1, false).getNode();
>   }
>   }
> }
> @@ -4292,17 +4292,17 @@
>           SDValue Val = N->getOperand(0).getOperand(0);
>           if (Val.getValueType() == MVT::f32) {
>             Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
> -            DCI.AddToWorklist(Val.Val);
> +            DCI.AddToWorklist(Val.getNode());
>           }
>
>           Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
> -          DCI.AddToWorklist(Val.Val);
> +          DCI.AddToWorklist(Val.getNode());
>           Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
> -          DCI.AddToWorklist(Val.Val);
> +          DCI.AddToWorklist(Val.getNode());
>           if (N->getValueType(0) == MVT::f32) {
>             Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val,
>                               DAG.getIntPtrConstant(0));
> -            DCI.AddToWorklist(Val.Val);
> +            DCI.AddToWorklist(Val.getNode());
>           }
>           return Val;
>         } else if (N->getOperand(0).getValueType() == MVT::i32) {
> @@ -4322,20 +4322,20 @@
>       SDValue Val = N->getOperand(1).getOperand(0);
>       if (Val.getValueType() == MVT::f32) {
>         Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
> -        DCI.AddToWorklist(Val.Val);
> +        DCI.AddToWorklist(Val.getNode());
>       }
>       Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
> -      DCI.AddToWorklist(Val.Val);
> +      DCI.AddToWorklist(Val.getNode());
>
>       Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N- 
> >getOperand(0), Val,
>                         N->getOperand(2), N->getOperand(3));
> -      DCI.AddToWorklist(Val.Val);
> +      DCI.AddToWorklist(Val.getNode());
>       return Val;
>     }
>
>     // Turn STORE (BSWAP) -> sthbrx/stwbrx.
>     if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
> -        N->getOperand(1).Val->hasOneUse() &&
> +        N->getOperand(1).getNode()->hasOneUse() &&
>         (N->getOperand(1).getValueType() == MVT::i32 ||
>          N->getOperand(1).getValueType() == MVT::i16)) {
>       SDValue BSwapOp = N->getOperand(1).getOperand(0);
> @@ -4350,7 +4350,7 @@
>     break;
>   case ISD::BSWAP:
>     // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
> -    if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
> +    if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
>         N->getOperand(0).hasOneUse() &&
>         (N->getValueType(0) == MVT::i32 || N->getValueType(0) ==  
> MVT::i16)) {
>       SDValue Load = N->getOperand(0);
> @@ -4379,7 +4379,7 @@
>
>       // Next, combine the load away, we give it a bogus result  
> value but a real
>       // chain result.  The result value is dead because the bswap  
> is dead.
> -      DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
> +      DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
>
>       // Return N so it doesn't get rechecked!
>       return SDValue(N, 0);
> @@ -4398,7 +4398,7 @@
>       // Scan all of the users of the LHS, looking for VCMPo's that  
> match.
>       SDNode *VCMPoNode = 0;
>
> -      SDNode *LHSN = N->getOperand(0).Val;
> +      SDNode *LHSN = N->getOperand(0).getNode();
>       for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN- 
> >use_end();
>            UI != E; ++UI)
>         if (UI->getOpcode() == PPCISD::VCMPo &&
> @@ -4650,7 +4650,7 @@
>   }
>   }
>
> -  if (Result.Val) {
> +  if (Result.getNode()) {
>     Ops.push_back(Result);
>     return;
>   }
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td Thu Aug 28  
> 16:40:38 2008
> @@ -113,7 +113,7 @@
>   return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
> }]>;
> def vecspltisb : PatLeaf<(build_vector), [{
> -  return PPC::get_VSPLTI_elt(N, 1, *CurDAG).Val != 0;
> +  return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0;
> }], VSPLTISB_get_imm>;
>
> // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH  
> imm.
> @@ -121,7 +121,7 @@
>   return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
> }]>;
> def vecspltish : PatLeaf<(build_vector), [{
> -  return PPC::get_VSPLTI_elt(N, 2, *CurDAG).Val != 0;
> +  return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0;
> }], VSPLTISH_get_imm>;
>
> // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW  
> imm.
> @@ -129,7 +129,7 @@
>   return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
> }]>;
> def vecspltisw : PatLeaf<(build_vector), [{
> -  return PPC::get_VSPLTI_elt(N, 4, *CurDAG).Val != 0;
> +  return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0;
> }], VSPLTISW_get_imm>;
>
> def V_immneg0 : PatLeaf<(build_vector), [{
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -120,7 +120,7 @@
>
>   if (Addr.getOpcode() == ISD::ADD) {
>     if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
> -        Predicate_simm13(Addr.getOperand(1).Val))
> +        Predicate_simm13(Addr.getOperand(1).getNode()))
>       return false;  // Let the reg+imm pattern catch this!
>     if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
>         Addr.getOperand(1).getOpcode() == SPISD::Lo)
> @@ -136,7 +136,7 @@
> }
>
> SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
> -  SDNode *N = Op.Val;
> +  SDNode *N = Op.getNode();
>   if (N->isMachineOpcode())
>     return NULL;   // Already selected.
>
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -40,7 +40,7 @@
>   CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs);
>
>   // Analize return values of ISD::RET
> -  CCInfo.AnalyzeReturn(Op.Val, RetCC_Sparc32);
> +  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Sparc32);
>
>   // If this is the first return lowered for this function, add the  
> regs to the
>   // liveout set for the function.
> @@ -66,7 +66,7 @@
>     Flag = Chain.getValue(1);
>   }
>
> -  if (Flag.Val)
> +  if (Flag.getNode())
>     return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain, Flag);
>   return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain);
> }
> @@ -233,7 +233,7 @@
>   // Analyze operands of the call, assigning locations to each  
> operand.
>   SmallVector<CCValAssign, 16> ArgLocs;
>   CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), ArgLocs);
> -  CCInfo.AnalyzeCallOperands(Op.Val, CC_Sparc32);
> +  CCInfo.AnalyzeCallOperands(Op.getNode(), CC_Sparc32);
>
>   // Get the size of the outgoing arguments stack space requirement.
>   unsigned ArgsSize = CCInfo.getNextStackOffset();
> @@ -374,7 +374,7 @@
>       break;
>     }
>
> -    if (ValToStore.Val) {
> +    if (ValToStore.getNode()) {
>       SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
>       SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
>       PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
> @@ -416,7 +416,7 @@
>   NodeTys.push_back(MVT::Other);   // Returns a chain
>   NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy  
> to use.
>   SDValue Ops[] = { Chain, Callee, InFlag };
> -  Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
> +  Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.getNode() ?  
> 3 : 2);
>   InFlag = Chain.getValue(1);
>
>   Chain = DAG.getCALLSEQ_END(Chain,
> @@ -428,7 +428,7 @@
>   SmallVector<CCValAssign, 16> RVLocs;
>   CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs);
>
> -  RVInfo.AnalyzeCallResult(Op.Val, RetCC_Sparc32);
> +  RVInfo.AnalyzeCallResult(Op.getNode(), RetCC_Sparc32);
>   SmallVector<SDValue, 8> ResultVals;
>
>   // Copy all of the result registers out of their specified physreg.
> @@ -448,7 +448,7 @@
>   ResultVals.push_back(Chain);
>
>   // Merge everything together with a MERGE_VALUES node.
> -  return DAG.getMergeValues(Op.Val->getVTList(), &ResultVals[0],
> +  return DAG.getMergeValues(Op.getNode()->getVTList(),  
> &ResultVals[0],
>                             ResultVals.size());
> }
>
> @@ -803,7 +803,7 @@
> }
>
> static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
> -  SDNode *Node = Op.Val;
> +  SDNode *Node = Op.getNode();
>   MVT VT = Node->getValueType(0);
>   SDValue InChain = Node->getOperand(0);
>   SDValue VAListPtr = Node->getOperand(1);
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -80,11 +80,11 @@
>     }
>     void dump() {
>       cerr << "X86ISelAddressMode " << this << "\n";
> -      cerr << "Base.Reg "; if (Base.Reg.Val!=0) Base.Reg.Val->dump();
> +      cerr << "Base.Reg "; if (Base.Reg.getNode()!=0)  
> Base.Reg.getNode()->dump();
>                            else cerr << "nul";
>       cerr << " Base.FrameIndex " << Base.FrameIndex << "\n";
>       cerr << "isRIPRel " << isRIPRel << " Scale" << Scale << "\n";
> -      cerr << "IndexReg "; if (IndexReg.Val!=0) IndexReg.Val->dump();
> +      cerr << "IndexReg "; if (IndexReg.getNode()!=0)  
> IndexReg.getNode()->dump();
>                           else cerr << "nul";
>       cerr << " Disp " << Disp << "\n";
>       cerr << "GV "; if (GV) GV->dump();
> @@ -253,7 +253,7 @@
>     SDNode *User = *I;
>     for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
>       SDValue Op = User->getOperand(i);
> -      if (Op.Val == N && Op.getResNo() == FlagResNo)
> +      if (Op.getNode() == N && Op.getResNo() == FlagResNo)
>         return User;
>     }
>   }
> @@ -272,7 +272,7 @@
>     return;
>
>   for (unsigned i = 0, e = Use->getNumOperands(); !found && i != e; + 
> +i) {
> -    SDNode *N = Use->getOperand(i).Val;
> +    SDNode *N = Use->getOperand(i).getNode();
>     if (N == Skip)
>       continue;
>     if (N == Def) {
> @@ -374,8 +374,8 @@
> static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
>                                  SDValue Store, SDValue TF) {
>   SmallVector<SDValue, 4> Ops;
> -  for (unsigned i = 0, e = TF.Val->getNumOperands(); i != e; ++i)
> -    if (Load.Val == TF.getOperand(i).Val)
> +  for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; + 
> +i)
> +    if (Load.getNode() == TF.getOperand(i).getNode())
>       Ops.push_back(Load.getOperand(0));
>     else
>       Ops.push_back(TF.getOperand(i));
> @@ -404,7 +404,7 @@
>
>   if (N.hasOneUse() &&
>       N.getOperand(1) == Address &&
> -      N.Val->isOperandOf(Chain.Val)) {
> +      N.getNode()->isOperandOf(Chain.getNode())) {
>     Load = N;
>     return true;
>   }
> @@ -416,8 +416,8 @@
> static void MoveBelowCallSeqStart(SelectionDAG *CurDAG, SDValue Load,
>                            SDValue Call, SDValue Chain) {
>   SmallVector<SDValue, 8> Ops;
> -  for (unsigned i = 0, e = Chain.Val->getNumOperands(); i != e; ++i)
> -    if (Load.Val == Chain.getOperand(i).Val)
> +  for (unsigned i = 0, e = Chain.getNode()->getNumOperands(); i !=  
> e; ++i)
> +    if (Load.getNode() == Chain.getOperand(i).getNode())
>       Ops.push_back(Load.getOperand(0));
>     else
>       Ops.push_back(Chain.getOperand(i));
> @@ -425,8 +425,8 @@
>   CurDAG->UpdateNodeOperands(Load, Call.getOperand(0),
>                              Load.getOperand(1), Load.getOperand(2));
>   Ops.clear();
> -  Ops.push_back(SDValue(Load.Val, 1));
> -  for (unsigned i = 1, e = Call.Val->getNumOperands(); i != e; ++i)
> +  Ops.push_back(SDValue(Load.getNode(), 1));
> +  for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i !=  
> e; ++i)
>     Ops.push_back(Call.getOperand(i));
>   CurDAG->UpdateNodeOperands(Call, &Ops[0], Ops.size());
> }
> @@ -435,9 +435,9 @@
> /// moved below CALLSEQ_START and the chains leading up to the call.
> /// Return the CALLSEQ_START by reference as a second output.
> static bool isCalleeLoad(SDValue Callee, SDValue &Chain) {
> -  if (Callee.Val == Chain.Val || !Callee.hasOneUse())
> +  if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
>     return false;
> -  LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.Val);
> +  LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
>   if (!LD ||
>       LD->isVolatile() ||
>       LD->getAddressingMode() != ISD::UNINDEXED ||
> @@ -450,7 +450,7 @@
>       return false;
>     Chain = Chain.getOperand(0);
>   }
> -  return Chain.getOperand(0).Val == Callee.Val;
> +  return Chain.getOperand(0).getNode() == Callee.getNode();
> }
>
>
> @@ -530,7 +530,7 @@
>       continue;
>     SDValue Chain = I->getOperand(0);
>
> -    if (Chain.Val->getOpcode() != ISD::TokenFactor)
> +    if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
>       continue;
>
>     SDValue N1 = I->getOperand(1);
> @@ -542,7 +542,7 @@
>
>     bool RModW = false;
>     SDValue Load;
> -    unsigned Opcode = N1.Val->getOpcode();
> +    unsigned Opcode = N1.getNode()->getOpcode();
>     switch (Opcode) {
>     case ISD::ADD:
>     case ISD::MUL:
> @@ -786,7 +786,7 @@
>     return true;
>   }
>
> -  int id = N.Val->getNodeId();
> +  int id = N.getNode()->getNodeId();
>   bool AlreadySelected = isSelected(id); // Already selected, not  
> yet replaced.
>
>   switch (N.getOpcode()) {
> @@ -808,14 +808,14 @@
>     // Under X86-64 non-small code model, GV (and friends) are 64- 
> bits.
>     // Also, base and index reg must be 0 in order to use rip as base.
>     if (is64Bit && (TM.getCodeModel() != CodeModel::Small ||
> -                    AM.Base.Reg.Val || AM.IndexReg.Val))
> +                    AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
>       break;
>     if (AM.GV != 0 || AM.CP != 0 || AM.ES != 0 || AM.JT != -1)
>       break;
>     // If value is available in a register both base and index  
> components have
>     // been picked, we can't fit the result available in the  
> register in the
>     // addressing mode. Duplicate GlobalAddress or ConstantPool as  
> displacement.
> -    if (!AlreadySelected || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
> +    if (!AlreadySelected || (AM.Base.Reg.getNode() &&  
> AM.IndexReg.getNode())) {
>       SDValue N0 = N.getOperand(0);
>       if (GlobalAddressSDNode *G =  
> dyn_cast<GlobalAddressSDNode>(N0)) {
>         GlobalValue *GV = G->getGlobal();
> @@ -847,7 +847,7 @@
>   }
>
>   case ISD::FrameIndex:
> -    if (AM.BaseType == X86ISelAddressMode::RegBase &&  
> AM.Base.Reg.Val == 0) {
> +    if (AM.BaseType == X86ISelAddressMode::RegBase &&  
> AM.Base.Reg.getNode() == 0) {
>       AM.BaseType = X86ISelAddressMode::FrameIndexBase;
>       AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
>       return false;
> @@ -855,23 +855,23 @@
>     break;
>
>   case ISD::SHL:
> -    if (AlreadySelected || AM.IndexReg.Val != 0 || AM.Scale != 1 ||  
> AM.isRIPRel)
> +    if (AlreadySelected || AM.IndexReg.getNode() != 0 || AM.Scale ! 
> = 1 || AM.isRIPRel)
>       break;
>
> -    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val- 
> >getOperand(1))) {
> +    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getNode()- 
> >getOperand(1))) {
>       unsigned Val = CN->getValue();
>       if (Val == 1 || Val == 2 || Val == 3) {
>         AM.Scale = 1 << Val;
> -        SDValue ShVal = N.Val->getOperand(0);
> +        SDValue ShVal = N.getNode()->getOperand(0);
>
>         // Okay, we know that we have a scale by now.  However, if  
> the scaled
>         // value is an add of something and a constant, we can fold  
> the
>         // constant into the disp field here.
> -        if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse()  
> &&
> -            isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
> -          AM.IndexReg = ShVal.Val->getOperand(0);
> +        if (ShVal.getNode()->getOpcode() == ISD::ADD &&  
> ShVal.hasOneUse() &&
> +            isa<ConstantSDNode>(ShVal.getNode()->getOperand(1))) {
> +          AM.IndexReg = ShVal.getNode()->getOperand(0);
>           ConstantSDNode *AddVal =
> -            cast<ConstantSDNode>(ShVal.Val->getOperand(1));
> +            cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
>           uint64_t Disp = AM.Disp + (AddVal->getValue() << Val);
>           if (isInt32(Disp))
>             AM.Disp = Disp;
> @@ -894,31 +894,31 @@
>     // X*[3,5,9] -> X+X*[2,4,8]
>     if (!AlreadySelected &&
>         AM.BaseType == X86ISelAddressMode::RegBase &&
> -        AM.Base.Reg.Val == 0 &&
> -        AM.IndexReg.Val == 0 &&
> +        AM.Base.Reg.getNode() == 0 &&
> +        AM.IndexReg.getNode() == 0 &&
>         !AM.isRIPRel) {
> -      if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val- 
> >getOperand(1)))
> +      if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getNode()- 
> >getOperand(1)))
>         if (CN->getValue() == 3 || CN->getValue() == 5 || CN- 
> >getValue() == 9) {
>           AM.Scale = unsigned(CN->getValue())-1;
>
> -          SDValue MulVal = N.Val->getOperand(0);
> +          SDValue MulVal = N.getNode()->getOperand(0);
>           SDValue Reg;
>
>           // Okay, we know that we have a scale by now.  However, if  
> the scaled
>           // value is an add of something and a constant, we can  
> fold the
>           // constant into the disp field here.
> -          if (MulVal.Val->getOpcode() == ISD::ADD &&  
> MulVal.hasOneUse() &&
> -              isa<ConstantSDNode>(MulVal.Val->getOperand(1))) {
> -            Reg = MulVal.Val->getOperand(0);
> +          if (MulVal.getNode()->getOpcode() == ISD::ADD &&  
> MulVal.hasOneUse() &&
> +              isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
> +            Reg = MulVal.getNode()->getOperand(0);
>             ConstantSDNode *AddVal =
> -              cast<ConstantSDNode>(MulVal.Val->getOperand(1));
> +              cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
>             uint64_t Disp = AM.Disp + AddVal->getValue() * CN- 
> >getValue();
>             if (isInt32(Disp))
>               AM.Disp = Disp;
>             else
> -              Reg = N.Val->getOperand(0);
> +              Reg = N.getNode()->getOperand(0);
>           } else {
> -            Reg = N.Val->getOperand(0);
> +            Reg = N.getNode()->getOperand(0);
>           }
>
>           AM.IndexReg = AM.Base.Reg = Reg;
> @@ -930,12 +930,12 @@
>   case ISD::ADD:
>     if (!AlreadySelected) {
>       X86ISelAddressMode Backup = AM;
> -      if (!MatchAddress(N.Val->getOperand(0), AM, false, Depth+1) &&
> -          !MatchAddress(N.Val->getOperand(1), AM, false, Depth+1))
> +      if (!MatchAddress(N.getNode()->getOperand(0), AM, false, Depth 
> +1) &&
> +          !MatchAddress(N.getNode()->getOperand(1), AM, false, Depth 
> +1))
>         return false;
>       AM = Backup;
> -      if (!MatchAddress(N.Val->getOperand(1), AM, false, Depth+1) &&
> -          !MatchAddress(N.Val->getOperand(0), AM, false, Depth+1))
> +      if (!MatchAddress(N.getNode()->getOperand(1), AM, false, Depth 
> +1) &&
> +          !MatchAddress(N.getNode()->getOperand(0), AM, false, Depth 
> +1))
>         return false;
>       AM = Backup;
>     }
> @@ -970,7 +970,7 @@
>     if (Shift.getOpcode() != ISD::SHL) break;
>
>     // Scale must not be used already.
> -    if (AM.IndexReg.Val != 0 || AM.Scale != 1) break;
> +    if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
>
>     // Not when RIP is used as the base.
>     if (AM.isRIPRel) break;
> @@ -995,8 +995,8 @@
>                                            SDValue(C2, 0),  
> SDValue(C1, 0));
>     SDValue NewAND = CurDAG->getNode(ISD::AND, N.getValueType(),
>                                        Shift.getOperand(0),  
> NewANDMask);
> -    NewANDMask.Val->setNodeId(Shift.Val->getNodeId());
> -    NewAND.Val->setNodeId(N.Val->getNodeId());
> +    NewANDMask.getNode()->setNodeId(Shift.getNode()->getNodeId());
> +    NewAND.getNode()->setNodeId(N.getNode()->getNodeId());
>
>     AM.Scale = 1 << ShiftCst;
>     AM.IndexReg = NewAND;
> @@ -1012,9 +1012,9 @@
> bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode  
> &AM,
>                                        bool isRoot, unsigned Depth) {
>   // Is the base register already occupied?
> -  if (AM.BaseType != X86ISelAddressMode::RegBase ||  
> AM.Base.Reg.Val) {
> +  if (AM.BaseType != X86ISelAddressMode::RegBase ||  
> AM.Base.Reg.getNode()) {
>     // If so, check to see if the scale index register is set.
> -    if (AM.IndexReg.Val == 0 && !AM.isRIPRel) {
> +    if (AM.IndexReg.getNode() == 0 && !AM.isRIPRel) {
>       AM.IndexReg = N;
>       AM.Scale = 1;
>       return false;
> @@ -1042,11 +1042,11 @@
>
>   MVT VT = N.getValueType();
>   if (AM.BaseType == X86ISelAddressMode::RegBase) {
> -    if (!AM.Base.Reg.Val)
> +    if (!AM.Base.Reg.getNode())
>       AM.Base.Reg = CurDAG->getRegister(0, VT);
>   }
>
> -  if (!AM.IndexReg.Val)
> +  if (!AM.IndexReg.getNode())
>     AM.IndexReg = CurDAG->getRegister(0, VT);
>
>   getAddressOperands(AM, Base, Scale, Index, Disp);
> @@ -1073,10 +1073,10 @@
>                                           SDValue &OutChain) {
>   if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
>     InChain = N.getOperand(0).getValue(1);
> -    if (ISD::isNON_EXTLoad(InChain.Val) &&
> +    if (ISD::isNON_EXTLoad(InChain.getNode()) &&
>         InChain.getValue(0).hasOneUse() &&
>         N.hasOneUse() &&
> -        CanBeFoldedBy(N.Val, Pred.Val, Op.Val)) {
> +        CanBeFoldedBy(N.getNode(), Pred.getNode(), Op.getNode())) {
>       LoadSDNode *LD = cast<LoadSDNode>(InChain);
>       if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
>         return false;
> @@ -1087,11 +1087,11 @@
>
>   // Also handle the case where we explicitly require zeros in the top
>   // elements.  This is a vector shuffle from the zero vector.
> -  if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.Val->hasOneUse() &&
> +  if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()- 
> >hasOneUse() &&
>       // Check to see if the top elements are all zeros (or bitcast  
> of zeros).
>       N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
> -      N.getOperand(0).Val->hasOneUse() &&
> -      ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).Val) &&
> +      N.getOperand(0).getNode()->hasOneUse() &&
> +      ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
>       N.getOperand(0).getOperand(0).hasOneUse()) {
>     // Okay, this is a zero extending load.  Fold it.
>     LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
> @@ -1117,14 +1117,14 @@
>   MVT VT = N.getValueType();
>   unsigned Complexity = 0;
>   if (AM.BaseType == X86ISelAddressMode::RegBase)
> -    if (AM.Base.Reg.Val)
> +    if (AM.Base.Reg.getNode())
>       Complexity = 1;
>     else
>       AM.Base.Reg = CurDAG->getRegister(0, VT);
>   else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
>     Complexity = 4;
>
> -  if (AM.IndexReg.Val)
> +  if (AM.IndexReg.getNode())
>     Complexity++;
>   else
>     AM.IndexReg = CurDAG->getRegister(0, VT);
> @@ -1148,7 +1148,7 @@
>       Complexity += 2;
>   }
>
> -  if (AM.Disp && (AM.Base.Reg.Val || AM.IndexReg.Val))
> +  if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
>     Complexity++;
>
>   if (Complexity > 2) {
> @@ -1161,9 +1161,9 @@
> bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
>                                   SDValue &Base, SDValue &Scale,
>                                   SDValue &Index, SDValue &Disp) {
> -  if (ISD::isNON_EXTLoad(N.Val) &&
> +  if (ISD::isNON_EXTLoad(N.getNode()) &&
>       N.hasOneUse() &&
> -      CanBeFoldedBy(N.Val, P.Val, P.Val))
> +      CanBeFoldedBy(N.getNode(), P.getNode(), P.getNode()))
>     return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp);
>   return false;
> }
> @@ -1198,14 +1198,14 @@
>     }
>
>   }
> -  return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val;
> +  return CurDAG->getRegister(GlobalBaseReg,  
> TLI.getPointerTy()).getNode();
> }
>
> static SDNode *FindCallStartFromCall(SDNode *Node) {
>   if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
>     assert(Node->getOperand(0).getValueType() == MVT::Other &&
>          "Node doesn't have a token chain argument!");
> -  return FindCallStartFromCall(Node->getOperand(0).Val);
> +  return FindCallStartFromCall(Node->getOperand(0).getNode());
> }
>
> /// getTruncateTo8Bit - return an SDNode that implements a subreg  
> based
> @@ -1239,7 +1239,7 @@
>
>
> SDNode *X86DAGToDAGISel::Select(SDValue N) {
> -  SDNode *Node = N.Val;
> +  SDNode *Node = N.getNode();
>   MVT NVT = Node->getValueType(0);
>   unsigned Opc, MOpc;
>   unsigned Opcode = Node->getOpcode();
> @@ -1277,7 +1277,7 @@
>       MVT PtrVT = TLI.getPointerTy();
>       SDValue N0 = N.getOperand(0);
>       SDValue N1 = N.getOperand(1);
> -      if (N.Val->getValueType(0) == PtrVT &&
> +      if (N.getNode()->getValueType(0) == PtrVT &&
>           N0.getOpcode() == X86ISD::Wrapper &&
>           N1.getOpcode() == ISD::Constant) {
>         unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)- 
> >getValue();
> @@ -1294,13 +1294,13 @@
>                                             CP->getOffset()+Offset);
>         }
>
> -        if (C.Val) {
> +        if (C.getNode()) {
>           if (Subtarget->is64Bit()) {
>             SDValue Ops[] = { CurDAG->getRegister(0, PtrVT),  
> getI8Imm(1),
>                                 CurDAG->getRegister(0, PtrVT), C };
> -            return CurDAG->SelectNodeTo(N.Val, X86::LEA64r,  
> MVT::i64, Ops, 4);
> +            return CurDAG->SelectNodeTo(N.getNode(), X86::LEA64r,  
> MVT::i64, Ops, 4);
>           } else
> -            return CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, PtrVT,  
> C);
> +            return CurDAG->SelectNodeTo(N.getNode(), X86::MOV32ri,  
> PtrVT, C);
>         }
>       }
>
> @@ -1379,7 +1379,7 @@
>         ReplaceUses(N.getValue(0), Result);
> #ifndef NDEBUG
>         DOUT << std::string(Indent-2, ' ') << "=> ";
> -        DEBUG(Result.Val->dump(CurDAG));
> +        DEBUG(Result.getNode()->dump(CurDAG));
>         DOUT << "\n";
> #endif
>       }
> @@ -1406,7 +1406,7 @@
>         ReplaceUses(N.getValue(1), Result);
> #ifndef NDEBUG
>         DOUT << std::string(Indent-2, ' ') << "=> ";
> -        DEBUG(Result.Val->dump(CurDAG));
> +        DEBUG(Result.getNode()->dump(CurDAG));
>         DOUT << "\n";
> #endif
>       }
> @@ -1538,7 +1538,7 @@
>         ReplaceUses(N.getValue(0), Result);
> #ifndef NDEBUG
>         DOUT << std::string(Indent-2, ' ') << "=> ";
> -        DEBUG(Result.Val->dump(CurDAG));
> +        DEBUG(Result.getNode()->dump(CurDAG));
>         DOUT << "\n";
> #endif
>       }
> @@ -1565,7 +1565,7 @@
>         ReplaceUses(N.getValue(1), Result);
> #ifndef NDEBUG
>         DOUT << std::string(Indent-2, ' ') << "=> ";
> -        DEBUG(Result.Val->dump(CurDAG));
> +        DEBUG(Result.getNode()->dump(CurDAG));
>         DOUT << "\n";
> #endif
>       }
> @@ -1599,7 +1599,7 @@
>
> #ifndef NDEBUG
>         DOUT << std::string(Indent-2, ' ') << "=> ";
> -        DEBUG(TruncOp.Val->dump(CurDAG));
> +        DEBUG(TruncOp.getNode()->dump(CurDAG));
>         DOUT << "\n";
>         DOUT << std::string(Indent-2, ' ') << "=> ";
>         DEBUG(ResNode->dump(CurDAG));
> @@ -1659,8 +1659,8 @@
>
> #ifndef NDEBUG
>   DOUT << std::string(Indent-2, ' ') << "=> ";
> -  if (ResNode == NULL || ResNode == N.Val)
> -    DEBUG(N.Val->dump(CurDAG));
> +  if (ResNode == NULL || ResNode == N.getNode())
> +    DEBUG(N.getNode()->dump(CurDAG));
>   else
>     DEBUG(ResNode->dump(CurDAG));
>   DOUT << "\n";
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Aug 28  
> 16:40:38 2008
> @@ -852,7 +852,7 @@
>   unsigned CC = DAG.getMachineFunction().getFunction()- 
> >getCallingConv();
>   bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
>   CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
> -  CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
> +  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
>
>   // If this is the first return lowered for this function, add the  
> regs to the
>   // liveout set for the function.
> @@ -944,7 +944,7 @@
>   RetOps[0] = Chain;  // Update chain.
>
>   // Add the flag if we have it.
> -  if (Flag.Val)
> +  if (Flag.getNode())
>     RetOps.push_back(Flag);
>
>   return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0],  
> RetOps.size());
> @@ -1000,7 +1000,7 @@
>   // Merge everything together with a MERGE_VALUES node.
>   ResultVals.push_back(Chain);
>   return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
> -                            ResultVals.size()).Val;
> +                            ResultVals.size()).getNode();
> }
>
>
> @@ -1038,7 +1038,7 @@
> /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node  
> uses struct
> /// return semantics.
> static bool ArgsAreStructReturn(SDValue Op) {
> -  unsigned NumArgs = Op.Val->getNumValues() - 1;
> +  unsigned NumArgs = Op.getNode()->getNumValues() - 1;
>   if (!NumArgs)
>     return false;
>
> @@ -1182,7 +1182,7 @@
>   // Assign locations to all of the incoming arguments.
>   SmallVector<CCValAssign, 16> ArgLocs;
>   CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
> -  CCInfo.AnalyzeFormalArguments(Op.Val, CCAssignFnForNode(Op));
> +  CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(Op));
>
>   SmallVector<SDValue, 8> ArgValues;
>   unsigned LastVal = ~0U;
> @@ -1395,7 +1395,7 @@
>   FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
>
>   // Return the new list of results.
> -  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
> +  return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
>                             ArgValues.size()).getValue(Op.getResNo());
> }
>
> @@ -1433,7 +1433,7 @@
>   OutRetAddr = getReturnAddressFrameIndex(DAG);
>   // Load the "old" Return address.
>   OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0);
> -  return SDValue(OutRetAddr.Val, 1);
> +  return SDValue(OutRetAddr.getNode(), 1);
> }
>
> /// EmitTailCallStoreRetAddr - Emit a store of the return adress if  
> tail call
> @@ -1472,7 +1472,7 @@
>   // Analyze operands of the call, assigning locations to each  
> operand.
>   SmallVector<CCValAssign, 16> ArgLocs;
>   CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
> -  CCInfo.AnalyzeCallOperands(Op.Val, CCAssignFnForNode(Op));
> +  CCInfo.AnalyzeCallOperands(Op.getNode(), CCAssignFnForNode(Op));
>
>   // Get a count of how many bytes are to be pushed on the stack.
>   unsigned NumBytes = CCInfo.getNextStackOffset();
> @@ -1562,7 +1562,7 @@
>     } else {
>       if (!IsTailCall || (IsTailCall && isByVal)) {
>         assert(VA.isMemLoc());
> -        if (StackPtr.Val == 0)
> +        if (StackPtr.getNode() == 0)
>           StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr,  
> getPointerTy());
>
>         MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr,  
> VA, Chain,
> @@ -1658,7 +1658,7 @@
>         if (Flags.isByVal()) {
>           // Copy relative to framepointer.
>           SDValue Source =  
> DAG.getIntPtrConstant(VA.getLocMemOffset());
> -          if (StackPtr.Val == 0)
> +          if (StackPtr.getNode() == 0)
>             StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr,  
> getPointerTy());
>           Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr,  
> Source);
>
> @@ -1719,7 +1719,7 @@
>     Ops.push_back(Chain);
>     Ops.push_back(DAG.getIntPtrConstant(NumBytes));
>     Ops.push_back(DAG.getIntPtrConstant(0));
> -    if (InFlag.Val)
> +    if (InFlag.getNode())
>       Ops.push_back(InFlag);
>     Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0],  
> Ops.size());
>     InFlag = Chain.getValue(1);
> @@ -1751,16 +1751,16 @@
>   if (Is64Bit && isVarArg)
>     Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
>
> -  if (InFlag.Val)
> +  if (InFlag.getNode())
>     Ops.push_back(InFlag);
>
>   if (IsTailCall) {
> -    assert(InFlag.Val &&
> +    assert(InFlag.getNode() &&
>            "Flag must be set. Depend on flag being set in LowerRET");
>     Chain = DAG.getNode(X86ISD::TAILCALL,
> -                        Op.Val->getVTList(), &Ops[0], Ops.size());
> +                        Op.getNode()->getVTList(), &Ops[0],  
> Ops.size());
>
> -    return SDValue(Chain.Val, Op.getResNo());
> +    return SDValue(Chain.getNode(), Op.getResNo());
>   }
>
>   Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
> @@ -1787,7 +1787,7 @@
>
>   // Handle result values, copying them out of physregs into vregs  
> that we
>   // return.
> -  return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG),  
> Op.getResNo());
> +  return SDValue(LowerCallResult(Chain, InFlag, Op.getNode(), CC,  
> DAG), Op.getResNo());
> }
>
>
> @@ -2457,7 +2457,7 @@
>     }
>   }
>
> -  if (!ElementBase.Val)
> +  if (!ElementBase.getNode())
>     return false;
>
>   for (; i != NumElems; ++i) {
> @@ -2661,7 +2661,7 @@
> /// required.
> static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
>   if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
> -    N = N->getOperand(0).Val;
> +    N = N->getOperand(0).getNode();
>     if (ISD::isNON_EXTLoad(N)) {
>       if (LD)
>         *LD = cast<LoadSDNode>(N);
> @@ -2758,18 +2758,18 @@
>
>     unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
>     if (Idx < NumElems) {
> -      unsigned Opc = V1.Val->getOpcode();
> -      if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.Val))
> +      unsigned Opc = V1.getNode()->getOpcode();
> +      if (Opc == ISD::UNDEF ||  
> ISD::isBuildVectorAllZeros(V1.getNode()))
>         continue;
>       if (Opc != ISD::BUILD_VECTOR ||
> -          !isZeroNode(V1.Val->getOperand(Idx)))
> +          !isZeroNode(V1.getNode()->getOperand(Idx)))
>         return false;
>     } else if (Idx >= NumElems) {
> -      unsigned Opc = V2.Val->getOpcode();
> -      if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.Val))
> +      unsigned Opc = V2.getNode()->getOpcode();
> +      if (Opc == ISD::UNDEF ||  
> ISD::isBuildVectorAllZeros(V2.getNode()))
>         continue;
>       if (Opc != ISD::BUILD_VECTOR ||
> -          !isZeroNode(V2.Val->getOperand(Idx - NumElems)))
> +          !isZeroNode(V2.getNode()->getOperand(Idx - NumElems)))
>         return false;
>     }
>   }
> @@ -2958,8 +2958,8 @@
>       ++NumZeros;
>       continue;
>     }
> -    SDValue Elt = DAG.getShuffleScalarElt(Op.Val, Index);
> -    if (Elt.Val && isZeroNode(Elt))
> +    SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index);
> +    if (Elt.getNode() && isZeroNode(Elt))
>       ++NumZeros;
>     else
>       break;
> @@ -3043,7 +3043,7 @@
>       } else
>         ThisElt = LastElt;
>
> -      if (ThisElt.Val)
> +      if (ThisElt.getNode())
>         V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V,  
> ThisElt,
>                         DAG.getIntPtrConstant(i/2));
>     }
> @@ -3097,14 +3097,14 @@
> SDValue
> X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
>   // All zero's are handled with pxor, all one's are handled with  
> pcmpeqd.
> -  if (ISD::isBuildVectorAllZeros(Op.Val) ||  
> ISD::isBuildVectorAllOnes(Op.Val)) {
> +  if (ISD::isBuildVectorAllZeros(Op.getNode()) ||  
> ISD::isBuildVectorAllOnes(Op.getNode())) {
>     // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs  
> MMX) to
>     // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64  
> scalars are
>     // eliminated on x86-32 hosts.
>     if (Op.getValueType() == MVT::v4i32 || Op.getValueType() ==  
> MVT::v2i32)
>       return Op;
>
> -    if (ISD::isBuildVectorAllOnes(Op.Val))
> +    if (ISD::isBuildVectorAllOnes(Op.getNode()))
>       return getOnesVector(Op.getValueType(), DAG);
>     return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(),  
> DAG);
>   }
> @@ -3252,13 +3252,13 @@
>   if (EVTBits == 8 && NumElems == 16) {
>     SDValue V = LowerBuildVectorv16i8(Op,  
> NonZeros,NumNonZero,NumZero, DAG,
>                                         *this);
> -    if (V.Val) return V;
> +    if (V.getNode()) return V;
>   }
>
>   if (EVTBits == 16 && NumElems == 8) {
>     SDValue V = LowerBuildVectorv8i16(Op,  
> NonZeros,NumNonZero,NumZero, DAG,
>                                         *this);
> -    if (V.Val) return V;
> +    if (V.getNode()) return V;
>   }
>
>   // If element VT is == 32 bits, turn it into a number of shuffles.
> @@ -3344,8 +3344,8 @@
>   MVT MaskVT = MVT::getIntVectorWithNumElements(8);
>   MVT MaskEVT = MaskVT.getVectorElementType();
>   MVT PtrVT = TLI.getPointerTy();
> -  SmallVector<SDValue, 8> MaskElts(PermMask.Val->op_begin(),
> -                                   PermMask.Val->op_end());
> +  SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(),
> +                                   PermMask.getNode()->op_end());
>
>   // First record which half of which vector the low elements come  
> from.
>   SmallVector<unsigned, 4> LowQuad(4);
> @@ -3653,7 +3653,7 @@
>                               const X86Subtarget *Subtarget) {
>   if (VT == MVT::v2f64 || VT == MVT::v4f32) {
>     LoadSDNode *LD = NULL;
> -    if (!isScalarLoadToVector(SrcOp.Val, &LD))
> +    if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
>       LD = dyn_cast<LoadSDNode>(SrcOp);
>     if (!LD) {
>       // movssrr and movsdrr do not clear top bits. Try to use movd,  
> movq
> @@ -3850,18 +3850,18 @@
>   bool V1IsSplat = false;
>   bool V2IsSplat = false;
>
> -  if (isUndefShuffle(Op.Val))
> +  if (isUndefShuffle(Op.getNode()))
>     return DAG.getNode(ISD::UNDEF, VT);
>
> -  if (isZeroShuffle(Op.Val))
> +  if (isZeroShuffle(Op.getNode()))
>     return getZeroVector(VT, Subtarget->hasSSE2(), DAG);
>
> -  if (isIdentityMask(PermMask.Val))
> +  if (isIdentityMask(PermMask.getNode()))
>     return V1;
> -  else if (isIdentityMask(PermMask.Val, true))
> +  else if (isIdentityMask(PermMask.getNode(), true))
>     return V2;
>
> -  if (isSplatMask(PermMask.Val)) {
> +  if (isSplatMask(PermMask.getNode())) {
>     if (isMMX || NumElems < 4) return Op;
>     // Promote it to a v4{if}32 splat.
>     return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
> @@ -3871,27 +3871,27 @@
>   // do it!
>   if (VT == MVT::v8i16 || VT == MVT::v16i8) {
>     SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,  
> DAG, *this);
> -    if (NewOp.Val)
> +    if (NewOp.getNode())
>       return DAG.getNode(ISD::BIT_CONVERT, VT,  
> LowerVECTOR_SHUFFLE(NewOp, DAG));
>   } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget- 
> >hasSSE2()))) {
>     // FIXME: Figure out a cleaner way to do this.
>     // Try to make use of movq to zero out the top part.
> -    if (ISD::isBuildVectorAllZeros(V2.Val)) {
> +    if (ISD::isBuildVectorAllZeros(V2.getNode())) {
>       SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
>                                                  DAG, *this);
> -      if (NewOp.Val) {
> +      if (NewOp.getNode()) {
>         SDValue NewV1 = NewOp.getOperand(0);
>         SDValue NewV2 = NewOp.getOperand(1);
>         SDValue NewMask = NewOp.getOperand(2);
> -        if (isCommutedMOVL(NewMask.Val, true, false)) {
> +        if (isCommutedMOVL(NewMask.getNode(), true, false)) {
>           NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask,  
> DAG);
>           return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG,  
> Subtarget);
>         }
>       }
> -    } else if (ISD::isBuildVectorAllZeros(V1.Val)) {
> +    } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
>       SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
>                                                 DAG, *this);
> -      if (NewOp.Val && X86::isMOVLMask(NewOp.getOperand(2).Val))
> +      if (NewOp.getNode() &&  
> X86::isMOVLMask(NewOp.getOperand(2).getNode()))
>         return getVZextMovL(VT, NewOp.getValueType(),  
> NewOp.getOperand(1),
>                              DAG, Subtarget);
>     }
> @@ -3910,24 +3910,24 @@
>     return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
>   }
>
> -  if (X86::isMOVLMask(PermMask.Val)) {
> +  if (X86::isMOVLMask(PermMask.getNode())) {
>     if (V1IsUndef)
>       return V2;
> -    if (ISD::isBuildVectorAllZeros(V1.Val))
> +    if (ISD::isBuildVectorAllZeros(V1.getNode()))
>       return getVZextMovL(VT, VT, V2, DAG, Subtarget);
>     if (!isMMX)
>       return Op;
>   }
>
> -  if (!isMMX && (X86::isMOVSHDUPMask(PermMask.Val) ||
> -                 X86::isMOVSLDUPMask(PermMask.Val) ||
> -                 X86::isMOVHLPSMask(PermMask.Val) ||
> -                 X86::isMOVHPMask(PermMask.Val) ||
> -                 X86::isMOVLPMask(PermMask.Val)))
> +  if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) ||
> +                 X86::isMOVSLDUPMask(PermMask.getNode()) ||
> +                 X86::isMOVHLPSMask(PermMask.getNode()) ||
> +                 X86::isMOVHPMask(PermMask.getNode()) ||
> +                 X86::isMOVLPMask(PermMask.getNode())))
>     return Op;
>
> -  if (ShouldXformToMOVHLPS(PermMask.Val) ||
> -      ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
> +  if (ShouldXformToMOVHLPS(PermMask.getNode()) ||
> +      ShouldXformToMOVLP(V1.getNode(), V2.getNode(),  
> PermMask.getNode()))
>     return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
>
>   if (isShift) {
> @@ -3940,8 +3940,8 @@
>   bool Commuted = false;
>   // FIXME: This should also accept a bitcast of a splat?  Be  
> careful, not
>   // 1,1,1,1 -> v8i16 though.
> -  V1IsSplat = isSplatVector(V1.Val);
> -  V2IsSplat = isSplatVector(V2.Val);
> +  V1IsSplat = isSplatVector(V1.getNode());
> +  V2IsSplat = isSplatVector(V2.getNode());
>
>   // Canonicalize the splat or undef, if present, to be on the RHS.
>   if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
> @@ -3952,7 +3952,7 @@
>   }
>
>   // FIXME: Figure out a cleaner way to do this.
> -  if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
> +  if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) {
>     if (V2IsUndef) return V1;
>     Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
>     if (V2IsSplat) {
> @@ -3960,16 +3960,16 @@
>       // to any V2 element. The instruction selectior won't like  
> this. Get
>       // a corrected mask and commute to form a proper MOVS{S|D}.
>       SDValue NewMask = getMOVLMask(NumElems, DAG);
> -      if (NewMask.Val != PermMask.Val)
> +      if (NewMask.getNode() != PermMask.getNode())
>         Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
>     }
>     return Op;
>   }
>
> -  if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
> -      X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
> -      X86::isUNPCKLMask(PermMask.Val) ||
> -      X86::isUNPCKHMask(PermMask.Val))
> +  if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
> +      X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
> +      X86::isUNPCKLMask(PermMask.getNode()) ||
> +      X86::isUNPCKHMask(PermMask.getNode()))
>     return Op;
>
>   if (V2IsSplat) {
> @@ -3977,11 +3977,11 @@
>     // element then try to match unpck{h|l} again. If match, return a
>     // new vector_shuffle with the corrected mask.
>     SDValue NewMask = NormalizeMask(PermMask, DAG);
> -    if (NewMask.Val != PermMask.Val) {
> -      if (X86::isUNPCKLMask(PermMask.Val, true)) {
> +    if (NewMask.getNode() != PermMask.getNode()) {
> +      if (X86::isUNPCKLMask(PermMask.getNode(), true)) {
>         SDValue NewMask = getUnpacklMask(NumElems, DAG);
>         return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
> -      } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
> +      } else if (X86::isUNPCKHMask(PermMask.getNode(), true)) {
>         SDValue NewMask = getUnpackhMask(NumElems, DAG);
>         return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
>       }
> @@ -3989,23 +3989,23 @@
>   }
>
>   // Normalize the node to match x86 shuffle ops if needed
> -  if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
> +  if (V2.getOpcode() != ISD::UNDEF &&  
> isCommutedSHUFP(PermMask.getNode()))
>       Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
>
>   if (Commuted) {
>     // Commute is back and try unpck* again.
>     Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
> -    if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
> -        X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
> -        X86::isUNPCKLMask(PermMask.Val) ||
> -        X86::isUNPCKHMask(PermMask.Val))
> +    if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
> +        X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
> +        X86::isUNPCKLMask(PermMask.getNode()) ||
> +        X86::isUNPCKHMask(PermMask.getNode()))
>       return Op;
>   }
>
>   // Try PSHUF* first, then SHUFP*.
>   // MMX doesn't have PSHUFD but it does have PSHUFW. While it's  
> theoretically
>   // possible to shuffle a v2i32 using PSHUFW, that's not yet  
> implemented.
> -  if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.Val)) {
> +  if (isMMX && NumElems == 4 &&  
> X86::isPSHUFDMask(PermMask.getNode())) {
>     if (V2.getOpcode() != ISD::UNDEF)
>       return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
>                          DAG.getNode(ISD::UNDEF, VT), PermMask);
> @@ -4014,9 +4014,9 @@
>
>   if (!isMMX) {
>     if (Subtarget->hasSSE2() &&
> -        (X86::isPSHUFDMask(PermMask.Val) ||
> -         X86::isPSHUFHWMask(PermMask.Val) ||
> -         X86::isPSHUFLWMask(PermMask.Val))) {
> +        (X86::isPSHUFDMask(PermMask.getNode()) ||
> +         X86::isPSHUFHWMask(PermMask.getNode()) ||
> +         X86::isPSHUFLWMask(PermMask.getNode()))) {
>       MVT RVT = VT;
>       if (VT == MVT::v4f32) {
>         RVT = MVT::v4i32;
> @@ -4032,15 +4032,15 @@
>     }
>
>     // Binary or unary shufps.
> -    if (X86::isSHUFPMask(PermMask.Val) ||
> -        (V2.getOpcode() == ISD::UNDEF &&  
> X86::isPSHUFDMask(PermMask.Val)))
> +    if (X86::isSHUFPMask(PermMask.getNode()) ||
> +        (V2.getOpcode() == ISD::UNDEF &&  
> X86::isPSHUFDMask(PermMask.getNode())))
>       return Op;
>   }
>
>   // Handle v8i16 specifically since SSE can do byte extraction and  
> insertion.
>   if (VT == MVT::v8i16) {
>     SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG,  
> *this);
> -    if (NewOp.Val)
> +    if (NewOp.getNode())
>       return NewOp;
>   }
>
> @@ -4073,7 +4073,7 @@
>     // result has a single use which is a store or a bitcast to i32.
>     if (!Op.hasOneUse())
>       return SDValue();
> -    SDNode *User = *Op.Val->use_begin();
> +    SDNode *User = *Op.getNode()->use_begin();
>     if (User->getOpcode() != ISD::STORE &&
>         (User->getOpcode() != ISD::BIT_CONVERT ||
>          User->getValueType(0) != MVT::i32))
> @@ -4094,7 +4094,7 @@
>
>   if (Subtarget->hasSSE41()) {
>     SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
> -    if (Res.Val)
> +    if (Res.getNode())
>       return Res;
>   }
>
> @@ -4599,7 +4599,7 @@
> SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG  
> &DAG) {
>   std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG);
>   SDValue FIST = Vals.first, StackSlot = Vals.second;
> -  if (FIST.Val == 0) return SDValue();
> +  if (FIST.getNode() == 0) return SDValue();
>
>   // Load the result.
>   return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
> @@ -4608,7 +4608,7 @@
> SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG  
> &DAG) {
>   std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0),  
> DAG);
>   SDValue FIST = Vals.first, StackSlot = Vals.second;
> -  if (FIST.Val == 0) return 0;
> +  if (FIST.getNode() == 0) return 0;
>
>   MVT VT = N->getValueType(0);
>
> @@ -4618,7 +4618,7 @@
>   // Use MERGE_VALUES to drop the chain result value and get a node  
> with one
>   // result.  This requires turning off getMergeValues  
> simplification, since
>   // otherwise it will give us Res back.
> -  return DAG.getMergeValues(&Res, 1, false).Val;
> +  return DAG.getMergeValues(&Res, 1, false).getNode();
> }
>
> SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
> @@ -5258,7 +5258,7 @@
>       DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
>     };
>
> -    return DAG.getMergeValues(Ops, 2).Val;
> +    return DAG.getMergeValues(Ops, 2).getNode();
>   }
>
>   SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32,  
> rd.getValue(1));
> @@ -5270,7 +5270,7 @@
>
>   // Use a MERGE_VALUES to return the value and chain.
>   Ops[1] = edx.getValue(1);
> -  return DAG.getMergeValues(Ops, 2).Val;
> +  return DAG.getMergeValues(Ops, 2).getNode();
> }
>
> SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG  
> &DAG) {
> @@ -5857,7 +5857,7 @@
>     if (Subtarget->is64Bit()) {
>       Reg = X86::RAX; size = 8;
>     } else //Should go away when LowerType stuff lands
> -      return SDValue(ExpandATOMIC_CMP_SWAP(Op.Val, DAG), 0);
> +      return SDValue(ExpandATOMIC_CMP_SWAP(Op.getNode(), DAG), 0);
>     break;
>   };
>   SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
> @@ -5907,7 +5907,7 @@
>   SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
>   SDValue ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
>   SDValue Vals[2] = { ResultVal, cpOutH.getValue(1) };
> -  return DAG.getMergeValues(Vals, 2).Val;
> +  return DAG.getMergeValues(Vals, 2).getNode();
> }
>
> SDNode* X86TargetLowering::ExpandATOMIC_LOAD_SUB(SDNode* Op,  
> SelectionDAG &DAG) {
> @@ -5920,7 +5920,7 @@
>                         T==MVT::i64 ? ISD::ATOMIC_LOAD_ADD_64: 0),
>                        Op->getOperand(0), Op->getOperand(1), negOp,
>                        cast<AtomicSDNode>(Op)->getSrcValue(),
> -                       cast<AtomicSDNode>(Op)->getAlignment()).Val;
> +                       cast<AtomicSDNode>(Op)- 
> >getAlignment()).getNode();
> }
>
> /// LowerOperation - Provide custom lowering hooks for some  
> operations.
> @@ -5974,7 +5974,7 @@
>
>   // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
>   case ISD::READCYCLECOUNTER:
> -    return SDValue(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0);
> +    return SDValue(ExpandREADCYCLECOUNTER(Op.getNode(), DAG), 0);
>   }
> }
>
> @@ -6135,15 +6135,15 @@
> X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const {
>   // Only do shuffles on 128-bit vector types for now.
>   if (VT.getSizeInBits() == 64) return false;
> -  return (Mask.Val->getNumOperands() <= 4 ||
> -          isIdentityMask(Mask.Val) ||
> -          isIdentityMask(Mask.Val, true) ||
> -          isSplatMask(Mask.Val)  ||
> -          isPSHUFHW_PSHUFLWMask(Mask.Val) ||
> -          X86::isUNPCKLMask(Mask.Val) ||
> -          X86::isUNPCKHMask(Mask.Val) ||
> -          X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
> -          X86::isUNPCKH_v_undef_Mask(Mask.Val));
> +  return (Mask.getNode()->getNumOperands() <= 4 ||
> +          isIdentityMask(Mask.getNode()) ||
> +          isIdentityMask(Mask.getNode(), true) ||
> +          isSplatMask(Mask.getNode())  ||
> +          isPSHUFHW_PSHUFLWMask(Mask.getNode()) ||
> +          X86::isUNPCKLMask(Mask.getNode()) ||
> +          X86::isUNPCKHMask(Mask.getNode()) ||
> +          X86::isUNPCKL_v_undef_Mask(Mask.getNode()) ||
> +          X86::isUNPCKH_v_undef_Mask(Mask.getNode()));
> }
>
> bool
> @@ -6695,11 +6695,11 @@
>     }
>
>     SDValue Elt = DAG.getShuffleScalarElt(N, i);
> -    if (!Elt.Val ||
> -        (Elt.getOpcode() != ISD::UNDEF && ! 
> ISD::isNON_EXTLoad(Elt.Val)))
> +    if (!Elt.getNode() ||
> +        (Elt.getOpcode() != ISD::UNDEF && ! 
> ISD::isNON_EXTLoad(Elt.getNode())))
>       return false;
>     if (!Base) {
> -      Base = Elt.Val;
> +      Base = Elt.getNode();
>       if (Base->getOpcode() == ISD::UNDEF)
>         return false;
>       continue;
> @@ -6707,7 +6707,7 @@
>     if (Elt.getOpcode() == ISD::UNDEF)
>       continue;
>
> -    if (!TLI.isConsecutiveLoad(Elt.Val, Base,
> +    if (!TLI.isConsecutiveLoad(Elt.getNode(), Base,
>                                EVT.getSizeInBits()/8, i, MFI))
>       return false;
>   }
> @@ -6731,7 +6731,7 @@
>     return SDValue();
>
>   LoadSDNode *LD = cast<LoadSDNode>(Base);
> -  if (isBaseAlignmentOfN(16, Base->getOperand(1).Val, TLI))
> +  if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI))
>     return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD- 
> >getSrcValue(),
>                        LD->getSrcValueOffset(), LD->isVolatile());
>   return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD- 
> >getSrcValue(),
> @@ -6762,11 +6762,11 @@
>     return SDValue();
>
>   // Value must be a load.
> -  SDNode *Base = N->getOperand(0).Val;
> +  SDNode *Base = N->getOperand(0).getNode();
>   if (!isa<LoadSDNode>(Base)) {
>     if (Base->getOpcode() != ISD::BIT_CONVERT)
>       return SDValue();
> -    Base = Base->getOperand(0).Val;
> +    Base = Base->getOperand(0).getNode();
>     if (!isa<LoadSDNode>(Base))
>       return SDValue();
>   }
> @@ -6866,11 +6866,11 @@
>       isa<LoadSDNode>(St->getValue()) &&
>       !cast<LoadSDNode>(St->getValue())->isVolatile() &&
>       St->getChain().hasOneUse() && !St->isVolatile()) {
> -    SDNode* LdVal = St->getValue().Val;
> +    SDNode* LdVal = St->getValue().getNode();
>     LoadSDNode *Ld = 0;
>     int TokenFactorIndex = -1;
>     SmallVector<SDValue, 8> Ops;
> -    SDNode* ChainVal = St->getChain().Val;
> +    SDNode* ChainVal = St->getChain().getNode();
>     // Must be a store of a load.  We currently handle two cases:   
> the load
>     // is a direct child, and it's under an intervening  
> TokenFactor.  It is
>     // possible to dig deeper under nested TokenFactors.
> @@ -6879,7 +6879,7 @@
>     else if (St->getValue().hasOneUse() &&
>              ChainVal->getOpcode() == ISD::TokenFactor) {
>       for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; + 
> +i) {
> -        if (ChainVal->getOperand(i).Val == LdVal) {
> +        if (ChainVal->getOperand(i).getNode() == LdVal) {
>           TokenFactorIndex = i;
>           Ld = cast<LoadSDNode>(St->getValue());
>         } else
> @@ -7108,7 +7108,7 @@
>   }
>   }
>
> -  if (Result.Val) {
> +  if (Result.getNode()) {
>     Ops.push_back(Result);
>     return;
>   }
>
> Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=55504&r1=55503&r2=55504&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Thu Aug 28 16:40:38  
> 2008
> @@ -506,17 +506,17 @@
>
>           if (NeedCheck) {
>             std::string ParentName(RootName.begin(),  
> RootName.end()-1);
> -            emitCheck("CanBeFoldedBy(" + RootName + ".Val, " +  
> ParentName +
> -                      ".Val, N.Val)");
> +            emitCheck("CanBeFoldedBy(" + RootName + ".getNode(), "  
> + ParentName +
> +                      ".getNode(), N.getNode())");
>           }
>         }
>       }
>
>       if (NodeHasChain) {
>         if (FoundChain) {
> -          emitCheck("(" + ChainName + ".Val == " + RootName + ".Val  
> || "
> -                    "IsChainCompatible(" + ChainName + ".Val, " +
> -                    RootName + ".Val))");
> +          emitCheck("(" + ChainName + ".getNode() == " + RootName +  
> ".getNode() || "
> +                    "IsChainCompatible(" + ChainName + ".getNode(),  
> " +
> +                    RootName + ".getNode()))");
>           OrigChains.push_back(std::make_pair(ChainName, RootName));
>         } else
>           FoundChain = true;
> @@ -543,7 +543,7 @@
>
>     // If there is a node predicate for this, emit the call.
>     if (!N->getPredicateFn().empty())
> -      emitCheck(N->getPredicateFn() + "(" + RootName + ".Val)");
> +      emitCheck(N->getPredicateFn() + "(" + RootName +  
> ".getNode())");
>
>
>     // If this is an 'and R, 1234' where the operation is AND/OR and  
> the RHS is
> @@ -720,7 +720,7 @@
>         // If there is a node predicate for this, emit the call.
>         if (!Child->getPredicateFn().empty())
>           emitCheck(Child->getPredicateFn() + "(" + RootName +
> -                    ".Val)");
> +                    ".getNode())");
>       } else if (IntInit *II =
>                  dynamic_cast<IntInit*>(Child->getLeafValue())) {
>         emitCheck("isa<ConstantSDNode>(" + RootName + ")");
> @@ -951,8 +951,8 @@
>         // case, the TokenFactor can have more operands.
>         emitCode("SmallVector<SDValue, 8> InChains;");
>         for (unsigned i = 0, e = OrigChains.size(); i < e; ++i) {
> -          emitCode("if (" + OrigChains[i].first + ".Val != " +
> -                   OrigChains[i].second + ".Val) {");
> +          emitCode("if (" + OrigChains[i].first + ".getNode() != " +
> +                   OrigChains[i].second + ".getNode()) {");
>           emitCode("  AddToISelQueue(" + OrigChains[i].first + ");");
>           emitCode("  InChains.push_back(" + OrigChains[i].first +  
> ");");
>           emitCode("}");
> @@ -1164,7 +1164,7 @@
>         std::string Code;
>         for (unsigned j = 0, e = FoldedChains.size(); j < e; j++) {
>           ReplaceFroms.push_back("SDValue(" +
> -                                 FoldedChains[j].first + ".Val, " +
> +                                 FoldedChains[j].first +  
> ".getNode(), " +
>                                  utostr(FoldedChains[j].second) +
>                                  ")");
>           ReplaceTos.push_back("SDValue(ResNode, " +
> @@ -1174,12 +1174,12 @@
>
>       if (NodeHasOutFlag) {
>         if (FoldedFlag.first != "") {
> -          ReplaceFroms.push_back("SDValue(" + FoldedFlag.first +  
> ".Val, " +
> +          ReplaceFroms.push_back("SDValue(" + FoldedFlag.first +  
> ".getNode(), " +
>                                  utostr(FoldedFlag.second) + ")");
>           ReplaceTos.push_back("InFlag");
>         } else {
>           assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP));
> -          ReplaceFroms.push_back("SDValue(N.Val, " +
> +          ReplaceFroms.push_back("SDValue(N.getNode(), " +
>                                  utostr(NumPatResults +  
> (unsigned)InputHasChain)
>                                  + ")");
>           ReplaceTos.push_back("InFlag");
> @@ -1187,9 +1187,9 @@
>       }
>
>       if (!ReplaceFroms.empty() && InputHasChain) {
> -        ReplaceFroms.push_back("SDValue(N.Val, " +
> +        ReplaceFroms.push_back("SDValue(N.getNode(), " +
>                                utostr(NumPatResults) + ")");
> -        ReplaceTos.push_back("SDValue(" + ChainName + ".Val, " +
> +        ReplaceTos.push_back("SDValue(" + ChainName + ".getNode(),  
> " +
>                              ChainName + ".getResNo()" + ")");
>         ChainAssignmentNeeded |= NodeHasChain;
>       }
> @@ -1200,12 +1200,12 @@
>       } else if (InputHasChain && !NodeHasChain) {
>         // One of the inner node produces a chain.
>         if (NodeHasOutFlag) {
> -          ReplaceFroms.push_back("SDValue(N.Val, " +
> +          ReplaceFroms.push_back("SDValue(N.getNode(), " +
>                                  utostr(NumPatResults+1) +
>                                  ")");
>           ReplaceTos.push_back("SDValue(ResNode, N.getResNo()-1)");
>         }
> -        ReplaceFroms.push_back("SDValue(N.Val, " +
> +        ReplaceFroms.push_back("SDValue(N.getNode(), " +
>                                utostr(NumPatResults) + ")");
>         ReplaceTos.push_back(ChainName);
>       }
> @@ -1216,7 +1216,7 @@
>         std::string ChainAssign;
>         if (!isRoot)
>           ChainAssign = ChainName + " = SDValue(" + NodeName +
> -                        ".Val, " + utostr(NumResults+NumDstRegs) +  
> ");";
> +                        ".getNode(), " + utostr(NumResults 
> +NumDstRegs) + ");";
>         else
>           ChainAssign = ChainName + " = SDValue(" + NodeName +
>                         ", " + utostr(NumResults+NumDstRegs) + ");";
> @@ -1251,7 +1251,7 @@
>       if (!isRoot || (InputHasChain && !NodeHasChain)) {
>         Code = "CurDAG->getTargetNode(" + Code;
>       } else {
> -        Code = "CurDAG->SelectNodeTo(N.Val, " + Code;
> +        Code = "CurDAG->SelectNodeTo(N.getNode(), " + Code;
>       }
>       if (isRoot) {
>         if (After.empty())
> @@ -1274,10 +1274,10 @@
>                        ResNodeDecled, true);
>       unsigned ResNo = TmpNo++;
>       emitCode("SDValue Tmp" + utostr(ResNo) + " = Transform_" + Op- 
> >getName()
> -               + "(" + Ops.back() + ".Val);");
> +               + "(" + Ops.back() + ".getNode());");
>       NodeOps.push_back("Tmp" + utostr(ResNo));
>       if (isRoot)
> -        emitCode("return Tmp" + utostr(ResNo) + ".Val;");
> +        emitCode("return Tmp" + utostr(ResNo) + ".getNode();");
>       return NodeOps;
>     } else {
>       N->dump();
> @@ -1298,7 +1298,7 @@
>       Pat->setTypes(Other->getExtTypes());
>       // The top level node type is checked outside of the select  
> function.
>       if (!isRoot)
> -        emitCheck(Prefix + ".Val->getValueType(0) == " +
> +        emitCheck(Prefix + ".getNode()->getValueType(0) == " +
>                   getName(Pat->getTypeNum(0)));
>       return true;
>     }
> @@ -1360,7 +1360,7 @@
>               std::string Decl = (!ResNodeDecled) ? "SDNode *" : "";
>               emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" +  
> ChainName +
>                        ", " + getQualifiedName(RR) +
> -                       ", " +  RootName + utostr(OpNo) + ",  
> InFlag).Val;");
> +                       ", " +  RootName + utostr(OpNo) + ",  
> InFlag).getNode();");
>               ResNodeDecled = true;
>               emitCode(ChainName + " = SDValue(ResNode, 0);");
>               emitCode("InFlag = SDValue(ResNode, 1);");
> @@ -1836,7 +1836,7 @@
>         if (OpName != "ISD::INTRINSIC_W_CHAIN" &&
>             OpName != "ISD::INTRINSIC_WO_CHAIN" &&
>             OpName != "ISD::INTRINSIC_VOID") {
> -          OS << "  N.Val->dump(CurDAG);\n";
> +          OS << "  N.getNode()->dump(CurDAG);\n";
>         } else {
>           OS << "  unsigned iid = cast<ConstantSDNode>(N.getOperand("
>             "N.getOperand(0).getValueType() == MVT::Other))- 
> >getValue();\n"
> @@ -1853,7 +1853,7 @@
>
>   // Emit boilerplate.
>   OS << "SDNode *Select_INLINEASM(SDValue N) {\n"
> -     << "  std::vector<SDValue> Ops(N.Val->op_begin(), N.Val- 
> >op_end());\n"
> +     << "  std::vector<SDValue> Ops(N.getNode()->op_begin(),  
> N.getNode()->op_end());\n"
>      << "  SelectInlineAsmMemoryOperands(Ops);\n\n"
>
>      << "  // Ensure that the asm operands are themselves selected.\n"
> @@ -1865,11 +1865,11 @@
>      << "  VTs.push_back(MVT::Flag);\n"
>      << "  SDValue New = CurDAG->getNode(ISD::INLINEASM, VTs,  
> &Ops[0], "
>                  "Ops.size());\n"
> -     << "  return New.Val;\n"
> +     << "  return New.getNode();\n"
>      << "}\n\n";
>
>   OS << "SDNode *Select_UNDEF(const SDValue &N) {\n"
> -     << "  return CurDAG->SelectNodeTo(N.Val,  
> TargetInstrInfo::IMPLICIT_DEF,\n"
> +     << "  return CurDAG->SelectNodeTo(N.getNode(),  
> TargetInstrInfo::IMPLICIT_DEF,\n"
>      << "                              N.getValueType());\n"
>      << "}\n\n";
>
> @@ -1878,7 +1878,7 @@
>      << "  unsigned C = cast<LabelSDNode>(N)->getLabelID();\n"
>      << "  SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
>      << "  AddToISelQueue(Chain);\n"
> -     << "  return CurDAG->SelectNodeTo(N.Val,  
> TargetInstrInfo::DBG_LABEL,\n"
> +     << "  return CurDAG->SelectNodeTo(N.getNode(),  
> TargetInstrInfo::DBG_LABEL,\n"
>      << "                              MVT::Other, Tmp, Chain);\n"
>      << "}\n\n";
>
> @@ -1887,7 +1887,7 @@
>      << "  unsigned C = cast<LabelSDNode>(N)->getLabelID();\n"
>      << "  SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
>      << "  AddToISelQueue(Chain);\n"
> -     << "  return CurDAG->SelectNodeTo(N.Val,  
> TargetInstrInfo::EH_LABEL,\n"
> +     << "  return CurDAG->SelectNodeTo(N.getNode(),  
> TargetInstrInfo::EH_LABEL,\n"
>      << "                              MVT::Other, Tmp, Chain);\n"
>      << "}\n\n";
>
> @@ -1897,7 +1897,7 @@
>      << "  SDValue N2 = N.getOperand(2);\n"
>      << "  if (!isa<FrameIndexSDNode>(N1) || ! 
> isa<GlobalAddressSDNode>(N2)) {\n"
>      << "    cerr << \"Cannot yet select llvm.dbg.declare: \";\n"
> -     << "    N.Val->dump(CurDAG);\n"
> +     << "    N.getNode()->dump(CurDAG);\n"
>      << "    abort();\n"
>      << "  }\n"
>      << "  int FI = cast<FrameIndexSDNode>(N1)->getIndex();\n"
> @@ -1907,7 +1907,7 @@
>      << "  SDValue Tmp2 = "
>      << "CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());\n"
>      << "  AddToISelQueue(Chain);\n"
> -     << "  return CurDAG->SelectNodeTo(N.Val,  
> TargetInstrInfo::DECLARE,\n"
> +     << "  return CurDAG->SelectNodeTo(N.getNode(),  
> TargetInstrInfo::DECLARE,\n"
>      << "                              MVT::Other, Tmp1, Tmp2,  
> Chain);\n"
>      << "}\n\n";
>
> @@ -1917,7 +1917,7 @@
>      << "  unsigned C = cast<ConstantSDNode>(N1)->getValue();\n"
>      << "  SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
>      << "  AddToISelQueue(N0);\n"
> -     << "  return CurDAG->SelectNodeTo(N.Val,  
> TargetInstrInfo::EXTRACT_SUBREG,\n"
> +     << "  return CurDAG->SelectNodeTo(N.getNode(),  
> TargetInstrInfo::EXTRACT_SUBREG,\n"
>      << "                              N.getValueType(), N0, Tmp);\n"
>      << "}\n\n";
>
> @@ -1929,7 +1929,7 @@
>      << "  SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
>      << "  AddToISelQueue(N1);\n"
>      << "  AddToISelQueue(N0);\n"
> -     << "  return CurDAG->SelectNodeTo(N.Val,  
> TargetInstrInfo::INSERT_SUBREG,\n"
> +     << "  return CurDAG->SelectNodeTo(N.getNode(),  
> TargetInstrInfo::INSERT_SUBREG,\n"
>      << "                              N.getValueType(), N0, N1,  
> Tmp);\n"
>      << "}\n\n";
>
> @@ -1938,7 +1938,7 @@
>      << "  if (N.isMachineOpcode()) {\n"
>      << "    return NULL;   // Already selected.\n"
>      << "  }\n\n"
> -     << "  MVT::SimpleValueType NVT = N.Val- 
> >getValueType(0).getSimpleVT();\n"
> +     << "  MVT::SimpleValueType NVT = N.getNode()- 
> >getValueType(0).getSimpleVT();\n"
>      << "  switch (N.getOpcode()) {\n"
>      << "  default: break;\n"
>      << "  case ISD::EntryToken:       // These leaves remain the  
> same.\n"
> @@ -2033,7 +2033,7 @@
>      << "  if (N.getOpcode() != ISD::INTRINSIC_W_CHAIN &&\n"
>      << "      N.getOpcode() != ISD::INTRINSIC_WO_CHAIN &&\n"
>      << "      N.getOpcode() != ISD::INTRINSIC_VOID) {\n"
> -     << "    N.Val->dump(CurDAG);\n"
> +     << "    N.getNode()->dump(CurDAG);\n"
>      << "  } else {\n"
>      << "    unsigned iid = cast<ConstantSDNode>(N.getOperand("
>                "N.getOperand(0).getValueType() == MVT::Other))- 
> >getValue();\n"
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From evan.cheng at apple.com  Fri Aug 29 17:13:22 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 29 Aug 2008 22:13:22 -0000
Subject: [llvm-commits] [llvm] r55548 - in /llvm/trunk/lib/Target/X86:
 X86ISelLowering.cpp X86InstrInfo.cpp X86InstrInfo.h
Message-ID: <200808292213.m7TMDMqE006095@zion.cs.uiuc.edu>

Author: evancheng
Date: Fri Aug 29 17:13:21 2008
New Revision: 55548

URL: http://llvm.org/viewvc/llvm-project?rev=55548&view=rev
Log:
Backing out 55521. Not safe.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.h

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=55548&r1=55547&r2=55548&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Aug 29 17:13:21 2008
@@ -1909,6 +1909,7 @@
 }
 
 
+
 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
 /// specific condition code. It returns a false if it cannot do a direct
 /// translation. X86CC is the translated CondCode.  LHS/RHS are modified as
@@ -1935,10 +1936,7 @@
         return true;
       }
     }
-  }
 
-  bool Flip = false;
-  if (!isFP) {
     switch (SetCCOpcode) {
     default: break;
     case ISD::SETEQ:  X86CC = X86::COND_E;  break;
@@ -1959,6 +1957,7 @@
     //  0 | 0 | 1 | X < Y
     //  1 | 0 | 0 | X == Y
     //  1 | 1 | 1 | unordered
+    bool Flip = false;
     switch (SetCCOpcode) {
     default: break;
     case ISD::SETUEQ:
@@ -1980,24 +1979,11 @@
     case ISD::SETUO: X86CC = X86::COND_P;  break;
     case ISD::SETO:  X86CC = X86::COND_NP; break;
     }
-  }
-
-  if (X86CC == X86::COND_INVALID)
-    return false;
-
-  if (Flip)
-    std::swap(LHS, RHS);
-
-  if (isFP) {
-    bool LHSCanFold = ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse();
-    bool RHSCanFold = ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse();
-    if (LHSCanFold && !RHSCanFold) {
-      X86CC = X86::GetSwappedBranchCondition(static_cast<X86::CondCode>(X86CC));
+    if (Flip)
       std::swap(LHS, RHS);
-    }
   }
 
-  return true;
+  return X86CC != X86::COND_INVALID;
 }
 
 /// hasFPCMov - is there a floating point cmov for the specific X86 condition

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=55548&r1=55547&r2=55548&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Aug 29 17:13:21 2008
@@ -1433,30 +1433,6 @@
   }
 }
 
-/// GetSwappedBranchCondition - Return the branch condition that would be
-/// the result of exchanging the two operands of a comparison without
-/// changing the result produced.
-/// e.g. COND_E to COND_E, COND_G -> COND_L
-X86::CondCode X86::GetSwappedBranchCondition(X86::CondCode CC) {
-  switch (CC) {
-  default: assert(0 && "Illegal condition code!");
-  case X86::COND_E:  return X86::COND_E;
-  case X86::COND_NE: return X86::COND_NE;
-  case X86::COND_L:  return X86::COND_G;
-  case X86::COND_LE: return X86::COND_GE;
-  case X86::COND_G:  return X86::COND_L;
-  case X86::COND_GE: return X86::COND_LE;
-  case X86::COND_B:  return X86::COND_A;
-  case X86::COND_BE: return X86::COND_AE;
-  case X86::COND_A:  return X86::COND_B;
-  case X86::COND_AE: return X86::COND_BE;
-  case X86::COND_P:  return X86::COND_P;
-  case X86::COND_NP: return X86::COND_NP;
-  case X86::COND_O:  return X86::COND_O;
-  case X86::COND_NO: return X86::COND_NO;
-  }
-}
-
 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
   const TargetInstrDesc &TID = MI->getDesc();
   if (!TID.isTerminator()) return false;
@@ -2397,8 +2373,7 @@
 bool X86InstrInfo::
 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
-  X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
-  Cond[0].setImm(GetOppositeBranchCondition(CC));
+  Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm()));
   return false;
 }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=55548&r1=55547&r2=55548&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Fri Aug 29 17:13:21 2008
@@ -54,11 +54,6 @@
   /// e.g. turning COND_E to COND_NE.
   CondCode GetOppositeBranchCondition(X86::CondCode CC);
 
-  /// GetSwappedBranchCondition - Return the branch condition that would be
-  /// the result of exchanging the two operands of a comparison without
-  /// changing the result produced.
-  /// e.g. COND_E to COND_E, COND_G -> COND_L
-  CondCode GetSwappedBranchCondition(X86::CondCode CC);
 }
   
 /// X86II - This namespace holds all of the target specific flags that




From evan.cheng at apple.com  Fri Aug 29 17:19:55 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 29 Aug 2008 15:19:55 -0700
Subject: [llvm-commits] [llvm] r55504 - in /llvm/trunk:
	include/llvm/CodeGen/ include/llvm/Target/	lib/CodeGen/SelectionDAG/
	lib/Target/ARM/ lib/Target/Alpha/	lib/Target/CellSPU/
	lib/Target/IA64/ lib/Target/Mips/	lib/Target/PIC16/
	lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/
	utils/TableGen/
In-Reply-To: <E7D8C0EF-7C45-4A8B-BDE5-49A50912093E@apple.com>
References: <200808282140.m7SLeelK008466@zion.cs.uiuc.edu>
	<E7D8C0EF-7C45-4A8B-BDE5-49A50912093E@apple.com>
Message-ID: <3F8EF893-BE9C-40F7-B5DA-A2C23204F8D9@apple.com>

Actually I decided I didn't need to back out your patch after all. I  
will fix DAG combiner only. Thanks.

Evan

On Aug 29, 2008, at 3:07 PM, Evan Cheng wrote:

> Hi Gabor,
>
> I am forced to back out this patch. I think it's fine but I can't
> cleanly back out 55498 without backing this out as well. Sorry about
> it. Can you re-commit the patch after getting DAG combiner to build
> again?
>
> Thanks,
>
> Evan
>
> On Aug 28, 2008, at 2:40 PM, Gabor Greif wrote:
>
>> Author: ggreif
>> Date: Thu Aug 28 16:40:38 2008
>> New Revision: 55504
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=55504&view=rev
>> Log:
>> erect abstraction boundaries for accessing SDValue members, rename
>> Val -> Node to reflect semantics
>>
>> Modified:
>>   llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h
>>   llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>>   llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
>>   llvm/trunk/include/llvm/Target/TargetLowering.h
>>   llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
>>   llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
>>   llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
>>   llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>>   llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
>>   llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
>>   llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
>>   llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
>>   llvm/trunk/lib/Target/CellSPU/SPUOperands.td
>>   llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp
>>   llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp
>>   llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
>>   llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
>>   llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
>>   llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
>>   llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
>>   llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
>>   llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
>>   llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
>>   llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
>>   llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>>   llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>>   llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h Thu Aug 28
>> 16:40:38 2008
>> @@ -37,7 +37,7 @@
>>  else if (Chain->getNumOperands() > 0) {
>>    SDValue C0 = Chain->getOperand(0);
>>    if (C0.getValueType() == MVT::Other)
>> -      return C0.Val != Op && IsChainCompatible(C0.Val, Op);
>> +      return C0.getNode() != Op && IsChainCompatible(C0.getNode(),
>> Op);
>>  }
>>  return true;
>> }
>> @@ -76,9 +76,9 @@
>> /// AddToISelQueue - adds a node to the instruction
>> /// selection queue.
>> void AddToISelQueue(SDValue N) DISABLE_INLINE {
>> -  int Id = N.Val->getNodeId();
>> +  int Id = N.getNode()->getNodeId();
>>  if (Id != -1 && !isQueued(Id)) {
>> -    ISelQueue.push_back(N.Val);
>> +    ISelQueue.push_back(N.getNode());
>>    std::push_heap(ISelQueue.begin(), ISelQueue.end(), isel_sort());
>>    setQueued(Id);
>>  }
>> @@ -120,7 +120,7 @@
>> void ReplaceUses(SDValue F, SDValue T) DISABLE_INLINE {
>>  ISelQueueUpdater ISQU(ISelQueue);
>>  CurDAG->ReplaceAllUsesOfValueWith(F, T, &ISQU);
>> -  setSelected(F.Val->getNodeId());
>> +  setSelected(F.getNode()->getNodeId());
>>  UpdateQueue(ISQU);
>> }
>>
>> @@ -131,7 +131,7 @@
>>  ISelQueueUpdater ISQU(ISelQueue);
>>  CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num, &ISQU);
>>  for (unsigned i = 0; i != Num; ++i)
>> -    setSelected(F[i].Val->getNodeId());
>> +    setSelected(F[i].getNode()->getNodeId());
>>  UpdateQueue(ISQU);
>> }
>>
>> @@ -165,7 +165,7 @@
>>  // a reference to the root node, preventing it from being deleted,
>>  // and tracking any changes of the root.
>>  HandleSDNode Dummy(CurDAG->getRoot());
>> -  ISelQueue.push_back(CurDAG->getRoot().Val);
>> +  ISelQueue.push_back(CurDAG->getRoot().getNode());
>>
>>  // Select pending nodes from the instruction selection queue
>>  // until no more nodes are left for selection.
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Thu Aug 28
>> 16:40:38 2008
>> @@ -170,7 +170,7 @@
>>  /// setRoot - Set the current root tag of the SelectionDAG.
>>  ///
>>  const SDValue &setRoot(SDValue N) {
>> -    assert((!N.Val || N.getValueType() == MVT::Other) &&
>> +    assert((!N.getNode() || N.getValueType() == MVT::Other) &&
>>           "DAG root value is not a chain!");
>>    return Root = N;
>>  }
>> @@ -295,7 +295,7 @@
>>                         SDValue Flag) {
>>    const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
>>    SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N,
>> Flag };
>> -    return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.Val ? 4 : 3);
>> +    return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.getNode() ?
>> 4 : 3);
>>  }
>>
>>  // Similar to last getCopyToReg() except parameter Reg is a SDValue
>> @@ -303,7 +303,7 @@
>>                         SDValue Flag) {
>>    const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
>>    SDValue Ops[] = { Chain, Reg, N, Flag };
>> -    return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.Val ? 4 : 3);
>> +    return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.getNode() ?
>> 4 : 3);
>>  }
>>
>>  SDValue getCopyFromReg(SDValue Chain, unsigned Reg, MVT VT) {
>> @@ -319,7 +319,7 @@
>>                           SDValue Flag) {
>>    const MVT *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag);
>>    SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag };
>> -    return getNode(ISD::CopyFromReg, VTs, 3, Ops, Flag.Val ? 3 : 2);
>> +    return getNode(ISD::CopyFromReg, VTs, 3, Ops, Flag.getNode() ?
>> 3 : 2);
>>  }
>>
>>  SDValue getCondCode(ISD::CondCode Cond);
>> @@ -347,7 +347,7 @@
>>    Ops.push_back(Op2);
>>    Ops.push_back(InFlag);
>>    return getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0],
>> -                   (unsigned)Ops.size() - (InFlag.Val == 0 ? 1 :  
>> 0));
>> +                   (unsigned)Ops.size() - (InFlag.getNode() == 0 ?
>> 1 : 0));
>>  }
>>
>>  /// getNode - Gets or creates the specified node.
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Aug 28
>> 16:40:38 2008
>> @@ -837,29 +837,33 @@
>> /// of information is represented with the SDValue value type.
>> ///
>> class SDValue {
>> -public:
>> -  SDNode *Val;        // The node defining the value we are using.
>> -private:
>> +  SDNode *Node;       // The node defining the value we are using.
>>  unsigned ResNo;     // Which return value of the node we are using.
>> public:
>> -  SDValue() : Val(0), ResNo(0) {}
>> -  SDValue(SDNode *val, unsigned resno) : Val(val), ResNo(resno) {}
>> +  SDValue() : Node(0), ResNo(0) {}
>> +  SDValue(SDNode *node, unsigned resno) : Node(node), ResNo(resno)  
>> {}
>>
>>  /// get the index which selects a specific result in the SDNode
>>  unsigned getResNo() const { return ResNo; }
>>
>> +  /// get the SDNode which holds the desired result
>> +  SDNode *getNode() const { return Node; }
>> +
>> +  /// set the SDNode
>> +  void setNode(SDNode *N) { Node = N; }
>> +
>>  bool operator==(const SDValue &O) const {
>> -    return Val == O.Val && ResNo == O.ResNo;
>> +    return Node == O.Node && ResNo == O.ResNo;
>>  }
>>  bool operator!=(const SDValue &O) const {
>>    return !operator==(O);
>>  }
>>  bool operator<(const SDValue &O) const {
>> -    return Val < O.Val || (Val == O.Val && ResNo < O.ResNo);
>> +    return Node < O.Node || (Node == O.Node && ResNo < O.ResNo);
>>  }
>>
>>  SDValue getValue(unsigned R) const {
>> -    return SDValue(Val, R);
>> +    return SDValue(Node, R);
>>  }
>>
>>  // isOperandOf - Return true if this node is an operand of N.
>> @@ -894,12 +898,12 @@
>>                                      unsigned Depth = 2) const;
>>
>>  /// use_empty - Return true if there are no nodes using value ResNo
>> -  /// of node Val.
>> +  /// of Node.
>>  ///
>>  inline bool use_empty() const;
>>
>>  /// hasOneUse - Return true if there is exactly one node using value
>> -  /// ResNo of node Val.
>> +  /// ResNo of Node.
>>  ///
>>  inline bool hasOneUse() const;
>> };
>> @@ -913,8 +917,8 @@
>>    return SDValue((SDNode*)-1, 0);
>>  }
>>  static unsigned getHashValue(const SDValue &Val) {
>> -    return ((unsigned)((uintptr_t)Val.Val >> 4) ^
>> -            (unsigned)((uintptr_t)Val.Val >> 9)) + Val.getResNo();
>> +    return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
>> +            (unsigned)((uintptr_t)Val.getNode() >> 9)) +
>> Val.getResNo();
>>  }
>>  static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
>>    return LHS == RHS;
>> @@ -927,13 +931,13 @@
>> template<> struct simplify_type<SDValue> {
>>  typedef SDNode* SimpleType;
>>  static SimpleType getSimplifiedValue(const SDValue &Val) {
>> -    return static_cast<SimpleType>(Val.Val);
>> +    return static_cast<SimpleType>(Val.getNode());
>>  }
>> };
>> template<> struct simplify_type<const SDValue> {
>>  typedef SDNode* SimpleType;
>>  static SimpleType getSimplifiedValue(const SDValue &Val) {
>> -    return static_cast<SimpleType>(Val.Val);
>> +    return static_cast<SimpleType>(Val.getNode());
>>  }
>> };
>>
>> @@ -977,8 +981,9 @@
>>
>>  const SDValue& getSDValue() const { return Operand; }
>>
>> -  SDNode *&getVal() { return Operand.Val; }
>> -  SDNode *const &getVal() const { return Operand.Val; }
>> +  SDValue &getSDValue() { return Operand; }
>> +  SDNode *getVal() { return Operand.getNode(); }
>> +  SDNode *getVal() const { return Operand.getNode(); } // FIXME:
>> const correct?
>>
>>  bool operator==(const SDValue &O) const {
>>    return Operand == O;
>> @@ -1323,7 +1328,7 @@
>>    for (unsigned i = 0; i != NumOps; ++i) {
>>      OperandList[i] = Ops[i];
>>      OperandList[i].setUser(this);
>> -      Ops[i].Val->addUse(OperandList[i]);
>> +      Ops[i].getNode()->addUse(OperandList[i]);
>>    }
>>
>>    ValueList = VTs.VTs;
>> @@ -1393,34 +1398,34 @@
>> // Define inline functions from the SDValue class.
>>
>> inline unsigned SDValue::getOpcode() const {
>> -  return Val->getOpcode();
>> +  return Node->getOpcode();
>> }
>> inline MVT SDValue::getValueType() const {
>> -  return Val->getValueType(ResNo);
>> +  return Node->getValueType(ResNo);
>> }
>> inline unsigned SDValue::getNumOperands() const {
>> -  return Val->getNumOperands();
>> +  return Node->getNumOperands();
>> }
>> inline const SDValue &SDValue::getOperand(unsigned i) const {
>> -  return Val->getOperand(i);
>> +  return Node->getOperand(i);
>> }
>> inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
>> -  return Val->getConstantOperandVal(i);
>> +  return Node->getConstantOperandVal(i);
>> }
>> inline bool SDValue::isTargetOpcode() const {
>> -  return Val->isTargetOpcode();
>> +  return Node->isTargetOpcode();
>> }
>> inline bool SDValue::isMachineOpcode() const {
>> -  return Val->isMachineOpcode();
>> +  return Node->isMachineOpcode();
>> }
>> inline unsigned SDValue::getMachineOpcode() const {
>> -  return Val->getMachineOpcode();
>> +  return Node->getMachineOpcode();
>> }
>> inline bool SDValue::use_empty() const {
>> -  return !Val->hasAnyUseOfValue(ResNo);
>> +  return !Node->hasAnyUseOfValue(ResNo);
>> }
>> inline bool SDValue::hasOneUse() const {
>> -  return Val->hasNUsesOfValue(1, ResNo);
>> +  return Node->hasNUsesOfValue(1, ResNo);
>> }
>>
>> /// UnarySDNode - This class is used for single-operand SDNodes.
>> This is solely
>> @@ -2321,7 +2326,7 @@
>>  }
>>
>>  pointer operator*() const {
>> -    return Node->getOperand(Operand).Val;
>> +    return Node->getOperand(Operand).getNode();
>>  }
>>  pointer operator->() const { return operator*(); }
>>
>>
>> Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
>> +++ llvm/trunk/include/llvm/Target/TargetLowering.h Thu Aug 28
>> 16:40:38 2008
>> @@ -1086,11 +1086,11 @@
>>  static bool CheckTailCallReturnConstraints(SDValue Call, SDValue
>> Ret) {
>>    unsigned NumOps = Ret.getNumOperands();
>>    if ((NumOps == 1 &&
>> -       (Ret.getOperand(0) == SDValue(Call.Val,1) ||
>> -        Ret.getOperand(0) == SDValue(Call.Val,0))) ||
>> +       (Ret.getOperand(0) == SDValue(Call.getNode(),1) ||
>> +        Ret.getOperand(0) == SDValue(Call.getNode(),0))) ||
>>      (NumOps > 1 &&
>> -       Ret.getOperand(0) == SDValue(Call.Val,Call.Val-
>>> getNumValues()-1) &&
>> -       Ret.getOperand(1) == SDValue(Call.Val,0)))
>> +       Ret.getOperand(0) == SDValue(Call.getNode(),Call.getNode()-
>>> getNumValues()-1) &&
>> +       Ret.getOperand(1) == SDValue(Call.getNode(),0)))
>>      return true;
>>    return false;
>>  }
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -148,8 +148,8 @@
>>    // Visitation implementation - Implement dag node combining for
>> different
>>    // node types.  The semantics are as follows:
>>    // Return Value:
>> -    //   SDValue.Val == 0   - No change was made
>> -    //   SDValue.Val == N   - N was replaced, is dead, and is
>> already handled.
>> +    //   SDValue.getNode() == 0   - No change was made
>> +    //   SDValue.getNode() == N   - N was replaced, is dead, and is
>> already handled.
>>    //   otherwise            - N should be replaced by the returned
>> Operand.
>>    //
>>    SDValue visitTokenFactor(SDNode *N);
>> @@ -491,7 +491,7 @@
>> // free when it is profitable to do so.
>> static bool isOneUseSetCC(SDValue N) {
>>  SDValue N0, N1, N2;
>> -  if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
>> +  if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
>>    return true;
>>  return false;
>> }
>> @@ -503,11 +503,11 @@
>>  if (N0.getOpcode() == Opc &&
>> isa<ConstantSDNode>(N0.getOperand(1))) {
>>    if (isa<ConstantSDNode>(N1)) {
>>      SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
>> -      AddToWorkList(OpNode.Val);
>> +      AddToWorkList(OpNode.getNode());
>>      return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
>>    } else if (N0.hasOneUse()) {
>>      SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
>> -      AddToWorkList(OpNode.Val);
>> +      AddToWorkList(OpNode.getNode());
>>      return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
>>    }
>>  }
>> @@ -516,11 +516,11 @@
>>  if (N1.getOpcode() == Opc &&
>> isa<ConstantSDNode>(N1.getOperand(1))) {
>>    if (isa<ConstantSDNode>(N0)) {
>>      SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
>> -      AddToWorkList(OpNode.Val);
>> +      AddToWorkList(OpNode.getNode());
>>      return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
>>    } else if (N1.hasOneUse()) {
>>      SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
>> -      AddToWorkList(OpNode.Val);
>> +      AddToWorkList(OpNode.getNode());
>>      return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
>>    }
>>  }
>> @@ -532,7 +532,7 @@
>>  assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
>>  ++NodesCombined;
>>  DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
>> -  DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
>> +  DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG));
>>  DOUT << " and " << NumTo-1 << " other values\n";
>>  WorkListRemover DeadNodes(*this);
>>  DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
>> @@ -540,8 +540,8 @@
>>  if (AddTo) {
>>    // Push the new nodes and any users onto the worklist
>>    for (unsigned i = 0, e = NumTo; i != e; ++i) {
>> -      AddToWorkList(To[i].Val);
>> -      AddUsersToWorkList(To[i].Val);
>> +      AddToWorkList(To[i].getNode());
>> +      AddUsersToWorkList(To[i].getNode());
>>    }
>>  }
>>
>> @@ -564,12 +564,12 @@
>>    return false;
>>
>>  // Revisit the node.
>> -  AddToWorkList(Op.Val);
>> +  AddToWorkList(Op.getNode());
>>
>>  // Replace the old value with the new one.
>>  ++NodesCombined;
>> -  DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
>> -  DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
>> +  DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG));
>> +  DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
>>  DOUT << '\n';
>>
>>  // Replace all uses.  If any nodes become isomorphic to other
>> nodes and
>> @@ -578,22 +578,22 @@
>>  DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
>>
>>  // Push the new node and any (possibly new) users onto the worklist.
>> -  AddToWorkList(TLO.New.Val);
>> -  AddUsersToWorkList(TLO.New.Val);
>> +  AddToWorkList(TLO.New.getNode());
>> +  AddUsersToWorkList(TLO.New.getNode());
>>
>>  // Finally, if the node is now dead, remove it from the graph.
>> The node
>>  // may not be dead if the replacement process recursively
>> simplified to
>>  // something else needing this node.
>> -  if (TLO.Old.Val->use_empty()) {
>> -    removeFromWorkList(TLO.Old.Val);
>> +  if (TLO.Old.getNode()->use_empty()) {
>> +    removeFromWorkList(TLO.Old.getNode());
>>
>>    // If the operands of this node are only used by the node, they
>> will now
>>    // be dead.  Make sure to visit them first to delete dead nodes
>> early.
>> -    for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e;
>> ++i)
>> -      if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
>> -        AddToWorkList(TLO.Old.Val->getOperand(i).Val);
>> +    for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
>> i != e; ++i)
>> +      if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
>> +        AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
>>
>> -    DAG.DeleteNode(TLO.Old.Val);
>> +    DAG.DeleteNode(TLO.Old.getNode());
>>  }
>>  return true;
>> }
>> @@ -608,7 +608,7 @@
>>  // reduced number of uses, allowing other xforms.
>>  if (N->use_empty() && N != &Dummy) {
>>    for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
>> -      AddToWorkList(N->getOperand(i).Val);
>> +      AddToWorkList(N->getOperand(i).getNode());
>>
>>    DAG.DeleteNode(N);
>>    return;
>> @@ -616,7 +616,7 @@
>>
>>  SDValue RV = combine(N);
>>
>> -  if (RV.Val == 0)
>> +  if (RV.getNode() == 0)
>>    return;
>>
>>  ++NodesCombined;
>> @@ -625,19 +625,19 @@
>>  // zero, we know that the node must have defined multiple values and
>>  // CombineTo was used.  Since CombineTo takes care of the worklist
>>  // mechanics for us, we have no work to do in this case.
>> -  if (RV.Val == N)
>> +  if (RV.getNode() == N)
>>    return;
>>
>>  assert(N->getOpcode() != ISD::DELETED_NODE &&
>> -         RV.Val->getOpcode() != ISD::DELETED_NODE &&
>> +         RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
>>         "Node was deleted but visit returned new node!");
>>
>>  DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
>> -  DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
>> +  DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG));
>>  DOUT << '\n';
>>
>> -  if (N->getNumValues() == RV.Val->getNumValues())
>> -    DAG.ReplaceAllUsesWith(N, RV.Val);
>> +  if (N->getNumValues() == RV.getNode()->getNumValues())
>> +    DAG.ReplaceAllUsesWith(N, RV.getNode());
>>  else {
>>    assert(N->getValueType(0) == RV.getValueType() &&
>>           N->getNumValues() == 1 && "Type mismatch");
>> @@ -650,8 +650,8 @@
>>  DAG.DeleteNode(N);
>>
>>  // Push the new node and any users onto the worklist
>> -  AddToWorkList(RV.Val);
>> -  AddUsersToWorkList(RV.Val);
>> +  AddToWorkList(RV.getNode());
>> +  AddUsersToWorkList(RV.getNode());
>> }
>>
>> void DAGCombiner::Run(bool RunningAfterLegalize) {
>> @@ -761,7 +761,7 @@
>>  SDValue RV = visit(N);
>>
>>  // If nothing happened, try a target-specific DAG combine.
>> -  if (RV.Val == 0) {
>> +  if (RV.getNode() == 0) {
>>    assert(N->getOpcode() != ISD::DELETED_NODE &&
>>           "Node was deleted but visit returned NULL!");
>>
>> @@ -778,7 +778,7 @@
>>
>>  // If N is a commutative binary node, try commuting it to enable
>> more
>>  // sdisel CSE.
>> -  if (RV.Val == 0 &&
>> +  if (RV.getNode() == 0 &&
>>      SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
>>      N->getNumValues() == 1) {
>>    SDValue N0 = N->getOperand(0);
>> @@ -815,9 +815,9 @@
>>  // If N has two operands, where one has an input chain equal to
>> the other,
>>  // the 'other' chain is redundant.
>>  if (N->getNumOperands() == 2) {
>> -    if (getInputChainForNode(N->getOperand(0).Val) == N-
>>> getOperand(1))
>> +    if (getInputChainForNode(N->getOperand(0).getNode()) == N-
>>> getOperand(1))
>>      return N->getOperand(0);
>> -    if (getInputChainForNode(N->getOperand(1).Val) == N-
>>> getOperand(0))
>> +    if (getInputChainForNode(N->getOperand(1).getNode()) == N-
>>> getOperand(0))
>>      return N->getOperand(1);
>>  }
>>
>> @@ -847,11 +847,11 @@
>>
>>      case ISD::TokenFactor:
>>        if ((CombinerAA || Op.hasOneUse()) &&
>> -            std::find(TFs.begin(), TFs.end(), Op.Val) ==  
>> TFs.end()) {
>> +            std::find(TFs.begin(), TFs.end(), Op.getNode()) ==
>> TFs.end()) {
>>          // Queue up for processing.
>> -          TFs.push_back(Op.Val);
>> +          TFs.push_back(Op.getNode());
>>          // Clean up in case the token factor is removed.
>> -          AddToWorkList(Op.Val);
>> +          AddToWorkList(Op.getNode());
>>          Changed = true;
>>          break;
>>        }
>> @@ -859,7 +859,7 @@
>>
>>      default:
>>        // Only add if it isn't already in the list.
>> -        if (SeenOps.insert(Op.Val))
>> +        if (SeenOps.insert(Op.getNode()))
>>          Ops.push_back(Op);
>>        else
>>          Changed = true;
>> @@ -905,7 +905,7 @@
>>  SDValue N00 = N0.getOperand(0);
>>  SDValue N01 = N0.getOperand(1);
>>  ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
>> -  if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
>> +  if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()-
>>> hasOneUse() &&
>>      isa<ConstantSDNode>(N00.getOperand(1))) {
>>    N0 = DAG.getNode(ISD::ADD, VT,
>>                     DAG.getNode(ISD::SHL, VT, N00.getOperand(0),
>> N01),
>> @@ -975,7 +975,7 @@
>>  // fold vector ops
>>  if (VT.isVector()) {
>>    SDValue FoldedVOp = SimplifyVBinOp(N);
>> -    if (FoldedVOp.Val) return FoldedVOp;
>> +    if (FoldedVOp.getNode()) return FoldedVOp;
>>  }
>>
>>  // fold (add x, undef) -> undef
>> @@ -1001,7 +1001,7 @@
>>                         N0.getOperand(1));
>>  // reassociate add
>>  SDValue RADD = ReassociateOps(ISD::ADD, N0, N1);
>> -  if (RADD.Val != 0)
>> +  if (RADD.getNode() != 0)
>>    return RADD;
>>  // fold ((0-A) + B) -> B-A
>>  if (N0.getOpcode() == ISD::SUB &&
>> isa<ConstantSDNode>(N0.getOperand(0)) &&
>> @@ -1036,23 +1036,23 @@
>>  }
>>
>>  // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2),
>> c1<<c2), )
>> -  if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
>> +  if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
>>    SDValue Result = combineShlAddConstant(N0, N1, DAG);
>> -    if (Result.Val) return Result;
>> +    if (Result.getNode()) return Result;
>>  }
>> -  if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
>> +  if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
>>    SDValue Result = combineShlAddConstant(N1, N0, DAG);
>> -    if (Result.Val) return Result;
>> +    if (Result.getNode()) return Result;
>>  }
>>
>>  // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
>> -  if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
>> +  if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
>>    SDValue Result = combineSelectAndUse(N, N0, N1, DAG);
>> -    if (Result.Val) return Result;
>> +    if (Result.getNode()) return Result;
>>  }
>> -  if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
>> +  if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
>>    SDValue Result = combineSelectAndUse(N, N1, N0, DAG);
>> -    if (Result.Val) return Result;
>> +    if (Result.getNode()) return Result;
>>  }
>>
>>  return SDValue();
>> @@ -1121,14 +1121,14 @@
>> SDValue DAGCombiner::visitSUB(SDNode *N) {
>>  SDValue N0 = N->getOperand(0);
>>  SDValue N1 = N->getOperand(1);
>> -  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
>> -  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
>> +  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
>> +  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
>>  MVT VT = N0.getValueType();
>>
>>  // fold vector ops
>>  if (VT.isVector()) {
>>    SDValue FoldedVOp = SimplifyVBinOp(N);
>> -    if (FoldedVOp.Val) return FoldedVOp;
>> +    if (FoldedVOp.getNode()) return FoldedVOp;
>>  }
>>
>>  // fold (sub x, x) -> 0
>> @@ -1148,9 +1148,9 @@
>>  if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
>>    return N0.getOperand(0);
>>  // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
>> -  if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
>> +  if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
>>    SDValue Result = combineSelectAndUse(N, N1, N0, DAG);
>> -    if (Result.Val) return Result;
>> +    if (Result.getNode()) return Result;
>>  }
>>  // If either operand of a sub is undef, the result is undef
>>  if (N0.getOpcode() == ISD::UNDEF)
>> @@ -1171,7 +1171,7 @@
>>  // fold vector ops
>>  if (VT.isVector()) {
>>    SDValue FoldedVOp = SimplifyVBinOp(N);
>> -    if (FoldedVOp.Val) return FoldedVOp;
>> +    if (FoldedVOp.getNode()) return FoldedVOp;
>>  }
>>
>>  // fold (mul x, undef) -> 0
>> @@ -1208,7 +1208,7 @@
>>  if (N1C && N0.getOpcode() == ISD::SHL &&
>>      isa<ConstantSDNode>(N0.getOperand(1))) {
>>    SDValue C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
>> -    AddToWorkList(C3.Val);
>> +    AddToWorkList(C3.getNode());
>>    return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
>>  }
>>
>> @@ -1218,19 +1218,19 @@
>>    SDValue Sh(0,0), Y(0,0);
>>    // Check for both (mul (shl X, C), Y)  and  (mul Y, (shl X, C)).
>>    if (N0.getOpcode() == ISD::SHL &&
>> isa<ConstantSDNode>(N0.getOperand(1)) &&
>> -        N0.Val->hasOneUse()) {
>> +        N0.getNode()->hasOneUse()) {
>>      Sh = N0; Y = N1;
>>    } else if (N1.getOpcode() == ISD::SHL &&
>> -               isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val-
>>> hasOneUse()) {
>> +               isa<ConstantSDNode>(N1.getOperand(1)) &&
>> N1.getNode()->hasOneUse()) {
>>      Sh = N1; Y = N0;
>>    }
>> -    if (Sh.Val) {
>> +    if (Sh.getNode()) {
>>      SDValue Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
>>      return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
>>    }
>>  }
>>  // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
>> -  if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
>> +  if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()-
>>> hasOneUse() &&
>>      isa<ConstantSDNode>(N0.getOperand(1))) {
>>    return DAG.getNode(ISD::ADD, VT,
>>                       DAG.getNode(ISD::MUL, VT, N0.getOperand(0),
>> N1),
>> @@ -1239,7 +1239,7 @@
>>
>>  // reassociate mul
>>  SDValue RMUL = ReassociateOps(ISD::MUL, N0, N1);
>> -  if (RMUL.Val != 0)
>> +  if (RMUL.getNode() != 0)
>>    return RMUL;
>>
>>  return SDValue();
>> @@ -1248,14 +1248,14 @@
>> SDValue DAGCombiner::visitSDIV(SDNode *N) {
>>  SDValue N0 = N->getOperand(0);
>>  SDValue N1 = N->getOperand(1);
>> -  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
>> -  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
>> +  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
>> +  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
>>  MVT VT = N->getValueType(0);
>>
>>  // fold vector ops
>>  if (VT.isVector()) {
>>    SDValue FoldedVOp = SimplifyVBinOp(N);
>> -    if (FoldedVOp.Val) return FoldedVOp;
>> +    if (FoldedVOp.getNode()) return FoldedVOp;
>>  }
>>
>>  // fold (sdiv c1, c2) -> c1/c2
>> @@ -1288,21 +1288,21 @@
>>    SDValue SGN = DAG.getNode(ISD::SRA, VT, N0,
>>                                DAG.getConstant(VT.getSizeInBits()-1,
>>
>> TLI.getShiftAmountTy()));
>> -    AddToWorkList(SGN.Val);
>> +    AddToWorkList(SGN.getNode());
>>    // Add (N0 < 0) ? abs2 - 1 : 0;
>>    SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN,
>>                                DAG.getConstant(VT.getSizeInBits()-
>> lg2,
>>
>> TLI.getShiftAmountTy()));
>>    SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
>> -    AddToWorkList(SRL.Val);
>> -    AddToWorkList(ADD.Val);    // Divide by pow2
>> +    AddToWorkList(SRL.getNode());
>> +    AddToWorkList(ADD.getNode());    // Divide by pow2
>>    SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD,
>>                                DAG.getConstant(lg2,
>> TLI.getShiftAmountTy()));
>>    // If we're dividing by a positive value, we're done.
>> Otherwise, we must
>>    // negate the result.
>>    if (pow2 > 0)
>>      return SRA;
>> -    AddToWorkList(SRA.Val);
>> +    AddToWorkList(SRA.getNode());
>>    return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
>>  }
>>  // if integer divide is expensive and we satisfy the requirements,
>> emit an
>> @@ -1310,7 +1310,7 @@
>>  if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended()
>>> 1) &&
>>      !TLI.isIntDivCheap()) {
>>    SDValue Op = BuildSDIV(N);
>> -    if (Op.Val) return Op;
>> +    if (Op.getNode()) return Op;
>>  }
>>
>>  // undef / X -> 0
>> @@ -1326,14 +1326,14 @@
>> SDValue DAGCombiner::visitUDIV(SDNode *N) {
>>  SDValue N0 = N->getOperand(0);
>>  SDValue N1 = N->getOperand(1);
>> -  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
>> -  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
>> +  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
>> +  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
>>  MVT VT = N->getValueType(0);
>>
>>  // fold vector ops
>>  if (VT.isVector()) {
>>    SDValue FoldedVOp = SimplifyVBinOp(N);
>> -    if (FoldedVOp.Val) return FoldedVOp;
>> +    if (FoldedVOp.getNode()) return FoldedVOp;
>>  }
>>
>>  // fold (udiv c1, c2) -> c1/c2
>> @@ -1353,7 +1353,7 @@
>>                                    DAG.getConstant(SHC-
>>> getAPIntValue()
>>                                                                    .logBase2
>> (),
>>                                                    ADDVT));
>> -        AddToWorkList(Add.Val);
>> +        AddToWorkList(Add.getNode());
>>        return DAG.getNode(ISD::SRL, VT, N0, Add);
>>      }
>>    }
>> @@ -1361,7 +1361,7 @@
>>  // fold (udiv x, c) -> alternate
>>  if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
>>    SDValue Op = BuildUDIV(N);
>> -    if (Op.Val) return Op;
>> +    if (Op.getNode()) return Op;
>>  }
>>
>>  // undef / X -> 0
>> @@ -1395,12 +1395,12 @@
>>  // X%C to the equivalent of X-X/C*C.
>>  if (N1C && !N1C->isNullValue()) {
>>    SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
>> -    AddToWorkList(Div.Val);
>> -    SDValue OptimizedDiv = combine(Div.Val);
>> -    if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
>> +    AddToWorkList(Div.getNode());
>> +    SDValue OptimizedDiv = combine(Div.getNode());
>> +    if (OptimizedDiv.getNode() && OptimizedDiv.getNode() !=
>> Div.getNode()) {
>>      SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
>>      SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
>> -      AddToWorkList(Mul.Val);
>> +      AddToWorkList(Mul.getNode());
>>      return Sub;
>>    }
>>  }
>> @@ -1437,7 +1437,7 @@
>>          DAG.getNode(ISD::ADD, VT, N1,
>>
>> DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
>>                                 VT));
>> -        AddToWorkList(Add.Val);
>> +        AddToWorkList(Add.getNode());
>>        return DAG.getNode(ISD::AND, VT, N0, Add);
>>      }
>>    }
>> @@ -1447,11 +1447,11 @@
>>  // X%C to the equivalent of X-X/C*C.
>>  if (N1C && !N1C->isNullValue()) {
>>    SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
>> -    SDValue OptimizedDiv = combine(Div.Val);
>> -    if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
>> +    SDValue OptimizedDiv = combine(Div.getNode());
>> +    if (OptimizedDiv.getNode() && OptimizedDiv.getNode() !=
>> Div.getNode()) {
>>      SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
>>      SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
>> -      AddToWorkList(Mul.Val);
>> +      AddToWorkList(Mul.getNode());
>>      return Sub;
>>    }
>>  }
>> @@ -1540,9 +1540,9 @@
>>  if (LoExists) {
>>    SDValue Lo = DAG.getNode(LoOp, N->getValueType(0),
>>                               N->op_begin(), N->getNumOperands());
>> -    AddToWorkList(Lo.Val);
>> -    SDValue LoOpt = combine(Lo.Val);
>> -    if (LoOpt.Val && LoOpt.Val != Lo.Val &&
>> +    AddToWorkList(Lo.getNode());
>> +    SDValue LoOpt = combine(Lo.getNode());
>> +    if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
>>        (!AfterLegalize ||
>>         TLI.isOperationLegal(LoOpt.getOpcode(),
>> LoOpt.getValueType())))
>>      return CombineTo(N, LoOpt, LoOpt);
>> @@ -1551,9 +1551,9 @@
>>  if (HiExists) {
>>    SDValue Hi = DAG.getNode(HiOp, N->getValueType(1),
>>                               N->op_begin(), N->getNumOperands());
>> -    AddToWorkList(Hi.Val);
>> -    SDValue HiOpt = combine(Hi.Val);
>> -    if (HiOpt.Val && HiOpt != Hi &&
>> +    AddToWorkList(Hi.getNode());
>> +    SDValue HiOpt = combine(Hi.getNode());
>> +    if (HiOpt.getNode() && HiOpt != Hi &&
>>        (!AfterLegalize ||
>>         TLI.isOperationLegal(HiOpt.getOpcode(),
>> HiOpt.getValueType())))
>>      return CombineTo(N, HiOpt, HiOpt);
>> @@ -1563,28 +1563,28 @@
>>
>> SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
>>  SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
>> -  if (Res.Val) return Res;
>> +  if (Res.getNode()) return Res;
>>
>>  return SDValue();
>> }
>>
>> SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
>>  SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
>> -  if (Res.Val) return Res;
>> +  if (Res.getNode()) return Res;
>>
>>  return SDValue();
>> }
>>
>> SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
>>  SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
>> -  if (Res.Val) return Res;
>> +  if (Res.getNode()) return Res;
>>
>>  return SDValue();
>> }
>>
>> SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
>>  SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
>> -  if (Res.Val) return Res;
>> +  if (Res.getNode()) return Res;
>>
>>  return SDValue();
>> }
>> @@ -1607,7 +1607,7 @@
>>    SDValue ORNode = DAG.getNode(N->getOpcode(),
>>                                   N0.getOperand(0).getValueType(),
>>                                   N0.getOperand(0),
>> N1.getOperand(0));
>> -    AddToWorkList(ORNode.Val);
>> +    AddToWorkList(ORNode.getNode());
>>    return DAG.getNode(N0.getOpcode(), VT, ORNode);
>>  }
>>
>> @@ -1621,7 +1621,7 @@
>>    SDValue ORNode = DAG.getNode(N->getOpcode(),
>>                                   N0.getOperand(0).getValueType(),
>>                                   N0.getOperand(0),
>> N1.getOperand(0));
>> -    AddToWorkList(ORNode.Val);
>> +    AddToWorkList(ORNode.getNode());
>>    return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
>>  }
>>
>> @@ -1640,7 +1640,7 @@
>>  // fold vector ops
>>  if (VT.isVector()) {
>>    SDValue FoldedVOp = SimplifyVBinOp(N);
>> -    if (FoldedVOp.Val) return FoldedVOp;
>> +    if (FoldedVOp.getNode()) return FoldedVOp;
>>  }
>>
>>  // fold (and x, undef) -> 0
>> @@ -1661,7 +1661,7 @@
>>    return DAG.getConstant(0, VT);
>>  // reassociate and
>>  SDValue RAND = ReassociateOps(ISD::AND, N0, N1);
>> -  if (RAND.Val != 0)
>> +  if (RAND.getNode() != 0)
>>    return RAND;
>>  // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
>>  if (N1C && N0.getOpcode() == ISD::OR)
>> @@ -1683,7 +1683,7 @@
>>      // We actually want to replace all uses of the any_extend with
>> the
>>      // zero_extend, to avoid duplicating things.  This will later
>> cause this
>>      // AND to be folded.
>> -      CombineTo(N0.Val, Zext);
>> +      CombineTo(N0.getNode(), Zext);
>>      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
>>    }
>>  }
>> @@ -1697,19 +1697,19 @@
>>      // fold (X == 0) & (Y == 0) -> (X|Y == 0)
>>      if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 ==
>> ISD::SETEQ) {
>>        SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL,
>> RL);
>> -        AddToWorkList(ORNode.Val);
>> +        AddToWorkList(ORNode.getNode());
>>        return DAG.getSetCC(VT, ORNode, LR, Op1);
>>      }
>>      // fold (X == -1) & (Y == -1) -> (X&Y == -1)
>>      if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 ==
>> ISD::SETEQ) {
>>        SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(),
>> LL, RL);
>> -        AddToWorkList(ANDNode.Val);
>> +        AddToWorkList(ANDNode.getNode());
>>        return DAG.getSetCC(VT, ANDNode, LR, Op1);
>>      }
>>      // fold (X >  -1) & (Y >  -1) -> (X|Y > -1)
>>      if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 ==
>> ISD::SETGT) {
>>        SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL,
>> RL);
>> -        AddToWorkList(ORNode.Val);
>> +        AddToWorkList(ORNode.getNode());
>>        return DAG.getSetCC(VT, ORNode, LR, Op1);
>>      }
>>    }
>> @@ -1729,7 +1729,7 @@
>>  // Simplify: and (op x...), (op y...)  -> (op (and x, y))
>>  if (N0.getOpcode() == N1.getOpcode()) {
>>    SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
>> -    if (Tmp.Val) return Tmp;
>> +    if (Tmp.getNode()) return Tmp;
>>  }
>>
>>  // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
>> @@ -1738,7 +1738,7 @@
>>      SimplifyDemandedBits(SDValue(N, 0)))
>>    return SDValue(N, 0);
>>  // fold (zext_inreg (extload x)) -> (zextload x)
>> -  if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
>> +  if (ISD::isEXTLoad(N0.getNode()) &&
>> ISD::isUNINDEXEDLoad(N0.getNode())) {
>>    LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>>    MVT EVT = LN0->getMemoryVT();
>>    // If we zero all the possible extended bits, then we can turn
>> this into
>> @@ -1754,12 +1754,12 @@
>>                                         LN0->isVolatile(),
>>                                         LN0->getAlignment());
>>      AddToWorkList(N);
>> -      CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
>> +      CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
>>      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
>>    }
>>  }
>>  // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one
>> use
>> -  if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
>> +  if (ISD::isSEXTLoad(N0.getNode()) &&
>> ISD::isUNINDEXEDLoad(N0.getNode()) &&
>>      N0.hasOneUse()) {
>>    LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>>    MVT EVT = LN0->getMemoryVT();
>> @@ -1776,7 +1776,7 @@
>>                                         LN0->isVolatile(),
>>                                         LN0->getAlignment());
>>      AddToWorkList(N);
>> -      CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
>> +      CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
>>      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
>>    }
>>  }
>> @@ -1813,13 +1813,13 @@
>>                               DAG.getConstant(PtrOff, PtrType));
>>          Alignment = MinAlign(Alignment, PtrOff);
>>        }
>> -        AddToWorkList(NewPtr.Val);
>> +        AddToWorkList(NewPtr.getNode());
>>        SDValue Load =
>>          DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
>>                         LN0->getSrcValue(), LN0-
>>> getSrcValueOffset(), EVT,
>>                         LN0->isVolatile(), Alignment);
>>        AddToWorkList(N);
>> -        CombineTo(N0.Val, Load, Load.getValue(1));
>> +        CombineTo(N0.getNode(), Load, Load.getValue(1));
>>        return SDValue(N, 0);   // Return N so it doesn't get
>> rechecked!
>>      }
>>    }
>> @@ -1839,7 +1839,7 @@
>>  // fold vector ops
>>  if (VT.isVector()) {
>>    SDValue FoldedVOp = SimplifyVBinOp(N);
>> -    if (FoldedVOp.Val) return FoldedVOp;
>> +    if (FoldedVOp.getNode()) return FoldedVOp;
>>  }
>>
>>  // fold (or x, undef) -> -1
>> @@ -1862,10 +1862,10 @@
>>    return N1;
>>  // reassociate or
>>  SDValue ROR = ReassociateOps(ISD::OR, N0, N1);
>> -  if (ROR.Val != 0)
>> +  if (ROR.getNode() != 0)
>>    return ROR;
>>  // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
>> -  if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
>> +  if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()-
>>> hasOneUse() &&
>>             isa<ConstantSDNode>(N0.getOperand(1))) {
>>    ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
>>    return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT,
>> N0.getOperand(0),
>> @@ -1885,7 +1885,7 @@
>>      if (cast<ConstantSDNode>(LR)->isNullValue() &&
>>          (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
>>        SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL,
>> RL);
>> -        AddToWorkList(ORNode.Val);
>> +        AddToWorkList(ORNode.getNode());
>>        return DAG.getSetCC(VT, ORNode, LR, Op1);
>>      }
>>      // fold (X != -1) | (Y != -1) -> (X&Y != -1)
>> @@ -1893,7 +1893,7 @@
>>      if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
>>          (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
>>        SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(),
>> LL, RL);
>> -        AddToWorkList(ANDNode.Val);
>> +        AddToWorkList(ANDNode.getNode());
>>        return DAG.getSetCC(VT, ANDNode, LR, Op1);
>>      }
>>    }
>> @@ -1913,7 +1913,7 @@
>>  // Simplify: or (op x...), (op y...)  -> (op (or x, y))
>>  if (N0.getOpcode() == N1.getOpcode()) {
>>    SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
>> -    if (Tmp.Val) return Tmp;
>> +    if (Tmp.getNode()) return Tmp;
>>  }
>>
>>  // (X & C1) | (Y & C2)  -> (X|Y) & C3  if possible.
>> @@ -1922,7 +1922,7 @@
>>      N0.getOperand(1).getOpcode() == ISD::Constant &&
>>      N1.getOperand(1).getOpcode() == ISD::Constant &&
>>      // Don't increase # computations.
>> -      (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
>> +      (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
>>    // We can only do this xform if we know that bits from X that
>> are set in C2
>>    // but not in C1 are already zero.  Likewise for Y.
>>    const APInt &LHSMask =
>> @@ -2023,14 +2023,14 @@
>>      Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
>>
>>    // If there is an AND of either shifted operand, apply it to the
>> result.
>> -    if (LHSMask.Val || RHSMask.Val) {
>> +    if (LHSMask.getNode() || RHSMask.getNode()) {
>>      APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
>>
>> -      if (LHSMask.Val) {
>> +      if (LHSMask.getNode()) {
>>        APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
>>        Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() |
>> RHSBits;
>>      }
>> -      if (RHSMask.Val) {
>> +      if (RHSMask.getNode()) {
>>        APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
>>        Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() |
>> LHSBits;
>>      }
>> @@ -2038,12 +2038,12 @@
>>      Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
>>    }
>>
>> -    return Rot.Val;
>> +    return Rot.getNode();
>>  }
>>
>>  // If there is a mask here, and we have a variable shift, we can't
>> be sure
>>  // that we're masking out the right stuff.
>> -  if (LHSMask.Val || RHSMask.Val)
>> +  if (LHSMask.getNode() || RHSMask.getNode())
>>    return 0;
>>
>>  // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
>> @@ -2054,9 +2054,9 @@
>>          dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
>>      if (SUBC->getAPIntValue() == OpSizeInBits) {
>>        if (HasROTL)
>> -          return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> LHSShiftAmt).Val;
>> +          return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> LHSShiftAmt).getNode();
>>        else
>> -          return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,
>> RHSShiftAmt).Val;
>> +          return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,
>> RHSShiftAmt).getNode();
>>      }
>>    }
>>  }
>> @@ -2069,9 +2069,9 @@
>>          dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
>>      if (SUBC->getAPIntValue() == OpSizeInBits) {
>>        if (HasROTL)
>> -          return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> LHSShiftAmt).Val;
>> +          return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> LHSShiftAmt).getNode();
>>        else
>> -          return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,
>> RHSShiftAmt).Val;
>> +          return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,
>> RHSShiftAmt).getNode();
>>      }
>>    }
>>  }
>> @@ -2094,9 +2094,9 @@
>>      if (ConstantSDNode *SUBC =
>> cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
>>        if (SUBC->getAPIntValue() == OpSizeInBits) {
>>          if (HasROTL)
>> -            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> LHSShiftAmt).Val;
>> +            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> LHSShiftAmt).getNode();
>>          else
>> -            return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,
>> RHSShiftAmt).Val;
>> +            return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,
>> RHSShiftAmt).getNode();
>>        }
>>      }
>>    } else if (LExtOp0.getOpcode() == ISD::SUB &&
>> @@ -2108,9 +2108,9 @@
>>      if (ConstantSDNode *SUBC =
>> cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
>>        if (SUBC->getAPIntValue() == OpSizeInBits) {
>>          if (HasROTL)
>> -            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> RHSShiftAmt).Val;
>> +            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> RHSShiftAmt).getNode();
>>          else
>> -            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> LHSShiftAmt).Val;
>> +            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> LHSShiftAmt).getNode();
>>        }
>>      }
>>    }
>> @@ -2131,7 +2131,7 @@
>>  // fold vector ops
>>  if (VT.isVector()) {
>>    SDValue FoldedVOp = SimplifyVBinOp(N);
>> -    if (FoldedVOp.Val) return FoldedVOp;
>> +    if (FoldedVOp.getNode()) return FoldedVOp;
>>  }
>>
>>  // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
>> @@ -2153,7 +2153,7 @@
>>    return N0;
>>  // reassociate xor
>>  SDValue RXOR = ReassociateOps(ISD::XOR, N0, N1);
>> -  if (RXOR.Val != 0)
>> +  if (RXOR.getNode() != 0)
>>    return RXOR;
>>  // fold !(x cc y) -> (x !cc y)
>>  if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS,
>> RHS, CC)) {
>> @@ -2169,11 +2169,11 @@
>>  }
>>  // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
>>  if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() ==
>> ISD::ZERO_EXTEND &&
>> -      N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0),
>> LHS, RHS, CC)){
>> +      N0.getNode()->hasOneUse() &&
>> isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
>>    SDValue V = N0.getOperand(0);
>>    V = DAG.getNode(ISD::XOR, V.getValueType(), V,
>>                    DAG.getConstant(1, V.getValueType()));
>> -    AddToWorkList(V.Val);
>> +    AddToWorkList(V.getNode());
>>    return DAG.getNode(ISD::ZERO_EXTEND, VT, V);
>>  }
>>
>> @@ -2185,7 +2185,7 @@
>>      unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR :
>> ISD::AND;
>>      LHS = DAG.getNode(ISD::XOR, VT, LHS, N1);  // RHS = ~LHS
>>      RHS = DAG.getNode(ISD::XOR, VT, RHS, N1);  // RHS = ~RHS
>> -      AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
>> +      AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
>>      return DAG.getNode(NewOpcode, VT, LHS, RHS);
>>    }
>>  }
>> @@ -2197,7 +2197,7 @@
>>      unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR :
>> ISD::AND;
>>      LHS = DAG.getNode(ISD::XOR, VT, LHS, N1);  // RHS = ~LHS
>>      RHS = DAG.getNode(ISD::XOR, VT, RHS, N1);  // RHS = ~RHS
>> -      AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
>> +      AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
>>      return DAG.getNode(NewOpcode, VT, LHS, RHS);
>>    }
>>  }
>> @@ -2229,7 +2229,7 @@
>>  // Simplify: xor (op x...), (op y...)  -> (op (xor x, y))
>>  if (N0.getOpcode() == N1.getOpcode()) {
>>    SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
>> -    if (Tmp.Val) return Tmp;
>> +    if (Tmp.getNode()) return Tmp;
>>  }
>>
>>  // Simplify the expression using non-local knowledge.
>> @@ -2243,7 +2243,7 @@
>> /// visitShiftByConstant - Handle transforms common to the three
>> shifts, when
>> /// the shift amount is a constant.
>> SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
>> -  SDNode *LHS = N->getOperand(0).Val;
>> +  SDNode *LHS = N->getOperand(0).getNode();
>>  if (!LHS->hasOneUse()) return SDValue();
>>
>>  // We want to pull some binops through shifts, so that we have
>> (and (shift))
>> @@ -2278,7 +2278,7 @@
>>  //
>>  //void foo(int *X, int i) { X[i & 1235] = 1; }
>>  //int bar(int *X, int i) { return X[i & 255]; }
>> -  SDNode *BinOpLHSVal = LHS->getOperand(0).Val;
>> +  SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
>>  if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
>>       BinOpLHSVal->getOpcode() != ISD::SRA &&
>>       BinOpLHSVal->getOpcode() != ISD::SRL) ||
>> @@ -2502,7 +2502,7 @@
>>      return DAG.getNode(ISD::UNDEF, VT);
>>
>>    SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT,
>> N0.getOperand(0), N1);
>> -    AddToWorkList(SmallShift.Val);
>> +    AddToWorkList(SmallShift.getNode());
>>    return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
>>  }
>>
>> @@ -2540,7 +2540,7 @@
>>      if (ShAmt) {
>>        Op = DAG.getNode(ISD::SRL, VT, Op,
>>                         DAG.getConstant(ShAmt,
>> TLI.getShiftAmountTy()));
>> -        AddToWorkList(Op.Val);
>> +        AddToWorkList(Op.getNode());
>>      }
>>      return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
>>    }
>> @@ -2612,7 +2612,7 @@
>>    SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0,
>> DAG.getConstant(1, VT0));
>>    if (VT == VT0)
>>      return XORNode;
>> -    AddToWorkList(XORNode.Val);
>> +    AddToWorkList(XORNode.getNode());
>>    if (VT.bitsGT(VT0))
>>      return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
>>    return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
>> @@ -2620,13 +2620,13 @@
>>  // fold select C, 0, X -> ~C & X
>>  if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
>>    SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0,
>> DAG.getConstant(1, VT));
>> -    AddToWorkList(XORNode.Val);
>> +    AddToWorkList(XORNode.getNode());
>>    return DAG.getNode(ISD::AND, VT, XORNode, N2);
>>  }
>>  // fold select C, X, 1 -> ~C | X
>>  if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() ==
>> 1) {
>>    SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0,
>> DAG.getConstant(1, VT));
>> -    AddToWorkList(XORNode.Val);
>> +    AddToWorkList(XORNode.getNode());
>>    return DAG.getNode(ISD::OR, VT, XORNode, N1);
>>  }
>>  // fold select C, X, 0 -> C & X
>> @@ -2673,9 +2673,9 @@
>>
>>  // Determine if the condition we're dealing with is constant
>>  SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1,
>> CC, false);
>> -  if (SCC.Val) AddToWorkList(SCC.Val);
>> +  if (SCC.getNode()) AddToWorkList(SCC.getNode());
>>
>> -  if (ConstantSDNode *SCCC =
>> dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
>> +  if (ConstantSDNode *SCCC =
>> dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
>>    if (!SCCC->isNullValue())
>>      return N2;    // cond always true -> true val
>>    else
>> @@ -2683,7 +2683,7 @@
>>  }
>>
>>  // Fold to a simpler select_cc
>> -  if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
>> +  if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
>>    return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
>>                       SCC.getOperand(0), SCC.getOperand(1), N2, N3,
>>                       SCC.getOperand(2));
>> @@ -2711,7 +2711,7 @@
>>                                    TargetLowering &TLI) {
>>  bool HasCopyToRegUses = false;
>>  bool isTruncFree = TLI.isTruncateFree(N->getValueType(0),
>> N0.getValueType());
>> -  for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val-
>>> use_end();
>> +  for (SDNode::use_iterator UI = N0.getNode()->use_begin(), UE =
>> N0.getNode()->use_end();
>>       UI != UE; ++UI) {
>>    SDNode *User = *UI;
>>    if (User == N)
>> @@ -2755,7 +2755,7 @@
>>      SDNode *User = *UI;
>>      for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
>>        SDValue UseOp = User->getOperand(i);
>> -        if (UseOp.Val == N && UseOp.getResNo() == 0) {
>> +        if (UseOp.getNode() == N && UseOp.getResNo() == 0) {
>>          BothLiveOut = true;
>>          break;
>>        }
>> @@ -2785,10 +2785,10 @@
>>  if (N0.getOpcode() == ISD::TRUNCATE) {
>>    // fold (sext (truncate (load x))) -> (sext (smaller load x))
>>    // fold (sext (truncate (srl (load x), c))) -> (sext (smaller
>> load (x+c/n)))
>> -    SDValue NarrowLoad = ReduceLoadWidth(N0.Val);
>> -    if (NarrowLoad.Val) {
>> -      if (NarrowLoad.Val != N0.Val)
>> -        CombineTo(N0.Val, NarrowLoad);
>> +    SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
>> +    if (NarrowLoad.getNode()) {
>> +      if (NarrowLoad.getNode() != N0.getNode())
>> +        CombineTo(N0.getNode(), NarrowLoad);
>>      return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
>>    }
>>
>> @@ -2830,7 +2830,7 @@
>>  }
>>
>>  // fold (sext (load x)) -> (sext (truncate (sextload x)))
>> -  if (ISD::isNON_EXTLoad(N0.Val) &&
>> +  if (ISD::isNON_EXTLoad(N0.getNode()) &&
>>      ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
>>       TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))) {
>>    bool DoXform = true;
>> @@ -2847,7 +2847,7 @@
>>                                         LN0->getAlignment());
>>      CombineTo(N, ExtLoad);
>>      SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(),
>> ExtLoad);
>> -      CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
>> +      CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
>>      // Extend SetCC uses if necessary.
>>      for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
>>        SDNode *SetCC = SetCCs[i];
>> @@ -2869,8 +2869,8 @@
>>
>>  // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
>>  // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
>> -  if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
>> -      ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
>> +  if ((ISD::isSEXTLoad(N0.getNode()) ||
>> ISD::isEXTLoad(N0.getNode())) &&
>> +      ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
>>    LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>>    MVT EVT = LN0->getMemoryVT();
>>    if ((!AfterLegalize && !LN0->isVolatile()) ||
>> @@ -2881,7 +2881,7 @@
>>                                         LN0->isVolatile(),
>>                                         LN0->getAlignment());
>>      CombineTo(N, ExtLoad);
>> -      CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE,
>> N0.getValueType(), ExtLoad),
>> +      CombineTo(N0.getNode(), DAG.getNode(ISD::TRUNCATE,
>> N0.getValueType(), ExtLoad),
>>                ExtLoad.getValue(1));
>>      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
>>    }
>> @@ -2893,7 +2893,7 @@
>>      SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
>>                       DAG.getConstant(~0ULL, VT),
>> DAG.getConstant(0, VT),
>>                       cast<CondCodeSDNode>(N0.getOperand(2))-
>>> get(), true);
>> -    if (SCC.Val) return SCC;
>> +    if (SCC.getNode()) return SCC;
>>  }
>>
>>  // fold (sext x) -> (zext x) if the sign bit is known zero.
>> @@ -2919,10 +2919,10 @@
>>  // fold (zext (truncate (load x))) -> (zext (smaller load x))
>>  // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x
>> +c/n)))
>>  if (N0.getOpcode() == ISD::TRUNCATE) {
>> -    SDValue NarrowLoad = ReduceLoadWidth(N0.Val);
>> -    if (NarrowLoad.Val) {
>> -      if (NarrowLoad.Val != N0.Val)
>> -        CombineTo(N0.Val, NarrowLoad);
>> +    SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
>> +    if (NarrowLoad.getNode()) {
>> +      if (NarrowLoad.getNode() != N0.getNode())
>> +        CombineTo(N0.getNode(), NarrowLoad);
>>      return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
>>    }
>>  }
>> @@ -2955,7 +2955,7 @@
>>  }
>>
>>  // fold (zext (load x)) -> (zext (truncate (zextload x)))
>> -  if (ISD::isNON_EXTLoad(N0.Val) &&
>> +  if (ISD::isNON_EXTLoad(N0.getNode()) &&
>>      ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
>>       TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
>>    bool DoXform = true;
>> @@ -2972,7 +2972,7 @@
>>                                         LN0->getAlignment());
>>      CombineTo(N, ExtLoad);
>>      SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(),
>> ExtLoad);
>> -      CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
>> +      CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
>>      // Extend SetCC uses if necessary.
>>      for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
>>        SDNode *SetCC = SetCCs[i];
>> @@ -2994,8 +2994,8 @@
>>
>>  // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
>>  // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
>> -  if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
>> -      ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
>> +  if ((ISD::isZEXTLoad(N0.getNode()) ||
>> ISD::isEXTLoad(N0.getNode())) &&
>> +      ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
>>    LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>>    MVT EVT = LN0->getMemoryVT();
>>    if ((!AfterLegalize && !LN0->isVolatile()) ||
>> @@ -3006,7 +3006,7 @@
>>                                         LN0->isVolatile(),
>>                                         LN0->getAlignment());
>>      CombineTo(N, ExtLoad);
>> -      CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE,
>> N0.getValueType(), ExtLoad),
>> +      CombineTo(N0.getNode(), DAG.getNode(ISD::TRUNCATE,
>> N0.getValueType(), ExtLoad),
>>                ExtLoad.getValue(1));
>>      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
>>    }
>> @@ -3018,7 +3018,7 @@
>>      SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
>>                       DAG.getConstant(1, VT), DAG.getConstant(0, VT),
>>                       cast<CondCodeSDNode>(N0.getOperand(2))-
>>> get(), true);
>> -    if (SCC.Val) return SCC;
>> +    if (SCC.getNode()) return SCC;
>>  }
>>
>>  return SDValue();
>> @@ -3042,10 +3042,10 @@
>>  // fold (aext (truncate (load x))) -> (aext (smaller load x))
>>  // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x
>> +c/n)))
>>  if (N0.getOpcode() == ISD::TRUNCATE) {
>> -    SDValue NarrowLoad = ReduceLoadWidth(N0.Val);
>> -    if (NarrowLoad.Val) {
>> -      if (NarrowLoad.Val != N0.Val)
>> -        CombineTo(N0.Val, NarrowLoad);
>> +    SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
>> +    if (NarrowLoad.getNode()) {
>> +      if (NarrowLoad.getNode() != N0.getNode())
>> +        CombineTo(N0.getNode(), NarrowLoad);
>>      return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
>>    }
>>  }
>> @@ -3076,7 +3076,7 @@
>>  }
>>
>>  // fold (aext (load x)) -> (aext (truncate (extload x)))
>> -  if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
>> +  if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
>>      ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
>>       TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
>>    LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>> @@ -3088,7 +3088,7 @@
>>                                       LN0->getAlignment());
>>    CombineTo(N, ExtLoad);
>>    // Redirect any chain users to the new load.
>> -    DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1),
>> SDValue(ExtLoad.Val, 1));
>> +    DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1),
>> SDValue(ExtLoad.getNode(), 1));
>>    // If any node needs the original loaded value, recompute it.
>>    if (!LN0->use_empty())
>>      CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(),
>> ExtLoad),
>> @@ -3100,7 +3100,7 @@
>>  // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
>>  // fold (aext ( extload x)) -> (aext (truncate (extload  x)))
>>  if (N0.getOpcode() == ISD::LOAD &&
>> -      !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
>> +      !ISD::isNON_EXTLoad(N0.getNode()) &&
>> ISD::isUNINDEXEDLoad(N0.getNode()) &&
>>      N0.hasOneUse()) {
>>    LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>>    MVT EVT = LN0->getMemoryVT();
>> @@ -3111,7 +3111,7 @@
>>                                       LN0->isVolatile(),
>>                                       LN0->getAlignment());
>>    CombineTo(N, ExtLoad);
>> -    CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(),
>> ExtLoad),
>> +    CombineTo(N0.getNode(), DAG.getNode(ISD::TRUNCATE,
>> N0.getValueType(), ExtLoad),
>>              ExtLoad.getValue(1));
>>    return SDValue(N, 0);   // Return N so it doesn't get rechecked!
>>  }
>> @@ -3122,7 +3122,7 @@
>>      SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
>>                       DAG.getConstant(1, VT), DAG.getConstant(0, VT),
>>                       cast<CondCodeSDNode>(N0.getOperand(2))-
>>> get(), true);
>> -    if (SCC.Val)
>> +    if (SCC.getNode())
>>      return SCC;
>>  }
>>
>> @@ -3145,14 +3145,14 @@
>>    break;
>>  case ISD::SRL:
>>    // Only look at single-use SRLs.
>> -    if (!V.Val->hasOneUse())
>> +    if (!V.getNode()->hasOneUse())
>>      break;
>>    if (ConstantSDNode *RHSC =
>> dyn_cast<ConstantSDNode>(V.getOperand(1))) {
>>      // See if we can recursively simplify the LHS.
>>      unsigned Amt = RHSC->getValue();
>>      APInt NewMask = Mask << Amt;
>>      SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
>> -      if (SimplifyLHS.Val) {
>> +      if (SimplifyLHS.getNode()) {
>>        return DAG.getNode(ISD::SRL, V.getValueType(),
>>                           SimplifyLHS, V.getOperand(1));
>>      }
>> @@ -3221,7 +3221,7 @@
>>    unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
>>    SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
>>                                   DAG.getConstant(PtrOff, PtrType));
>> -    AddToWorkList(NewPtr.Val);
>> +    AddToWorkList(NewPtr.getNode());
>>    SDValue Load = (ExtType == ISD::NON_EXTLOAD)
>>      ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
>>                    LN0->getSrcValue(), LN0->getSrcValueOffset() +
>> PtrOff,
>> @@ -3234,9 +3234,9 @@
>>      WorkListRemover DeadNodes(*this);
>>      DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
>>                                    &DeadNodes);
>> -      CombineTo(N->getOperand(0).Val, Load);
>> +      CombineTo(N->getOperand(0).getNode(), Load);
>>    } else
>> -      CombineTo(N0.Val, Load, Load.getValue(1));
>> +      CombineTo(N0.getNode(), Load, Load.getValue(1));
>>    if (ShAmt) {
>>      if (Opc == ISD::SIGN_EXTEND_INREG)
>>        return DAG.getNode(Opc, VT, Load, N->getOperand(1));
>> @@ -3293,7 +3293,7 @@
>>  // fold (sext_in_reg (load x)) -> (smaller sextload x)
>>  // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/
>> evtbits))
>>  SDValue NarrowLoad = ReduceLoadWidth(N);
>> -  if (NarrowLoad.Val)
>> +  if (NarrowLoad.getNode())
>>    return NarrowLoad;
>>
>>  // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
>> @@ -3311,8 +3311,8 @@
>>  }
>>
>>  // fold (sext_inreg (extload x)) -> (sextload x)
>> -  if (ISD::isEXTLoad(N0.Val) &&
>> -      ISD::isUNINDEXEDLoad(N0.Val) &&
>> +  if (ISD::isEXTLoad(N0.getNode()) &&
>> +      ISD::isUNINDEXEDLoad(N0.getNode()) &&
>>      EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
>>      ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
>>       TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
>> @@ -3323,11 +3323,11 @@
>>                                       LN0->isVolatile(),
>>                                       LN0->getAlignment());
>>    CombineTo(N, ExtLoad);
>> -    CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
>> +    CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
>>    return SDValue(N, 0);   // Return N so it doesn't get rechecked!
>>  }
>>  // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one
>> use
>> -  if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
>> +  if (ISD::isZEXTLoad(N0.getNode()) &&
>> ISD::isUNINDEXEDLoad(N0.getNode()) &&
>>      N0.hasOneUse() &&
>>      EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
>>      ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
>> @@ -3339,7 +3339,7 @@
>>                                       LN0->isVolatile(),
>>                                       LN0->getAlignment());
>>    CombineTo(N, ExtLoad);
>> -    CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
>> +    CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
>>    return SDValue(N, 0);   // Return N so it doesn't get rechecked!
>>  }
>>  return SDValue();
>> @@ -3379,7 +3379,7 @@
>>  SDValue Shorter =
>>    GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
>>                                             VT.getSizeInBits()));
>> -  if (Shorter.Val)
>> +  if (Shorter.getNode())
>>    return DAG.getNode(ISD::TRUNCATE, VT, Shorter);
>>
>>  // fold (truncate (load x)) -> (smaller load x)
>> @@ -3390,8 +3390,8 @@
>> static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
>>  SDValue Elt = N->getOperand(i);
>>  if (Elt.getOpcode() != ISD::MERGE_VALUES)
>> -    return Elt.Val;
>> -  return Elt.getOperand(Elt.getResNo()).Val;
>> +    return Elt.getNode();
>> +  return Elt.getOperand(Elt.getResNo()).getNode();
>> }
>>
>> /// CombineConsecutiveLoads - build_pair (load, load) -> load
>> @@ -3434,7 +3434,7 @@
>>  // on the bitconvert.
>>  // First check to see if this is all constant.
>>  if (!AfterLegalize &&
>> -      N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
>> +      N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()-
>>> hasOneUse() &&
>>      VT.isVector()) {
>>    bool isSimple = true;
>>    for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
>> @@ -3449,14 +3449,14 @@
>>    assert(!DestEltVT.isVector() &&
>>           "Element type of vector ValueType must not be vector!");
>>    if (isSimple) {
>> -      return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val,
>> DestEltVT);
>> +      return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(),
>> DestEltVT);
>>    }
>>  }
>>
>>  // If the input is a constant, let getNode() fold it.
>>  if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
>>    SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
>> -    if (Res.Val != N) return Res;
>> +    if (Res.getNode() != N) return Res;
>>  }
>>
>>  if (N0.getOpcode() == ISD::BIT_CONVERT)  // conv(conv(x,t1),t2) ->
>> conv(x,t2)
>> @@ -3464,7 +3464,7 @@
>>
>>  // fold (conv (load x)) -> (load (conv*)x)
>>  // If the resultant load doesn't need a higher alignment than the
>> original!
>> -  if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() &&
>> +  if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
>>      // Do not change the width of a volatile load.
>>      !cast<LoadSDNode>(N0)->isVolatile() &&
>>      (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) {
>> @@ -3477,7 +3477,7 @@
>>                                   LN0->getSrcValue(), LN0-
>>> getSrcValueOffset(),
>>                                   LN0->isVolatile(), OrigAlign);
>>      AddToWorkList(N);
>> -      CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT,
>> N0.getValueType(), Load),
>> +      CombineTo(N0.getNode(), DAG.getNode(ISD::BIT_CONVERT,
>> N0.getValueType(), Load),
>>                Load.getValue(1));
>>      return Load;
>>    }
>> @@ -3487,9 +3487,9 @@
>>  // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit)
>>  // This often reduces constant pool loads.
>>  if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
>> -      N0.Val->hasOneUse() && VT.isInteger() && !VT.isVector()) {
>> +      N0.getNode()->hasOneUse() && VT.isInteger() && !
>> VT.isVector()) {
>>    SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT,
>> N0.getOperand(0));
>> -    AddToWorkList(NewConv.Val);
>> +    AddToWorkList(NewConv.getNode());
>>
>>    APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
>>    if (N0.getOpcode() == ISD::FNEG)
>> @@ -3501,45 +3501,45 @@
>>  // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign |
>> cst&~sign'
>>  // Note that we don't handle copysign(x,cst) because this can
>> always be folded
>>  // to an fneg or fabs.
>> -  if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() &&
>> +  if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()
>> &&
>>      isa<ConstantFPSDNode>(N0.getOperand(0)) &&
>>      VT.isInteger() && !VT.isVector()) {
>>    unsigned OrigXWidth =
>> N0.getOperand(1).getValueType().getSizeInBits();
>>    SDValue X = DAG.getNode(ISD::BIT_CONVERT,
>>                              MVT::getIntegerVT(OrigXWidth),
>>                              N0.getOperand(1));
>> -    AddToWorkList(X.Val);
>> +    AddToWorkList(X.getNode());
>>
>>    // If X has a different width than the result/lhs, sext it or
>> truncate it.
>>    unsigned VTWidth = VT.getSizeInBits();
>>    if (OrigXWidth < VTWidth) {
>>      X = DAG.getNode(ISD::SIGN_EXTEND, VT, X);
>> -      AddToWorkList(X.Val);
>> +      AddToWorkList(X.getNode());
>>    } else if (OrigXWidth > VTWidth) {
>>      // To get the sign bit in the right place, we have to shift it
>> right
>>      // before truncating.
>>      X = DAG.getNode(ISD::SRL, X.getValueType(), X,
>>                      DAG.getConstant(OrigXWidth-VTWidth,
>> X.getValueType()));
>> -      AddToWorkList(X.Val);
>> +      AddToWorkList(X.getNode());
>>      X = DAG.getNode(ISD::TRUNCATE, VT, X);
>> -      AddToWorkList(X.Val);
>> +      AddToWorkList(X.getNode());
>>    }
>>
>>    APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
>>    X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT));
>> -    AddToWorkList(X.Val);
>> +    AddToWorkList(X.getNode());
>>
>>    SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
>>    Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit,
>> VT));
>> -    AddToWorkList(Cst.Val);
>> +    AddToWorkList(Cst.getNode());
>>
>>    return DAG.getNode(ISD::OR, VT, X, Cst);
>>  }
>>
>>  // bitconvert(build_pair(ld, ld)) -> ld iff load locations are
>> consecutive.
>>  if (N0.getOpcode() == ISD::BUILD_PAIR) {
>> -    SDValue CombineLD = CombineConsecutiveLoads(N0.Val, VT);
>> -    if (CombineLD.Val)
>> +    SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
>> +    if (CombineLD.getNode())
>>      return CombineLD;
>>  }
>>
>> @@ -3570,7 +3570,7 @@
>>    SmallVector<SDValue, 8> Ops;
>>    for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
>>      Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV-
>>> getOperand(i)));
>> -      AddToWorkList(Ops.back().Val);
>> +      AddToWorkList(Ops.back().getNode());
>>    }
>>    MVT VT = MVT::getVectorVT(DstEltVT,
>>                              BV-
>>> getValueType(0).getVectorNumElements());
>> @@ -3585,7 +3585,7 @@
>>    // same sizes.
>>    assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) &&
>> "Unknown FP VT!");
>>    MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits());
>> -    BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
>> +    BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
>>    SrcEltVT = IntVT;
>>  }
>>
>> @@ -3594,7 +3594,7 @@
>>  if (DstEltVT.isFloatingPoint()) {
>>    assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) &&
>> "Unknown FP VT!");
>>    MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits());
>> -    SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV,
>> TmpVT).Val;
>> +    SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV,
>> TmpVT).getNode();
>>
>>    // Next, convert to FP elements of the same size.
>>    return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
>> @@ -3674,7 +3674,7 @@
>>  // fold vector ops
>>  if (VT.isVector()) {
>>    SDValue FoldedVOp = SimplifyVBinOp(N);
>> -    if (FoldedVOp.Val) return FoldedVOp;
>> +    if (FoldedVOp.getNode()) return FoldedVOp;
>>  }
>>
>>  // fold (fadd c1, c2) -> c1+c2
>> @@ -3694,7 +3694,7 @@
>>
>>  // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1,
>> c2))
>>  if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
>> -      N0.Val->hasOneUse() &&  
>> isa<ConstantFPSDNode>(N0.getOperand(1)))
>> +      N0.getNode()->hasOneUse() &&
>> isa<ConstantFPSDNode>(N0.getOperand(1)))
>>    return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
>>                       DAG.getNode(ISD::FADD, VT, N0.getOperand(1),
>> N1));
>>
>> @@ -3711,7 +3711,7 @@
>>  // fold vector ops
>>  if (VT.isVector()) {
>>    SDValue FoldedVOp = SimplifyVBinOp(N);
>> -    if (FoldedVOp.Val) return FoldedVOp;
>> +    if (FoldedVOp.getNode()) return FoldedVOp;
>>  }
>>
>>  // fold (fsub c1, c2) -> c1-c2
>> @@ -3741,7 +3741,7 @@
>>  // fold vector ops
>>  if (VT.isVector()) {
>>    SDValue FoldedVOp = SimplifyVBinOp(N);
>> -    if (FoldedVOp.Val) return FoldedVOp;
>> +    if (FoldedVOp.getNode()) return FoldedVOp;
>>  }
>>
>>  // fold (fmul c1, c2) -> c1*c2
>> @@ -3771,7 +3771,7 @@
>>
>>  // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1,
>> c2))
>>  if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
>> -      N0.Val->hasOneUse() &&  
>> isa<ConstantFPSDNode>(N0.getOperand(1)))
>> +      N0.getNode()->hasOneUse() &&
>> isa<ConstantFPSDNode>(N0.getOperand(1)))
>>    return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
>>                       DAG.getNode(ISD::FMUL, VT, N0.getOperand(1),
>> N1));
>>
>> @@ -3788,7 +3788,7 @@
>>  // fold vector ops
>>  if (VT.isVector()) {
>>    SDValue FoldedVOp = SimplifyVBinOp(N);
>> -    if (FoldedVOp.Val) return FoldedVOp;
>> +    if (FoldedVOp.getNode()) return FoldedVOp;
>>  }
>>
>>  // fold (fdiv c1, c2) -> c1/c2
>> @@ -3955,15 +3955,15 @@
>>  if (N0.getOpcode() == ISD::FP_ROUND) {
>>    // This is a value preserving truncation if both round's are.
>>    bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
>> -                   N0.Val->getConstantOperandVal(1) == 1;
>> +                   N0.getNode()->getConstantOperandVal(1) == 1;
>>    return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0),
>>                       DAG.getIntPtrConstant(IsTrunc));
>>  }
>>
>>  // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
>> -  if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
>> +  if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()-
>>> hasOneUse()) {
>>    SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0),
>> N1);
>> -    AddToWorkList(Tmp.Val);
>> +    AddToWorkList(Tmp.getNode());
>>    return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
>>  }
>>
>> @@ -4000,7 +4000,7 @@
>>
>>  // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't
>> affect the
>>  // value of X.
>> -  if (N0.getOpcode() == ISD::FP_ROUND && N0.Val-
>>> getConstantOperandVal(1) == 1){
>> +  if (N0.getOpcode() == ISD::FP_ROUND && N0.getNode()-
>>> getConstantOperandVal(1) == 1){
>>    SDValue In = N0.getOperand(0);
>>    if (In.getValueType() == VT) return In;
>>    if (VT.bitsLT(In.getValueType()))
>> @@ -4009,7 +4009,7 @@
>>  }
>>
>>  // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
>> -  if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
>> +  if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
>>      ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
>>       TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
>>    LoadSDNode *LN0 = cast<LoadSDNode>(N0);
>> @@ -4020,7 +4020,7 @@
>>                                       LN0->isVolatile(),
>>                                       LN0->getAlignment());
>>    CombineTo(N, ExtLoad);
>> -    CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(),
>> ExtLoad,
>> +    CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND,
>> N0.getValueType(), ExtLoad,
>>                                  DAG.getIntPtrConstant(1)),
>>              ExtLoad.getValue(1));
>>    return SDValue(N, 0);   // Return N so it doesn't get rechecked!
>> @@ -4037,7 +4037,7 @@
>>
>>  // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid
>> loading
>>  // constant pool values.
>> -  if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() &&
>> +  if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()-
>>> hasOneUse() &&
>>      N0.getOperand(0).getValueType().isInteger() &&
>>      !N0.getOperand(0).getValueType().isVector()) {
>>    SDValue Int = N0.getOperand(0);
>> @@ -4045,7 +4045,7 @@
>>    if (IntVT.isInteger() && !IntVT.isVector()) {
>>      Int = DAG.getNode(ISD::XOR, IntVT, Int,
>>                        DAG.getConstant(IntVT.getIntegerVTSignBit(),
>> IntVT));
>> -      AddToWorkList(Int.Val);
>> +      AddToWorkList(Int.getNode());
>>      return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
>>    }
>>  }
>> @@ -4071,7 +4071,7 @@
>>
>>  // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid
>> loading
>>  // constant pool values.
>> -  if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() &&
>> +  if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()-
>>> hasOneUse() &&
>>      N0.getOperand(0).getValueType().isInteger() &&
>>      !N0.getOperand(0).getValueType().isVector()) {
>>    SDValue Int = N0.getOperand(0);
>> @@ -4079,7 +4079,7 @@
>>    if (IntVT.isInteger() && !IntVT.isVector()) {
>>      Int = DAG.getNode(ISD::AND, IntVT, Int,
>>
>> DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT));
>> -      AddToWorkList(Int.Val);
>> +      AddToWorkList(Int.getNode());
>>      return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
>>    }
>>  }
>> @@ -4117,9 +4117,9 @@
>>
>>  // Use SimplifySetCC to simplify SETCC's.
>>  SDValue Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(),
>> false);
>> -  if (Simp.Val) AddToWorkList(Simp.Val);
>> +  if (Simp.getNode()) AddToWorkList(Simp.getNode());
>>
>> -  ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
>> +  ConstantSDNode *SCCC =
>> dyn_cast_or_null<ConstantSDNode>(Simp.getNode());
>>
>>  // fold br_cc true, dest -> br dest (unconditional branch)
>>  if (SCCC && !SCCC->isNullValue())
>> @@ -4130,7 +4130,7 @@
>>    return N->getOperand(0);
>>
>>  // fold to a simpler setcc
>> -  if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
>> +  if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
>>    return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
>>                       Simp.getOperand(2), Simp.getOperand(0),
>>                       Simp.getOperand(1), N->getOperand(4));
>> @@ -4174,7 +4174,7 @@
>>  // If the pointer is not an add/sub, or if it doesn't have
>> multiple uses, bail
>>  // out.  There is no reason to make this a preinc/predec.
>>  if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
>> -      Ptr.Val->hasOneUse())
>> +      Ptr.getNode()->hasOneUse())
>>    return false;
>>
>>  // Ask the target to do addressing mode selection.
>> @@ -4204,14 +4204,14 @@
>>  // Check #2.
>>  if (!isLoad) {
>>    SDValue Val = cast<StoreSDNode>(N)->getValue();
>> -    if (Val == BasePtr || BasePtr.Val->isPredecessorOf(Val.Val))
>> +    if (Val == BasePtr || BasePtr.getNode()-
>>> isPredecessorOf(Val.getNode()))
>>      return false;
>>  }
>>
>>  // Now check for #3 and #4.
>>  bool RealUse = false;
>> -  for (SDNode::use_iterator I = Ptr.Val->use_begin(),
>> -         E = Ptr.Val->use_end(); I != E; ++I) {
>> +  for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
>> +         E = Ptr.getNode()->use_end(); I != E; ++I) {
>>    SDNode *Use = *I;
>>    if (Use == N)
>>      continue;
>> @@ -4235,7 +4235,7 @@
>>  ++PreIndexedNodes;
>>  ++NodesCombined;
>>  DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
>> -  DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
>> +  DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
>>  DOUT << '\n';
>>  WorkListRemover DeadNodes(*this);
>>  if (isLoad) {
>> @@ -4254,8 +4254,8 @@
>>  // Replace the uses of Ptr with uses of the updated base value.
>>  DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
>>                                &DeadNodes);
>> -  removeFromWorkList(Ptr.Val);
>> -  DAG.DeleteNode(Ptr.Val);
>> +  removeFromWorkList(Ptr.getNode());
>> +  DAG.DeleteNode(Ptr.getNode());
>>
>>  return true;
>> }
>> @@ -4292,11 +4292,11 @@
>>  } else
>>    return false;
>>
>> -  if (Ptr.Val->hasOneUse())
>> +  if (Ptr.getNode()->hasOneUse())
>>    return false;
>>
>> -  for (SDNode::use_iterator I = Ptr.Val->use_begin(),
>> -         E = Ptr.Val->use_end(); I != E; ++I) {
>> +  for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
>> +         E = Ptr.getNode()->use_end(); I != E; ++I) {
>>    SDNode *Op = *I;
>>    if (Op == N ||
>>        (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
>> @@ -4323,10 +4323,10 @@
>>
>>      // Check for #1.
>>      bool TryNext = false;
>> -      for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
>> -             EE = BasePtr.Val->use_end(); II != EE; ++II) {
>> +      for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
>> +             EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
>>        SDNode *Use = *II;
>> -        if (Use == Ptr.Val)
>> +        if (Use == Ptr.getNode())
>>          continue;
>>
>>        // If all the uses are load / store addresses, then don't do
>> the
>> @@ -4337,9 +4337,9 @@
>>                 EEE = Use->use_end(); III != EEE; ++III) {
>>            SDNode *UseUse = *III;
>>            if (!((UseUse->getOpcode() == ISD::LOAD &&
>> -                   cast<LoadSDNode>(UseUse)->getBasePtr().Val ==
>> Use) ||
>> +                   cast<LoadSDNode>(UseUse)->getBasePtr().getNode()
>> == Use) ||
>>                  (UseUse->getOpcode() == ISD::STORE &&
>> -                   cast<StoreSDNode>(UseUse)->getBasePtr().Val ==
>> Use)))
>> +                   cast<StoreSDNode>(UseUse)-
>>> getBasePtr().getNode() == Use)))
>>              RealUse = true;
>>          }
>>
>> @@ -4360,7 +4360,7 @@
>>        ++PostIndexedNodes;
>>        ++NodesCombined;
>>        DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
>> -        DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
>> +        DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
>>        DOUT << '\n';
>>        WorkListRemover DeadNodes(*this);
>>        if (isLoad) {
>> @@ -4463,7 +4463,7 @@
>>        // Now we replace use of chain2 with chain1.  This makes the
>> second load
>>        // isomorphic to the one we are deleting, and thus makes
>> this load live.
>>        DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
>> -        DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG));
>> +        DOUT << "\nWith chain: "; DEBUG(Chain.getNode()- 
>> >dump(&DAG));
>>        DOUT << "\n";
>>        WorkListRemover DeadNodes(*this);
>>        DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain,
>> &DeadNodes);
>> @@ -4479,7 +4479,7 @@
>>      if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
>>        SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0));
>>        DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
>> -        DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG));
>> +        DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG));
>>        DOUT << " and 2 other values\n";
>>        WorkListRemover DeadNodes(*this);
>>        DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef,
>> &DeadNodes);
>> @@ -4500,7 +4500,7 @@
>>  // TODO: Handle TRUNCSTORE/LOADEXT
>>  if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
>>      !LD->isVolatile()) {
>> -    if (ISD::isNON_TRUNCStore(Chain.Val)) {
>> +    if (ISD::isNON_TRUNCStore(Chain.getNode())) {
>>      StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
>>      if (PrevST->getBasePtr() == Ptr &&
>>          PrevST->getValue().getValueType() == N->getValueType(0))
>> @@ -4684,8 +4684,8 @@
>>      GetDemandedBits(Value,
>>                 APInt::getLowBitsSet(Value.getValueSizeInBits(),
>>                                      ST-
>>> getMemoryVT().getSizeInBits()));
>> -    AddToWorkList(Value.Val);
>> -    if (Shorter.Val)
>> +    AddToWorkList(Value.getNode());
>> +    if (Shorter.getNode())
>>      return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(),
>>                               ST->getSrcValueOffset(), ST-
>>> getMemoryVT(),
>>                               ST->isVolatile(), ST->getAlignment());
>> @@ -4715,7 +4715,7 @@
>>  // If this is an FP_ROUND or TRUNC followed by a store, fold this
>> into a
>>  // truncating store.  We can do this even if this is already a
>> truncstore.
>>  if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() ==
>> ISD::TRUNCATE)
>> -      && Value.Val->hasOneUse() && ST->isUnindexed() &&
>> +      && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
>>      TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
>>                            ST->getMemoryVT())) {
>>    return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST-
>>> getSrcValue(),
>> @@ -4735,7 +4735,7 @@
>>  // vector with the inserted element.
>>  if (InVec.getOpcode() == ISD::BUILD_VECTOR &&
>> isa<ConstantSDNode>(EltNo)) {
>>    unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
>> -    SmallVector<SDValue, 8> Ops(InVec.Val->op_begin(), InVec.Val-
>>> op_end());
>> +    SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
>> InVec.getNode()->op_end());
>>    if (Elt < Ops.size())
>>      Ops[Elt] = InVal;
>>    return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
>> @@ -4773,11 +4773,11 @@
>>    }
>>
>>    LoadSDNode *LN0 = NULL;
>> -    if (ISD::isNormalLoad(InVec.Val))
>> +    if (ISD::isNormalLoad(InVec.getNode()))
>>      LN0 = cast<LoadSDNode>(InVec);
>>    else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
>>             InVec.getOperand(0).getValueType() == EVT &&
>> -             ISD::isNormalLoad(InVec.getOperand(0).Val)) {
>> +             ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
>>      LN0 = cast<LoadSDNode>(InVec.getOperand(0));
>>    } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) {
>>      // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
>> @@ -4789,7 +4789,7 @@
>>      InVec = (Idx < NumElems) ? InVec.getOperand(0) :
>> InVec.getOperand(1);
>>      if (InVec.getOpcode() == ISD::BIT_CONVERT)
>>        InVec = InVec.getOperand(0);
>> -      if (ISD::isNormalLoad(InVec.Val)) {
>> +      if (ISD::isNormalLoad(InVec.getNode())) {
>>        LN0 = cast<LoadSDNode>(InVec);
>>        Elt = (Idx < NumElems) ? Idx : Idx - NumElems;
>>      }
>> @@ -4859,9 +4859,9 @@
>>    if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
>>      continue;
>>
>> -    if (VecIn1.Val == 0) {
>> +    if (VecIn1.getNode() == 0) {
>>      VecIn1 = ExtractedFromVec;
>> -    } else if (VecIn2.Val == 0) {
>> +    } else if (VecIn2.getNode() == 0) {
>>      VecIn2 = ExtractedFromVec;
>>    } else {
>>      // Too many inputs.
>> @@ -4871,7 +4871,7 @@
>>  }
>>
>>  // If everything is good, we can make a shuffle operation.
>> -  if (VecIn1.Val) {
>> +  if (VecIn1.getNode()) {
>>    SmallVector<SDValue, 8> BuildVecIndices;
>>    for (unsigned i = 0; i != NumInScalars; ++i) {
>>      if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
>> @@ -4898,7 +4898,7 @@
>>    // Return the new VECTOR_SHUFFLE node.
>>    SDValue Ops[5];
>>    Ops[0] = VecIn1;
>> -    if (VecIn2.Val) {
>> +    if (VecIn2.getNode()) {
>>      Ops[1] = VecIn2;
>>    } else {
>>      // Use an undef build_vector as input for the second operand.
>> @@ -4907,7 +4907,7 @@
>>                                               EltType));
>>      Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
>>                           &UnOps[0], UnOps.size());
>> -      AddToWorkList(Ops[1].Val);
>> +      AddToWorkList(Ops[1].getNode());
>>    }
>>    Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
>>                         &BuildVecIndices[0], BuildVecIndices.size());
>> @@ -4989,7 +4989,7 @@
>>  // If it is a splat, check if the argument vector is a
>> build_vector with
>>  // all scalar elements the same.
>>  if (isSplat) {
>> -    SDNode *V = N0.Val;
>> +    SDNode *V = N0.getNode();
>>
>>    // If this is a bit convert that changes the element type of the
>> vector but
>>    // not the number of vector elements, look through it.  Be
>> careful not to
>> @@ -4998,7 +4998,7 @@
>>      SDValue ConvInput = V->getOperand(0);
>>      if (ConvInput.getValueType().isVector() &&
>>          ConvInput.getValueType().getVectorNumElements() == NumElts)
>> -        V = ConvInput.Val;
>> +        V = ConvInput.getNode();
>>    }
>>
>>    if (V->getOpcode() == ISD::BUILD_VECTOR) {
>> @@ -5013,7 +5013,7 @@
>>          }
>>        }
>>        // Splat of <u, u, u, u>, return <u, u, u, u>
>> -        if (!Base.Val)
>> +        if (!Base.getNode())
>>          return N0;
>>        for (unsigned i = 0; i != NumElems; ++i) {
>>          if (V->getOperand(i) != Base) {
>> @@ -5047,7 +5047,7 @@
>>    }
>>    ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
>>                           &MappedOps[0], MappedOps.size());
>> -    AddToWorkList(ShufMask.Val);
>> +    AddToWorkList(ShufMask.getNode());
>>    return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
>>                       N0,
>>                       DAG.getNode(ISD::UNDEF, N->getValueType(0)),
>> @@ -5093,7 +5093,7 @@
>>      std::vector<SDValue> Ops;
>>      LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
>>      Ops.push_back(LHS);
>> -      AddToWorkList(LHS.Val);
>> +      AddToWorkList(LHS.getNode());
>>      std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT));
>>      Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
>>                                &ZeroOps[0], ZeroOps.size()));
>> @@ -5123,7 +5123,7 @@
>>  SDValue LHS = N->getOperand(0);
>>  SDValue RHS = N->getOperand(1);
>>  SDValue Shuffle = XformToShuffleWithZero(N);
>> -  if (Shuffle.Val) return Shuffle;
>> +  if (Shuffle.getNode()) return Shuffle;
>>
>>  // If the LHS and RHS are BUILD_VECTOR nodes, see if we can
>> constant fold
>>  // this operation.
>> @@ -5145,13 +5145,13 @@
>>      if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV
>> ||
>>          N->getOpcode() == ISD::FDIV) {
>>        if ((RHSOp.getOpcode() == ISD::Constant &&
>> -             cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
>> +             cast<ConstantSDNode>(RHSOp.getNode())->isNullValue())  
>> ||
>>            (RHSOp.getOpcode() == ISD::ConstantFP &&
>> -             cast<ConstantFPSDNode>(RHSOp.Val)-
>>> getValueAPF().isZero()))
>> +             cast<ConstantFPSDNode>(RHSOp.getNode())-
>>> getValueAPF().isZero()))
>>          break;
>>      }
>>      Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp,
>> RHSOp));
>> -      AddToWorkList(Ops.back().Val);
>> +      AddToWorkList(Ops.back().getNode());
>>      assert((Ops.back().getOpcode() == ISD::UNDEF ||
>>              Ops.back().getOpcode() == ISD::Constant ||
>>              Ops.back().getOpcode() == ISD::ConstantFP) &&
>> @@ -5175,14 +5175,14 @@
>>  // If we got a simplified select_cc node back from
>> SimplifySelectCC, then
>>  // break it down into a new SETCC node, and a new SELECT node, and
>> then return
>>  // the SELECT node, since we were called with a SELECT node.
>> -  if (SCC.Val) {
>> +  if (SCC.getNode()) {
>>    // Check to see if we got a select_cc back (to turn into setcc/
>> select).
>>    // Otherwise, just return whatever node we got back, like fabs.
>>    if (SCC.getOpcode() == ISD::SELECT_CC) {
>>      SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
>>                                    SCC.getOperand(0),
>> SCC.getOperand(1),
>>                                    SCC.getOperand(4));
>> -      AddToWorkList(SETCC.Val);
>> +      AddToWorkList(SETCC.getNode());
>>      return DAG.getNode(ISD::SELECT, SCC.getValueType(),
>> SCC.getOperand(2),
>>                         SCC.getOperand(3), SETCC);
>>    }
>> @@ -5226,8 +5226,8 @@
>>        if (TheSelect->getOpcode() == ISD::SELECT) {
>>          // Check that the condition doesn't reach either load.  If
>> so, folding
>>          // this will induce a cycle into the DAG.
>> -          if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) &&
>> -              !RLD->isPredecessorOf(TheSelect->getOperand(0).Val)) {
>> +          if (!LLD->isPredecessorOf(TheSelect-
>>> getOperand(0).getNode()) &&
>> +              !RLD->isPredecessorOf(TheSelect-
>>> getOperand(0).getNode())) {
>>            Addr = DAG.getNode(ISD::SELECT, LLD-
>>> getBasePtr().getValueType(),
>>                               TheSelect->getOperand(0), LLD-
>>> getBasePtr(),
>>                               RLD->getBasePtr());
>> @@ -5235,10 +5235,10 @@
>>        } else {
>>          // Check that the condition doesn't reach either load.  If
>> so, folding
>>          // this will induce a cycle into the DAG.
>> -          if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) &&
>> -              !RLD->isPredecessorOf(TheSelect->getOperand(0).Val) &&
>> -              !LLD->isPredecessorOf(TheSelect->getOperand(1).Val) &&
>> -              !RLD->isPredecessorOf(TheSelect->getOperand(1).Val)) {
>> +          if (!LLD->isPredecessorOf(TheSelect-
>>> getOperand(0).getNode()) &&
>> +              !RLD->isPredecessorOf(TheSelect-
>>> getOperand(0).getNode()) &&
>> +              !LLD->isPredecessorOf(TheSelect-
>>> getOperand(1).getNode()) &&
>> +              !RLD->isPredecessorOf(TheSelect-
>>> getOperand(1).getNode())) {
>>            Addr = DAG.getNode(ISD::SELECT_CC, LLD-
>>> getBasePtr().getValueType(),
>>                             TheSelect->getOperand(0),
>>                             TheSelect->getOperand(1),
>> @@ -5247,7 +5247,7 @@
>>          }
>>        }
>>
>> -        if (Addr.Val) {
>> +        if (Addr.getNode()) {
>>          SDValue Load;
>>          if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
>>            Load = DAG.getLoad(TheSelect->getValueType(0), LLD-
>>> getChain(),
>> @@ -5269,8 +5269,8 @@
>>
>>          // Users of the old loads now use the new load's chain.
>> We know the
>>          // old-load value is dead now.
>> -          CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
>> -          CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
>> +          CombineTo(LHS.getNode(), Load.getValue(0),
>> Load.getValue(1));
>> +          CombineTo(RHS.getNode(), Load.getValue(0),
>> Load.getValue(1));
>>          return true;
>>        }
>>      }
>> @@ -5285,14 +5285,14 @@
>>                                      ISD::CondCode CC, bool
>> NotExtCompare) {
>>
>>  MVT VT = N2.getValueType();
>> -  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
>> -  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
>> -  ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
>> +  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
>> +  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
>> +  ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
>>
>>  // Determine if the condition we're dealing with is constant
>>  SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1,
>> CC, false);
>> -  if (SCC.Val) AddToWorkList(SCC.Val);
>> -  ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
>> +  if (SCC.getNode()) AddToWorkList(SCC.getNode());
>> +  ConstantSDNode *SCCC =
>> dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
>>
>>  // fold select_cc true, x, y -> x
>>  if (SCCC && !SCCC->isNullValue())
>> @@ -5336,20 +5336,20 @@
>>        ShCtV = XType.getSizeInBits()-ShCtV-1;
>>        SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
>>        SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
>> -        AddToWorkList(Shift.Val);
>> +        AddToWorkList(Shift.getNode());
>>        if (XType.bitsGT(AType)) {
>>          Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
>> -          AddToWorkList(Shift.Val);
>> +          AddToWorkList(Shift.getNode());
>>        }
>>        return DAG.getNode(ISD::AND, AType, Shift, N2);
>>      }
>>      SDValue Shift = DAG.getNode(ISD::SRA, XType, N0,
>>
>> DAG.getConstant(XType.getSizeInBits()-1,
>>
>> TLI.getShiftAmountTy()));
>> -      AddToWorkList(Shift.Val);
>> +      AddToWorkList(Shift.getNode());
>>      if (XType.bitsGT(AType)) {
>>        Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
>> -        AddToWorkList(Shift.Val);
>> +        AddToWorkList(Shift.getNode());
>>      }
>>      return DAG.getNode(ISD::AND, AType, Shift, N2);
>>    }
>> @@ -5379,8 +5379,8 @@
>>      SCC  = DAG.getSetCC(MVT::i1, N0, N1, CC);
>>      Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
>>    }
>> -    AddToWorkList(SCC.Val);
>> -    AddToWorkList(Temp.Val);
>> +    AddToWorkList(SCC.getNode());
>> +    AddToWorkList(Temp.getNode());
>>
>>    if (N2C->getAPIntValue() == 1)
>>      return Temp;
>> @@ -5442,8 +5442,8 @@
>>
>> DAG.getConstant(XType.getSizeInBits()-1,
>>
>> TLI.getShiftAmountTy()));
>>    SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
>> -    AddToWorkList(Shift.Val);
>> -    AddToWorkList(Add.Val);
>> +    AddToWorkList(Shift.getNode());
>> +    AddToWorkList(Add.getNode());
>>    return DAG.getNode(ISD::XOR, XType, Add, Shift);
>>  }
>>  // Check to see if this is an integer abs. select_cc setgt X, -1,
>> X, -X ->
>> @@ -5457,8 +5457,8 @@
>>
>> DAG.getConstant(XType.getSizeInBits()-1,
>>
>> TLI.getShiftAmountTy()));
>>        SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
>> -        AddToWorkList(Shift.Val);
>> -        AddToWorkList(Add.Val);
>> +        AddToWorkList(Shift.getNode());
>> +        AddToWorkList(Add.getNode());
>>        return DAG.getNode(ISD::XOR, XType, Add, Shift);
>>      }
>>    }
>> @@ -5612,8 +5612,8 @@
>>    Chains.pop_back();
>>
>>     // Don't bother if we've been before.
>> -    if (Visited.find(Chain.Val) != Visited.end()) continue;
>> -    Visited.insert(Chain.Val);
>> +    if (Visited.find(Chain.getNode()) != Visited.end()) continue;
>> +    Visited.insert(Chain.getNode());
>>
>>    switch (Chain.getOpcode()) {
>>    case ISD::EntryToken:
>> @@ -5627,7 +5627,7 @@
>>      int64_t OpSize;
>>      const Value *OpSrcValue;
>>      int OpSrcValueOffset;
>> -      bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
>> +      bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
>>                                    OpSrcValue, OpSrcValueOffset);
>>
>>      // If chain is alias then stop here.
>> @@ -5639,7 +5639,7 @@
>>        // Look further up the chain.
>>        Chains.push_back(Chain.getOperand(0));
>>        // Clean up old chain.
>> -        AddToWorkList(Chain.Val);
>> +        AddToWorkList(Chain.getNode());
>>      }
>>      break;
>>    }
>> @@ -5652,7 +5652,7 @@
>>      for (unsigned n = Chain.getNumOperands(); n;)
>>        Chains.push_back(Chain.getOperand(--n));
>>      // Eliminate the token factor if we can.
>> -      AddToWorkList(Chain.Val);
>> +      AddToWorkList(Chain.getNode());
>>      break;
>>
>>    default:
>> @@ -5684,7 +5684,7 @@
>>                                   &Aliases[0], Aliases.size());
>>
>>  // Make sure the old chain gets cleaned up.
>> -  if (NewChain != OldChain) AddToWorkList(OldChain.Val);
>> +  if (NewChain != OldChain) AddToWorkList(OldChain.getNode());
>>
>>  return NewChain;
>> }
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -260,7 +260,7 @@
>>    break;
>>  }
>>  }
>> -  return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
>> +  return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
>> }
>>
>> SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
>> @@ -350,7 +350,7 @@
>>
>>  assert(Node->getOperand(0).getValueType() == MVT::Other &&
>>         "Node doesn't have a token chain argument!");
>> -  return FindCallStartFromCallEnd(Node->getOperand(0).Val);
>> +  return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
>> }
>>
>> /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N,
>> looking to
>> @@ -387,7 +387,7 @@
>>  bool OperandsLeadToDest = false;
>>  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
>>    OperandsLeadToDest |=     // If an operand leads to Dest, so do
>> we.
>> -      LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest,
>> NodesLeadingTo);
>> +      LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(),
>> Dest, NodesLeadingTo);
>>
>>  if (OperandsLeadToDest) {
>>    NodesLeadingTo.insert(N);
>> @@ -667,7 +667,7 @@
>>  MVT VT = Op.getValueType();
>>  assert(isTypeLegal(VT) &&
>>         "Caller should expand or promote operands that are not
>> legal!");
>> -  assert(Op.Val->getNumValues() == 1 &&
>> +  assert(Op.getNode()->getNumValues() == 1 &&
>>         "Can't unroll a vector with multiple results!");
>>  unsigned NE = VT.getVectorNumElements();
>>  MVT EltVT = VT.getVectorElementType();
>> @@ -733,7 +733,7 @@
>>  MVT PtrVT = TLI.getPointerTy();
>>  SDValue StackPtr = DAG.CreateStackTemporary(VT);
>>
>> -  int SPFI = cast<FrameIndexSDNode>(StackPtr.Val)->getIndex();
>> +  int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
>>
>>  // Store the vector.
>>  SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
>> @@ -764,7 +764,7 @@
>>
>>  assert(isTypeLegal(Op.getValueType()) &&
>>         "Caller should expand or promote operands that are not
>> legal!");
>> -  SDNode *Node = Op.Val;
>> +  SDNode *Node = Op.getNode();
>>
>>  // If this operation defines any values that cannot be represented
>> in a
>>  // register on this target, make sure to expand or promote them.
>> @@ -839,7 +839,7 @@
>>    default: assert(0 && "This action is not supported yet!");
>>    case TargetLowering::Custom:
>>      Tmp1 = TLI.LowerOperation(Op, DAG);
>> -      if (Tmp1.Val) Result = Tmp1;
>> +      if (Tmp1.getNode()) Result = Tmp1;
>>      // FALLTHROUGH if the target doesn't want to lower this op
>> after all.
>>    case TargetLowering::Legal:
>>      break;
>> @@ -850,7 +850,7 @@
>>    // The only option for these nodes is to custom lower them.  If
>> the target
>>    // does not custom lower them, then return zero.
>>    Tmp1 = TLI.LowerOperation(Op, DAG);
>> -    if (Tmp1.Val)
>> +    if (Tmp1.getNode())
>>      Result = Tmp1;
>>    else
>>      Result = DAG.getConstant(0, TLI.getPointerTy());
>> @@ -861,7 +861,7 @@
>>    default: assert(0 && "This action is not supported yet!");
>>    case TargetLowering::Custom:
>>      Result = TLI.LowerOperation(Op, DAG);
>> -      if (Result.Val) break;
>> +      if (Result.getNode()) break;
>>      // Fall Thru
>>    case TargetLowering::Legal:
>>      Result = DAG.getConstant(0, VT);
>> @@ -881,7 +881,7 @@
>>      break;
>>    case TargetLowering::Custom:
>>      Result = TLI.LowerOperation(Op, DAG);
>> -      if (Result.Val) break;
>> +      if (Result.getNode()) break;
>>      // Fall Thru
>>    case TargetLowering::Legal: {
>>      SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
>> @@ -890,9 +890,9 @@
>>    }
>>    }
>>    }
>> -    if (Result.Val->getNumValues() == 1) break;
>> +    if (Result.getNode()->getNumValues() == 1) break;
>>
>> -    assert(Result.Val->getNumValues() == 2 &&
>> +    assert(Result.getNode()->getNumValues() == 2 &&
>>           "Cannot return more than two values!");
>>
>>    // Since we produced two values, make sure to remember that we
>> @@ -915,7 +915,7 @@
>>      break;
>>    case TargetLowering::Custom:
>>      Result = TLI.LowerOperation(Op, DAG);
>> -      if (Result.Val) break;
>> +      if (Result.getNode()) break;
>>      // Fall Thru
>>    case TargetLowering::Legal: {
>>      SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
>> @@ -924,9 +924,9 @@
>>    }
>>    }
>>    }
>> -    if (Result.Val->getNumValues() == 1) break;
>> +    if (Result.getNode()->getNumValues() == 1) break;
>>
>> -    assert(Result.Val->getNumValues() == 2 &&
>> +    assert(Result.getNode()->getNumValues() == 2 &&
>>           "Cannot return more than two values!");
>>
>>    // Since we produced two values, make sure to remember that we
>> @@ -943,7 +943,7 @@
>>    default: assert(0 && "This action is not supported at all!");
>>    case TargetLowering::Custom:
>>      Result = TLI.LowerOperation(Op, DAG);
>> -      if (Result.Val) break;
>> +      if (Result.getNode()) break;
>>      // Fall Thru
>>    case TargetLowering::Legal:
>>      // Target does not know, how to lower this, lower to noop
>> @@ -1012,13 +1012,13 @@
>>    if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
>>        TargetLowering::Custom) {
>>      Tmp3 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp3.Val) Result = Tmp3;
>> +      if (Tmp3.getNode()) Result = Tmp3;
>>    }
>>
>> -    if (Result.Val->getNumValues() == 1) break;
>> +    if (Result.getNode()->getNumValues() == 1) break;
>>
>>    // Must have return value and chain result.
>> -    assert(Result.Val->getNumValues() == 2 &&
>> +    assert(Result.getNode()->getNumValues() == 2 &&
>>           "Cannot return more than two values!");
>>
>>    // Since loads produce two values, make sure to remember that we
>> @@ -1261,7 +1261,7 @@
>>      Result = TLI.LowerOperation(Result, DAG);
>>      break;
>>    case TargetLowering::Expand:
>> -      Result = SDValue(TLI.ReplaceNodeResults(Op.Val, DAG),0);
>> +      Result = SDValue(TLI.ReplaceNodeResults(Op.getNode(), DAG),0);
>>      break;
>>    case TargetLowering::Legal:
>>      break;
>> @@ -1280,7 +1280,7 @@
>>
>>    if (opAction == TargetLowering::Custom) {
>>      Tmp1 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp1.Val)
>> +      if (Tmp1.getNode())
>>        Result = Tmp1;
>>    }
>>    break;
>> @@ -1298,7 +1298,7 @@
>>      break;
>>    case TargetLowering::Custom:
>>      Tmp3 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp3.Val) {
>> +      if (Tmp3.getNode()) {
>>        Result = Tmp3;
>>        break;
>>      }
>> @@ -1344,27 +1344,27 @@
>>  case ISD::CALL:
>>    // The only option for this is to custom lower it.
>>    Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
>> -    assert(Tmp3.Val && "Target didn't custom lower this node!");
>> +    assert(Tmp3.getNode() && "Target didn't custom lower this
>> node!");
>>    // A call within a calling sequence must be legalized to something
>>    // other than the normal CALLSEQ_END.  Violating this gets
>> Legalize
>>    // into an infinite loop.
>>    assert ((!IsLegalizingCall ||
>>             Node->getOpcode() != ISD::CALL ||
>> -             Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) &&
>> +             Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
>>            "Nested CALLSEQ_START..CALLSEQ_END not supported.");
>>
>>    // The number of incoming and outgoing values should match;
>> unless the final
>>    // outgoing value is a flag.
>> -    assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues()  
>> ||
>> -            (Tmp3.Val->getNumValues() == Result.Val->getNumValues()
>> + 1 &&
>> -             Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
>> +    assert((Tmp3.getNode()->getNumValues() == Result.getNode()-
>>> getNumValues() ||
>> +            (Tmp3.getNode()->getNumValues() == Result.getNode()-
>>> getNumValues() + 1 &&
>> +             Tmp3.getNode()->getValueType(Tmp3.getNode()-
>>> getNumValues() - 1) ==
>>               MVT::Flag)) &&
>>           "Lowering call/formal_arguments produced unexpected #
>> results!");
>>
>>    // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values,
>> make sure to
>>    // remember that we legalized all of them, so it doesn't get
>> relegalized.
>> -    for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; + 
>> +i) {
>> -      if (Tmp3.Val->getValueType(i) == MVT::Flag)
>> +    for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i !=
>> e; ++i) {
>> +      if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
>>        continue;
>>      Tmp1 = LegalizeOp(Tmp3.getValue(i));
>>      if (Op.getResNo() == i)
>> @@ -1394,13 +1394,13 @@
>>    default: assert(0 && "This action is not supported yet!");
>>    case TargetLowering::Custom:
>>      Tmp3 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp3.Val) {
>> +      if (Tmp3.getNode()) {
>>        Result = Tmp3;
>>        break;
>>      }
>>      // FALLTHROUGH
>>    case TargetLowering::Expand:
>> -      Result = ExpandBUILD_VECTOR(Result.Val);
>> +      Result = ExpandBUILD_VECTOR(Result.getNode());
>>      break;
>>    }
>>    break;
>> @@ -1425,7 +1425,7 @@
>>      break;
>>    case TargetLowering::Custom:
>>      Tmp4 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp4.Val) {
>> +      if (Tmp4.getNode()) {
>>        Result = Tmp4;
>>        break;
>>      }
>> @@ -1485,7 +1485,7 @@
>>      break;
>>    case TargetLowering::Custom:
>>      Tmp3 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp3.Val) {
>> +      if (Tmp3.getNode()) {
>>        Result = Tmp3;
>>        break;
>>      }
>> @@ -1509,7 +1509,7 @@
>>      break;
>>    case TargetLowering::Custom:
>>      Tmp3 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp3.Val) {
>> +      if (Tmp3.getNode()) {
>>        Result = Tmp3;
>>        break;
>>      }
>> @@ -1550,7 +1550,7 @@
>>
>>      // Convert the shuffle mask to the right # elements.
>>      Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
>> -      assert(Tmp3.Val && "Shuffle not legal?");
>> +      assert(Tmp3.getNode() && "Shuffle not legal?");
>>      Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2,
>> Tmp3);
>>      Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
>>      break;
>> @@ -1580,7 +1580,7 @@
>>    // are inserted *before* the CALLSEQ_START.
>>    {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
>>    for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
>> -      LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
>> +      LegalizeAllNodesNotLeadingTo(CallEnd-
>>> getOperand(i).getNode(), Node,
>>                                   NodesLeadingTo);
>>    }
>>
>> @@ -1624,7 +1624,7 @@
>>  case ISD::CALLSEQ_END:
>>    // If the CALLSEQ_START node hasn't been legalized first,
>> legalize it.  This
>>    // will cause this node to be legalized as well as handling
>> libcalls right.
>> -    if (LastCALLSEQ_END.Val != Node) {
>> +    if (LastCALLSEQ_END.getNode() != Node) {
>>      LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
>>      DenseMap<SDValue, SDValue>::iterator I =
>> LegalizedNodes.find(Op);
>>      assert(I != LegalizedNodes.end() &&
>> @@ -1708,7 +1708,7 @@
>>    }
>>    case TargetLowering::Custom:
>>      Tmp3 = TLI.LowerOperation(Tmp1, DAG);
>> -      if (Tmp3.Val) {
>> +      if (Tmp3.getNode()) {
>>        Tmp1 = LegalizeOp(Tmp3);
>>        Tmp2 = LegalizeOp(Tmp3.getValue(1));
>>      }
>> @@ -1797,7 +1797,7 @@
>>    case TargetLowering::Legal: break;
>>    case TargetLowering::Custom:
>>      Tmp1 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp1.Val) Result = Tmp1;
>> +      if (Tmp1.getNode()) Result = Tmp1;
>>      break;
>>    case TargetLowering::Expand: {
>>      SDValue Chain = Result.getOperand(0);
>> @@ -1866,7 +1866,7 @@
>>    case TargetLowering::Legal: break;
>>    case TargetLowering::Custom:
>>      Tmp1 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp1.Val) Result = Tmp1;
>> +      if (Tmp1.getNode()) Result = Tmp1;
>>      break;
>>    case TargetLowering::Expand:
>>      // Expand brcond's setcc into its constituent parts and create
>> a BR_CC
>> @@ -1899,7 +1899,7 @@
>>    // If we didn't get both a LHS and RHS back from
>> LegalizeSetCCOperands,
>>    // the LHS is a legal SETCC itself.  In this case, we need to
>> compare
>>    // the result against zero to select between true and false
>> values.
>> -    if (Tmp3.Val == 0) {
>> +    if (Tmp3.getNode() == 0) {
>>      Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
>>      Tmp4 = DAG.getCondCode(ISD::SETNE);
>>    }
>> @@ -1912,7 +1912,7 @@
>>    case TargetLowering::Legal: break;
>>    case TargetLowering::Custom:
>>      Tmp4 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp4.Val) Result = Tmp4;
>> +      if (Tmp4.getNode()) Result = Tmp4;
>>      break;
>>    }
>>    break;
>> @@ -1937,7 +1937,7 @@
>>          unsigned ABIAlignment = TLI.getTargetData()->
>>            getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
>>          if (LD->getAlignment() < ABIAlignment){
>> -            Result =
>> ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
>> +            Result =
>> ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
>>                                         TLI);
>>            Tmp3 = Result.getOperand(0);
>>            Tmp4 = Result.getOperand(1);
>> @@ -1948,7 +1948,7 @@
>>        break;
>>      case TargetLowering::Custom:
>>        Tmp1 = TLI.LowerOperation(Tmp3, DAG);
>> -        if (Tmp1.Val) {
>> +        if (Tmp1.getNode()) {
>>          Tmp3 = LegalizeOp(Tmp1);
>>          Tmp4 = LegalizeOp(Tmp1.getValue(1));
>>        }
>> @@ -2105,7 +2105,7 @@
>>
>>          if (isCustom) {
>>            Tmp3 = TLI.LowerOperation(Result, DAG);
>> -            if (Tmp3.Val) {
>> +            if (Tmp3.getNode()) {
>>              Tmp1 = LegalizeOp(Tmp3);
>>              Tmp2 = LegalizeOp(Tmp3.getValue(1));
>>            }
>> @@ -2116,7 +2116,7 @@
>>              unsigned ABIAlignment = TLI.getTargetData()->
>>                getABITypeAlignment(LD-
>>> getMemoryVT().getTypeForMVT());
>>              if (LD->getAlignment() < ABIAlignment){
>> -                Result =
>> ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
>> +                Result =
>> ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
>>                                             TLI);
>>                Tmp1 = Result.getOperand(0);
>>                Tmp2 = Result.getOperand(1);
>> @@ -2244,13 +2244,13 @@
>>          if (TLI.isBigEndian())
>>            std::swap(Lo, Hi);
>>
>> -          if (Hi.Val)
>> +          if (Hi.getNode())
>>            Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo,
>> Tmp3, Hi,Tmp3);
>>          else
>>            Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo,
>> Tmp3);
>>          Result = LegalizeOp(Result);
>>        } else {
>> -          SDNode *InVal = Tmp2.Val;
>> +          SDNode *InVal = Tmp2.getNode();
>>          int InIx = Tmp2.getResNo();
>>          unsigned NumElems = InVal-
>>> getValueType(InIx).getVectorNumElements();
>>          MVT EVT = InVal->getValueType(InIx).getVectorElementType();
>> @@ -2310,7 +2310,7 @@
>>          ExpandOp(Node->getOperand(i), Lo, Hi);
>>          NewValues.push_back(Lo);
>>          NewValues.push_back(Node->getOperand(i+1));
>> -          if (Hi.Val) {
>> +          if (Hi.getNode()) {
>>            NewValues.push_back(Hi);
>>            NewValues.push_back(Node->getOperand(i+1));
>>          }
>> @@ -2335,7 +2335,7 @@
>>      case TargetLowering::Legal: break;
>>      case TargetLowering::Custom:
>>        Tmp1 = TLI.LowerOperation(Result, DAG);
>> -        if (Tmp1.Val) Result = Tmp1;
>> +        if (Tmp1.getNode()) Result = Tmp1;
>>        break;
>>      }
>>    }
>> @@ -2411,13 +2411,13 @@
>>            unsigned ABIAlignment = TLI.getTargetData()->
>>              getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
>>            if (ST->getAlignment() < ABIAlignment)
>> -              Result =
>> ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
>> +              Result =
>> ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
>>                                            TLI);
>>          }
>>          break;
>>        case TargetLowering::Custom:
>>          Tmp1 = TLI.LowerOperation(Result, DAG);
>> -          if (Tmp1.Val) Result = Tmp1;
>> +          if (Tmp1.getNode()) Result = Tmp1;
>>          break;
>>        case TargetLowering::Promote:
>>          assert(VT.isVector() && "Unknown legal promote case!");
>> @@ -2446,7 +2446,7 @@
>>        // the product of the element size in bytes, and the number
>> of elements
>>        // in the high half of the vector.
>>        if (ST->getValue().getValueType().isVector()) {
>> -          SDNode *InVal = ST->getValue().Val;
>> +          SDNode *InVal = ST->getValue().getNode();
>>          int InIx = ST->getValue().getResNo();
>>          MVT InVT = InVal->getValueType(InIx);
>>          unsigned NumElems = InVT.getVectorNumElements();
>> @@ -2473,12 +2473,12 @@
>>            break;
>>          } else {
>>            SplitVectorOp(ST->getValue(), Lo, Hi);
>> -            IncrementSize = Lo.Val-
>>> getValueType(0).getVectorNumElements() *
>> +            IncrementSize = Lo.getNode()-
>>> getValueType(0).getVectorNumElements() *
>>                            EVT.getSizeInBits()/8;
>>          }
>>        } else {
>>          ExpandOp(ST->getValue(), Lo, Hi);
>> -          IncrementSize = Hi.Val ?
>> Hi.getValueType().getSizeInBits()/8 : 0;
>> +          IncrementSize = Hi.getNode() ?
>> Hi.getValueType().getSizeInBits()/8 : 0;
>>
>>          if (TLI.isBigEndian())
>>            std::swap(Lo, Hi);
>> @@ -2487,7 +2487,7 @@
>>        Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
>>                          SVOffset, isVolatile, Alignment);
>>
>> -        if (Hi.Val == NULL) {
>> +        if (Hi.getNode() == NULL) {
>>          // Must be int <-> float one-to-one expansion.
>>          Result = Lo;
>>          break;
>> @@ -2598,7 +2598,7 @@
>>            unsigned ABIAlignment = TLI.getTargetData()->
>>              getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
>>            if (ST->getAlignment() < ABIAlignment)
>> -              Result =
>> ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
>> +              Result =
>> ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
>>                                            TLI);
>>          }
>>          break;
>> @@ -2632,7 +2632,7 @@
>>    case TargetLowering::Legal: break;
>>    case TargetLowering::Custom:
>>      Tmp3 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp3.Val) {
>> +      if (Tmp3.getNode()) {
>>        Tmp1 = LegalizeOp(Tmp3);
>>        Tmp2 = LegalizeOp(Tmp3.getValue(1));
>>      }
>> @@ -2667,7 +2667,7 @@
>>    case TargetLowering::Legal: break;
>>    case TargetLowering::Custom:
>>      Tmp1 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp1.Val) Result = Tmp1;
>> +      if (Tmp1.getNode()) Result = Tmp1;
>>      break;
>>    case TargetLowering::Expand:
>>      // Expand to CopyToReg if the target set
>> @@ -2730,7 +2730,7 @@
>>    case TargetLowering::Legal: break;
>>    case TargetLowering::Custom: {
>>      Tmp1 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp1.Val) Result = Tmp1;
>> +      if (Tmp1.getNode()) Result = Tmp1;
>>      break;
>>    }
>>    case TargetLowering::Expand:
>> @@ -2784,7 +2784,7 @@
>>    // If we didn't get both a LHS and RHS back from
>> LegalizeSetCCOperands,
>>    // the LHS is a legal SETCC itself.  In this case, we need to
>> compare
>>    // the result against zero to select between true and false
>> values.
>> -    if (Tmp2.Val == 0) {
>> +    if (Tmp2.getNode() == 0) {
>>      Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
>>      CC = DAG.getCondCode(ISD::SETNE);
>>    }
>> @@ -2796,7 +2796,7 @@
>>    case TargetLowering::Legal: break;
>>    case TargetLowering::Custom:
>>      Tmp1 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp1.Val) Result = Tmp1;
>> +      if (Tmp1.getNode()) Result = Tmp1;
>>      break;
>>    }
>>    break;
>> @@ -2810,7 +2810,7 @@
>>    // If we had to Expand the SetCC operands into a SELECT node,
>> then it may
>>    // not always be possible to return a true LHS & RHS.  In this
>> case, just
>>    // return the value we legalized, returned in the LHS
>> -    if (Tmp2.Val == 0) {
>> +    if (Tmp2.getNode() == 0) {
>>      Result = Tmp1;
>>      break;
>>    }
>> @@ -2824,7 +2824,7 @@
>>      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
>>      if (isCustom) {
>>        Tmp4 = TLI.LowerOperation(Result, DAG);
>> -        if (Tmp4.Val) Result = Tmp4;
>> +        if (Tmp4.getNode()) Result = Tmp4;
>>      }
>>      break;
>>    case TargetLowering::Promote: {
>> @@ -2882,7 +2882,7 @@
>>    case TargetLowering::Legal: break;
>>    case TargetLowering::Custom:
>>      Tmp1 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp1.Val) Result = Tmp1;
>> +      if (Tmp1.getNode()) Result = Tmp1;
>>      break;
>>    }
>>    break;
>> @@ -2906,7 +2906,7 @@
>>    case TargetLowering::Legal: break;
>>    case TargetLowering::Custom:
>>      Tmp1 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp1.Val) {
>> +      if (Tmp1.getNode()) {
>>        SDValue Tmp2, RetVal(0, 0);
>>        for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
>>          Tmp2 = LegalizeOp(Tmp1.getValue(i));
>> @@ -2914,7 +2914,7 @@
>>          if (i == Op.getResNo())
>>            RetVal = Tmp2;
>>        }
>> -        assert(RetVal.Val && "Illegal result number");
>> +        assert(RetVal.getNode() && "Illegal result number");
>>        return RetVal;
>>      }
>>      break;
>> @@ -2974,7 +2974,7 @@
>>    case TargetLowering::Legal: break;
>>    case TargetLowering::Custom:
>>      Tmp1 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp1.Val) {
>> +      if (Tmp1.getNode()) {
>>        Result = Tmp1;
>>        break;
>>      }
>> @@ -3004,28 +3004,28 @@
>>          OpToUse = ISD::UMUL_LOHI;
>>        }
>>        if (OpToUse) {
>> -          Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1,
>> Tmp2).Val, 0);
>> +          Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1,
>> Tmp2).getNode(), 0);
>>          break;
>>        }
>>      }
>>      if (Node->getOpcode() == ISD::MULHS &&
>>          TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
>> -        Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1,
>> Tmp2).Val, 1);
>> +        Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1,
>> Tmp2).getNode(), 1);
>>        break;
>>      }
>>      if (Node->getOpcode() == ISD::MULHU &&
>>          TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
>> -        Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1,
>> Tmp2).Val, 1);
>> +        Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1,
>> Tmp2).getNode(), 1);
>>        break;
>>      }
>>      if (Node->getOpcode() == ISD::SDIV &&
>>          TLI.isOperationLegal(ISD::SDIVREM, VT)) {
>> -        Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1,
>> Tmp2).Val, 0);
>> +        Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1,
>> Tmp2).getNode(), 0);
>>        break;
>>      }
>>      if (Node->getOpcode() == ISD::UDIV &&
>>          TLI.isOperationLegal(ISD::UDIVREM, VT)) {
>> -        Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1,
>> Tmp2).Val, 0);
>> +        Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1,
>> Tmp2).getNode(), 0);
>>        break;
>>      }
>>
>> @@ -3113,7 +3113,7 @@
>>    default: assert(0 && "Operation not supported");
>>    case TargetLowering::Custom:
>>      Tmp1 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp1.Val) Result = Tmp1;
>> +      if (Tmp1.getNode()) Result = Tmp1;
>>      break;
>>    case TargetLowering::Legal: break;
>>    case TargetLowering::Expand: {
>> @@ -3216,7 +3216,7 @@
>>      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
>>      if (isCustom) {
>>        Tmp1 = TLI.LowerOperation(Result, DAG);
>> -        if (Tmp1.Val) Result = Tmp1;
>> +        if (Tmp1.getNode()) Result = Tmp1;
>>      }
>>      break;
>>    case TargetLowering::Expand: {
>> @@ -3228,12 +3228,12 @@
>>      SDVTList VTs = DAG.getVTList(VT, VT);
>>      if (Node->getOpcode() == ISD::SREM &&
>>          TLI.isOperationLegal(ISD::SDIVREM, VT)) {
>> -        Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1,
>> Tmp2).Val, 1);
>> +        Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1,
>> Tmp2).getNode(), 1);
>>        break;
>>      }
>>      if (Node->getOpcode() == ISD::UREM &&
>>          TLI.isOperationLegal(ISD::UDIVREM, VT)) {
>> -        Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1,
>> Tmp2).Val, 1);
>> +        Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1,
>> Tmp2).getNode(), 1);
>>        break;
>>      }
>>
>> @@ -3288,7 +3288,7 @@
>>
>>      if (isCustom) {
>>        Tmp2 = TLI.LowerOperation(Result, DAG);
>> -        if (Tmp2.Val) {
>> +        if (Tmp2.getNode()) {
>>          Result = LegalizeOp(Tmp2);
>>          Tmp1 = LegalizeOp(Tmp2.getValue(1));
>>        }
>> @@ -3332,7 +3332,7 @@
>>                                      Node->getOperand(3), Node-
>>> getOperand(4));
>>      if (isCustom) {
>>        Tmp1 = TLI.LowerOperation(Result, DAG);
>> -        if (Tmp1.Val) Result = Tmp1;
>> +        if (Tmp1.getNode()) Result = Tmp1;
>>      }
>>      break;
>>    case TargetLowering::Expand:
>> @@ -3359,7 +3359,7 @@
>>      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node-
>>> getOperand(2));
>>      if (isCustom) {
>>        Tmp1 = TLI.LowerOperation(Tmp1, DAG);
>> -        if (Tmp1.Val) Result = Tmp1;
>> +        if (Tmp1.getNode()) Result = Tmp1;
>>      }
>>      break;
>>    case TargetLowering::Expand:
>> @@ -3379,7 +3379,7 @@
>>    case TargetLowering::Legal: break;
>>    case TargetLowering::Custom:
>>      Tmp1 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp1.Val) Result = Tmp1;
>> +      if (Tmp1.getNode()) Result = Tmp1;
>>      break;
>>    }
>>    break;
>> @@ -3397,7 +3397,7 @@
>>      break;
>>    case TargetLowering::Custom:
>>      Tmp1 = TLI.LowerOperation(Result, DAG);
>> -      if (Tmp1.Val) Result = Tmp1;
>> +      if (Tmp1.getNode()) Result = Tmp1;
>>      break;
>>    case TargetLowering::Promote:
>>      assert(0 && "Do not know how to promote ROTL/ROTR");
>> @@ -3444,7 +3444,7 @@
>>      if (TLI.getOperationAction(Node->getOpcode(), Node-
>>> getValueType(0)) ==
>>          TargetLowering::Custom) {
>>        Tmp1 = TLI.LowerOperation(Result, DAG);
>> -        if (Tmp1.Val) {
>> +        if (Tmp1.getNode()) {
>>          Result = Tmp1;
>>        }
>>      }
>> @@ -3505,7 +3505,7 @@
>>      Result = DAG.UpdateNodeOperands(Result, Tmp1);
>>      if (isCustom) {
>>        Tmp1 = TLI.LowerOperation(Result, DAG);
>> -        if (Tmp1.Val) Result = Tmp1;
>> +        if (Tmp1.getNode()) Result = Tmp1;
>>      }
>>      break;
>>    case TargetLowering::Expand:
>> @@ -3609,7 +3609,7 @@
>>    } else if (Op.getOperand(0).getValueType().isVector()) {
>>      // The input has to be a vector type, we have to either
>> scalarize it, pack
>>      // it, or convert it based on whether the input vector type is
>> legal.
>> -      SDNode *InVal = Node->getOperand(0).Val;
>> +      SDNode *InVal = Node->getOperand(0).getNode();
>>      int InIx = Node->getOperand(0).getResNo();
>>      unsigned NumElems = InVal-
>>> getValueType(InIx).getVectorNumElements();
>>      MVT EVT = InVal->getValueType(InIx).getVectorElementType();
>> @@ -3690,7 +3690,7 @@
>>        Result = DAG.UpdateNodeOperands(Result, Tmp1);
>>        if (isCustom) {
>>          Tmp1 = TLI.LowerOperation(Result, DAG);
>> -          if (Tmp1.Val) Result = Tmp1;
>> +          if (Tmp1.getNode()) Result = Tmp1;
>>        }
>>        break;
>>      case TargetLowering::Promote:
>> @@ -3832,7 +3832,7 @@
>>      if (TLI.getOperationAction(Node->getOpcode(), Node-
>>> getValueType(0)) ==
>>          TargetLowering::Custom) {
>>        Tmp1 = TLI.LowerOperation(Result, DAG);
>> -        if (Tmp1.Val) Result = Tmp1;
>> +        if (Tmp1.getNode()) Result = Tmp1;
>>      }
>>      break;
>>    case Promote:
>> @@ -3904,7 +3904,7 @@
>>    Result = DAG.UpdateNodeOperands(Result, Ops, 6);
>>    // The only option for this node is to custom lower it.
>>    Result = TLI.LowerOperation(Result, DAG);
>> -    assert(Result.Val && "Should always custom lower!");
>> +    assert(Result.getNode() && "Should always custom lower!");
>>
>>    // Since trampoline produces two values, make sure to remember
>> that we
>>    // legalized both of them.
>> @@ -3920,7 +3920,7 @@
>>    default: assert(0 && "This action not supported for this op
>> yet!");
>>    case TargetLowering::Custom:
>>      Result = TLI.LowerOperation(Op, DAG);
>> -      if (Result.Val) break;
>> +      if (Result.getNode()) break;
>>      // Fall Thru
>>    case TargetLowering::Legal:
>>      // If this operation is not supported, lower it to constant 1
>> @@ -3939,7 +3939,7 @@
>>      break;
>>    case TargetLowering::Custom:
>>      Result = TLI.LowerOperation(Op, DAG);
>> -      if (Result.Val) break;
>> +      if (Result.getNode()) break;
>>      // Fall Thru
>>    case TargetLowering::Expand:
>>      // If this operation is not supported, lower it to 'abort()'
>> call
>> @@ -3984,7 +3984,7 @@
>>
>>  SDValue Tmp1, Tmp2, Tmp3;
>>  SDValue Result;
>> -  SDNode *Node = Op.Val;
>> +  SDNode *Node = Op.getNode();
>>
>>  DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
>>  if (I != PromotedNodes.end()) return I->second;
>> @@ -4461,7 +4461,7 @@
>>    break;
>>  }
>>
>> -  assert(Result.Val && "Didn't set a result!");
>> +  assert(Result.getNode() && "Didn't set a result!");
>>
>>  // Make sure the result is itself legal.
>>  Result = LegalizeOp(Result);
>> @@ -4491,7 +4491,7 @@
>>    Vec = LegalizeOp(Vec);
>>    Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
>>    SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
>> -    if (Tmp3.Val)
>> +    if (Tmp3.getNode())
>>      return Tmp3;
>>    break;
>>  }
>> @@ -4697,14 +4697,14 @@
>>
>>      SDValue Dummy;
>>      SDValue Ops[2] = { LHS, RHS };
>> -      Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).Val,
>> +      Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops,  
>> 2).getNode(),
>>                           false /*sign irrelevant*/, Dummy);
>>      Tmp2 = DAG.getConstant(0, MVT::i32);
>>      CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
>>      if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
>>        Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1),
>> Tmp1, Tmp2,
>>                           CC);
>> -        LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).Val,
>> +        LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops,
>> 2).getNode(),
>>                            false /*sign irrelevant*/, Dummy);
>>        Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS),
>> LHS, Tmp2,
>>                           DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
>> @@ -4791,16 +4791,16 @@
>>      TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false,
>> true, NULL);
>>      Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo,
>> RHSLo,
>>                               LowCC, false, DagCombineInfo);
>> -      if (!Tmp1.Val)
>> +      if (!Tmp1.getNode())
>>        Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo,
>> RHSLo, LowCC);
>>      Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi,
>> RHSHi,
>>                               CCCode, false, DagCombineInfo);
>> -      if (!Tmp2.Val)
>> +      if (!Tmp2.getNode())
>>        Tmp2 = DAG.getNode(ISD::SETCC,
>> TLI.getSetCCResultType(LHSHi), LHSHi,
>>                           RHSHi,CC);
>>
>> -      ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
>> -      ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
>> +      ConstantSDNode *Tmp1C =
>> dyn_cast<ConstantSDNode>(Tmp1.getNode());
>> +      ConstantSDNode *Tmp2C =
>> dyn_cast<ConstantSDNode>(Tmp2.getNode());
>>      if ((Tmp1C && Tmp1C->isNullValue()) ||
>>          (Tmp2C && Tmp2C->isNullValue() &&
>>           (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
>> @@ -4816,7 +4816,7 @@
>>      } else {
>>        Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi),
>> LHSHi, RHSHi,
>>                                   ISD::SETEQ, false, DagCombineInfo);
>> -        if (!Result.Val)
>> +        if (!Result.getNode())
>>          Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi,
>> RHSHi,
>>                              ISD::SETEQ);
>>        Result = LegalizeOp(DAG.getNode(ISD::SELECT,
>> Tmp1.getValueType(),
>> @@ -4958,7 +4958,7 @@
>>                       PseudoSourceValue::getConstantPool(), 0);
>>  }
>>
>> -  if (SplatValue.Val) {   // Splat of one value?
>> +  if (SplatValue.getNode()) {   // Splat of one value?
>>    // Build the shuffle constant vector: <0, 0, 0, 0>
>>    MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
>>    SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
>> @@ -5095,7 +5095,7 @@
>>  unsigned NVTBits = NVT.getSizeInBits();
>>
>>  // Handle the case when Amt is an immediate.
>> -  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
>> +  if (ConstantSDNode *CN =  
>> dyn_cast<ConstantSDNode>(Amt.getNode())) {
>>    unsigned Cst = CN->getValue();
>>    // Expand the incoming operand to be shifted, so that we have
>> its parts
>>    SDValue InL, InH;
>> @@ -5292,14 +5292,14 @@
>>      // FALLTHROUGH
>>    case TargetLowering::Legal:
>>      Tmp1 = LegalizeOp(Op);
>> -      if (Result.Val)
>> +      if (Result.getNode())
>>        Result = DAG.UpdateNodeOperands(Result, Tmp1);
>>      else
>>        Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP :
>> ISD::UINT_TO_FP,
>>                             DestTy, Tmp1);
>>      if (isCustom) {
>>        Tmp1 = TLI.LowerOperation(Result, DAG);
>> -        if (Tmp1.Val) Result = Tmp1;
>> +        if (Tmp1.getNode()) Result = Tmp1;
>>      }
>>      break;
>>    case TargetLowering::Expand:
>> @@ -5322,7 +5322,7 @@
>>      Tmp1 = DAG.getZeroExtendInReg(Tmp1,
>>                                    Op.getValueType());
>>    }
>> -    if (Result.Val)
>> +    if (Result.getNode())
>>      Result = DAG.UpdateNodeOperands(Result, Tmp1);
>>    else
>>      Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP :
>> ISD::UINT_TO_FP,
>> @@ -5427,7 +5427,7 @@
>>  case TargetLowering::Custom: {
>>    SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP,
>> DestTy,
>>                                                  Source), DAG);
>> -    if (NV.Val)
>> +    if (NV.getNode())
>>      return LegalizeOp(NV);
>>    break;   // The target decided this was legal after all
>>  }
>> @@ -5448,8 +5448,8 @@
>>
>>  Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
>>  SDValue HiPart;
>> -  SDValue Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart);
>> -  if (Result.getValueType() != DestTy && HiPart.Val)
>> +  SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned,
>> HiPart);
>> +  if (Result.getValueType() != DestTy && HiPart.getNode())
>>    Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
>>  return Result;
>> }
>> @@ -5665,8 +5665,8 @@
>>  // the target lowering hooks to expand it.  Just keep the low part
>> of the
>>  // expanded operation, we know that we're truncating anyway.
>>  if (getTypeAction(NewOutTy) == Expand) {
>> -    Operation = SDValue(TLI.ReplaceNodeResults(Operation.Val, DAG),
>> 0);
>> -    assert(Operation.Val && "Didn't return anything");
>> +    Operation = SDValue(TLI.ReplaceNodeResults(Operation.getNode(),
>> DAG), 0);
>> +    assert(Operation.getNode() && "Didn't return anything");
>>  }
>>
>>  // Truncate the result of the extended FP_TO_*INT operation to the
>> desired
>> @@ -5794,7 +5794,7 @@
>> void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue
>> &Hi){
>>  MVT VT = Op.getValueType();
>>  MVT NVT = TLI.getTypeToTransformTo(VT);
>> -  SDNode *Node = Op.Val;
>> +  SDNode *Node = Op.getNode();
>>  assert(getTypeAction(VT) == Expand && "Not an expanded type!");
>>  assert(((NVT.isInteger() && NVT.bitsLT(VT)) ||
>> VT.isFloatingPoint() ||
>>         VT.isVector()) && "Cannot expand to FP value or to larger
>> int value!");
>> @@ -5820,9 +5820,9 @@
>>      Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
>>      SDValue Result = TLI.LowerOperation(
>>        DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)),
>> DAG);
>> -      assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
>> -      Lo = Result.Val->getOperand(0);
>> -      Hi = Result.Val->getOperand(1);
>> +      assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
>> +      Lo = Result.getNode()->getOperand(0);
>> +      Hi = Result.getNode()->getOperand(1);
>>      break;
>>    }
>>    // fall through
>> @@ -6145,7 +6145,7 @@
>>    }
>>
>>    // Turn this into a load/store pair by default.
>> -    if (Tmp.Val == 0)
>> +    if (Tmp.getNode() == 0)
>>      Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
>>
>>    ExpandOp(Tmp, Lo, Hi);
>> @@ -6157,7 +6157,7 @@
>>                 TargetLowering::Custom &&
>>           "Must custom expand ReadCycleCounter");
>>    SDValue Tmp = TLI.LowerOperation(Op, DAG);
>> -    assert(Tmp.Val && "Node must be custom expanded!");
>> +    assert(Tmp.getNode() && "Node must be custom expanded!");
>>    ExpandOp(Tmp.getValue(0), Lo, Hi);
>>    AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized
>> the chain.
>>                        LegalizeOp(Tmp.getValue(1)));
>> @@ -6170,7 +6170,7 @@
>>  case ISD::ATOMIC_CMP_SWAP_32:
>>  case ISD::ATOMIC_CMP_SWAP_64: {
>>    SDValue Tmp = TLI.LowerOperation(Op, DAG);
>> -    assert(Tmp.Val && "Node must be custom expanded!");
>> +    assert(Tmp.getNode() && "Node must be custom expanded!");
>>    ExpandOp(Tmp.getValue(0), Lo, Hi);
>>    AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized
>> the chain.
>>                        LegalizeOp(Tmp.getValue(1)));
>> @@ -6194,7 +6194,7 @@
>>
>>      // Now that the custom expander is done, expand the result,
>> which is still
>>      // VT.
>> -      if (Op.Val) {
>> +      if (Op.getNode()) {
>>        ExpandOp(Op, Lo, Hi);
>>        break;
>>      }
>> @@ -6219,7 +6219,7 @@
>>      Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op),
>> DAG);
>>
>>      // Now that the custom expander is done, expand the result.
>> -      if (Op.Val) {
>> +      if (Op.getNode()) {
>>        ExpandOp(Op, Lo, Hi);
>>        break;
>>      }
>> @@ -6238,7 +6238,7 @@
>>    if (TLI.getOperationAction(ISD::SHL, VT) ==
>> TargetLowering::Custom) {
>>      SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0),
>> ShiftAmt);
>>      Op = TLI.LowerOperation(Op, DAG);
>> -      if (Op.Val) {
>> +      if (Op.getNode()) {
>>        // Now that the custom expander is done, expand the result,
>> which is
>>        // still VT.
>>        ExpandOp(Op, Lo, Hi);
>> @@ -6288,7 +6288,7 @@
>>    if (TLI.getOperationAction(ISD::SRA, VT) ==
>> TargetLowering::Custom) {
>>      SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0),
>> ShiftAmt);
>>      Op = TLI.LowerOperation(Op, DAG);
>> -      if (Op.Val) {
>> +      if (Op.getNode()) {
>>        // Now that the custom expander is done, expand the result,
>> which is
>>        // still VT.
>>        ExpandOp(Op, Lo, Hi);
>> @@ -6320,7 +6320,7 @@
>>    if (TLI.getOperationAction(ISD::SRL, VT) ==
>> TargetLowering::Custom) {
>>      SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0),
>> ShiftAmt);
>>      Op = TLI.LowerOperation(Op, DAG);
>> -      if (Op.Val) {
>> +      if (Op.getNode()) {
>>        // Now that the custom expander is done, expand the result,
>> which is
>>        // still VT.
>>        ExpandOp(Op, Lo, Hi);
>> @@ -6352,7 +6352,7 @@
>>    if (TLI.getOperationAction(Node->getOpcode(), VT) ==
>>            TargetLowering::Custom) {
>>      SDValue Result = TLI.LowerOperation(Op, DAG);
>> -      if (Result.Val) {
>> +      if (Result.getNode()) {
>>        ExpandOp(Result, Lo, Hi);
>>        break;
>>      }
>> @@ -6425,7 +6425,7 @@
>>    // If the target wants to custom expand this, let them.
>>    if (TLI.getOperationAction(ISD::MUL, VT) ==
>> TargetLowering::Custom) {
>>      SDValue New = TLI.LowerOperation(Op, DAG);
>> -      if (New.Val) {
>> +      if (New.getNode()) {
>>        ExpandOp(New, Lo, Hi);
>>        break;
>>      }
>> @@ -6450,7 +6450,7 @@
>>        if (HasUMUL_LOHI) {
>>          // We can emit a umul_lohi.
>>          Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT),
>> LL, RL);
>> -          Hi = SDValue(Lo.Val, 1);
>> +          Hi = SDValue(Lo.getNode(), 1);
>>          break;
>>        }
>>        if (HasMULHU) {
>> @@ -6465,7 +6465,7 @@
>>        if (HasSMUL_LOHI) {
>>          // We can emit a smul_lohi.
>>          Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT),
>> LL, RL);
>> -          Hi = SDValue(Lo.Val, 1);
>> +          Hi = SDValue(Lo.getNode(), 1);
>>          break;
>>        }
>>        if (HasMULHS) {
>> @@ -6678,7 +6678,7 @@
>>        ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
>>                      DAG.getValueType(SrcVT))
>>        : DAG.getZeroExtendInReg(Tmp, SrcVT);
>> -      Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
>> +      Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
>>      SrcVT = Node->getOperand(0).getValueType();
>>    }
>>
>> @@ -6739,7 +6739,7 @@
>>  // is a type that requires multi-step expansion.
>>  if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
>>    Lo = LegalizeOp(Lo);
>> -    if (Hi.Val)
>> +    if (Hi.getNode())
>>      // Don't legalize the high part if it is expanded to a single
>> node.
>>      Hi = LegalizeOp(Hi);
>>  }
>> @@ -6755,7 +6755,7 @@
>> void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
>>                                         SDValue &Hi) {
>>  assert(Op.getValueType().isVector() && "Cannot split non-vector
>> type!");
>> -  SDNode *Node = Op.Val;
>> +  SDNode *Node = Op.getNode();
>>  unsigned NumElements = Op.getValueType().getVectorNumElements();
>>  assert(NumElements > 1 && "Cannot split a single element vector!");
>>
>> @@ -7033,7 +7033,7 @@
>>      unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
>>
>> Op.getValueType().getTypeForMVT());
>>      SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(),
>> LdAlign);
>> -      int FI = cast<FrameIndexSDNode>(Ptr.Val)->getIndex();
>> +      int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
>>
>>      SDValue St = DAG.getStore(DAG.getEntryNode(),
>>                                  InOp, Ptr,
>> @@ -7061,7 +7061,7 @@
>> /// scalar (e.g. f32) value.
>> SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
>>  assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp
>> invocation!");
>> -  SDNode *Node = Op.Val;
>> +  SDNode *Node = Op.getNode();
>>  MVT NewVT = Op.getValueType().getVectorElementType();
>>  assert(Op.getValueType().getVectorNumElements() == 1);
>>
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Thu
>> Aug 28 16:40:38 2008
>> @@ -76,7 +76,7 @@
>>  }
>>
>>  // If R is null, the sub-method took care of registering the result.
>> -  if (R.Val)
>> +  if (R.getNode())
>>    SetSoftenedFloat(SDValue(N, ResNo), R);
>> }
>>
>> @@ -311,11 +311,11 @@
>>  }
>>
>>  // If the result is null, the sub-method took care of registering
>> results etc.
>> -  if (!Res.Val) return false;
>> +  if (!Res.getNode()) return false;
>>
>>  // If the result is N, the sub-method updated N in place.  Check
>> to see if any
>>  // operands are new, and if so, mark them.
>> -  if (Res.Val == N) {
>> +  if (Res.getNode() == N) {
>>    // Mark N as new and remark N and its operands.  This allows us
>> to correctly
>>    // revisit N if it needs another step of promotion and allows us
>> to visit
>>    // any new operands to N.
>> @@ -438,7 +438,7 @@
>>
>>  // If SoftenSetCCOperands returned a scalar, we need to compare
>> the result
>>  // against zero to select between true and false values.
>> -  if (NewRHS.Val == 0) {
>> +  if (NewRHS.getNode() == 0) {
>>    NewRHS = DAG.getConstant(0, NewLHS.getValueType());
>>    CCCode = ISD::SETNE;
>>  }
>> @@ -472,7 +472,7 @@
>>
>>  // If SoftenSetCCOperands returned a scalar, we need to compare
>> the result
>>  // against zero to select between true and false values.
>> -  if (NewRHS.Val == 0) {
>> +  if (NewRHS.getNode() == 0) {
>>    NewRHS = DAG.getConstant(0, NewLHS.getValueType());
>>    CCCode = ISD::SETNE;
>>  }
>> @@ -489,7 +489,7 @@
>>  SoftenSetCCOperands(NewLHS, NewRHS, CCCode);
>>
>>  // If SoftenSetCCOperands returned a scalar, use it.
>> -  if (NewRHS.Val == 0) {
>> +  if (NewRHS.getNode() == 0) {
>>    assert(NewLHS.getValueType() == N->getValueType(0) &&
>>           "Unexpected setcc expansion!");
>>    return NewLHS;
>> @@ -577,7 +577,7 @@
>>  }
>>
>>  // If Lo/Hi is null, the sub-method took care of registering
>> results etc.
>> -  if (Lo.Val)
>> +  if (Lo.getNode())
>>    SetExpandedFloat(SDValue(N, ResNo), Lo, Hi);
>> }
>>
>> @@ -603,7 +603,7 @@
>>                                            RTLIB::ADD_PPCF128),
>>                               N->getValueType(0), Ops, 2,
>>                               false);
>> -  assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered
>> wrongly!");
>> +  assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call
>> lowered wrongly!");
>>  Lo = Call.getOperand(0); Hi = Call.getOperand(1);
>> }
>>
>> @@ -630,7 +630,7 @@
>>                                            RTLIB::DIV_PPCF128),
>>                               N->getValueType(0), Ops, 2,
>>                               false);
>> -  assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered
>> wrongly!");
>> +  assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call
>> lowered wrongly!");
>>  Lo = Call.getOperand(0); Hi = Call.getOperand(1);
>> }
>>
>> @@ -644,7 +644,7 @@
>>                                            RTLIB::MUL_PPCF128),
>>                               N->getValueType(0), Ops, 2,
>>                               false);
>> -  assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered
>> wrongly!");
>> +  assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call
>> lowered wrongly!");
>>  Lo = Call.getOperand(0); Hi = Call.getOperand(1);
>> }
>>
>> @@ -672,7 +672,7 @@
>>                                            RTLIB::SUB_PPCF128),
>>                               N->getValueType(0), Ops, 2,
>>                               false);
>> -  assert(Call.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered
>> wrongly!");
>> +  assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call
>> lowered wrongly!");
>>  Lo = Call.getOperand(0); Hi = Call.getOperand(1);
>> }
>>
>> @@ -734,7 +734,7 @@
>>    assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
>>
>>    Hi = MakeLibCall(LC, VT, &Src, 1, true);
>> -    assert(Hi.Val->getOpcode() == ISD::BUILD_PAIR && "Call lowered
>> wrongly!");
>> +    assert(Hi.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call
>> lowered wrongly!");
>>    Lo = Hi.getOperand(0); Hi = Hi.getOperand(1);
>>  }
>>
>> @@ -790,7 +790,7 @@
>>      == TargetLowering::Custom)
>>    Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
>>
>> -  if (Res.Val == 0) {
>> +  if (Res.getNode() == 0) {
>>    switch (N->getOpcode()) {
>>    default:
>>  #ifndef NDEBUG
>> @@ -816,10 +816,10 @@
>>  }
>>
>>  // If the result is null, the sub-method took care of registering
>> results etc.
>> -  if (!Res.Val) return false;
>> +  if (!Res.getNode()) return false;
>>  // If the result is N, the sub-method updated N in place.  Check
>> to see if any
>>  // operands are new, and if so, mark them.
>> -  if (Res.Val == N) {
>> +  if (Res.getNode() == N) {
>>    // Mark N as new and remark N and its operands.  This allows us
>> to correctly
>>    // revisit N if it needs another step of expansion and allows us
>> to visit
>>    // any new operands to N.
>> @@ -869,7 +869,7 @@
>>
>>  // If ExpandSetCCOperands returned a scalar, we need to compare
>> the result
>>  // against zero to select between true and false values.
>> -  if (NewRHS.Val == 0) {
>> +  if (NewRHS.getNode() == 0) {
>>    NewRHS = DAG.getConstant(0, NewLHS.getValueType());
>>    CCCode = ISD::SETNE;
>>  }
>> @@ -910,7 +910,7 @@
>>
>>  // If ExpandSetCCOperands returned a scalar, we need to compare
>> the result
>>  // against zero to select between true and false values.
>> -  if (NewRHS.Val == 0) {
>> +  if (NewRHS.getNode() == 0) {
>>    NewRHS = DAG.getConstant(0, NewLHS.getValueType());
>>    CCCode = ISD::SETNE;
>>  }
>> @@ -927,7 +927,7 @@
>>  FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode);
>>
>>  // If ExpandSetCCOperands returned a scalar, use it.
>> -  if (NewRHS.Val == 0) {
>> +  if (NewRHS.getNode() == 0) {
>>    assert(NewLHS.getValueType() == N->getValueType(0) &&
>>           "Unexpected setcc expansion!");
>>    return NewLHS;
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ 
>> LegalizeIntegerTypes.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Thu
>> Aug 28 16:40:38 2008
>> @@ -99,7 +99,7 @@
>>  }
>>
>>  // If Result is null, the sub-method took care of registering the
>> result.
>> -  if (Result.Val)
>> +  if (Result.getNode())
>>    SetPromotedInteger(SDValue(N, ResNo), Result);
>> }
>>
>> @@ -167,7 +167,7 @@
>>  // Otherwise, lower the bit-convert to a store/load from the
>> stack, then
>>  // promote the load.
>>  SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0));
>> -  return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.Val));
>> +  return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.getNode()));
>> }
>>
>> SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
>> @@ -494,7 +494,7 @@
>>      == TargetLowering::Custom)
>>    Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
>>
>> -  if (Res.Val == 0) {
>> +  if (Res.getNode() == 0) {
>>    switch (N->getOpcode()) {
>>      default:
>>  #ifndef NDEBUG
>> @@ -529,9 +529,9 @@
>>  }
>>
>>  // If the result is null, the sub-method took care of registering
>> results etc.
>> -  if (!Res.Val) return false;
>> +  if (!Res.getNode()) return false;
>>  // If the result is N, the sub-method updated N in place.
>> -  if (Res.Val == N) {
>> +  if (Res.getNode() == N) {
>>    // Mark N as new and remark N and its operands.  This allows us
>> to correctly
>>    // revisit N if it needs another step of promotion and allows us
>> to visit
>>    // any new operands to N.
>> @@ -885,7 +885,7 @@
>>  }
>>
>>  // If Lo/Hi is null, the sub-method took care of registering
>> results etc.
>> -  if (Lo.Val)
>> +  if (Lo.getNode())
>>    SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
>> }
>>
>> @@ -1395,7 +1395,7 @@
>>      if (HasUMUL_LOHI) {
>>        // We can emit a umul_lohi.
>>        Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT),
>> LL, RL);
>> -        Hi = SDValue(Lo.Val, 1);
>> +        Hi = SDValue(Lo.getNode(), 1);
>>        return;
>>      }
>>      if (HasMULHU) {
>> @@ -1410,7 +1410,7 @@
>>      if (HasSMUL_LOHI) {
>>        // We can emit a smul_lohi.
>>        Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT),
>> LL, RL);
>> -        Hi = SDValue(Lo.Val, 1);
>> +        Hi = SDValue(Lo.getNode(), 1);
>>        return;
>>      }
>>      if (HasMULHS) {
>> @@ -1706,7 +1706,7 @@
>>      == TargetLowering::Custom)
>>    Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
>>
>> -  if (Res.Val == 0) {
>> +  if (Res.getNode() == 0) {
>>    switch (N->getOpcode()) {
>>    default:
>>  #ifndef NDEBUG
>> @@ -1732,10 +1732,10 @@
>>  }
>>
>>  // If the result is null, the sub-method took care of registering
>> results etc.
>> -  if (!Res.Val) return false;
>> +  if (!Res.getNode()) return false;
>>  // If the result is N, the sub-method updated N in place.  Check
>> to see if any
>>  // operands are new, and if so, mark them.
>> -  if (Res.Val == N) {
>> +  if (Res.getNode() == N) {
>>    // Mark N as new and remark N and its operands.  This allows us
>> to correctly
>>    // revisit N if it needs another step of expansion and allows us
>> to visit
>>    // any new operands to N.
>> @@ -1814,16 +1814,16 @@
>>  SDValue Tmp1, Tmp2;
>>  Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo,
>> RHSLo, LowCC,
>>                           false, DagCombineInfo);
>> -  if (!Tmp1.Val)
>> +  if (!Tmp1.getNode())
>>    Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
>> LowCC);
>>  Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi,
>> RHSHi,
>>                           CCCode, false, DagCombineInfo);
>> -  if (!Tmp2.Val)
>> +  if (!Tmp2.getNode())
>>    Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi),
>> LHSHi, RHSHi,
>>                       DAG.getCondCode(CCCode));
>>
>> -  ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
>> -  ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
>> +  ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
>> +  ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
>>  if ((Tmp1C && Tmp1C->isNullValue()) ||
>>      (Tmp2C && Tmp2C->isNullValue() &&
>>       (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
>> @@ -1841,7 +1841,7 @@
>>
>>  NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi,
>> RHSHi,
>>                             ISD::SETEQ, false, DagCombineInfo);
>> -  if (!NewLHS.Val)
>> +  if (!NewLHS.getNode())
>>    NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
>>                          ISD::SETEQ);
>>  NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
>> @@ -1856,7 +1856,7 @@
>>
>>  // If ExpandSetCCOperands returned a scalar, we need to compare
>> the result
>>  // against zero to select between true and false values.
>> -  if (NewRHS.Val == 0) {
>> +  if (NewRHS.getNode() == 0) {
>>    NewRHS = DAG.getConstant(0, NewLHS.getValueType());
>>    CCCode = ISD::SETNE;
>>  }
>> @@ -1874,7 +1874,7 @@
>>
>>  // If ExpandSetCCOperands returned a scalar, we need to compare
>> the result
>>  // against zero to select between true and false values.
>> -  if (NewRHS.Val == 0) {
>> +  if (NewRHS.getNode() == 0) {
>>    NewRHS = DAG.getConstant(0, NewLHS.getValueType());
>>    CCCode = ISD::SETNE;
>>  }
>> @@ -1891,7 +1891,7 @@
>>  IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
>>
>>  // If ExpandSetCCOperands returned a scalar, use it.
>> -  if (NewRHS.Val == 0) {
>> +  if (NewRHS.getNode() == 0) {
>>    assert(NewLHS.getValueType() == N->getValueType(0) &&
>>           "Unexpected setcc expansion!");
>>    return NewLHS;
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -92,7 +92,7 @@
>>    bool NeedsRevisit = false;
>>    unsigned i;
>>    for (i = 0; i != NumOperands; ++i) {
>> -      if (IgnoreNodeResults(N->getOperand(i).Val))
>> +      if (IgnoreNodeResults(N->getOperand(i).getNode()))
>>        continue;
>>
>>      MVT OpVT = N->getOperand(i).getValueType();
>> @@ -194,7 +194,7 @@
>>
>>    // Check that all operand types are legal.
>>    for (unsigned i = 0, NumOps = I->getNumOperands(); i < NumOps; +
>> +i)
>> -      if (!IgnoreNodeResults(I->getOperand(i).Val) &&
>> +      if (!IgnoreNodeResults(I->getOperand(i).getNode()) &&
>>          !isTypeLegal(I->getOperand(i).getValueType())) {
>>        cerr << "Operand type " << i << " illegal!\n";
>>        Failed = true;
>> @@ -221,7 +221,8 @@
>> /// AnalyzeNewNode - The specified node is the root of a subtree of
>> potentially
>> /// new nodes.  Correct any processed operands (this may change the
>> node) and
>> /// calculate the NodeId.
>> -void DAGTypeLegalizer::AnalyzeNewNode(SDNode *&N) {
>> +void DAGTypeLegalizer::AnalyzeNewNode(SDValue &Val) {
>> +  SDNode * const N(Val.getNode());
>>  // If this was an existing node that is already done, we're done.
>>  if (N->getNodeId() != NewNode)
>>    return;
>> @@ -246,12 +247,12 @@
>>    SDValue OrigOp = N->getOperand(i);
>>    SDValue Op = OrigOp;
>>
>> -    if (Op.Val->getNodeId() == Processed)
>> +    if (Op.getNode()->getNodeId() == Processed)
>>      RemapNode(Op);
>>
>> -    if (Op.Val->getNodeId() == NewNode)
>> -      AnalyzeNewNode(Op.Val);
>> -    else if (Op.Val->getNodeId() == Processed)
>> +    if (Op.getNode()->getNodeId() == NewNode)
>> +      AnalyzeNewNode(Op);
>> +    else if (Op.getNode()->getNodeId() == Processed)
>>      ++NumProcessed;
>>
>>    if (!NewOps.empty()) {
>> @@ -267,11 +268,14 @@
>>
>>  // Some operands changed - update the node.
>>  if (!NewOps.empty())
>> -    N = DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0],
>> NewOps.size()).Val;
>> -
>> -  N->setNodeId(N->getNumOperands()-NumProcessed);
>> -  if (N->getNodeId() == ReadyToProcess)
>> -    Worklist.push_back(N);
>> +    Val.setNode(DAG.UpdateNodeOperands(SDValue(N, 0),
>> +				       &NewOps[0],
>> +				       NewOps.size()).getNode());
>> +
>> +  SDNode * const Nu(Val.getNode());
>> +  Nu->setNodeId(Nu->getNumOperands()-NumProcessed);
>> +  if (Nu->getNodeId() == ReadyToProcess)
>> +    Worklist.push_back(Nu);
>> }
>>
>> namespace {
>> @@ -313,8 +317,8 @@
>>  if (From == To) return;
>>
>>  // If expansion produced new nodes, make sure they are properly
>> marked.
>> -  ExpungeNode(From.Val);
>> -  AnalyzeNewNode(To.Val); // Expunges To.
>> +  ExpungeNode(From.getNode());
>> +  AnalyzeNewNode(To); // Expunges To.
>>
>>  // Anything that used the old node should now use the new one.
>> Note that this
>>  // can potentially cause recursive merging.
>> @@ -333,7 +337,10 @@
>>
>>  // If expansion produced new nodes, make sure they are properly
>> marked.
>>  ExpungeNode(From);
>> -  AnalyzeNewNode(To); // Expunges To.
>> +
>> +  SDValue ToNode(To, 0);
>> +  AnalyzeNewNode(ToNode); // Expunges To.
>> +  To = ToNode.getNode();
>>
>>  assert(From->getNumValues() == To->getNumValues() &&
>>         "Node results don't match");
>> @@ -394,39 +401,39 @@
>>
>>  for (DenseMap<SDValue, SDValue>::iterator I =
>> PromotedIntegers.begin(),
>>       E = PromotedIntegers.end(); I != E; ++I) {
>> -    assert(I->first.Val != N);
>> +    assert(I->first.getNode() != N);
>>    RemapNode(I->second);
>>  }
>>
>>  for (DenseMap<SDValue, SDValue>::iterator I =
>> SoftenedFloats.begin(),
>>       E = SoftenedFloats.end(); I != E; ++I) {
>> -    assert(I->first.Val != N);
>> +    assert(I->first.getNode() != N);
>>    RemapNode(I->second);
>>  }
>>
>>  for (DenseMap<SDValue, SDValue>::iterator I =
>> ScalarizedVectors.begin(),
>>       E = ScalarizedVectors.end(); I != E; ++I) {
>> -    assert(I->first.Val != N);
>> +    assert(I->first.getNode() != N);
>>    RemapNode(I->second);
>>  }
>>
>>  for (DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator
>>       I = ExpandedIntegers.begin(), E = ExpandedIntegers.end(); I !
>> = E; ++I){
>> -    assert(I->first.Val != N);
>> +    assert(I->first.getNode() != N);
>>    RemapNode(I->second.first);
>>    RemapNode(I->second.second);
>>  }
>>
>>  for (DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator
>>       I = ExpandedFloats.begin(), E = ExpandedFloats.end(); I != E;
>> ++I) {
>> -    assert(I->first.Val != N);
>> +    assert(I->first.getNode() != N);
>>    RemapNode(I->second.first);
>>    RemapNode(I->second.second);
>>  }
>>
>>  for (DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator
>>       I = SplitVectors.begin(), E = SplitVectors.end(); I != E; +
>> +I) {
>> -    assert(I->first.Val != N);
>> +    assert(I->first.getNode() != N);
>>    RemapNode(I->second.first);
>>    RemapNode(I->second.second);
>>  }
>> @@ -440,26 +447,26 @@
>> }
>>
>> void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue
>> Result) {
>> -  AnalyzeNewNode(Result.Val);
>> +  AnalyzeNewNode(Result);
>>
>>  SDValue &OpEntry = PromotedIntegers[Op];
>> -  assert(OpEntry.Val == 0 && "Node is already promoted!");
>> +  assert(OpEntry.getNode() == 0 && "Node is already promoted!");
>>  OpEntry = Result;
>> }
>>
>> void DAGTypeLegalizer::SetSoftenedFloat(SDValue Op, SDValue Result) {
>> -  AnalyzeNewNode(Result.Val);
>> +  AnalyzeNewNode(Result);
>>
>>  SDValue &OpEntry = SoftenedFloats[Op];
>> -  assert(OpEntry.Val == 0 && "Node is already converted to
>> integer!");
>> +  assert(OpEntry.getNode() == 0 && "Node is already converted to
>> integer!");
>>  OpEntry = Result;
>> }
>>
>> void DAGTypeLegalizer::SetScalarizedVector(SDValue Op, SDValue
>> Result) {
>> -  AnalyzeNewNode(Result.Val);
>> +  AnalyzeNewNode(Result);
>>
>>  SDValue &OpEntry = ScalarizedVectors[Op];
>> -  assert(OpEntry.Val == 0 && "Node is already scalarized!");
>> +  assert(OpEntry.getNode() == 0 && "Node is already scalarized!");
>>  OpEntry = Result;
>> }
>>
>> @@ -468,7 +475,7 @@
>>  std::pair<SDValue, SDValue> &Entry = ExpandedIntegers[Op];
>>  RemapNode(Entry.first);
>>  RemapNode(Entry.second);
>> -  assert(Entry.first.Val && "Operand isn't expanded");
>> +  assert(Entry.first.getNode() && "Operand isn't expanded");
>>  Lo = Entry.first;
>>  Hi = Entry.second;
>> }
>> @@ -476,12 +483,12 @@
>> void DAGTypeLegalizer::SetExpandedInteger(SDValue Op, SDValue Lo,
>>                                          SDValue Hi) {
>>  // Lo/Hi may have been newly allocated, if so, add nodeid's as
>> relevant.
>> -  AnalyzeNewNode(Lo.Val);
>> -  AnalyzeNewNode(Hi.Val);
>> +  AnalyzeNewNode(Lo);
>> +  AnalyzeNewNode(Hi);
>>
>>  // Remember that this is the result of the node.
>>  std::pair<SDValue, SDValue> &Entry = ExpandedIntegers[Op];
>> -  assert(Entry.first.Val == 0 && "Node already expanded");
>> +  assert(Entry.first.getNode() == 0 && "Node already expanded");
>>  Entry.first = Lo;
>>  Entry.second = Hi;
>> }
>> @@ -491,7 +498,7 @@
>>  std::pair<SDValue, SDValue> &Entry = ExpandedFloats[Op];
>>  RemapNode(Entry.first);
>>  RemapNode(Entry.second);
>> -  assert(Entry.first.Val && "Operand isn't expanded");
>> +  assert(Entry.first.getNode() && "Operand isn't expanded");
>>  Lo = Entry.first;
>>  Hi = Entry.second;
>> }
>> @@ -499,12 +506,12 @@
>> void DAGTypeLegalizer::SetExpandedFloat(SDValue Op, SDValue Lo,
>>                                        SDValue Hi) {
>>  // Lo/Hi may have been newly allocated, if so, add nodeid's as
>> relevant.
>> -  AnalyzeNewNode(Lo.Val);
>> -  AnalyzeNewNode(Hi.Val);
>> +  AnalyzeNewNode(Lo);
>> +  AnalyzeNewNode(Hi);
>>
>>  // Remember that this is the result of the node.
>>  std::pair<SDValue, SDValue> &Entry = ExpandedFloats[Op];
>> -  assert(Entry.first.Val == 0 && "Node already expanded");
>> +  assert(Entry.first.getNode() == 0 && "Node already expanded");
>>  Entry.first = Lo;
>>  Entry.second = Hi;
>> }
>> @@ -514,7 +521,7 @@
>>  std::pair<SDValue, SDValue> &Entry = SplitVectors[Op];
>>  RemapNode(Entry.first);
>>  RemapNode(Entry.second);
>> -  assert(Entry.first.Val && "Operand isn't split");
>> +  assert(Entry.first.getNode() && "Operand isn't split");
>>  Lo = Entry.first;
>>  Hi = Entry.second;
>> }
>> @@ -522,12 +529,12 @@
>> void DAGTypeLegalizer::SetSplitVector(SDValue Op, SDValue Lo,
>>                                      SDValue Hi) {
>>  // Lo/Hi may have been newly allocated, if so, add nodeid's as
>> relevant.
>> -  AnalyzeNewNode(Lo.Val);
>> -  AnalyzeNewNode(Hi.Val);
>> +  AnalyzeNewNode(Lo);
>> +  AnalyzeNewNode(Hi);
>>
>>  // Remember that this is the result of the node.
>>  std::pair<SDValue, SDValue> &Entry = SplitVectors[Op];
>> -  assert(Entry.first.Val == 0 && "Node already split");
>> +  assert(Entry.first.getNode() == 0 && "Node already split");
>>  Entry.first = Lo;
>>  Entry.second = Hi;
>> }
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Thu Aug 28
>> 16:40:38 2008
>> @@ -157,7 +157,8 @@
>>  /// for the specified node, adding it to the worklist if ready.
>>  void ReanalyzeNode(SDNode *N) {
>>    N->setNodeId(NewNode);
>> -    AnalyzeNewNode(N);
>> +    SDValue V(N, 0);
>> +    AnalyzeNewNode(V); // FIXME: ignore the change?
>>  }
>>
>>  void NoteDeletion(SDNode *Old, SDNode *New) {
>> @@ -168,7 +169,7 @@
>>  }
>>
>> private:
>> -  void AnalyzeNewNode(SDNode *&N);
>> +  void AnalyzeNewNode(SDValue &Val);
>>
>>  void ReplaceValueWith(SDValue From, SDValue To);
>>  void ReplaceNodeWith(SDNode *From, SDNode *To);
>> @@ -197,7 +198,7 @@
>>  SDValue GetPromotedInteger(SDValue Op) {
>>    SDValue &PromotedOp = PromotedIntegers[Op];
>>    RemapNode(PromotedOp);
>> -    assert(PromotedOp.Val && "Operand wasn't promoted?");
>> +    assert(PromotedOp.getNode() && "Operand wasn't promoted?");
>>    return PromotedOp;
>>  }
>>  void SetPromotedInteger(SDValue Op, SDValue Result);
>> @@ -324,7 +325,7 @@
>>  SDValue GetSoftenedFloat(SDValue Op) {
>>    SDValue &SoftenedOp = SoftenedFloats[Op];
>>    RemapNode(SoftenedOp);
>> -    assert(SoftenedOp.Val && "Operand wasn't converted to  
>> integer?");
>> +    assert(SoftenedOp.getNode() && "Operand wasn't converted to
>> integer?");
>>    return SoftenedOp;
>>  }
>>  void SetSoftenedFloat(SDValue Op, SDValue Result);
>> @@ -403,7 +404,7 @@
>>  SDValue GetScalarizedVector(SDValue Op) {
>>    SDValue &ScalarizedOp = ScalarizedVectors[Op];
>>    RemapNode(ScalarizedOp);
>> -    assert(ScalarizedOp.Val && "Operand wasn't scalarized?");
>> +    assert(ScalarizedOp.getNode() && "Operand wasn't scalarized?");
>>    return ScalarizedOp;
>>  }
>>  void SetScalarizedVector(SDValue Op, SDValue Result);
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ 
>> LegalizeTypesGeneric.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Thu
>> Aug 28 16:40:38 2008
>> @@ -75,7 +75,7 @@
>>
>>  // Lower the bit-convert to a store/load from the stack, then
>> expand the load.
>>  SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0));
>> -  ExpandRes_NormalLoad(Op.Val, Lo, Hi);
>> +  ExpandRes_NormalLoad(Op.getNode(), Lo, Hi);
>> }
>>
>> void DAGTypeLegalizer::ExpandRes_BUILD_PAIR(SDNode *N, SDValue &Lo,
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Thu
>> Aug 28 16:40:38 2008
>> @@ -88,7 +88,7 @@
>>  }
>>
>>  // If R is null, the sub-method took care of registering the result.
>> -  if (R.Val)
>> +  if (R.getNode())
>>    SetScalarizedVector(SDValue(N, ResNo), R);
>> }
>>
>> @@ -184,7 +184,7 @@
>>        cerr << "\n");
>>  SDValue Res = SDValue();
>>
>> -  if (Res.Val == 0) {
>> +  if (Res.getNode() == 0) {
>>    switch (N->getOpcode()) {
>>    default:
>> #ifndef NDEBUG
>> @@ -206,11 +206,11 @@
>>  }
>>
>>  // If the result is null, the sub-method took care of registering
>> results etc.
>> -  if (!Res.Val) return false;
>> +  if (!Res.getNode()) return false;
>>
>>  // If the result is N, the sub-method updated N in place.  Check
>> to see if any
>>  // operands are new, and if so, mark them.
>> -  if (Res.Val == N) {
>> +  if (Res.getNode() == N) {
>>    // Mark N as new and remark N and its operands.  This allows us
>> to correctly
>>    // revisit N if it needs another step of promotion and allows us
>> to visit
>>    // any new operands to N.
>> @@ -332,7 +332,7 @@
>>  }
>>
>>  // If Lo/Hi is null, the sub-method took care of registering
>> results etc.
>> -  if (Lo.Val)
>> +  if (Lo.getNode())
>>    SetSplitVector(SDValue(N, ResNo), Lo, Hi);
>> }
>>
>> @@ -475,7 +475,7 @@
>>  SDValue Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0);
>>
>>  // Split it.
>> -  SplitVecRes_LOAD(cast<LoadSDNode>(Load.Val), Lo, Hi);
>> +  SplitVecRes_LOAD(cast<LoadSDNode>(Load.getNode()), Lo, Hi);
>> }
>>
>> void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
>> @@ -595,7 +595,7 @@
>>  DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
>>  SDValue Res = SDValue();
>>
>> -  if (Res.Val == 0) {
>> +  if (Res.getNode() == 0) {
>>    switch (N->getOpcode()) {
>>    default:
>> #ifndef NDEBUG
>> @@ -615,11 +615,11 @@
>>  }
>>
>>  // If the result is null, the sub-method took care of registering
>> results etc.
>> -  if (!Res.Val) return false;
>> +  if (!Res.getNode()) return false;
>>
>>  // If the result is N, the sub-method updated N in place.  Check
>> to see if any
>>  // operands are new, and if so, mark them.
>> -  if (Res.Val == N) {
>> +  if (Res.getNode() == N) {
>>    // Mark N as new and remark N and its operands.  This allows us
>> to correctly
>>    // revisit N if it needs another step of promotion and allows us
>> to visit
>>    // any new operands to N.
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -122,7 +122,7 @@
>>    if (N->getNumOperands() &&
>>        N->getOperand(N->getNumOperands()-1).getValueType() ==
>> MVT::Flag) {
>>      do {
>> -        N = N->getOperand(N->getNumOperands()-1).Val;
>> +        N = N->getOperand(N->getNumOperands()-1).getNode();
>>        NodeSUnit->FlaggedNodes.push_back(N);
>>        assert(N->getNodeId() == -1 && "Node already inserted!");
>>        N->setNodeId(NodeSUnit->NodeNum);
>> @@ -192,7 +192,7 @@
>>        SU->hasPhysRegDefs = true;
>>
>>      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
>> -        SDNode *OpN = N->getOperand(i).Val;
>> +        SDNode *OpN = N->getOperand(i).getNode();
>>        if (isPassiveNode(OpN)) continue;   // Not scheduled.
>>        SUnit *OpSU = &SUnits[OpN->getNodeId()];
>>        assert(OpSU && "Node has no SUnit!");
>> @@ -373,7 +373,7 @@
>> /// actual operands that will go into the resulting MachineInstr.
>> unsigned ScheduleDAG::CountOperands(SDNode *Node) {
>>  unsigned N = ComputeMemOperandsEnd(Node);
>> -  while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).Val))
>> +  while (N && isa<MemOperandSDNode>(Node->getOperand(N -
>> 1).getNode()))
>>    --N; // Ignore MEMOPERAND nodes
>>  return N;
>> }
>> @@ -429,7 +429,7 @@
>>    SDNode *User = *UI;
>>    bool Match = true;
>>    if (User->getOpcode() == ISD::CopyToReg &&
>> -        User->getOperand(2).Val == Node &&
>> +        User->getOperand(2).getNode() == Node &&
>>        User->getOperand(2).getResNo() == ResNo) {
>>      unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))-
>>> getReg();
>>      if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
>> @@ -440,7 +440,7 @@
>>    } else {
>>      for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
>>        SDValue Op = User->getOperand(i);
>> -        if (Op.Val != Node || Op.getResNo() != ResNo)
>> +        if (Op.getNode() != Node || Op.getResNo() != ResNo)
>>          continue;
>>        MVT VT = Node->getValueType(Op.getResNo());
>>        if (VT != MVT::Other && VT != MVT::Flag)
>> @@ -489,7 +489,7 @@
>>
>>  SDNode *User = *Node->use_begin();
>>  if (User->getOpcode() == ISD::CopyToReg &&
>> -      User->getOperand(2).Val == Node &&
>> +      User->getOperand(2).getNode() == Node &&
>>      User->getOperand(2).getResNo() == ResNo) {
>>    unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))-
>>> getReg();
>>    if (TargetRegisterInfo::isVirtualRegister(Reg))
>> @@ -513,7 +513,7 @@
>>         UI != E; ++UI) {
>>      SDNode *User = *UI;
>>      if (User->getOpcode() == ISD::CopyToReg &&
>> -          User->getOperand(2).Val == Node &&
>> +          User->getOperand(2).getNode() == Node &&
>>          User->getOperand(2).getResNo() == i) {
>>        unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))-
>>> getReg();
>>        if (TargetRegisterInfo::isVirtualRegister(Reg)) {
>> @@ -547,7 +547,7 @@
>>  if (Op.isMachineOpcode() &&
>>      Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
>>    // Add an IMPLICIT_DEF instruction before every use.
>> -    unsigned VReg = getDstOfOnlyCopyToRegUse(Op.Val, Op.getResNo());
>> +    unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(),
>> Op.getResNo());
>>    // IMPLICIT_DEF can produce any type of result so its
>> TargetInstrDesc
>>    // does not include operand register class info.
>>    if (!VReg) {
>> @@ -600,7 +600,7 @@
>>      if (RC && VRC != RC) {
>>        cerr << "Register class of operand and regclass of use don't
>> agree!\n";
>>        cerr << "Operand = " << IIOpNum << "\n";
>> -        cerr << "Op->Val = "; Op.Val->dump(&DAG); cerr << "\n";
>> +        cerr << "Op->Val = "; Op.getNode()->dump(&DAG); cerr <<  
>> "\n";
>>        cerr << "MI = "; MI->print(cerr);
>>        cerr << "VReg = " << VReg << "\n";
>>        cerr << "VReg RegClass     size = " << VRC->getSize()
>> @@ -712,7 +712,7 @@
>>       UI != E; ++UI) {
>>    SDNode *User = *UI;
>>    if (User->getOpcode() == ISD::CopyToReg &&
>> -        User->getOperand(2).Val == Node) {
>> +        User->getOperand(2).getNode() == Node) {
>>      unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))-
>>> getReg();
>>      if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
>>        VRBase = DestReg;
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu
>> Aug 28 16:40:38 2008
>> @@ -224,7 +224,7 @@
>>        if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1)
>>          continue;
>>
>> -        SDNode *OpN = SU->Node->getOperand(j).Val;
>> +        SDNode *OpN = SU->Node->getOperand(j).getNode();
>>        SUnit *OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN-
>>> getNodeId()];
>>        if (OpSU && OperandSeen.count(OpSU) == 1) {
>>          // Ok, so SU is not the last use of OpSU, but SU is two-
>> address so
>> @@ -233,7 +233,7 @@
>>          bool DoCommute = true;
>>          for (unsigned k = 0; k < NumOps; ++k) {
>>            if (k != j) {
>> -              OpN = SU->Node->getOperand(k).Val;
>> +              OpN = SU->Node->getOperand(k).getNode();
>>              OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN-
>>> getNodeId()];
>>              if (OpSU && OperandSeen.count(OpSU) == 1) {
>>                DoCommute = false;
>> @@ -641,7 +641,7 @@
>>  }
>>  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
>>    const SDValue &Op = N->getOperand(i);
>> -    MVT VT = Op.Val->getValueType(Op.getResNo());
>> +    MVT VT = Op.getNode()->getValueType(Op.getResNo());
>>    if (VT == MVT::Flag)
>>      return NULL;
>>  }
>> @@ -930,7 +930,7 @@
>>  unsigned CurCycle = 0;
>>  // Add root to Available queue.
>>  if (!SUnits.empty()) {
>> -    SUnit *RootSU = &SUnits[DAG.getRoot().Val->getNodeId()];
>> +    SUnit *RootSU = &SUnits[DAG.getRoot().getNode()->getNodeId()];
>>    assert(RootSU->Succs.empty() && "Graph root shouldn't have
>> successors!");
>>    RootSU->isAvailable = true;
>>    AvailableQueue->push(RootSU);
>> @@ -1668,7 +1668,7 @@
>>    unsigned NumOps = TID.getNumOperands() - NumRes;
>>    for (unsigned i = 0; i != NumOps; ++i) {
>>      if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) {
>> -        SDNode *DU = SU->Node->getOperand(i).Val;
>> +        SDNode *DU = SU->Node->getOperand(i).getNode();
>>        if (DU->getNodeId() != -1 &&
>>            Op->OrigNode == &(*SUnits)[DU->getNodeId()])
>>          return true;
>> @@ -1742,7 +1742,7 @@
>>    unsigned NumOps = TID.getNumOperands() - NumRes;
>>    for (unsigned j = 0; j != NumOps; ++j) {
>>      if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) != -1) {
>> -        SDNode *DU = SU->Node->getOperand(j).Val;
>> +        SDNode *DU = SU->Node->getOperand(j).getNode();
>>        if (DU->getNodeId() == -1)
>>          continue;
>>        const SUnit *DUSU = &(*SUnits)[DU->getNodeId()];
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -96,7 +96,7 @@
>> bool ISD::isBuildVectorAllOnes(const SDNode *N) {
>>  // Look through a bit convert.
>>  if (N->getOpcode() == ISD::BIT_CONVERT)
>> -    N = N->getOperand(0).Val;
>> +    N = N->getOperand(0).getNode();
>>
>>  if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
>>
>> @@ -137,7 +137,7 @@
>> bool ISD::isBuildVectorAllZeros(const SDNode *N) {
>>  // Look through a bit convert.
>>  if (N->getOpcode() == ISD::BIT_CONVERT)
>> -    N = N->getOperand(0).Val;
>> +    N = N->getOperand(0).getNode();
>>
>>  if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
>>
>> @@ -326,7 +326,7 @@
>> static void AddNodeIDOperands(FoldingSetNodeID &ID,
>>                              const SDValue *Ops, unsigned NumOps) {
>>  for (; NumOps; --NumOps, ++Ops) {
>> -    ID.AddPointer(Ops->Val);
>> +    ID.AddPointer(Ops->getNode());
>>    ID.AddInteger(Ops->getResNo());
>>  }
>> }
>> @@ -1230,9 +1230,9 @@
>>    break;
>>  }
>>
>> -  if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val)) {
>> +  if (ConstantSDNode *N2C =  
>> dyn_cast<ConstantSDNode>(N2.getNode())) {
>>    const APInt &C2 = N2C->getAPIntValue();
>> -    if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
>> +    if (ConstantSDNode *N1C =
>> dyn_cast<ConstantSDNode>(N1.getNode())) {
>>      const APInt &C1 = N1C->getAPIntValue();
>>
>>      switch (Cond) {
>> @@ -1250,8 +1250,8 @@
>>      }
>>    }
>>  }
>> -  if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
>> -    if (ConstantFPSDNode *N2C =  
>> dyn_cast<ConstantFPSDNode>(N2.Val)) {
>> +  if (ConstantFPSDNode *N1C =
>> dyn_cast<ConstantFPSDNode>(N1.getNode())) {
>> +    if (ConstantFPSDNode *N2C =
>> dyn_cast<ConstantFPSDNode>(N2.getNode())) {
>>      // No compile time operations on this type yet.
>>      if (N1C->getValueType(0) == MVT::ppcf128)
>>        return SDValue();
>> @@ -1572,7 +1572,7 @@
>>    return;
>>  }
>>  case ISD::LOAD: {
>> -    if (ISD::isZEXTLoad(Op.Val)) {
>> +    if (ISD::isZEXTLoad(Op.getNode())) {
>>      LoadSDNode *LD = cast<LoadSDNode>(Op);
>>      MVT VT = LD->getMemoryVT();
>>      unsigned MemBits = VT.getSizeInBits();
>> @@ -2024,7 +2024,7 @@
>>  if (V.getOpcode() == ISD::BUILD_VECTOR)
>>    return V.getOperand(Index);
>>  if (V.getOpcode() == ISD::VECTOR_SHUFFLE)
>> -    return getShuffleScalarElt(V.Val, Index);
>> +    return getShuffleScalarElt(V.getNode(), Index);
>>  return SDValue();
>> }
>>
>> @@ -2050,7 +2050,7 @@
>>
>> SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue
>> Operand) {
>>  // Constant fold unary operations with an integer constant operand.
>> -  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) {
>> +  if (ConstantSDNode *C =
>> dyn_cast<ConstantSDNode>(Operand.getNode())) {
>>    const APInt &Val = C->getAPIntValue();
>>    unsigned BitWidth = VT.getSizeInBits();
>>    switch (Opcode) {
>> @@ -2091,7 +2091,7 @@
>>  }
>>
>>  // Constant fold unary operations with a floating point constant
>> operand.
>> -  if (ConstantFPSDNode *C =
>> dyn_cast<ConstantFPSDNode>(Operand.Val)) {
>> +  if (ConstantFPSDNode *C =
>> dyn_cast<ConstantFPSDNode>(Operand.getNode())) {
>>    APFloat V = C->getValueAPF();    // make copy
>>    if (VT != MVT::ppcf128 && Operand.getValueType() !=
>> MVT::ppcf128) {
>>      switch (Opcode) {
>> @@ -2130,7 +2130,7 @@
>>    }
>>  }
>>
>> -  unsigned OpOpcode = Operand.Val->getOpcode();
>> +  unsigned OpOpcode = Operand.getNode()->getOpcode();
>>  switch (Opcode) {
>>  case ISD::TokenFactor:
>>  case ISD::CONCAT_VECTORS:
>> @@ -2150,7 +2150,7 @@
>>    assert(Operand.getValueType().bitsLT(VT)
>>           && "Invalid sext node, dst < src!");
>>    if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
>> -      return getNode(OpOpcode, VT, Operand.Val->getOperand(0));
>> +      return getNode(OpOpcode, VT, Operand.getNode()- 
>> >getOperand(0));
>>    break;
>>  case ISD::ZERO_EXTEND:
>>    assert(VT.isInteger() && Operand.getValueType().isInteger() &&
>> @@ -2159,7 +2159,7 @@
>>    assert(Operand.getValueType().bitsLT(VT)
>>           && "Invalid zext node, dst < src!");
>>    if (OpOpcode == ISD::ZERO_EXTEND)   // (zext (zext x)) -> (zext x)
>> -      return getNode(ISD::ZERO_EXTEND, VT, Operand.Val-
>>> getOperand(0));
>> +      return getNode(ISD::ZERO_EXTEND, VT, Operand.getNode()-
>>> getOperand(0));
>>    break;
>>  case ISD::ANY_EXTEND:
>>    assert(VT.isInteger() && Operand.getValueType().isInteger() &&
>> @@ -2169,7 +2169,7 @@
>>           && "Invalid anyext node, dst < src!");
>>    if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND)
>>      // (ext (zext x)) -> (zext x)  and  (ext (sext x)) -> (sext x)
>> -      return getNode(OpOpcode, VT, Operand.Val->getOperand(0));
>> +      return getNode(OpOpcode, VT, Operand.getNode()- 
>> >getOperand(0));
>>    break;
>>  case ISD::TRUNCATE:
>>    assert(VT.isInteger() && Operand.getValueType().isInteger() &&
>> @@ -2178,16 +2178,16 @@
>>    assert(Operand.getValueType().bitsGT(VT)
>>           && "Invalid truncate node, src < dst!");
>>    if (OpOpcode == ISD::TRUNCATE)
>> -      return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0));
>> +      return getNode(ISD::TRUNCATE, VT, Operand.getNode()-
>>> getOperand(0));
>>    else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode ==
>> ISD::SIGN_EXTEND ||
>>             OpOpcode == ISD::ANY_EXTEND) {
>>      // If the source is smaller than the dest, we still need an
>> extend.
>> -      if (Operand.Val->getOperand(0).getValueType().bitsLT(VT))
>> -        return getNode(OpOpcode, VT, Operand.Val->getOperand(0));
>> -      else if (Operand.Val->getOperand(0).getValueType().bitsGT(VT))
>> -        return getNode(ISD::TRUNCATE, VT, Operand.Val-
>>> getOperand(0));
>> +      if (Operand.getNode()- 
>> >getOperand(0).getValueType().bitsLT(VT))
>> +        return getNode(OpOpcode, VT, Operand.getNode()-
>>> getOperand(0));
>> +      else if (Operand.getNode()-
>>> getOperand(0).getValueType().bitsGT(VT))
>> +        return getNode(ISD::TRUNCATE, VT, Operand.getNode()-
>>> getOperand(0));
>>      else
>> -        return Operand.Val->getOperand(0);
>> +        return Operand.getNode()->getOperand(0);
>>    }
>>    break;
>>  case ISD::BIT_CONVERT:
>> @@ -2215,14 +2215,14 @@
>>    break;
>>  case ISD::FNEG:
>>    if (OpOpcode == ISD::FSUB)   // -(X-Y) -> (Y-X)
>> -      return getNode(ISD::FSUB, VT, Operand.Val->getOperand(1),
>> -                     Operand.Val->getOperand(0));
>> +      return getNode(ISD::FSUB, VT, Operand.getNode()- 
>> >getOperand(1),
>> +                     Operand.getNode()->getOperand(0));
>>    if (OpOpcode == ISD::FNEG)  // --X -> X
>> -      return Operand.Val->getOperand(0);
>> +      return Operand.getNode()->getOperand(0);
>>    break;
>>  case ISD::FABS:
>>    if (OpOpcode == ISD::FNEG)  // abs(-X) -> abs(X)
>> -      return getNode(ISD::FABS, VT, Operand.Val->getOperand(0));
>> +      return getNode(ISD::FABS, VT, Operand.getNode()-
>>> getOperand(0));
>>    break;
>>  }
>>
>> @@ -2252,8 +2252,8 @@
>>
>> SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
>>                              SDValue N1, SDValue N2) {
>> -  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
>> -  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
>> +  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
>> +  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
>>  switch (Opcode) {
>>  default: break;
>>  case ISD::TokenFactor:
>> @@ -2268,8 +2268,8 @@
>>    // one big BUILD_VECTOR.
>>    if (N1.getOpcode() == ISD::BUILD_VECTOR &&
>>        N2.getOpcode() == ISD::BUILD_VECTOR) {
>> -      SmallVector<SDValue, 16> Elts(N1.Val->op_begin(), N1.Val-
>>> op_end());
>> -      Elts.insert(Elts.end(), N2.Val->op_begin(), N2.Val->op_end());
>> +      SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(),
>> N1.getNode()->op_end());
>> +      Elts.insert(Elts.end(), N2.getNode()->op_begin(),
>> N2.getNode()->op_end());
>>      return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size());
>>    }
>>    break;
>> @@ -2471,8 +2471,8 @@
>>  }
>>
>>  // Constant fold FP operations.
>> -  ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val);
>> -  ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val);
>> +  ConstantFPSDNode *N1CFP =  
>> dyn_cast<ConstantFPSDNode>(N1.getNode());
>> +  ConstantFPSDNode *N2CFP =  
>> dyn_cast<ConstantFPSDNode>(N2.getNode());
>>  if (N1CFP) {
>>    if (!N2CFP && isCommutativeBinOp(Opcode)) {
>>      // Cannonicalize constant to RHS if commutative
>> @@ -2615,8 +2615,8 @@
>> SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
>>                              SDValue N1, SDValue N2, SDValue N3) {
>>  // Perform various simplifications.
>> -  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
>> -  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
>> +  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
>> +  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
>>  switch (Opcode) {
>>  case ISD::CONCAT_VECTORS:
>>    // A CONCAT_VECTOR with all operands BUILD_VECTOR can be
>> simplified to
>> @@ -2624,16 +2624,16 @@
>>    if (N1.getOpcode() == ISD::BUILD_VECTOR &&
>>        N2.getOpcode() == ISD::BUILD_VECTOR &&
>>        N3.getOpcode() == ISD::BUILD_VECTOR) {
>> -      SmallVector<SDValue, 16> Elts(N1.Val->op_begin(), N1.Val-
>>> op_end());
>> -      Elts.insert(Elts.end(), N2.Val->op_begin(), N2.Val->op_end());
>> -      Elts.insert(Elts.end(), N3.Val->op_begin(), N3.Val->op_end());
>> +      SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(),
>> N1.getNode()->op_end());
>> +      Elts.insert(Elts.end(), N2.getNode()->op_begin(),
>> N2.getNode()->op_end());
>> +      Elts.insert(Elts.end(), N3.getNode()->op_begin(),
>> N3.getNode()->op_end());
>>      return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size());
>>    }
>>    break;
>>  case ISD::SETCC: {
>>    // Use FoldSetCC to simplify SETCC's.
>>    SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)-
>>> get());
>> -    if (Simp.Val) return Simp;
>> +    if (Simp.getNode()) return Simp;
>>    break;
>>  }
>>  case ISD::SELECT:
>> @@ -3049,7 +3049,7 @@
>>    SDValue Result =
>>      getMemcpyLoadsAndStores(*this, Chain, Dst, Src, ConstantSize-
>>> getValue(),
>>                              Align, false, DstSV, DstSVOff, SrcSV,
>> SrcSVOff);
>> -    if (Result.Val)
>> +    if (Result.getNode())
>>      return Result;
>>  }
>>
>> @@ -3059,7 +3059,7 @@
>>    TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align,
>>                                AlwaysInline,
>>                                DstSV, DstSVOff, SrcSV, SrcSVOff);
>> -  if (Result.Val)
>> +  if (Result.getNode())
>>    return Result;
>>
>>  // If we really need inline code and the target declined to
>> provide it,
>> @@ -3103,7 +3103,7 @@
>>    SDValue Result =
>>      getMemmoveLoadsAndStores(*this, Chain, Dst, Src, ConstantSize-
>>> getValue(),
>>                               Align, false, DstSV, DstSVOff, SrcSV,
>> SrcSVOff);
>> -    if (Result.Val)
>> +    if (Result.getNode())
>>      return Result;
>>  }
>>
>> @@ -3112,7 +3112,7 @@
>>  SDValue Result =
>>    TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align,
>>                                 DstSV, DstSVOff, SrcSV, SrcSVOff);
>> -  if (Result.Val)
>> +  if (Result.getNode())
>>    return Result;
>>
>>  // Emit a library call.
>> @@ -3146,7 +3146,7 @@
>>    SDValue Result =
>>      getMemsetStores(*this, Chain, Dst, Src, ConstantSize-
>>> getValue(), Align,
>>                      DstSV, DstSVOff);
>> -    if (Result.Val)
>> +    if (Result.getNode())
>>      return Result;
>>  }
>>
>> @@ -3155,7 +3155,7 @@
>>  SDValue Result =
>>    TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align,
>>                                DstSV, DstSVOff);
>> -  if (Result.Val)
>> +  if (Result.getNode())
>>    return Result;
>>
>>  // Emit a library call.
>> @@ -3737,7 +3737,7 @@
>> /// input node is returned.  As a degenerate case, if you specify
>> the same
>> /// input operands as the node already has, the input node is
>> returned.
>> SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) {
>> -  SDNode *N = InN.Val;
>> +  SDNode *N = InN.getNode();
>>  assert(N->getNumOperands() == 1 && "Update with wrong number of
>> operands");
>>
>>  // Check to see if there is no change.
>> @@ -3756,7 +3756,7 @@
>>  N->OperandList[0].getVal()->removeUser(0, N);
>>  N->OperandList[0] = Op;
>>  N->OperandList[0].setUser(N);
>> -  Op.Val->addUser(0, N);
>> +  Op.getNode()->addUser(0, N);
>>
>>  // If this gets put into a CSE map, add it.
>>  if (InsertPos) CSEMap.InsertNode(N, InsertPos);
>> @@ -3765,7 +3765,7 @@
>>
>> SDValue SelectionDAG::
>> UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) {
>> -  SDNode *N = InN.Val;
>> +  SDNode *N = InN.getNode();
>>  assert(N->getNumOperands() == 2 && "Update with wrong number of
>> operands");
>>
>>  // Check to see if there is no change.
>> @@ -3786,13 +3786,13 @@
>>    N->OperandList[0].getVal()->removeUser(0, N);
>>    N->OperandList[0] = Op1;
>>    N->OperandList[0].setUser(N);
>> -    Op1.Val->addUser(0, N);
>> +    Op1.getNode()->addUser(0, N);
>>  }
>>  if (N->OperandList[1] != Op2) {
>>    N->OperandList[1].getVal()->removeUser(1, N);
>>    N->OperandList[1] = Op2;
>>    N->OperandList[1].setUser(N);
>> -    Op2.Val->addUser(1, N);
>> +    Op2.getNode()->addUser(1, N);
>>  }
>>
>>  // If this gets put into a CSE map, add it.
>> @@ -3822,7 +3822,7 @@
>>
>> SDValue SelectionDAG::
>> UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned  
>> NumOps) {
>> -  SDNode *N = InN.Val;
>> +  SDNode *N = InN.getNode();
>>  assert(N->getNumOperands() == NumOps &&
>>         "Update with wrong number of operands");
>>
>> @@ -3853,7 +3853,7 @@
>>      N->OperandList[i].getVal()->removeUser(i, N);
>>      N->OperandList[i] = Ops[i];
>>      N->OperandList[i].setUser(N);
>> -      Ops[i].Val->addUser(i, N);
>> +      Ops[i].getNode()->addUser(i, N);
>>    }
>>  }
>>
>> @@ -4134,70 +4134,70 @@
>> /// node of the specified opcode and operands, it returns that node
>> instead of
>> /// the current one.
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) {
>> -  return getNode(~Opcode, VT).Val;
>> +  return getNode(~Opcode, VT).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue
>> Op1) {
>> -  return getNode(~Opcode, VT, Op1).Val;
>> +  return getNode(~Opcode, VT, Op1).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
>>                                    SDValue Op1, SDValue Op2) {
>> -  return getNode(~Opcode, VT, Op1, Op2).Val;
>> +  return getNode(~Opcode, VT, Op1, Op2).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
>>                                    SDValue Op1, SDValue Op2,
>>                                    SDValue Op3) {
>> -  return getNode(~Opcode, VT, Op1, Op2, Op3).Val;
>> +  return getNode(~Opcode, VT, Op1, Op2, Op3).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
>>                                    const SDValue *Ops, unsigned
>> NumOps) {
>> -  return getNode(~Opcode, VT, Ops, NumOps).Val;
>> +  return getNode(~Opcode, VT, Ops, NumOps).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT
>> VT2) {
>>  const MVT *VTs = getNodeValueTypes(VT1, VT2);
>>  SDValue Op;
>> -  return getNode(~Opcode, VTs, 2, &Op, 0).Val;
>> +  return getNode(~Opcode, VTs, 2, &Op, 0).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>>                                    MVT VT2, SDValue Op1) {
>>  const MVT *VTs = getNodeValueTypes(VT1, VT2);
>> -  return getNode(~Opcode, VTs, 2, &Op1, 1).Val;
>> +  return getNode(~Opcode, VTs, 2, &Op1, 1).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>>                                    MVT VT2, SDValue Op1,
>>                                    SDValue Op2) {
>>  const MVT *VTs = getNodeValueTypes(VT1, VT2);
>>  SDValue Ops[] = { Op1, Op2 };
>> -  return getNode(~Opcode, VTs, 2, Ops, 2).Val;
>> +  return getNode(~Opcode, VTs, 2, Ops, 2).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>>                                    MVT VT2, SDValue Op1,
>>                                    SDValue Op2, SDValue Op3) {
>>  const MVT *VTs = getNodeValueTypes(VT1, VT2);
>>  SDValue Ops[] = { Op1, Op2, Op3 };
>> -  return getNode(~Opcode, VTs, 2, Ops, 3).Val;
>> +  return getNode(~Opcode, VTs, 2, Ops, 3).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT  
>> VT2,
>>                                    const SDValue *Ops, unsigned
>> NumOps) {
>>  const MVT *VTs = getNodeValueTypes(VT1, VT2);
>> -  return getNode(~Opcode, VTs, 2, Ops, NumOps).Val;
>> +  return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT
>> VT2, MVT VT3,
>>                                    SDValue Op1, SDValue Op2) {
>>  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
>>  SDValue Ops[] = { Op1, Op2 };
>> -  return getNode(~Opcode, VTs, 3, Ops, 2).Val;
>> +  return getNode(~Opcode, VTs, 3, Ops, 2).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT
>> VT2, MVT VT3,
>>                                    SDValue Op1, SDValue Op2,
>>                                    SDValue Op3) {
>>  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
>>  SDValue Ops[] = { Op1, Op2, Op3 };
>> -  return getNode(~Opcode, VTs, 3, Ops, 3).Val;
>> +  return getNode(~Opcode, VTs, 3, Ops, 3).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT
>> VT2, MVT VT3,
>>                                    const SDValue *Ops, unsigned
>> NumOps) {
>>  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
>> -  return getNode(~Opcode, VTs, 3, Ops, NumOps).Val;
>> +  return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>>                                    MVT VT2, MVT VT3, MVT VT4,
>> @@ -4208,14 +4208,14 @@
>>  VTList.push_back(VT3);
>>  VTList.push_back(VT4);
>>  const MVT *VTs = getNodeValueTypes(VTList);
>> -  return getNode(~Opcode, VTs, 4, Ops, NumOps).Val;
>> +  return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode();
>> }
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
>>                                    const std::vector<MVT> &ResultTys,
>>                                    const SDValue *Ops, unsigned
>> NumOps) {
>>  const MVT *VTs = getNodeValueTypes(ResultTys);
>>  return getNode(~Opcode, VTs, ResultTys.size(),
>> -                 Ops, NumOps).Val;
>> +                 Ops, NumOps).getNode();
>> }
>>
>> /// getNodeIfExists - Get the specified node if it's already
>> available, or
>> @@ -4240,10 +4240,10 @@
>> ///
>> void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To,
>>                                      DAGUpdateListener
>> *UpdateListener) {
>> -  SDNode *From = FromN.Val;
>> +  SDNode *From = FromN.getNode();
>>  assert(From->getNumValues() == 1 && FromN.getResNo() == 0 &&
>>         "Cannot replace with this method!");
>> -  assert(From != To.Val && "Cannot replace uses of with self");
>> +  assert(From != To.getNode() && "Cannot replace uses of with  
>> self");
>>
>>  while (!From->use_empty()) {
>>    SDNode::use_iterator UI = From->use_begin();
>> @@ -4258,7 +4258,7 @@
>>        From->removeUser(operandNum, U);
>>        *I = To;
>>        I->setUser(U);
>> -        To.Val->addUser(operandNum, U);
>> +        To.getNode()->addUser(operandNum, U);
>>      }
>>
>>    // Now that we have modified U, add it back to the CSE maps.  If
>> it already
>> @@ -4305,7 +4305,7 @@
>>         I != E; ++I, ++operandNum)
>>      if (I->getVal() == From) {
>>        From->removeUser(operandNum, U);
>> -        I->getVal() = To;
>> +        I->getSDValue().setNode(To);
>>        To->addUser(operandNum, U);
>>      }
>>
>> @@ -4351,7 +4351,7 @@
>>        From->removeUser(operandNum, U);
>>        *I = ToOp;
>>        I->setUser(U);
>> -        ToOp.Val->addUser(operandNum, U);
>> +        ToOp.getNode()->addUser(operandNum, U);
>>      }
>>
>>    // Now that we have modified U, add it back to the CSE maps.  If
>> it already
>> @@ -4372,7 +4372,7 @@
>> }
>>
>> /// ReplaceAllUsesOfValueWith - Replace any uses of From with To,
>> leaving
>> -/// uses of other values produced by From.Val alone.  The Deleted
>> vector is
>> +/// uses of other values produced by From.getVal() alone.  The
>> Deleted vector is
>> /// handled the same way as for ReplaceAllUsesWith.
>> void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue  
>> To,
>>                                             DAGUpdateListener
>> *UpdateListener){
>> @@ -4380,14 +4380,14 @@
>>  if (From == To) return;
>>
>>  // Handle the simple, trivial, case efficiently.
>> -  if (From.Val->getNumValues() == 1) {
>> +  if (From.getNode()->getNumValues() == 1) {
>>    ReplaceAllUsesWith(From, To, UpdateListener);
>>    return;
>>  }
>>
>> -  // Get all of the users of From.Val.  We want these in a nice,
>> +  // Get all of the users of From.getNode().  We want these in a
>> nice,
>>  // deterministically ordered and uniqued set, so we use a
>> SmallSetVector.
>> -  SmallSetVector<SDNode*, 16> Users(From.Val->use_begin(), From.Val-
>>> use_end());
>> +  SmallSetVector<SDNode*, 16> Users(From.getNode()->use_begin(),
>> From.getNode()->use_end());
>>
>>  while (!Users.empty()) {
>>    // We know that this user uses some value of From.  If it is the
>> right
>> @@ -4410,10 +4410,10 @@
>>    // Update all operands that match "From" in case there are
>> multiple uses.
>>    for (; Op != E; ++Op) {
>>      if (*Op == From) {
>> -        From.Val->removeUser(Op-User->op_begin(), User);
>> +        From.getNode()->removeUser(Op-User->op_begin(), User);
>>        *Op = To;
>>        Op->setUser(User);
>> -        To.Val->addUser(Op-User->op_begin(), User);
>> +        To.getNode()->addUser(Op-User->op_begin(), User);
>>      }
>>    }
>>
>> @@ -4437,7 +4437,7 @@
>> }
>>
>> /// ReplaceAllUsesOfValuesWith - Replace any uses of From with To,
>> leaving
>> -/// uses of other values produced by From.Val alone.  The same
>> value may
>> +/// uses of other values produced by From.getVal() alone.  The same
>> value may
>> /// appear in both the From and To list.  The Deleted vector is
>> /// handled the same way as for ReplaceAllUsesWith.
>> void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From,
>> @@ -4450,8 +4450,8 @@
>>
>>  SmallVector<std::pair<SDNode *, unsigned>, 16> Users;
>>  for (unsigned i = 0; i != Num; ++i)
>> -    for (SDNode::use_iterator UI = From[i].Val->use_begin(),
>> -         E = From[i].Val->use_end(); UI != E; ++UI)
>> +    for (SDNode::use_iterator UI = From[i].getNode()->use_begin(),
>> +         E = From[i].getNode()->use_end(); UI != E; ++UI)
>>      Users.push_back(std::make_pair(*UI, i));
>>
>>  while (!Users.empty()) {
>> @@ -4476,10 +4476,10 @@
>>    // Update all operands that match "From" in case there are
>> multiple uses.
>>    for (; Op != E; ++Op) {
>>      if (*Op == From[i]) {
>> -        From[i].Val->removeUser(Op-User->op_begin(), User);
>> +        From[i].getNode()->removeUser(Op-User->op_begin(), User);
>>        *Op = To[i];
>>        Op->setUser(User);
>> -        To[i].Val->addUser(Op-User->op_begin(), User);
>> +        To[i].getNode()->addUser(Op-User->op_begin(), User);
>>      }
>>    }
>>
>> @@ -4617,7 +4617,7 @@
>>
>>  // Check if the memory reference references a frame index
>>  const FrameIndexSDNode *FI =
>> -  dyn_cast<const FrameIndexSDNode>(getBasePtr().Val);
>> +  dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode());
>>  if (!getSrcValue() && FI)
>>    return MachineMemOperand(PseudoSourceValue::getFixedStack(FI-
>>> getIndex()),
>>                             Flags, 0, Size, getAlignment());
>> @@ -4746,7 +4746,7 @@
>>    return;
>>
>>  for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; +
>> +i) {
>> -    SDNode *Op = N->getOperand(i).Val;
>> +    SDNode *Op = N->getOperand(i).getNode();
>>    if (Op == P) {
>>      found = true;
>>      return;
>> @@ -5115,13 +5115,13 @@
>>  OS << " ";
>>  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
>>    if (i) OS << ", ";
>> -    OS << (void*)getOperand(i).Val;
>> +    OS << (void*)getOperand(i).getNode();
>>    if (unsigned RN = getOperand(i).getResNo())
>>      OS << ":" << RN;
>>  }
>>
>>  if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) {
>> -    SDNode *Mask = getOperand(2).Val;
>> +    SDNode *Mask = getOperand(2).getNode();
>>    OS << "<";
>>    for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) {
>>      if (i) OS << ",";
>> @@ -5262,11 +5262,11 @@
>>
>> static void DumpNodes(const SDNode *N, unsigned indent, const
>> SelectionDAG *G) {
>>  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
>> -    if (N->getOperand(i).Val->hasOneUse())
>> -      DumpNodes(N->getOperand(i).Val, indent+2, G);
>> +    if (N->getOperand(i).getNode()->hasOneUse())
>> +      DumpNodes(N->getOperand(i).getNode(), indent+2, G);
>>    else
>>      cerr << "\n" << std::string(indent+2, ' ')
>> -           << (void*)N->getOperand(i).Val << ": <multiple use>";
>> +           << (void*)N->getOperand(i).getNode() << ": <multiple
>> use>";
>>
>>
>>  cerr << "\n" << std::string(indent, ' ');
>> @@ -5279,11 +5279,11 @@
>>  for (allnodes_const_iterator I = allnodes_begin(), E =
>> allnodes_end();
>>       I != E; ++I) {
>>    const SDNode *N = I;
>> -    if (!N->hasOneUse() && N != getRoot().Val)
>> +    if (!N->hasOneUse() && N != getRoot().getNode())
>>      DumpNodes(N, 2, this);
>>  }
>>
>> -  if (getRoot().Val) DumpNodes(getRoot().Val, 2, this);
>> +  if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this);
>>
>>  cerr << "\n\n";
>> }
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Aug
>> 28 16:40:38 2008
>> @@ -784,8 +784,8 @@
>>    if (Root.getOpcode() != ISD::EntryToken) {
>>      unsigned i = 0, e = PendingExports.size();
>>      for (; i != e; ++i) {
>> -        assert(PendingExports[i].Val->getNumOperands() > 1);
>> -        if (PendingExports[i].Val->getOperand(0) == Root)
>> +        assert(PendingExports[i].getNode()->getNumOperands() > 1);
>> +        if (PendingExports[i].getNode()->getOperand(0) == Root)
>>          break;  // Don't add the root if we already indirectly
>> depend on it.
>>      }
>>
>> @@ -824,7 +824,7 @@
>>
>>  void setValue(const Value *V, SDValue NewN) {
>>    SDValue &N = NodeMap[V];
>> -    assert(N.Val == 0 && "Already set a value for this node!");
>> +    assert(N.getNode() == 0 && "Already set a value for this  
>> node!");
>>    N = NewN;
>>  }
>>
>> @@ -1286,7 +1286,7 @@
>>
>> SDValue SelectionDAGLowering::getValue(const Value *V) {
>>  SDValue &N = NodeMap[V];
>> -  if (N.Val) return N;
>> +  if (N.getNode()) return N;
>>
>>  if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
>>    MVT VT = TLI.getValueType(V->getType(), true);
>> @@ -1310,7 +1310,7 @@
>>    if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
>>      visit(CE->getOpcode(), *CE);
>>      SDValue N1 = NodeMap[V];
>> -      assert(N1.Val && "visit didn't populate the ValueMap!");
>> +      assert(N1.getNode() && "visit didn't populate the ValueMap!");
>>      return N1;
>>    }
>>
>> @@ -1318,7 +1318,7 @@
>>      SmallVector<SDValue, 4> Constants;
>>      for (User::const_op_iterator OI = C->op_begin(), OE = C-
>>> op_end();
>>           OI != OE; ++OI) {
>> -        SDNode *Val = getValue(*OI).Val;
>> +        SDNode *Val = getValue(*OI).getNode();
>>        for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
>>          Constants.push_back(SDValue(Val, i));
>>      }
>> @@ -1428,7 +1428,7 @@
>>      else if (F->paramHasAttr(0, ParamAttr::ZExt))
>>        ExtendKind = ISD::ZERO_EXTEND;
>>
>> -      getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.getResNo() + j),
>> +      getCopyToParts(DAG, SDValue(RetOp.getNode(), RetOp.getResNo()
>> + j),
>>                     &Parts[0], NumParts, PartVT, ExtendKind);
>>
>>      for (unsigned i = 0; i < NumParts; ++i) {
>> @@ -2855,15 +2855,15 @@
>>  // Copy the beginning value(s) from the original aggregate.
>>  for (; i != LinearIndex; ++i)
>>    Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
>> -                SDValue(Agg.Val, Agg.getResNo() + i);
>> +                SDValue(Agg.getNode(), Agg.getResNo() + i);
>>  // Copy values from the inserted value(s).
>>  for (; i != LinearIndex + NumValValues; ++i)
>>    Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
>> -                SDValue(Val.Val, Val.getResNo() + i - LinearIndex);
>> +                SDValue(Val.getNode(), Val.getResNo() + i -
>> LinearIndex);
>>  // Copy remaining value(s) from the original aggregate.
>>  for (; i != NumAggValues; ++i)
>>    Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
>> -                SDValue(Agg.Val, Agg.getResNo() + i);
>> +                SDValue(Agg.getNode(), Agg.getResNo() + i);
>>
>>  setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0],
>> NumAggValues),
>>                                  &Values[0], NumAggValues));
>> @@ -2888,8 +2888,8 @@
>>  // Copy out the selected value(s).
>>  for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
>>    Values[i - LinearIndex] =
>> -      OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val-
>>> getValueType(Agg.getResNo() + i)) :
>> -                   SDValue(Agg.Val, Agg.getResNo() + i);
>> +      OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.getNode()-
>>> getValueType(Agg.getResNo() + i)) :
>> +                   SDValue(Agg.getNode(), Agg.getResNo() + i);
>>
>>  setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0],
>> NumValValues),
>>                                  &Values[0], NumValValues));
>> @@ -3084,7 +3084,7 @@
>>  bool isVolatile = I.isVolatile();
>>  unsigned Alignment = I.getAlignment();
>>  for (unsigned i = 0; i != NumValues; ++i)
>> -    Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.getResNo()
>> + i),
>> +    Chains[i] = DAG.getStore(Root, SDValue(Src.getNode(),
>> Src.getResNo() + i),
>>                             DAG.getNode(ISD::ADD, PtrVT, Ptr,
>>                                         DAG.getConstant(Offsets[i],
>> PtrVT)),
>>                             PtrV, Offsets[i],
>> @@ -3154,7 +3154,7 @@
>>                         &Ops[0], Ops.size());
>>
>>  if (HasChain) {
>> -    SDValue Chain = Result.getValue(Result.Val->getNumValues()-1);
>> +    SDValue Chain = Result.getValue(Result.getNode()-
>>> getNumValues()-1);
>>    if (OnlyLoad)
>>      PendingLoads.push_back(Chain);
>>    else
>> @@ -3621,7 +3621,7 @@
>>      Value *Alloca = I.getOperand(1);
>>      Constant *TypeMap = cast<Constant>(I.getOperand(2));
>>
>> -      FrameIndexSDNode *FI =
>> cast<FrameIndexSDNode>(getValue(Alloca).Val);
>> +      FrameIndexSDNode *FI =
>> cast<FrameIndexSDNode>(getValue(Alloca).getNode());
>>      GFI->addStackRoot(FI->getIndex(), TypeMap);
>>    }
>>    return 0;
>> @@ -4751,7 +4751,7 @@
>>
>>  // Finish up input operands.
>>  AsmNodeOperands[0] = Chain;
>> -  if (Flag.Val) AsmNodeOperands.push_back(Flag);
>> +  if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
>>
>>  Chain = DAG.getNode(ISD::INLINEASM,
>>                      DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
>> @@ -4770,7 +4770,7 @@
>>    // bit_convert.
>>    if (const StructType *ResSTy =
>> dyn_cast<StructType>(CS.getType())) {
>>      for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; +
>> +i) {
>> -        if (Val.Val->getValueType(i).isVector())
>> +        if (Val.getNode()->getValueType(i).isVector())
>>          Val = DAG.getNode(ISD::BIT_CONVERT,
>>                            TLI.getValueType(ResSTy-
>>> getElementType(i)), Val);
>>      }
>> @@ -4963,7 +4963,7 @@
>>  // Create the node.
>>  SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
>>                               DAG.getVTList(&RetVals[0],
>> RetVals.size()),
>> -                               &Ops[0], Ops.size()).Val;
>> +                               &Ops[0], Ops.size()).getNode();
>>
>>  // Prelower FORMAL_ARGUMENTS.  This isn't required for
>> functionality, but
>>  // allows exposing the loads that may be part of the argument
>> access to the
>> @@ -4972,18 +4972,18 @@
>>
>>  // The number of results should match up, except that the lowered
>> one may have
>>  // an extra flag result.
>> -  assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
>> -          (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
>> +  assert((Result->getNumValues() == TmpRes.getNode()-
>>> getNumValues() ||
>> +          (Result->getNumValues()+1 == TmpRes.getNode()-
>>> getNumValues() &&
>>           TmpRes.getValue(Result->getNumValues()).getValueType() ==
>> MVT::Flag))
>>         && "Lowering produced unexpected number of results!");
>>
>>  // The FORMAL_ARGUMENTS node itself is likely no longer needed.
>> -  if (Result != TmpRes.Val && Result->use_empty()) {
>> +  if (Result != TmpRes.getNode() && Result->use_empty()) {
>>    HandleSDNode Dummy(DAG.getRoot());
>>    DAG.RemoveDeadNode(Result);
>>  }
>>
>> -  Result = TmpRes.Val;
>> +  Result = TmpRes.getNode();
>>
>>  unsigned NumArgRegs = Result->getNumValues() - 1;
>>  DAG.setRoot(SDValue(Result, NumArgRegs));
>> @@ -5044,7 +5044,7 @@
>>         Value != NumValues; ++Value) {
>>      MVT VT = ValueVTs[Value];
>>      const Type *ArgTy = VT.getTypeForMVT();
>> -      SDValue Op = SDValue(Args[i].Node.Val,
>> Args[i].Node.getResNo() + Value);
>> +      SDValue Op = SDValue(Args[i].Node.getNode(),
>> Args[i].Node.getResNo() + Value);
>>      ISD::ArgFlagsTy Flags;
>>      unsigned OriginalAlignment =
>>        getTargetData()->getABITypeAlignment(ArgTy);
>> @@ -5333,7 +5333,7 @@
>>
>>  // Find RET node.
>>  if (Terminator.getOpcode() == ISD::RET) {
>> -    Ret = Terminator.Val;
>> +    Ret = Terminator.getNode();
>>  }
>>
>>  // Fix tail call attribute of CALL nodes.
>> @@ -5355,8 +5355,8 @@
>>        // Not eligible. Mark CALL node as non tail call.
>>        SmallVector<SDValue, 32> Ops;
>>        unsigned idx=0;
>> -        for(SDNode::op_iterator I =OpCall.Val->op_begin(),
>> -              E = OpCall.Val->op_end(); I != E; I++, idx++) {
>> +        for(SDNode::op_iterator I =OpCall.getNode()->op_begin(),
>> +              E = OpCall.getNode()->op_end(); I != E; I++, idx++) {
>>          if (idx!=3)
>>            Ops.push_back(*I);
>>          else
>> @@ -5369,8 +5369,8 @@
>>        SmallVector<SDValue, 32> Ops;
>>        SDValue Chain = OpCall.getOperand(0), InFlag;
>>        unsigned idx=0;
>> -        for(SDNode::op_iterator I = OpCall.Val->op_begin(),
>> -              E = OpCall.Val->op_end(); I != E; I++, idx++) {
>> +        for(SDNode::op_iterator I = OpCall.getNode()->op_begin(),
>> +              E = OpCall.getNode()->op_end(); I != E; I++, idx++) {
>>          SDValue Arg = *I;
>>          if (idx > 4 && (idx % 2)) {
>>            bool isByVal =
>> cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
>> @@ -5557,7 +5557,7 @@
>>  SmallPtrSet<SDNode*, 128> VisitedNodes;
>>  SmallVector<SDNode*, 128> Worklist;
>>
>> -  Worklist.push_back(CurDAG->getRoot().Val);
>> +  Worklist.push_back(CurDAG->getRoot().getNode());
>>
>>  APInt Mask;
>>  APInt KnownZero;
>> @@ -5574,7 +5574,7 @@
>>    // Otherwise, add all chain operands to the worklist.
>>    for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
>>      if (N->getOperand(i).getValueType() == MVT::Other)
>> -        Worklist.push_back(N->getOperand(i).Val);
>> +        Worklist.push_back(N->getOperand(i).getNode());
>>
>>    // If this is a CopyToReg with a vreg dest, process it.
>>    if (N->getOpcode() != ISD::CopyToReg)
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Thu
>> Aug 28 16:40:38 2008
>> @@ -109,8 +109,8 @@
>>    static void addCustomGraphFeatures(SelectionDAG *G,
>>                                       GraphWriter<SelectionDAG*>
>> &GW) {
>>      GW.emitSimpleNode(0, "plaintext=circle", "GraphRoot");
>> -      if (G->getRoot().Val)
>> -        GW.emitEdge(0, -1, G->getRoot().Val, G- 
>> >getRoot().getResNo(),
>> +      if (G->getRoot().getNode())
>> +        GW.emitEdge(0, -1, G->getRoot().getNode(), G-
>>> getRoot().getResNo(),
>>                    "color=blue,style=dashed");
>>    }
>>  };
>> @@ -356,7 +356,7 @@
>>    static void addCustomGraphFeatures(ScheduleDAG *G,
>>                                       GraphWriter<ScheduleDAG*>
>> &GW) {
>>      GW.emitSimpleNode(0, "plaintext=circle", "GraphRoot");
>> -      const SDNode *N = G->DAG.getRoot().Val;
>> +      const SDNode *N = G->DAG.getRoot().getNode();
>>      if (N && N->getNodeId() != -1)
>>        GW.emitEdge(0, -1, &G->SUnits[N->getNodeId()], -1,
>>                    "color=blue,style=dashed");
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Aug
>> 28 16:40:38 2008
>> @@ -674,7 +674,7 @@
>>  KnownZero = KnownOne = APInt(BitWidth, 0);
>>
>>  // Other users may use these bits.
>> -  if (!Op.Val->hasOneUse()) {
>> +  if (!Op.getNode()->hasOneUse()) {
>>    if (Depth != 0) {
>>      // If not at the root, Just compute the KnownZero/KnownOne
>> bits to
>>      // simplify things downstream.
>> @@ -1131,7 +1131,7 @@
>>
>>    // If the input is only used by this truncate, see if we can
>> shrink it based
>>    // on the known demanded bits.
>> -    if (Op.getOperand(0).Val->hasOneUse()) {
>> +    if (Op.getOperand(0).getNode()->hasOneUse()) {
>>      SDValue In = Op.getOperand(0);
>>      unsigned InBitWidth = In.getValueSizeInBits();
>>      switch (In.getOpcode()) {
>> @@ -1259,9 +1259,9 @@
>>  case ISD::SETTRUE2:  return DAG.getConstant(1, VT);
>>  }
>>
>> -  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
>> +  if (ConstantSDNode *N1C =  
>> dyn_cast<ConstantSDNode>(N1.getNode())) {
>>    const APInt &C1 = N1C->getAPIntValue();
>> -    if (isa<ConstantSDNode>(N0.Val)) {
>> +    if (isa<ConstantSDNode>(N0.getNode())) {
>>      return DAG.FoldSetCC(VT, N0, N1, Cond);
>>    } else {
>>      // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this
>> is an
>> @@ -1356,7 +1356,7 @@
>>                               DAG.getConstant(Imm, Op0Ty));
>>        }
>>        if (!DCI.isCalledByLegalizer())
>> -          DCI.AddToWorklist(ZextOp.Val);
>> +          DCI.AddToWorklist(ZextOp.getNode());
>>        // Otherwise, make this a use of a zext.
>>        return DAG.getSetCC(VT, ZextOp,
>>                            DAG.getConstant(C1 & APInt::getLowBitsSet(
>> @@ -1493,16 +1493,16 @@
>>          }
>>        }
>>    }
>> -  } else if (isa<ConstantSDNode>(N0.Val)) {
>> +  } else if (isa<ConstantSDNode>(N0.getNode())) {
>>      // Ensure that the constant occurs on the RHS.
>>    return DAG.getSetCC(VT, N1, N0,
>> ISD::getSetCCSwappedOperands(Cond));
>>  }
>>
>> -  if (isa<ConstantFPSDNode>(N0.Val)) {
>> +  if (isa<ConstantFPSDNode>(N0.getNode())) {
>>    // Constant fold or commute setcc.
>>    SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond);
>> -    if (O.Val) return O;
>> -  } else if (ConstantFPSDNode *CFP =
>> dyn_cast<ConstantFPSDNode>(N1.Val)) {
>> +    if (O.getNode()) return O;
>> +  } else if (ConstantFPSDNode *CFP =
>> dyn_cast<ConstantFPSDNode>(N1.getNode())) {
>>    // If the RHS of an FP comparison is a constant, simplify it
>> away in
>>    // some cases.
>>    if (CFP->getValueAPF().isNaN()) {
>> @@ -1564,7 +1564,7 @@
>>      if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
>>        if (ConstantSDNode *LHSR =
>> dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
>>          // Turn (X+C1) == C2 --> X == C2-C1
>> -          if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
>> +          if (N0.getOpcode() == ISD::ADD && N0.getNode()-
>>> hasOneUse()) {
>>            return DAG.getSetCC(VT, N0.getOperand(0),
>>                              DAG.getConstant(RHSC->getValue()-LHSR-
>>> getValue(),
>>                                N0.getValueType()), Cond);
>> @@ -1585,7 +1585,7 @@
>>
>>        // Turn (C1-X) == C2 --> X == C1-C2
>>        if (ConstantSDNode *SUBC =
>> dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
>> -          if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
>> +          if (N0.getOpcode() == ISD::SUB && N0.getNode()-
>>> hasOneUse()) {
>>            return
>>              DAG.getSetCC(VT, N0.getOperand(1),
>>                           DAG.getConstant(SUBC->getAPIntValue() -
>> @@ -1604,14 +1604,14 @@
>>        if (DAG.isCommutativeBinOp(N0.getOpcode()))
>>          return DAG.getSetCC(VT, N0.getOperand(0),
>>                          DAG.getConstant(0, N0.getValueType()),
>> Cond);
>> -        else if (N0.Val->hasOneUse()) {
>> +        else if (N0.getNode()->hasOneUse()) {
>>          assert(N0.getOpcode() == ISD::SUB && "Unexpected
>> operation!");
>>          // (Z-X) == X  --> Z == X<<1
>>          SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(),
>>                                     N1,
>>                                     DAG.getConstant(1,
>> getShiftAmountTy()));
>>          if (!DCI.isCalledByLegalizer())
>> -            DCI.AddToWorklist(SH.Val);
>> +            DCI.AddToWorklist(SH.getNode());
>>          return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
>>        }
>>      }
>> @@ -1627,13 +1627,13 @@
>>        if (DAG.isCommutativeBinOp(N1.getOpcode())) {
>>          return DAG.getSetCC(VT, N1.getOperand(0),
>>                          DAG.getConstant(0, N1.getValueType()),
>> Cond);
>> -        } else if (N1.Val->hasOneUse()) {
>> +        } else if (N1.getNode()->hasOneUse()) {
>>          assert(N1.getOpcode() == ISD::SUB && "Unexpected
>> operation!");
>>          // X == (Z-X)  --> X<<1 == Z
>>          SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
>>                                     DAG.getConstant(1,
>> getShiftAmountTy()));
>>          if (!DCI.isCalledByLegalizer())
>> -            DCI.AddToWorklist(SH.Val);
>> +            DCI.AddToWorklist(SH.getNode());
>>          return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
>>        }
>>      }
>> @@ -1649,7 +1649,7 @@
>>      Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
>>      N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1,
>> MVT::i1));
>>      if (!DCI.isCalledByLegalizer())
>> -        DCI.AddToWorklist(Temp.Val);
>> +        DCI.AddToWorklist(Temp.getNode());
>>      break;
>>    case ISD::SETNE:  // X != Y   -->  (X^Y)
>>      N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
>> @@ -1659,21 +1659,21 @@
>>      Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1,
>> MVT::i1));
>>      N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
>>      if (!DCI.isCalledByLegalizer())
>> -        DCI.AddToWorklist(Temp.Val);
>> +        DCI.AddToWorklist(Temp.getNode());
>>      break;
>>    case ISD::SETLT:  // X <s Y   --> X == 1 & Y == 0  -->  Y^1 & X
>>    case ISD::SETUGT: // X >u Y   --> X == 1 & Y == 0  -->  Y^1 & X
>>      Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1,
>> MVT::i1));
>>      N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
>>      if (!DCI.isCalledByLegalizer())
>> -        DCI.AddToWorklist(Temp.Val);
>> +        DCI.AddToWorklist(Temp.getNode());
>>      break;
>>    case ISD::SETULE: // X <=u Y  --> X == 0 | Y == 1  -->  X^1 | Y
>>    case ISD::SETGE:  // X >=s Y  --> X == 0 | Y == 1  -->  X^1 | Y
>>      Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1,
>> MVT::i1));
>>      N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
>>      if (!DCI.isCalledByLegalizer())
>> -        DCI.AddToWorklist(Temp.Val);
>> +        DCI.AddToWorklist(Temp.getNode());
>>      break;
>>    case ISD::SETUGE: // X >=u Y  --> X == 1 | Y == 0  -->  Y^1 | X
>>    case ISD::SETLE:  // X <=s Y  --> X == 1 | Y == 0  -->  Y^1 | X
>> @@ -1683,7 +1683,7 @@
>>    }
>>    if (VT != MVT::i1) {
>>      if (!DCI.isCalledByLegalizer())
>> -        DCI.AddToWorklist(N0.Val);
>> +        DCI.AddToWorklist(N0.getNode());
>>      // FIXME: If running after legalize, we probably can't do this.
>>      N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
>>    }
>> @@ -1708,13 +1708,13 @@
>>  if (N->getOpcode() == ISD::ADD) {
>>    SDValue N1 = N->getOperand(0);
>>    SDValue N2 = N->getOperand(1);
>> -    if (isGAPlusOffset(N1.Val, GA, Offset)) {
>> +    if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
>>      ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
>>      if (V) {
>>        Offset += V->getSignExtended();
>>        return true;
>>      }
>> -    } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
>> +    } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
>>      ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
>>      if (V) {
>>        Offset += V->getSignExtended();
>> @@ -1732,7 +1732,7 @@
>> bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base,
>>                                       unsigned Bytes, int Dist,
>>                                       const MachineFrameInfo *MFI)
>> const {
>> -  if (LD->getOperand(0).Val != Base->getOperand(0).Val)
>> +  if (LD->getOperand(0).getNode() != Base->getOperand(0).getNode())
>>    return false;
>>  MVT VT = LD->getValueType(0);
>>  if (VT.getSizeInBits() / 8 != Bytes)
>> @@ -1755,8 +1755,8 @@
>>  GlobalValue *GV2 = NULL;
>>  int64_t Offset1 = 0;
>>  int64_t Offset2 = 0;
>> -  bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
>> -  bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
>> +  bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1);
>> +  bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
>>  if (isGA1 && isGA2 && GV1 == GV2)
>>    return Offset1 == (Offset2 + Dist*Bytes);
>>  return false;
>> @@ -1979,7 +1979,7 @@
>>    // For example, on X86 we might have an 'rI' constraint.  If the
>> operand
>>    // is an integer in the range [0..31] we want to use I (saving a
>> load
>>    // of a register), otherwise we must use 'r'.
>> -    if (CType == TargetLowering::C_Other && Op.Val) {
>> +    if (CType == TargetLowering::C_Other && Op.getNode()) {
>>      assert(OpInfo.Codes[i].size() == 1 &&
>>             "Unhandled multi-letter 'other' constraint");
>>      std::vector<SDValue> ResultOps;
>> @@ -2273,34 +2273,34 @@
>>  else if (isOperationLegal(ISD::SMUL_LOHI, VT))
>>    Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT),
>>                              N->getOperand(0),
>> -                              DAG.getConstant(magics.m, VT)).Val,  
>> 1);
>> +                              DAG.getConstant(magics.m,
>> VT)).getNode(), 1);
>>  else
>>    return SDValue();       // No mulhs or equvialent
>>  // If d > 0 and m < 0, add the numerator
>>  if (d > 0 && magics.m < 0) {
>>    Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
>>    if (Created)
>> -      Created->push_back(Q.Val);
>> +      Created->push_back(Q.getNode());
>>  }
>>  // If d < 0 and m > 0, subtract the numerator.
>>  if (d < 0 && magics.m > 0) {
>>    Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
>>    if (Created)
>> -      Created->push_back(Q.Val);
>> +      Created->push_back(Q.getNode());
>>  }
>>  // Shift right algebraic if shift value is nonzero
>>  if (magics.s > 0) {
>>    Q = DAG.getNode(ISD::SRA, VT, Q,
>>                    DAG.getConstant(magics.s, getShiftAmountTy()));
>>    if (Created)
>> -      Created->push_back(Q.Val);
>> +      Created->push_back(Q.getNode());
>>  }
>>  // Extract the sign bit and add it to the quotient
>>  SDValue T =
>>    DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
>>                                                 getShiftAmountTy()));
>>  if (Created)
>> -    Created->push_back(T.Val);
>> +    Created->push_back(T.getNode());
>>  return DAG.getNode(ISD::ADD, VT, Q, T);
>> }
>>
>> @@ -2327,11 +2327,11 @@
>>  else if (isOperationLegal(ISD::UMUL_LOHI, VT))
>>    Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT),
>>                              N->getOperand(0),
>> -                              DAG.getConstant(magics.m, VT)).Val,  
>> 1);
>> +                              DAG.getConstant(magics.m,
>> VT)).getNode(), 1);
>>  else
>>    return SDValue();       // No mulhu or equvialent
>>  if (Created)
>> -    Created->push_back(Q.Val);
>> +    Created->push_back(Q.getNode());
>>
>>  if (magics.a == 0) {
>>    return DAG.getNode(ISD::SRL, VT, Q,
>> @@ -2339,14 +2339,14 @@
>>  } else {
>>    SDValue NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
>>    if (Created)
>> -      Created->push_back(NPQ.Val);
>> +      Created->push_back(NPQ.getNode());
>>    NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
>>                      DAG.getConstant(1, getShiftAmountTy()));
>>    if (Created)
>> -      Created->push_back(NPQ.Val);
>> +      Created->push_back(NPQ.getNode());
>>    NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
>>    if (Created)
>> -      Created->push_back(NPQ.Val);
>> +      Created->push_back(NPQ.getNode());
>>    return DAG.getNode(ISD::SRL, VT, NPQ,
>>                       DAG.getConstant(magics.s-1,
>> getShiftAmountTy()));
>>  }
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -529,7 +529,7 @@
>>
>>
>> SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
>> -  SDNode *N = Op.Val;
>> +  SDNode *N = Op.getNode();
>>
>>  if (N->isMachineOpcode())
>>    return NULL;   // Already selected.
>> @@ -729,11 +729,11 @@
>>    SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
>>    SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other,
>> MVT::Flag, Ops, 5);
>>    Chain = SDValue(ResNode, 0);
>> -    if (Op.Val->getNumValues() == 2) {
>> +    if (Op.getNode()->getNumValues() == 2) {
>>      InFlag = SDValue(ResNode, 1);
>> -      ReplaceUses(SDValue(Op.Val, 1), InFlag);
>> +      ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
>>    }
>> -    ReplaceUses(SDValue(Op.Val, 0), SDValue(Chain.Val,
>> Chain.getResNo()));
>> +    ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(),
>> Chain.getResNo()));
>>    return NULL;
>>  }
>>  case ARMISD::CMOV: {
>> @@ -763,7 +763,7 @@
>>      SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
>>                               cast<ConstantSDNode>(N2)-
>>> getValue()), MVT::i32);
>>      SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3,
>> InFlag };
>> -      return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCs, MVT::i32,
>> Ops, 7);
>> +      return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs,
>> MVT::i32, Ops, 7);
>>    }
>>
>>    // Pattern: (ARMcmov:i32 GPR:i32:$false,
>> @@ -774,16 +774,16 @@
>>    // Pattern complexity = 10  cost = 1  size = 0
>>    if (VT == MVT::i32 &&
>>        N3.getOpcode() == ISD::Constant &&
>> -        Predicate_so_imm(N3.Val)) {
>> +        Predicate_so_imm(N3.getNode())) {
>>      AddToISelQueue(N0);
>>      AddToISelQueue(InFlag);
>>      SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
>>                               cast<ConstantSDNode>(N1)-
>>> getValue()), MVT::i32);
>> -      Tmp1 = Transform_so_imm_XFORM(Tmp1.Val);
>> +      Tmp1 = Transform_so_imm_XFORM(Tmp1.getNode());
>>      SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
>>                               cast<ConstantSDNode>(N2)-
>>> getValue()), MVT::i32);
>>      SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
>> -      return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCi, MVT::i32,
>> Ops, 5);
>> +      return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCi,
>> MVT::i32, Ops, 5);
>>    }
>>
>>    // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true,
>> (imm:i32):$cc)
>> @@ -815,7 +815,7 @@
>>      Opc = ARM::FCPYDcc;
>>      break;
>>    }
>> -    return CurDAG->SelectNodeTo(Op.Val, Opc, VT, Ops, 5);
>> +    return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
>>  }
>>  case ARMISD::CNEG: {
>>    MVT VT = Op.getValueType();
>> @@ -844,7 +844,7 @@
>>      Opc = ARM::FNEGDcc;
>>      break;
>>    }
>> -    return CurDAG->SelectNodeTo(Op.Val, Opc, VT, Ops, 5);
>> +    return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
>>  }
>>  }
>>  return SelectCode(Op);
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -400,7 +400,7 @@
>> /// ARMISD:CALL <- callseq_end chain. Also add input and output
>> parameter
>> /// nodes.
>> SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
>> -  MVT RetVT= Op.Val->getValueType(0);
>> +  MVT RetVT= Op.getNode()->getValueType(0);
>>  SDValue Chain    = Op.getOperand(0);
>>  unsigned CallConv  = cast<ConstantSDNode>(Op.getOperand(1))-
>>> getValue();
>>  assert((CallConv == CallingConv::C ||
>> @@ -597,7 +597,7 @@
>>    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
>>
>> RegsToPass[i].second.getValueType()));
>>
>> -  if (InFlag.Val)
>> +  if (InFlag.getNode())
>>    Ops.push_back(InFlag);
>>  // Returns a chain and a flag for retval copy to use.
>>  Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag),
>> @@ -621,7 +621,7 @@
>>  case MVT::i32:
>>    Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32,
>> InFlag).getValue(1);
>>    ResultVals.push_back(Chain.getValue(0));
>> -    if (Op.Val->getValueType(1) == MVT::i32) {
>> +    if (Op.getNode()->getValueType(1) == MVT::i32) {
>>      // Returns a i64 value.
>>      Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32,
>>                                 Chain.getValue(2)).getValue(1);
>> @@ -981,7 +981,7 @@
>>  unsigned ArgOffset = 0;   // Frame mechanisms handle retaddr slot
>>  unsigned NumGPRs = 0;     // GPRs used for parameter passing.
>>
>> -  unsigned NumArgs = Op.Val->getNumValues()-1;
>> +  unsigned NumArgs = Op.getNode()->getNumValues()-1;
>>  for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
>>    ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo,
>>                                             NumGPRs, ArgOffset));
>> @@ -1029,7 +1029,7 @@
>>  ArgValues.push_back(Root);
>>
>>  // Return the new list of results.
>> -  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
>> +  return DAG.getMergeValues(Op.getNode()->getVTList(),  
>> &ArgValues[0],
>>                            ArgValues.size());
>> }
>>
>> @@ -1037,7 +1037,7 @@
>> static bool isFloatingPointZero(SDValue Op) {
>>  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
>>    return CFP->getValueAPF().isPosZero();
>> -  else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
>> +  else if (ISD::isEXTLoad(Op.getNode()) ||
>> ISD::isNON_EXTLoad(Op.getNode())) {
>>    // Maybe this has already been legalized into the constant pool?
>>    if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
>>      SDValue WrapperOp = Op.getOperand(1).getOperand(0);
>> @@ -1058,7 +1058,7 @@
>> /// the given operands.
>> static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
>>                           SDValue &ARMCC, SelectionDAG &DAG, bool
>> isThumb) {
>> -  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) {
>> +  if (ConstantSDNode *RHSC =
>> dyn_cast<ConstantSDNode>(RHS.getNode())) {
>>    unsigned C = RHSC->getValue();
>>    if (!isLegalCmpImmediate(C, isThumb)) {
>>      // Constant does not fit, try adjusting it by one?
>> @@ -1362,7 +1362,7 @@
>>                              &Op, 1);
>>
>>  // Merge the pieces into a single i64 value.
>> -  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt,
>> Cvt.getValue(1)).Val;
>> +  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt,
>> Cvt.getValue(1)).getNode();
>> }
>>
>> static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const
>> ARMSubtarget *ST) {
>> @@ -1393,7 +1393,7 @@
>>  Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
>>
>>  // Merge the pieces into a single i64 value.
>> - return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).Val;
>> + return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).getNode();
>> }
>>
>>
>> @@ -1424,9 +1424,9 @@
>>
>>
>>  // FIXME: Remove these when LegalizeDAGTypes lands.
>> -  case ISD::BIT_CONVERT:   return SDValue(ExpandBIT_CONVERT(Op.Val,
>> DAG), 0);
>> +  case ISD::BIT_CONVERT:   return
>> SDValue(ExpandBIT_CONVERT(Op.getNode(), DAG), 0);
>>  case ISD::SRL:
>> -  case ISD::SRA:           return SDValue(ExpandSRx(Op.Val,
>> DAG,Subtarget),0);
>> +  case ISD::SRA:           return SDValue(ExpandSRx(Op.getNode(),
>> DAG,Subtarget),0);
>>  }
>>  return SDValue();
>> }
>> @@ -1734,7 +1734,7 @@
>>    return false;
>>
>>  bool isInc;
>> -  bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad,
>> Base, Offset,
>> +  bool isLegal = getIndexedAddressParts(Ptr.getNode(), VT,
>> isSEXTLoad, Base, Offset,
>>                                        isInc, DAG);
>>  if (isLegal) {
>>    AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
>>
>> Modified: llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -75,7 +75,7 @@
>>          Result |= 1 << i;
>>          if (((Constant >> 8*i) & 0xFF) == 0xFF) {
>>            // If the entire byte is set, zapnot the byte.
>> -          } else if (LHS.Val == 0) {
>> +          } else if (LHS.getNode() == 0) {
>>            // Otherwise, if the mask was previously validated, we
>> know its okay
>>            // to zapnot this entire byte even though all the bits
>> aren't set.
>>          } else {
>> @@ -242,7 +242,7 @@
>> // Select - Convert the specified operand from a target-independent
>> to a
>> // target-specific node if it hasn't already been changed.
>> SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
>> -  SDNode *N = Op.Val;
>> +  SDNode *N = Op.getNode();
>>  if (N->isMachineOpcode()) {
>>    return NULL;   // Already selected.
>>  }
>> @@ -345,7 +345,7 @@
>>  }
>>
>>  case ISD::SETCC:
>> -    if (N->getOperand(0).Val->getValueType(0).isFloatingPoint()) {
>> +    if (N->getOperand(0).getNode()-
>>> getValueType(0).isFloatingPoint()) {
>>      ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))-
>>> get();
>>
>>      unsigned Opc = Alpha::WTF;
>> @@ -460,7 +460,7 @@
>> void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
>>  //TODO: add flag stuff to prevent nondeturministic breakage!
>>
>> -  SDNode *N = Op.Val;
>> +  SDNode *N = Op.getNode();
>>  SDValue Chain = N->getOperand(0);
>>  SDValue Addr = N->getOperand(1);
>>  SDValue InFlag(0,0);  // Null incoming flag value.
>>
>> Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -215,7 +215,7 @@
>>  unsigned args_float[] = {
>>    Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20,
>> Alpha::F21};
>>
>> -  for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo !=
>> e; ++ArgNo) {
>> +  for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1;
>> ArgNo != e; ++ArgNo) {
>>    SDValue argt;
>>    MVT ObjectVT = Op.getValue(ArgNo).getValueType();
>>    SDValue ArgVal;
>> @@ -255,7 +255,7 @@
>>  // If the functions takes variable number of arguments, copy all
>> regs to stack
>>  bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))-
>>> getValue() != 0;
>>  if (isVarArg) {
>> -    VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
>> +    VarArgsOffset = (Op.getNode()->getNumValues()-1) * 8;
>>    std::vector<SDValue> LS;
>>    for (int i = 0; i < 6; ++i) {
>>      if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
>> @@ -281,7 +281,7 @@
>>  ArgValues.push_back(Root);
>>
>>  // Return the new list of results.
>> -  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
>> +  return DAG.getMergeValues(Op.getNode()->getVTList(),  
>> &ArgValues[0],
>>                            ArgValues.size());
>> }
>>
>> @@ -491,10 +491,10 @@
>>  case ISD::SREM:
>>    //Expand only on constant case
>>    if (Op.getOperand(1).getOpcode() == ISD::Constant) {
>> -      MVT VT = Op.Val->getValueType(0);
>> -      SDValue Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
>> -        BuildUDIV(Op.Val, DAG, NULL) :
>> -        BuildSDIV(Op.Val, DAG, NULL);
>> +      MVT VT = Op.getNode()->getValueType(0);
>> +      SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ?
>> +        BuildUDIV(Op.getNode(), DAG, NULL) :
>> +        BuildSDIV(Op.getNode(), DAG, NULL);
>>      Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
>>      Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
>>      return Tmp1;
>> @@ -504,8 +504,8 @@
>>  case ISD::UDIV:
>>    if (Op.getValueType().isInteger()) {
>>      if (Op.getOperand(1).getOpcode() == ISD::Constant)
>> -        return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG,
>> NULL)
>> -          : BuildUDIV(Op.Val, DAG, NULL);
>> +        return Op.getOpcode() == ISD::SDIV ?
>> BuildSDIV(Op.getNode(), DAG, NULL)
>> +          : BuildUDIV(Op.getNode(), DAG, NULL);
>>      const char* opstr = 0;
>>      switch (Op.getOpcode()) {
>>      case ISD::UREM: opstr = "__remqu"; break;
>> @@ -522,7 +522,7 @@
>>
>>  case ISD::VAARG: {
>>    SDValue Chain, DataPtr;
>> -    LowerVAARG(Op.Val, Chain, DataPtr, DAG);
>> +    LowerVAARG(Op.getNode(), Chain, DataPtr, DAG);
>>
>>    SDValue Result;
>>    if (Op.getValueType() == MVT::i32)
>> @@ -578,7 +578,7 @@
>>
>>  SDValue Chain, DataPtr;
>>  LowerVAARG(N, Chain, DataPtr, DAG);
>> -  return DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL,
>> 0).Val;
>> +  return DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL,
>> 0).getNode();
>> }
>>
>>
>>
>> Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -579,7 +579,7 @@
>> */
>> SDNode *
>> SPUDAGToDAGISel::Select(SDValue Op) {
>> -  SDNode *N = Op.Val;
>> +  SDNode *N = Op.getNode();
>>  unsigned Opc = N->getOpcode();
>>  int n_ops = -1;
>>  unsigned NewOpc;
>> @@ -669,9 +669,9 @@
>>      MVT VT = Op.getValueType();
>>
>>      DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = ");
>> -      DEBUG(Op.getOperand(0).Val->dump(CurDAG));
>> +      DEBUG(Op.getOperand(0).getNode()->dump(CurDAG));
>>      DEBUG(cerr << "\nOp1 = ");
>> -      DEBUG(Op.getOperand(1).Val->dump(CurDAG));
>> +      DEBUG(Op.getOperand(1).getNode()->dump(CurDAG));
>>      DEBUG(cerr << "\n");
>>
>>      if (Op1.getOpcode() == ISD::Constant) {
>>
>> Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -503,7 +503,7 @@
>>  SDValue chain = LSN->getChain();
>>
>>  if (basePtr.getOpcode() == ISD::ADD) {
>> -    SDValue Op1 = basePtr.Val->getOperand(1);
>> +    SDValue Op1 = basePtr.getNode()->getOperand(1);
>>
>>    if (Op1.getOpcode() == ISD::Constant || Op1.getOpcode() ==
>> ISD::TargetConstant) {
>>      const ConstantSDNode *CN =
>> cast<ConstantSDNode>(basePtr.getOperand(1));
>> @@ -579,7 +579,7 @@
>>  LoadSDNode *LN = cast<LoadSDNode>(Op);
>>  SDValue the_chain = LN->getChain();
>>  MVT VT = LN->getMemoryVT();
>> -  MVT OpVT = Op.Val->getValueType(0);
>> +  MVT OpVT = Op.getNode()->getValueType(0);
>>  ISD::LoadExtType ExtType = LN->getExtensionType();
>>  unsigned alignment = LN->getAlignment();
>>  SDValue Ops[8];
>> @@ -591,7 +591,7 @@
>>    SDValue result =
>>      AlignedLoad(Op, DAG, ST, LN,alignment, offset, rotamt, VT,
>> was16aligned);
>>
>> -    if (result.Val == 0)
>> +    if (result.getNode() == 0)
>>      return result;
>>
>>    the_chain = result.getValue(1);
>> @@ -708,7 +708,7 @@
>>      AlignedLoad(Op, DAG, ST, SN, alignment,
>>                  chunk_offset, slot_offset, VT, was16aligned);
>>
>> -    if (alignLoadVec.Val == 0)
>> +    if (alignLoadVec.getNode() == 0)
>>      return alignLoadVec;
>>
>>    LoadSDNode *LN = cast<LoadSDNode>(alignLoadVec);
>> @@ -736,7 +736,7 @@
>>    // Otherwise generate a D-form address with the slot offset
>> relative
>>    // to the stack pointer, which is always aligned.
>>    DEBUG(cerr << "CellSPU LowerSTORE: basePtr = ");
>> -    DEBUG(basePtr.Val->dump(&DAG));
>> +    DEBUG(basePtr.getNode()->dump(&DAG));
>>    DEBUG(cerr << "\n");
>>
>>    if (basePtr.getOpcode() == SPUISD::IndirectAddr ||
>> @@ -859,7 +859,7 @@
>> static SDValue
>> LowerConstant(SDValue Op, SelectionDAG &DAG) {
>>  MVT VT = Op.getValueType();
>> -  ConstantSDNode *CN = cast<ConstantSDNode>(Op.Val);
>> +  ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode());
>>
>>  if (VT == MVT::i64) {
>>    SDValue T = DAG.getConstant(CN->getValue(), MVT::i64);
>> @@ -880,7 +880,7 @@
>> static SDValue
>> LowerConstantFP(SDValue Op, SelectionDAG &DAG) {
>>  MVT VT = Op.getValueType();
>> -  ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.Val);
>> +  ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.getNode());
>>
>>  assert((FP != 0) &&
>>         "LowerConstantFP: Node is not ConstantFPSDNode");
>> @@ -932,7 +932,7 @@
>>  MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
>>
>>  // Add DAG nodes to load the arguments or copy them out of
>> registers.
>> -  for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo !=
>> e; ++ArgNo) {
>> +  for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1;
>> ArgNo != e; ++ArgNo) {
>>    SDValue ArgVal;
>>    bool needsLoad = false;
>>    MVT ObjectVT = Op.getValue(ArgNo).getValueType();
>> @@ -1061,7 +1061,7 @@
>>  ArgValues.push_back(Root);
>>
>>  // Return the new list of results.
>> -  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
>> +  return DAG.getMergeValues(Op.getNode()->getVTList(),  
>> &ArgValues[0],
>>                            ArgValues.size());
>> }
>>
>> @@ -1076,7 +1076,7 @@
>>      (Addr << 14 >> 14) != Addr)
>>    return 0;  // Top 14 bits have to be sext of immediate.
>>
>> -  return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
>> +  return DAG.getConstant((int)C->getValue() >> 2,
>> MVT::i32).getNode();
>> }
>>
>> static
>> @@ -1226,7 +1226,7 @@
>>    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
>>
>> RegsToPass[i].second.getValueType()));
>>
>> -  if (InFlag.Val)
>> +  if (InFlag.getNode())
>>    Ops.push_back(InFlag);
>>  // Returns a chain and a flag for retval copy to use.
>>  Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag),
>> @@ -1237,18 +1237,18 @@
>>                             DAG.getConstant(NumStackBytes, PtrVT),
>>                             DAG.getConstant(0, PtrVT),
>>                             InFlag);
>> -  if (Op.Val->getValueType(0) != MVT::Other)
>> +  if (Op.getNode()->getValueType(0) != MVT::Other)
>>    InFlag = Chain.getValue(1);
>>
>>  SDValue ResultVals[3];
>>  unsigned NumResults = 0;
>>
>>  // If the call has results, copy the values out of the ret val
>> registers.
>> -  switch (Op.Val->getValueType(0).getSimpleVT()) {
>> +  switch (Op.getNode()->getValueType(0).getSimpleVT()) {
>>  default: assert(0 && "Unexpected ret value!");
>>  case MVT::Other: break;
>>  case MVT::i32:
>> -    if (Op.Val->getValueType(1) == MVT::i32) {
>> +    if (Op.getNode()->getValueType(1) == MVT::i32) {
>>      Chain = DAG.getCopyFromReg(Chain, SPU::R4, MVT::i32,
>> InFlag).getValue(1);
>>      ResultVals[0] = Chain.getValue(0);
>>      Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i32,
>> @@ -1268,7 +1268,7 @@
>>    break;
>>  case MVT::f32:
>>  case MVT::f64:
>> -    Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.Val-
>>> getValueType(0),
>> +    Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.getNode()-
>>> getValueType(0),
>>                               InFlag).getValue(1);
>>    ResultVals[0] = Chain.getValue(0);
>>    NumResults = 1;
>> @@ -1278,7 +1278,7 @@
>>  case MVT::v4i32:
>>  case MVT::v8i16:
>>  case MVT::v16i8:
>> -    Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.Val-
>>> getValueType(0),
>> +    Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.getNode()-
>>> getValueType(0),
>>                                   InFlag).getValue(1);
>>    ResultVals[0] = Chain.getValue(0);
>>    NumResults = 1;
>> @@ -1301,7 +1301,7 @@
>>  unsigned CC = DAG.getMachineFunction().getFunction()-
>>> getCallingConv();
>>  bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
>>  CCState CCInfo(CC, isVarArg, TM, RVLocs);
>> -  CCInfo.AnalyzeReturn(Op.Val, RetCC_SPU);
>> +  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SPU);
>>
>>  // If this is the first return lowered for this function, add the
>> regs to the
>>  // liveout set for the function.
>> @@ -1321,7 +1321,7 @@
>>    Flag = Chain.getValue(1);
>>  }
>>
>> -  if (Flag.Val)
>> +  if (Flag.getNode())
>>    return DAG.getNode(SPUISD::RET_FLAG, MVT::Other, Chain, Flag);
>>  else
>>    return DAG.getNode(SPUISD::RET_FLAG, MVT::Other, Chain);
>> @@ -1339,13 +1339,13 @@
>>  // Check to see if this buildvec has a single non-undef value in
>> its elements.
>>  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
>>    if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
>> -    if (OpVal.Val == 0)
>> +    if (OpVal.getNode() == 0)
>>      OpVal = N->getOperand(i);
>>    else if (OpVal != N->getOperand(i))
>>      return 0;
>>  }
>>
>> -  if (OpVal.Val != 0) {
>> +  if (OpVal.getNode() != 0) {
>>    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
>>      return CN;
>>    }
>> @@ -1599,7 +1599,7 @@
>>  uint64_t UndefBits[2];
>>  uint64_t SplatBits, SplatUndef;
>>  int SplatSize;
>> -  if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)
>> +  if (GetConstantBuildVectorBits(Op.getNode(), VectorBits,  
>> UndefBits)
>>      || !isConstantSplat(VectorBits, UndefBits,
>>                          VT.getVectorElementType().getSizeInBits(),
>>                          SplatBits, SplatUndef, SplatSize))
>> @@ -1842,11 +1842,11 @@
>> static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
>>  SDValue Op0 = Op.getOperand(0);                     // Op0 = the
>> scalar
>>
>> -  if (Op0.Val->getOpcode() == ISD::Constant) {
>> +  if (Op0.getNode()->getOpcode() == ISD::Constant) {
>>    // For a constant, build the appropriate constant vector, which
>> will
>>    // eventually simplify to a vector register load.
>>
>> -    ConstantSDNode *CN = cast<ConstantSDNode>(Op0.Val);
>> +    ConstantSDNode *CN = cast<ConstantSDNode>(Op0.getNode());
>>    SmallVector<SDValue, 16> ConstVecValues;
>>    MVT VT;
>>    size_t n_copies;
>> @@ -2447,25 +2447,25 @@
>>
>>  ConstVec = Op.getOperand(0);
>>  Arg = Op.getOperand(1);
>> -  if (ConstVec.Val->getOpcode() != ISD::BUILD_VECTOR) {
>> -    if (ConstVec.Val->getOpcode() == ISD::BIT_CONVERT) {
>> +  if (ConstVec.getNode()->getOpcode() != ISD::BUILD_VECTOR) {
>> +    if (ConstVec.getNode()->getOpcode() == ISD::BIT_CONVERT) {
>>      ConstVec = ConstVec.getOperand(0);
>>    } else {
>>      ConstVec = Op.getOperand(1);
>>      Arg = Op.getOperand(0);
>> -      if (ConstVec.Val->getOpcode() == ISD::BIT_CONVERT) {
>> +      if (ConstVec.getNode()->getOpcode() == ISD::BIT_CONVERT) {
>>        ConstVec = ConstVec.getOperand(0);
>>      }
>>    }
>>  }
>>
>> -  if (ConstVec.Val->getOpcode() == ISD::BUILD_VECTOR) {
>> +  if (ConstVec.getNode()->getOpcode() == ISD::BUILD_VECTOR) {
>>    uint64_t VectorBits[2];
>>    uint64_t UndefBits[2];
>>    uint64_t SplatBits, SplatUndef;
>>    int SplatSize;
>>
>> -    if (!GetConstantBuildVectorBits(ConstVec.Val, VectorBits,
>> UndefBits)
>> +    if (!GetConstantBuildVectorBits(ConstVec.getNode(), VectorBits,
>> UndefBits)
>>        && isConstantSplat(VectorBits, UndefBits,
>>                           VT.getVectorElementType().getSizeInBits(),
>>                           SplatBits, SplatUndef, SplatSize)) {
>> @@ -2477,7 +2477,7 @@
>>      for (size_t i = 0; i < tcVecSize; ++i)
>>        tcVec[i] = tc;
>>
>> -      return DAG.getNode(Op.Val->getOpcode(), VT, Arg,
>> +      return DAG.getNode(Op.getNode()->getOpcode(), VT, Arg,
>>                         DAG.getNode(ISD::BUILD_VECTOR, VT, tcVec,
>> tcVecSize));
>>    }
>>  }
>> @@ -2632,8 +2632,8 @@
>>  default: {
>>    cerr << "SPUTargetLowering::LowerOperation(): need to lower this!
>> \n";
>>    cerr << "Op.getOpcode() = " << Opc << "\n";
>> -    cerr << "*Op.Val:\n";
>> -    Op.Val->dump();
>> +    cerr << "*Op.getNode():\n";
>> +    Op.getNode()->dump();
>>    abort();
>>  }
>>  case ISD::LOAD:
>> @@ -2796,7 +2796,7 @@
>>      DEBUG(cerr << "Replace: ");
>>      DEBUG(N->dump(&DAG));
>>      DEBUG(cerr << "\nWith:    ");
>> -      DEBUG(Op0.Val->dump(&DAG));
>> +      DEBUG(Op0.getNode()->dump(&DAG));
>>      DEBUG(cerr << "\n");
>>
>>      return Op0;
>> @@ -2813,7 +2813,7 @@
>>        DEBUG(cerr << "Replace: ");
>>        DEBUG(N->dump(&DAG));
>>        DEBUG(cerr << "\nWith:    ");
>> -        DEBUG(Op0.Val->dump(&DAG));
>> +        DEBUG(Op0.getNode()->dump(&DAG));
>>        DEBUG(cerr << "\n");
>>
>>        return Op0;
>> @@ -2871,11 +2871,11 @@
>>  }
>>  // Otherwise, return unchanged.
>> #if 1
>> -  if (Result.Val) {
>> +  if (Result.getNode()) {
>>    DEBUG(cerr << "\nReplace.SPU: ");
>>    DEBUG(N->dump(&DAG));
>>    DEBUG(cerr << "\nWith:        ");
>> -    DEBUG(Result.Val->dump(&DAG));
>> +    DEBUG(Result.getNode()->dump(&DAG));
>>    DEBUG(cerr << "\n");
>>  }
>> #endif
>>
>> Modified: llvm/trunk/lib/Target/CellSPU/SPUOperands.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUOperands.td?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/CellSPU/SPUOperands.td (original)
>> +++ llvm/trunk/lib/Target/CellSPU/SPUOperands.td Thu Aug 28 16:40:38
>> 2008
>> @@ -24,13 +24,13 @@
>>         && "LO16_vec got something other than a BUILD_VECTOR");
>>
>>  // Get first constant operand...
>> -  for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 &&
>> i != e; ++i) {
>> +  for (unsigned i = 0, e = N->getNumOperands(); OpVal.getNode() ==
>> 0 && i != e; ++i) {
>>    if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
>> -    if (OpVal.Val == 0)
>> +    if (OpVal.getNode() == 0)
>>      OpVal = N->getOperand(i);
>>  }
>>
>> -  assert(OpVal.Val != 0 && "LO16_vec did not locate a <defined>
>> node");
>> +  assert(OpVal.getNode() != 0 && "LO16_vec did not locate a
>> <defined> node");
>>  ConstantSDNode *CN = cast<ConstantSDNode>(OpVal);
>>  return getI32Imm((unsigned)CN->getValue() & 0xffff);
>> }]>;
>> @@ -49,13 +49,13 @@
>>         && "HI16_vec got something other than a BUILD_VECTOR");
>>
>>  // Get first constant operand...
>> -  for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 &&
>> i != e; ++i) {
>> +  for (unsigned i = 0, e = N->getNumOperands(); OpVal.getNode() ==
>> 0 && i != e; ++i) {
>>    if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
>> -    if (OpVal.Val == 0)
>> +    if (OpVal.getNode() == 0)
>>      OpVal = N->getOperand(i);
>>  }
>>
>> -  assert(OpVal.Val != 0 && "HI16_vec did not locate a <defined>
>> node");
>> +  assert(OpVal.getNode() != 0 && "HI16_vec did not locate a
>> <defined> node");
>>  ConstantSDNode *CN = cast<ConstantSDNode>(OpVal);
>>  return getI32Imm((unsigned)CN->getValue() >> 16);
>> }]>;
>> @@ -244,7 +244,7 @@
>> // incoming constant being a 16-bit quantity, where the upper and
>> lower bytes
>> // are EXACTLY the same (e.g., 0x2a2a)
>> def v16i8SExt8Imm: PatLeaf<(build_vector), [{
>> -  return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
>> +  return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
>> }], v16i8SExt8Imm_xform>;
>>
>> // v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit
>> @@ -259,7 +259,7 @@
>> // incoming constant being a 16-bit quantity, where the upper and
>> lower bytes
>> // are EXACTLY the same (e.g., 0x2a2a)
>> def v16i8U8Imm: PatLeaf<(build_vector), [{
>> -  return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
>> +  return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
>> }], v16i8U8Imm_xform>;
>>
>> // v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign
>> extended
>> @@ -271,7 +271,7 @@
>> // v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate
>> constant
>> // load, works in conjunction with its transform function.
>> def v8i16SExt8Imm: PatLeaf<(build_vector), [{
>> -  return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).Val != 0;
>> +  return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).getNode() != 0;
>> }], v8i16SExt8Imm_xform>;
>>
>> // v8i16SExt10Imm_xform function: convert build_vector to 16-bit
>> sign extended
>> @@ -283,7 +283,7 @@
>> // v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate
>> constant
>> // load, works in conjunction with its transform function.
>> def v8i16SExt10Imm: PatLeaf<(build_vector), [{
>> -  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
>> +  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
>> }], v8i16SExt10Imm_xform>;
>>
>> // v8i16Uns10Imm_xform function: convert build_vector to 16-bit
>> unsigned
>> @@ -295,7 +295,7 @@
>> // v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate
>> constant
>> // load, works in conjunction with its transform function.
>> def v8i16Uns10Imm: PatLeaf<(build_vector), [{
>> -  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
>> +  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
>> }], v8i16Uns10Imm_xform>;
>>
>> // v8i16SExt16Imm_xform function: convert build_vector to 16-bit
>> sign extended
>> @@ -307,7 +307,7 @@
>> // v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate
>> constant
>> // load, works in conjunction with its transform function.
>> def v8i16SExt16Imm: PatLeaf<(build_vector), [{
>> -  return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).Val != 0;
>> +  return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).getNode() != 0;
>> }], v8i16Uns16Imm_xform>;
>>
>> // v4i32SExt10Imm_xform function: convert build_vector to 10-bit
>> sign extended
>> @@ -319,7 +319,7 @@
>> // v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate
>> constant
>> // load, works in conjunction with its transform function.
>> def v4i32SExt10Imm: PatLeaf<(build_vector), [{
>> -  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
>> +  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
>> }], v4i32SExt10Imm_xform>;
>>
>> // v4i32Uns10Imm_xform function: convert build_vector to 10-bit
>> unsigned
>> @@ -331,7 +331,7 @@
>> // v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate
>> constant
>> // load, works in conjunction with its transform function.
>> def v4i32Uns10Imm: PatLeaf<(build_vector), [{
>> -  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
>> +  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
>> }], v4i32Uns10Imm_xform>;
>>
>> // v4i32SExt16Imm_xform function: convert build_vector to 16-bit
>> sign extended
>> @@ -343,7 +343,7 @@
>> // v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate
>> constant
>> // load, works in conjunction with its transform function.
>> def v4i32SExt16Imm: PatLeaf<(build_vector), [{
>> -  return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).Val != 0;
>> +  return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).getNode() != 0;
>> }], v4i32SExt16Imm_xform>;
>>
>> // v4i32Uns18Imm_xform function: convert build_vector to 18-bit
>> unsigned
>> @@ -355,7 +355,7 @@
>> // v4i32Uns18Imm: Predicate test for 18-bit unsigned immediate
>> constant load,
>> // works in conjunction with its transform function.
>> def v4i32Uns18Imm: PatLeaf<(build_vector), [{
>> -  return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).Val != 0;
>> +  return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).getNode() != 0;
>> }], v4i32Uns18Imm_xform>;
>>
>> // ILHUvec_get_imm xform function: convert build_vector to ILHUvec
>> imm constant
>> @@ -366,7 +366,7 @@
>>
>> /// immILHUvec: Predicate test for a ILHU constant vector.
>> def immILHUvec: PatLeaf<(build_vector), [{
>> -  return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).Val != 0;
>> +  return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).getNode() != 0;
>> }], ILHUvec_get_imm>;
>>
>> // Catch-all for any other i32 vector constants
>> @@ -375,7 +375,7 @@
>> }]>;
>>
>> def v4i32Imm: PatLeaf<(build_vector), [{
>> -  return SPU::get_v4i32_imm(N, *CurDAG).Val != 0;
>> +  return SPU::get_v4i32_imm(N, *CurDAG).getNode() != 0;
>> }], v4i32_get_imm>;
>>
>> // v2i64SExt10Imm_xform function: convert build_vector to 10-bit
>> sign extended
>> @@ -387,7 +387,7 @@
>> // v2i64SExt10Imm: Predicate test for 10-bit sign extended immediate
>> constant
>> // load, works in conjunction with its transform function.
>> def v2i64SExt10Imm: PatLeaf<(build_vector), [{
>> -  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).Val != 0;
>> +  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).getNode() != 0;
>> }], v2i64SExt10Imm_xform>;
>>
>> // v2i64SExt16Imm_xform function: convert build_vector to 16-bit
>> sign extended
>> @@ -399,7 +399,7 @@
>> // v2i64SExt16Imm: Predicate test for 16-bit sign extended immediate
>> constant
>> // load, works in conjunction with its transform function.
>> def v2i64SExt16Imm: PatLeaf<(build_vector), [{
>> -  return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).Val != 0;
>> +  return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).getNode() != 0;
>> }], v2i64SExt16Imm_xform>;
>>
>> // v2i64Uns18Imm_xform function: convert build_vector to 18-bit
>> unsigned
>> @@ -411,12 +411,12 @@
>> // v2i64Uns18Imm: Predicate test for 18-bit unsigned immediate
>> constant load,
>> // works in conjunction with its transform function.
>> def v2i64Uns18Imm: PatLeaf<(build_vector), [{
>> -  return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).Val != 0;
>> +  return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).getNode() != 0;
>> }], v2i64Uns18Imm_xform>;
>>
>> /// immILHUvec: Predicate test for a ILHU constant vector.
>> def immILHUvec_i64: PatLeaf<(build_vector), [{
>> -  return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).Val != 0;
>> +  return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).getNode() != 0;
>> }], ILHUvec_get_imm>;
>>
>> // Catch-all for any other i32 vector constants
>> @@ -425,7 +425,7 @@
>> }]>;
>>
>> def v2i64Imm: PatLeaf<(build_vector), [{
>> -  return SPU::get_v2i64_imm(N, *CurDAG).Val != 0;
>> +  return SPU::get_v2i64_imm(N, *CurDAG).getNode() != 0;
>> }], v2i64_get_imm>;
>>
>> //
>> =
>> =
>> =
>> ----------------------------------------------------------------------=
>> ==//
>>
>> Modified: llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -105,7 +105,7 @@
>> }
>>
>> SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) {
>> -  SDNode *N = Op.Val;
>> +  SDNode *N = Op.getNode();
>>  SDValue Chain = N->getOperand(0);
>>  SDValue Tmp1 = N->getOperand(0);
>>  SDValue Tmp2 = N->getOperand(1);
>> @@ -304,7 +304,7 @@
>> // Select - Convert the specified operand from a target-independent
>> to a
>> // target-specific node if it hasn't already been changed.
>> SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
>> -  SDNode *N = Op.Val;
>> +  SDNode *N = Op.getNode();
>>  if (N->isMachineOpcode())
>>    return NULL;   // Already selected.
>>
>> @@ -367,7 +367,7 @@
>>  }
>>
>>   // Finally, once everything is setup, emit the call itself
>> -   if(InFlag.Val)
>> +   if (InFlag.getNode())
>>     Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other,
>> MVT::Flag,
>>                                             CallOperand, InFlag), 0);
>>   else // there might be no arguments
>>
>> Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -387,8 +387,8 @@
>>        break;
>>      }
>>
>> -      if(ValToStore.Val) {
>> -        if(!StackPtr.Val) {
>> +      if(ValToStore.getNode()) {
>> +        if(!StackPtr.getNode()) {
>>          StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
>>        }
>>        SDValue PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
>> @@ -397,7 +397,7 @@
>>        ArgOffset += ObjSize;
>>      }
>>
>> -      if(ValToConvert.Val) {
>> +      if(ValToConvert.getNode()) {
>>        Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64,
>> ValToConvert));
>>      }
>>    }
>> @@ -471,7 +471,7 @@
>>  CallOperands.push_back(Callee);
>>
>>  // emit the call itself
>> -  if (InFlag.Val)
>> +  if (InFlag.getNode())
>>    CallOperands.push_back(InFlag);
>>  else
>>    assert(0 && "this should never happen!\n");
>>
>> Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -193,7 +193,7 @@
>> SDNode* MipsDAGToDAGISel::
>> Select(SDValue N)
>> {
>> -  SDNode *Node = N.Val;
>> +  SDNode *Node = N.getNode();
>>  unsigned Opcode = Node->getOpcode();
>>
>>  // Dump information about the Node being selected
>> @@ -252,7 +252,7 @@
>>      SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT,
>>                                               SDValue(Carry,0), RHS);
>>
>> -      return CurDAG->SelectNodeTo(N.Val, MOp, VT, MVT::Flag,
>> +      return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, MVT::Flag,
>>                                  LHS, SDValue(AddCarry,0));
>>    }
>>
>> @@ -391,8 +391,8 @@
>>
>>  #ifndef NDEBUG
>>  DOUT << std::string(Indent-2, ' ') << "=> ";
>> -  if (ResNode == NULL || ResNode == N.Val)
>> -    DEBUG(N.Val->dump(CurDAG));
>> +  if (ResNode == NULL || ResNode == N.getNode())
>> +    DEBUG(N.getNode()->dump(CurDAG));
>>  else
>>    DEBUG(ResNode->dump(CurDAG));
>>  DOUT << "\n";
>>
>> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -602,7 +602,7 @@
>>    MFI->CreateFixedObject(VTsize, (VTsize*3));
>>  }
>>
>> -  CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
>> +  CCInfo.AnalyzeCallOperands(Op.getNode(), CC_Mips);
>>
>>  // Get a count of how many bytes are to be pushed on the stack.
>>  unsigned NumBytes = CCInfo.getNextStackOffset();
>> @@ -706,7 +706,7 @@
>>    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
>>
>> RegsToPass[i].second.getValueType()));
>>
>> -  if (InFlag.Val)
>> +  if (InFlag.getNode())
>>    Ops.push_back(InFlag);
>>
>>  Chain  = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0],
>> Ops.size());
>> @@ -750,7 +750,7 @@
>>
>>  // Handle result values, copying them out of physregs into vregs
>> that we
>>  // return.
>> -  return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG),
>> Op.getResNo());
>> +  return SDValue(LowerCallResult(Chain, InFlag, Op.getNode(), CC,
>> DAG), Op.getResNo());
>> }
>>
>> /// LowerCallResult - Lower the result values of an ISD::CALL into  
>> the
>> @@ -783,7 +783,7 @@
>>
>>  // Merge everything together with a MERGE_VALUES node.
>>  return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
>> -                            ResultVals.size()).Val;
>> +                            ResultVals.size()).getNode();
>> }
>>
>> //
>> =
>> =
>> =
>> ----------------------------------------------------------------------=
>> ==//
>> @@ -814,7 +814,7 @@
>>  SmallVector<CCValAssign, 16> ArgLocs;
>>  CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
>>
>> -  CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
>> +  CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_Mips);
>>  SmallVector<SDValue, 16> ArgValues;
>>  SDValue StackPtr;
>>
>> @@ -865,7 +865,7 @@
>>      // To meet ABI, when VARARGS are passed on registers, the
>> registers
>>      // must have their values written to the caller stack frame.
>>      if ((isVarArg) && (Subtarget->isABI_O32())) {
>> -        if (StackPtr.Val == 0)
>> +        if (StackPtr.getNode() == 0)
>>          StackPtr = DAG.getRegister(StackReg, getPointerTy());
>>
>>        // The stack pointer offset is relative to the caller stack
>> frame.
>> @@ -925,7 +925,7 @@
>>  ArgValues.push_back(Root);
>>
>>  // Return the new list of results.
>> -  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
>> +  return DAG.getMergeValues(Op.getNode()->getVTList(),  
>> &ArgValues[0],
>>                            ArgValues.size()).getValue(Op.getResNo());
>> }
>>
>> @@ -946,7 +946,7 @@
>>  CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
>>
>>  // Analize return values of ISD::RET
>> -  CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
>> +  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Mips);
>>
>>  // If this is the first return lowered for this function, add
>>  // the regs to the liveout set for the function.
>> @@ -992,7 +992,7 @@
>>  }
>>
>>  // Return on Mips is always a "jr $ra"
>> -  if (Flag.Val)
>> +  if (Flag.getNode())
>>    return DAG.getNode(MipsISD::Ret, MVT::Other,
>>                       Chain, DAG.getRegister(Mips::RA, MVT::i32),
>> Flag);
>>  else // Return Void
>>
>> Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -168,11 +168,11 @@
>>    if (LD) {
>>      fsr = LD->getBasePtr();
>>    }
>> -    else if (isa<RegisterSDNode>(N.Val)) {
>> +    else if (isa<RegisterSDNode>(N.getNode())) {
>>      //FIXME an attempt to retrieve the register number
>>      //but does not work
>>      DOUT << "this is a register\n";
>> -      Reg = dyn_cast<RegisterSDNode>(N.Val);
>> +      Reg = dyn_cast<RegisterSDNode>(N.getNode());
>>      fsr = CurDAG->getRegister(Reg->getReg(),MVT::i16);
>>    }
>>    else {
>> @@ -198,7 +198,7 @@
>>    return true;
>>  }
>>  else if (N.getOpcode() == PIC16ISD::Package) {
>> -    CurDAG->setGraphColor(Op.Val, "blue");
>> +    CurDAG->setGraphColor(Op.getNode(), "blue");
>>    CurDAG->viewGraph();
>>  }
>>
>> @@ -227,7 +227,7 @@
>> /// expanded, promoted and normal instructions.
>> SDNode* PIC16DAGToDAGISel::Select(SDValue N)
>> {
>> -  SDNode *Node = N.Val;
>> +  SDNode *Node = N.getNode();
>>  unsigned Opcode = Node->getOpcode();
>>
>>  // Dump information about the Node being selected
>> @@ -262,8 +262,8 @@
>>
>> #ifndef NDEBUG
>>  DOUT << std::string(Indent-2, ' ') << "=> ";
>> -  if (ResNode == NULL || ResNode == N.Val)
>> -    DEBUG(N.Val->dump(CurDAG));
>> +  if (ResNode == NULL || ResNode == N.getNode())
>> +    DEBUG(N.getNode()->dump(CurDAG));
>>  else
>>    DEBUG(ResNode->dump(CurDAG));
>>  DOUT << "\n";
>>
>> Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -334,7 +334,7 @@
>>  LoadSDNode *LD  = cast<LoadSDNode>(N);
>>  SDValue Ptr   = LD->getBasePtr();
>>  if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
>> -    if (ISD::isNON_TRUNCStore(Chain.Val)) {
>> +    if (ISD::isNON_TRUNCStore(Chain.getNode())) {
>>      StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
>>      if (PrevST->getBasePtr() == Ptr &&
>>          PrevST->getValue().getValueType() == N->getValueType(0))
>> @@ -352,7 +352,7 @@
>>  Outs[1] = DAG.getLoad(MVT::i8, Chain, toWorklist, NULL, 0);
>>  // FIXME: Add to worklist may not be needed.
>>  // It is meant to merge sequences of add with constant into one.
>> -  DCI.AddToWorklist(toWorklist.Val);
>> +  DCI.AddToWorklist(toWorklist.getNode());
>>
>>  // Create the tokenfactors and carry it on to the build_pair node
>>  OutChains[0] = Outs[0].getValue(1);
>> @@ -443,7 +443,7 @@
>>      changed = true;
>>      // LowerLOAD returns a Package node or it may combine and return
>>      // anything else.
>> -      SDValue lowered = LowerLOAD(InOp[i].Val, DAG, DCI);
>> +      SDValue lowered = LowerLOAD(InOp[i].getNode(), DAG, DCI);
>>
>>      // So If LowerLOAD returns something other than Package,
>>      // then just call ADD again.
>> @@ -462,7 +462,7 @@
>>      changed = true;
>>      // Must call LowerADDSUB recursively here,
>>      // LowerADDSUB returns a Package node.
>> -      SDValue lowered = LowerADDSUB(InOp[i].Val, DAG, DCI);
>> +      SDValue lowered = LowerADDSUB(InOp[i].getNode(), DAG, DCI);
>>
>>      LoOps[i] = lowered.getOperand(0);
>>      HiOps[i] = lowered.getOperand(1);
>> @@ -543,7 +543,7 @@
>>  // FIXME: Just copy right now.
>>  ArgValues.push_back(Root);
>>
>> -  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
>> +  return DAG.getMergeValues(Op.getNode()->getVTList(),  
>> &ArgValues[0],
>>                            ArgValues.size()).getValue(Op.getResNo());
>> }
>>
>> @@ -622,7 +622,7 @@
>>      if ((Src.getOpcode() == ISD::ANY_EXTEND) ||
>>          (Src.getOpcode() == ISD::SIGN_EXTEND) ||
>>          (Src.getOpcode() == ISD::ZERO_EXTEND)) {
>> -        Src = Src.Val->getOperand(0);
>> +        Src = Src.getNode()->getOperand(0);
>>        Stores[0] = DAG.getStore(Chain, Src, Dest, NULL,0);
>>        return Stores[0];
>>      }
>> @@ -721,10 +721,10 @@
>>          // We want to merge sequence of add with constant to one
>> add and a
>>          // constant, so add the ADD node to worklist to have llvm
>> do that
>>          // automatically.
>> -          DCI.AddToWorklist(toWorkList.Val);
>> +          DCI.AddToWorklist(toWorkList.getNode());
>>
>>          // We don't need the Package so add to worklist so llvm
>> deletes it
>> -          DCI.AddToWorklist(Src.Val);
>> +          DCI.AddToWorklist(Src.getNode());
>>          retVal = DAG.getNode(ISD::TokenFactor, MVT::Other,
>> &Stores[0], 2);
>>        }
>>
>>
>> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -294,7 +294,7 @@
>>      BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
>>    }
>>  }
>> -  return CurDAG->getRegister(GlobalBaseReg,
>> PPCLowering.getPointerTy()).Val;
>> +  return CurDAG->getRegister(GlobalBaseReg,
>> PPCLowering.getPointerTy()).getNode();
>> }
>>
>> /// isIntS16Immediate - This method tests to see if the node is
>> either a 32-bit
>> @@ -313,7 +313,7 @@
>> }
>>
>> static bool isIntS16Immediate(SDValue Op, short &Imm) {
>> -  return isIntS16Immediate(Op.Val, Imm);
>> +  return isIntS16Immediate(Op.getNode(), Imm);
>> }
>>
>>
>> @@ -340,7 +340,7 @@
>> // isInt32Immediate - This method tests to see if a constant operand.
>> // If so Imm will receive the 32 bit value.
>> static bool isInt32Immediate(SDValue N, unsigned &Imm) {
>> -  return isInt32Immediate(N.Val, Imm);
>> +  return isInt32Immediate(N.getNode(), Imm);
>> }
>>
>>
>> @@ -348,7 +348,7 @@
>> // opcode and that it has a immediate integer right operand.
>> // If so Imm will receive the 32 bit value.
>> static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned&
>> Imm) {
>> -  return N->getOpcode() == Opc && isInt32Immediate(N-
>>> getOperand(1).Val, Imm);
>> +  return N->getOpcode() == Opc && isInt32Immediate(N-
>>> getOperand(1).getNode(), Imm);
>> }
>>
>> bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB,
>> unsigned &ME) {
>> @@ -384,7 +384,7 @@
>>  unsigned Indeterminant = ~0;  // bit mask marking indeterminant
>> results
>>  unsigned Opcode = N->getOpcode();
>>  if (N->getNumOperands() != 2 ||
>> -      !isInt32Immediate(N->getOperand(1).Val, Shift) || (Shift >  
>> 31))
>> +      !isInt32Immediate(N->getOperand(1).getNode(), Shift) ||
>> (Shift > 31))
>>    return false;
>>
>>  if (Opcode == ISD::SHL) {
>> @@ -540,7 +540,7 @@
>>  } else if (LHS.getValueType() == MVT::i64) {
>>    uint64_t Imm;
>>    if (CC == ISD::SETEQ || CC == ISD::SETNE) {
>> -      if (isInt64Immediate(RHS.Val, Imm)) {
>> +      if (isInt64Immediate(RHS.getNode(), Imm)) {
>>        // SETEQ/SETNE comparison with 16-bit immediate, fold it.
>>        if (isUInt16(Imm))
>>          return SDValue(CurDAG->getTargetNode(PPC::CMPLDI,
>> MVT::i64, LHS,
>> @@ -568,7 +568,7 @@
>>      }
>>      Opc = PPC::CMPLD;
>>    } else if (ISD::isUnsignedIntSetCC(CC)) {
>> -      if (isInt64Immediate(RHS.Val, Imm) && isUInt16(Imm))
>> +      if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm))
>>        return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64,
>> LHS,
>>                                               getI64Imm(Imm &
>> 0xFFFF)), 0);
>>      Opc = PPC::CMPLD;
>> @@ -653,7 +653,7 @@
>> }
>>
>> SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
>> -  SDNode *N = Op.Val;
>> +  SDNode *N = Op.getNode();
>>  unsigned Imm;
>>  ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
>>  if (isInt32Immediate(N->getOperand(1), Imm)) {
>> @@ -773,7 +773,7 @@
>> // Select - Convert the specified operand from a target-independent
>> to a
>> // target-specific node if it hasn't already been changed.
>> SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
>> -  SDNode *N = Op.Val;
>> +  SDNode *N = Op.getNode();
>>  if (N->isMachineOpcode())
>>    return NULL;   // Already selected.
>>
>> @@ -974,7 +974,7 @@
>>    // If this is an and of a value rotated between 0 and 31 bits
>> and then and'd
>>    // with a mask, emit rlwinm
>>    if (isInt32Immediate(N->getOperand(1), Imm) &&
>> -        isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB,
>> ME)) {
>> +        isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH,
>> MB, ME)) {
>>      SDValue Val = N->getOperand(0).getOperand(0);
>>      AddToISelQueue(Val);
>>      SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB),
>> getI32Imm(ME) };
>> @@ -1025,7 +1025,7 @@
>>    break;
>>  case ISD::SHL: {
>>    unsigned Imm, SH, MB, ME;
>> -    if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm)  
>> &&
>> +    if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND,
>> Imm) &&
>>        isRotateAndMask(N, Imm, true, SH, MB, ME)) {
>>      AddToISelQueue(N->getOperand(0).getOperand(0));
>>      SDValue Ops[] = { N->getOperand(0).getOperand(0),
>> @@ -1038,7 +1038,7 @@
>>  }
>>  case ISD::SRL: {
>>    unsigned Imm, SH, MB, ME;
>> -    if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm)  
>> &&
>> +    if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND,
>> Imm) &&
>>        isRotateAndMask(N, Imm, true, SH, MB, ME)) {
>>      AddToISelQueue(N->getOperand(0).getOperand(0));
>>      SDValue Ops[] = { N->getOperand(0).getOperand(0),
>>
>> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=55504&r1=55503&r2=55504&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Aug 28
>> 16:40:38 2008
>> @@ -423,7 +423,7 @@
>> static bool isFloatingPointZero(SDValue Op) {
>>  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
>>    return CFP->getValueAPF().isZero();
>> -  else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
>> +  else if (ISD::isEXTLoad(Op.getNode()) ||
>> ISD::isNON_EXTLoad(Op.getNode())) {
>>    // Maybe this has already been legalized into the constant pool?
>>    if (ConstantPoolSDNode *CP =
>> dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
>>      if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
>> @@ -625,7 +625,7 @@