Writing an LLVM backend

- Writing an LLVM backend +

+ Writing an LLVM Compiler Backend

Introduction -
Writing a backend -
1. Machine backends -
  1. Outline
  2. Implementation details
2. Language backends
Related reading material +
- Audience
- Prerequisite Reading
- Basic Steps
- Preliminaries
+
Target Machine
Register Set and Register Classes

Defining a Register
Defining a Register Class
Implement a subclass of TargetRegisterInfo

Instruction Set

Implement a subclass of TargetInstrInfo
Branch Folding and If Conversion

Instruction Selector

The SelectionDAG Legalize Phase

Promote
Expand
Custom
Legal

Calling Conventions

Assembly Printer
Subtarget Support
JIT Support

Machine Code Emitter
Target JIT Info

Written by Misha Brukman

Written by Mason Woo and Misha Brukman

@@ -37,258 +63,2001 @@

This document describes techniques for writing compiler backends +that convert the LLVM IR (intermediate representation) to code for a specified +machine or other languages. Code intended for a specific machine can take the +form of either assembly code or binary code (usable for a JIT compiler).

+ +

The backend of LLVM features a target-independent code generator +that may create output for several types of target CPUs, including X86, +PowerPC, Alpha, and SPARC. The backend may also be used to generate code +targeted at SPUs of the Cell processor or GPUs to support the execution of +compute kernels.

+ +

The document focuses on existing examples found in subdirectories +of llvm/lib/Target in a downloaded LLVM release. In particular, this document +focuses on the example of creating a static compiler (one that emits text +assembly) for a SPARC target, because SPARC has fairly standard +characteristics, such as a RISC instruction set and straightforward calling +conventions.

This document describes techniques for writing backends for LLVM which -convert the LLVM representation to machine assembly code or other languages.

+ Audience +

The audience for this document is anyone who needs to write an +LLVM backend to generate code for a specific hardware or software target.

- -

- Writing a backend +

+ Prerequisite Reading +

+ +

+These essential documents must be read before reading this document: +

+LLVM Language Reference Manual - +a reference manual for the LLVM assembly language +
+The LLVM Target-Independent Code Generator - +a guide to the components (classes and code generation algorithms) for translating +the LLVM internal representation to the machine code for a specified target. +Pay particular attention to the descriptions of code generation stages: +Instruction Selection, Scheduling and Formation, SSA-based Optimization, +Register Allocation, Prolog/Epilog Code Insertion, Late Machine Code Optimizations, +and Code Emission. +
+TableGen Fundamentals - +a document that describes the TableGen (tblgen) application that manages domain-specific +information to support LLVM code generation. TableGen processes input from a +target description file (.td suffix) and generates C++ code that can be used +for code generation. +
+Writing an LLVM Pass - +The assembly printer is a FunctionPass, as are several SelectionDAG processing steps. +

+To follow the SPARC examples in this document, have a copy of +The SPARC Architecture Manual, Version 8 +for reference. For details about the ARM instruction set, refer to the +ARM Architecture Reference Manual +For more about the GNU Assembler format (GAS), see +Using As +especially for the assembly printer. Using As contains lists of target machine dependent features.

- -

- Machine backends + Basic Steps

- - -

- Outline +

To write a compiler +backend for LLVM that converts the LLVM IR (intermediate representation) +to code for a specified target (machine or other language), follow these steps:

+ +

+Create a subclass of the TargetMachine class that describes +characteristics of your target machine. Copy existing examples of specific +TargetMachine class and header files; for example, start with SparcTargetMachine.cpp +and SparcTargetMachine.h, but change the file names for your target. Similarly, +change code that references "Sparc" to reference your target.
Describe the register set of the target. Use TableGen to generate +code for register definition, register aliases, and register classes from a +target-specific RegisterInfo.td input file. You should also write additional +code for a subclass of TargetRegisterInfo class that represents the class +register file data used for register allocation and also describes the +interactions between registers.
Describe the instruction set of the target. Use TableGen to +generate code for target-specific instructions from target-specific versions of +TargetInstrFormats.td and TargetInstrInfo.td. You should write additional code +for a subclass of the TargetInstrInfo +class to represent machine +instructions supported by the target machine.
Describe the selection and conversion of the LLVM IR from a DAG (directed +acyclic graph) representation of instructions to native target-specific +instructions. Use TableGen to generate code that matches patterns and selects +instructions based on additional information in a target-specific version of +TargetInstrInfo.td. Write code for XXXISelDAGToDAG.cpp +(where XXX identifies the specific target) to perform pattern +matching and DAG-to-DAG instruction selection. Also write code in XXXISelLowering.cpp +to replace or remove operations and data types that are not supported natively +in a SelectionDAG.
Write code for an +assembly printer that converts LLVM IR to a GAS format for your target machine. +You should add assembly strings to the instructions defined in your +target-specific version of TargetInstrInfo.td. You should also write code for a +subclass of AsmPrinter that performs the LLVM-to-assembly conversion and a +trivial subclass of TargetAsmInfo.
Optionally, add support for subtargets (that is, variants with +different capabilities). You should also write code for a subclass of the +TargetSubtarget class, which allows you to use the -mcpu= +and -mattr= command-line options.
Optionally, add JIT support and create a machine code emitter (subclass +of TargetJITInfo) that is used to emit binary code directly into memory.

+ +

In the .cpp and .h files, initially stub up these methods and +then implement them later. Initially, you may not know which private members +that the class will need and which components will need to be subclassed.

+ +

+ Preliminaries +

To actually create +your compiler backend, you need to create and modify a few files. The absolute +minimum is discussed here, but to actually use the LLVM target-independent code +generator, you must perform the steps described in the LLVM +Target-Independent Code Generator document.

+ +

First, you should +create a subdirectory under lib/Target to hold all the files related to your +target. If your target is called "Dummy", create the directory +lib/Target/Dummy.

+ +

In this new +directory, create a Makefile. It is easiest to copy a Makefile of another +target and modify it. It should at least contain the LEVEL, LIBRARYNAME and +TARGET variables, and then include $(LEVEL)/Makefile.common. The library can be +named LLVMDummy (for example, see the MIPS target). Alternatively, you can +split the library into LLVMDummyCodeGen and LLVMDummyAsmPrinter, the latter of +which should be implemented in a subdirectory below lib/Target/Dummy (for +example, see the PowerPC target).

+ +

Note that these two +naming schemes are hardcoded into llvm-config. Using any other naming scheme +will confuse llvm-config and produce lots of (seemingly unrelated) linker +errors when linking llc.

+ +

To make your target +actually do something, you need to implement a subclass of TargetMachine. This +implementation should typically be in the file +lib/Target/DummyTargetMachine.cpp, but any file in the lib/Target directory will +be built and should work. To use LLVM's target +independent code generator, you should do what all current machine backends do: create a subclass +of LLVMTargetMachine. (To create a target from scratch, create a subclass of +TargetMachine.)

+ +

To get LLVM to +actually build and link your target, you need to add it to the TARGETS_TO_BUILD +variable. To do this, you modify the configure script to know about your target +when parsing the --enable-targets option. Search the configure script for TARGETS_TO_BUILD, +add your target to the lists there (some creativity required) and then +reconfigure. Alternatively, you can change autotools/configure.ac and +regenerate configure by running ./autoconf/AutoRegen.sh

+ +

+ Target Machine +

LLVMTargetMachine is designed as a base class for targets +implemented with the LLVM target-independent code generator. The +LLVMTargetMachine class should be specialized by a concrete target class that +implements the various virtual methods. LLVMTargetMachine is defined as a +subclass of TargetMachine in include/llvm/Target/TargetMachine.h. The +TargetMachine class implementation (TargetMachine.cpp) also processes numerous +command-line options.

+ +

To create a concrete target-specific subclass of +LLVMTargetMachine, start by copying an existing TargetMachine class and header. +You should name the files that you create to reflect your specific target. For +instance, for the SPARC target, name the files SparcTargetMachine.h and +SparcTargetMachine.cpp

+ +

For a target machine XXX, the implementation of XXXTargetMachine +must have access methods to obtain objects that represent target components. +These methods are named get*Info and are intended to obtain the instruction set +(getInstrInfo), register set (getRegisterInfo), stack frame layout +(getFrameInfo), and similar information. XXXTargetMachine must also implement +the getTargetData method to access an object with target-specific data +characteristics, such as data type size and alignment requirements.

+ +

For instance, for the SPARC target, the header file SparcTargetMachine.h +declares prototypes for several get*Info and getTargetData methods that simply +return a class member.

In general, you want to follow the format of SPARC, X86 or PowerPC (in -lib/Target). SPARC is the simplest backend, and is RISC, so if -you're working on a RISC target, it is a good one to start with.

namespace llvm {
 
-To create a static compiler (one that emits text assembly), you need to
-implement the following:
+class Module;
 
+class SparcTargetMachine : public LLVMTargetMachine {
+  const TargetData DataLayout;       // Calculates type size & alignment
+  SparcSubtarget Subtarget;
+  SparcInstrInfo InstrInfo;
+  TargetFrameInfo FrameInfo;
+  
+protected:
+  virtual const TargetAsmInfo *createTargetAsmInfo()
+const;
+  
+public:
+  SparcTargetMachine(const Module &M, const std::string &FS);
+
+  virtual const SparcInstrInfo *getInstrInfo() const {return &InstrInfo; }
+  virtual const TargetFrameInfo *getFrameInfo() const {return &FrameInfo; }
+  virtual const TargetSubtarget *getSubtargetImpl() const{return &Subtarget; }
+  virtual const TargetRegisterInfo *getRegisterInfo() const {
+    return &InstrInfo.getRegisterInfo();
+  }
+  virtual const TargetData *getTargetData() const { return &DataLayout; }
+  static unsigned getModuleMatchQuality(const Module &M);
+
+  // Pass Pipeline Configuration
+  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+                                  std::ostream &Out);
+};
+
+} // end namespace llvm
+

+ +

Describe the register set. -
- Create a TableGen description of - the register set and register classes
- Implement a subclass of TargetRegisterInfo
Describe the instruction set. -
- Create a TableGen description of - the instruction set
- Implement a subclass of TargetInstrInfo
Describe the target machine. -
- Create a TableGen description of - the target that describes the pointer size and references the instruction - set
- Implement a subclass of TargetMachine, which - configures TargetData - correctly
- Register your new target using the RegisterTarget - template:
  
  -
```
-RegisterTarget<MyTargetMachine> M("short_name", "  Target name");
-
```
  -
  Here, MyTargetMachine is the name of your implemented - subclass of TargetMachine, - short_name is the option that will be active following - -march= to select a target in llc and lli, and the last string - is the description of your target to appear in -help - listing.
Implement the assembly printer for the architecture. -
- Define all of the assembly strings for your target, adding them to the - instructions in your *InstrInfo.td file.
- Implement the llvm::AsmPrinter interface.
-
Implement an instruction selector for the architecture. -
- The recommended method is the - pattern-matching DAG-to-DAG instruction selector (for example, see - the PowerPC backend in PPCISelDAGtoDAG.cpp). Parts of instruction - selector creation can be performed by adding patterns to the instructions - in your .td file.
-
Optionally, add subtarget support. -
- If your target has multiple subtargets (e.g. variants with different - capabilities), implement the llvm::TargetSubtarget interface - for your architecture. This allows you to add -mcpu= and - -mattr= options.
- getInstrInfo
- getRegisterInfo
- getFrameInfo
- getTargetData
- getSubtargetImpl
-
Optionally, add JIT support. -
- Create a subclass of TargetJITInfo
- Create a machine code emitter that will be used to emit binary code - directly into memory, given MachineInstrs
+
For some targets, you also need to support the following methods: +
+ +
- getTargetLowering
- getJITInfo
+
In addition, the XXXTargetMachine constructor should specify a +TargetDescription string that determines the data layout for the target machine, +including characteristics such as pointer size, alignment, and endianness. For +example, the constructor for SparcTargetMachine contains the following:

- -

- Implementation details +

+SparcTargetMachine::SparcTargetMachine(const Module &M, const std::string &FS)
+  : DataLayout("E-p:32:32-f128:128:128"),
+    Subtarget(M, FS), InstrInfo(Subtarget),
+    FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
+}
+

- +

Hyphens separate portions of the TargetDescription string.

The "E" in the string indicates a big-endian target data model; a +lower-case "e" would indicate little-endian.
"p:" is followed by pointer information: size, ABI alignment, and +preferred alignment. If only two figures follow "p:", then the first value is +pointer size, and the second value is both ABI and preferred alignment.
then a letter for numeric type alignment: "i", "f", "v", or "a" +(corresponding to integer, floating point, vector, or aggregate). "i", "v", or +"a" are followed by ABI alignment and preferred alignment. "f" is followed by +three values, the first indicates the size of a long double, then ABI alignment +and preferred alignment.

You must also register your target using the RegisterTarget +template. (See the TargetMachineRegistry class.) For example, in SparcTargetMachine.cpp, +the target is registered with:

TableGen register info description - describe a class which -will store the register's number in the binary encoding of the instruction -(e.g., for JIT purposes).

+namespace {
+  // Register the target.
+  RegisterTarget<SparcTargetMachine>X("sparc", "SPARC");
+}
+

You also need to define register classes to contain these registers, such as -the integer register class and floating-point register class, so that you can -allocate virtual registers to instructions from these sets, and let the -target-independent register allocator automatically choose the actual -architected registers.

+ +

+ Register Set and Register Classes +

+ +

You should describe +a concrete target-specific class +that represents the register file of a target machine. This class is +called XXXRegisterInfo (where XXX identifies the target) and represents the +class register file data that is used for register allocation and also +describes the interactions between registers.

+ +

You also need to +define register classes to categorize related registers. A register class +should be added for groups of registers that are all treated the same way for +some instruction. Typical examples are register classes that include integer, +floating-point, or vector registers. A register allocator allows an +instruction to use any register in a specified register class to perform the +instruction in a similar manner. Register classes allocate virtual registers to +instructions from these sets, and register classes let the target-independent +register allocator automatically choose the actual registers.

+ +

Much of the code for registers, including register definition, +register aliases, and register classes, is generated by TableGen from +XXXRegisterInfo.td input files and placed in XXXGenRegisterInfo.h.inc and +XXXGenRegisterInfo.inc output files. Some of the code in the implementation of +XXXRegisterInfo requires hand-coding.

+ +

+ Defining a Register +

The XXXRegisterInfo.td file typically starts with register definitions +for a target machine. The Register class (specified in Target.td) is used to +define an object for each register. The specified string n becomes the Name of +the register. The basic Register object does not have any subregisters and does +not specify any aliases.

-// class Register is defined in Target.td
-class TargetReg<string name> : Register<name> {
-  let Namespace = "Target";
+class Register<string n> {
+  string Namespace = "";
+  string AsmName = n;
+  string Name = n;
+  int SpillSize = 0;
+  int SpillAlignment = 0;
+  list<Register> Aliases = [];
+  list<Register> SubRegs = [];
+  list<int> DwarfNumbers = [];
 }
+

-class IntReg<bits<5> num, string name> : TargetReg<name> { - field bits<5> Num = num; -} +

For example, in the X86RegisterInfo.td file, there are register +definitions that utilize the Register class, such as:

+def AL : Register<"AL">,
+DwarfRegNum<[0, 0, 0]>;
+

-def R0 : IntReg<0, "%R0">; -... +

This defines the register AL and assigns it values (with +DwarfRegNum) that are used by gcc, gdb, or a debug information writer (such as +DwarfWriter in llvm/lib/CodeGen) to identify a register. For register AL, +DwarfRegNum takes an array of 3 values, representing 3 different modes: the +first element is for X86-64, the second for EH (exception handling) on X86-32, +and the third is generic. -1 is a special Dwarf number that indicates the gcc +number is undefined, and -2 indicates the register number is invalid for this +mode.

-// class RegisterClass is defined in Target.td -def IReg : RegisterClass<i64, 64, [R0, ... ]>; +

From the previously described line in the X86RegisterInfo.td +file, TableGen generates this code in the X86GenRegisterInfo.inc file:

+  static const unsigned GR8[] = { X86::AL, ... };
+ 
+  const unsigned AL_AliasSet[] = { X86::AX, X86::EAX, X86::RAX, 0 };
+ 
+  const TargetRegisterDesc RegisterDescriptors[] = { 
+    ...
+    { "AL", "AL", AL_AliasSet, Empty_SubRegsSet, Empty_SubRegsSet, AL_SuperRegsSet }, ...

TableGen instruction info description - break up instructions into -classes, usually that's already done by the manufacturer (see instruction -manual). Define a class for each instruction category. Define each opcode as a -subclass of the category, with appropriate parameters such as the fixed binary -encoding of opcodes and extended opcodes, and map the register bits to the bits -of the instruction which they are encoded in (for the JIT). Also specify how -the instruction should be printed so it can use the automatic assembly printer, -e.g.:

From the register info file, TableGen generates a +TargetRegisterDesc object for each register. TargetRegisterDesc is defined in +include/llvm/Target/TargetRegisterInfo.h with the following fields:

-// class Instruction is defined in Target.td
-class Form<bits<6> opcode, dag OL, string asmstr> : Instruction {
-  field bits<42> Inst;
+struct TargetRegisterDesc {
+  const char     *AsmName;      // Assembly language name for the register
+  const char     *Name;         // Printable name for the reg (for debugging)
+  const unsigned *AliasSet;     // Register Alias Set
+  const unsigned *SubRegs;      // Sub-register set
+  const unsigned *ImmSubRegs;   // Immediate sub-register set
+  const unsigned *SuperRegs;    // Super-register set
+};

- let Namespace = "Target"; - let Inst{0-6} = opcode; - let OperandList = OL; - let AsmString = asmstr; -} +

TableGen uses the entire target description file (.td) to +determine text names for the register (in the AsmName and Name fields of +TargetRegisterDesc) and the relationships of other registers to the defined +register (in the other TargetRegisterDesc fields). In this example, other +definitions establish the registers "AX", "EAX", and "RAX" as aliases for one +another, so TableGen generates a null-terminated array (AL_AliasSet) for this +register alias set.

+ +

The Register class is commonly used as a base class for more +complex classes. In Target.td, the Register class is the base for the +RegisterWithSubRegs class that is used to define registers that need to specify +subregisters in the SubRegs list, as shown here:

+class RegisterWithSubRegs<string n,
+list<Register> subregs> : Register<n> {
+  let SubRegs = subregs;
+}

-def ADD : Form<42, (ops IReg:$rD, IReg:$rA, IReg:$rB), "add $rD, $rA, $rB">; +

In SparcRegisterInfo.td, additional register classes are defined +for SPARC: a Register subclass, SparcReg, and further subclasses: Ri, Rf, and +Rd. SPARC registers are identified by 5-bit ID numbers, which is a feature +common to these subclasses. Note the use of ‘let’ expressions to override values +that are initially defined in a superclass (such as SubRegs field in the Rd +class).

+class SparcReg<string n> : Register<n> {
+  field bits<5> Num;
+  let Namespace = "SP";
+}
+// Ri - 32-bit integer registers
+class Ri<bits<5> num, string n> :
+SparcReg<n> {
+  let Num = num;
+}
+// Rf - 32-bit floating-point registers
+class Rf<bits<5> num, string n> :
+SparcReg<n> {
+  let Num = num;
+}
+// Rd - Slots in the FP register file for 64-bit
+floating-point values.
+class Rd<bits<5> num, string n,
+list<Register> subregs> : SparcReg<n> {
+  let Num = num;
+  let SubRegs = subregs;
+}

In the SparcRegisterInfo.td file, there are register definitions +that utilize these subclasses of Register, such as:

+def G0 : Ri< 0, "G0">,
+DwarfRegNum<[0]>;
+def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
+...
+def F0 : Rf< 0, "F0">,
+DwarfRegNum<[32]>;
+def F1 : Rf< 1, "F1">,
+DwarfRegNum<[33]>;
+...
+def D0 : Rd< 0, "F0", [F0, F1]>,
+DwarfRegNum<[32]>;
+def D1 : Rd< 2, "F2", [F2, F3]>,
+DwarfRegNum<[34]>;

- - - +

The last two registers shown above (D0 and D1) are double-precision +floating-point registers that are aliases for pairs of single-precision +floating-point sub-registers. In addition to aliases, the sub-register and +super-register relationships of the defined register are in fields of a +register’s TargetRegisterDesc.

- Language backends + Defining a Register Class +

The RegisterClass class (specified in Target.td) is used to +define an object that represents a group of related registers and also defines +the default allocation order of the registers. A target description file +XXXRegisterInfo.td that uses Target.td can construct register classes using the +following class:

+class RegisterClass<string namespace,
+list<ValueType> regTypes, int alignment,
+                    list<Register> regList> {
+  string Namespace = namespace;
+  list<ValueType> RegTypes = regTypes;
+  int Size = 0;  // spill size, in bits; zero lets tblgen pick the size
+  int Alignment = alignment;
+ 
+  // CopyCost is the cost of copying a value between two registers
+  // default value 1 means a single instruction
+  // A negative value means copying is extremely expensive or impossible
+  int CopyCost = 1;  
+  list<Register> MemberList = regList;
+  
+  // for register classes that are subregisters of this class
+  list<RegisterClass> SubRegClassList = [];  
+  
+  code MethodProtos = [{}];  // to insert arbitrary code
+  code MethodBodies = [{}];
+}

To define a RegisterClass, use the following 4 arguments:

The first argument of the definition is the name of the +namespace.
The second argument is a list of ValueType register type values +that are defined in include/llvm/CodeGen/ValueTypes.td. Defined values include +integer types (such as i16, i32, and i1 for Boolean), floating-point types +(f32, f64), and vector types (for example, v8i16 for an 8 x i16 vector). All +registers in a RegisterClass must have the same ValueType, but some registers +may store vector data in different configurations. For example a register that +can process a 128-bit vector may be able to handle 16 8-bit integer elements, 8 +16-bit integers, 4 32-bit integers, and so on.
The third argument of the RegisterClass definition specifies the +alignment required of the registers when they are stored or loaded to memory.
The final argument, regList, specifies which registers are in +this class. If an allocation_order_* method is not specified, then regList also +defines the order of allocation used by the register allocator.

For now, just take a look at lib/Target/CBackend for an example of -how the C backend is written.

In SparcRegisterInfo.td, three RegisterClass objects are defined: +FPRegs, DFPRegs, and IntRegs. For all three register classes, the first +argument defines the namespace with the string “SP”. FPRegs defines a group of 32 +single-precision floating-point registers (F0 to F31); DFPRegs defines a group +of 16 double-precision registers (D0-D15). For IntRegs, the MethodProtos and +MethodBodies methods are used by TableGen to insert the specified code into generated +output.

+def FPRegs : RegisterClass<"SP", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7,   
+  F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
+  F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
+ 
+def DFPRegs : RegisterClass<"SP", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7,
+  D8, D9, D10, D11, D12, D13, D14, D15]>;
+ 
+def IntRegs : RegisterClass<"SP", [i32], 32, [L0, L1, L2, L3, L4, L5, L6, L7,
+                                     I0, I1, I2, I3, I4, I5,
+                                     O0, O1, O2, O3, O4, O5, O7,
+                                     G1,
+                                     // Non-allocatable regs:
+                                     G2, G3, G4, 
+                                     O6, // stack ptr
+                                     I6, // frame ptr
+                                     I7, // return address
+                                     G0, // constant zero
+                                     G5, G6, G7 // reserved for kernel
+                                     ]> {
+  let MethodProtos = [{
+    iterator allocation_order_end(const MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    IntRegsClass::iterator
+    IntRegsClass::allocation_order_end(const MachineFunction &MF) const {
+      return end()-10  // Don't allocate special registers
+         -1;  
+    }
+  }];
+}
+

+ +

Using SparcRegisterInfo.td with TableGen generates several output +files that are intended for inclusion in other source code that you write. +SparcRegisterInfo.td generates SparcGenRegisterInfo.h.inc, which should be +included in the header file for the implementation of the SPARC register +implementation that you write (SparcRegisterInfo.h). In +SparcGenRegisterInfo.h.inc a new structure is defined called +SparcGenRegisterInfo that uses TargetRegisterInfo as its base. It also +specifies types, based upon the defined register classes: DFPRegsClass, FPRegsClass, +and IntRegsClass.

+ +

SparcRegisterInfo.td also generates SparcGenRegisterInfo.inc, +which is included at the bottom of SparcRegisterInfo.cpp, the SPARC register +implementation. The code below shows only the generated integer registers and +associated register classes. The order of registers in IntRegs reflects the +order in the definition of IntRegs in the target description file. Take special +note of the use of MethodBodies in SparcRegisterInfo.td to create code in +SparcGenRegisterInfo.inc. MethodProtos generates similar code in +SparcGenRegisterInfo.h.inc.

  // IntRegs Register Class...
+  static const unsigned IntRegs[] = {
+    SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5,
+SP::L6, SP::L7, SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::O0, SP::O1,
+SP::O2, SP::O3, SP::O4, SP::O5, SP::O7, SP::G1, SP::G2, SP::G3, SP::G4, SP::O6,
+SP::I6, SP::I7, SP::G0, SP::G5, SP::G6, SP::G7, 
+  };
+ 
+  // IntRegsVTs Register Class Value Types...
+  static const MVT::ValueType IntRegsVTs[] = {
+    MVT::i32, MVT::Other
+  };
+namespace SP {   // Register class instances
+  DFPRegsClass    DFPRegsRegClass;
+  FPRegsClass     FPRegsRegClass;
+  IntRegsClass    IntRegsRegClass;
+...
+ 
+// IntRegs Sub-register Classess...
+  static const TargetRegisterClass* const IntRegsSubRegClasses [] = {
+    NULL
+  };
+...
+// IntRegs Super-register Classess...
+  static const TargetRegisterClass* const IntRegsSuperRegClasses [] = {
+    NULL
+  };
+ 
+// IntRegs Register Class sub-classes...
+  static const TargetRegisterClass* const IntRegsSubclasses [] = {
+    NULL
+  };
+...
+ 
+// IntRegs Register Class super-classes...
+  static const TargetRegisterClass* const IntRegsSuperclasses [] = {
+    NULL
+  };
+...
+ 
+  IntRegsClass::iterator
+  IntRegsClass::allocation_order_end(const MachineFunction &MF) const {
+
+     return end()-10  // Don't allocate special registers
+         -1; 
+  }
+  
+IntRegsClass::IntRegsClass() : TargetRegisterClass(IntRegsRegClassID, 
+   IntRegsVTs, IntRegsSubclasses, IntRegsSuperclasses, IntRegsSubRegClasses, 
+   IntRegsSuperRegClasses, 4, 4, 1, IntRegs, IntRegs + 32) {}
+}
+

- Files to create/modify + Implement a subclass of + TargetRegisterInfo

The final step is to hand code portions of XXXRegisterInfo, which +implements the interface described in TargetRegisterInfo.h. These functions +return 0, NULL, or false, unless overridden. Here’s a list of functions that +are overridden for the SPARC implementation in SparcRegisterInfo.cpp:

getCalleeSavedRegs (returns a list of callee-saved registers in +the order of the desired callee-save stack frame offset)

To actually create your backend, you need to create and modify a few files. -Here, the absolute minimum will be discussed. To actually use LLVM's target -independent codegenerator, you must implement extra -things.

getCalleeSavedRegClasses (returns a list of preferred register +classes with which to spill each callee saved register)

First of all, you should create a subdirectory under lib/Target, -which will hold all the files related to your target. Let's assume that our -target is called, "Dummy", we would create the directory -lib/Target/Dummy.

getReservedRegs (returns a bitset indexed by physical register +numbers, indicating if a particular register is unavailable)
hasFP (return a Boolean indicating if a function should have a +dedicated frame pointer register)

In this new directory, you should put a Makefile. You can probably -copy one from another target and modify it. It should at least contain the -LEVEL, LIBRARYNAME and TARGET variables, and then -include $(LEVEL)/Makefile.common. Be careful to give the library the -correct name, it must be named LLVMDummy (see the MIPS target, for -example). Alternatively, you can split the library into -LLVMDummyCodeGen and LLVMDummyAsmPrinter, the latter of which -should be implemented in a subdirectory below lib/Target/Dummy (see the -PowerPC target, for example).

Note that these two naming schemes are hardcoded into llvm-config. Using any -other naming scheme will confuse llvm-config and produce lots of (seemingly -unrelated) linker errors when linking llc.

To make your target actually do something, you need to implement a subclass -of TargetMachine. This implementation should typically be in the file -lib/Target/DummyTargetMachine.cpp, but any file in the -lib/Target directory will be built and should work. To use LLVM's target independent code generator, you should -create a subclass of LLVMTargetMachine. This is what all current -machine backends do. To create a target from scratch, create a subclass of -TargetMachine. This is what the current language backends do.

To get LLVM to actually build and link your target, you also need to add it -to the TARGETS_TO_BUILD variable. To do this, you need to modify the -configure script to know about your target when parsing the ---enable-targets option. Search the configure script for -TARGETS_TO_BUILD, add your target to the lists there (some creativity -required) and then reconfigure. Alternatively, you can change -autotools/configure.ac and regenerate configure by running -./autoconf/AutoRegen.sh. +

eliminateCallFramePseudoInstr (if call frame setup or destroy +pseudo instructions are used, this can be called to eliminate them)
eliminateFrameIndex (eliminate abstract frame indices from +instructions that may use them)
emitPrologue (insert prologue code into the function)
emitEpilogue (insert epilogue code into the function)

During the early stages of code generation, the LLVM IR code is +converted to a SelectionDAG with nodes that are instances of the SDNode class +containing target instructions. An SDNode has an opcode, operands, type +requirements, and operation properties (for example, is an operation +commutative, does an operation load from memory). The various operation node +types are described in the include/llvm/CodeGen/SelectionDAGNodes.h file (values +of the NodeType enum in the ISD namespace).

+ +

TableGen uses the following target description (.td) input files +to generate much of the code for instruction definition:

Target.td, where the Instruction, Operand, InstrInfo, and other +fundamental classes are defined
TargetSelectionDAG.td, used by SelectionDAG instruction selection +generators, contains SDTC* classes (selection DAG type constraint), definitions +of SelectionDAG nodes (such as imm, cond, bb, add, fadd, sub), and pattern +support (Pattern, Pat, PatFrag, PatLeaf, ComplexPattern)
XXXInstrFormats.td, patterns for definitions of target-specific +instructions
XXXInstrInfo.td, target-specific definitions of instruction +templates, condition codes, and instructions of an instruction set. (For architecture +modifications, a different file name may be used. For example, for Pentium with +SSE instruction, this file is X86InstrSSE.td, and for Pentium with MMX, this +file is X86InstrMMX.td.)

There is also a target-specific XXX.td file, where XXX is the +name of the target. The XXX.td file includes the other .td input files, but its +contents are only directly important for subtargets.

+ +

You should describe +a concrete target-specific class +XXXInstrInfo that represents machine +instructions supported by a target machine. XXXInstrInfo contains an array of +XXXInstrDescriptor objects, each of which describes one instruction. An +instruction descriptor defines:

opcode mnemonic
number of operands
list of implicit register definitions and uses
target-independent properties (such as memory access, is +commutable)
target-specific flags

+ +

The Instruction class (defined in Target.td) is mostly used as a +base for more complex instruction classes.

+ +

class Instruction {
+  string Namespace = "";
+  dag OutOperandList;       // An dag containing the MI def operand list.
+  dag InOperandList;        // An dag containing the MI use operand list.
+  string AsmString = "";    // The .s format to print the instruction with.
+  list<dag> Pattern;  // Set to the DAG pattern for this instruction
+  list<Register> Uses = []; 
+  list<Register> Defs = [];
+  list<Predicate> Predicates = [];  // predicates turned into isel match code
+  ... remainder not shown for space ...
+}
+

A SelectionDAG node (SDNode) should contain an object +representing a target-specific instruction that is defined in XXXInstrInfo.td. The +instruction objects should represent instructions from the architecture manual +of the target machine (such as the +SPARC Architecture Manual for the SPARC target).

+ +

A single +instruction from the architecture manual is often modeled as multiple target +instructions, depending upon its operands. For example, a manual might +describe an add instruction that takes a register or an immediate operand. An +LLVM target could model this with two instructions named ADDri and ADDrr.

+ +

You should define a +class for each instruction category and define each opcode as a subclass of the +category with appropriate parameters such as the fixed binary encoding of +opcodes and extended opcodes. You should map the register bits to the bits of +the instruction in which they are encoded (for the JIT). Also you should specify +how the instruction should be printed when the automatic assembly printer is +used.

+ +

As is described in +the SPARC Architecture Manual, Version 8, there are three major 32-bit formats +for instructions. Format 1 is only for the CALL instruction. Format 2 is for +branch on condition codes and SETHI (set high bits of a register) instructions. +Format 3 is for other instructions.

+ +

Each of these +formats has corresponding classes in SparcInstrFormat.td. InstSP is a base +class for other instruction classes. Additional base classes are specified for +more precise formats: for example in SparcInstrFormat.td, F2_1 is for SETHI, +and F2_2 is for branches. There are three other base classes: F3_1 for +register/register operations, F3_2 for register/immediate operations, and F3_3 for +floating-point operations. SparcInstrInfo.td also adds the base class Pseudo for +synthetic SPARC instructions.

+ +

SparcInstrInfo.td +largely consists of operand and instruction definitions for the SPARC target. In +SparcInstrInfo.td, the following target description file entry, LDrr, defines +the Load Integer instruction for a Word (the LD SPARC opcode) from a memory +address to a register. The first parameter, the value 3 (11₂), is +the operation value for this category of operation. The second parameter +(000000₂) is the specific operation value for LD/Load Word. The +third parameter is the output destination, which is a register operand and +defined in the Register target description file (IntRegs).

def LDrr : F3_1 <3, 0b000000, (outs IntRegs:$dst), (ins MEMrr:$addr),
+                 "ld [$addr], $dst",
+                 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
+

+ +

The fourth +parameter is the input source, which uses the address operand MEMrr that is +defined earlier in SparcInstrInfo.td:

def MEMrr : Operand<i32> {
+  let PrintMethod = "printMemOperand";
+  let MIOperandInfo = (ops IntRegs, IntRegs);
+}
+

The fifth parameter is a string that is used by the assembly +printer and can be left as an empty string until the assembly printer interface +is implemented. The sixth and final parameter is the pattern used to match the +instruction during the SelectionDAG Select Phase described in +(The LLVM Target-Independent Code Generator). +This parameter is detailed in the next section, Instruction Selector.

+ +

Instruction class definitions are not overloaded for different +operand types, so separate versions of instructions are needed for register, +memory, or immediate value operands. For example, to perform a +Load Integer instruction for a Word +from an immediate operand to a register, the following instruction class is +defined:

def LDri : F3_2 <3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr),
+                 "ld [$addr], $dst",
+                 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
+

Writing these definitions for so many similar instructions can +involve a lot of cut and paste. In td files, the multiclass directive enables +the creation of templates to define several instruction classes at once (using +the defm directive). For example in +SparcInstrInfo.td, the multiclass pattern F3_12 is defined to create 2 +instruction classes each time F3_12 is invoked:

multiclass F3_12 <string OpcStr, bits<6> Op3Val, SDNode OpNode> {
+  def rr  : F3_1 <2, Op3Val, 
+                 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
+                 !strconcat(OpcStr, " $b, $c, $dst"),
+                 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
+  def ri  : F3_2 <2, Op3Val,
+                 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
+                 !strconcat(OpcStr, " $b, $c, $dst"),
+                 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>;
+}
+

So when the defm directive is used for the XOR and ADD +instructions, as seen below, it creates four instruction objects: XORrr, XORri, +ADDrr, and ADDri.

defm XOR   : F3_12<"xor", 0b000011, xor>;
+defm ADD   : F3_12<"add", 0b000000, add>;
+

+ +

SparcInstrInfo.td +also includes definitions for condition codes that are referenced by branch +instructions. The following definitions in SparcInstrInfo.td indicate the bit location +of the SPARC condition code; for example, the 10^th bit represents +the ‘greater than’ condition for integers, and the 22^nd bit +represents the ‘greater than’ condition for floats.

+ +

def ICC_NE  : ICC_VAL< 9>;  // Not Equal
+def ICC_E   : ICC_VAL< 1>;  // Equal
+def ICC_G   : ICC_VAL<10>;  // Greater
+...
+def FCC_U   : FCC_VAL<23>;  // Unordered
+def FCC_G   : FCC_VAL<22>;  // Greater
+def FCC_UG  : FCC_VAL<21>;  // Unordered or Greater
+...
+

+ +

(Note that Sparc.h +also defines enums that correspond to the same SPARC condition codes. Care must +be taken to ensure the values in Sparc.h correspond to the values in +SparcInstrInfo.td; that is, SPCC::ICC_NE = 9, SPCC::FCC_U = 23 and so on.)

+ + +

+ Implement a subclass of + TargetInstrInfo +

+ +

The final step is to hand code portions of XXXInstrInfo, which +implements the interface described in TargetInstrInfo.h. These functions return +0 or a Boolean or they assert, unless overridden. Here's a list of functions +that are overridden for the SPARC implementation in SparcInstrInfo.cpp:

isMoveInstr (return true if the instruction is a register to +register move; false, otherwise)
isLoadFromStackSlot (if the specified machine instruction is a +direct load from a stack slot, return the register number of the destination +and the FrameIndex of the stack slot)
isStoreToStackSlot (if the specified machine instruction is a +direct store to a stack slot, return the register number of the destination and +the FrameIndex of the stack slot)
copyRegToReg (copy values between a pair of registers)
storeRegToStackSlot (store a register value to a stack slot)
loadRegFromStackSlot (load a register value from a stack slot)
storeRegToAddr (store a register value to memory)
loadRegFromAddr (load a register value from memory)
foldMemoryOperand (attempt to combine instructions of any load or +store instruction for the specified operand(s))

+ + +

+ Branch Folding and If Conversion +

Performance can be improved by combining instructions or by eliminating +instructions that are never reached. The AnalyzeBranch method in XXXInstrInfo may +be implemented to examine conditional instructions and remove unnecessary +instructions. AnalyzeBranch looks at the end of a machine basic block (MBB) for +opportunities for improvement, such as branch folding and if conversion. The +BranchFolder and IfConverter machine function passes (see the source files +BranchFolding.cpp and IfConversion.cpp in the lib/CodeGen directory) call +AnalyzeBranch to improve the control flow graph that represents the +instructions.

+ +

Several implementations of AnalyzeBranch (for ARM, Alpha, and +X86) can be examined as models for your own AnalyzeBranch implementation. Since +SPARC does not implement a useful AnalyzeBranch, the ARM target implementation +is shown below.

AnalyzeBranch returns a Boolean value and takes four parameters:

Code generator - - describes some of the classes in code generation at a high level, but - it is not (yet) complete
TableGen fundamentals - - describes how to use TableGen to describe your target information - succinctly
Debugging code generation with - bugpoint - shows bugpoint usage scenarios to simplify backend - development
MachineBasicBlock &MBB – the incoming block to be +examined
MachineBasicBlock *&TBB – a destination block that is +returned; for a conditional branch that evaluates to true, TBB is the +destination
MachineBasicBlock *&FBB – for a conditional branch that +evaluates to false, FBB is returned as the destination
std::vector<MachineOperand> &Cond – list of +operands to evaluate a condition for a conditional branch

In the simplest case, if a block ends without a branch, then it +falls through to the successor block. No destination blocks are specified for +either TBB or FBB, so both parameters return NULL. The start of the AnalyzeBranch +(see code below for the ARM target) shows the function parameters and the code +for the simplest case.

+ +

bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
+        MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
+        std::vector<MachineOperand> &Cond) const
+{
+  MachineBasicBlock::iterator I = MBB.end();
+  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
+    return false;
+

+ +

If a block ends with a single unconditional branch instruction, +then AnalyzeBranch (shown below) should return the destination of that branch +in the TBB parameter.

+ +

if (LastOpc == ARM::B || LastOpc == ARM::tB) {
+      TBB = LastInst->getOperand(0).getMBB();
+      return false;
+    }
+

+ +

If a block ends with two unconditional branches, then the second +branch is never reached. In that situation, as shown below, remove the last +branch instruction and return the penultimate branch in the TBB parameter.

+ +

if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
+      (LastOpc == ARM::B || LastOpc == ARM::tB)) {
+    TBB = SecondLastInst->getOperand(0).getMBB();
+    I = LastInst;
+    I->eraseFromParent();
+    return false;
+  }
+

A block may end with a single conditional branch instruction that +falls through to successor block if the condition evaluates to false. In that +case, AnalyzeBranch (shown below) should return the destination of that +conditional branch in the TBB parameter and a list of operands in the Cond +parameter to evaluate the condition.

+ +

if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
+      // Block ends with fall-through condbranch.
+      TBB = LastInst->getOperand(0).getMBB();
+      Cond.push_back(LastInst->getOperand(1));
+      Cond.push_back(LastInst->getOperand(2));
+      return false;
+    }
+

+ +

If a block ends with both a conditional branch and an ensuing +unconditional branch, then AnalyzeBranch (shown below) should return the +conditional branch destination (assuming it corresponds to a conditional +evaluation of ‘true’) in the TBB parameter and the unconditional branch +destination in the FBB (corresponding to a conditional evaluation of ‘false’). +A list of operands to evaluate the condition should be returned in the Cond +parameter.

+ +

unsigned SecondLastOpc = SecondLastInst->getOpcode();
+  if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
+      (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
+    TBB =  SecondLastInst->getOperand(0).getMBB();
+    Cond.push_back(SecondLastInst->getOperand(1));
+    Cond.push_back(SecondLastInst->getOperand(2));
+    FBB = LastInst->getOperand(0).getMBB();
+    return false;
+  }
+

+ +

For the last two cases (ending with a single conditional branch or +ending with one conditional and one unconditional branch), the operands returned +in the Cond parameter can be passed to methods of other instructions to create +new branches or perform other operations. An implementation of AnalyzeBranch +requires the helper methods RemoveBranch and InsertBranch to manage subsequent +operations.

+ +

AnalyzeBranch should return false indicating success in most circumstances. +AnalyzeBranch should only return true when the method is stumped about what to +do, for example, if a block has three terminating branches. AnalyzeBranch may +return true if it encounters a terminator it cannot handle, such as an indirect +branch.

+ + +

+ Instruction Selector +

+ + +

LLVM uses a SelectionDAG to represent LLVM IR instructions, and nodes +of the SelectionDAG ideally represent native target instructions. During code +generation, instruction selection passes are performed to convert non-native +DAG instructions into native target-specific instructions. The pass described +in XXXISelDAGToDAG.cpp is used to match patterns and perform DAG-to-DAG +instruction selection. Optionally, a pass may be defined (in +XXXBranchSelector.cpp) to perform similar DAG-to-DAG operations for branch +instructions. Later, +the code in XXXISelLowering.cpp replaces or removes operations and data types +not supported natively (legalizes) in a Selection DAG.

+ +

TableGen generates code for instruction selection using the +following target description input files:

XXXInstrInfo.td contains definitions of instructions in a +target-specific instruction set, generates XXXGenDAGISel.inc, which is included +in XXXISelDAGToDAG.cpp.
XXXCallingConv.td contains the calling and return value conventions +for the target architecture, and it generates XXXGenCallingConv.inc, which is +included in XXXISelLowering.cpp.

+ +

The implementation of an instruction selection pass must include +a header that declares the FunctionPass class or a subclass of FunctionPass. In +XXXTargetMachine.cpp, a Pass Manager (PM) should add each instruction selection +pass into the queue of passes to run.

+ +

The LLVM static +compiler (llc) is an excellent tool for visualizing the contents of DAGs. To display +the SelectionDAG before or after specific processing phases, use the command +line options for llc, described at +SelectionDAG Instruction Selection Process. +

+ +

To describe instruction selector behavior, you should add +patterns for lowering LLVM code into a SelectionDAG as the last parameter of +the instruction definitions in XXXInstrInfo.td. For example, in +SparcInstrInfo.td, this entry defines a register store operation, and the last +parameter describes a pattern with the store DAG operator.

+ +

def STrr  : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src),
+                 "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>;
+

+ +

ADDRrr is a memory mode that is also defined in SparcInstrInfo.td:

+ +

def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
+

+ +

The definition of ADDRrr refers to SelectADDRrr, which is a function defined in an +implementation of the Instructor Selector (such as SparcISelDAGToDAG.cpp).

+ +

In lib/Target/TargetSelectionDAG.td, the DAG operator for store +is defined below:

+ +

def store : PatFrag<(ops node:$val, node:$ptr),
+                    (st node:$val, node:$ptr), [{
+  if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
+    return !ST->isTruncatingStore() && 
+           ST->getAddressingMode() == ISD::UNINDEXED;
+  return false;
+}]>;
+

XXXInstrInfo.td also generates (in XXXGenDAGISel.inc) the +SelectCode method that is used to call the appropriate processing method for an +instruction. In this example, SelectCode calls Select_ISD_STORE for the +ISD::STORE opcode.

+ +

SDNode *SelectCode(SDOperand N) {
+  ... 
+  MVT::ValueType NVT = N.Val->getValueType(0);
+  switch (N.getOpcode()) {
+  case ISD::STORE: {
+    switch (NVT) {
+    default:
+      return Select_ISD_STORE(N);
+      break;
+    }
+    break;
+  }
+  ...
+

The pattern for STrr is matched, so elsewhere in +XXXGenDAGISel.inc, code for STrr is created for Select_ISD_STORE. The Emit_22 method +is also generated in XXXGenDAGISel.inc to complete the processing of this +instruction.

+ +

SDNode *Select_ISD_STORE(const SDOperand &N) {
+  SDOperand Chain = N.getOperand(0);
+  if (Predicate_store(N.Val)) {
+    SDOperand N1 = N.getOperand(1);
+    SDOperand N2 = N.getOperand(2);
+    SDOperand CPTmp0;
+    SDOperand CPTmp1;
+ 
+    // Pattern: (st:void IntRegs:i32:$src, 
+    //           ADDRrr:i32:$addr)<<P:Predicate_store>>
+    // Emits: (STrr:void ADDRrr:i32:$addr, IntRegs:i32:$src)
+    // Pattern complexity = 13  cost = 1  size = 0
+    if (SelectADDRrr(N, N2, CPTmp0, CPTmp1) &&
+        N1.Val->getValueType(0) == MVT::i32 &&
+        N2.Val->getValueType(0) == MVT::i32) {
+      return Emit_22(N, SP::STrr, CPTmp0, CPTmp1);
+    }
+...
+

+ + +

+ The SelectionDAG Legalize Phase +

The Legalize phase converts a DAG to use types and operations +that are natively supported by the target. For natively unsupported types and +operations, you need to add code to the target-specific XXXTargetLowering implementation +to convert unsupported types and operations to supported ones.

+ +

In the constructor for the XXXTargetLowering class, first use the +addRegisterClass method to specify which types are supports and which register +classes are associated with them. The code for the register classes are generated +by TableGen from XXXRegisterInfo.td and placed in XXXGenRegisterInfo.h.inc. For +example, the implementation of the constructor for the SparcTargetLowering +class (in SparcISelLowering.cpp) starts with the following code:

+ +

addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
+addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
+addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 
+

+ +

You should examine the node types in the ISD namespace +(include/llvm/CodeGen/SelectionDAGNodes.h) +and determine which operations the target natively supports. For operations +that do not have native support, add a callback to the constructor for +the XXXTargetLowering class, so the instruction selection process knows what to +do. The TargetLowering class callback methods (declared in +llvm/Target/TargetLowering.h) are:

setOperationAction (general operation)
setLoadExtAction (load with extension)
setTruncStoreAction (truncating store)
setIndexedLoadAction (indexed load)
setIndexedStoreAction (indexed store)
setConvertAction (type conversion)
setCondCodeAction (support for a given condition code)

+ +

Note: on older releases, setLoadXAction is used instead of setLoadExtAction. +Also, on older releases, setCondCodeAction may not be supported. Examine your +release to see what methods are specifically supported.

+ +

These callbacks are used to determine that an operation does or +does not work with a specified type (or types). And in all cases, the third +parameter is a LegalAction type enum value: Promote, Expand, +Custom, or Legal. SparcISelLowering.cpp +contains examples of all four LegalAction values.

+ + +

+ Promote +

+ +

For an operation without native support for a given type, the +specified type may be promoted to a larger type that is supported. For example, +SPARC does not support a sign-extending load for Boolean values (i1 type), so +in SparcISelLowering.cpp the third +parameter below, Promote, changes i1 type +values to a large type before loading.

+ +

setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+

+ + +

+ Expand +

For a type without native support, a value may need to be broken +down further, rather than promoted. For an operation without native support, a +combination of other operations may be used to similar effect. In SPARC, the +floating-point sine and cosine trig operations are supported by expansion to +other operations, as indicated by the third parameter, Expand, to +setOperationAction:

+ +

setOperationAction(ISD::FSIN, MVT::f32, Expand);
+setOperationAction(ISD::FCOS, MVT::f32, Expand);
+

+ + +

+ Custom +

For some operations, simple type promotion or operation expansion +may be insufficient. In some cases, a special intrinsic function must be +implemented.

+ +

For example, a constant value may require special treatment, or +an operation may require spilling and restoring registers in the stack and +working with register allocators.

+ +

As seen in SparcISelLowering.cpp code below, to perform a type +conversion from a floating point value to a signed integer, first the +setOperationAction should be called with Custom as the third parameter:

+ +

setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
+

In the LowerOperation method, for each Custom operation, a case +statement should be added to indicate what function to call. In the following +code, an FP_TO_SINT opcode will call the LowerFP_TO_SINT method:

+ +

SDOperand SparcTargetLowering::LowerOperation(
+                               SDOperand Op, SelectionDAG &DAG) {
+  switch (Op.getOpcode()) {
+  case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
+  ...
+  }
+}
+

Finally, the LowerFP_TO_SINT method is implemented, using an FP +register to convert the floating-point value to an integer.

+ +

static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
+assert(Op.getValueType() == MVT::i32);
+  Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
+  return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
+}
+

+ +

+ Legal +

The Legal LegalizeAction enum value simply indicates that an +operation is natively supported. Legal represents the default condition, +so it is rarely used. In SparcISelLowering.cpp, the action for CTPOP (an +operation to count the bits set in an integer) is natively supported only for +SPARC v9. The following code enables the Expand conversion technique for non-v9 +SPARC implementations.

+ +

setOperationAction(ISD::CTPOP, MVT::i32, Expand);
+...
+if (TM.getSubtarget<SparcSubtarget>().isV9())
+  setOperationAction(ISD::CTPOP, MVT::i32, Legal);
+  case ISD::SETULT: return SPCC::ICC_CS;
+  case ISD::SETULE: return SPCC::ICC_LEU;
+  case ISD::SETUGT: return SPCC::ICC_GU;
+  case ISD::SETUGE: return SPCC::ICC_CC;
+  }
+}
+

+ +

+ Calling Conventions +

To support target-specific calling conventions, XXXGenCallingConv.td +uses interfaces (such as CCIfType and CCAssignToReg) that are defined in +lib/Target/TargetCallingConv.td. TableGen can take the target descriptor file +XXXGenCallingConv.td and generate the header file XXXGenCallingConv.inc, which +is typically included in XXXISelLowering.cpp. You can use the interfaces in +TargetCallingConv.td to specify:

the order of parameter allocation
where parameters and return values are placed (that is, on the +stack or in registers)
which registers may be used
whether the caller or callee unwinds the stack

+ +

The following example demonstrates the use of the CCIfType and +CCAssignToReg interfaces. If the CCIfType predicate is true (that is, if the +current argument is of type f32 or f64), then the action is performed. In this +case, the CCAssignToReg action assigns the argument value to the first +available register: either R0 or R1.

CCIfType<[f32,f64], CCAssignToReg<[R0, R1]>>
+

SparcCallingConv.td contains definitions for a target-specific return-value +calling convention (RetCC_Sparc32) and a basic 32-bit C calling convention +(CC_Sparc32). The definition of RetCC_Sparc32 (shown below) indicates which +registers are used for specified scalar return types. A single-precision float +is returned to register F0, and a double-precision float goes to register D0. A +32-bit integer is returned in register I0 or I1.

+ +

def RetCC_Sparc32 : CallingConv<[
+  CCIfType<[i32], CCAssignToReg<[I0, I1]>>,
+  CCIfType<[f32], CCAssignToReg<[F0]>>,
+  CCIfType<[f64], CCAssignToReg<[D0]>>
+]>;
+

The definition of CC_Sparc32 in SparcCallingConv.td introduces +CCAssignToStack, which assigns the value to a stack slot with the specified size +and alignment. In the example below, the first parameter, 4, indicates the size +of the slot, and the second parameter, also 4, indicates the stack alignment +along 4-byte units. (Special cases: if size is zero, then the ABI size is used; +if alignment is zero, then the ABI alignment is used.)

+ +

def CC_Sparc32 : CallingConv<[
+  // All arguments get passed in integer registers if there is space.
+  CCIfType<[i32, f32, f64], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
+  CCAssignToStack<4, 4>
+]>;
+

CCDelegateTo is another commonly used interface, which tries to find +a specified sub-calling convention and, if a match is found, it is invoked. In +the following example (in X86CallingConv.td), the definition of RetCC_X86_32_C +ends with CCDelegateTo. After the current value is assigned to the register ST0 +or ST1, the RetCC_X86Common is invoked.

+ +

def RetCC_X86_32_C : CallingConv<[
+  CCIfType<[f32], CCAssignToReg<[ST0, ST1]>>,
+  CCIfType<[f64], CCAssignToReg<[ST0, ST1]>>,
+  CCDelegateTo<RetCC_X86Common>
+]>;
+

CCIfCC is an interface that attempts to match the given name to +the current calling convention. If the name identifies the current calling +convention, then a specified action is invoked. In the following example (in +X86CallingConv.td), if the Fast calling convention is in use, then RetCC_X86_32_Fast +is invoked. If the SSECall calling convention is in use, then RetCC_X86_32_SSE +is invoked.

+ +

def RetCC_X86_32 : CallingConv<[
+  CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
+  CCIfCC<"CallingConv::X86_SSECall", CCDelegateTo<RetCC_X86_32_SSE>>,
+  CCDelegateTo<RetCC_X86_32_C>
+]>;
+

Other calling convention interfaces include:

CCIf <predicate, action> - if the predicate matches, apply +the action
CCIfInReg <action> - if the argument is marked with the +‘inreg’ attribute, then apply the action
CCIfNest <action> - if the argument is marked with the +‘nest’ attribute, then apply the action
CCIfNotVarArg <action> - if the current function does not +take a variable number of arguments, apply the action
CCAssignToRegWithShadow <registerList, shadowList> - +similar to CCAssignToReg, but with a shadow list of registers
CCPassByVal <size, align> - assign value to a stack slot +with the minimum specified size and alignment
CCPromoteToType <type> - promote the current value to the specified +type
CallingConv <[actions]> - define each calling convention +that is supported

+ + +

+ Assembly Printer +

+ + +

During the code +emission stage, the code generator may utilize an LLVM pass to produce assembly +output. To do this, you want to implement the code for a printer that converts +LLVM IR to a GAS-format assembly language for your target machine, using the +following steps:

Define all the assembly strings for your target, adding them to +the instructions defined in the XXXInstrInfo.td file. +(See Instruction Set.) +TableGen will produce an output file (XXXGenAsmWriter.inc) with an +implementation of the printInstruction method for the XXXAsmPrinter class.
Write XXXTargetAsmInfo.h, which contains the bare-bones +declaration of the XXXTargetAsmInfo class (a subclass of TargetAsmInfo).
Write XXXTargetAsmInfo.cpp, which contains target-specific values +for TargetAsmInfo properties and sometimes new implementations for methods
Write XXXAsmPrinter.cpp, which implements the AsmPrinter class +that performs the LLVM-to-assembly conversion.

+ +

The code in XXXTargetAsmInfo.h is usually a trivial declaration +of the XXXTargetAsmInfo class for use in XXXTargetAsmInfo.cpp. Similarly, +XXXTargetAsmInfo.cpp usually has a few declarations of XXXTargetAsmInfo replacement +values that override the default values in TargetAsmInfo.cpp. For example in +SparcTargetAsmInfo.cpp,

+ +

SparcTargetAsmInfo::SparcTargetAsmInfo(const SparcTargetMachine &TM) {
+  Data16bitsDirective = "\t.half\t";
+  Data32bitsDirective = "\t.word\t";
+  Data64bitsDirective = 0;  // .xword is only supported by V9.
+  ZeroDirective = "\t.skip\t";
+  CommentString = "!";
+  ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
+}
+

The X86 assembly printer implementation (X86TargetAsmInfo) is an +example where the target specific TargetAsmInfo class uses overridden methods: +ExpandInlineAsm and PreferredEHDataFormat.

+ +

A target-specific implementation of AsmPrinter is written in +XXXAsmPrinter.cpp, which implements the AsmPrinter class that converts the LLVM +to printable assembly. The implementation must include the following headers +that have declarations for the AsmPrinter and MachineFunctionPass classes. The +MachineFunctionPass is a subclass of FunctionPass.

+ +

#include "llvm/CodeGen/AsmPrinter.h"
+#include "llvm/CodeGen/MachineFunctionPass.h" 
+

+ +

As a FunctionPass, AsmPrinter first calls doInitialization to set +up the AsmPrinter. In SparcAsmPrinter, a Mangler object is instantiated to +process variable names.

+ +

In XXXAsmPrinter.cpp, the runOnMachineFunction method (declared +in MachineFunctionPass) must be implemented for XXXAsmPrinter. In +MachineFunctionPass, the runOnFunction method invokes runOnMachineFunction. +Target-specific implementations of runOnMachineFunction differ, but generally +do the following to process each machine function:

call SetupMachineFunction to perform initialization
call EmitConstantPool to print out (to the output stream) +constants which have been spilled to memory
call EmitJumpTableInfo to print out jump tables used by the +current function
print out the label for the current function
print out the code for the function, including basic block labels +and the assembly for the instruction (using printInstruction)

The XXXAsmPrinter implementation must also include the code +generated by TableGen that is output in the XXXGenAsmWriter.inc file. The code +in XXXGenAsmWriter.inc contains an implementation of the printInstruction +method that may call these methods:

printOperand
printMemOperand
printCCOperand (for conditional statements)
printDataDirective
printDeclare
printImplicitDef
printInlineAsm
printLabel
printPICJumpTableEntry
printPICJumpTableSetLabel

+ +

The implementations of printDeclare, printImplicitDef, +printInlineAsm, and printLabel in AsmPrinter.cpp are generally adequate for +printing assembly and do not need to be overridden. (printBasicBlockLabel is +another method that is implemented in AsmPrinter.cpp that may be directly used +in an implementation of XXXAsmPrinter.)

+ +

The printOperand method is implemented with a long switch/case +statement for the type of operand: register, immediate, basic block, external +symbol, global address, constant pool index, or jump table index. For an +instruction with a memory address operand, the printMemOperand method should be +implemented to generate the proper output. Similarly, printCCOperand should be +used to print a conditional operand.

+ +

doFinalization should be overridden in XXXAsmPrinter, and +it should be called to shut down the assembly printer. During doFinalization, +global variables and constants are printed to output.

+ +

+ Subtarget Support +

+ + +

Subtarget support is used to inform the code generation process +of instruction set variations for a given chip set. For example, the LLVM +SPARC implementation provided covers three major versions of the SPARC +microprocessor architecture: Version 8 (V8, which is a 32-bit architecture), +Version 9 (V9, a 64-bit architecture), and the UltraSPARC architecture. V8 has +16 double-precision floating-point registers that are also usable as either 32 +single-precision or 8 quad-precision registers. V8 is also purely big-endian. V9 +has 32 double-precision floating-point registers that are also usable as 16 +quad-precision registers, but cannot be used as single-precision registers. The +UltraSPARC architecture combines V9 with UltraSPARC Visual Instruction Set +extensions.

+ +

If subtarget support is needed, you should implement a +target-specific XXXSubtarget class for your architecture. This class should +process the command-line options –mcpu= and –mattr=

+ +

TableGen uses definitions in the Target.td and Sparc.td files to +generate code in SparcGenSubtarget.inc. In Target.td, shown below, the +SubtargetFeature interface is defined. The first 4 string parameters of the +SubtargetFeature interface are a feature name, an attribute set by the feature, +the value of the attribute, and a description of the feature. (The fifth +parameter is a list of features whose presence is implied, and its default +value is an empty array.)

+ +

class SubtargetFeature<string n, string a,  string v, string d,
+                       list<SubtargetFeature> i = []> {
+  string Name = n;
+  string Attribute = a;
+  string Value = v;
+  string Desc = d;
+  list<SubtargetFeature> Implies = i;
+}
+

In the Sparc.td file, the SubtargetFeature is used to define the +following features.

+ +

def FeatureV9 : SubtargetFeature<"v9", "IsV9", "true",
+                     "Enable SPARC-V9 instructions">;
+def FeatureV8Deprecated : SubtargetFeature<"deprecated-v8", 
+                     "V8DeprecatedInsts", "true",
+                     "Enable deprecated V8 instructions in V9 mode">;
+def FeatureVIS : SubtargetFeature<"vis", "IsVIS", "true",
+                     "Enable UltraSPARC Visual Instruction Set extensions">;
+

+ +

Elsewhere in Sparc.td, the Proc class is defined and then is used +to define particular SPARC processor subtypes that may have the previously +described features.

+ +

class Proc<string Name, list<SubtargetFeature> Features>
+ : Processor<Name, NoItineraries, Features>;
+ 
+def : Proc<"generic",         []>;
+def : Proc<"v8",              []>;
+def : Proc<"supersparc",      []>;
+def : Proc<"sparclite",       []>;
+def : Proc<"f934",            []>;
+def : Proc<"hypersparc",      []>;
+def : Proc<"sparclite86x",    []>;
+def : Proc<"sparclet",        []>;
+def : Proc<"tsc701",          []>;
+def : Proc<"v9",              [FeatureV9]>;
+def : Proc<"ultrasparc",      [FeatureV9, FeatureV8Deprecated]>;
+def : Proc<"ultrasparc3",     [FeatureV9, FeatureV8Deprecated]>;
+def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
+

+ +

From Target.td and Sparc.td files, the resulting +SparcGenSubtarget.inc specifies enum values to identify the features, arrays of +constants to represent the CPU features and CPU subtypes, and the +ParseSubtargetFeatures method that parses the features string that sets +specified subtarget options. The generated SparcGenSubtarget.inc file should be +included in the SparcSubtarget.cpp. The target-specific implementation of the XXXSubtarget +method should follow this pseudocode:

+ +

XXXSubtarget::XXXSubtarget(const Module &M, const std::string &FS) {
+  // Set the default features
+  // Determine default and user specified characteristics of the CPU
+  // Call ParseSubtargetFeatures(FS, CPU) to parse the features string
+  // Perform any additional operations
+}
+

+ + +

+ JIT Support +

+ + +

The implementation of a target machine optionally includes a Just-In-Time +(JIT) code generator that emits machine code and auxiliary structures as binary +output that can be written directly to memory. +To do this, implement JIT code generation by performing the following +steps:

Write an XXXCodeEmitter.cpp file that contains a machine function +pass that transforms target-machine instructions into relocatable machine code.
Write an XXXJITInfo.cpp file that implements the JIT interfaces +for target-specific code-generation +activities, such as emitting machine code and stubs.
Modify XXXTargetMachine so that it provides a TargetJITInfo +object through its getJITInfo method.

+ +

There are several different approaches to writing the JIT support +code. For instance, TableGen and target descriptor files may be used for +creating a JIT code generator, but are not mandatory. For the Alpha and PowerPC +target machines, TableGen is used to generate XXXGenCodeEmitter.inc, which +contains the binary coding of machine instructions and the +getBinaryCodeForInstr method to access those codes. Other JIT implementations +do not.

+ +

Both XXXJITInfo.cpp and XXXCodeEmitter.cpp must include the +llvm/CodeGen/MachineCodeEmitter.h header file that defines the MachineCodeEmitter +class containing code for several callback functions that write data (in bytes, +words, strings, etc.) to the output stream.

+ +

+ Machine Code Emitter +

+ +

In XXXCodeEmitter.cpp, a target-specific of the Emitter class is +implemented as a function pass (subclass of MachineFunctionPass). The +target-specific implementation of runOnMachineFunction (invoked by +runOnFunction in MachineFunctionPass) iterates through the MachineBasicBlock +calls emitInstruction to process each instruction and emit binary code. emitInstruction +is largely implemented with case statements on the instruction types defined in +XXXInstrInfo.h. For example, in X86CodeEmitter.cpp, the emitInstruction method +is built around the following switch/case statements:

+ +

switch (Desc->TSFlags & X86::FormMask) {
+case X86II::Pseudo:  // for not yet implemented instructions 
+   ...               // or pseudo-instructions
+   break;
+case X86II::RawFrm:  // for instructions with a fixed opcode value
+   ...
+   break;
+case X86II::AddRegFrm: // for instructions that have one register operand 
+   ...                 // added to their opcode
+   break;
+case X86II::MRMDestReg:// for instructions that use the Mod/RM byte
+   ...                 // to specify a destination (register)
+   break;
+case X86II::MRMDestMem:// for instructions that use the Mod/RM byte
+   ...                 // to specify a destination (memory)
+   break;
+case X86II::MRMSrcReg: // for instructions that use the Mod/RM byte
+   ...                 // to specify a source (register)
+   break;
+case X86II::MRMSrcMem: // for instructions that use the Mod/RM byte
+   ...                 // to specify a source (memory)
+   break;
+case X86II::MRM0r: case X86II::MRM1r:  // for instructions that operate on 
+case X86II::MRM2r: case X86II::MRM3r:  // a REGISTER r/m operand and
+case X86II::MRM4r: case X86II::MRM5r:  // use the Mod/RM byte and a field
+case X86II::MRM6r: case X86II::MRM7r:  // to hold extended opcode data
+   ...  
+   break;
+case X86II::MRM0m: case X86II::MRM1m:  // for instructions that operate on
+case X86II::MRM2m: case X86II::MRM3m:  // a MEMORY r/m operand and
+case X86II::MRM4m: case X86II::MRM5m:  // use the Mod/RM byte and a field
+case X86II::MRM6m: case X86II::MRM7m:  // to hold extended opcode data
+   ...  
+   break;
+case X86II::MRMInitReg: // for instructions whose source and
+   ...                  // destination are the same register
+   break;
+}
+

The implementations of these case statements often first emit the +opcode and then get the operand(s). Then depending upon the operand, helper +methods may be called to process the operand(s). For example, in X86CodeEmitter.cpp, +for the X86II::AddRegFrm case, the first data emitted (by emitByte) is the +opcode added to the register operand. Then an object representing the machine +operand, MO1, is extracted. The helper methods such as isImmediate, +isGlobalAddress, isExternalSymbol, isConstantPoolIndex, and +isJumpTableIndex +determine the operand type. (X86CodeEmitter.cpp also has private methods such +as emitConstant, emitGlobalAddress, +emitExternalSymbolAddress, emitConstPoolAddress, +and emitJumpTableAddress that emit the data into the output stream.)

+ +

case X86II::AddRegFrm:
+  MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
+  
+  if (CurOp != NumOps) {
+    const MachineOperand &MO1 = MI.getOperand(CurOp++);
+    unsigned Size = X86InstrInfo::sizeOfImm(Desc);
+    if (MO1.isImmediate())
+      emitConstant(MO1.getImm(), Size);
+    else {
+      unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
+        : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
+      if (Opcode == X86::MOV64ri) 
+        rt = X86::reloc_absolute_dword;  // FIXME: add X86II flag?
+      if (MO1.isGlobalAddress()) {
+        bool NeedStub = isa<Function>(MO1.getGlobal());
+        bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
+        emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
+                          NeedStub, isLazy);
+      } else if (MO1.isExternalSymbol())
+        emitExternalSymbolAddress(MO1.getSymbolName(), rt);
+      else if (MO1.isConstantPoolIndex())
+        emitConstPoolAddress(MO1.getIndex(), rt);
+      else if (MO1.isJumpTableIndex())
+        emitJumpTableAddress(MO1.getIndex(), rt);
+    }
+  }
+  break;
+

In the previous example, XXXCodeEmitter.cpp uses the variable rt, +which is a RelocationType enum that may be used to relocate addresses (for +example, a global address with a PIC base offset). The RelocationType enum for +that target is defined in the short target-specific XXXRelocations.h file. The +RelocationType is used by the relocate method defined in XXXJITInfo.cpp to +rewrite addresses for referenced global symbols.

+ +

For example, X86Relocations.h specifies the following relocation +types for the X86 addresses. In all four cases, the relocated value is added to +the value already in memory. For reloc_pcrel_word and reloc_picrel_word, +there is an additional initial adjustment.

+ +

enum RelocationType {
+  reloc_pcrel_word = 0,  // add reloc value after adjusting for the PC loc
+  reloc_picrel_word = 1, // add reloc value after adjusting for the PIC base
+  reloc_absolute_word = 2, // absolute relocation; no additional adjustment 
+  reloc_absolute_dword = 3 // absolute relocation; no additional adjustment
+};
+

+ +

+ Target JIT Info +

XXXJITInfo.cpp implements the JIT interfaces for target-specific code-generation +activities, such as emitting machine code and stubs. At minimum, +a target-specific version of XXXJITInfo implements the following:

getLazyResolverFunction – initializes the JIT, gives the +target a function that is used for compilation
emitFunctionStub – returns a native function with a +specified address for a callback function
relocate – changes the addresses of referenced globals, +based on relocation types
callback function that are wrappers to a function stub that is +used when the real target is not initially known

+ +

getLazyResolverFunction is generally trivial to implement. It +makes the incoming parameter as the global JITCompilerFunction and returns the +callback function that will be used a function wrapper. For the Alpha target +(in AlphaJITInfo.cpp), the getLazyResolverFunction implementation is simply:

+ +

TargetJITInfo::LazyResolverFn AlphaJITInfo::getLazyResolverFunction(  
+                                            JITCompilerFn F) 
+{
+  JITCompilerFunction = F;
+  return AlphaCompilationCallback;
+}
+

For the X86 target, the getLazyResolverFunction implementation is +a little more complication, because it returns a different callback function +for processors with SSE instructions and XMM registers.

+ +

The callback function initially saves and later restores the +callee register values, incoming arguments, and frame and return address. The +callback function needs low-level access to the registers or stack, so it is typically +implemented with assembler.

@@ -300,7 +2069,7 @@

- Misha Brukman
+ Mason Woo and Misha Brukman
The LLVM Compiler Infrastructure
Last modified: $Date$ From sabre at nondot.org Tue Nov 11 13:31:26 2008 From: sabre at nondot.org (Chris Lattner) Date: Tue, 11 Nov 2008 19:31:26 -0000 Subject: [llvm-commits] [llvm] r59067 - /llvm/trunk/docs/WritingAnLLVMBackend.html Message-ID: <200811111931.mABJVQiN004137@zion.cs.uiuc.edu> Author: lattner Date: Tue Nov 11 13:31:26 2008 New Revision: 59067 URL: http://llvm.org/viewvc/llvm-project?rev=59067&view=rev Log: remove an extraneous tag Modified: llvm/trunk/docs/WritingAnLLVMBackend.html Modified: llvm/trunk/docs/WritingAnLLVMBackend.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/WritingAnLLVMBackend.html?rev=59067&r1=59066&r2=59067&view=diff ============================================================================== --- llvm/trunk/docs/WritingAnLLVMBackend.html (original) +++ llvm/trunk/docs/WritingAnLLVMBackend.html Tue Nov 11 13:31:26 2008 @@ -8,7 +8,7 @@ -

Writing an LLVM Compiler Backend

From dpatel at apple.com Tue Nov 11 13:33:39 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 11 Nov 2008 19:33:39 -0000 Subject: [llvm-commits] [llvm] r59068 - in /llvm/trunk: include/llvm/LinkAllPasses.h include/llvm/Transforms/IPO.h lib/Transforms/Utils/DbgInfoRemover.cpp Message-ID: <200811111933.mABJXdfA004224@zion.cs.uiuc.edu> Author: dpatel Date: Tue Nov 11 13:33:39 2008 New Revision: 59068 URL: http://llvm.org/viewvc/llvm-project?rev=59068&view=rev Log: Add utility pass to remove dbg info. Added: llvm/trunk/lib/Transforms/Utils/DbgInfoRemover.cpp Modified: llvm/trunk/include/llvm/LinkAllPasses.h llvm/trunk/include/llvm/Transforms/IPO.h Modified: llvm/trunk/include/llvm/LinkAllPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=59068&r1=59067&r2=59068&view=diff ============================================================================== --- llvm/trunk/include/llvm/LinkAllPasses.h (original) +++ llvm/trunk/include/llvm/LinkAllPasses.h Tue Nov 11 13:33:39 2008 @@ -125,6 +125,7 @@ (void) llvm::createMergeFunctionsPass(); (void) llvm::createPrintModulePass(0); (void) llvm::createPrintFunctionPass("", 0); + (void) llvm::createRemoveDbgInfoPass(); (void)new llvm::IntervalPartition(); (void)new llvm::FindUsedTypes(); Modified: llvm/trunk/include/llvm/Transforms/IPO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/IPO.h?rev=59068&r1=59067&r2=59068&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/IPO.h (original) +++ llvm/trunk/include/llvm/Transforms/IPO.h Tue Nov 11 13:33:39 2008 @@ -200,6 +200,13 @@ /// ModulePass *createMergeFunctionsPass(); +//===----------------------------------------------------------------------===// +// +// RemoveDbgInfoPass - This pass removes debug info. intrinsics. +// +ModulePass *createRemoveDbgInfoPass(); + + } // End llvm namespace #endif Added: llvm/trunk/lib/Transforms/Utils/DbgInfoRemover.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/DbgInfoRemover.cpp?rev=59068&view=auto ============================================================================== --- llvm/trunk/lib/Transforms/Utils/DbgInfoRemover.cpp (added) +++ llvm/trunk/lib/Transforms/Utils/DbgInfoRemover.cpp Tue Nov 11 13:33:39 2008 @@ -0,0 +1,97 @@ +//===- DbgInforemover.cpp - Remove Debug Info Intrinsics ------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This is utility pass removes all debug information intrinsics from a +// function. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Transforms/IPO.h" +#include "llvm/Module.h" +#include "llvm/IntrinsicInst.h" +#include "llvm/Pass.h" +#include "llvm/ADT/SmallPtrSet.h" +using namespace llvm; + +namespace { + // Remove dbg intrinsics and related globals from this module. + struct RemoveDbgInfoPass : public ModulePass { + static char ID; // Pass identification, replacement for typeid + RemoveDbgInfoPass() : ModulePass(&ID) {} + + void getAnalysisUsage(AnalysisUsage &Info) const { + Info.setPreservesCFG(); + } + + bool runOnModule(Module &M) { + bool Changed = false; + DbgGlobals.clear(); + + for (Module::iterator I = M.begin(), E = M.end(); I != E; ) { + Function *F = I++; + Changed |= cleanupFunction(*F); + if (F->hasName() && !strncmp(F->getNameStart(), "llvm.dbg", 8)) + M.getFunctionList().erase(F); + } + + for (Module::global_iterator GVI = M.global_begin(), E = M.global_end(); + GVI != E; ) { + GlobalVariable *GV = GVI++; + if (GV->hasName() && !strncmp(GV->getNameStart(), "llvm.dbg", 8)) { + if (GV->hasInitializer()) + CollectDbgGlobals(GV->getInitializer()); + GV->replaceAllUsesWith(UndefValue::get(GV->getType())); + GV->removeDeadConstantUsers(); + M.getGlobalList().erase(GV); + } + } + + for (SmallPtrSet::iterator CI = DbgGlobals.begin(), + CE = DbgGlobals.end(); CI != CE; ) { + GlobalVariable *GV = *CI++; + GV->removeDeadConstantUsers(); + if (GV->use_empty()) + M.getGlobalList().erase(GV); + } + return Changed; + } + + void CollectDbgGlobals(Constant *C) { + if (GlobalVariable *GV = dyn_cast(C)) + DbgGlobals.insert(GV); + for (User::op_iterator I = C->op_begin(), E = C->op_end(); I != E; ++I) + CollectDbgGlobals(cast(*I)); + } + + bool cleanupFunction(Function &F) { + SmallVector WorkList; + for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) + for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) + if (isa(I)) + WorkList.push_back(I); + + for (SmallVector::iterator WI = WorkList.begin(), + WE = WorkList.end(); WI != WE; ++WI) + (*WI)->eraseFromParent(); + + return !WorkList.empty(); + } + + private: + SmallPtrSet DbgGlobals; + }; + + char RemoveDbgInfoPass::ID = 0; + static RegisterPass X("remove-dbginfo", + "Remove Debugging Information"); +} + +ModulePass *llvm::createRemoveDbgInfoPass() { + return new RemoveDbgInfoPass(); +} From sabre at nondot.org Tue Nov 11 13:34:28 2008 From: sabre at nondot.org (Chris Lattner) Date: Tue, 11 Nov 2008 19:34:28 -0000 Subject: [llvm-commits] [llvm] r59069 - /llvm/trunk/docs/WritingAnLLVMBackend.html Message-ID: <200811111934.mABJYSKT004259@zion.cs.uiuc.edu> Author: lattner Date: Tue Nov 11 13:34:28 2008 New Revision: 59069 URL: http://llvm.org/viewvc/llvm-project?rev=59069&view=rev Log: fix some validation errors. Modified: llvm/trunk/docs/WritingAnLLVMBackend.html Modified: llvm/trunk/docs/WritingAnLLVMBackend.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/WritingAnLLVMBackend.html?rev=59069&r1=59068&r2=59069&view=diff ============================================================================== --- llvm/trunk/docs/WritingAnLLVMBackend.html (original) +++ llvm/trunk/docs/WritingAnLLVMBackend.html Tue Nov 11 13:34:28 2008 @@ -21,35 +21,35 @@

Preliminaries

Target Machine

Defining a Register
Defining a Register Class
Implement a subclass of TargetRegisterInfo

Instruction Set

+ +

Instruction Set

Implement a subclass of TargetInstrInfo
Branch Folding and If Conversion

Instruction Selector

+ +

Instruction Selector

The SelectionDAG Legalize Phase
The SelectionDAG Legalize Phase
- Promote
- Expand
- Custom
- Legal
+

- +

Machine Code Emitter
Target JIT Info

@@ -99,7 +99,7 @@ These essential documents must be read before reading this document:

-LLVM Language Reference Manual - +LLVM Language Reference Manual - a reference manual for the LLVM assembly language
From sabre at nondot.org Tue Nov 11 13:35:16 2008 From: sabre at nondot.org (Chris Lattner) Date: Tue, 11 Nov 2008 19:35:16 -0000 Subject: [llvm-commits] [llvm] r59070 - /llvm/trunk/docs/WritingAnLLVMBackend.html Message-ID: <200811111935.mABJZGIo004298@zion.cs.uiuc.edu> Author: lattner Date: Tue Nov 11 13:35:15 2008 New Revision: 59070 URL: http://llvm.org/viewvc/llvm-project?rev=59070&view=rev Log: fix some validation errors -> Modified: llvm/trunk/docs/WritingAnLLVMBackend.html Modified: llvm/trunk/docs/WritingAnLLVMBackend.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/WritingAnLLVMBackend.html?rev=59070&r1=59069&r2=59070&view=diff ============================================================================== --- llvm/trunk/docs/WritingAnLLVMBackend.html (original) +++ llvm/trunk/docs/WritingAnLLVMBackend.html Tue Nov 11 13:35:15 2008 @@ -103,7 +103,7 @@ a reference manual for the LLVM assembly language

-The LLVM Target-Independent Code Generator - +The LLVM Target-Independent Code Generator - a guide to the components (classes and code generation algorithms) for translating the LLVM internal representation to the machine code for a specified target. Pay particular attention to the descriptions of code generation stages: @@ -112,24 +112,24 @@ and Code Emission.

-TableGen Fundamentals - +TableGen Fundamentals - a document that describes the TableGen (tblgen) application that manages domain-specific information to support LLVM code generation. TableGen processes input from a target description file (.td suffix) and generates C++ code that can be used for code generation.

-Writing an LLVM Pass - +Writing an LLVM Pass - The assembly printer is a FunctionPass, as are several SelectionDAG processing steps.

To follow the SPARC examples in this document, have a copy of -The SPARC Architecture Manual, Version 8 +The SPARC Architecture Manual, Version 8 for reference. For details about the ARM instruction set, refer to the -ARM Architecture Reference Manual +ARM Architecture Reference Manual For more about the GNU Assembler format (GAS), see -Using As -especially for the assembly printer. Using As contains lists of target machine dependent features. +Using As +especially for the assembly printer. Using As contains lists of target machine dependent features.

From dpatel at apple.com Tue Nov 11 13:35:39 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 11 Nov 2008 19:35:39 -0000 Subject: [llvm-commits] [llvm] r59071 - /llvm/trunk/tools/lto-bugpoint/ Message-ID: <200811111935.mABJZd43004350@zion.cs.uiuc.edu> Author: dpatel Date: Tue Nov 11 13:35:38 2008 New Revision: 59071 URL: http://llvm.org/viewvc/llvm-project?rev=59071&view=rev Log: Remove incomplete lto-bugpoint tool. If there is an interest then we can resurrect this tool later on and finish implementation. Removed: llvm/trunk/tools/lto-bugpoint/ From sabre at nondot.org Tue Nov 11 13:36:32 2008 From: sabre at nondot.org (Chris Lattner) Date: Tue, 11 Nov 2008 19:36:32 -0000 Subject: [llvm-commits] [llvm] r59072 - /llvm/trunk/docs/WritingAnLLVMBackend.html Message-ID: <200811111936.mABJaWCK004430@zion.cs.uiuc.edu> Author: lattner Date: Tue Nov 11 13:36:31 2008 New Revision: 59072 URL: http://llvm.org/viewvc/llvm-project?rev=59072&view=rev Log: last validation errors Modified: llvm/trunk/docs/WritingAnLLVMBackend.html Modified: llvm/trunk/docs/WritingAnLLVMBackend.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/WritingAnLLVMBackend.html?rev=59072&r1=59071&r2=59072&view=diff ============================================================================== --- llvm/trunk/docs/WritingAnLLVMBackend.html (original) +++ llvm/trunk/docs/WritingAnLLVMBackend.html Tue Nov 11 13:36:31 2008 @@ -742,8 +742,8 @@

- Implement a subclass of - TargetRegisterInfo + Implement a subclass of + TargetRegisterInfo

The final step is to hand code portions of XXXRegisterInfo, which @@ -998,8 +998,8 @@
- Implement a subclass of - TargetInstrInfo + Implement a subclass of + TargetInstrInfo

@@ -1339,7 +1339,7 @@
You should examine the node types in the ISD namespace (include/llvm/CodeGen/SelectionDAGNodes.h) and determine which operations the target natively supports. For operations -that do not have native support, add a callback to the constructor for +that do not have native support, add a callback to the constructor for the XXXTargetLowering class, so the instruction selection process knows what to do. The TargetLowering class callback methods (declared in llvm/Target/TargetLowering.h) are:
@@ -1465,7 +1465,7 @@

The Legal LegalizeAction enum value simply indicates that an -operation is natively supported. Legal represents the default condition, +operation is natively supported. Legal represents the default condition, so it is rarely used. In SparcISelLowering.cpp, the action for CTPOP (an operation to count the bits set in an integer) is natively supported only for SPARC v9. The following code enables the Expand conversion technique for non-v9 @@ -2067,7 +2067,7 @@ + src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!"> Mason Woo and Misha Brukman
The LLVM Compiler Infrastructure From evan.cheng at apple.com Tue Nov 11 13:40:26 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 11 Nov 2008 19:40:26 -0000 Subject: [llvm-commits] [llvm] r59074 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMInstrFormats.td ARMInstrInfo.h ARMInstrVFP.td Message-ID: <200811111940.mABJeQL5004633@zion.cs.uiuc.edu> Author: evancheng Date: Tue Nov 11 13:40:26 2008 New Revision: 59074 URL: http://llvm.org/viewvc/llvm-project?rev=59074&view=rev Log: Encode VFP conversion instructions. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.h llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=59074&r1=59073&r2=59074&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Nov 11 13:40:26 2008 @@ -122,6 +122,8 @@ void emitVFPArithInstruction(const MachineInstr &MI); + void emitVFPConversionInstruction(const MachineInstr &MI); + /// getBinaryCodeForInstr - This function, generated by the /// CodeEmitterGenerator using TableGen, produces the binary encoding for /// machine instructions. @@ -320,6 +322,10 @@ case ARMII::VFPBinaryFrm: emitVFPArithInstruction(MI); break; + case ARMII::VFPConv1Frm: + case ARMII::VFPConv2Frm: + emitVFPConversionInstruction(MI); + break; } } @@ -999,7 +1005,7 @@ // Encode Dd / Sd. unsigned RegD = getMachineOpValue(MI, OpIdx++); - Binary |= (RegD & 0x0f) << ARMII::RegFdShift; + Binary |= (RegD & 0x0f) << ARMII::RegRdShift; Binary |= (RegD & 0x10) << ARMII::D_BitShift; // If this is a two-address operand, skip it, e.g. FMACD. @@ -1009,7 +1015,7 @@ // Encode Dn / Sn. if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) { unsigned RegN = getMachineOpValue(MI, OpIdx++); - Binary |= (RegN & 0x0f); + Binary |= (RegN & 0x0f) << ARMII::RegRnShift; Binary |= (RegN & 0x10) << ARMII::N_BitShift; } @@ -1021,4 +1027,41 @@ emitWordLE(Binary); } +void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { + const TargetInstrDesc &TID = MI.getDesc(); + + // Part of binary is determined by TableGn. + unsigned Binary = getBinaryCodeForInstr(MI); + + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << ARMII::CondShift; + + unsigned OpIdx = 0; + + // Encode Dd / Sd. + unsigned RegD = getMachineOpValue(MI, OpIdx++); + Binary |= (RegD & 0x0f) << ARMII::RegRdShift; + Binary |= (RegD & 0x10) << ARMII::D_BitShift; + + // Encode Dn / Sn. + if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPConv1Frm) { + unsigned RegN = getMachineOpValue(MI, OpIdx++); + Binary |= (RegN & 0x0f) << ARMII::RegRnShift; + Binary |= (RegN & 0x10) << ARMII::N_BitShift; + + // FMRS / FMSR do not have Rm. + if (!TID.OpInfo[2].isPredicate()) { + unsigned RegM = getMachineOpValue(MI, OpIdx++); + Binary |= (RegM & 0x0f); + Binary |= (RegM & 0x10) << ARMII::M_BitShift; + } + } else { + unsigned RegM = getMachineOpValue(MI, OpIdx++); + Binary |= (RegM & 0x0f); + Binary |= (RegM & 0x10) << ARMII::M_BitShift; + } + + emitWordLE(Binary); +} + #include "ARMGenCodeEmitter.inc" Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=59074&r1=59073&r2=59074&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Nov 11 13:40:26 2008 @@ -39,7 +39,9 @@ def VFPFrm : Format<15>; def VFPUnaryFrm : Format<16>; def VFPBinaryFrm: Format<17>; -def ThumbFrm : Format<18>; +def VFPConv1Frm : Format<18>; +def VFPConv2Frm : Format<19>; +def ThumbFrm : Format<20>; // Misc flag for data processing instructions that indicates whether // the instruction has a Rn register operand. @@ -798,6 +800,23 @@ let Inst{11-8} = 0b1010; } +class AVConv1I opcod1, bits<4> opcod2, dag oops, dag iops, string opc, + string asm, list pattern> + : AI { + let Inst{27-20} = opcod1; + let Inst{11-8} = opcod2; + let Inst{4} = 1; +} + +class AVConv2I opcod1, bits<4> opcod2, bits<4> opcod3, + dag oops, dag iops, string opc, string asm, list pattern> + : AI { + let Inst{27-20} = opcod1; + let Inst{19-16} = opcod2; + let Inst{11-8} = opcod3; + let Inst{6} = 1; +} + // Special cases. class AXSI pattern> : XI GPR Copies. Int <-> FP Conversions. // -def FMRS : ASI<(outs GPR:$dst), (ins SPR:$src), +def FMRS : AVConv1I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src), "fmrs", " $dst, $src", [(set GPR:$dst, (bitconvert SPR:$src))]>; -def FMSR : ASI<(outs SPR:$dst), (ins GPR:$src), +def FMSR : AVConv1I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src), "fmsr", " $dst, $src", [(set SPR:$dst, (bitconvert GPR:$src))]>; - -def FMRRD : ADI<(outs GPR:$dst1, GPR:$dst2), (ins DPR:$src), +def FMRRD : AVConv1I<0b11000101, 0b1011, + (outs GPR:$dst1, GPR:$dst2), (ins DPR:$src), "fmrrd", " $dst1, $dst2, $src", [/* FIXME: Can't write pattern for multiple result instr*/]>; // FMDHR: GPR -> SPR // FMDLR: GPR -> SPR -def FMDRR : ADI<(outs DPR:$dst), (ins GPR:$src1, GPR:$src2), +def FMDRR : AVConv1I<0b11000100, 0b1011, (outs DPR:$dst), (ins GPR:$src1, GPR:$src2), "fmdrr", " $dst, $src1, $src2", [(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>; @@ -238,48 +238,65 @@ // FMSRR: GPR -> SPR -let Defs = [CPSR] in -def FMSTAT : ASI<(outs), (ins), "fmstat", "", [(arm_fmstat)]>; - // FMXR: GPR -> VFP Sstem reg // Int to FP: -def FSITOD : ADI<(outs DPR:$dst), (ins SPR:$a), +def FSITOD : AVConv2I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a), "fsitod", " $dst, $a", - [(set DPR:$dst, (arm_sitof SPR:$a))]>; + [(set DPR:$dst, (arm_sitof SPR:$a))]> { + let Inst{7} = 1; // Z bit +} -def FSITOS : ASI<(outs SPR:$dst), (ins SPR:$a), +def FSITOS : AVConv2I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a), "fsitos", " $dst, $a", - [(set SPR:$dst, (arm_sitof SPR:$a))]>; + [(set SPR:$dst, (arm_sitof SPR:$a))]> { + let Inst{7} = 1; // Z bit +} -def FUITOD : ADI<(outs DPR:$dst), (ins SPR:$a), +def FUITOD : AVConv2I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a), "fuitod", " $dst, $a", - [(set DPR:$dst, (arm_uitof SPR:$a))]>; + [(set DPR:$dst, (arm_uitof SPR:$a))]> { + let Inst{7} = 0; // Z bit +} -def FUITOS : ASI<(outs SPR:$dst), (ins SPR:$a), +def FUITOS : AVConv2I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a), "fuitos", " $dst, $a", - [(set SPR:$dst, (arm_uitof SPR:$a))]>; + [(set SPR:$dst, (arm_uitof SPR:$a))]> { + let Inst{7} = 1; // Z bit +} // FP to Int: // Always set Z bit in the instruction, i.e. "round towards zero" variants. -def FTOSIZD : ADI<(outs SPR:$dst), (ins DPR:$a), +def FTOSIZD : AVConv2I<0b11101011, 0b1101, 0b1011, + (outs SPR:$dst), (ins DPR:$a), "ftosizd", " $dst, $a", - [(set SPR:$dst, (arm_ftosi DPR:$a))]>; + [(set SPR:$dst, (arm_ftosi DPR:$a))]> { + let Inst{7} = 1; // Z bit +} -def FTOSIZS : ASI<(outs SPR:$dst), (ins SPR:$a), +def FTOSIZS : AVConv2I<0b11101011, 0b1101, 0b1010, + (outs SPR:$dst), (ins SPR:$a), "ftosizs", " $dst, $a", - [(set SPR:$dst, (arm_ftosi SPR:$a))]>; + [(set SPR:$dst, (arm_ftosi SPR:$a))]> { + let Inst{7} = 1; // Z bit +} -def FTOUIZD : ADI<(outs SPR:$dst), (ins DPR:$a), +def FTOUIZD : AVConv2I<0b11101011, 0b1100, 0b1011, + (outs SPR:$dst), (ins DPR:$a), "ftouizd", " $dst, $a", - [(set SPR:$dst, (arm_ftoui DPR:$a))]>; + [(set SPR:$dst, (arm_ftoui DPR:$a))]> { + let Inst{7} = 1; // Z bit +} -def FTOUIZS : ASI<(outs SPR:$dst), (ins SPR:$a), +def FTOUIZS : AVConv2I<0b11101011, 0b1100, 0b1010, + (outs SPR:$dst), (ins SPR:$a), "ftouizs", " $dst, $a", - [(set SPR:$dst, (arm_ftoui SPR:$a))]>; + [(set SPR:$dst, (arm_ftoui SPR:$a))]> { + let Inst{7} = 1; // Z bit +} //===----------------------------------------------------------------------===// // FP FMA Operations. @@ -337,22 +354,34 @@ // FP Conditional moves. // -def FCPYDcc : ADI<(outs DPR:$dst), (ins DPR:$false, DPR:$true), +def FCPYDcc : ADuI<0b11101011, 0b0000, 0b0100, + (outs DPR:$dst), (ins DPR:$false, DPR:$true), "fcpyd", " $dst, $true", [/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>, RegConstraint<"$false = $dst">; -def FCPYScc : ASI<(outs SPR:$dst), (ins SPR:$false, SPR:$true), +def FCPYScc : ASuI<0b11101011, 0b0000, 0b0100, + (outs SPR:$dst), (ins SPR:$false, SPR:$true), "fcpys", " $dst, $true", [/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>, RegConstraint<"$false = $dst">; -def FNEGDcc : ADI<(outs DPR:$dst), (ins DPR:$false, DPR:$true), +def FNEGDcc : ADuI<0b11101011, 0b0001, 0b0100, + (outs DPR:$dst), (ins DPR:$false, DPR:$true), "fnegd", " $dst, $true", [/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>, RegConstraint<"$false = $dst">; -def FNEGScc : ASI<(outs SPR:$dst), (ins SPR:$false, SPR:$true), +def FNEGScc : ASuI<0b11101011, 0b0001, 0b0100, + (outs SPR:$dst), (ins SPR:$false, SPR:$true), "fnegs", " $dst, $true", [/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>, RegConstraint<"$false = $dst">; + + +//===----------------------------------------------------------------------===// +// Misc. +// + +let Defs = [CPSR] in +def FMSTAT : ASI<(outs), (ins), "fmstat", "", [(arm_fmstat)]>; From ofv at wanadoo.es Tue Nov 11 13:51:36 2008 From: ofv at wanadoo.es (Oscar Fuentes) Date: Tue, 11 Nov 2008 19:51:36 -0000 Subject: [llvm-commits] [llvm] r59077 - /llvm/trunk/lib/Transforms/Utils/CMakeLists.txt Message-ID: <200811111951.mABJpabQ004989@zion.cs.uiuc.edu> Author: ofv Date: Tue Nov 11 13:51:36 2008 New Revision: 59077 URL: http://llvm.org/viewvc/llvm-project?rev=59077&view=rev Log: CMake: Updated list of source files for lib/Transforms/Utils. Modified: llvm/trunk/lib/Transforms/Utils/CMakeLists.txt Modified: llvm/trunk/lib/Transforms/Utils/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CMakeLists.txt?rev=59077&r1=59076&r2=59077&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/CMakeLists.txt (original) +++ llvm/trunk/lib/Transforms/Utils/CMakeLists.txt Tue Nov 11 13:51:36 2008 @@ -7,6 +7,7 @@ CloneModule.cpp CloneTrace.cpp CodeExtractor.cpp + DbgInfoRemover.cpp DbgInfoUtils.cpp DemoteRegToStack.cpp InlineCost.cpp From ofv at wanadoo.es Tue Nov 11 14:04:41 2008 From: ofv at wanadoo.es (Oscar Fuentes) Date: Tue, 11 Nov 2008 20:04:41 -0000 Subject: [llvm-commits] [llvm] r59079 - /llvm/trunk/cmake/modules/LLVMConfig.cmake Message-ID: <200811112004.mABK4fh3005497@zion.cs.uiuc.edu> Author: ofv Date: Tue Nov 11 14:04:40 2008 New Revision: 59079 URL: http://llvm.org/viewvc/llvm-project?rev=59079&view=rev Log: CMake: Updated library dependency info used for MSVC++. Modified: llvm/trunk/cmake/modules/LLVMConfig.cmake Modified: llvm/trunk/cmake/modules/LLVMConfig.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMConfig.cmake?rev=59079&r1=59078&r2=59079&view=diff ============================================================================== --- llvm/trunk/cmake/modules/LLVMConfig.cmake (original) +++ llvm/trunk/cmake/modules/LLVMConfig.cmake Tue Nov 11 14:04:40 2008 @@ -132,10 +132,11 @@ set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMARMCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMCodeGen LLVMCore LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMAlpha LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMSelectionDAG LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMAlphaAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMAlphaCodeGen LLVMAlphaAsmPrinter LLVMCodeGen LLVMCore LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMCBackend LLVMAnalysis LLVMCodeGen LLVMCore LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils LLVMipa) -set(MSVC_LIB_DEPS_LLVMCBase LLVMSupport) -set(MSVC_LIB_DEPS_LLVMCellSPU LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMSelectionDAG LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMCellSPUAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMCellSPUCodeGen LLVMCellSPUAsmPrinter LLVMCodeGen LLVMCore LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMCppBackend LLVMCore LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMExecutionEngine LLVMCodeGen LLVMCore LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMJIT LLVMCodeGen LLVMCore LLVMSupport LLVMSystem LLVMTarget) @@ -146,9 +147,11 @@ set(MSVC_LIB_DEPS_LLVMPIC16 LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMPowerPCAsmPrinter LLVMPowerPCCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMPowerPCCodeGen LLVMCodeGen LLVMCore LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMSparc LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMSelectionDAG LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMSparcAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMSparcCodeGen LLVMSparcAsmPrinter LLVMCodeGen LLVMCore LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMX86AsmPrinter LLVMX86CodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMCodeGen LLVMCore LLVMSelectionDAG LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMXCore LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMArchive LLVMBitReader LLVMCore LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMAsmParser LLVMCore LLVMSupport) @@ -158,6 +161,7 @@ set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMScalarOpts LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils) set(MSVC_LIB_DEPS_LLVMCore LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMDebugger LLVMAnalysis LLVMBitReader LLVMCore LLVMSupport LLVMSystem) +set(MSVC_LIB_DEPS_LLVMHello LLVMCore LLVMSupport) set(MSVC_LIB_DEPS_LLVMInstrumentation LLVMCore LLVMScalarOpts LLVMSupport LLVMTransformUtils) set(MSVC_LIB_DEPS_LLVMLinker LLVMArchive LLVMBitReader LLVMCore LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMScalarOpts LLVMAnalysis LLVMCore LLVMSupport LLVMTarget LLVMTransformUtils) From gohman at apple.com Tue Nov 11 15:31:59 2008 From: gohman at apple.com (Dan Gohman) Date: Tue, 11 Nov 2008 21:31:59 -0000 Subject: [llvm-commits] [llvm] r59082 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Message-ID: <200811112132.mABLW0E3009760@zion.cs.uiuc.edu> Author: djg Date: Tue Nov 11 15:31:56 2008 New Revision: 59082 URL: http://llvm.org/viewvc/llvm-project?rev=59082&view=rev Log: Avoid relying on the SelectionDAG for initializing the MachineFunction and TargetLoweringInfo variables for the scheduler. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=59082&r1=59081&r2=59082&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Tue Nov 11 15:31:56 2008 @@ -24,10 +24,10 @@ const TargetMachine &tm) : DAG(dag), BB(bb), TM(tm), MRI(BB->getParent()->getRegInfo()) { TII = TM.getInstrInfo(); - MF = &DAG.getMachineFunction(); + MF = BB->getParent(); TRI = TM.getRegisterInfo(); - TLI = &DAG.getTargetLoweringInfo(); - ConstPool = BB->getParent()->getConstantPool(); + TLI = TM.getTargetLowering(); + ConstPool = MF->getConstantPool(); } /// CheckForPhysRegDependency - Check if the dependency between def and use of From gohman at apple.com Tue Nov 11 15:34:44 2008 From: gohman at apple.com (Dan Gohman) Date: Tue, 11 Nov 2008 21:34:44 -0000 Subject: [llvm-commits] [llvm] r59083 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Message-ID: <200811112134.mABLYiTd009915@zion.cs.uiuc.edu> Author: djg Date: Tue Nov 11 15:34:44 2008 New Revision: 59083 URL: http://llvm.org/viewvc/llvm-project?rev=59083&view=rev Log: In ScheduleDAGRRList::CopyAndMoveSuccessors, create the SUnit for the load before creating the SUnit for the operation that it was unfolded from. This allows each SUnit to have all of its predecessor SUnits available at the time it is created. I don't know yet if this will be absolutely required, but it is a little tidier to do it this way. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=59083&r1=59082&r2=59083&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Nov 11 15:34:44 2008 @@ -666,6 +666,23 @@ DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, OldNumVals-1), SDValue(LoadNode, 1)); + // LoadNode may already exist. This can happen when there is another + // load from the same location and producing the same type of value + // but it has different alignment or volatileness. + bool isNewLoad = true; + SUnit *LoadSU; + if (LoadNode->getNodeId() != -1) { + LoadSU = &SUnits[LoadNode->getNodeId()]; + isNewLoad = false; + } else { + LoadSU = CreateNewSUnit(LoadNode); + LoadNode->setNodeId(LoadSU->NodeNum); + + LoadSU->Depth = SU->Depth; + LoadSU->Height = SU->Height; + ComputeLatency(LoadSU); + } + SUnit *NewSU = CreateNewSUnit(N); assert(N->getNodeId() == -1 && "Node already inserted!"); N->setNodeId(NewSU->NodeNum); @@ -684,23 +701,6 @@ NewSU->Height = SU->Height; ComputeLatency(NewSU); - // LoadNode may already exist. This can happen when there is another - // load from the same location and producing the same type of value - // but it has different alignment or volatileness. - bool isNewLoad = true; - SUnit *LoadSU; - if (LoadNode->getNodeId() != -1) { - LoadSU = &SUnits[LoadNode->getNodeId()]; - isNewLoad = false; - } else { - LoadSU = CreateNewSUnit(LoadNode); - LoadNode->setNodeId(LoadSU->NodeNum); - - LoadSU->Depth = SU->Depth; - LoadSU->Height = SU->Height; - ComputeLatency(LoadSU); - } - SUnit *ChainPred = NULL; SmallVector ChainSuccs; SmallVector LoadPreds; From evan.cheng at apple.com Tue Nov 11 15:48:48 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 11 Nov 2008 21:48:48 -0000 Subject: [llvm-commits] [llvm] r59084 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMInstrFormats.td ARMInstrInfo.h ARMInstrVFP.td Message-ID: <200811112148.mABLmn1Y010456@zion.cs.uiuc.edu> Author: evancheng Date: Tue Nov 11 15:48:44 2008 New Revision: 59084 URL: http://llvm.org/viewvc/llvm-project?rev=59084&view=rev Log: Encode VFP load / store instructions. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.h llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=59084&r1=59083&r2=59084&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Nov 11 15:48:44 2008 @@ -124,6 +124,12 @@ void emitVFPConversionInstruction(const MachineInstr &MI); + void emitVFPLoadStoreInstruction(const MachineInstr &MI); + + void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); + + void emitMiscInstruction(const MachineInstr &MI); + /// getBinaryCodeForInstr - This function, generated by the /// CodeEmitterGenerator using TableGen, produces the binary encoding for /// machine instructions. @@ -326,6 +332,15 @@ case ARMII::VFPConv2Frm: emitVFPConversionInstruction(MI); break; + case ARMII::VFPLdStFrm: + emitVFPLoadStoreInstruction(MI); + break; + case ARMII::VFPLdStMulFrm: + emitVFPLoadStoreMultipleInstruction(MI); + break; + case ARMII::VFPMiscFrm: + emitMiscInstruction(MI); + break; } } @@ -759,23 +774,14 @@ emitWordLE(Binary); } -void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { - // Part of binary is determined by TableGn. - unsigned Binary = getBinaryCodeForInstr(MI); - - // Set the conditional execution predicate - Binary |= II->getPredicate(&MI) << ARMII::CondShift; - - // Set first operand - Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift; +static unsigned getAddrModeUPBits(unsigned Mode) { + unsigned Binary = 0; // Set addressing mode by modifying bits U(23) and P(24) // IA - Increment after - bit U = 1 and bit P = 0 // IB - Increment before - bit U = 1 and bit P = 1 // DA - Decrement after - bit U = 0 and bit P = 0 // DB - Decrement before - bit U = 0 and bit P = 1 - const MachineOperand &MO = MI.getOperand(1); - ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm()); switch (Mode) { default: assert(0 && "Unknown addressing sub-mode!"); case ARM_AM::da: break; @@ -784,6 +790,23 @@ case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break; } + return Binary; +} + +void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { + // Part of binary is determined by TableGn. + unsigned Binary = getBinaryCodeForInstr(MI); + + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << ARMII::CondShift; + + // Set base address operand + Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift; + + // Set addressing mode by modifying bits U(23) and P(24) + const MachineOperand &MO = MI.getOperand(1); + Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm())); + // Set bit W(21) if (ARM_AM::getAM4WBFlag(MO.getImm())) Binary |= 0x1 << ARMII::W_BitShift; @@ -791,8 +814,8 @@ // Set registers for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI.getOperand(i); - if (MO.isReg() && MO.isImplicit()) - continue; + if (!MO.isReg() || MO.isImplicit()) + break; unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg()); assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && RegNum < 16); @@ -1064,4 +1087,87 @@ emitWordLE(Binary); } +void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { + // Part of binary is determined by TableGn. + unsigned Binary = getBinaryCodeForInstr(MI); + + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << ARMII::CondShift; + + unsigned OpIdx = 0; + + // Encode Dd / Sd. + unsigned RegD = getMachineOpValue(MI, OpIdx++); + Binary |= (RegD & 0x0f) << ARMII::RegRdShift; + Binary |= (RegD & 0x10) << ARMII::D_BitShift; + + // Encode address base. + const MachineOperand &Base = MI.getOperand(OpIdx++); + Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift; + + // If there is a non-zero immediate offset, encode it. + if (Base.isReg()) { + const MachineOperand &Offset = MI.getOperand(OpIdx); + if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) { + if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add) + Binary |= 1 << ARMII::U_BitShift; + // Immediate offset is multiplied by 4. + Binary |= ImmOffs >> 2; + emitWordLE(Binary); + return; + } + } + + // If immediate offset is omitted, default to +0. + Binary |= 1 << ARMII::U_BitShift; + + emitWordLE(Binary); +} + +void +ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { + // Part of binary is determined by TableGn. + unsigned Binary = getBinaryCodeForInstr(MI); + + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << ARMII::CondShift; + + // Set base address operand + Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift; + + // Set addressing mode by modifying bits U(23) and P(24) + const MachineOperand &MO = MI.getOperand(1); + Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm())); + + // Set bit W(21) + if (ARM_AM::getAM5WBFlag(MO.getImm())) + Binary |= 0x1 << ARMII::W_BitShift; + + // First register is encoded in Dd. + unsigned FirstReg = MI.getOperand(4).getReg(); + Binary |= ARMRegisterInfo::getRegisterNumbering(FirstReg)<< ARMII::RegRdShift; + + // Number of registers are encoded in offset field. + unsigned NumRegs = 1; + for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI.getOperand(i); + if (!MO.isReg() || MO.isImplicit()) + break; + ++NumRegs; + } + Binary |= NumRegs * 2; + + emitWordLE(Binary); +} + +void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) { + // Part of binary is determined by TableGn. + unsigned Binary = getBinaryCodeForInstr(MI); + + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << ARMII::CondShift; + + emitWordLE(Binary); +} + #include "ARMGenCodeEmitter.inc" Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=59084&r1=59083&r2=59084&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Nov 11 15:48:44 2008 @@ -19,29 +19,33 @@ bits<5> Value = val; } -def Pseudo : Format<1>; -def MulFrm : Format<2>; -def BrFrm : Format<3>; -def BrMiscFrm : Format<4>; - -def DPFrm : Format<5>; -def DPSoRegFrm : Format<6>; - -def LdFrm : Format<7>; -def StFrm : Format<8>; -def LdMiscFrm : Format<9>; -def StMiscFrm : Format<10>; -def LdMulFrm : Format<11>; -def StMulFrm : Format<12>; - -def ArithMiscFrm: Format<13>; -def ExtFrm : Format<14>; -def VFPFrm : Format<15>; -def VFPUnaryFrm : Format<16>; -def VFPBinaryFrm: Format<17>; -def VFPConv1Frm : Format<18>; -def VFPConv2Frm : Format<19>; -def ThumbFrm : Format<20>; +def Pseudo : Format<1>; +def MulFrm : Format<2>; +def BrFrm : Format<3>; +def BrMiscFrm : Format<4>; + +def DPFrm : Format<5>; +def DPSoRegFrm : Format<6>; + +def LdFrm : Format<7>; +def StFrm : Format<8>; +def LdMiscFrm : Format<9>; +def StMiscFrm : Format<10>; +def LdMulFrm : Format<11>; +def StMulFrm : Format<12>; + +def ArithMiscFrm : Format<13>; +def ExtFrm : Format<14>; + +def VFPUnaryFrm : Format<15>; +def VFPBinaryFrm : Format<16>; +def VFPConv1Frm : Format<17>; +def VFPConv2Frm : Format<18>; +def VFPLdStFrm : Format<19>; +def VFPLdStMulFrm : Format<20>; +def VFPMiscFrm : Format<21>; + +def ThumbFrm : Format<22>; // Misc flag for data processing instructions that indicates whether // the instruction has a Rn register operand. @@ -738,30 +742,45 @@ // ARM VFP Instruction templates. // -// ARM Float Instruction -class ASI pattern> - : AI { +// ARM VFP addrmode5 loads and stores +class ADI5 opcod1, bits<2> opcod2, dag oops, dag iops, + string opc, string asm, list pattern> + : I { // TODO: Mark the instructions with the appropriate subtarget info. + let Inst{27-24} = opcod1; + let Inst{21-20} = opcod2; + let Inst{11-8} = 0b1011; } -class ASI5 pattern> +class ASI5 opcod1, bits<2> opcod2, dag oops, dag iops, + string opc, string asm, list pattern> : I { + VFPLdStFrm, opc, asm, "", pattern> { // TODO: Mark the instructions with the appropriate subtarget info. + let Inst{27-24} = opcod1; + let Inst{21-20} = opcod2; + let Inst{11-8} = 0b1010; } -// ARM Double Instruction -class ADI pattern> - : AI { +// Load / store multiple +class AXSI5 pattern> + : XI { // TODO: Mark the instructions with the appropriate subtarget info. + let Inst{27-25} = 0b110; + let Inst{11-8} = 0b1011; } -class ADI5 pattern> - : I { +class AXDI5 pattern> + : XI { // TODO: Mark the instructions with the appropriate subtarget info. + let Inst{27-25} = 0b110; + let Inst{11-8} = 0b1010; } + // Double precision, unary class ADuI opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops, string opc, string asm, list pattern> @@ -817,32 +836,6 @@ let Inst{6} = 1; } -// Special cases. -class AXSI pattern> - : XI { - // TODO: Mark the instructions with the appropriate subtarget info. -} - -class AXSI5 pattern> - : XI { - // TODO: Mark the instructions with the appropriate subtarget info. -} - -class AXDI pattern> - : XI { - // TODO: Mark the instructions with the appropriate subtarget info. -} - -class AXDI5 pattern> - : XI { - // TODO: Mark the instructions with the appropriate subtarget info. -} - - //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=59084&r1=59083&r2=59084&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Tue Nov 11 15:48:44 2008 @@ -69,46 +69,48 @@ //===------------------------------------------------------------------===// // Instruction encoding formats. // - FormShift = 10, - FormMask = 0x1f << FormShift, + FormShift = 10, + FormMask = 0x1f << FormShift, // Pseudo instructions - Pseudo = 1 << FormShift, + Pseudo = 1 << FormShift, // Multiply instructions - MulFrm = 2 << FormShift, + MulFrm = 2 << FormShift, // Branch instructions - BrFrm = 3 << FormShift, - BrMiscFrm = 4 << FormShift, + BrFrm = 3 << FormShift, + BrMiscFrm = 4 << FormShift, // Data Processing instructions - DPFrm = 5 << FormShift, - DPSoRegFrm = 6 << FormShift, + DPFrm = 5 << FormShift, + DPSoRegFrm = 6 << FormShift, // Load and Store - LdFrm = 7 << FormShift, - StFrm = 8 << FormShift, - LdMiscFrm = 9 << FormShift, - StMiscFrm = 10 << FormShift, - LdMulFrm = 11 << FormShift, - StMulFrm = 12 << FormShift, + LdFrm = 7 << FormShift, + StFrm = 8 << FormShift, + LdMiscFrm = 9 << FormShift, + StMiscFrm = 10 << FormShift, + LdMulFrm = 11 << FormShift, + StMulFrm = 12 << FormShift, // Miscellaneous arithmetic instructions - ArithMiscFrm= 13 << FormShift, + ArithMiscFrm = 13 << FormShift, // Extend instructions - ExtFrm = 14 << FormShift, + ExtFrm = 14 << FormShift, // VFP formats - VPFFrm = 15 << FormShift, - VFPUnaryFrm = 16 << FormShift, - VFPBinaryFrm = 17 << FormShift, - VFPConv1Frm = 18 << FormShift, - VFPConv2Frm = 19 << FormShift, + VFPUnaryFrm = 15 << FormShift, + VFPBinaryFrm = 16 << FormShift, + VFPConv1Frm = 17 << FormShift, + VFPConv2Frm = 18 << FormShift, + VFPLdStFrm = 19 << FormShift, + VFPLdStMulFrm = 20 << FormShift, + VFPMiscFrm = 21 << FormShift, // Thumb format - ThumbFrm = 20 << FormShift, + ThumbFrm = 22 << FormShift, //===------------------------------------------------------------------===// // Field shifts - such shifts are used to set field while generating Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=59084&r1=59083&r2=59084&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Nov 11 15:48:44 2008 @@ -35,20 +35,20 @@ // let isSimpleLoad = 1 in { -def FLDD : ADI5<(outs DPR:$dst), (ins addrmode5:$addr), +def FLDD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr), "fldd", " $dst, $addr", [(set DPR:$dst, (load addrmode5:$addr))]>; -def FLDS : ASI5<(outs SPR:$dst), (ins addrmode5:$addr), +def FLDS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr), "flds", " $dst, $addr", [(set SPR:$dst, (load addrmode5:$addr))]>; } // isSimpleLoad -def FSTD : ADI5<(outs), (ins DPR:$src, addrmode5:$addr), +def FSTD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr), "fstd", " $src, $addr", [(store DPR:$src, addrmode5:$addr)]>; -def FSTS : ASI5<(outs), (ins SPR:$src, addrmode5:$addr), +def FSTS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr), "fsts", " $src, $addr", [(store SPR:$src, addrmode5:$addr)]>; @@ -60,24 +60,32 @@ def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1, variable_ops), "fldm${addr:submode}d${p} ${addr:base}, $dst1", - []>; + []> { + let Inst{20} = 1; +} def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1, variable_ops), "fldm${addr:submode}s${p} ${addr:base}, $dst1", - []>; + []> { + let Inst{20} = 1; +} } let mayStore = 1 in { def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1, variable_ops), "fstm${addr:submode}d${p} ${addr:base}, $src1", - []>; + []> { + let Inst{20} = 0; +} def FSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1, variable_ops), "fstm${addr:submode}s${p} ${addr:base}, $src1", - []>; + []> { + let Inst{20} = 0; +} } // mayStore // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores @@ -384,4 +392,11 @@ // let Defs = [CPSR] in -def FMSTAT : ASI<(outs), (ins), "fmstat", "", [(arm_fmstat)]>; +def FMSTAT : AI<(outs), (ins), VFPMiscFrm, "fmstat", "", [(arm_fmstat)]> { + let Inst{27-20} = 0b11101111; + let Inst{19-16} = 0b0001; + let Inst{15-12} = 0b1111; + let Inst{11-8} = 0b1010; + let Inst{7} = 0; + let Inst{4} = 1; +} From dpatel at apple.com Tue Nov 11 16:04:36 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 11 Nov 2008 14:04:36 -0800 Subject: [llvm-commits] [llvm] r59068 - in /llvm/trunk: include/llvm/LinkAllPasses.h include/llvm/Transforms/IPO.h lib/Transforms/Utils/DbgInfoRemover.cpp In-Reply-To: <200811111933.mABJXdfA004224@zion.cs.uiuc.edu> References: <200811111933.mABJXdfA004224@zion.cs.uiuc.edu> Message-ID: <3AF8A513-2268-4FA6-9E40-D9FD6CBF371D@apple.com> On Nov 11, 2008, at 11:33 AM, Devang Patel wrote: > Author: dpatel > Date: Tue Nov 11 13:33:39 2008 > New Revision: 59068 > > URL: http://llvm.org/viewvc/llvm-project?rev=59068&view=rev > Log: > Add utility pass to remove dbg info. This is redundant. StrpSymbols.cpp is available. I'll remove this shortly! - Devang From resistor at mac.com Tue Nov 11 16:11:27 2008 From: resistor at mac.com (Owen Anderson) Date: Tue, 11 Nov 2008 22:11:27 -0000 Subject: [llvm-commits] [llvm] r59086 - /llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Message-ID: <200811112211.mABMBR2I011476@zion.cs.uiuc.edu> Author: resistor Date: Tue Nov 11 16:11:27 2008 New Revision: 59086 URL: http://llvm.org/viewvc/llvm-project?rev=59086&view=rev Log: Don't walk into predecessors in which the vreg is not live when doing shrinkwrapping. This lets several failing tests get farther along, but doesn't completely fix any of them. Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=59086&r1=59085&r2=59086&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original) +++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Tue Nov 11 16:11:27 2008 @@ -618,6 +618,8 @@ // Pred is the def bb and the def reaches other val#s, we must // allow the value to be live out of the bb. continue; + if (!CurrLI->liveAt(LIs->getMBBEndIdx(Pred)-1)) + return; ShrinkWrapLiveInterval(ValNo, Pred, MBB, DefMBB, Visited, Uses, UseMIs, UseMBBs); } From evan.cheng at apple.com Tue Nov 11 16:19:31 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 11 Nov 2008 22:19:31 -0000 Subject: [llvm-commits] [llvm] r59087 - /llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Message-ID: <200811112219.mABMJVeE011783@zion.cs.uiuc.edu> Author: evancheng Date: Tue Nov 11 16:19:31 2008 New Revision: 59087 URL: http://llvm.org/viewvc/llvm-project?rev=59087&view=rev Log: Handle floating point constpool_entry's. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=59087&r1=59086&r2=59087&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Nov 11 16:19:31 2008 @@ -75,6 +75,8 @@ void emitWordLE(unsigned Binary); + void emitDWordLE(uint64_t Binary); + void emitConstPoolInstruction(const MachineInstr &MI); void emitMOVi2piecesInstruction(const MachineInstr &MI); @@ -281,6 +283,16 @@ MCE.emitWordLE(Binary); } +void ARMCodeEmitter::emitDWordLE(uint64_t Binary) { +#ifndef NDEBUG + DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0') + << (unsigned)Binary << std::dec << "\n"; + DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0') + << (unsigned)(Binary >> 32) << std::dec << "\n"; +#endif + MCE.emitDWordLE(Binary); +} + void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI; @@ -385,12 +397,21 @@ if (GlobalValue *GV = dyn_cast(CV)) { emitGlobalAddress(GV, ARM::reloc_arm_absolute, false); emitWordLE(0); - } else { - assert(CV->getType()->isInteger() && - "Not expecting non-integer constpool entries yet!"); - const ConstantInt *CI = dyn_cast(CV); + } else if (const ConstantInt *CI = dyn_cast(CV)) { uint32_t Val = *(uint32_t*)CI->getValue().getRawData(); emitWordLE(Val); + } else if (const ConstantFP *CFP = dyn_cast(CV)) { + if (CFP->getType() == Type::FloatTy) + emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); + else if (CFP->getType() == Type::DoubleTy) + emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); + else { + assert(0 && "Unable to handle this constantpool entry!"); + abort(); + } + } else { + assert(0 && "Unable to handle this constantpool entry!"); + abort(); } } } From evan.cheng at apple.com Tue Nov 11 16:46:12 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 11 Nov 2008 22:46:12 -0000 Subject: [llvm-commits] [llvm] r59088 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMInstrFormats.td ARMInstrInfo.h ARMInstrVFP.td Message-ID: <200811112246.mABMkCnO013278@zion.cs.uiuc.edu> Author: evancheng Date: Tue Nov 11 16:46:12 2008 New Revision: 59088 URL: http://llvm.org/viewvc/llvm-project?rev=59088&view=rev Log: Fix FMDRR encoding. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.h llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=59088&r1=59087&r2=59088&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Nov 11 16:46:12 2008 @@ -342,6 +342,7 @@ break; case ARMII::VFPConv1Frm: case ARMII::VFPConv2Frm: + case ARMII::VFPConv3Frm: emitVFPConversionInstruction(MI); break; case ARMII::VFPLdStFrm: @@ -1080,27 +1081,41 @@ // Set the conditional execution predicate Binary |= II->getPredicate(&MI) << ARMII::CondShift; - unsigned OpIdx = 0; + // FMDRR encodes registers in reverse order. + unsigned Form = TID.TSFlags & ARMII::FormMask; + unsigned OpIdx = (Form == ARMII::VFPConv2Frm) ? 2 : 0; // Encode Dd / Sd. - unsigned RegD = getMachineOpValue(MI, OpIdx++); + unsigned RegD = getMachineOpValue(MI, OpIdx); Binary |= (RegD & 0x0f) << ARMII::RegRdShift; Binary |= (RegD & 0x10) << ARMII::D_BitShift; + if (Form == ARMII::VFPConv2Frm) + --OpIdx; + else + ++OpIdx; // Encode Dn / Sn. - if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPConv1Frm) { - unsigned RegN = getMachineOpValue(MI, OpIdx++); + if (Form == ARMII::VFPConv1Frm || Form == ARMII::VFPConv2Frm) { + unsigned RegN = getMachineOpValue(MI, OpIdx); Binary |= (RegN & 0x0f) << ARMII::RegRnShift; Binary |= (RegN & 0x10) << ARMII::N_BitShift; + if (Form == ARMII::VFPConv2Frm) + --OpIdx; + else + ++OpIdx; // FMRS / FMSR do not have Rm. - if (!TID.OpInfo[2].isPredicate()) { - unsigned RegM = getMachineOpValue(MI, OpIdx++); + if (TID.getNumOperands() > OpIdx && MI.getOperand(OpIdx).isReg()) { + unsigned RegM = getMachineOpValue(MI, OpIdx); Binary |= (RegM & 0x0f); Binary |= (RegM & 0x10) << ARMII::M_BitShift; + } else if (Form == ARMII::VFPConv2Frm) { + // FMDRR encodes definition register in Dm field. + Binary |= getMachineOpValue(MI, 0); } } else { - unsigned RegM = getMachineOpValue(MI, OpIdx++); + assert(Form == ARMII::VFPConv3Frm && "Unsupported format!"); + unsigned RegM = getMachineOpValue(MI, OpIdx); Binary |= (RegM & 0x0f); Binary |= (RegM & 0x10) << ARMII::M_BitShift; } Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=59088&r1=59087&r2=59088&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Nov 11 16:46:12 2008 @@ -41,11 +41,12 @@ def VFPBinaryFrm : Format<16>; def VFPConv1Frm : Format<17>; def VFPConv2Frm : Format<18>; -def VFPLdStFrm : Format<19>; -def VFPLdStMulFrm : Format<20>; -def VFPMiscFrm : Format<21>; +def VFPConv3Frm : Format<19>; +def VFPLdStFrm : Format<20>; +def VFPLdStMulFrm : Format<21>; +def VFPMiscFrm : Format<22>; -def ThumbFrm : Format<22>; +def ThumbFrm : Format<23>; // Misc flag for data processing instructions that indicates whether // the instruction has a Rn register operand. @@ -827,9 +828,17 @@ let Inst{4} = 1; } -class AVConv2I opcod1, bits<4> opcod2, bits<4> opcod3, +class AVConv2I opcod1, bits<4> opcod2, dag oops, dag iops, string opc, + string asm, list pattern> + : AI { + let Inst{27-20} = opcod1; + let Inst{11-8} = opcod2; + let Inst{4} = 1; +} + +class AVConv3I opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops, string opc, string asm, list pattern> - : AI { + : AI { let Inst{27-20} = opcod1; let Inst{19-16} = opcod2; let Inst{11-8} = opcod3; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=59088&r1=59087&r2=59088&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Tue Nov 11 16:46:12 2008 @@ -105,12 +105,13 @@ VFPBinaryFrm = 16 << FormShift, VFPConv1Frm = 17 << FormShift, VFPConv2Frm = 18 << FormShift, - VFPLdStFrm = 19 << FormShift, - VFPLdStMulFrm = 20 << FormShift, - VFPMiscFrm = 21 << FormShift, + VFPConv3Frm = 19 << FormShift, + VFPLdStFrm = 20 << FormShift, + VFPLdStMulFrm = 21 << FormShift, + VFPMiscFrm = 22 << FormShift, // Thumb format - ThumbFrm = 22 << FormShift, + ThumbFrm = 23 << FormShift, //===------------------------------------------------------------------===// // Field shifts - such shifts are used to set field while generating Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=59088&r1=59087&r2=59088&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Nov 11 16:46:12 2008 @@ -235,7 +235,7 @@ // FMDHR: GPR -> SPR // FMDLR: GPR -> SPR -def FMDRR : AVConv1I<0b11000100, 0b1011, (outs DPR:$dst), (ins GPR:$src1, GPR:$src2), +def FMDRR : AVConv2I<0b11000100, 0b1011, (outs DPR:$dst), (ins GPR:$src1, GPR:$src2), "fmdrr", " $dst, $src1, $src2", [(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>; @@ -251,25 +251,25 @@ // Int to FP: -def FSITOD : AVConv2I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a), +def FSITOD : AVConv3I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a), "fsitod", " $dst, $a", [(set DPR:$dst, (arm_sitof SPR:$a))]> { let Inst{7} = 1; // Z bit } -def FSITOS : AVConv2I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a), +def FSITOS : AVConv3I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a), "fsitos", " $dst, $a", [(set SPR:$dst, (arm_sitof SPR:$a))]> { let Inst{7} = 1; // Z bit } -def FUITOD : AVConv2I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a), +def FUITOD : AVConv3I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a), "fuitod", " $dst, $a", [(set DPR:$dst, (arm_uitof SPR:$a))]> { let Inst{7} = 0; // Z bit } -def FUITOS : AVConv2I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a), +def FUITOS : AVConv3I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a), "fuitos", " $dst, $a", [(set SPR:$dst, (arm_uitof SPR:$a))]> { let Inst{7} = 1; // Z bit @@ -278,28 +278,28 @@ // FP to Int: // Always set Z bit in the instruction, i.e. "round towards zero" variants. -def FTOSIZD : AVConv2I<0b11101011, 0b1101, 0b1011, +def FTOSIZD : AVConv3I<0b11101011, 0b1101, 0b1011, (outs SPR:$dst), (ins DPR:$a), "ftosizd", " $dst, $a", [(set SPR:$dst, (arm_ftosi DPR:$a))]> { let Inst{7} = 1; // Z bit } -def FTOSIZS : AVConv2I<0b11101011, 0b1101, 0b1010, +def FTOSIZS : AVConv3I<0b11101011, 0b1101, 0b1010, (outs SPR:$dst), (ins SPR:$a), "ftosizs", " $dst, $a", [(set SPR:$dst, (arm_ftosi SPR:$a))]> { let Inst{7} = 1; // Z bit } -def FTOUIZD : AVConv2I<0b11101011, 0b1100, 0b1011, +def FTOUIZD : AVConv3I<0b11101011, 0b1100, 0b1011, (outs SPR:$dst), (ins DPR:$a), "ftouizd", " $dst, $a", [(set SPR:$dst, (arm_ftoui DPR:$a))]> { let Inst{7} = 1; // Z bit } -def FTOUIZS : AVConv2I<0b11101011, 0b1100, 0b1010, +def FTOUIZS : AVConv3I<0b11101011, 0b1100, 0b1010, (outs SPR:$dst), (ins SPR:$a), "ftouizs", " $dst, $a", [(set SPR:$dst, (arm_ftoui SPR:$a))]> { From alenhar2 at cs.uiuc.edu Tue Nov 11 17:19:51 2008 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 11 Nov 2008 23:19:51 -0000 Subject: [llvm-commits] [llvm] r59090 - /llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td Message-ID: <200811112319.mABNJpP8014691@zion.cs.uiuc.edu> Author: alenhar2 Date: Tue Nov 11 17:19:51 2008 New Revision: 59090 URL: http://llvm.org/viewvc/llvm-project?rev=59090&view=rev Log: This shouldn't be necessary Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td?rev=59090&r1=59089&r2=59090&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td Tue Nov 11 17:19:51 2008 @@ -93,7 +93,8 @@ }], SExt16>; def zappat : PatFrag<(ops node:$LHS), (and node:$LHS, imm:$L), [{ - ConstantSDNode *RHS = cast(N->getOperand(1)); + ConstantSDNode *RHS = dyn_cast(N->getOperand(1)); + if (!RHS) return 0; uint64_t build = get_zapImm(N->getOperand(0), (uint64_t)RHS->getZExtValue()); return build != 0; }]>; From dpatel at apple.com Tue Nov 11 17:57:34 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 11 Nov 2008 23:57:34 -0000 Subject: [llvm-commits] [llvm] r59092 - in /llvm/trunk: include/llvm/LinkAllPasses.h include/llvm/Transforms/IPO.h lib/Transforms/Utils/DbgInfoRemover.cpp Message-ID: <200811112357.mABNvZ4r016547@zion.cs.uiuc.edu> Author: dpatel Date: Tue Nov 11 17:57:33 2008 New Revision: 59092 URL: http://llvm.org/viewvc/llvm-project?rev=59092&view=rev Log: Undo previous check-in. Modified: llvm/trunk/include/llvm/LinkAllPasses.h llvm/trunk/include/llvm/Transforms/IPO.h llvm/trunk/lib/Transforms/Utils/DbgInfoRemover.cpp Modified: llvm/trunk/include/llvm/LinkAllPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=59092&r1=59091&r2=59092&view=diff ============================================================================== --- llvm/trunk/include/llvm/LinkAllPasses.h (original) +++ llvm/trunk/include/llvm/LinkAllPasses.h Tue Nov 11 17:57:33 2008 @@ -125,7 +125,6 @@ (void) llvm::createMergeFunctionsPass(); (void) llvm::createPrintModulePass(0); (void) llvm::createPrintFunctionPass("", 0); - (void) llvm::createRemoveDbgInfoPass(); (void)new llvm::IntervalPartition(); (void)new llvm::FindUsedTypes(); Modified: llvm/trunk/include/llvm/Transforms/IPO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/IPO.h?rev=59092&r1=59091&r2=59092&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/IPO.h (original) +++ llvm/trunk/include/llvm/Transforms/IPO.h Tue Nov 11 17:57:33 2008 @@ -200,13 +200,6 @@ /// ModulePass *createMergeFunctionsPass(); -//===----------------------------------------------------------------------===// -// -// RemoveDbgInfoPass - This pass removes debug info. intrinsics. -// -ModulePass *createRemoveDbgInfoPass(); - - } // End llvm namespace #endif Modified: llvm/trunk/lib/Transforms/Utils/DbgInfoRemover.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/DbgInfoRemover.cpp?rev=59092&r1=59091&r2=59092&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/DbgInfoRemover.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/DbgInfoRemover.cpp Tue Nov 11 17:57:33 2008 @@ -1,97 +0,0 @@ -//===- DbgInforemover.cpp - Remove Debug Info Intrinsics ------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This is utility pass removes all debug information intrinsics from a -// function. -// -//===----------------------------------------------------------------------===// - -#include "llvm/Transforms/IPO.h" -#include "llvm/Module.h" -#include "llvm/IntrinsicInst.h" -#include "llvm/Pass.h" -#include "llvm/ADT/SmallPtrSet.h" -using namespace llvm; - -namespace { - // Remove dbg intrinsics and related globals from this module. - struct RemoveDbgInfoPass : public ModulePass { - static char ID; // Pass identification, replacement for typeid - RemoveDbgInfoPass() : ModulePass(&ID) {} - - void getAnalysisUsage(AnalysisUsage &Info) const { - Info.setPreservesCFG(); - } - - bool runOnModule(Module &M) { - bool Changed = false; - DbgGlobals.clear(); - - for (Module::iterator I = M.begin(), E = M.end(); I != E; ) { - Function *F = I++; - Changed |= cleanupFunction(*F); - if (F->hasName() && !strncmp(F->getNameStart(), "llvm.dbg", 8)) - M.getFunctionList().erase(F); - } - - for (Module::global_iterator GVI = M.global_begin(), E = M.global_end(); - GVI != E; ) { - GlobalVariable *GV = GVI++; - if (GV->hasName() && !strncmp(GV->getNameStart(), "llvm.dbg", 8)) { - if (GV->hasInitializer()) - CollectDbgGlobals(GV->getInitializer()); - GV->replaceAllUsesWith(UndefValue::get(GV->getType())); - GV->removeDeadConstantUsers(); - M.getGlobalList().erase(GV); - } - } - - for (SmallPtrSet::iterator CI = DbgGlobals.begin(), - CE = DbgGlobals.end(); CI != CE; ) { - GlobalVariable *GV = *CI++; - GV->removeDeadConstantUsers(); - if (GV->use_empty()) - M.getGlobalList().erase(GV); - } - return Changed; - } - - void CollectDbgGlobals(Constant *C) { - if (GlobalVariable *GV = dyn_cast(C)) - DbgGlobals.insert(GV); - for (User::op_iterator I = C->op_begin(), E = C->op_end(); I != E; ++I) - CollectDbgGlobals(cast(*I)); - } - - bool cleanupFunction(Function &F) { - SmallVector WorkList; - for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) - for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) - if (isa(I)) - WorkList.push_back(I); - - for (SmallVector::iterator WI = WorkList.begin(), - WE = WorkList.end(); WI != WE; ++WI) - (*WI)->eraseFromParent(); - - return !WorkList.empty(); - } - - private: - SmallPtrSet DbgGlobals; - }; - - char RemoveDbgInfoPass::ID = 0; - static RegisterPass X("remove-dbginfo", - "Remove Debugging Information"); -} - -ModulePass *llvm::createRemoveDbgInfoPass() { - return new RemoveDbgInfoPass(); -} From dpatel at apple.com Tue Nov 11 17:58:16 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 11 Nov 2008 23:58:16 -0000 Subject: [llvm-commits] [llvm] r59093 - /llvm/trunk/lib/Transforms/Utils/DbgInfoRemover.cpp Message-ID: <200811112358.mABNwGsh016580@zion.cs.uiuc.edu> Author: dpatel Date: Tue Nov 11 17:58:15 2008 New Revision: 59093 URL: http://llvm.org/viewvc/llvm-project?rev=59093&view=rev Log: Remove Removed: llvm/trunk/lib/Transforms/Utils/DbgInfoRemover.cpp Removed: llvm/trunk/lib/Transforms/Utils/DbgInfoRemover.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/DbgInfoRemover.cpp?rev=59092&view=auto ============================================================================== (empty) From foldr at codedgers.com Tue Nov 11 18:04:46 2008 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Wed, 12 Nov 2008 00:04:46 -0000 Subject: [llvm-commits] [llvm] r59096 - in /llvm/trunk: tools/llvmc2/driver/CompilationGraph.cpp utils/TableGen/LLVMCConfigurationEmitter.cpp Message-ID: <200811120004.mAC04k0F016846@zion.cs.uiuc.edu> Author: foldr Date: Tue Nov 11 18:04:46 2008 New Revision: 59096 URL: http://llvm.org/viewvc/llvm-project?rev=59096&view=rev Log: Some cosmetic changes. Modified: llvm/trunk/tools/llvmc2/driver/CompilationGraph.cpp llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Modified: llvm/trunk/tools/llvmc2/driver/CompilationGraph.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc2/driver/CompilationGraph.cpp?rev=59096&r1=59095&r2=59096&view=diff ============================================================================== --- llvm/trunk/tools/llvmc2/driver/CompilationGraph.cpp (original) +++ llvm/trunk/tools/llvmc2/driver/CompilationGraph.cpp Tue Nov 11 18:04:46 2008 @@ -109,12 +109,8 @@ } void CompilationGraph::insertNode(Tool* V) { - if (NodesMap.count(V->Name()) == 0) { - Node N; - N.OwningGraph = this; - N.ToolPtr = V; - NodesMap[V->Name()] = N; - } + if (NodesMap.count(V->Name()) == 0) + NodesMap[V->Name()] = Node(this, V); } void CompilationGraph::insertEdge(const std::string& A, Edge* Edg) { Modified: llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp?rev=59096&r1=59095&r2=59096&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Tue Nov 11 18:04:46 2008 @@ -20,12 +20,14 @@ #include "llvm/ADT/StringMap.h" #include "llvm/ADT/StringSet.h" #include "llvm/Support/Streams.h" + #include #include #include #include #include #include + using namespace llvm; namespace { From foldr at codedgers.com Tue Nov 11 18:05:17 2008 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Wed, 12 Nov 2008 00:05:17 -0000 Subject: [llvm-commits] [llvm] r59097 - /llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Message-ID: <200811120005.mAC05HEd016869@zion.cs.uiuc.edu> Author: foldr Date: Tue Nov 11 18:05:17 2008 New Revision: 59097 URL: http://llvm.org/viewvc/llvm-project?rev=59097&view=rev Log: Add a bit of lazy evaluation to PopulateCompilationGraph(). Only the tools that are mentioned in the compilation graph definition are now inserted by PopulateCompilationGraph(). This should cut down plugin loading time a little. Modified: llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Modified: llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp?rev=59097&r1=59096&r2=59097&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Tue Nov 11 18:05:17 2008 @@ -1595,26 +1595,33 @@ { ListInit* edges = CompilationGraph->getValueAsListInit("edges"); - // Generate code O << "namespace {\n\n"; O << "void PopulateCompilationGraphLocal(CompilationGraph& G) {\n"; - // Insert vertices + // Insert vertices. + // Only tools mentioned in the graph definition are inserted. - RecordVector Tools = Records.getAllDerivedDefinitions("Tool"); - if (Tools.empty()) - throw std::string("No tool definitions found!"); + llvm::StringSet<> ToolsInGraph; + + for (unsigned i = 0; i < edges->size(); ++i) { + Record* Edge = edges->getElementAsRecord(i); + Record* A = Edge->getValueAsDef("a"); + Record* B = Edge->getValueAsDef("b"); - for (RecordVector::iterator B = Tools.begin(), E = Tools.end(); B != E; ++B) { - const std::string& Name = (*B)->getName(); - if (Name != "root") - O << Indent1 << "G.insertNode(new " - << Name << "());\n"; + if (A->getName() != "root") + ToolsInGraph.insert(A->getName()); + if (B->getName() != "root") + ToolsInGraph.insert(B->getName()); } + for (llvm::StringSet<>::iterator B = ToolsInGraph.begin(), + E = ToolsInGraph.end(); B != E; ++B) + O << Indent1 << "G.insertNode(new " << B->first() << "());\n"; + O << '\n'; - // Insert edges + // Insert edges. + for (unsigned i = 0; i < edges->size(); ++i) { Record* Edge = edges->getElementAsRecord(i); Record* A = Edge->getValueAsDef("a"); From ofv at wanadoo.es Tue Nov 11 18:14:17 2008 From: ofv at wanadoo.es (Oscar Fuentes) Date: Wed, 12 Nov 2008 00:14:17 -0000 Subject: [llvm-commits] [llvm] r59098 - /llvm/trunk/lib/Transforms/Utils/CMakeLists.txt Message-ID: <200811120014.mAC0EHmO017265@zion.cs.uiuc.edu> Author: ofv Date: Tue Nov 11 18:14:12 2008 New Revision: 59098 URL: http://llvm.org/viewvc/llvm-project?rev=59098&view=rev Log: CMake: Remove removed source file. Modified: llvm/trunk/lib/Transforms/Utils/CMakeLists.txt Modified: llvm/trunk/lib/Transforms/Utils/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CMakeLists.txt?rev=59098&r1=59097&r2=59098&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/CMakeLists.txt (original) +++ llvm/trunk/lib/Transforms/Utils/CMakeLists.txt Tue Nov 11 18:14:12 2008 @@ -7,7 +7,6 @@ CloneModule.cpp CloneTrace.cpp CodeExtractor.cpp - DbgInfoRemover.cpp DbgInfoUtils.cpp DemoteRegToStack.cpp InlineCost.cpp From evan.cheng at apple.com Tue Nov 11 19:02:25 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Nov 2008 01:02:25 -0000 Subject: [llvm-commits] [llvm] r59100 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMJITInfo.cpp ARMRelocations.h Message-ID: <200811120102.mAC12PXU018916@zion.cs.uiuc.edu> Author: evancheng Date: Tue Nov 11 19:02:24 2008 New Revision: 59100 URL: http://llvm.org/viewvc/llvm-project?rev=59100&view=rev Log: VFP fld / fst immediate field is multiplied by 4. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp llvm/trunk/lib/Target/ARM/ARMRelocations.h Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=59100&r1=59099&r2=59100&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Nov 11 19:02:24 2008 @@ -222,9 +222,13 @@ emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true); else if (MO.isSymbol()) emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch); - else if (MO.isCPI()) - emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); - else if (MO.isJTI()) + else if (MO.isCPI()) { + const TargetInstrDesc &TID = MI.getDesc(); + // For VFP load, the immediate offset is multiplied by 4. + unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) + ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry; + emitConstPoolAddress(MO.getIndex(), Reloc); + } else if (MO.isJTI()) emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative); else if (MO.isMBB()) emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); Modified: llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp?rev=59100&r1=59099&r2=59100&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp Tue Nov 11 19:02:24 2008 @@ -13,6 +13,7 @@ #define DEBUG_TYPE "jit" #include "ARMJITInfo.h" +#include "ARMInstrInfo.h" #include "ARMConstantPoolValue.h" #include "ARMRelocations.h" #include "ARMSubtarget.h" @@ -201,16 +202,20 @@ intptr_t ARMJITInfo::resolveRelocDestAddr(MachineRelocation *MR) const { ARM::RelocationType RT = (ARM::RelocationType)MR->getRelocationType(); - if (RT == ARM::reloc_arm_pic_jt) + switch (RT) { + default: + return (intptr_t)(MR->getResultPointer()); + case ARM::reloc_arm_pic_jt: // Destination address - jump table base. return (intptr_t)(MR->getResultPointer()) - MR->getConstantVal(); - else if (RT == ARM::reloc_arm_jt_base) + case ARM::reloc_arm_jt_base: // Jump table base address. return getJumpTableBaseAddr(MR->getJumpTableIndex()); - else if (RT == ARM::reloc_arm_cp_entry) + case ARM::reloc_arm_cp_entry: + case ARM::reloc_arm_vfp_cp_entry: // Constant pool entry address. return getConstantPoolEntryAddr(MR->getConstantPoolIndex()); - else if (RT == ARM::reloc_arm_machine_cp_entry) { + case ARM::reloc_arm_machine_cp_entry: { ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)MR->getConstantVal(); assert((!ACPV->hasModifier() && !ACPV->mustAddCurrentAddress()) && "Can't handle this machine constant pool entry yet!"); @@ -218,7 +223,7 @@ Addr -= getPCLabelAddr(ACPV->getLabelId()) + ACPV->getPCAdjustment(); return Addr; } - return (intptr_t)(MR->getResultPointer()); + } } /// relocate - Before the JIT can run a block of code that has been emitted, @@ -231,30 +236,35 @@ intptr_t ResultPtr = resolveRelocDestAddr(MR); switch ((ARM::RelocationType)MR->getRelocationType()) { case ARM::reloc_arm_cp_entry: + case ARM::reloc_arm_vfp_cp_entry: case ARM::reloc_arm_relative: { // It is necessary to calculate the correct PC relative value. We // subtract the base addr from the target addr to form a byte offset. - ResultPtr = ResultPtr-(intptr_t)RelocPos-8; + ResultPtr = ResultPtr - (intptr_t)RelocPos - 8; // If the result is positive, set bit U(23) to 1. if (ResultPtr >= 0) - *((unsigned*)RelocPos) |= 1 << 23; + *((intptr_t*)RelocPos) |= 1 << ARMII::U_BitShift; else { - // Otherwise, obtain the absolute value and set - // bit U(23) to 0. - ResultPtr *= -1; - *((unsigned*)RelocPos) &= 0xFF7FFFFF; + // Otherwise, obtain the absolute value and set bit U(23) to 0. + assert((*((intptr_t*)RelocPos) & (1 << ARMII::U_BitShift)) == 0 && + "U bit is not zero?"); + ResultPtr = - ResultPtr; } // Set the immed value calculated. - *((unsigned*)RelocPos) |= (unsigned)ResultPtr; + // VFP immediate offset is multiplied by 4. + if (MR->getRelocationType() == ARM::reloc_arm_vfp_cp_entry) + ResultPtr = ResultPtr >> 2; + *((intptr_t*)RelocPos) |= ResultPtr; // Set register Rn to PC. - *((unsigned*)RelocPos) |= 0xF << 16; + *((intptr_t*)RelocPos) |= + ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift; break; } case ARM::reloc_arm_pic_jt: case ARM::reloc_arm_machine_cp_entry: case ARM::reloc_arm_absolute: { // These addresses have already been resolved. - *((unsigned*)RelocPos) |= (unsigned)ResultPtr; + *((intptr_t*)RelocPos) |= (intptr_t)ResultPtr; break; } case ARM::reloc_arm_branch: { @@ -266,13 +276,13 @@ ResultPtr = ResultPtr - (intptr_t)RelocPos - 8; ResultPtr = (ResultPtr & 0x03FFFFFC) >> 2; assert(ResultPtr >= -33554432 && ResultPtr <= 33554428); - *((unsigned*)RelocPos) |= ResultPtr; + *((intptr_t*)RelocPos) |= ResultPtr; break; } case ARM::reloc_arm_jt_base: { // JT base - (instruction addr + 8) ResultPtr = ResultPtr - (intptr_t)RelocPos - 8; - *((unsigned*)RelocPos) |= ResultPtr; + *((intptr_t*)RelocPos) |= ResultPtr; break; } } Modified: llvm/trunk/lib/Target/ARM/ARMRelocations.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRelocations.h?rev=59100&r1=59099&r2=59100&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRelocations.h (original) +++ llvm/trunk/lib/Target/ARM/ARMRelocations.h Tue Nov 11 19:02:24 2008 @@ -31,6 +31,10 @@ // addresses are kept locally in a map. reloc_arm_cp_entry, + // reloc_arm_vfp_cp_entry - Same as reloc_arm_cp_entry except the offset + // should be divided by 4. + reloc_arm_vfp_cp_entry, + // reloc_arm_machine_cp_entry - Relocation of a ARM machine constantpool // entry. reloc_arm_machine_cp_entry, From dalej at apple.com Tue Nov 11 20:00:35 2008 From: dalej at apple.com (Dale Johannesen) Date: Wed, 12 Nov 2008 02:00:35 -0000 Subject: [llvm-commits] [llvm] r59101 - in /llvm/trunk: lib/CodeGen/SelectionDAG/TargetLowering.cpp test/CodeGen/X86/2008-11-06-testb.ll Message-ID: <200811120200.mAC20Z8b021316@zion.cs.uiuc.edu> Author: johannes Date: Tue Nov 11 20:00:35 2008 New Revision: 59101 URL: http://llvm.org/viewvc/llvm-project?rev=59101&view=rev Log: Fix the testb optimization so x86 also bootstraps. Reenable test. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/trunk/test/CodeGen/X86/2008-11-06-testb.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=59101&r1=59100&r2=59101&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Nov 11 20:00:35 2008 @@ -1353,7 +1353,6 @@ } } -#if 0 // If the LHS is '(and load, const)', the RHS is 0, // the test is for equality or unsigned, and all 1 bits of the const are // in the same partial word, see if we can shorten the load. @@ -1380,7 +1379,7 @@ bestOffset = (origWidth/width - offset - 1) * (width/8); else bestOffset = (uint64_t)offset * (width/8); - bestMask = Mask >> (offset * 8); + bestMask = Mask >> (offset * (width/8) * 8); bestWidth = width; break; } @@ -1407,7 +1406,6 @@ } } } -#endif // If the LHS is a ZERO_EXTEND, perform the comparison on the input. if (N0.getOpcode() == ISD::ZERO_EXTEND) { Modified: llvm/trunk/test/CodeGen/X86/2008-11-06-testb.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-11-06-testb.ll?rev=59101&r1=59100&r2=59101&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-11-06-testb.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-11-06-testb.ll Tue Nov 11 20:00:35 2008 @@ -1,5 +1,4 @@ ; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | grep testb -; XFAIL: * ; ModuleID = '' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" From evan.cheng at apple.com Tue Nov 11 20:19:38 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Nov 2008 02:19:38 -0000 Subject: [llvm-commits] [llvm] r59102 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMInstrVFP.td ARMRegisterInfo.cpp ARMRegisterInfo.h Message-ID: <200811120219.mAC2JcBc022024@zion.cs.uiuc.edu> Author: evancheng Date: Tue Nov 11 20:19:38 2008 New Revision: 59102 URL: http://llvm.org/viewvc/llvm-project?rev=59102&view=rev Log: Fix encoding of single-precision VFP registers. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrVFP.td llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=59102&r1=59101&r2=59102&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Nov 11 20:19:38 2008 @@ -1053,9 +1053,16 @@ (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!"); // Encode Dd / Sd. - unsigned RegD = getMachineOpValue(MI, OpIdx++); - Binary |= (RegD & 0x0f) << ARMII::RegRdShift; - Binary |= (RegD & 0x10) << ARMII::D_BitShift; + unsigned RegD = MI.getOperand(OpIdx++).getReg(); + bool isSPVFP = false; + RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP); + if (!isSPVFP) + Binary |= RegD << ARMII::RegRdShift; + else { + Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; + Binary |= (RegD & 0x01) << ARMII::D_BitShift; + } + // If this is a two-address operand, skip it, e.g. FMACD. if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) @@ -1063,15 +1070,27 @@ // Encode Dn / Sn. if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) { - unsigned RegN = getMachineOpValue(MI, OpIdx++); - Binary |= (RegN & 0x0f) << ARMII::RegRnShift; - Binary |= (RegN & 0x10) << ARMII::N_BitShift; + unsigned RegN = MI.getOperand(OpIdx++).getReg(); + isSPVFP = false; + RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP); + if (!isSPVFP) + Binary |= RegN << ARMII::RegRnShift; + else { + Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; + Binary |= (RegN & 0x01) << ARMII::N_BitShift; + } } // Encode Dm / Sm. - unsigned RegM = getMachineOpValue(MI, OpIdx++); - Binary |= (RegM & 0x0f); - Binary |= (RegM & 0x10) << ARMII::M_BitShift; + unsigned RegM = MI.getOperand(OpIdx++).getReg(); + isSPVFP = false; + RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP); + if (!isSPVFP) + Binary |= RegM; + else { + Binary |= ((RegM & 0x1E) >> 1); + Binary |= (RegM & 0x01) << ARMII::M_BitShift; + } emitWordLE(Binary); } @@ -1087,41 +1106,65 @@ // FMDRR encodes registers in reverse order. unsigned Form = TID.TSFlags & ARMII::FormMask; - unsigned OpIdx = (Form == ARMII::VFPConv2Frm) ? 2 : 0; + unsigned OpIdx = (Form == ARMII::VFPConv2Frm) + ? MI.findFirstPredOperandIdx()-1 : 0; // Encode Dd / Sd. - unsigned RegD = getMachineOpValue(MI, OpIdx); - Binary |= (RegD & 0x0f) << ARMII::RegRdShift; - Binary |= (RegD & 0x10) << ARMII::D_BitShift; + unsigned RegD = MI.getOperand(OpIdx).getReg(); + bool isSPVFP = false; + RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP); + if (!isSPVFP) + Binary |= RegD << ARMII::RegRdShift; + else { + Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; + Binary |= (RegD & 0x01) << ARMII::D_BitShift; + } if (Form == ARMII::VFPConv2Frm) --OpIdx; else ++OpIdx; + if (Form == ARMII::VFPConv3Frm) { + unsigned RegM = MI.getOperand(OpIdx).getReg(); + isSPVFP = false; + RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP); + if (!isSPVFP) + Binary |= RegM; + else { + Binary |= ((RegM & 0x1E) >> 1); + Binary |= (RegM & 0x01) << ARMII::M_BitShift; + } + + emitWordLE(Binary); + return; + } + // Encode Dn / Sn. - if (Form == ARMII::VFPConv1Frm || Form == ARMII::VFPConv2Frm) { - unsigned RegN = getMachineOpValue(MI, OpIdx); - Binary |= (RegN & 0x0f) << ARMII::RegRnShift; - Binary |= (RegN & 0x10) << ARMII::N_BitShift; - if (Form == ARMII::VFPConv2Frm) - --OpIdx; - else - ++OpIdx; - - // FMRS / FMSR do not have Rm. - if (TID.getNumOperands() > OpIdx && MI.getOperand(OpIdx).isReg()) { - unsigned RegM = getMachineOpValue(MI, OpIdx); - Binary |= (RegM & 0x0f); - Binary |= (RegM & 0x10) << ARMII::M_BitShift; - } else if (Form == ARMII::VFPConv2Frm) { - // FMDRR encodes definition register in Dm field. - Binary |= getMachineOpValue(MI, 0); + unsigned RegN = MI.getOperand(OpIdx).getReg(); + isSPVFP = false; + RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP); + if (!isSPVFP) + Binary |= RegN << ARMII::RegRnShift; + else { + Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; + Binary |= (RegN & 0x01) << ARMII::N_BitShift; + } + if (Form == ARMII::VFPConv2Frm) + --OpIdx; + else + ++OpIdx; + + // FMRS / FMSR do not have Rm. + if (TID.getNumOperands() > OpIdx && MI.getOperand(OpIdx).isReg()) { + unsigned RegM = MI.getOperand(OpIdx).getReg(); + isSPVFP = false; + RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP); + if (!isSPVFP) + Binary |= RegM; + else { + Binary |= ((RegM & 0x1E) >> 1); + Binary |= (RegM & 0x01) << ARMII::M_BitShift; } - } else { - assert(Form == ARMII::VFPConv3Frm && "Unsupported format!"); - unsigned RegM = getMachineOpValue(MI, OpIdx); - Binary |= (RegM & 0x0f); - Binary |= (RegM & 0x10) << ARMII::M_BitShift; } emitWordLE(Binary); @@ -1137,9 +1180,15 @@ unsigned OpIdx = 0; // Encode Dd / Sd. - unsigned RegD = getMachineOpValue(MI, OpIdx++); - Binary |= (RegD & 0x0f) << ARMII::RegRdShift; - Binary |= (RegD & 0x10) << ARMII::D_BitShift; + unsigned RegD = MI.getOperand(OpIdx++).getReg(); + bool isSPVFP = false; + RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP); + if (!isSPVFP) + Binary |= RegD << ARMII::RegRdShift; + else { + Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; + Binary |= (RegD & 0x01) << ARMII::D_BitShift; + } // Encode address base. const MachineOperand &Base = MI.getOperand(OpIdx++); @@ -1184,8 +1233,15 @@ Binary |= 0x1 << ARMII::W_BitShift; // First register is encoded in Dd. - unsigned FirstReg = MI.getOperand(4).getReg(); - Binary |= ARMRegisterInfo::getRegisterNumbering(FirstReg)<< ARMII::RegRdShift; + unsigned RegD = MI.getOperand(4).getReg(); + bool isSPVFP = false; + RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP); + if (!isSPVFP) + Binary |= RegD << ARMII::RegRdShift; + else { + Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; + Binary |= (RegD & 0x01) << ARMII::D_BitShift; + } // Number of registers are encoded in offset field. unsigned NumRegs = 1; Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=59102&r1=59101&r2=59102&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Nov 11 20:19:38 2008 @@ -223,7 +223,7 @@ "fmrs", " $dst, $src", [(set GPR:$dst, (bitconvert SPR:$src))]>; -def FMSR : AVConv1I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src), +def FMSR : AVConv2I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src), "fmsr", " $dst, $src", [(set SPR:$dst, (bitconvert GPR:$src))]>; Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp?rev=59102&r1=59101&r2=59102&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Tue Nov 11 20:19:38 2008 @@ -81,6 +81,80 @@ } } +unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum, + bool &isSPVFP) { + isSPVFP = false; + + using namespace ARM; + switch (RegEnum) { + default: + assert(0 && "Unknown ARM register!"); + abort(); + case R0: case D0: return 0; + case R1: case D1: return 1; + case R2: case D2: return 2; + case R3: case D3: return 3; + case R4: case D4: return 4; + case R5: case D5: return 5; + case R6: case D6: return 6; + case R7: case D7: return 7; + case R8: case D8: return 8; + case R9: case D9: return 9; + case R10: case D10: return 10; + case R11: case D11: return 11; + case R12: case D12: return 12; + case SP: case D13: return 13; + case LR: case D14: return 14; + case PC: case D15: return 15; + + case S0: case S1: case S2: case S3: + case S4: case S5: case S6: case S7: + case S8: case S9: case S10: case S11: + case S12: case S13: case S14: case S15: + case S16: case S17: case S18: case S19: + case S20: case S21: case S22: case S23: + case S24: case S25: case S26: case S27: + case S28: case S29: case S30: case S31: { + isSPVFP = true; + switch (RegEnum) { + default: return 0; // Avoid compile time warning. + case S0: return 0; + case S1: return 1; + case S2: return 2; + case S3: return 3; + case S4: return 4; + case S5: return 5; + case S6: return 6; + case S7: return 7; + case S8: return 8; + case S9: return 9; + case S10: return 10; + case S11: return 11; + case S12: return 12; + case S13: return 13; + case S14: return 14; + case S15: return 15; + case S16: return 16; + case S17: return 17; + case S18: return 18; + case S19: return 19; + case S20: return 20; + case S21: return 21; + case S22: return 22; + case S23: return 23; + case S24: return 24; + case S25: return 25; + case S26: return 26; + case S27: return 27; + case S28: return 28; + case S29: return 29; + case S30: return 30; + case S31: return 31; + } + } + } +} + ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &sti) : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h?rev=59102&r1=59101&r2=59102&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h Tue Nov 11 20:19:38 2008 @@ -44,6 +44,10 @@ /// ARM::LR, return the number that it corresponds to (e.g. 14). static unsigned getRegisterNumbering(unsigned RegEnum); + /// Same as previous getRegisterNumbering except it returns true in isSPVFP + /// if the register is a single precision VFP register. + static unsigned getRegisterNumbering(unsigned RegEnum, bool &isSPVFP); + /// Code Generation virtual methods... const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const; From wangmp at apple.com Tue Nov 11 22:29:20 2008 From: wangmp at apple.com (Mon Ping Wang) Date: Tue, 11 Nov 2008 20:29:20 -0800 Subject: [llvm-commits] Patch: split vector shuffle in LegalizeType In-Reply-To: <200811072107.14135.duncan.sands@math.u-psud.fr> References: <7C812DE7-E002-4767-A0AE-192738C25237@apple.com> <79D867D7-9AA7-4B9A-AF4C-CD7DC36C1B1C@apple.com> <726CDE41-CC30-4D97-99D5-4F3E8BB08AA9@apple.com> <200811072107.14135.duncan.sands@math.u-psud.fr> Message-ID: <5DABA659-A082-45EF-B08F-6C283D911365@apple.com> Hi Duncan, You are correct that I'm doing the same thing twice but with different indexes. I didn't like DeterVectorShuffleUses because of the number of parameters it took and the interesting side effect it had so I took your advice and inlined it. For now, I left it assuming LoVT and HiVT after the split may be different. Functionality, I left it pretty much alone and left the other helper function alone. If anyone has any comments, please let me know and thanks for the review. -- Mon Ping -------------- next part -------------- A non-text attachment was scrubbed... Name: shuffle3.patch Type: application/octet-stream Size: 10994 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20081111/de343a73/attachment.obj -------------- next part -------------- On Nov 7, 2008, at 12:07 PM, Duncan Sands wrote: > Hi Mon Ping, I can't help feeling that rather than repeating almost > the same code twice, you could use a loop instead. Then you can > "inline" DeterVectorShuffleUse, which as far as I can see can lead > to additional simplifications (it also seems to be written in a kind > of complicated way). In fact, you can determine which lo/hi parts > to use on the fly as you work your way down the mask, building the > new mask vector as you go, rather than prescanning the mask, then > building the new mask vector afterwards. Just some thoughts. > > Ciao, > > Duncan. From evan.cheng at apple.com Wed Nov 12 00:41:42 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Nov 2008 06:41:42 -0000 Subject: [llvm-commits] [llvm] r59104 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMInstrFormats.td ARMInstrInfo.h ARMInstrVFP.td Message-ID: <200811120641.mAC6fhIf031586@zion.cs.uiuc.edu> Author: evancheng Date: Wed Nov 12 00:41:41 2008 New Revision: 59104 URL: http://llvm.org/viewvc/llvm-project?rev=59104&view=rev Log: Fix VFP conversion instruction encodings. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.h llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=59104&r1=59103&r2=59104&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Wed Nov 12 00:41:41 2008 @@ -347,6 +347,8 @@ case ARMII::VFPConv1Frm: case ARMII::VFPConv2Frm: case ARMII::VFPConv3Frm: + case ARMII::VFPConv4Frm: + case ARMII::VFPConv5Frm: emitVFPConversionInstruction(MI); break; case ARMII::VFPLdStFrm: @@ -1095,22 +1097,9 @@ emitWordLE(Binary); } -void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { - const TargetInstrDesc &TID = MI.getDesc(); - - // Part of binary is determined by TableGn. - unsigned Binary = getBinaryCodeForInstr(MI); - - // Set the conditional execution predicate - Binary |= II->getPredicate(&MI) << ARMII::CondShift; - - // FMDRR encodes registers in reverse order. - unsigned Form = TID.TSFlags & ARMII::FormMask; - unsigned OpIdx = (Form == ARMII::VFPConv2Frm) - ? MI.findFirstPredOperandIdx()-1 : 0; - - // Encode Dd / Sd. +static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { unsigned RegD = MI.getOperand(OpIdx).getReg(); + unsigned Binary = 0; bool isSPVFP = false; RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP); if (!isSPVFP) @@ -1119,29 +1108,13 @@ Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; Binary |= (RegD & 0x01) << ARMII::D_BitShift; } - if (Form == ARMII::VFPConv2Frm) - --OpIdx; - else - ++OpIdx; - - if (Form == ARMII::VFPConv3Frm) { - unsigned RegM = MI.getOperand(OpIdx).getReg(); - isSPVFP = false; - RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP); - if (!isSPVFP) - Binary |= RegM; - else { - Binary |= ((RegM & 0x1E) >> 1); - Binary |= (RegM & 0x01) << ARMII::M_BitShift; - } - - emitWordLE(Binary); - return; - } + return Binary; +} - // Encode Dn / Sn. +static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) { unsigned RegN = MI.getOperand(OpIdx).getReg(); - isSPVFP = false; + unsigned Binary = 0; + bool isSPVFP = false; RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP); if (!isSPVFP) Binary |= RegN << ARMII::RegRnShift; @@ -1149,23 +1122,74 @@ Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; Binary |= (RegN & 0x01) << ARMII::N_BitShift; } - if (Form == ARMII::VFPConv2Frm) - --OpIdx; - else - ++OpIdx; + return Binary; +} - // FMRS / FMSR do not have Rm. - if (TID.getNumOperands() > OpIdx && MI.getOperand(OpIdx).isReg()) { - unsigned RegM = MI.getOperand(OpIdx).getReg(); - isSPVFP = false; - RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP); - if (!isSPVFP) - Binary |= RegM; - else { - Binary |= ((RegM & 0x1E) >> 1); - Binary |= (RegM & 0x01) << ARMII::M_BitShift; - } +static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) { + unsigned RegM = MI.getOperand(OpIdx).getReg(); + unsigned Binary = 0; + bool isSPVFP = false; + RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP); + if (!isSPVFP) + Binary |= RegM; + else { + Binary |= ((RegM & 0x1E) >> 1); + Binary |= (RegM & 0x01) << ARMII::M_BitShift; } + return Binary; +} + +void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { + const TargetInstrDesc &TID = MI.getDesc(); + unsigned Form = TID.TSFlags & ARMII::FormMask; + + // Part of binary is determined by TableGn. + unsigned Binary = getBinaryCodeForInstr(MI); + + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << ARMII::CondShift; + + switch (Form) { + default: break; + case ARMII::VFPConv1Frm: + case ARMII::VFPConv2Frm: + case ARMII::VFPConv3Frm: + // Encode Dd / Sd. + Binary |= encodeVFPRd(MI, 0); + break; + case ARMII::VFPConv4Frm: + // Encode Dn / Sn. + Binary |= encodeVFPRn(MI, 0); + break; + case ARMII::VFPConv5Frm: + // Encode Dm / Sm. + Binary |= encodeVFPRm(MI, 0); + break; + } + + switch (Form) { + default: break; + case ARMII::VFPConv1Frm: + // Encode Dm / Sm. + Binary |= encodeVFPRm(MI, 1); + case ARMII::VFPConv2Frm: + case ARMII::VFPConv3Frm: + // Encode Dn / Sn. + Binary |= encodeVFPRn(MI, 1); + break; + case ARMII::VFPConv4Frm: + case ARMII::VFPConv5Frm: + // Encode Dd / Sd. + Binary |= encodeVFPRd(MI, 1); + break; + } + + if (Form == ARMII::VFPConv5Frm) + // Encode Dn / Sn. + Binary |= encodeVFPRn(MI, 2); + else if (Form == ARMII::VFPConv3Frm) + // Encode Dm / Sm. + Binary |= encodeVFPRm(MI, 2); emitWordLE(Binary); } Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=59104&r1=59103&r2=59104&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Nov 12 00:41:41 2008 @@ -42,11 +42,13 @@ def VFPConv1Frm : Format<17>; def VFPConv2Frm : Format<18>; def VFPConv3Frm : Format<19>; -def VFPLdStFrm : Format<20>; -def VFPLdStMulFrm : Format<21>; -def VFPMiscFrm : Format<22>; +def VFPConv4Frm : Format<20>; +def VFPConv5Frm : Format<21>; +def VFPLdStFrm : Format<22>; +def VFPLdStMulFrm : Format<23>; +def VFPMiscFrm : Format<24>; -def ThumbFrm : Format<23>; +def ThumbFrm : Format<25>; // Misc flag for data processing instructions that indicates whether // the instruction has a Rn register operand. @@ -820,30 +822,39 @@ let Inst{11-8} = 0b1010; } -class AVConv1I opcod1, bits<4> opcod2, dag oops, dag iops, string opc, - string asm, list pattern> +// VFP conversion instructions +class AVConv1I opcod1, bits<4> opcod2, bits<4> opcod3, + dag oops, dag iops, string opc, string asm, list pattern> : AI { let Inst{27-20} = opcod1; - let Inst{11-8} = opcod2; - let Inst{4} = 1; + let Inst{19-16} = opcod2; + let Inst{11-8} = opcod3; + let Inst{6} = 1; } -class AVConv2I opcod1, bits<4> opcod2, dag oops, dag iops, string opc, - string asm, list pattern> - : AI { +class AVConvXI opcod1, bits<4> opcod2, dag oops, dag iops, Format f, + string opc, string asm, list pattern> + : AI { let Inst{27-20} = opcod1; let Inst{11-8} = opcod2; let Inst{4} = 1; } -class AVConv3I opcod1, bits<4> opcod2, bits<4> opcod3, - dag oops, dag iops, string opc, string asm, list pattern> - : AI { - let Inst{27-20} = opcod1; - let Inst{19-16} = opcod2; - let Inst{11-8} = opcod3; - let Inst{6} = 1; -} +class AVConv2I opcod1, bits<4> opcod2, dag oops, dag iops, string opc, + string asm, list pattern> + : AVConvXI; + +class AVConv3I opcod1, bits<4> opcod2, dag oops, dag iops, string opc, + string asm, list pattern> + : AVConvXI; + +class AVConv4I opcod1, bits<4> opcod2, dag oops, dag iops, string opc, + string asm, list pattern> + : AVConvXI; + +class AVConv5I opcod1, bits<4> opcod2, dag oops, dag iops, string opc, + string asm, list pattern> + : AVConvXI; //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=59104&r1=59103&r2=59104&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Wed Nov 12 00:41:41 2008 @@ -106,12 +106,14 @@ VFPConv1Frm = 17 << FormShift, VFPConv2Frm = 18 << FormShift, VFPConv3Frm = 19 << FormShift, - VFPLdStFrm = 20 << FormShift, - VFPLdStMulFrm = 21 << FormShift, - VFPMiscFrm = 22 << FormShift, + VFPConv4Frm = 20 << FormShift, + VFPConv5Frm = 21 << FormShift, + VFPLdStFrm = 22 << FormShift, + VFPLdStMulFrm = 23 << FormShift, + VFPMiscFrm = 24 << FormShift, // Thumb format - ThumbFrm = 23 << FormShift, + ThumbFrm = 25 << FormShift, //===------------------------------------------------------------------===// // Field shifts - such shifts are used to set field while generating Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=59104&r1=59103&r2=59104&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Wed Nov 12 00:41:41 2008 @@ -219,15 +219,15 @@ // FP <-> GPR Copies. Int <-> FP Conversions. // -def FMRS : AVConv1I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src), +def FMRS : AVConv2I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src), "fmrs", " $dst, $src", [(set GPR:$dst, (bitconvert SPR:$src))]>; -def FMSR : AVConv2I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src), +def FMSR : AVConv4I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src), "fmsr", " $dst, $src", [(set SPR:$dst, (bitconvert GPR:$src))]>; -def FMRRD : AVConv1I<0b11000101, 0b1011, +def FMRRD : AVConv3I<0b11000101, 0b1011, (outs GPR:$dst1, GPR:$dst2), (ins DPR:$src), "fmrrd", " $dst1, $dst2, $src", [/* FIXME: Can't write pattern for multiple result instr*/]>; @@ -235,7 +235,7 @@ // FMDHR: GPR -> SPR // FMDLR: GPR -> SPR -def FMDRR : AVConv2I<0b11000100, 0b1011, (outs DPR:$dst), (ins GPR:$src1, GPR:$src2), +def FMDRR : AVConv5I<0b11000100, 0b1011, (outs DPR:$dst), (ins GPR:$src1, GPR:$src2), "fmdrr", " $dst, $src1, $src2", [(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>; @@ -251,25 +251,25 @@ // Int to FP: -def FSITOD : AVConv3I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a), +def FSITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a), "fsitod", " $dst, $a", [(set DPR:$dst, (arm_sitof SPR:$a))]> { let Inst{7} = 1; // Z bit } -def FSITOS : AVConv3I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a), +def FSITOS : AVConv1I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a), "fsitos", " $dst, $a", [(set SPR:$dst, (arm_sitof SPR:$a))]> { let Inst{7} = 1; // Z bit } -def FUITOD : AVConv3I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a), +def FUITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a), "fuitod", " $dst, $a", [(set DPR:$dst, (arm_uitof SPR:$a))]> { let Inst{7} = 0; // Z bit } -def FUITOS : AVConv3I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a), +def FUITOS : AVConv1I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a), "fuitos", " $dst, $a", [(set SPR:$dst, (arm_uitof SPR:$a))]> { let Inst{7} = 1; // Z bit @@ -278,28 +278,28 @@ // FP to Int: // Always set Z bit in the instruction, i.e. "round towards zero" variants. -def FTOSIZD : AVConv3I<0b11101011, 0b1101, 0b1011, +def FTOSIZD : AVConv1I<0b11101011, 0b1101, 0b1011, (outs SPR:$dst), (ins DPR:$a), "ftosizd", " $dst, $a", [(set SPR:$dst, (arm_ftosi DPR:$a))]> { let Inst{7} = 1; // Z bit } -def FTOSIZS : AVConv3I<0b11101011, 0b1101, 0b1010, +def FTOSIZS : AVConv1I<0b11101011, 0b1101, 0b1010, (outs SPR:$dst), (ins SPR:$a), "ftosizs", " $dst, $a", [(set SPR:$dst, (arm_ftosi SPR:$a))]> { let Inst{7} = 1; // Z bit } -def FTOUIZD : AVConv3I<0b11101011, 0b1100, 0b1011, +def FTOUIZD : AVConv1I<0b11101011, 0b1100, 0b1011, (outs SPR:$dst), (ins DPR:$a), "ftouizd", " $dst, $a", [(set SPR:$dst, (arm_ftoui DPR:$a))]> { let Inst{7} = 1; // Z bit } -def FTOUIZS : AVConv3I<0b11101011, 0b1100, 0b1010, +def FTOUIZS : AVConv1I<0b11101011, 0b1100, 0b1010, (outs SPR:$dst), (ins SPR:$a), "ftouizs", " $dst, $a", [(set SPR:$dst, (arm_ftoui SPR:$a))]> { From tonic at nondot.org Wed Nov 12 01:17:57 2008 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 12 Nov 2008 07:17:57 -0000 Subject: [llvm-commits] [llvm] r59106 - /llvm/trunk/include/llvm/Intrinsics.td Message-ID: <200811120717.mAC7HvvO000935@zion.cs.uiuc.edu> Author: tbrethou Date: Wed Nov 12 01:17:57 2008 New Revision: 59106 URL: http://llvm.org/viewvc/llvm-project?rev=59106&view=rev Log: Add ptr annotation intrinsic. Modified: llvm/trunk/include/llvm/Intrinsics.td Modified: llvm/trunk/include/llvm/Intrinsics.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=59106&r1=59105&r2=59106&view=diff ============================================================================== --- llvm/trunk/include/llvm/Intrinsics.td (original) +++ llvm/trunk/include/llvm/Intrinsics.td Wed Nov 12 01:17:57 2008 @@ -277,7 +277,10 @@ def int_var_annotation : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], [], "llvm.var.annotation">; - +def int_ptr_annotation : Intrinsic<[LLVMAnyPointerType, + LLVMMatchType<0>, + llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], + [], "llvm.ptr.annotation">; def int_annotation : Intrinsic<[llvm_anyint_ty, LLVMMatchType<0>, llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], [], "llvm.annotation">; From evan.cheng at apple.com Wed Nov 12 01:18:38 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Nov 2008 07:18:38 -0000 Subject: [llvm-commits] [llvm] r59107 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMInstrFormats.td ARMInstrInfo.h ARMInstrInfo.td ARMInstrVFP.td Message-ID: <200811120718.mAC7IctI000968@zion.cs.uiuc.edu> Author: evancheng Date: Wed Nov 12 01:18:38 2008 New Revision: 59107 URL: http://llvm.org/viewvc/llvm-project?rev=59107&view=rev Log: Consolidate formats; fix FCMPED etc. encodings. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.h llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=59107&r1=59106&r2=59107&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Wed Nov 12 01:18:38 2008 @@ -312,16 +312,13 @@ case ARMII::DPSoRegFrm: emitDataProcessingInstruction(MI); break; - case ARMII::LdFrm: - case ARMII::StFrm: + case ARMII::LdStFrm: emitLoadStoreInstruction(MI); break; - case ARMII::LdMiscFrm: - case ARMII::StMiscFrm: + case ARMII::LdStMiscFrm: emitMiscLoadStoreInstruction(MI); break; - case ARMII::LdMulFrm: - case ARMII::StMulFrm: + case ARMII::LdStMulFrm: emitLoadStoreMultipleInstruction(MI); break; case ARMII::MulFrm: @@ -1040,63 +1037,6 @@ emitWordLE(Binary); } -void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { - const TargetInstrDesc &TID = MI.getDesc(); - - // Part of binary is determined by TableGn. - unsigned Binary = getBinaryCodeForInstr(MI); - - // Set the conditional execution predicate - Binary |= II->getPredicate(&MI) << ARMII::CondShift; - - unsigned OpIdx = 0; - assert((Binary & ARMII::D_BitShift) == 0 && - (Binary & ARMII::N_BitShift) == 0 && - (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!"); - - // Encode Dd / Sd. - unsigned RegD = MI.getOperand(OpIdx++).getReg(); - bool isSPVFP = false; - RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP); - if (!isSPVFP) - Binary |= RegD << ARMII::RegRdShift; - else { - Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; - Binary |= (RegD & 0x01) << ARMII::D_BitShift; - } - - - // If this is a two-address operand, skip it, e.g. FMACD. - if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) - ++OpIdx; - - // Encode Dn / Sn. - if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) { - unsigned RegN = MI.getOperand(OpIdx++).getReg(); - isSPVFP = false; - RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP); - if (!isSPVFP) - Binary |= RegN << ARMII::RegRnShift; - else { - Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; - Binary |= (RegN & 0x01) << ARMII::N_BitShift; - } - } - - // Encode Dm / Sm. - unsigned RegM = MI.getOperand(OpIdx++).getReg(); - isSPVFP = false; - RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP); - if (!isSPVFP) - Binary |= RegM; - else { - Binary |= ((RegM & 0x1E) >> 1); - Binary |= (RegM & 0x01) << ARMII::M_BitShift; - } - - emitWordLE(Binary); -} - static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { unsigned RegD = MI.getOperand(OpIdx).getReg(); unsigned Binary = 0; @@ -1139,6 +1079,45 @@ return Binary; } +void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { + const TargetInstrDesc &TID = MI.getDesc(); + + // Part of binary is determined by TableGn. + unsigned Binary = getBinaryCodeForInstr(MI); + + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << ARMII::CondShift; + + unsigned OpIdx = 0; + assert((Binary & ARMII::D_BitShift) == 0 && + (Binary & ARMII::N_BitShift) == 0 && + (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!"); + + // Encode Dd / Sd. + Binary |= encodeVFPRd(MI, OpIdx++); + + // If this is a two-address operand, skip it, e.g. FMACD. + if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) + ++OpIdx; + + // Encode Dn / Sn. + if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) + Binary |= encodeVFPRn(MI, OpIdx); + + if (OpIdx == TID.getNumOperands() || + TID.OpInfo[OpIdx].isPredicate() || + TID.OpInfo[OpIdx].isOptionalDef()) { + // FCMPEZD etc. has only one operand. + emitWordLE(Binary); + return; + } + + // Encode Dm / Sm. + Binary |= encodeVFPRm(MI, OpIdx); + + emitWordLE(Binary); +} + void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); unsigned Form = TID.TSFlags & ARMII::FormMask; @@ -1204,15 +1183,7 @@ unsigned OpIdx = 0; // Encode Dd / Sd. - unsigned RegD = MI.getOperand(OpIdx++).getReg(); - bool isSPVFP = false; - RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP); - if (!isSPVFP) - Binary |= RegD << ARMII::RegRdShift; - else { - Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; - Binary |= (RegD & 0x01) << ARMII::D_BitShift; - } + Binary |= encodeVFPRd(MI, OpIdx++); // Encode address base. const MachineOperand &Base = MI.getOperand(OpIdx++); @@ -1257,15 +1228,7 @@ Binary |= 0x1 << ARMII::W_BitShift; // First register is encoded in Dd. - unsigned RegD = MI.getOperand(4).getReg(); - bool isSPVFP = false; - RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP); - if (!isSPVFP) - Binary |= RegD << ARMII::RegRdShift; - else { - Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; - Binary |= (RegD & 0x01) << ARMII::D_BitShift; - } + Binary |= encodeVFPRd(MI, 4); // Number of registers are encoded in offset field. unsigned NumRegs = 1; Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=59107&r1=59106&r2=59107&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Nov 12 01:18:38 2008 @@ -27,28 +27,25 @@ def DPFrm : Format<5>; def DPSoRegFrm : Format<6>; -def LdFrm : Format<7>; -def StFrm : Format<8>; -def LdMiscFrm : Format<9>; -def StMiscFrm : Format<10>; -def LdMulFrm : Format<11>; -def StMulFrm : Format<12>; - -def ArithMiscFrm : Format<13>; -def ExtFrm : Format<14>; - -def VFPUnaryFrm : Format<15>; -def VFPBinaryFrm : Format<16>; -def VFPConv1Frm : Format<17>; -def VFPConv2Frm : Format<18>; -def VFPConv3Frm : Format<19>; -def VFPConv4Frm : Format<20>; -def VFPConv5Frm : Format<21>; -def VFPLdStFrm : Format<22>; -def VFPLdStMulFrm : Format<23>; -def VFPMiscFrm : Format<24>; +def LdStFrm : Format<7>; +def LdStMiscFrm : Format<8>; +def LdStMulFrm : Format<9>; + +def ArithMiscFrm : Format<10>; +def ExtFrm : Format<11>; + +def VFPUnaryFrm : Format<12>; +def VFPBinaryFrm : Format<13>; +def VFPConv1Frm : Format<14>; +def VFPConv2Frm : Format<15>; +def VFPConv3Frm : Format<16>; +def VFPConv4Frm : Format<17>; +def VFPConv5Frm : Format<18>; +def VFPLdStFrm : Format<19>; +def VFPLdStMulFrm : Format<20>; +def VFPMiscFrm : Format<21>; -def ThumbFrm : Format<25>; +def ThumbFrm : Format<22>; // Misc flag for data processing instructions that indicates whether // the instruction has a Rn register operand. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=59107&r1=59106&r2=59107&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Wed Nov 12 01:18:38 2008 @@ -73,47 +73,44 @@ FormMask = 0x1f << FormShift, // Pseudo instructions - Pseudo = 1 << FormShift, + Pseudo = 1 << FormShift, // Multiply instructions - MulFrm = 2 << FormShift, + MulFrm = 2 << FormShift, // Branch instructions - BrFrm = 3 << FormShift, - BrMiscFrm = 4 << FormShift, + BrFrm = 3 << FormShift, + BrMiscFrm = 4 << FormShift, // Data Processing instructions - DPFrm = 5 << FormShift, - DPSoRegFrm = 6 << FormShift, + DPFrm = 5 << FormShift, + DPSoRegFrm = 6 << FormShift, // Load and Store - LdFrm = 7 << FormShift, - StFrm = 8 << FormShift, - LdMiscFrm = 9 << FormShift, - StMiscFrm = 10 << FormShift, - LdMulFrm = 11 << FormShift, - StMulFrm = 12 << FormShift, + LdStFrm = 7 << FormShift, + LdStMiscFrm = 8 << FormShift, + LdStMulFrm = 9 << FormShift, // Miscellaneous arithmetic instructions - ArithMiscFrm = 13 << FormShift, + ArithMiscFrm = 10 << FormShift, // Extend instructions - ExtFrm = 14 << FormShift, + ExtFrm = 11 << FormShift, // VFP formats - VFPUnaryFrm = 15 << FormShift, - VFPBinaryFrm = 16 << FormShift, - VFPConv1Frm = 17 << FormShift, - VFPConv2Frm = 18 << FormShift, - VFPConv3Frm = 19 << FormShift, - VFPConv4Frm = 20 << FormShift, - VFPConv5Frm = 21 << FormShift, - VFPLdStFrm = 22 << FormShift, - VFPLdStMulFrm = 23 << FormShift, - VFPMiscFrm = 24 << FormShift, + VFPUnaryFrm = 12 << FormShift, + VFPBinaryFrm = 13 << FormShift, + VFPConv1Frm = 14 << FormShift, + VFPConv2Frm = 15 << FormShift, + VFPConv3Frm = 16 << FormShift, + VFPConv4Frm = 17 << FormShift, + VFPConv5Frm = 18 << FormShift, + VFPLdStFrm = 19 << FormShift, + VFPLdStMulFrm = 20 << FormShift, + VFPMiscFrm = 21 << FormShift, // Thumb format - ThumbFrm = 25 << FormShift, + ThumbFrm = 22 << FormShift, //===------------------------------------------------------------------===// // Field shifts - such shifts are used to set field while generating Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=59107&r1=59106&r2=59107&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 12 01:18:38 2008 @@ -533,7 +533,7 @@ let isReturn = 1, isTerminator = 1 in def LDM_RET : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), - LdMulFrm, "ldm${p}${addr:submode} $addr, $dst1", + LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1", []>; let isCall = 1, @@ -615,134 +615,134 @@ // Load let isSimpleLoad = 1 in -def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, +def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdStFrm, "ldr", " $dst, $addr", [(set GPR:$dst, (load addrmode2:$addr))]>; // Special LDR for loads from non-pc-relative constpools. let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1 in -def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, +def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdStFrm, "ldr", " $dst, $addr", []>; // Loads with zero extension -def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, +def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdStMiscFrm, "ldr", "h $dst, $addr", [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>; -def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, +def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdStFrm, "ldr", "b $dst, $addr", [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>; // Loads with sign extension -def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, +def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdStMiscFrm, "ldr", "sh $dst, $addr", [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>; -def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, +def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdStMiscFrm, "ldr", "sb $dst, $addr", [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>; let mayLoad = 1 in { // Load doubleword -def LDRD : AI3ldd<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, +def LDRD : AI3ldd<(outs GPR:$dst), (ins addrmode3:$addr), LdStMiscFrm, "ldr", "d $dst, $addr", []>, Requires<[IsARM, HasV5T]>; // Indexed loads def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb), - (ins addrmode2:$addr), LdFrm, + (ins addrmode2:$addr), LdStFrm, "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>; def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base, am2offset:$offset), LdFrm, + (ins GPR:$base, am2offset:$offset), LdStFrm, "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>; def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb), - (ins addrmode3:$addr), LdMiscFrm, + (ins addrmode3:$addr), LdStMiscFrm, "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>; def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base,am3offset:$offset), LdMiscFrm, + (ins GPR:$base,am3offset:$offset), LdStMiscFrm, "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>; def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb), - (ins addrmode2:$addr), LdFrm, + (ins addrmode2:$addr), LdStFrm, "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>; def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base,am2offset:$offset), LdFrm, + (ins GPR:$base,am2offset:$offset), LdStFrm, "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>; def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb), - (ins addrmode3:$addr), LdMiscFrm, + (ins addrmode3:$addr), LdStMiscFrm, "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>; def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base,am3offset:$offset), LdMiscFrm, + (ins GPR:$base,am3offset:$offset), LdStMiscFrm, "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>; def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb), - (ins addrmode3:$addr), LdMiscFrm, + (ins addrmode3:$addr), LdStMiscFrm, "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>; def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base,am3offset:$offset), LdMiscFrm, + (ins GPR:$base,am3offset:$offset), LdStMiscFrm, "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>; } // Store -def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, +def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), LdStFrm, "str", " $src, $addr", [(store GPR:$src, addrmode2:$addr)]>; // Stores with truncate -def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, +def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), LdStMiscFrm, "str", "h $src, $addr", [(truncstorei16 GPR:$src, addrmode3:$addr)]>; -def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, +def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), LdStFrm, "str", "b $src, $addr", [(truncstorei8 GPR:$src, addrmode2:$addr)]>; // Store doubleword let mayStore = 1 in -def STRD : AI3std<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, +def STRD : AI3std<(outs), (ins GPR:$src, addrmode3:$addr), LdStMiscFrm, "str", "d $src, $addr", []>, Requires<[IsARM, HasV5T]>; // Indexed stores def STR_PRE : AI2stwpr<(outs GPR:$base_wb), - (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm, + (ins GPR:$src, GPR:$base, am2offset:$offset), LdStFrm, "str", " $src, [$base, $offset]!", "$base = $base_wb", [(set GPR:$base_wb, (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>; def STR_POST : AI2stwpo<(outs GPR:$base_wb), - (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, + (ins GPR:$src, GPR:$base,am2offset:$offset), LdStFrm, "str", " $src, [$base], $offset", "$base = $base_wb", [(set GPR:$base_wb, (post_store GPR:$src, GPR:$base, am2offset:$offset))]>; def STRH_PRE : AI3sthpr<(outs GPR:$base_wb), - (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm, + (ins GPR:$src, GPR:$base,am3offset:$offset), LdStMiscFrm, "str", "h $src, [$base, $offset]!", "$base = $base_wb", [(set GPR:$base_wb, (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>; def STRH_POST: AI3sthpo<(outs GPR:$base_wb), - (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm, + (ins GPR:$src, GPR:$base,am3offset:$offset), LdStMiscFrm, "str", "h $src, [$base], $offset", "$base = $base_wb", [(set GPR:$base_wb, (post_truncsti16 GPR:$src, GPR:$base, am3offset:$offset))]>; def STRB_PRE : AI2stbpr<(outs GPR:$base_wb), - (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, + (ins GPR:$src, GPR:$base,am2offset:$offset), LdStFrm, "str", "b $src, [$base, $offset]!", "$base = $base_wb", [(set GPR:$base_wb, (pre_truncsti8 GPR:$src, GPR:$base, am2offset:$offset))]>; def STRB_POST: AI2stbpo<(outs GPR:$base_wb), - (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, + (ins GPR:$src, GPR:$base,am2offset:$offset), LdStFrm, "str", "b $src, [$base], $offset", "$base = $base_wb", [(set GPR:$base_wb, (post_truncsti8 GPR:$src, GPR:$base, am2offset:$offset))]>; @@ -755,13 +755,13 @@ let mayLoad = 1 in def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), - LdMulFrm, "ldm${p}${addr:submode} $addr, $dst1", + LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1", []>; let mayStore = 1 in def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), - StMulFrm, "stm${p}${addr:submode} $addr, $src1", + LdStMulFrm, "stm${p}${addr:submode} $addr, $src1", []>; //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=59107&r1=59106&r2=59107&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Wed Nov 12 01:18:38 2008 @@ -102,19 +102,14 @@ "fadds", " $dst, $a, $b", [(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>; -def FCMPED : ADbI<0b11101011, (outs), (ins DPR:$a, DPR:$b), +// These are encoded as unary instructions. +def FCMPED : ADuI<0b11101011, 0b0100, 0b1100, (outs), (ins DPR:$a, DPR:$b), "fcmped", " $a, $b", - [(arm_cmpfp DPR:$a, DPR:$b)]> { - let Inst{19-16} = 0b0100; - let Inst{7-6} = 0b11; -} + [(arm_cmpfp DPR:$a, DPR:$b)]>; -def FCMPES : ASbI<0b11101011, (outs), (ins SPR:$a, SPR:$b), +def FCMPES : ASuI<0b11101011, 0b0100, 0b1100, (outs), (ins SPR:$a, SPR:$b), "fcmpes", " $a, $b", - [(arm_cmpfp SPR:$a, SPR:$b)]> { - let Inst{19-16} = 0b0100; - let Inst{7-6} = 0b11; -} + [(arm_cmpfp SPR:$a, SPR:$b)]>; def FDIVD : ADbI<0b11101000, (outs DPR:$dst), (ins DPR:$a, DPR:$b), "fdivd", " $dst, $a, $b", From tonic at nondot.org Wed Nov 12 01:23:10 2008 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 12 Nov 2008 07:23:10 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r59108 - in /llvm-gcc-4.2/trunk/gcc: c-common.c llvm-convert.cpp Message-ID: <200811120723.mAC7NA6F001155@zion.cs.uiuc.edu> Author: tbrethou Date: Wed Nov 12 01:23:09 2008 New Revision: 59108 URL: http://llvm.org/viewvc/llvm-project?rev=59108&view=rev Log: Add the ability to annotate structs in a generic way. Modified: llvm-gcc-4.2/trunk/gcc/c-common.c llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/c-common.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/c-common.c?rev=59108&r1=59107&r2=59108&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/c-common.c (original) +++ llvm-gcc-4.2/trunk/gcc/c-common.c Wed Nov 12 01:23:09 2008 @@ -6380,6 +6380,7 @@ id = TREE_VALUE (args); if (TREE_CODE (*node) == FUNCTION_DECL || + TREE_CODE (*node) == FIELD_DECL || TREE_CODE (*node) == VAR_DECL || TREE_CODE (*node) == PARM_DECL) { Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=59108&r1=59107&r2=59108&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Nov 12 01:23:09 2008 @@ -6022,7 +6022,59 @@ const StructLayout *SL = TD.getStructLayout(cast(StructTy)); BitStart -= SL->getElementOffset(MemberIndex) * 8; } - + + // If the FIELD_DECL has an annotate attribute on it, emit it. + + // Handle annotate attribute on global. + if (tree AnnotateAttr = + lookup_attribute("annotate", DECL_ATTRIBUTES(FieldDecl))) { + + const Type *OrigPtrTy = FieldPtr->getType(); + + Function *Fn = Intrinsic::getDeclaration(TheModule, + Intrinsic::ptr_annotation, + &OrigPtrTy, 1); + + // Get file and line number. FIXME: Should this be for the decl or the + // use. Is there a location info for the use? + Constant *LineNo = ConstantInt::get(Type::Int32Ty, + DECL_SOURCE_LINE(FieldDecl)); + Constant *File = ConvertMetadataStringToGV(DECL_SOURCE_FILE(FieldDecl)); + const Type *SBP = PointerType::getUnqual(Type::Int8Ty); + File = TheFolder->CreateBitCast(File, SBP); + + // There may be multiple annotate attributes. Pass return of lookup_attr + // to successive lookups. + while (AnnotateAttr) { + // Each annotate attribute is a tree list. + // Get value of list which is our linked list of args. + tree args = TREE_VALUE(AnnotateAttr); + + // Each annotate attribute may have multiple args. + // Treat each arg as if it were a separate annotate attribute. + for (tree a = args; a; a = TREE_CHAIN(a)) { + // Each element of the arg list is a tree list, so get value + tree val = TREE_VALUE(a); + + // Assert its a string, and then get that string. + assert(TREE_CODE(val) == STRING_CST && + "Annotate attribute arg should always be a string"); + + const Type *SBP = PointerType::getUnqual(Type::Int8Ty); + Constant *strGV = TreeConstantToLLVM::EmitLV_STRING_CST(val); + Value *Ops[4] = { + FieldPtr, BitCastToType(strGV, SBP), File, LineNo + }; + + FieldPtr = Builder.CreateCall(Fn, Ops, Ops+4); + } + + // Get next annotate attribute. + AnnotateAttr = TREE_CHAIN(AnnotateAttr); + if (AnnotateAttr) + AnnotateAttr = lookup_attribute("annotate", AnnotateAttr); + } + } } else { Value *Offset = Emit(field_offset, 0); @@ -7242,6 +7294,7 @@ const StructLayout *SL = TD.getStructLayout(cast(StructTy)); BitStart -= SL->getElementOffset(MemberIndex) * 8; } + } else { Constant *Offset = Convert(field_offset); Constant *Ptr = TheFolder->CreatePtrToInt(StructAddrLV, Offset->getType()); From evan.cheng at apple.com Wed Nov 12 01:34:38 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Nov 2008 07:34:38 -0000 Subject: [llvm-commits] [llvm] r59109 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMInstrInfo.h Message-ID: <200811120734.mAC7YcZJ001545@zion.cs.uiuc.edu> Author: evancheng Date: Wed Nov 12 01:34:37 2008 New Revision: 59109 URL: http://llvm.org/viewvc/llvm-project?rev=59109&view=rev Log: Fix address mode 3 immediate offset mode encoding. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=59109&r1=59108&r2=59109&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Wed Nov 12 01:34:37 2008 @@ -736,11 +736,11 @@ // Set bit[3:0] to the corresponding Rm register Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); - // if this instr is in scaled register offset/index instruction, set + // If this instr is in scaled register offset/index instruction, set // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) { - Binary |= getShiftOp(AM2Opc) << 5; // shift - Binary |= ShImm << 7; // shift_immed + Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift + Binary |= ShImm << ARMII::ShiftShift; // shift_immed } emitWordLE(Binary); @@ -792,8 +792,8 @@ Binary |= 1 << ARMII::AM3_I_BitShift; if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) { // Set operands - Binary |= (ImmOffs >> 4) << 8; // immedH - Binary |= (ImmOffs & ~0xF); // immedL + Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH + Binary |= (ImmOffs & 0xF); // immedL } emitWordLE(Binary); Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=59109&r1=59108&r2=59109&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Wed Nov 12 01:34:37 2008 @@ -116,8 +116,10 @@ // Field shifts - such shifts are used to set field while generating // machine instructions. M_BitShift = 5, + ShiftImmShift = 5, ShiftShift = 7, N_BitShift = 7, + ImmHiShift = 8, SoRotImmShift = 8, RegRsShift = 8, ExtRotImmShift = 10, From wangmp at apple.com Wed Nov 12 02:09:05 2008 From: wangmp at apple.com (Mon Ping Wang) Date: Wed, 12 Nov 2008 00:09:05 -0800 Subject: [llvm-commits] [llvm] r59025 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h In-Reply-To: <200811110947.37471.duncan.sands@math.u-psud.fr> References: <200811110540.mAB5e7MV024421@zion.cs.uiuc.edu> <200811110947.37471.duncan.sands@math.u-psud.fr> Message-ID: Hi Duncan, On Nov 11, 2008, at 12:47 AM, Duncan Sands wrote: > Hi, > >> +SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { >> + ISD::CvtCode CvtCode = cast(N)->getCvtCode(); >> + assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || >> + CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || >> + CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && >> + "can only promote integers"); > > to promote the result, you should only need to modify the return > type of the node, right? I'm not sure why it's helpful to look > at the operand here (some promote methods look at the operand > because they can then promote in a more optimal way). I'm probably misunderstanding the design. PromoteIntRes will just promote the result. PromoteIntOp promotes an operand. An operation that can have an integer result will need a PromteIntRes routine and any operation that can take an integer input will need a PromoteIntOp. The only cases where PromoteIntRes routine will look at is operand is to know how to promote the result correctly. (e.g., bit convert needs to know what the input operand is to know what to generate). >> + case PromoteInteger: >> + return DAG.getConvertRndSat(OutVT, GetPromotedInteger(InOp), > > Also, promoted integers in general have rubbish in the extra bits. > So suppose originally you were converting i8 to i16, and i8 and > i16 get promoted to i32. Then here you will convert an i32 with > the original i8 in the lowest 8 bits, but with garbage in the upper > 24 bits, into an i32. This may give wrong results. In general > you need to do a SIGN_EXTEND_INREG or DAG.ZeroExtendInReg on the > promoted value to ensure that the extra bits are as desired. I didn't do the sign extensions or zero extensions because how these convert operate. If the convert is i8 to a float, it will do the operation on the lower 8 bits and ignore the rest so having junk up there is fine. The issue is that I shouldn't look at the promoted value. > Ciao, > > Duncan. > > PS: > >> + case ISD::CONVERT_RNDSAT: { >> + SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0)); >> + Result = DAG.getConvertRndSat(NewVT, Op0, >> + DAG.getValueType(NewVT), >> + DAG.getValueType(Op0.getValueType >> ()), >> + Node->getOperand(3), >> + Node->getOperand(4), >> + >> cast(Node)->getCvtCode()); + break; > > For CONVERT_RNDSAT on vectors, how about storing the vector element > types > as src and dest types, rather than the vector types. So a > CONVERT_RNDSAT > on [4 x i32], turning into [4 x i16] would have src = i16 and dest = > i32. > This seems conceptually a bit simpler to me, and also you wouldn't > have > to recalculate src and dest types here and in split. That is a good idea. The convert operator should store the kind of conversion that is being done. Storing the vector in the node doesn't provide any additional useful information. Thanks, -- Mon Ping From evan.cheng at apple.com Wed Nov 12 02:14:21 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Nov 2008 08:14:21 -0000 Subject: [llvm-commits] [llvm] r59116 - /llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Message-ID: <200811120814.mAC8ELll002999@zion.cs.uiuc.edu> Author: evancheng Date: Wed Nov 12 02:14:21 2008 New Revision: 59116 URL: http://llvm.org/viewvc/llvm-project?rev=59116&view=rev Log: Fix a VFP binary arithmetic instruction encoding bug. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=59116&r1=59115&r2=59116&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Wed Nov 12 02:14:21 2008 @@ -1102,7 +1102,7 @@ // Encode Dn / Sn. if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) - Binary |= encodeVFPRn(MI, OpIdx); + Binary |= encodeVFPRn(MI, OpIdx++); if (OpIdx == TID.getNumOperands() || TID.OpInfo[OpIdx].isPredicate() || From evan.cheng at apple.com Wed Nov 12 02:21:12 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Nov 2008 08:21:12 -0000 Subject: [llvm-commits] [llvm] r59117 - /llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Message-ID: <200811120821.mAC8LCdY003218@zion.cs.uiuc.edu> Author: evancheng Date: Wed Nov 12 02:21:12 2008 New Revision: 59117 URL: http://llvm.org/viewvc/llvm-project?rev=59117&view=rev Log: Address mode immediate offset has already been divided by 4. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=59117&r1=59116&r2=59117&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Wed Nov 12 02:21:12 2008 @@ -1195,8 +1195,7 @@ if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) { if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add) Binary |= 1 << ARMII::U_BitShift; - // Immediate offset is multiplied by 4. - Binary |= ImmOffs >> 2; + Binary |= ImmOffs; emitWordLE(Binary); return; } From evan.cheng at apple.com Wed Nov 12 02:22:43 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Nov 2008 08:22:43 -0000 Subject: [llvm-commits] [llvm] r59119 - /llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp Message-ID: <200811120822.mAC8Mhj8003300@zion.cs.uiuc.edu> Author: evancheng Date: Wed Nov 12 02:22:43 2008 New Revision: 59119 URL: http://llvm.org/viewvc/llvm-project?rev=59119&view=rev Log: Change binary dump format. Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp?rev=59119&r1=59118&r2=59119&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp Wed Nov 12 02:22:43 2008 @@ -965,18 +965,30 @@ #ifndef NDEBUG { - DOUT << "JIT: Disassembled code:\n"; - if (sys::hasDisassembler()) + if (sys::hasDisassembler()) { + DOUT << "JIT: Disassembled code:\n"; DOUT << sys::disassembleBuffer(FnStart, FnEnd-FnStart, (uintptr_t)FnStart); - else { + } else { + DOUT << "JIT: Binary code:\n"; DOUT << std::hex; - int i; unsigned char* q = FnStart; - for (i=1; q!=FnEnd; q++, i++) { - if (i%8==1) - DOUT << "JIT: 0x" << (long)q << ": "; - DOUT<< std::setw(2) << std::setfill('0') << (unsigned short)*q << " "; - if (i%8==0) + for (int i = 0; q < FnEnd; q += 4, ++i) { + if (i == 4) + i = 0; + if (i == 0) + DOUT << "JIT: " << std::setw(8) << std::setfill('0') + << (long)(q - FnStart) << ": "; + bool Done = false; + for (int j = 3; j >= 0; --j) { + if (q + j >= FnEnd) + Done = true; + else + DOUT << std::setw(2) << std::setfill('0') << (unsigned short)q[j]; + } + if (Done) + break; + DOUT << ' '; + if (i == 3) DOUT << '\n'; } DOUT << std::dec; From baldrick at free.fr Wed Nov 12 02:23:26 2008 From: baldrick at free.fr (Duncan Sands) Date: Wed, 12 Nov 2008 08:23:26 -0000 Subject: [llvm-commits] [llvm] r59120 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp test/CodeGen/Alpha/2008-11-12-Add128.ll Message-ID: <200811120823.mAC8NQup003335@zion.cs.uiuc.edu> Author: baldrick Date: Wed Nov 12 02:23:26 2008 New Revision: 59120 URL: http://llvm.org/viewvc/llvm-project?rev=59120&view=rev Log: Correct some thinkos in the expansion of ADD/SUB when the target does not support ADDC/SUBC. This fixes PR3044. Added: llvm/trunk/test/CodeGen/Alpha/2008-11-12-Add128.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=59120&r1=59119&r2=59120&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Wed Nov 12 02:23:26 2008 @@ -1228,7 +1228,6 @@ GetExpandedInteger(N->getOperand(1), RHSL, RHSH); MVT NVT = LHSL.getValueType(); - SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); SDValue LoOps[2] = { LHSL, RHSL }; SDValue HiOps[3] = { LHSH, RHSH }; @@ -1242,6 +1241,7 @@ TLI.getTypeToExpandTo(NVT)); if (hasCarry) { + SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); if (N->getOpcode() == ISD::ADD) { Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); HiOps[2] = Lo.getValue(1); @@ -1253,8 +1253,8 @@ } } else { if (N->getOpcode() == ISD::ADD) { - Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2); - Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2); + Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2); + Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2); SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[0], ISD::SETULT); SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1, @@ -1266,9 +1266,10 @@ DAG.getConstant(1, NVT), Carry1); Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2); } else { - Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2); - Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2); - SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT); + Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2); + Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2); + SDValue Cmp = DAG.getSetCC(TLI.getSetCCResultType(LoOps[0]), + LoOps[0], LoOps[1], ISD::SETULT); SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp, DAG.getConstant(1, NVT), DAG.getConstant(0, NVT)); Added: llvm/trunk/test/CodeGen/Alpha/2008-11-12-Add128.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Alpha/2008-11-12-Add128.ll?rev=59120&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Alpha/2008-11-12-Add128.ll (added) +++ llvm/trunk/test/CodeGen/Alpha/2008-11-12-Add128.ll Wed Nov 12 02:23:26 2008 @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc +; PR3044 +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f128:128:128" +target triple = "alphaev6-unknown-linux-gnu" + +define i128 @__mulvti3(i128 %u, i128 %v) nounwind { +entry: + %0 = load i128* null, align 16 ; [#uses=1] + %1 = load i64* null, align 8 ; [#uses=1] + %2 = zext i64 %1 to i128 ; [#uses=1] + %3 = add i128 %2, %0 ; [#uses=1] + store i128 %3, i128* null, align 16 + unreachable +} From duncan.sands at math.u-psud.fr Wed Nov 12 02:26:44 2008 From: duncan.sands at math.u-psud.fr (Duncan Sands) Date: Wed, 12 Nov 2008 09:26:44 +0100 Subject: [llvm-commits] [llvm] r59025 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h In-Reply-To: References: <200811110540.mAB5e7MV024421@zion.cs.uiuc.edu> <200811110947.37471.duncan.sands@math.u-psud.fr> Message-ID: <200811120926.45016.duncan.sands@math.u-psud.fr> Hi, > I'm probably misunderstanding the design. PromoteIntRes will just > promote the result. PromoteIntOp promotes an operand. An operation > that can have an integer result will need a PromteIntRes routine and > any operation that can take an integer input will need a > PromoteIntOp. The only cases where PromoteIntRes routine will look at > is operand is to know how to promote the result correctly. (e.g., bit > convert needs to know what the input operand is to know what to > generate). exactly. So why does PromoteIntRes_CONVERT_RNDSAT look at the operand? And why did you remove the operand promotion version? > I didn't do the sign extensions or zero extensions because how these > convert operate. If the convert is i8 to a float, it will do the > operation on the lower 8 bits and ignore the rest so having junk up > there is fine. The issue is that I shouldn't look at the promoted > value. OK. Ciao, Duncan. From baldrick at free.fr Wed Nov 12 02:37:58 2008 From: baldrick at free.fr (Duncan Sands) Date: Wed, 12 Nov 2008 08:37:58 -0000 Subject: [llvm-commits] [llvm] r59122 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Message-ID: <200811120837.mAC8bwGs004832@zion.cs.uiuc.edu> Author: baldrick Date: Wed Nov 12 02:37:57 2008 New Revision: 59122 URL: http://llvm.org/viewvc/llvm-project?rev=59122&view=rev Log: Simplify SplitVecRes_EXTRACT_SUBVECTOR. This means that it no longer handles non-power-of-two vectors. However it previously only handled them sometimes, depending on obscure numerical relationships between the index and vector type. For example, for a vector of length 6, it would succeed if and only if the index was an even multiple of 6. I consider this more confusing than useful. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=59122&r1=59121&r2=59122&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Wed Nov 12 02:37:57 2008 @@ -355,8 +355,8 @@ case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break; case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; case ISD::LOAD: SplitVecRes_LOAD(cast(N), Lo, Hi);break; - case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break; - case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break; + case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break; + case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break; case ISD::CTTZ: case ISD::CTLZ: @@ -520,28 +520,20 @@ void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi) { + SDValue Vec = N->getOperand(0); + SDValue Idx = N->getOperand(1); + MVT IdxVT = Idx.getValueType(); + MVT LoVT, HiVT; GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); - unsigned LoNumElts = LoVT.getVectorNumElements(); + // The indices are not guaranteed to be a multiple of the new vector + // size unless the original vector type was split in two. + assert(LoVT == HiVT && "Non power-of-two vectors not supported!"); - SDValue Vec = N->getOperand(0); - SDValue Idx = N->getOperand(1); - MVT IdxVT = Idx.getValueType(); Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, LoVT, Vec, Idx); - - ConstantSDNode *CIdx = dyn_cast(Idx); - if (CIdx) { - unsigned IdxVal = CIdx->getZExtValue(); - assert (IdxVal % LoVT.getVectorNumElements() == 0 && - (IdxVal+LoNumElts) % HiVT.getVectorNumElements()==0 && - "Index must be a multiple of the result type"); - Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, HiVT, Vec, - DAG.getConstant(IdxVal + LoNumElts, IdxVT)); - } else { - assert(LoVT == HiVT && "Low and High value type should be the same"); - Idx = DAG.getNode(ISD::ADD, IdxVT, Idx, DAG.getConstant(LoNumElts, IdxVT)); - Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, HiVT, Vec, Idx); - } + Idx = DAG.getNode(ISD::ADD, IdxVT, Idx, + DAG.getConstant(LoVT.getVectorNumElements(), IdxVT)); + Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, HiVT, Vec, Idx); } void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, From baldrick at free.fr Wed Nov 12 04:10:27 2008 From: baldrick at free.fr (Duncan Sands) Date: Wed, 12 Nov 2008 10:10:27 -0000 Subject: [llvm-commits] [llvm] r59126 - /llvm/trunk/docs/index.html Message-ID: <200811121010.mACAASOl017445@zion.cs.uiuc.edu> Author: baldrick Date: Wed Nov 12 04:10:25 2008 New Revision: 59126 URL: http://llvm.org/viewvc/llvm-project?rev=59126&view=rev Log: Correct these links. Modified: llvm/trunk/docs/index.html Modified: llvm/trunk/docs/index.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/index.html?rev=59126&r1=59125&r2=59126&view=diff ============================================================================== --- llvm/trunk/docs/index.html (original) +++ llvm/trunk/docs/index.html Wed Nov 12 04:10:25 2008 @@ -233,27 +233,27 @@
-
The +
The LLVM Announcements List: This is a low volume list that provides important announcements regarding LLVM. It gets email about once a month.
-
The Developer's +
The Developer's List: This list is for people who want to be included in technical discussions of LLVM. People post to this list when they have questions about writing code for or using the LLVM tools. It is relatively low volume.
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The Bugs & +
The Bugs & Patches Archive: This list gets emailed every time a bug is opened and closed, and when people submit patches to be included in LLVM. It is higher volume than the LLVMdev list.
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The Commits +
The Commits Archive: This list contains all commit messages that are made when LLVM developers commit code changes to the repository. It is useful for those who want to stay on the bleeding edge of LLVM development. This list is very high volume.
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The +
The Test Results Archive: A message is automatically sent to this list by every active nightly tester when it completes. As such, this list gets email several times each day, making it a high volume list.
From foldr at codedgers.com Wed Nov 12 06:41:18 2008 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Wed, 12 Nov 2008 12:41:18 -0000 Subject: [llvm-commits] [llvm] r59131 - /llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Message-ID: <200811121241.mACCfI7X024233@zion.cs.uiuc.edu> Author: foldr Date: Wed Nov 12 06:41:18 2008 New Revision: 59131 URL: http://llvm.org/viewvc/llvm-project?rev=59131&view=rev Log: Check the return value of std::getenv. When constructing std::strings from C strings, we should check the input value to be not NULL so that the std::string constructor does not segfault. Fixes #3047. Modified: llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Modified: llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp?rev=59131&r1=59130&r2=59131&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Wed Nov 12 06:41:18 2008 @@ -1121,9 +1121,9 @@ if (cmd.size() == 5) throw std::string("$ENV invocation: empty argument list!"); - ret += "std::getenv(\""; + ret += "checkCString(std::getenv(\""; ret += std::string(cmd.begin() + 5, cmd.begin() + cparen); - ret += "\")"; + ret += "\"))"; } else { throw "Unknown special command: " + cmd; @@ -1729,7 +1729,8 @@ << "static llvmc::RegisterPlugin RP;\n\n}\n\n"; } -/// EmitInclude - Emit necessary #include directives. +/// EmitIncludes - Emit necessary #include directives and some +/// additional declarations. void EmitIncludes(std::ostream& O) { O << "#include \"llvm/CompilerDriver/CompilationGraph.h\"\n" << "#include \"llvm/CompilerDriver/Plugin.h\"\n" @@ -1744,7 +1745,10 @@ << "using namespace llvm;\n" << "using namespace llvmc;\n\n" - << "extern cl::opt OutputFilename;\n\n"; + << "extern cl::opt OutputFilename;\n\n" + + << "inline const char* checkCString(const char* s)\n" + << "{ return s == NULL ? \"\" : s; }\n\n"; } // End of anonymous namespace From tonic at nondot.org Wed Nov 12 10:12:32 2008 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 12 Nov 2008 16:12:32 -0000 Subject: [llvm-commits] [llvm] r59142 - /llvm/trunk/test/FrontendC/2008-11-11-AnnotateStructFieldAttribute.c Message-ID: <200811121612.mACGCW4T001669@zion.cs.uiuc.edu> Author: tbrethou Date: Wed Nov 12 10:12:27 2008 New Revision: 59142 URL: http://llvm.org/viewvc/llvm-project?rev=59142&view=rev Log: Add test case for ptr annotation. Added: llvm/trunk/test/FrontendC/2008-11-11-AnnotateStructFieldAttribute.c Added: llvm/trunk/test/FrontendC/2008-11-11-AnnotateStructFieldAttribute.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2008-11-11-AnnotateStructFieldAttribute.c?rev=59142&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/2008-11-11-AnnotateStructFieldAttribute.c (added) +++ llvm/trunk/test/FrontendC/2008-11-11-AnnotateStructFieldAttribute.c Wed Nov 12 10:12:27 2008 @@ -0,0 +1,18 @@ +// RUN: %llvmgcc -c -emit-llvm %s -o - | llvm-dis | grep llvm.ptr.annotation | count 3 + +#include + +/* Struct with element X being annotated */ +struct foo { + int X __attribute__((annotate("StructAnnotation"))); + int Y; + int Z; +}; + + +void test(struct foo *F) { + F->X = 42; + F->Z = 1; + F->Y = F->X; +} + From gohman at apple.com Wed Nov 12 10:53:46 2008 From: gohman at apple.com (Dan Gohman) Date: Wed, 12 Nov 2008 16:53:46 -0000 Subject: [llvm-commits] [llvm] r59143 - /llvm/trunk/include/llvm/CodeGen/LiveInterval.h Message-ID: <200811121653.mACGrkGn004015@zion.cs.uiuc.edu> Author: djg Date: Wed Nov 12 10:53:40 2008 New Revision: 59143 URL: http://llvm.org/viewvc/llvm-project?rev=59143&view=rev Log: Correct a function name in a comment. Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=59143&r1=59142&r2=59143&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Wed Nov 12 10:53:40 2008 @@ -198,7 +198,7 @@ return VNI; } - /// addKillForValNum - Add a kill instruction index to the specified value + /// addKill - Add a kill instruction index to the specified value /// number. static void addKill(VNInfo *VNI, unsigned KillIdx) { SmallVector &kills = VNI->kills; From gohman at apple.com Wed Nov 12 11:02:38 2008 From: gohman at apple.com (Dan Gohman) Date: Wed, 12 Nov 2008 17:02:38 -0000 Subject: [llvm-commits] [llvm] r59145 - /llvm/trunk/include/llvm/CodeGen/LiveVariables.h Message-ID: <200811121702.mACH2fN4004456@zion.cs.uiuc.edu> Author: djg Date: Wed Nov 12 11:02:24 2008 New Revision: 59145 URL: http://llvm.org/viewvc/llvm-project?rev=59145&view=rev Log: Update VarInfo's comments to reflect the current code. LiveVar no longer records a unique defining instruction, and virtual registers may have multiple kills while still being defined and killed in the same block. Modified: llvm/trunk/include/llvm/CodeGen/LiveVariables.h Modified: llvm/trunk/include/llvm/CodeGen/LiveVariables.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveVariables.h?rev=59145&r1=59144&r2=59145&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveVariables.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveVariables.h Wed Nov 12 11:02:24 2008 @@ -47,20 +47,17 @@ /// VarInfo - This represents the regions where a virtual register is live in /// the program. We represent this with three different pieces of - /// information: the instruction that uniquely defines the value, the set of - /// blocks the instruction is live into and live out of, and the set of - /// non-phi instructions that are the last users of the value. + /// information: the set of blocks in which the instruction is live + /// throughout, the set of blocks in which the instruction is actually used, + /// and the set of non-phi instructions that are the last users of the value. /// - /// In the common case where a value is defined and killed in the same block, - /// There is one killing instruction, and AliveBlocks is empty. - /// - /// Otherwise, the value is live out of the block. If the value is live - /// across any blocks, these blocks are listed in AliveBlocks. Blocks where - /// the liveness range ends are not included in AliveBlocks, instead being - /// captured by the Kills set. In these blocks, the value is live into the - /// block (unless the value is defined and killed in the same block) and lives - /// until the specified instruction. Note that there cannot ever be a value - /// whose Kills set contains two instructions from the same basic block. + /// If the value is live throughout any blocks, these blocks are listed in + /// AliveBlocks. Blocks where the liveness range ends are not included in + /// AliveBlocks, instead being captured by the Kills set. In these blocks, + /// the value is live into the block (unless the value is defined and killed + /// in the same block) and lives until the specified instruction. Note that + /// there cannot ever be a value whose Kills set contains two instructions + /// from the same basic block. /// /// PHI nodes complicate things a bit. If a PHI node is the last user of a /// value in one of its predecessor blocks, it is not listed in the kills set, @@ -72,13 +69,13 @@ /// included). This is sensical because the value must be live to the end of /// the block, but is not live in any successor blocks. struct VarInfo { - /// AliveBlocks - Set of blocks of which this value is alive completely + /// AliveBlocks - Set of blocks in which this value is alive completely /// through. This is a bit set which uses the basic block number as an /// index. /// BitVector AliveBlocks; - /// UsedBlocks - Set of blocks of which this value is actually used. This + /// UsedBlocks - Set of blocks in which this value is actually used. This /// is a bit set which uses the basic block number as an index. BitVector UsedBlocks; From duncan.sands at math.u-psud.fr Wed Nov 12 11:05:32 2008 From: duncan.sands at math.u-psud.fr (Duncan Sands) Date: Wed, 12 Nov 2008 18:05:32 +0100 Subject: [llvm-commits] [llvm] r58964 - in /llvm/trunk: docs/LangRef.html lib/Bitcode/Reader/BitcodeReader.cpp lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp lib/Transforms/Scalar/InstructionCombining.cpp lib/VMCore/ConstantFold.cpp lib/VMCore/Instructions.cpp lib/VMCore/Verifier.cpp In-Reply-To: <200811100446.mAA4kN1Y027799@zion.cs.uiuc.edu> References: <200811100446.mAA4kN1Y027799@zion.cs.uiuc.edu> Message-ID: <200811121805.33109.duncan.sands@math.u-psud.fr> Hi Mon Ping, what do you think of this for splitting vector shuffle? I didn't bother trying to handle non-power-of-two vector sizes since that is (a) awkward in this setup, and (b) they are going away soon anyway thanks to widening. Ciao, Duncan. PS: I've attached the final function, since that may be easier to read. PPS: I didn't test it much but it seems to work! Index: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp =================================================================== --- llvm.orig/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 2008-11-12 11:18:51.000000000 +0100 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 2008-11-12 17:56:08.000000000 +0100 @@ -650,52 +650,110 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo, SDValue &Hi) { - // Build the low part. + // The low and high parts of the original input give four input vectors. + SDValue Inputs[4]; + GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]); + GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]); + MVT NewVT = Inputs[0].getValueType(); + unsigned NewElts = NewVT.getVectorNumElements(); + assert(NewVT == Inputs[1].getValueType() && + "Non power-of-two vectors not supported!"); + + // If Lo or Hi uses elements from at most two of the four input vectors, then + // express it as a vector shuffle of those two inputs. Otherwise extract the + // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR. SDValue Mask = N->getOperand(2); - SmallVector Ops; - MVT LoVT, HiVT; - GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); - MVT EltVT = LoVT.getVectorElementType(); - unsigned LoNumElts = LoVT.getVectorNumElements(); - unsigned NumElements = Mask.getNumOperands(); - - // Insert all of the elements from the input that are needed. We use - // buildvector of extractelement here because the input vectors will have - // to be legalized, so this makes the code simpler. - for (unsigned i = 0; i != LoNumElts; ++i) { - SDValue Arg = Mask.getOperand(i); - if (Arg.getOpcode() == ISD::UNDEF) { - Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); - } else { - unsigned Idx = cast(Mask.getOperand(i))->getZExtValue(); - SDValue InVec = N->getOperand(0); - if (Idx >= NumElements) { - InVec = N->getOperand(1); - Idx -= NumElements; + MVT IdxVT = Mask.getValueType().getVectorElementType(); + MVT EltVT = NewVT.getVectorElementType(); + SmallVector BuildOps; + SmallVector MaskOps; + for (unsigned High = 0; High < 2; ++High) { + SDValue &Output = High ? Hi : Lo; + + // Build a shuffle mask for the output, discovering on the fly which + // input vectors to use as shuffle operands (recorded in InputUsed). + // At the same time, accumulate the final vector elements in BuildOps, + // for use if building a suitable shuffle vector proves too hard. + unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered. + unsigned FirstMaskIdx = High * NewElts; + bool useBuildVector = false; + for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { + SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset); + if (Arg.getOpcode() == ISD::UNDEF) { + MaskOps.push_back(Arg); + BuildOps.push_back(DAG.getNode(ISD::UNDEF, EltVT)); + continue; } - Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec, - DAG.getIntPtrConstant(Idx))); + + // The mask element. This indexes into the input. + unsigned Idx = cast(Arg)->getZExtValue(); + // The input vector this mask element indexes into. + unsigned Input = Idx / NewElts; + + if (Input >= array_lengthof(Inputs)) { + // The mask element indexes off the end of the input! This is illegal + // but handle it anyway. + MaskOps.push_back(DAG.getNode(ISD::UNDEF, IdxVT)); + BuildOps.push_back(DAG.getNode(ISD::UNDEF, EltVT)); + continue; + } + + // Turn the index into an offset from the start of the input vector. + Idx -= Input * NewElts; + + // Extract the vector element by hand, and record it for later use. + BuildOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, + Inputs[Input], + DAG.getIntPtrConstant(Idx))); + + if (useBuildVector) + // The following logic is only needed when creating a new shuffle, so + // skip it for a small speedup if we won't be building a vector shuffle. + continue; + + // Find or create a shuffle vector operand to hold this input. + unsigned OpNo; + for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { + if (InputUsed[OpNo] == Input) { + // This input vector is already an operand. + break; + } else if (InputUsed[OpNo] == -1U) { + // Create a new operand for this input vector. + InputUsed[OpNo] = Input; + break; + } + } + + if (OpNo < array_lengthof(InputUsed)) + // Add the mask index for the new shuffle vector. + MaskOps.push_back(DAG.getConstant(Idx + OpNo * NewElts, IdxVT)); + else + // More than two input vectors used! Give up on trying to create a + // shuffle vector. Insert all elements into a BUILD_VECTOR instead. + useBuildVector = true; } - } - Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &Ops[0], Ops.size()); - Ops.clear(); - for (unsigned i = LoNumElts; i != NumElements; ++i) { - SDValue Arg = Mask.getOperand(i); - if (Arg.getOpcode() == ISD::UNDEF) { - Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); + if (useBuildVector) { + Output = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &BuildOps[0], + BuildOps.size()); + } else if (InputUsed[0] == -1U) { + // No input vectors were used! The result is undefined. + Output = DAG.getNode(ISD::UNDEF, NewVT); } else { - unsigned Idx = cast(Mask.getOperand(i))->getZExtValue(); - SDValue InVec = N->getOperand(0); - if (Idx >= NumElements) { - InVec = N->getOperand(1); - Idx -= NumElements; - } - Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec, - DAG.getIntPtrConstant(Idx))); + // At least one input vector was used. Create a new shuffle vector. + SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, + MVT::getVectorVT(IdxVT, MaskOps.size()), + &MaskOps[0], MaskOps.size()); + SDValue Op0 = Inputs[InputUsed[0]]; + // If only one input was used, use an undefined vector for the other. + SDValue Op1 = InputUsed[1] == -1U ? + DAG.getNode(ISD::UNDEF, NewVT) : Inputs[InputUsed[1]]; + Output = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, Op0, Op1, NewMask); } + + BuildOps.clear(); + MaskOps.clear(); } - Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size()); } void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo, -------------- next part -------------- void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo, SDValue &Hi) { // The low and high parts of the original input give four input vectors. SDValue Inputs[4]; GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]); GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]); MVT NewVT = Inputs[0].getValueType(); unsigned NewElts = NewVT.getVectorNumElements(); assert(NewVT == Inputs[1].getValueType() && "Non power-of-two vectors not supported!"); // If Lo or Hi uses elements from at most two of the four input vectors, then // express it as a vector shuffle of those two inputs. Otherwise extract the // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR. SDValue Mask = N->getOperand(2); MVT IdxVT = Mask.getValueType().getVectorElementType(); MVT EltVT = NewVT.getVectorElementType(); SmallVector BuildOps; SmallVector MaskOps; for (unsigned High = 0; High < 2; ++High) { SDValue &Output = High ? Hi : Lo; // Build a shuffle mask for the output, discovering on the fly which // input vectors to use as shuffle operands (recorded in InputUsed). // At the same time, accumulate the final vector elements in BuildOps, // for use if building a suitable shuffle vector proves too hard. unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered. unsigned FirstMaskIdx = High * NewElts; bool useBuildVector = false; for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset); if (Arg.getOpcode() == ISD::UNDEF) { MaskOps.push_back(Arg); BuildOps.push_back(DAG.getNode(ISD::UNDEF, EltVT)); continue; } // The mask element. This indexes into the input. unsigned Idx = cast(Arg)->getZExtValue(); // The input vector this mask element indexes into. unsigned Input = Idx / NewElts; if (Input >= array_lengthof(Inputs)) { // The mask element indexes off the end of the input! This is illegal // but handle it anyway. MaskOps.push_back(DAG.getNode(ISD::UNDEF, IdxVT)); BuildOps.push_back(DAG.getNode(ISD::UNDEF, EltVT)); continue; } // Turn the index into an offset from the start of the input vector. Idx -= Input * NewElts; // Extract the vector element by hand, and record it for later use. BuildOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Inputs[Input], DAG.getIntPtrConstant(Idx))); if (useBuildVector) // The following logic is only needed when creating a new shuffle, so // skip it for a small speedup if we won't be building a vector shuffle. continue; // Find or create a shuffle vector operand to hold this input. unsigned OpNo; for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { if (InputUsed[OpNo] == Input) { // This input vector is already an operand. break; } else if (InputUsed[OpNo] == -1U) { // Create a new operand for this input vector. InputUsed[OpNo] = Input; break; } } if (OpNo < array_lengthof(InputUsed)) // Add the mask index for the new shuffle vector. MaskOps.push_back(DAG.getConstant(Idx + OpNo * NewElts, IdxVT)); else // More than two input vectors used! Give up on trying to create a // shuffle vector. Insert all elements into a BUILD_VECTOR instead. useBuildVector = true; } if (useBuildVector) { Output = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &BuildOps[0], BuildOps.size()); } else if (InputUsed[0] == -1U) { // No input vectors were used! The result is undefined. Output = DAG.getNode(ISD::UNDEF, NewVT); } else { // At least one input vector was used. Create a new shuffle vector. SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::getVectorVT(IdxVT, MaskOps.size()), &MaskOps[0], MaskOps.size()); SDValue Op0 = Inputs[InputUsed[0]]; // If only one input was used, use an undefined vector for the other. SDValue Op1 = InputUsed[1] == -1U ? DAG.getNode(ISD::UNDEF, NewVT) : Inputs[InputUsed[1]]; Output = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, Op0, Op1, NewMask); } BuildOps.clear(); MaskOps.clear(); } } From gohman at apple.com Wed Nov 12 11:09:31 2008 From: gohman at apple.com (Dan Gohman) Date: Wed, 12 Nov 2008 17:09:31 -0000 Subject: [llvm-commits] [llvm] r59146 - /llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Message-ID: <200811121709.mACH9WKV004794@zion.cs.uiuc.edu> Author: djg Date: Wed Nov 12 11:09:23 2008 New Revision: 59146 URL: http://llvm.org/viewvc/llvm-project?rev=59146&view=rev Log: Remove some debugging code made redundant by the change to do coalescing as a separate pass rather than inside of LiveIntervalAnalysis. Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=59146&r1=59145&r2=59146&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Nov 12 11:09:23 2008 @@ -54,7 +54,6 @@ cl::init(false), cl::Hidden); STATISTIC(numIntervals, "Number of original intervals"); -STATISTIC(numIntervalsAfter, "Number of intervals after coalescing"); STATISTIC(numFolds , "Number of loads/stores folded into instructions"); STATISTIC(numSplits , "Number of intervals split"); @@ -260,13 +259,6 @@ numIntervals += getNumIntervals(); - DOUT << "********** INTERVALS **********\n"; - for (iterator I = begin(), E = end(); I != E; ++I) { - I->second->print(DOUT, tri_); - DOUT << "\n"; - } - - numIntervalsAfter += getNumIntervals(); DEBUG(dump()); return true; } From gohman at apple.com Wed Nov 12 11:15:30 2008 From: gohman at apple.com (Dan Gohman) Date: Wed, 12 Nov 2008 17:15:30 -0000 Subject: [llvm-commits] [llvm] r59147 - /llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Message-ID: <200811121715.mACHFWOc005099@zion.cs.uiuc.edu> Author: djg Date: Wed Nov 12 11:15:19 2008 New Revision: 59147 URL: http://llvm.org/viewvc/llvm-project?rev=59147&view=rev Log: Do the LiveVariables update before printing the instruction in the debug output, so that the updated liveness flags are reflected in the debug output. Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=59147&r1=59146&r2=59147&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original) +++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Wed Nov 12 11:15:19 2008 @@ -419,7 +419,6 @@ } MachineBasicBlock::iterator prevMi = prior(mi); - DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM)); // Update live variables for regB. if (LV) { @@ -434,6 +433,8 @@ if (LV->removeVirtualRegisterDead(regB, mi)) LV->addVirtualRegisterDead(regB, prevMi); } + + DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM)); // Replace all occurences of regB with regA. for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { From evan.cheng at apple.com Wed Nov 12 12:12:28 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Nov 2008 10:12:28 -0800 Subject: [llvm-commits] [llvm] r59145 - /llvm/trunk/include/llvm/CodeGen/LiveVariables.h In-Reply-To: <200811121702.mACH2fN4004456@zion.cs.uiuc.edu> References: <200811121702.mACH2fN4004456@zion.cs.uiuc.edu> Message-ID: On Nov 12, 2008, at 9:02 AM, Dan Gohman wrote: > Author: djg > Date: Wed Nov 12 11:02:24 2008 > New Revision: 59145 > > URL: http://llvm.org/viewvc/llvm-project?rev=59145&view=rev > Log: > Update VarInfo's comments to reflect the current code. LiveVar > no longer records a unique defining instruction, > and virtual > registers may have multiple kills while still being defined > and killed in the same block. Are you sure? Evan > > > Modified: > llvm/trunk/include/llvm/CodeGen/LiveVariables.h > > Modified: llvm/trunk/include/llvm/CodeGen/LiveVariables.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveVariables.h?rev=59145&r1=59144&r2=59145&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/CodeGen/LiveVariables.h (original) > +++ llvm/trunk/include/llvm/CodeGen/LiveVariables.h Wed Nov 12 > 11:02:24 2008 > @@ -47,20 +47,17 @@ > > /// VarInfo - This represents the regions where a virtual register > is live in > /// the program. We represent this with three different pieces of > - /// information: the instruction that uniquely defines the value, > the set of > - /// blocks the instruction is live into and live out of, and the > set of > - /// non-phi instructions that are the last users of the value. > + /// information: the set of blocks in which the instruction is live > + /// throughout, the set of blocks in which the instruction is > actually used, > + /// and the set of non-phi instructions that are the last users > of the value. > /// > - /// In the common case where a value is defined and killed in the > same block, > - /// There is one killing instruction, and AliveBlocks is empty. > - /// > - /// Otherwise, the value is live out of the block. If the value > is live > - /// across any blocks, these blocks are listed in AliveBlocks. > Blocks where > - /// the liveness range ends are not included in AliveBlocks, > instead being > - /// captured by the Kills set. In these blocks, the value is > live into the > - /// block (unless the value is defined and killed in the same > block) and lives > - /// until the specified instruction. Note that there cannot ever > be a value > - /// whose Kills set contains two instructions from the same basic > block. > + /// If the value is live throughout any blocks, these blocks are > listed in > + /// AliveBlocks. Blocks where the liveness range ends are not > included in > + /// AliveBlocks, instead being captured by the Kills set. In > these blocks, > + /// the value is live into the block (unless the value is defined > and killed > + /// in the same block) and lives until the specified > instruction. Note that > + /// there cannot ever be a value whose Kills set contains two > instructions > + /// from the same basic block. > /// > /// PHI nodes complicate things a bit. If a PHI node is the last > user of a > /// value in one of its predecessor blocks, it is not listed in > the kills set, > @@ -72,13 +69,13 @@ > /// included). This is sensical because the value must be live to > the end of > /// the block, but is not live in any successor blocks. > struct VarInfo { > - /// AliveBlocks - Set of blocks of which this value is alive > completely > + /// AliveBlocks - Set of blocks in which this value is alive > completely > /// through. This is a bit set which uses the basic block > number as an > /// index. > /// > BitVector AliveBlocks; > > - /// UsedBlocks - Set of blocks of which this value is actually > used. This > + /// UsedBlocks - Set of blocks in which this value is actually > used. This > /// is a bit set which uses the basic block number as an index. > BitVector UsedBlocks; > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dalej at apple.com Wed Nov 12 12:38:55 2008 From: dalej at apple.com (Dale Johannesen) Date: Wed, 12 Nov 2008 18:38:55 -0000 Subject: [llvm-commits] [llvm] r59150 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Message-ID: <200811121838.mACIcuBl008219@zion.cs.uiuc.edu> Author: johannes Date: Wed Nov 12 12:38:44 2008 New Revision: 59150 URL: http://llvm.org/viewvc/llvm-project?rev=59150&view=rev Log: Fix unsigned char->ppcf128 conversion. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=59150&r1=59149&r2=59150&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Wed Nov 12 12:38:44 2008 @@ -919,17 +919,22 @@ MVT NVT = TLI.getTypeToTransformTo(VT); SDValue Src = N->getOperand(0); MVT SrcVT = Src.getValueType(); + bool isSigned = N->getOpcode() == ISD::SINT_TO_FP; // First do an SINT_TO_FP, whether the original was signed or unsigned. + // When promoting partial word types to i32 we must honor the signedness, + // though. if (SrcVT.bitsLE(MVT::i32)) { // The integer can be represented exactly in an f64. - Src = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Src); + Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, + MVT::i32, Src); Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT); Hi = DAG.getNode(ISD::SINT_TO_FP, NVT, Src); } else { RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; if (SrcVT.bitsLE(MVT::i64)) { - Src = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Src); + Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, + MVT::i64, Src); LC = RTLIB::SINTTOFP_I64_PPCF128; } else if (SrcVT.bitsLE(MVT::i128)) { Src = DAG.getNode(ISD::SIGN_EXTEND, MVT::i128, Src); @@ -943,7 +948,7 @@ Lo = Hi.getOperand(0); Hi = Hi.getOperand(1); } - if (N->getOpcode() == ISD::SINT_TO_FP) + if (isSigned) return; // Unsigned - fix up the SINT_TO_FP value just calculated. From ofv at wanadoo.es Wed Nov 12 14:39:27 2008 From: ofv at wanadoo.es (Oscar Fuentes) Date: Wed, 12 Nov 2008 20:39:27 -0000 Subject: [llvm-commits] [llvm] r59158 - /llvm/trunk/utils/GenLibDeps.pl Message-ID: <200811122039.mACKdUxE013474@zion.cs.uiuc.edu> Author: ofv Date: Wed Nov 12 14:39:06 2008 New Revision: 59158 URL: http://llvm.org/viewvc/llvm-project?rev=59158&view=rev Log: Tell GenLibDeps.pl to inspect .so and .dylib shared files. Modified: llvm/trunk/utils/GenLibDeps.pl Modified: llvm/trunk/utils/GenLibDeps.pl URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/GenLibDeps.pl?rev=59158&r1=59157&r2=59158&view=diff ============================================================================== --- llvm/trunk/utils/GenLibDeps.pl (original) +++ llvm/trunk/utils/GenLibDeps.pl Wed Nov 12 14:39:06 2008 @@ -48,7 +48,7 @@ opendir DIR,$Directory; my @files = readdir DIR; closedir DIR; -my @libs = grep(/libLLVM.*\.a$/,sort(@files)); +my @libs = grep(/libLLVM.*\.(dylib|so|a)$/,sort(@files)); my @objs = grep(/LLVM.*\.o$/,sort(@files)); # Declare the hashes we will use to keep track of the library and object file From ofv at wanadoo.es Wed Nov 12 14:40:58 2008 From: ofv at wanadoo.es (Oscar Fuentes) Date: Wed, 12 Nov 2008 20:40:58 -0000 Subject: [llvm-commits] [llvm] r59159 - /llvm/trunk/lib/System/CMakeLists.txt Message-ID: <200811122040.mACKewxK013534@zion.cs.uiuc.edu> Author: ofv Date: Wed Nov 12 14:40:56 2008 New Revision: 59159 URL: http://llvm.org/viewvc/llvm-project?rev=59159&view=rev Log: CMake: when bulding shared libraries on non-WIN32 systems, link dl to LLVMSystem. Modified: llvm/trunk/lib/System/CMakeLists.txt Modified: llvm/trunk/lib/System/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/CMakeLists.txt?rev=59159&r1=59158&r2=59159&view=diff ============================================================================== --- llvm/trunk/lib/System/CMakeLists.txt (original) +++ llvm/trunk/lib/System/CMakeLists.txt Wed Nov 12 14:40:56 2008 @@ -12,3 +12,7 @@ Signals.cpp TimeValue.cpp ) + +if( BUILD_SHARED_LIBS AND NOT WIN32 ) + target_link_libraries(LLVMSystem dl) +endif() From kremenek at apple.com Wed Nov 12 15:19:03 2008 From: kremenek at apple.com (Ted Kremenek) Date: Wed, 12 Nov 2008 21:19:03 -0000 Subject: [llvm-commits] [llvm] r59164 - /llvm/tags/checker/checker-125/ Message-ID: <200811122119.mACLJ4C3015088@zion.cs.uiuc.edu> Author: kremenek Date: Wed Nov 12 15:18:53 2008 New Revision: 59164 URL: http://llvm.org/viewvc/llvm-project?rev=59164&view=rev Log: Tagging checker-125. Added: llvm/tags/checker/checker-125/ - copied from r59163, llvm/trunk/ From evan.cheng at apple.com Wed Nov 12 15:38:01 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Nov 2008 21:38:01 -0000 Subject: [llvm-commits] [llvm] r59170 - /llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp Message-ID: <200811122138.mACLc2QI016099@zion.cs.uiuc.edu> Author: evancheng Date: Wed Nov 12 15:37:59 2008 New Revision: 59170 URL: http://llvm.org/viewvc/llvm-project?rev=59170&view=rev Log: Remove the incorrect assertion. We don't have enough information before relocation to set U bit. Modified: llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp?rev=59170&r1=59169&r2=59170&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp Wed Nov 12 15:37:59 2008 @@ -246,8 +246,7 @@ *((intptr_t*)RelocPos) |= 1 << ARMII::U_BitShift; else { // Otherwise, obtain the absolute value and set bit U(23) to 0. - assert((*((intptr_t*)RelocPos) & (1 << ARMII::U_BitShift)) == 0 && - "U bit is not zero?"); + *((intptr_t*)RelocPos) &= ~(1 << ARMII::U_BitShift); ResultPtr = - ResultPtr; } // Set the immed value calculated. From kremenek at apple.com Wed Nov 12 15:48:57 2008 From: kremenek at apple.com (Ted Kremenek) Date: Wed, 12 Nov 2008 21:48:57 -0000 Subject: [llvm-commits] [llvm] r59171 - /llvm/tags/checker/checker-125/ Message-ID: <200811122148.mACLmvoT016599@zion.cs.uiuc.edu> Author: kremenek Date: Wed Nov 12 15:48:42 2008 New Revision: 59171 URL: http://llvm.org/viewvc/llvm-project?rev=59171&view=rev Log: Removing checker-125. Removed: llvm/tags/checker/checker-125/ From ggreif at gmail.com Wed Nov 12 15:58:30 2008 From: ggreif at gmail.com (Gabor Greif) Date: Wed, 12 Nov 2008 21:58:30 -0000 Subject: [llvm-commits] [llvm] r59175 - /llvm/branches/ggreif/son-of-use-diet_24/ Message-ID: <200811122158.mACLwVF9017272@zion.cs.uiuc.edu> Author: ggreif Date: Wed Nov 12 15:58:20 2008 New Revision: 59175 URL: http://llvm.org/viewvc/llvm-project?rev=59175&view=rev Log: branch for further memory footprint reductions Added: llvm/branches/ggreif/son-of-use-diet_24/ - copied from r59174, llvm/branches/release_24/ From kremenek at apple.com Wed Nov 12 15:59:19 2008 From: kremenek at apple.com (Ted Kremenek) Date: Wed, 12 Nov 2008 21:59:19 -0000 Subject: [llvm-commits] [llvm] r59177 - /llvm/tags/checker/checker-125/ Message-ID: <200811122159.mACLxJa9017335@zion.cs.uiuc.edu> Author: kremenek Date: Wed Nov 12 15:59:19 2008 New Revision: 59177 URL: http://llvm.org/viewvc/llvm-project?rev=59177&view=rev Log: Tagging checker-125. Added: llvm/tags/checker/checker-125/ - copied from r59176, llvm/trunk/ From scott.llvm at h4ck3r.net Wed Nov 12 12:06:36 2008 From: scott.llvm at h4ck3r.net (Scott Graham) Date: Wed, 12 Nov 2008 10:06:36 -0800 Subject: [llvm-commits] Include extern "C" ints to help registration global ctors Message-ID: <84decce20811121006k31b87095mf9b1577e32fc60c9@mail.gmail.com> Hi This patch adds extern "C" ints to the .cpp files that use RegisterTarget, as well as 2 files that use "Registrator"s. These are to be used by the MSVC builds (separate patch by ?scar), as the Win32 linker does not include libs that are otherwise unreferenced, even if global constructors in the lib have side-effects. It seems this list wants patches inline, not attached? Apologies if it's supposed to be the other way. scott Index: lib/Target/XCore/XCoreTargetMachine.cpp =================================================================== --- lib/Target/XCore/XCoreTargetMachine.cpp (revision 59091) +++ lib/Target/XCore/XCoreTargetMachine.cpp (working copy) @@ -18,6 +18,13 @@ #include "llvm/Target/TargetMachineRegistry.h" using namespace llvm; +/// XCoreTargetMachineModule - Note that this is used on hosts that cannot link +/// in a library unless there are references into the library. In particular, +/// it seems that it is not possible to get things to work on Win32 without +/// this. Though it is unused, do not remove it. +extern "C" int XCoreTargetMachineModule; +int XCoreTargetMachineModule = 0; + namespace { // Register the target. RegisterTarget X("xcore", " XCore"); Index: lib/Target/PIC16/PIC16TargetMachine.cpp =================================================================== --- lib/Target/PIC16/PIC16TargetMachine.cpp (revision 59091) +++ lib/Target/PIC16/PIC16TargetMachine.cpp (working copy) @@ -21,6 +21,13 @@ using namespace llvm; +/// PIC16TargetMachineModule - Note that this is used on hosts that cannot link +/// in a library unless there are references into the library. In particular, +/// it seems that it is not possible to get things to work on Win32 without +/// this. Though it is unused, do not remove it. +extern "C" int PIC16TargetMachineModule; +int PIC16TargetMachineModule = 0; + namespace { // Register the targets RegisterTarget X("pic16", "PIC16 14-bit [experimental]"); Index: lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp =================================================================== --- lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp (revision 59091) +++ lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp (working copy) @@ -41,3 +41,6 @@ } } Registrator; } + +extern "C" int X86AsmPrinterForceLink; +int X86AsmPrinterForceLink = 0; Index: lib/Target/CBackend/CBackend.cpp =================================================================== --- lib/Target/CBackend/CBackend.cpp (revision 59091) +++ lib/Target/CBackend/CBackend.cpp (working copy) @@ -48,6 +48,13 @@ #include using namespace llvm; +/// CBackendTargetMachineModule - Note that this is used on hosts that cannot link +/// in a library unless there are references into the library. In particular, +/// it seems that it is not possible to get things to work on Win32 without +/// this. Though it is unused, do not remove it. +extern "C" int CBackendTargetMachineModule; +int CBackendTargetMachineModule = 0; + // Register the target. static RegisterTarget X("c", "C backend"); Index: lib/Target/CellSPU/SPUTargetMachine.cpp =================================================================== --- lib/Target/CellSPU/SPUTargetMachine.cpp (revision 59091) +++ lib/Target/CellSPU/SPUTargetMachine.cpp (working copy) @@ -21,6 +21,13 @@ using namespace llvm; +/// CellSPUTargetMachineModule - Note that this is used on hosts that cannot link +/// in a library unless there are references into the library. In particular, +/// it seems that it is not possible to get things to work on Win32 without +/// this. Though it is unused, do not remove it. +extern "C" int CellSPUTargetMachineModule; +int CellSPUTargetMachineModule = 0; + namespace { // Register the targets RegisterTarget Index: lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp =================================================================== --- lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp (revision 59091) +++ lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp (working copy) @@ -1112,3 +1112,7 @@ } } Registrator; } + +extern "C" int PowerPCAsmPrinterForceLink; +int PowerPCAsmPrinterForceLink = 0; + Index: lib/Target/PowerPC/PPCTargetMachine.cpp =================================================================== --- lib/Target/PowerPC/PPCTargetMachine.cpp (revision 59091) +++ lib/Target/PowerPC/PPCTargetMachine.cpp (working copy) @@ -21,6 +21,13 @@ #include "llvm/Support/raw_ostream.h" using namespace llvm; +/// PowerPCTargetMachineModule - Note that this is used on hosts that cannot link +/// in a library unless there are references into the library. In particular, +/// it seems that it is not possible to get things to work on Win32 without +/// this. Though it is unused, do not remove it. +extern "C" int PowerPCTargetMachineModule; +int PowerPCTargetMachineModule = 0; + // Register the targets static RegisterTarget X("ppc32", "PowerPC 32"); Index: lib/Target/ARM/ARMTargetMachine.cpp =================================================================== --- lib/Target/ARM/ARMTargetMachine.cpp (revision 59091) +++ lib/Target/ARM/ARMTargetMachine.cpp (working copy) @@ -28,6 +28,13 @@ static cl::opt DisableIfConversion("disable-arm-if-conversion",cl::Hidden, cl::desc("Disable if-conversion pass")); +/// ARMTargetMachineModule - Note that this is used on hosts that cannot link +/// in a library unless there are references into the library. In particular, +/// it seems that it is not possible to get things to work on Win32 without +/// this. Though it is unused, do not remove it. +extern "C" int ARMTargetMachineModule; +int ARMTargetMachineModule = 0; + // Register the target. static RegisterTarget X("arm", "ARM"); static RegisterTarget Y("thumb", "Thumb"); Index: lib/Target/Alpha/AlphaTargetMachine.cpp =================================================================== --- lib/Target/Alpha/AlphaTargetMachine.cpp (revision 59091) +++ lib/Target/Alpha/AlphaTargetMachine.cpp (working copy) @@ -21,6 +21,13 @@ using namespace llvm; +/// AlphaTargetMachineModule - Note that this is used on hosts that cannot link +/// in a library unless there are references into the library. In particular, +/// it seems that it is not possible to get things to work on Win32 without +/// this. Though it is unused, do not remove it. +extern "C" int AlphaTargetMachineModule; +int AlphaTargetMachineModule = 0; + // Register the targets static RegisterTarget X("alpha", "Alpha [experimental]"); Index: lib/Target/CppBackend/CPPBackend.cpp =================================================================== --- lib/Target/CppBackend/CPPBackend.cpp (revision 59091) +++ lib/Target/CppBackend/CPPBackend.cpp (working copy) @@ -71,6 +71,13 @@ cl::desc("Specify the name of the thing to generate"), cl::init("!bad!")); +/// CppBackendTargetMachineModule - Note that this is used on hosts that cannot link +/// in a library unless there are references into the library. In particular, +/// it seems that it is not possible to get things to work on Win32 without +/// this. Though it is unused, do not remove it. +extern "C" int CppBackendTargetMachineModule; +int CppBackendTargetMachineModule = 0; + // Register the target. static RegisterTarget X("cpp", "C++ backend"); Index: lib/Target/MSIL/MSILWriter.cpp =================================================================== --- lib/Target/MSIL/MSILWriter.cpp (revision 59091) +++ lib/Target/MSIL/MSILWriter.cpp (working copy) @@ -44,6 +44,12 @@ }; } +/// MSILTargetMachineModule - Note that this is used on hosts that cannot link +/// in a library unless there are references into the library. In particular, +/// it seems that it is not possible to get things to work on Win32 without +/// this. Though it is unused, do not remove it. +extern "C" int MSILTargetMachineModule; +int MSILTargetMachineModule = 0; static RegisterTarget X("msil", "MSIL backend"); Index: lib/Target/Sparc/SparcTargetMachine.cpp =================================================================== --- lib/Target/Sparc/SparcTargetMachine.cpp (revision 59091) +++ lib/Target/Sparc/SparcTargetMachine.cpp (working copy) @@ -18,6 +18,13 @@ #include "llvm/Target/TargetMachineRegistry.h" using namespace llvm; +/// SparcTargetMachineModule - Note that this is used on hosts that cannot link +/// in a library unless there are references into the library. In particular, +/// it seems that it is not possible to get things to work on Win32 without +/// this. Though it is unused, do not remove it. +extern "C" int SparcTargetMachineModule; +int SparcTargetMachineModule = 0; + // Register the target. static RegisterTarget X("sparc", "SPARC"); Index: lib/Target/Mips/MipsTargetMachine.cpp =================================================================== --- lib/Target/Mips/MipsTargetMachine.cpp (revision 59091) +++ lib/Target/Mips/MipsTargetMachine.cpp (working copy) @@ -19,6 +19,13 @@ #include "llvm/Target/TargetMachineRegistry.h" using namespace llvm; +/// MipsTargetMachineModule - Note that this is used on hosts that cannot link +/// in a library unless there are references into the library. In particular, +/// it seems that it is not possible to get things to work on Win32 without +/// this. Though it is unused, do not remove it. +extern "C" int MipsTargetMachineModule; +int MipsTargetMachineModule = 0; + // Register the target. static RegisterTarget X("mips", "Mips"); static RegisterTarget Y("mipsel", "Mipsel"); From ggreif at gmail.com Wed Nov 12 16:51:38 2008 From: ggreif at gmail.com (Gabor Greif) Date: Wed, 12 Nov 2008 22:51:38 -0000 Subject: [llvm-commits] [llvm] r59189 - in /llvm/branches/ggreif/son-of-use-diet_24: include/llvm/Use.h include/llvm/Value.h lib/VMCore/Use.cpp lib/VMCore/Value.cpp lib/VMCore/getValue.cpp Message-ID: <200811122251.mACMphwF019683@zion.cs.uiuc.edu> Author: ggreif Date: Wed Nov 12 16:51:31 2008 New Revision: 59189 URL: http://llvm.org/viewvc/llvm-project?rev=59189&view=rev Log: merge -r56159:HEAD from branches/ggreif/use-diet Added: llvm/branches/ggreif/son-of-use-diet_24/lib/VMCore/getValue.cpp - copied unchanged from r59184, llvm/branches/ggreif/use-diet/lib/VMCore/getValue.cpp Modified: llvm/branches/ggreif/son-of-use-diet_24/include/llvm/Use.h llvm/branches/ggreif/son-of-use-diet_24/include/llvm/Value.h llvm/branches/ggreif/son-of-use-diet_24/lib/VMCore/Use.cpp llvm/branches/ggreif/son-of-use-diet_24/lib/VMCore/Value.cpp Modified: llvm/branches/ggreif/son-of-use-diet_24/include/llvm/Use.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/son-of-use-diet_24/include/llvm/Use.h?rev=59189&r1=59188&r2=59189&view=diff ============================================================================== --- llvm/branches/ggreif/son-of-use-diet_24/include/llvm/Use.h (original) +++ llvm/branches/ggreif/son-of-use-diet_24/include/llvm/Use.h Wed Nov 12 16:51:31 2008 @@ -66,7 +66,19 @@ // Use is here to make keeping the "use" list of a Value up-to-date really easy. // class Use { -private: + class UseWaymark; + friend class UseWaymark; + Value *getValue() const; + /// nilUse - returns a 'token' that marks the end of the def/use chain + static Use *nilUse(const Value *V) { + return addTag((Use*)V, fullStopTagN); + } + static bool isNil(Use *U) { return extractTag(U) == fullStopTagN; } + void showWaymarks() const; + static bool isStop(Use *U) { + return isStopTag(extractTag(U)); + } + /// init - specify Value and User /// @deprecated in 2.4, will be removed soon inline void init(Value *V, User *U); @@ -81,7 +93,7 @@ /// Destructor - Only for zap() inline ~Use() { - if (Val) removeFromList(); + if (Next != nilUse(0)) removeFromList(); } /// Default ctor - This leaves the Use completely uninitialized. The only thing @@ -91,11 +103,22 @@ enum PrevPtrTag { zeroDigitTag = noTag , oneDigitTag = tagOne , stopTag = tagTwo - , fullStopTag = tagThree }; + , fullStopTag = tagThree + , tagMask = tagThree }; + enum NextPtrTag { zeroDigitTagN = tagTwo + , oneDigitTagN = tagOne + , stopTagN = noTag + , fullStopTagN = tagThree + , tagMaskN = tagThree }; + + static bool isStopTag(NextPtrTag T) { + const bool P[4] = { true, false, false, true }; + return P[T]; + } public: - operator Value*() const { return Val; } - Value *get() const { return Val; } + operator Value*() const { return get(); } + inline Value *get() const; User *getUser() const; const Use* getImpliedUser() const; static Use *initTags(Use *Start, Use *Stop, ptrdiff_t Done = 0); @@ -108,31 +131,37 @@ return RHS; } const Use &operator=(const Use &RHS) { - set(RHS.Val); + set(RHS.get()); return *this; } - Value *operator->() { return Val; } - const Value *operator->() const { return Val; } + Value *operator->() { return get(); } + const Value *operator->() const { return get(); } - Use *getNext() const { return Next; } + Use *getNext() const { return extractTag(Next) == fullStopTagN + ? 0 + : stripTag(Next); } private: - Value *Val; Use *Next, **Prev; void setPrev(Use **NewPrev) { - Prev = transferTag(Prev, NewPrev); + Prev = transferTag(Prev, NewPrev); } void addToList(Use **List) { Next = *List; - if (Next) Next->setPrev(&Next); + Use *StrippedNext(getNext()); + if (StrippedNext) StrippedNext->setPrev(&Next); setPrev(List); *List = this; } void removeFromList() { - Use **StrippedPrev = stripTag(Prev); - *StrippedPrev = Next; - if (Next) Next->setPrev(StrippedPrev); + __builtin_prefetch(Next); + Use **StrippedPrev = stripTag(Prev); + Use *StrippedNext(getNext()); + *StrippedPrev = !isStop(Next) && isStop(*StrippedPrev) + ? stripTag(Next) + : Next; + if (StrippedNext) StrippedNext->setPrev(StrippedPrev); } friend class Value; @@ -161,7 +190,10 @@ typedef value_use_iterator _Self; Use *U; - explicit value_use_iterator(Use *u) : U(u) {} + explicit value_use_iterator(Use *u) : U(extractTag(u) + == Use::fullStopTagN + ? 0 + : stripTag(u)) {} friend class Value; public: typedef typename super::reference reference; @@ -178,11 +210,11 @@ } /// atEnd - return true if this iterator is equal to use_end() on the value. - bool atEnd() const { return U == 0; } + bool atEnd() const { return !U; } // Iterator traversal: forward iteration only _Self &operator++() { // Preincrement - assert(U && "Cannot increment end iterator!"); + assert(!atEnd() && "Cannot increment end iterator!"); U = U->getNext(); return *this; } @@ -192,7 +224,7 @@ // Retrieve a pointer to the current User. UserTy *operator*() const { - assert(U && "Cannot dereference end iterator!"); + assert(!atEnd() && "Cannot dereference end iterator!"); return U->getUser(); } @@ -206,6 +238,11 @@ unsigned getOperandNo() const; }; +Value *Use::get() const { + return fullStopTagN == extractTag(Next) + ? reinterpret_cast(stripTag(Next)) + : getValue(); +} template<> struct simplify_type > { typedef User* SimpleType; Modified: llvm/branches/ggreif/son-of-use-diet_24/include/llvm/Value.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/son-of-use-diet_24/include/llvm/Value.h?rev=59189&r1=59188&r2=59189&view=diff ============================================================================== --- llvm/branches/ggreif/son-of-use-diet_24/include/llvm/Value.h (original) +++ llvm/branches/ggreif/son-of-use-diet_24/include/llvm/Value.h Wed Nov 12 16:51:31 2008 @@ -138,7 +138,7 @@ typedef value_use_iterator use_iterator; typedef value_use_iterator use_const_iterator; - bool use_empty() const { return UseList == 0; } + bool use_empty() const { return Use::isNil(UseList); } use_iterator use_begin() { return use_iterator(UseList); } use_const_iterator use_begin() const { return use_const_iterator(UseList); } use_iterator use_end() { return use_iterator(0); } @@ -254,14 +254,14 @@ } void Use::init(Value *V, User *) { - Val = V; if (V) V->addUse(*this); + else Next = nilUse(0); } void Use::set(Value *V) { - if (Val) removeFromList(); - Val = V; + if (Next != nilUse(0)) removeFromList(); if (V) V->addUse(*this); + else Next = nilUse(0); } Modified: llvm/branches/ggreif/son-of-use-diet_24/lib/VMCore/Use.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/son-of-use-diet_24/lib/VMCore/Use.cpp?rev=59189&r1=59188&r2=59189&view=diff ============================================================================== --- llvm/branches/ggreif/son-of-use-diet_24/lib/VMCore/Use.cpp (original) +++ llvm/branches/ggreif/son-of-use-diet_24/lib/VMCore/Use.cpp Wed Nov 12 16:51:31 2008 @@ -20,27 +20,27 @@ //===----------------------------------------------------------------------===// void Use::swap(Use &RHS) { - Value *V1(Val); - Value *V2(RHS.Val); - if (V1 != V2) { - if (V1) { - removeFromList(); - } - - if (V2) { - RHS.removeFromList(); - Val = V2; - V2->addUse(*this); - } else { - Val = 0; - } + ptrdiff_t dist((char*)&RHS - (char*)this); - if (V1) { - RHS.Val = V1; - V1->addUse(RHS); - } else { - RHS.Val = 0; - } + if (dist) { + Use *valid1(stripTag(Next)); + Use *valid2(stripTag(RHS.Next)); + if (valid1 && valid2) { + bool real1(fullStopTagN != extractTag(Next)); + bool real2(fullStopTagN != extractTag(RHS.Next)); + (char*&)*stripTag(Prev) += dist; + (char*&)*stripTag(RHS.Prev) -= dist; + if (real1) + (char*&)valid1->Prev += dist; + if (real2) + (char*&)valid2->Prev -= dist; + } + + // swap the members + std::swap(Next, RHS.Next); + Use** Prev1 = transferTag(Prev, stripTag(RHS.Prev)); + RHS.Prev = transferTag(RHS.Prev, stripTag(Prev)); + Prev = Prev1; } } @@ -52,7 +52,7 @@ const Use *Current = this; while (true) { - unsigned Tag = extractTag((Current++)->Prev); + unsigned Tag = extractTag((Current++)->Prev); switch (Tag) { case zeroDigitTag: case oneDigitTag: @@ -62,7 +62,7 @@ ++Current; ptrdiff_t Offset = 1; while (true) { - unsigned Tag = extractTag(Current->Prev); + unsigned Tag = extractTag(Current->Prev); switch (Tag) { case zeroDigitTag: case oneDigitTag: @@ -89,7 +89,7 @@ ptrdiff_t Count = Done; while (Start != Stop) { --Stop; - Stop->Val = 0; + Stop->Next = nilUse(0); if (!Count) { Stop->Prev = reinterpret_cast(Done == 0 ? fullStopTag : stopTag); ++Done; Modified: llvm/branches/ggreif/son-of-use-diet_24/lib/VMCore/Value.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/son-of-use-diet_24/lib/VMCore/Value.cpp?rev=59189&r1=59188&r2=59189&view=diff ============================================================================== --- llvm/branches/ggreif/son-of-use-diet_24/lib/VMCore/Value.cpp (original) +++ llvm/branches/ggreif/son-of-use-diet_24/lib/VMCore/Value.cpp Wed Nov 12 16:51:31 2008 @@ -34,7 +34,7 @@ Value::Value(const Type *ty, unsigned scid) : SubclassID(scid), SubclassData(0), VTy(checkType(ty)), - UseList(0), Name(0) { + UseList(Use::nilUse(this)), Name(0) { if (isa(this) || isa(this)) assert((VTy->isFirstClassType() || VTy == Type::VoidTy || isa(ty) || VTy->getTypeID() == Type::StructTyID) && @@ -298,7 +298,7 @@ // void Value::uncheckedReplaceAllUsesWith(Value *New) { while (!use_empty()) { - Use &U = *UseList; + Use &U = *use_begin().U; // Must handle Constants specially, we cannot call replaceUsesOfWith on a // constant because they are uniqued. if (Constant *C = dyn_cast(U.getUser())) { From gohman at apple.com Wed Nov 12 16:55:32 2008 From: gohman at apple.com (Dan Gohman) Date: Wed, 12 Nov 2008 22:55:32 -0000 Subject: [llvm-commits] [llvm] r59190 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGISel.h lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp lib/Target/X86/CMakeLists.txt lib/Target/X86/X86.h lib/Target/X86/X86FloatingPointRegKill.cpp lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86TargetMachine.cpp Message-ID: <200811122255.mACMteua019813@zion.cs.uiuc.edu> Author: djg Date: Wed Nov 12 16:55:05 2008 New Revision: 59190 URL: http://llvm.org/viewvc/llvm-project?rev=59190&view=rev Log: Move the code that inserts X87 FP_REG_KILL instructions from a special-purpose hook to a new pass. Also, add check to see if any x87 virtual registers are used, to avoid doing any work in the common case that no x87 code is needed. Added: llvm/trunk/lib/Target/X86/X86FloatingPointRegKill.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/trunk/lib/Target/X86/CMakeLists.txt llvm/trunk/lib/Target/X86/X86.h llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=59190&r1=59189&r2=59190&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Wed Nov 12 16:55:05 2008 @@ -64,7 +64,6 @@ virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {} virtual void InstructionSelect() = 0; - virtual void InstructionSelectPostProcessing() {} void SelectRootInit() { DAGSize = CurDAG->AssignTopologicalOrder(); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=59190&r1=59189&r2=59190&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Nov 12 16:55:05 2008 @@ -840,9 +840,6 @@ void SelectionDAGISel::FinishBasicBlock() { - // Perform target specific isel post processing. - InstructionSelectPostProcessing(); - DOUT << "Target-post-processed machine code:\n"; DEBUG(BB->dump()); Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=59190&r1=59189&r2=59190&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/CMakeLists.txt Wed Nov 12 16:55:05 2008 @@ -16,6 +16,7 @@ X86CodeEmitter.cpp X86ELFWriterInfo.cpp X86FloatingPoint.cpp + X86FloatingPointRegKill.cpp X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86InstrInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=59190&r1=59189&r2=59190&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86.h (original) +++ llvm/trunk/lib/Target/X86/X86.h Wed Nov 12 16:55:05 2008 @@ -35,6 +35,11 @@ /// FunctionPass *createX86FloatingPointStackifierPass(); +/// createX87FPRegKillInserterPass - This function returns a pass which +/// inserts FP_REG_KILL instructions where needed. +/// +FunctionPass *createX87FPRegKillInserterPass(); + /// createX86CodePrinterPass - Returns a pass that prints the X86 /// assembly code for a MachineFunction to the given output stream, /// using the given target machine description. Added: llvm/trunk/lib/Target/X86/X86FloatingPointRegKill.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPointRegKill.cpp?rev=59190&view=auto ============================================================================== --- llvm/trunk/lib/Target/X86/X86FloatingPointRegKill.cpp (added) +++ llvm/trunk/lib/Target/X86/X86FloatingPointRegKill.cpp Wed Nov 12 16:55:05 2008 @@ -0,0 +1,139 @@ +//===-- X86FloatingPoint.cpp - FP_REG_KILL inserter -----------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the pass which inserts FP_REG_KILL instructions. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "x86-codegen" +#include "X86.h" +#include "X86InstrInfo.h" +#include "X86Subtarget.h" +#include "llvm/Instructions.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/Compiler.h" +#include "llvm/Support/CFG.h" +#include "llvm/ADT/Statistic.h" +using namespace llvm; + +STATISTIC(NumFPKill, "Number of FP_REG_KILL instructions added"); + +namespace { + struct VISIBILITY_HIDDEN FPRegKiller : public MachineFunctionPass { + static char ID; + FPRegKiller() : MachineFunctionPass(&ID) {} + + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addPreservedID(MachineLoopInfoID); + AU.addPreservedID(MachineDominatorsID); + MachineFunctionPass::getAnalysisUsage(AU); + } + + virtual bool runOnMachineFunction(MachineFunction &MF); + + virtual const char *getPassName() const { return "X86 FP_REG_KILL inserter"; } + }; + char FPRegKiller::ID = 0; +} + +FunctionPass *llvm::createX87FPRegKillInserterPass() { return new FPRegKiller(); } + +bool FPRegKiller::runOnMachineFunction(MachineFunction &MF) { + // If we are emitting FP stack code, scan the basic block to determine if this + // block defines any FP values. If so, put an FP_REG_KILL instruction before + // the terminator of the block. + + // Note that FP stack instructions are used in all modes for long double, + // so we always need to do this check. + // Also note that it's possible for an FP stack register to be live across + // an instruction that produces multiple basic blocks (SSE CMOV) so we + // must check all the generated basic blocks. + + // Scan all of the machine instructions in these MBBs, checking for FP + // stores. (RFP32 and RFP64 will not exist in SSE mode, but RFP80 might.) + + // Fast-path: If nothing is using the x87 registers, we don't need to do + // any scanning. + MachineRegisterInfo &MRI = MF.getRegInfo(); + if (MRI.getRegClassVirtRegs(X86::RFP80RegisterClass).empty() && + MRI.getRegClassVirtRegs(X86::RFP64RegisterClass).empty() && + MRI.getRegClassVirtRegs(X86::RFP32RegisterClass).empty()) + return false; + + bool Changed = false; + const X86Subtarget &Subtarget = MF.getTarget().getSubtarget(); + MachineFunction::iterator MBBI = MF.begin(); + MachineFunction::iterator EndMBB = MF.end(); + for (; MBBI != EndMBB; ++MBBI) { + MachineBasicBlock *MBB = MBBI; + + // If this block returns, ignore it. We don't want to insert an FP_REG_KILL + // before the return. + if (!MBB->empty()) { + MachineBasicBlock::iterator EndI = MBB->end(); + --EndI; + if (EndI->getDesc().isReturn()) + continue; + } + + bool ContainsFPCode = false; + for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); + !ContainsFPCode && I != E; ++I) { + if (I->getNumOperands() != 0 && I->getOperand(0).isReg()) { + const TargetRegisterClass *clas; + for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) { + if (I->getOperand(op).isReg() && I->getOperand(op).isDef() && + TargetRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) && + ((clas = MRI.getRegClass(I->getOperand(op).getReg())) == + X86::RFP32RegisterClass || + clas == X86::RFP64RegisterClass || + clas == X86::RFP80RegisterClass)) { + ContainsFPCode = true; + break; + } + } + } + } + // Check PHI nodes in successor blocks. These PHI's will be lowered to have + // a copy of the input value in this block. In SSE mode, we only care about + // 80-bit values. + if (!ContainsFPCode) { + // Final check, check LLVM BB's that are successors to the LLVM BB + // corresponding to BB for FP PHI nodes. + const BasicBlock *LLVMBB = MBB->getBasicBlock(); + const PHINode *PN; + for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB); + !ContainsFPCode && SI != E; ++SI) { + for (BasicBlock::const_iterator II = SI->begin(); + (PN = dyn_cast(II)); ++II) { + if (PN->getType()==Type::X86_FP80Ty || + (!Subtarget.hasSSE1() && PN->getType()->isFloatingPoint()) || + (!Subtarget.hasSSE2() && PN->getType()==Type::DoubleTy)) { + ContainsFPCode = true; + break; + } + } + } + } + // Finally, if we found any FP code, emit the FP_REG_KILL instruction. + if (ContainsFPCode) { + BuildMI(*MBB, MBBI->getFirstTerminator(), + MF.getTarget().getInstrInfo()->get(X86::FP_REG_KILL)); + ++NumFPKill; + Changed = true; + } + } + + return Changed; +} Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=59190&r1=59189&r2=59190&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Nov 12 16:55:05 2008 @@ -41,7 +41,6 @@ #include "llvm/ADT/Statistic.h" using namespace llvm; -STATISTIC(NumFPKill , "Number of FP_REG_KILL instructions added"); STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor"); //===----------------------------------------------------------------------===// @@ -140,10 +139,6 @@ /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. virtual void InstructionSelect(); - /// InstructionSelectPostProcessing - Post processing of selected and - /// scheduled basic blocks. - virtual void InstructionSelectPostProcessing(); - virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF); virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const; @@ -663,81 +658,6 @@ CurDAG->RemoveDeadNodes(); } -void X86DAGToDAGISel::InstructionSelectPostProcessing() { - // If we are emitting FP stack code, scan the basic block to determine if this - // block defines any FP values. If so, put an FP_REG_KILL instruction before - // the terminator of the block. - - // Note that FP stack instructions are used in all modes for long double, - // so we always need to do this check. - // Also note that it's possible for an FP stack register to be live across - // an instruction that produces multiple basic blocks (SSE CMOV) so we - // must check all the generated basic blocks. - - // Scan all of the machine instructions in these MBBs, checking for FP - // stores. (RFP32 and RFP64 will not exist in SSE mode, but RFP80 might.) - MachineFunction::iterator MBBI = CurBB; - MachineFunction::iterator EndMBB = BB; ++EndMBB; - for (; MBBI != EndMBB; ++MBBI) { - MachineBasicBlock *MBB = MBBI; - - // If this block returns, ignore it. We don't want to insert an FP_REG_KILL - // before the return. - if (!MBB->empty()) { - MachineBasicBlock::iterator EndI = MBB->end(); - --EndI; - if (EndI->getDesc().isReturn()) - continue; - } - - bool ContainsFPCode = false; - for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); - !ContainsFPCode && I != E; ++I) { - if (I->getNumOperands() != 0 && I->getOperand(0).isReg()) { - const TargetRegisterClass *clas; - for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) { - if (I->getOperand(op).isReg() && I->getOperand(op).isDef() && - TargetRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) && - ((clas = RegInfo->getRegClass(I->getOperand(0).getReg())) == - X86::RFP32RegisterClass || - clas == X86::RFP64RegisterClass || - clas == X86::RFP80RegisterClass)) { - ContainsFPCode = true; - break; - } - } - } - } - // Check PHI nodes in successor blocks. These PHI's will be lowered to have - // a copy of the input value in this block. In SSE mode, we only care about - // 80-bit values. - if (!ContainsFPCode) { - // Final check, check LLVM BB's that are successors to the LLVM BB - // corresponding to BB for FP PHI nodes. - const BasicBlock *LLVMBB = BB->getBasicBlock(); - const PHINode *PN; - for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB); - !ContainsFPCode && SI != E; ++SI) { - for (BasicBlock::const_iterator II = SI->begin(); - (PN = dyn_cast(II)); ++II) { - if (PN->getType()==Type::X86_FP80Ty || - (!Subtarget->hasSSE1() && PN->getType()->isFloatingPoint()) || - (!Subtarget->hasSSE2() && PN->getType()==Type::DoubleTy)) { - ContainsFPCode = true; - break; - } - } - } - } - // Finally, if we found any FP code, emit the FP_REG_KILL instruction. - if (ContainsFPCode) { - BuildMI(*MBB, MBBI->getFirstTerminator(), - TM.getInstrInfo()->get(X86::FP_REG_KILL)); - ++NumFPKill; - } - } -} - /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in /// the main function. void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB, Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=59190&r1=59189&r2=59190&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Wed Nov 12 16:55:05 2008 @@ -188,6 +188,9 @@ if (EnableFastISel) PM.add(createDeadMachineInstructionElimPass()); + // Install a pass to insert x87 FP_REG_KILL instructions, as needed. + PM.add(createX87FPRegKillInserterPass()); + return false; } From gohman at apple.com Wed Nov 12 17:24:22 2008 From: gohman at apple.com (Dan Gohman) Date: Wed, 12 Nov 2008 23:24:22 -0000 Subject: [llvm-commits] [llvm] r59194 - /llvm/trunk/include/llvm/CodeGen/LiveVariables.h Message-ID: <200811122324.mACNOPJM020821@zion.cs.uiuc.edu> Author: djg Date: Wed Nov 12 17:24:15 2008 New Revision: 59194 URL: http://llvm.org/viewvc/llvm-project?rev=59194&view=rev Log: Revert the part of r59145 that changed the comment about virtual registers possibly having multiple kills while still being defined and killed in the same block. If LiveIntervals is manually re-run after two-address lowering, it currently does add extra kills to two-address instructions, but this is considered a bug. Modified: llvm/trunk/include/llvm/CodeGen/LiveVariables.h Modified: llvm/trunk/include/llvm/CodeGen/LiveVariables.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveVariables.h?rev=59194&r1=59193&r2=59194&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveVariables.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveVariables.h Wed Nov 12 17:24:15 2008 @@ -51,13 +51,16 @@ /// throughout, the set of blocks in which the instruction is actually used, /// and the set of non-phi instructions that are the last users of the value. /// - /// If the value is live throughout any blocks, these blocks are listed in - /// AliveBlocks. Blocks where the liveness range ends are not included in - /// AliveBlocks, instead being captured by the Kills set. In these blocks, - /// the value is live into the block (unless the value is defined and killed - /// in the same block) and lives until the specified instruction. Note that - /// there cannot ever be a value whose Kills set contains two instructions - /// from the same basic block. + /// In the common case where a value is defined and killed in the same block, + /// There is one killing instruction, and AliveBlocks is empty. + /// + /// Otherwise, the value is live out of the block. If the value is live + /// throughout any blocks, these blocks are listed in AliveBlocks. Blocks + /// where the liveness range ends are not included in AliveBlocks, instead + /// being captured by the Kills set. In these blocks, the value is live into + /// the block (unless the value is defined and killed in the same block) and + /// lives until the specified instruction. Note that there cannot ever be a + /// value whose Kills set contains two instructions from the same basic block. /// /// PHI nodes complicate things a bit. If a PHI node is the last user of a /// value in one of its predecessor blocks, it is not listed in the kills set, From wangmp at apple.com Wed Nov 12 17:59:33 2008 From: wangmp at apple.com (Mon Ping Wang) Date: Wed, 12 Nov 2008 15:59:33 -0800 Subject: [llvm-commits] [llvm] r58964 - in /llvm/trunk: docs/LangRef.html lib/Bitcode/Reader/BitcodeReader.cpp lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp lib/Transforms/Scalar/InstructionCombining.cpp lib/VMCore/ConstantFold.cpp lib/VMCore/Instructions.cpp lib/VMCore/Verifier.cpp In-Reply-To: <200811121805.33109.duncan.sands@math.u-psud.fr> References: <200811100446.mAA4kN1Y027799@zion.cs.uiuc.edu> <200811121805.33109.duncan.sands@math.u-psud.fr> Message-ID: <5709F358-C4B9-45B0-AC88-0590CD4553FF@apple.com> Hi Duncan, I like this implementation in general and you capture a case that I missed (in avoid using build vector) :-> . In my thinking (which is why I went more for a prescan methodology), the typical case is when we can use split vectors for the new shuffle. So pre splitting the vectors seems fine as we will using some of the result of the presplit in the vector shuffle. I don't particular like prebuilding the BuildOps though because we build a set of extract element nodes that we will typically throw away. It seems a little cleaner to me to iterate through the mask again and build these nodes when we need them. What do you think? Cheers, -- Mon Ping On Nov 12, 2008, at 9:05 AM, Duncan Sands wrote: > Hi Mon Ping, what do you think of this for splitting > vector shuffle? I didn't bother trying to handle > non-power-of-two vector sizes since that is (a) awkward > in this setup, and (b) they are going away soon anyway > thanks to widening. > > Ciao, > > Duncan. > > PS: I've attached the final function, since that may > be easier to read. > PPS: I didn't test it much but it seems to work! > > Index: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp > =================================================================== > --- llvm.orig/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp > 2008-11-12 11:18:51.000000000 +0100 > +++ llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 2008-11-12 > 17:56:08.000000000 +0100 > @@ -650,52 +650,110 @@ > > void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue > &Lo, > SDValue &Hi) { > - // Build the low part. > + // The low and high parts of the original input give four input > vectors. > + SDValue Inputs[4]; > + GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]); > + GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]); > + MVT NewVT = Inputs[0].getValueType(); > + unsigned NewElts = NewVT.getVectorNumElements(); > + assert(NewVT == Inputs[1].getValueType() && > + "Non power-of-two vectors not supported!"); > + > + // If Lo or Hi uses elements from at most two of the four input > vectors, then > + // express it as a vector shuffle of those two inputs. Otherwise > extract the > + // input elements by hand and construct the Lo/Hi output using a > BUILD_VECTOR. > SDValue Mask = N->getOperand(2); > - SmallVector Ops; > - MVT LoVT, HiVT; > - GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); > - MVT EltVT = LoVT.getVectorElementType(); > - unsigned LoNumElts = LoVT.getVectorNumElements(); > - unsigned NumElements = Mask.getNumOperands(); > - > - // Insert all of the elements from the input that are needed. We > use > - // buildvector of extractelement here because the input vectors > will have > - // to be legalized, so this makes the code simpler. > - for (unsigned i = 0; i != LoNumElts; ++i) { > - SDValue Arg = Mask.getOperand(i); > - if (Arg.getOpcode() == ISD::UNDEF) { > - Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); > - } else { > - unsigned Idx = cast(Mask.getOperand(i))- > >getZExtValue(); > - SDValue InVec = N->getOperand(0); > - if (Idx >= NumElements) { > - InVec = N->getOperand(1); > - Idx -= NumElements; > + MVT IdxVT = Mask.getValueType().getVectorElementType(); > + MVT EltVT = NewVT.getVectorElementType(); > + SmallVector BuildOps; > + SmallVector MaskOps; > + for (unsigned High = 0; High < 2; ++High) { > + SDValue &Output = High ? Hi : Lo; > + > + // Build a shuffle mask for the output, discovering on the fly > which > + // input vectors to use as shuffle operands (recorded in > InputUsed). > + // At the same time, accumulate the final vector elements in > BuildOps, > + // for use if building a suitable shuffle vector proves too hard. > + unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered. > + unsigned FirstMaskIdx = High * NewElts; > + bool useBuildVector = false; > + for (unsigned MaskOffset = 0; MaskOffset < NewElts; + > +MaskOffset) { > + SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset); > + if (Arg.getOpcode() == ISD::UNDEF) { > + MaskOps.push_back(Arg); > + BuildOps.push_back(DAG.getNode(ISD::UNDEF, EltVT)); > + continue; > } > - Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, > InVec, > - DAG.getIntPtrConstant(Idx))); > + > + // The mask element. This indexes into the input. > + unsigned Idx = cast(Arg)->getZExtValue(); > + // The input vector this mask element indexes into. > + unsigned Input = Idx / NewElts; > + > + if (Input >= array_lengthof(Inputs)) { > + // The mask element indexes off the end of the input! This > is illegal > + // but handle it anyway. > + MaskOps.push_back(DAG.getNode(ISD::UNDEF, IdxVT)); > + BuildOps.push_back(DAG.getNode(ISD::UNDEF, EltVT)); > + continue; > + } > + > + // Turn the index into an offset from the start of the input > vector. > + Idx -= Input * NewElts; > + > + // Extract the vector element by hand, and record it for > later use. > + BuildOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, > + Inputs[Input], > + DAG.getIntPtrConstant(Idx))); > + > + if (useBuildVector) > + // The following logic is only needed when creating a new > shuffle, so > + // skip it for a small speedup if we won't be building a > vector shuffle. > + continue; > + > + // Find or create a shuffle vector operand to hold this input. > + unsigned OpNo; > + for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { > + if (InputUsed[OpNo] == Input) { > + // This input vector is already an operand. > + break; > + } else if (InputUsed[OpNo] == -1U) { > + // Create a new operand for this input vector. > + InputUsed[OpNo] = Input; > + break; > + } > + } > + > + if (OpNo < array_lengthof(InputUsed)) > + // Add the mask index for the new shuffle vector. > + MaskOps.push_back(DAG.getConstant(Idx + OpNo * NewElts, > IdxVT)); > + else > + // More than two input vectors used! Give up on trying to > create a > + // shuffle vector. Insert all elements into a BUILD_VECTOR > instead. > + useBuildVector = true; > } > - } > - Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &Ops[0], Ops.size()); > - Ops.clear(); > > - for (unsigned i = LoNumElts; i != NumElements; ++i) { > - SDValue Arg = Mask.getOperand(i); > - if (Arg.getOpcode() == ISD::UNDEF) { > - Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); > + if (useBuildVector) { > + Output = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &BuildOps[0], > + BuildOps.size()); > + } else if (InputUsed[0] == -1U) { > + // No input vectors were used! The result is undefined. > + Output = DAG.getNode(ISD::UNDEF, NewVT); > } else { > - unsigned Idx = cast(Mask.getOperand(i))- > >getZExtValue(); > - SDValue InVec = N->getOperand(0); > - if (Idx >= NumElements) { > - InVec = N->getOperand(1); > - Idx -= NumElements; > - } > - Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, > InVec, > - DAG.getIntPtrConstant(Idx))); > + // At least one input vector was used. Create a new shuffle > vector. > + SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, > + MVT::getVectorVT(IdxVT, > MaskOps.size()), > + &MaskOps[0], MaskOps.size()); > + SDValue Op0 = Inputs[InputUsed[0]]; > + // If only one input was used, use an undefined vector for > the other. > + SDValue Op1 = InputUsed[1] == -1U ? > + DAG.getNode(ISD::UNDEF, NewVT) : Inputs[InputUsed[1]]; > + Output = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, Op0, Op1, > NewMask); > } > + > + BuildOps.clear(); > + MaskOps.clear(); > } > - Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size()); > } > > void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo, > From kremenek at apple.com Wed Nov 12 18:09:24 2008 From: kremenek at apple.com (Ted Kremenek) Date: Thu, 13 Nov 2008 00:09:24 -0000 Subject: [llvm-commits] [llvm] r59198 - /llvm/tags/checker/checker-126/ Message-ID: <200811130009.mAD09OBY022297@zion.cs.uiuc.edu> Author: kremenek Date: Wed Nov 12 18:09:10 2008 New Revision: 59198 URL: http://llvm.org/viewvc/llvm-project?rev=59198&view=rev Log: Tagging checker-126. Added: llvm/tags/checker/checker-126/ - copied from r59197, llvm/trunk/ From isanbard at gmail.com Wed Nov 12 18:47:37 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 13 Nov 2008 00:47:37 -0000 Subject: [llvm-commits] [test-suite] r59200 - /test-suite/trunk/Makefile.programs Message-ID: <200811130047.mAD0lfos023609@zion.cs.uiuc.edu> Author: void Date: Wed Nov 12 18:47:24 2008 New Revision: 59200 URL: http://llvm.org/viewvc/llvm-project?rev=59200&view=rev Log: Finish stack protector beta testing. Modified: test-suite/trunk/Makefile.programs Modified: test-suite/trunk/Makefile.programs URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=59200&r1=59199&r2=59200&view=diff ============================================================================== --- test-suite/trunk/Makefile.programs (original) +++ test-suite/trunk/Makefile.programs Wed Nov 12 18:47:24 2008 @@ -231,11 +231,7 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86) -ifeq ($(OS),Darwin) -LLCBETAOPTION := -enable-stack-protector=all -else LLCBETAOPTION := -fast-isel -endif #-fast-isel #-aggressive-remat #-machine-licm From isanbard at gmail.com Wed Nov 12 19:02:19 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 13 Nov 2008 01:02:19 -0000 Subject: [llvm-commits] [llvm] r59202 - in /llvm/trunk: include/llvm/Attributes.h include/llvm/CodeGen/Passes.h lib/AsmParser/LLLexer.cpp lib/AsmParser/llvmAsmParser.y lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/StackProtector.cpp lib/VMCore/Attributes.cpp Message-ID: <200811130102.mAD12KwL024185@zion.cs.uiuc.edu> Author: void Date: Wed Nov 12 19:02:14 2008 New Revision: 59202 URL: http://llvm.org/viewvc/llvm-project?rev=59202&view=rev Log: Implement stack protectors as function attributes: "ssp" and "sspreq". Modified: llvm/trunk/include/llvm/Attributes.h llvm/trunk/include/llvm/CodeGen/Passes.h llvm/trunk/lib/AsmParser/LLLexer.cpp llvm/trunk/lib/AsmParser/llvmAsmParser.y llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp llvm/trunk/lib/CodeGen/StackProtector.cpp llvm/trunk/lib/VMCore/Attributes.cpp Modified: llvm/trunk/include/llvm/Attributes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Attributes.h?rev=59202&r1=59201&r2=59202&view=diff ============================================================================== --- llvm/trunk/include/llvm/Attributes.h (original) +++ llvm/trunk/include/llvm/Attributes.h Wed Nov 12 19:02:14 2008 @@ -47,6 +47,8 @@ const Attributes NoInline = 1<<11; // inline=never const Attributes AlwaysInline = 1<<12; // inline=always const Attributes OptimizeForSize = 1<<13; // opt_size +const Attributes StackProtect = 1<<14; // Stack protection. +const Attributes StackProtectReq = 1<<15; // Stack protection required. const Attributes Alignment = 0xffff<<16; ///< Alignment of parameter (16 bits) // 0 = unknown, else in clear (not log) @@ -55,7 +57,7 @@ /// @brief Attributes that only apply to function. const Attributes FunctionOnly = NoReturn | NoUnwind | ReadNone | ReadOnly | - NoInline | AlwaysInline | OptimizeForSize; + NoInline | AlwaysInline | OptimizeForSize | StackProtect | StackProtectReq; /// @brief Parameter attributes that do not apply to vararg call arguments. const Attributes VarArgsIncompatible = StructRet; Modified: llvm/trunk/include/llvm/CodeGen/Passes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=59202&r1=59201&r2=59202&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/Passes.h (original) +++ llvm/trunk/include/llvm/CodeGen/Passes.h Wed Nov 12 19:02:14 2008 @@ -26,16 +26,6 @@ class TargetLowering; class RegisterCoalescer; - /// StackProtectorLevel - An enumeration for when to determin when to turn - /// stack smashing protection (SSP) on. - namespace SSP { - enum StackProtectorLevel { - OFF, // Stack protectors are off. - SOME, // Stack protectors on only for functions that require them. - ALL // Stack protectors on for all functions. - }; - } // end SSP namespace - /// createUnreachableBlockEliminationPass - The LLVM code generator does not /// work well with unreachable basic blocks (what live ranges make sense for a /// block that cannot be reached?). As such, a code generator should either @@ -204,8 +194,7 @@ FunctionPass *createStackSlotColoringPass(); /// createStackProtectorPass - This pass adds stack protectors to functions. - FunctionPass *createStackProtectorPass(SSP::StackProtectorLevel lvl, - const TargetLowering *tli); + FunctionPass *createStackProtectorPass(const TargetLowering *tli); } // End llvm namespace Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=59202&r1=59201&r2=59202&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLLexer.cpp (original) +++ llvm/trunk/lib/AsmParser/LLLexer.cpp Wed Nov 12 19:02:14 2008 @@ -499,6 +499,8 @@ KEYWORD("noinline", NOINLINE); KEYWORD("alwaysinline", ALWAYSINLINE); KEYWORD("optsize", OPTSIZE); + KEYWORD("ssp", SSP); + KEYWORD("sspreq", SSPREQ); KEYWORD("type", TYPE); KEYWORD("opaque", OPAQUE); Modified: llvm/trunk/lib/AsmParser/llvmAsmParser.y URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/llvmAsmParser.y?rev=59202&r1=59201&r2=59202&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/llvmAsmParser.y (original) +++ llvm/trunk/lib/AsmParser/llvmAsmParser.y Wed Nov 12 19:02:14 2008 @@ -1137,7 +1137,7 @@ // Function Attributes %token SIGNEXT ZEROEXT NORETURN INREG SRET NOUNWIND NOALIAS BYVAL NEST -%token READNONE READONLY GC OPTSIZE NOINLINE ALWAYSINLINE +%token READNONE READONLY GC OPTSIZE NOINLINE ALWAYSINLINE SSP SSPREQ // Visibility Styles %token DEFAULT HIDDEN PROTECTED @@ -1305,7 +1305,9 @@ | READONLY { $$ = Attribute::ReadOnly; } | NOINLINE { $$ = Attribute::NoInline; } | ALWAYSINLINE { $$ = Attribute::AlwaysInline; } - | OPTSIZE { $$ = Attribute::OptimizeForSize; } + | OPTSIZE { $$ = Attribute::OptimizeForSize; } + | SSP { $$ = Attribute::StackProtect; } + | SSPREQ { $$ = Attribute::StackProtectReq; } ; OptFuncAttrs : /* empty */ { $$ = Attribute::None; } Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=59202&r1=59201&r2=59202&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Nov 12 19:02:14 2008 @@ -60,19 +60,6 @@ EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the experimental \"fast\" instruction selector")); -// Enable stack protectors. -static cl::opt -EnableStackProtector("enable-stack-protector", - cl::desc("Stack canary protection level: (default: off)"), - cl::init(SSP::OFF), - cl::values(clEnumValN(SSP::ALL, "all", - "All functions get stack protectors."), - clEnumValN(SSP::SOME, "some", - "Only functions requiring stack protectors get them."), - clEnumValN(SSP::OFF, "off", - "No functions get stack protectors."), - clEnumValEnd)); - FileModel::Model LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, raw_ostream &Out, @@ -178,8 +165,7 @@ if (!Fast) PM.add(createCodeGenPreparePass(getTargetLowering())); - if (EnableStackProtector != SSP::OFF) - PM.add(createStackProtectorPass(EnableStackProtector, getTargetLowering())); + PM.add(createStackProtectorPass(getTargetLowering())); if (PrintISelInput) PM.add(createPrintFunctionPass("\n\n" Modified: llvm/trunk/lib/CodeGen/StackProtector.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackProtector.cpp?rev=59202&r1=59201&r2=59202&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/StackProtector.cpp (original) +++ llvm/trunk/lib/CodeGen/StackProtector.cpp Wed Nov 12 19:02:14 2008 @@ -16,6 +16,7 @@ #define DEBUG_TYPE "stack-protector" #include "llvm/CodeGen/Passes.h" +#include "llvm/Attributes.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Function.h" @@ -37,9 +38,6 @@ namespace { class VISIBILITY_HIDDEN StackProtector : public FunctionPass { - /// Level - The level of stack protection. - SSP::StackProtectorLevel Level; - /// TLI - Keep a pointer of a TargetLowering to consult for determining /// target type sizes. const TargetLowering *TLI; @@ -64,9 +62,9 @@ bool RequiresStackProtector() const; public: static char ID; // Pass identification, replacement for typeid. - StackProtector() : FunctionPass(&ID), Level(SSP::OFF), TLI(0) {} - StackProtector(SSP::StackProtectorLevel lvl, const TargetLowering *tli) - : FunctionPass(&ID), Level(lvl), TLI(tli) {} + StackProtector() : FunctionPass(&ID), TLI(0) {} + StackProtector(const TargetLowering *tli) + : FunctionPass(&ID), TLI(tli) {} virtual bool runOnFunction(Function &Fn); }; @@ -76,9 +74,8 @@ static RegisterPass X("stack-protector", "Insert stack protectors"); -FunctionPass *llvm::createStackProtectorPass(SSP::StackProtectorLevel lvl, - const TargetLowering *tli) { - return new StackProtector(lvl, tli); +FunctionPass *llvm::createStackProtectorPass(const TargetLowering *tli) { + return new StackProtector(tli); } bool StackProtector::runOnFunction(Function &Fn) { @@ -193,10 +190,10 @@ /// add a guard variable to functions that call alloca, and functions with /// buffers larger than 8 bytes. bool StackProtector::RequiresStackProtector() const { - switch (Level) { - default: return false; - case SSP::ALL: return true; - case SSP::SOME: { + if (F->hasFnAttr(Attribute::StackProtectReq)) + return true; + + if (F->hasFnAttr(Attribute::StackProtect)) { const TargetData *TD = TLI->getTargetData(); for (Function::iterator I = F->begin(), E = F->end(); I != E; ++I) { @@ -220,5 +217,6 @@ return false; } - } + + return false; } Modified: llvm/trunk/lib/VMCore/Attributes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Attributes.cpp?rev=59202&r1=59201&r2=59202&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Attributes.cpp (original) +++ llvm/trunk/lib/VMCore/Attributes.cpp Wed Nov 12 19:02:14 2008 @@ -53,6 +53,10 @@ Result += "noinline "; if (Attrs & Attribute::AlwaysInline) Result += "alwaysinline "; + if (Attrs & Attribute::StackProtect) + Result += "ssp "; + if (Attrs & Attribute::StackProtectReq) + Result += "sspreq "; if (Attrs & Attribute::Alignment) { Result += "align "; Result += utostr((Attrs & Attribute::Alignment) >> 16); From isanbard at gmail.com Wed Nov 12 19:02:52 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 13 Nov 2008 01:02:52 -0000 Subject: [llvm-commits] [llvm] r59203 - /llvm/trunk/docs/LangRef.html Message-ID: <200811130102.mAD12qpO024221@zion.cs.uiuc.edu> Author: void Date: Wed Nov 12 19:02:51 2008 New Revision: 59203 URL: http://llvm.org/viewvc/llvm-project?rev=59203&view=rev Log: Update docs for ssp and sspreq function attributes. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=59203&r1=59202&r2=59203&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Wed Nov 12 19:02:51 2008 @@ -985,6 +985,18 @@ be set in the caller. A readonly function always returns the same value (or throws the same exception) when called with the same set of arguments and global state. + +
ssp
+
This attribute indicates that the function should emit a stack smashing +protector. It is in the form of a "canary"—a random value placed on the +stack before the local variables that's checked upon return from the function to +see if it has been overwritten. A heuristic is used to determine if a function +needs stack protectors or not.
+ +
ssp-req
+
This attribute indicates that the function should always emit a +stack smashing protector. This overrides the ssp +function attribute.

From isanbard at gmail.com Wed Nov 12 19:03:00 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 13 Nov 2008 01:03:00 -0000 Subject: [llvm-commits] [llvm] r59204 - in /llvm/trunk/lib/AsmParser: llvmAsmParser.cpp.cvs llvmAsmParser.h.cvs llvmAsmParser.y.cvs Message-ID: <200811130103.mAD130TU024240@zion.cs.uiuc.edu> Author: void Date: Wed Nov 12 19:03:00 2008 New Revision: 59204 URL: http://llvm.org/viewvc/llvm-project?rev=59204&view=rev Log: Regenerated Modified: llvm/trunk/lib/AsmParser/llvmAsmParser.cpp.cvs llvm/trunk/lib/AsmParser/llvmAsmParser.h.cvs llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs Modified: llvm/trunk/lib/AsmParser/llvmAsmParser.cpp.cvs URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/llvmAsmParser.cpp.cvs?rev=59204&r1=59203&r2=59204&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/llvmAsmParser.cpp.cvs (original) +++ llvm/trunk/lib/AsmParser/llvmAsmParser.cpp.cvs Wed Nov 12 19:03:00 2008 @@ -227,9 +227,11 @@ OPTSIZE = 408, NOINLINE = 409, ALWAYSINLINE = 410, - DEFAULT = 411, - HIDDEN = 412, - PROTECTED = 413 + SSP = 411, + SSPREQ = 412, + DEFAULT = 413, + HIDDEN = 414, + PROTECTED = 415 }; #endif /* Tokens. */ @@ -386,15 +388,17 @@ #define OPTSIZE 408 #define NOINLINE 409 #define ALWAYSINLINE 410 -#define DEFAULT 411 -#define HIDDEN 412 -#define PROTECTED 413 +#define SSP 411 +#define SSPREQ 412 +#define DEFAULT 413 +#define HIDDEN 414 +#define PROTECTED 415 /* Copy the first part of user declarations. */ -#line 14 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 14 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" #include "ParserInternals.h" #include "llvm/CallingConv.h" @@ -1387,7 +1391,7 @@ #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED typedef union YYSTYPE -#line 986 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 986 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { llvm::Module *ModuleVal; llvm::Function *FunctionVal; @@ -1435,8 +1439,8 @@ llvm::ICmpInst::Predicate IPredicate; llvm::FCmpInst::Predicate FPredicate; } -/* Line 187 of yacc.c. */ -#line 1440 "llvmAsmParser.tab.c" +/* Line 193 of yacc.c. */ +#line 1444 "llvmAsmParser.tab.c" YYSTYPE; # define yystype YYSTYPE /* obsolescent; will be withdrawn */ # define YYSTYPE_IS_DECLARED 1 @@ -1449,7 +1453,7 @@ /* Line 216 of yacc.c. */ -#line 1453 "llvmAsmParser.tab.c" +#line 1457 "llvmAsmParser.tab.c" #ifdef short # undef short @@ -1499,7 +1503,7 @@ #define YYSIZE_MAXIMUM ((YYSIZE_T) -1) #ifndef YY_ -# if YYENABLE_NLS +# if defined YYENABLE_NLS && YYENABLE_NLS # if ENABLE_NLS # include /* INFRINGES ON USER NAME SPACE */ # define YY_(msgid) dgettext ("bison-runtime", msgid) @@ -1664,20 +1668,20 @@ /* YYFINAL -- State number of the termination state. */ #define YYFINAL 44 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 2377 +#define YYLAST 2433 /* YYNTOKENS -- Number of terminals. */ -#define YYNTOKENS 173 +#define YYNTOKENS 175 /* YYNNTS -- Number of nonterminals. */ #define YYNNTS 87 /* YYNRULES -- Number of rules. */ -#define YYNRULES 348 +#define YYNRULES 350 /* YYNRULES -- Number of states. */ -#define YYNSTATES 708 +#define YYNSTATES 710 /* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX. */ #define YYUNDEFTOK 2 -#define YYMAXUTOK 413 +#define YYMAXUTOK 415 #define YYTRANSLATE(YYX) \ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) @@ -1689,15 +1693,15 @@ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 159, 160, 163, 2, 162, 2, 2, 2, 2, 2, + 161, 162, 165, 2, 164, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 168, 161, 169, 2, 2, 2, 2, 2, 2, 2, + 170, 163, 171, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 2, 165, 164, 167, 2, 2, 2, 2, 2, 172, + 2, 167, 166, 169, 2, 2, 2, 2, 2, 174, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 166, 2, 2, 170, 2, 171, 2, 2, 2, 2, + 168, 2, 2, 172, 2, 173, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, @@ -1726,7 +1730,7 @@ 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, - 155, 156, 157, 158 + 155, 156, 157, 158, 159, 160 }; #if YYDEBUG @@ -1746,35 +1750,36 @@ 178, 180, 181, 183, 185, 186, 188, 190, 192, 194, 196, 199, 201, 203, 205, 207, 209, 211, 213, 215, 217, 220, 221, 224, 226, 228, 230, 231, 234, 236, - 238, 240, 242, 244, 246, 248, 250, 252, 254, 255, - 258, 259, 262, 263, 266, 267, 271, 274, 275, 277, - 278, 282, 284, 287, 289, 291, 293, 295, 297, 299, - 301, 303, 305, 309, 311, 314, 320, 326, 332, 338, - 342, 345, 351, 356, 359, 361, 363, 365, 369, 371, - 375, 377, 378, 380, 384, 389, 393, 397, 402, 407, - 411, 418, 424, 427, 430, 433, 436, 439, 442, 445, - 448, 451, 454, 457, 460, 467, 473, 482, 489, 496, - 504, 512, 520, 528, 535, 544, 553, 559, 567, 571, - 573, 575, 577, 579, 580, 583, 590, 592, 593, 595, - 598, 599, 603, 604, 608, 612, 616, 620, 621, 630, - 631, 641, 642, 652, 658, 661, 665, 667, 671, 675, - 679, 683, 685, 686, 692, 696, 698, 702, 704, 705, - 717, 719, 721, 726, 728, 730, 733, 737, 738, 740, + 238, 240, 242, 244, 246, 248, 250, 252, 254, 256, + 258, 259, 262, 263, 266, 267, 270, 271, 275, 278, + 279, 281, 282, 286, 288, 291, 293, 295, 297, 299, + 301, 303, 305, 307, 309, 313, 315, 318, 324, 330, + 336, 342, 346, 349, 355, 360, 363, 365, 367, 369, + 373, 375, 379, 381, 382, 384, 388, 393, 397, 401, + 406, 411, 415, 422, 428, 431, 434, 437, 440, 443, + 446, 449, 452, 455, 458, 461, 464, 471, 477, 486, + 493, 500, 508, 516, 524, 532, 539, 548, 557, 563, + 571, 575, 577, 579, 581, 583, 584, 587, 594, 596, + 597, 599, 602, 603, 607, 608, 612, 616, 620, 624, + 625, 634, 635, 645, 646, 656, 662, 665, 669, 671, + 675, 679, 683, 687, 689, 690, 696, 700, 702, 706, + 708, 709, 721, 723, 725, 730, 732, 734, 737, 741, 742, 744, 746, 748, 750, 752, 754, 756, 758, 760, - 764, 768, 771, 774, 778, 781, 787, 792, 794, 800, - 802, 804, 806, 808, 810, 812, 815, 817, 821, 824, - 827, 831, 835, 838, 839, 841, 844, 847, 851, 861, - 871, 880, 896, 898, 900, 907, 913, 916, 919, 926, - 934, 939, 944, 951, 958, 959, 960, 964, 967, 971, - 974, 976, 982, 988, 995, 1002, 1009, 1016, 1021, 1028, - 1033, 1038, 1045, 1052, 1055, 1065, 1067, 1069, 1070, 1074, - 1081, 1085, 1092, 1095, 1101, 1109, 1115, 1120, 1125 + 762, 764, 768, 772, 775, 778, 782, 785, 791, 796, + 798, 804, 806, 808, 810, 812, 814, 816, 819, 821, + 825, 828, 831, 835, 839, 842, 843, 845, 848, 851, + 855, 865, 875, 884, 900, 902, 904, 911, 917, 920, + 923, 930, 938, 943, 948, 955, 962, 963, 964, 968, + 971, 975, 978, 980, 986, 992, 999, 1006, 1013, 1020, + 1025, 1032, 1037, 1042, 1049, 1056, 1059, 1069, 1071, 1073, + 1074, 1078, 1085, 1089, 1096, 1099, 1105, 1113, 1119, 1124, + 1129 }; /* YYRHS -- A `-1'-separated list of the rules' RHS. */ static const yytype_int16 yyrhs[] = { - 220, 0, -1, 75, -1, 76, -1, 77, -1, 78, + 222, 0, -1, 75, -1, 76, -1, 77, -1, 78, -1, 79, -1, 80, -1, 81, -1, 82, -1, 83, -1, 87, -1, 88, -1, 89, -1, 84, -1, 85, -1, 86, -1, 120, -1, 121, -1, 122, -1, 123, @@ -1785,109 +1790,109 @@ -1, 106, -1, 107, -1, 108, -1, 109, -1, 110, -1, 111, -1, 112, -1, 113, -1, 100, -1, 101, -1, 102, -1, 103, -1, 26, -1, 27, -1, 19, - -1, 22, -1, 24, -1, 179, -1, -1, 55, 159, - 4, 160, -1, -1, 179, 161, -1, -1, 7, 161, - -1, 20, -1, 23, -1, 186, -1, -1, 184, 161, + -1, 22, -1, 24, -1, 181, -1, -1, 55, 161, + 4, 162, -1, -1, 181, 163, -1, -1, 7, 163, + -1, 20, -1, 23, -1, 188, -1, -1, 186, 163, -1, 42, -1, 44, -1, 43, -1, 45, -1, 47, -1, 49, -1, 46, -1, 48, -1, 51, -1, -1, - 156, -1, 157, -1, 158, -1, -1, 46, -1, 48, + 158, -1, 159, -1, 160, -1, -1, 46, -1, 48, -1, -1, 42, -1, 43, -1, 44, -1, 47, -1, -1, 44, -1, 42, -1, -1, 63, -1, 64, -1, 65, -1, 66, -1, 67, -1, 62, 4, -1, 142, -1, 121, -1, 141, -1, 122, -1, 144, -1, 145, -1, 147, -1, 148, -1, 149, -1, 54, 4, -1, - -1, 195, 194, -1, 144, -1, 142, -1, 141, -1, - -1, 197, 196, -1, 143, -1, 146, -1, 144, -1, + -1, 197, 196, -1, 144, -1, 142, -1, 141, -1, + -1, 199, 198, -1, 143, -1, 146, -1, 144, -1, 142, -1, 141, -1, 150, -1, 151, -1, 154, -1, - 155, -1, 153, -1, -1, 199, 198, -1, -1, 152, - 22, -1, -1, 54, 4, -1, -1, 162, 54, 4, - -1, 34, 22, -1, -1, 203, -1, -1, 162, 206, - 205, -1, 203, -1, 54, 4, -1, 11, -1, 12, - -1, 13, -1, 16, -1, 15, -1, 14, -1, 17, - -1, 50, -1, 207, -1, 208, 181, 163, -1, 242, - -1, 164, 4, -1, 208, 159, 212, 160, 199, -1, - 10, 159, 212, 160, 199, -1, 165, 4, 166, 208, - 167, -1, 168, 4, 166, 208, 169, -1, 170, 213, - 171, -1, 170, 171, -1, 168, 170, 213, 171, 169, - -1, 168, 170, 171, 169, -1, 208, 195, -1, 208, - -1, 10, -1, 209, -1, 211, 162, 209, -1, 211, - -1, 211, 162, 39, -1, 39, -1, -1, 208, -1, - 213, 162, 208, -1, 208, 165, 216, 167, -1, 208, - 165, 167, -1, 208, 172, 22, -1, 208, 168, 216, - 169, -1, 208, 170, 216, 171, -1, 208, 170, 171, - -1, 208, 168, 170, 216, 171, 169, -1, 208, 168, - 170, 171, 169, -1, 208, 40, -1, 208, 41, -1, - 208, 242, -1, 208, 215, -1, 208, 25, -1, 208, - 3, -1, 208, 5, -1, 208, 4, -1, 208, 6, - -1, 208, 26, -1, 208, 27, -1, 208, 9, -1, - 176, 159, 214, 38, 208, 160, -1, 119, 159, 214, - 254, 160, -1, 133, 159, 214, 162, 214, 162, 214, - 160, -1, 174, 159, 214, 162, 214, 160, -1, 175, - 159, 214, 162, 214, 160, -1, 90, 177, 159, 214, - 162, 214, 160, -1, 91, 178, 159, 214, 162, 214, - 160, -1, 92, 177, 159, 214, 162, 214, 160, -1, - 93, 178, 159, 214, 162, 214, 160, -1, 135, 159, - 214, 162, 214, 160, -1, 136, 159, 214, 162, 214, - 162, 214, 160, -1, 137, 159, 214, 162, 214, 162, - 214, 160, -1, 139, 159, 214, 255, 160, -1, 140, - 159, 214, 162, 214, 255, 160, -1, 216, 162, 214, - -1, 214, -1, 32, -1, 33, -1, 37, -1, -1, - 210, 242, -1, 125, 159, 219, 38, 208, 160, -1, - 221, -1, -1, 222, -1, 221, 222, -1, -1, 31, - 223, 238, -1, -1, 30, 224, 239, -1, 60, 59, - 228, -1, 182, 18, 208, -1, 182, 18, 10, -1, - -1, 185, 189, 218, 217, 214, 181, 225, 205, -1, - -1, 185, 187, 189, 218, 217, 214, 181, 226, 205, - -1, -1, 185, 188, 189, 218, 217, 208, 181, 227, - 205, -1, 185, 189, 35, 192, 219, -1, 52, 229, - -1, 56, 161, 230, -1, 22, -1, 53, 161, 22, - -1, 68, 161, 22, -1, 165, 231, 167, -1, 231, - 162, 22, -1, 22, -1, -1, 232, 162, 208, 195, - 180, -1, 208, 195, 180, -1, 232, -1, 232, 162, - 39, -1, 39, -1, -1, 193, 197, 210, 184, 159, - 233, 160, 199, 204, 201, 200, -1, 28, -1, 170, - -1, 191, 189, 234, 235, -1, 29, -1, 171, -1, - 246, 237, -1, 190, 189, 234, -1, -1, 61, -1, - 3, -1, 4, -1, 5, -1, 6, -1, 9, -1, - 26, -1, 27, -1, 40, -1, 41, -1, 25, -1, - 168, 216, 169, -1, 165, 216, 167, -1, 165, 167, - -1, 172, 22, -1, 170, 216, 171, -1, 170, 171, - -1, 168, 170, 216, 171, 169, -1, 168, 170, 171, - 169, -1, 215, -1, 59, 240, 22, 162, 22, -1, - 7, -1, 8, -1, 179, -1, 184, -1, 242, -1, - 241, -1, 208, 243, -1, 244, -1, 245, 162, 244, - -1, 246, 247, -1, 236, 247, -1, 248, 182, 249, - -1, 248, 183, 249, -1, 248, 251, -1, -1, 21, - -1, 69, 245, -1, 69, 10, -1, 70, 17, 243, - -1, 70, 11, 243, 162, 17, 243, 162, 17, 243, - -1, 71, 11, 243, 162, 17, 243, 165, 250, 167, - -1, 71, 11, 243, 162, 17, 243, 165, 167, -1, - 72, 193, 197, 210, 243, 159, 253, 160, 199, 38, - 17, 243, 73, 17, 243, -1, 73, -1, 74, -1, - 250, 11, 241, 162, 17, 243, -1, 11, 241, 162, - 17, 243, -1, 182, 257, -1, 183, 257, -1, 208, - 165, 243, 162, 243, 167, -1, 252, 162, 165, 243, - 162, 243, 167, -1, 208, 195, 243, 195, -1, 17, - 195, 243, 195, -1, 253, 162, 208, 195, 243, 195, - -1, 253, 162, 17, 195, 243, 195, -1, -1, -1, - 254, 162, 244, -1, 162, 4, -1, 255, 162, 4, - -1, 58, 57, -1, 57, -1, 174, 208, 243, 162, - 243, -1, 175, 208, 243, 162, 243, -1, 90, 177, - 208, 243, 162, 243, -1, 91, 178, 208, 243, 162, - 243, -1, 92, 177, 208, 243, 162, 243, -1, 93, - 178, 208, 243, 162, 243, -1, 176, 244, 38, 208, - -1, 133, 244, 162, 244, 162, 244, -1, 134, 244, - 162, 208, -1, 135, 244, 162, 244, -1, 136, 244, - 162, 244, 162, 244, -1, 137, 244, 162, 244, 162, - 244, -1, 132, 252, -1, 256, 193, 197, 210, 243, - 159, 253, 160, 199, -1, 259, -1, 36, -1, -1, - 114, 208, 202, -1, 114, 208, 162, 11, 243, 202, - -1, 115, 208, 202, -1, 115, 208, 162, 11, 243, - 202, -1, 116, 244, -1, 258, 117, 208, 243, 202, - -1, 258, 118, 244, 162, 208, 243, 202, -1, 138, - 208, 243, 162, 4, -1, 119, 208, 243, 254, -1, - 139, 208, 243, 255, -1, 140, 208, 243, 162, 208, - 243, 255, -1 + 155, -1, 153, -1, 156, -1, 157, -1, -1, 201, + 200, -1, -1, 152, 22, -1, -1, 54, 4, -1, + -1, 164, 54, 4, -1, 34, 22, -1, -1, 205, + -1, -1, 164, 208, 207, -1, 205, -1, 54, 4, + -1, 11, -1, 12, -1, 13, -1, 16, -1, 15, + -1, 14, -1, 17, -1, 50, -1, 209, -1, 210, + 183, 165, -1, 244, -1, 166, 4, -1, 210, 161, + 214, 162, 201, -1, 10, 161, 214, 162, 201, -1, + 167, 4, 168, 210, 169, -1, 170, 4, 168, 210, + 171, -1, 172, 215, 173, -1, 172, 173, -1, 170, + 172, 215, 173, 171, -1, 170, 172, 173, 171, -1, + 210, 197, -1, 210, -1, 10, -1, 211, -1, 213, + 164, 211, -1, 213, -1, 213, 164, 39, -1, 39, + -1, -1, 210, -1, 215, 164, 210, -1, 210, 167, + 218, 169, -1, 210, 167, 169, -1, 210, 174, 22, + -1, 210, 170, 218, 171, -1, 210, 172, 218, 173, + -1, 210, 172, 173, -1, 210, 170, 172, 218, 173, + 171, -1, 210, 170, 172, 173, 171, -1, 210, 40, + -1, 210, 41, -1, 210, 244, -1, 210, 217, -1, + 210, 25, -1, 210, 3, -1, 210, 5, -1, 210, + 4, -1, 210, 6, -1, 210, 26, -1, 210, 27, + -1, 210, 9, -1, 178, 161, 216, 38, 210, 162, + -1, 119, 161, 216, 256, 162, -1, 133, 161, 216, + 164, 216, 164, 216, 162, -1, 176, 161, 216, 164, + 216, 162, -1, 177, 161, 216, 164, 216, 162, -1, + 90, 179, 161, 216, 164, 216, 162, -1, 91, 180, + 161, 216, 164, 216, 162, -1, 92, 179, 161, 216, + 164, 216, 162, -1, 93, 180, 161, 216, 164, 216, + 162, -1, 135, 161, 216, 164, 216, 162, -1, 136, + 161, 216, 164, 216, 164, 216, 162, -1, 137, 161, + 216, 164, 216, 164, 216, 162, -1, 139, 161, 216, + 257, 162, -1, 140, 161, 216, 164, 216, 257, 162, + -1, 218, 164, 216, -1, 216, -1, 32, -1, 33, + -1, 37, -1, -1, 212, 244, -1, 125, 161, 221, + 38, 210, 162, -1, 223, -1, -1, 224, -1, 223, + 224, -1, -1, 31, 225, 240, -1, -1, 30, 226, + 241, -1, 60, 59, 230, -1, 184, 18, 210, -1, + 184, 18, 10, -1, -1, 187, 191, 220, 219, 216, + 183, 227, 207, -1, -1, 187, 189, 191, 220, 219, + 216, 183, 228, 207, -1, -1, 187, 190, 191, 220, + 219, 210, 183, 229, 207, -1, 187, 191, 35, 194, + 221, -1, 52, 231, -1, 56, 163, 232, -1, 22, + -1, 53, 163, 22, -1, 68, 163, 22, -1, 167, + 233, 169, -1, 233, 164, 22, -1, 22, -1, -1, + 234, 164, 210, 197, 182, -1, 210, 197, 182, -1, + 234, -1, 234, 164, 39, -1, 39, -1, -1, 195, + 199, 212, 186, 161, 235, 162, 201, 206, 203, 202, + -1, 28, -1, 172, -1, 193, 191, 236, 237, -1, + 29, -1, 173, -1, 248, 239, -1, 192, 191, 236, + -1, -1, 61, -1, 3, -1, 4, -1, 5, -1, + 6, -1, 9, -1, 26, -1, 27, -1, 40, -1, + 41, -1, 25, -1, 170, 218, 171, -1, 167, 218, + 169, -1, 167, 169, -1, 174, 22, -1, 172, 218, + 173, -1, 172, 173, -1, 170, 172, 218, 173, 171, + -1, 170, 172, 173, 171, -1, 217, -1, 59, 242, + 22, 164, 22, -1, 7, -1, 8, -1, 181, -1, + 186, -1, 244, -1, 243, -1, 210, 245, -1, 246, + -1, 247, 164, 246, -1, 248, 249, -1, 238, 249, + -1, 250, 184, 251, -1, 250, 185, 251, -1, 250, + 253, -1, -1, 21, -1, 69, 247, -1, 69, 10, + -1, 70, 17, 245, -1, 70, 11, 245, 164, 17, + 245, 164, 17, 245, -1, 71, 11, 245, 164, 17, + 245, 167, 252, 169, -1, 71, 11, 245, 164, 17, + 245, 167, 169, -1, 72, 195, 199, 212, 245, 161, + 255, 162, 201, 38, 17, 245, 73, 17, 245, -1, + 73, -1, 74, -1, 252, 11, 243, 164, 17, 245, + -1, 11, 243, 164, 17, 245, -1, 184, 259, -1, + 185, 259, -1, 210, 167, 245, 164, 245, 169, -1, + 254, 164, 167, 245, 164, 245, 169, -1, 210, 197, + 245, 197, -1, 17, 197, 245, 197, -1, 255, 164, + 210, 197, 245, 197, -1, 255, 164, 17, 197, 245, + 197, -1, -1, -1, 256, 164, 246, -1, 164, 4, + -1, 257, 164, 4, -1, 58, 57, -1, 57, -1, + 176, 210, 245, 164, 245, -1, 177, 210, 245, 164, + 245, -1, 90, 179, 210, 245, 164, 245, -1, 91, + 180, 210, 245, 164, 245, -1, 92, 179, 210, 245, + 164, 245, -1, 93, 180, 210, 245, 164, 245, -1, + 178, 246, 38, 210, -1, 133, 246, 164, 246, 164, + 246, -1, 134, 246, 164, 210, -1, 135, 246, 164, + 246, -1, 136, 246, 164, 246, 164, 246, -1, 137, + 246, 164, 246, 164, 246, -1, 132, 254, -1, 258, + 195, 199, 212, 245, 161, 255, 162, 201, -1, 261, + -1, 36, -1, -1, 114, 210, 204, -1, 114, 210, + 164, 11, 245, 204, -1, 115, 210, 204, -1, 115, + 210, 164, 11, 245, 204, -1, 116, 246, -1, 260, + 117, 210, 245, 204, -1, 260, 118, 246, 164, 210, + 245, 204, -1, 138, 210, 245, 164, 4, -1, 119, + 210, 245, 256, -1, 139, 210, 245, 257, -1, 140, + 210, 245, 164, 210, 245, 257, -1 }; /* YYRLINE[YYN] -- source line where rule number YYN was defined. */ @@ -1905,29 +1910,30 @@ 1246, 1250, 1251, 1252, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1281, 1282, 1287, 1288, 1289, 1292, 1293, 1299, 1300, - 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1311, 1312, - 1318, 1319, 1326, 1327, 1333, 1334, 1343, 1351, 1352, 1357, - 1358, 1359, 1364, 1377, 1377, 1377, 1377, 1377, 1377, 1377, - 1380, 1384, 1388, 1395, 1400, 1408, 1443, 1474, 1479, 1489, - 1499, 1503, 1513, 1520, 1529, 1536, 1541, 1546, 1553, 1554, - 1561, 1568, 1576, 1582, 1594, 1622, 1638, 1665, 1693, 1719, - 1739, 1765, 1785, 1797, 1804, 1870, 1880, 1890, 1901, 1914, - 1925, 1939, 1946, 1953, 1971, 1983, 2004, 2012, 2018, 2029, - 2034, 2039, 2044, 2049, 2055, 2061, 2067, 2075, 2086, 2090, - 2098, 2098, 2101, 2101, 2104, 2116, 2137, 2142, 2150, 2151, - 2155, 2155, 2159, 2159, 2162, 2165, 2189, 2201, 2200, 2212, - 2211, 2221, 2220, 2231, 2271, 2274, 2280, 2290, 2294, 2299, - 2301, 2306, 2311, 2320, 2330, 2341, 2345, 2354, 2363, 2368, - 2517, 2517, 2519, 2528, 2528, 2530, 2535, 2547, 2551, 2556, - 2560, 2564, 2569, 2574, 2578, 2582, 2586, 2590, 2594, 2598, - 2620, 2642, 2648, 2661, 2673, 2678, 2690, 2696, 2700, 2710, - 2714, 2718, 2723, 2730, 2730, 2736, 2745, 2750, 2755, 2759, - 2768, 2777, 2790, 2799, 2803, 2811, 2831, 2835, 2840, 2851, - 2870, 2879, 2983, 2987, 2994, 3005, 3018, 3027, 3040, 3051, - 3061, 3072, 3080, 3090, 3097, 3100, 3101, 3109, 3115, 3124, - 3128, 3133, 3149, 3166, 3178, 3190, 3204, 3218, 3230, 3251, - 3258, 3264, 3270, 3276, 3291, 3401, 3406, 3410, 3417, 3424, - 3434, 3441, 3451, 3459, 3473, 3490, 3504, 3519, 3534 + 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, + 1313, 1314, 1320, 1321, 1328, 1329, 1335, 1336, 1345, 1353, + 1354, 1359, 1360, 1361, 1366, 1379, 1379, 1379, 1379, 1379, + 1379, 1379, 1382, 1386, 1390, 1397, 1402, 1410, 1445, 1476, + 1481, 1491, 1501, 1505, 1515, 1522, 1531, 1538, 1543, 1548, + 1555, 1556, 1563, 1570, 1578, 1584, 1596, 1624, 1640, 1667, + 1695, 1721, 1741, 1767, 1787, 1799, 1806, 1872, 1882, 1892, + 1903, 1916, 1927, 1941, 1948, 1955, 1973, 1985, 2006, 2014, + 2020, 2031, 2036, 2041, 2046, 2051, 2057, 2063, 2069, 2077, + 2088, 2092, 2100, 2100, 2103, 2103, 2106, 2118, 2139, 2144, + 2152, 2153, 2157, 2157, 2161, 2161, 2164, 2167, 2191, 2203, + 2202, 2214, 2213, 2223, 2222, 2233, 2273, 2276, 2282, 2292, + 2296, 2301, 2303, 2308, 2313, 2322, 2332, 2343, 2347, 2356, + 2365, 2370, 2519, 2519, 2521, 2530, 2530, 2532, 2537, 2549, + 2553, 2558, 2562, 2566, 2571, 2576, 2580, 2584, 2588, 2592, + 2596, 2600, 2622, 2644, 2650, 2663, 2675, 2680, 2692, 2698, + 2702, 2712, 2716, 2720, 2725, 2732, 2732, 2738, 2747, 2752, + 2757, 2761, 2770, 2779, 2792, 2801, 2805, 2813, 2833, 2837, + 2842, 2853, 2872, 2881, 2985, 2989, 2996, 3007, 3020, 3029, + 3042, 3053, 3063, 3074, 3082, 3092, 3099, 3102, 3103, 3111, + 3117, 3126, 3130, 3135, 3151, 3168, 3180, 3192, 3206, 3220, + 3232, 3253, 3260, 3266, 3272, 3278, 3293, 3403, 3408, 3412, + 3419, 3426, 3436, 3443, 3453, 3461, 3475, 3492, 3506, 3521, + 3536 }; #endif @@ -1960,16 +1966,16 @@ "GETRESULT", "EXTRACTVALUE", "INSERTVALUE", "SIGNEXT", "ZEROEXT", "NORETURN", "INREG", "SRET", "NOUNWIND", "NOALIAS", "BYVAL", "NEST", "READNONE", "READONLY", "GC", "OPTSIZE", "NOINLINE", "ALWAYSINLINE", - "DEFAULT", "HIDDEN", "PROTECTED", "'('", "')'", "'='", "','", "'*'", - "'\\\\'", "'['", "'x'", "']'", "'<'", "'>'", "'{'", "'}'", "'c'", - "$accept", "ArithmeticOps", "LogicalOps", "CastOps", "IPredicates", - "FPredicates", "LocalName", "OptLocalName", "OptAddrSpace", - "OptLocalAssign", "LocalNumber", "GlobalName", "OptGlobalAssign", - "GlobalAssign", "GVInternalLinkage", "GVExternalLinkage", - "GVVisibilityStyle", "FunctionDeclareLinkage", "FunctionDefineLinkage", - "AliasLinkage", "OptCallingConv", "Attribute", "OptAttributes", - "RetAttr", "OptRetAttrs", "FuncAttr", "OptFuncAttrs", "OptGC", - "OptAlign", "OptCAlign", "SectionString", "OptSection", + "SSP", "SSPREQ", "DEFAULT", "HIDDEN", "PROTECTED", "'('", "')'", "'='", + "','", "'*'", "'\\\\'", "'['", "'x'", "']'", "'<'", "'>'", "'{'", "'}'", + "'c'", "$accept", "ArithmeticOps", "LogicalOps", "CastOps", + "IPredicates", "FPredicates", "LocalName", "OptLocalName", + "OptAddrSpace", "OptLocalAssign", "LocalNumber", "GlobalName", + "OptGlobalAssign", "GlobalAssign", "GVInternalLinkage", + "GVExternalLinkage", "GVVisibilityStyle", "FunctionDeclareLinkage", + "FunctionDefineLinkage", "AliasLinkage", "OptCallingConv", "Attribute", + "OptAttributes", "RetAttr", "OptRetAttrs", "FuncAttr", "OptFuncAttrs", + "OptGC", "OptAlign", "OptCAlign", "SectionString", "OptSection", "GlobalVarAttributes", "GlobalVarAttribute", "PrimType", "Types", "ArgType", "ResultTypes", "ArgTypeList", "ArgTypeListI", "TypeListI", "ConstVal", "ConstExpr", "ConstVector", "GlobalType", "ThreadLocal", @@ -2005,50 +2011,51 @@ 375, 376, 377, 378, 379, 380, 381, 382, 383, 384, 385, 386, 387, 388, 389, 390, 391, 392, 393, 394, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, - 405, 406, 407, 408, 409, 410, 411, 412, 413, 40, - 41, 61, 44, 42, 92, 91, 120, 93, 60, 62, - 123, 125, 99 + 405, 406, 407, 408, 409, 410, 411, 412, 413, 414, + 415, 40, 41, 61, 44, 42, 92, 91, 120, 93, + 60, 62, 123, 125, 99 }; # endif /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ static const yytype_uint16 yyr1[] = { - 0, 173, 174, 174, 174, 174, 174, 174, 174, 174, - 174, 175, 175, 175, 175, 175, 175, 176, 176, 176, - 176, 176, 176, 176, 176, 176, 176, 176, 176, 177, - 177, 177, 177, 177, 177, 177, 177, 177, 177, 178, - 178, 178, 178, 178, 178, 178, 178, 178, 178, 178, - 178, 178, 178, 178, 178, 179, 179, 179, 180, 180, - 181, 181, 182, 182, 183, 184, 184, 185, 185, 186, - 187, 187, 187, 187, 187, 187, 188, 188, 188, 189, - 189, 189, 189, 190, 190, 190, 191, 191, 191, 191, - 191, 192, 192, 192, 193, 193, 193, 193, 193, 193, - 193, 194, 194, 194, 194, 194, 194, 194, 194, 194, - 194, 195, 195, 196, 196, 196, 197, 197, 198, 198, - 198, 198, 198, 198, 198, 198, 198, 198, 199, 199, - 200, 200, 201, 201, 202, 202, 203, 204, 204, 205, - 205, 206, 206, 207, 207, 207, 207, 207, 207, 207, - 208, 208, 208, 208, 208, 208, 208, 208, 208, 208, - 208, 208, 208, 209, 210, 210, 211, 211, 212, 212, - 212, 212, 213, 213, 214, 214, 214, 214, 214, 214, - 214, 214, 214, 214, 214, 214, 214, 214, 214, 214, - 214, 214, 214, 214, 215, 215, 215, 215, 215, 215, - 215, 215, 215, 215, 215, 215, 215, 215, 216, 216, - 217, 217, 218, 218, 219, 219, 220, 220, 221, 221, - 223, 222, 224, 222, 222, 222, 222, 225, 222, 226, - 222, 227, 222, 222, 222, 222, 228, 229, 229, 230, - 231, 231, 231, 232, 232, 233, 233, 233, 233, 234, - 235, 235, 236, 237, 237, 238, 239, 240, 240, 241, - 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, - 241, 241, 241, 241, 241, 241, 241, 241, 241, 242, - 242, 242, 242, 243, 243, 244, 245, 245, 246, 246, - 247, 247, 248, 248, 248, 249, 249, 249, 249, 249, - 249, 249, 249, 249, 250, 250, 251, 251, 252, 252, - 253, 253, 253, 253, 253, 254, 254, 255, 255, 256, - 256, 257, 257, 257, 257, 257, 257, 257, 257, 257, - 257, 257, 257, 257, 257, 257, 258, 258, 259, 259, - 259, 259, 259, 259, 259, 259, 259, 259, 259 + 0, 175, 176, 176, 176, 176, 176, 176, 176, 176, + 176, 177, 177, 177, 177, 177, 177, 178, 178, 178, + 178, 178, 178, 178, 178, 178, 178, 178, 178, 179, + 179, 179, 179, 179, 179, 179, 179, 179, 179, 180, + 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, + 180, 180, 180, 180, 180, 181, 181, 181, 182, 182, + 183, 183, 184, 184, 185, 186, 186, 187, 187, 188, + 189, 189, 189, 189, 189, 189, 190, 190, 190, 191, + 191, 191, 191, 192, 192, 192, 193, 193, 193, 193, + 193, 194, 194, 194, 195, 195, 195, 195, 195, 195, + 195, 196, 196, 196, 196, 196, 196, 196, 196, 196, + 196, 197, 197, 198, 198, 198, 199, 199, 200, 200, + 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, + 201, 201, 202, 202, 203, 203, 204, 204, 205, 206, + 206, 207, 207, 208, 208, 209, 209, 209, 209, 209, + 209, 209, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 211, 212, 212, 213, 213, + 214, 214, 214, 214, 215, 215, 216, 216, 216, 216, + 216, 216, 216, 216, 216, 216, 216, 216, 216, 216, + 216, 216, 216, 216, 216, 216, 217, 217, 217, 217, + 217, 217, 217, 217, 217, 217, 217, 217, 217, 217, + 218, 218, 219, 219, 220, 220, 221, 221, 222, 222, + 223, 223, 225, 224, 226, 224, 224, 224, 224, 227, + 224, 228, 224, 229, 224, 224, 224, 224, 230, 231, + 231, 232, 233, 233, 233, 234, 234, 235, 235, 235, + 235, 236, 237, 237, 238, 239, 239, 240, 241, 242, + 242, 243, 243, 243, 243, 243, 243, 243, 243, 243, + 243, 243, 243, 243, 243, 243, 243, 243, 243, 243, + 243, 244, 244, 244, 244, 245, 245, 246, 247, 247, + 248, 248, 249, 249, 250, 250, 250, 251, 251, 251, + 251, 251, 251, 251, 251, 251, 252, 252, 253, 253, + 254, 254, 255, 255, 255, 255, 255, 256, 256, 257, + 257, 258, 258, 259, 259, 259, 259, 259, 259, 259, + 259, 259, 259, 259, 259, 259, 259, 259, 260, 260, + 261, 261, 261, 261, 261, 261, 261, 261, 261, 261, + 261 }; /* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */ @@ -2066,29 +2073,30 @@ 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 0, 2, 1, 1, 1, 0, 2, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 0, 2, - 0, 2, 0, 2, 0, 3, 2, 0, 1, 0, - 3, 1, 2, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 3, 1, 2, 5, 5, 5, 5, 3, - 2, 5, 4, 2, 1, 1, 1, 3, 1, 3, - 1, 0, 1, 3, 4, 3, 3, 4, 4, 3, - 6, 5, 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 6, 5, 8, 6, 6, 7, - 7, 7, 7, 6, 8, 8, 5, 7, 3, 1, - 1, 1, 1, 0, 2, 6, 1, 0, 1, 2, - 0, 3, 0, 3, 3, 3, 3, 0, 8, 0, - 9, 0, 9, 5, 2, 3, 1, 3, 3, 3, - 3, 1, 0, 5, 3, 1, 3, 1, 0, 11, - 1, 1, 4, 1, 1, 2, 3, 0, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, - 3, 2, 2, 3, 2, 5, 4, 1, 5, 1, - 1, 1, 1, 1, 1, 2, 1, 3, 2, 2, - 3, 3, 2, 0, 1, 2, 2, 3, 9, 9, - 8, 15, 1, 1, 6, 5, 2, 2, 6, 7, - 4, 4, 6, 6, 0, 0, 3, 2, 3, 2, - 1, 5, 5, 6, 6, 6, 6, 4, 6, 4, - 4, 6, 6, 2, 9, 1, 1, 0, 3, 6, - 3, 6, 2, 5, 7, 5, 4, 4, 7 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 0, 2, 0, 2, 0, 2, 0, 3, 2, 0, + 1, 0, 3, 1, 2, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 3, 1, 2, 5, 5, 5, + 5, 3, 2, 5, 4, 2, 1, 1, 1, 3, + 1, 3, 1, 0, 1, 3, 4, 3, 3, 4, + 4, 3, 6, 5, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 6, 5, 8, 6, + 6, 7, 7, 7, 7, 6, 8, 8, 5, 7, + 3, 1, 1, 1, 1, 0, 2, 6, 1, 0, + 1, 2, 0, 3, 0, 3, 3, 3, 3, 0, + 8, 0, 9, 0, 9, 5, 2, 3, 1, 3, + 3, 3, 3, 1, 0, 5, 3, 1, 3, 1, + 0, 11, 1, 1, 4, 1, 1, 2, 3, 0, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 3, 3, 2, 2, 3, 2, 5, 4, 1, + 5, 1, 1, 1, 1, 1, 1, 2, 1, 3, + 2, 2, 3, 3, 2, 0, 1, 2, 2, 3, + 9, 9, 8, 15, 1, 1, 6, 5, 2, 2, + 6, 7, 4, 4, 6, 6, 0, 0, 3, 2, + 3, 2, 1, 5, 5, 6, 6, 6, 6, 4, + 6, 4, 4, 6, 6, 2, 9, 1, 1, 0, + 3, 6, 3, 6, 2, 5, 7, 5, 4, 4, + 7 }; /* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state @@ -2096,672 +2104,684 @@ means the default is an error. */ static const yytype_uint16 yydefact[] = { - 68, 55, 65, 56, 66, 57, 222, 220, 0, 0, - 0, 0, 0, 0, 79, 67, 0, 68, 218, 83, - 86, 0, 0, 234, 0, 0, 62, 0, 69, 70, + 68, 55, 65, 56, 66, 57, 224, 222, 0, 0, + 0, 0, 0, 0, 79, 67, 0, 68, 220, 83, + 86, 0, 0, 236, 0, 0, 62, 0, 69, 70, 72, 71, 73, 76, 74, 77, 75, 78, 80, 81, - 82, 79, 79, 213, 1, 219, 84, 85, 79, 223, - 87, 88, 89, 90, 79, 293, 221, 293, 0, 0, - 242, 235, 236, 224, 279, 280, 226, 143, 144, 145, - 148, 147, 146, 149, 150, 0, 0, 0, 0, 281, - 282, 151, 225, 153, 213, 213, 91, 212, 0, 94, - 94, 294, 289, 63, 253, 254, 255, 288, 237, 238, - 241, 0, 171, 154, 0, 0, 0, 0, 160, 172, - 0, 0, 171, 0, 0, 0, 93, 92, 0, 210, - 211, 0, 0, 95, 96, 97, 98, 99, 116, 256, - 0, 0, 337, 337, 292, 0, 239, 170, 111, 166, - 168, 0, 0, 0, 0, 0, 0, 159, 0, 0, - 152, 0, 0, 165, 0, 164, 0, 233, 61, 61, - 100, 0, 250, 251, 252, 64, 336, 320, 0, 0, - 0, 0, 94, 302, 303, 2, 3, 4, 5, 6, + 82, 79, 79, 215, 1, 221, 84, 85, 79, 225, + 87, 88, 89, 90, 79, 295, 223, 295, 0, 0, + 244, 237, 238, 226, 281, 282, 228, 145, 146, 147, + 150, 149, 148, 151, 152, 0, 0, 0, 0, 283, + 284, 153, 227, 155, 215, 215, 91, 214, 0, 94, + 94, 296, 291, 63, 255, 256, 257, 290, 239, 240, + 243, 0, 173, 156, 0, 0, 0, 0, 162, 174, + 0, 0, 173, 0, 0, 0, 93, 92, 0, 212, + 213, 0, 0, 95, 96, 97, 98, 99, 116, 258, + 0, 0, 339, 339, 294, 0, 241, 172, 111, 168, + 170, 0, 0, 0, 0, 0, 0, 161, 0, 0, + 154, 0, 0, 167, 0, 166, 0, 235, 61, 61, + 100, 0, 252, 253, 254, 64, 338, 322, 0, 0, + 0, 0, 94, 304, 305, 2, 3, 4, 5, 6, 7, 8, 9, 10, 14, 15, 16, 11, 12, 13, 0, 0, 0, 0, 0, 0, 0, 0, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 290, 94, 306, 0, 335, 291, 307, 240, - 163, 0, 128, 61, 61, 162, 0, 173, 0, 128, - 61, 61, 0, 214, 187, 189, 188, 190, 193, 186, - 191, 192, 182, 183, 0, 0, 0, 0, 0, 0, + 0, 0, 292, 94, 308, 0, 337, 293, 309, 242, + 165, 0, 130, 61, 61, 164, 0, 175, 0, 130, + 61, 61, 0, 216, 189, 191, 190, 192, 195, 188, + 193, 194, 184, 185, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 185, 184, 227, 115, 114, 113, 117, 0, - 319, 296, 61, 286, 295, 0, 0, 0, 116, 29, + 0, 0, 187, 186, 229, 115, 114, 113, 117, 0, + 321, 298, 61, 288, 297, 0, 0, 0, 116, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 0, 53, 54, 49, 50, 51, 52, 39, 40, 41, 42, - 43, 44, 45, 46, 47, 48, 0, 0, 0, 134, - 134, 342, 61, 61, 333, 0, 0, 0, 0, 0, + 43, 44, 45, 46, 47, 48, 0, 0, 0, 136, + 136, 344, 61, 61, 335, 0, 0, 0, 0, 0, 61, 61, 61, 61, 61, 0, 116, 0, 0, 0, 102, 104, 103, 101, 105, 106, 107, 108, 109, 112, - 169, 167, 156, 157, 158, 161, 60, 155, 229, 231, + 171, 169, 158, 159, 160, 163, 60, 157, 231, 233, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 175, 209, 0, 0, 0, 179, 0, 176, - 0, 0, 0, 139, 0, 259, 260, 261, 262, 263, - 268, 264, 265, 266, 267, 257, 0, 0, 0, 0, - 277, 284, 283, 285, 0, 0, 297, 0, 0, 61, - 61, 61, 61, 0, 338, 0, 340, 315, 0, 0, + 0, 0, 177, 211, 0, 0, 0, 181, 0, 178, + 0, 0, 0, 141, 0, 261, 262, 263, 264, 265, + 270, 266, 267, 268, 269, 259, 0, 0, 0, 0, + 279, 286, 285, 287, 0, 0, 299, 0, 0, 61, + 61, 61, 61, 0, 340, 0, 342, 317, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 61, 0, 110, 122, 121, 118, 120, 119, - 123, 124, 127, 125, 126, 129, 139, 139, 0, 0, - 0, 0, 0, 315, 0, 0, 0, 0, 0, 0, - 0, 174, 160, 172, 0, 177, 178, 0, 0, 0, - 0, 228, 248, 258, 0, 271, 0, 0, 0, 274, - 0, 272, 287, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 346, 0, 0, 0, 329, 330, 0, - 0, 0, 0, 347, 0, 0, 0, 327, 0, 134, - 0, 230, 232, 61, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 208, 181, 0, 0, 0, - 0, 0, 0, 141, 139, 247, 111, 245, 0, 0, - 270, 160, 0, 269, 273, 0, 0, 0, 0, 0, - 0, 0, 134, 135, 134, 0, 0, 0, 0, 0, - 0, 345, 317, 0, 61, 321, 322, 0, 0, 343, - 61, 215, 0, 0, 0, 0, 195, 0, 0, 0, - 0, 206, 0, 180, 0, 0, 61, 136, 142, 140, - 59, 0, 128, 0, 276, 0, 0, 0, 314, 323, - 324, 325, 326, 339, 341, 316, 0, 0, 328, 331, - 332, 318, 0, 314, 134, 0, 0, 0, 0, 0, - 203, 0, 0, 0, 197, 198, 194, 58, 244, 246, - 111, 137, 278, 275, 0, 0, 111, 111, 0, 308, - 0, 348, 0, 344, 199, 200, 201, 202, 0, 0, - 0, 207, 59, 138, 132, 0, 0, 300, 0, 0, - 0, 128, 0, 309, 128, 196, 204, 205, 243, 0, - 130, 298, 0, 0, 299, 102, 104, 111, 111, 0, - 111, 111, 334, 133, 0, 249, 0, 0, 311, 310, - 0, 0, 0, 131, 0, 0, 0, 111, 111, 305, - 0, 0, 313, 312, 304, 0, 0, 301 + 123, 124, 127, 125, 126, 128, 129, 131, 141, 141, + 0, 0, 0, 0, 0, 317, 0, 0, 0, 0, + 0, 0, 0, 176, 162, 174, 0, 179, 180, 0, + 0, 0, 0, 230, 250, 260, 0, 273, 0, 0, + 0, 276, 0, 274, 289, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 348, 0, 0, 0, 331, + 332, 0, 0, 0, 0, 349, 0, 0, 0, 329, + 0, 136, 0, 232, 234, 61, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 210, 183, 0, + 0, 0, 0, 0, 0, 143, 141, 249, 111, 247, + 0, 0, 272, 162, 0, 271, 275, 0, 0, 0, + 0, 0, 0, 0, 136, 137, 136, 0, 0, 0, + 0, 0, 0, 347, 319, 0, 61, 323, 324, 0, + 0, 345, 61, 217, 0, 0, 0, 0, 197, 0, + 0, 0, 0, 208, 0, 182, 0, 0, 61, 138, + 144, 142, 59, 0, 130, 0, 278, 0, 0, 0, + 316, 325, 326, 327, 328, 341, 343, 318, 0, 0, + 330, 333, 334, 320, 0, 316, 136, 0, 0, 0, + 0, 0, 205, 0, 0, 0, 199, 200, 196, 58, + 246, 248, 111, 139, 280, 277, 0, 0, 111, 111, + 0, 310, 0, 350, 0, 346, 201, 202, 203, 204, + 0, 0, 0, 209, 59, 140, 134, 0, 0, 302, + 0, 0, 0, 130, 0, 311, 130, 198, 206, 207, + 245, 0, 132, 300, 0, 0, 301, 102, 104, 111, + 111, 0, 111, 111, 336, 135, 0, 251, 0, 0, + 313, 312, 0, 0, 0, 133, 0, 0, 0, 111, + 111, 307, 0, 0, 315, 314, 306, 0, 0, 303 }; /* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int16 yydefgoto[] = { - -1, 269, 270, 271, 299, 316, 79, 628, 113, 12, + -1, 269, 270, 271, 299, 316, 79, 630, 113, 12, 133, 80, 14, 15, 41, 42, 43, 48, 54, 118, - 128, 349, 230, 278, 161, 445, 352, 685, 670, 414, - 533, 654, 471, 534, 81, 158, 139, 156, 140, 141, + 128, 349, 230, 278, 161, 447, 352, 687, 672, 414, + 535, 656, 473, 536, 81, 158, 139, 156, 140, 141, 110, 373, 400, 374, 121, 88, 157, 16, 17, 18, - 20, 19, 383, 446, 447, 63, 23, 61, 101, 537, - 538, 129, 164, 55, 96, 56, 49, 474, 401, 83, - 403, 283, 284, 57, 92, 93, 222, 658, 134, 324, - 638, 493, 503, 223, 224, 225, 226 + 20, 19, 383, 448, 449, 63, 23, 61, 101, 539, + 540, 129, 164, 55, 96, 56, 49, 476, 401, 83, + 403, 283, 284, 57, 92, 93, 222, 660, 134, 324, + 640, 495, 505, 223, 224, 225, 226 }; /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing STATE-NUM. */ -#define YYPACT_NINF -624 +#define YYPACT_NINF -615 static const yytype_int16 yypact[] = { - 815, -624, -624, -624, -624, -624, -624, -624, 14, -114, - 16, -73, 78, -31, 299, -624, 163, 2187, -624, 164, - 80, 19, 22, -624, 2, 179, -624, 1912, -624, -624, - -624, -624, -624, -624, -624, -624, -624, -624, -624, -624, - -624, 68, 68, 201, -624, -624, -624, -624, 68, -624, - -624, -624, -624, -624, 68, 200, -624, 5, 215, 222, - 225, -624, -624, -624, -624, -624, 117, -624, -624, -624, - -624, -624, -624, -624, -624, 264, 277, 7, 49, -624, - -624, -624, -12, -624, 252, 252, 198, -624, 79, 231, - 231, -624, -624, 83, -624, -624, -624, -624, -624, -624, - -624, -21, 649, -624, 138, 149, 627, 117, -624, -12, - -120, 159, 649, 158, 79, 79, -624, -624, 1557, -624, - -624, 2012, 320, -624, -624, -624, -624, -624, -624, -624, - -13, 173, 2237, 2237, -624, 313, -624, -624, -12, -624, - 174, 177, 2012, 2012, 169, -118, 2012, -624, 336, 191, - -624, 2012, 2012, 117, 193, -12, 226, -624, 1296, 308, - -624, 1516, -624, -624, -624, -624, -624, -624, 307, 2031, - 108, 357, 231, -624, -624, -624, -624, -624, -624, -624, - -624, -624, -624, -624, -624, -624, -624, -624, -624, -624, - 454, 958, 454, 958, 2012, 2012, 2012, 2012, -624, -624, - -624, -624, -624, -624, -624, -624, -624, -624, -624, -624, - 2012, 2012, 2012, 2012, 2012, 2012, 2012, 2012, 2012, 2012, - 2012, 2012, -624, 231, -624, 55, -624, -624, -624, -624, - 161, 1748, -624, -23, -41, -624, 203, -12, 214, -624, - 308, -20, 1557, -624, -624, -624, -624, -624, -624, -624, - -624, -624, -624, -624, 454, 958, 454, 958, 216, 217, - 218, 220, 221, 224, 227, 1789, 2076, 732, 351, 228, - 229, 230, -624, -624, -624, -624, -624, -624, -624, 109, - -624, 117, 956, -624, 219, 1466, 1466, 1466, -624, -624, - -624, -624, -624, -624, -624, -624, -624, -624, -624, 2012, - -624, -624, -624, -624, -624, -624, -624, -624, -624, -624, - -624, -624, -624, -624, -624, -624, 2012, 2012, 2012, -10, - 3, -624, 956, -17, 223, 237, 238, 239, 240, 241, - 956, 956, 956, 956, 956, 352, -624, 2012, 2012, 387, - -624, -624, -624, -624, -624, -624, -624, -624, -624, -624, - -624, -624, 539, -624, -624, -624, -624, 539, -624, 158, - 354, 234, 248, 249, 250, 2012, 2012, 2012, 2012, 2012, - 2012, 2012, -624, -624, 42, 1006, -121, -624, -116, -624, - 2012, 2012, 2012, 253, 251, -624, -624, -624, -624, -624, - -624, -624, -624, -624, -624, 353, 1807, 2094, 1175, 390, - -624, -624, -624, -624, 2012, 255, -624, 256, 1516, 956, - 956, 956, 956, 20, -624, 29, -624, -624, 1466, 254, - 2012, 2012, 2012, 2012, 2012, 258, 259, 261, 262, 263, - 2012, 1516, 956, 266, -624, -624, -624, -624, -624, -624, - -624, -624, -624, -624, -624, -624, 253, 253, 2012, 2012, - 2012, 2012, 2012, -624, 269, 270, 272, 273, 259, 274, - 2012, -624, 268, 1126, -84, -624, -624, 280, 281, 406, - -5, -624, 1830, -624, 423, -624, 61, 1345, -56, -624, - -77, -624, -624, 430, 431, 1466, 288, 290, 291, 292, - 1466, 455, 1466, 296, 298, 1466, 300, -12, -624, 301, - 302, 457, 461, 306, 2012, 1466, 1466, -12, 1466, 311, - 2012, -624, -624, -1, 312, 314, 317, 319, 101, 2012, - 2012, 2012, 2012, 112, 2012, -624, -624, 318, 2012, 2012, - 2012, 453, 478, -624, 253, -624, -12, 321, 326, 327, - -624, 323, -67, -624, -624, 1466, 1466, 329, 1466, 1466, - 1466, 1466, 311, -624, 311, 2012, 1466, 328, 2012, 2012, - 2012, -624, -624, 489, 956, -624, -624, 335, 441, -624, - 956, -624, 2012, 2012, 2012, 2012, -624, 334, 337, 339, - 340, -624, 259, -624, 343, 345, 15, -624, -624, -624, - 178, 1848, -624, 484, -624, 338, 350, 349, 2117, -624, - -624, -624, -624, -624, -624, -624, 348, 1466, -624, -624, - -624, -624, 259, 2117, 311, 356, 359, 360, 361, 2012, - -624, 2012, 2012, 115, -624, -624, -624, -624, -624, -624, - -12, 116, -624, -624, 505, -7, 59, -12, 118, -624, - 358, 306, 124, -624, -624, -624, -624, -624, 363, 364, - 366, -624, 178, -624, 473, 1466, 1614, -624, -6, 802, - 802, -624, 2135, -624, -624, -624, -624, -624, -624, 526, - 379, -624, 374, 1614, -624, 378, 380, -624, -624, 442, - 59, -12, 539, -624, 516, -624, 523, 396, 161, 161, - 524, 802, 802, -624, 1466, 525, 1466, -624, -624, -624, - 1466, 486, 161, 161, -624, 543, 1466, -624 + 789, -615, -615, -615, -615, -615, -615, -615, -10, -110, + 29, -106, 31, -56, 22, -615, 45, 1491, -615, 162, + 194, 20, 33, -615, -43, 141, -615, 1998, -615, -615, + -615, -615, -615, -615, -615, -615, -615, -615, -615, -615, + -615, 88, 88, 176, -615, -615, -615, -615, 88, -615, + -615, -615, -615, -615, 88, 178, -615, -11, 207, 213, + 243, -615, -615, -615, -615, -615, 115, -615, -615, -615, + -615, -615, -615, -615, -615, 275, 289, 1, 480, -615, + -615, -615, 36, -615, 263, 263, 200, -615, 143, 197, + 197, -615, -615, 65, -615, -615, -615, -615, -615, -615, + -615, -54, 1723, -615, 140, 155, 549, 115, -615, 36, + -122, 167, 1723, 160, 143, 143, -615, -615, 1767, -615, + -615, 2023, 327, -615, -615, -615, -615, -615, -615, -615, + -16, 180, 2293, 2293, -615, 322, -615, -615, 36, -615, + 181, 184, 2023, 2023, 179, -118, 2023, -615, 343, 189, + -615, 2023, 2023, 115, 191, 36, 55, -615, 1277, 298, + -615, 1678, -615, -615, -615, -615, -615, -615, 297, 2064, + 112, 344, 197, -615, -615, -615, -615, -615, -615, -615, + -615, -615, -615, -615, -615, -615, -615, -615, -615, -615, + 219, 555, 219, 555, 2023, 2023, 2023, 2023, -615, -615, + -615, -615, -615, -615, -615, -615, -615, -615, -615, -615, + 2023, 2023, 2023, 2023, 2023, 2023, 2023, 2023, 2023, 2023, + 2023, 2023, -615, 197, -615, 132, -615, -615, -615, -615, + 334, 1816, -615, -39, -40, -615, 188, 36, 198, -615, + 298, -14, 1767, -615, -615, -615, -615, -615, -615, -615, + -615, -615, -615, -615, 219, 555, 219, 555, 195, 201, + 202, 203, 205, 206, 210, 1857, 2123, 983, 339, 211, + 212, 214, -615, -615, -615, -615, -615, -615, -615, 105, + -615, 115, 933, -615, 216, 1449, 1449, 1449, -615, -615, + -615, -615, -615, -615, -615, -615, -615, -615, -615, 2023, + -615, -615, -615, -615, -615, -615, -615, -615, -615, -615, + -615, -615, -615, -615, -615, -615, 2023, 2023, 2023, 54, + 56, -615, 933, -29, 217, 223, 226, 227, 228, 229, + 933, 933, 933, 933, 933, 336, -615, 2023, 2023, 372, + -615, -615, -615, -615, -615, -615, -615, -615, -615, -615, + -615, -615, 556, -615, -615, -615, -615, 556, -615, 160, + 345, 224, 240, 242, 245, 2023, 2023, 2023, 2023, 2023, + 2023, 2023, -615, -615, -19, 1154, -52, -615, -117, -615, + 2023, 2023, 2023, 247, 252, -615, -615, -615, -615, -615, + -615, -615, -615, -615, -615, 316, 1898, 2164, 1326, 392, + -615, -615, -615, -615, 2023, 251, -615, 254, 1678, 933, + 933, 933, 933, 27, -615, 28, -615, -615, 1449, 253, + 2023, 2023, 2023, 2023, 2023, 255, 258, 259, 261, 262, + 2023, 1678, 933, 264, -615, -615, -615, -615, -615, -615, + -615, -615, -615, -615, -615, -615, -615, -615, 247, 247, + 2023, 2023, 2023, 2023, 2023, -615, 265, 267, 268, 269, + 258, 270, 2023, -615, 250, 1105, -74, -615, -615, 271, + 272, 399, 6, -615, 1939, -615, 416, -615, 34, 1637, + -37, -615, -70, -615, -615, 424, 429, 1449, 283, 285, + 287, 288, 1449, 450, 1449, 293, 295, 1449, 301, 36, + -615, 302, 303, 464, 465, 306, 2023, 1449, 1449, 36, + 1449, 310, 2023, -615, -615, -1, 313, 320, 321, 325, + 107, 2023, 2023, 2023, 2023, 108, 2023, -615, -615, 341, + 2023, 2023, 2023, 476, 501, -615, 247, -615, 36, 349, + 352, 351, -615, 350, -60, -615, -615, 1449, 1449, 361, + 1449, 1449, 1449, 1449, 310, -615, 310, 2023, 1449, 359, + 2023, 2023, 2023, -615, -615, 520, 933, -615, -615, 364, + 472, -615, 933, -615, 2023, 2023, 2023, 2023, -615, 363, + 366, 365, 368, -615, 258, -615, 371, 375, 4, -615, + -615, -615, 185, 1957, -615, 516, -615, 369, 377, 376, + 2189, -615, -615, -615, -615, -615, -615, -615, 370, 1449, + -615, -615, -615, -615, 258, 2189, 310, 380, 382, 383, + 384, 2023, -615, 2023, 2023, 118, -615, -615, -615, -615, + -615, -615, 36, -2, -615, -615, 530, -5, 41, 36, + 121, -615, 379, 306, 122, -615, -615, -615, -615, -615, + 388, 389, 390, -615, 185, -615, 504, 1449, 1587, -615, + 3, 777, 777, -615, 2230, -615, -615, -615, -615, -615, + -615, 551, 418, -615, 411, 1587, -615, 415, 417, -615, + -615, 473, 41, 36, 556, -615, 557, -615, 560, 419, + 334, 334, 563, 777, 777, -615, 1449, 567, 1449, -615, + -615, -615, 1449, 514, 334, 334, -615, 574, 1449, -615 }; /* YYPGOTO[NTERM-NUM]. */ static const yytype_int16 yypgoto[] = { - -624, 132, 155, 181, -165, -154, 0, -86, -143, 474, - -624, 6, -624, -624, -624, -624, 67, -624, -624, -624, - -142, -624, -499, -624, -252, -624, -231, -624, -624, -313, - -63, -624, -434, -624, -624, -26, 342, -152, -624, 458, - 463, -11, -156, -242, 202, 244, 332, -624, -624, 554, - -624, -624, -624, -624, -624, -624, -624, -624, -624, -624, - -624, 485, -624, -624, -624, -624, -624, -624, -623, -79, - 213, -193, -624, -624, 520, -624, 445, -624, -624, -624, - -34, 129, -448, -624, 456, -624, -624 + -615, 156, 164, 166, -159, -157, 0, -61, -135, 508, + -615, 8, -615, -615, -615, -615, 60, -615, -615, -615, + -138, -615, -405, -615, -253, -615, -236, -615, -615, -311, + -31, -615, -418, -615, -615, -26, 374, -150, -615, 491, + 500, -114, -156, -239, 221, 257, 367, -615, -615, 590, + -615, -615, -615, -615, -615, -615, -615, -615, -615, -615, + -615, 518, -615, -615, -615, -615, -615, -615, -614, -108, + 186, -192, -615, -615, 553, -615, 478, -615, -615, -615, + -3, 158, -447, -615, 487, -615, -615 }; /* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If positive, shift that token. If negative, reduce the rule which number is the opposite. If zero, do what YYDEFACT says. If YYTABLE_NINF, syntax error. */ -#define YYTABLE_NINF -218 +#define YYTABLE_NINF -220 static const yytype_int16 yytable[] = { - 11, 82, 272, 321, 656, 673, 13, 416, 357, 279, - 523, 105, 511, 512, 111, 162, 274, 11, 325, 326, - 327, 328, 329, 13, 376, 378, 91, 317, 335, 531, - 288, 490, 111, 672, 94, 111, 408, 590, 111, 318, - 492, 460, 146, 111, 146, 111, 460, 24, 465, 532, - 687, 147, 109, 236, 111, 466, 64, 65, 111, 107, - 67, 68, 69, 70, 71, 72, 73, 21, 1, 2, - 111, 3, 4, 5, 491, 25, 138, 243, 460, 273, - 109, 336, 22, 491, 431, 460, 138, 527, 26, 361, - 131, 363, 155, 11, 544, 460, 27, 358, 359, 74, - 589, 362, 1, 364, 595, 3, 460, 5, 84, 85, - 159, 119, 120, 543, -149, 89, 233, 234, 112, 285, - 237, 90, 50, 51, 52, 286, 241, 53, 354, 2, - 28, 652, 4, 464, 623, 155, 112, 659, 660, 112, - 240, 135, 112, 282, 353, 433, 136, 112, 418, 112, - 531, -61, 413, -61, 476, 478, 480, 163, 112, 571, - 657, 674, 112, 44, 641, 415, -61, 60, 319, 320, - 282, 322, 337, 338, 112, 626, 95, 106, 688, 689, - 58, 691, 692, 59, 323, 282, 282, 282, 282, 282, - 330, 331, 332, 333, 334, 282, 569, 1, 702, 703, - 3, 62, 5, 402, 460, 138, 402, 402, 402, 461, - 46, 482, 47, 75, 76, 339, 155, 77, -149, 78, - 108, 91, -149, 460, 38, 39, 40, 496, 540, 498, - 499, 500, 339, 64, 65, 542, 86, 98, 87, 603, - 116, 604, 117, 402, 99, 1, 2, 100, 3, 4, - 5, 402, 402, 402, 402, 402, 485, 435, 436, 437, - 438, 576, 439, 555, 219, 219, 440, 441, 103, 442, - 443, 444, 581, 409, 563, 651, 102, 563, 661, 508, - 662, 104, 340, 341, 664, 384, 662, 220, 220, 87, - 410, 411, 412, 122, 123, 124, 125, 126, 127, 340, - 341, 643, 342, 343, 142, 344, 345, 272, 346, 347, - 348, 432, 282, 221, 221, 143, 151, 152, 148, 342, - 343, 150, 344, 345, 160, 346, 347, 348, 114, 115, - 402, 402, 402, 402, 165, 229, 231, 232, 235, 402, - 238, 29, 30, 31, 32, 33, 34, 35, 36, 463, - 37, 239, 242, 402, 453, 454, 455, 456, 457, 458, - 459, 631, 605, 111, 280, 608, 609, 610, 287, 467, - 468, 469, 355, 379, 356, 365, 366, 367, 282, 368, - 369, 404, 155, 370, 273, 419, 371, 380, 381, 382, - 430, 434, 448, 449, 282, 497, 282, 282, 282, 420, - 421, 422, 423, 424, 507, 155, 402, 450, 451, 452, - 472, 402, 481, 402, 473, 470, 402, 483, 484, 495, - 501, 502, 513, 504, 505, 506, 402, 402, 510, 402, - 679, 519, 520, 682, 521, 522, 524, 526, 514, 515, - 516, 517, 528, 529, 530, 539, 536, 545, 546, 525, - 548, 463, 549, 550, 551, 38, 39, 40, 555, 553, - 556, 561, 558, 559, 560, 562, 402, 402, 563, 402, - 402, 402, 402, 568, 572, 587, 573, 402, 564, 574, - 690, 575, 588, 591, 570, 402, 592, 583, 598, 593, - 607, 402, 594, 611, 613, 491, 619, 620, 405, 406, - 407, 621, 622, 624, 586, 625, 632, 633, 577, 578, - 579, 580, 634, 582, 635, 639, 644, 584, 585, 645, - 646, 647, 655, 665, 666, 663, 667, 669, 402, 282, - 683, 684, 282, 282, 282, 417, 686, -18, 693, -19, - 694, 696, 700, 425, 426, 427, 428, 429, 289, 290, - 291, 292, 293, 294, 295, 296, 297, 298, 695, 705, - 706, 615, 616, 617, 618, 630, 668, 132, 653, 145, - 149, 45, 637, 351, 360, 130, 402, 97, 227, 642, - 402, 402, 518, 435, 436, 437, 438, 637, 439, 228, - 627, 0, 440, 441, 0, 442, 443, 444, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 648, 0, - 649, 650, 402, 402, 0, 402, 0, 402, 0, 0, - 0, 402, 486, 487, 488, 489, 0, 402, 0, 0, - 0, 494, 0, 0, 64, 65, 681, 107, 67, 68, - 69, 70, 71, 72, 73, 509, 1, 2, 0, 3, - 4, 5, 627, 0, 0, 0, 64, 65, 0, 107, - 67, 68, 69, 70, 71, 72, 73, 0, 1, 2, - 0, 3, 4, 5, 0, 0, 0, 74, 0, 0, - 435, 436, 437, 438, 0, 439, 0, 0, 137, 440, - 441, 0, 442, 443, 444, 0, 0, 0, 547, 74, - 0, 0, 0, 552, 0, 554, 0, 0, 557, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 565, 566, - 0, 567, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 64, - 65, 0, 107, 67, 68, 69, 70, 71, 72, 73, - 0, 1, 2, 0, 3, 4, 5, 0, 596, 597, - 0, 599, 600, 601, 602, 0, 0, 0, 0, 606, - 0, 0, 0, 0, 0, 0, 0, 612, 0, 0, - 0, 0, 74, 614, 0, 0, 0, 0, 0, 0, - 0, 75, 76, 0, 0, 77, 0, 78, 144, 0, - 0, 0, 0, 0, 0, 385, 386, 387, 388, 64, - 65, 389, 0, 75, 76, -217, 0, 77, 0, 78, - 640, 1, 2, 0, 3, 4, 5, 390, 391, 392, - 0, 0, 0, -63, 1, 2, 0, 3, 4, 5, - 0, 0, 393, 394, 0, 6, 7, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 339, 0, 0, 0, - 0, 395, 0, 0, 0, 0, 0, 8, 671, 0, - 0, 9, 677, 678, 0, 10, 0, 175, 176, 177, - 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, - 188, 189, 254, 255, 256, 257, 75, 76, 0, 0, - 77, 0, 78, 377, 697, 698, 0, 699, 0, 701, - 0, 0, 0, 704, 0, 0, 0, 0, 0, 707, - 0, 258, 198, 675, 676, 201, 202, 203, 204, 205, - 206, 207, 208, 209, 0, 259, 0, 260, 261, 262, - 0, 263, 264, 342, 343, 0, 344, 345, 0, 346, - 347, 348, 0, 0, 0, 0, 0, 0, 0, 385, - 386, 387, 388, 64, 65, 389, 0, 396, 0, 0, - 397, 0, 398, 0, 399, 1, 2, 0, 3, 4, - 5, 390, 391, 392, 300, 301, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 393, 394, 0, 0, + 11, 82, 272, 357, 321, 105, 658, 159, 13, 416, + 91, 279, 162, 525, 675, 111, 111, 11, 94, 325, + 326, 327, 328, 329, 274, 13, 111, 376, 378, 335, + 513, 514, 533, 317, 288, 408, 318, 240, 492, 494, + 533, 111, 146, 21, 674, 44, 146, 462, 243, 27, + 273, 147, 109, 24, 111, 236, 468, 26, 22, 111, + 534, 689, 64, 65, 29, 30, 31, 32, 33, 34, + 35, 36, 131, 37, 1, 2, 138, 3, 4, 5, + 109, 493, 493, 431, 1, 336, 138, 3, 25, 5, + 462, 111, 155, 11, 462, 361, -151, 363, 362, 529, + 364, 84, 85, 546, 462, 358, 359, 28, 89, 111, + 135, 111, 462, 597, 90, 136, 233, 234, 591, 467, + 237, 112, 112, 285, 60, 2, 241, 462, 4, 286, + 353, 354, 112, 592, 545, 155, 466, 625, 418, 435, + 436, 437, 438, 282, 439, 462, 433, 112, 440, 441, + 463, 442, 443, 444, 445, 446, 163, 478, 480, 482, + 112, 573, 95, 62, 659, 112, 628, 643, 319, 320, + 282, 322, 676, 106, 402, 119, 120, 402, 402, 402, + 38, 39, 40, 58, 323, 282, 282, 282, 282, 282, + 330, 331, 332, 333, 334, 282, 59, 112, 462, 91, + 571, -61, -151, 542, 1, 138, -151, 3, 46, 5, + 47, 86, 484, 87, 402, 112, 155, 112, 413, -61, + 415, -61, 402, 402, 402, 402, 402, 654, 498, 98, + 500, 501, 502, 661, 662, 99, 50, 51, 52, 339, + 544, 53, 116, 605, 117, 606, 38, 39, 40, 337, + 338, 455, 456, 457, 458, 459, 460, 461, 487, 122, + 123, 124, 125, 126, 127, 100, 469, 470, 471, 578, + 583, 557, 565, 409, 690, 691, 102, 693, 694, 103, + 653, 510, 565, 663, 666, 664, 664, 384, 219, 219, + 410, 411, 412, 104, 704, 705, 220, 220, 221, 221, + 87, 402, 402, 402, 402, 645, 340, 341, 142, 272, + 402, 432, 282, 289, 290, 291, 292, 293, 294, 295, + 296, 297, 298, 143, 402, 150, 342, 343, 148, 344, + 345, 160, 346, 347, 348, 151, 152, 516, 517, 518, + 519, 114, 115, 165, 229, 231, 232, 238, 527, 465, + 235, 239, 242, 111, 280, 287, 365, 273, 633, 355, + 356, 379, 366, 367, 368, 607, 369, 370, 610, 611, + 612, 371, 380, 381, 430, 382, 434, 475, 282, 402, + 404, 419, 155, 450, 402, 451, 402, 420, 339, 402, + 421, 422, 423, 424, 282, 499, 282, 282, 282, 402, + 402, 452, 402, 453, 509, 155, 454, 579, 580, 581, + 582, 472, 584, 474, 483, 485, 586, 587, 486, 503, + 497, 528, 504, 506, 515, 507, 508, 681, 512, 521, + 684, 522, 523, 524, 526, 530, 531, 532, 541, 402, + 402, 547, 402, 402, 402, 402, 548, 550, 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385, 386, 387, 388, + 64, 65, 389, 0, 396, 0, 0, 397, 0, 398, + 0, 399, 1, 2, 0, 3, 4, 5, 390, 391, + 392, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 393, 394, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 111, 0, + 64, 65, 395, 107, 67, 68, 69, 70, 71, 72, + 73, 0, 1, 2, 0, 3, 4, 5, 175, 176, + 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, + 187, 188, 189, 254, 255, 256, 257, 0, 0, 0, + 0, 0, 0, 74, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 258, 198, 199, 200, 201, - 202, 203, 204, 205, 206, 207, 208, 209, 0, 259, - 0, 260, 261, 262, 0, 263, 264, 0, 0, 0, + 0, 0, 258, 198, 199, 200, 201, 202, 203, 204, + 205, 206, 207, 208, 209, 0, 259, 0, 260, 261, + 262, 0, 263, 264, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 112, 0, 0, 0, -61, - 0, 265, 0, 0, 266, 0, 267, 0, 268, 244, - 245, 246, 247, 64, 65, 248, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 2, 0, 3, 4, - 5, 249, 250, 251, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 252, 253, 0, 75, - 76, 0, 0, 77, 0, 78, 479, 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73, 0, 1, 2, 0, 3, 4, 5, 64, 65, 0, 107, 67, 68, - 69, 70, 71, 72, 73, 0, 1, 2, 0, 3, - 4, 5, 0, 0, 0, 0, 0, 64, 65, 74, - 107, 67, 68, 69, 70, 71, 72, 73, 0, 1, - 2, 0, 3, 4, 5, 64, 65, 74, 107, 67, - 68, 69, 70, 71, 72, 73, 0, 1, 2, 535, - 3, 4, 5, 0, 0, 0, 0, 0, 0, 0, - 74, 0, 0, 0, 0, 0, 0, 629, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 74, 0, + 69, 70, 71, 72, 73, 0, 1, 2, 537, 3, + 4, 5, 75, 76, 0, 0, 77, 0, 78, 74, + 0, 0, 0, 0, 0, 0, 631, 0, 0, 0, + 0, 0, 0, 0, 0, 64, 65, 74, 66, 67, + 68, 69, 70, 71, 72, 73, 0, 1, 2, 0, + 3, 4, 5, 75, 76, 0, 372, 77, 0, 78, + 64, 65, 0, 107, 67, 68, 69, 70, 71, 72, + 73, 0, 1, 2, 0, 3, 4, 5, 74, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 75, 76, 0, 0, 77, 0, 78, 64, - 65, 0, 66, 67, 68, 69, 70, 71, 72, 73, - 0, 1, 2, 0, 3, 4, 5, 0, 0, 0, + 0, 0, 0, 0, 75, 76, 0, 477, 77, 0, + 78, 64, 65, 74, 281, 67, 68, 69, 70, 71, + 72, 73, 0, 1, 2, 0, 3, 4, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 75, 76, 0, 372, 77, 0, 78, - 0, 0, 74, 0, 0, 0, 0, 0, 0, 0, - 0, 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0, 0, 77, - 0, 78, 0, 0, 0, -63, 1, 2, 0, 3, - 4, 5, 0, 0, 0, 0, 0, 6, 7, 0, + 78, 64, 65, 74, 107, 67, 68, 69, 70, 71, + 72, 73, 0, 1, 2, 0, 3, 4, 5, 75, + 76, 0, 0, 77, 0, 78, 64, 65, 0, 107, + 67, 68, 69, 70, 71, 72, 638, 0, 1, 2, + 0, 3, 4, 5, 74, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 75, 76, 0, 0, 77, 0, 78, 64, 65, 74, + 107, 67, 68, 69, 70, 71, 72, 682, 0, 1, + 2, 0, 3, 4, 5, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 74, 0, 0, 0, 0, 0, 0, 0, 0, 75, + 76, 0, 0, 77, 0, 375, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, - 75, 76, 0, 9, 77, 0, 375, 10, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 75, 76, - 0, 0, 77, 0, 477, 0, 0, 0, 0, 0, - 0, 0, 0, 166, 0, 0, 0, 0, 0, 0, - 0, 75, 76, 0, 0, 77, 0, 78, 0, 0, - 0, 0, 0, 0, 167, 168, 0, 0, 0, 75, - 76, 0, 0, 77, 0, 78, 169, 170, 171, 172, - 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, - 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, - 193, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 194, 195, 196, 0, 0, 197, 198, 199, 200, - 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, - 211, 212, 213, 214, 215, 216, 217, 218 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 166, + 75, 76, 0, 0, 77, 0, 479, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 167, 168, 0, 0, 0, 75, 76, 0, 0, 77, + 0, 78, 169, 170, 171, 172, 173, 174, 175, 176, + 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, + 187, 188, 189, 190, 191, 192, 193, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 75, 76, 0, 0, + 77, 0, 78, 0, 0, 0, 0, 194, 195, 196, + 0, 0, 197, 198, 199, 200, 201, 202, 203, 204, + 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, + 215, 216, 217, 218 }; static const yytype_int16 yycheck[] = { - 0, 27, 158, 196, 11, 11, 0, 320, 239, 161, - 458, 4, 446, 447, 55, 28, 159, 17, 211, 212, - 213, 214, 215, 17, 266, 267, 21, 192, 221, 34, - 172, 11, 55, 656, 29, 55, 288, 536, 55, 193, - 11, 162, 162, 55, 162, 55, 162, 161, 169, 54, - 673, 171, 78, 171, 55, 171, 7, 8, 55, 10, - 11, 12, 13, 14, 15, 16, 17, 53, 19, 20, - 55, 22, 23, 24, 54, 59, 102, 156, 162, 158, - 106, 223, 68, 54, 336, 162, 112, 171, 161, 254, - 7, 256, 118, 93, 171, 162, 18, 240, 241, 50, - 534, 255, 19, 257, 171, 22, 162, 24, 41, 42, - 121, 32, 33, 169, 55, 48, 142, 143, 159, 11, - 146, 54, 42, 43, 44, 17, 152, 47, 169, 20, - 161, 630, 23, 375, 582, 161, 159, 636, 637, 159, - 151, 162, 159, 169, 167, 338, 167, 159, 165, 159, - 34, 163, 162, 163, 396, 397, 398, 170, 159, 160, - 167, 167, 159, 0, 612, 162, 163, 165, 194, 195, - 196, 197, 117, 118, 159, 160, 171, 170, 677, 678, - 161, 680, 681, 161, 210, 211, 212, 213, 214, 215, - 216, 217, 218, 219, 220, 221, 509, 19, 697, 698, - 22, 22, 24, 282, 162, 231, 285, 286, 287, 167, - 46, 404, 48, 164, 165, 54, 242, 168, 159, 170, - 171, 21, 163, 162, 156, 157, 158, 420, 167, 422, - 423, 424, 54, 7, 8, 477, 35, 22, 37, 552, - 42, 554, 44, 322, 22, 19, 20, 22, 22, 23, - 24, 330, 331, 332, 333, 334, 408, 141, 142, 143, - 144, 160, 146, 162, 132, 133, 150, 151, 4, 153, - 154, 155, 160, 299, 162, 160, 159, 162, 160, 431, - 162, 4, 121, 122, 160, 279, 162, 132, 133, 37, - 316, 317, 318, 62, 63, 64, 65, 66, 67, 121, - 122, 614, 141, 142, 166, 144, 145, 463, 147, 148, - 149, 337, 338, 132, 133, 166, 114, 115, 159, 141, - 142, 163, 144, 145, 4, 147, 148, 149, 84, 85, - 409, 410, 411, 412, 161, 22, 162, 160, 169, 418, - 4, 42, 43, 44, 45, 46, 47, 48, 49, 375, - 51, 160, 159, 432, 365, 366, 367, 368, 369, 370, - 371, 592, 555, 55, 57, 558, 559, 560, 11, 380, - 381, 382, 169, 22, 160, 159, 159, 159, 404, 159, - 159, 162, 408, 159, 463, 162, 159, 159, 159, 159, - 38, 4, 38, 159, 420, 421, 422, 423, 424, 162, - 162, 162, 162, 162, 430, 431, 485, 159, 159, 159, - 159, 490, 22, 492, 61, 162, 495, 162, 162, 165, - 162, 162, 448, 162, 162, 162, 505, 506, 162, 508, - 661, 162, 162, 664, 162, 162, 162, 169, 449, 450, - 451, 452, 162, 162, 38, 22, 472, 17, 17, 460, - 162, 477, 162, 162, 162, 156, 157, 158, 162, 4, - 162, 4, 162, 162, 162, 4, 545, 546, 162, 548, - 549, 550, 551, 162, 162, 22, 162, 556, 504, 162, - 38, 162, 4, 162, 510, 564, 160, 169, 159, 162, - 162, 570, 169, 4, 159, 54, 162, 160, 285, 286, - 287, 162, 162, 160, 530, 160, 22, 169, 519, 520, - 521, 522, 162, 524, 165, 167, 160, 528, 529, 160, - 160, 160, 17, 160, 160, 167, 160, 54, 607, 555, - 4, 152, 558, 559, 560, 322, 162, 159, 22, 159, - 17, 17, 17, 330, 331, 332, 333, 334, 94, 95, - 96, 97, 98, 99, 100, 101, 102, 103, 162, 73, - 17, 572, 573, 574, 575, 591, 652, 93, 631, 106, - 112, 17, 598, 231, 242, 90, 655, 57, 133, 613, - 659, 660, 453, 141, 142, 143, 144, 613, 146, 133, - 590, -1, 150, 151, -1, 153, 154, 155, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, 619, -1, - 621, 622, 691, 692, -1, 694, -1, 696, -1, -1, - -1, 700, 409, 410, 411, 412, -1, 706, -1, -1, - -1, 418, -1, -1, 7, 8, 662, 10, 11, 12, - 13, 14, 15, 16, 17, 432, 19, 20, -1, 22, - 23, 24, 652, -1, -1, -1, 7, 8, -1, 10, - 11, 12, 13, 14, 15, 16, 17, -1, 19, 20, - -1, 22, 23, 24, -1, -1, -1, 50, -1, -1, - 141, 142, 143, 144, -1, 146, -1, -1, 39, 150, - 151, -1, 153, 154, 155, -1, -1, -1, 485, 50, - -1, -1, -1, 490, -1, 492, -1, -1, 495, -1, - -1, -1, -1, -1, -1, -1, -1, -1, 505, 506, - -1, 508, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, -1, 7, - 8, -1, 10, 11, 12, 13, 14, 15, 16, 17, - -1, 19, 20, -1, 22, 23, 24, -1, 545, 546, - -1, 548, 549, 550, 551, -1, -1, -1, -1, 556, - -1, -1, -1, -1, -1, -1, -1, 564, -1, -1, - -1, -1, 50, 570, -1, -1, -1, -1, -1, -1, - -1, 164, 165, -1, -1, 168, -1, 170, 171, -1, - -1, -1, -1, -1, -1, 3, 4, 5, 6, 7, - 8, 9, -1, 164, 165, 0, -1, 168, -1, 170, - 607, 19, 20, -1, 22, 23, 24, 25, 26, 27, - -1, -1, -1, 18, 19, 20, -1, 22, 23, 24, - -1, -1, 40, 41, -1, 30, 31, -1, -1, -1, - -1, -1, -1, -1, -1, -1, 54, -1, -1, -1, - -1, 59, -1, -1, -1, -1, -1, 52, 655, -1, - -1, 56, 659, 660, -1, 60, -1, 75, 76, 77, - 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, - 88, 89, 90, 91, 92, 93, 164, 165, -1, -1, - 168, -1, 170, 171, 691, 692, -1, 694, -1, 696, - -1, -1, -1, 700, -1, -1, -1, -1, -1, 706, - -1, 119, 120, 121, 122, 123, 124, 125, 126, 127, - 128, 129, 130, 131, -1, 133, -1, 135, 136, 137, - -1, 139, 140, 141, 142, -1, 144, 145, -1, 147, - 148, 149, -1, -1, -1, -1, -1, -1, -1, 3, - 4, 5, 6, 7, 8, 9, -1, 165, -1, -1, - 168, -1, 170, -1, 172, 19, 20, -1, 22, 23, - 24, 25, 26, 27, 26, 27, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, 40, 41, -1, -1, + 0, 27, 158, 239, 196, 4, 11, 121, 0, 320, + 21, 161, 28, 460, 11, 55, 55, 17, 29, 211, + 212, 213, 214, 215, 159, 17, 55, 266, 267, 221, + 448, 449, 34, 192, 172, 288, 193, 151, 11, 11, + 34, 55, 164, 53, 658, 0, 164, 164, 156, 18, + 158, 173, 78, 163, 55, 173, 173, 163, 68, 55, + 54, 675, 7, 8, 42, 43, 44, 45, 46, 47, + 48, 49, 7, 51, 19, 20, 102, 22, 23, 24, + 106, 54, 54, 336, 19, 223, 112, 22, 59, 24, + 164, 55, 118, 93, 164, 254, 55, 256, 255, 173, + 257, 41, 42, 173, 164, 240, 241, 163, 48, 55, + 164, 55, 164, 173, 54, 169, 142, 143, 536, 171, + 146, 161, 161, 11, 167, 20, 152, 164, 23, 17, + 169, 171, 161, 538, 171, 161, 375, 584, 167, 141, + 142, 143, 144, 169, 146, 164, 338, 161, 150, 151, + 169, 153, 154, 155, 156, 157, 172, 396, 397, 398, + 161, 162, 173, 22, 169, 161, 162, 614, 194, 195, + 196, 197, 169, 172, 282, 32, 33, 285, 286, 287, + 158, 159, 160, 163, 210, 211, 212, 213, 214, 215, + 216, 217, 218, 219, 220, 221, 163, 161, 164, 21, + 511, 165, 161, 169, 19, 231, 165, 22, 46, 24, + 48, 35, 404, 37, 322, 161, 242, 161, 164, 165, + 164, 165, 330, 331, 332, 333, 334, 632, 420, 22, + 422, 423, 424, 638, 639, 22, 42, 43, 44, 54, + 479, 47, 42, 554, 44, 556, 158, 159, 160, 117, + 118, 365, 366, 367, 368, 369, 370, 371, 408, 62, + 63, 64, 65, 66, 67, 22, 380, 381, 382, 162, + 162, 164, 164, 299, 679, 680, 161, 682, 683, 4, + 162, 431, 164, 162, 162, 164, 164, 279, 132, 133, + 316, 317, 318, 4, 699, 700, 132, 133, 132, 133, + 37, 409, 410, 411, 412, 616, 121, 122, 168, 465, + 418, 337, 338, 94, 95, 96, 97, 98, 99, 100, + 101, 102, 103, 168, 432, 165, 141, 142, 161, 144, + 145, 4, 147, 148, 149, 114, 115, 451, 452, 453, + 454, 84, 85, 163, 22, 164, 162, 4, 462, 375, + 171, 162, 161, 55, 57, 11, 161, 465, 594, 171, + 162, 22, 161, 161, 161, 557, 161, 161, 560, 561, + 562, 161, 161, 161, 38, 161, 4, 61, 404, 487, + 164, 164, 408, 38, 492, 161, 494, 164, 54, 497, + 164, 164, 164, 164, 420, 421, 422, 423, 424, 507, + 508, 161, 510, 161, 430, 431, 161, 521, 522, 523, + 524, 164, 526, 161, 22, 164, 530, 531, 164, 164, + 167, 171, 164, 164, 450, 164, 164, 663, 164, 164, + 666, 164, 164, 164, 164, 164, 164, 38, 22, 547, + 548, 17, 550, 551, 552, 553, 17, 164, 474, 164, + 558, 164, 164, 479, 4, 121, 122, 164, 566, 164, + 574, 575, 576, 577, 572, 164, 164, 164, 4, 4, + 164, 285, 286, 287, 164, 141, 142, 164, 144, 145, + 506, 147, 148, 149, 164, 164, 512, 7, 8, 164, + 10, 11, 12, 13, 14, 15, 16, 17, 22, 19, + 20, 609, 22, 23, 24, 4, 532, 621, 322, 623, + 624, 38, 171, 164, 162, 164, 330, 331, 332, 333, + 334, 171, 161, 164, 4, 161, 54, 164, 162, 164, + 50, 557, 164, 162, 560, 561, 562, 162, 22, 169, + 171, 164, 162, 167, 162, 162, 162, 17, 169, 657, + 162, 162, 162, 661, 662, 4, 7, 8, 54, 10, + 11, 12, 13, 14, 15, 16, 17, 593, 19, 20, + 152, 22, 23, 24, 600, 164, 161, 17, 161, 22, + 17, 26, 27, 164, 17, 693, 694, 73, 696, 615, + 698, 17, 592, 654, 702, 409, 410, 411, 412, 50, + 708, 93, 633, 112, 418, 231, 106, 17, 90, 242, + 57, 133, 615, 455, 141, 142, 143, 144, 432, 146, + 133, -1, -1, 150, 151, -1, 153, 154, 155, 156, + 157, -1, -1, -1, -1, -1, -1, -1, 664, -1, + -1, -1, -1, -1, -1, -1, 166, 167, -1, -1, + 170, -1, 172, 173, 654, 100, 101, 102, 103, 104, + 105, 106, 107, 108, 109, 110, 111, 112, 113, -1, + -1, -1, -1, 487, -1, -1, -1, -1, 492, -1, + 494, -1, -1, 497, -1, -1, -1, -1, -1, -1, + -1, -1, -1, 507, 508, -1, 510, 141, 142, 143, + 144, -1, 146, -1, -1, -1, 150, 151, -1, 153, + 154, 155, 156, 157, -1, 166, 167, -1, -1, 170, + -1, 172, 173, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, 547, 548, -1, 550, 551, 552, 553, + -1, -1, -1, -1, 558, -1, -1, -1, -1, -1, + -1, -1, 566, -1, -1, -1, -1, -1, 572, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, 55, -1, 7, 8, 59, 10, 11, 12, 13, - 14, 15, 16, 17, -1, 19, 20, -1, 22, 23, - 24, 75, 76, 77, 78, 79, 80, 81, 82, 83, - 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, - -1, -1, -1, -1, -1, -1, 50, -1, 100, 101, - 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, - 112, 113, -1, -1, -1, 119, 120, 121, 122, 123, - 124, 125, 126, 127, 128, 129, 130, 131, -1, 133, - -1, 135, 136, 137, -1, 139, 140, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, 159, -1, -1, -1, -1, - -1, 165, -1, -1, 168, -1, 170, -1, 172, 3, - 4, 5, 6, 7, 8, 9, -1, -1, -1, -1, - -1, -1, -1, -1, -1, 19, 20, -1, 22, 23, - 24, 25, 26, 27, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, 40, 41, -1, -1, - 164, 165, -1, -1, 168, -1, 170, 171, -1, -1, - -1, 55, 7, 8, -1, 10, 11, 12, 13, 14, - 15, 16, 17, -1, 19, 20, -1, 22, 23, 24, - -1, 75, 76, 77, 78, 79, 80, 81, 82, 83, - 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, - -1, -1, -1, -1, -1, 50, -1, -1, -1, -1, + 3, 4, 5, 6, 7, 8, 9, -1, -1, 0, + -1, -1, -1, -1, -1, 609, 19, 20, -1, 22, + 23, 24, 25, 26, 27, -1, -1, 18, 19, 20, + -1, 22, 23, 24, -1, -1, -1, 40, 41, 30, + 31, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, 54, -1, -1, -1, -1, 59, -1, -1, -1, + -1, 52, -1, 657, -1, 56, -1, 661, 662, 60, + -1, -1, 75, 76, 77, 78, 79, 80, 81, 82, + 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, + 93, -1, -1, -1, -1, -1, -1, -1, -1, 693, + 694, -1, 696, -1, 698, -1, -1, -1, 702, -1, + -1, -1, -1, -1, 708, -1, 119, 120, 121, 122, + 123, 124, 125, 126, 127, 128, 129, 130, 131, -1, + 133, -1, 135, 136, 137, -1, 139, 140, 141, 142, + -1, 144, 145, -1, 147, 148, 149, -1, -1, -1, + -1, -1, -1, -1, -1, -1, 3, 4, 5, 6, + 7, 8, 9, -1, 167, -1, -1, 170, -1, 172, + -1, 174, 19, 20, -1, 22, 23, 24, 25, 26, + 27, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, 40, 41, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, 55, -1, + 7, 8, 59, 10, 11, 12, 13, 14, 15, 16, + 17, -1, 19, 20, -1, 22, 23, 24, 75, 76, + 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, + 87, 88, 89, 90, 91, 92, 93, -1, -1, -1, + -1, -1, -1, 50, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, 119, 120, 121, 122, 123, 124, 125, 126, + 127, 128, 129, 130, 131, -1, 133, -1, 135, 136, + 137, -1, 139, 140, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, 161, -1, -1, -1, -1, -1, + 167, -1, -1, 170, -1, 172, -1, 174, 3, 4, + 5, 6, 7, 8, 9, -1, -1, -1, -1, -1, + -1, -1, -1, -1, 19, 20, -1, 22, 23, 24, + 25, 26, 27, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, 40, 41, -1, -1, 166, + 167, -1, -1, 170, -1, 172, 173, -1, -1, -1, + 55, 7, 8, -1, 10, 11, 12, 13, 14, 15, + 16, 17, -1, 19, 20, -1, 22, 23, 24, -1, + 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, + 85, 86, 87, 88, 89, 90, 91, 92, 93, -1, + -1, -1, -1, -1, 50, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, 119, 120, 121, 122, 123, 124, + 125, 126, 127, 128, 129, 130, 131, -1, 133, -1, + 135, 136, 137, -1, 139, 140, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, 119, 120, 121, 122, 123, - 124, 125, 126, 127, 128, 129, 130, 131, -1, 133, - -1, 135, 136, 137, -1, 139, 140, -1, -1, -1, + -1, -1, -1, -1, -1, -1, 161, -1, -1, -1, + 165, -1, 167, -1, -1, 170, -1, 172, -1, 174, + 3, 4, 5, 6, 7, 8, 9, -1, -1, -1, + -1, -1, -1, -1, -1, -1, 19, 20, -1, 22, + 23, 24, 25, 26, 27, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, 40, 41, -1, + 166, 167, -1, -1, 170, -1, 172, 173, -1, -1, + -1, -1, 55, 7, 8, -1, 10, 11, 12, 13, + 14, 15, 16, 17, -1, 19, 20, -1, 22, 23, + 24, -1, 75, 76, 77, 78, 79, 80, 81, 82, + 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, + 93, -1, -1, -1, -1, -1, 50, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, 159, -1, -1, -1, 163, - -1, 165, -1, -1, 168, -1, 170, -1, 172, 3, - 4, 5, 6, 7, 8, 9, -1, -1, -1, -1, - -1, -1, -1, -1, -1, 19, 20, -1, 22, 23, - 24, 25, 26, 27, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, 40, 41, -1, 164, - 165, -1, -1, 168, -1, 170, 171, -1, -1, -1, - -1, 55, 7, 8, -1, 10, 11, 12, 13, 14, - 15, 16, 17, -1, 19, 20, -1, 22, 23, 24, - -1, 75, 76, 77, 78, 79, 80, 81, 82, 83, - 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, - -1, -1, -1, -1, -1, 50, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, 119, 120, 121, 122, + 123, 124, 125, 126, 127, 128, 129, 130, 131, -1, + 133, -1, 135, 136, 137, -1, 139, 140, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, 161, -1, + -1, -1, -1, -1, 167, -1, -1, 170, -1, 172, + -1, 174, 3, 4, 5, 6, 7, 8, 9, -1, + -1, -1, -1, -1, -1, -1, -1, -1, 19, 20, + -1, 22, 23, 24, 25, 26, 27, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, 40, + 41, 0, 166, 167, -1, -1, 170, -1, 172, 173, + -1, -1, -1, -1, -1, -1, -1, -1, 59, 18, + 19, 20, -1, 22, 23, 24, -1, -1, -1, -1, + -1, 30, 31, -1, 75, 76, 77, 78, 79, 80, + 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, + 91, 92, 93, 52, -1, -1, -1, 56, -1, -1, + -1, 60, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, 119, 120, + 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, + 131, -1, 133, -1, 135, 136, 137, -1, 139, 140, + 3, 4, 5, 6, -1, -1, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, 119, 120, 121, 122, 123, - 124, 125, 126, 127, 128, 129, 130, 131, -1, 133, - -1, 135, 136, 137, -1, 139, 140, -1, -1, -1, + -1, -1, 25, 26, 27, -1, 167, -1, -1, 170, + -1, 172, -1, 174, -1, -1, -1, 40, 41, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, 159, -1, -1, -1, -1, - -1, 165, -1, -1, 168, -1, 170, -1, 172, 3, - 4, 5, 6, 7, 8, 9, -1, -1, -1, -1, - -1, -1, -1, -1, -1, 19, 20, -1, 22, 23, - 24, 25, 26, 27, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, 40, 41, -1, 164, - 165, -1, -1, 168, -1, 170, 171, -1, -1, -1, - -1, -1, -1, 7, 8, 59, 10, 11, 12, 13, + -1, -1, -1, -1, 7, 8, 59, 10, 11, 12, + 13, 14, 15, 16, 17, -1, 19, 20, -1, 22, + 23, 24, 75, 76, 77, 78, 79, 80, 81, 82, + 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, + 93, -1, -1, -1, -1, 7, 8, 50, 10, 11, + 12, 13, 14, 15, 16, 17, -1, 19, 20, -1, + 22, 23, 24, -1, -1, -1, 119, 120, 121, 122, + 123, 124, 125, 126, 127, 128, 129, 130, 131, -1, + 133, -1, 135, 136, 137, -1, 139, 140, 50, -1, + 7, 8, -1, 10, 11, 12, 13, 14, 15, 16, + 17, -1, 19, 20, -1, 22, 23, 24, -1, -1, + -1, -1, -1, -1, 167, -1, -1, 170, -1, 172, + -1, 174, 39, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, 50, 7, 8, -1, 10, 11, 12, + 13, 14, 15, 16, 17, -1, 19, 20, -1, 22, + 23, 24, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, 166, 167, -1, -1, 170, -1, 172, + 173, -1, -1, -1, -1, -1, -1, 50, -1, 141, + 142, -1, 144, 7, 8, -1, 10, 11, 12, 13, 14, 15, 16, 17, -1, 19, 20, -1, 22, 23, - 24, 75, 76, 77, 78, 79, 80, 81, 82, 83, - 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, + 24, -1, -1, -1, 166, 167, -1, -1, 170, -1, + 172, -1, -1, -1, -1, 39, -1, -1, -1, -1, -1, -1, -1, -1, 7, 8, 50, 10, 11, 12, 13, 14, 15, 16, 17, -1, 19, 20, -1, 22, - 23, 24, -1, -1, -1, 119, 120, 121, 122, 123, - 124, 125, 126, 127, 128, 129, 130, 131, -1, 133, - -1, 135, 136, 137, -1, 139, 140, 50, -1, -1, - -1, -1, -1, -1, -1, -1, -1, 3, 4, 5, - 6, -1, -1, 9, -1, -1, -1, -1, -1, -1, - -1, 165, -1, -1, 168, -1, 170, -1, 172, 25, - 26, 27, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, 40, 41, -1, 141, 142, -1, - 144, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, 59, -1, -1, -1, -1, -1, -1, - 164, 165, 125, -1, 168, -1, 170, -1, -1, 75, - 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, - 86, 87, 88, 89, 90, 91, 92, 93, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, 164, 165, -1, -1, 168, -1, 170, -1, -1, - -1, -1, -1, 119, 120, 121, 122, 123, 124, 125, - 126, 127, 128, 129, 130, 131, -1, 133, -1, 135, - 136, 137, -1, 139, 140, 7, 8, -1, 10, 11, + 23, 24, -1, -1, -1, -1, -1, -1, -1, 166, + 167, -1, 125, 170, -1, 172, -1, -1, -1, -1, + -1, -1, -1, -1, -1, 7, 8, 50, 10, 11, 12, 13, 14, 15, 16, 17, -1, 19, 20, -1, - 22, 23, 24, -1, -1, -1, -1, -1, -1, 165, - -1, -1, 168, -1, 170, -1, 172, 39, -1, -1, + 22, 23, 24, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, 166, 167, -1, -1, 170, -1, 172, -1, -1, -1, -1, -1, -1, 7, 8, 50, 10, 11, 12, 13, 14, 15, 16, 17, -1, 19, 20, -1, 22, 23, 24, 7, 8, -1, 10, 11, 12, - 13, 14, 15, 16, 17, -1, 19, 20, -1, 22, - 23, 24, -1, -1, -1, -1, -1, 7, 8, 50, + 13, 14, 15, 16, 17, -1, 19, 20, 39, 22, + 23, 24, 166, 167, -1, -1, 170, -1, 172, 50, + -1, -1, -1, -1, -1, -1, 39, -1, -1, -1, + -1, -1, -1, -1, -1, 7, 8, 50, 10, 11, + 12, 13, 14, 15, 16, 17, -1, 19, 20, -1, + 22, 23, 24, 166, 167, -1, 169, 170, -1, 172, + 7, 8, -1, 10, 11, 12, 13, 14, 15, 16, + 17, -1, 19, 20, -1, 22, 23, 24, 50, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, 166, 167, -1, 169, 170, -1, + 172, 7, 8, 50, 10, 11, 12, 13, 14, 15, + 16, 17, -1, 19, 20, -1, 22, 23, 24, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, 166, 167, -1, -1, 170, + -1, 172, -1, -1, 50, -1, -1, -1, -1, -1, + -1, -1, -1, 166, 167, -1, -1, 170, -1, 172, + 7, 8, -1, 10, 11, 12, 13, 14, 15, 16, + 17, -1, 19, 20, -1, 22, 23, 24, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, 166, 167, -1, -1, 170, -1, + 172, 7, 8, 50, 10, 11, 12, 13, 14, 15, + 16, 17, -1, 19, 20, -1, 22, 23, 24, 166, + 167, -1, -1, 170, -1, 172, 7, 8, -1, 10, + 11, 12, 13, 14, 15, 16, 17, -1, 19, 20, + -1, 22, 23, 24, 50, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + 166, 167, -1, -1, 170, -1, 172, 7, 8, 50, 10, 11, 12, 13, 14, 15, 16, 17, -1, 19, - 20, -1, 22, 23, 24, 7, 8, 50, 10, 11, - 12, 13, 14, 15, 16, 17, -1, 19, 20, 39, - 22, 23, 24, -1, -1, -1, -1, -1, -1, -1, - 50, -1, -1, -1, -1, -1, -1, 39, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, 50, -1, + 20, -1, 22, 23, 24, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, 164, 165, -1, -1, 168, -1, 170, 7, - 8, -1, 10, 11, 12, 13, 14, 15, 16, 17, - -1, 19, 20, -1, 22, 23, 24, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, 164, 165, -1, 167, 168, -1, 170, - -1, -1, 50, -1, -1, -1, -1, -1, -1, -1, - -1, 164, 165, -1, 167, 168, -1, 170, -1, -1, + 50, -1, -1, -1, -1, -1, -1, -1, -1, 166, + 167, -1, -1, 170, -1, 172, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, 164, 165, -1, -1, 168, -1, - 170, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, 164, 165, -1, -1, 168, -1, 170, 7, - 8, -1, 10, 11, 12, 13, 14, 15, 16, 17, - -1, 19, 20, -1, 22, 23, 24, -1, 7, 8, - -1, 10, 11, 12, 13, 14, 15, 16, 17, -1, - 19, 20, -1, 22, 23, 24, -1, -1, -1, -1, - -1, -1, 50, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, 164, 165, -1, -1, - 168, 50, 170, 7, 8, -1, 10, 11, 12, 13, - 14, 15, 16, 17, -1, 19, 20, -1, 22, 23, - 24, 7, 8, -1, 10, 11, 12, 13, 14, 15, - 16, 17, -1, 19, 20, -1, 22, 23, 24, -1, - -1, -1, -1, -1, 7, 8, 50, 10, 11, 12, - 13, 14, 15, 16, 17, -1, 19, 20, -1, 22, - 23, 24, 7, 8, 50, 10, 11, 12, 13, 14, - 15, 16, 17, -1, 19, 20, -1, 22, 23, 24, - -1, -1, -1, -1, -1, -1, -1, 50, -1, -1, - -1, -1, -1, -1, -1, -1, 164, 165, -1, -1, - 168, -1, 170, -1, -1, 50, -1, 0, -1, -1, - -1, -1, -1, -1, -1, 164, 165, -1, -1, 168, - -1, 170, -1, -1, -1, 18, 19, 20, -1, 22, - 23, 24, -1, -1, -1, -1, -1, 30, 31, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, -1, 52, - 164, 165, -1, 56, 168, -1, 170, 60, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, 164, 165, - -1, -1, 168, -1, 170, -1, -1, -1, -1, -1, - -1, -1, -1, 36, -1, -1, -1, -1, -1, -1, - -1, 164, 165, -1, -1, 168, -1, 170, -1, -1, - -1, -1, -1, -1, 57, 58, -1, -1, -1, 164, - 165, -1, -1, 168, -1, 170, 69, 70, 71, 72, - 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, - 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, - 93, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, 36, + 166, 167, -1, -1, 170, -1, 172, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, 114, 115, 116, -1, -1, 119, 120, 121, 122, - 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, - 133, 134, 135, 136, 137, 138, 139, 140 + 57, 58, -1, -1, -1, 166, 167, -1, -1, 170, + -1, 172, 69, 70, 71, 72, 73, 74, 75, 76, + 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, + 87, 88, 89, 90, 91, 92, 93, -1, -1, -1, + -1, -1, -1, -1, -1, -1, 166, 167, -1, -1, + 170, -1, 172, -1, -1, -1, -1, 114, 115, 116, + -1, -1, 119, 120, 121, 122, 123, 124, 125, 126, + 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, + 137, 138, 139, 140 }; /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing @@ -2769,76 +2789,76 @@ static const yytype_uint16 yystos[] = { 0, 19, 20, 22, 23, 24, 30, 31, 52, 56, - 60, 179, 182, 184, 185, 186, 220, 221, 222, 224, - 223, 53, 68, 229, 161, 59, 161, 18, 161, 42, - 43, 44, 45, 46, 47, 48, 49, 51, 156, 157, - 158, 187, 188, 189, 0, 222, 46, 48, 190, 239, - 42, 43, 44, 47, 191, 236, 238, 246, 161, 161, - 165, 230, 22, 228, 7, 8, 10, 11, 12, 13, - 14, 15, 16, 17, 50, 164, 165, 168, 170, 179, - 184, 207, 208, 242, 189, 189, 35, 37, 218, 189, - 189, 21, 247, 248, 29, 171, 237, 247, 22, 22, - 22, 231, 159, 4, 4, 4, 170, 10, 171, 208, - 213, 55, 159, 181, 218, 218, 42, 44, 192, 32, - 33, 217, 62, 63, 64, 65, 66, 67, 193, 234, - 234, 7, 182, 183, 251, 162, 167, 39, 208, 209, - 211, 212, 166, 166, 171, 213, 162, 171, 159, 212, - 163, 217, 217, 10, 125, 208, 210, 219, 208, 214, - 4, 197, 28, 170, 235, 161, 36, 57, 58, 69, + 60, 181, 184, 186, 187, 188, 222, 223, 224, 226, + 225, 53, 68, 231, 163, 59, 163, 18, 163, 42, + 43, 44, 45, 46, 47, 48, 49, 51, 158, 159, + 160, 189, 190, 191, 0, 224, 46, 48, 192, 241, + 42, 43, 44, 47, 193, 238, 240, 248, 163, 163, + 167, 232, 22, 230, 7, 8, 10, 11, 12, 13, + 14, 15, 16, 17, 50, 166, 167, 170, 172, 181, + 186, 209, 210, 244, 191, 191, 35, 37, 220, 191, + 191, 21, 249, 250, 29, 173, 239, 249, 22, 22, + 22, 233, 161, 4, 4, 4, 172, 10, 173, 210, + 215, 55, 161, 183, 220, 220, 42, 44, 194, 32, + 33, 219, 62, 63, 64, 65, 66, 67, 195, 236, + 236, 7, 184, 185, 253, 164, 169, 39, 210, 211, + 213, 214, 168, 168, 173, 215, 164, 173, 161, 214, + 165, 219, 219, 10, 125, 210, 212, 221, 210, 216, + 4, 199, 28, 172, 237, 163, 36, 57, 58, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 114, 115, 116, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, - 132, 133, 134, 135, 136, 137, 138, 139, 140, 174, - 175, 176, 249, 256, 257, 258, 259, 249, 257, 22, - 195, 162, 160, 208, 208, 169, 171, 208, 4, 160, - 214, 208, 159, 242, 3, 4, 5, 6, 9, 25, + 132, 133, 134, 135, 136, 137, 138, 139, 140, 176, + 177, 178, 251, 258, 259, 260, 261, 251, 259, 22, + 197, 164, 162, 210, 210, 171, 173, 210, 4, 162, + 216, 210, 161, 244, 3, 4, 5, 6, 9, 25, 26, 27, 40, 41, 90, 91, 92, 93, 119, 133, - 135, 136, 137, 139, 140, 165, 168, 170, 172, 174, - 175, 176, 215, 242, 181, 141, 142, 144, 196, 210, - 57, 10, 208, 244, 245, 11, 17, 11, 193, 94, - 95, 96, 97, 98, 99, 100, 101, 102, 103, 177, + 135, 136, 137, 139, 140, 167, 170, 172, 174, 176, + 177, 178, 217, 244, 183, 141, 142, 144, 198, 212, + 57, 10, 210, 246, 247, 11, 17, 11, 195, 94, + 95, 96, 97, 98, 99, 100, 101, 102, 103, 179, 26, 27, 100, 101, 102, 103, 104, 105, 106, 107, - 108, 109, 110, 111, 112, 113, 178, 177, 178, 208, - 208, 244, 208, 208, 252, 244, 244, 244, 244, 244, - 208, 208, 208, 208, 208, 244, 193, 117, 118, 54, - 121, 122, 141, 142, 144, 145, 147, 148, 149, 194, - 39, 209, 199, 167, 169, 169, 160, 199, 181, 181, - 219, 177, 178, 177, 178, 159, 159, 159, 159, 159, - 159, 159, 167, 214, 216, 170, 216, 171, 216, 22, - 159, 159, 159, 225, 184, 3, 4, 5, 6, 9, - 25, 26, 27, 40, 41, 59, 165, 168, 170, 172, - 215, 241, 242, 243, 162, 243, 243, 243, 197, 208, - 208, 208, 208, 162, 202, 162, 202, 243, 165, 162, - 162, 162, 162, 162, 162, 243, 243, 243, 243, 243, - 38, 197, 208, 244, 4, 141, 142, 143, 144, 146, - 150, 151, 153, 154, 155, 198, 226, 227, 38, 159, - 159, 159, 159, 214, 214, 214, 214, 214, 214, 214, - 162, 167, 171, 208, 216, 169, 171, 214, 214, 214, - 162, 205, 159, 61, 240, 167, 216, 170, 216, 171, - 216, 22, 244, 162, 162, 210, 243, 243, 243, 243, - 11, 54, 11, 254, 243, 165, 244, 208, 244, 244, - 244, 162, 162, 255, 162, 162, 162, 208, 210, 243, - 162, 205, 205, 208, 214, 214, 214, 214, 254, 162, - 162, 162, 162, 255, 162, 214, 169, 171, 162, 162, - 38, 34, 54, 203, 206, 39, 208, 232, 233, 22, - 167, 171, 216, 169, 171, 17, 17, 243, 162, 162, - 162, 162, 243, 4, 243, 162, 162, 243, 162, 162, - 162, 4, 4, 162, 208, 243, 243, 243, 162, 202, - 208, 160, 162, 162, 162, 162, 160, 214, 214, 214, - 214, 160, 214, 169, 214, 214, 208, 22, 4, 205, - 195, 162, 160, 162, 169, 171, 243, 243, 159, 243, - 243, 243, 243, 202, 202, 244, 243, 162, 244, 244, - 244, 4, 243, 159, 243, 214, 214, 214, 214, 162, - 160, 162, 162, 255, 160, 160, 160, 179, 180, 39, - 208, 199, 22, 169, 162, 165, 17, 208, 253, 167, - 243, 255, 253, 202, 160, 160, 160, 160, 214, 214, - 214, 160, 195, 203, 204, 17, 11, 167, 250, 195, - 195, 160, 162, 167, 160, 160, 160, 160, 180, 54, - 201, 243, 241, 11, 167, 121, 122, 243, 243, 199, - 17, 208, 199, 4, 152, 200, 162, 241, 195, 195, - 38, 195, 195, 22, 17, 162, 17, 243, 243, 243, - 17, 243, 195, 195, 243, 73, 17, 243 + 108, 109, 110, 111, 112, 113, 180, 179, 180, 210, + 210, 246, 210, 210, 254, 246, 246, 246, 246, 246, + 210, 210, 210, 210, 210, 246, 195, 117, 118, 54, + 121, 122, 141, 142, 144, 145, 147, 148, 149, 196, + 39, 211, 201, 169, 171, 171, 162, 201, 183, 183, + 221, 179, 180, 179, 180, 161, 161, 161, 161, 161, + 161, 161, 169, 216, 218, 172, 218, 173, 218, 22, + 161, 161, 161, 227, 186, 3, 4, 5, 6, 9, + 25, 26, 27, 40, 41, 59, 167, 170, 172, 174, + 217, 243, 244, 245, 164, 245, 245, 245, 199, 210, + 210, 210, 210, 164, 204, 164, 204, 245, 167, 164, + 164, 164, 164, 164, 164, 245, 245, 245, 245, 245, + 38, 199, 210, 246, 4, 141, 142, 143, 144, 146, + 150, 151, 153, 154, 155, 156, 157, 200, 228, 229, + 38, 161, 161, 161, 161, 216, 216, 216, 216, 216, + 216, 216, 164, 169, 173, 210, 218, 171, 173, 216, + 216, 216, 164, 207, 161, 61, 242, 169, 218, 172, + 218, 173, 218, 22, 246, 164, 164, 212, 245, 245, + 245, 245, 11, 54, 11, 256, 245, 167, 246, 210, + 246, 246, 246, 164, 164, 257, 164, 164, 164, 210, + 212, 245, 164, 207, 207, 210, 216, 216, 216, 216, + 256, 164, 164, 164, 164, 257, 164, 216, 171, 173, + 164, 164, 38, 34, 54, 205, 208, 39, 210, 234, + 235, 22, 169, 173, 218, 171, 173, 17, 17, 245, + 164, 164, 164, 164, 245, 4, 245, 164, 164, 245, + 164, 164, 164, 4, 4, 164, 210, 245, 245, 245, + 164, 204, 210, 162, 164, 164, 164, 164, 162, 216, + 216, 216, 216, 162, 216, 171, 216, 216, 210, 22, + 4, 207, 197, 164, 162, 164, 171, 173, 245, 245, + 161, 245, 245, 245, 245, 204, 204, 246, 245, 164, + 246, 246, 246, 4, 245, 161, 245, 216, 216, 216, + 216, 164, 162, 164, 164, 257, 162, 162, 162, 181, + 182, 39, 210, 201, 22, 171, 164, 167, 17, 210, + 255, 169, 245, 257, 255, 204, 162, 162, 162, 162, + 216, 216, 216, 162, 197, 205, 206, 17, 11, 169, + 252, 197, 197, 162, 164, 169, 162, 162, 162, 162, + 182, 54, 203, 245, 243, 11, 169, 121, 122, 245, + 245, 201, 17, 210, 201, 4, 152, 202, 164, 243, + 197, 197, 38, 197, 197, 22, 17, 164, 17, 245, + 245, 245, 17, 245, 197, 197, 245, 73, 17, 245 }; #define yyerrok (yyerrstatus = 0) @@ -2912,7 +2932,7 @@ we won't break user code: when these are the locations we know. */ #ifndef YY_LOCATION_PRINT -# if YYLTYPE_IS_TRIVIAL +# if defined YYLTYPE_IS_TRIVIAL && YYLTYPE_IS_TRIVIAL # define YY_LOCATION_PRINT(File, Loc) \ fprintf (File, "%d.%d-%d.%d", \ (Loc).first_line, (Loc).first_column, \ @@ -3653,152 +3673,152 @@ switch (yyn) { case 29: -#line 1158 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1158 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_EQ; ;} break; case 30: -#line 1158 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1158 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_NE; ;} break; case 31: -#line 1159 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1159 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_SLT; ;} break; case 32: -#line 1159 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1159 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_SGT; ;} break; case 33: -#line 1160 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1160 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_SLE; ;} break; case 34: -#line 1160 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1160 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_SGE; ;} break; case 35: -#line 1161 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1161 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_ULT; ;} break; case 36: -#line 1161 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1161 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_UGT; ;} break; case 37: -#line 1162 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1162 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_ULE; ;} break; case 38: -#line 1162 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1162 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_UGE; ;} break; case 39: -#line 1166 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1166 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_OEQ; ;} break; case 40: -#line 1166 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1166 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_ONE; ;} break; case 41: -#line 1167 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1167 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_OLT; ;} break; case 42: -#line 1167 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1167 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_OGT; ;} break; case 43: -#line 1168 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1168 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_OLE; ;} break; case 44: -#line 1168 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1168 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_OGE; ;} break; case 45: -#line 1169 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1169 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_ORD; ;} break; case 46: -#line 1169 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1169 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_UNO; ;} break; case 47: -#line 1170 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1170 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_UEQ; ;} break; case 48: -#line 1170 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1170 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_UNE; ;} break; case 49: -#line 1171 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1171 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_ULT; ;} break; case 50: -#line 1171 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1171 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_UGT; ;} break; case 51: -#line 1172 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1172 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_ULE; ;} break; case 52: -#line 1172 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1172 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_UGE; ;} break; case 53: -#line 1173 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1173 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_TRUE; ;} break; case 54: -#line 1174 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1174 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_FALSE; ;} break; case 59: -#line 1178 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1178 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.StrVal) = 0; ;} break; case 60: -#line 1180 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1180 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal)=(yyvsp[(3) - (4)].UInt64Val); ;} break; case 61: -#line 1181 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1181 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal)=0; ;} break; case 62: -#line 1185 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1185 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.StrVal) = (yyvsp[(1) - (2)].StrVal); CHECK_FOR_ERROR @@ -3806,7 +3826,7 @@ break; case 63: -#line 1189 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1189 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.StrVal) = 0; CHECK_FOR_ERROR @@ -3814,7 +3834,7 @@ break; case 64: -#line 1194 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1194 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = (yyvsp[(1) - (2)].UIntVal); CHECK_FOR_ERROR @@ -3822,7 +3842,7 @@ break; case 68: -#line 1203 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1203 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.StrVal) = 0; CHECK_FOR_ERROR @@ -3830,7 +3850,7 @@ break; case 69: -#line 1208 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1208 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.StrVal) = (yyvsp[(1) - (2)].StrVal); CHECK_FOR_ERROR @@ -3838,157 +3858,157 @@ break; case 70: -#line 1214 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1214 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::InternalLinkage; ;} break; case 71: -#line 1215 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1215 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::WeakLinkage; ;} break; case 72: -#line 1216 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1216 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::LinkOnceLinkage; ;} break; case 73: -#line 1217 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1217 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::AppendingLinkage; ;} break; case 74: -#line 1218 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1218 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::DLLExportLinkage; ;} break; case 75: -#line 1219 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1219 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::CommonLinkage; ;} break; case 76: -#line 1223 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1223 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::DLLImportLinkage; ;} break; case 77: -#line 1224 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1224 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::ExternalWeakLinkage; ;} break; case 78: -#line 1225 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1225 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::ExternalLinkage; ;} break; case 79: -#line 1229 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1229 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Visibility) = GlobalValue::DefaultVisibility; ;} break; case 80: -#line 1230 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1230 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Visibility) = GlobalValue::DefaultVisibility; ;} break; case 81: -#line 1231 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1231 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Visibility) = GlobalValue::HiddenVisibility; ;} break; case 82: -#line 1232 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1232 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Visibility) = GlobalValue::ProtectedVisibility; ;} break; case 83: -#line 1236 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1236 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::ExternalLinkage; ;} break; case 84: -#line 1237 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1237 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::DLLImportLinkage; ;} break; case 85: -#line 1238 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1238 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::ExternalWeakLinkage; ;} break; case 86: -#line 1242 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1242 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::ExternalLinkage; ;} break; case 87: -#line 1243 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1243 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::InternalLinkage; ;} break; case 88: -#line 1244 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1244 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::LinkOnceLinkage; ;} break; case 89: -#line 1245 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1245 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::WeakLinkage; ;} break; case 90: -#line 1246 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1246 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::DLLExportLinkage; ;} break; case 91: -#line 1250 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1250 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::ExternalLinkage; ;} break; case 92: -#line 1251 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1251 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::WeakLinkage; ;} break; case 93: -#line 1252 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1252 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::InternalLinkage; ;} break; case 94: -#line 1255 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1255 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = CallingConv::C; ;} break; case 95: -#line 1256 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1256 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = CallingConv::C; ;} break; case 96: -#line 1257 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1257 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = CallingConv::Fast; ;} break; case 97: -#line 1258 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1258 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = CallingConv::Cold; ;} break; case 98: -#line 1259 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1259 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = CallingConv::X86_StdCall; ;} break; case 99: -#line 1260 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1260 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = CallingConv::X86_FastCall; ;} break; case 100: -#line 1261 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1261 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if ((unsigned)(yyvsp[(2) - (2)].UInt64Val) != (yyvsp[(2) - (2)].UInt64Val)) GEN_ERROR("Calling conv too large"); @@ -3998,176 +4018,186 @@ break; case 101: -#line 1268 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1268 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::ZExt; ;} break; case 102: -#line 1269 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1269 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::ZExt; ;} break; case 103: -#line 1270 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1270 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::SExt; ;} break; case 104: -#line 1271 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1271 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::SExt; ;} break; case 105: -#line 1272 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1272 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::InReg; ;} break; case 106: -#line 1273 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1273 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::StructRet; ;} break; case 107: -#line 1274 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1274 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::NoAlias; ;} break; case 108: -#line 1275 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1275 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::ByVal; ;} break; case 109: -#line 1276 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1276 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::Nest; ;} break; case 110: -#line 1277 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1277 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::constructAlignmentFromInt((yyvsp[(2) - (2)].UInt64Val)); ;} break; case 111: -#line 1281 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1281 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::None; ;} break; case 112: -#line 1282 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1282 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = (yyvsp[(1) - (2)].Attributes) | (yyvsp[(2) - (2)].Attributes); ;} break; case 113: -#line 1287 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1287 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::InReg; ;} break; case 114: -#line 1288 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1288 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::ZExt; ;} break; case 115: -#line 1289 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1289 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::SExt; ;} break; case 116: -#line 1292 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1292 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::None; ;} break; case 117: -#line 1293 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1293 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = (yyvsp[(1) - (2)].Attributes) | (yyvsp[(2) - (2)].Attributes); ;} break; case 118: -#line 1299 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1299 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::NoReturn; ;} break; case 119: -#line 1300 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1300 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::NoUnwind; ;} break; case 120: -#line 1301 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1301 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::InReg; ;} break; case 121: -#line 1302 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1302 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::ZExt; ;} break; case 122: -#line 1303 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1303 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::SExt; ;} break; case 123: -#line 1304 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1304 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::ReadNone; ;} break; case 124: -#line 1305 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1305 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::ReadOnly; ;} break; case 125: -#line 1306 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1306 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::NoInline; ;} break; case 126: -#line 1307 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1307 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::AlwaysInline; ;} break; case 127: -#line 1308 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1308 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = Attribute::OptimizeForSize; ;} break; case 128: -#line 1311 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" - { (yyval.Attributes) = Attribute::None; ;} +#line 1309 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" + { (yyval.Attributes) = Attribute::StackProtect; ;} break; case 129: -#line 1312 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1310 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" + { (yyval.Attributes) = Attribute::StackProtectReq; ;} + break; + + case 130: +#line 1313 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" + { (yyval.Attributes) = Attribute::None; ;} + break; + + case 131: +#line 1314 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.Attributes) = (yyvsp[(1) - (2)].Attributes) | (yyvsp[(2) - (2)].Attributes); ;} break; - case 130: -#line 1318 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 132: +#line 1320 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.StrVal) = 0; ;} break; - case 131: -#line 1319 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 133: +#line 1321 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.StrVal) = (yyvsp[(2) - (2)].StrVal); ;} break; - case 132: -#line 1326 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 134: +#line 1328 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = 0; ;} break; - case 133: -#line 1327 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 135: +#line 1329 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = (yyvsp[(2) - (2)].UInt64Val); if ((yyval.UIntVal) != 0 && !isPowerOf2_32((yyval.UIntVal))) @@ -4176,13 +4206,13 @@ ;} break; - case 134: -#line 1333 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 136: +#line 1335 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = 0; ;} break; - case 135: -#line 1334 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 137: +#line 1336 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = (yyvsp[(3) - (3)].UInt64Val); if ((yyval.UIntVal) != 0 && !isPowerOf2_32((yyval.UIntVal))) @@ -4191,8 +4221,8 @@ ;} break; - case 136: -#line 1343 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 138: +#line 1345 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { for (unsigned i = 0, e = (yyvsp[(2) - (2)].StrVal)->length(); i != e; ++i) if ((*(yyvsp[(2) - (2)].StrVal))[i] == '"' || (*(yyvsp[(2) - (2)].StrVal))[i] == '\\') @@ -4202,28 +4232,28 @@ ;} break; - case 137: -#line 1351 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 139: +#line 1353 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.StrVal) = 0; ;} break; - case 138: -#line 1352 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 140: +#line 1354 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.StrVal) = (yyvsp[(1) - (1)].StrVal); ;} break; - case 139: -#line 1357 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 141: +#line 1359 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" {;} break; - case 140: -#line 1358 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 142: +#line 1360 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" {;} break; - case 141: -#line 1359 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 143: +#line 1361 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CurGV->setSection(*(yyvsp[(1) - (1)].StrVal)); delete (yyvsp[(1) - (1)].StrVal); @@ -4231,8 +4261,8 @@ ;} break; - case 142: -#line 1364 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 144: +#line 1366 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if ((yyvsp[(2) - (2)].UInt64Val) != 0 && !isPowerOf2_32((yyvsp[(2) - (2)].UInt64Val))) GEN_ERROR("Alignment must be a power of two"); @@ -4241,24 +4271,24 @@ ;} break; - case 150: -#line 1380 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 152: +#line 1382 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeVal) = new PATypeHolder(OpaqueType::get()); CHECK_FOR_ERROR ;} break; - case 151: -#line 1384 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 153: +#line 1386 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeVal) = new PATypeHolder((yyvsp[(1) - (1)].PrimType)); CHECK_FOR_ERROR ;} break; - case 152: -#line 1388 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 154: +#line 1390 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Pointer type? if (*(yyvsp[(1) - (3)].TypeVal) == Type::LabelTy) GEN_ERROR("Cannot form a pointer to a basic block"); @@ -4268,8 +4298,8 @@ ;} break; - case 153: -#line 1395 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 155: +#line 1397 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Named types are also simple types... const Type* tmp = getTypeVal((yyvsp[(1) - (1)].ValIDVal)); CHECK_FOR_ERROR @@ -4277,8 +4307,8 @@ ;} break; - case 154: -#line 1400 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 156: +#line 1402 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Type UpReference if ((yyvsp[(2) - (2)].UInt64Val) > (uint64_t)~0U) GEN_ERROR("Value out of range"); OpaqueType *OT = OpaqueType::get(); // Use temporary placeholder @@ -4289,8 +4319,8 @@ ;} break; - case 155: -#line 1408 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 157: +#line 1410 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Allow but ignore attributes on function types; this permits auto-upgrade. // FIXME: remove in LLVM 3.0. @@ -4328,8 +4358,8 @@ ;} break; - case 156: -#line 1443 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 158: +#line 1445 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Allow but ignore attributes on function types; this permits auto-upgrade. // FIXME: remove in LLVM 3.0. @@ -4362,8 +4392,8 @@ ;} break; - case 157: -#line 1474 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 159: +#line 1476 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Sized array type? (yyval.TypeVal) = new PATypeHolder(HandleUpRefs(ArrayType::get(*(yyvsp[(4) - (5)].TypeVal), (yyvsp[(2) - (5)].UInt64Val)))); delete (yyvsp[(4) - (5)].TypeVal); @@ -4371,8 +4401,8 @@ ;} break; - case 158: -#line 1479 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 160: +#line 1481 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Vector type? const llvm::Type* ElemTy = (yyvsp[(4) - (5)].TypeVal)->get(); if ((unsigned)(yyvsp[(2) - (5)].UInt64Val) != (yyvsp[(2) - (5)].UInt64Val)) @@ -4385,8 +4415,8 @@ ;} break; - case 159: -#line 1489 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 161: +#line 1491 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Structure type? std::vector Elements; for (std::list::iterator I = (yyvsp[(2) - (3)].TypeList)->begin(), @@ -4399,16 +4429,16 @@ ;} break; - case 160: -#line 1499 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 162: +#line 1501 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Empty structure type? (yyval.TypeVal) = new PATypeHolder(StructType::get(std::vector())); CHECK_FOR_ERROR ;} break; - case 161: -#line 1503 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 163: +#line 1505 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { std::vector Elements; for (std::list::iterator I = (yyvsp[(3) - (5)].TypeList)->begin(), @@ -4421,16 +4451,16 @@ ;} break; - case 162: -#line 1513 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 164: +#line 1515 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Empty structure type? (yyval.TypeVal) = new PATypeHolder(StructType::get(std::vector(), true)); CHECK_FOR_ERROR ;} break; - case 163: -#line 1520 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 165: +#line 1522 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Allow but ignore attributes on function types; this permits auto-upgrade. // FIXME: remove in LLVM 3.0. @@ -4439,8 +4469,8 @@ ;} break; - case 164: -#line 1529 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 166: +#line 1531 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (1)].TypeVal))->getDescription()); @@ -4450,15 +4480,15 @@ ;} break; - case 165: -#line 1536 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 167: +#line 1538 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeVal) = new PATypeHolder(Type::VoidTy); ;} break; - case 166: -#line 1541 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 168: +#line 1543 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeWithAttrsList) = new TypeWithAttrsList(); (yyval.TypeWithAttrsList)->push_back((yyvsp[(1) - (1)].TypeWithAttrs)); @@ -4466,16 +4496,16 @@ ;} break; - case 167: -#line 1546 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 169: +#line 1548 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { ((yyval.TypeWithAttrsList)=(yyvsp[(1) - (3)].TypeWithAttrsList))->push_back((yyvsp[(3) - (3)].TypeWithAttrs)); CHECK_FOR_ERROR ;} break; - case 169: -#line 1554 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 171: +#line 1556 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeWithAttrsList)=(yyvsp[(1) - (3)].TypeWithAttrsList); TypeWithAttrs TWA; TWA.Attrs = Attribute::None; @@ -4485,8 +4515,8 @@ ;} break; - case 170: -#line 1561 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 172: +#line 1563 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeWithAttrsList) = new TypeWithAttrsList; TypeWithAttrs TWA; TWA.Attrs = Attribute::None; @@ -4496,16 +4526,16 @@ ;} break; - case 171: -#line 1568 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 173: +#line 1570 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeWithAttrsList) = new TypeWithAttrsList(); CHECK_FOR_ERROR ;} break; - case 172: -#line 1576 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 174: +#line 1578 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeList) = new std::list(); (yyval.TypeList)->push_back(*(yyvsp[(1) - (1)].TypeVal)); @@ -4514,8 +4544,8 @@ ;} break; - case 173: -#line 1582 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 175: +#line 1584 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { ((yyval.TypeList)=(yyvsp[(1) - (3)].TypeList))->push_back(*(yyvsp[(3) - (3)].TypeVal)); delete (yyvsp[(3) - (3)].TypeVal); @@ -4523,8 +4553,8 @@ ;} break; - case 174: -#line 1594 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 176: +#line 1596 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Nonempty unsized arr if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (4)].TypeVal))->getDescription()); @@ -4555,8 +4585,8 @@ ;} break; - case 175: -#line 1622 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 177: +#line 1624 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (3)].TypeVal))->getDescription()); @@ -4575,8 +4605,8 @@ ;} break; - case 176: -#line 1638 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 178: +#line 1640 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (3)].TypeVal))->getDescription()); @@ -4606,8 +4636,8 @@ ;} break; - case 177: -#line 1665 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 179: +#line 1667 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Nonempty unsized arr if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (4)].TypeVal))->getDescription()); @@ -4638,8 +4668,8 @@ ;} break; - case 178: -#line 1693 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 180: +#line 1695 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { const StructType *STy = dyn_cast((yyvsp[(1) - (4)].TypeVal)->get()); if (STy == 0) @@ -4668,8 +4698,8 @@ ;} break; - case 179: -#line 1719 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 181: +#line 1721 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (3)].TypeVal))->getDescription()); @@ -4692,8 +4722,8 @@ ;} break; - case 180: -#line 1739 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 182: +#line 1741 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { const StructType *STy = dyn_cast((yyvsp[(1) - (6)].TypeVal)->get()); if (STy == 0) @@ -4722,8 +4752,8 @@ ;} break; - case 181: -#line 1765 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 183: +#line 1767 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (5)].TypeVal))->getDescription()); @@ -4746,8 +4776,8 @@ ;} break; - case 182: -#line 1785 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 184: +#line 1787 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (2)].TypeVal))->getDescription()); @@ -4762,8 +4792,8 @@ ;} break; - case 183: -#line 1797 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 185: +#line 1799 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (2)].TypeVal))->getDescription()); @@ -4773,8 +4803,8 @@ ;} break; - case 184: -#line 1804 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 186: +#line 1806 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (2)].TypeVal))->getDescription()); @@ -4843,8 +4873,8 @@ ;} break; - case 185: -#line 1870 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 187: +#line 1872 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (2)].TypeVal))->getDescription()); @@ -4857,8 +4887,8 @@ ;} break; - case 186: -#line 1880 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 188: +#line 1882 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (2)].TypeVal))->getDescription()); @@ -4871,8 +4901,8 @@ ;} break; - case 187: -#line 1890 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 189: +#line 1892 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // integral constants if (IntegerType *IT = dyn_cast((yyvsp[(1) - (2)].TypeVal)->get())) { if (!ConstantInt::isValueValidForType(IT, (yyvsp[(2) - (2)].SInt64Val))) @@ -4886,8 +4916,8 @@ ;} break; - case 188: -#line 1901 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 190: +#line 1903 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // arbitrary precision integer constants if (IntegerType *IT = dyn_cast((yyvsp[(1) - (2)].TypeVal)->get())) { if ((yyvsp[(2) - (2)].APIntVal)->getBitWidth() > IT->getBitWidth()) @@ -4903,8 +4933,8 @@ ;} break; - case 189: -#line 1914 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 191: +#line 1916 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // integral constants if (IntegerType *IT = dyn_cast((yyvsp[(1) - (2)].TypeVal)->get())) { if (!ConstantInt::isValueValidForType(IT, (yyvsp[(2) - (2)].UInt64Val))) @@ -4918,8 +4948,8 @@ ;} break; - case 190: -#line 1925 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 192: +#line 1927 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // arbitrary precision integer constants if (IntegerType *IT = dyn_cast((yyvsp[(1) - (2)].TypeVal)->get())) { if ((yyvsp[(2) - (2)].APIntVal)->getBitWidth() > IT->getBitWidth()) @@ -4936,8 +4966,8 @@ ;} break; - case 191: -#line 1939 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 193: +#line 1941 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Boolean constants if ((yyvsp[(1) - (2)].TypeVal)->get() != Type::Int1Ty) GEN_ERROR("Constant true must have type i1"); @@ -4947,8 +4977,8 @@ ;} break; - case 192: -#line 1946 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 194: +#line 1948 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Boolean constants if ((yyvsp[(1) - (2)].TypeVal)->get() != Type::Int1Ty) GEN_ERROR("Constant false must have type i1"); @@ -4958,8 +4988,8 @@ ;} break; - case 193: -#line 1953 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 195: +#line 1955 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Floating point constants if (!ConstantFP::isValueValidForType((yyvsp[(1) - (2)].TypeVal)->get(), *(yyvsp[(2) - (2)].FPVal))) GEN_ERROR("Floating point constant invalid for type"); @@ -4978,8 +5008,8 @@ ;} break; - case 194: -#line 1971 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 196: +#line 1973 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(5) - (6)].TypeVal))->getDescription()); @@ -4994,8 +5024,8 @@ ;} break; - case 195: -#line 1983 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 197: +#line 1985 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!isa((yyvsp[(3) - (5)].ConstVal)->getType())) GEN_ERROR("GetElementPtr requires a pointer operand"); @@ -5019,8 +5049,8 @@ ;} break; - case 196: -#line 2004 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 198: +#line 2006 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if ((yyvsp[(3) - (8)].ConstVal)->getType() != Type::Int1Ty) GEN_ERROR("Select condition must be of boolean type"); @@ -5031,8 +5061,8 @@ ;} break; - case 197: -#line 2012 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 199: +#line 2014 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if ((yyvsp[(3) - (6)].ConstVal)->getType() != (yyvsp[(5) - (6)].ConstVal)->getType()) GEN_ERROR("Binary operator types must match"); @@ -5041,8 +5071,8 @@ ;} break; - case 198: -#line 2018 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 200: +#line 2020 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if ((yyvsp[(3) - (6)].ConstVal)->getType() != (yyvsp[(5) - (6)].ConstVal)->getType()) GEN_ERROR("Logical operator types must match"); @@ -5056,8 +5086,8 @@ ;} break; - case 199: -#line 2029 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 201: +#line 2031 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if ((yyvsp[(4) - (7)].ConstVal)->getType() != (yyvsp[(6) - (7)].ConstVal)->getType()) GEN_ERROR("icmp operand types must match"); @@ -5065,8 +5095,8 @@ ;} break; - case 200: -#line 2034 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 202: +#line 2036 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if ((yyvsp[(4) - (7)].ConstVal)->getType() != (yyvsp[(6) - (7)].ConstVal)->getType()) GEN_ERROR("fcmp operand types must match"); @@ -5074,8 +5104,8 @@ ;} break; - case 201: -#line 2039 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 203: +#line 2041 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if ((yyvsp[(4) - (7)].ConstVal)->getType() != (yyvsp[(6) - (7)].ConstVal)->getType()) GEN_ERROR("vicmp operand types must match"); @@ -5083,8 +5113,8 @@ ;} break; - case 202: -#line 2044 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 204: +#line 2046 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if ((yyvsp[(4) - (7)].ConstVal)->getType() != (yyvsp[(6) - (7)].ConstVal)->getType()) GEN_ERROR("vfcmp operand types must match"); @@ -5092,8 +5122,8 @@ ;} break; - case 203: -#line 2049 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 205: +#line 2051 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!ExtractElementInst::isValidOperands((yyvsp[(3) - (6)].ConstVal), (yyvsp[(5) - (6)].ConstVal))) GEN_ERROR("Invalid extractelement operands"); @@ -5102,8 +5132,8 @@ ;} break; - case 204: -#line 2055 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 206: +#line 2057 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!InsertElementInst::isValidOperands((yyvsp[(3) - (8)].ConstVal), (yyvsp[(5) - (8)].ConstVal), (yyvsp[(7) - (8)].ConstVal))) GEN_ERROR("Invalid insertelement operands"); @@ -5112,8 +5142,8 @@ ;} break; - case 205: -#line 2061 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 207: +#line 2063 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!ShuffleVectorInst::isValidOperands((yyvsp[(3) - (8)].ConstVal), (yyvsp[(5) - (8)].ConstVal), (yyvsp[(7) - (8)].ConstVal))) GEN_ERROR("Invalid shufflevector operands"); @@ -5122,8 +5152,8 @@ ;} break; - case 206: -#line 2067 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 208: +#line 2069 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!isa((yyvsp[(3) - (5)].ConstVal)->getType()) && !isa((yyvsp[(3) - (5)].ConstVal)->getType())) GEN_ERROR("ExtractValue requires an aggregate operand"); @@ -5134,8 +5164,8 @@ ;} break; - case 207: -#line 2075 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 209: +#line 2077 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!isa((yyvsp[(3) - (7)].ConstVal)->getType()) && !isa((yyvsp[(3) - (7)].ConstVal)->getType())) GEN_ERROR("InsertValue requires an aggregate operand"); @@ -5146,16 +5176,16 @@ ;} break; - case 208: -#line 2086 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 210: +#line 2088 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { ((yyval.ConstVector) = (yyvsp[(1) - (3)].ConstVector))->push_back((yyvsp[(3) - (3)].ConstVal)); CHECK_FOR_ERROR ;} break; - case 209: -#line 2090 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 211: +#line 2092 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ConstVector) = new std::vector(); (yyval.ConstVector)->push_back((yyvsp[(1) - (1)].ConstVal)); @@ -5163,28 +5193,28 @@ ;} break; - case 210: -#line 2098 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 212: +#line 2100 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = false; ;} break; - case 211: -#line 2098 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 213: +#line 2100 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = true; ;} break; - case 212: -#line 2101 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 214: +#line 2103 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = true; ;} break; - case 213: -#line 2101 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 215: +#line 2103 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = false; ;} break; - case 214: -#line 2104 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 216: +#line 2106 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { const Type* VTy = (yyvsp[(1) - (2)].TypeVal)->get(); Value *V = getVal(VTy, (yyvsp[(2) - (2)].ValIDVal)); @@ -5199,8 +5229,8 @@ ;} break; - case 215: -#line 2116 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 217: +#line 2118 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { Constant *Val = (yyvsp[(3) - (6)].ConstVal); const Type *DestTy = (yyvsp[(5) - (6)].TypeVal)->get(); @@ -5215,8 +5245,8 @@ ;} break; - case 216: -#line 2137 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 218: +#line 2139 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ModuleVal) = ParserResult = CurModule.CurrentModule; CurModule.ModuleDone(); @@ -5224,8 +5254,8 @@ ;} break; - case 217: -#line 2142 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 219: +#line 2144 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ModuleVal) = ParserResult = CurModule.CurrentModule; CurModule.ModuleDone(); @@ -5233,40 +5263,40 @@ ;} break; - case 220: -#line 2155 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 222: +#line 2157 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CurFun.isDeclare = false; ;} break; - case 221: -#line 2155 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 223: +#line 2157 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CurFun.FunctionDone(); CHECK_FOR_ERROR ;} break; - case 222: -#line 2159 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 224: +#line 2161 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CurFun.isDeclare = true; ;} break; - case 223: -#line 2159 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 225: +#line 2161 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CHECK_FOR_ERROR ;} break; - case 224: -#line 2162 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 226: +#line 2164 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CHECK_FOR_ERROR ;} break; - case 225: -#line 2165 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 227: +#line 2167 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (3)].TypeVal))->getDescription()); @@ -5293,8 +5323,8 @@ ;} break; - case 226: -#line 2189 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 228: +#line 2191 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { ResolveTypeTo((yyvsp[(1) - (3)].StrVal), (yyvsp[(3) - (3)].PrimType)); @@ -5308,8 +5338,8 @@ ;} break; - case 227: -#line 2201 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 229: +#line 2203 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { /* "Externally Visible" Linkage */ if ((yyvsp[(5) - (6)].ConstVal) == 0) @@ -5320,15 +5350,15 @@ ;} break; - case 228: -#line 2208 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 230: +#line 2210 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CurGV = 0; ;} break; - case 229: -#line 2212 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 231: +#line 2214 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if ((yyvsp[(6) - (7)].ConstVal) == 0) GEN_ERROR("Global value initializer is not a constant"); @@ -5337,15 +5367,15 @@ ;} break; - case 230: -#line 2217 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 232: +#line 2219 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CurGV = 0; ;} break; - case 231: -#line 2221 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 233: +#line 2223 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(6) - (7)].TypeVal))->getDescription()); @@ -5355,16 +5385,16 @@ ;} break; - case 232: -#line 2227 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 234: +#line 2229 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CurGV = 0; CHECK_FOR_ERROR ;} break; - case 233: -#line 2231 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 235: +#line 2233 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { std::string Name; if ((yyvsp[(1) - (5)].StrVal)) { @@ -5407,22 +5437,22 @@ ;} break; - case 234: -#line 2271 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 236: +#line 2273 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CHECK_FOR_ERROR ;} break; - case 235: -#line 2274 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 237: +#line 2276 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CHECK_FOR_ERROR ;} break; - case 236: -#line 2280 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 238: +#line 2282 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { const std::string &AsmSoFar = CurModule.CurrentModule->getModuleInlineAsm(); if (AsmSoFar.empty()) @@ -5434,24 +5464,24 @@ ;} break; - case 237: -#line 2290 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 239: +#line 2292 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->setTargetTriple(*(yyvsp[(3) - (3)].StrVal)); delete (yyvsp[(3) - (3)].StrVal); ;} break; - case 238: -#line 2294 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 240: +#line 2296 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->setDataLayout(*(yyvsp[(3) - (3)].StrVal)); delete (yyvsp[(3) - (3)].StrVal); ;} break; - case 240: -#line 2301 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 242: +#line 2303 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->addLibrary(*(yyvsp[(3) - (3)].StrVal)); delete (yyvsp[(3) - (3)].StrVal); @@ -5459,8 +5489,8 @@ ;} break; - case 241: -#line 2306 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 243: +#line 2308 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->addLibrary(*(yyvsp[(1) - (1)].StrVal)); delete (yyvsp[(1) - (1)].StrVal); @@ -5468,15 +5498,15 @@ ;} break; - case 242: -#line 2311 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 244: +#line 2313 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CHECK_FOR_ERROR ;} break; - case 243: -#line 2320 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 245: +#line 2322 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (5)].TypeVal))->getDescription()); @@ -5489,8 +5519,8 @@ ;} break; - case 244: -#line 2330 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 246: +#line 2332 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (3)].TypeVal))->getDescription()); @@ -5503,16 +5533,16 @@ ;} break; - case 245: -#line 2341 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 247: +#line 2343 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ArgList) = (yyvsp[(1) - (1)].ArgList); CHECK_FOR_ERROR ;} break; - case 246: -#line 2345 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 248: +#line 2347 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ArgList) = (yyvsp[(1) - (3)].ArgList); struct ArgListEntry E; @@ -5524,8 +5554,8 @@ ;} break; - case 247: -#line 2354 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 249: +#line 2356 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ArgList) = new ArgListType; struct ArgListEntry E; @@ -5537,16 +5567,16 @@ ;} break; - case 248: -#line 2363 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 250: +#line 2365 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ArgList) = 0; CHECK_FOR_ERROR ;} break; - case 249: -#line 2369 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 251: +#line 2371 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { std::string FunctionName(*(yyvsp[(4) - (11)].StrVal)); delete (yyvsp[(4) - (11)].StrVal); // Free strdup'd memory! @@ -5696,8 +5726,8 @@ ;} break; - case 252: -#line 2519 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 254: +#line 2521 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FunctionVal) = CurFun.CurrentFunction; @@ -5708,16 +5738,16 @@ ;} break; - case 255: -#line 2530 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 257: +#line 2532 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FunctionVal) = (yyvsp[(1) - (2)].FunctionVal); CHECK_FOR_ERROR ;} break; - case 256: -#line 2535 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 258: +#line 2537 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CurFun.CurrentFunction->setLinkage((yyvsp[(1) - (3)].Linkage)); CurFun.CurrentFunction->setVisibility((yyvsp[(2) - (3)].Visibility)); @@ -5727,40 +5757,40 @@ ;} break; - case 257: -#line 2547 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 259: +#line 2549 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = false; CHECK_FOR_ERROR ;} break; - case 258: -#line 2551 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 260: +#line 2553 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = true; CHECK_FOR_ERROR ;} break; - case 259: -#line 2556 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 261: +#line 2558 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // A reference to a direct constant (yyval.ValIDVal) = ValID::create((yyvsp[(1) - (1)].SInt64Val)); CHECK_FOR_ERROR ;} break; - case 260: -#line 2560 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 262: +#line 2562 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ValIDVal) = ValID::create((yyvsp[(1) - (1)].UInt64Val)); CHECK_FOR_ERROR ;} break; - case 261: -#line 2564 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 263: +#line 2566 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // arbitrary precision integer constants (yyval.ValIDVal) = ValID::create(*(yyvsp[(1) - (1)].APIntVal), true); delete (yyvsp[(1) - (1)].APIntVal); @@ -5768,8 +5798,8 @@ ;} break; - case 262: -#line 2569 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 264: +#line 2571 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // arbitrary precision integer constants (yyval.ValIDVal) = ValID::create(*(yyvsp[(1) - (1)].APIntVal), false); delete (yyvsp[(1) - (1)].APIntVal); @@ -5777,56 +5807,56 @@ ;} break; - case 263: -#line 2574 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 265: +#line 2576 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Perhaps it's an FP constant? (yyval.ValIDVal) = ValID::create((yyvsp[(1) - (1)].FPVal)); CHECK_FOR_ERROR ;} break; - case 264: -#line 2578 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 266: +#line 2580 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ValIDVal) = ValID::create(ConstantInt::getTrue()); CHECK_FOR_ERROR ;} break; - case 265: -#line 2582 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 267: +#line 2584 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ValIDVal) = ValID::create(ConstantInt::getFalse()); CHECK_FOR_ERROR ;} break; - case 266: -#line 2586 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 268: +#line 2588 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ValIDVal) = ValID::createNull(); CHECK_FOR_ERROR ;} break; - case 267: -#line 2590 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 269: +#line 2592 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ValIDVal) = ValID::createUndef(); CHECK_FOR_ERROR ;} break; - case 268: -#line 2594 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 270: +#line 2596 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // A vector zero constant. (yyval.ValIDVal) = ValID::createZeroInit(); CHECK_FOR_ERROR ;} break; - case 269: -#line 2598 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 271: +#line 2600 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Nonempty unsized packed vector const Type *ETy = (*(yyvsp[(2) - (3)].ConstVector))[0]->getType(); unsigned NumElements = (yyvsp[(2) - (3)].ConstVector)->size(); @@ -5851,8 +5881,8 @@ ;} break; - case 270: -#line 2620 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 272: +#line 2622 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Nonempty unsized arr const Type *ETy = (*(yyvsp[(2) - (3)].ConstVector))[0]->getType(); uint64_t NumElements = (yyvsp[(2) - (3)].ConstVector)->size(); @@ -5877,8 +5907,8 @@ ;} break; - case 271: -#line 2642 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 273: +#line 2644 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Use undef instead of an array because it's inconvenient to determine // the element type at this point, there being no elements to examine. @@ -5887,8 +5917,8 @@ ;} break; - case 272: -#line 2648 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 274: +#line 2650 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { uint64_t NumElements = (yyvsp[(2) - (2)].StrVal)->length(); const Type *ETy = Type::Int8Ty; @@ -5904,8 +5934,8 @@ ;} break; - case 273: -#line 2661 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 275: +#line 2663 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { std::vector Elements((yyvsp[(2) - (3)].ConstVector)->size()); for (unsigned i = 0, e = (yyvsp[(2) - (3)].ConstVector)->size(); i != e; ++i) @@ -5920,8 +5950,8 @@ ;} break; - case 274: -#line 2673 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 276: +#line 2675 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { const StructType *STy = StructType::get(std::vector()); (yyval.ValIDVal) = ValID::create(ConstantStruct::get(STy, std::vector())); @@ -5929,8 +5959,8 @@ ;} break; - case 275: -#line 2678 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 277: +#line 2680 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { std::vector Elements((yyvsp[(3) - (5)].ConstVector)->size()); for (unsigned i = 0, e = (yyvsp[(3) - (5)].ConstVector)->size(); i != e; ++i) @@ -5945,8 +5975,8 @@ ;} break; - case 276: -#line 2690 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 278: +#line 2692 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { const StructType *STy = StructType::get(std::vector(), /*isPacked=*/true); @@ -5955,16 +5985,16 @@ ;} break; - case 277: -#line 2696 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 279: +#line 2698 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ValIDVal) = ValID::create((yyvsp[(1) - (1)].ConstVal)); CHECK_FOR_ERROR ;} break; - case 278: -#line 2700 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 280: +#line 2702 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ValIDVal) = ValID::createInlineAsm(*(yyvsp[(3) - (5)].StrVal), *(yyvsp[(5) - (5)].StrVal), (yyvsp[(2) - (5)].BoolVal)); delete (yyvsp[(3) - (5)].StrVal); @@ -5973,24 +6003,24 @@ ;} break; - case 279: -#line 2710 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 281: +#line 2712 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Is it an integer reference...? (yyval.ValIDVal) = ValID::createLocalID((yyvsp[(1) - (1)].UIntVal)); CHECK_FOR_ERROR ;} break; - case 280: -#line 2714 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 282: +#line 2716 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ValIDVal) = ValID::createGlobalID((yyvsp[(1) - (1)].UIntVal)); CHECK_FOR_ERROR ;} break; - case 281: -#line 2718 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 283: +#line 2720 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Is it a named reference...? (yyval.ValIDVal) = ValID::createLocalName(*(yyvsp[(1) - (1)].StrVal)); delete (yyvsp[(1) - (1)].StrVal); @@ -5998,8 +6028,8 @@ ;} break; - case 282: -#line 2723 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 284: +#line 2725 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Is it a named reference...? (yyval.ValIDVal) = ValID::createGlobalName(*(yyvsp[(1) - (1)].StrVal)); delete (yyvsp[(1) - (1)].StrVal); @@ -6007,8 +6037,8 @@ ;} break; - case 285: -#line 2736 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 287: +#line 2738 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (2)].TypeVal))->getDescription()); @@ -6018,8 +6048,8 @@ ;} break; - case 286: -#line 2745 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 288: +#line 2747 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ValueList) = new std::vector(); (yyval.ValueList)->push_back((yyvsp[(1) - (1)].ValueVal)); @@ -6027,32 +6057,32 @@ ;} break; - case 287: -#line 2750 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 289: +#line 2752 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { ((yyval.ValueList)=(yyvsp[(1) - (3)].ValueList))->push_back((yyvsp[(3) - (3)].ValueVal)); CHECK_FOR_ERROR ;} break; - case 288: -#line 2755 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 290: +#line 2757 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.FunctionVal) = (yyvsp[(1) - (2)].FunctionVal); CHECK_FOR_ERROR ;} break; - case 289: -#line 2759 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 291: +#line 2761 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Do not allow functions with 0 basic blocks (yyval.FunctionVal) = (yyvsp[(1) - (2)].FunctionVal); CHECK_FOR_ERROR ;} break; - case 290: -#line 2768 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 292: +#line 2770 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { setValueName((yyvsp[(3) - (3)].TermInstVal), (yyvsp[(2) - (3)].StrVal)); CHECK_FOR_ERROR @@ -6063,8 +6093,8 @@ ;} break; - case 291: -#line 2777 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 293: +#line 2779 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CHECK_FOR_ERROR int ValNum = InsertValue((yyvsp[(3) - (3)].TermInstVal)); @@ -6078,8 +6108,8 @@ ;} break; - case 292: -#line 2790 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 294: +#line 2792 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (CastInst *CI1 = dyn_cast((yyvsp[(2) - (2)].InstVal))) if (CastInst *CI2 = dyn_cast(CI1->getOperand(0))) @@ -6091,16 +6121,16 @@ ;} break; - case 293: -#line 2799 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 295: +#line 2801 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Empty space between instruction lists (yyval.BasicBlockVal) = defineBBVal(ValID::createLocalID(CurFun.NextValNum)); CHECK_FOR_ERROR ;} break; - case 294: -#line 2803 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 296: +#line 2805 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Labelled (named) basic block (yyval.BasicBlockVal) = defineBBVal(ValID::createLocalName(*(yyvsp[(1) - (1)].StrVal))); delete (yyvsp[(1) - (1)].StrVal); @@ -6109,8 +6139,8 @@ ;} break; - case 295: -#line 2811 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 297: +#line 2813 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Return with a result... ValueList &VL = *(yyvsp[(2) - (2)].ValueList); assert(!VL.empty() && "Invalid ret operands!"); @@ -6133,16 +6163,16 @@ ;} break; - case 296: -#line 2831 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 298: +#line 2833 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Return with no result... (yyval.TermInstVal) = ReturnInst::Create(); CHECK_FOR_ERROR ;} break; - case 297: -#line 2835 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 299: +#line 2837 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Unconditional Branch... BasicBlock* tmpBB = getBBVal((yyvsp[(3) - (3)].ValIDVal)); CHECK_FOR_ERROR @@ -6150,8 +6180,8 @@ ;} break; - case 298: -#line 2840 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 300: +#line 2842 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (cast((yyvsp[(2) - (9)].PrimType))->getBitWidth() != 1) GEN_ERROR("Branch condition must have type i1"); @@ -6165,8 +6195,8 @@ ;} break; - case 299: -#line 2851 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 301: +#line 2853 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { Value* tmpVal = getVal((yyvsp[(2) - (9)].PrimType), (yyvsp[(3) - (9)].ValIDVal)); CHECK_FOR_ERROR @@ -6188,8 +6218,8 @@ ;} break; - case 300: -#line 2870 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 302: +#line 2872 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { Value* tmpVal = getVal((yyvsp[(2) - (8)].PrimType), (yyvsp[(3) - (8)].ValIDVal)); CHECK_FOR_ERROR @@ -6201,8 +6231,8 @@ ;} break; - case 301: -#line 2880 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 303: +#line 2882 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Handle the short syntax @@ -6308,24 +6338,24 @@ ;} break; - case 302: -#line 2983 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 304: +#line 2985 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.TermInstVal) = new UnwindInst(); CHECK_FOR_ERROR ;} break; - case 303: -#line 2987 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 305: +#line 2989 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.TermInstVal) = new UnreachableInst(); CHECK_FOR_ERROR ;} break; - case 304: -#line 2994 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 306: +#line 2996 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.JumpTable) = (yyvsp[(1) - (6)].JumpTable); Constant *V = cast(getExistingVal((yyvsp[(2) - (6)].PrimType), (yyvsp[(3) - (6)].ValIDVal))); @@ -6339,8 +6369,8 @@ ;} break; - case 305: -#line 3005 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 307: +#line 3007 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.JumpTable) = new std::vector >(); Constant *V = cast(getExistingVal((yyvsp[(1) - (5)].PrimType), (yyvsp[(2) - (5)].ValIDVal))); @@ -6355,8 +6385,8 @@ ;} break; - case 306: -#line 3018 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 308: +#line 3020 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Is this definition named?? if so, assign the name... setValueName((yyvsp[(2) - (2)].InstVal), (yyvsp[(1) - (2)].StrVal)); @@ -6367,8 +6397,8 @@ ;} break; - case 307: -#line 3027 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 309: +#line 3029 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { CHECK_FOR_ERROR int ValNum = InsertValue((yyvsp[(2) - (2)].InstVal)); @@ -6382,8 +6412,8 @@ ;} break; - case 308: -#line 3040 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 310: +#line 3042 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Used for PHI nodes if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (6)].TypeVal))->getDescription()); @@ -6397,8 +6427,8 @@ ;} break; - case 309: -#line 3051 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 311: +#line 3053 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.PHIList) = (yyvsp[(1) - (7)].PHIList); Value* tmpVal = getVal((yyvsp[(1) - (7)].PHIList)->front().first->getType(), (yyvsp[(4) - (7)].ValIDVal)); @@ -6409,8 +6439,8 @@ ;} break; - case 310: -#line 3061 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 312: +#line 3063 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // FIXME: Remove trailing OptAttributes in LLVM 3.0, it was a mistake in 2.0 if (!UpRefs.empty()) @@ -6424,8 +6454,8 @@ ;} break; - case 311: -#line 3072 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 313: +#line 3074 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // FIXME: Remove trailing OptAttributes in LLVM 3.0, it was a mistake in 2.0 // Labels are only valid in ASMs @@ -6436,8 +6466,8 @@ ;} break; - case 312: -#line 3080 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 314: +#line 3082 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // FIXME: Remove trailing OptAttributes in LLVM 3.0, it was a mistake in 2.0 if (!UpRefs.empty()) @@ -6450,8 +6480,8 @@ ;} break; - case 313: -#line 3090 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 315: +#line 3092 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // FIXME: Remove trailing OptAttributes in LLVM 3.0, it was a mistake in 2.0 (yyval.ParamList) = (yyvsp[(1) - (6)].ParamList); @@ -6461,18 +6491,18 @@ ;} break; - case 314: -#line 3097 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 316: +#line 3099 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamList) = new ParamList(); ;} break; - case 315: -#line 3100 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 317: +#line 3102 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ValueList) = new std::vector(); ;} break; - case 316: -#line 3101 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 318: +#line 3103 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ValueList) = (yyvsp[(1) - (3)].ValueList); (yyval.ValueList)->push_back((yyvsp[(3) - (3)].ValueVal)); @@ -6480,8 +6510,8 @@ ;} break; - case 317: -#line 3109 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 319: +#line 3111 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ConstantList) = new std::vector(); if ((unsigned)(yyvsp[(2) - (2)].UInt64Val) != (yyvsp[(2) - (2)].UInt64Val)) @@ -6490,8 +6520,8 @@ ;} break; - case 318: -#line 3115 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 320: +#line 3117 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.ConstantList) = (yyvsp[(1) - (3)].ConstantList); if ((unsigned)(yyvsp[(3) - (3)].UInt64Val) != (yyvsp[(3) - (3)].UInt64Val)) @@ -6501,24 +6531,24 @@ ;} break; - case 319: -#line 3124 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 321: +#line 3126 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = true; CHECK_FOR_ERROR ;} break; - case 320: -#line 3128 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 322: +#line 3130 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = false; CHECK_FOR_ERROR ;} break; - case 321: -#line 3133 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 323: +#line 3135 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (5)].TypeVal))->getDescription()); @@ -6537,8 +6567,8 @@ ;} break; - case 322: -#line 3149 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 324: +#line 3151 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (5)].TypeVal))->getDescription()); @@ -6558,8 +6588,8 @@ ;} break; - case 323: -#line 3166 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 325: +#line 3168 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (6)].TypeVal))->getDescription()); @@ -6574,8 +6604,8 @@ ;} break; - case 324: -#line 3178 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 326: +#line 3180 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (6)].TypeVal))->getDescription()); @@ -6590,8 +6620,8 @@ ;} break; - case 325: -#line 3190 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 327: +#line 3192 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (6)].TypeVal))->getDescription()); @@ -6608,8 +6638,8 @@ ;} break; - case 326: -#line 3204 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 328: +#line 3206 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (6)].TypeVal))->getDescription()); @@ -6626,8 +6656,8 @@ ;} break; - case 327: -#line 3218 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 329: +#line 3220 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(4) - (4)].TypeVal))->getDescription()); @@ -6642,8 +6672,8 @@ ;} break; - case 328: -#line 3230 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 330: +#line 3232 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (isa((yyvsp[(2) - (6)].ValueVal)->getType())) { // vector select @@ -6667,8 +6697,8 @@ ;} break; - case 329: -#line 3251 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 331: +#line 3253 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(4) - (4)].TypeVal))->getDescription()); @@ -6678,8 +6708,8 @@ ;} break; - case 330: -#line 3258 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 332: +#line 3260 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!ExtractElementInst::isValidOperands((yyvsp[(2) - (4)].ValueVal), (yyvsp[(4) - (4)].ValueVal))) GEN_ERROR("Invalid extractelement operands"); @@ -6688,8 +6718,8 @@ ;} break; - case 331: -#line 3264 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 333: +#line 3266 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!InsertElementInst::isValidOperands((yyvsp[(2) - (6)].ValueVal), (yyvsp[(4) - (6)].ValueVal), (yyvsp[(6) - (6)].ValueVal))) GEN_ERROR("Invalid insertelement operands"); @@ -6698,8 +6728,8 @@ ;} break; - case 332: -#line 3270 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 334: +#line 3272 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!ShuffleVectorInst::isValidOperands((yyvsp[(2) - (6)].ValueVal), (yyvsp[(4) - (6)].ValueVal), (yyvsp[(6) - (6)].ValueVal))) GEN_ERROR("Invalid shufflevector operands"); @@ -6708,8 +6738,8 @@ ;} break; - case 333: -#line 3276 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 335: +#line 3278 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { const Type *Ty = (yyvsp[(2) - (2)].PHIList)->front().first->getType(); if (!Ty->isFirstClassType()) @@ -6727,8 +6757,8 @@ ;} break; - case 334: -#line 3292 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 336: +#line 3294 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { // Handle the short syntax @@ -6840,32 +6870,32 @@ ;} break; - case 335: -#line 3401 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 337: +#line 3403 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.InstVal) = (yyvsp[(1) - (1)].InstVal); CHECK_FOR_ERROR ;} break; - case 336: -#line 3406 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 338: +#line 3408 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = true; CHECK_FOR_ERROR ;} break; - case 337: -#line 3410 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 339: +#line 3412 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = false; CHECK_FOR_ERROR ;} break; - case 338: -#line 3417 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 340: +#line 3419 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (3)].TypeVal))->getDescription()); @@ -6875,8 +6905,8 @@ ;} break; - case 339: -#line 3424 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 341: +#line 3426 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (6)].TypeVal))->getDescription()); @@ -6889,8 +6919,8 @@ ;} break; - case 340: -#line 3434 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 342: +#line 3436 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (3)].TypeVal))->getDescription()); @@ -6900,8 +6930,8 @@ ;} break; - case 341: -#line 3441 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 343: +#line 3443 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (6)].TypeVal))->getDescription()); @@ -6914,8 +6944,8 @@ ;} break; - case 342: -#line 3451 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 344: +#line 3453 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!isa((yyvsp[(2) - (2)].ValueVal)->getType())) GEN_ERROR("Trying to free nonpointer type " + @@ -6925,8 +6955,8 @@ ;} break; - case 343: -#line 3459 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 345: +#line 3461 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (5)].TypeVal))->getDescription()); @@ -6943,8 +6973,8 @@ ;} break; - case 344: -#line 3473 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 346: +#line 3475 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(5) - (7)].TypeVal))->getDescription()); @@ -6964,8 +6994,8 @@ ;} break; - case 345: -#line 3490 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 347: +#line 3492 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (5)].TypeVal))->getDescription()); @@ -6982,8 +7012,8 @@ ;} break; - case 346: -#line 3504 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 348: +#line 3506 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (4)].TypeVal))->getDescription()); @@ -7001,8 +7031,8 @@ ;} break; - case 347: -#line 3519 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 349: +#line 3521 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (4)].TypeVal))->getDescription()); @@ -7020,8 +7050,8 @@ ;} break; - case 348: -#line 3534 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" + case 350: +#line 3536 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (7)].TypeVal))->getDescription()); @@ -7043,7 +7073,7 @@ /* Line 1267 of yacc.c. */ -#line 7047 "llvmAsmParser.tab.c" +#line 7077 "llvmAsmParser.tab.c" default: break; } YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc); @@ -7257,7 +7287,7 @@ } -#line 3553 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 3555 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" // common code from the two 'RunVMAsmParser' functions Modified: llvm/trunk/lib/AsmParser/llvmAsmParser.h.cvs URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/llvmAsmParser.h.cvs?rev=59204&r1=59203&r2=59204&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/llvmAsmParser.h.cvs (original) +++ llvm/trunk/lib/AsmParser/llvmAsmParser.h.cvs Wed Nov 12 19:03:00 2008 @@ -192,9 +192,11 @@ OPTSIZE = 408, NOINLINE = 409, ALWAYSINLINE = 410, - DEFAULT = 411, - HIDDEN = 412, - PROTECTED = 413 + SSP = 411, + SSPREQ = 412, + DEFAULT = 413, + HIDDEN = 414, + PROTECTED = 415 }; #endif /* Tokens. */ @@ -351,16 +353,18 @@ #define OPTSIZE 408 #define NOINLINE 409 #define ALWAYSINLINE 410 -#define DEFAULT 411 -#define HIDDEN 412 -#define PROTECTED 413 +#define SSP 411 +#define SSPREQ 412 +#define DEFAULT 413 +#define HIDDEN 414 +#define PROTECTED 415 #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED typedef union YYSTYPE -#line 986 "/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 986 "/Volumes/Gir/devel/llvm/llvm.src/lib/AsmParser/llvmAsmParser.y" { llvm::Module *ModuleVal; llvm::Function *FunctionVal; @@ -408,8 +412,8 @@ llvm::ICmpInst::Predicate IPredicate; llvm::FCmpInst::Predicate FPredicate; } -/* Line 1489 of yacc.c. */ -#line 413 "llvmAsmParser.tab.h" +/* Line 1529 of yacc.c. */ +#line 417 "llvmAsmParser.tab.h" YYSTYPE; # define yystype YYSTYPE /* obsolescent; will be withdrawn */ # define YYSTYPE_IS_DECLARED 1 Modified: llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs?rev=59204&r1=59203&r2=59204&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs (original) +++ llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs Wed Nov 12 19:03:00 2008 @@ -1137,7 +1137,7 @@ // Function Attributes %token SIGNEXT ZEROEXT NORETURN INREG SRET NOUNWIND NOALIAS BYVAL NEST -%token READNONE READONLY GC OPTSIZE NOINLINE ALWAYSINLINE +%token READNONE READONLY GC OPTSIZE NOINLINE ALWAYSINLINE SSP SSPREQ // Visibility Styles %token DEFAULT HIDDEN PROTECTED @@ -1305,7 +1305,9 @@ | READONLY { $$ = Attribute::ReadOnly; } | NOINLINE { $$ = Attribute::NoInline; } | ALWAYSINLINE { $$ = Attribute::AlwaysInline; } - | OPTSIZE { $$ = Attribute::OptimizeForSize; } + | OPTSIZE { $$ = Attribute::OptimizeForSize; } + | SSP { $$ = Attribute::StackProtect; } + | SSPREQ { $$ = Attribute::StackProtectReq; } ; OptFuncAttrs : /* empty */ { $$ = Attribute::None; } From isanbard at gmail.com Wed Nov 12 19:04:15 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 13 Nov 2008 01:04:15 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r59205 - in /llvm-gcc-4.2/trunk/gcc: llvm-backend.cpp llvm-convert.cpp Message-ID: <200811130104.mAD14Ggk024296@zion.cs.uiuc.edu> Author: void Date: Wed Nov 12 19:04:15 2008 New Revision: 59205 URL: http://llvm.org/viewvc/llvm-project?rev=59205&view=rev Log: Implement stack protectors using function attributes instead of command line options. This allows LTO to generate proper stack protectors. Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=59205&r1=59204&r2=59205&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Wed Nov 12 19:04:15 2008 @@ -167,16 +167,8 @@ } if (flag_stack_protect > 0) { - std::string Arg; - - if (flag_stack_protect == 1) - Arg = "--enable-stack-protector=some"; - else - Arg = "--enable-stack-protector=all"; - - ArgStrings.push_back(Arg); - Arg = "--stack-protector-buffer-size=" + - utostr(PARAM_VALUE(PARAM_SSP_BUFFER_SIZE)); + std::string Arg("--stack-protector-buffer-size=" + + utostr(PARAM_VALUE(PARAM_SSP_BUFFER_SIZE))); ArgStrings.push_back(Arg); } Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=59205&r1=59204&r2=59205&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Nov 12 19:04:15 2008 @@ -679,6 +679,12 @@ if (optimize_size) Fn->addFnAttr(Attribute::OptimizeForSize); + // Handle stack smashing protection. + if (flag_stack_protect == 1) + Fn->addFnAttr(Attribute::StackProtect); + else if (flag_stack_protect == 2) + Fn->addFnAttr(Attribute::StackProtectReq); + // Handle annotate attributes if (DECL_ATTRIBUTES(FnDecl)) AddAnnotateAttrsToGlobal(Fn, FnDecl); From dpatel at apple.com Wed Nov 12 19:28:41 2008 From: dpatel at apple.com (Devang Patel) Date: Thu, 13 Nov 2008 01:28:41 -0000 Subject: [llvm-commits] [llvm] r59208 - /llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp Message-ID: <200811130128.mAD1SfCx025350@zion.cs.uiuc.edu> Author: dpatel Date: Wed Nov 12 19:28:40 2008 New Revision: 59208 URL: http://llvm.org/viewvc/llvm-project?rev=59208&view=rev Log: Really remove all debug information. Modified: llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp Modified: llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp?rev=59208&r1=59207&r2=59208&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp Wed Nov 12 19:28:40 2008 @@ -56,13 +56,23 @@ return new StripSymbols(OnlyDebugInfo); } +/// OnlyUsedBy - Return true if V is only used by Usr. +static bool OnlyUsedBy(Value *V, Value *Usr) { + for(Value::use_iterator I = V->use_begin(), E = V->use_end(); I != E; ++I) { + User *U = *I; + if (U != Usr) + return false; + } + return true; +} + static void RemoveDeadConstant(Constant *C) { assert(C->use_empty() && "Constant is not dead!"); - std::vector Operands; + SmallPtrSet Operands; for (unsigned i = 0, e = C->getNumOperands(); i != e; ++i) if (isa(C->getOperand(i)->getType()) && - C->getOperand(i)->hasOneUse()) - Operands.push_back(C->getOperand(i)); + OnlyUsedBy(C->getOperand(i), C)) + Operands.insert(C->getOperand(i)); if (GlobalVariable *GV = dyn_cast(C)) { if (!GV->hasInternalLinkage()) return; // Don't delete non static globals. GV->eraseFromParent(); @@ -71,10 +81,9 @@ C->destroyConstant(); // If the constant referenced anything, see if we can delete it as well. - while (!Operands.empty()) { - RemoveDeadConstant(Operands.back()); - Operands.pop_back(); - } + for (SmallPtrSet::iterator OI = Operands.begin(), + OE = Operands.end(); OI != OE; ++OI) + RemoveDeadConstant(*OI); } // Strip the symbol table of its names. @@ -145,8 +154,6 @@ Function *RegionStart = M.getFunction("llvm.dbg.region.start"); Function *RegionEnd = M.getFunction("llvm.dbg.region.end"); Function *Declare = M.getFunction("llvm.dbg.declare"); - if (!FuncStart && !StopPoint && !RegionStart && !RegionEnd && !Declare) - return true; std::vector DeadGlobals; @@ -213,8 +220,30 @@ Declare->eraseFromParent(); } - // Finally, delete any internal globals that were only used by the debugger - // intrinsics. + // llvm.dbg.compile_units and llvm.dbg.subprograms are marked as linkonce + // but since we are removing all debug information, make them internal now. + if (Constant *C = M.getNamedGlobal("llvm.dbg.compile_units")) + if (GlobalVariable *GV = dyn_cast(C)) + GV->setLinkage(GlobalValue::InternalLinkage); + + if (Constant *C = M.getNamedGlobal("llvm.dbg.subprograms")) + if (GlobalVariable *GV = dyn_cast(C)) + GV->setLinkage(GlobalValue::InternalLinkage); + + // Delete all dbg variables. + const Type *DbgVTy = M.getTypeByName("llvm.dbg.variable.type"); + const Type *DbgGVTy = M.getTypeByName("llvm.dbg.global_variable.type"); + if (DbgVTy || DbgGVTy) + for (Module::global_iterator I = M.global_begin(), E = M.global_end(); + I != E; ++I) + if (GlobalVariable *GV = dyn_cast(I)) + if (GV->hasName() && GV->use_empty() + && !strncmp(GV->getNameStart(), "llvm.dbg", 8) + && (GV->getType()->getElementType() == DbgVTy + || GV->getType()->getElementType() == DbgGVTy)) + DeadGlobals.push_back(GV); + + // Delete any internal globals that were only used by the debugger intrinsics. while (!DeadGlobals.empty()) { GlobalVariable *GV = DeadGlobals.back(); DeadGlobals.pop_back(); @@ -222,5 +251,17 @@ RemoveDeadConstant(GV); } + // Remove all llvm.dbg types. + TypeSymbolTable &ST = M.getTypeSymbolTable(); + TypeSymbolTable::iterator TI = ST.begin(); + TypeSymbolTable::iterator TE = ST.end(); + while ( TI != TE ) { + const std::string &Name = TI->first; + if (!strncmp(Name.c_str(), "llvm.dbg.", 9)) + ST.remove(TI++); + else + ++TI; + } + return true; } From isanbard at gmail.com Wed Nov 12 20:42:05 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 13 Nov 2008 02:42:05 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r59214 - /llvm-gcc-4.2/trunk/gcc/config/darwin.c Message-ID: <200811130242.mAD2g5SN027838@zion.cs.uiuc.edu> Author: void Date: Wed Nov 12 20:42:05 2008 New Revision: 59214 URL: http://llvm.org/viewvc/llvm-project?rev=59214&view=rev Log: Emit the correct sections for ObjC metadata when compiled as 64-bit. This syncs up with Apple's GCC. Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.c Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/darwin.c?rev=59214&r1=59213&r2=59214&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/darwin.c (original) +++ llvm-gcc-4.2/trunk/gcc/config/darwin.c Wed Nov 12 20:42:05 2008 @@ -1608,70 +1608,113 @@ } #ifdef ENABLE_LLVM -const char *darwin_objc_llvm_special_name_section(const char* name) { - if (!strncmp (name, "CLASS_METHODS_", 14)) - return "__OBJC,__cls_meth,regular,no_dead_strip"; - else if (!strncmp (name, "INSTANCE_METHODS_", 17)) - return "__OBJC,__inst_meth,regular,no_dead_strip"; - else if (!strncmp (name, "CATEGORY_CLASS_METHODS_", 23)) - return "__OBJC,__cat_cls_meth,regular,no_dead_strip"; - else if (!strncmp (name, "CATEGORY_INSTANCE_METHODS_", 26)) - return "__OBJC,__cat_inst_meth,regular,no_dead_strip"; - else if (!strncmp (name, "CLASS_VARIABLES_", 16)) - return "__OBJC,__class_vars,regular,no_dead_strip"; - else if (!strncmp (name, "INSTANCE_VARIABLES_", 19)) - return "__OBJC,__instance_vars,regular,no_dead_strip"; - else if (!strncmp (name, "CLASS_PROTOCOLS_", 16)) - return "__OBJC,__cat_cls_meth,regular,no_dead_strip"; - else if (!strncmp (name, "CLASS_NAME_", 11)) - return "__TEXT,__cstring,cstring_literals"; - else if (!strncmp (name, "METH_VAR_NAME_", 14)) - return "__TEXT,__cstring,cstring_literals"; - else if (!strncmp (name, "METH_VAR_TYPE_", 14)) - return "__TEXT,__cstring,cstring_literals"; - else if (!strncmp (name, "PROP_NAME_ATTR_", 15)) - return "__TEXT,__cstring,cstring_literals"; - else if (!strncmp (name, "CLASS_REFERENCES", 16)) - return "__OBJC,__cls_refs,literal_pointers,no_dead_strip"; - else if (!strncmp (name, "CLASS_", 6)) - return (flag_objc_abi == 1 ? - "__OBJC,__class,regular,no_dead_strip" : - "__DATA,__data"); - else if (!strncmp (name, "METACLASS_", 10)) - return (flag_objc_abi == 1 ? - "__OBJC,__meta_class,regular,no_dead_strip" : - "__DATA,__data"); - else if (!strncmp (name, "CATEGORY_", 9)) - return "__OBJC,__category,regular,no_dead_strip"; - else if (!strncmp (name, "SELECTOR_REFERENCES", 19)) - return (flag_objc_abi == 1 ? - "__OBJC,__message_refs,literal_pointers,no_dead_strip" : - "__DATA, __objc_selrefs, regular, no_dead_strip"); - else if (!strncmp (name, "SELECTOR_FIXUP", 14)) - return "__OBJC,__sel_fixup,regular";/*,no_dead_strip";*/ - else if (!strncmp (name, "SYMBOLS", 7)) - return "__OBJC,__symbols,regular,no_dead_strip"; - else if (!strncmp (name, "MODULES", 7)) - return "__OBJC,__module_info,regular,no_dead_strip"; - else if (!strncmp (name, "IMAGE_INFO", 10)) - return (flag_objc_abi == 1 ? - "__OBJC, __image_info,regular" /*,no_dead_strip";*/ : - "__DATA, __objc_imageinfo, regular, no_dead_strip"); - else if (!strncmp (name, "PROTOCOL_INSTANCE_METHODS_", 26)) - return "__OBJC,__cat_inst_meth,regular,no_dead_strip"; - else if (!strncmp (name, "PROTOCOL_CLASS_METHODS_", 23)) - return "__OBJC,__cat_cls_meth,regular,no_dead_strip"; - else if (!strncmp (name, "PROTOCOL_REFS_", 14)) - return "__OBJC,__cat_cls_meth,regular,no_dead_strip"; - else if (!strncmp (name, "PROTOCOL_", 9)) - return "__OBJC,__protocol,regular,no_dead_strip"; - else if (flag_objc_abi == 2) { - if (!strncmp (name, "CLASSLIST_REFERENCES_", 21)) - return "__DATA, __objc_classrefs, regular, no_dead_strip"; +static const char *skip_objc_prefix(const char *name) +{ + if (!strncmp (name, "_OBJC_", 6)) + return name + 6; + else if (!strncmp (name, "OBJC_", 5)) + return name + 5; + + return name + 7; +} + +static const char * +darwin_objc_llvm_special_name_section_help(tree decl) { + /* Get a pointer to the name, past the L_OBJC_ prefix. */ + const char *name = IDENTIFIER_POINTER (DECL_NAME (decl)); + const char *base_section = 0; + const char *section = 0; + bool weak_p = (DECL_P (decl) && DECL_WEAK (decl) + && (lookup_attribute ("weak", DECL_ATTRIBUTES (decl)) + || ! lookup_attribute ("weak_import", + DECL_ATTRIBUTES (decl)))); + + if (TREE_READONLY (decl) || TREE_CONSTANT (decl)) + base_section = weak_p ? "__DATA,__const_coal,coalesced" : "__DATA,__const"; + else + base_section = weak_p ? "__DATA,__datacoal_nt,coalesced" : "__DATA,__data"; + + name = skip_objc_prefix(name); + section = darwin_objc_llvm_special_name_section(name); + + if (!section && flag_objc_abi == 2) + section = strcmp(base_section, "__DATA,__data") == 0 ? + "__DATA, __objc_const" : base_section; + + return section ? section : base_section; +} + +const char *darwin_objc_llvm_special_name_section(const char *name) { + if (flag_objc_abi == 1) { + if (!strncmp (name, "CLASS_METHODS_", 14)) + return "__OBJC,__cls_meth,regular,no_dead_strip"; + else if (!strncmp (name, "INSTANCE_METHODS_", 17)) + return "__OBJC,__inst_meth,regular,no_dead_strip"; + else if (!strncmp (name, "CATEGORY_CLASS_METHODS_", 23)) + return "__OBJC,__cat_cls_meth,regular,no_dead_strip"; + else if (!strncmp (name, "CATEGORY_INSTANCE_METHODS_", 26)) + return "__OBJC,__cat_inst_meth,regular,no_dead_strip"; + else if (!strncmp (name, "CLASS_VARIABLES_", 16)) + return "__OBJC,__class_vars,regular,no_dead_strip"; + else if (!strncmp (name, "INSTANCE_VARIABLES_", 19)) + return "__OBJC,__instance_vars,regular,no_dead_strip"; + else if (!strncmp (name, "CLASS_PROTOCOLS_", 16)) + return "__OBJC,__cat_cls_meth,regular,no_dead_strip"; + else if (!strncmp (name, "CLASS_NAME_", 11)) + return "__TEXT,__cstring,cstring_literals"; + else if (!strncmp (name, "METH_VAR_NAME_", 14)) + return "__TEXT,__cstring,cstring_literals"; + else if (!strncmp (name, "METH_VAR_TYPE_", 14)) + return "__TEXT,__cstring,cstring_literals"; + else if (!strncmp (name, "PROP_NAME_ATTR_", 15)) + return "__TEXT,__cstring,cstring_literals"; + else if (!strncmp (name, "CLASS_REFERENCES", 16)) + return "__OBJC,__cls_refs,literal_pointers,no_dead_strip"; + else if (!strncmp (name, "CLASS_", 6)) + return "__OBJC,__class,regular,no_dead_strip"; + else if (!strncmp (name, "METACLASS_", 10)) + return "__OBJC,__meta_class,regular,no_dead_strip"; + else if (!strncmp (name, "CATEGORY_", 9)) + return "__OBJC,__category,regular,no_dead_strip"; + else if (!strncmp (name, "SELECTOR_REFERENCES", 19)) + return "__OBJC,__message_refs,literal_pointers,no_dead_strip"; + else if (!strncmp (name, "SELECTOR_FIXUP", 14)) + return "__OBJC,__sel_fixup,regular";/*,no_dead_strip";*/ + else if (!strncmp (name, "SYMBOLS", 7)) + return "__OBJC,__symbols,regular,no_dead_strip"; + else if (!strncmp (name, "MODULES", 7)) + return "__OBJC,__module_info,regular,no_dead_strip"; + else if (!strncmp (name, "IMAGE_INFO", 10)) + return "__OBJC, __image_info,regular" /*,no_dead_strip";*/; + else if (!strncmp (name, "PROTOCOL_INSTANCE_METHODS_", 26)) + return "__OBJC,__cat_inst_meth,regular,no_dead_strip"; + else if (!strncmp (name, "PROTOCOL_CLASS_METHODS_", 23)) + return "__OBJC,__cat_cls_meth,regular,no_dead_strip"; + else if (!strncmp (name, "PROTOCOL_REFS_", 14)) + return "__OBJC,__cat_cls_meth,regular,no_dead_strip"; + else if (!strncmp (name, "PROTOCOL_", 9)) + return "__OBJC,__protocol,regular,no_dead_strip"; + else if (!strncmp (name, "CLASSEXT_", 9)) + return "__OBJC,__class_ext,regular,no_dead_strip"; + else if (!strncmp (name, "$_PROP_LIST", 11) + || !strncmp (name, "$_PROP_PROTO", 12)) + return "__OBJC,__property,regular,no_dead_strip"; + else if (!strncmp (name, "PROTOCOLEXT", 11)) + return "__OBJC,__protocol_ext,regular,no_dead_strip"; + else if (!strncmp (name, "PROP_NAME_ATTR_", 15)) + return "__TEXT,__cstring,cstring_literals"; + } else if (flag_objc_abi == 2) { + if (!strncmp (name, "PROP_NAME_ATTR_", 15) + || !strncmp (name, "CLASS_NAME_", 11) + || !strncmp (name, "METH_VAR_NAME_", 14) + || !strncmp (name, "METH_VAR_TYPE_", 14)) + return "__TEXT,__cstring,cstring_literals"; + else if (!strncmp (name, "CLASSLIST_REFERENCES_", 21)) + return "__DATA, __objc_classrefs, regular, no_dead_strip"; else if (!strncmp (name, "CLASSLIST_SUP_REFS_", 19)) return "__DATA, __objc_superrefs, regular, no_dead_strip"; - else if (!strncmp (name, "MESSAGE_REF", 11)) - return "__DATA, __objc_msgrefs, regular, no_dead_strip"; + else if (!strncmp (name, "msgSend", 7)) + return "__DATA, __objc_msgrefs, coalesced"; else if (!strncmp (name, "LABEL_CLASS_", 12)) return "__DATA, __objc_classlist, regular, no_dead_strip"; else if (!strncmp (name, "LABEL_PROTOCOL_", 15)) @@ -1684,13 +1727,18 @@ return "__DATA, __objc_nlcatlist, regular, no_dead_strip"; else if (!strncmp (name, "PROTOCOL_REFERENCE_", 19)) return "__DATA, __objc_protorefs, regular, no_dead_strip"; + else if (!strncmp (name, "SELECTOR_REFERENCES", 19)) + return "__DATA, __objc_selrefs, regular, no_dead_strip"; + else if (!strncmp (name, "IMAGE_INFO", 10)) + return "__DATA, __objc_imageinfo, regular, no_dead_strip"; + else if (!strncmp (name, "CLASS_$_", 8) + || !strncmp (name, "METACLASS_$_", 12)) + return "__DATA, __objc_data"; } return 0; } const char *darwin_objc_llvm_implicit_target_global_var_section(tree decl) { - const char *name; - if (TREE_CODE(decl) == CONST_DECL) { extern int flag_next_runtime; tree typename = TYPE_NAME(TREE_TYPE(decl)); @@ -1709,10 +1757,7 @@ } } - /* Get a pointer to the name, past the L_OBJC_ prefix. */ - name = IDENTIFIER_POINTER (DECL_NAME (decl))+7; - - return darwin_objc_llvm_special_name_section(name); + return darwin_objc_llvm_special_name_section_help(decl); } #endif /* LLVM LOCAL end */ From evan.cheng at apple.com Wed Nov 12 21:24:49 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 13 Nov 2008 03:24:49 -0000 Subject: [llvm-commits] [test-suite] r59215 - in /test-suite/trunk: Makefile.programs RunSafely.sh Message-ID: <200811130324.mAD3OnUs029087@zion.cs.uiuc.edu> Author: evancheng Date: Wed Nov 12 21:24:49 2008 New Revision: 59215 URL: http://llvm.org/viewvc/llvm-project?rev=59215&view=rev Log: Allow remote JIT testing. Modified: test-suite/trunk/Makefile.programs test-suite/trunk/RunSafely.sh Modified: test-suite/trunk/Makefile.programs URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=59215&r1=59214&r2=59215&view=diff ============================================================================== --- test-suite/trunk/Makefile.programs (original) +++ test-suite/trunk/Makefile.programs Wed Nov 12 21:24:49 2008 @@ -163,11 +163,6 @@ profile:: $(PROFOUTPUT) print-profile:: $(PRINTPROFOUTPUT) -# JIT remote tests are not supported yet. -ifdef REMOTE_HOST - DISABLE_JIT := 1 -endif - ifdef RUN_GCC_ONLY DISABLE_DIFFS = 1 all:: $(GCCOUTPUT) Modified: test-suite/trunk/RunSafely.sh URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/RunSafely.sh?rev=59215&r1=59214&r2=59215&view=diff ============================================================================== --- test-suite/trunk/RunSafely.sh (original) +++ test-suite/trunk/RunSafely.sh Wed Nov 12 21:24:49 2008 @@ -79,6 +79,11 @@ shift 5 SYSTEM=`uname -s` +PROG=${PROGRAM} +if [ `basename ${PROGRAM}` == "lli" ]; then + PROG=`basename ${PROGRAM}` +fi + ULIMITCMD="" case $SYSTEM in CYGWIN*) @@ -130,14 +135,14 @@ !/^user/ && !/^sys/ { print; } END { printf("program %f\n", cpu); }' > $OUTFILE.time else - rm -f "$PWD/${PROGRAM}.command" - rm -f "$PWD/${PROGRAM}.remote" - rm -f "$PWD/${PROGRAM}.remote.time" - echo "$ULIMITCMD cd $PWD; (time -p ($COMMAND > $PWD/${OUTFILE}.remote 2>&1 < $INFILE;); echo exit $?) > $PWD/${OUTFILE}.remote.time 2>&1" > "$PWD/${PROGRAM}.command" - chmod +x "$PWD/${PROGRAM}.command" + rm -f "$PWD/${PROG}.command" + rm -f "$PWD/${PROG}.remote" + rm -f "$PWD/${PROG}.remote.time" + echo "$ULIMITCMD cd $PWD; (time -p ($COMMAND > $PWD/${OUTFILE}.remote 2>&1 < $INFILE;); echo exit $?) > $PWD/${OUTFILE}.remote.time 2>&1" > "$PWD/${PROG}.command" + chmod +x "$PWD/${PROG}.command" - ( $RCLIENT -l $RUSER $RHOST $RPORT "ls $PWD/${PROGRAM}.command" ) > /dev/null 2>&1 - ( $RCLIENT -l $RUSER $RHOST $RPORT "$PWD/${PROGRAM}.command" ) + ( $RCLIENT -l $RUSER $RHOST $RPORT "ls $PWD/${PROG}.command" ) > /dev/null 2>&1 + ( $RCLIENT -l $RUSER $RHOST $RPORT "$PWD/${PROG}.command" ) cat $PWD/${OUTFILE}.remote.time | awk -- '\ BEGIN { cpu = 0.0; } /^user/ { cpu += $2; print; } From isanbard at gmail.com Wed Nov 12 22:05:38 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 13 Nov 2008 04:05:38 -0000 Subject: [llvm-commits] [llvm] r59216 - /llvm/tags/Apple/llvmCore-2080/ Message-ID: <200811130405.mAD45cDk030388@zion.cs.uiuc.edu> Author: void Date: Wed Nov 12 22:05:36 2008 New Revision: 59216 URL: http://llvm.org/viewvc/llvm-project?rev=59216&view=rev Log: Creating llvmCore-2080 branch Added: llvm/tags/Apple/llvmCore-2080/ - copied from r59215, llvm/trunk/ From isanbard at gmail.com Wed Nov 12 22:05:46 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 13 Nov 2008 04:05:46 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r59217 - /llvm-gcc-4.2/tags/Apple/llvmgcc42-2080/ Message-ID: <200811130405.mAD45kii030402@zion.cs.uiuc.edu> Author: void Date: Wed Nov 12 22:05:46 2008 New Revision: 59217 URL: http://llvm.org/viewvc/llvm-project?rev=59217&view=rev Log: Creating llvmgcc42-2080 branch Added: llvm-gcc-4.2/tags/Apple/llvmgcc42-2080/ - copied from r59216, llvm-gcc-4.2/trunk/ From isanbard at gmail.com Wed Nov 12 22:09:04 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 13 Nov 2008 04:09:04 -0000 Subject: [llvm-commits] [llvm] r59218 - /llvm/trunk/test/FrontendObjC/2008-11-12-Metadata.m Message-ID: <200811130409.mAD494aR030583@zion.cs.uiuc.edu> Author: void Date: Wed Nov 12 22:09:04 2008 New Revision: 59218 URL: http://llvm.org/viewvc/llvm-project?rev=59218&view=rev Log: Added testcase for r59214. Added: llvm/trunk/test/FrontendObjC/2008-11-12-Metadata.m Added: llvm/trunk/test/FrontendObjC/2008-11-12-Metadata.m URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendObjC/2008-11-12-Metadata.m?rev=59218&view=auto ============================================================================== --- llvm/trunk/test/FrontendObjC/2008-11-12-Metadata.m (added) +++ llvm/trunk/test/FrontendObjC/2008-11-12-Metadata.m Wed Nov 12 22:09:04 2008 @@ -0,0 +1,14 @@ +// RUN: %llvmgcc -x objective-c -m64 -c %s -o /dev/null + + at interface A + at end + at protocol P + at end + at interface B : A
+{ +} + at end + at implementation B +- (void)test { +} + at end From daniel at zuster.org Wed Nov 12 23:01:08 2008 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 13 Nov 2008 05:01:08 -0000 Subject: [llvm-commits] [llvm] r59219 - in /llvm/trunk: include/llvm/Support/raw_ostream.h lib/Support/raw_ostream.cpp tools/llc/llc.cpp tools/lto/LTOCodeGenerator.cpp Message-ID: <200811130501.mAD519WT032313@zion.cs.uiuc.edu> Author: ddunbar Date: Wed Nov 12 23:01:07 2008 New Revision: 59219 URL: http://llvm.org/viewvc/llvm-project?rev=59219&view=rev Log: Add Binary flag to raw_fd_ostream constructor. Document raw_fd_ostream's treatment of "-". Modified: llvm/trunk/include/llvm/Support/raw_ostream.h llvm/trunk/lib/Support/raw_ostream.cpp llvm/trunk/tools/llc/llc.cpp llvm/trunk/tools/lto/LTOCodeGenerator.cpp Modified: llvm/trunk/include/llvm/Support/raw_ostream.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/raw_ostream.h?rev=59219&r1=59218&r2=59219&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/raw_ostream.h (original) +++ llvm/trunk/include/llvm/Support/raw_ostream.h Wed Nov 12 23:01:07 2008 @@ -156,7 +156,12 @@ /// error occurs, information about the error is put into ErrorInfo, /// and the stream should be immediately destroyed; the string will /// be empty if no error occurred. - raw_fd_ostream(const char *Filename, std::string &ErrorInfo); + /// + /// \param Filename - The file to open. If this is "-" then the + /// stream will use stdout instead. + /// \param Binary - The file should be opened in binary mode on + /// platforms that support this distinction. + raw_fd_ostream(const char *Filename, bool Binary, std::string &ErrorInfo); /// raw_fd_ostream ctor - FD is the file descriptor that this writes to. If /// ShouldClose is true, this closes the file when Modified: llvm/trunk/lib/Support/raw_ostream.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/raw_ostream.cpp?rev=59219&r1=59218&r2=59219&view=diff ============================================================================== --- llvm/trunk/lib/Support/raw_ostream.cpp (original) +++ llvm/trunk/lib/Support/raw_ostream.cpp Wed Nov 12 23:01:07 2008 @@ -13,6 +13,7 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/Support/Format.h" +#include "llvm/System/Program.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Config/config.h" #include @@ -200,17 +201,27 @@ /// occurs, information about the error is put into ErrorInfo, and the /// stream should be immediately destroyed; the string will be empty /// if no error occurred. -raw_fd_ostream::raw_fd_ostream(const char *Filename, std::string &ErrorInfo) { +raw_fd_ostream::raw_fd_ostream(const char *Filename, bool Binary, + std::string &ErrorInfo) { ErrorInfo.clear(); // Handle "-" as stdout. if (Filename[0] == '-' && Filename[1] == 0) { FD = STDOUT_FILENO; + // If user requested binary then put stdout into binary mode if + // possible. + if (Binary) + sys::Program::ChangeStdoutToBinary(); ShouldClose = false; return; } - FD = open(Filename, O_WRONLY|O_CREAT|O_TRUNC, 0644); + int Flags = O_WRONLY|O_CREAT|O_TRUNC; +#ifdef O_BINARY + if (Binary) + Flags |= O_BINARY; +#endif + FD = open(Filename, Flags, 0644); if (FD < 0) { ErrorInfo = "Error opening output file '" + std::string(Filename) + "'"; ShouldClose = false; Modified: llvm/trunk/tools/llc/llc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=59219&r1=59218&r2=59219&view=diff ============================================================================== --- llvm/trunk/tools/llc/llc.cpp (original) +++ llvm/trunk/tools/llc/llc.cpp Wed Nov 12 23:01:07 2008 @@ -125,7 +125,7 @@ sys::RemoveFileOnSignal(sys::Path(OutputFilename)); std::string error; - raw_ostream *Out = new raw_fd_ostream(OutputFilename.c_str(), error); + raw_ostream *Out = new raw_fd_ostream(OutputFilename.c_str(), true, error); if (!error.empty()) { std::cerr << error << '\n'; delete Out; @@ -142,6 +142,7 @@ OutputFilename = GetFileNameRoot(InputFilename); + bool Binary = false; switch (FileType) { case TargetMachine::AssemblyFile: if (MArch->Name[0] == 'c') { @@ -156,9 +157,11 @@ break; case TargetMachine::ObjectFile: OutputFilename += ".o"; + Binary = true; break; case TargetMachine::DynamicLibrary: OutputFilename += LTDL_SHLIB_EXT; + Binary = true; break; } @@ -175,7 +178,7 @@ sys::RemoveFileOnSignal(sys::Path(OutputFilename)); std::string error; - raw_ostream *Out = new raw_fd_ostream(OutputFilename.c_str(), error); + raw_ostream *Out = new raw_fd_ostream(OutputFilename.c_str(), Binary, error); if (!error.empty()) { std::cerr << error << '\n'; delete Out; Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=59219&r1=59218&r2=59219&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original) +++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Nov 12 23:01:07 2008 @@ -165,7 +165,7 @@ // generate assembly code bool genResult = false; { - raw_fd_ostream asmFile(uniqueAsmPath.c_str(), errMsg); + raw_fd_ostream asmFile(uniqueAsmPath.c_str(), false, errMsg); if (!errMsg.empty()) return NULL; genResult = this->generateAssemblyCode(asmFile, errMsg); From isanbard at gmail.com Thu Nov 13 01:11:27 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 13 Nov 2008 07:11:27 -0000 Subject: [llvm-commits] [llvm] r59228 - /llvm/trunk/lib/VMCore/Verifier.cpp Message-ID: <200811130711.mAD7BRom004259@zion.cs.uiuc.edu> Author: void Date: Thu Nov 13 01:11:27 2008 New Revision: 59228 URL: http://llvm.org/viewvc/llvm-project?rev=59228&view=rev Log: Refactor the code that does the type checking for intrinsics. Modified: llvm/trunk/lib/VMCore/Verifier.cpp Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=59228&r1=59227&r2=59228&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Thu Nov 13 01:11:27 2008 @@ -266,6 +266,8 @@ void visitInsertValueInst(InsertValueInst &IVI); void VerifyCallSite(CallSite CS); + bool PerformTypeCheck(Intrinsic::ID ID, Function *F, const Type *Ty, + int VT, unsigned ArgNo, std::string &Suffix); void VerifyIntrinsicPrototype(Intrinsic::ID ID, Function *F, unsigned Count, ...); void VerifyAttrs(Attributes Attrs, const Type *Ty, @@ -1375,6 +1377,133 @@ } } +bool Verifier::PerformTypeCheck(Intrinsic::ID ID, Function *F, const Type *Ty, + int VT, unsigned ArgNo, std::string &Suffix) { + const FunctionType *FTy = F->getFunctionType(); + + unsigned NumElts = 0; + const Type *EltTy = Ty; + if (const VectorType *VTy = dyn_cast(Ty)) { + EltTy = VTy->getElementType(); + NumElts = VTy->getNumElements(); + } + + if (VT < 0) { + int Match = ~VT; + if (Match == 0) { + if (Ty != FTy->getReturnType()) { + CheckFailed("Intrinsic parameter #" + utostr(ArgNo - 1) + " does not " + "match return type.", F); + return false; + } + } else { + if (Ty != FTy->getParamType(Match - 1)) { + CheckFailed("Intrinsic parameter #" + utostr(ArgNo - 1) + " does not " + "match parameter %" + utostr(Match - 1) + ".", F); + return false; + } + } + } else if (VT == MVT::iAny) { + if (!EltTy->isInteger()) { + if (ArgNo == 0) + CheckFailed("Intrinsic result type is not an integer type.", F); + else + CheckFailed("Intrinsic parameter #" + utostr(ArgNo - 1) + " is not " + "an integer type.", F); + + return false; + } + + unsigned GotBits = cast(EltTy)->getBitWidth(); + Suffix += "."; + + if (EltTy != Ty) + Suffix += "v" + utostr(NumElts); + + Suffix += "i" + utostr(GotBits);; + + // Check some constraints on various intrinsics. + switch (ID) { + default: break; // Not everything needs to be checked. + case Intrinsic::bswap: + if (GotBits < 16 || GotBits % 16 != 0) + CheckFailed("Intrinsic requires even byte width argument", F); + break; + } + } else if (VT == MVT::fAny) { + if (!EltTy->isFloatingPoint()) { + if (ArgNo == 0) + CheckFailed("Intrinsic result type is not a floating-point type.", F); + else + CheckFailed("Intrinsic parameter #" + utostr(ArgNo - 1) + " is not " + "a floating-point type.", F); + return false; + } + + Suffix += "."; + + if (EltTy != Ty) + Suffix += "v" + utostr(NumElts); + + Suffix += MVT::getMVT(EltTy).getMVTString(); + } else if (VT == MVT::iPTR) { + if (!isa(Ty)) { + if (ArgNo == 0) + CheckFailed("Intrinsic result type is not a " + "pointer and a pointer is required.", F); + else + CheckFailed("Intrinsic parameter #" + utostr(ArgNo - 1) + " is not a " + "pointer and a pointer is required.", F); + } + } else if (VT == MVT::iPTRAny) { + // Outside of TableGen, we don't distinguish iPTRAny (to any address space) + // and iPTR. In the verifier, we can not distinguish which case we have so + // allow either case to be legal. + if (const PointerType* PTyp = dyn_cast(Ty)) { + Suffix += ".p" + utostr(PTyp->getAddressSpace()) + + MVT::getMVT(PTyp->getElementType()).getMVTString(); + } else { + if (ArgNo == 0) + CheckFailed("Intrinsic result type is not a " + "pointer and a pointer is required.", F); + else + CheckFailed("Intrinsic parameter #" + utostr(ArgNo-1) + " is not a " + "pointer and a pointer is required.", F); + return false; + } + } else if (MVT((MVT::SimpleValueType)VT).isVector()) { + MVT VVT = MVT((MVT::SimpleValueType)VT); + + // If this is a vector argument, verify the number and type of elements. + if (VVT.getVectorElementType() != MVT::getMVT(EltTy)) { + CheckFailed("Intrinsic prototype has incorrect vector element type!", F); + return false; + } + + if (VVT.getVectorNumElements() != NumElts) { + CheckFailed("Intrinsic prototype has incorrect number of " + "vector elements!", F); + return false; + } + } else if (MVT((MVT::SimpleValueType)VT).getTypeForMVT() != EltTy) { + if (ArgNo == 0) + CheckFailed("Intrinsic prototype has incorrect result type!", F); + else + CheckFailed("Intrinsic parameter #" + utostr(ArgNo-1) + " is wrong!",F); + + return false; + } else if (EltTy != Ty) { + if (ArgNo == 0) + CheckFailed("Intrinsic result type is vector " + "and a scalar is required.", F); + else + CheckFailed("Intrinsic parameter #" + utostr(ArgNo-1) + " is vector " + "and a scalar is required.", F); + } + + return true; +} + /// VerifyIntrinsicPrototype - TableGen emits calls to this function into /// Intrinsics.gen. This implements a little state machine that verifies the /// prototype of intrinsics. @@ -1405,123 +1534,11 @@ break; } - const Type *Ty; - if (ArgNo == 0) - Ty = FTy->getReturnType(); - else - Ty = FTy->getParamType(ArgNo-1); + const Type *Ty = (ArgNo == 0) ? + FTy->getReturnType() : FTy->getParamType(ArgNo - 1); - unsigned NumElts = 0; - const Type *EltTy = Ty; - if (const VectorType *VTy = dyn_cast(Ty)) { - EltTy = VTy->getElementType(); - NumElts = VTy->getNumElements(); - } - - if (VT < 0) { - int Match = ~VT; - if (Match == 0) { - if (Ty != FTy->getReturnType()) { - CheckFailed("Intrinsic parameter #" + utostr(ArgNo-1) + " does not " - "match return type.", F); - break; - } - } else { - if (Ty != FTy->getParamType(Match-1)) { - CheckFailed("Intrinsic parameter #" + utostr(ArgNo-1) + " does not " - "match parameter %" + utostr(Match-1) + ".", F); - break; - } - } - } else if (VT == MVT::iAny) { - if (!EltTy->isInteger()) { - if (ArgNo == 0) - CheckFailed("Intrinsic result type is not " - "an integer type.", F); - else - CheckFailed("Intrinsic parameter #" + utostr(ArgNo-1) + " is not " - "an integer type.", F); - break; - } - unsigned GotBits = cast(EltTy)->getBitWidth(); - Suffix += "."; - if (EltTy != Ty) - Suffix += "v" + utostr(NumElts); - Suffix += "i" + utostr(GotBits);; - // Check some constraints on various intrinsics. - switch (ID) { - default: break; // Not everything needs to be checked. - case Intrinsic::bswap: - if (GotBits < 16 || GotBits % 16 != 0) - CheckFailed("Intrinsic requires even byte width argument", F); - break; - } - } else if (VT == MVT::fAny) { - if (!EltTy->isFloatingPoint()) { - if (ArgNo == 0) - CheckFailed("Intrinsic result type is not " - "a floating-point type.", F); - else - CheckFailed("Intrinsic parameter #" + utostr(ArgNo-1) + " is not " - "a floating-point type.", F); - break; - } - Suffix += "."; - if (EltTy != Ty) - Suffix += "v" + utostr(NumElts); - Suffix += MVT::getMVT(EltTy).getMVTString(); - } else if (VT == MVT::iPTR) { - if (!isa(Ty)) { - if (ArgNo == 0) - CheckFailed("Intrinsic result type is not a " - "pointer and a pointer is required.", F); - else - CheckFailed("Intrinsic parameter #" + utostr(ArgNo-1) + " is not a " - "pointer and a pointer is required.", F); - } - } else if (VT == MVT::iPTRAny) { - // Outside of TableGen, we don't distinguish iPTRAny (to any address - // space) and iPTR. In the verifier, we can not distinguish which case - // we have so allow either case to be legal. - if (const PointerType* PTyp = dyn_cast(Ty)) { - Suffix += ".p" + utostr(PTyp->getAddressSpace()) + - MVT::getMVT(PTyp->getElementType()).getMVTString(); - } else { - if (ArgNo == 0) - CheckFailed("Intrinsic result type is not a " - "pointer and a pointer is required.", F); - else - CheckFailed("Intrinsic parameter #" + utostr(ArgNo-1) + " is not a " - "pointer and a pointer is required.", F); - break; - } - } else if (MVT((MVT::SimpleValueType)VT).isVector()) { - MVT VVT = MVT((MVT::SimpleValueType)VT); - // If this is a vector argument, verify the number and type of elements. - if (VVT.getVectorElementType() != MVT::getMVT(EltTy)) { - CheckFailed("Intrinsic prototype has incorrect vector element type!", - F); - break; - } - if (VVT.getVectorNumElements() != NumElts) { - CheckFailed("Intrinsic prototype has incorrect number of " - "vector elements!",F); - break; - } - } else if (MVT((MVT::SimpleValueType)VT).getTypeForMVT() != EltTy) { - if (ArgNo == 0) - CheckFailed("Intrinsic prototype has incorrect result type!", F); - else - CheckFailed("Intrinsic parameter #" + utostr(ArgNo-1) + " is wrong!",F); + if (!PerformTypeCheck(ID, F, Ty, VT, ArgNo, Suffix)) break; - } else if (EltTy != Ty) { - if (ArgNo == 0) - CheckFailed("Intrinsic result type is vector " - "and a scalar is required.", F); - else - CheckFailed("Intrinsic parameter #" + utostr(ArgNo-1) + " is vector " - "and a scalar is required.", F); - } } va_end(VA); From evan.cheng at apple.com Thu Nov 13 01:35:06 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 13 Nov 2008 07:35:06 -0000 Subject: [llvm-commits] [llvm] r59230 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMInstrFormats.td ARMInstrInfo.h ARMInstrInfo.td Message-ID: <200811130735.mAD7Z7YJ005089@zion.cs.uiuc.edu> Author: evancheng Date: Thu Nov 13 01:34:59 2008 New Revision: 59230 URL: http://llvm.org/viewvc/llvm-project?rev=59230&view=rev Log: Fix pre- and post-indexed load / store encoding bugs. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.h llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=59230&r1=59229&r2=59230&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Thu Nov 13 01:34:59 2008 @@ -312,10 +312,12 @@ case ARMII::DPSoRegFrm: emitDataProcessingInstruction(MI); break; - case ARMII::LdStFrm: + case ARMII::LdFrm: + case ARMII::StFrm: emitLoadStoreInstruction(MI); break; - case ARMII::LdStMiscFrm: + case ARMII::LdMiscFrm: + case ARMII::StMiscFrm: emitMiscLoadStoreInstruction(MI); break; case ARMII::LdStMulFrm: @@ -687,6 +689,8 @@ unsigned ImplicitRd, unsigned ImplicitRn) { const TargetInstrDesc &TID = MI.getDesc(); + unsigned Form = TID.TSFlags & ARMII::FormMask; + bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -694,8 +698,17 @@ // Set the conditional execution predicate Binary |= II->getPredicate(&MI) << ARMII::CondShift; - // Set first operand unsigned OpIdx = 0; + + // Operand 0 of a pre- and post-indexed store is the address base + // writeback. Skip it. + bool Skipped = false; + if (IsPrePost && Form == ARMII::StFrm) { + ++OpIdx; + Skipped = true; + } + + // Set first operand if (ImplicitRd) // Special handling for implicit use (e.g. PC). Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd) @@ -712,7 +725,7 @@ Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; // If this is a two-address operand, skip it. e.g. LDR_PRE. - if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) + if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) ++OpIdx; const MachineOperand &MO2 = MI.getOperand(OpIdx); @@ -749,6 +762,8 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, unsigned ImplicitRn) { const TargetInstrDesc &TID = MI.getDesc(); + unsigned Form = TID.TSFlags & ARMII::FormMask; + bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -756,11 +771,20 @@ // Set the conditional execution predicate Binary |= II->getPredicate(&MI) << ARMII::CondShift; + unsigned OpIdx = 0; + + // Operand 0 of a pre- and post-indexed store is the address base + // writeback. Skip it. + bool Skipped = false; + if (IsPrePost && Form == ARMII::StMiscFrm) { + ++OpIdx; + Skipped = true; + } + // Set first operand - Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; + Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; // Set second operand - unsigned OpIdx = 1; if (ImplicitRn) // Special handling for implicit use (e.g. PC). Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) @@ -769,7 +793,7 @@ Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; // If this is a two-address operand, skip it. e.g. LDRH_POST. - if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) + if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) ++OpIdx; const MachineOperand &MO2 = MI.getOperand(OpIdx); Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=59230&r1=59229&r2=59230&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Nov 13 01:34:59 2008 @@ -27,25 +27,27 @@ def DPFrm : Format<5>; def DPSoRegFrm : Format<6>; -def LdStFrm : Format<7>; -def LdStMiscFrm : Format<8>; -def LdStMulFrm : Format<9>; - -def ArithMiscFrm : Format<10>; -def ExtFrm : Format<11>; - -def VFPUnaryFrm : Format<12>; -def VFPBinaryFrm : Format<13>; -def VFPConv1Frm : Format<14>; -def VFPConv2Frm : Format<15>; -def VFPConv3Frm : Format<16>; -def VFPConv4Frm : Format<17>; -def VFPConv5Frm : Format<18>; -def VFPLdStFrm : Format<19>; -def VFPLdStMulFrm : Format<20>; -def VFPMiscFrm : Format<21>; +def LdFrm : Format<7>; +def StFrm : Format<8>; +def LdMiscFrm : Format<9>; +def StMiscFrm : Format<10>; +def LdStMulFrm : Format<11>; + +def ArithMiscFrm : Format<12>; +def ExtFrm : Format<13>; + +def VFPUnaryFrm : Format<14>; +def VFPBinaryFrm : Format<15>; +def VFPConv1Frm : Format<16>; +def VFPConv2Frm : Format<17>; +def VFPConv3Frm : Format<18>; +def VFPConv4Frm : Format<19>; +def VFPConv5Frm : Format<20>; +def VFPLdStFrm : Format<21>; +def VFPLdStMulFrm : Format<22>; +def VFPMiscFrm : Format<23>; -def ThumbFrm : Format<22>; +def ThumbFrm : Format<24>; // Misc flag for data processing instructions that indicates whether // the instruction has a Rn register operand. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=59230&r1=59229&r2=59230&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Thu Nov 13 01:34:59 2008 @@ -87,30 +87,32 @@ DPSoRegFrm = 6 << FormShift, // Load and Store - LdStFrm = 7 << FormShift, - LdStMiscFrm = 8 << FormShift, - LdStMulFrm = 9 << FormShift, + LdFrm = 7 << FormShift, + StFrm = 8 << FormShift, + LdMiscFrm = 9 << FormShift, + StMiscFrm = 10 << FormShift, + LdStMulFrm = 11 << FormShift, // Miscellaneous arithmetic instructions - ArithMiscFrm = 10 << FormShift, + ArithMiscFrm = 12 << FormShift, // Extend instructions - ExtFrm = 11 << FormShift, + ExtFrm = 13 << FormShift, // VFP formats - VFPUnaryFrm = 12 << FormShift, - VFPBinaryFrm = 13 << FormShift, - VFPConv1Frm = 14 << FormShift, - VFPConv2Frm = 15 << FormShift, - VFPConv3Frm = 16 << FormShift, - VFPConv4Frm = 17 << FormShift, - VFPConv5Frm = 18 << FormShift, - VFPLdStFrm = 19 << FormShift, - VFPLdStMulFrm = 20 << FormShift, - VFPMiscFrm = 21 << FormShift, + VFPUnaryFrm = 14 << FormShift, + VFPBinaryFrm = 15 << FormShift, + VFPConv1Frm = 16 << FormShift, + VFPConv2Frm = 17 << FormShift, + VFPConv3Frm = 18 << FormShift, + VFPConv4Frm = 19 << FormShift, + VFPConv5Frm = 20 << FormShift, + VFPLdStFrm = 21 << FormShift, + VFPLdStMulFrm = 22 << FormShift, + VFPMiscFrm = 23 << FormShift, // Thumb format - ThumbFrm = 22 << FormShift, + ThumbFrm = 24 << FormShift, //===------------------------------------------------------------------===// // Field shifts - such shifts are used to set field while generating Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=59230&r1=59229&r2=59230&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Nov 13 01:34:59 2008 @@ -615,134 +615,134 @@ // Load let isSimpleLoad = 1 in -def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdStFrm, +def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, "ldr", " $dst, $addr", [(set GPR:$dst, (load addrmode2:$addr))]>; // Special LDR for loads from non-pc-relative constpools. let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1 in -def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdStFrm, +def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, "ldr", " $dst, $addr", []>; // Loads with zero extension -def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdStMiscFrm, +def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, "ldr", "h $dst, $addr", [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>; -def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdStFrm, +def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, "ldr", "b $dst, $addr", [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>; // Loads with sign extension -def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdStMiscFrm, +def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, "ldr", "sh $dst, $addr", [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>; -def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdStMiscFrm, +def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, "ldr", "sb $dst, $addr", [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>; let mayLoad = 1 in { // Load doubleword -def LDRD : AI3ldd<(outs GPR:$dst), (ins addrmode3:$addr), LdStMiscFrm, +def LDRD : AI3ldd<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, "ldr", "d $dst, $addr", []>, Requires<[IsARM, HasV5T]>; // Indexed loads def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb), - (ins addrmode2:$addr), LdStFrm, + (ins addrmode2:$addr), LdFrm, "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>; def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base, am2offset:$offset), LdStFrm, + (ins GPR:$base, am2offset:$offset), LdFrm, "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>; def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb), - (ins addrmode3:$addr), LdStMiscFrm, + (ins addrmode3:$addr), LdMiscFrm, "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>; def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base,am3offset:$offset), LdStMiscFrm, + (ins GPR:$base,am3offset:$offset), LdMiscFrm, "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>; def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb), - (ins addrmode2:$addr), LdStFrm, + (ins addrmode2:$addr), LdFrm, "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>; def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base,am2offset:$offset), LdStFrm, + (ins GPR:$base,am2offset:$offset), LdFrm, "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>; def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb), - (ins addrmode3:$addr), LdStMiscFrm, + (ins addrmode3:$addr), LdMiscFrm, "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>; def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base,am3offset:$offset), LdStMiscFrm, - "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>; + (ins GPR:$base,am3offset:$offset), LdMiscFrm, + "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>; def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb), - (ins addrmode3:$addr), LdStMiscFrm, + (ins addrmode3:$addr), LdMiscFrm, "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>; def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base,am3offset:$offset), LdStMiscFrm, + (ins GPR:$base,am3offset:$offset), LdMiscFrm, "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>; } // Store -def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), LdStFrm, +def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, "str", " $src, $addr", [(store GPR:$src, addrmode2:$addr)]>; // Stores with truncate -def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), LdStMiscFrm, +def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, "str", "h $src, $addr", [(truncstorei16 GPR:$src, addrmode3:$addr)]>; -def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), LdStFrm, +def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, "str", "b $src, $addr", [(truncstorei8 GPR:$src, addrmode2:$addr)]>; // Store doubleword let mayStore = 1 in -def STRD : AI3std<(outs), (ins GPR:$src, addrmode3:$addr), LdStMiscFrm, +def STRD : AI3std<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, "str", "d $src, $addr", []>, Requires<[IsARM, HasV5T]>; // Indexed stores def STR_PRE : AI2stwpr<(outs GPR:$base_wb), - (ins GPR:$src, GPR:$base, am2offset:$offset), LdStFrm, + (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm, "str", " $src, [$base, $offset]!", "$base = $base_wb", [(set GPR:$base_wb, (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>; def STR_POST : AI2stwpo<(outs GPR:$base_wb), - (ins GPR:$src, GPR:$base,am2offset:$offset), LdStFrm, + (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, "str", " $src, [$base], $offset", "$base = $base_wb", [(set GPR:$base_wb, (post_store GPR:$src, GPR:$base, am2offset:$offset))]>; def STRH_PRE : AI3sthpr<(outs GPR:$base_wb), - (ins GPR:$src, GPR:$base,am3offset:$offset), LdStMiscFrm, + (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm, "str", "h $src, [$base, $offset]!", "$base = $base_wb", [(set GPR:$base_wb, (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>; def STRH_POST: AI3sthpo<(outs GPR:$base_wb), - (ins GPR:$src, GPR:$base,am3offset:$offset), LdStMiscFrm, + (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm, "str", "h $src, [$base], $offset", "$base = $base_wb", [(set GPR:$base_wb, (post_truncsti16 GPR:$src, GPR:$base, am3offset:$offset))]>; def STRB_PRE : AI2stbpr<(outs GPR:$base_wb), - (ins GPR:$src, GPR:$base,am2offset:$offset), LdStFrm, + (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, "str", "b $src, [$base, $offset]!", "$base = $base_wb", [(set GPR:$base_wb, (pre_truncsti8 GPR:$src, GPR:$base, am2offset:$offset))]>; def STRB_POST: AI2stbpo<(outs GPR:$base_wb), - (ins GPR:$src, GPR:$base,am2offset:$offset), LdStFrm, + (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, "str", "b $src, [$base], $offset", "$base = $base_wb", [(set GPR:$base_wb, (post_truncsti8 GPR:$src, GPR:$base, am2offset:$offset))]>; From evan.cheng at apple.com Thu Nov 13 01:47:16 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 13 Nov 2008 07:47:16 -0000 Subject: [llvm-commits] [llvm] r59231 - /llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Message-ID: <200811130747.mAD7lHXO005416@zion.cs.uiuc.edu> Author: evancheng Date: Thu Nov 13 01:46:59 2008 New Revision: 59231 URL: http://llvm.org/viewvc/llvm-project?rev=59231&view=rev Log: Missed a break statement. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=59231&r1=59230&r2=59231&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Thu Nov 13 01:46:59 2008 @@ -1175,6 +1175,7 @@ case ARMII::VFPConv1Frm: // Encode Dm / Sm. Binary |= encodeVFPRm(MI, 1); + break; case ARMII::VFPConv2Frm: case ARMII::VFPConv3Frm: // Encode Dn / Sn. From evan.cheng at apple.com Thu Nov 13 01:59:49 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 13 Nov 2008 07:59:49 -0000 Subject: [llvm-commits] [llvm] r59234 - /llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Message-ID: <200811130759.mAD7xnGD005866@zion.cs.uiuc.edu> Author: evancheng Date: Thu Nov 13 01:59:48 2008 New Revision: 59234 URL: http://llvm.org/viewvc/llvm-project?rev=59234&view=rev Log: fsub{d|s} encoding bugs. Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=59234&r1=59233&r2=59234&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Thu Nov 13 01:59:48 2008 @@ -148,11 +148,15 @@ def FSUBD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b), "fsubd", " $dst, $a, $b", - [(set DPR:$dst, (fsub DPR:$a, DPR:$b))]>; + [(set DPR:$dst, (fsub DPR:$a, DPR:$b))]> { + let Inst{6} = 1; +} def FSUBS : ASbI<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b), "fsubs", " $dst, $a, $b", - [(set SPR:$dst, (fsub SPR:$a, SPR:$b))]>; + [(set SPR:$dst, (fsub SPR:$a, SPR:$b))]> { + let Inst{6} = 1; +} //===----------------------------------------------------------------------===// // FP Unary Operations. From duncan.sands at math.u-psud.fr Thu Nov 13 02:48:14 2008 From: duncan.sands at math.u-psud.fr (Duncan Sands) Date: Thu, 13 Nov 2008 09:48:14 +0100 Subject: [llvm-commits] [llvm] r59202 - in /llvm/trunk: include/llvm/Attributes.h include/llvm/CodeGen/Passes.h lib/AsmParser/LLLexer.cpp lib/AsmParser/llvmAsmParser.y lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/StackProtector.cpp lib/VMCore/Attributes.cpp In-Reply-To: <200811130102.mAD12KwL024185@zion.cs.uiuc.edu> References: <200811130102.mAD12KwL024185@zion.cs.uiuc.edu> Message-ID: <200811130948.15523.duncan.sands@math.u-psud.fr> Hi Bill, > Implement stack protectors as function attributes: "ssp" and "sspreq". if a sspreq function is inlined into a function without either of these attributes, then you won't get stack protection on the inlined code, right? Ciao, Duncan. From isanbard at gmail.com Thu Nov 13 03:08:35 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 13 Nov 2008 09:08:35 -0000 Subject: [llvm-commits] [llvm] r59237 - in /llvm/trunk: include/llvm/Intrinsics.td include/llvm/IntrinsicsARM.td include/llvm/IntrinsicsAlpha.td include/llvm/IntrinsicsCellSPU.td include/llvm/IntrinsicsPowerPC.td include/llvm/IntrinsicsX86.td lib/VMCore/Verifier.cpp utils/TableGen/CodeGenDAGPatterns.cpp utils/TableGen/CodeGenIntrinsics.h utils/TableGen/CodeGenTarget.cpp utils/TableGen/IntrinsicEmitter.cpp Message-ID: <200811130908.mAD98ZqI017821@zion.cs.uiuc.edu> Author: void Date: Thu Nov 13 03:08:33 2008 New Revision: 59237 URL: http://llvm.org/viewvc/llvm-project?rev=59237&view=rev Log: Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; Modified: llvm/trunk/include/llvm/Intrinsics.td llvm/trunk/include/llvm/IntrinsicsARM.td llvm/trunk/include/llvm/IntrinsicsAlpha.td llvm/trunk/include/llvm/IntrinsicsCellSPU.td llvm/trunk/include/llvm/IntrinsicsPowerPC.td llvm/trunk/include/llvm/IntrinsicsX86.td llvm/trunk/lib/VMCore/Verifier.cpp llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp llvm/trunk/utils/TableGen/CodeGenIntrinsics.h llvm/trunk/utils/TableGen/CodeGenTarget.cpp llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Modified: llvm/trunk/include/llvm/Intrinsics.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=59237&r1=59236&r2=59237&view=diff ============================================================================== --- llvm/trunk/include/llvm/Intrinsics.td (original) +++ llvm/trunk/include/llvm/Intrinsics.td Thu Nov 13 03:08:33 2008 @@ -117,16 +117,20 @@ // name with the "llvm." prefix removed, and all "."s turned into "_"s. For // example, llvm.bswap.i16 -> int_bswap_i16. // -// * Types is a list containing the return type and the argument types -// expected for the intrinsic. +// * RetTypes is a list containing the return types expected for the +// intrinsic. +// * ParamTypes is a list containing the parameter types expected for the +// intrinsic. // * Properties can be set to describe the behavior of the intrinsic. // -class Intrinsic types, +class Intrinsic ret_types, + list param_types = [], list properties = [], string name = ""> { string LLVMName = name; string TargetPrefix = ""; // Set to a prefix for target-specific intrinsics. - list Types = types; + list RetTypes = ret_types; + list ParamTypes = param_types; list Properties = properties; } @@ -141,64 +145,71 @@ //===--------------- Variable Argument Handling Intrinsics ----------------===// // -def int_vastart : Intrinsic<[llvm_void_ty, llvm_ptr_ty], [], "llvm.va_start">; -def int_vacopy : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_ptr_ty], [], +def int_vastart : Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [], "llvm.va_start">; +def int_vacopy : Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_ptr_ty], [], "llvm.va_copy">; -def int_vaend : Intrinsic<[llvm_void_ty, llvm_ptr_ty], [], "llvm.va_end">; +def int_vaend : Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [], "llvm.va_end">; //===------------------- Garbage Collection Intrinsics --------------------===// // -def int_gcroot : Intrinsic<[llvm_void_ty, llvm_ptrptr_ty, llvm_ptr_ty]>; -def int_gcread : Intrinsic<[llvm_ptr_ty, llvm_ptr_ty, llvm_ptrptr_ty], +def int_gcroot : Intrinsic<[llvm_void_ty], [llvm_ptrptr_ty, llvm_ptr_ty]>; +def int_gcread : Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_ptrptr_ty], [IntrReadArgMem]>; -def int_gcwrite : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_ptr_ty, +def int_gcwrite : Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_ptr_ty, llvm_ptrptr_ty], [IntrWriteArgMem]>; //===--------------------- Code Generator Intrinsics ----------------------===// // -def int_returnaddress : Intrinsic<[llvm_ptr_ty, llvm_i32_ty], [IntrNoMem]>; -def int_frameaddress : Intrinsic<[llvm_ptr_ty, llvm_i32_ty], [IntrNoMem]>; +def int_returnaddress : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty], [IntrNoMem]>; +def int_frameaddress : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty], [IntrNoMem]>; // Note: we treat stacksave/stackrestore as writemem because we don't otherwise // model their dependencies on allocas. def int_stacksave : Intrinsic<[llvm_ptr_ty]>, GCCBuiltin<"__builtin_stack_save">; -def int_stackrestore : Intrinsic<[llvm_void_ty, llvm_ptr_ty]>, +def int_stackrestore : Intrinsic<[llvm_void_ty], [llvm_ptr_ty]>, GCCBuiltin<"__builtin_stack_restore">; // IntrWriteArgMem is more pessimistic than strictly necessary for prefetch, // however it does conveniently prevent the prefetch from being reordered // with respect to nearby accesses to the same memory. -def int_prefetch : Intrinsic<[llvm_void_ty, llvm_ptr_ty, - llvm_i32_ty, llvm_i32_ty], +def int_prefetch : Intrinsic<[llvm_void_ty], + [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [IntrWriteArgMem]>; -def int_pcmarker : Intrinsic<[llvm_void_ty, llvm_i32_ty]>; +def int_pcmarker : Intrinsic<[llvm_void_ty], [llvm_i32_ty]>; def int_readcyclecounter : Intrinsic<[llvm_i64_ty]>; // Stack Protector Intrinsics - The stackprotector_create writes the stack guard // to the correct place on the stack frame. The stackprotector_check reads back // the stack guard that the stackprotector_create stored. -def int_stackprotector_create : Intrinsic<[llvm_void_ty, llvm_ptr_ty, - llvm_ptrptr_ty], [IntrWriteMem]>; -def int_stackprotector_check : Intrinsic<[llvm_ptr_ty, llvm_ptrptr_ty], +def int_stackprotector_create : Intrinsic<[llvm_void_ty], + [llvm_ptr_ty, llvm_ptrptr_ty], + [IntrWriteMem]>; +def int_stackprotector_check : Intrinsic<[llvm_ptr_ty], [llvm_ptrptr_ty], [IntrReadMem]>; //===------------------- Standard C Library Intrinsics --------------------===// // let Properties = [IntrWriteArgMem] in { - def int_memcpy_i32 : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_ptr_ty, + def int_memcpy_i32 : Intrinsic<[llvm_void_ty], + [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty]>; - def int_memcpy_i64 : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_ptr_ty, + def int_memcpy_i64 : Intrinsic<[llvm_void_ty], + [llvm_ptr_ty, llvm_ptr_ty, llvm_i64_ty, llvm_i32_ty]>; - def int_memmove_i32 : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_ptr_ty, + def int_memmove_i32 : Intrinsic<[llvm_void_ty], + [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty]>; - def int_memmove_i64 : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_ptr_ty, + def int_memmove_i64 : Intrinsic<[llvm_void_ty], + [llvm_ptr_ty, llvm_ptr_ty, llvm_i64_ty, llvm_i32_ty]>; - def int_memset_i32 : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_i8_ty, + def int_memset_i32 : Intrinsic<[llvm_void_ty], + [llvm_ptr_ty, llvm_i8_ty, llvm_i32_ty, llvm_i32_ty]>; - def int_memset_i64 : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_i8_ty, + def int_memset_i64 : Intrinsic<[llvm_void_ty], + [llvm_ptr_ty, llvm_i8_ty, llvm_i64_ty, llvm_i32_ty]>; } @@ -206,156 +217,159 @@ // rounding mode. This needs to be modelled separately; in the meantime // declaring them as reading memory is conservatively correct. let Properties = [IntrReadMem] in { - def int_sqrt : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>]>; - def int_powi : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>, llvm_i32_ty]>; - def int_sin : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>]>; - def int_cos : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>]>; - def int_pow : Intrinsic<[llvm_anyfloat_ty, - LLVMMatchType<0>, LLVMMatchType<0>]>; - def int_log : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>]>; - def int_log10: Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>]>; - def int_log2 : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>]>; - def int_exp : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>]>; - def int_exp2 : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>]>; + def int_sqrt : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>; + def int_powi : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty]>; + def int_sin : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>; + def int_cos : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>; + def int_pow : Intrinsic<[llvm_anyfloat_ty], + [LLVMMatchType<0>, LLVMMatchType<0>]>; + def int_log : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>; + def int_log10: Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>; + def int_log2 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>; + def int_exp : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>; + def int_exp2 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>; } // NOTE: these are internal interfaces. -def int_setjmp : Intrinsic<[llvm_i32_ty , llvm_ptr_ty]>; -def int_longjmp : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_i32_ty]>; -def int_sigsetjmp : Intrinsic<[llvm_i32_ty , llvm_ptr_ty, llvm_i32_ty]>; -def int_siglongjmp : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_i32_ty]>; +def int_setjmp : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>; +def int_longjmp : Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_i32_ty]>; +def int_sigsetjmp : Intrinsic<[llvm_i32_ty] , [llvm_ptr_ty, llvm_i32_ty]>; +def int_siglongjmp : Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_i32_ty]>; //===-------------------- Bit Manipulation Intrinsics ---------------------===// // // None of these intrinsics accesses memory at all. let Properties = [IntrNoMem] in { - def int_bswap: Intrinsic<[llvm_anyint_ty, LLVMMatchType<0>]>; - def int_ctpop: Intrinsic<[llvm_anyint_ty, LLVMMatchType<0>]>; - def int_ctlz : Intrinsic<[llvm_anyint_ty, LLVMMatchType<0>]>; - def int_cttz : Intrinsic<[llvm_anyint_ty, LLVMMatchType<0>]>; + def int_bswap: Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>; + def int_ctpop: Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>; + def int_ctlz : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>; + def int_cttz : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>; def int_part_select : - Intrinsic<[llvm_anyint_ty, LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty]>; + Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty]>; def int_part_set : - Intrinsic<[llvm_anyint_ty, LLVMMatchType<0>, llvm_anyint_ty, llvm_i32_ty, - llvm_i32_ty]>; + Intrinsic<[llvm_anyint_ty], + [LLVMMatchType<0>, llvm_anyint_ty, llvm_i32_ty, llvm_i32_ty]>; } //===------------------------ Debugger Intrinsics -------------------------===// // -def int_dbg_stoppoint : Intrinsic<[llvm_void_ty, - llvm_i32_ty, llvm_i32_ty, +def int_dbg_stoppoint : Intrinsic<[llvm_void_ty], + [llvm_i32_ty, llvm_i32_ty, llvm_descriptor_ty]>; -def int_dbg_region_start : Intrinsic<[llvm_void_ty, llvm_descriptor_ty]>; -def int_dbg_region_end : Intrinsic<[llvm_void_ty, llvm_descriptor_ty]>; -def int_dbg_func_start : Intrinsic<[llvm_void_ty, llvm_descriptor_ty]>; -def int_dbg_declare : Intrinsic<[llvm_void_ty, llvm_descriptor_ty, - llvm_descriptor_ty]>; +def int_dbg_region_start : Intrinsic<[llvm_void_ty], [llvm_descriptor_ty]>; +def int_dbg_region_end : Intrinsic<[llvm_void_ty], [llvm_descriptor_ty]>; +def int_dbg_func_start : Intrinsic<[llvm_void_ty], [llvm_descriptor_ty]>; +def int_dbg_declare : Intrinsic<[llvm_void_ty], + [llvm_descriptor_ty, llvm_descriptor_ty]>; //===------------------ Exception Handling Intrinsics----------------------===// // -def int_eh_exception : Intrinsic<[llvm_ptr_ty]>; -def int_eh_selector_i32 : Intrinsic<[llvm_i32_ty, llvm_ptr_ty, llvm_ptr_ty, - llvm_vararg_ty]>; -def int_eh_selector_i64 : Intrinsic<[llvm_i64_ty, llvm_ptr_ty, llvm_ptr_ty, - llvm_vararg_ty]>; +def int_eh_exception : Intrinsic<[llvm_ptr_ty]>; +def int_eh_selector_i32 : Intrinsic<[llvm_i32_ty], + [llvm_ptr_ty, llvm_ptr_ty, llvm_vararg_ty]>; +def int_eh_selector_i64 : Intrinsic<[llvm_i64_ty], + [llvm_ptr_ty, llvm_ptr_ty, llvm_vararg_ty]>; -def int_eh_typeid_for_i32 : Intrinsic<[llvm_i32_ty, llvm_ptr_ty]>; -def int_eh_typeid_for_i64 : Intrinsic<[llvm_i64_ty, llvm_ptr_ty]>; +def int_eh_typeid_for_i32 : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>; +def int_eh_typeid_for_i64 : Intrinsic<[llvm_i64_ty], [llvm_ptr_ty]>; -def int_eh_return_i32 : Intrinsic<[llvm_void_ty, llvm_i32_ty, llvm_ptr_ty]>; -def int_eh_return_i64 : Intrinsic<[llvm_void_ty, llvm_i64_ty, llvm_ptr_ty]>; +def int_eh_return_i32 : Intrinsic<[llvm_void_ty], [llvm_i32_ty, llvm_ptr_ty]>; +def int_eh_return_i64 : Intrinsic<[llvm_void_ty], [llvm_i64_ty, llvm_ptr_ty]>; def int_eh_unwind_init: Intrinsic<[llvm_void_ty]>, GCCBuiltin<"__builtin_unwind_init">; -def int_eh_dwarf_cfa : Intrinsic<[llvm_ptr_ty, llvm_i32_ty]>; +def int_eh_dwarf_cfa : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty]>; //===---------------- Generic Variable Attribute Intrinsics----------------===// // -def int_var_annotation : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_ptr_ty, +def int_var_annotation : Intrinsic<[llvm_void_ty], + [llvm_ptr_ty, llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], [], "llvm.var.annotation">; -def int_ptr_annotation : Intrinsic<[LLVMAnyPointerType, - LLVMMatchType<0>, - llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], - [], "llvm.ptr.annotation">; -def int_annotation : Intrinsic<[llvm_anyint_ty, LLVMMatchType<0>, llvm_ptr_ty, - llvm_ptr_ty, llvm_i32_ty], - [], "llvm.annotation">; +def int_ptr_annotation : Intrinsic<[LLVMAnyPointerType], + [LLVMMatchType<0>, llvm_ptr_ty, llvm_ptr_ty, + llvm_i32_ty], + [], "llvm.ptr.annotation">; +def int_annotation : Intrinsic<[llvm_anyint_ty], + [LLVMMatchType<0>, llvm_ptr_ty, + llvm_ptr_ty, llvm_i32_ty], + [], "llvm.annotation">; //===------------------------ Trampoline Intrinsics -----------------------===// // -def int_init_trampoline : Intrinsic<[llvm_ptr_ty, llvm_ptr_ty, llvm_ptr_ty, - llvm_ptr_ty], []>, +def int_init_trampoline : Intrinsic<[llvm_ptr_ty], + [llvm_ptr_ty, llvm_ptr_ty, llvm_ptr_ty], + []>, GCCBuiltin<"__builtin_init_trampoline">; //===------------------------- Atomic Intrinsics --------------------------===// // -def int_memory_barrier : Intrinsic<[llvm_void_ty, llvm_i1_ty, llvm_i1_ty, +def int_memory_barrier : Intrinsic<[llvm_void_ty], [llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty], []>, GCCBuiltin<"__builtin_llvm_memory_barrier">; -def int_atomic_cmp_swap : Intrinsic<[llvm_anyint_ty, - LLVMAnyPointerType>, - LLVMMatchType<0>, LLVMMatchType<0>], - [IntrWriteArgMem]>, +def int_atomic_cmp_swap : Intrinsic<[llvm_anyint_ty], + [LLVMAnyPointerType>, + LLVMMatchType<0>, LLVMMatchType<0>], + [IntrWriteArgMem]>, GCCBuiltin<"__sync_val_compare_and_swap">; -def int_atomic_load_add : Intrinsic<[llvm_anyint_ty, - LLVMAnyPointerType>, - LLVMMatchType<0>], - [IntrWriteArgMem]>, +def int_atomic_load_add : Intrinsic<[llvm_anyint_ty], + [LLVMAnyPointerType>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, GCCBuiltin<"__sync_fetch_and_add">; -def int_atomic_swap : Intrinsic<[llvm_anyint_ty, - LLVMAnyPointerType>, - LLVMMatchType<0>], - [IntrWriteArgMem]>, +def int_atomic_swap : Intrinsic<[llvm_anyint_ty], + [LLVMAnyPointerType>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, GCCBuiltin<"__sync_lock_test_and_set">; -def int_atomic_load_sub : Intrinsic<[llvm_anyint_ty, - LLVMAnyPointerType>, - LLVMMatchType<0>], - [IntrWriteArgMem]>, +def int_atomic_load_sub : Intrinsic<[llvm_anyint_ty], + [LLVMAnyPointerType>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, GCCBuiltin<"__sync_fetch_and_sub">; -def int_atomic_load_and : Intrinsic<[llvm_anyint_ty, - LLVMAnyPointerType>, - LLVMMatchType<0>], - [IntrWriteArgMem]>, +def int_atomic_load_and : Intrinsic<[llvm_anyint_ty], + [LLVMAnyPointerType>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, GCCBuiltin<"__sync_fetch_and_and">; -def int_atomic_load_or : Intrinsic<[llvm_anyint_ty, - LLVMAnyPointerType>, - LLVMMatchType<0>], - [IntrWriteArgMem]>, +def int_atomic_load_or : Intrinsic<[llvm_anyint_ty], + [LLVMAnyPointerType>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, GCCBuiltin<"__sync_fetch_and_or">; -def int_atomic_load_xor : Intrinsic<[llvm_anyint_ty, - LLVMAnyPointerType>, - LLVMMatchType<0>], - [IntrWriteArgMem]>, +def int_atomic_load_xor : Intrinsic<[llvm_anyint_ty], + [LLVMAnyPointerType>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, GCCBuiltin<"__sync_fetch_and_xor">; -def int_atomic_load_nand : Intrinsic<[llvm_anyint_ty, - LLVMAnyPointerType>, - LLVMMatchType<0>], - [IntrWriteArgMem]>, +def int_atomic_load_nand : Intrinsic<[llvm_anyint_ty], + [LLVMAnyPointerType>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, GCCBuiltin<"__sync_fetch_and_nand">; -def int_atomic_load_min : Intrinsic<[llvm_anyint_ty, - LLVMAnyPointerType>, - LLVMMatchType<0>], - [IntrWriteArgMem]>, +def int_atomic_load_min : Intrinsic<[llvm_anyint_ty], + [LLVMAnyPointerType>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, GCCBuiltin<"__sync_fetch_and_min">; -def int_atomic_load_max : Intrinsic<[llvm_anyint_ty, - LLVMAnyPointerType>, - LLVMMatchType<0>], - [IntrWriteArgMem]>, +def int_atomic_load_max : Intrinsic<[llvm_anyint_ty], + [LLVMAnyPointerType>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, GCCBuiltin<"__sync_fetch_and_max">; -def int_atomic_load_umin : Intrinsic<[llvm_anyint_ty, - LLVMAnyPointerType>, - LLVMMatchType<0>], - [IntrWriteArgMem]>, +def int_atomic_load_umin : Intrinsic<[llvm_anyint_ty], + [LLVMAnyPointerType>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, GCCBuiltin<"__sync_fetch_and_umin">; -def int_atomic_load_umax : Intrinsic<[llvm_anyint_ty, - LLVMAnyPointerType>, - LLVMMatchType<0>], - [IntrWriteArgMem]>, +def int_atomic_load_umax : Intrinsic<[llvm_anyint_ty], + [LLVMAnyPointerType>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, GCCBuiltin<"__sync_fetch_and_umax">; //===-------------------------- Other Intrinsics --------------------------===// @@ -369,24 +383,24 @@ // various types with rounding and saturation. NOTE: avoid using these // intrinsics as they might be removed sometime in the future and // most targets don't support them. -def int_convertff : Intrinsic<[llvm_anyfloat_ty, llvm_anyfloat_ty, - llvm_i32_ty, llvm_i32_ty]>; -def int_convertfsi : Intrinsic<[llvm_anyfloat_ty, llvm_anyint_ty, - llvm_i32_ty, llvm_i32_ty]>; -def int_convertfui : Intrinsic<[llvm_anyfloat_ty, llvm_anyint_ty, - llvm_i32_ty, llvm_i32_ty]>; -def int_convertsif : Intrinsic<[llvm_anyint_ty, llvm_anyfloat_ty, - llvm_i32_ty, llvm_i32_ty]>; -def int_convertuif : Intrinsic<[llvm_anyint_ty, llvm_anyfloat_ty, - llvm_i32_ty, llvm_i32_ty]>; -def int_convertss : Intrinsic<[llvm_anyint_ty, llvm_anyint_ty, - llvm_i32_ty, llvm_i32_ty]>; -def int_convertsu : Intrinsic<[llvm_anyint_ty, llvm_anyint_ty, - llvm_i32_ty, llvm_i32_ty]>; -def int_convertus : Intrinsic<[llvm_anyint_ty, llvm_anyint_ty, - llvm_i32_ty, llvm_i32_ty]>; -def int_convertuu : Intrinsic<[llvm_anyint_ty, llvm_anyint_ty, - llvm_i32_ty, llvm_i32_ty]>; +def int_convertff : Intrinsic<[llvm_anyfloat_ty], + [llvm_anyfloat_ty, llvm_i32_ty, llvm_i32_ty]>; +def int_convertfsi : Intrinsic<[llvm_anyfloat_ty], + [llvm_anyint_ty, llvm_i32_ty, llvm_i32_ty]>; +def int_convertfui : Intrinsic<[llvm_anyfloat_ty], + [llvm_anyint_ty, llvm_i32_ty, llvm_i32_ty]>; +def int_convertsif : Intrinsic<[llvm_anyint_ty], + [llvm_anyfloat_ty, llvm_i32_ty, llvm_i32_ty]>; +def int_convertuif : Intrinsic<[llvm_anyint_ty], + [llvm_anyfloat_ty, llvm_i32_ty, llvm_i32_ty]>; +def int_convertss : Intrinsic<[llvm_anyint_ty], + [llvm_anyint_ty, llvm_i32_ty, llvm_i32_ty]>; +def int_convertsu : Intrinsic<[llvm_anyint_ty], + [llvm_anyint_ty, llvm_i32_ty, llvm_i32_ty]>; +def int_convertus : Intrinsic<[llvm_anyint_ty], + [llvm_anyint_ty, llvm_i32_ty, llvm_i32_ty]>; +def int_convertuu : Intrinsic<[llvm_anyint_ty], + [llvm_anyint_ty, llvm_i32_ty, llvm_i32_ty]>; //===----------------------------------------------------------------------===// // Target-specific intrinsics Modified: llvm/trunk/include/llvm/IntrinsicsARM.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsARM.td?rev=59237&r1=59236&r2=59237&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsARM.td (original) +++ llvm/trunk/include/llvm/IntrinsicsARM.td Thu Nov 13 03:08:33 2008 @@ -17,5 +17,5 @@ let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.". def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">, - Intrinsic<[llvm_ptr_ty],[IntrNoMem]>; + Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>; } Modified: llvm/trunk/include/llvm/IntrinsicsAlpha.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsAlpha.td?rev=59237&r1=59236&r2=59237&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsAlpha.td (original) +++ llvm/trunk/include/llvm/IntrinsicsAlpha.td Thu Nov 13 03:08:33 2008 @@ -14,6 +14,5 @@ let TargetPrefix = "alpha" in { // All intrinsics start with "llvm.alpha.". def int_alpha_umulh : GCCBuiltin<"__builtin_alpha_umulh">, - Intrinsic<[llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>; - + Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>; } Modified: llvm/trunk/include/llvm/IntrinsicsCellSPU.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsCellSPU.td?rev=59237&r1=59236&r2=59237&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsCellSPU.td (original) +++ llvm/trunk/include/llvm/IntrinsicsCellSPU.td Thu Nov 13 03:08:33 2008 @@ -25,77 +25,77 @@ class v16i8_u7imm : GCCBuiltin, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, cell_i7_ty], + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, cell_i7_ty], [IntrNoMem]>; class v16i8_u8imm : GCCBuiltin, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty], + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i8_ty], [IntrNoMem]>; class v16i8_s10imm : GCCBuiltin, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty], + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i16_ty], [IntrNoMem]>; class v16i8_u16imm : GCCBuiltin, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty], + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i16_ty], [IntrNoMem]>; class v16i8_rr : GCCBuiltin, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; class v8i16_s10imm : GCCBuiltin, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_i16_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i16_ty], [IntrNoMem]>; class v8i16_u16imm : GCCBuiltin, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_i16_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i16_ty], [IntrNoMem]>; class v8i16_rr : GCCBuiltin, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; class v4i32_rr : GCCBuiltin, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; class v4i32_u7imm : GCCBuiltin, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, cell_i7_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, cell_i7_ty], [IntrNoMem]>; class v4i32_s10imm : GCCBuiltin, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i16_ty], [IntrNoMem]>; class v4i32_u16imm : GCCBuiltin, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i16_ty], [IntrNoMem]>; class v4f32_rr : GCCBuiltin, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; class v4f32_rrr : GCCBuiltin, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; class v2f64_rr : GCCBuiltin, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; // All Cell SPU intrinsics start with "llvm.spu.". @@ -117,60 +117,60 @@ def int_spu_si_bgx : v4i32_rr<"bgx">; def int_spu_si_mpy : // This is special: GCCBuiltin<"__builtin_si_mpy">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_spu_si_mpyu : // This is special: GCCBuiltin<"__builtin_si_mpyu">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_spu_si_mpyi : // This is special: GCCBuiltin<"__builtin_si_mpyi">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_i16_ty], [IntrNoMem]>; def int_spu_si_mpyui : // This is special: GCCBuiltin<"__builtin_si_mpyui">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_i16_ty], [IntrNoMem]>; def int_spu_si_mpya : // This is special: GCCBuiltin<"__builtin_si_mpya">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_spu_si_mpyh : // This is special: GCCBuiltin<"__builtin_si_mpyh">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_spu_si_mpys : // This is special: GCCBuiltin<"__builtin_si_mpys">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_spu_si_mpyhh : // This is special: GCCBuiltin<"__builtin_si_mpyhh">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_spu_si_mpyhha : // This is special: GCCBuiltin<"__builtin_si_mpyhha">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_spu_si_mpyhhu : // This is special: GCCBuiltin<"__builtin_si_mpyhhu">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_spu_si_mpyhhau : // This is special: GCCBuiltin<"__builtin_si_mpyhhau">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_spu_si_shli: v4i32_u7imm<"shli">; def int_spu_si_shlqbi: GCCBuiltin, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>; def int_spu_si_shlqbii: v16i8_u7imm<"shlqbii">; def int_spu_si_shlqby: GCCBuiltin, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>; def int_spu_si_shlqbyi: v16i8_u7imm<"shlqbyi">; Modified: llvm/trunk/include/llvm/IntrinsicsPowerPC.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsPowerPC.td?rev=59237&r1=59236&r2=59237&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsPowerPC.td (original) +++ llvm/trunk/include/llvm/IntrinsicsPowerPC.td Thu Nov 13 03:08:33 2008 @@ -18,26 +18,27 @@ // Non-altivec intrinsics. let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". // dcba/dcbf/dcbi/dcbst/dcbt/dcbz/dcbzl(PPC970) instructions. - def int_ppc_dcba : Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>; - def int_ppc_dcbf : Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>; - def int_ppc_dcbi : Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>; - def int_ppc_dcbst : Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>; - def int_ppc_dcbt : Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>; - def int_ppc_dcbtst: Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>; - def int_ppc_dcbz : Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>; - def int_ppc_dcbzl : Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>; + def int_ppc_dcba : Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>; + def int_ppc_dcbf : Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>; + def int_ppc_dcbi : Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>; + def int_ppc_dcbst : Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>; + def int_ppc_dcbt : Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>; + def int_ppc_dcbtst: Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>; + def int_ppc_dcbz : Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>; + def int_ppc_dcbzl : Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>; // sync instruction - def int_ppc_sync : Intrinsic<[llvm_void_ty], [IntrWriteMem]>; + def int_ppc_sync : Intrinsic<[llvm_void_ty], [], [IntrWriteMem]>; } let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.". /// PowerPC_Vec_Intrinsic - Base class for all altivec intrinsics. - class PowerPC_Vec_Intrinsic types, + class PowerPC_Vec_Intrinsic ret_types, + list param_types, list properties> : GCCBuiltin, - Intrinsic; + Intrinsic; } //===----------------------------------------------------------------------===// @@ -48,34 +49,34 @@ /// vector and returns one. These intrinsics have no side effects. class PowerPC_Vec_FF_Intrinsic : PowerPC_Vec_Intrinsic; + [llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; /// PowerPC_Vec_FFF_Intrinsic - A PowerPC intrinsic that takes two v4f32 /// vectors and returns one. These intrinsics have no side effects. class PowerPC_Vec_FFF_Intrinsic : PowerPC_Vec_Intrinsic; /// PowerPC_Vec_BBB_Intrinsic - A PowerPC intrinsic that takes two v16f8 /// vectors and returns one. These intrinsics have no side effects. class PowerPC_Vec_BBB_Intrinsic : PowerPC_Vec_Intrinsic; /// PowerPC_Vec_HHH_Intrinsic - A PowerPC intrinsic that takes two v8i16 /// vectors and returns one. These intrinsics have no side effects. class PowerPC_Vec_HHH_Intrinsic : PowerPC_Vec_Intrinsic; /// PowerPC_Vec_WWW_Intrinsic - A PowerPC intrinsic that takes two v4i32 /// vectors and returns one. These intrinsics have no side effects. class PowerPC_Vec_WWW_Intrinsic : PowerPC_Vec_Intrinsic; @@ -85,146 +86,150 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". // Data Stream Control. def int_ppc_altivec_dss : GCCBuiltin<"__builtin_altivec_dss">, - Intrinsic<[llvm_void_ty, llvm_i32_ty], [IntrWriteMem]>; + Intrinsic<[llvm_void_ty], [llvm_i32_ty], [IntrWriteMem]>; def int_ppc_altivec_dssall : GCCBuiltin<"__builtin_altivec_dssall">, - Intrinsic<[llvm_void_ty], [IntrWriteMem]>; + Intrinsic<[llvm_void_ty], [], [IntrWriteMem]>; def int_ppc_altivec_dst : GCCBuiltin<"__builtin_altivec_dst">, - Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + Intrinsic<[llvm_void_ty], + [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [IntrWriteMem]>; def int_ppc_altivec_dstt : GCCBuiltin<"__builtin_altivec_dstt">, - Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + Intrinsic<[llvm_void_ty], + [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [IntrWriteMem]>; def int_ppc_altivec_dstst : GCCBuiltin<"__builtin_altivec_dstst">, - Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + Intrinsic<[llvm_void_ty], + [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [IntrWriteMem]>; def int_ppc_altivec_dststt : GCCBuiltin<"__builtin_altivec_dststt">, - Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + Intrinsic<[llvm_void_ty], + [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [IntrWriteMem]>; // VSCR access. def int_ppc_altivec_mfvscr : GCCBuiltin<"__builtin_altivec_mfvscr">, - Intrinsic<[llvm_v8i16_ty], [IntrReadMem]>; + Intrinsic<[llvm_v8i16_ty], [], [IntrReadMem]>; def int_ppc_altivec_mtvscr : GCCBuiltin<"__builtin_altivec_mtvscr">, - Intrinsic<[llvm_void_ty, llvm_v4i32_ty], [IntrWriteMem]>; + Intrinsic<[llvm_void_ty], [llvm_v4i32_ty], [IntrWriteMem]>; // Loads. These don't map directly to GCC builtins because they represent the // source address with a single pointer. def int_ppc_altivec_lvx : - Intrinsic<[llvm_v4i32_ty, llvm_ptr_ty], [IntrReadMem]>; + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], [IntrReadMem]>; def int_ppc_altivec_lvxl : - Intrinsic<[llvm_v4i32_ty, llvm_ptr_ty], [IntrReadMem]>; + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], [IntrReadMem]>; def int_ppc_altivec_lvebx : - Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [IntrReadMem]>; + Intrinsic<[llvm_v16i8_ty], [llvm_ptr_ty], [IntrReadMem]>; def int_ppc_altivec_lvehx : - Intrinsic<[llvm_v8i16_ty, llvm_ptr_ty], [IntrReadMem]>; + Intrinsic<[llvm_v8i16_ty], [llvm_ptr_ty], [IntrReadMem]>; def int_ppc_altivec_lvewx : - Intrinsic<[llvm_v4i32_ty, llvm_ptr_ty], [IntrReadMem]>; + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], [IntrReadMem]>; // Stores. These don't map directly to GCC builtins because they represent the // source address with a single pointer. def int_ppc_altivec_stvx : - Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_ptr_ty], + Intrinsic<[llvm_void_ty], [llvm_v4i32_ty, llvm_ptr_ty], [IntrWriteMem]>; def int_ppc_altivec_stvxl : - Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_ptr_ty], + Intrinsic<[llvm_void_ty], [llvm_v4i32_ty, llvm_ptr_ty], [IntrWriteMem]>; def int_ppc_altivec_stvebx : - Intrinsic<[llvm_void_ty, llvm_v16i8_ty, llvm_ptr_ty], + Intrinsic<[llvm_void_ty], [llvm_v16i8_ty, llvm_ptr_ty], [IntrWriteMem]>; def int_ppc_altivec_stvehx : - Intrinsic<[llvm_void_ty, llvm_v8i16_ty, llvm_ptr_ty], + Intrinsic<[llvm_void_ty], [llvm_v8i16_ty, llvm_ptr_ty], [IntrWriteMem]>; def int_ppc_altivec_stvewx : - Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_ptr_ty], + Intrinsic<[llvm_void_ty], [llvm_v4i32_ty, llvm_ptr_ty], [IntrWriteMem]>; // Comparisons setting a vector. def int_ppc_altivec_vcmpbfp : GCCBuiltin<"__builtin_altivec_vcmpbfp">, - Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_v4f32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpeqfp : GCCBuiltin<"__builtin_altivec_vcmpeqfp">, - Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_v4f32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpgefp : GCCBuiltin<"__builtin_altivec_vcmpgefp">, - Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_v4f32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpgtfp : GCCBuiltin<"__builtin_altivec_vcmpgtfp">, - Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_v4f32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpequw : GCCBuiltin<"__builtin_altivec_vcmpequw">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpgtsw : GCCBuiltin<"__builtin_altivec_vcmpgtsw">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpgtuw : GCCBuiltin<"__builtin_altivec_vcmpgtuw">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpequh : GCCBuiltin<"__builtin_altivec_vcmpequh">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpgtsh : GCCBuiltin<"__builtin_altivec_vcmpgtsh">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpgtuh : GCCBuiltin<"__builtin_altivec_vcmpgtuh">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpequb : GCCBuiltin<"__builtin_altivec_vcmpequb">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpgtsb : GCCBuiltin<"__builtin_altivec_vcmpgtsb">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpgtub : GCCBuiltin<"__builtin_altivec_vcmpgtub">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; // Predicate Comparisons. The first operand specifies interpretation of CR6. def int_ppc_altivec_vcmpbfp_p : GCCBuiltin<"__builtin_altivec_vcmpbfp_p">, - Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_v4f32_ty,llvm_v4f32_ty], + Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v4f32_ty,llvm_v4f32_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpeqfp_p : GCCBuiltin<"__builtin_altivec_vcmpeqfp_p">, - Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_v4f32_ty,llvm_v4f32_ty], + Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v4f32_ty,llvm_v4f32_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpgefp_p : GCCBuiltin<"__builtin_altivec_vcmpgefp_p">, - Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_v4f32_ty,llvm_v4f32_ty], + Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v4f32_ty,llvm_v4f32_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpgtfp_p : GCCBuiltin<"__builtin_altivec_vcmpgtfp_p">, - Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_v4f32_ty,llvm_v4f32_ty], + Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v4f32_ty,llvm_v4f32_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpequw_p : GCCBuiltin<"__builtin_altivec_vcmpequw_p">, - Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_v4i32_ty,llvm_v4i32_ty], + Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v4i32_ty,llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpgtsw_p : GCCBuiltin<"__builtin_altivec_vcmpgtsw_p">, - Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_v4i32_ty,llvm_v4i32_ty], + Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v4i32_ty,llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpgtuw_p : GCCBuiltin<"__builtin_altivec_vcmpgtuw_p">, - Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_v4i32_ty,llvm_v4i32_ty], + Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v4i32_ty,llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpequh_p : GCCBuiltin<"__builtin_altivec_vcmpequh_p">, - Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_v8i16_ty,llvm_v8i16_ty], + Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v8i16_ty,llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpgtsh_p : GCCBuiltin<"__builtin_altivec_vcmpgtsh_p">, - Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_v8i16_ty,llvm_v8i16_ty], + Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v8i16_ty,llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpgtuh_p : GCCBuiltin<"__builtin_altivec_vcmpgtuh_p">, - Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_v8i16_ty,llvm_v8i16_ty], + Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v8i16_ty,llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpequb_p : GCCBuiltin<"__builtin_altivec_vcmpequb_p">, - Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_v16i8_ty,llvm_v16i8_ty], + Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v16i8_ty,llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpgtsb_p : GCCBuiltin<"__builtin_altivec_vcmpgtsb_p">, - Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_v16i8_ty,llvm_v16i8_ty], + Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v16i8_ty,llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_altivec_vcmpgtub_p : GCCBuiltin<"__builtin_altivec_vcmpgtub_p">, - Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_v16i8_ty,llvm_v16i8_ty], + Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v16i8_ty,llvm_v16i8_ty], [IntrNoMem]>; } @@ -275,150 +280,150 @@ let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.". // Saturating multiply-adds. def int_ppc_altivec_vmhaddshs : GCCBuiltin<"__builtin_altivec_vmhaddshs">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vmhraddshs : GCCBuiltin<"__builtin_altivec_vmhraddshs">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vmaddfp : GCCBuiltin<"__builtin_altivec_vmaddfp">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_ppc_altivec_vnmsubfp : GCCBuiltin<"__builtin_altivec_vnmsubfp">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; // Vector Multiply Sum Intructions. def int_ppc_altivec_vmsummbm : GCCBuiltin<"__builtin_altivec_vmsummbm">, - Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vmsumshm : GCCBuiltin<"__builtin_altivec_vmsumshm">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vmsumshs : GCCBuiltin<"__builtin_altivec_vmsumshs">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vmsumubm : GCCBuiltin<"__builtin_altivec_vmsumubm">, - Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vmsumuhm : GCCBuiltin<"__builtin_altivec_vmsumuhm">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vmsumuhs : GCCBuiltin<"__builtin_altivec_vmsumuhs">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty], [IntrNoMem]>; // Vector Multiply Intructions. def int_ppc_altivec_vmulesb : GCCBuiltin<"__builtin_altivec_vmulesb">, - Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_altivec_vmulesh : GCCBuiltin<"__builtin_altivec_vmulesh">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vmuleub : GCCBuiltin<"__builtin_altivec_vmuleub">, - Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_altivec_vmuleuh : GCCBuiltin<"__builtin_altivec_vmuleuh">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vmulosb : GCCBuiltin<"__builtin_altivec_vmulosb">, - Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_altivec_vmulosh : GCCBuiltin<"__builtin_altivec_vmulosh">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vmuloub : GCCBuiltin<"__builtin_altivec_vmuloub">, - Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_altivec_vmulouh : GCCBuiltin<"__builtin_altivec_vmulouh">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; // Vector Sum Intructions. def int_ppc_altivec_vsumsws : GCCBuiltin<"__builtin_altivec_vsumsws">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vsum2sws : GCCBuiltin<"__builtin_altivec_vsum2sws">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vsum4sbs : GCCBuiltin<"__builtin_altivec_vsum4sbs">, - Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vsum4shs : GCCBuiltin<"__builtin_altivec_vsum4shs">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vsum4ubs : GCCBuiltin<"__builtin_altivec_vsum4ubs">, - Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_v4i32_ty], [IntrNoMem]>; // Other multiplies. def int_ppc_altivec_vmladduhm : GCCBuiltin<"__builtin_altivec_vmladduhm">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; // Packs. def int_ppc_altivec_vpkpx : GCCBuiltin<"__builtin_altivec_vpkpx">, - Intrinsic<[llvm_v8i16_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vpkshss : GCCBuiltin<"__builtin_altivec_vpkshss">, - Intrinsic<[llvm_v16i8_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v16i8_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vpkshus : GCCBuiltin<"__builtin_altivec_vpkshus">, - Intrinsic<[llvm_v16i8_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v16i8_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vpkswss : GCCBuiltin<"__builtin_altivec_vpkswss">, - Intrinsic<[llvm_v16i8_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v16i8_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vpkswus : GCCBuiltin<"__builtin_altivec_vpkswus">, - Intrinsic<[llvm_v8i16_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; // vpkuhum is lowered to a shuffle. def int_ppc_altivec_vpkuhus : GCCBuiltin<"__builtin_altivec_vpkuhus">, - Intrinsic<[llvm_v16i8_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v16i8_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; // vpkuwum is lowered to a shuffle. def int_ppc_altivec_vpkuwus : GCCBuiltin<"__builtin_altivec_vpkuwus">, - Intrinsic<[llvm_v8i16_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; // Unpacks. def int_ppc_altivec_vupkhpx : GCCBuiltin<"__builtin_altivec_vupkhpx">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vupkhsb : GCCBuiltin<"__builtin_altivec_vupkhsb">, - Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty], [IntrNoMem]>; + Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_altivec_vupkhsh : GCCBuiltin<"__builtin_altivec_vupkhsh">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vupklpx : GCCBuiltin<"__builtin_altivec_vupklpx">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vupklsb : GCCBuiltin<"__builtin_altivec_vupklsb">, - Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty], [IntrNoMem]>; + Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_altivec_vupklsh : GCCBuiltin<"__builtin_altivec_vupklsh">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty], [IntrNoMem]>; // FP <-> integer conversion. def int_ppc_altivec_vcfsx : GCCBuiltin<"__builtin_altivec_vcfsx">, - Intrinsic<[llvm_v4f32_ty, llvm_v4i32_ty, llvm_i32_ty], + Intrinsic<[llvm_v4f32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_ppc_altivec_vcfux : GCCBuiltin<"__builtin_altivec_vcfux">, - Intrinsic<[llvm_v4f32_ty, llvm_v4i32_ty, llvm_i32_ty], + Intrinsic<[llvm_v4f32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_ppc_altivec_vctsxs : GCCBuiltin<"__builtin_altivec_vctsxs">, - Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_i32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>; def int_ppc_altivec_vctuxs : GCCBuiltin<"__builtin_altivec_vctuxs">, - Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_i32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>; def int_ppc_altivec_vrfim : GCCBuiltin<"__builtin_altivec_vrfim">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_ppc_altivec_vrfin : GCCBuiltin<"__builtin_altivec_vrfin">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_ppc_altivec_vrfip : GCCBuiltin<"__builtin_altivec_vrfip">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_ppc_altivec_vrfiz : GCCBuiltin<"__builtin_altivec_vrfiz">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; } def int_ppc_altivec_vsl : PowerPC_Vec_WWW_Intrinsic<"vsl">; @@ -447,15 +452,15 @@ let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.". // Miscellaneous. def int_ppc_altivec_lvsl : - Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [IntrNoMem]>; + Intrinsic<[llvm_v16i8_ty], [llvm_ptr_ty], [IntrNoMem]>; def int_ppc_altivec_lvsr : - Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [IntrNoMem]>; + Intrinsic<[llvm_v16i8_ty], [llvm_ptr_ty], [IntrNoMem]>; def int_ppc_altivec_vperm : GCCBuiltin<"__builtin_altivec_vperm_4si">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_altivec_vsel : GCCBuiltin<"__builtin_altivec_vsel_4si">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; } Modified: llvm/trunk/include/llvm/IntrinsicsX86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=59237&r1=59236&r2=59237&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) +++ llvm/trunk/include/llvm/IntrinsicsX86.td Thu Nov 13 03:08:33 2008 @@ -18,92 +18,92 @@ // Arithmetic ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse_add_ss : GCCBuiltin<"__builtin_ia32_addss">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem, Commutative]>; def int_x86_sse_sub_ss : GCCBuiltin<"__builtin_ia32_subss">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_mul_ss : GCCBuiltin<"__builtin_ia32_mulss">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem, Commutative]>; def int_x86_sse_div_ss : GCCBuiltin<"__builtin_ia32_divss">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_sqrt_ss : GCCBuiltin<"__builtin_ia32_sqrtss">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_sqrt_ps : GCCBuiltin<"__builtin_ia32_sqrtps">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_rcp_ss : GCCBuiltin<"__builtin_ia32_rcpss">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_rcp_ps : GCCBuiltin<"__builtin_ia32_rcpps">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_rsqrt_ss : GCCBuiltin<"__builtin_ia32_rsqrtss">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_rsqrt_ps : GCCBuiltin<"__builtin_ia32_rsqrtps">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_min_ss : GCCBuiltin<"__builtin_ia32_minss">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_min_ps : GCCBuiltin<"__builtin_ia32_minps">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_max_ss : GCCBuiltin<"__builtin_ia32_maxss">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_max_ps : GCCBuiltin<"__builtin_ia32_maxps">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; } // Comparison ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse_cmp_ss : - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty], [IntrNoMem]>; def int_x86_sse_cmp_ps : - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty], [IntrNoMem]>; def int_x86_sse_comieq_ss : GCCBuiltin<"__builtin_ia32_comieq">, - Intrinsic<[llvm_i32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_comilt_ss : GCCBuiltin<"__builtin_ia32_comilt">, - Intrinsic<[llvm_i32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_comile_ss : GCCBuiltin<"__builtin_ia32_comile">, - Intrinsic<[llvm_i32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_comigt_ss : GCCBuiltin<"__builtin_ia32_comigt">, - Intrinsic<[llvm_i32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_comige_ss : GCCBuiltin<"__builtin_ia32_comige">, - Intrinsic<[llvm_i32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_comineq_ss : GCCBuiltin<"__builtin_ia32_comineq">, - Intrinsic<[llvm_i32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_ucomieq_ss : GCCBuiltin<"__builtin_ia32_ucomieq">, - Intrinsic<[llvm_i32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_ucomilt_ss : GCCBuiltin<"__builtin_ia32_ucomilt">, - Intrinsic<[llvm_i32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_ucomile_ss : GCCBuiltin<"__builtin_ia32_ucomile">, - Intrinsic<[llvm_i32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_ucomigt_ss : GCCBuiltin<"__builtin_ia32_ucomigt">, - Intrinsic<[llvm_i32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_ucomige_ss : GCCBuiltin<"__builtin_ia32_ucomige">, - Intrinsic<[llvm_i32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_ucomineq_ss : GCCBuiltin<"__builtin_ia32_ucomineq">, - Intrinsic<[llvm_i32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; } @@ -111,62 +111,62 @@ // Conversion ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse_cvtss2si : GCCBuiltin<"__builtin_ia32_cvtss2si">, - Intrinsic<[llvm_i32_ty, llvm_v4f32_ty], [IntrNoMem]>; + Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_cvtss2si64 : GCCBuiltin<"__builtin_ia32_cvtss2si64">, - Intrinsic<[llvm_i64_ty, llvm_v4f32_ty], [IntrNoMem]>; + Intrinsic<[llvm_i64_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_cvttss2si : GCCBuiltin<"__builtin_ia32_cvttss2si">, - Intrinsic<[llvm_i32_ty, llvm_v4f32_ty], [IntrNoMem]>; + Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_cvttss2si64 : GCCBuiltin<"__builtin_ia32_cvttss2si64">, - Intrinsic<[llvm_i64_ty, llvm_v4f32_ty], [IntrNoMem]>; + Intrinsic<[llvm_i64_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_cvtsi2ss : GCCBuiltin<"__builtin_ia32_cvtsi2ss">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse_cvtsi642ss : GCCBuiltin<"__builtin_ia32_cvtsi642ss">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i64_ty], [IntrNoMem]>; def int_x86_sse_cvtps2pi : GCCBuiltin<"__builtin_ia32_cvtps2pi">, - Intrinsic<[llvm_v2i32_ty, llvm_v4f32_ty], [IntrNoMem]>; + Intrinsic<[llvm_v2i32_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_cvttps2pi: GCCBuiltin<"__builtin_ia32_cvttps2pi">, - Intrinsic<[llvm_v2i32_ty, llvm_v4f32_ty], [IntrNoMem]>; + Intrinsic<[llvm_v2i32_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_cvtpi2ps : GCCBuiltin<"__builtin_ia32_cvtpi2ps">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v2i32_ty], [IntrNoMem]>; } // SIMD load ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse_loadu_ps : GCCBuiltin<"__builtin_ia32_loadups">, - Intrinsic<[llvm_v4f32_ty, llvm_ptr_ty], [IntrReadMem]>; + Intrinsic<[llvm_v4f32_ty], [llvm_ptr_ty], [IntrReadMem]>; } // SIMD store ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse_storeu_ps : GCCBuiltin<"__builtin_ia32_storeups">, - Intrinsic<[llvm_void_ty, llvm_ptr_ty, + Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>; } // Cacheability support ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">, - Intrinsic<[llvm_void_ty, llvm_ptr_ty, + Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>; def int_x86_sse_sfence : GCCBuiltin<"__builtin_ia32_sfence">, - Intrinsic<[llvm_void_ty], [IntrWriteMem]>; + Intrinsic<[llvm_void_ty], [], [IntrWriteMem]>; } // Control register. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse_stmxcsr : - Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>; + Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>; def int_x86_sse_ldmxcsr : - Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>; + Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>; } // Misc. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse_movmsk_ps : GCCBuiltin<"__builtin_ia32_movmskps">, - Intrinsic<[llvm_i32_ty, llvm_v4f32_ty], [IntrNoMem]>; + Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty], [IntrNoMem]>; } //===----------------------------------------------------------------------===// @@ -175,336 +175,336 @@ // FP arithmetic ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_add_sd : GCCBuiltin<"__builtin_ia32_addsd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem, Commutative]>; def int_x86_sse2_sub_sd : GCCBuiltin<"__builtin_ia32_subsd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_mul_sd : GCCBuiltin<"__builtin_ia32_mulsd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem, Commutative]>; def int_x86_sse2_div_sd : GCCBuiltin<"__builtin_ia32_divsd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_sqrt_sd : GCCBuiltin<"__builtin_ia32_sqrtsd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty], + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_sqrt_pd : GCCBuiltin<"__builtin_ia32_sqrtpd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty], + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_min_sd : GCCBuiltin<"__builtin_ia32_minsd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_min_pd : GCCBuiltin<"__builtin_ia32_minpd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_max_sd : GCCBuiltin<"__builtin_ia32_maxsd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_max_pd : GCCBuiltin<"__builtin_ia32_maxpd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; } // FP comparison ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_cmp_sd : - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty], [IntrNoMem]>; def int_x86_sse2_cmp_pd : - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty], [IntrNoMem]>; def int_x86_sse2_comieq_sd : GCCBuiltin<"__builtin_ia32_comisdeq">, - Intrinsic<[llvm_i32_ty, llvm_v2f64_ty, + Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_comilt_sd : GCCBuiltin<"__builtin_ia32_comisdlt">, - Intrinsic<[llvm_i32_ty, llvm_v2f64_ty, + Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_comile_sd : GCCBuiltin<"__builtin_ia32_comisdle">, - Intrinsic<[llvm_i32_ty, llvm_v2f64_ty, + Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_comigt_sd : GCCBuiltin<"__builtin_ia32_comisdgt">, - Intrinsic<[llvm_i32_ty, llvm_v2f64_ty, + Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_comige_sd : GCCBuiltin<"__builtin_ia32_comisdge">, - Intrinsic<[llvm_i32_ty, llvm_v2f64_ty, + Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_comineq_sd : GCCBuiltin<"__builtin_ia32_comisdneq">, - Intrinsic<[llvm_i32_ty, llvm_v2f64_ty, + Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_ucomieq_sd : GCCBuiltin<"__builtin_ia32_ucomisdeq">, - Intrinsic<[llvm_i32_ty, llvm_v2f64_ty, + Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_ucomilt_sd : GCCBuiltin<"__builtin_ia32_ucomisdlt">, - Intrinsic<[llvm_i32_ty, llvm_v2f64_ty, + Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_ucomile_sd : GCCBuiltin<"__builtin_ia32_ucomisdle">, - Intrinsic<[llvm_i32_ty, llvm_v2f64_ty, + Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_ucomigt_sd : GCCBuiltin<"__builtin_ia32_ucomisdgt">, - Intrinsic<[llvm_i32_ty, llvm_v2f64_ty, + Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_ucomige_sd : GCCBuiltin<"__builtin_ia32_ucomisdge">, - Intrinsic<[llvm_i32_ty, llvm_v2f64_ty, + Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_ucomineq_sd : GCCBuiltin<"__builtin_ia32_ucomisdneq">, - Intrinsic<[llvm_i32_ty, llvm_v2f64_ty, + Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; } // Integer arithmetic ops. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_padds_b : GCCBuiltin<"__builtin_ia32_paddsb128">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem, Commutative]>; def int_x86_sse2_padds_w : GCCBuiltin<"__builtin_ia32_paddsw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem, Commutative]>; def int_x86_sse2_paddus_b : GCCBuiltin<"__builtin_ia32_paddusb128">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem, Commutative]>; def int_x86_sse2_paddus_w : GCCBuiltin<"__builtin_ia32_paddusw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem, Commutative]>; def int_x86_sse2_psubs_b : GCCBuiltin<"__builtin_ia32_psubsb128">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_x86_sse2_psubs_w : GCCBuiltin<"__builtin_ia32_psubsw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_x86_sse2_psubus_b : GCCBuiltin<"__builtin_ia32_psubusb128">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_x86_sse2_psubus_w : GCCBuiltin<"__builtin_ia32_psubusw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_x86_sse2_pmulhu_w : GCCBuiltin<"__builtin_ia32_pmulhuw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem, Commutative]>; def int_x86_sse2_pmulh_w : GCCBuiltin<"__builtin_ia32_pmulhw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem, Commutative]>; def int_x86_sse2_pmulu_dq : GCCBuiltin<"__builtin_ia32_pmuludq128">, - Intrinsic<[llvm_v2i64_ty, llvm_v4i32_ty, + Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem, Commutative]>; def int_x86_sse2_pmadd_wd : GCCBuiltin<"__builtin_ia32_pmaddwd128">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem, Commutative]>; def int_x86_sse2_pavg_b : GCCBuiltin<"__builtin_ia32_pavgb128">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem, Commutative]>; def int_x86_sse2_pavg_w : GCCBuiltin<"__builtin_ia32_pavgw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem, Commutative]>; def int_x86_sse2_pmaxu_b : GCCBuiltin<"__builtin_ia32_pmaxub128">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem, Commutative]>; def int_x86_sse2_pmaxs_w : GCCBuiltin<"__builtin_ia32_pmaxsw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem, Commutative]>; def int_x86_sse2_pminu_b : GCCBuiltin<"__builtin_ia32_pminub128">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem, Commutative]>; def int_x86_sse2_pmins_w : GCCBuiltin<"__builtin_ia32_pminsw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem, Commutative]>; def int_x86_sse2_psad_bw : GCCBuiltin<"__builtin_ia32_psadbw128">, - Intrinsic<[llvm_v2i64_ty, llvm_v16i8_ty, + Intrinsic<[llvm_v2i64_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem, Commutative]>; } // Integer shift ops. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_psll_w : GCCBuiltin<"__builtin_ia32_psllw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_x86_sse2_psll_d : GCCBuiltin<"__builtin_ia32_pslld128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_x86_sse2_psll_q : GCCBuiltin<"__builtin_ia32_psllq128">, - Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, + Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>; def int_x86_sse2_psrl_w : GCCBuiltin<"__builtin_ia32_psrlw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_x86_sse2_psrl_d : GCCBuiltin<"__builtin_ia32_psrld128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_x86_sse2_psrl_q : GCCBuiltin<"__builtin_ia32_psrlq128">, - Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, + Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>; def int_x86_sse2_psra_w : GCCBuiltin<"__builtin_ia32_psraw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_x86_sse2_psra_d : GCCBuiltin<"__builtin_ia32_psrad128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_x86_sse2_pslli_w : GCCBuiltin<"__builtin_ia32_psllwi128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse2_pslli_d : GCCBuiltin<"__builtin_ia32_pslldi128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse2_pslli_q : GCCBuiltin<"__builtin_ia32_psllqi128">, - Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, + Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse2_psrli_w : GCCBuiltin<"__builtin_ia32_psrlwi128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse2_psrli_d : GCCBuiltin<"__builtin_ia32_psrldi128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse2_psrli_q : GCCBuiltin<"__builtin_ia32_psrlqi128">, - Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, + Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse2_psrai_w : GCCBuiltin<"__builtin_ia32_psrawi128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse2_psrai_d : GCCBuiltin<"__builtin_ia32_psradi128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse2_psll_dq : GCCBuiltin<"__builtin_ia32_pslldqi128">, - Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, + Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse2_psrl_dq : GCCBuiltin<"__builtin_ia32_psrldqi128">, - Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, + Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse2_psll_dq_bs : GCCBuiltin<"__builtin_ia32_pslldqi128_byteshift">, - Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, + Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse2_psrl_dq_bs : GCCBuiltin<"__builtin_ia32_psrldqi128_byteshift">, - Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, + Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>; } // Integer comparison ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_pcmpeq_b : GCCBuiltin<"__builtin_ia32_pcmpeqb128">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_x86_sse2_pcmpeq_w : GCCBuiltin<"__builtin_ia32_pcmpeqw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_x86_sse2_pcmpeq_d : GCCBuiltin<"__builtin_ia32_pcmpeqd128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_x86_sse2_pcmpgt_b : GCCBuiltin<"__builtin_ia32_pcmpgtb128">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_x86_sse2_pcmpgt_w : GCCBuiltin<"__builtin_ia32_pcmpgtw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_x86_sse2_pcmpgt_d : GCCBuiltin<"__builtin_ia32_pcmpgtd128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; } // Conversion ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_cvtdq2pd : GCCBuiltin<"__builtin_ia32_cvtdq2pd">, - Intrinsic<[llvm_v2f64_ty, llvm_v4i32_ty], [IntrNoMem]>; + Intrinsic<[llvm_v2f64_ty], [llvm_v4i32_ty], [IntrNoMem]>; def int_x86_sse2_cvtdq2ps : GCCBuiltin<"__builtin_ia32_cvtdq2ps">, - Intrinsic<[llvm_v4f32_ty, llvm_v4i32_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4f32_ty], [llvm_v4i32_ty], [IntrNoMem]>; def int_x86_sse2_cvtpd2dq : GCCBuiltin<"__builtin_ia32_cvtpd2dq">, - Intrinsic<[llvm_v4i32_ty, llvm_v2f64_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_cvttpd2dq : GCCBuiltin<"__builtin_ia32_cvttpd2dq">, - Intrinsic<[llvm_v4i32_ty, llvm_v2f64_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_cvtpd2ps : GCCBuiltin<"__builtin_ia32_cvtpd2ps">, - Intrinsic<[llvm_v4f32_ty, llvm_v2f64_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4f32_ty], [llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_cvtps2dq : GCCBuiltin<"__builtin_ia32_cvtps2dq">, - Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse2_cvttps2dq : GCCBuiltin<"__builtin_ia32_cvttps2dq">, - Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse2_cvtps2pd : GCCBuiltin<"__builtin_ia32_cvtps2pd">, - Intrinsic<[llvm_v2f64_ty, llvm_v4f32_ty], [IntrNoMem]>; + Intrinsic<[llvm_v2f64_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse2_cvtsd2si : GCCBuiltin<"__builtin_ia32_cvtsd2si">, - Intrinsic<[llvm_i32_ty, llvm_v2f64_ty], [IntrNoMem]>; + Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_cvtsd2si64 : GCCBuiltin<"__builtin_ia32_cvtsd2si64">, - Intrinsic<[llvm_i64_ty, llvm_v2f64_ty], [IntrNoMem]>; + Intrinsic<[llvm_i64_ty], [llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_cvttsd2si : GCCBuiltin<"__builtin_ia32_cvttsd2si">, - Intrinsic<[llvm_i32_ty, llvm_v2f64_ty], [IntrNoMem]>; + Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_cvttsd2si64 : GCCBuiltin<"__builtin_ia32_cvttsd2si64">, - Intrinsic<[llvm_i64_ty, llvm_v2f64_ty], [IntrNoMem]>; + Intrinsic<[llvm_i64_ty], [llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_cvtsi2sd : GCCBuiltin<"__builtin_ia32_cvtsi2sd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse2_cvtsi642sd : GCCBuiltin<"__builtin_ia32_cvtsi642sd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_i64_ty], [IntrNoMem]>; def int_x86_sse2_cvtsd2ss : GCCBuiltin<"__builtin_ia32_cvtsd2ss">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_cvtss2sd : GCCBuiltin<"__builtin_ia32_cvtss2sd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_cvtpd2pi : GCCBuiltin<"__builtin_ia32_cvtpd2pi">, - Intrinsic<[llvm_v2i32_ty, llvm_v2f64_ty], [IntrNoMem]>; + Intrinsic<[llvm_v2i32_ty], [llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse_cvttpd2pi: GCCBuiltin<"__builtin_ia32_cvttpd2pi">, - Intrinsic<[llvm_v2i32_ty, llvm_v2f64_ty], [IntrNoMem]>; + Intrinsic<[llvm_v2i32_ty], [llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse_cvtpi2pd : GCCBuiltin<"__builtin_ia32_cvtpi2pd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2i32_ty], [IntrNoMem]>; + Intrinsic<[llvm_v2f64_ty], [llvm_v2i32_ty], [IntrNoMem]>; } // SIMD load ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_loadu_pd : GCCBuiltin<"__builtin_ia32_loadupd">, - Intrinsic<[llvm_v2f64_ty, llvm_ptr_ty], [IntrReadMem]>; + Intrinsic<[llvm_v2f64_ty], [llvm_ptr_ty], [IntrReadMem]>; def int_x86_sse2_loadu_dq : GCCBuiltin<"__builtin_ia32_loaddqu">, - Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [IntrReadMem]>; + Intrinsic<[llvm_v16i8_ty], [llvm_ptr_ty], [IntrReadMem]>; } // SIMD store ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_storeu_pd : GCCBuiltin<"__builtin_ia32_storeupd">, - Intrinsic<[llvm_void_ty, llvm_ptr_ty, + Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_v2f64_ty], [IntrWriteMem]>; def int_x86_sse2_storeu_dq : GCCBuiltin<"__builtin_ia32_storedqu">, - Intrinsic<[llvm_void_ty, llvm_ptr_ty, + Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_v16i8_ty], [IntrWriteMem]>; def int_x86_sse2_storel_dq : GCCBuiltin<"__builtin_ia32_storelv4si">, - Intrinsic<[llvm_void_ty, llvm_ptr_ty, + Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_v4i32_ty], [IntrWriteMem]>; } // Cacheability support ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_movnt_dq : GCCBuiltin<"__builtin_ia32_movntdq">, - Intrinsic<[llvm_void_ty, llvm_ptr_ty, + Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_v2i64_ty], [IntrWriteMem]>; def int_x86_sse2_movnt_pd : GCCBuiltin<"__builtin_ia32_movntpd">, - Intrinsic<[llvm_void_ty, llvm_ptr_ty, + Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_v2f64_ty], [IntrWriteMem]>; def int_x86_sse2_movnt_i : GCCBuiltin<"__builtin_ia32_movnti">, - Intrinsic<[llvm_void_ty, llvm_ptr_ty, + Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrWriteMem]>; } // Misc. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_x86_sse2_packssdw_128 : GCCBuiltin<"__builtin_ia32_packssdw128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_x86_sse2_packuswb_128 : GCCBuiltin<"__builtin_ia32_packuswb128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_x86_sse2_movmsk_pd : GCCBuiltin<"__builtin_ia32_movmskpd">, - Intrinsic<[llvm_i32_ty, llvm_v2f64_ty], [IntrNoMem]>; + Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_pmovmskb_128 : GCCBuiltin<"__builtin_ia32_pmovmskb128">, - Intrinsic<[llvm_i32_ty, llvm_v16i8_ty], [IntrNoMem]>; + Intrinsic<[llvm_i32_ty], [llvm_v16i8_ty], [IntrNoMem]>; def int_x86_sse2_maskmov_dqu : GCCBuiltin<"__builtin_ia32_maskmovdqu">, - Intrinsic<[llvm_void_ty, llvm_v16i8_ty, + Intrinsic<[llvm_void_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_ptr_ty], [IntrWriteMem]>; def int_x86_sse2_clflush : GCCBuiltin<"__builtin_ia32_clflush">, - Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>; + Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>; def int_x86_sse2_lfence : GCCBuiltin<"__builtin_ia32_lfence">, - Intrinsic<[llvm_void_ty], [IntrWriteMem]>; + Intrinsic<[llvm_void_ty], [], [IntrWriteMem]>; def int_x86_sse2_mfence : GCCBuiltin<"__builtin_ia32_mfence">, - Intrinsic<[llvm_void_ty], [IntrWriteMem]>; + Intrinsic<[llvm_void_ty], [], [IntrWriteMem]>; } //===----------------------------------------------------------------------===// @@ -513,42 +513,42 @@ // Addition / subtraction ops. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse3_addsub_ps : GCCBuiltin<"__builtin_ia32_addsubps">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse3_addsub_pd : GCCBuiltin<"__builtin_ia32_addsubpd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; } // Horizontal ops. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse3_hadd_ps : GCCBuiltin<"__builtin_ia32_haddps">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse3_hadd_pd : GCCBuiltin<"__builtin_ia32_haddpd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse3_hsub_ps : GCCBuiltin<"__builtin_ia32_hsubps">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse3_hsub_pd : GCCBuiltin<"__builtin_ia32_hsubpd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; } // Specialized unaligned load. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse3_ldu_dq : GCCBuiltin<"__builtin_ia32_lddqu">, - Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [IntrReadMem]>; + Intrinsic<[llvm_v16i8_ty], [llvm_ptr_ty], [IntrReadMem]>; } // Thread synchronization ops. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse3_monitor : GCCBuiltin<"__builtin_ia32_monitor">, - Intrinsic<[llvm_void_ty, llvm_ptr_ty, + Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [IntrWriteMem]>; def int_x86_sse3_mwait : GCCBuiltin<"__builtin_ia32_mwait">, - Intrinsic<[llvm_void_ty, llvm_i32_ty, + Intrinsic<[llvm_void_ty], [llvm_i32_ty, llvm_i32_ty], [IntrWriteMem]>; } @@ -558,124 +558,124 @@ // Horizontal arithmetic ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_ssse3_phadd_w : GCCBuiltin<"__builtin_ia32_phaddw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; def int_x86_ssse3_phadd_w_128 : GCCBuiltin<"__builtin_ia32_phaddw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_x86_ssse3_phadd_d : GCCBuiltin<"__builtin_ia32_phaddd">, - Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; def int_x86_ssse3_phadd_d_128 : GCCBuiltin<"__builtin_ia32_phaddd128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_x86_ssse3_phadd_sw : GCCBuiltin<"__builtin_ia32_phaddsw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; def int_x86_ssse3_phadd_sw_128 : GCCBuiltin<"__builtin_ia32_phaddsw128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_x86_ssse3_phsub_w : GCCBuiltin<"__builtin_ia32_phsubw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; def int_x86_ssse3_phsub_w_128 : GCCBuiltin<"__builtin_ia32_phsubw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_x86_ssse3_phsub_d : GCCBuiltin<"__builtin_ia32_phsubd">, - Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; def int_x86_ssse3_phsub_d_128 : GCCBuiltin<"__builtin_ia32_phsubd128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_x86_ssse3_phsub_sw : GCCBuiltin<"__builtin_ia32_phsubsw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; def int_x86_ssse3_phsub_sw_128 : GCCBuiltin<"__builtin_ia32_phsubsw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_x86_ssse3_pmadd_ub_sw : GCCBuiltin<"__builtin_ia32_pmaddubsw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; def int_x86_ssse3_pmadd_ub_sw_128 : GCCBuiltin<"__builtin_ia32_pmaddubsw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; } // Packed multiply high with round and scale let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_ssse3_pmul_hr_sw : GCCBuiltin<"__builtin_ia32_pmulhrsw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem, Commutative]>; def int_x86_ssse3_pmul_hr_sw_128 : GCCBuiltin<"__builtin_ia32_pmulhrsw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem, Commutative]>; } // Shuffle ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_ssse3_pshuf_b : GCCBuiltin<"__builtin_ia32_pshufb">, - Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty, + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; def int_x86_ssse3_pshuf_b_128 : GCCBuiltin<"__builtin_ia32_pshufb128">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; } // Sign ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_ssse3_psign_b : GCCBuiltin<"__builtin_ia32_psignb">, - Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty, + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; def int_x86_ssse3_psign_b_128 : GCCBuiltin<"__builtin_ia32_psignb128">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_x86_ssse3_psign_w : GCCBuiltin<"__builtin_ia32_psignw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; def int_x86_ssse3_psign_w_128 : GCCBuiltin<"__builtin_ia32_psignw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_x86_ssse3_psign_d : GCCBuiltin<"__builtin_ia32_psignd">, - Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; def int_x86_ssse3_psign_d_128 : GCCBuiltin<"__builtin_ia32_psignd128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; } // Absolute value ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_ssse3_pabs_b : GCCBuiltin<"__builtin_ia32_pabsb">, - Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty], [IntrNoMem]>; def int_x86_ssse3_pabs_b_128 : GCCBuiltin<"__builtin_ia32_pabsb128">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>; def int_x86_ssse3_pabs_w : GCCBuiltin<"__builtin_ia32_pabsw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty], [IntrNoMem]>; def int_x86_ssse3_pabs_w_128 : GCCBuiltin<"__builtin_ia32_pabsw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty], [IntrNoMem]>; def int_x86_ssse3_pabs_d : GCCBuiltin<"__builtin_ia32_pabsd">, - Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty], [IntrNoMem]>; def int_x86_ssse3_pabs_d_128 : GCCBuiltin<"__builtin_ia32_pabsd128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty], [IntrNoMem]>; } // Align ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_ssse3_palign_r : GCCBuiltin<"__builtin_ia32_palignr">, - Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_i16_ty], [IntrNoMem]>; def int_x86_ssse3_palign_r_128 : GCCBuiltin<"__builtin_ia32_palignr128">, - Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, + Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>; } @@ -685,186 +685,186 @@ // FP rounding ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse41_round_ss : GCCBuiltin<"__builtin_ia32_roundss">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse41_round_ps : GCCBuiltin<"__builtin_ia32_roundps">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse41_round_sd : GCCBuiltin<"__builtin_ia32_roundsd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse41_round_pd : GCCBuiltin<"__builtin_ia32_roundpd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_i32_ty], [IntrNoMem]>; } // Vector sign and zero extend let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse41_pmovsxbd : GCCBuiltin<"__builtin_ia32_pmovsxbd128">, - Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty], [IntrNoMem]>; def int_x86_sse41_pmovsxbq : GCCBuiltin<"__builtin_ia32_pmovsxbq128">, - Intrinsic<[llvm_v2i64_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v2i64_ty], [llvm_v16i8_ty], [IntrNoMem]>; def int_x86_sse41_pmovsxbw : GCCBuiltin<"__builtin_ia32_pmovsxbw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty], [IntrNoMem]>; def int_x86_sse41_pmovsxdq : GCCBuiltin<"__builtin_ia32_pmovsxdq128">, - Intrinsic<[llvm_v2i64_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem]>; def int_x86_sse41_pmovsxwd : GCCBuiltin<"__builtin_ia32_pmovsxwd128">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty], [IntrNoMem]>; def int_x86_sse41_pmovsxwq : GCCBuiltin<"__builtin_ia32_pmovsxwq128">, - Intrinsic<[llvm_v2i64_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v2i64_ty], [llvm_v8i16_ty], [IntrNoMem]>; def int_x86_sse41_pmovzxbd : GCCBuiltin<"__builtin_ia32_pmovzxbd128">, - Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty], [IntrNoMem]>; def int_x86_sse41_pmovzxbq : GCCBuiltin<"__builtin_ia32_pmovzxbq128">, - Intrinsic<[llvm_v2i64_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v2i64_ty], [llvm_v16i8_ty], [IntrNoMem]>; def int_x86_sse41_pmovzxbw : GCCBuiltin<"__builtin_ia32_pmovzxbw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty], [IntrNoMem]>; def int_x86_sse41_pmovzxdq : GCCBuiltin<"__builtin_ia32_pmovzxdq128">, - Intrinsic<[llvm_v2i64_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem]>; def int_x86_sse41_pmovzxwd : GCCBuiltin<"__builtin_ia32_pmovzxwd128">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty], [IntrNoMem]>; def int_x86_sse41_pmovzxwq : GCCBuiltin<"__builtin_ia32_pmovzxwq128">, - Intrinsic<[llvm_v2i64_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v2i64_ty], [llvm_v8i16_ty], [IntrNoMem]>; } // Vector min element let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse41_phminposuw : GCCBuiltin<"__builtin_ia32_phminposuw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty], [IntrNoMem]>; } // Vector compare, min, max let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse41_pcmpeqq : GCCBuiltin<"__builtin_ia32_pcmpeqq">, - Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty], + Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem, Commutative]>; def int_x86_sse42_pcmpgtq : GCCBuiltin<"__builtin_ia32_pcmpgtq">, - Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty], + Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>; def int_x86_sse41_pmaxsb : GCCBuiltin<"__builtin_ia32_pmaxsb128">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem, Commutative]>; def int_x86_sse41_pmaxsd : GCCBuiltin<"__builtin_ia32_pmaxsd128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem, Commutative]>; def int_x86_sse41_pmaxud : GCCBuiltin<"__builtin_ia32_pmaxud128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem, Commutative]>; def int_x86_sse41_pmaxuw : GCCBuiltin<"__builtin_ia32_pmaxuw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem, Commutative]>; def int_x86_sse41_pminsb : GCCBuiltin<"__builtin_ia32_pminsb128">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem, Commutative]>; def int_x86_sse41_pminsd : GCCBuiltin<"__builtin_ia32_pminsd128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem, Commutative]>; def int_x86_sse41_pminud : GCCBuiltin<"__builtin_ia32_pminud128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem, Commutative]>; def int_x86_sse41_pminuw : GCCBuiltin<"__builtin_ia32_pminuw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem, Commutative]>; } // Vector pack let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse41_packusdw : GCCBuiltin<"__builtin_ia32_packusdw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; } // Vector multiply let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse41_pmuldq : GCCBuiltin<"__builtin_ia32_pmuldq128">, - Intrinsic<[llvm_v2i64_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem, Commutative]>; def int_x86_sse41_pmulld : GCCBuiltin<"__builtin_ia32_pmulld128">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem, Commutative]>; } // Vector extract let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse41_pextrb : - Intrinsic<[llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty], + Intrinsic<[llvm_i32_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse41_pextrd : - Intrinsic<[llvm_i32_ty, llvm_v4i32_ty, llvm_i32_ty], + Intrinsic<[llvm_i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse41_pextrq : - Intrinsic<[llvm_i64_ty, llvm_v2i64_ty, llvm_i32_ty], + Intrinsic<[llvm_i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse41_extractps : GCCBuiltin<"__builtin_ia32_extractps128">, - Intrinsic<[llvm_i32_ty, llvm_v4f32_ty, llvm_i32_ty], + Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>; } // Vector insert let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse41_pinsrb : GCCBuiltin<"__builtin_ia32_vec_set_v16qi">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty], + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse41_insertps : GCCBuiltin<"__builtin_ia32_insertps128">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty], + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty,llvm_i32_ty], [IntrNoMem]>; } // Vector blend let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse41_pblendvb : GCCBuiltin<"__builtin_ia32_pblendvb128">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty,llvm_v16i8_ty], [IntrNoMem]>; def int_x86_sse41_pblendw : GCCBuiltin<"__builtin_ia32_pblendw128">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty], + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse41_blendpd : GCCBuiltin<"__builtin_ia32_blendpd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty], + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse41_blendps : GCCBuiltin<"__builtin_ia32_blendps">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty], + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_sse41_blendvpd : GCCBuiltin<"__builtin_ia32_blendvpd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty,llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse41_blendvps : GCCBuiltin<"__builtin_ia32_blendvps">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty,llvm_v4f32_ty], [IntrNoMem]>; } // Vector dot product let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse41_dppd : GCCBuiltin<"__builtin_ia32_dppd">, - Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty], + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty,llvm_i32_ty], [IntrNoMem, Commutative]>; def int_x86_sse41_dpps : GCCBuiltin<"__builtin_ia32_dpps">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty], + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty,llvm_i32_ty], [IntrNoMem, Commutative]>; } // Vector sum of absolute differences let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse41_mpsadbw : GCCBuiltin<"__builtin_ia32_mpsadbw128">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty], + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty,llvm_i32_ty], [IntrNoMem, Commutative]>; } // Cacheability support ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse41_movntdqa : GCCBuiltin<"__builtin_ia32_movntdqa">, - Intrinsic<[llvm_v2i64_ty, llvm_ptr_ty], [IntrReadMem]>; + Intrinsic<[llvm_v2i64_ty], [llvm_ptr_ty], [IntrReadMem]>; } @@ -874,84 +874,84 @@ // Empty MMX state op. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_mmx_emms : GCCBuiltin<"__builtin_ia32_emms">, - Intrinsic<[llvm_void_ty], [IntrWriteMem]>; + Intrinsic<[llvm_void_ty], [], [IntrWriteMem]>; def int_x86_mmx_femms : GCCBuiltin<"__builtin_ia32_femms">, - Intrinsic<[llvm_void_ty], [IntrWriteMem]>; + Intrinsic<[llvm_void_ty], [], [IntrWriteMem]>; } // Integer arithmetic ops. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". // Addition def int_x86_mmx_padds_b : GCCBuiltin<"__builtin_ia32_paddsb">, - Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty, + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem, Commutative]>; def int_x86_mmx_padds_w : GCCBuiltin<"__builtin_ia32_paddsw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem, Commutative]>; def int_x86_mmx_paddus_b : GCCBuiltin<"__builtin_ia32_paddusb">, - Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty, + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem, Commutative]>; def int_x86_mmx_paddus_w : GCCBuiltin<"__builtin_ia32_paddusw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem, Commutative]>; // Subtraction def int_x86_mmx_psubs_b : GCCBuiltin<"__builtin_ia32_psubsb">, - Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty, + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; def int_x86_mmx_psubs_w : GCCBuiltin<"__builtin_ia32_psubsw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; def int_x86_mmx_psubus_b : GCCBuiltin<"__builtin_ia32_psubusb">, - Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty, + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; def int_x86_mmx_psubus_w : GCCBuiltin<"__builtin_ia32_psubusw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; // Multiplication def int_x86_mmx_pmulh_w : GCCBuiltin<"__builtin_ia32_pmulhw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem, Commutative]>; def int_x86_mmx_pmulhu_w : GCCBuiltin<"__builtin_ia32_pmulhuw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem, Commutative]>; def int_x86_mmx_pmulu_dq : GCCBuiltin<"__builtin_ia32_pmuludq">, - Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem, Commutative]>; def int_x86_mmx_pmadd_wd : GCCBuiltin<"__builtin_ia32_pmaddwd">, - Intrinsic<[llvm_v2i32_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem, Commutative]>; // Averages def int_x86_mmx_pavg_b : GCCBuiltin<"__builtin_ia32_pavgb">, - Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty, + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem, Commutative]>; def int_x86_mmx_pavg_w : GCCBuiltin<"__builtin_ia32_pavgw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem, Commutative]>; // Maximum def int_x86_mmx_pmaxu_b : GCCBuiltin<"__builtin_ia32_pmaxub">, - Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty, + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem, Commutative]>; def int_x86_mmx_pmaxs_w : GCCBuiltin<"__builtin_ia32_pmaxsw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem, Commutative]>; // Minimum def int_x86_mmx_pminu_b : GCCBuiltin<"__builtin_ia32_pminub">, - Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty, + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem, Commutative]>; def int_x86_mmx_pmins_w : GCCBuiltin<"__builtin_ia32_pminsw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem, Commutative]>; // Packed sum of absolute differences def int_x86_mmx_psad_bw : GCCBuiltin<"__builtin_ia32_psadbw">, - Intrinsic<[llvm_v4i16_ty, llvm_v8i8_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem, Commutative]>; } @@ -959,106 +959,107 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". // Shift left logical def int_x86_mmx_psll_w : GCCBuiltin<"__builtin_ia32_psllw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v1i64_ty], [IntrNoMem]>; def int_x86_mmx_psll_d : GCCBuiltin<"__builtin_ia32_pslld">, - Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v1i64_ty], [IntrNoMem]>; def int_x86_mmx_psll_q : GCCBuiltin<"__builtin_ia32_psllq">, - Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; def int_x86_mmx_psrl_w : GCCBuiltin<"__builtin_ia32_psrlw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v1i64_ty], [IntrNoMem]>; def int_x86_mmx_psrl_d : GCCBuiltin<"__builtin_ia32_psrld">, - Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v1i64_ty], [IntrNoMem]>; def int_x86_mmx_psrl_q : GCCBuiltin<"__builtin_ia32_psrlq">, - Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; def int_x86_mmx_psra_w : GCCBuiltin<"__builtin_ia32_psraw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v1i64_ty], [IntrNoMem]>; def int_x86_mmx_psra_d : GCCBuiltin<"__builtin_ia32_psrad">, - Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v1i64_ty], [IntrNoMem]>; def int_x86_mmx_pslli_w : GCCBuiltin<"__builtin_ia32_psllwi">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_pslli_d : GCCBuiltin<"__builtin_ia32_pslldi">, - Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_pslli_q : GCCBuiltin<"__builtin_ia32_psllqi">, - Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psrli_w : GCCBuiltin<"__builtin_ia32_psrlwi">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psrli_d : GCCBuiltin<"__builtin_ia32_psrldi">, - Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psrli_q : GCCBuiltin<"__builtin_ia32_psrlqi">, - Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psrai_w : GCCBuiltin<"__builtin_ia32_psrawi">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psrai_d : GCCBuiltin<"__builtin_ia32_psradi">, - Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_i32_ty], [IntrNoMem]>; } // Pack ops. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_mmx_packsswb : GCCBuiltin<"__builtin_ia32_packsswb">, - Intrinsic<[llvm_v8i8_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v8i8_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; def int_x86_mmx_packssdw : GCCBuiltin<"__builtin_ia32_packssdw">, - Intrinsic<[llvm_v4i16_ty, llvm_v2i32_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; def int_x86_mmx_packuswb : GCCBuiltin<"__builtin_ia32_packuswb">, - Intrinsic<[llvm_v8i8_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v8i8_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; } // Integer comparison ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_mmx_pcmpeq_b : GCCBuiltin<"__builtin_ia32_pcmpeqb">, - Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty, + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; def int_x86_mmx_pcmpeq_w : GCCBuiltin<"__builtin_ia32_pcmpeqw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; def int_x86_mmx_pcmpeq_d : GCCBuiltin<"__builtin_ia32_pcmpeqd">, - Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; def int_x86_mmx_pcmpgt_b : GCCBuiltin<"__builtin_ia32_pcmpgtb">, - Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty, + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; def int_x86_mmx_pcmpgt_w : GCCBuiltin<"__builtin_ia32_pcmpgtw">, - Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; def int_x86_mmx_pcmpgt_d : GCCBuiltin<"__builtin_ia32_pcmpgtd">, - Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>; } // Misc. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_mmx_maskmovq : GCCBuiltin<"__builtin_ia32_maskmovq">, - Intrinsic<[llvm_void_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_ptr_ty], + Intrinsic<[llvm_void_ty], + [llvm_v8i8_ty, llvm_v8i8_ty, llvm_ptr_ty], [IntrWriteMem]>; def int_x86_mmx_pmovmskb : GCCBuiltin<"__builtin_ia32_pmovmskb">, - Intrinsic<[llvm_i32_ty, llvm_v8i8_ty], [IntrNoMem]>; + Intrinsic<[llvm_i32_ty], [llvm_v8i8_ty], [IntrNoMem]>; def int_x86_mmx_movnt_dq : GCCBuiltin<"__builtin_ia32_movntq">, - Intrinsic<[llvm_void_ty, llvm_ptr_ty, + Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_v1i64_ty], [IntrWriteMem]>; } Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=59237&r1=59236&r2=59237&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Thu Nov 13 03:08:33 2008 @@ -269,7 +269,7 @@ bool PerformTypeCheck(Intrinsic::ID ID, Function *F, const Type *Ty, int VT, unsigned ArgNo, std::string &Suffix); void VerifyIntrinsicPrototype(Intrinsic::ID ID, Function *F, - unsigned Count, ...); + unsigned RetNum, unsigned ParamNum, ...); void VerifyAttrs(Attributes Attrs, const Type *Ty, bool isReturnValue, const Value *V); void VerifyFunctionAttrs(const FunctionType *FT, const AttrListPtr &Attrs, @@ -1507,11 +1507,11 @@ /// VerifyIntrinsicPrototype - TableGen emits calls to this function into /// Intrinsics.gen. This implements a little state machine that verifies the /// prototype of intrinsics. -void Verifier::VerifyIntrinsicPrototype(Intrinsic::ID ID, - Function *F, - unsigned Count, ...) { +void Verifier::VerifyIntrinsicPrototype(Intrinsic::ID ID, Function *F, + unsigned RetNum, + unsigned ParamNum, ...) { va_list VA; - va_start(VA, Count); + va_start(VA, ParamNum); const FunctionType *FTy = F->getFunctionType(); // For overloaded intrinsics, the Suffix of the function name must match the @@ -1519,13 +1519,31 @@ // suffix, to be checked at the end. std::string Suffix; - if (FTy->getNumParams() + FTy->isVarArg() != Count - 1) { + if (FTy->getNumParams() + FTy->isVarArg() != ParamNum) { CheckFailed("Intrinsic prototype has incorrect number of arguments!", F); return; } - // Note that "arg#0" is the return type. - for (unsigned ArgNo = 0; ArgNo < Count; ++ArgNo) { + const Type *Ty = FTy->getReturnType(); + const StructType *ST = dyn_cast(Ty); + + // Verify the return types. + if (ST && ST->getNumElements() != RetNum) { + CheckFailed("Intrinsic prototype has incorrect number of return types!", F); + return; + } + + for (unsigned ArgNo = 0; ArgNo < RetNum; ++ArgNo) { + int VT = va_arg(VA, int); // An MVT::SimpleValueType when non-negative. + + if (ST) Ty = ST->getElementType(ArgNo); + + if (!PerformTypeCheck(ID, F, Ty, VT, ArgNo, Suffix)) + break; + } + + // Verify the parameter types. + for (unsigned ArgNo = 0; ArgNo < ParamNum; ++ArgNo) { int VT = va_arg(VA, int); // An MVT::SimpleValueType when non-negative. if (VT == MVT::isVoid && ArgNo > 0) { @@ -1534,10 +1552,7 @@ break; } - const Type *Ty = (ArgNo == 0) ? - FTy->getReturnType() : FTy->getParamType(ArgNo - 1); - - if (!PerformTypeCheck(ID, F, Ty, VT, ArgNo, Suffix)) + if (!PerformTypeCheck(ID, F, FTy->getParamType(ArgNo), VT, ArgNo, Suffix)) break; } Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=59237&r1=59236&r2=59237&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Thu Nov 13 03:08:33 2008 @@ -471,7 +471,8 @@ } if (getExtTypeNum(0) == MVT::iPTR || getExtTypeNum(0) == MVT::iPTRAny) { - if (ExtVTs[0] == MVT::iPTR || ExtVTs[0] == MVT::iPTRAny || ExtVTs[0] == EMVT::isInt) + if (ExtVTs[0] == MVT::iPTR || ExtVTs[0] == MVT::iPTRAny || + ExtVTs[0] == EMVT::isInt) return false; if (EMVT::isExtIntegerInVTs(ExtVTs)) { std::vector FVTs = FilterEVTs(ExtVTs, isInteger); @@ -885,18 +886,22 @@ bool MadeChange = false; // Apply the result type to the node. - MadeChange = UpdateNodeType(Int->ArgVTs[0], TP); + unsigned NumRetVTs = Int->IS.RetVTs.size(); + unsigned NumParamVTs = Int->IS.ParamVTs.size(); - if (getNumChildren() != Int->ArgVTs.size()) + for (unsigned i = 0, e = NumRetVTs; i != e; ++i) + MadeChange |= UpdateNodeType(Int->IS.RetVTs[i], TP); + + if (getNumChildren() != NumParamVTs + NumRetVTs) TP.error("Intrinsic '" + Int->Name + "' expects " + - utostr(Int->ArgVTs.size()-1) + " operands, not " + - utostr(getNumChildren()-1) + " operands!"); + utostr(NumParamVTs + NumRetVTs - 1) + " operands, not " + + utostr(getNumChildren() - 1) + " operands!"); // Apply type info to the intrinsic ID. MadeChange |= getChild(0)->UpdateNodeType(MVT::iPTR, TP); - for (unsigned i = 1, e = getNumChildren(); i != e; ++i) { - MVT::SimpleValueType OpVT = Int->ArgVTs[i]; + for (unsigned i = NumRetVTs, e = getNumChildren(); i != e; ++i) { + MVT::SimpleValueType OpVT = Int->IS.ParamVTs[i - NumRetVTs]; MadeChange |= getChild(i)->UpdateNodeType(OpVT, TP); MadeChange |= getChild(i)->ApplyTypeConstraints(TP, NotRegisters); } @@ -1232,7 +1237,7 @@ // If this intrinsic returns void, it must have side-effects and thus a // chain. - if (Int.ArgVTs[0] == MVT::isVoid) { + if (Int.IS.RetVTs[0] == MVT::isVoid) { Operator = getDAGPatterns().get_intrinsic_void_sdnode(); } else if (Int.ModRef != CodeGenIntrinsic::NoMem) { // Has side-effects, requires chain. Modified: llvm/trunk/utils/TableGen/CodeGenIntrinsics.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenIntrinsics.h?rev=59237&r1=59236&r2=59237&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenIntrinsics.h (original) +++ llvm/trunk/utils/TableGen/CodeGenIntrinsics.h Thu Nov 13 03:08:33 2008 @@ -30,16 +30,34 @@ std::string GCCBuiltinName;// Name of the corresponding GCC builtin, or "". std::string TargetPrefix; // Target prefix, e.g. "ppc" for t-s intrinsics. - /// ArgVTs - The MVT::SimpleValueType for each argument type. Note that - /// this list is only populated when in the context of a target .td file. - /// When building Intrinsics.td, this isn't available, because we don't know - /// the target pointer size. - std::vector ArgVTs; - - /// ArgTypeDefs - The records for each argument type. - /// - std::vector ArgTypeDefs; - + /// IntrinsicSignature - This structure holds the return values and + /// parameter values of an intrinsic. If the number of return values is > 1, + /// then the intrinsic implicitly returns a first-class aggregate. The + /// numbering of the types starts at 0 with the first return value and + /// continues from there throug the parameter list. This is useful for + /// "matching" types. + struct IntrinsicSignature { + /// RetVTs - The MVT::SimpleValueType for each return type. Note that this + /// list is only populated when in the context of a target .td file. When + /// building Intrinsics.td, this isn't available, because we don't know + /// the target pointer size. + std::vector RetVTs; + + /// RetTypeDefs - The records for each return type. + std::vector RetTypeDefs; + + /// ParamVTs - The MVT::SimpleValueType for each parameter type. Note that + /// this list is only populated when in the context of a target .td file. + /// When building Intrinsics.td, this isn't available, because we don't + /// know the target pointer size. + std::vector ParamVTs; + + /// ParamTypeDefs - The records for each parameter type. + std::vector ParamTypeDefs; + }; + + IntrinsicSignature IS; + // Memory mod/ref behavior of this intrinsic. enum { NoMem, ReadArgMem, ReadMem, WriteArgMem, WriteMem Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=59237&r1=59236&r2=59237&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Thu Nov 13 03:08:33 2008 @@ -438,25 +438,27 @@ isCommutative = false; if (DefName.size() <= 4 || - std::string(DefName.begin(), DefName.begin()+4) != "int_") + std::string(DefName.begin(), DefName.begin() + 4) != "int_") throw "Intrinsic '" + DefName + "' does not start with 'int_'!"; + EnumName = std::string(DefName.begin()+4, DefName.end()); + if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field. GCCBuiltinName = R->getValueAsString("GCCBuiltinName"); - TargetPrefix = R->getValueAsString("TargetPrefix"); + + TargetPrefix = R->getValueAsString("TargetPrefix"); Name = R->getValueAsString("LLVMName"); + if (Name == "") { // If an explicit name isn't specified, derive one from the DefName. Name = "llvm."; + for (unsigned i = 0, e = EnumName.size(); i != e; ++i) - if (EnumName[i] == '_') - Name += '.'; - else - Name += EnumName[i]; + Name += (EnumName[i] == '_') ? '.' : EnumName[i]; } else { // Verify it starts with "llvm.". if (Name.size() <= 5 || - std::string(Name.begin(), Name.begin()+5) != "llvm.") + std::string(Name.begin(), Name.begin() + 5) != "llvm.") throw "Intrinsic '" + DefName + "'s name does not start with 'llvm.'!"; } @@ -464,26 +466,37 @@ // "llvm..". if (!TargetPrefix.empty()) { if (Name.size() < 6+TargetPrefix.size() || - std::string(Name.begin()+5, Name.begin()+6+TargetPrefix.size()) - != (TargetPrefix+".")) - throw "Intrinsic '" + DefName + "' does not start with 'llvm." + + std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size()) + != (TargetPrefix + ".")) + throw "Intrinsic '" + DefName + "' does not start with 'llvm." + TargetPrefix + ".'!"; } - // Parse the list of argument types. - ListInit *TypeList = R->getValueAsListInit("Types"); + // Parse the list of return types. + ListInit *TypeList = R->getValueAsListInit("RetTypes"); for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) { Record *TyEl = TypeList->getElementAsRecord(i); assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT")); isOverloaded |= VT == MVT::iAny || VT == MVT::fAny || VT == MVT::iPTRAny; - ArgVTs.push_back(VT); - ArgTypeDefs.push_back(TyEl); + IS.RetVTs.push_back(VT); + IS.RetTypeDefs.push_back(TyEl); } - if (ArgVTs.size() == 0) + + if (IS.RetVTs.size() == 0) throw "Intrinsic '"+DefName+"' needs at least a type for the ret value!"; - + // Parse the list of parameter types. + TypeList = R->getValueAsListInit("ParamTypes"); + for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) { + Record *TyEl = TypeList->getElementAsRecord(i); + assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); + MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT")); + isOverloaded |= VT == MVT::iAny || VT == MVT::fAny || VT == MVT::iPTRAny; + IS.ParamVTs.push_back(VT); + IS.ParamTypeDefs.push_back(TyEl); + } + // Parse the intrinsic properties. ListInit *PropList = R->getValueAsListInit("Properties"); for (unsigned i = 0, e = PropList->getSize(); i != e; ++i) { Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=59237&r1=59236&r2=59237&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Thu Nov 13 03:08:33 2008 @@ -138,7 +138,27 @@ } } -static void EmitTypeGenerate(std::ostream &OS, Record *ArgType, +static void EmitTypeGenerate(std::ostream &OS, const Record *ArgType, + unsigned &ArgNo); + +static void EmitTypeGenerate(std::ostream &OS, + const std::vector &ArgTypes, + unsigned &ArgNo) { + if (ArgTypes.size() == 1) { + EmitTypeGenerate(OS, ArgTypes.front(), ArgNo); + return; + } + + OS << "StructType::get("; + + for (std::vector::const_iterator + I = ArgTypes.begin(), E = ArgTypes.end(); I != E; ++I) + EmitTypeGenerate(OS, *I, ArgNo); + + OS << ", NULL)"; +} + +static void EmitTypeGenerate(std::ostream &OS, const Record *ArgType, unsigned &ArgNo) { MVT::SimpleValueType VT = getValueType(ArgType->getValueAsDef("VT")); @@ -184,17 +204,37 @@ /// RecordListComparator - Provide a determinstic comparator for lists of /// records. namespace { + typedef std::pair, std::vector > RecPair; struct RecordListComparator { - bool operator()(const std::vector &LHS, - const std::vector &RHS) const { + bool operator()(const RecPair &LHS, + const RecPair &RHS) const { unsigned i = 0; + const std::vector *LHSVec = &LHS.first; + const std::vector *RHSVec = &RHS.first; + unsigned RHSSize = RHSVec->size(); + unsigned LHSSize = LHSVec->size(); + do { - if (i == RHS.size()) return false; // RHS is shorter than LHS. - if (LHS[i] != RHS[i]) - return LHS[i]->getName() < RHS[i]->getName(); - } while (++i != LHS.size()); - - return i != RHS.size(); + if (i == RHSSize) return false; // RHS is shorter than LHS. + if ((*LHSVec)[i] != (*RHSVec)[i]) + return (*LHSVec)[i]->getName() < (*RHSVec)[i]->getName(); + } while (++i != LHSSize); + + if (i != RHSSize) return false; + + i = 0; + LHSVec = &LHS.second; + RHSVec = &RHS.second; + RHSSize = RHSVec->size(); + LHSSize = LHSVec->size(); + + for (i = 0; i != LHSSize; ++i) { + if (i == RHSSize) return false; // RHS is shorter than LHS. + if ((*LHSVec)[i] != (*RHSVec)[i]) + return (*LHSVec)[i]->getName() < (*RHSVec)[i]->getName(); + } + + return i != RHSSize; } }; } @@ -209,26 +249,33 @@ // This checking can emit a lot of very common code. To reduce the amount of // code that we emit, batch up cases that have identical types. This avoids // problems where GCC can run out of memory compiling Verifier.cpp. - typedef std::map, std::vector, - RecordListComparator> MapTy; + typedef std::map, RecordListComparator> MapTy; MapTy UniqueArgInfos; // Compute the unique argument type info. for (unsigned i = 0, e = Ints.size(); i != e; ++i) - UniqueArgInfos[Ints[i].ArgTypeDefs].push_back(i); + UniqueArgInfos[make_pair(Ints[i].IS.RetTypeDefs, + Ints[i].IS.ParamTypeDefs)].push_back(i); // Loop through the array, emitting one comparison for each batch. for (MapTy::iterator I = UniqueArgInfos.begin(), E = UniqueArgInfos.end(); I != E; ++I) { - for (unsigned i = 0, e = I->second.size(); i != e; ++i) { + for (unsigned i = 0, e = I->second.size(); i != e; ++i) OS << " case Intrinsic::" << Ints[I->second[i]].EnumName << ":\t\t// " << Ints[I->second[i]].Name << "\n"; - } - const std::vector &ArgTypes = I->first; - OS << " VerifyIntrinsicPrototype(ID, IF, " << ArgTypes.size() << ", "; - for (unsigned j = 0; j != ArgTypes.size(); ++j) { - Record *ArgType = ArgTypes[j]; + const RecPair &ArgTypes = I->first; + const std::vector &RetTys = ArgTypes.first; + const std::vector &ParamTys = ArgTypes.second; + + OS << " VerifyIntrinsicPrototype(ID, IF, " << RetTys.size() << ", " + << ParamTys.size(); + + // Emit return types. + for (unsigned j = 0, je = RetTys.size(); j != je; ++j) { + Record *ArgType = RetTys[j]; + OS << ", "; + if (ArgType->isSubClassOf("LLVMMatchType")) { unsigned Number = ArgType->getValueAsInt("Number"); assert(Number < j && "Invalid matching number!"); @@ -236,11 +283,28 @@ } else { MVT::SimpleValueType VT = getValueType(ArgType->getValueAsDef("VT")); OS << getEnumName(VT); - if (VT == MVT::isVoid && j != 0 && j != ArgTypes.size()-1) + + if (VT == MVT::isVoid && j != 0 && j != je - 1) + throw "Var arg type not last argument"; + } + } + + // Emit the parameter types. + for (unsigned j = 0, je = ParamTys.size(); j != je; ++j) { + Record *ArgType = ParamTys[j]; + OS << ", "; + + if (ArgType->isSubClassOf("LLVMMatchType")) { + unsigned Number = ArgType->getValueAsInt("Number"); + assert(Number < j + RetTys.size() && "Invalid matching number!"); + OS << "~" << Number; + } else { + MVT::SimpleValueType VT = getValueType(ArgType->getValueAsDef("VT")); + OS << getEnumName(VT); + + if (VT == MVT::isVoid && j != 0 && j != je - 1) throw "Var arg type not last argument"; } - if (j != ArgTypes.size()-1) - OS << ", "; } OS << ");\n"; @@ -259,43 +323,47 @@ // Similar to GET_INTRINSIC_VERIFIER, batch up cases that have identical // types. - typedef std::map, std::vector, - RecordListComparator> MapTy; + typedef std::map, RecordListComparator> MapTy; MapTy UniqueArgInfos; // Compute the unique argument type info. for (unsigned i = 0, e = Ints.size(); i != e; ++i) - UniqueArgInfos[Ints[i].ArgTypeDefs].push_back(i); + UniqueArgInfos[make_pair(Ints[i].IS.RetTypeDefs, + Ints[i].IS.ParamTypeDefs)].push_back(i); // Loop through the array, emitting one generator for each batch. for (MapTy::iterator I = UniqueArgInfos.begin(), E = UniqueArgInfos.end(); I != E; ++I) { - for (unsigned i = 0, e = I->second.size(); i != e; ++i) { + for (unsigned i = 0, e = I->second.size(); i != e; ++i) OS << " case Intrinsic::" << Ints[I->second[i]].EnumName << ":\t\t// " << Ints[I->second[i]].Name << "\n"; - } - const std::vector &ArgTypes = I->first; - unsigned N = ArgTypes.size(); + const RecPair &ArgTypes = I->first; + const std::vector &RetTys = ArgTypes.first; + const std::vector &ParamTys = ArgTypes.second; + + unsigned N = ParamTys.size(); if (N > 1 && - getValueType(ArgTypes[N-1]->getValueAsDef("VT")) == MVT::isVoid) { + getValueType(ParamTys[N - 1]->getValueAsDef("VT")) == MVT::isVoid) { OS << " IsVarArg = true;\n"; --N; } - + unsigned ArgNo = 0; OS << " ResultTy = "; - EmitTypeGenerate(OS, ArgTypes[0], ArgNo); + EmitTypeGenerate(OS, RetTys, ArgNo); OS << ";\n"; - for (unsigned j = 1; j != N; ++j) { + for (unsigned j = 0; j != N; ++j) { OS << " ArgTys.push_back("; - EmitTypeGenerate(OS, ArgTypes[j], ArgNo); + EmitTypeGenerate(OS, ParamTys[j], ArgNo); OS << ");\n"; } + OS << " break;\n"; } + OS << " }\n"; OS << "#endif\n\n"; } From duncan.sands at math.u-psud.fr Thu Nov 13 03:16:30 2008 From: duncan.sands at math.u-psud.fr (Duncan Sands) Date: Thu, 13 Nov 2008 10:16:30 +0100 Subject: [llvm-commits] [llvm] r58964 - in /llvm/trunk: docs/LangRef.html lib/Bitcode/Reader/BitcodeReader.cpp lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp lib/Transforms/Scalar/InstructionCombining.cpp lib/VMCore/ConstantFold.cpp lib/VMCore/Instructions.cpp lib/VMCore/Verifier.cpp In-Reply-To: <5709F358-C4B9-45B0-AC88-0590CD4553FF@apple.com> References: <200811100446.mAA4kN1Y027799@zion.cs.uiuc.edu> <200811121805.33109.duncan.sands@math.u-psud.fr> <5709F358-C4B9-45B0-AC88-0590CD4553FF@apple.com> Message-ID: <200811131016.30368.duncan.sands@math.u-psud.fr> Hi Mon Ping, > I like this implementation in general and you capture a case that I > missed (in avoid using build vector) :-> . In my thinking (which is > why I went more for a prescan methodology), the typical case is when > we can use split vectors for the new shuffle. So pre splitting the > vectors seems fine as we will using some of the result of the presplit > in the vector shuffle. I don't particular like prebuilding the > BuildOps though because we build a set of extract element nodes that > we will typically throw away. It seems a little cleaner to me to > iterate through the mask again and build these nodes when we need > them. What do you think? I don't much like this either, yet it seems a pity to duplicate the logic, most of which is the same. I decided to do it this way after a small analysis of the probability of being able to make a vector shuffle assuming that the original mask indices are uniformly randomly distributed. If the vector being split has length 2 or 4 then a vector shuffle is always used. However when splitting a vector of length 8, I calculate that there is only about one chance in three that you can construct a vector shuffle. For length 16 this drops to one chance in 50. Thus making build vector elements is only likely to be a waste of time for vectors of length 2 or 4. In these cases you construct either 2 or 4 pointless nodes. This is not a big cost. Ciao, Duncan. From isanbard at gmail.com Thu Nov 13 03:33:01 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 13 Nov 2008 01:33:01 -0800 Subject: [llvm-commits] [llvm] r59202 - in /llvm/trunk: include/llvm/Attributes.h include/llvm/CodeGen/Passes.h lib/AsmParser/LLLexer.cpp lib/AsmParser/llvmAsmParser.y lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/StackProtector.cpp lib/VMCore/Attributes.cpp In-Reply-To: <200811130948.15523.duncan.sands@math.u-psud.fr> References: <200811130102.mAD12KwL024185@zion.cs.uiuc.edu> <200811130948.15523.duncan.sands@math.u-psud.fr> Message-ID: <8C882454-0062-4026-BE5A-3ADBBAE55C25@gmail.com> On Nov 13, 2008, at 12:48 AM, Duncan Sands wrote: > Hi Bill, > >> Implement stack protectors as function attributes: "ssp" and >> "sspreq". > > if a sspreq function is inlined into a function without either of > these > attributes, then you won't get stack protection on the inlined code, > right? > That's correct. The attribute doesn't transfer during inlining. That might change in the future, though. -bw From isanbard at gmail.com Thu Nov 13 04:18:36 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 13 Nov 2008 10:18:36 -0000 Subject: [llvm-commits] [llvm] r59241 - /llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Message-ID: <200811131018.mADAIa6E021142@zion.cs.uiuc.edu> Author: void Date: Thu Nov 13 04:18:35 2008 New Revision: 59241 URL: http://llvm.org/viewvc/llvm-project?rev=59241&view=rev Log: Put comma in correct place for call to StructType::get Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=59241&r1=59240&r2=59241&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Thu Nov 13 04:18:35 2008 @@ -152,10 +152,12 @@ OS << "StructType::get("; for (std::vector::const_iterator - I = ArgTypes.begin(), E = ArgTypes.end(); I != E; ++I) + I = ArgTypes.begin(), E = ArgTypes.end(); I != E; ++I) { EmitTypeGenerate(OS, *I, ArgNo); + OS << ", "; + } - OS << ", NULL)"; + OS << " NULL)"; } static void EmitTypeGenerate(std::ostream &OS, const Record *ArgType, From isanbard at gmail.com Thu Nov 13 06:03:02 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 13 Nov 2008 12:03:02 -0000 Subject: [llvm-commits] [llvm] r59242 - /llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Message-ID: <200811131203.mADC32bG024642@zion.cs.uiuc.edu> Author: void Date: Thu Nov 13 06:03:00 2008 New Revision: 59242 URL: http://llvm.org/viewvc/llvm-project?rev=59242&view=rev Log: Fix to record comparator to make it work for return values > 1. Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=59242&r1=59241&r2=59242&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Thu Nov 13 06:03:00 2008 @@ -222,7 +222,7 @@ return (*LHSVec)[i]->getName() < (*RHSVec)[i]->getName(); } while (++i != LHSSize); - if (i != RHSSize) return false; + if (i != RHSSize) return true; i = 0; LHSVec = &LHS.second; From criswell at cs.uiuc.edu Thu Nov 13 10:24:15 2008 From: criswell at cs.uiuc.edu (John Criswell) Date: Thu, 13 Nov 2008 10:24:15 -0600 Subject: [llvm-commits] [llvm] r59208 - /llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp In-Reply-To: <200811130128.mAD1SfCx025350@zion.cs.uiuc.edu> References: <200811130128.mAD1SfCx025350@zion.cs.uiuc.edu> Message-ID: <491C54AF.90805@cs.uiuc.edu> Dear Devang, This patch breaks the -strip pass. The RemoveDeadConstant() method is defined as: virtual void destroyConstant() { assert(0 && "Not reached!"); } ... on line 94 of include/llvm/Constant.h. -- John T. Devang Patel wrote: > Author: dpatel > Date: Wed Nov 12 19:28:40 2008 > New Revision: 59208 > > URL: http://llvm.org/viewvc/llvm-project?rev=59208&view=rev > Log: > Really remove all debug information. > > Modified: > llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp > > Modified: llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp?rev=59208&r1=59207&r2=59208&view=diff > > ============================================================================== > --- llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp (original) > +++ llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp Wed Nov 12 19:28:40 2008 > @@ -56,13 +56,23 @@ > return new StripSymbols(OnlyDebugInfo); > } > > +/// OnlyUsedBy - Return true if V is only used by Usr. > +static bool OnlyUsedBy(Value *V, Value *Usr) { > + for(Value::use_iterator I = V->use_begin(), E = V->use_end(); I != E; ++I) { > + User *U = *I; > + if (U != Usr) > + return false; > + } > + return true; > +} > + > static void RemoveDeadConstant(Constant *C) { > assert(C->use_empty() && "Constant is not dead!"); > - std::vector Operands; > + SmallPtrSet Operands; > for (unsigned i = 0, e = C->getNumOperands(); i != e; ++i) > if (isa(C->getOperand(i)->getType()) && > - C->getOperand(i)->hasOneUse()) > - Operands.push_back(C->getOperand(i)); > + OnlyUsedBy(C->getOperand(i), C)) > + Operands.insert(C->getOperand(i)); > if (GlobalVariable *GV = dyn_cast(C)) { > if (!GV->hasInternalLinkage()) return; // Don't delete non static globals. > GV->eraseFromParent(); > @@ -71,10 +81,9 @@ > C->destroyConstant(); > > // If the constant referenced anything, see if we can delete it as well. > - while (!Operands.empty()) { > - RemoveDeadConstant(Operands.back()); > - Operands.pop_back(); > - } > + for (SmallPtrSet::iterator OI = Operands.begin(), > + OE = Operands.end(); OI != OE; ++OI) > + RemoveDeadConstant(*OI); > } > > // Strip the symbol table of its names. > @@ -145,8 +154,6 @@ > Function *RegionStart = M.getFunction("llvm.dbg.region.start"); > Function *RegionEnd = M.getFunction("llvm.dbg.region.end"); > Function *Declare = M.getFunction("llvm.dbg.declare"); > - if (!FuncStart && !StopPoint && !RegionStart && !RegionEnd && !Declare) > - return true; > > std::vector DeadGlobals; > > @@ -213,8 +220,30 @@ > Declare->eraseFromParent(); > } > > - // Finally, delete any internal globals that were only used by the debugger > - // intrinsics. > + // llvm.dbg.compile_units and llvm.dbg.subprograms are marked as linkonce > + // but since we are removing all debug information, make them internal now. > + if (Constant *C = M.getNamedGlobal("llvm.dbg.compile_units")) > + if (GlobalVariable *GV = dyn_cast(C)) > + GV->setLinkage(GlobalValue::InternalLinkage); > + > + if (Constant *C = M.getNamedGlobal("llvm.dbg.subprograms")) > + if (GlobalVariable *GV = dyn_cast(C)) > + GV->setLinkage(GlobalValue::InternalLinkage); > + > + // Delete all dbg variables. > + const Type *DbgVTy = M.getTypeByName("llvm.dbg.variable.type"); > + const Type *DbgGVTy = M.getTypeByName("llvm.dbg.global_variable.type"); > + if (DbgVTy || DbgGVTy) > + for (Module::global_iterator I = M.global_begin(), E = M.global_end(); > + I != E; ++I) > + if (GlobalVariable *GV = dyn_cast(I)) > + if (GV->hasName() && GV->use_empty() > + && !strncmp(GV->getNameStart(), "llvm.dbg", 8) > + && (GV->getType()->getElementType() == DbgVTy > + || GV->getType()->getElementType() == DbgGVTy)) > + DeadGlobals.push_back(GV); > + > + // Delete any internal globals that were only used by the debugger intrinsics. > while (!DeadGlobals.empty()) { > GlobalVariable *GV = DeadGlobals.back(); > DeadGlobals.pop_back(); > @@ -222,5 +251,17 @@ > RemoveDeadConstant(GV); > } > > + // Remove all llvm.dbg types. > + TypeSymbolTable &ST = M.getTypeSymbolTable(); > + TypeSymbolTable::iterator TI = ST.begin(); > + TypeSymbolTable::iterator TE = ST.end(); > + while ( TI != TE ) { > + const std::string &Name = TI->first; > + if (!strncmp(Name.c_str(), "llvm.dbg.", 9)) > + ST.remove(TI++); > + else > + ++TI; > + } > + > return true; > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From gohman at apple.com Thu Nov 13 10:31:45 2008 From: gohman at apple.com (Dan Gohman) Date: Thu, 13 Nov 2008 16:31:45 -0000 Subject: [llvm-commits] [llvm] r59246 - in /llvm/trunk/lib/CodeGen: LiveIntervalAnalysis.cpp LiveVariables.cpp Message-ID: <200811131631.mADGVoO3001564@zion.cs.uiuc.edu> Author: djg Date: Thu Nov 13 10:31:27 2008 New Revision: 59246 URL: http://llvm.org/viewvc/llvm-project?rev=59246&view=rev Log: Use find_first/find_next to iterate through all the set bits in a BitVector, instead of manually testing each bit. Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp llvm/trunk/lib/CodeGen/LiveVariables.cpp Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=59246&r1=59245&r2=59246&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Thu Nov 13 10:31:27 2008 @@ -399,14 +399,13 @@ // Iterate over all of the blocks that the variable is completely // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the // live interval. - for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) { - if (vi.AliveBlocks[i]) { - LiveRange LR(getMBBStartIdx(i), - getMBBEndIdx(i)+1, // MBB ends at -1. - ValNo); - interval.addRange(LR); - DOUT << " +" << LR; - } + for (int i = vi.AliveBlocks.find_first(); i != -1; + i = vi.AliveBlocks.find_next(i)) { + LiveRange LR(getMBBStartIdx(i), + getMBBEndIdx(i)+1, // MBB ends at -1. + ValNo); + interval.addRange(LR); + DOUT << " +" << LR; } // Finally, this virtual register is live from the start of any killing Modified: llvm/trunk/lib/CodeGen/LiveVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveVariables.cpp?rev=59246&r1=59245&r2=59246&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveVariables.cpp Thu Nov 13 10:31:27 2008 @@ -52,11 +52,11 @@ void LiveVariables::VarInfo::dump() const { cerr << " Alive in blocks: "; - for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i) - if (AliveBlocks[i]) cerr << i << ", "; + for (int i = AliveBlocks.find_first(); i != -1; i = AliveBlocks.find_next(i)) + cerr << i << ", "; cerr << " Used in blocks: "; - for (unsigned i = 0, e = UsedBlocks.size(); i != e; ++i) - if (UsedBlocks[i]) cerr << i << ", "; + for (int i = UsedBlocks.find_first(); i != -1; i = UsedBlocks.find_next(i)) + cerr << i << ", "; cerr << "\n Killed by:"; if (Kills.empty()) cerr << " No instructions.\n"; From dpatel at apple.com Thu Nov 13 11:35:43 2008 From: dpatel at apple.com (Devang Patel) Date: Thu, 13 Nov 2008 09:35:43 -0800 Subject: [llvm-commits] [llvm] r59208 - /llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp In-Reply-To: <491C54AF.90805@cs.uiuc.edu> References: <200811130128.mAD1SfCx025350@zion.cs.uiuc.edu> <491C54AF.90805@cs.uiuc.edu> Message-ID: <7D146BD2-E7AE-49F9-BC59-9D523DF0354E@apple.com> On Nov 13, 2008, at 8:24 AM, John Criswell wrote: > Dear Devang, > > This patch breaks the -strip pass. The RemoveDeadConstant() method > is defined as: > > virtual void destroyConstant() { assert(0 && "Not reached!"); } > > ... on line 94 of include/llvm/Constant.h. Hmm.. the patch does not add RemoveDeadConstant() function. However, this function uses destroyContent(). Do you have a test case handy ? Thanks, - Devang > > > -- John T. > > Devang Patel wrote: >> Author: dpatel >> Date: Wed Nov 12 19:28:40 2008 >> New Revision: 59208 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=59208&view=rev >> Log: >> Really remove all debug information. >> >> Modified: >> llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp >> >> Modified: llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp?rev=59208&r1=59207&r2=59208&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp (original) >> +++ llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp Wed Nov 12 >> 19:28:40 2008 >> @@ -56,13 +56,23 @@ >> return new StripSymbols(OnlyDebugInfo); >> } >> +/// OnlyUsedBy - Return true if V is only used by Usr. >> +static bool OnlyUsedBy(Value *V, Value *Usr) { >> + for(Value::use_iterator I = V->use_begin(), E = V->use_end(); I ! >> = E; ++I) { >> + User *U = *I; >> + if (U != Usr) >> + return false; >> + } >> + return true; >> +} >> + >> static void RemoveDeadConstant(Constant *C) { >> assert(C->use_empty() && "Constant is not dead!"); >> - std::vector Operands; >> + SmallPtrSet Operands; >> for (unsigned i = 0, e = C->getNumOperands(); i != e; ++i) >> if (isa(C->getOperand(i)->getType()) && >> - C->getOperand(i)->hasOneUse()) >> - Operands.push_back(C->getOperand(i)); >> + OnlyUsedBy(C->getOperand(i), C)) + Operands.insert(C- >> >getOperand(i)); >> if (GlobalVariable *GV = dyn_cast(C)) { >> if (!GV->hasInternalLinkage()) return; // Don't delete non >> static globals. >> GV->eraseFromParent(); >> @@ -71,10 +81,9 @@ >> C->destroyConstant(); >> // If the constant referenced anything, see if we can delete it >> as well. >> - while (!Operands.empty()) { >> - RemoveDeadConstant(Operands.back()); >> - Operands.pop_back(); >> - } >> + for (SmallPtrSet::iterator OI = Operands.begin(), >> + OE = Operands.end(); OI != OE; ++OI) >> + RemoveDeadConstant(*OI); >> } >> // Strip the symbol table of its names. >> @@ -145,8 +154,6 @@ >> Function *RegionStart = M.getFunction("llvm.dbg.region.start"); >> Function *RegionEnd = M.getFunction("llvm.dbg.region.end"); >> Function *Declare = M.getFunction("llvm.dbg.declare"); >> - if (!FuncStart && !StopPoint && !RegionStart && !RegionEnd && ! >> Declare) >> - return true; >> std::vector DeadGlobals; >> @@ -213,8 +220,30 @@ >> Declare->eraseFromParent(); >> } >> - // Finally, delete any internal globals that were only used by >> the debugger >> - // intrinsics. >> + // llvm.dbg.compile_units and llvm.dbg.subprograms are marked as >> linkonce >> + // but since we are removing all debug information, make them >> internal now. >> + if (Constant *C = M.getNamedGlobal("llvm.dbg.compile_units")) >> + if (GlobalVariable *GV = dyn_cast(C)) >> + GV->setLinkage(GlobalValue::InternalLinkage); >> + >> + if (Constant *C = M.getNamedGlobal("llvm.dbg.subprograms")) >> + if (GlobalVariable *GV = dyn_cast(C)) >> + GV->setLinkage(GlobalValue::InternalLinkage); >> + >> + // Delete all dbg variables. >> + const Type *DbgVTy = M.getTypeByName("llvm.dbg.variable.type"); >> + const Type *DbgGVTy = >> M.getTypeByName("llvm.dbg.global_variable.type"); >> + if (DbgVTy || DbgGVTy) >> + for (Module::global_iterator I = M.global_begin(), E = >> M.global_end(); + I != E; ++I) + if (GlobalVariable >> *GV = dyn_cast(I)) >> + if (GV->hasName() && GV->use_empty() >> + && !strncmp(GV->getNameStart(), "llvm.dbg", 8) >> + && (GV->getType()->getElementType() == DbgVTy >> + || GV->getType()->getElementType() == DbgGVTy)) >> + DeadGlobals.push_back(GV); >> + >> + // Delete any internal globals that were only used by the >> debugger intrinsics. >> while (!DeadGlobals.empty()) { >> GlobalVariable *GV = DeadGlobals.back(); >> DeadGlobals.pop_back(); >> @@ -222,5 +251,17 @@ >> RemoveDeadConstant(GV); >> } >> + // Remove all llvm.dbg types. >> + TypeSymbolTable &ST = M.getTypeSymbolTable(); >> + TypeSymbolTable::iterator TI = ST.begin(); >> + TypeSymbolTable::iterator TE = ST.end(); >> + while ( TI != TE ) { >> + const std::string &Name = TI->first; >> + if (!strncmp(Name.c_str(), "llvm.dbg.", 9)) >> + ST.remove(TI++); >> + else + ++TI; >> + } >> + return true; >> } >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > From gohman at apple.com Thu Nov 13 13:07:27 2008 From: gohman at apple.com (Dan Gohman) Date: Thu, 13 Nov 2008 19:07:27 -0000 Subject: [llvm-commits] [llvm] r59257 - /llvm/trunk/docs/GettingStarted.html Message-ID: <200811131907.mADJ7UYr008010@zion.cs.uiuc.edu> Author: djg Date: Thu Nov 13 13:07:07 2008 New Revision: 59257 URL: http://llvm.org/viewvc/llvm-project?rev=59257&view=rev Log: LLVM can generate native code for amd64 on "Linux". Modified: llvm/trunk/docs/GettingStarted.html Modified: llvm/trunk/docs/GettingStarted.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GettingStarted.html?rev=59257&r1=59256&r2=59257&view=diff ============================================================================== --- llvm/trunk/docs/GettingStarted.html (original) +++ llvm/trunk/docs/GettingStarted.html Thu Nov 13 13:07:07 2008 @@ -252,7 +252,7 @@

From sabre at nondot.org Mon Nov 10 00:49:44 2008 From: sabre at nondot.org (Chris Lattner) Date: Mon, 10 Nov 2008 00:49:44 -0600 Subject: [llvm-commits] CVS: llvm-www/www-index.html header.incl Message-ID: <200811100649.mAA6nio3022629@zion.cs.uiuc.edu> Changes in directory llvm-www: www-index.html updated: 1.166 -> 1.167 header.incl updated: 1.73 -> 1.74 --- Log message: 2.4 is live. --- Diffs of the changes: (+5 -4) header.incl \| 5 +++-- www-index.html \| 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) Index: llvm-www/www-index.html diff -u llvm-www/www-index.html:1.166 llvm-www/www-index.html:1.167 --- llvm-www/www-index.html:1.166 Thu Nov 6 19:44:54 2008 +++ llvm-www/www-index.html Mon Nov 10 00:49:25 2008 @@ -91,9 +91,9 @@ Latest LLVM Release! - June 9, 2008: LLVM 2.3 is now available + November 9, 2008: LLVM 2.4 is now available for download! LLVM is publicly available under an open source License. Also, you might want to + href="releases/2.4/LICENSE.TXT">License. Also, you might want to check out the new features in SVN that will appear in the next LLVM release. If you want them early, download LLVM through Index: llvm-www/header.incl diff -u llvm-www/header.incl:1.73 llvm-www/header.incl:1.74 --- llvm-www/header.incl:1.73 Sun Sep 21 22:15:35 2008 +++ llvm-www/header.incl Mon Nov 10 00:49:25 2008 @@ -39,7 +39,7 @@ Download! Download now: -LLVM 2.3 +LLVM 2.4 Try the @@ -47,7 +47,7 @@ View the open-source -license +license @@ -69,6 +69,7 @@ Status Updates + Nov 9, 2008 Jun 9, 2008 Feb 11, 2008 Sep 26, 2007 From sabre at nondot.org Mon Nov 10 00:51:22 2008 From: sabre at nondot.org (Chris Lattner) Date: Mon, 10 Nov 2008 00:51:22 -0600 Subject: [llvm-commits] CVS: llvm-www/www-index.html Message-ID: <200811100651.mAA6pMTl022712@zion.cs.uiuc.edu> Changes in directory llvm-www: www-index.html updated: 1.167 -> 1.168 --- Log message: 2.4 is done. --- Diffs of the changes: (+2 -9) www-index.html \| 11 ++--------- 1 files changed, 2 insertions(+), 9 deletions(-) Index: llvm-www/www-index.html diff -u llvm-www/www-index.html:1.167 llvm-www/www-index.html:1.168 --- llvm-www/www-index.html:1.167 Mon Nov 10 00:49:25 2008 +++ llvm-www/www-index.html Mon Nov 10 00:51:03 2008 @@ -105,15 +105,8 @@ Upcoming Releases - LLVM 2.4 release schedule: - - Oct 6, 2008: Branch creation/Code Freeze (9PM PDT). - Oct 9, 2008: First round of pre-release testing begins. - Oct 19, 2008: Pre-release testing ends. - Oct 31, 2008: Second round of pre-release testing begins. - Nov 5, 2008: Pre-release testing ends. - Nov 9, 2008: 2.4 Released. - + LLVM 2.5 release schedule: + Roughly February or March, stay tuned for details. From sabre at nondot.org Mon Nov 10 00:52:38 2008 From: sabre at nondot.org (Chris Lattner) Date: Mon, 10 Nov 2008 00:52:38 -0600 Subject: [llvm-commits] CVS: llvm-www/www-index.html Message-ID: <200811100652.mAA6qcre022770@zion.cs.uiuc.edu> Changes in directory llvm-www: www-index.html updated: 1.168 -> 1.169 --- Log message: remove 'random neat uses' boxes, which are quite old. --- Diffs of the changes: (+4 -0) www-index.html \| 4 ++++ 1 files changed, 4 insertions(+) Index: llvm-www/www-index.html diff -u llvm-www/www-index.html:1.168 llvm-www/www-index.html:1.169 --- llvm-www/www-index.html:1.168 Mon Nov 10 00:51:03 2008 +++ llvm-www/www-index.html Mon Nov 10 00:52:19 2008 @@ -132,6 +132,8 @@ + +
Linux	amd64³	amd64	GCC