From evan.cheng at apple.com Mon Jan 26 01:31:20 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 26 Jan 2009 07:31:20 -0000 Subject: [llvm-commits] [llvm] r63005 - /llvm/trunk/include/llvm/Analysis/DebugInfo.h Message-ID: <200901260731.n0Q7VLNX019857@zion.cs.uiuc.edu> Author: evancheng Date: Mon Jan 26 01:31:20 2009 New Revision: 63005 URL: http://llvm.org/viewvc/llvm-project?rev=63005&view=rev Log: LLVM_SUPPORT_DEBUGINFO_H -> LLVM_ANALYSIS_DEBUGINFO_H since DebugInfo.h is under Analysis. Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=63005&r1=63004&r2=63005&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Mon Jan 26 01:31:20 2009 @@ -12,8 +12,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_SUPPORT_DEBUGINFO_H -#define LLVM_SUPPORT_DEBUGINFO_H +#ifndef LLVM_ANALYSIS_DEBUGINFO_H +#define LLVM_ANALYSIS_DEBUGINFO_H #include "llvm/ADT/StringMap.h" #include "llvm/ADT/DenseMap.h" From evan.cheng at apple.com Mon Jan 26 01:40:14 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 26 Jan 2009 07:40:14 -0000 Subject: [llvm-commits] [llvm] r63007 - /llvm/trunk/include/llvm/CodeGen/DwarfWriter.h Message-ID: <200901260740.n0Q7eEwK020163@zion.cs.uiuc.edu> Author: evancheng Date: Mon Jan 26 01:40:13 2009 New Revision: 63007 URL: http://llvm.org/viewvc/llvm-project?rev=63007&view=rev Log: Looks like comments were chopped off. Modified: llvm/trunk/include/llvm/CodeGen/DwarfWriter.h Modified: llvm/trunk/include/llvm/CodeGen/DwarfWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DwarfWriter.h?rev=63007&r1=63006&r2=63007&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/DwarfWriter.h (original) +++ llvm/trunk/include/llvm/CodeGen/DwarfWriter.h Mon Jan 26 01:40:13 2009 @@ -79,8 +79,9 @@ /// ValidDebugInfo - Return true if V represents valid debug info value. bool ValidDebugInfo(Value *V); - /// label. Returns a unique label ID used to generate a label and provide - /// correspondence to the source line list. + /// RecordSourceLine - Register a source line with debug info. Returns a + /// unique label ID used to generate a label and provide correspondence to + /// the source line list. unsigned RecordSourceLine(unsigned Line, unsigned Col, unsigned Src); /// RecordSource - Register a source file with debug info. Returns an source From evan.cheng at apple.com Mon Jan 26 01:41:49 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 26 Jan 2009 07:41:49 -0000 Subject: [llvm-commits] [llvm] r63008 - in /llvm/trunk: include/llvm/CodeGen/DebugLoc.h include/llvm/CodeGen/MachineFunction.h lib/CodeGen/MachineFunction.cpp Message-ID: <200901260741.n0Q7fnOn020226@zion.cs.uiuc.edu> Author: evancheng Date: Mon Jan 26 01:41:49 2009 New Revision: 63008 URL: http://llvm.org/viewvc/llvm-project?rev=63008&view=rev Log: Add data structure to define and track debug location during codegen. Added: llvm/trunk/include/llvm/CodeGen/DebugLoc.h Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h llvm/trunk/lib/CodeGen/MachineFunction.cpp Added: llvm/trunk/include/llvm/CodeGen/DebugLoc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DebugLoc.h?rev=63008&view=auto ============================================================================== --- llvm/trunk/include/llvm/CodeGen/DebugLoc.h (added) +++ llvm/trunk/include/llvm/CodeGen/DebugLoc.h Mon Jan 26 01:41:49 2009 @@ -0,0 +1,109 @@ +//===---- llvm/CodeGen/DebugLoc.h - Debug Location Information --*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines a number of light weight data structures used by the code +// generator to describe and track debug location information. + +#ifndef LLVM_CODEGEN_DEBUGLOC_H +#define LLVM_CODEGEN_DEBUGLOC_H + +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/StringMap.h" +#include + +namespace llvm { + + /// DebugLocTuple - Debug location tuple of filename id, line and column. + /// + struct DebugLocTuple { + unsigned FileId, Line, Col; + + DebugLocTuple(unsigned fi, unsigned l, unsigned c) + : FileId(fi), Line(l), Col(c) {}; + }; + + /// DebugLoc - Debug location id. This is carried by SDNode and + /// MachineInstr to index into a vector of unique debug location tuples. + class DebugLoc { + unsigned Idx; + + public: + DebugLoc() : Idx(~0U) {} + + static DebugLoc getNoDebugLoc() { DebugLoc L; L.Idx = 0; return L; } + static DebugLoc get(unsigned idx) { DebugLoc L; L.Idx = idx; return L; } + + bool isInvalid() { return Idx == ~0U; } + bool isUnknown() { return Idx == 0; } + }; + + struct DebugLocTupleDenseMapInfo { + static inline DebugLocTuple getEmptyKey() { + return DebugLocTuple(~0U, ~0U, ~0U); + } + static inline DebugLocTuple getTombstoneKey() { + return DebugLocTuple(~1U, ~1U, ~1U); + } + static unsigned getHashValue(const DebugLocTuple &Val) { + return DenseMapInfo::getHashValue(Val.FileId) ^ + DenseMapInfo::getHashValue(Val.Line) ^ + DenseMapInfo::getHashValue(Val.Col); + } + static bool isEqual(const DebugLocTuple &LHS, const DebugLocTuple &RHS) { + return LHS.FileId == RHS.FileId && + LHS.Line == RHS.Line && + LHS.Col == RHS.Col; + } + + static bool isPod() { return true; } + }; + + typedef DenseMap + DebugIdMapType; + + /// DebugLocTracker - This class tracks debug location information. + /// + struct DebugLocTracker { + // NumFilenames - Size of the DebugFilenames vector. + // + unsigned NumFilenames; + + // DebugFilenames - A vector of unique file names. + // + std::vector DebugFilenames; + + // DebugFilenamesMap - File name to DebugFilenames index map. + // + StringMap DebugFilenamesMap; + + // NumDebugLocations - Size of the DebugLocations vector. + unsigned NumDebugLocations; + + // DebugLocations - A vector of unique DebugLocTuple's. + // + std::vector DebugLocations; + + // DebugIdsMap - This maps DebugLocTuple's to indices into + // DebugLocations vector. + DebugIdMapType DebugIdMap; + + DebugLocTracker() : NumFilenames(0), NumDebugLocations(0) {} + + ~DebugLocTracker() { + NumFilenames = 0; + DebugFilenames.clear(); + DebugFilenamesMap.clear(); + DebugLocations.clear(); + DebugIdMap.clear(); + } + }; + +} // end namespace llvm + +#endif /* LLVM_CODEGEN_DEBUGLOC_H */ Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=63008&r1=63007&r2=63008&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Mon Jan 26 01:41:49 2009 @@ -19,6 +19,7 @@ #define LLVM_CODEGEN_MACHINEFUNCTION_H #include "llvm/ADT/ilist.h" +#include "llvm/CodeGen/DebugLoc.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/Support/Annotation.h" #include "llvm/Support/Allocator.h" @@ -27,11 +28,11 @@ namespace llvm { class Function; -class TargetMachine; class MachineRegisterInfo; class MachineFrameInfo; class MachineConstantPool; class MachineJumpTableInfo; +class TargetMachine; template <> struct ilist_traits @@ -94,6 +95,9 @@ typedef ilist BasicBlockListType; BasicBlockListType BasicBlocks; + // Tracks debug locations. + DebugLocTracker DebugLocInfo; + public: MachineFunction(const Function *Fn, const TargetMachine &TM); ~MachineFunction(); @@ -302,6 +306,15 @@ /// DeleteMachineBasicBlock - Delete the given MachineBasicBlock. /// void DeleteMachineBasicBlock(MachineBasicBlock *MBB); + + //===--------------------------------------------------------------------===// + // Debug location. + // + + /// lookUpDebugLocId - Look up the DebugLocTuple index with the given + /// filename, line, and column. It may add a new filename and / or + /// a new DebugLocTuple. + unsigned lookUpDebugLocId(const char *Filename, unsigned Line, unsigned Col); }; //===--------------------------------------------------------------------===// Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=63008&r1=63007&r2=63008&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Mon Jan 26 01:41:49 2009 @@ -378,6 +378,33 @@ return *mc; } +/// lookUpDebugLocId - Look up the DebugLocTuple index with the given +/// filename, line, and column. It may add a new filename and / or +/// a new DebugLocTuple. +unsigned MachineFunction::lookUpDebugLocId(const char *Filename, unsigned Line, + unsigned Col) { + unsigned FileId; + StringMap::iterator I = + DebugLocInfo.DebugFilenamesMap.find(Filename); + if (I != DebugLocInfo.DebugFilenamesMap.end()) + FileId = I->second; + else { + // Add a new filename. + FileId = DebugLocInfo.NumFilenames++; + DebugLocInfo.DebugFilenames.push_back(Filename); + DebugLocInfo.DebugFilenamesMap[Filename] = FileId; + } + + struct DebugLocTuple Tuple(FileId, Line, Col); + DebugIdMapType::iterator II = DebugLocInfo.DebugIdMap.find(Tuple); + if (II != DebugLocInfo.DebugIdMap.end()) + return II->second; + // Add a new tuple. + DebugLocInfo.DebugLocations.push_back(Tuple); + DebugLocInfo.DebugIdMap[Tuple] = DebugLocInfo.NumDebugLocations; + return DebugLocInfo.NumDebugLocations++; +} + //===----------------------------------------------------------------------===// // MachineFrameInfo implementation //===----------------------------------------------------------------------===// From evan.cheng at apple.com Mon Jan 26 01:53:42 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 26 Jan 2009 07:53:42 -0000 Subject: [llvm-commits] [llvm] r63009 - in /llvm/trunk: include/llvm/CodeGen/DebugLoc.h include/llvm/CodeGen/MachineFunction.h lib/CodeGen/MachineFunction.cpp Message-ID: <200901260753.n0Q7rgjS020573@zion.cs.uiuc.edu> Author: evancheng Date: Mon Jan 26 01:53:42 2009 New Revision: 63009 URL: http://llvm.org/viewvc/llvm-project?rev=63009&view=rev Log: Actually source file has already been uniquified into an id during isel. Eliminate the StringMap. Modified: llvm/trunk/include/llvm/CodeGen/DebugLoc.h llvm/trunk/include/llvm/CodeGen/MachineFunction.h llvm/trunk/lib/CodeGen/MachineFunction.cpp Modified: llvm/trunk/include/llvm/CodeGen/DebugLoc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DebugLoc.h?rev=63009&r1=63008&r2=63009&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/DebugLoc.h (original) +++ llvm/trunk/include/llvm/CodeGen/DebugLoc.h Mon Jan 26 01:53:42 2009 @@ -14,7 +14,6 @@ #define LLVM_CODEGEN_DEBUGLOC_H #include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/StringMap.h" #include namespace llvm { @@ -22,10 +21,10 @@ /// DebugLocTuple - Debug location tuple of filename id, line and column. /// struct DebugLocTuple { - unsigned FileId, Line, Col; + unsigned Src, Line, Col; - DebugLocTuple(unsigned fi, unsigned l, unsigned c) - : FileId(fi), Line(l), Col(c) {}; + DebugLocTuple(unsigned s, unsigned l, unsigned c) + : Src(s), Line(l), Col(c) {}; }; /// DebugLoc - Debug location id. This is carried by SDNode and @@ -51,14 +50,14 @@ return DebugLocTuple(~1U, ~1U, ~1U); } static unsigned getHashValue(const DebugLocTuple &Val) { - return DenseMapInfo::getHashValue(Val.FileId) ^ + return DenseMapInfo::getHashValue(Val.Src) ^ DenseMapInfo::getHashValue(Val.Line) ^ DenseMapInfo::getHashValue(Val.Col); } static bool isEqual(const DebugLocTuple &LHS, const DebugLocTuple &RHS) { - return LHS.FileId == RHS.FileId && + return LHS.Src == RHS.Src && LHS.Line == RHS.Line && - LHS.Col == RHS.Col; + LHS.Col == RHS.Col; } static bool isPod() { return true; } @@ -70,18 +69,6 @@ /// DebugLocTracker - This class tracks debug location information. /// struct DebugLocTracker { - // NumFilenames - Size of the DebugFilenames vector. - // - unsigned NumFilenames; - - // DebugFilenames - A vector of unique file names. - // - std::vector DebugFilenames; - - // DebugFilenamesMap - File name to DebugFilenames index map. - // - StringMap DebugFilenamesMap; - // NumDebugLocations - Size of the DebugLocations vector. unsigned NumDebugLocations; @@ -93,12 +80,9 @@ // DebugLocations vector. DebugIdMapType DebugIdMap; - DebugLocTracker() : NumFilenames(0), NumDebugLocations(0) {} + DebugLocTracker() : NumDebugLocations(0) {} ~DebugLocTracker() { - NumFilenames = 0; - DebugFilenames.clear(); - DebugFilenamesMap.clear(); DebugLocations.clear(); DebugIdMap.clear(); } Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=63009&r1=63008&r2=63009&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Mon Jan 26 01:53:42 2009 @@ -312,9 +312,9 @@ // /// lookUpDebugLocId - Look up the DebugLocTuple index with the given - /// filename, line, and column. It may add a new filename and / or + /// source file, line, and column. It may add a new filename and / or /// a new DebugLocTuple. - unsigned lookUpDebugLocId(const char *Filename, unsigned Line, unsigned Col); + unsigned lookUpDebugLocId(unsigned Src, unsigned Line, unsigned Col); }; //===--------------------------------------------------------------------===// Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=63009&r1=63008&r2=63009&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Mon Jan 26 01:53:42 2009 @@ -379,23 +379,11 @@ } /// lookUpDebugLocId - Look up the DebugLocTuple index with the given -/// filename, line, and column. It may add a new filename and / or +/// source file, line, and column. It may add a new filename and / or /// a new DebugLocTuple. -unsigned MachineFunction::lookUpDebugLocId(const char *Filename, unsigned Line, +unsigned MachineFunction::lookUpDebugLocId(unsigned Src, unsigned Line, unsigned Col) { - unsigned FileId; - StringMap::iterator I = - DebugLocInfo.DebugFilenamesMap.find(Filename); - if (I != DebugLocInfo.DebugFilenamesMap.end()) - FileId = I->second; - else { - // Add a new filename. - FileId = DebugLocInfo.NumFilenames++; - DebugLocInfo.DebugFilenames.push_back(Filename); - DebugLocInfo.DebugFilenamesMap[Filename] = FileId; - } - - struct DebugLocTuple Tuple(FileId, Line, Col); + struct DebugLocTuple Tuple(Src, Line, Col); DebugIdMapType::iterator II = DebugLocInfo.DebugIdMap.find(Tuple); if (II != DebugLocInfo.DebugIdMap.end()) return II->second; From espindola at google.com Mon Jan 26 02:59:23 2009 From: espindola at google.com (Rafael Espindola) Date: Mon, 26 Jan 2009 08:59:23 +0000 Subject: [llvm-commits] [llvm] r62987 - in /llvm/trunk/tools: Makefile lto/Makefile In-Reply-To: <200901260304.n0Q34vaF011440@zion.cs.uiuc.edu> References: <200901260304.n0Q34vaF011440@zion.cs.uiuc.edu> Message-ID: <38a0d8450901260059o26bf89c3ja428fd676e7b05bc@mail.gmail.com> Thanks :-) 2009/1/26 Nick Lewycky : > Author: nicholas > Date: Sun Jan 25 21:04:57 2009 > New Revision: 62987 > > URL: http://llvm.org/viewvc/llvm-project?rev=62987&view=rev > Log: > Build libLTO on any platform so long as PIC is enabled. > > Modified: > llvm/trunk/tools/Makefile > llvm/trunk/tools/lto/Makefile > > Modified: llvm/trunk/tools/Makefile > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/Makefile?rev=62987&r1=62986&r2=62987&view=diff > > ============================================================================== > --- llvm/trunk/tools/Makefile (original) > +++ llvm/trunk/tools/Makefile Sun Jan 25 21:04:57 2009 > @@ -25,8 +25,7 @@ > > include $(LEVEL)/Makefile.config > > -# only build new lto project on Darwin for now > -ifeq ($(OS),Darwin) > +ifeq ($(ENABLE_PIC),1) > PARALLEL_DIRS += lto > endif > > > Modified: llvm/trunk/tools/lto/Makefile > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/Makefile?rev=62987&r1=62986&r2=62987&view=diff > > ============================================================================== > --- llvm/trunk/tools/lto/Makefile (original) > +++ llvm/trunk/tools/lto/Makefile Sun Jan 25 21:04:57 2009 > @@ -16,12 +16,8 @@ > include $(LEVEL)/Makefile.config > > LINK_LIBS_IN_SHARED = 1 > -ifeq ($(OS),Darwin) > - SHARED_LIBRARY = 1 > - DONT_BUILD_RELINKED = 1 > -else > - BUILD_ARCHIVE = 1 > -endif > +SHARED_LIBRARY = 1 > +DONT_BUILD_RELINKED = 1 > > LINK_COMPONENTS := $(TARGETS_TO_BUILD) ipo scalaropts linker bitreader bitwriter > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -- Rafael Avila de Espindola Google | Gordon House | Barrow Street | Dublin 4 | Ireland Registered in Dublin, Ireland | Registration Number: 368047 From romix.llvm at googlemail.com Mon Jan 26 05:07:29 2009 From: romix.llvm at googlemail.com (Roman Levenstein) Date: Mon, 26 Jan 2009 11:07:29 -0000 Subject: [llvm-commits] [llvm] r63012 - /llvm/trunk/include/llvm/ADT/BitVector.h Message-ID: <200901261107.n0QB7U3U004379@zion.cs.uiuc.edu> Author: romix Date: Mon Jan 26 05:07:20 2009 New Revision: 63012 URL: http://llvm.org/viewvc/llvm-project?rev=63012&view=rev Log: Fix a bug in BitVector.h. All assignment operations (except the usual assignment operator) were returning a copy of the bit vector, instead of a reference! This old semantics probably did not meet the expectations. With this patch, chained assignments happen to the right object. Modified: llvm/trunk/include/llvm/ADT/BitVector.h Modified: llvm/trunk/include/llvm/ADT/BitVector.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/BitVector.h?rev=63012&r1=63011&r2=63012&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/BitVector.h (original) +++ llvm/trunk/include/llvm/ADT/BitVector.h Mon Jan 26 05:07:20 2009 @@ -286,7 +286,7 @@ } // Intersection, union, disjoint union. - BitVector operator&=(const BitVector &RHS) { + BitVector &operator&=(const BitVector &RHS) { unsigned ThisWords = NumBitWords(size()); unsigned RHSWords = NumBitWords(RHS.size()); unsigned i; @@ -302,14 +302,14 @@ return *this; } - BitVector operator|=(const BitVector &RHS) { + BitVector &operator|=(const BitVector &RHS) { assert(Size == RHS.Size && "Illegal operation!"); for (unsigned i = 0; i < NumBitWords(size()); ++i) Bits[i] |= RHS.Bits[i]; return *this; } - BitVector operator^=(const BitVector &RHS) { + BitVector &operator^=(const BitVector &RHS) { assert(Size == RHS.Size && "Illegal operation!"); for (unsigned i = 0; i < NumBitWords(size()); ++i) Bits[i] ^= RHS.Bits[i]; From snaroff at apple.com Mon Jan 26 12:08:56 2009 From: snaroff at apple.com (Steve Naroff) Date: Mon, 26 Jan 2009 18:08:56 -0000 Subject: [llvm-commits] [llvm] r63017 - in /llvm/trunk/win32: Analysis/Analysis.vcproj CodeGen/CodeGen.vcproj Message-ID: <200901261808.n0QI8uES018228@zion.cs.uiuc.edu> Author: snaroff Date: Mon Jan 26 12:08:55 2009 New Revision: 63017 URL: http://llvm.org/viewvc/llvm-project?rev=63017&view=rev Log: Update VS project files. Modified: llvm/trunk/win32/Analysis/Analysis.vcproj llvm/trunk/win32/CodeGen/CodeGen.vcproj Modified: llvm/trunk/win32/Analysis/Analysis.vcproj URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/win32/Analysis/Analysis.vcproj?rev=63017&r1=63016&r2=63017&view=diff ============================================================================== --- llvm/trunk/win32/Analysis/Analysis.vcproj (original) +++ llvm/trunk/win32/Analysis/Analysis.vcproj Mon Jan 26 12:08:55 2009 @@ -436,6 +436,10 @@ > + + Modified: llvm/trunk/win32/CodeGen/CodeGen.vcproj URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/win32/CodeGen/CodeGen.vcproj?rev=63017&r1=63016&r2=63017&view=diff ============================================================================== --- llvm/trunk/win32/CodeGen/CodeGen.vcproj (original) +++ llvm/trunk/win32/CodeGen/CodeGen.vcproj Mon Jan 26 12:08:55 2009 @@ -341,6 +341,10 @@ > + + @@ -485,6 +489,14 @@ > + + + + @@ -572,6 +584,14 @@ > + + + + From evan.cheng at apple.com Mon Jan 26 12:33:51 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 26 Jan 2009 18:33:51 -0000 Subject: [llvm-commits] [llvm] r63021 - /llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Message-ID: <200901261833.n0QIXpxI019191@zion.cs.uiuc.edu> Author: evancheng Date: Mon Jan 26 12:33:51 2009 New Revision: 63021 URL: http://llvm.org/viewvc/llvm-project?rev=63021&view=rev Log: Silence a bogus compiler warning. Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=63021&r1=63020&r2=63021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original) +++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Mon Jan 26 12:33:51 2009 @@ -1238,7 +1238,7 @@ } // Find a point to restore the value after the barrier. - unsigned RestoreIndex; + unsigned RestoreIndex = 0; MachineBasicBlock::iterator RestorePt = findRestorePoint(BarrierMBB, Barrier, LR->end, RefsInMBB, RestoreIndex); if (RestorePt == BarrierMBB->end()) From evan.cheng at apple.com Mon Jan 26 12:43:35 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 26 Jan 2009 18:43:35 -0000 Subject: [llvm-commits] [llvm] r63022 - in /llvm/trunk: lib/Target/X86/X86ISelDAGToDAG.cpp test/CodeGen/X86/fold-call-3.ll Message-ID: <200901261843.n0QIhZmc019503@zion.cs.uiuc.edu> Author: evancheng Date: Mon Jan 26 12:43:34 2009 New Revision: 63022 URL: http://llvm.org/viewvc/llvm-project?rev=63022&view=rev Log: Enhance logic in X86DAGToDAGISel::PreprocessForRMW which move load inside callseq_start to allow it to be folded into a call. It was not considering the cases where a token factor is between the load and the callseq_start. Added: llvm/trunk/test/CodeGen/X86/fold-call-3.ll Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=63022&r1=63021&r2=63022&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Jan 26 12:43:34 2009 @@ -432,14 +432,27 @@ /// MoveBelowCallSeqStart - Replace CALLSEQ_START operand with load's chain /// operand and move load below the call's chain operand. static void MoveBelowCallSeqStart(SelectionDAG *CurDAG, SDValue Load, - SDValue Call, SDValue Chain) { + SDValue Call, SDValue CallSeqStart) { SmallVector Ops; - for (unsigned i = 0, e = Chain.getNode()->getNumOperands(); i != e; ++i) - if (Load.getNode() == Chain.getOperand(i).getNode()) - Ops.push_back(Load.getOperand(0)); - else - Ops.push_back(Chain.getOperand(i)); - CurDAG->UpdateNodeOperands(Chain, &Ops[0], Ops.size()); + SDValue Chain = CallSeqStart.getOperand(0); + if (Chain.getNode() == Load.getNode()) + Ops.push_back(Load.getOperand(0)); + else { + assert(Chain.getOpcode() == ISD::TokenFactor && + "Unexpected CallSeqStart chain operand"); + for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) + if (Chain.getOperand(i).getNode() == Load.getNode()) + Ops.push_back(Load.getOperand(0)); + else + Ops.push_back(Chain.getOperand(i)); + SDValue NewChain = + CurDAG->getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); + Ops.clear(); + Ops.push_back(NewChain); + } + for (unsigned i = 1, e = CallSeqStart.getNumOperands(); i != e; ++i) + Ops.push_back(CallSeqStart.getOperand(i)); + CurDAG->UpdateNodeOperands(CallSeqStart, &Ops[0], Ops.size()); CurDAG->UpdateNodeOperands(Load, Call.getOperand(0), Load.getOperand(1), Load.getOperand(2)); Ops.clear(); @@ -468,7 +481,13 @@ return false; Chain = Chain.getOperand(0); } - return Chain.getOperand(0).getNode() == Callee.getNode(); + + if (Chain.getOperand(0).getNode() == Callee.getNode()) + return true; + if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor && + Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode())) + return true; + return false; } Added: llvm/trunk/test/CodeGen/X86/fold-call-3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-call-3.ll?rev=63022&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/fold-call-3.ll (added) +++ llvm/trunk/test/CodeGen/X86/fold-call-3.ll Mon Jan 26 12:43:34 2009 @@ -0,0 +1,45 @@ +; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep call | grep 560 +; rdar://6522427 + + %"struct.clang::Action" = type { %"struct.clang::ActionBase" } + %"struct.clang::ActionBase" = type { i32 (...)** } + %"struct.clang::ActionBase::ActionResult<0u>" = type { i8*, i8 } + at NumTrials = internal global i32 10000000 ; [#uses=2] + at llvm.used = appending global [1 x i8*] [ i8* bitcast (void (i8*, %"struct.clang::Action"*)* @_Z25RawPointerPerformanceTestPvRN5clang6ActionE to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] + +define void @_Z25RawPointerPerformanceTestPvRN5clang6ActionE(i8* %Val, %"struct.clang::Action"* %Actions) nounwind { +entry: + %0 = alloca %"struct.clang::ActionBase::ActionResult<0u>", align 8 ; <%"struct.clang::ActionBase::ActionResult<0u>"*> [#uses=3] + %1 = load i32* @NumTrials, align 4 ; [#uses=1] + %2 = icmp eq i32 %1, 0 ; [#uses=1] + br i1 %2, label %return, label %bb.nph + +bb.nph: ; preds = %entry + %3 = getelementptr %"struct.clang::Action"* %Actions, i64 0, i32 0, i32 0 ; [#uses=1] + %mrv_gep = bitcast %"struct.clang::ActionBase::ActionResult<0u>"* %0 to i64* ; [#uses=1] + %mrv_gep1 = getelementptr %"struct.clang::ActionBase::ActionResult<0u>"* %0, i64 0, i32 1 ; [#uses=1] + %4 = bitcast i8* %mrv_gep1 to i64* ; [#uses=1] + %5 = getelementptr %"struct.clang::ActionBase::ActionResult<0u>"* %0, i64 0, i32 0 ; [#uses=1] + br label %bb + +bb: ; preds = %bb, %bb.nph + %Trial.01 = phi i32 [ 0, %bb.nph ], [ %12, %bb ] ; [#uses=1] + %Val_addr.02 = phi i8* [ %Val, %bb.nph ], [ %11, %bb ] ; [#uses=1] + %6 = load i32 (...)*** %3, align 8 ; [#uses=1] + %7 = getelementptr i32 (...)** %6, i64 70 ; [#uses=1] + %8 = load i32 (...)** %7, align 8 ; [#uses=1] + %9 = bitcast i32 (...)* %8 to { i64, i64 } (%"struct.clang::Action"*, i8*)* ; <{ i64, i64 } (%"struct.clang::Action"*, i8*)*> [#uses=1] + %10 = call { i64, i64 } %9(%"struct.clang::Action"* %Actions, i8* %Val_addr.02) nounwind ; <{ i64, i64 }> [#uses=2] + %mrv_gr = extractvalue { i64, i64 } %10, 0 ; [#uses=1] + store i64 %mrv_gr, i64* %mrv_gep + %mrv_gr2 = extractvalue { i64, i64 } %10, 1 ; [#uses=1] + store i64 %mrv_gr2, i64* %4 + %11 = load i8** %5, align 8 ; [#uses=1] + %12 = add i32 %Trial.01, 1 ; [#uses=2] + %13 = load i32* @NumTrials, align 4 ; [#uses=1] + %14 = icmp ult i32 %12, %13 ; [#uses=1] + br i1 %14, label %bb, label %return + +return: ; preds = %bb, %entry + ret void +} From evan.cheng at apple.com Mon Jan 26 12:55:10 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 26 Jan 2009 18:55:10 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63023 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Message-ID: <200901261855.n0QItA9o019891@zion.cs.uiuc.edu> Author: evancheng Date: Mon Jan 26 12:55:10 2009 New Revision: 63023 URL: http://llvm.org/viewvc/llvm-project?rev=63023&view=rev Log: Do not run aggressive loop unswitch at -O2. Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=63023&r1=63022&r2=63023&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Mon Jan 26 12:55:10 2009 @@ -438,7 +438,7 @@ PM->add(createReassociatePass()); // Reassociate expressions PM->add(createLoopRotatePass()); // Rotate Loop PM->add(createLICMPass()); // Hoist loop invariants - PM->add(createLoopUnswitchPass(optimize_size ? true : false)); + PM->add(createLoopUnswitchPass(optimize_size || optimize < 3)); PM->add(createLoopIndexSplitPass()); // Split loop index PM->add(createInstructionCombiningPass()); PM->add(createIndVarSimplifyPass()); // Canonicalize indvars From resistor at mac.com Mon Jan 26 13:12:07 2009 From: resistor at mac.com (Owen Anderson) Date: Mon, 26 Jan 2009 19:12:07 -0000 Subject: [llvm-commits] [llvm] r63025 - /llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Message-ID: <200901261912.n0QJC7tA020667@zion.cs.uiuc.edu> Author: resistor Date: Mon Jan 26 13:12:06 2009 New Revision: 63025 URL: http://llvm.org/viewvc/llvm-project?rev=63025&view=rev Log: Fix an issue where LiveIntervals was trying to be smart about removing kill markers, and ended up foiling the interval reconstruction. This allows us to turn on reconstruction in the pre alloc splitter, which fixes a number of miscompilations. Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=63025&r1=63024&r2=63025&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original) +++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Mon Jan 26 13:12:06 2009 @@ -748,12 +748,12 @@ ret = PerformPHIConstruction(walker, MBB, LI, Visited, Defs, Uses, NewVNs, LiveOut, Phis, false, true); + LI->addRange(LiveRange(UseIndex, EndIndex+1, ret)); + // FIXME: Need to set kills properly for inter-block stuff. if (LI->isKill(ret, UseIndex)) LI->removeKill(ret, UseIndex); if (intrablock) LI->addKill(ret, EndIndex); - - LI->addRange(LiveRange(UseIndex, EndIndex+1, ret)); } else if (ContainsDefs && ContainsUses){ SmallPtrSet& BlockDefs = Defs[MBB]; SmallPtrSet& BlockUses = Uses[MBB]; @@ -805,13 +805,13 @@ ret = PerformPHIConstruction(walker, MBB, LI, Visited, Defs, Uses, NewVNs, LiveOut, Phis, false, true); + LI->addRange(LiveRange(StartIndex, EndIndex+1, ret)); + if (foundUse && LI->isKill(ret, StartIndex)) LI->removeKill(ret, StartIndex); if (intrablock) { LI->addKill(ret, EndIndex); } - - LI->addRange(LiveRange(StartIndex, EndIndex+1, ret)); } // Memoize results so we don't have to recompute them. @@ -1131,18 +1131,10 @@ TII->reMaterialize(MBB, RestorePt, vreg, DefMI); LIs->InsertMachineInstrInMaps(prior(RestorePt), RestoreIdx); - if (KillPt->getParent() == BarrierMBB) { - VNInfo* After = UpdateRegisterInterval(ValNo, LIs->getUseIndex(KillIdx)+1, - LIs->getDefIndex(RestoreIdx)); - - RenumberValno(After); - - ++NumSplits; - ++NumRemats; - return true; - } - - RepairLiveInterval(CurrLI, ValNo, DefMI, RestoreIdx); + ReconstructLiveInterval(CurrLI); + unsigned RematIdx = LIs->getInstructionIndex(prior(RestorePt)); + RematIdx = LiveIntervals::getDefIndex(RematIdx); + RenumberValno(CurrLI->findDefinedVNInfo(RematIdx)); ++NumSplits; ++NumRemats; @@ -1315,28 +1307,14 @@ MachineInstr *LoadMI = prior(RestorePt); LIs->InsertMachineInstrInMaps(LoadMI, RestoreIndex); - // If live interval is spilled in the same block as the barrier, just - // create a hole in the interval. - if (!DefMBB || - (SpillMI && SpillMI->getParent() == BarrierMBB)) { - // Update spill stack slot live interval. - UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1, - LIs->getDefIndex(RestoreIndex)); - - VNInfo* After = UpdateRegisterInterval(ValNo, - LIs->getUseIndex(SpillIndex)+1, - LIs->getDefIndex(RestoreIndex)); - RenumberValno(After); - - ++NumSplits; - return true; - } - // Update spill stack slot live interval. UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1, LIs->getDefIndex(RestoreIndex)); - RepairLiveInterval(CurrLI, ValNo, DefMI, RestoreIndex); + ReconstructLiveInterval(CurrLI); + unsigned RestoreIdx = LIs->getInstructionIndex(prior(RestorePt)); + RestoreIdx = LiveIntervals::getDefIndex(RestoreIdx); + RenumberValno(CurrLI->findDefinedVNInfo(RestoreIdx)); ++NumSplits; return true; From resistor at mac.com Mon Jan 26 13:18:06 2009 From: resistor at mac.com (Owen Anderson) Date: Mon, 26 Jan 2009 19:18:06 -0000 Subject: [llvm-commits] [llvm] r63026 - /llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Message-ID: <200901261918.n0QJI6Ot020919@zion.cs.uiuc.edu> Author: resistor Date: Mon Jan 26 13:18:06 2009 New Revision: 63026 URL: http://llvm.org/viewvc/llvm-project?rev=63026&view=rev Log: Get rid of a bunch of dead code now that interval reconstruction is enabled. Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=63026&r1=63025&r2=63026&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original) +++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Mon Jan 26 13:18:06 2009 @@ -139,26 +139,11 @@ void UpdateSpillSlotInterval(VNInfo*, unsigned, unsigned); - VNInfo* UpdateRegisterInterval(VNInfo*, unsigned, unsigned); - - bool ShrinkWrapToLastUse(MachineBasicBlock*, VNInfo*, - SmallVector&, - SmallPtrSet&); - - void ShrinkWrapLiveInterval(VNInfo*, MachineBasicBlock*, MachineBasicBlock*, - MachineBasicBlock*, SmallPtrSet&, - DenseMap >&, - DenseMap >&, - SmallVector&); - bool SplitRegLiveInterval(LiveInterval*); bool SplitRegLiveIntervals(const TargetRegisterClass **, SmallPtrSet&); - void RepairLiveInterval(LiveInterval* CurrLI, VNInfo* ValNo, - MachineInstr* DefMI, unsigned RestoreIdx); - bool createsNewJoin(LiveRange* LR, MachineBasicBlock* DefMBB, MachineBasicBlock* BarrierMBB); bool Rematerialize(unsigned vreg, VNInfo* ValNo, @@ -423,176 +408,6 @@ } } -/// UpdateRegisterInterval - Given the specified val# of the current live -/// interval is being split, and the spill and restore indices, update the live -/// interval accordingly. -VNInfo* -PreAllocSplitting::UpdateRegisterInterval(VNInfo *ValNo, unsigned SpillIndex, - unsigned RestoreIndex) { - assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB && - "Expect restore in the barrier mbb"); - - SmallVector, 4> Before; - SmallVector, 4> After; - SmallVector BeforeKills; - SmallVector AfterKills; - SmallPtrSet Processed; - - // First, let's figure out which parts of the live interval is now defined - // by the restore, which are defined by the original definition. - const LiveRange *LR = CurrLI->getLiveRangeContaining(RestoreIndex); - After.push_back(std::make_pair(RestoreIndex, LR->end)); - if (CurrLI->isKill(ValNo, LR->end)) - AfterKills.push_back(LR->end); - - assert(LR->contains(SpillIndex)); - if (SpillIndex > LR->start) { - Before.push_back(std::make_pair(LR->start, SpillIndex)); - BeforeKills.push_back(SpillIndex); - } - Processed.insert(LR); - - // Start from the restore mbb, figure out what part of the live interval - // are defined by the restore. - SmallVector WorkList; - MachineBasicBlock *MBB = BarrierMBB; - for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), - SE = MBB->succ_end(); SI != SE; ++SI) - WorkList.push_back(*SI); - - SmallPtrSet ProcessedBlocks; - ProcessedBlocks.insert(MBB); - - while (!WorkList.empty()) { - MBB = WorkList.back(); - WorkList.pop_back(); - unsigned Idx = LIs->getMBBStartIdx(MBB); - LR = CurrLI->getLiveRangeContaining(Idx); - if (LR && LR->valno == ValNo && !Processed.count(LR)) { - After.push_back(std::make_pair(LR->start, LR->end)); - if (CurrLI->isKill(ValNo, LR->end)) - AfterKills.push_back(LR->end); - Idx = LIs->getMBBEndIdx(MBB); - if (LR->end > Idx) { - // Live range extend beyond at least one mbb. Let's see what other - // mbbs it reaches. - LIs->findReachableMBBs(LR->start, LR->end, WorkList); - } - Processed.insert(LR); - } - - ProcessedBlocks.insert(MBB); - if (LR) - for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), - SE = MBB->succ_end(); SI != SE; ++SI) - if (!ProcessedBlocks.count(*SI)) - WorkList.push_back(*SI); - } - - for (LiveInterval::iterator I = CurrLI->begin(), E = CurrLI->end(); - I != E; ++I) { - LiveRange *LR = I; - if (LR->valno == ValNo && !Processed.count(LR)) { - Before.push_back(std::make_pair(LR->start, LR->end)); - if (CurrLI->isKill(ValNo, LR->end)) - BeforeKills.push_back(LR->end); - } - } - - // Now create new val#s to represent the live ranges defined by the old def - // those defined by the restore. - unsigned AfterDef = ValNo->def; - MachineInstr *AfterCopy = ValNo->copy; - bool HasPHIKill = ValNo->hasPHIKill; - CurrLI->removeValNo(ValNo); - VNInfo *BValNo = (Before.empty()) - ? NULL - : CurrLI->getNextValue(AfterDef, AfterCopy, LIs->getVNInfoAllocator()); - if (BValNo) - CurrLI->addKills(BValNo, BeforeKills); - - VNInfo *AValNo = (After.empty()) - ? NULL - : CurrLI->getNextValue(RestoreIndex, 0, LIs->getVNInfoAllocator()); - if (AValNo) { - AValNo->hasPHIKill = HasPHIKill; - CurrLI->addKills(AValNo, AfterKills); - } - - for (unsigned i = 0, e = Before.size(); i != e; ++i) { - unsigned Start = Before[i].first; - unsigned End = Before[i].second; - CurrLI->addRange(LiveRange(Start, End, BValNo)); - } - for (unsigned i = 0, e = After.size(); i != e; ++i) { - unsigned Start = After[i].first; - unsigned End = After[i].second; - CurrLI->addRange(LiveRange(Start, End, AValNo)); - } - - return AValNo; -} - -/// ShrinkWrapToLastUse - There are uses of the current live interval in the -/// given block, shrink wrap the live interval to the last use (i.e. remove -/// from last use to the end of the mbb). In case mbb is the where the barrier -/// is, remove from the last use to the barrier. -bool -PreAllocSplitting::ShrinkWrapToLastUse(MachineBasicBlock *MBB, VNInfo *ValNo, - SmallVector &Uses, - SmallPtrSet &UseMIs) { - MachineOperand *LastMO = 0; - MachineInstr *LastMI = 0; - if (MBB != BarrierMBB && Uses.size() == 1) { - // Single use, no need to traverse the block. We can't assume this for the - // barrier bb though since the use is probably below the barrier. - LastMO = Uses[0]; - LastMI = LastMO->getParent(); - } else { - MachineBasicBlock::iterator MEE = MBB->begin(); - MachineBasicBlock::iterator MII; - if (MBB == BarrierMBB) - MII = Barrier; - else - MII = MBB->end(); - while (MII != MEE) { - --MII; - MachineInstr *UseMI = &*MII; - if (!UseMIs.count(UseMI)) - continue; - for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = UseMI->getOperand(i); - if (MO.isReg() && MO.getReg() == CurrLI->reg) { - LastMO = &MO; - break; - } - } - LastMI = UseMI; - break; - } - } - - // Cut off live range from last use (or beginning of the mbb if there - // are no uses in it) to the end of the mbb. - unsigned RangeStart, RangeEnd = LIs->getMBBEndIdx(MBB)+1; - if (LastMI) { - RangeStart = LIs->getUseIndex(LIs->getInstructionIndex(LastMI))+1; - assert(!LastMO->isKill() && "Last use already terminates the interval?"); - LastMO->setIsKill(); - } else { - assert(MBB == BarrierMBB); - RangeStart = LIs->getMBBStartIdx(MBB); - } - if (MBB == BarrierMBB) - RangeEnd = LIs->getUseIndex(BarrierIdx)+1; - CurrLI->removeRange(RangeStart, RangeEnd); - if (LastMI) - CurrLI->addKill(ValNo, RangeStart); - - // Return true if the last use becomes a new kill. - return LastMI; -} - /// PerformPHIConstruction - From properly set up use and def lists, use a PHI /// construction algorithm to compute the ranges and valnos for an interval. VNInfo* PreAllocSplitting::PerformPHIConstruction( @@ -890,142 +705,6 @@ } } -/// ShrinkWrapLiveInterval - Recursively traverse the predecessor -/// chain to find the new 'kills' and shrink wrap the live interval to the -/// new kill indices. -void -PreAllocSplitting::ShrinkWrapLiveInterval(VNInfo *ValNo, MachineBasicBlock *MBB, - MachineBasicBlock *SuccMBB, MachineBasicBlock *DefMBB, - SmallPtrSet &Visited, - DenseMap > &Uses, - DenseMap > &UseMIs, - SmallVector &UseMBBs) { - if (Visited.count(MBB)) - return; - - // If live interval is live in another successor path, then we can't process - // this block. But we may able to do so after all the successors have been - // processed. - if (MBB != BarrierMBB) { - for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), - SE = MBB->succ_end(); SI != SE; ++SI) { - MachineBasicBlock *SMBB = *SI; - if (SMBB == SuccMBB) - continue; - if (CurrLI->liveAt(LIs->getMBBStartIdx(SMBB))) - return; - } - } - - Visited.insert(MBB); - - DenseMap >::iterator - UMII = Uses.find(MBB); - if (UMII != Uses.end()) { - // At least one use in this mbb, lets look for the kill. - DenseMap >::iterator - UMII2 = UseMIs.find(MBB); - if (ShrinkWrapToLastUse(MBB, ValNo, UMII->second, UMII2->second)) - // Found a kill, shrink wrapping of this path ends here. - return; - } else if (MBB == DefMBB) { - // There are no uses after the def. - MachineInstr *DefMI = LIs->getInstructionFromIndex(ValNo->def); - if (UseMBBs.empty()) { - // The only use must be below barrier in the barrier block. It's safe to - // remove the def. - LIs->RemoveMachineInstrFromMaps(DefMI); - DefMI->eraseFromParent(); - CurrLI->removeRange(ValNo->def, LIs->getMBBEndIdx(MBB)+1); - } - } else if (MBB == BarrierMBB) { - // Remove entire live range from start of mbb to barrier. - CurrLI->removeRange(LIs->getMBBStartIdx(MBB), - LIs->getUseIndex(BarrierIdx)+1); - } else { - // Remove entire live range of the mbb out of the live interval. - CurrLI->removeRange(LIs->getMBBStartIdx(MBB), LIs->getMBBEndIdx(MBB)+1); - } - - if (MBB == DefMBB) - // Reached the def mbb, stop traversing this path further. - return; - - // Traverse the pathes up the predecessor chains further. - for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(), - PE = MBB->pred_end(); PI != PE; ++PI) { - MachineBasicBlock *Pred = *PI; - if (Pred == MBB) - continue; - if (Pred == DefMBB && ValNo->hasPHIKill) - // Pred is the def bb and the def reaches other val#s, we must - // allow the value to be live out of the bb. - continue; - if (!CurrLI->liveAt(LIs->getMBBEndIdx(Pred)-1)) - return; - ShrinkWrapLiveInterval(ValNo, Pred, MBB, DefMBB, Visited, - Uses, UseMIs, UseMBBs); - } - - return; -} - - -void PreAllocSplitting::RepairLiveInterval(LiveInterval* CurrLI, - VNInfo* ValNo, - MachineInstr* DefMI, - unsigned RestoreIdx) { - // Shrink wrap the live interval by walking up the CFG and find the - // new kills. - // Now let's find all the uses of the val#. - DenseMap > Uses; - DenseMap > UseMIs; - SmallPtrSet Seen; - SmallVector UseMBBs; - for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(CurrLI->reg), - UE = MRI->use_end(); UI != UE; ++UI) { - MachineOperand &UseMO = UI.getOperand(); - MachineInstr *UseMI = UseMO.getParent(); - unsigned UseIdx = LIs->getInstructionIndex(UseMI); - LiveInterval::iterator ULR = CurrLI->FindLiveRangeContaining(UseIdx); - if (ULR->valno != ValNo) - continue; - MachineBasicBlock *UseMBB = UseMI->getParent(); - // Remember which other mbb's use this val#. - if (Seen.insert(UseMBB) && UseMBB != BarrierMBB) - UseMBBs.push_back(UseMBB); - DenseMap >::iterator - UMII = Uses.find(UseMBB); - if (UMII != Uses.end()) { - DenseMap >::iterator - UMII2 = UseMIs.find(UseMBB); - UMII->second.push_back(&UseMO); - UMII2->second.insert(UseMI); - } else { - SmallVector Ops; - Ops.push_back(&UseMO); - Uses.insert(std::make_pair(UseMBB, Ops)); - SmallPtrSet MIs; - MIs.insert(UseMI); - UseMIs.insert(std::make_pair(UseMBB, MIs)); - } - } - - // Walk up the predecessor chains. - SmallPtrSet Visited; - ShrinkWrapLiveInterval(ValNo, BarrierMBB, NULL, DefMI->getParent(), Visited, - Uses, UseMIs, UseMBBs); - - // Remove live range from barrier to the restore. FIXME: Find a better - // point to re-start the live interval. - VNInfo* AfterValNo = UpdateRegisterInterval(ValNo, - LIs->getUseIndex(BarrierIdx)+1, - LIs->getDefIndex(RestoreIdx)); - - // Attempt to renumber the new valno into a new vreg. - RenumberValno(AfterValNo); -} - /// RenumberValno - Split the given valno out into a new vreg, allowing it to /// be allocated to a different register. This function creates a new vreg, /// copies the valno and its live ranges over to the new vreg's interval, From asl at math.spbu.ru Mon Jan 26 13:26:02 2009 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Mon, 26 Jan 2009 19:26:02 -0000 Subject: [llvm-commits] [llvm] r63027 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Message-ID: <200901261926.n0QJQ2dt021198@zion.cs.uiuc.edu> Author: asl Date: Mon Jan 26 13:26:01 2009 New Revision: 63027 URL: http://llvm.org/viewvc/llvm-project?rev=63027&view=rev Log: During bittest switch lowering emit shift in the test block, which should (theoretically) allow us to generate more efficient code. We don't do this now though :) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63027&r1=63026&r2=63027&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon Jan 26 13:26:01 2009 @@ -1416,14 +1416,8 @@ else ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); - // Make desired shift - SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), - DAG.getConstant(1, TLI.getPointerTy()), - ShiftOp); - - unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); - SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal); - B.Reg = SwitchReg; + B.Reg = FuncInfo.MakeReg(TLI.getShiftAmountTy()); + SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), B.Reg, ShiftOp); // Set NextBlock to be the MBB immediately after the current one, if any. // This is used to avoid emitting unnecessary branches to the next block. @@ -1453,10 +1447,14 @@ void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, unsigned Reg, BitTestCase &B) { - // Emit bit tests and jumps - SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg, - TLI.getPointerTy()); + // Make desired shift + SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), Reg, + TLI.getShiftAmountTy()); + SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), + DAG.getConstant(1, TLI.getPointerTy()), + ShiftOp); + // Emit bit tests and jumps SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal, DAG.getConstant(B.Mask, TLI.getPointerTy())); SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp.getValueType()), From gohman at apple.com Mon Jan 26 14:27:11 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 26 Jan 2009 20:27:11 -0000 Subject: [llvm-commits] [llvm] r63037 - /llvm/trunk/include/llvm/CodeGen/LiveStackAnalysis.h Message-ID: <200901262027.n0QKRBrS023522@zion.cs.uiuc.edu> Author: djg Date: Mon Jan 26 14:27:11 2009 New Revision: 63037 URL: http://llvm.org/viewvc/llvm-project?rev=63037&view=rev Log: Fix the name of an argument. Modified: llvm/trunk/include/llvm/CodeGen/LiveStackAnalysis.h Modified: llvm/trunk/include/llvm/CodeGen/LiveStackAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveStackAnalysis.h?rev=63037&r1=63036&r2=63037&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveStackAnalysis.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveStackAnalysis.h Mon Jan 26 14:27:11 2009 @@ -64,8 +64,8 @@ return I->second; } - bool hasInterval(unsigned reg) const { - return s2iMap.count(reg); + bool hasInterval(unsigned Slot) const { + return s2iMap.count(Slot); } BumpPtrAllocator& getVNInfoAllocator() { return VNInfoAllocator; } From isanbard at gmail.com Mon Jan 26 15:27:03 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 26 Jan 2009 21:27:03 -0000 Subject: [llvm-commits] [llvm] r63040 - /llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Message-ID: <200901262127.n0QLR3pY025810@zion.cs.uiuc.edu> Author: void Date: Mon Jan 26 15:27:03 2009 New Revision: 63040 URL: http://llvm.org/viewvc/llvm-project?rev=63040&view=rev Log: Temporarily revert r63025 until the testsuite failures can be fixed. Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=63040&r1=63039&r2=63040&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original) +++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Mon Jan 26 15:27:03 2009 @@ -563,12 +563,12 @@ ret = PerformPHIConstruction(walker, MBB, LI, Visited, Defs, Uses, NewVNs, LiveOut, Phis, false, true); - LI->addRange(LiveRange(UseIndex, EndIndex+1, ret)); - // FIXME: Need to set kills properly for inter-block stuff. if (LI->isKill(ret, UseIndex)) LI->removeKill(ret, UseIndex); if (intrablock) LI->addKill(ret, EndIndex); + + LI->addRange(LiveRange(UseIndex, EndIndex+1, ret)); } else if (ContainsDefs && ContainsUses){ SmallPtrSet& BlockDefs = Defs[MBB]; SmallPtrSet& BlockUses = Uses[MBB]; @@ -620,13 +620,13 @@ ret = PerformPHIConstruction(walker, MBB, LI, Visited, Defs, Uses, NewVNs, LiveOut, Phis, false, true); - LI->addRange(LiveRange(StartIndex, EndIndex+1, ret)); - if (foundUse && LI->isKill(ret, StartIndex)) LI->removeKill(ret, StartIndex); if (intrablock) { LI->addKill(ret, EndIndex); } + + LI->addRange(LiveRange(StartIndex, EndIndex+1, ret)); } // Memoize results so we don't have to recompute them. @@ -810,10 +810,18 @@ TII->reMaterialize(MBB, RestorePt, vreg, DefMI); LIs->InsertMachineInstrInMaps(prior(RestorePt), RestoreIdx); - ReconstructLiveInterval(CurrLI); - unsigned RematIdx = LIs->getInstructionIndex(prior(RestorePt)); - RematIdx = LiveIntervals::getDefIndex(RematIdx); - RenumberValno(CurrLI->findDefinedVNInfo(RematIdx)); + if (KillPt->getParent() == BarrierMBB) { + VNInfo* After = UpdateRegisterInterval(ValNo, LIs->getUseIndex(KillIdx)+1, + LIs->getDefIndex(RestoreIdx)); + + RenumberValno(After); + + ++NumSplits; + ++NumRemats; + return true; + } + + RepairLiveInterval(CurrLI, ValNo, DefMI, RestoreIdx); ++NumSplits; ++NumRemats; @@ -986,14 +994,28 @@ MachineInstr *LoadMI = prior(RestorePt); LIs->InsertMachineInstrInMaps(LoadMI, RestoreIndex); + // If live interval is spilled in the same block as the barrier, just + // create a hole in the interval. + if (!DefMBB || + (SpillMI && SpillMI->getParent() == BarrierMBB)) { + // Update spill stack slot live interval. + UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1, + LIs->getDefIndex(RestoreIndex)); + + VNInfo* After = UpdateRegisterInterval(ValNo, + LIs->getUseIndex(SpillIndex)+1, + LIs->getDefIndex(RestoreIndex)); + RenumberValno(After); + + ++NumSplits; + return true; + } + // Update spill stack slot live interval. UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1, LIs->getDefIndex(RestoreIndex)); - ReconstructLiveInterval(CurrLI); - unsigned RestoreIdx = LIs->getInstructionIndex(prior(RestorePt)); - RestoreIdx = LiveIntervals::getDefIndex(RestoreIdx); - RenumberValno(CurrLI->findDefinedVNInfo(RestoreIdx)); + RepairLiveInterval(CurrLI, ValNo, DefMI, RestoreIndex); ++NumSplits; return true; From isanbard at gmail.com Mon Jan 26 15:30:17 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 26 Jan 2009 21:30:17 -0000 Subject: [llvm-commits] [llvm] r63041 - /llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Message-ID: <200901262130.n0QLUHQ2025926@zion.cs.uiuc.edu> Author: void Date: Mon Jan 26 15:30:17 2009 New Revision: 63041 URL: http://llvm.org/viewvc/llvm-project?rev=63041&view=rev Log: Also revert r63206 Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=63041&r1=63040&r2=63041&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original) +++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Mon Jan 26 15:30:17 2009 @@ -139,11 +139,26 @@ void UpdateSpillSlotInterval(VNInfo*, unsigned, unsigned); + VNInfo* UpdateRegisterInterval(VNInfo*, unsigned, unsigned); + + bool ShrinkWrapToLastUse(MachineBasicBlock*, VNInfo*, + SmallVector&, + SmallPtrSet&); + + void ShrinkWrapLiveInterval(VNInfo*, MachineBasicBlock*, MachineBasicBlock*, + MachineBasicBlock*, SmallPtrSet&, + DenseMap >&, + DenseMap >&, + SmallVector&); + bool SplitRegLiveInterval(LiveInterval*); bool SplitRegLiveIntervals(const TargetRegisterClass **, SmallPtrSet&); + void RepairLiveInterval(LiveInterval* CurrLI, VNInfo* ValNo, + MachineInstr* DefMI, unsigned RestoreIdx); + bool createsNewJoin(LiveRange* LR, MachineBasicBlock* DefMBB, MachineBasicBlock* BarrierMBB); bool Rematerialize(unsigned vreg, VNInfo* ValNo, @@ -408,6 +423,176 @@ } } +/// UpdateRegisterInterval - Given the specified val# of the current live +/// interval is being split, and the spill and restore indices, update the live +/// interval accordingly. +VNInfo* +PreAllocSplitting::UpdateRegisterInterval(VNInfo *ValNo, unsigned SpillIndex, + unsigned RestoreIndex) { + assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB && + "Expect restore in the barrier mbb"); + + SmallVector, 4> Before; + SmallVector, 4> After; + SmallVector BeforeKills; + SmallVector AfterKills; + SmallPtrSet Processed; + + // First, let's figure out which parts of the live interval is now defined + // by the restore, which are defined by the original definition. + const LiveRange *LR = CurrLI->getLiveRangeContaining(RestoreIndex); + After.push_back(std::make_pair(RestoreIndex, LR->end)); + if (CurrLI->isKill(ValNo, LR->end)) + AfterKills.push_back(LR->end); + + assert(LR->contains(SpillIndex)); + if (SpillIndex > LR->start) { + Before.push_back(std::make_pair(LR->start, SpillIndex)); + BeforeKills.push_back(SpillIndex); + } + Processed.insert(LR); + + // Start from the restore mbb, figure out what part of the live interval + // are defined by the restore. + SmallVector WorkList; + MachineBasicBlock *MBB = BarrierMBB; + for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), + SE = MBB->succ_end(); SI != SE; ++SI) + WorkList.push_back(*SI); + + SmallPtrSet ProcessedBlocks; + ProcessedBlocks.insert(MBB); + + while (!WorkList.empty()) { + MBB = WorkList.back(); + WorkList.pop_back(); + unsigned Idx = LIs->getMBBStartIdx(MBB); + LR = CurrLI->getLiveRangeContaining(Idx); + if (LR && LR->valno == ValNo && !Processed.count(LR)) { + After.push_back(std::make_pair(LR->start, LR->end)); + if (CurrLI->isKill(ValNo, LR->end)) + AfterKills.push_back(LR->end); + Idx = LIs->getMBBEndIdx(MBB); + if (LR->end > Idx) { + // Live range extend beyond at least one mbb. Let's see what other + // mbbs it reaches. + LIs->findReachableMBBs(LR->start, LR->end, WorkList); + } + Processed.insert(LR); + } + + ProcessedBlocks.insert(MBB); + if (LR) + for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), + SE = MBB->succ_end(); SI != SE; ++SI) + if (!ProcessedBlocks.count(*SI)) + WorkList.push_back(*SI); + } + + for (LiveInterval::iterator I = CurrLI->begin(), E = CurrLI->end(); + I != E; ++I) { + LiveRange *LR = I; + if (LR->valno == ValNo && !Processed.count(LR)) { + Before.push_back(std::make_pair(LR->start, LR->end)); + if (CurrLI->isKill(ValNo, LR->end)) + BeforeKills.push_back(LR->end); + } + } + + // Now create new val#s to represent the live ranges defined by the old def + // those defined by the restore. + unsigned AfterDef = ValNo->def; + MachineInstr *AfterCopy = ValNo->copy; + bool HasPHIKill = ValNo->hasPHIKill; + CurrLI->removeValNo(ValNo); + VNInfo *BValNo = (Before.empty()) + ? NULL + : CurrLI->getNextValue(AfterDef, AfterCopy, LIs->getVNInfoAllocator()); + if (BValNo) + CurrLI->addKills(BValNo, BeforeKills); + + VNInfo *AValNo = (After.empty()) + ? NULL + : CurrLI->getNextValue(RestoreIndex, 0, LIs->getVNInfoAllocator()); + if (AValNo) { + AValNo->hasPHIKill = HasPHIKill; + CurrLI->addKills(AValNo, AfterKills); + } + + for (unsigned i = 0, e = Before.size(); i != e; ++i) { + unsigned Start = Before[i].first; + unsigned End = Before[i].second; + CurrLI->addRange(LiveRange(Start, End, BValNo)); + } + for (unsigned i = 0, e = After.size(); i != e; ++i) { + unsigned Start = After[i].first; + unsigned End = After[i].second; + CurrLI->addRange(LiveRange(Start, End, AValNo)); + } + + return AValNo; +} + +/// ShrinkWrapToLastUse - There are uses of the current live interval in the +/// given block, shrink wrap the live interval to the last use (i.e. remove +/// from last use to the end of the mbb). In case mbb is the where the barrier +/// is, remove from the last use to the barrier. +bool +PreAllocSplitting::ShrinkWrapToLastUse(MachineBasicBlock *MBB, VNInfo *ValNo, + SmallVector &Uses, + SmallPtrSet &UseMIs) { + MachineOperand *LastMO = 0; + MachineInstr *LastMI = 0; + if (MBB != BarrierMBB && Uses.size() == 1) { + // Single use, no need to traverse the block. We can't assume this for the + // barrier bb though since the use is probably below the barrier. + LastMO = Uses[0]; + LastMI = LastMO->getParent(); + } else { + MachineBasicBlock::iterator MEE = MBB->begin(); + MachineBasicBlock::iterator MII; + if (MBB == BarrierMBB) + MII = Barrier; + else + MII = MBB->end(); + while (MII != MEE) { + --MII; + MachineInstr *UseMI = &*MII; + if (!UseMIs.count(UseMI)) + continue; + for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = UseMI->getOperand(i); + if (MO.isReg() && MO.getReg() == CurrLI->reg) { + LastMO = &MO; + break; + } + } + LastMI = UseMI; + break; + } + } + + // Cut off live range from last use (or beginning of the mbb if there + // are no uses in it) to the end of the mbb. + unsigned RangeStart, RangeEnd = LIs->getMBBEndIdx(MBB)+1; + if (LastMI) { + RangeStart = LIs->getUseIndex(LIs->getInstructionIndex(LastMI))+1; + assert(!LastMO->isKill() && "Last use already terminates the interval?"); + LastMO->setIsKill(); + } else { + assert(MBB == BarrierMBB); + RangeStart = LIs->getMBBStartIdx(MBB); + } + if (MBB == BarrierMBB) + RangeEnd = LIs->getUseIndex(BarrierIdx)+1; + CurrLI->removeRange(RangeStart, RangeEnd); + if (LastMI) + CurrLI->addKill(ValNo, RangeStart); + + // Return true if the last use becomes a new kill. + return LastMI; +} + /// PerformPHIConstruction - From properly set up use and def lists, use a PHI /// construction algorithm to compute the ranges and valnos for an interval. VNInfo* PreAllocSplitting::PerformPHIConstruction( @@ -705,6 +890,142 @@ } } +/// ShrinkWrapLiveInterval - Recursively traverse the predecessor +/// chain to find the new 'kills' and shrink wrap the live interval to the +/// new kill indices. +void +PreAllocSplitting::ShrinkWrapLiveInterval(VNInfo *ValNo, MachineBasicBlock *MBB, + MachineBasicBlock *SuccMBB, MachineBasicBlock *DefMBB, + SmallPtrSet &Visited, + DenseMap > &Uses, + DenseMap > &UseMIs, + SmallVector &UseMBBs) { + if (Visited.count(MBB)) + return; + + // If live interval is live in another successor path, then we can't process + // this block. But we may able to do so after all the successors have been + // processed. + if (MBB != BarrierMBB) { + for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), + SE = MBB->succ_end(); SI != SE; ++SI) { + MachineBasicBlock *SMBB = *SI; + if (SMBB == SuccMBB) + continue; + if (CurrLI->liveAt(LIs->getMBBStartIdx(SMBB))) + return; + } + } + + Visited.insert(MBB); + + DenseMap >::iterator + UMII = Uses.find(MBB); + if (UMII != Uses.end()) { + // At least one use in this mbb, lets look for the kill. + DenseMap >::iterator + UMII2 = UseMIs.find(MBB); + if (ShrinkWrapToLastUse(MBB, ValNo, UMII->second, UMII2->second)) + // Found a kill, shrink wrapping of this path ends here. + return; + } else if (MBB == DefMBB) { + // There are no uses after the def. + MachineInstr *DefMI = LIs->getInstructionFromIndex(ValNo->def); + if (UseMBBs.empty()) { + // The only use must be below barrier in the barrier block. It's safe to + // remove the def. + LIs->RemoveMachineInstrFromMaps(DefMI); + DefMI->eraseFromParent(); + CurrLI->removeRange(ValNo->def, LIs->getMBBEndIdx(MBB)+1); + } + } else if (MBB == BarrierMBB) { + // Remove entire live range from start of mbb to barrier. + CurrLI->removeRange(LIs->getMBBStartIdx(MBB), + LIs->getUseIndex(BarrierIdx)+1); + } else { + // Remove entire live range of the mbb out of the live interval. + CurrLI->removeRange(LIs->getMBBStartIdx(MBB), LIs->getMBBEndIdx(MBB)+1); + } + + if (MBB == DefMBB) + // Reached the def mbb, stop traversing this path further. + return; + + // Traverse the pathes up the predecessor chains further. + for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(), + PE = MBB->pred_end(); PI != PE; ++PI) { + MachineBasicBlock *Pred = *PI; + if (Pred == MBB) + continue; + if (Pred == DefMBB && ValNo->hasPHIKill) + // Pred is the def bb and the def reaches other val#s, we must + // allow the value to be live out of the bb. + continue; + if (!CurrLI->liveAt(LIs->getMBBEndIdx(Pred)-1)) + return; + ShrinkWrapLiveInterval(ValNo, Pred, MBB, DefMBB, Visited, + Uses, UseMIs, UseMBBs); + } + + return; +} + + +void PreAllocSplitting::RepairLiveInterval(LiveInterval* CurrLI, + VNInfo* ValNo, + MachineInstr* DefMI, + unsigned RestoreIdx) { + // Shrink wrap the live interval by walking up the CFG and find the + // new kills. + // Now let's find all the uses of the val#. + DenseMap > Uses; + DenseMap > UseMIs; + SmallPtrSet Seen; + SmallVector UseMBBs; + for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(CurrLI->reg), + UE = MRI->use_end(); UI != UE; ++UI) { + MachineOperand &UseMO = UI.getOperand(); + MachineInstr *UseMI = UseMO.getParent(); + unsigned UseIdx = LIs->getInstructionIndex(UseMI); + LiveInterval::iterator ULR = CurrLI->FindLiveRangeContaining(UseIdx); + if (ULR->valno != ValNo) + continue; + MachineBasicBlock *UseMBB = UseMI->getParent(); + // Remember which other mbb's use this val#. + if (Seen.insert(UseMBB) && UseMBB != BarrierMBB) + UseMBBs.push_back(UseMBB); + DenseMap >::iterator + UMII = Uses.find(UseMBB); + if (UMII != Uses.end()) { + DenseMap >::iterator + UMII2 = UseMIs.find(UseMBB); + UMII->second.push_back(&UseMO); + UMII2->second.insert(UseMI); + } else { + SmallVector Ops; + Ops.push_back(&UseMO); + Uses.insert(std::make_pair(UseMBB, Ops)); + SmallPtrSet MIs; + MIs.insert(UseMI); + UseMIs.insert(std::make_pair(UseMBB, MIs)); + } + } + + // Walk up the predecessor chains. + SmallPtrSet Visited; + ShrinkWrapLiveInterval(ValNo, BarrierMBB, NULL, DefMI->getParent(), Visited, + Uses, UseMIs, UseMBBs); + + // Remove live range from barrier to the restore. FIXME: Find a better + // point to re-start the live interval. + VNInfo* AfterValNo = UpdateRegisterInterval(ValNo, + LIs->getUseIndex(BarrierIdx)+1, + LIs->getDefIndex(RestoreIdx)); + + // Attempt to renumber the new valno into a new vreg. + RenumberValno(AfterValNo); +} + /// RenumberValno - Split the given valno out into a new vreg, allowing it to /// be allocated to a different register. This function creates a new vreg, /// copies the valno and its live ranges over to the new vreg's interval, From gohman at apple.com Mon Jan 26 15:36:32 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 26 Jan 2009 21:36:32 -0000 Subject: [llvm-commits] [llvm] r63042 - in /llvm/trunk/test/CodeGen/X86: dag-rauw-cse.ll pr3018.ll Message-ID: <200901262136.n0QLaW8p026161@zion.cs.uiuc.edu> Author: djg Date: Mon Jan 26 15:36:31 2009 New Revision: 63042 URL: http://llvm.org/viewvc/llvm-project?rev=63042&view=rev Log: At Nick Lewycky's request, rename this test with a more informative name. Added: llvm/trunk/test/CodeGen/X86/dag-rauw-cse.ll - copied unchanged from r63041, llvm/trunk/test/CodeGen/X86/pr3018.ll Removed: llvm/trunk/test/CodeGen/X86/pr3018.ll Removed: llvm/trunk/test/CodeGen/X86/pr3018.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr3018.ll?rev=63041&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pr3018.ll (original) +++ llvm/trunk/test/CodeGen/X86/pr3018.ll (removed) @@ -1,9 +0,0 @@ -; RUN: llvm-as < %s | llc -march=x86 | grep {orl \$1} -; PR3018 - -define i32 @test(i32 %A) nounwind { - %B = or i32 %A, 1 - %C = or i32 %B, 1 - %D = and i32 %C, 7057 - ret i32 %D -} From gohman at apple.com Mon Jan 26 15:41:10 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 26 Jan 2009 13:41:10 -0800 Subject: [llvm-commits] [llvm] r63008 - in /llvm/trunk: include/llvm/CodeGen/DebugLoc.h include/llvm/CodeGen/MachineFunction.h lib/CodeGen/MachineFunction.cpp In-Reply-To: <200901260741.n0Q7fnOn020226@zion.cs.uiuc.edu> References: <200901260741.n0Q7fnOn020226@zion.cs.uiuc.edu> Message-ID: <3CF8B982-5512-4854-BCA4-847689438D80@apple.com> On Jan 25, 2009, at 11:41 PM, Evan Cheng wrote: > > + // NumDebugLocations - Size of the DebugLocations vector. > + unsigned NumDebugLocations; > + > + // DebugLocations - A vector of unique DebugLocTuple's. > + // > + std::vector DebugLocations; Hi Evan, std::vector keeps track of its own size. Is it necessary to keep a separate count of the number of elements? Dan From kremenek at apple.com Mon Jan 26 15:42:04 2009 From: kremenek at apple.com (Ted Kremenek) Date: Mon, 26 Jan 2009 21:42:04 -0000 Subject: [llvm-commits] [llvm] r63044 - in /llvm/trunk: include/llvm/Support/raw_ostream.h lib/Support/raw_ostream.cpp Message-ID: <200901262142.n0QLg4XL026404@zion.cs.uiuc.edu> Author: kremenek Date: Mon Jan 26 15:42:04 2009 New Revision: 63044 URL: http://llvm.org/viewvc/llvm-project?rev=63044&view=rev Log: Add method raw_fd_ostream::seek() for random access within a file. Modified: llvm/trunk/include/llvm/Support/raw_ostream.h llvm/trunk/lib/Support/raw_ostream.cpp Modified: llvm/trunk/include/llvm/Support/raw_ostream.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/raw_ostream.h?rev=63044&r1=63043&r2=63044&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/raw_ostream.h (original) +++ llvm/trunk/include/llvm/Support/raw_ostream.h Mon Jan 26 15:42:04 2009 @@ -181,7 +181,11 @@ /// tell - Return the current offset with the file. uint64_t tell() { return pos + (OutBufCur - OutBufStart); - } + } + + /// seek - Flushes the stream and repositions the underlying file descriptor + /// positition to the offset specified from the beginning of the file. + uint64_t seek(uint64_t off); }; /// raw_stdout_ostream - This is a stream that always prints to stdout. Modified: llvm/trunk/lib/Support/raw_ostream.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/raw_ostream.cpp?rev=63044&r1=63043&r2=63044&view=diff ============================================================================== --- llvm/trunk/lib/Support/raw_ostream.cpp (original) +++ llvm/trunk/lib/Support/raw_ostream.cpp Mon Jan 26 15:42:04 2009 @@ -255,6 +255,12 @@ FD = -1; } +uint64_t raw_fd_ostream::seek(uint64_t off) { + flush(); + pos = lseek(FD, off, SEEK_SET); + return pos; +} + //===----------------------------------------------------------------------===// // raw_stdout/err_ostream //===----------------------------------------------------------------------===// From isanbard at gmail.com Mon Jan 26 15:46:01 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 26 Jan 2009 21:46:01 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63046 - /llvm-gcc-4.2/trunk/build_gcc Message-ID: <200901262146.n0QLk1Om026554@zion.cs.uiuc.edu> Author: void Date: Mon Jan 26 15:46:01 2009 New Revision: 63046 URL: http://llvm.org/viewvc/llvm-project?rev=63046&view=rev Log: Change to help llvm-gcc build ARM executables. Modified: llvm-gcc-4.2/trunk/build_gcc Modified: llvm-gcc-4.2/trunk/build_gcc URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/build_gcc?rev=63046&r1=63045&r2=63046&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/build_gcc (original) +++ llvm-gcc-4.2/trunk/build_gcc Mon Jan 26 15:46:01 2009 @@ -113,7 +113,7 @@ ARM_SYSROOT="/Developer/SDKs/Extra" ARM_LIBSTDCXX_VERSION=4.2.1 ARM_CONFIGFLAGS="--with-build-sysroot=\"$ARM_SYSROOT\" \ - --with-gxx-include-dir=\${prefix}/include/c++/$ARM_LIBSTDCXX_VERSION" + --with-gxx-include-dir=/usr/include/c++/$ARM_LIBSTDCXX_VERSION" # APPLE LOCAL end ARM ARM_CONFIGFLAGS # This is the libstdc++ version to use. From baldrick at free.fr Mon Jan 26 15:54:19 2009 From: baldrick at free.fr (Duncan Sands) Date: Mon, 26 Jan 2009 21:54:19 -0000 Subject: [llvm-commits] [llvm] r63048 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeTypes.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h test/CodeGen/X86/2009-01-26-WrongCheck.ll Message-ID: <200901262154.n0QLsJmP026893@zion.cs.uiuc.edu> Author: baldrick Date: Mon Jan 26 15:54:18 2009 New Revision: 63048 URL: http://llvm.org/viewvc/llvm-project?rev=63048&view=rev Log: Fix PR3393, which amounts to a bug in the expensive checking logic. Rather than make the checking more complicated, I've tweaked some logic to make things conform to how the checking thought things ought to be, since this results in a simpler "mental model". Added: llvm/trunk/test/CodeGen/X86/2009-01-26-WrongCheck.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=63048&r1=63047&r2=63048&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Mon Jan 26 15:54:18 2009 @@ -328,14 +328,21 @@ continue; // The node morphed - this is equivalent to legalizing by replacing every - // value of N with the corresponding value of M. So do that now. - N->setNodeId(ReadyToProcess); + // value of N with the corresponding value of M. So do that now. However + // there is no need to remember the replacement - morphing will make sure + // it is never used non-trivially. assert(N->getNumValues() == M->getNumValues() && "Node morphing changed the number of results!"); for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) - // Replacing the value takes care of remapping the new value. - ReplaceValueWith(SDValue(N, i), SDValue(M, i)); - // Fall through. + // Replacing the value takes care of remapping the new value. Do the + // replacement without recording it in ReplacedValues. This does not + // expunge From but that is fine - it is not really a new node. + ReplaceValueWithHelper(SDValue(N, i), SDValue(M, i)); + assert(N->getNodeId() == NewNode && "Unexpected node state!"); + // The node continues to live on as part of the NewNode fungus that + // grows on top of the useful nodes. Nothing more needs to be done + // with it - move on to the next node. + continue; } if (i == NumOperands) { @@ -668,16 +675,14 @@ } -/// ReplaceValueWith - The specified value was legalized to the specified other -/// value. Update the DAG and NodeIds replacing any uses of From to use To -/// instead. -void DAGTypeLegalizer::ReplaceValueWith(SDValue From, SDValue To) { - assert(From.getNode()->getNodeId() == ReadyToProcess && - "Only the node being processed may be remapped!"); +/// ReplaceValueWithHelper - Internal helper for ReplaceValueWith. Updates the +/// DAG causing any uses of From to use To instead, but without expunging From +/// or recording the replacement in ReplacedValues. Do not call directly unless +/// you really know what you are doing! +void DAGTypeLegalizer::ReplaceValueWithHelper(SDValue From, SDValue To) { assert(From.getNode() != To.getNode() && "Potential legalization loop!"); // If expansion produced new nodes, make sure they are properly marked. - ExpungeNode(From.getNode()); AnalyzeNewValue(To); // Expunges To. // Anything that used the old node should now use the new one. Note that this @@ -686,10 +691,6 @@ NodeUpdateListener NUL(*this, NodesToAnalyze); DAG.ReplaceAllUsesOfValueWith(From, To, &NUL); - // The old node may still be present in a map like ExpandedIntegers or - // PromotedIntegers. Inform maps about the replacement. - ReplacedValues[From] = To; - // Process the list of nodes that need to be reanalyzed. while (!NodesToAnalyze.empty()) { SDNode *N = NodesToAnalyze.back(); @@ -719,6 +720,25 @@ } } +/// ReplaceValueWith - The specified value was legalized to the specified other +/// value. Update the DAG and NodeIds replacing any uses of From to use To +/// instead. +void DAGTypeLegalizer::ReplaceValueWith(SDValue From, SDValue To) { + assert(From.getNode()->getNodeId() == ReadyToProcess && + "Only the node being processed may be remapped!"); + + // If expansion produced new nodes, make sure they are properly marked. + ExpungeNode(From.getNode()); + AnalyzeNewValue(To); // Expunges To. + + // The old node may still be present in a map like ExpandedIntegers or + // PromotedIntegers. Inform maps about the replacement. + ReplacedValues[From] = To; + + // Do the replacement. + ReplaceValueWithHelper(From, To); +} + void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) { AnalyzeNewValue(Result); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=63048&r1=63047&r2=63048&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Mon Jan 26 15:54:18 2009 @@ -199,6 +199,7 @@ const SDValue *Ops, unsigned NumOps, bool isSigned); SDValue PromoteTargetBoolean(SDValue Bool, MVT VT); void ReplaceValueWith(SDValue From, SDValue To); + void ReplaceValueWithHelper(SDValue From, SDValue To); void SetIgnoredNodeResult(SDNode* N); void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi); void SplitInteger(SDValue Op, MVT LoVT, MVT HiVT, Added: llvm/trunk/test/CodeGen/X86/2009-01-26-WrongCheck.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-01-26-WrongCheck.ll?rev=63048&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-01-26-WrongCheck.ll (added) +++ llvm/trunk/test/CodeGen/X86/2009-01-26-WrongCheck.ll Mon Jan 26 15:54:18 2009 @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=x86 -enable-legalize-types-checking +; PR3393 + +define void @foo(i32 inreg %x) { + %t709 = select i1 false, i32 0, i32 %x ; [#uses=1] + %t711 = add i32 %t709, 1 ; [#uses=4] + %t801 = icmp slt i32 %t711, 0 ; [#uses=1] + %t712 = zext i32 %t711 to i64 ; [#uses=1] + %t804 = select i1 %t801, i64 0, i64 %t712 ; [#uses=1] + store i64 %t804, i64* null + %t815 = icmp slt i32 %t711, 0 ; [#uses=1] + %t814 = sext i32 %t711 to i64 ; [#uses=1] + %t816 = select i1 %t815, i64 0, i64 %t814 ; [#uses=1] + store i64 %t816, i64* null + unreachable +} From resistor at mac.com Mon Jan 26 15:57:32 2009 From: resistor at mac.com (Owen Anderson) Date: Mon, 26 Jan 2009 21:57:32 -0000 Subject: [llvm-commits] [llvm] r63049 - /llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Message-ID: <200901262157.n0QLvWu8027110@zion.cs.uiuc.edu> Author: resistor Date: Mon Jan 26 15:57:31 2009 New Revision: 63049 URL: http://llvm.org/viewvc/llvm-project?rev=63049&view=rev Log: Reapply r63025 and r63026, with fixes for the failing testcases. Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=63049&r1=63048&r2=63049&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original) +++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Mon Jan 26 15:57:31 2009 @@ -139,26 +139,11 @@ void UpdateSpillSlotInterval(VNInfo*, unsigned, unsigned); - VNInfo* UpdateRegisterInterval(VNInfo*, unsigned, unsigned); - - bool ShrinkWrapToLastUse(MachineBasicBlock*, VNInfo*, - SmallVector&, - SmallPtrSet&); - - void ShrinkWrapLiveInterval(VNInfo*, MachineBasicBlock*, MachineBasicBlock*, - MachineBasicBlock*, SmallPtrSet&, - DenseMap >&, - DenseMap >&, - SmallVector&); - bool SplitRegLiveInterval(LiveInterval*); bool SplitRegLiveIntervals(const TargetRegisterClass **, SmallPtrSet&); - void RepairLiveInterval(LiveInterval* CurrLI, VNInfo* ValNo, - MachineInstr* DefMI, unsigned RestoreIdx); - bool createsNewJoin(LiveRange* LR, MachineBasicBlock* DefMBB, MachineBasicBlock* BarrierMBB); bool Rematerialize(unsigned vreg, VNInfo* ValNo, @@ -423,176 +408,6 @@ } } -/// UpdateRegisterInterval - Given the specified val# of the current live -/// interval is being split, and the spill and restore indices, update the live -/// interval accordingly. -VNInfo* -PreAllocSplitting::UpdateRegisterInterval(VNInfo *ValNo, unsigned SpillIndex, - unsigned RestoreIndex) { - assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB && - "Expect restore in the barrier mbb"); - - SmallVector, 4> Before; - SmallVector, 4> After; - SmallVector BeforeKills; - SmallVector AfterKills; - SmallPtrSet Processed; - - // First, let's figure out which parts of the live interval is now defined - // by the restore, which are defined by the original definition. - const LiveRange *LR = CurrLI->getLiveRangeContaining(RestoreIndex); - After.push_back(std::make_pair(RestoreIndex, LR->end)); - if (CurrLI->isKill(ValNo, LR->end)) - AfterKills.push_back(LR->end); - - assert(LR->contains(SpillIndex)); - if (SpillIndex > LR->start) { - Before.push_back(std::make_pair(LR->start, SpillIndex)); - BeforeKills.push_back(SpillIndex); - } - Processed.insert(LR); - - // Start from the restore mbb, figure out what part of the live interval - // are defined by the restore. - SmallVector WorkList; - MachineBasicBlock *MBB = BarrierMBB; - for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), - SE = MBB->succ_end(); SI != SE; ++SI) - WorkList.push_back(*SI); - - SmallPtrSet ProcessedBlocks; - ProcessedBlocks.insert(MBB); - - while (!WorkList.empty()) { - MBB = WorkList.back(); - WorkList.pop_back(); - unsigned Idx = LIs->getMBBStartIdx(MBB); - LR = CurrLI->getLiveRangeContaining(Idx); - if (LR && LR->valno == ValNo && !Processed.count(LR)) { - After.push_back(std::make_pair(LR->start, LR->end)); - if (CurrLI->isKill(ValNo, LR->end)) - AfterKills.push_back(LR->end); - Idx = LIs->getMBBEndIdx(MBB); - if (LR->end > Idx) { - // Live range extend beyond at least one mbb. Let's see what other - // mbbs it reaches. - LIs->findReachableMBBs(LR->start, LR->end, WorkList); - } - Processed.insert(LR); - } - - ProcessedBlocks.insert(MBB); - if (LR) - for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), - SE = MBB->succ_end(); SI != SE; ++SI) - if (!ProcessedBlocks.count(*SI)) - WorkList.push_back(*SI); - } - - for (LiveInterval::iterator I = CurrLI->begin(), E = CurrLI->end(); - I != E; ++I) { - LiveRange *LR = I; - if (LR->valno == ValNo && !Processed.count(LR)) { - Before.push_back(std::make_pair(LR->start, LR->end)); - if (CurrLI->isKill(ValNo, LR->end)) - BeforeKills.push_back(LR->end); - } - } - - // Now create new val#s to represent the live ranges defined by the old def - // those defined by the restore. - unsigned AfterDef = ValNo->def; - MachineInstr *AfterCopy = ValNo->copy; - bool HasPHIKill = ValNo->hasPHIKill; - CurrLI->removeValNo(ValNo); - VNInfo *BValNo = (Before.empty()) - ? NULL - : CurrLI->getNextValue(AfterDef, AfterCopy, LIs->getVNInfoAllocator()); - if (BValNo) - CurrLI->addKills(BValNo, BeforeKills); - - VNInfo *AValNo = (After.empty()) - ? NULL - : CurrLI->getNextValue(RestoreIndex, 0, LIs->getVNInfoAllocator()); - if (AValNo) { - AValNo->hasPHIKill = HasPHIKill; - CurrLI->addKills(AValNo, AfterKills); - } - - for (unsigned i = 0, e = Before.size(); i != e; ++i) { - unsigned Start = Before[i].first; - unsigned End = Before[i].second; - CurrLI->addRange(LiveRange(Start, End, BValNo)); - } - for (unsigned i = 0, e = After.size(); i != e; ++i) { - unsigned Start = After[i].first; - unsigned End = After[i].second; - CurrLI->addRange(LiveRange(Start, End, AValNo)); - } - - return AValNo; -} - -/// ShrinkWrapToLastUse - There are uses of the current live interval in the -/// given block, shrink wrap the live interval to the last use (i.e. remove -/// from last use to the end of the mbb). In case mbb is the where the barrier -/// is, remove from the last use to the barrier. -bool -PreAllocSplitting::ShrinkWrapToLastUse(MachineBasicBlock *MBB, VNInfo *ValNo, - SmallVector &Uses, - SmallPtrSet &UseMIs) { - MachineOperand *LastMO = 0; - MachineInstr *LastMI = 0; - if (MBB != BarrierMBB && Uses.size() == 1) { - // Single use, no need to traverse the block. We can't assume this for the - // barrier bb though since the use is probably below the barrier. - LastMO = Uses[0]; - LastMI = LastMO->getParent(); - } else { - MachineBasicBlock::iterator MEE = MBB->begin(); - MachineBasicBlock::iterator MII; - if (MBB == BarrierMBB) - MII = Barrier; - else - MII = MBB->end(); - while (MII != MEE) { - --MII; - MachineInstr *UseMI = &*MII; - if (!UseMIs.count(UseMI)) - continue; - for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = UseMI->getOperand(i); - if (MO.isReg() && MO.getReg() == CurrLI->reg) { - LastMO = &MO; - break; - } - } - LastMI = UseMI; - break; - } - } - - // Cut off live range from last use (or beginning of the mbb if there - // are no uses in it) to the end of the mbb. - unsigned RangeStart, RangeEnd = LIs->getMBBEndIdx(MBB)+1; - if (LastMI) { - RangeStart = LIs->getUseIndex(LIs->getInstructionIndex(LastMI))+1; - assert(!LastMO->isKill() && "Last use already terminates the interval?"); - LastMO->setIsKill(); - } else { - assert(MBB == BarrierMBB); - RangeStart = LIs->getMBBStartIdx(MBB); - } - if (MBB == BarrierMBB) - RangeEnd = LIs->getUseIndex(BarrierIdx)+1; - CurrLI->removeRange(RangeStart, RangeEnd); - if (LastMI) - CurrLI->addKill(ValNo, RangeStart); - - // Return true if the last use becomes a new kill. - return LastMI; -} - /// PerformPHIConstruction - From properly set up use and def lists, use a PHI /// construction algorithm to compute the ranges and valnos for an interval. VNInfo* PreAllocSplitting::PerformPHIConstruction( @@ -748,12 +563,12 @@ ret = PerformPHIConstruction(walker, MBB, LI, Visited, Defs, Uses, NewVNs, LiveOut, Phis, false, true); + LI->addRange(LiveRange(UseIndex, EndIndex+1, ret)); + // FIXME: Need to set kills properly for inter-block stuff. if (LI->isKill(ret, UseIndex)) LI->removeKill(ret, UseIndex); if (intrablock) LI->addKill(ret, EndIndex); - - LI->addRange(LiveRange(UseIndex, EndIndex+1, ret)); } else if (ContainsDefs && ContainsUses){ SmallPtrSet& BlockDefs = Defs[MBB]; SmallPtrSet& BlockUses = Uses[MBB]; @@ -805,13 +620,13 @@ ret = PerformPHIConstruction(walker, MBB, LI, Visited, Defs, Uses, NewVNs, LiveOut, Phis, false, true); + LI->addRange(LiveRange(StartIndex, EndIndex+1, ret)); + if (foundUse && LI->isKill(ret, StartIndex)) LI->removeKill(ret, StartIndex); if (intrablock) { LI->addKill(ret, EndIndex); } - - LI->addRange(LiveRange(StartIndex, EndIndex+1, ret)); } // Memoize results so we don't have to recompute them. @@ -890,142 +705,6 @@ } } -/// ShrinkWrapLiveInterval - Recursively traverse the predecessor -/// chain to find the new 'kills' and shrink wrap the live interval to the -/// new kill indices. -void -PreAllocSplitting::ShrinkWrapLiveInterval(VNInfo *ValNo, MachineBasicBlock *MBB, - MachineBasicBlock *SuccMBB, MachineBasicBlock *DefMBB, - SmallPtrSet &Visited, - DenseMap > &Uses, - DenseMap > &UseMIs, - SmallVector &UseMBBs) { - if (Visited.count(MBB)) - return; - - // If live interval is live in another successor path, then we can't process - // this block. But we may able to do so after all the successors have been - // processed. - if (MBB != BarrierMBB) { - for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), - SE = MBB->succ_end(); SI != SE; ++SI) { - MachineBasicBlock *SMBB = *SI; - if (SMBB == SuccMBB) - continue; - if (CurrLI->liveAt(LIs->getMBBStartIdx(SMBB))) - return; - } - } - - Visited.insert(MBB); - - DenseMap >::iterator - UMII = Uses.find(MBB); - if (UMII != Uses.end()) { - // At least one use in this mbb, lets look for the kill. - DenseMap >::iterator - UMII2 = UseMIs.find(MBB); - if (ShrinkWrapToLastUse(MBB, ValNo, UMII->second, UMII2->second)) - // Found a kill, shrink wrapping of this path ends here. - return; - } else if (MBB == DefMBB) { - // There are no uses after the def. - MachineInstr *DefMI = LIs->getInstructionFromIndex(ValNo->def); - if (UseMBBs.empty()) { - // The only use must be below barrier in the barrier block. It's safe to - // remove the def. - LIs->RemoveMachineInstrFromMaps(DefMI); - DefMI->eraseFromParent(); - CurrLI->removeRange(ValNo->def, LIs->getMBBEndIdx(MBB)+1); - } - } else if (MBB == BarrierMBB) { - // Remove entire live range from start of mbb to barrier. - CurrLI->removeRange(LIs->getMBBStartIdx(MBB), - LIs->getUseIndex(BarrierIdx)+1); - } else { - // Remove entire live range of the mbb out of the live interval. - CurrLI->removeRange(LIs->getMBBStartIdx(MBB), LIs->getMBBEndIdx(MBB)+1); - } - - if (MBB == DefMBB) - // Reached the def mbb, stop traversing this path further. - return; - - // Traverse the pathes up the predecessor chains further. - for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(), - PE = MBB->pred_end(); PI != PE; ++PI) { - MachineBasicBlock *Pred = *PI; - if (Pred == MBB) - continue; - if (Pred == DefMBB && ValNo->hasPHIKill) - // Pred is the def bb and the def reaches other val#s, we must - // allow the value to be live out of the bb. - continue; - if (!CurrLI->liveAt(LIs->getMBBEndIdx(Pred)-1)) - return; - ShrinkWrapLiveInterval(ValNo, Pred, MBB, DefMBB, Visited, - Uses, UseMIs, UseMBBs); - } - - return; -} - - -void PreAllocSplitting::RepairLiveInterval(LiveInterval* CurrLI, - VNInfo* ValNo, - MachineInstr* DefMI, - unsigned RestoreIdx) { - // Shrink wrap the live interval by walking up the CFG and find the - // new kills. - // Now let's find all the uses of the val#. - DenseMap > Uses; - DenseMap > UseMIs; - SmallPtrSet Seen; - SmallVector UseMBBs; - for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(CurrLI->reg), - UE = MRI->use_end(); UI != UE; ++UI) { - MachineOperand &UseMO = UI.getOperand(); - MachineInstr *UseMI = UseMO.getParent(); - unsigned UseIdx = LIs->getInstructionIndex(UseMI); - LiveInterval::iterator ULR = CurrLI->FindLiveRangeContaining(UseIdx); - if (ULR->valno != ValNo) - continue; - MachineBasicBlock *UseMBB = UseMI->getParent(); - // Remember which other mbb's use this val#. - if (Seen.insert(UseMBB) && UseMBB != BarrierMBB) - UseMBBs.push_back(UseMBB); - DenseMap >::iterator - UMII = Uses.find(UseMBB); - if (UMII != Uses.end()) { - DenseMap >::iterator - UMII2 = UseMIs.find(UseMBB); - UMII->second.push_back(&UseMO); - UMII2->second.insert(UseMI); - } else { - SmallVector Ops; - Ops.push_back(&UseMO); - Uses.insert(std::make_pair(UseMBB, Ops)); - SmallPtrSet MIs; - MIs.insert(UseMI); - UseMIs.insert(std::make_pair(UseMBB, MIs)); - } - } - - // Walk up the predecessor chains. - SmallPtrSet Visited; - ShrinkWrapLiveInterval(ValNo, BarrierMBB, NULL, DefMI->getParent(), Visited, - Uses, UseMIs, UseMBBs); - - // Remove live range from barrier to the restore. FIXME: Find a better - // point to re-start the live interval. - VNInfo* AfterValNo = UpdateRegisterInterval(ValNo, - LIs->getUseIndex(BarrierIdx)+1, - LIs->getDefIndex(RestoreIdx)); - - // Attempt to renumber the new valno into a new vreg. - RenumberValno(AfterValNo); -} - /// RenumberValno - Split the given valno out into a new vreg, allowing it to /// be allocated to a different register. This function creates a new vreg, /// copies the valno and its live ranges over to the new vreg's interval, @@ -1055,12 +734,12 @@ for (SmallVector::iterator KI = OldVN->kills.begin(), KE = OldVN->kills.end(); KI != KE; ++KI) { MachineInstr* MI = LIs->getInstructionFromIndex(*KI); - //if (!MI) continue; unsigned DefIdx = MI->findRegisterDefOperandIdx(CurrLI->reg); if (DefIdx == ~0U) continue; if (MI->isRegReDefinedByTwoAddr(DefIdx)) { VNInfo* NextVN = CurrLI->findDefinedVNInfo(LiveIntervals::getDefIndex(*KI)); + if (NextVN == OldVN) continue; Stack.push_back(NextVN); } } @@ -1131,18 +810,10 @@ TII->reMaterialize(MBB, RestorePt, vreg, DefMI); LIs->InsertMachineInstrInMaps(prior(RestorePt), RestoreIdx); - if (KillPt->getParent() == BarrierMBB) { - VNInfo* After = UpdateRegisterInterval(ValNo, LIs->getUseIndex(KillIdx)+1, - LIs->getDefIndex(RestoreIdx)); - - RenumberValno(After); - - ++NumSplits; - ++NumRemats; - return true; - } - - RepairLiveInterval(CurrLI, ValNo, DefMI, RestoreIdx); + ReconstructLiveInterval(CurrLI); + unsigned RematIdx = LIs->getInstructionIndex(prior(RestorePt)); + RematIdx = LiveIntervals::getDefIndex(RematIdx); + RenumberValno(CurrLI->findDefinedVNInfo(RematIdx)); ++NumSplits; ++NumRemats; @@ -1315,28 +986,14 @@ MachineInstr *LoadMI = prior(RestorePt); LIs->InsertMachineInstrInMaps(LoadMI, RestoreIndex); - // If live interval is spilled in the same block as the barrier, just - // create a hole in the interval. - if (!DefMBB || - (SpillMI && SpillMI->getParent() == BarrierMBB)) { - // Update spill stack slot live interval. - UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1, - LIs->getDefIndex(RestoreIndex)); - - VNInfo* After = UpdateRegisterInterval(ValNo, - LIs->getUseIndex(SpillIndex)+1, - LIs->getDefIndex(RestoreIndex)); - RenumberValno(After); - - ++NumSplits; - return true; - } - // Update spill stack slot live interval. UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1, LIs->getDefIndex(RestoreIndex)); - RepairLiveInterval(CurrLI, ValNo, DefMI, RestoreIndex); + ReconstructLiveInterval(CurrLI); + unsigned RestoreIdx = LIs->getInstructionIndex(prior(RestorePt)); + RestoreIdx = LiveIntervals::getDefIndex(RestoreIdx); + RenumberValno(CurrLI->findDefinedVNInfo(RestoreIdx)); ++NumSplits; return true; From dpatel at apple.com Mon Jan 26 15:57:29 2009 From: dpatel at apple.com (Devang Patel) Date: Mon, 26 Jan 2009 13:57:29 -0800 Subject: [llvm-commits] [llvm] r63008 - in /llvm/trunk: include/llvm/CodeGen/DebugLoc.h include/llvm/CodeGen/MachineFunction.h lib/CodeGen/MachineFunction.cpp In-Reply-To: <200901260741.n0Q7fnOn020226@zion.cs.uiuc.edu> References: <200901260741.n0Q7fnOn020226@zion.cs.uiuc.edu> Message-ID: <517B4716-1012-43CB-8033-9D15F85548A6@apple.com> On Jan 25, 2009, at 11:41 PM, Evan Cheng wrote: > Author: evancheng > Date: Mon Jan 26 01:41:49 2009 > New Revision: 63008 > > URL: http://llvm.org/viewvc/llvm-project?rev=63008&view=rev > Log: > Add data structure to define and track debug location during codegen. > > Added: > llvm/trunk/include/llvm/CodeGen/DebugLoc.h > Modified: > llvm/trunk/include/llvm/CodeGen/MachineFunction.h > llvm/trunk/lib/CodeGen/MachineFunction.cpp > > Added: llvm/trunk/include/llvm/CodeGen/DebugLoc.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DebugLoc.h?rev=63008&view=auto > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/CodeGen/DebugLoc.h (added) > +++ llvm/trunk/include/llvm/CodeGen/DebugLoc.h Mon Jan 26 01:41:49 > 2009 > @@ -0,0 +1,109 @@ > +//===---- llvm/CodeGen/DebugLoc.h - Debug Location Information --*- > C++ -*-===// > +// > +// The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open > Source > +// License. See LICENSE.TXT for details. > +// > +// > = > = > = > ----------------------------------------------------------------------= > ==// > +// > +// This file defines a number of light weight data structures used > by the code > +// generator to describe and track debug location information. > + > +#ifndef LLVM_CODEGEN_DEBUGLOC_H > +#define LLVM_CODEGEN_DEBUGLOC_H > + > +#include "llvm/ADT/DenseMap.h" > +#include "llvm/ADT/StringMap.h" > +#include > + > +namespace llvm { > + > + /// DebugLocTuple - Debug location tuple of filename id, line and > column. > + /// > + struct DebugLocTuple { > + unsigned FileId, Line, Col; > + > + DebugLocTuple(unsigned fi, unsigned l, unsigned c) > + : FileId(fi), Line(l), Col(c) {}; > + }; > + Why not use SourceLineInfo directly instead of introducing DebugLocTuple ? // = = =---------------------------------------------------------------------- ===// /// SourceLineInfo - This class is used to record source line correspondence. /// class SourceLineInfo { unsigned Line; // Source line number. unsigned Column; // Source column. unsigned SourceID; // Source ID number. unsigned LabelID; // Label in code ID number. public ... SourceLineInfo is managed using UniqueVector in DwarfWriter. Is there a known reason to use DenseMap ? I'm just curious. - Devan > > + /// DebugLoc - Debug location id. This is carried by SDNode and > + /// MachineInstr to index into a vector of unique debug location > tuples. > + class DebugLoc { > + unsigned Idx; > + > + public: > + DebugLoc() : Idx(~0U) {} > + > + static DebugLoc getNoDebugLoc() { DebugLoc L; L.Idx = 0; > return L; } > + static DebugLoc get(unsigned idx) { DebugLoc L; L.Idx = idx; > return L; } > + > + bool isInvalid() { return Idx == ~0U; } > + bool isUnknown() { return Idx == 0; } > + }; > + > + struct DebugLocTupleDenseMapInfo { > + static inline DebugLocTuple getEmptyKey() { > + return DebugLocTuple(~0U, ~0U, ~0U); > + } > + static inline DebugLocTuple getTombstoneKey() { > + return DebugLocTuple(~1U, ~1U, ~1U); > + } > + static unsigned getHashValue(const DebugLocTuple &Val) { > + return DenseMapInfo::getHashValue(Val.FileId) ^ > + DenseMapInfo::getHashValue(Val.Line) ^ > + DenseMapInfo::getHashValue(Val.Col); > + } > + static bool isEqual(const DebugLocTuple &LHS, const > DebugLocTuple &RHS) { > + return LHS.FileId == RHS.FileId && > + LHS.Line == RHS.Line && > + LHS.Col == RHS.Col; > + } > + > + static bool isPod() { return true; } > + }; > + > + typedef DenseMap DebugLocTupleDenseMapInfo> > + DebugIdMapType; > + > + /// DebugLocTracker - This class tracks debug location information. > + /// > + struct DebugLocTracker { > + // NumFilenames - Size of the DebugFilenames vector. > + // > + unsigned NumFilenames; > + > + // DebugFilenames - A vector of unique file names. > + // > + std::vector DebugFilenames; > + > + // DebugFilenamesMap - File name to DebugFilenames index map. > + // > + StringMap DebugFilenamesMap; > + > + // NumDebugLocations - Size of the DebugLocations vector. > + unsigned NumDebugLocations; > + > + // DebugLocations - A vector of unique DebugLocTuple's. > + // > + std::vector DebugLocations; > + > + // DebugIdsMap - This maps DebugLocTuple's to indices into > + // DebugLocations vector. > + DebugIdMapType DebugIdMap; > + > + DebugLocTracker() : NumFilenames(0), NumDebugLocations(0) {} > + > + ~DebugLocTracker() { > + NumFilenames = 0; > + DebugFilenames.clear(); > + DebugFilenamesMap.clear(); > + DebugLocations.clear(); > + DebugIdMap.clear(); > + } > + }; > + > +} // end namespace llvm > + > +#endif /* LLVM_CODEGEN_DEBUGLOC_H */ > > Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=63008&r1=63007&r2=63008&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original) > +++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Mon Jan 26 > 01:41:49 2009 > @@ -19,6 +19,7 @@ > #define LLVM_CODEGEN_MACHINEFUNCTION_H > > #include "llvm/ADT/ilist.h" > +#include "llvm/CodeGen/DebugLoc.h" > #include "llvm/CodeGen/MachineBasicBlock.h" > #include "llvm/Support/Annotation.h" > #include "llvm/Support/Allocator.h" > @@ -27,11 +28,11 @@ > namespace llvm { > > class Function; > -class TargetMachine; > class MachineRegisterInfo; > class MachineFrameInfo; > class MachineConstantPool; > class MachineJumpTableInfo; > +class TargetMachine; > > template <> > struct ilist_traits > @@ -94,6 +95,9 @@ > typedef ilist BasicBlockListType; > BasicBlockListType BasicBlocks; > > + // Tracks debug locations. > + DebugLocTracker DebugLocInfo; > + > public: > MachineFunction(const Function *Fn, const TargetMachine &TM); > ~MachineFunction(); > @@ -302,6 +306,15 @@ > /// DeleteMachineBasicBlock - Delete the given MachineBasicBlock. > /// > void DeleteMachineBasicBlock(MachineBasicBlock *MBB); > + > + // > = > = > =-------------------------------------------------------------------- > ===// > + // Debug location. > + // > + > + /// lookUpDebugLocId - Look up the DebugLocTuple index with the > given > + /// filename, line, and column. It may add a new filename and / or > + /// a new DebugLocTuple. > + unsigned lookUpDebugLocId(const char *Filename, unsigned Line, > unsigned Col); > }; > > // > = > = > =-------------------------------------------------------------------- > ===// > > Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=63008&r1=63007&r2=63008&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original) > +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Mon Jan 26 01:41:49 > 2009 > @@ -378,6 +378,33 @@ > return *mc; > } > > +/// lookUpDebugLocId - Look up the DebugLocTuple index with the given > +/// filename, line, and column. It may add a new filename and / or > +/// a new DebugLocTuple. > +unsigned MachineFunction::lookUpDebugLocId(const char *Filename, > unsigned Line, > + unsigned Col) { > + unsigned FileId; > + StringMap::iterator I = > + DebugLocInfo.DebugFilenamesMap.find(Filename); > + if (I != DebugLocInfo.DebugFilenamesMap.end()) > + FileId = I->second; > + else { > + // Add a new filename. > + FileId = DebugLocInfo.NumFilenames++; > + DebugLocInfo.DebugFilenames.push_back(Filename); > + DebugLocInfo.DebugFilenamesMap[Filename] = FileId; > + } > + > + struct DebugLocTuple Tuple(FileId, Line, Col); > + DebugIdMapType::iterator II = DebugLocInfo.DebugIdMap.find(Tuple); > + if (II != DebugLocInfo.DebugIdMap.end()) > + return II->second; > + // Add a new tuple. > + DebugLocInfo.DebugLocations.push_back(Tuple); > + DebugLocInfo.DebugIdMap[Tuple] = DebugLocInfo.NumDebugLocations; > + return DebugLocInfo.NumDebugLocations++; > +} > + > // > = > = > = > ----------------------------------------------------------------------= > ==// > // MachineFrameInfo implementation > // > = > = > = > ----------------------------------------------------------------------= > ==// > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090126/c3056c55/attachment.html From snaroff at apple.com Mon Jan 26 16:03:42 2009 From: snaroff at apple.com (Steve Naroff) Date: Mon, 26 Jan 2009 22:03:42 -0000 Subject: [llvm-commits] [llvm] r63050 - in /llvm/trunk/win32: Analysis/Analysis.vcproj AsmParser/AsmParser.vcproj Message-ID: <200901262203.n0QM3gnq027365@zion.cs.uiuc.edu> Author: snaroff Date: Mon Jan 26 16:03:42 2009 New Revision: 63050 URL: http://llvm.org/viewvc/llvm-project?rev=63050&view=rev Log: More updates to VC proj... Modified: llvm/trunk/win32/Analysis/Analysis.vcproj llvm/trunk/win32/AsmParser/AsmParser.vcproj Modified: llvm/trunk/win32/Analysis/Analysis.vcproj URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/win32/Analysis/Analysis.vcproj?rev=63050&r1=63049&r2=63050&view=diff ============================================================================== --- llvm/trunk/win32/Analysis/Analysis.vcproj (original) +++ llvm/trunk/win32/Analysis/Analysis.vcproj Mon Jan 26 16:03:42 2009 @@ -341,6 +341,10 @@ > + + Modified: llvm/trunk/win32/AsmParser/AsmParser.vcproj URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/win32/AsmParser/AsmParser.vcproj?rev=63050&r1=63049&r2=63050&view=diff ============================================================================== --- llvm/trunk/win32/AsmParser/AsmParser.vcproj (original) +++ llvm/trunk/win32/AsmParser/AsmParser.vcproj Mon Jan 26 16:03:42 2009 @@ -90,11 +90,11 @@ /> - - - - - - - - - - - - - - - - From isanbard at gmail.com Mon Jan 26 16:13:14 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 26 Jan 2009 22:13:14 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63051 - in /llvm-gcc-4.2/trunk/gcc: gimplify.c llvm-backend.cpp llvm-convert.cpp tree.h Message-ID: <200901262213.n0QMDFiF027762@zion.cs.uiuc.edu> Author: void Date: Mon Jan 26 16:13:14 2009 New Revision: 63051 URL: http://llvm.org/viewvc/llvm-project?rev=63051&view=rev Log: This "private" stuff was causing Objective-C programs to fail. Reverting r62850: $ cat f.m #include void foo() { NSLog(@""); NSLog(@"hello world"); } int main() { foo(); return 0; } $ llvm-gcc -o - -S f.m f.m: In function ?foo?: f.m:2: internal compiler error: tree check: expected tree that contains ?decl with visibility? structure, have ?const_decl? in emit_global_to_llvm, at llvm-backend.cpp:1087 Please submit a full bug report, with preprocessed source if appropriate. See for instructions. Modified: llvm-gcc-4.2/trunk/gcc/gimplify.c llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp llvm-gcc-4.2/trunk/gcc/tree.h Modified: llvm-gcc-4.2/trunk/gcc/gimplify.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gimplify.c?rev=63051&r1=63050&r2=63051&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/gimplify.c (original) +++ llvm-gcc-4.2/trunk/gcc/gimplify.c Mon Jan 26 16:13:14 2009 @@ -3096,7 +3096,6 @@ gimple_add_tmp_var (new); TREE_STATIC (new) = 1; TREE_READONLY (new) = 1; - DECL_LLVM_PRIVATE (new) = 1; DECL_INITIAL (new) = ctor; if (align > DECL_ALIGN (new)) { Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=63051&r1=63050&r2=63051&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Mon Jan 26 16:13:14 2009 @@ -830,9 +830,7 @@ GlobalValue::LinkageTypes Linkage; // A weak alias has TREE_PUBLIC set but not the other bits. - if (DECL_LLVM_PRIVATE(decl)) - Linkage = GlobalValue::PrivateLinkage; - else if (DECL_WEAK(decl)) + if (DECL_WEAK(decl)) Linkage = GlobalValue::WeakLinkage; else if (!TREE_PUBLIC(decl)) Linkage = GlobalValue::InternalLinkage; @@ -1084,9 +1082,7 @@ GV->setThreadLocal(true); // Set the linkage. - if (DECL_LLVM_PRIVATE(decl)) { - GV->setLinkage(GlobalValue::PrivateLinkage); - } else if (!TREE_PUBLIC(decl)) { + if (!TREE_PUBLIC(decl)) { GV->setLinkage(GlobalValue::InternalLinkage); } else if (DECL_WEAK(decl) || DECL_ONE_ONLY(decl)) { GV->setLinkage(GlobalValue::WeakLinkage); Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=63051&r1=63050&r2=63051&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Jan 26 16:13:14 2009 @@ -642,9 +642,7 @@ // emitted; hack this by pretending they're static. That will either // make them go away or emit a static definition that won't collide with // anything. - if (DECL_LLVM_PRIVATE(FnDecl)) { - Fn->setLinkage(Function::PrivateLinkage); - } else if (!TREE_PUBLIC(FnDecl) /*|| lang_hooks.llvm_is_in_anon(subr)*/) { + if (!TREE_PUBLIC(FnDecl) /*|| lang_hooks.llvm_is_in_anon(subr)*/) { Fn->setLinkage(Function::InternalLinkage); } else if (DECL_EXTERNAL(FnDecl) && lookup_attribute ("always_inline", DECL_ATTRIBUTES (FnDecl))) { Modified: llvm-gcc-4.2/trunk/gcc/tree.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/tree.h?rev=63051&r1=63050&r2=63051&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/tree.h (original) +++ llvm-gcc-4.2/trunk/gcc/tree.h Mon Jan 26 16:13:14 2009 @@ -2916,9 +2916,6 @@ /* Used to indicate that this DECL has weak linkage. */ #define DECL_WEAK(NODE) (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.weak_flag) -#define DECL_LLVM_PRIVATE(NODE) \ - (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.llvm_private_flag) - /* Internal to the gimplifier. Indicates that the value is a formal temporary controlled by the gimplifier. */ #define DECL_GIMPLE_FORMAL_TEMP_P(DECL) \ @@ -3055,10 +3052,6 @@ unsigned weak_flag:1; unsigned seen_in_bind_expr : 1; unsigned comdat_flag : 1; - - /* LLVM LOCAL */ - unsigned llvm_private_flag : 1; - ENUM_BITFIELD(symbol_visibility) visibility : 2; unsigned visibility_specified : 1; /* Belong to FUNCTION_DECL exclusively. */ @@ -3079,7 +3072,7 @@ unsigned block_synthesized_function : 1; /* APPLE LOCAL radar 5847976 */ unsigned block_weak : 1; - /* 4 unused bits. */ + /* 5 unused bits. */ /* APPLE LOCAL end radar 5932809 - copyable byref blocks */ /* APPLE LOCAL end radar 5732232 - blocks */ }; From evan.cheng at apple.com Mon Jan 26 16:15:55 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 26 Jan 2009 22:15:55 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63053 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <200901262215.n0QMFtaJ027893@zion.cs.uiuc.edu> Author: evancheng Date: Mon Jan 26 16:15:54 2009 New Revision: 63053 URL: http://llvm.org/viewvc/llvm-project?rev=63053&view=rev Log: llvm-gcc is asserting on this at -O1 and above (Calling a function with a bad signature!): static int bar(); void foo() { int a = bar(); } int bar(unsigned a) { } It should pad the CallOperands vector with an undef before creating the call instruction. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=63053&r1=63052&r2=63053&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Jan 26 16:15:54 2009 @@ -2828,6 +2828,21 @@ Value *Call; if (!LandingPad) { + if (CallOperands.empty()) { + const FunctionType *FTy = cast + (cast(Callee->getType())->getElementType()); + if (!FTy->isVarArg() && FTy->getNumParams() > 0) { + // Something like this: + // static int func2(); + // void func1() { + // int a = func2(); + // } + // int func2(unsigned a) { + // } + // gcc4.2 allows this. + CallOperands.push_back(UndefValue::get(FTy->getParamType(0))); + } + } Call = Builder.CreateCall(Callee, CallOperands.begin(), CallOperands.end()); cast(Call)->setCallingConv(CallingConvention); cast(Call)->setAttributes(PAL); From gohman at apple.com Mon Jan 26 16:22:32 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 26 Jan 2009 22:22:32 -0000 Subject: [llvm-commits] [llvm] r63056 - in /llvm/trunk: include/llvm/Target/TargetOptions.h lib/Target/TargetMachine.cpp lib/Target/X86/X86RegisterInfo.cpp Message-ID: <200901262222.n0QMMWix028199@zion.cs.uiuc.edu> Author: djg Date: Mon Jan 26 16:22:31 2009 New Revision: 63056 URL: http://llvm.org/viewvc/llvm-project?rev=63056&view=rev Log: Implement Red Zone utilization on x86-64. This is currently disabled by default; I'll enable it when I hook it up with the llvm-gcc flag which controls it. Modified: llvm/trunk/include/llvm/Target/TargetOptions.h llvm/trunk/lib/Target/TargetMachine.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/include/llvm/Target/TargetOptions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=63056&r1=63055&r2=63056&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetOptions.h (original) +++ llvm/trunk/include/llvm/Target/TargetOptions.h Mon Jan 26 16:22:31 2009 @@ -107,6 +107,10 @@ /// wth earlier copy coalescing. extern bool StrongPHIElim; + /// DisableRedZone - This flag disables use of the "Red Zone" on + /// targets which would otherwise have one. + extern bool DisableRedZone; + } // End llvm namespace #endif Modified: llvm/trunk/lib/Target/TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=63056&r1=63055&r2=63056&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/TargetMachine.cpp Mon Jan 26 16:22:31 2009 @@ -40,6 +40,7 @@ bool VerboseAsm; bool DisableJumpTables; bool StrongPHIElim; + bool DisableRedZone; } static cl::opt PrintCode("print-machineinstrs", @@ -164,6 +165,12 @@ cl::location(StrongPHIElim), cl::init(false)); +static cl::opt +DisableRedZoneOption("disable-red-zone", + cl::desc("Do not emit code that uses the red zone."), + cl::location(DisableRedZone), + cl::init(true)); + //--------------------------------------------------------------------------- // TargetMachine Class // Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=63056&r1=63055&r2=63056&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon Jan 26 16:22:31 2009 @@ -721,6 +721,18 @@ // Get desired stack alignment uint64_t MaxAlign = MFI->getMaxAlignment(); + // If this is x86-64 and the Red Zone is not disabled, if we are a leaf + // function, and use up to 128 bytes of stack space, don't have a frame + // pointer, calls, or dynamic alloca then we do not need to adjust the + // stack pointer (we fit in the Red Zone). + if (Is64Bit && !DisableRedZone && + !MFI->hasVarSizedObjects() && // No dynamic alloca. + !MFI->hasCalls()) { // No calls. + StackSize = std::max((uint64_t)X86FI->getCalleeSavedFrameSize(), + StackSize > 128 ? StackSize - 128 : 0); + MFI->setStackSize(StackSize); + } + // Add RETADDR move area to callee saved frame size. int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); if (TailCallReturnAddrDelta < 0) From scottm at aero.org Mon Jan 26 16:32:52 2009 From: scottm at aero.org (Scott Michel) Date: Mon, 26 Jan 2009 22:32:52 -0000 Subject: [llvm-commits] [llvm] r63058 - in /llvm/trunk: include/llvm/Target/TargetAsmInfo.h lib/CodeGen/AsmPrinter/DwarfWriter.cpp lib/Target/TargetAsmInfo.cpp Message-ID: <200901262232.n0QMWq14028553@zion.cs.uiuc.edu> Author: pingbak Date: Mon Jan 26 16:32:51 2009 New Revision: 63058 URL: http://llvm.org/viewvc/llvm-project?rev=63058&view=rev Log: Make the Dwarf macro information section optional; CellSPU's assembler doesn't support it. The default is set to 'true', so this should not impact any other target backends. Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp llvm/trunk/lib/Target/TargetAsmInfo.cpp Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=63058&r1=63057&r2=63058&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Mon Jan 26 16:32:51 2009 @@ -429,27 +429,31 @@ /// HasLEB128 - True if target asm supports leb128 directives. /// bool HasLEB128; // Defaults to false. - + /// hasDotLocAndDotFile - True if target asm supports .loc and .file /// directives for emitting debugging information. /// bool HasDotLocAndDotFile; // Defaults to false. - + /// SupportsDebugInformation - True if target supports emission of debugging /// information. bool SupportsDebugInformation; - + /// SupportsExceptionHandling - True if target supports /// exception handling. /// bool SupportsExceptionHandling; // Defaults to false. - + /// RequiresFrameSection - true if the Dwarf2 output needs a frame section /// bool DwarfRequiresFrameSection; // Defaults to true. + /// SupportsMacInfo - true if the Dwarf output supports macro information + /// + bool SupportsMacInfoSection; // Defaults to true + /// NonLocalEHFrameLabel - If set, the EH_frame label needs to be non-local. - /// + /// bool NonLocalEHFrameLabel; // Defaults to false. /// GlobalEHDirective - This is the directive used to make exception frame @@ -818,6 +822,9 @@ bool doesDwarfRequireFrameSection() const { return DwarfRequiresFrameSection; } + bool doesSupportMacInfoSection() const { + return SupportsMacInfoSection; + } bool doesRequireNonLocalEHFrameLabel() const { return NonLocalEHFrameLabel; } Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=63058&r1=63057&r2=63058&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Mon Jan 26 16:32:51 2009 @@ -2167,8 +2167,10 @@ EmitLabel("section_abbrev", 0); Asm->SwitchToDataSection(TAI->getDwarfARangesSection()); EmitLabel("section_aranges", 0); - Asm->SwitchToDataSection(TAI->getDwarfMacInfoSection()); - EmitLabel("section_macinfo", 0); + if (TAI->doesSupportMacInfoSection()) { + Asm->SwitchToDataSection(TAI->getDwarfMacInfoSection()); + EmitLabel("section_macinfo", 0); + } Asm->SwitchToDataSection(TAI->getDwarfLineSection()); EmitLabel("section_line", 0); Asm->SwitchToDataSection(TAI->getDwarfLocSection()); @@ -2755,10 +2757,12 @@ /// EmitDebugMacInfo - Emit visible names into a debug macinfo section. /// void EmitDebugMacInfo() { - // Start the dwarf macinfo section. - Asm->SwitchToDataSection(TAI->getDwarfMacInfoSection()); + if (TAI->doesSupportMacInfoSection()) { + // Start the dwarf macinfo section. + Asm->SwitchToDataSection(TAI->getDwarfMacInfoSection()); - Asm->EOL(); + Asm->EOL(); + } } /// ConstructCompileUnits - Create a compile unit DIEs. Modified: llvm/trunk/lib/Target/TargetAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetAsmInfo.cpp?rev=63058&r1=63057&r2=63058&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetAsmInfo.cpp Mon Jan 26 16:32:51 2009 @@ -99,6 +99,7 @@ SupportsDebugInformation = false; SupportsExceptionHandling = false; DwarfRequiresFrameSection = true; + SupportsMacInfoSection = true; NonLocalEHFrameLabel = false; GlobalEHDirective = 0; SupportsWeakOmittedEHFrame = true; From scottm at aero.org Mon Jan 26 16:33:38 2009 From: scottm at aero.org (Scott Michel) Date: Mon, 26 Jan 2009 22:33:38 -0000 Subject: [llvm-commits] [llvm] r63059 - in /llvm/trunk/lib/Target/CellSPU: AsmPrinter/SPUAsmPrinter.cpp SPUISelDAGToDAG.cpp SPUISelLowering.cpp SPUInstrFormats.td SPUInstrInfo.td SPUTargetAsmInfo.cpp Message-ID: <200901262233.n0QMXciL028589@zion.cs.uiuc.edu> Author: pingbak Date: Mon Jan 26 16:33:37 2009 New Revision: 63059 URL: http://llvm.org/viewvc/llvm-project?rev=63059&view=rev Log: CellSPU: - Update DWARF debugging support. Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUInstrFormats.td llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td llvm/trunk/lib/Target/CellSPU/SPUTargetAsmInfo.cpp Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=63059&r1=63058&r2=63059&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Mon Jan 26 16:33:37 2009 @@ -90,13 +90,13 @@ printOp(MO); } } - + bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode); bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode); - - + + void printS7ImmOperand(const MachineInstr *MI, unsigned OpNo) { @@ -115,7 +115,7 @@ assert(value < (1 << 8) && "Invalid u7 argument"); O << value; } - + void printShufAddr(const MachineInstr *MI, unsigned OpNo) { @@ -143,7 +143,7 @@ { O << (unsigned)MI->getOperand(OpNo).getImm(); } - + void printMemRegReg(const MachineInstr *MI, unsigned OpNo) { // When used as the base register, r0 reads constant zero rather than @@ -286,7 +286,7 @@ /// LinuxAsmPrinter - SPU assembly printer, customized for Linux struct VISIBILITY_HIDDEN LinuxAsmPrinter : public SPUAsmPrinter { - + DwarfWriter *DW; MachineModuleInfo *MMI; @@ -300,12 +300,12 @@ virtual const char *getPassName() const { return "STI CBEA SPU Assembly Printer"; } - + bool runOnMachineFunction(MachineFunction &F); bool doInitialization(Module &M); //! Dump globals, perform cleanup after function emission bool doFinalization(Module &M); - + void getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesAll(); AU.addRequired(); @@ -365,7 +365,7 @@ } } O << Name; - + if (GV->hasExternalWeakLinkage()) ExtWeakSymbols.insert(GV); return; @@ -380,15 +380,15 @@ /// PrintAsmOperand - Print out an operand for an inline asm expression. /// bool SPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, + unsigned AsmVariant, const char *ExtraCode) { // Does this asm operand have a single letter operand modifier? if (ExtraCode && ExtraCode[0]) { if (ExtraCode[1] != 0) return true; // Unknown modifier. - + switch (ExtraCode[0]) { default: return true; // Unknown modifier. - case 'L': // Write second word of DImode reference. + case 'L': // Write second word of DImode reference. // Verify that this operand has two consecutive registers. if (!MI->getOperand(OpNo).isReg() || OpNo+1 == MI->getNumOperands() || @@ -398,14 +398,14 @@ break; } } - + printOperand(MI, OpNo); return false; } bool SPUAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, + unsigned AsmVariant, const char *ExtraCode) { if (ExtraCode && ExtraCode[0]) return true; // Unknown modifier. @@ -429,7 +429,7 @@ { SetupMachineFunction(MF); O << "\n\n"; - + // Print out constants referenced by the function EmitConstantPool(MF.getConstantPool()); @@ -478,10 +478,10 @@ // Print out jump tables referenced by the function. EmitJumpTableInfo(MF.getJumpTableInfo(), MF); - + // Emit post-function debug information. DW->EndFunction(&MF); - + // We didn't modify anything. return false; } @@ -509,7 +509,7 @@ /*! Emit a global variable according to its section, alignment, etc. - + \note This code was shamelessly copied from the PowerPC's assembly printer, which sort of screams for some kind of refactorization of common code. */ @@ -602,8 +602,6 @@ I != E; ++I) printModuleLevelGV(I); - // TODO - // Emit initial debug information. DW->EndModule(); Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=63059&r1=63058&r2=63059&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Mon Jan 26 16:33:37 2009 @@ -51,16 +51,6 @@ return isS10Constant(CN->getSExtValue()); } -#if 0 - //! SDNode predicate for sign-extended, 10-bit immediate values - bool - isI32IntS10Immediate(SDNode *N) - { - return (N->getOpcode() == ISD::Constant - && isI32IntS10Immediate(cast(N))); - } -#endif - //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values bool isI32IntU10Immediate(ConstantSDNode *CN) @@ -79,8 +69,8 @@ bool isI16IntS10Immediate(SDNode *N) { - return (N->getOpcode() == ISD::Constant - && isI16IntS10Immediate(cast(N))); + ConstantSDNode *CN = dyn_cast(N); + return (CN != 0 && isI16IntS10Immediate(CN)); } //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values @@ -230,7 +220,7 @@ SelectionDAGISel(tm), TM(tm), SPUtli(*tm.getTargetLowering()) - {} + { } virtual bool runOnFunction(Function &Fn) { // Make sure we re-emit a set of the global base reg if necessary @@ -259,32 +249,21 @@ SDNode *emitBuildVector(SDValue build_vec) { MVT vecVT = build_vec.getValueType(); SDNode *bvNode = build_vec.getNode(); - bool canBeSelected = false; // Check to see if this vector can be represented as a CellSPU immediate - // constant. - if (vecVT == MVT::v8i16) { - if (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0) { - canBeSelected = true; - } - } else if (vecVT == MVT::v4i32) { - if ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) - || (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) - || (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) - || (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0)) { - canBeSelected = true; - } - } else if (vecVT == MVT::v2i64) { - if ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) - || (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) - || (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)) { - canBeSelected = true; - } - } - - if (canBeSelected) { + // constant by invoking all of the instruction selection predicates: + if (((vecVT == MVT::v8i16) && + (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) || + ((vecVT == MVT::v4i32) && + ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) || + (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) || + (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) || + (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) || + ((vecVT == MVT::v2i64) && + ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) || + (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) || + (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)))) return Select(build_vec); - } // No, need to emit a constant pool spill: std::vector CV; @@ -411,7 +390,7 @@ } /*! - \arg Op The ISD instructio operand + \arg Op The ISD instruction operand \arg N The address to be tested \arg Base The base address \arg Index The base address index @@ -790,9 +769,10 @@ if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL) && OpVT == MVT::i32 && Op0.getValueType() == MVT::i64) { - // Catch the (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32 to - // take advantage of the fact that the upper 32 bits are in the - // i32 preferred slot and avoid all kinds of other shuffle gymnastics: + // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32 + // + // Take advantage of the fact that the upper 32 bits are in the + // i32 preferred slot and avoid shuffle gymnastics: ConstantSDNode *CN = dyn_cast(Op0.getOperand(1)); if (CN != 0) { unsigned shift_amt = unsigned(CN->getZExtValue()); @@ -806,7 +786,7 @@ // Take care of the additional shift, if present: SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32); unsigned Opc = SPU::ROTMAIr32_i32; - + if (Op0.getOpcode() == ISD::SRL) Opc = SPU::ROTMr32; @@ -1113,8 +1093,8 @@ // The degenerate case where the upper and lower bits in the splat are // identical: SDValue Op0 = i64vec.getOperand(0); - ReplaceUses(i64vec, Op0); + ReplaceUses(i64vec, Op0); return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(emitBuildVector(Op0), 0)); } else if (i64vec.getOpcode() == SPUISD::SHUFB) { @@ -1139,7 +1119,7 @@ SDNode *rhsNode = (rhs.getNode()->isMachineOpcode() ? rhs.getNode() : emitBuildVector(rhs)); - + if (shufmask.getOpcode() == ISD::BIT_CONVERT) { ReplaceUses(shufmask, shufmask.getOperand(0)); shufmask = shufmask.getOperand(0); Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=63059&r1=63058&r2=63059&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Mon Jan 26 16:33:37 2009 @@ -293,7 +293,7 @@ // FDIV on SPU requires custom lowering setOperationAction(ISD::FDIV, MVT::f64, Expand); // to libcall - // SPU has [U|S]INT_TO_FP + // SPU has [U|S]INT_TO_FP for f32->i32, but not for f64->i32, f64->i64: setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); @@ -2281,6 +2281,7 @@ DAG.getNode(ISD::BUILD_VECTOR, VT, tcVec, tcVecSize)); } } + // These operations (AND, OR, XOR) are legal, they just couldn't be custom // lowered. Return the operation, rather than a null SDValue. return Op; @@ -2417,7 +2418,7 @@ return ExpandLibCall(LC, Op, DAG, false, Dummy, TLI); } - return SDValue(); + return Op; // return unmolested, legalized op } //! Lower ISD::SINT_TO_FP, ISD::UINT_TO_FP for i32 @@ -2443,7 +2444,7 @@ return ExpandLibCall(LC, Op, DAG, false, Dummy, TLI); } - return SDValue(); + return Op; // return unmolested, legalized } //! Lower ISD::SETCC Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrFormats.td?rev=63059&r1=63058&r2=63059&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrFormats.td (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrFormats.td Mon Jan 26 16:33:37 2009 @@ -290,6 +290,9 @@ class Pseudo pattern> : SPUInstr { + let OutOperandList = OOL; + let InOperandList = IOL; + let AsmString = asmstr; let Pattern = pattern; let Inst{31-0} = 0; } Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td?rev=63059&r1=63058&r2=63059&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td Mon Jan 26 16:33:37 2009 @@ -34,10 +34,9 @@ // DWARF debugging Pseudo Instructions //===----------------------------------------------------------------------===// -def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), - "${:comment} .loc $file, $line, $col", - [(dwarf_loc (i32 imm:$line), (i32 imm:$col), - (i32 imm:$file))]>; +def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), + ".loc $file, $line, $col", + [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>; //===----------------------------------------------------------------------===// // Loads: Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetAsmInfo.cpp?rev=63059&r1=63058&r2=63059&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUTargetAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUTargetAsmInfo.cpp Mon Jan 26 16:33:37 2009 @@ -15,8 +15,10 @@ #include "SPUTargetMachine.h" #include "llvm/Function.h" #include "llvm/Support/Compiler.h" +#include "llvm/Support/Dwarf.h" using namespace llvm; +using namespace llvm::dwarf; SPULinuxTargetAsmInfo::SPULinuxTargetAsmInfo(const SPUTargetMachine &TM) : SPUTargetAsmInfo(TM) { @@ -27,12 +29,34 @@ // This corresponds to what the gcc SPU compiler emits, for consistency. CStringSection = ".rodata.str"; + // Has leb128, .loc and .file + HasLEB128 = true; + HasDotLocAndDotFile = true; + // BSS section needs to be emitted as ".section" BSSSection = "\t.section\t.bss"; BSSSection_ = getUnnamedSection("\t.section\t.bss", SectionFlags::Writeable | SectionFlags::BSS, true); + SupportsDebugInformation = true; + NeedsSet = true; + SupportsMacInfoSection = false; + DwarfAbbrevSection = "\t.section .debug_abbrev,\"\", at progbits"; + DwarfInfoSection = "\t.section .debug_info,\"\", at progbits"; + DwarfLineSection = "\t.section .debug_line,\"\", at progbits"; + DwarfFrameSection = "\t.section .debug_frame,\"\", at progbits"; + DwarfPubNamesSection = "\t.section .debug_pubnames,\"\", at progbits"; + DwarfPubTypesSection = "\t.section .debug_pubtypes,\"\",progbits"; + DwarfStrSection = "\t.section .debug_str,\"MS\", at progbits,1"; + DwarfLocSection = "\t.section .debug_loc,\"\", at progbits"; + DwarfARangesSection = "\t.section .debug_aranges,\"\", at progbits"; + DwarfRangesSection = "\t.section .debug_ranges,\"\", at progbits"; + DwarfMacInfoSection = "\t.section .debug_macinfo,\"\",progbits"; + + // Exception handling is not supported on CellSPU (think about it: you only + // have 256K for code+data. Would you support exception handling?) + SupportsExceptionHandling = false; } /// PreferredEHDataFormat - This hook allows the target to select data From dalej at apple.com Mon Jan 26 17:21:31 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 26 Jan 2009 23:21:31 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63066 - /llvm-gcc-4.2/trunk/gcc/objc/objc-act.c Message-ID: <200901262321.n0QNLVof030325@zion.cs.uiuc.edu> Author: johannes Date: Mon Jan 26 17:21:30 2009 New Revision: 63066 URL: http://llvm.org/viewvc/llvm-project?rev=63066&view=rev Log: Fix for 5541393 caused a strong-cast write barrier not to be inserted in a case where it is needed (block-assigngcstrongcast.c in gcc testsuite). Block-pointer-type should be OK in this position and doesn't break anything in practice. Modified: llvm-gcc-4.2/trunk/gcc/objc/objc-act.c Modified: llvm-gcc-4.2/trunk/gcc/objc/objc-act.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/objc/objc-act.c?rev=63066&r1=63065&r2=63066&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/objc/objc-act.c (original) +++ llvm-gcc-4.2/trunk/gcc/objc/objc-act.c Mon Jan 26 17:21:30 2009 @@ -7514,11 +7514,12 @@ } /* APPLE LOCAL end radar 4426814 */ - /* LLVM LOCAL - begin 5541393 */ + /* LLVM LOCAL - begin 5541393 + 6522054 */ #ifdef ENABLE_LLVM - if (TREE_CODE(TREE_TYPE(lhs)) != POINTER_TYPE) return NULL_TREE; + if (TREE_CODE(TREE_TYPE(lhs)) != POINTER_TYPE && + TREE_CODE(TREE_TYPE(lhs)) != BLOCK_POINTER_TYPE) return NULL_TREE; #endif - /* LLVM LOCAL - end 5541393 */ + /* LLVM LOCAL - end 5541393 + 6522054 */ /* APPLE LOCAL begin ObjC GC */ /* Use the strong-cast write barrier as a last resort. */ if (warn_assign_intercept) From dalej at apple.com Mon Jan 26 17:22:20 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 26 Jan 2009 23:22:20 -0000 Subject: [llvm-commits] [llvm] r63067 - /llvm/trunk/test/FrontendObjC/2009-01-26-WriteBarrier-2.m Message-ID: <200901262322.n0QNMKPh030362@zion.cs.uiuc.edu> Author: johannes Date: Mon Jan 26 17:22:19 2009 New Revision: 63067 URL: http://llvm.org/viewvc/llvm-project?rev=63067&view=rev Log: Testcase for 6522054. Added: llvm/trunk/test/FrontendObjC/2009-01-26-WriteBarrier-2.m Added: llvm/trunk/test/FrontendObjC/2009-01-26-WriteBarrier-2.m URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendObjC/2009-01-26-WriteBarrier-2.m?rev=63067&view=auto ============================================================================== --- llvm/trunk/test/FrontendObjC/2009-01-26-WriteBarrier-2.m (added) +++ llvm/trunk/test/FrontendObjC/2009-01-26-WriteBarrier-2.m Mon Jan 26 17:22:19 2009 @@ -0,0 +1,14 @@ +// RUN: %llvmgcc -x objective-c -S %s -fobjc-gc -o - | grep objc_assign_strongCast +// rdar://5541393 + +typedef struct { + void (^ivarBlock)(void); +} StructWithBlock_t; + +int main(char *argc, char *argv[]) { + StructWithBlock_t *swbp = (StructWithBlock_t *)malloc(sizeof(StructWithBlock_t*)); + __block int i = 10; + // assigning a Block into an struct slot should elicit a write-barrier under GC + swbp->ivarBlock = ^ { ++i; }; + return 0; +} From evan.cheng at apple.com Mon Jan 26 17:22:15 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 26 Jan 2009 15:22:15 -0800 Subject: [llvm-commits] [llvm] r63008 - in /llvm/trunk: include/llvm/CodeGen/DebugLoc.h include/llvm/CodeGen/MachineFunction.h lib/CodeGen/MachineFunction.cpp In-Reply-To: <3CF8B982-5512-4854-BCA4-847689438D80@apple.com> References: <200901260741.n0Q7fnOn020226@zion.cs.uiuc.edu> <3CF8B982-5512-4854-BCA4-847689438D80@apple.com> Message-ID: No, there is no reason. I just forgot to clean it up. Evan On Jan 26, 2009, at 1:41 PM, Dan Gohman wrote: > > On Jan 25, 2009, at 11:41 PM, Evan Cheng wrote: >> >> + // NumDebugLocations - Size of the DebugLocations vector. >> + unsigned NumDebugLocations; >> + >> + // DebugLocations - A vector of unique DebugLocTuple's. >> + // >> + std::vector DebugLocations; > > Hi Evan, > > std::vector keeps track of its own size. Is it necessary to > keep a separate count of the number of elements? > > Dan > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon Jan 26 17:34:08 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 26 Jan 2009 15:34:08 -0800 Subject: [llvm-commits] [llvm] r63008 - in /llvm/trunk: include/llvm/CodeGen/DebugLoc.h include/llvm/CodeGen/MachineFunction.h lib/CodeGen/MachineFunction.cpp In-Reply-To: <517B4716-1012-43CB-8033-9D15F85548A6@apple.com> References: <200901260741.n0Q7fnOn020226@zion.cs.uiuc.edu> <517B4716-1012-43CB-8033-9D15F85548A6@apple.com> Message-ID: <557C3941-79AF-43DA-8B6A-AA164C9CF65C@apple.com> On Jan 26, 2009, at 1:57 PM, Devang Patel wrote: > > > Why not use SourceLineInfo directly instead of introducing > DebugLocTuple ? > > // > = > = > = > ----------------------------------------------------------------------= > ==// > /// SourceLineInfo - This class is used to record source line > correspondence. > /// > class SourceLineInfo { > unsigned Line; // Source line number. > unsigned Column; // Source column. > unsigned SourceID; // Source ID number. > unsigned LabelID; // Label in code ID number. > public > ... > > SourceLineInfo is managed using UniqueVector in DwarfWriter. Is > there a known reason to use DenseMap ? I'm just curious. Is there a way to look up the id given line, column, sourceid? It looks like DwarfWrite is just keeping a list of source lines so it can be dumped out at the end. There are obvious duplicates we need to get rid. I don't particularly care the way we use DwarfWriter to track debug info. It should be used to print dwarf, not managing debug info like it's doing right now. Evan > > - > Devan > >> >> + /// DebugLoc - Debug location id. This is carried by SDNode and >> + /// MachineInstr to index into a vector of unique debug location >> tuples. >> + class DebugLoc { >> + unsigned Idx; >> + >> + public: >> + DebugLoc() : Idx(~0U) {} >> + >> + static DebugLoc getNoDebugLoc() { DebugLoc L; L.Idx = 0; >> return L; } >> + static DebugLoc get(unsigned idx) { DebugLoc L; L.Idx = idx; >> return L; } >> + >> + bool isInvalid() { return Idx == ~0U; } >> + bool isUnknown() { return Idx == 0; } >> + }; >> + >> + struct DebugLocTupleDenseMapInfo { >> + static inline DebugLocTuple getEmptyKey() { >> + return DebugLocTuple(~0U, ~0U, ~0U); >> + } >> + static inline DebugLocTuple getTombstoneKey() { >> + return DebugLocTuple(~1U, ~1U, ~1U); >> + } >> + static unsigned getHashValue(const DebugLocTuple &Val) { >> + return DenseMapInfo::getHashValue(Val.FileId) ^ >> + DenseMapInfo::getHashValue(Val.Line) ^ >> + DenseMapInfo::getHashValue(Val.Col); >> + } >> + static bool isEqual(const DebugLocTuple &LHS, const >> DebugLocTuple &RHS) { >> + return LHS.FileId == RHS.FileId && >> + LHS.Line == RHS.Line && >> + LHS.Col == RHS.Col; >> + } >> + >> + static bool isPod() { return true; } >> + }; >> + >> + typedef DenseMap> DebugLocTupleDenseMapInfo> >> + DebugIdMapType; >> + >> + /// DebugLocTracker - This class tracks debug location >> information. >> + /// >> + struct DebugLocTracker { >> + // NumFilenames - Size of the DebugFilenames vector. >> + // >> + unsigned NumFilenames; >> + >> + // DebugFilenames - A vector of unique file names. >> + // >> + std::vector DebugFilenames; >> + >> + // DebugFilenamesMap - File name to DebugFilenames index map. >> + // >> + StringMap DebugFilenamesMap; >> + >> + // NumDebugLocations - Size of the DebugLocations vector. >> + unsigned NumDebugLocations; >> + >> + // DebugLocations - A vector of unique DebugLocTuple's. >> + // >> + std::vector DebugLocations; >> + >> + // DebugIdsMap - This maps DebugLocTuple's to indices into >> + // DebugLocations vector. >> + DebugIdMapType DebugIdMap; >> + >> + DebugLocTracker() : NumFilenames(0), NumDebugLocations(0) {} >> + >> + ~DebugLocTracker() { >> + NumFilenames = 0; >> + DebugFilenames.clear(); >> + DebugFilenamesMap.clear(); >> + DebugLocations.clear(); >> + DebugIdMap.clear(); >> + } >> + }; >> + >> +} // end namespace llvm >> + >> +#endif /* LLVM_CODEGEN_DEBUGLOC_H */ >> >> Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=63008&r1=63007&r2=63008&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original) >> +++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Mon Jan 26 >> 01:41:49 2009 >> @@ -19,6 +19,7 @@ >> #define LLVM_CODEGEN_MACHINEFUNCTION_H >> >> #include "llvm/ADT/ilist.h" >> +#include "llvm/CodeGen/DebugLoc.h" >> #include "llvm/CodeGen/MachineBasicBlock.h" >> #include "llvm/Support/Annotation.h" >> #include "llvm/Support/Allocator.h" >> @@ -27,11 +28,11 @@ >> namespace llvm { >> >> class Function; >> -class TargetMachine; >> class MachineRegisterInfo; >> class MachineFrameInfo; >> class MachineConstantPool; >> class MachineJumpTableInfo; >> +class TargetMachine; >> >> template <> >> struct ilist_traits >> @@ -94,6 +95,9 @@ >> typedef ilist BasicBlockListType; >> BasicBlockListType BasicBlocks; >> >> + // Tracks debug locations. >> + DebugLocTracker DebugLocInfo; >> + >> public: >> MachineFunction(const Function *Fn, const TargetMachine &TM); >> ~MachineFunction(); >> @@ -302,6 +306,15 @@ >> /// DeleteMachineBasicBlock - Delete the given MachineBasicBlock. >> /// >> void DeleteMachineBasicBlock(MachineBasicBlock *MBB); >> + >> + // >> = >> = >> = >> -------------------------------------------------------------------- >> ===// >> + // Debug location. >> + // >> + >> + /// lookUpDebugLocId - Look up the DebugLocTuple index with the >> given >> + /// filename, line, and column. It may add a new filename and / or >> + /// a new DebugLocTuple. >> + unsigned lookUpDebugLocId(const char *Filename, unsigned Line, >> unsigned Col); >> }; >> >> // >> = >> = >> = >> -------------------------------------------------------------------- >> ===// >> >> Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=63008&r1=63007&r2=63008&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original) >> +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Mon Jan 26 01:41:49 >> 2009 >> @@ -378,6 +378,33 @@ >> return *mc; >> } >> >> +/// lookUpDebugLocId - Look up the DebugLocTuple index with the >> given >> +/// filename, line, and column. It may add a new filename and / or >> +/// a new DebugLocTuple. >> +unsigned MachineFunction::lookUpDebugLocId(const char *Filename, >> unsigned Line, >> + unsigned Col) { >> + unsigned FileId; >> + StringMap::iterator I = >> + DebugLocInfo.DebugFilenamesMap.find(Filename); >> + if (I != DebugLocInfo.DebugFilenamesMap.end()) >> + FileId = I->second; >> + else { >> + // Add a new filename. >> + FileId = DebugLocInfo.NumFilenames++; >> + DebugLocInfo.DebugFilenames.push_back(Filename); >> + DebugLocInfo.DebugFilenamesMap[Filename] = FileId; >> + } >> + >> + struct DebugLocTuple Tuple(FileId, Line, Col); >> + DebugIdMapType::iterator II = DebugLocInfo.DebugIdMap.find(Tuple); >> + if (II != DebugLocInfo.DebugIdMap.end()) >> + return II->second; >> + // Add a new tuple. >> + DebugLocInfo.DebugLocations.push_back(Tuple); >> + DebugLocInfo.DebugIdMap[Tuple] = DebugLocInfo.NumDebugLocations; >> + return DebugLocInfo.NumDebugLocations++; >> +} >> + >> // >> = >> = >> = >> ----------------------------------------------------------------------= >> ==// >> // MachineFrameInfo implementation >> // >> = >> = >> = >> ----------------------------------------------------------------------= >> ==// >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090126/5cd12987/attachment.html From evan.cheng at apple.com Mon Jan 26 17:47:31 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 26 Jan 2009 23:47:31 -0000 Subject: [llvm-commits] [llvm] r63070 - in /llvm/trunk: include/llvm/CodeGen/DebugLoc.h lib/CodeGen/MachineFunction.cpp Message-ID: <200901262347.n0QNlVfU031144@zion.cs.uiuc.edu> Author: evancheng Date: Mon Jan 26 17:47:30 2009 New Revision: 63070 URL: http://llvm.org/viewvc/llvm-project?rev=63070&view=rev Log: No need to keep size of DebugLocations vector separately. Modified: llvm/trunk/include/llvm/CodeGen/DebugLoc.h llvm/trunk/lib/CodeGen/MachineFunction.cpp Modified: llvm/trunk/include/llvm/CodeGen/DebugLoc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DebugLoc.h?rev=63070&r1=63069&r2=63070&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/DebugLoc.h (original) +++ llvm/trunk/include/llvm/CodeGen/DebugLoc.h Mon Jan 26 17:47:30 2009 @@ -69,9 +69,6 @@ /// DebugLocTracker - This class tracks debug location information. /// struct DebugLocTracker { - // NumDebugLocations - Size of the DebugLocations vector. - unsigned NumDebugLocations; - // DebugLocations - A vector of unique DebugLocTuple's. // std::vector DebugLocations; @@ -80,7 +77,7 @@ // DebugLocations vector. DebugIdMapType DebugIdMap; - DebugLocTracker() : NumDebugLocations(0) {} + DebugLocTracker() {} ~DebugLocTracker() { DebugLocations.clear(); Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=63070&r1=63069&r2=63070&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Mon Jan 26 17:47:30 2009 @@ -388,9 +388,10 @@ if (II != DebugLocInfo.DebugIdMap.end()) return II->second; // Add a new tuple. + unsigned Id = DebugLocInfo.DebugLocations.size(); DebugLocInfo.DebugLocations.push_back(Tuple); - DebugLocInfo.DebugIdMap[Tuple] = DebugLocInfo.NumDebugLocations; - return DebugLocInfo.NumDebugLocations++; + DebugLocInfo.DebugIdMap[Tuple] = Id; + return Id; } //===----------------------------------------------------------------------===// From dpatel at apple.com Mon Jan 26 17:47:39 2009 From: dpatel at apple.com (Devang Patel) Date: Mon, 26 Jan 2009 15:47:39 -0800 Subject: [llvm-commits] [llvm] r63008 - in /llvm/trunk: include/llvm/CodeGen/DebugLoc.h include/llvm/CodeGen/MachineFunction.h lib/CodeGen/MachineFunction.cpp In-Reply-To: <557C3941-79AF-43DA-8B6A-AA164C9CF65C@apple.com> References: <200901260741.n0Q7fnOn020226@zion.cs.uiuc.edu> <517B4716-1012-43CB-8033-9D15F85548A6@apple.com> <557C3941-79AF-43DA-8B6A-AA164C9CF65C@apple.com> Message-ID: <403F9866-8E24-4629-B945-223AB061F2F6@apple.com> On Jan 26, 2009, at 3:34 PM, Evan Cheng wrote: > > On Jan 26, 2009, at 1:57 PM, Devang Patel wrote: > >> >> >> Why not use SourceLineInfo directly instead of introducing >> DebugLocTuple ? >> >> // >> = >> = >> = >> ----------------------------------------------------------------------= >> ==// >> /// SourceLineInfo - This class is used to record source line >> correspondence. >> /// >> class SourceLineInfo { >> unsigned Line; // Source line number. >> unsigned Column; // Source column. >> unsigned SourceID; // Source ID number. >> unsigned LabelID; // Label in code ID number. >> public >> ... >> >> SourceLineInfo is managed using UniqueVector in DwarfWriter. Is >> there a known reason to use DenseMap ? I'm just curious. > > > Is there a way to look up the id given line, column, sourceid? It > looks like DwarfWrite is just keeping a list of source lines so it > can be dumped out at the end. It does not need to query, so no it does not have a way to look up the id given line, column, sourceid. It has a way to look up sourceid based on file name and directory, which can be reused. > There are obvious duplicates we need to get rid. Now, SourceLineInfo is nearly identical to newly added DebugLocTuple. > I don't particularly care the way we use DwarfWriter to track debug > info. It should be used to print dwarf, not managing debug info like > it's doing right now. I am not sure I understand here. AFAIU, DwarfWriter's DwarfDebug does not try to manage debug info. - Devang -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090126/b745caba/attachment.html From clattner at apple.com Mon Jan 26 17:56:26 2009 From: clattner at apple.com (Chris Lattner) Date: Mon, 26 Jan 2009 15:56:26 -0800 Subject: [llvm-commits] [llvm] r63044 - in /llvm/trunk: include/llvm/Support/raw_ostream.h lib/Support/raw_ostream.cpp In-Reply-To: <200901262142.n0QLg4XL026404@zion.cs.uiuc.edu> References: <200901262142.n0QLg4XL026404@zion.cs.uiuc.edu> Message-ID: <0E6FAC36-11B2-485C-9DA0-CA7579F10DE0@apple.com> On Jan 26, 2009, at 1:42 PM, Ted Kremenek wrote: > Author: kremenek > Date: Mon Jan 26 15:42:04 2009 > New Revision: 63044 > > URL: http://llvm.org/viewvc/llvm-project?rev=63044&view=rev > Log: > Add method raw_fd_ostream::seek() for random access within a file. Huh? But now it's not a stream! I guess it is ok as long as only raw_fd_ostream has this and not all raw_ostreams do. -Chris > > > Modified: > llvm/trunk/include/llvm/Support/raw_ostream.h > llvm/trunk/lib/Support/raw_ostream.cpp > > Modified: llvm/trunk/include/llvm/Support/raw_ostream.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/raw_ostream.h?rev=63044&r1=63043&r2=63044&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Support/raw_ostream.h (original) > +++ llvm/trunk/include/llvm/Support/raw_ostream.h Mon Jan 26 > 15:42:04 2009 > @@ -181,7 +181,11 @@ > /// tell - Return the current offset with the file. > uint64_t tell() { > return pos + (OutBufCur - OutBufStart); > - } > + } > + > + /// seek - Flushes the stream and repositions the underlying file > descriptor > + /// positition to the offset specified from the beginning of the > file. > + uint64_t seek(uint64_t off); > }; > > /// raw_stdout_ostream - This is a stream that always prints to > stdout. > > Modified: llvm/trunk/lib/Support/raw_ostream.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/raw_ostream.cpp?rev=63044&r1=63043&r2=63044&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Support/raw_ostream.cpp (original) > +++ llvm/trunk/lib/Support/raw_ostream.cpp Mon Jan 26 15:42:04 2009 > @@ -255,6 +255,12 @@ > FD = -1; > } > > +uint64_t raw_fd_ostream::seek(uint64_t off) { > + flush(); > + pos = lseek(FD, off, SEEK_SET); > + return pos; > +} > + > // > = > = > = > ----------------------------------------------------------------------= > ==// > // raw_stdout/err_ostream > // > = > = > = > ----------------------------------------------------------------------= > ==// > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Mon Jan 26 18:00:09 2009 From: clattner at apple.com (Chris Lattner) Date: Mon, 26 Jan 2009 16:00:09 -0800 Subject: [llvm-commits] [llvm] r63056 - in /llvm/trunk: include/llvm/Target/TargetOptions.h lib/Target/TargetMachine.cpp lib/Target/X86/X86RegisterInfo.cpp In-Reply-To: <200901262222.n0QMMWix028199@zion.cs.uiuc.edu> References: <200901262222.n0QMMWix028199@zion.cs.uiuc.edu> Message-ID: On Jan 26, 2009, at 2:22 PM, Dan Gohman wrote: > Author: djg > Date: Mon Jan 26 16:22:31 2009 > New Revision: 63056 > > URL: http://llvm.org/viewvc/llvm-project?rev=63056&view=rev > Log: > Implement Red Zone utilization on x86-64. This is currently > disabled by default; I'll enable it when I hook it up with > the llvm-gcc flag which controls it. When would you ever want to disable it? -Chris From gohman at apple.com Mon Jan 26 18:37:11 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 27 Jan 2009 00:37:11 -0000 Subject: [llvm-commits] [llvm] r63073 - /llvm/trunk/test/Transforms/IndMemRem/ Message-ID: <200901270037.n0R0bCHw032725@zion.cs.uiuc.edu> Author: djg Date: Mon Jan 26 18:37:09 2009 New Revision: 63073 URL: http://llvm.org/viewvc/llvm-project?rev=63073&view=rev Log: Add an svn:ignore property. Modified: llvm/trunk/test/Transforms/IndMemRem/ (props changed) Propchange: llvm/trunk/test/Transforms/IndMemRem/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Jan 26 18:37:09 2009 @@ -0,0 +1 @@ +Output From gohman at apple.com Mon Jan 26 18:40:07 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 27 Jan 2009 00:40:07 -0000 Subject: [llvm-commits] [llvm] r63074 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <200901270040.n0R0e7ER000375@zion.cs.uiuc.edu> Author: djg Date: Mon Jan 26 18:40:06 2009 New Revision: 63074 URL: http://llvm.org/viewvc/llvm-project?rev=63074&view=rev Log: Fix the Red Zone calculation for functions with frame pointers. Don't use the Red Zone when dynamic stack realignment is needed. This could be implemented, but most x86-64 ABIs don't require dynamic stack realignment so it isn't urgent. Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=63074&r1=63073&r2=63074&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon Jan 26 18:40:06 2009 @@ -721,24 +721,27 @@ // Get desired stack alignment uint64_t MaxAlign = MFI->getMaxAlignment(); + // Add RETADDR move area to callee saved frame size. + int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); + if (TailCallReturnAddrDelta < 0) + X86FI->setCalleeSavedFrameSize( + X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta)); + // If this is x86-64 and the Red Zone is not disabled, if we are a leaf // function, and use up to 128 bytes of stack space, don't have a frame // pointer, calls, or dynamic alloca then we do not need to adjust the // stack pointer (we fit in the Red Zone). if (Is64Bit && !DisableRedZone && + !needsStackRealignment(MF) && !MFI->hasVarSizedObjects() && // No dynamic alloca. !MFI->hasCalls()) { // No calls. - StackSize = std::max((uint64_t)X86FI->getCalleeSavedFrameSize(), + uint64_t MinSize = X86FI->getCalleeSavedFrameSize(); + if (hasFP(MF)) MinSize += SlotSize; + StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0); MFI->setStackSize(StackSize); } - // Add RETADDR move area to callee saved frame size. - int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); - if (TailCallReturnAddrDelta < 0) - X86FI->setCalleeSavedFrameSize( - X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta)); - // Insert stack pointer adjustment for later moving of return addr. Only // applies to tail call optimized functions where the callee argument stack // size is bigger than the callers. From gohman at apple.com Mon Jan 26 18:40:28 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 27 Jan 2009 00:40:28 -0000 Subject: [llvm-commits] [llvm] r63075 - /llvm/trunk/test/CodeGen/X86/red-zone.ll Message-ID: <200901270040.n0R0eSxU000396@zion.cs.uiuc.edu> Author: djg Date: Mon Jan 26 18:40:27 2009 New Revision: 63075 URL: http://llvm.org/viewvc/llvm-project?rev=63075&view=rev Log: Add a regression test for x86-64 red zone usage. Added: llvm/trunk/test/CodeGen/X86/red-zone.ll Added: llvm/trunk/test/CodeGen/X86/red-zone.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/red-zone.ll?rev=63075&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/red-zone.ll (added) +++ llvm/trunk/test/CodeGen/X86/red-zone.ll Mon Jan 26 18:40:27 2009 @@ -0,0 +1,13 @@ +; RUN: llvm-as < %s | llc -march=x86-64 > %t +; RUN: not grep subq %t +; RUN: not grep addq %t +; RUN: grep {\\-4(%%rsp)} %t | count 2 +; RUN: llvm-as < %s | llc -march=x86-64 -disable-red-zone > %t +; RUN: grep subq %t | count 1 +; RUN: grep addq %t | count 1 + +define x86_fp80 @f0(float %f) nounwind readnone { +entry: + %0 = fpext float %f to x86_fp80 ; [#uses=1] + ret x86_fp80 %0 +} From gohman at apple.com Mon Jan 26 18:42:11 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 27 Jan 2009 00:42:11 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63076 - in /llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386-target.h llvm-backend.cpp Message-ID: <200901270042.n0R0gBEq000456@zion.cs.uiuc.edu> Author: djg Date: Mon Jan 26 18:42:11 2009 New Revision: 63076 URL: http://llvm.org/viewvc/llvm-project?rev=63076&view=rev Log: Translate GCC's -mno-red-zone option to LLVM's -disable-red-zone option. Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=63076&r1=63075&r2=63076&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Mon Jan 26 18:42:11 2009 @@ -89,6 +89,10 @@ } \ } +#define LLVM_SET_ARCH_OPTIONS(argvec) \ + if (TARGET_NO_RED_ZONE) \ + argvec.push_back("--disable-red-zone"); + #ifdef LLVM_ABI_H /* On x86-32 objects containing SSE vectors are 16 byte aligned, everything Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=63076&r1=63075&r2=63076&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Mon Jan 26 18:42:11 2009 @@ -131,6 +131,9 @@ // Allow targets to specify PIC options and other stuff to the corresponding // LLVM backends. +#ifdef LLVM_SET_ARCH_OPTIONS + LLVM_SET_ARCH_OPTIONS(Args); +#endif #ifdef LLVM_SET_TARGET_OPTIONS LLVM_SET_TARGET_OPTIONS(Args); #endif From evan.cheng at apple.com Mon Jan 26 18:44:21 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 26 Jan 2009 16:44:21 -0800 Subject: [llvm-commits] [llvm] r63008 - in /llvm/trunk: include/llvm/CodeGen/DebugLoc.h include/llvm/CodeGen/MachineFunction.h lib/CodeGen/MachineFunction.cpp In-Reply-To: <403F9866-8E24-4629-B945-223AB061F2F6@apple.com> References: <200901260741.n0Q7fnOn020226@zion.cs.uiuc.edu> <517B4716-1012-43CB-8033-9D15F85548A6@apple.com> <557C3941-79AF-43DA-8B6A-AA164C9CF65C@apple.com> <403F9866-8E24-4629-B945-223AB061F2F6@apple.com> Message-ID: <9DB4C927-39DB-475F-A94F-7C0283A6364E@apple.com> On Jan 26, 2009, at 3:47 PM, Devang Patel wrote: > > On Jan 26, 2009, at 3:34 PM, Evan Cheng wrote: > >> >> On Jan 26, 2009, at 1:57 PM, Devang Patel wrote: >> >>> >>> >>> Why not use SourceLineInfo directly instead of introducing >>> DebugLocTuple ? >>> >>> // >>> = >>> = >>> = >>> ----------------------------------------------------------------------= >>> ==// >>> /// SourceLineInfo - This class is used to record source line >>> correspondence. >>> /// >>> class SourceLineInfo { >>> unsigned Line; // Source line number. >>> unsigned Column; // Source column. >>> unsigned SourceID; // Source ID number. >>> unsigned LabelID; // Label in code ID number. >>> public >>> ... >>> >>> SourceLineInfo is managed using UniqueVector in DwarfWriter. Is >>> there a known reason to use DenseMap ? I'm just curious. >> >> >> Is there a way to look up the id given line, column, sourceid? It >> looks like DwarfWrite is just keeping a list of source lines so it >> can be dumped out at the end. > > It does not need to query, so no it does not have a way to look up > the id given line, column, sourceid. It has a way to look up > sourceid based on file name and directory, which can be reused. It is. > >> There are obvious duplicates we need to get rid. > > Now, SourceLineInfo is nearly identical to newly added DebugLocTuple. Yes, stuff in MachineModuleInfo should be eliminated or moved elsewhere. > >> I don't particularly care the way we use DwarfWriter to track debug >> info. It should be used to print dwarf, not managing debug info >> like it's doing right now. > > I am not sure I understand here. AFAIU, DwarfWriter's DwarfDebug > does not try to manage debug info. There are basically 2 parts of debug info (in codegen). There is the actually dwarf writing, which obviously DwarfWriter should do. Then there is code that validate debug info (e.g. ValidDebugInfo), track file name to id mapping, map labels, etc. Some of it is in dwarf writer, some in machine module info. These probably should go to a separate class. Then we can merge DebugLoc in it. Does that make sense? Evan > > - > Devang > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090126/4244c72f/attachment.html From evan.cheng at apple.com Mon Jan 26 18:44:53 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 26 Jan 2009 16:44:53 -0800 Subject: [llvm-commits] [llvm] r63056 - in /llvm/trunk: include/llvm/Target/TargetOptions.h lib/Target/TargetMachine.cpp lib/Target/X86/X86RegisterInfo.cpp In-Reply-To: References: <200901262222.n0QMMWix028199@zion.cs.uiuc.edu> Message-ID: <1E8708C8-CF55-46EC-B1AE-D8E863068C9A@apple.com> Kernle mode. Evan On Jan 26, 2009, at 4:00 PM, Chris Lattner wrote: > > On Jan 26, 2009, at 2:22 PM, Dan Gohman wrote: > >> Author: djg >> Date: Mon Jan 26 16:22:31 2009 >> New Revision: 63056 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=63056&view=rev >> Log: >> Implement Red Zone utilization on x86-64. This is currently >> disabled by default; I'll enable it when I hook it up with >> the llvm-gcc flag which controls it. > > When would you ever want to disable it? > > -Chris > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Mon Jan 26 18:45:05 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 27 Jan 2009 00:45:05 -0000 Subject: [llvm-commits] [llvm] r63077 - in /llvm/trunk: lib/CodeGen/AsmPrinter/DwarfWriter.cpp test/DebugInfo/forwardDecl.ll Message-ID: <200901270045.n0R0j57e000544@zion.cs.uiuc.edu> Author: dpatel Date: Mon Jan 26 18:45:04 2009 New Revision: 63077 URL: http://llvm.org/viewvc/llvm-project?rev=63077&view=rev Log: Assorted debug info fixes. - DW_AT_bit_size is only suitable for bitfields. - Encode source location info for derived types. - Source location and type size info is not useful for subroutine_type (info is included in respective DISubprogram) and array_type. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp llvm/trunk/test/DebugInfo/forwardDecl.ll Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=63077&r1=63076&r2=63077&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Mon Jan 26 18:45:04 2009 @@ -1733,8 +1733,8 @@ // Add source line info if available and TyDesc is not a forward // declaration. - // FIXME - Enable this. if (!DTy.isForwardDecl()) - // FIXME - Enable this. AddSourceLine(&Buffer, *DTy); + if (!DTy.isForwardDecl()) + AddSourceLine(&Buffer, &DTy); } /// ConstructTypeDIE - Construct type DIE from DICompositeType. @@ -1815,20 +1815,23 @@ // Add name if not anonymous or intermediate type. if (!Name.empty()) AddString(&Buffer, DW_AT_name, DW_FORM_string, Name); - // Add size if non-zero (derived types might be zero-sized.) - if (Size) - AddUInt(&Buffer, DW_AT_byte_size, 0, Size); - else { - // Add zero size if it is not a forward declaration. - if (CTy.isForwardDecl()) - AddUInt(&Buffer, DW_AT_declaration, DW_FORM_flag, 1); - else - AddUInt(&Buffer, DW_AT_byte_size, 0, 0); + if (Tag == DW_TAG_enumeration_type || Tag == DW_TAG_structure_type + || Tag == DW_TAG_union_type) { + // Add size if non-zero (derived types might be zero-sized.) + if (Size) + AddUInt(&Buffer, DW_AT_byte_size, 0, Size); + else { + // Add zero size if it is not a forward declaration. + if (CTy.isForwardDecl()) + AddUInt(&Buffer, DW_AT_declaration, DW_FORM_flag, 1); + else + AddUInt(&Buffer, DW_AT_byte_size, 0, 0); + } + + // Add source line info if available. + if (!CTy.isForwardDecl()) + AddSourceLine(&Buffer, &CTy); } - - // Add source line info if available. - if (!CTy.isForwardDecl()) - AddSourceLine(&Buffer, &CTy); } // ConstructSubrangeDIE - Construct subrange DIE from DISubrange. @@ -1853,7 +1856,6 @@ AddUInt(&Buffer, DW_AT_GNU_vector, DW_FORM_flag, 1); DIArray Elements = CTy->getTypeArray(); - AddType(DW_Unit, &Buffer, CTy->getTypeDerivedFrom()); // Construct an anonymous type for index type. DIE IdxBuffer(DW_TAG_base_type); @@ -1906,7 +1908,7 @@ AddSourceLine(MemberDie, &DT); - AddUInt(MemberDie, DW_AT_bit_size, 0, DT.getSizeInBits()); + // FIXME _ Handle bitfields DIEBlock *Block = new DIEBlock(); AddUInt(Block, 0, DW_FORM_data1, DW_OP_plus_uconst); AddUInt(Block, 0, DW_FORM_udata, DT.getOffsetInBits() >> 3); Modified: llvm/trunk/test/DebugInfo/forwardDecl.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/forwardDecl.ll?rev=63077&r1=63076&r2=63077&view=diff ============================================================================== --- llvm/trunk/test/DebugInfo/forwardDecl.ll (original) +++ llvm/trunk/test/DebugInfo/forwardDecl.ll Mon Jan 26 18:45:04 2009 @@ -18,7 +18,7 @@ @.str3 = internal constant [4 x i8] c"foo\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] @llvm.dbg.variable = internal constant %llvm.dbg.variable.type { i32 393473, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([2 x i8]* @.str4, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 3, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=1] @.str4 = internal constant [2 x i8] c"x\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1] - at llvm.dbg.derivedtype = internal constant %llvm.dbg.derivedtype.type { i32 393231, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.derivedtype = internal constant %llvm.dbg.derivedtype.type { i32 393231, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] @llvm.dbg.compositetype = internal constant %llvm.dbg.compositetype.type { i32 393235, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([3 x i8]* @.str5, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 1, i64 0, i64 8, i64 0, i32 4, { }* null, { }* bitcast ([0 x { }*]* @llvm.dbg.array to { }*) }, section "llvm.metadata" ; <%llvm.dbg.compositetype.type*> [#uses=1] @.str5 = internal constant [3 x i8] c"ST\00", section "llvm.metadata" ; <[3 x i8]*> [#uses=1] @llvm.dbg.array = internal constant [0 x { }*] zeroinitializer, section "llvm.metadata" ; <[0 x { }*]*> [#uses=1] From dpatel at apple.com Mon Jan 26 18:56:10 2009 From: dpatel at apple.com (Devang Patel) Date: Mon, 26 Jan 2009 16:56:10 -0800 Subject: [llvm-commits] [llvm] r63008 - in /llvm/trunk: include/llvm/CodeGen/DebugLoc.h include/llvm/CodeGen/MachineFunction.h lib/CodeGen/MachineFunction.cpp In-Reply-To: <9DB4C927-39DB-475F-A94F-7C0283A6364E@apple.com> References: <200901260741.n0Q7fnOn020226@zion.cs.uiuc.edu> <517B4716-1012-43CB-8033-9D15F85548A6@apple.com> <557C3941-79AF-43DA-8B6A-AA164C9CF65C@apple.com> <403F9866-8E24-4629-B945-223AB061F2F6@apple.com> <9DB4C927-39DB-475F-A94F-7C0283A6364E@apple.com> Message-ID: <8E41BDC8-566B-429A-8A10-369B239A3BCC@apple.com> >>> I don't particularly care the way we use DwarfWriter to track >>> debug info. It should be used to print dwarf, not managing debug >>> info like it's doing right now. >> >> I am not sure I understand here. AFAIU, DwarfWriter's DwarfDebug >> does not try to manage debug info. > > There are basically 2 parts of debug info (in codegen). There is the > actually dwarf writing, which obviously DwarfWriter should do. (Just to avoid confusion : DwarfDebug info emits debug info. DwarfWriter also includes DwarfException which emits EH info.) > Then there is code that validate debug info (e.g. ValidDebugInfo), This only validates dbg values at LLVM IR level. Ideally this should be part of Verifier. I put it here, for now, to side step circular dependencies :) > track file name to id mapping, map labels, etc. Some of it is in > dwarf writer, some in machine module info. labels are managed by machine module info. > These probably should go to a separate class. Then we can merge > DebugLoc in it. Does that make sense? id mapping can be moved in to DebugLoc and we can use one struct to collect info, whether you name it as SourceLineInfo or DebugLocTuple - Devang From gohman at apple.com Mon Jan 26 18:58:48 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 27 Jan 2009 00:58:48 -0000 Subject: [llvm-commits] [llvm] r63078 - /llvm/trunk/lib/Target/TargetMachine.cpp Message-ID: <200901270058.n0R0wm7D000961@zion.cs.uiuc.edu> Author: djg Date: Mon Jan 26 18:58:47 2009 New Revision: 63078 URL: http://llvm.org/viewvc/llvm-project?rev=63078&view=rev Log: Enable the red zone on x86-64 by default. Modified: llvm/trunk/lib/Target/TargetMachine.cpp Modified: llvm/trunk/lib/Target/TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=63078&r1=63077&r2=63078&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/TargetMachine.cpp Mon Jan 26 18:58:47 2009 @@ -169,7 +169,7 @@ DisableRedZoneOption("disable-red-zone", cl::desc("Do not emit code that uses the red zone."), cl::location(DisableRedZone), - cl::init(true)); + cl::init(false)); //--------------------------------------------------------------------------- // TargetMachine Class From gohman at apple.com Mon Jan 26 18:59:55 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 27 Jan 2009 00:59:55 -0000 Subject: [llvm-commits] [llvm] r63079 - /llvm/trunk/test/FrontendC/x86-64-red-zone.c Message-ID: <200901270059.n0R0xt3h001002@zion.cs.uiuc.edu> Author: djg Date: Mon Jan 26 18:59:55 2009 New Revision: 63079 URL: http://llvm.org/viewvc/llvm-project?rev=63079&view=rev Log: Add a FrontendC testcase for the x86-64 Red Zone feature, to help verify that the feature may be disabled through the -mno-red-zone option. Added: llvm/trunk/test/FrontendC/x86-64-red-zone.c Added: llvm/trunk/test/FrontendC/x86-64-red-zone.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/x86-64-red-zone.c?rev=63079&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/x86-64-red-zone.c (added) +++ llvm/trunk/test/FrontendC/x86-64-red-zone.c Mon Jan 26 18:59:55 2009 @@ -0,0 +1,11 @@ +// RUN: $llvmgcc -m64 -fomit-frame-pointer -O2 %s -S -o - > %t +// RUN: not grep subq %t +// RUN: not grep addq %t +// RUN: grep {\\-4(%%rsp)} %t | count 2 +// RUN: $llvmgcc -m64 -fomit-frame-pointer -O2 %s -S -o - -mno-red-zone > %t +// RUN: grep subq %t | count 1 +// RUN: grep addq %t | count 1 +// This is a test for x86-64, add your target below if it FAILs. +// XFAIL: alpha|ia64|arm|powerpc|sparc|x86 + +long double f0(float f) { return f; } From clattner at apple.com Mon Jan 26 19:21:36 2009 From: clattner at apple.com (Chris Lattner) Date: Mon, 26 Jan 2009 17:21:36 -0800 Subject: [llvm-commits] [llvm] r63056 - in /llvm/trunk: include/llvm/Target/TargetOptions.h lib/Target/TargetMachine.cpp lib/Target/X86/X86RegisterInfo.cpp In-Reply-To: <1E8708C8-CF55-46EC-B1AE-D8E863068C9A@apple.com> References: <200901262222.n0QMMWix028199@zion.cs.uiuc.edu> <1E8708C8-CF55-46EC-B1AE-D8E863068C9A@apple.com> Message-ID: <79584A50-9E25-43C4-A4C6-7F087CDD66C1@apple.com> On Jan 26, 2009, at 4:44 PM, Evan Cheng wrote: > Kernle mode. Aha, ok. -Chris > > > Evan > On Jan 26, 2009, at 4:00 PM, Chris Lattner wrote: > >> >> On Jan 26, 2009, at 2:22 PM, Dan Gohman wrote: >> >>> Author: djg >>> Date: Mon Jan 26 16:22:31 2009 >>> New Revision: 63056 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=63056&view=rev >>> Log: >>> Implement Red Zone utilization on x86-64. This is currently >>> disabled by default; I'll enable it when I hook it up with >>> the llvm-gcc flag which controls it. >> >> When would you ever want to disable it? >> >> -Chris >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From kremenek at apple.com Mon Jan 26 19:23:46 2009 From: kremenek at apple.com (Ted Kremenek) Date: Tue, 27 Jan 2009 01:23:46 -0000 Subject: [llvm-commits] [llvm] r63081 - /llvm/tags/checker/checker-0.145/ Message-ID: <200901270123.n0R1Nku1001709@zion.cs.uiuc.edu> Author: kremenek Date: Mon Jan 26 19:23:45 2009 New Revision: 63081 URL: http://llvm.org/viewvc/llvm-project?rev=63081&view=rev Log: Tagging checker-0.145. Added: llvm/tags/checker/checker-0.145/ - copied from r63080, llvm/trunk/ From dalej at apple.com Mon Jan 26 20:02:36 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 27 Jan 2009 02:02:36 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63087 - /llvm-gcc-4.2/trunk/gcc/tree-nested.c Message-ID: <200901270202.n0R22aB6002964@zion.cs.uiuc.edu> Author: johannes Date: Mon Jan 26 20:02:36 2009 New Revision: 63087 URL: http://llvm.org/viewvc/llvm-project?rev=63087&view=rev Log: Fix g++.apple/blocks-in_structors.c on Darwin. This allows a null "root" in initialize_chains, and removes a mysterious llvm assert in convert_all_function_calls. Both situtations seem to occur legitimately in this example, and nothing in the testsuite breaks. Modified: llvm-gcc-4.2/trunk/gcc/tree-nested.c Modified: llvm-gcc-4.2/trunk/gcc/tree-nested.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/tree-nested.c?rev=63087&r1=63086&r2=63087&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/tree-nested.c (original) +++ llvm-gcc-4.2/trunk/gcc/tree-nested.c Mon Jan 26 20:02:36 2009 @@ -1732,7 +1732,7 @@ static void initialize_chains (struct nesting_info *root) { - do + while (root) { if (root->inner) initialize_chains (root->inner); @@ -1747,7 +1747,6 @@ root = root->next; } - while (root); } /* Helper for propagate_chains. Set the chain flag on a function and all of @@ -1972,20 +1971,11 @@ walk_function (convert_tramp_reference, root); walk_function (convert_call_expr, root); - /* LLVM LOCAL begin */ - /* FIXME: Keep the LLVM-way? */ -#ifdef ENABLE_LLVM - gcc_assert (!root->outer || - DECL_NO_STATIC_CHAIN (root->context) == - !(root->chain_decl || root->chain_field)); -#else /* If the function does not use a static chain, then remember that. */ if (root->outer && !root->chain_decl && !root->chain_field) DECL_NO_STATIC_CHAIN (root->context) = 1; else gcc_assert (!DECL_NO_STATIC_CHAIN (root->context)); -#endif - /* LLVM LOCAL end */ root = root->next; } From gohman at apple.com Mon Jan 26 20:37:43 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 27 Jan 2009 02:37:43 -0000 Subject: [llvm-commits] [llvm] r63088 - /llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Message-ID: <200901270237.n0R2bhAx003999@zion.cs.uiuc.edu> Author: djg Date: Mon Jan 26 20:37:43 2009 New Revision: 63088 URL: http://llvm.org/viewvc/llvm-project?rev=63088&view=rev Log: Eliminate unnecessary operands-list traversals. Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=63088&r1=63087&r2=63088&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Jan 26 20:37:43 2009 @@ -242,12 +242,9 @@ static SDNode *findFlagUse(SDNode *N) { unsigned FlagResNo = N->getNumValues()-1; for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { - SDNode *User = *I; - for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { - SDValue Op = User->getOperand(i); - if (Op.getNode() == N && Op.getResNo() == FlagResNo) - return User; - } + SDUse &Use = I.getUse(); + if (Use.getResNo() == FlagResNo) + return Use.getUser(); } return NULL; } From evan.cheng at apple.com Mon Jan 26 20:59:40 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 27 Jan 2009 02:59:40 -0000 Subject: [llvm-commits] [llvm] r63089 - /llvm/trunk/test/FrontendC/implicit-arg.c Message-ID: <200901270259.n0R2xei1004658@zion.cs.uiuc.edu> Author: evancheng Date: Mon Jan 26 20:59:39 2009 New Revision: 63089 URL: http://llvm.org/viewvc/llvm-project?rev=63089&view=rev Log: Forgot this test case. Added: llvm/trunk/test/FrontendC/implicit-arg.c Added: llvm/trunk/test/FrontendC/implicit-arg.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/implicit-arg.c?rev=63089&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/implicit-arg.c (added) +++ llvm/trunk/test/FrontendC/implicit-arg.c Mon Jan 26 20:59:39 2009 @@ -0,0 +1,10 @@ +// RUN: %llvmgcc %s -S -emit-llvm -O0 -o - +// RUN: %llvmgcc %s -S -emit-llvm -O1 -o - +// rdar://6518089 + +static int bar(); +void foo() { + int a = bar(); +} +int bar(unsigned a) { +} From evan.cheng at apple.com Mon Jan 26 21:30:42 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 27 Jan 2009 03:30:42 -0000 Subject: [llvm-commits] [llvm] r63090 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/smul-with-overflow-2.ll Message-ID: <200901270330.n0R3UgVN005529@zion.cs.uiuc.edu> Author: evancheng Date: Mon Jan 26 21:30:42 2009 New Revision: 63090 URL: http://llvm.org/viewvc/llvm-project?rev=63090&view=rev Log: Implement multiple with overflow by 2 with an add instruction. Added: llvm/trunk/test/CodeGen/X86/smul-with-overflow-2.ll Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=63090&r1=63089&r2=63090&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Jan 26 21:30:42 2009 @@ -3612,6 +3612,17 @@ (implicit EFLAGS)), (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; +// Optimize multiple with overflow by 2. +let AddedComplexity = 2 in { +def : Pat<(parallel (X86smul_ovf GR16:$src1, 2), + (implicit EFLAGS)), + (ADD16rr GR16:$src1, GR16:$src1)>; + +def : Pat<(parallel (X86smul_ovf GR32:$src1, 2), + (implicit EFLAGS)), + (ADD32rr GR32:$src1, GR32:$src1)>; +} + //===----------------------------------------------------------------------===// // Floating Point Stack Support //===----------------------------------------------------------------------===// Added: llvm/trunk/test/CodeGen/X86/smul-with-overflow-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/smul-with-overflow-2.ll?rev=63090&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/smul-with-overflow-2.ll (added) +++ llvm/trunk/test/CodeGen/X86/smul-with-overflow-2.ll Mon Jan 26 21:30:42 2009 @@ -0,0 +1,20 @@ +; RUN: llvm-as < %s | llc -march=x86 | grep mul | count 1 +; RUN: llvm-as < %s | llc -march=x86 | grep add | count 3 + +define i32 @t1(i32 %a, i32 %b) nounwind readnone { +entry: + %tmp0 = add i32 %b, %a + %tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 2) + %tmp2 = extractvalue { i32, i1 } %tmp1, 0 + ret i32 %tmp2 +} + +define i32 @t2(i32 %a, i32 %b) nounwind readnone { +entry: + %tmp0 = add i32 %b, %a + %tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 4) + %tmp2 = extractvalue { i32, i1 } %tmp1, 0 + ret i32 %tmp2 +} + +declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32) nounwind From clattner at apple.com Mon Jan 26 22:53:33 2009 From: clattner at apple.com (Chris Lattner) Date: Mon, 26 Jan 2009 20:53:33 -0800 Subject: [llvm-commits] [llvm] r63008 - in /llvm/trunk: include/llvm/CodeGen/DebugLoc.h include/llvm/CodeGen/MachineFunction.h lib/CodeGen/MachineFunction.cpp In-Reply-To: <200901260741.n0Q7fnOn020226@zion.cs.uiuc.edu> References: <200901260741.n0Q7fnOn020226@zion.cs.uiuc.edu> Message-ID: On Jan 25, 2009, at 11:41 PM, Evan Cheng wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=63008&view=rev > Log: > Add data structure to define and track debug location during codegen. Thanks for working on this Evan, this is an important area to get right. > > + > + /// DebugLocTuple - Debug location tuple of filename id, line and > column. > + /// > + struct DebugLocTuple { > + unsigned FileId, Line, Col; > + > + DebugLocTuple(unsigned fi, unsigned l, unsigned c) > + : FileId(fi), Line(l), Col(c) {}; > + }; I think this looks good, and should be kept separate from the dwarf data-structures. > + /// DebugLoc - Debug location id. This is carried by SDNode and > + /// MachineInstr to index into a vector of unique debug location > tuples. Please mention that it defaults to 'invalid' but can be set to 'noinfo' explicitly. > + class DebugLoc { > + unsigned Idx; > + > + public: > + DebugLoc() : Idx(~0U) {} > + > + static DebugLoc getNoDebugLoc() { DebugLoc L; L.Idx = 0; > return L; } > + static DebugLoc get(unsigned idx) { DebugLoc L; L.Idx = idx; > return L; } > + > + bool isInvalid() { return Idx == ~0U; } > + bool isUnknown() { return Idx == 0; } These should be const. If you want to use 'isUnknown', please change getNoDebugLoc() to getUnknownLoc(), and please comment the accessor to say that this is true when there is no debug info for a statement. > + }; > + > + struct DebugLocTupleDenseMapInfo { Please partially specialize DenseMapInfo instead of defining a new struct. > + typedef DenseMap DebugLocTupleDenseMapInfo> > + DebugIdMapType; Do you need this typedef? DenseMap isn't too crazy. > + /// DebugLocTracker - This class tracks debug location information. > + /// > + struct DebugLocTracker { > + // NumFilenames - Size of the DebugFilenames vector. > + // > + unsigned NumFilenames; > + > + // DebugFilenames - A vector of unique file names. > + // > + std::vector DebugFilenames; Instead of the vector having a copy of the strings please keep a pointer to the string entries in DebugFilenamesMap. I actually just wrote this very similar code for clang: ... llvm::StringMap FilenameIDs; std::vector*> FilenamesByID; .. unsigned LineTableInfo::getLineTableFilenameID(const char *Ptr, unsigned Len) { // Look up the filename in the string table, returning the pre- existing value // if it exists. llvm::StringMapEntry &Entry = FilenameIDs.GetOrCreateValue(Ptr, Ptr+Len, ~0U); if (Entry.getValue() != ~0U) return Entry.getValue(); // Otherwise, assign this the next available ID. Entry.setValue(FilenamesByID.size()); FilenamesByID.push_back(&Entry); return FilenamesByID.size()-1; } > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original) > +++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Mon Jan 26 > 01:41:49 2009 > @@ -302,6 +306,15 @@ > + // > = > = > =-------------------------------------------------------------------- > ===// > + // Debug location. > + // > + > + /// lookUpDebugLocId - Look up the DebugLocTuple index with the > given > + /// filename, line, and column. It may add a new filename and / or > + /// a new DebugLocTuple. > + unsigned lookUpDebugLocId(const char *Filename, unsigned Line, > unsigned Col); How about getOrCreateDebugLocID(...) that would be more consistent with other APIs. > > }; > > // > = > = > =-------------------------------------------------------------------- > ===// > > Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=63008&r1=63007&r2=63008&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original) > +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Mon Jan 26 01:41:49 > 2009 > @@ -378,6 +378,33 @@ > return *mc; > } > > +/// lookUpDebugLocId - Look up the DebugLocTuple index with the given > +/// filename, line, and column. It may add a new filename and / or > +/// a new DebugLocTuple. > +unsigned MachineFunction::lookUpDebugLocId(const char *Filename, > unsigned Line, > + unsigned Col) { > + unsigned FileId; > + StringMap::iterator I = > + DebugLocInfo.DebugFilenamesMap.find(Filename); Please use code similar to what I pasted above, it will be a bit more efficient. -Chris From clattner at apple.com Mon Jan 26 22:54:22 2009 From: clattner at apple.com (Chris Lattner) Date: Mon, 26 Jan 2009 20:54:22 -0800 Subject: [llvm-commits] [llvm] r63009 - in /llvm/trunk: include/llvm/CodeGen/DebugLoc.h include/llvm/CodeGen/MachineFunction.h lib/CodeGen/MachineFunction.cpp In-Reply-To: <200901260753.n0Q7rgjS020573@zion.cs.uiuc.edu> References: <200901260753.n0Q7rgjS020573@zion.cs.uiuc.edu> Message-ID: <44340EEE-D084-4DFD-A996-C633F5E3CF60@apple.com> On Jan 25, 2009, at 11:53 PM, Evan Cheng wrote: > Author: evancheng > Date: Mon Jan 26 01:53:42 2009 > New Revision: 63009 > > URL: http://llvm.org/viewvc/llvm-project?rev=63009&view=rev > Log: > Actually source file has already been uniquified into an id during > isel. Eliminate the StringMap. Oh, ok. Well please still rename lookUpDebugLocId :) Thanks Evan, -Chris From resistor at mac.com Mon Jan 26 23:01:17 2009 From: resistor at mac.com (Owen Anderson) Date: Tue, 27 Jan 2009 05:01:17 -0000 Subject: [llvm-commits] [llvm] r63091 - /llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Message-ID: <200901270501.n0R51H3s008493@zion.cs.uiuc.edu> Author: resistor Date: Mon Jan 26 23:01:15 2009 New Revision: 63091 URL: http://llvm.org/viewvc/llvm-project?rev=63091&view=rev Log: Make the pre-split-limit option more useful by using a per-function counter. Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=63091&r1=63090&r2=63091&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original) +++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Mon Jan 26 23:01:15 2009 @@ -38,7 +38,7 @@ static cl::opt PreSplitLimit("pre-split-limit", cl::init(-1), cl::Hidden); -STATISTIC(NumSplits, "Number of intervals split"); +STATISTIC(NumTotalSplits, "Number of intervals split"); STATISTIC(NumRemats, "Number of intervals split by rematerialization"); STATISTIC(NumFolds, "Number of intervals split with spill folding"); STATISTIC(NumRenumbers, "Number of intervals renumbered into new registers"); @@ -77,6 +77,8 @@ // Def2SpillMap - A map from a def instruction index to spill index. DenseMap Def2SpillMap; + + unsigned NumSplits; public: static char ID; @@ -1191,6 +1193,7 @@ LSs = &getAnalysis(); bool MadeChange = false; + NumSplits = 0; // Make sure blocks are numbered in order. MF.RenumberBlocks(); @@ -1217,6 +1220,9 @@ } MadeChange |= removeDeadSpills(Split); + + if (NumSplits) + NumTotalSplits += NumSplits; return MadeChange; } From dpatel at apple.com Mon Jan 26 23:52:49 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 27 Jan 2009 05:52:49 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63096 - in /llvm-gcc-4.2/trunk/gcc: llvm-debug.cpp llvm-debug.h Message-ID: <200901270552.n0R5qoYZ010148@zion.cs.uiuc.edu> Author: dpatel Date: Mon Jan 26 23:52:49 2009 New Revision: 63096 URL: http://llvm.org/viewvc/llvm-project?rev=63096&view=rev Log: Remove dead code. Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp llvm-gcc-4.2/trunk/gcc/llvm-debug.h Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp?rev=63096&r1=63095&r2=63096&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Mon Jan 26 23:52:49 2009 @@ -198,11 +198,6 @@ , PrevFullPath("") , PrevLineNo(0) , PrevBB(NULL) -, StopPointFn(NULL) -, FuncStartFn(NULL) -, RegionStartFn(NULL) -, RegionEndFn(NULL) -, DeclareFn(NULL) , RegionStack() { MainCompileUnit = createCompileUnit(main_input_filename); Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.h?rev=63096&r1=63095&r2=63096&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-debug.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-debug.h Mon Jan 26 23:52:49 2009 @@ -63,11 +63,6 @@ std::map TypeCache; // Cache of previously constructed // Types. - Function *StopPointFn; // llvm.dbg.stoppoint - Function *FuncStartFn; // llvm.dbg.func.start - Function *RegionStartFn; // llvm.dbg.region.start - Function *RegionEndFn; // llvm.dbg.region.end - Function *DeclareFn; // llvm.dbg.declare std::vector RegionStack; // Stack to track declarative scopes. From dpatel at apple.com Tue Jan 27 01:13:22 2009 From: dpatel at apple.com (Devang Patel) Date: Mon, 26 Jan 2009 23:13:22 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63023 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp In-Reply-To: <200901261855.n0QItA9o019891@zion.cs.uiuc.edu> References: <200901261855.n0QItA9o019891@zion.cs.uiuc.edu> Message-ID: <5EABD9D4-FD7E-4A75-BFB8-36ADDB37B8C8@apple.com> On Jan 26, 2009, at 10:55 AM, Evan Cheng wrote: > Author: evancheng > Date: Mon Jan 26 12:55:10 2009 > New Revision: 63023 > > URL: http://llvm.org/viewvc/llvm-project?rev=63023&view=rev > Log: > Do not run aggressive loop unswitch at -O2. > > Modified: > llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=63023&r1=63022&r2=63023&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Mon Jan 26 12:55:10 2009 > @@ -438,7 +438,7 @@ > PM->add(createReassociatePass()); // Reassociate > expressions > PM->add(createLoopRotatePass()); // Rotate Loop > PM->add(createLICMPass()); // Hoist loop > invariants > - PM->add(createLoopUnswitchPass(optimize_size ? true : false)); > + PM->add(createLoopUnswitchPass(optimize_size || optimize < 3)); Pl. do if (optimize >= 3) PM->add(createLoopUnswitchPass(optimize_size || optimize < 3)); LoopUnswitchPass constructor accepts a boolean flag that indicates whether we're optimize for size or not. Right now loop-unswitch pass does not unswitch loop if optimizing for size, but that is implementation detail. If you want to disable the pass for -O2 then pl. avoid indirect approach because -O2 does not mean optimize for size. Thanks, - Devang From echristo at apple.com Tue Jan 27 01:35:47 2009 From: echristo at apple.com (Eric Christopher) Date: Mon, 26 Jan 2009 23:35:47 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63023 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp In-Reply-To: <5EABD9D4-FD7E-4A75-BFB8-36ADDB37B8C8@apple.com> References: <200901261855.n0QItA9o019891@zion.cs.uiuc.edu> <5EABD9D4-FD7E-4A75-BFB8-36ADDB37B8C8@apple.com> Message-ID: <6844FD5A-A16B-4689-8D44-5E890336BB1D@apple.com> On Jan 26, 2009, at 11:13 PM, Devang Patel wrote: > Pl. do > if (optimize >= 3) > PM->add(createLoopUnswitchPass(optimize_size || optimize < 3)); Ur? if optimize >= 3 then the right half of that or statement will never be true. -eric From dpatel at apple.com Tue Jan 27 01:41:30 2009 From: dpatel at apple.com (Devang Patel) Date: Mon, 26 Jan 2009 23:41:30 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63023 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp In-Reply-To: <6844FD5A-A16B-4689-8D44-5E890336BB1D@apple.com> References: <200901261855.n0QItA9o019891@zion.cs.uiuc.edu> <5EABD9D4-FD7E-4A75-BFB8-36ADDB37B8C8@apple.com> <6844FD5A-A16B-4689-8D44-5E890336BB1D@apple.com> Message-ID: <8F863E44-3E37-4527-95D4-0BE5031F3B96@apple.com> On Jan 26, 2009, at 11:35 PM, Eric Christopher wrote: > > > if optimize >= 3 then the right half of that or statement will never > be true. oops.. I meant if (optimize >= 3) // Do not optimize for size PM->add(createLoopUnswitchPass(false)); else if (optimize_size) // Optimize for size if -Os is set. PM->add(createLoopUnswitchPass(true)); From echeng at apple.com Tue Jan 27 02:00:08 2009 From: echeng at apple.com (Evan Cheng) Date: Tue, 27 Jan 2009 00:00:08 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63023 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp In-Reply-To: <5EABD9D4-FD7E-4A75-BFB8-36ADDB37B8C8@apple.com> References: <200901261855.n0QItA9o019891@zion.cs.uiuc.edu> <5EABD9D4-FD7E-4A75-BFB8-36ADDB37B8C8@apple.com> Message-ID: On Jan 26, 2009, at 11:13 PM, Devang Patel wrote: > > On Jan 26, 2009, at 10:55 AM, Evan Cheng wrote: > >> Author: evancheng >> Date: Mon Jan 26 12:55:10 2009 >> New Revision: 63023 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=63023&view=rev >> Log: >> Do not run aggressive loop unswitch at -O2. >> >> Modified: >> llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp >> >> Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=63023&r1=63022&r2=63023&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) >> +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Mon Jan 26 12:55:10 2009 >> @@ -438,7 +438,7 @@ >> PM->add(createReassociatePass()); // Reassociate >> expressions >> PM->add(createLoopRotatePass()); // Rotate Loop >> PM->add(createLICMPass()); // Hoist loop >> invariants >> - PM->add(createLoopUnswitchPass(optimize_size ? true : false)); >> + PM->add(createLoopUnswitchPass(optimize_size || optimize < 3)); > > Pl. do > if (optimize >= 3) > PM->add(createLoopUnswitchPass(optimize_size || optimize < 3)); > > LoopUnswitchPass constructor accepts a boolean flag that indicates > whether we're optimize for size or not. Right now loop-unswitch pass > does not unswitch loop if optimizing for size, but that is > implementation detail. If you want to disable the pass for -O2 then > pl. avoid indirect approach because -O2 does not mean optimize for > size. Looks like there are confusion about the semantics of the value being passed to createLoopUnswitchPass. My understanding is if it's true then it does loop switching but not aggressively. That is, it reduces the aggressiveness so it doesn't bloat code size. From your statement, that doesn't seem like the case? At -O2, we want to do this optimization, but we want to limit code size increase. Evan > > > Thanks, > - > Devang > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Tue Jan 27 02:03:16 2009 From: clattner at apple.com (Chris Lattner) Date: Tue, 27 Jan 2009 00:03:16 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63023 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp In-Reply-To: References: <200901261855.n0QItA9o019891@zion.cs.uiuc.edu> <5EABD9D4-FD7E-4A75-BFB8-36ADDB37B8C8@apple.com> Message-ID: On Jan 27, 2009, at 12:00 AM, Evan Cheng wrote: > Looks like there are confusion about the semantics of the value being > passed to createLoopUnswitchPass. My understanding is if it's true > then it does loop switching but not aggressively. That is, it reduces > the aggressiveness so it doesn't bloat code size. From your statement, > that doesn't seem like the case? > > At -O2, we want to do this optimization, but we want to limit code > size increase. Evan's right, we want to run it at both -Os and -O2, but not in the "aggressive" mode. In fact, since you can't have -Os -O3, should the "aggressive" mode just be enabled when optimize >= 3 and drop the optimize_size condition? -Chris From baldrick at free.fr Tue Jan 27 06:47:46 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 27 Jan 2009 13:47:46 +0100 Subject: [llvm-commits] [llvm-gcc-4.2] r63087 - /llvm-gcc-4.2/trunk/gcc/tree-nested.c In-Reply-To: <200901270202.n0R22aB6002964@zion.cs.uiuc.edu> References: <200901270202.n0R22aB6002964@zion.cs.uiuc.edu> Message-ID: <200901271347.46820.baldrick@free.fr> Hi Dale, > Fix g++.apple/blocks-in_structors.c on Darwin. > This allows a null "root" in initialize_chains, > and removes a mysterious llvm assert in > convert_all_function_calls. Both situtations > seem to occur legitimately in this example, and > nothing in the testsuite breaks. this assertion is not really mysterious. It is here because I had to add a bunch of code to fix a long standing tree-nested bug in which nested function bodies and callers have different opinions as to whether the function takes a static chain parameter or not. This doesn't matter much for gcc because the parameter is passed out of line, but it is rather horrible for llvm-gcc because it is added as an explicit parameter to the function. I never got round to pushing this upstream, but I really should. Anyway, the assertion is checking that a nested subroutine (the root->outer check ensures that this is a nested subroutine) takes an extra parameter for passing variables belonging to the parent (the "static chain") if and only if either it itself accesses a variable belonging to its parent (in which case root->chain_field is not null) or one of its child nested subroutines does (in which case root->chain_decl is not null). > - gcc_assert (!root->outer || > - DECL_NO_STATIC_CHAIN (root->context) == > - !(root->chain_decl || root->chain_field)); If the assertion is failing, it seems to me that something bad is going on. Ciao, Duncan. From dpatel at apple.com Tue Jan 27 11:06:00 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 27 Jan 2009 09:06:00 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63023 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp In-Reply-To: References: <200901261855.n0QItA9o019891@zion.cs.uiuc.edu> <5EABD9D4-FD7E-4A75-BFB8-36ADDB37B8C8@apple.com> Message-ID: On Jan 27, 2009, at 12:03 AM, Chris Lattner wrote: > On Jan 27, 2009, at 12:00 AM, Evan Cheng wrote: >> > Evan's right, we want to run it at both -Os and -O2, but not in the > "aggressive" mode. Aha.. I thought Evan want to disable loop unswitch at -O2. - Devang From gohman at apple.com Tue Jan 27 11:28:24 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 27 Jan 2009 17:28:24 -0000 Subject: [llvm-commits] [llvm] r63104 - /llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Message-ID: <200901271728.n0RHSOJg012546@zion.cs.uiuc.edu> Author: djg Date: Tue Jan 27 11:28:23 2009 New Revision: 63104 URL: http://llvm.org/viewvc/llvm-project?rev=63104&view=rev Log: Make some comments doxygen-friendly. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63104&r1=63103&r2=63104&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Jan 27 11:28:23 2009 @@ -533,11 +533,11 @@ SDValue getIndexedStore(SDValue OrigStoe, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM); - // getSrcValue - Construct a node to track a Value* through the backend. + /// getSrcValue - Construct a node to track a Value* through the backend. SDValue getSrcValue(const Value *v); - // getMemOperand - Construct a node to track a memory reference - // through the backend. + /// getMemOperand - Construct a node to track a memory reference + /// through the backend. SDValue getMemOperand(const MachineMemOperand &MO); /// UpdateNodeOperands - *Mutate* the specified node in-place to have the @@ -814,10 +814,10 @@ void allnodes_clear(); - // List of non-single value types. + /// VTList - List of non-single value types. std::vector VTList; - // Maps to auto-CSE operations. + /// CondCodeNodes - Maps to auto-CSE operations. std::vector CondCodeNodes; std::vector ValueTypeNodes; From kremenek at apple.com Tue Jan 27 11:43:22 2009 From: kremenek at apple.com (Ted Kremenek) Date: Tue, 27 Jan 2009 17:43:22 -0000 Subject: [llvm-commits] [llvm] r63105 - /llvm/tags/checker/checker-0.145/ Message-ID: <200901271743.n0RHhMrE013308@zion.cs.uiuc.edu> Author: kremenek Date: Tue Jan 27 11:43:22 2009 New Revision: 63105 URL: http://llvm.org/viewvc/llvm-project?rev=63105&view=rev Log: Removing checker-0.145. Removed: llvm/tags/checker/checker-0.145/ From edwintorok at gmail.com Tue Jan 27 12:06:05 2009 From: edwintorok at gmail.com (Torok Edwin) Date: Tue, 27 Jan 2009 18:06:05 -0000 Subject: [llvm-commits] [llvm] r63107 - in /llvm/trunk: lib/Support/APInt.cpp unittests/ADT/APInt.cpp Message-ID: <200901271806.n0RI65PB014174@zion.cs.uiuc.edu> Author: edwin Date: Tue Jan 27 12:06:03 2009 New Revision: 63107 URL: http://llvm.org/viewvc/llvm-project?rev=63107&view=rev Log: APInt's countLeadingOnes() was broken for negative i128 values, causing assertion failures in getSExtValue(). Fix it by making highWordBits actually contain what its name says, and add some more unit-tests for APInt. This fixes PR3419. Modified: llvm/trunk/lib/Support/APInt.cpp llvm/trunk/unittests/ADT/APInt.cpp Modified: llvm/trunk/lib/Support/APInt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/APInt.cpp?rev=63107&r1=63106&r2=63107&view=diff ============================================================================== --- llvm/trunk/lib/Support/APInt.cpp (original) +++ llvm/trunk/lib/Support/APInt.cpp Tue Jan 27 12:06:03 2009 @@ -683,7 +683,13 @@ return countLeadingOnes_64(VAL, APINT_BITS_PER_WORD - BitWidth); unsigned highWordBits = BitWidth % APINT_BITS_PER_WORD; - unsigned shift = (highWordBits == 0 ? 0 : APINT_BITS_PER_WORD - highWordBits); + unsigned shift; + if (!highWordBits) { + highWordBits = APINT_BITS_PER_WORD; + shift = 0; + } else { + shift = APINT_BITS_PER_WORD - highWordBits; + } int i = getNumWords() - 1; unsigned Count = countLeadingOnes_64(pVal[i], shift); if (Count == highWordBits) { Modified: llvm/trunk/unittests/ADT/APInt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/APInt.cpp?rev=63107&r1=63106&r2=63107&view=diff ============================================================================== --- llvm/trunk/unittests/ADT/APInt.cpp (original) +++ llvm/trunk/unittests/ADT/APInt.cpp Tue Jan 27 12:06:03 2009 @@ -18,8 +18,83 @@ TEST(APIntTest, ShiftLeftByZero) { APInt One = APInt::getNullValue(65) + 1; APInt Shl = One.shl(0); - EXPECT_EQ(Shl[0], true); - EXPECT_EQ(Shl[1], false); + EXPECT_EQ(true, Shl[0]); + EXPECT_EQ(false, Shl[1]); +} + +TEST(APIntTest, I128NegativeCount) { + APInt Minus3(128, (uint64_t)-3, true); + EXPECT_EQ(126u, Minus3.countLeadingOnes()); + EXPECT_EQ(-3, Minus3.getSExtValue()); + + APInt Minus1(128, (uint64_t)-1, true); + EXPECT_EQ(0u, Minus1.countLeadingZeros()); + EXPECT_EQ(128u, Minus1.countLeadingOnes()); + EXPECT_EQ(128u, Minus1.getActiveBits()); + EXPECT_EQ(0u, Minus1.countTrailingZeros()); + EXPECT_EQ(128u, Minus1.countTrailingOnes()); + EXPECT_EQ(128u, Minus1.countPopulation()); + EXPECT_EQ(-1, Minus1.getSExtValue()); +} + +TEST(APIntTest, I33Count) { + APInt i33minus2(33, -2, true); + EXPECT_EQ(0u, i33minus2.countLeadingZeros()); + EXPECT_EQ(32u, i33minus2.countLeadingOnes()); + EXPECT_EQ(33u, i33minus2.getActiveBits()); + EXPECT_EQ(1u, i33minus2.countTrailingZeros()); + EXPECT_EQ(32u, i33minus2.countPopulation()); + EXPECT_EQ(-2, i33minus2.getSExtValue()); + EXPECT_EQ(((uint64_t)-2)&((1ull<<33) -1), i33minus2.getZExtValue()); +} + +TEST(APIntTest, I65Count) { + APInt i65minus(65, 0, true); + i65minus.set(64); + EXPECT_EQ(0u, i65minus.countLeadingZeros()); + EXPECT_EQ(1u, i65minus.countLeadingOnes()); + EXPECT_EQ(65u, i65minus.getActiveBits()); + EXPECT_EQ(64u, i65minus.countTrailingZeros()); + EXPECT_EQ(1u, i65minus.countPopulation()); +} + +TEST(APIntTest, I128PositiveCount) { + APInt u128max = APInt::getAllOnesValue(128); + EXPECT_EQ(128u, u128max.countLeadingOnes()); + EXPECT_EQ(0u, u128max.countLeadingZeros()); + EXPECT_EQ(128u, u128max.getActiveBits()); + EXPECT_EQ(0u, u128max.countTrailingZeros()); + EXPECT_EQ(128u, u128max.countTrailingOnes()); + EXPECT_EQ(128u, u128max.countPopulation()); + + APInt u64max(128, (uint64_t)-1, false); + EXPECT_EQ(64u, u64max.countLeadingZeros()); + EXPECT_EQ(0u, u64max.countLeadingOnes()); + EXPECT_EQ(64u, u64max.getActiveBits()); + EXPECT_EQ(0u, u64max.countTrailingZeros()); + EXPECT_EQ(64u, u64max.countTrailingOnes()); + EXPECT_EQ(64u, u64max.countPopulation()); + EXPECT_EQ((uint64_t)~0ull, u64max.getZExtValue()); + + APInt zero(128, 0, true); + EXPECT_EQ(128u, zero.countLeadingZeros()); + EXPECT_EQ(0u, zero.countLeadingOnes()); + EXPECT_EQ(0u, zero.getActiveBits()); + EXPECT_EQ(128u, zero.countTrailingZeros()); + EXPECT_EQ(0u, zero.countTrailingOnes()); + EXPECT_EQ(0u, zero.countPopulation()); + EXPECT_EQ(0u, zero.getSExtValue()); + EXPECT_EQ(0u, zero.getZExtValue()); + + APInt one(128, 1, true); + EXPECT_EQ(127u, one.countLeadingZeros()); + EXPECT_EQ(0u, one.countLeadingOnes()); + EXPECT_EQ(1u, one.getActiveBits()); + EXPECT_EQ(0u, one.countTrailingZeros()); + EXPECT_EQ(1u, one.countTrailingOnes()); + EXPECT_EQ(1u, one.countPopulation()); + EXPECT_EQ(1, one.getSExtValue()); + EXPECT_EQ(1u, one.getZExtValue()); } } From stuart at apple.com Tue Jan 27 12:10:47 2009 From: stuart at apple.com (Stuart Hastings) Date: Tue, 27 Jan 2009 18:10:47 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63109 - in /llvm-gcc-4.2/trunk/gcc: gimplify.c llvm-backend.cpp llvm-convert.cpp tree.h Message-ID: <200901271810.n0RIAmiZ014379@zion.cs.uiuc.edu> Author: stuart Date: Tue Jan 27 12:10:47 2009 New Revision: 63109 URL: http://llvm.org/viewvc/llvm-project?rev=63109&view=rev Log: Restoring DECL_LLVM_PRIVATE (rev 62850) with a patch to fix some ObjC DejaGNU regressions. Modified: llvm-gcc-4.2/trunk/gcc/gimplify.c llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp llvm-gcc-4.2/trunk/gcc/tree.h Modified: llvm-gcc-4.2/trunk/gcc/gimplify.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gimplify.c?rev=63109&r1=63108&r2=63109&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/gimplify.c (original) +++ llvm-gcc-4.2/trunk/gcc/gimplify.c Tue Jan 27 12:10:47 2009 @@ -3096,6 +3096,7 @@ gimple_add_tmp_var (new); TREE_STATIC (new) = 1; TREE_READONLY (new) = 1; + DECL_LLVM_PRIVATE (new) = 1; DECL_INITIAL (new) = ctor; if (align > DECL_ALIGN (new)) { Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=63109&r1=63108&r2=63109&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Tue Jan 27 12:10:47 2009 @@ -833,7 +833,9 @@ GlobalValue::LinkageTypes Linkage; // A weak alias has TREE_PUBLIC set but not the other bits. - if (DECL_WEAK(decl)) + if (DECL_LLVM_PRIVATE(decl)) + Linkage = GlobalValue::PrivateLinkage; + else if (DECL_WEAK(decl)) Linkage = GlobalValue::WeakLinkage; else if (!TREE_PUBLIC(decl)) Linkage = GlobalValue::InternalLinkage; @@ -1085,7 +1087,10 @@ GV->setThreadLocal(true); // Set the linkage. - if (!TREE_PUBLIC(decl)) { + if (CODE_CONTAINS_STRUCT (TREE_CODE (decl), TS_DECL_WITH_VIS) + && DECL_LLVM_PRIVATE(decl)) { + GV->setLinkage(GlobalValue::PrivateLinkage); + } else if (!TREE_PUBLIC(decl)) { GV->setLinkage(GlobalValue::InternalLinkage); } else if (DECL_WEAK(decl) || DECL_ONE_ONLY(decl)) { GV->setLinkage(GlobalValue::WeakLinkage); Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=63109&r1=63108&r2=63109&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Jan 27 12:10:47 2009 @@ -642,7 +642,9 @@ // emitted; hack this by pretending they're static. That will either // make them go away or emit a static definition that won't collide with // anything. - if (!TREE_PUBLIC(FnDecl) /*|| lang_hooks.llvm_is_in_anon(subr)*/) { + if (DECL_LLVM_PRIVATE(FnDecl)) { + Fn->setLinkage(Function::PrivateLinkage); + } else if (!TREE_PUBLIC(FnDecl) /*|| lang_hooks.llvm_is_in_anon(subr)*/) { Fn->setLinkage(Function::InternalLinkage); } else if (DECL_EXTERNAL(FnDecl) && lookup_attribute ("always_inline", DECL_ATTRIBUTES (FnDecl))) { Modified: llvm-gcc-4.2/trunk/gcc/tree.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/tree.h?rev=63109&r1=63108&r2=63109&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/tree.h (original) +++ llvm-gcc-4.2/trunk/gcc/tree.h Tue Jan 27 12:10:47 2009 @@ -2916,6 +2916,9 @@ /* Used to indicate that this DECL has weak linkage. */ #define DECL_WEAK(NODE) (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.weak_flag) +#define DECL_LLVM_PRIVATE(NODE) \ + (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.llvm_private_flag) + /* Internal to the gimplifier. Indicates that the value is a formal temporary controlled by the gimplifier. */ #define DECL_GIMPLE_FORMAL_TEMP_P(DECL) \ @@ -3052,6 +3055,10 @@ unsigned weak_flag:1; unsigned seen_in_bind_expr : 1; unsigned comdat_flag : 1; + + /* LLVM LOCAL */ + unsigned llvm_private_flag : 1; + ENUM_BITFIELD(symbol_visibility) visibility : 2; unsigned visibility_specified : 1; /* Belong to FUNCTION_DECL exclusively. */ @@ -3072,7 +3079,7 @@ unsigned block_synthesized_function : 1; /* APPLE LOCAL radar 5847976 */ unsigned block_weak : 1; - /* 5 unused bits. */ + /* 4 unused bits. */ /* APPLE LOCAL end radar 5932809 - copyable byref blocks */ /* APPLE LOCAL end radar 5732232 - blocks */ }; From dalej at apple.com Tue Jan 27 12:13:48 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 27 Jan 2009 10:13:48 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63087 - /llvm-gcc-4.2/trunk/gcc/tree-nested.c In-Reply-To: <200901271347.46820.baldrick@free.fr> References: <200901270202.n0R22aB6002964@zion.cs.uiuc.edu> <200901271347.46820.baldrick@free.fr> Message-ID: <46B005A4-AA7B-4856-BE11-153CC5F93AC9@apple.com> On Jan 27, 2009, at 4:47 AMPST, Duncan Sands wrote: > Hi Dale, > >> Fix g++.apple/blocks-in_structors.c on Darwin. >> This allows a null "root" in initialize_chains, >> and removes a mysterious llvm assert in >> convert_all_function_calls. Both situtations >> seem to occur legitimately in this example, and >> nothing in the testsuite breaks. > > this assertion is not really mysterious. Well, it had no comments, no pointer to a bug it fixed, and no test case.... > It is here > because I had to add a bunch of code to fix a long > standing tree-nested bug in which nested function bodies > and callers have different opinions as to whether > the function takes a static chain parameter or not. > This doesn't matter much for gcc because the parameter > is passed out of line, but it is rather horrible for > llvm-gcc because it is added as an explicit parameter > to the function. I never got round to pushing this > upstream, but I really should. Anyway, the assertion > is checking that a nested subroutine (the root->outer > check ensures that this is a nested subroutine) takes > an extra parameter for passing variables belonging to > the parent (the "static chain") if and only if either > it itself accesses a variable belonging to its parent > (in which case root->chain_field is not null) or one > of its child nested subroutines does (in which case > root->chain_decl is not null). > >> - gcc_assert (!root->outer || >> - DECL_NO_STATIC_CHAIN (root->context) == >> - !(root->chain_decl || root->chain_field)); > > If the assertion is failing, it seems to me that something > bad is going on. You may be right, or this may be another case where ObjC isn't doing what you expect (which you would probably consider abuse). I concluded it was the latter, but you seem to understand what this code is doing better than I, maybe you could look at the testcase? It's misspelled in the checkin message above, should be block- in_structors.C . From baldrick at free.fr Tue Jan 27 12:26:51 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 27 Jan 2009 19:26:51 +0100 Subject: [llvm-commits] [llvm-gcc-4.2] r63087 - /llvm-gcc-4.2/trunk/gcc/tree-nested.c In-Reply-To: <46B005A4-AA7B-4856-BE11-153CC5F93AC9@apple.com> References: <200901270202.n0R22aB6002964@zion.cs.uiuc.edu> <200901271347.46820.baldrick@free.fr> <46B005A4-AA7B-4856-BE11-153CC5F93AC9@apple.com> Message-ID: <200901271926.52091.baldrick@free.fr> Hi Dale, > > this assertion is not really mysterious. > > Well, it had no comments, no pointer to a bug it fixed, and no test > case.... maybe the commit log is helpful: r45934 | baldrick | 2008-01-13 19:42:27 +0100 (Sun, 13 Jan 2008) | 20 lines Fix [Bug tree-optimization/30927], which results in suboptimal code for gcc, but maybe wrong code for llvm-gcc. The problem occurs when one nested function, A, calls another nested function B, when the body of B is output after the body of A (so at the moment of the call, A only has the declaration of B). The bug results in the call thinking that B takes a static chain, whether or not B actually does. Since gcc does not have the static chain as an actual function parameter, but as an implicit one always passed in a register, it is fairly harmless if A sets the register value and B never uses it. But in LLVM the static chain is a normal function parameter, and the mismatch between the call and the callee can result in trouble, not to mention unpleasant warnings from instcombine about "While resolving call to function 'B' arguments were dropped!". It is true that there is no testcase for this assertion, but how do you test for something that can't happen (the testcase for the bug being fixed is FrontendC/2008-01-11-ChainConsistency.c)? There are more details in the gcc bug report. > > It is here > > because I had to add a bunch of code to fix a long > > standing tree-nested bug in which nested function bodies > > and callers have different opinions as to whether > > the function takes a static chain parameter or not. > > This doesn't matter much for gcc because the parameter > > is passed out of line, but it is rather horrible for > > llvm-gcc because it is added as an explicit parameter > > to the function. I never got round to pushing this > > upstream, but I really should. Anyway, the assertion > > is checking that a nested subroutine (the root->outer > > check ensures that this is a nested subroutine) takes > > an extra parameter for passing variables belonging to > > the parent (the "static chain") if and only if either > > it itself accesses a variable belonging to its parent > > (in which case root->chain_field is not null) or one > > of its child nested subroutines does (in which case > > root->chain_decl is not null). > > > >> - gcc_assert (!root->outer || > >> - DECL_NO_STATIC_CHAIN (root->context) == > >> - !(root->chain_decl || root->chain_field)); > > > > If the assertion is failing, it seems to me that something > > bad is going on. > > You may be right, or this may be another case where ObjC isn't doing > what you expect (which you would probably consider abuse). I > concluded it was the latter, but you seem to understand what this > code is doing better than I, maybe you could look at the testcase? I will. Sadly I do understand the horror that is tree-nested, at least I used to. I had to in order to implement support for nested functions in llvm-gcc :( :) > It's misspelled in the checkin message above, should be block- > in_structors.C . Thanks! Ciao, Duncan. From dalej at apple.com Tue Jan 27 12:30:46 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 27 Jan 2009 10:30:46 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63087 - /llvm-gcc-4.2/trunk/gcc/tree-nested.c In-Reply-To: <200901271926.52091.baldrick@free.fr> References: <200901270202.n0R22aB6002964@zion.cs.uiuc.edu> <200901271347.46820.baldrick@free.fr> <46B005A4-AA7B-4856-BE11-153CC5F93AC9@apple.com> <200901271926.52091.baldrick@free.fr> Message-ID: <11EA744B-ED1F-4B9C-8BBB-73CEEEAE702C@apple.com> On Jan 27, 2009, at 10:26 AMPST, Duncan Sands wrote: > Hi Dale, >> >>> It is here >>> because I had to add a bunch of code to fix a long >>> standing tree-nested bug in which nested function bodies >>> and callers have different opinions as to whether >>> the function takes a static chain parameter or not. >>> This doesn't matter much for gcc because the parameter >>> is passed out of line, but it is rather horrible for >>> llvm-gcc because it is added as an explicit parameter >>> to the function. I never got round to pushing this >>> upstream, but I really should. Anyway, the assertion >>> is checking that a nested subroutine (the root->outer >>> check ensures that this is a nested subroutine) takes >>> an extra parameter for passing variables belonging to >>> the parent (the "static chain") if and only if either >>> it itself accesses a variable belonging to its parent >>> (in which case root->chain_field is not null) or one >>> of its child nested subroutines does (in which case >>> root->chain_decl is not null). >>> >>>> - gcc_assert (!root->outer || >>>> - DECL_NO_STATIC_CHAIN (root->context) == >>>> - !(root->chain_decl || root->chain_field)); >>> >>> If the assertion is failing, it seems to me that something >>> bad is going on. >> >> You may be right, or this may be another case where ObjC isn't doing >> what you expect (which you would probably consider abuse). I >> concluded it was the latter, but you seem to understand what this >> code is doing better than I, maybe you could look at the testcase? > > I will. Sadly I do understand the horror that is tree-nested, at > least I used to. I had to in order to implement support for nested > functions in llvm-gcc :( :) OK. I've also got a question in the guy who implemented the "blocks" stuff in ObjC, who fortunately is still here:) He can probably clarify what ObjC is doing. From kremenek at apple.com Tue Jan 27 12:46:37 2009 From: kremenek at apple.com (Ted Kremenek) Date: Tue, 27 Jan 2009 18:46:37 -0000 Subject: [llvm-commits] [llvm] r63114 - /llvm/tags/checker/checker-0.145/ Message-ID: <200901271846.n0RIkb1Q015910@zion.cs.uiuc.edu> Author: kremenek Date: Tue Jan 27 12:46:37 2009 New Revision: 63114 URL: http://llvm.org/viewvc/llvm-project?rev=63114&view=rev Log: Tagging checker-0.145. Added: llvm/tags/checker/checker-0.145/ - copied from r63113, llvm/trunk/ From baldrick at free.fr Tue Jan 27 12:48:22 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 27 Jan 2009 19:48:22 +0100 Subject: [llvm-commits] [llvm-gcc-4.2] r63109 - in /llvm-gcc-4.2/trunk/gcc: gimplify.c llvm-backend.cpp llvm-convert.cpp tree.h In-Reply-To: <200901271810.n0RIAmiZ014379@zion.cs.uiuc.edu> References: <200901271810.n0RIAmiZ014379@zion.cs.uiuc.edu> Message-ID: <200901271948.23083.baldrick@free.fr> > Restoring DECL_LLVM_PRIVATE (rev 62850) with a patch to fix some ObjC DejaGNU regressions. What was the fix and what was regressing? Thanks, Duncan. From stuart at apple.com Tue Jan 27 13:03:18 2009 From: stuart at apple.com (Stuart Hastings) Date: Tue, 27 Jan 2009 11:03:18 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63109 - in /llvm-gcc-4.2/trunk/gcc: gimplify.c llvm-backend.cpp llvm-convert.cpp tree.h In-Reply-To: <200901271948.23083.baldrick@free.fr> References: <200901271810.n0RIAmiZ014379@zion.cs.uiuc.edu> <200901271948.23083.baldrick@free.fr> Message-ID: <6E65104D-66C7-497F-A287-BD674D0ED8F9@apple.com> On Jan 27, 2009, at 10:48 AM, Duncan Sands wrote: >> Restoring DECL_LLVM_PRIVATE (rev 62850) with a patch to fix some >> ObjC DejaGNU regressions. > > What was the fix and what was regressing? In llvm-backend.cpp, I added the "CODE_CONTAINS_STRUCT" voodoo around line 1085: + if (CODE_CONTAINS_STRUCT (TREE_CODE (decl), TS_DECL_WITH_VIS) + && DECL_LLVM_PRIVATE(decl)) { There were at least three ICEs in the ObjC DejaGNU tests: FAIL: objc.dg/const-cfstring-6.m (test for excess errors) FAIL: objc.dg/pubtypes-id-test.m (test for excess errors) FAIL: obj-c++.dg/const-cfstring-6.mm (test for excess errors) While the patch doesn't make all the tests pass, at least the ICE-ing is gone. (On my dev machine, the const-cfstring-6.{m,mm} tests now fail with a linker error.) > Thanks, You're very welcome, stuart From gohman at apple.com Tue Jan 27 13:04:30 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 27 Jan 2009 19:04:30 -0000 Subject: [llvm-commits] [llvm] r63118 - /llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Message-ID: <200901271904.n0RJ4URZ016629@zion.cs.uiuc.edu> Author: djg Date: Tue Jan 27 13:04:30 2009 New Revision: 63118 URL: http://llvm.org/viewvc/llvm-project?rev=63118&view=rev Log: Simplify findNonImmUse; return the result using the return value instead of via a by-reference argument. No functionality change. Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=63118&r1=63117&r2=63118&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Jan 27 13:04:30 2009 @@ -249,30 +249,30 @@ return NULL; } -/// findNonImmUse - Return true by reference in "found" if "Use" is an -/// non-immediate use of "Def". This function recursively traversing -/// up the operand chain ignoring certain nodes. -static void findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, - SDNode *Root, bool &found, +/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". +/// This function recursively traverses up the operand chain, ignoring +/// certain nodes. +static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, + SDNode *Root, SmallPtrSet &Visited) { - if (found || - Use->getNodeId() < Def->getNodeId() || + if (Use->getNodeId() < Def->getNodeId() || !Visited.insert(Use)) - return; - - for (unsigned i = 0, e = Use->getNumOperands(); !found && i != e; ++i) { + return false; + + for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { SDNode *N = Use->getOperand(i).getNode(); if (N == Def) { if (Use == ImmedUse || Use == Root) continue; // We are not looking for immediate use. assert(N != Root); - found = true; - break; + return true; } // Traverse up the operand chain. - findNonImmUse(N, Def, ImmedUse, Root, found, Visited); + if (findNonImmUse(N, Def, ImmedUse, Root, Visited)) + return true; } + return false; } /// isNonImmUse - Start searching from Root up the DAG to check is Def can @@ -287,9 +287,7 @@ /// its chain operand. static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) { SmallPtrSet Visited; - bool found = false; - findNonImmUse(Root, Def, ImmedUse, Root, found, Visited); - return found; + return findNonImmUse(Root, Def, ImmedUse, Root, Visited); } From gohman at apple.com Tue Jan 27 13:19:28 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 27 Jan 2009 19:19:28 -0000 Subject: [llvm-commits] [llvm] r63119 - /llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Message-ID: <200901271919.n0RJJSgY017150@zion.cs.uiuc.edu> Author: djg Date: Tue Jan 27 13:19:28 2009 New Revision: 63119 URL: http://llvm.org/viewvc/llvm-project?rev=63119&view=rev Log: Respect the DisableRedZone flag on PowerPC. Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=63119&r1=63118&r2=63119&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Jan 27 13:19:28 2009 @@ -893,7 +893,8 @@ // If we are a leaf function, and use up to 224 bytes of stack space, // don't have a frame pointer, calls, or dynamic alloca then we do not need // to adjust the stack pointer (we fit in the Red Zone). - if (FrameSize <= 224 && // Fits in red zone. + if (!DisableRedZone && + FrameSize <= 224 && // Fits in red zone. !MFI->hasVarSizedObjects() && // No dynamic alloca. !MFI->hasCalls() && // No calls. (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. From clattner at apple.com Tue Jan 27 13:20:24 2009 From: clattner at apple.com (Chris Lattner) Date: Tue, 27 Jan 2009 11:20:24 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63087 - /llvm-gcc-4.2/trunk/gcc/tree-nested.c In-Reply-To: <11EA744B-ED1F-4B9C-8BBB-73CEEEAE702C@apple.com> References: <200901270202.n0R22aB6002964@zion.cs.uiuc.edu> <200901271347.46820.baldrick@free.fr> <46B005A4-AA7B-4856-BE11-153CC5F93AC9@apple.com> <200901271926.52091.baldrick@free.fr> <11EA744B-ED1F-4B9C-8BBB-73CEEEAE702C@apple.com> Message-ID: <01044A52-0568-4A89-8872-AD970B83D721@apple.com> On Jan 27, 2009, at 10:30 AM, Dale Johannesen wrote: >> I will. Sadly I do understand the horror that is tree-nested, at >> least I used to. I had to in order to implement support for nested >> functions in llvm-gcc :( :) > > OK. I've also got a question in the guy who implemented the "blocks" > stuff in ObjC, who fortunately is still here:) He can probably > clarify what ObjC is doing. blocks should never use any of the interesting support in tree- nested. If it is, then there is something going wrong in the front- end block lowering code. -Chris From gohman at apple.com Tue Jan 27 13:23:23 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 27 Jan 2009 19:23:23 -0000 Subject: [llvm-commits] [llvm] r63120 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Message-ID: <200901271923.n0RJNNIW017305@zion.cs.uiuc.edu> Author: djg Date: Tue Jan 27 13:23:22 2009 New Revision: 63120 URL: http://llvm.org/viewvc/llvm-project?rev=63120&view=rev Log: Delete redundant return statements. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63120&r1=63119&r2=63120&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Tue Jan 27 13:23:22 2009 @@ -1341,7 +1341,6 @@ SDValue Table = DAG.getJumpTable(JT.JTI, PTy); DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), Table, Index)); - return; } /// visitJumpTableHeader - This function emits necessary code to produce index @@ -1392,8 +1391,6 @@ else DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, DAG.getBasicBlock(JT.MBB))); - - return; } /// visitBitTestHeader - This function emits necessary code to produce value @@ -1439,8 +1436,6 @@ else DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, DAG.getBasicBlock(MBB))); - - return; } /// visitBitTestCase - this function produces one "bit test" @@ -1479,8 +1474,6 @@ else DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, DAG.getBasicBlock(NextMBB))); - - return; } void SelectionDAGLowering::visitInvoke(InvokeInst &I) { From gohman at apple.com Tue Jan 27 13:25:38 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 27 Jan 2009 19:25:38 -0000 Subject: [llvm-commits] [llvm] r63121 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.td Message-ID: <200901271925.n0RJPcYM017453@zion.cs.uiuc.edu> Author: djg Date: Tue Jan 27 13:25:38 2009 New Revision: 63121 URL: http://llvm.org/viewvc/llvm-project?rev=63121&view=rev Log: Reformat the allocation-order arrays to a more conventional style. Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=63121&r1=63120&r2=63121&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Tue Jan 27 13:25:38 2009 @@ -237,20 +237,23 @@ iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ - // Does the function dedicate RBP / EBP to being a frame ptr? - // If so, don't allocate SPL or BPL. - static const unsigned X86_GR8_AO_64_fp[] = - {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, - X86::R8B, X86::R9B, X86::R10B, X86::R11B, - X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B}; - // If not, just don't allocate SPL. - static const unsigned X86_GR8_AO_64[] = - {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, - X86::R8B, X86::R9B, X86::R10B, X86::R11B, - X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL}; - // In 32-mode, none of the 8-bit registers aliases EBP or ESP. - static const unsigned X86_GR8_AO_32[] = - {X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH}; + // Does the function dedicate RBP / EBP to being a frame ptr? + // If so, don't allocate SPL or BPL. + static const unsigned X86_GR8_AO_64_fp[] = { + X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, + X86::R8B, X86::R9B, X86::R10B, X86::R11B, + X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B + }; + // If not, just don't allocate SPL. + static const unsigned X86_GR8_AO_64[] = { + X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, + X86::R8B, X86::R9B, X86::R10B, X86::R11B, + X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL + }; + // In 32-mode, none of the 8-bit registers aliases EBP or ESP. + static const unsigned X86_GR8_AO_32[] = { + X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH + }; GR8Class::iterator GR8Class::allocation_order_begin(const MachineFunction &MF) const { @@ -290,21 +293,25 @@ iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ - // Does the function dedicate RBP / EBP to being a frame ptr? - // If so, don't allocate SP or BP. - static const unsigned X86_GR16_AO_64_fp[] = - {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, - X86::R8W, X86::R9W, X86::R10W, X86::R11W, - X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W}; - static const unsigned X86_GR16_AO_32_fp[] = - {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX}; - // If not, just don't allocate SPL. - static const unsigned X86_GR16_AO_64[] = - {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, - X86::R8W, X86::R9W, X86::R10W, X86::R11W, - X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP}; - static const unsigned X86_GR16_AO_32[] = - {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP}; + // Does the function dedicate RBP / EBP to being a frame ptr? + // If so, don't allocate SP or BP. + static const unsigned X86_GR16_AO_64_fp[] = { + X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, + X86::R8W, X86::R9W, X86::R10W, X86::R11W, + X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W + }; + static const unsigned X86_GR16_AO_32_fp[] = { + X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX + }; + // If not, just don't allocate SPL. + static const unsigned X86_GR16_AO_64[] = { + X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, + X86::R8W, X86::R9W, X86::R10W, X86::R11W, + X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP + }; + static const unsigned X86_GR16_AO_32[] = { + X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP + }; GR16Class::iterator GR16Class::allocation_order_begin(const MachineFunction &MF) const { @@ -354,21 +361,25 @@ iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ - // Does the function dedicate RBP / EBP to being a frame ptr? - // If so, don't allocate ESP or EBP. - static const unsigned X86_GR32_AO_64_fp[] = - {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, - X86::R8D, X86::R9D, X86::R10D, X86::R11D, - X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D}; - static const unsigned X86_GR32_AO_32_fp[] = - {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX}; - // If not, just don't allocate SPL. - static const unsigned X86_GR32_AO_64[] = - {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, - X86::R8D, X86::R9D, X86::R10D, X86::R11D, - X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP}; - static const unsigned X86_GR32_AO_32[] = - {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP}; + // Does the function dedicate RBP / EBP to being a frame ptr? + // If so, don't allocate ESP or EBP. + static const unsigned X86_GR32_AO_64_fp[] = { + X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, + X86::R8D, X86::R9D, X86::R10D, X86::R11D, + X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D + }; + static const unsigned X86_GR32_AO_32_fp[] = { + X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX + }; + // If not, just don't allocate SPL. + static const unsigned X86_GR32_AO_64[] = { + X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, + X86::R8D, X86::R9D, X86::R10D, X86::R11D, + X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP + }; + static const unsigned X86_GR32_AO_32[] = { + X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP + }; GR32Class::iterator GR32Class::allocation_order_begin(const MachineFunction &MF) const { From evan.cheng at apple.com Tue Jan 27 13:36:13 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 27 Jan 2009 19:36:13 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63123 - in /llvm-gcc-4.2/branches/Apple/Dib/gcc: cgraphunit.c ipa-inline.c passes.c tree-pass.h Message-ID: <200901271936.n0RJaEtC017856@zion.cs.uiuc.edu> Author: evancheng Date: Tue Jan 27 13:36:13 2009 New Revision: 63123 URL: http://llvm.org/viewvc/llvm-project?rev=63123&view=rev Log: Restore gcc inliner in teh Dib branch for now. It's exposing some performance issues. Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/cgraphunit.c llvm-gcc-4.2/branches/Apple/Dib/gcc/ipa-inline.c llvm-gcc-4.2/branches/Apple/Dib/gcc/passes.c llvm-gcc-4.2/branches/Apple/Dib/gcc/tree-pass.h Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/cgraphunit.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/cgraphunit.c?rev=63123&r1=63122&r2=63123&view=diff ============================================================================== --- llvm-gcc-4.2/branches/Apple/Dib/gcc/cgraphunit.c (original) +++ llvm-gcc-4.2/branches/Apple/Dib/gcc/cgraphunit.c Tue Jan 27 13:36:13 2009 @@ -1600,8 +1600,6 @@ return false; } -/* LLVM LOCAL begin */ -#ifndef ENABLE_LLVM static void ipa_passes (void) { @@ -1611,8 +1609,6 @@ execute_ipa_pass_list (all_ipa_passes); bitmap_obstack_release (NULL); } -#endif -/* LLVM LOCAL end */ /* Perform simple optimizations based on callgraph. */ @@ -1650,13 +1646,9 @@ dump_cgraph (cgraph_dump_file); } - /* LLVM LOCAL begin */ -#ifndef ENABLE_LLVM /* Don't run the IPA passes if there was any error or sorry messages. */ if (errorcount == 0 && sorrycount == 0) ipa_passes (); -#endif - /* LLVM LOCAL end */ /* This pass remove bodies of extern inline functions we never inlined. Do this later so other IPA passes see what is really going on. */ Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/ipa-inline.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/ipa-inline.c?rev=63123&r1=63122&r2=63123&view=diff ============================================================================== --- llvm-gcc-4.2/branches/Apple/Dib/gcc/ipa-inline.c (original) +++ llvm-gcc-4.2/branches/Apple/Dib/gcc/ipa-inline.c Tue Jan 27 13:36:13 2009 @@ -942,7 +942,11 @@ /* At the moment, no IPA passes change function bodies before inlining. Save some time by not recomputing function body sizes if early inlining already did so. */ + /* LLVM local begin - Don't rely on pass_early_ipa_inline being run. */ +#ifndef ENABLE_LLVM if (!flag_early_inlining) +#endif + /* LLVM local end */ node->local.self_insns = node->global.insns = estimate_num_insns (node->decl); @@ -1029,9 +1033,19 @@ overall_insns - old_insns); } + /* LLVM local begin */ +#ifdef ENABLE_LLVM + if (1) /* FIXME: 1 should be 0 some day, see PR2353. */ +#endif + /* LLVM local end*/ if (!flag_really_no_inline) cgraph_decide_inlining_of_small_functions (); + /* LLVM local begin */ +#ifdef ENABLE_LLVM + if (1) /* FIXME: 1 should be 0 some day, see PR2353. */ +#endif + /* LLVM local end*/ if (!flag_really_no_inline && flag_inline_functions_called_once) { @@ -1150,6 +1164,11 @@ } /* Now do the automatic inlining. */ + /* LLVM local begin */ +#ifdef ENABLE_LLVM + if (1) /* FIXME: 1 should be 0 some day, see PR2353. */ +#endif + /* LLVM local end */ if (!flag_really_no_inline) for (e = node->callees; e; e = e->next_callee) if (e->callee->local.inlinable Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/passes.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/passes.c?rev=63123&r1=63122&r2=63123&view=diff ============================================================================== --- llvm-gcc-4.2/branches/Apple/Dib/gcc/passes.c (original) +++ llvm-gcc-4.2/branches/Apple/Dib/gcc/passes.c Tue Jan 27 13:36:13 2009 @@ -333,11 +333,10 @@ /* The root of the compilation pass tree, once constructed. */ +struct tree_opt_pass *all_passes, *all_ipa_passes, *all_lowering_passes; /* LLVM LOCAL begin */ #ifdef ENABLE_LLVM -struct tree_opt_pass *all_lowering_passes, *all_extra_lowering_passes; -#else -struct tree_opt_pass *all_passes, *all_ipa_passes, *all_lowering_passes; +struct tree_opt_pass *all_extra_lowering_passes; #endif /* LLVM LOCAL end */ @@ -480,21 +479,23 @@ struct tree_opt_pass **p; #define NEXT_PASS(PASS) (p = next_pass_1 (p, &PASS)) - /* LLVM LOCAL begin */ -#ifndef ENABLE_LLVM /* Interprocedural optimization passes. */ p = &all_ipa_passes; + /* LLVM local begin */ +#ifndef ENABLE_LLVM NEXT_PASS (pass_early_ipa_inline); NEXT_PASS (pass_early_local_passes); NEXT_PASS (pass_ipa_cp); - NEXT_PASS (pass_ipa_inline); +#endif + NEXT_PASS (pass_ipa_inline); /* LLVM: inline functions marked always_inline */ +#ifndef ENABLE_LLVM NEXT_PASS (pass_ipa_reference); NEXT_PASS (pass_ipa_pure_const); NEXT_PASS (pass_ipa_type_escape); NEXT_PASS (pass_ipa_pta); - *p = NULL; #endif - /* LLVM LOCAL end */ + /* LLVM local end */ + *p = NULL; /* All passes needed to lower the function into shape optimizers can operate on. */ @@ -764,18 +765,14 @@ NEXT_PASS (pass_final); *p = NULL; #endif - /* LLVM LOCAL end */ + /* LLVM local end */ #undef NEXT_PASS /* Register the passes with the tree dump code. */ - /* LLVM LOCAL begin */ -#ifndef ENABLE_LLVM register_dump_files (all_ipa_passes, true, PROP_gimple_any | PROP_gimple_lcf | PROP_gimple_leh | PROP_cfg); -#endif - /* LLVM LOCAL end */ register_dump_files (all_lowering_passes, false, PROP_gimple_any); /* LLVM LOCAL begin */ #ifdef ENABLE_LLVM @@ -853,7 +850,6 @@ dump_file, dump_flags); else { -/* LLVM LOCAL begin */ #ifndef ENABLE_LLVM if (dump_flags & TDF_SLIM) print_rtl_slim_with_bb (dump_file, get_insns (), dump_flags); @@ -862,7 +858,6 @@ else print_rtl (dump_file, get_insns ()); #endif -/* LLVM LOCAL end */ if (curr_properties & PROP_cfg && graph_dump_format != no_graph && (dump_flags & TDF_GRAPH)) Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/tree-pass.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/tree-pass.h?rev=63123&r1=63122&r2=63123&view=diff ============================================================================== --- llvm-gcc-4.2/branches/Apple/Dib/gcc/tree-pass.h (original) +++ llvm-gcc-4.2/branches/Apple/Dib/gcc/tree-pass.h Tue Jan 27 13:36:13 2009 @@ -399,11 +399,10 @@ extern struct tree_opt_pass pass_rtl_seqabstr; /* The root of the compilation pass tree, once constructed. */ +extern struct tree_opt_pass *all_passes, *all_ipa_passes, *all_lowering_passes; /* LLVM LOCAL begin */ #ifdef ENABLE_LLVM -extern struct tree_opt_pass *all_lowering_passes, *all_extra_lowering_passes; -#else -extern struct tree_opt_pass *all_passes, *all_ipa_passes, *all_lowering_passes; +extern struct tree_opt_pass *all_extra_lowering_passes; #endif /* LLVM LOCAL end */ From isanbard at gmail.com Tue Jan 27 13:37:47 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 27 Jan 2009 19:37:47 -0000 Subject: [llvm-commits] [llvm] r63124 - /llvm/branches/Apple/Dib/test/Transforms/InstCombine/cast-store-gep.ll Message-ID: <200901271937.n0RJbl5J017911@zion.cs.uiuc.edu> Author: void Date: Tue Jan 27 13:37:47 2009 New Revision: 63124 URL: http://llvm.org/viewvc/llvm-project?rev=63124&view=rev Log: Forgot to commit testcase. Added: llvm/branches/Apple/Dib/test/Transforms/InstCombine/cast-store-gep.ll Added: llvm/branches/Apple/Dib/test/Transforms/InstCombine/cast-store-gep.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/Transforms/InstCombine/cast-store-gep.ll?rev=63124&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/Transforms/InstCombine/cast-store-gep.ll (added) +++ llvm/branches/Apple/Dib/test/Transforms/InstCombine/cast-store-gep.ll Tue Jan 27 13:37:47 2009 @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep inttoptr +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | not grep alloca + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-apple-darwin10.0" + %T = type { i8*, i8 } + +define i8* @test(i8* %Val, i64 %V) nounwind { +entry: + %A = alloca %T, align 8 + %mrv_gep = bitcast %T* %A to i64* ; [#uses=1] + %B = getelementptr %T* %A, i64 0, i32 0 ; [#uses=1] + + store i64 %V, i64* %mrv_gep + %C = load i8** %B, align 8 ; [#uses=1] + ret i8* %C +} From isanbard at gmail.com Tue Jan 27 13:38:19 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 27 Jan 2009 19:38:19 -0000 Subject: [llvm-commits] [llvm] r63125 - in /llvm/branches/Apple/Dib: lib/CodeGen/AsmPrinter/DwarfWriter.cpp test/DebugInfo/forwardDecl.ll Message-ID: <200901271938.n0RJcJkD017937@zion.cs.uiuc.edu> Author: void Date: Tue Jan 27 13:38:19 2009 New Revision: 63125 URL: http://llvm.org/viewvc/llvm-project?rev=63125&view=rev Log: Pull r63077 into Dib: Assorted debug info fixes. - DW_AT_bit_size is only suitable for bitfields. - Encode source location info for derived types. - Source location and type size info is not useful for subroutine_type (info is included in respective DISubprogram) and array_type. Modified: llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp llvm/branches/Apple/Dib/test/DebugInfo/forwardDecl.ll Modified: llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=63125&r1=63124&r2=63125&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Tue Jan 27 13:38:19 2009 @@ -1733,8 +1733,8 @@ // Add source line info if available and TyDesc is not a forward // declaration. - // FIXME - Enable this. if (!DTy.isForwardDecl()) - // FIXME - Enable this. AddSourceLine(&Buffer, *DTy); + if (!DTy.isForwardDecl()) + AddSourceLine(&Buffer, &DTy); } /// ConstructTypeDIE - Construct type DIE from DICompositeType. @@ -1815,20 +1815,23 @@ // Add name if not anonymous or intermediate type. if (!Name.empty()) AddString(&Buffer, DW_AT_name, DW_FORM_string, Name); - // Add size if non-zero (derived types might be zero-sized.) - if (Size) - AddUInt(&Buffer, DW_AT_byte_size, 0, Size); - else { - // Add zero size if it is not a forward declaration. - if (CTy.isForwardDecl()) - AddUInt(&Buffer, DW_AT_declaration, DW_FORM_flag, 1); - else - AddUInt(&Buffer, DW_AT_byte_size, 0, 0); + if (Tag == DW_TAG_enumeration_type || Tag == DW_TAG_structure_type + || Tag == DW_TAG_union_type) { + // Add size if non-zero (derived types might be zero-sized.) + if (Size) + AddUInt(&Buffer, DW_AT_byte_size, 0, Size); + else { + // Add zero size if it is not a forward declaration. + if (CTy.isForwardDecl()) + AddUInt(&Buffer, DW_AT_declaration, DW_FORM_flag, 1); + else + AddUInt(&Buffer, DW_AT_byte_size, 0, 0); + } + + // Add source line info if available. + if (!CTy.isForwardDecl()) + AddSourceLine(&Buffer, &CTy); } - - // Add source line info if available. - if (!CTy.isForwardDecl()) - AddSourceLine(&Buffer, &CTy); } // ConstructSubrangeDIE - Construct subrange DIE from DISubrange. @@ -1853,7 +1856,6 @@ AddUInt(&Buffer, DW_AT_GNU_vector, DW_FORM_flag, 1); DIArray Elements = CTy->getTypeArray(); - AddType(DW_Unit, &Buffer, CTy->getTypeDerivedFrom()); // Construct an anonymous type for index type. DIE IdxBuffer(DW_TAG_base_type); @@ -1906,7 +1908,7 @@ AddSourceLine(MemberDie, &DT); - AddUInt(MemberDie, DW_AT_bit_size, 0, DT.getSizeInBits()); + // FIXME _ Handle bitfields DIEBlock *Block = new DIEBlock(); AddUInt(Block, 0, DW_FORM_data1, DW_OP_plus_uconst); AddUInt(Block, 0, DW_FORM_udata, DT.getOffsetInBits() >> 3); Modified: llvm/branches/Apple/Dib/test/DebugInfo/forwardDecl.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/DebugInfo/forwardDecl.ll?rev=63125&r1=63124&r2=63125&view=diff ============================================================================== --- llvm/branches/Apple/Dib/test/DebugInfo/forwardDecl.ll (original) +++ llvm/branches/Apple/Dib/test/DebugInfo/forwardDecl.ll Tue Jan 27 13:38:19 2009 @@ -18,7 +18,7 @@ @.str3 = internal constant [4 x i8] c"foo\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] @llvm.dbg.variable = internal constant %llvm.dbg.variable.type { i32 393473, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([2 x i8]* @.str4, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 3, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=1] @.str4 = internal constant [2 x i8] c"x\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1] - at llvm.dbg.derivedtype = internal constant %llvm.dbg.derivedtype.type { i32 393231, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.derivedtype = internal constant %llvm.dbg.derivedtype.type { i32 393231, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] @llvm.dbg.compositetype = internal constant %llvm.dbg.compositetype.type { i32 393235, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([3 x i8]* @.str5, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 1, i64 0, i64 8, i64 0, i32 4, { }* null, { }* bitcast ([0 x { }*]* @llvm.dbg.array to { }*) }, section "llvm.metadata" ; <%llvm.dbg.compositetype.type*> [#uses=1] @.str5 = internal constant [3 x i8] c"ST\00", section "llvm.metadata" ; <[3 x i8]*> [#uses=1] @llvm.dbg.array = internal constant [0 x { }*] zeroinitializer, section "llvm.metadata" ; <[0 x { }*]*> [#uses=1] From dalej at apple.com Tue Jan 27 13:38:35 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 27 Jan 2009 11:38:35 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63087 - /llvm-gcc-4.2/trunk/gcc/tree-nested.c In-Reply-To: <11EA744B-ED1F-4B9C-8BBB-73CEEEAE702C@apple.com> References: <200901270202.n0R22aB6002964@zion.cs.uiuc.edu> <200901271347.46820.baldrick@free.fr> <46B005A4-AA7B-4856-BE11-153CC5F93AC9@apple.com> <200901271926.52091.baldrick@free.fr> <11EA744B-ED1F-4B9C-8BBB-73CEEEAE702C@apple.com> Message-ID: <33E4A122-4703-4341-8C05-301E9A9E80FD@apple.com> On Jan 27, 2009, at 10:30 AMPST, Dale Johannesen wrote: > On Jan 27, 2009, at 10:26 AMPST, Duncan Sands wrote: > >> Hi Dale, >>> >>>> It is here >>>> because I had to add a bunch of code to fix a long >>>> standing tree-nested bug in which nested function bodies >>>> and callers have different opinions as to whether >>>> the function takes a static chain parameter or not. >>>> This doesn't matter much for gcc because the parameter >>>> is passed out of line, but it is rather horrible for >>>> llvm-gcc because it is added as an explicit parameter >>>> to the function. I never got round to pushing this >>>> upstream, but I really should. Anyway, the assertion >>>> is checking that a nested subroutine (the root->outer >>>> check ensures that this is a nested subroutine) takes >>>> an extra parameter for passing variables belonging to >>>> the parent (the "static chain") if and only if either >>>> it itself accesses a variable belonging to its parent >>>> (in which case root->chain_field is not null) or one >>>> of its child nested subroutines does (in which case >>>> root->chain_decl is not null). >>>> >>>>> - gcc_assert (!root->outer || >>>>> - DECL_NO_STATIC_CHAIN (root->context) == >>>>> - !(root->chain_decl || root->chain_field)); >>>> >>>> If the assertion is failing, it seems to me that something >>>> bad is going on. >>> >>> You may be right, or this may be another case where ObjC isn't doing >>> what you expect (which you would probably consider abuse). I >>> concluded it was the latter, but you seem to understand what this >>> code is doing better than I, maybe you could look at the testcase? >> >> I will. Sadly I do understand the horror that is tree-nested, at >> least I used to. I had to in order to implement support for nested >> functions in llvm-gcc :( :) > > OK. I've also got a question in the guy who implemented the > "blocks" stuff in ObjC, who fortunately is still here:) He can > probably clarify what ObjC is doing. He says the intent is that blocks code should never access variables in the parent, thus we should never need a static chain. Ah, I see, the default is to assume a static chain (peculiar), so the problem is ObjC may need to set that bit explicitly, probably isn't doing that...you can put the assertion back if you like. From dalej at apple.com Tue Jan 27 13:40:58 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 27 Jan 2009 11:40:58 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63123 - in /llvm-gcc-4.2/branches/Apple/Dib/gcc: cgraphunit.c ipa-inline.c passes.c tree-pass.h In-Reply-To: <200901271936.n0RJaEtC017856@zion.cs.uiuc.edu> References: <200901271936.n0RJaEtC017856@zion.cs.uiuc.edu> Message-ID: <2B00F7FD-7B84-4EC8-8699-86B7E6F21B8F@apple.com> On Jan 27, 2009, at 11:36 AMPST, Evan Cheng wrote: > Author: evancheng > Date: Tue Jan 27 13:36:13 2009 > New Revision: 63123 > > URL: http://llvm.org/viewvc/llvm-project?rev=63123&view=rev > Log: > Restore gcc inliner in teh Dib branch for now. It's exposing some > performance issues. Is this some general performance issue, or just that some specific code that's been extensively tuned to work well with gcc's inliner doesn't work as well now? The latter would be expected. From evan.cheng at apple.com Tue Jan 27 13:51:42 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 27 Jan 2009 11:51:42 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63123 - in /llvm-gcc-4.2/branches/Apple/Dib/gcc: cgraphunit.c ipa-inline.c passes.c tree-pass.h In-Reply-To: <2B00F7FD-7B84-4EC8-8699-86B7E6F21B8F@apple.com> References: <200901271936.n0RJaEtC017856@zion.cs.uiuc.edu> <2B00F7FD-7B84-4EC8-8699-86B7E6F21B8F@apple.com> Message-ID: <920B3D83-A2F6-49E9-99CB-51502528872C@apple.com> On Jan 27, 2009, at 11:40 AM, Dale Johannesen wrote: > > On Jan 27, 2009, at 11:36 AMPST, Evan Cheng wrote: > >> Author: evancheng >> Date: Tue Jan 27 13:36:13 2009 >> New Revision: 63123 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=63123&view=rev >> Log: >> Restore gcc inliner in teh Dib branch for now. It's exposing some >> performance issues. > > Is this some general performance issue, or just that some specific > code that's been extensively tuned to work well with gcc's inliner > doesn't work as well now? The latter would be expected. > I considered it a general performance issue that just happen to be exposed by a particular test case. Evan From edwintorok at gmail.com Tue Jan 27 13:52:40 2009 From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=) Date: Tue, 27 Jan 2009 21:52:40 +0200 Subject: [llvm-commits] [llvm] r63079 - /llvm/trunk/test/FrontendC/x86-64-red-zone.c In-Reply-To: <200901270059.n0R0xt3h001002@zion.cs.uiuc.edu> References: <200901270059.n0R0xt3h001002@zion.cs.uiuc.edu> Message-ID: <497F6608.50805@gmail.com> On 2009-01-27 02:59, Dan Gohman wrote: > Author: djg > Date: Mon Jan 26 18:59:55 2009 > New Revision: 63079 > > URL: http://llvm.org/viewvc/llvm-project?rev=63079&view=rev > Log: > Add a FrontendC testcase for the x86-64 Red Zone feature, > to help verify that the feature may be disabled through > the -mno-red-zone option. > > Added: > llvm/trunk/test/FrontendC/x86-64-red-zone.c > > Added: llvm/trunk/test/FrontendC/x86-64-red-zone.c > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/x86-64-red-zone.c?rev=63079&view=auto > > ============================================================================== > --- llvm/trunk/test/FrontendC/x86-64-red-zone.c (added) > +++ llvm/trunk/test/FrontendC/x86-64-red-zone.c Mon Jan 26 18:59:55 2009 > @@ -0,0 +1,11 @@ > +// RUN: $llvmgcc -m64 -fomit-frame-pointer -O2 %s -S -o - > %t > +// RUN: not grep subq %t > +// RUN: not grep addq %t > +// RUN: grep {\\-4(%%rsp)} %t | count 2 > +// RUN: $llvmgcc -m64 -fomit-frame-pointer -O2 %s -S -o - -mno-red-zone > %t > +// RUN: grep subq %t | count 1 > +// RUN: grep addq %t | count 1 > +// This is a test for x86-64, add your target below if it FAILs. > +// XFAIL: alpha|ia64|arm|powerpc|sparc|x86 Hi Dan, I get an XPASS on x86_64. It appears that x86_64 == x86 for XFAIL :( Best regards, --Edwin From baldrick at free.fr Tue Jan 27 14:02:22 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 27 Jan 2009 21:02:22 +0100 Subject: [llvm-commits] [llvm-gcc-4.2] r63087 - /llvm-gcc-4.2/trunk/gcc/tree-nested.c In-Reply-To: <33E4A122-4703-4341-8C05-301E9A9E80FD@apple.com> References: <200901270202.n0R22aB6002964@zion.cs.uiuc.edu> <11EA744B-ED1F-4B9C-8BBB-73CEEEAE702C@apple.com> <33E4A122-4703-4341-8C05-301E9A9E80FD@apple.com> Message-ID: <200901272102.23091.baldrick@free.fr> Hi Dale, > He says the intent is that blocks code should never access variables > in the parent, thus we should never need a static chain. Ah, I see, > the default is to assume a static chain (peculiar), so the problem is > ObjC may need to set that bit explicitly, probably isn't doing > that...you can put the assertion back if you like. IIRC the way DECL_NO_STATIC_CHAIN works is: when creating trees (before tree-nested is run) you can set DECL_NO_STATIC_CHAIN on a nested function to indicate that it definitely doesn't need a static chain. So if blocks are known not to use static chains then they should set this. Later on, when tree-nested runs, IIRC, tree-nested examines functions with !DECL_NO_STATIC_CHAIN and works out which ones need chains, and sets DECL_NO_STATIC_CHAIN if none is needed. The Ada front-end sets DECL_NO_STATIC_CHAIN on functions declared as nested functions but imported from C (eg: you can import a C standard library function as a local nested function - using nesting for visibility control). Ciao, Duncan. From gohman at apple.com Tue Jan 27 14:39:34 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 27 Jan 2009 20:39:34 -0000 Subject: [llvm-commits] [llvm] r63128 - in /llvm/trunk: include/llvm/CodeGen/ValueTypes.h lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200901272039.n0RKdYAi020445@zion.cs.uiuc.edu> Author: djg Date: Tue Jan 27 14:39:34 2009 New Revision: 63128 URL: http://llvm.org/viewvc/llvm-project?rev=63128&view=rev Log: Add an assertion to the form of SelectionDAG::getConstant that takes a uint64_t to verify that the value is in range for the given type, to help catch accidental overflow. Fix a few places that relied on getConstant implicitly truncating the value. Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.h?rev=63128&r1=63127&r2=63128&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original) +++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Tue Jan 27 14:39:34 2009 @@ -444,8 +444,11 @@ /// getIntegerVTBitMask - Return an integer with 1's every place there are /// bits in the specified integer value type. FIXME: Should return an apint. uint64_t getIntegerVTBitMask() const { - assert(isInteger() && !isVector() && "Only applies to int scalars!"); - return ~uint64_t(0UL) >> (64-getSizeInBits()); + assert(isInteger() && "Only applies to integers!"); + MVT EltVT = isVector() ? getVectorElementType() : *this; + assert(EltVT.getSizeInBits() <= 64 && + "getIntegerVTBitMask doesn't use APInt!"); + return ~uint64_t(0UL) >> (64-EltVT.getSizeInBits()); } /// getIntegerVTSignBit - Return an integer with a 1 in the position of the Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63128&r1=63127&r2=63128&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Jan 27 14:39:34 2009 @@ -2434,11 +2434,12 @@ if (ConstantSDNode *N101C = dyn_cast(N101)) { MVT TruncVT = N1.getValueType(); SDValue N100 = N1.getOperand(0).getOperand(0); + uint64_t TruncC = TruncVT.getIntegerVTBitMask() & + N101C->getZExtValue(); return DAG.getNode(ISD::SHL, VT, N0, DAG.getNode(ISD::AND, TruncVT, DAG.getNode(ISD::TRUNCATE, TruncVT, N100), - DAG.getConstant(N101C->getZExtValue(), - TruncVT))); + DAG.getConstant(TruncC, TruncVT))); } } @@ -2561,11 +2562,12 @@ if (ConstantSDNode *N101C = dyn_cast(N101)) { MVT TruncVT = N1.getValueType(); SDValue N100 = N1.getOperand(0).getOperand(0); + uint64_t TruncC = TruncVT.getIntegerVTBitMask() & + N101C->getZExtValue(); return DAG.getNode(ISD::SRA, VT, N0, DAG.getNode(ISD::AND, TruncVT, DAG.getNode(ISD::TRUNCATE, TruncVT, N100), - DAG.getConstant(N101C->getZExtValue(), - TruncVT))); + DAG.getConstant(TruncC, TruncVT))); } } @@ -2678,11 +2680,12 @@ if (ConstantSDNode *N101C = dyn_cast(N101)) { MVT TruncVT = N1.getValueType(); SDValue N100 = N1.getOperand(0).getOperand(0); + uint64_t TruncC = TruncVT.getIntegerVTBitMask() & + N101C->getZExtValue(); return DAG.getNode(ISD::SRL, VT, N0, DAG.getNode(ISD::AND, TruncVT, DAG.getNode(ISD::TRUNCATE, TruncVT, N100), - DAG.getConstant(N101C->getZExtValue(), - TruncVT))); + DAG.getConstant(TruncC, TruncVT))); } } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63128&r1=63127&r2=63128&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Jan 27 14:39:34 2009 @@ -6293,7 +6293,7 @@ unsigned len = VT.getSizeInBits(); for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) - SDValue Tmp2 = DAG.getConstant(mask[i], VT); + SDValue Tmp2 = DAG.getConstant(VT.getIntegerVTBitMask() & mask[i], VT); SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), DAG.getNode(ISD::AND, VT, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63128&r1=63127&r2=63128&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Jan 27 14:39:34 2009 @@ -848,6 +848,9 @@ SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; + assert((EltVT.getSizeInBits() >= 64 || + (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) && + "getConstant with a uint64_t value that doesn't fit in the type!"); return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); } From isanbard at gmail.com Tue Jan 27 14:45:22 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 27 Jan 2009 20:45:22 -0000 Subject: [llvm-commits] [llvm] r63130 - /llvm/tags/Apple/llvmCore-2094/ Message-ID: <200901272045.n0RKjMDn020663@zion.cs.uiuc.edu> Author: void Date: Tue Jan 27 14:45:22 2009 New Revision: 63130 URL: http://llvm.org/viewvc/llvm-project?rev=63130&view=rev Log: Tag Dib to llvmCore-2094. Added: llvm/tags/Apple/llvmCore-2094/ - copied from r63129, llvm/branches/Apple/Dib/ From isanbard at gmail.com Tue Jan 27 14:46:00 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 27 Jan 2009 20:46:00 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63131 - /llvm-gcc-4.2/tags/Apple/llvmgcc42-2094/ Message-ID: <200901272046.n0RKk0IZ020694@zion.cs.uiuc.edu> Author: void Date: Tue Jan 27 14:46:00 2009 New Revision: 63131 URL: http://llvm.org/viewvc/llvm-project?rev=63131&view=rev Log: Tag Dib to llvmgcc42-2094. Added: llvm-gcc-4.2/tags/Apple/llvmgcc42-2094/ - copied from r63130, llvm-gcc-4.2/branches/Apple/Dib/ From dalej at apple.com Tue Jan 27 14:57:26 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 27 Jan 2009 12:57:26 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63123 - in /llvm-gcc-4.2/branches/Apple/Dib/gcc: cgraphunit.c ipa-inline.c passes.c tree-pass.h In-Reply-To: <920B3D83-A2F6-49E9-99CB-51502528872C@apple.com> References: <200901271936.n0RJaEtC017856@zion.cs.uiuc.edu> <2B00F7FD-7B84-4EC8-8699-86B7E6F21B8F@apple.com> <920B3D83-A2F6-49E9-99CB-51502528872C@apple.com> Message-ID: <85B32A50-F86B-47D3-B238-D3DDC92FE222@apple.com> On Jan 27, 2009, at 11:51 AMPST, Evan Cheng wrote: > On Jan 27, 2009, at 11:40 AM, Dale Johannesen wrote: >> On Jan 27, 2009, at 11:36 AMPST, Evan Cheng wrote: >> >>> Author: evancheng >>> Date: Tue Jan 27 13:36:13 2009 >>> New Revision: 63123 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=63123&view=rev >>> Log: >>> Restore gcc inliner in teh Dib branch for now. It's exposing some >>> performance issues. >> >> Is this some general performance issue, or just that some specific >> code that's been extensively tuned to work well with gcc's inliner >> doesn't work as well now? The latter would be expected > > I considered it a general performance issue that just happen to be > exposed by a particular test case. Do you have evidence for this? I've looked at it quite a bit, and concluded that llvm-gcc's inliner does less inlining on average than gcc's, but that this is not, in general, a problem: in other words, benchmarks that are better and worse are about equal in number. (And performance being roughly equal, smaller code size is to be preferred.) I understand that some benchmarks are more important than others in particular situations, and I'm not objecting to the patch, but I think you are overgeneralizing what the problem is. From clattner at apple.com Tue Jan 27 15:03:44 2009 From: clattner at apple.com (Chris Lattner) Date: Tue, 27 Jan 2009 13:03:44 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63123 - in /llvm-gcc-4.2/branches/Apple/Dib/gcc: cgraphunit.c ipa-inline.c passes.c tree-pass.h In-Reply-To: <85B32A50-F86B-47D3-B238-D3DDC92FE222@apple.com> References: <200901271936.n0RJaEtC017856@zion.cs.uiuc.edu> <2B00F7FD-7B84-4EC8-8699-86B7E6F21B8F@apple.com> <920B3D83-A2F6-49E9-99CB-51502528872C@apple.com> <85B32A50-F86B-47D3-B238-D3DDC92FE222@apple.com> Message-ID: <614897D8-AAAF-4305-A880-4B648276B795@apple.com> On Jan 27, 2009, at 12:57 PM, Dale Johannesen wrote: >>> Is this some general performance issue, or just that some specific >>> code that's been extensively tuned to work well with gcc's inliner >>> doesn't work as well now? The latter would be expected >> >> I considered it a general performance issue that just happen to be >> exposed by a particular test case. > > Do you have evidence for this? I've looked at it quite a bit, and > concluded that llvm-gcc's inliner does less inlining on average than > gcc's, but that this is not, in general, a problem: in other words, > benchmarks that are better and worse are about equal in number. > (And performance being roughly equal, smaller code size is to be > preferred.) I can give two easy examples. 1: SROA is not promoting aggregates in all cases that it could. This is particularly a problem for the "by value struct passing" stuff in the ABI lowering code of llvmgcc. 2: llvm's optimizer doesn't do C++ copy constructor elision. Both of these mean that if the GCC inliner runs before tree -> LLVM, that you'll get the optimizations and performance will be good. Running tree -> LLVM before the LLVM inliner will prevent these from happening. -Chris From dalej at apple.com Tue Jan 27 15:09:09 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 27 Jan 2009 13:09:09 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63123 - in /llvm-gcc-4.2/branches/Apple/Dib/gcc: cgraphunit.c ipa-inline.c passes.c tree-pass.h In-Reply-To: <614897D8-AAAF-4305-A880-4B648276B795@apple.com> References: <200901271936.n0RJaEtC017856@zion.cs.uiuc.edu> <2B00F7FD-7B84-4EC8-8699-86B7E6F21B8F@apple.com> <920B3D83-A2F6-49E9-99CB-51502528872C@apple.com> <85B32A50-F86B-47D3-B238-D3DDC92FE222@apple.com> <614897D8-AAAF-4305-A880-4B648276B795@apple.com> Message-ID: <8E59CBD3-DAA0-4779-8E9D-334748AE4407@apple.com> On Jan 27, 2009, at 1:03 PMPST, Chris Lattner wrote: > On Jan 27, 2009, at 12:57 PM, Dale Johannesen wrote: >>>> Is this some general performance issue, or just that some specific >>>> code that's been extensively tuned to work well with gcc's inliner >>>> doesn't work as well now? The latter would be expected >>> >>> I considered it a general performance issue that just happen to be >>> exposed by a particular test case. >> >> Do you have evidence for this? I've looked at it quite a bit, and >> concluded that llvm-gcc's inliner does less inlining on average than >> gcc's, but that this is not, in general, a problem: in other words, >> benchmarks that are better and worse are about equal in number. >> (And performance being roughly equal, smaller code size is to be >> preferred.) > > I can give two easy examples. 1: SROA is not promoting aggregates in > all cases that it could. This is particularly a problem for the "by > value struct passing" stuff in the ABI lowering code of llvmgcc. 2: > llvm's optimizer doesn't do C++ copy constructor elision. > > Both of these mean that if the GCC inliner runs before tree -> LLVM, > that you'll get the optimizations and performance will be good. > Running tree -> LLVM before the LLVM inliner will prevent these from > happening. Ah OK, these are not issues with the inliner itself but with other missing optimizations. I read Evan's message as saying this was a general issue with the inliner, but I see he didn't say that. Going away now. From evan.cheng at apple.com Tue Jan 27 15:15:07 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 27 Jan 2009 21:15:07 -0000 Subject: [llvm-commits] [llvm] r63132 - in /llvm/trunk: include/llvm/CodeGen/DebugLoc.h include/llvm/CodeGen/MachineFunction.h lib/CodeGen/MachineFunction.cpp Message-ID: <200901272115.n0RLF7a7021730@zion.cs.uiuc.edu> Author: evancheng Date: Tue Jan 27 15:15:07 2009 New Revision: 63132 URL: http://llvm.org/viewvc/llvm-project?rev=63132&view=rev Log: Refine DebugLoc per review comments. Modified: llvm/trunk/include/llvm/CodeGen/DebugLoc.h llvm/trunk/include/llvm/CodeGen/MachineFunction.h llvm/trunk/lib/CodeGen/MachineFunction.cpp Modified: llvm/trunk/include/llvm/CodeGen/DebugLoc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DebugLoc.h?rev=63132&r1=63131&r2=63132&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/DebugLoc.h (original) +++ llvm/trunk/include/llvm/CodeGen/DebugLoc.h Tue Jan 27 15:15:07 2009 @@ -33,16 +33,21 @@ unsigned Idx; public: - DebugLoc() : Idx(~0U) {} + DebugLoc() : Idx(~0U) {} // Defaults to invalid. - static DebugLoc getNoDebugLoc() { DebugLoc L; L.Idx = 0; return L; } + static DebugLoc getUnknownLoc() { DebugLoc L; L.Idx = 0; return L; } static DebugLoc get(unsigned idx) { DebugLoc L; L.Idx = idx; return L; } - bool isInvalid() { return Idx == ~0U; } - bool isUnknown() { return Idx == 0; } + // isInvalid - Return true if the DebugLoc is invalid. + bool isInvalid() const { return Idx == ~0U; } + + // isUnknown - Return true if there is no debug info for the SDNode / + // MachineInstr. + bool isUnknown() const { return Idx == 0; } }; - struct DebugLocTupleDenseMapInfo { + // Partially specialize DenseMapInfo for DebugLocTyple. + template<> struct DenseMapInfo { static inline DebugLocTuple getEmptyKey() { return DebugLocTuple(~0U, ~0U, ~0U); } @@ -63,9 +68,6 @@ static bool isPod() { return true; } }; - typedef DenseMap - DebugIdMapType; - /// DebugLocTracker - This class tracks debug location information. /// struct DebugLocTracker { @@ -75,7 +77,7 @@ // DebugIdsMap - This maps DebugLocTuple's to indices into // DebugLocations vector. - DebugIdMapType DebugIdMap; + DenseMap DebugIdMap; DebugLocTracker() {} Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=63132&r1=63131&r2=63132&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Tue Jan 27 15:15:07 2009 @@ -311,10 +311,10 @@ // Debug location. // - /// lookUpDebugLocId - Look up the DebugLocTuple index with the given - /// source file, line, and column. It may add a new filename and / or - /// a new DebugLocTuple. - unsigned lookUpDebugLocId(unsigned Src, unsigned Line, unsigned Col); + /// getOrCreateDebugLocID - Look up the DebugLocTuple index with the given + /// source file, line, and column. If none currently exists, create add a new + /// new DebugLocTuple and insert it into the DebugIdMap. + unsigned getOrCreateDebugLocID(unsigned Src, unsigned Line, unsigned Col); }; //===--------------------------------------------------------------------===// Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=63132&r1=63131&r2=63132&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Jan 27 15:15:07 2009 @@ -378,13 +378,14 @@ return *mc; } -/// lookUpDebugLocId - Look up the DebugLocTuple index with the given -/// source file, line, and column. It may add a new filename and / or -/// a new DebugLocTuple. -unsigned MachineFunction::lookUpDebugLocId(unsigned Src, unsigned Line, - unsigned Col) { +/// getOrCreateDebugLocID - Look up the DebugLocTuple index with the given +/// source file, line, and column. If none currently exists, create add a new +/// new DebugLocTuple and insert it into the DebugIdMap. +unsigned MachineFunction::getOrCreateDebugLocID(unsigned Src, unsigned Line, + unsigned Col) { struct DebugLocTuple Tuple(Src, Line, Col); - DebugIdMapType::iterator II = DebugLocInfo.DebugIdMap.find(Tuple); + DenseMap::iterator II + = DebugLocInfo.DebugIdMap.find(Tuple); if (II != DebugLocInfo.DebugIdMap.end()) return II->second; // Add a new tuple. From dpatel at apple.com Tue Jan 27 15:18:46 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 27 Jan 2009 21:18:46 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63133 - in /llvm-gcc-4.2/trunk/gcc: llvm-debug.cpp llvm-debug.h Message-ID: <200901272118.n0RLIk5t021876@zion.cs.uiuc.edu> Author: dpatel Date: Tue Jan 27 15:18:46 2009 New Revision: 63133 URL: http://llvm.org/viewvc/llvm-project?rev=63133&view=rev Log: Keep track of context info. findRegion() is not comprehensive enough to find appropriate scope in all cases, but it is significantly better then what llvm-gcc ever did for debug info. Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp llvm-gcc-4.2/trunk/gcc/llvm-debug.h Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp?rev=63133&r1=63132&r2=63133&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Tue Jan 27 15:18:46 2009 @@ -214,39 +214,51 @@ const char *FnName = GetNodeName(FnDecl); const char *LinkageName = getLinkageName(FnDecl); - tree func_type = TREE_TYPE(FnDecl); - llvm::SmallVector ArgTys; - // Add the result type at least. - ArgTys.push_back(getOrCreateType(TREE_TYPE(func_type))); - - // Set up remainder of arguments. - for (tree arg = TYPE_ARG_TYPES(func_type); arg; arg = TREE_CHAIN(arg)) { - tree formal_type = TREE_VALUE(arg); - if (formal_type == void_type_node) break; - ArgTys.push_back(getOrCreateType(formal_type)); - } - - llvm::DIArray FnTypeArray = - DebugFactory.GetOrCreateArray(&ArgTys[0], ArgTys.size()); - - llvm::DICompositeType FnTy = - DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_subroutine_type, - MainCompileUnit, "", - MainCompileUnit, 0, 0, 0, 0, 0, - llvm::DIType(), FnTypeArray); - - DISubprogram SP = DebugFactory.CreateSubprogram(MainCompileUnit, - FnName, FnName, LinkageName, - MainCompileUnit, CurLineNo, - FnTy, - Fn->hasInternalLinkage(), - true /*definition*/, - &Filename, &Directory); + DISubprogram SP = + DebugFactory.CreateSubprogram(findRegion(FnDecl), + FnName, FnName, LinkageName, + MainCompileUnit, CurLineNo, + getOrCreateType(TREE_TYPE(FnDecl)), + Fn->hasInternalLinkage(), + true /*definition*/, + &Filename, &Directory); DebugFactory.InsertSubprogramStart(SP, CurBB); // Push function on region stack. RegionStack.push_back(SP); + RegionMap[FnDecl] = SP; +} + + /// findRegion - Find tree_node N's region. +DIDescriptor DebugInfo::findRegion(tree Node) { + if (Node == NULL_TREE) + return MainCompileUnit; + + std::map::iterator I = RegionMap.find(Node); + if (I != RegionMap.end()) + return I->second; + + if (TYPE_P (Node)) { + if (TYPE_CONTEXT (Node)) + return findRegion (TYPE_CONTEXT(Node)); + } else if (DECL_P (Node)) { + tree decl = Node; + tree context = NULL_TREE; + if (TREE_CODE (decl) != FUNCTION_DECL || ! DECL_VINDEX (decl)) + context = DECL_CONTEXT (decl); + else + context = TYPE_MAIN_VARIANT + (TREE_TYPE (TREE_VALUE (TYPE_ARG_TYPES (TREE_TYPE (decl))))); + + if (context && !TYPE_P (context)) + context = NULL_TREE; + if (context != NULL_TREE) + return findRegion(context); + } + + // Otherwise main compile unit covers everything. + return MainCompileUnit; } /// EmitRegionStart- Constructs the debug code for entering a declarative @@ -397,7 +409,7 @@ DebugFactory.GetOrCreateArray(&EltTys[0], EltTys.size()); return DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_subroutine_type, - MainCompileUnit, "", + findRegion(type), "", MainCompileUnit, 0, 0, 0, 0, 0, llvm::DIType(), EltTypeArray); } @@ -412,7 +424,7 @@ TREE_CODE(type) == BLOCK_POINTER_TYPE) ? DW_TAG_pointer_type : DW_TAG_reference_type; - return DebugFactory.CreateDerivedType(Tag, MainCompileUnit, "", + return DebugFactory.CreateDerivedType(Tag, findRegion(type), "", MainCompileUnit, 0 /*line no*/, NodeSizeInBits(type), NodeAlignInBits(type), @@ -466,7 +478,7 @@ DebugFactory.GetOrCreateArray(&Subscripts[0], Subscripts.size()); return DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_array_type, - MainCompileUnit, "", + findRegion(type), "", MainCompileUnit, 0, NodeSizeInBits(type), NodeAlignInBits(type), 0, 0, @@ -500,7 +512,7 @@ DirectoryAndFile(Loc.file, Directory, Filename); } return DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_enumeration_type, - MainCompileUnit, GetNodeName(type), + findRegion(type), GetNodeName(type), MainCompileUnit, Loc.line, NodeSizeInBits(type), NodeAlignInBits(type), 0, 0, @@ -526,7 +538,9 @@ std::string Filename, Directory; DirectoryAndFile(Loc.file, Directory, Filename); llvm::DIType FwdDecl = - DebugFactory.CreateCompositeType(Tag, MainCompileUnit, GetNodeName(type), + DebugFactory.CreateCompositeType(Tag, + findRegion(type), + GetNodeName(type), MainCompileUnit, Loc.line, 0, 0, 0, llvm::DIType::FlagFwdDecl, llvm::DIType(), llvm::DIArray(), @@ -554,7 +568,7 @@ // FIXME : name, size, align etc... DIType DTy = DebugFactory.CreateDerivedType(DW_TAG_inheritance, - MainCompileUnit,"", + findRegion(type),"", MainCompileUnit, 0,0,0, getInt64(BINFO_OFFSET(BInfo), 0), 0, BaseClass); @@ -595,7 +609,7 @@ Flags = llvm::DIType::FlagPrivate; DIType DTy = - DebugFactory.CreateDerivedType(DW_TAG_member, MainCompileUnit, + DebugFactory.CreateDerivedType(DW_TAG_member, findRegion(Member), MemberName, MainCompileUnit, MemLoc.line, NodeSizeInBits(Member), NodeAlignInBits(FieldNodeType), @@ -622,7 +636,7 @@ const char *LinkageName = getLinkageName(Member); DIType SPTy = getOrCreateType(TREE_TYPE(Member)); DISubprogram SP = - DebugFactory.CreateSubprogram(MainCompileUnit, MemberName, MemberName, + DebugFactory.CreateSubprogram(findRegion(Member), MemberName, MemberName, LinkageName, MainCompileUnit, MemLoc.line, SPTy, false, false, &MemFilename, &MemDirectory); @@ -634,7 +648,7 @@ DebugFactory.GetOrCreateArray(&EltTys[0], EltTys.size()); llvm::DIType RealDecl = - DebugFactory.CreateCompositeType(Tag, MainCompileUnit, + DebugFactory.CreateCompositeType(Tag, findRegion(type), GetNodeName(type), MainCompileUnit, Loc.line, NodeSizeInBits(type), NodeAlignInBits(type), @@ -657,7 +671,7 @@ expanded_location TypeDefLoc = GetNodeLocation(Name); std::string Filename, Directory; DirectoryAndFile(TypeDefLoc.file, Directory, Filename); - Ty = DebugFactory.CreateDerivedType(DW_TAG_typedef, MainCompileUnit, + Ty = DebugFactory.CreateDerivedType(DW_TAG_typedef, findRegion(type), GetNodeName(Name), MainCompileUnit, TypeDefLoc.line, 0 /*size*/, @@ -673,7 +687,7 @@ if (TYPE_VOLATILE(type)) { Ty = DebugFactory.CreateDerivedType(DW_TAG_volatile_type, - MainCompileUnit, "", + findRegion(type), "", MainCompileUnit, 0 /*line no*/, NodeSizeInBits(type), NodeAlignInBits(type), @@ -685,7 +699,7 @@ if (TYPE_READONLY(type)) Ty = DebugFactory.CreateDerivedType(DW_TAG_const_type, - MainCompileUnit, "", + findRegion(type), "", MainCompileUnit, 0 /*line no*/, NodeSizeInBits(type), NodeAlignInBits(type), Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.h?rev=63133&r1=63132&r2=63133&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-debug.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-debug.h Tue Jan 27 15:18:46 2009 @@ -66,6 +66,7 @@ std::vector RegionStack; // Stack to track declarative scopes. + std::map RegionMap; public: DebugInfo(Module *m); @@ -126,7 +127,9 @@ /// createCompileUnit - Create a new compile unit. DICompileUnit createCompileUnit(const std::string &FullPath); - + + /// findRegion - Find tree_node N's region. + DIDescriptor findRegion(tree_node *n); }; } // end namespace llvm From dalej at apple.com Tue Jan 27 15:41:04 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 27 Jan 2009 21:41:04 -0000 Subject: [llvm-commits] [llvm] r63136 - /llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Message-ID: <200901272141.n0RLf4rE022850@zion.cs.uiuc.edu> Author: johannes Date: Tue Jan 27 15:41:04 2009 New Revision: 63136 URL: http://llvm.org/viewvc/llvm-project?rev=63136&view=rev Log: Add DebugLoc field and simple accessors. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=63136&r1=63135&r2=63136&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Tue Jan 27 15:41:04 2009 @@ -30,6 +30,7 @@ #include "llvm/Support/Allocator.h" #include "llvm/Support/RecyclingAllocator.h" #include "llvm/Support/DataTypes.h" +#include "llvm/CodeGen/DebugLoc.h" #include namespace llvm { @@ -901,6 +902,7 @@ inline bool isTargetOpcode() const; inline bool isMachineOpcode() const; inline unsigned getMachineOpcode() const; + inline DebugLoc getDebugLoc() const; /// reachesChainWithoutSideEffects - Return true if this operand (which must @@ -1077,6 +1079,9 @@ /// NodeId - Unique id per SDNode in the DAG. int NodeId; + /// debugLoc - source line information. + DebugLoc debugLoc; + /// OperandList - The values that are used by this operation. /// SDUse *OperandList; @@ -1146,6 +1151,12 @@ /// setNodeId - Set unique node id. void setNodeId(int Id) { NodeId = Id; } + /// getDebugLoc - Return the source location info. + DebugLoc getDebugLoc() const { return debugLoc; } + + /// setDebugLoc - Set source location info. + void setDebugLoc(DebugLoc sl) { debugLoc = sl; } + /// use_iterator - This class provides iterator support for SDUse /// operands that use a specific SDNode. class use_iterator @@ -1326,9 +1337,11 @@ return Ret; } + /// The constructors that supply DebugLoc explicitly should be preferred + /// for new code. SDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, unsigned NumOps) : NodeType(Opc), OperandsNeedDelete(true), SubclassData(0), - NodeId(-1), + NodeId(-1), debugLoc(DebugLoc::getNoDebugLoc()), OperandList(NumOps ? new SDUse[NumOps] : 0), ValueList(VTs.VTs), NumOperands(NumOps), NumValues(VTs.NumVTs), @@ -1343,8 +1356,33 @@ /// set later with InitOperands. SDNode(unsigned Opc, SDVTList VTs) : NodeType(Opc), OperandsNeedDelete(false), SubclassData(0), - NodeId(-1), OperandList(0), ValueList(VTs.VTs), - NumOperands(0), NumValues(VTs.NumVTs), + NodeId(-1), debugLoc(DebugLoc::getNoDebugLoc()), OperandList(0), + ValueList(VTs.VTs), NumOperands(0), NumValues(VTs.NumVTs), + UseList(NULL) {} + + /// The next two constructors specify DebugLoc explicitly; the intent + /// is that they will replace the above two over time, and eventually + /// the ones above can be removed. + SDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, unsigned NumOps, + DebugLoc sl) + : NodeType(Opc), OperandsNeedDelete(true), SubclassData(0), + NodeId(-1), debugLoc(sl), + OperandList(NumOps ? new SDUse[NumOps] : 0), + ValueList(VTs.VTs), + NumOperands(NumOps), NumValues(VTs.NumVTs), + UseList(NULL) { + for (unsigned i = 0; i != NumOps; ++i) { + OperandList[i].setUser(this); + OperandList[i].setInitial(Ops[i]); + } + } + + /// This constructor adds no operands itself; operands can be + /// set later with InitOperands. + SDNode(unsigned Opc, SDVTList VTs, DebugLoc sl) + : NodeType(Opc), OperandsNeedDelete(false), SubclassData(0), + NodeId(-1), debugLoc(sl), OperandList(0), + ValueList(VTs.VTs), NumOperands(0), NumValues(VTs.NumVTs), UseList(NULL) {} /// InitOperands - Initialize the operands list of this with 1 operand. @@ -1441,6 +1479,9 @@ inline bool SDValue::hasOneUse() const { return Node->hasNUsesOfValue(1, ResNo); } +inline DebugLoc SDValue::getDebugLoc() const { + return Node->getDebugLoc(); +} // Define inline functions from the SDUse class. From evan.cheng at apple.com Tue Jan 27 15:46:11 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 27 Jan 2009 13:46:11 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63133 - in /llvm-gcc-4.2/trunk/gcc: llvm-debug.cpp llvm-debug.h In-Reply-To: <200901272118.n0RLIk5t021876@zion.cs.uiuc.edu> References: <200901272118.n0RLIk5t021876@zion.cs.uiuc.edu> Message-ID: Unless you believe RegionMap is going to be large. DenseMap is probably the better choice. Evan On Jan 27, 2009, at 1:18 PM, Devang Patel wrote: > Author: dpatel > Date: Tue Jan 27 15:18:46 2009 > New Revision: 63133 > > URL: http://llvm.org/viewvc/llvm-project?rev=63133&view=rev > Log: > Keep track of context info. findRegion() is not comprehensive enough > to find appropriate scope in all cases, but it is significantly > better then what llvm-gcc ever did for debug info. > > > Modified: > llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp > llvm-gcc-4.2/trunk/gcc/llvm-debug.h > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp?rev=63133&r1=63132&r2=63133&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Tue Jan 27 15:18:46 2009 > @@ -214,39 +214,51 @@ > const char *FnName = GetNodeName(FnDecl); > const char *LinkageName = getLinkageName(FnDecl); > > - tree func_type = TREE_TYPE(FnDecl); > - llvm::SmallVector ArgTys; > - // Add the result type at least. > - ArgTys.push_back(getOrCreateType(TREE_TYPE(func_type))); > - > - // Set up remainder of arguments. > - for (tree arg = TYPE_ARG_TYPES(func_type); arg; arg = > TREE_CHAIN(arg)) { > - tree formal_type = TREE_VALUE(arg); > - if (formal_type == void_type_node) break; > - ArgTys.push_back(getOrCreateType(formal_type)); > - } > - > - llvm::DIArray FnTypeArray = > - DebugFactory.GetOrCreateArray(&ArgTys[0], ArgTys.size()); > - > - llvm::DICompositeType FnTy = > - > DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_subroutine_type, > - MainCompileUnit, "", > - MainCompileUnit, 0, 0, 0, 0, 0, > - llvm::DIType(), FnTypeArray); > - > - DISubprogram SP = DebugFactory.CreateSubprogram(MainCompileUnit, > - FnName, FnName, > LinkageName, > - MainCompileUnit, > CurLineNo, > - FnTy, > - Fn- > >hasInternalLinkage(), > - true / > *definition*/, > - &Filename, > &Directory); > + DISubprogram SP = > + DebugFactory.CreateSubprogram(findRegion(FnDecl), > + FnName, FnName, LinkageName, > + MainCompileUnit, CurLineNo, > + getOrCreateType(TREE_TYPE(FnDecl)), > + Fn->hasInternalLinkage(), > + true /*definition*/, > + &Filename, &Directory); > > DebugFactory.InsertSubprogramStart(SP, CurBB); > > // Push function on region stack. > RegionStack.push_back(SP); > + RegionMap[FnDecl] = SP; > +} > + > + /// findRegion - Find tree_node N's region. > +DIDescriptor DebugInfo::findRegion(tree Node) { > + if (Node == NULL_TREE) > + return MainCompileUnit; > + > + std::map::iterator I = > RegionMap.find(Node); > + if (I != RegionMap.end()) > + return I->second; > + > + if (TYPE_P (Node)) { > + if (TYPE_CONTEXT (Node)) > + return findRegion (TYPE_CONTEXT(Node)); > + } else if (DECL_P (Node)) { > + tree decl = Node; > + tree context = NULL_TREE; > + if (TREE_CODE (decl) != FUNCTION_DECL || ! DECL_VINDEX (decl)) > + context = DECL_CONTEXT (decl); > + else > + context = TYPE_MAIN_VARIANT > + (TREE_TYPE (TREE_VALUE (TYPE_ARG_TYPES (TREE_TYPE (decl))))); > + > + if (context && !TYPE_P (context)) > + context = NULL_TREE; > + if (context != NULL_TREE) > + return findRegion(context); > + } > + > + // Otherwise main compile unit covers everything. > + return MainCompileUnit; > } > > /// EmitRegionStart- Constructs the debug code for entering a > declarative > @@ -397,7 +409,7 @@ > DebugFactory.GetOrCreateArray(&EltTys[0], EltTys.size()); > > return > DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_subroutine_type, > - MainCompileUnit, "", > + findRegion(type), "", > MainCompileUnit, 0, 0, 0, > 0, 0, > llvm::DIType(), > EltTypeArray); > } > @@ -412,7 +424,7 @@ > TREE_CODE(type) == BLOCK_POINTER_TYPE) ? > DW_TAG_pointer_type : > DW_TAG_reference_type; > - return DebugFactory.CreateDerivedType(Tag, MainCompileUnit, "", > + return DebugFactory.CreateDerivedType(Tag, findRegion(type), "", > MainCompileUnit, 0 /*line > no*/, > NodeSizeInBits(type), > NodeAlignInBits(type), > @@ -466,7 +478,7 @@ > DebugFactory.GetOrCreateArray(&Subscripts[0], Subscripts.size()); > > return > DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_array_type, > - MainCompileUnit, "", > + findRegion(type), "", > MainCompileUnit, > 0, NodeSizeInBits(type), > NodeAlignInBits(type), 0, 0, > @@ -500,7 +512,7 @@ > DirectoryAndFile(Loc.file, Directory, Filename); > } > return > DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_enumeration_type, > - MainCompileUnit, > GetNodeName(type), > + findRegion(type), > GetNodeName(type), > MainCompileUnit, Loc.line, > NodeSizeInBits(type), > NodeAlignInBits(type), 0, 0, > @@ -526,7 +538,9 @@ > std::string Filename, Directory; > DirectoryAndFile(Loc.file, Directory, Filename); > llvm::DIType FwdDecl = > - DebugFactory.CreateCompositeType(Tag, MainCompileUnit, > GetNodeName(type), > + DebugFactory.CreateCompositeType(Tag, > + findRegion(type), > + GetNodeName(type), > MainCompileUnit, Loc.line, > 0, 0, 0, > llvm::DIType::FlagFwdDecl, > llvm::DIType(), llvm::DIArray(), > @@ -554,7 +568,7 @@ > // FIXME : name, size, align etc... > DIType DTy = > DebugFactory.CreateDerivedType(DW_TAG_inheritance, > - MainCompileUnit,"", > + findRegion(type),"", > MainCompileUnit, 0,0,0, > getInt64(BINFO_OFFSET(BInfo), > 0), > 0, BaseClass); > @@ -595,7 +609,7 @@ > Flags = llvm::DIType::FlagPrivate; > > DIType DTy = > - DebugFactory.CreateDerivedType(DW_TAG_member, > MainCompileUnit, > + DebugFactory.CreateDerivedType(DW_TAG_member, > findRegion(Member), > MemberName, MainCompileUnit, > MemLoc.line, > NodeSizeInBits(Member), > NodeAlignInBits(FieldNodeType), > @@ -622,7 +636,7 @@ > const char *LinkageName = getLinkageName(Member); > DIType SPTy = getOrCreateType(TREE_TYPE(Member)); > DISubprogram SP = > - DebugFactory.CreateSubprogram(MainCompileUnit, MemberName, > MemberName, > + DebugFactory.CreateSubprogram(findRegion(Member), MemberName, > MemberName, > LinkageName, MainCompileUnit, > MemLoc.line, SPTy, false, false, > &MemFilename, &MemDirectory); > @@ -634,7 +648,7 @@ > DebugFactory.GetOrCreateArray(&EltTys[0], EltTys.size()); > > llvm::DIType RealDecl = > - DebugFactory.CreateCompositeType(Tag, MainCompileUnit, > + DebugFactory.CreateCompositeType(Tag, findRegion(type), > GetNodeName(type), > MainCompileUnit, Loc.line, > NodeSizeInBits(type), > NodeAlignInBits(type), > @@ -657,7 +671,7 @@ > expanded_location TypeDefLoc = GetNodeLocation(Name); > std::string Filename, Directory; > DirectoryAndFile(TypeDefLoc.file, Directory, Filename); > - Ty = DebugFactory.CreateDerivedType(DW_TAG_typedef, > MainCompileUnit, > + Ty = DebugFactory.CreateDerivedType(DW_TAG_typedef, > findRegion(type), > GetNodeName(Name), > MainCompileUnit, > TypeDefLoc.line, > 0 /*size*/, > @@ -673,7 +687,7 @@ > > if (TYPE_VOLATILE(type)) { > Ty = DebugFactory.CreateDerivedType(DW_TAG_volatile_type, > - MainCompileUnit, "", > + findRegion(type), "", > MainCompileUnit, 0 /*line > no*/, > NodeSizeInBits(type), > NodeAlignInBits(type), > @@ -685,7 +699,7 @@ > > if (TYPE_READONLY(type)) > Ty = DebugFactory.CreateDerivedType(DW_TAG_const_type, > - MainCompileUnit, "", > + findRegion(type), "", > MainCompileUnit, 0 /*line > no*/, > NodeSizeInBits(type), > NodeAlignInBits(type), > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.h > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.h?rev=63133&r1=63132&r2=63133&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-debug.h (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-debug.h Tue Jan 27 15:18:46 2009 > @@ -66,6 +66,7 @@ > std::vector RegionStack; > // Stack to track > declarative scopes. > > + std::map RegionMap; > public: > DebugInfo(Module *m); > > @@ -126,7 +127,9 @@ > > /// createCompileUnit - Create a new compile unit. > DICompileUnit createCompileUnit(const std::string &FullPath); > - > + > + /// findRegion - Find tree_node N's region. > + DIDescriptor findRegion(tree_node *n); > }; > > } // end namespace llvm > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dalej at apple.com Tue Jan 27 16:09:11 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 27 Jan 2009 22:09:11 -0000 Subject: [llvm-commits] [llvm] r63138 - /llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Message-ID: <200901272209.n0RM9B8n023817@zion.cs.uiuc.edu> Author: johannes Date: Tue Jan 27 16:09:11 2009 New Revision: 63138 URL: http://llvm.org/viewvc/llvm-project?rev=63138&view=rev Log: Update to latest spelling. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=63138&r1=63137&r2=63138&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Tue Jan 27 16:09:11 2009 @@ -1341,7 +1341,7 @@ /// for new code. SDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, unsigned NumOps) : NodeType(Opc), OperandsNeedDelete(true), SubclassData(0), - NodeId(-1), debugLoc(DebugLoc::getNoDebugLoc()), + NodeId(-1), debugLoc(DebugLoc::getUnknownLoc()), OperandList(NumOps ? new SDUse[NumOps] : 0), ValueList(VTs.VTs), NumOperands(NumOps), NumValues(VTs.NumVTs), @@ -1356,7 +1356,7 @@ /// set later with InitOperands. SDNode(unsigned Opc, SDVTList VTs) : NodeType(Opc), OperandsNeedDelete(false), SubclassData(0), - NodeId(-1), debugLoc(DebugLoc::getNoDebugLoc()), OperandList(0), + NodeId(-1), debugLoc(DebugLoc::getUnknownLoc()), OperandList(0), ValueList(VTs.VTs), NumOperands(0), NumValues(VTs.NumVTs), UseList(NULL) {} From gohman at apple.com Tue Jan 27 16:12:23 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 27 Jan 2009 22:12:23 -0000 Subject: [llvm-commits] [llvm] r63139 - /llvm/trunk/include/llvm/CodeGen/ScheduleDAGSDNodes.h Message-ID: <200901272212.n0RMCNGn023940@zion.cs.uiuc.edu> Author: djg Date: Tue Jan 27 16:12:23 2009 New Revision: 63139 URL: http://llvm.org/viewvc/llvm-project?rev=63139&view=rev Log: Use .empty() instead of comparing .size() with 0. Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAGSDNodes.h Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAGSDNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAGSDNodes.h?rev=63139&r1=63138&r2=63139&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ScheduleDAGSDNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/ScheduleDAGSDNodes.h Tue Jan 27 16:12:23 2009 @@ -61,7 +61,7 @@ SUnit *NewSUnit(SDNode *N) { #ifndef NDEBUG const SUnit *Addr = 0; - if (SUnits.size() > 0) + if (!SUnits.empty()) Addr = &SUnits[0]; #endif SUnits.push_back(SUnit(N, (unsigned)SUnits.size())); From clattner at apple.com Tue Jan 27 16:23:33 2009 From: clattner at apple.com (Chris Lattner) Date: Tue, 27 Jan 2009 14:23:33 -0800 Subject: [llvm-commits] [llvm] r63136 - /llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h In-Reply-To: <200901272141.n0RLf4rE022850@zion.cs.uiuc.edu> References: <200901272141.n0RLf4rE022850@zion.cs.uiuc.edu> Message-ID: On Jan 27, 2009, at 1:41 PM, Dale Johannesen wrote: > Author: johannes > Date: Tue Jan 27 15:41:04 2009 > New Revision: 63136 > > URL: http://llvm.org/viewvc/llvm-project?rev=63136&view=rev > Log: > Add DebugLoc field and simple accessors. Thanks Dale! > + /// is that they will replace the above two over time, and > eventually > + /// the ones above can be removed. > + SDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, unsigned > NumOps, > + DebugLoc sl) Do you think it would be reasonable to pass DebugLoc immediately after Opc? Since all ctor/get methods will eventually convert to passing a location, it would be nice for them to be consistent. If it is at the end of the list then we have get(opcode, ...random stuff depending on the accessor... , loc). It would be nicer to have get(opcode, loc, ... random stuff depending on the accessor...) -Chris From dalej at apple.com Tue Jan 27 16:26:00 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 27 Jan 2009 14:26:00 -0800 Subject: [llvm-commits] [llvm] r63136 - /llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h In-Reply-To: References: <200901272141.n0RLf4rE022850@zion.cs.uiuc.edu> Message-ID: On Jan 27, 2009, at 2:23 PMPST, Chris Lattner wrote: > On Jan 27, 2009, at 1:41 PM, Dale Johannesen wrote: >> >> + /// is that they will replace the above two over time, and >> eventually >> + /// the ones above can be removed. >> + SDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, unsigned >> NumOps, >> + DebugLoc sl) > > Do you think it would be reasonable to pass DebugLoc immediately after > Opc? Since all ctor/get methods will eventually convert to passing a > location, it would be nice for them to be consistent. If it is at the > end of the list then we have get(opcode, ...random stuff depending on > the accessor... , loc). It would be nicer to have get(opcode, > loc, ... random stuff depending on the accessor...) OK, and now's the time to do it. Should be a const argument too. From asl at math.spbu.ru Tue Jan 27 16:29:25 2009 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Tue, 27 Jan 2009 22:29:25 -0000 Subject: [llvm-commits] [llvm] r63142 - in /llvm/trunk/lib/Target: DarwinTargetAsmInfo.cpp ELFTargetAsmInfo.cpp TargetAsmInfo.cpp Message-ID: <200901272229.n0RMTPEj024749@zion.cs.uiuc.edu> Author: asl Date: Tue Jan 27 16:29:24 2009 New Revision: 63142 URL: http://llvm.org/viewvc/llvm-project?rev=63142&view=rev Log: Treat [1 x i8] zeroinitializer as a C string, placing such stuff into mergeable string section. I don't see any bad impact of such decision (rather then placing it into mergeable const section, as it was before), but at least Darwin linker won't complain anymore. The problem in LLVM is that we don't have special type for string constants (like gcc does). Even more, we have two separate types: ConstatArray for non-null strings and ConstantAggregateZero for null stuff.... It's a bit weird :) Modified: llvm/trunk/lib/Target/DarwinTargetAsmInfo.cpp llvm/trunk/lib/Target/ELFTargetAsmInfo.cpp llvm/trunk/lib/Target/TargetAsmInfo.cpp Modified: llvm/trunk/lib/Target/DarwinTargetAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/DarwinTargetAsmInfo.cpp?rev=63142&r1=63141&r2=63142&view=diff ============================================================================== --- llvm/trunk/lib/Target/DarwinTargetAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/DarwinTargetAsmInfo.cpp Tue Jan 27 16:29:24 2009 @@ -115,9 +115,9 @@ DarwinTargetAsmInfo::MergeableStringSection(const GlobalVariable *GV) const { const TargetData *TD = TM.getTargetData(); Constant *C = cast(GV)->getInitializer(); - const Type *Type = cast(C)->getType()->getElementType(); + const Type *Ty = cast(C->getType())->getElementType(); - unsigned Size = TD->getTypePaddedSize(Type); + unsigned Size = TD->getTypePaddedSize(Ty); if (Size) { unsigned Align = TD->getPreferredAlignment(GV); if (Align <= 32) Modified: llvm/trunk/lib/Target/ELFTargetAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ELFTargetAsmInfo.cpp?rev=63142&r1=63141&r2=63142&view=diff ============================================================================== --- llvm/trunk/lib/Target/ELFTargetAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/ELFTargetAsmInfo.cpp Tue Jan 27 16:29:24 2009 @@ -126,8 +126,7 @@ ELFTargetAsmInfo::MergeableStringSection(const GlobalVariable *GV) const { const TargetData *TD = TM.getTargetData(); Constant *C = cast(GV)->getInitializer(); - const ConstantArray *CVA = cast(C); - const Type *Ty = CVA->getType()->getElementType(); + const Type *Ty = cast(C->getType())->getElementType(); unsigned Size = TD->getTypePaddedSize(Ty); if (Size <= 16) { Modified: llvm/trunk/lib/Target/TargetAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetAsmInfo.cpp?rev=63142&r1=63141&r2=63142&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetAsmInfo.cpp Tue Jan 27 16:29:24 2009 @@ -13,6 +13,7 @@ //===----------------------------------------------------------------------===// #include "llvm/Constants.h" +#include "llvm/DerivedTypes.h" #include "llvm/GlobalVariable.h" #include "llvm/Function.h" #include "llvm/Module.h" @@ -170,6 +171,25 @@ return (C->isNullValue() && !GV->isConstant() && !NoZerosInBSS); } +static bool isConstantString(const Constant *C) { + // First check: is we have constant array of i8 terminated with zero + const ConstantArray *CVA = dyn_cast(C); + // Check, if initializer is a null-terminated string + if (CVA && CVA->isCString()) + return true; + + // Another possibility: [1 x i8] zeroinitializer + if (isa(C)) { + if (const ArrayType *Ty = dyn_cast(C->getType())) { + return (Ty->getElementType() == Type::Int8Ty && + Ty->getNumElements() == 1); + } + } + + return false; +} + + SectionKind::Kind TargetAsmInfo::SectionKindForGlobal(const GlobalValue *GV) const { // Early exit - functions should be always in text sections. @@ -191,9 +211,8 @@ if (C->ContainsRelocations()) return SectionKind::ROData; else { - const ConstantArray *CVA = dyn_cast(C); // Check, if initializer is a null-terminated string - if (CVA && CVA->isCString()) + if (isConstantString(C)) return SectionKind::RODataMergeStr; else return SectionKind::RODataMergeConst; From tonic at nondot.org Tue Jan 27 16:33:34 2009 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 27 Jan 2009 22:33:34 -0000 Subject: [llvm-commits] [llvm] r63143 - /llvm/branches/release_25/include/llvm/Config/config.h.in Message-ID: <200901272233.n0RMXYMr024937@zion.cs.uiuc.edu> Author: tbrethou Date: Tue Jan 27 16:33:34 2009 New Revision: 63143 URL: http://llvm.org/viewvc/llvm-project?rev=63143&view=rev Log: This was reverted, forgot to commit this autogenerated file. Modified: llvm/branches/release_25/include/llvm/Config/config.h.in Modified: llvm/branches/release_25/include/llvm/Config/config.h.in URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/include/llvm/Config/config.h.in?rev=63143&r1=63142&r2=63143&view=diff ============================================================================== --- llvm/branches/release_25/include/llvm/Config/config.h.in (original) +++ llvm/branches/release_25/include/llvm/Config/config.h.in Tue Jan 27 16:33:34 2009 @@ -20,9 +20,6 @@ /* Define if threads enabled */ #undef ENABLE_THREADS -/* Path to ffi.h */ -#undef FFI_HEADER - /* Define to 1 if you have `alloca', as a function or macro. */ #undef HAVE_ALLOCA @@ -187,9 +184,6 @@ /* Define to 1 if you have the `elf' library (-lelf). */ #undef HAVE_LIBELF -/* Define to 1 if you have the libffi library (-lffi). */ -#undef HAVE_LIBFFI - /* Define to 1 if you have the `imagehlp' library (-limagehlp). */ #undef HAVE_LIBIMAGEHLP From tonic at nondot.org Tue Jan 27 16:34:30 2009 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 27 Jan 2009 22:34:30 -0000 Subject: [llvm-commits] [llvm] r63144 - in /llvm/branches/release_25: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/X86/negate-add-zero.ll Message-ID: <200901272234.n0RMYUWh024981@zion.cs.uiuc.edu> Author: tbrethou Date: Tue Jan 27 16:34:30 2009 New Revision: 63144 URL: http://llvm.org/viewvc/llvm-project?rev=63144&view=rev Log: Merge from mainline. Don't create ISD::FNEG nodes after legalize if they aren't legal. Simplify x+0 to x in unsafe-fp-math mode. This avoids a bunch of redundant work in many cases, because in unsafe-fp-math mode, ISD::FADD with a constant is considered free to negate, so the DAGCombiner often negates x+0 to -0-x thinking it's free, when in reality the end result is -x, which is more expensive than x. Also, combine x*0 to 0. This fixes PR3374. Added: llvm/branches/release_25/test/CodeGen/X86/negate-add-zero.ll - copied unchanged from r62789, llvm/trunk/test/CodeGen/X86/negate-add-zero.ll Modified: llvm/branches/release_25/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/branches/release_25/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63144&r1=63143&r2=63144&view=diff ============================================================================== --- llvm/branches/release_25/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/branches/release_25/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Jan 27 16:34:30 2009 @@ -3814,6 +3814,9 @@ // canonicalize constant to RHS if (N0CFP && !N1CFP) return DAG.getNode(ISD::FADD, VT, N1, N0); + // fold (A + 0) -> A + if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) + return N0; // fold (A + (-B)) -> A-B if (isNegatibleForFree(N1, LegalOperations) == 2) return DAG.getNode(ISD::FSUB, VT, N0, @@ -3852,7 +3855,8 @@ if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { if (isNegatibleForFree(N1, LegalOperations)) return GetNegatedExpression(N1, DAG, LegalOperations); - return DAG.getNode(ISD::FNEG, VT, N1); + if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) + return DAG.getNode(ISD::FNEG, VT, N1); } // fold (A-(-B)) -> A+B if (isNegatibleForFree(N1, LegalOperations)) @@ -3881,12 +3885,16 @@ // canonicalize constant to RHS if (N0CFP && !N1CFP) return DAG.getNode(ISD::FMUL, VT, N1, N0); + // fold (A * 0) -> 0 + if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) + return N1; // fold (fmul X, 2.0) -> (fadd X, X) if (N1CFP && N1CFP->isExactlyValue(+2.0)) return DAG.getNode(ISD::FADD, VT, N0, N0); // fold (fmul X, -1.0) -> (fneg X) if (N1CFP && N1CFP->isExactlyValue(-1.0)) - return DAG.getNode(ISD::FNEG, VT, N0); + if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) + return DAG.getNode(ISD::FNEG, VT, N0); // -X * -Y -> X*Y if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { @@ -3970,10 +3978,13 @@ const APFloat& V = N1CFP->getValueAPF(); // copysign(x, c1) -> fabs(x) iff ispos(c1) // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) - if (!V.isNegative()) - return DAG.getNode(ISD::FABS, VT, N0); - else - return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); + if (!V.isNegative()) { + if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) + return DAG.getNode(ISD::FABS, VT, N0); + } else { + if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) + return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); + } } // copysign(fabs(x), y) -> copysign(x, y) Modified: llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63144&r1=63143&r2=63144&view=diff ============================================================================== --- llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Jan 27 16:34:30 2009 @@ -27,6 +27,7 @@ #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLowering.h" +#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/CommandLine.h" @@ -2376,16 +2377,26 @@ case ISD::UREM: case ISD::MULHU: case ISD::MULHS: - assert(VT.isInteger() && "This operator does not apply to FP types!"); - // fall through case ISD::MUL: case ISD::SDIV: case ISD::SREM: + assert(VT.isInteger() && "This operator does not apply to FP types!"); + // fall through case ISD::FADD: case ISD::FSUB: case ISD::FMUL: case ISD::FDIV: case ISD::FREM: + if (UnsafeFPMath && Opcode == ISD::FADD) { + // 0+x --> x + if (ConstantFPSDNode *CFP = dyn_cast(N1)) + if (CFP->getValueAPF().isZero()) + return N2; + // x+0 --> x + if (ConstantFPSDNode *CFP = dyn_cast(N2)) + if (CFP->getValueAPF().isZero()) + return N1; + } assert(N1.getValueType() == N2.getValueType() && N1.getValueType() == VT && "Binary operator types must match!"); break; From isanbard at gmail.com Tue Jan 27 16:37:27 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 27 Jan 2009 22:37:27 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63145 - in /llvm-gcc-4.2/branches/Apple/Dib/gcc: llvm-debug.cpp llvm-debug.h Message-ID: <200901272237.n0RMbRrh025101@zion.cs.uiuc.edu> Author: void Date: Tue Jan 27 16:37:27 2009 New Revision: 63145 URL: http://llvm.org/viewvc/llvm-project?rev=63145&view=rev Log: Pull these patches into Dib: r63133: Keep track of context info. findRegion() is not comprehensive enough to find appropriate scope in all cases, but it is significantly better then what llvm-gcc ever did for debug info. r63096: Remove dead code. r62856: Set function linkage name appropriately. This allows debugger to find fn/methods. Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.cpp llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.h Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.cpp?rev=63145&r1=63144&r2=63145&view=diff ============================================================================== --- llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.cpp (original) +++ llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.cpp Tue Jan 27 16:37:27 2009 @@ -198,11 +198,6 @@ , PrevFullPath("") , PrevLineNo(0) , PrevBB(NULL) -, StopPointFn(NULL) -, FuncStartFn(NULL) -, RegionStartFn(NULL) -, RegionEndFn(NULL) -, DeclareFn(NULL) , RegionStack() { MainCompileUnit = createCompileUnit(main_input_filename); @@ -216,42 +211,54 @@ expanded_location Loc = GetNodeLocation(FnDecl, false); std::string Filename, Directory; DirectoryAndFile(Loc.file, Directory, Filename); + const char *FnName = GetNodeName(FnDecl); const char *LinkageName = getLinkageName(FnDecl); - tree func_type = TREE_TYPE(FnDecl); - llvm::SmallVector ArgTys; - // Add the result type at least. - ArgTys.push_back(getOrCreateType(TREE_TYPE(func_type))); - - // Set up remainder of arguments. - for (tree arg = TYPE_ARG_TYPES(func_type); arg; arg = TREE_CHAIN(arg)) { - tree formal_type = TREE_VALUE(arg); - if (formal_type == void_type_node) break; - ArgTys.push_back(getOrCreateType(formal_type)); - } - - llvm::DIArray FnTypeArray = - DebugFactory.GetOrCreateArray(&ArgTys[0], ArgTys.size()); - - llvm::DICompositeType FnTy = - DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_subroutine_type, - MainCompileUnit, "", - MainCompileUnit, 0, 0, 0, 0, 0, - llvm::DIType(), FnTypeArray); - - DISubprogram SP = DebugFactory.CreateSubprogram(MainCompileUnit, - Fn->getNameStr(), - Fn->getNameStr(), LinkageName, - MainCompileUnit, CurLineNo, - FnTy, - Fn->hasInternalLinkage(), - true /*definition*/, - &Filename, &Directory); + DISubprogram SP = + DebugFactory.CreateSubprogram(findRegion(FnDecl), + FnName, FnName, LinkageName, + MainCompileUnit, CurLineNo, + getOrCreateType(TREE_TYPE(FnDecl)), + Fn->hasInternalLinkage(), + true /*definition*/, + &Filename, &Directory); DebugFactory.InsertSubprogramStart(SP, CurBB); // Push function on region stack. RegionStack.push_back(SP); + RegionMap[FnDecl] = SP; +} + + /// findRegion - Find tree_node N's region. +DIDescriptor DebugInfo::findRegion(tree Node) { + if (Node == NULL_TREE) + return MainCompileUnit; + + std::map::iterator I = RegionMap.find(Node); + if (I != RegionMap.end()) + return I->second; + + if (TYPE_P (Node)) { + if (TYPE_CONTEXT (Node)) + return findRegion (TYPE_CONTEXT(Node)); + } else if (DECL_P (Node)) { + tree decl = Node; + tree context = NULL_TREE; + if (TREE_CODE (decl) != FUNCTION_DECL || ! DECL_VINDEX (decl)) + context = DECL_CONTEXT (decl); + else + context = TYPE_MAIN_VARIANT + (TREE_TYPE (TREE_VALUE (TYPE_ARG_TYPES (TREE_TYPE (decl))))); + + if (context && !TYPE_P (context)) + context = NULL_TREE; + if (context != NULL_TREE) + return findRegion(context); + } + + // Otherwise main compile unit covers everything. + return MainCompileUnit; } /// EmitRegionStart- Constructs the debug code for entering a declarative @@ -402,7 +409,7 @@ DebugFactory.GetOrCreateArray(&EltTys[0], EltTys.size()); return DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_subroutine_type, - MainCompileUnit, "", + findRegion(type), "", MainCompileUnit, 0, 0, 0, 0, 0, llvm::DIType(), EltTypeArray); } @@ -417,7 +424,7 @@ TREE_CODE(type) == BLOCK_POINTER_TYPE) ? DW_TAG_pointer_type : DW_TAG_reference_type; - return DebugFactory.CreateDerivedType(Tag, MainCompileUnit, "", + return DebugFactory.CreateDerivedType(Tag, findRegion(type), "", MainCompileUnit, 0 /*line no*/, NodeSizeInBits(type), NodeAlignInBits(type), @@ -471,7 +478,7 @@ DebugFactory.GetOrCreateArray(&Subscripts[0], Subscripts.size()); return DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_array_type, - MainCompileUnit, "", + findRegion(type), "", MainCompileUnit, 0, NodeSizeInBits(type), NodeAlignInBits(type), 0, 0, @@ -500,7 +507,7 @@ std::string Filename, Directory; DirectoryAndFile(Loc.file, Directory, Filename); return DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_enumeration_type, - MainCompileUnit, GetNodeName(type), + findRegion(type), GetNodeName(type), MainCompileUnit, Loc.line, NodeSizeInBits(type), NodeAlignInBits(type), 0, 0, @@ -526,7 +533,9 @@ std::string Filename, Directory; DirectoryAndFile(Loc.file, Directory, Filename); llvm::DIType FwdDecl = - DebugFactory.CreateCompositeType(Tag, MainCompileUnit, GetNodeName(type), + DebugFactory.CreateCompositeType(Tag, + findRegion(type), + GetNodeName(type), MainCompileUnit, Loc.line, 0, 0, 0, llvm::DIType::FlagFwdDecl, llvm::DIType(), llvm::DIArray(), @@ -554,7 +563,7 @@ // FIXME : name, size, align etc... DIType DTy = DebugFactory.CreateDerivedType(DW_TAG_inheritance, - MainCompileUnit,"", + findRegion(type),"", MainCompileUnit, 0,0,0, getInt64(BINFO_OFFSET(BInfo), 0), 0, BaseClass); @@ -595,7 +604,7 @@ Flags = llvm::DIType::FlagPrivate; DIType DTy = - DebugFactory.CreateDerivedType(DW_TAG_member, MainCompileUnit, + DebugFactory.CreateDerivedType(DW_TAG_member, findRegion(Member), MemberName, MainCompileUnit, MemLoc.line, NodeSizeInBits(Member), NodeAlignInBits(FieldNodeType), @@ -619,10 +628,11 @@ DirectoryAndFile(MemLoc.file, MemDirectory, MemFilename); const char *MemberName = GetNodeName(Member); + const char *LinkageName = getLinkageName(Member); DIType SPTy = getOrCreateType(TREE_TYPE(Member)); DISubprogram SP = - DebugFactory.CreateSubprogram(MainCompileUnit, MemberName, MemberName, - MemberName, MainCompileUnit, + DebugFactory.CreateSubprogram(findRegion(Member), MemberName, MemberName, + LinkageName, MainCompileUnit, MemLoc.line, SPTy, false, false, &MemFilename, &MemDirectory); @@ -633,7 +643,7 @@ DebugFactory.GetOrCreateArray(&EltTys[0], EltTys.size()); llvm::DIType RealDecl = - DebugFactory.CreateCompositeType(Tag, MainCompileUnit, + DebugFactory.CreateCompositeType(Tag, findRegion(type), GetNodeName(type), MainCompileUnit, Loc.line, NodeSizeInBits(type), NodeAlignInBits(type), @@ -656,7 +666,7 @@ expanded_location TypeDefLoc = GetNodeLocation(Name); std::string Filename, Directory; DirectoryAndFile(TypeDefLoc.file, Directory, Filename); - Ty = DebugFactory.CreateDerivedType(DW_TAG_typedef, MainCompileUnit, + Ty = DebugFactory.CreateDerivedType(DW_TAG_typedef, findRegion(type), GetNodeName(Name), MainCompileUnit, TypeDefLoc.line, 0 /*size*/, @@ -672,7 +682,7 @@ if (TYPE_VOLATILE(type)) { Ty = DebugFactory.CreateDerivedType(DW_TAG_volatile_type, - MainCompileUnit, "", + findRegion(type), "", MainCompileUnit, 0 /*line no*/, NodeSizeInBits(type), NodeAlignInBits(type), @@ -684,7 +694,7 @@ if (TYPE_READONLY(type)) Ty = DebugFactory.CreateDerivedType(DW_TAG_const_type, - MainCompileUnit, "", + findRegion(type), "", MainCompileUnit, 0 /*line no*/, NodeSizeInBits(type), NodeAlignInBits(type), Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.h?rev=63145&r1=63144&r2=63145&view=diff ============================================================================== --- llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.h (original) +++ llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.h Tue Jan 27 16:37:27 2009 @@ -63,14 +63,10 @@ std::map TypeCache; // Cache of previously constructed // Types. - Function *StopPointFn; // llvm.dbg.stoppoint - Function *FuncStartFn; // llvm.dbg.func.start - Function *RegionStartFn; // llvm.dbg.region.start - Function *RegionEndFn; // llvm.dbg.region.end - Function *DeclareFn; // llvm.dbg.declare std::vector RegionStack; // Stack to track declarative scopes. + std::map RegionMap; public: DebugInfo(Module *m); @@ -131,7 +127,9 @@ /// createCompileUnit - Create a new compile unit. DICompileUnit createCompileUnit(const std::string &FullPath); - + + /// findRegion - Find tree_node N's region. + DIDescriptor findRegion(tree_node *n); }; } // end namespace llvm From isanbard at gmail.com Tue Jan 27 16:42:15 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 27 Jan 2009 22:42:15 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63146 - /llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.cpp Message-ID: <200901272242.n0RMgFoC025339@zion.cs.uiuc.edu> Author: void Date: Tue Jan 27 16:42:15 2009 New Revision: 63146 URL: http://llvm.org/viewvc/llvm-project?rev=63146&view=rev Log: Pull in: r62865: Incomplete enum does not have any location info available. r62874: Initialize location info. Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.cpp Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.cpp?rev=63146&r1=63145&r2=63146&view=diff ============================================================================== --- llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.cpp (original) +++ llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.cpp Tue Jan 27 16:42:15 2009 @@ -503,9 +503,14 @@ llvm::DIArray EltArray = DebugFactory.GetOrCreateArray(&Elements[0], Elements.size()); - expanded_location Loc = GetNodeLocation(TREE_CHAIN(type), false); - std::string Filename, Directory; - DirectoryAndFile(Loc.file, Directory, Filename); + expanded_location Loc = { NULL, 0 }; + std::string Filename = ""; + std::string Directory= ""; + if (TYPE_SIZE(type)) { + // Incomplete enums do not have any location info. + Loc = GetNodeLocation(TREE_CHAIN(type), false); + DirectoryAndFile(Loc.file, Directory, Filename); + } return DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_enumeration_type, findRegion(type), GetNodeName(type), MainCompileUnit, Loc.line, From isanbard at gmail.com Tue Jan 27 16:46:51 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 27 Jan 2009 22:46:51 -0000 Subject: [llvm-commits] [llvm] r63147 - /llvm/branches/Apple/Dib/include/llvm/Config/config.h.in Message-ID: <200901272246.n0RMkpw2025485@zion.cs.uiuc.edu> Author: void Date: Tue Jan 27 16:46:51 2009 New Revision: 63147 URL: http://llvm.org/viewvc/llvm-project?rev=63147&view=rev Log: Merge with release_25 branch. Committing autogenerated file. Modified: llvm/branches/Apple/Dib/include/llvm/Config/config.h.in Modified: llvm/branches/Apple/Dib/include/llvm/Config/config.h.in URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/Config/config.h.in?rev=63147&r1=63146&r2=63147&view=diff ============================================================================== --- llvm/branches/Apple/Dib/include/llvm/Config/config.h.in (original) +++ llvm/branches/Apple/Dib/include/llvm/Config/config.h.in Tue Jan 27 16:46:51 2009 @@ -20,9 +20,6 @@ /* Define if threads enabled */ #undef ENABLE_THREADS -/* Path to ffi.h */ -#undef FFI_HEADER - /* Define to 1 if you have `alloca', as a function or macro. */ #undef HAVE_ALLOCA @@ -187,9 +184,6 @@ /* Define to 1 if you have the `elf' library (-lelf). */ #undef HAVE_LIBELF -/* Define to 1 if you have the libffi library (-lffi). */ -#undef HAVE_LIBFFI - /* Define to 1 if you have the `imagehlp' library (-limagehlp). */ #undef HAVE_LIBIMAGEHLP From isanbard at gmail.com Tue Jan 27 16:47:45 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 27 Jan 2009 22:47:45 -0000 Subject: [llvm-commits] [llvm] r63148 - in /llvm/branches/Apple/Dib: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/X86/negate-add-zero.ll Message-ID: <200901272247.n0RMlj27025526@zion.cs.uiuc.edu> Author: void Date: Tue Jan 27 16:47:45 2009 New Revision: 63148 URL: http://llvm.org/viewvc/llvm-project?rev=63148&view=rev Log: Merge from release 2.5 branch: New Revision: 63144 URL: http://llvm.org/viewvc/llvm-project?rev=63144&view=rev Log: Merge from mainline. Don't create ISD::FNEG nodes after legalize if they aren't legal. Simplify x+0 to x in unsafe-fp-math mode. This avoids a bunch of redundant work in many cases, because in unsafe-fp-math mode, ISD::FADD with a constant is considered free to negate, so the DAGCombiner often negates x+0 to -0-x thinking it's free, when in reality the end result is -x, which is more expensive than x. Also, combine x*0 to 0. This fixes PR3374. Added: llvm/branches/Apple/Dib/test/CodeGen/X86/negate-add-zero.ll Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63148&r1=63147&r2=63148&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Jan 27 16:47:45 2009 @@ -3814,6 +3814,9 @@ // canonicalize constant to RHS if (N0CFP && !N1CFP) return DAG.getNode(ISD::FADD, VT, N1, N0); + // fold (A + 0) -> A + if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) + return N0; // fold (A + (-B)) -> A-B if (isNegatibleForFree(N1, LegalOperations) == 2) return DAG.getNode(ISD::FSUB, VT, N0, @@ -3852,7 +3855,8 @@ if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { if (isNegatibleForFree(N1, LegalOperations)) return GetNegatedExpression(N1, DAG, LegalOperations); - return DAG.getNode(ISD::FNEG, VT, N1); + if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) + return DAG.getNode(ISD::FNEG, VT, N1); } // fold (A-(-B)) -> A+B if (isNegatibleForFree(N1, LegalOperations)) @@ -3881,12 +3885,16 @@ // canonicalize constant to RHS if (N0CFP && !N1CFP) return DAG.getNode(ISD::FMUL, VT, N1, N0); + // fold (A * 0) -> 0 + if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) + return N1; // fold (fmul X, 2.0) -> (fadd X, X) if (N1CFP && N1CFP->isExactlyValue(+2.0)) return DAG.getNode(ISD::FADD, VT, N0, N0); // fold (fmul X, -1.0) -> (fneg X) if (N1CFP && N1CFP->isExactlyValue(-1.0)) - return DAG.getNode(ISD::FNEG, VT, N0); + if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) + return DAG.getNode(ISD::FNEG, VT, N0); // -X * -Y -> X*Y if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { @@ -3970,10 +3978,13 @@ const APFloat& V = N1CFP->getValueAPF(); // copysign(x, c1) -> fabs(x) iff ispos(c1) // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) - if (!V.isNegative()) - return DAG.getNode(ISD::FABS, VT, N0); - else - return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); + if (!V.isNegative()) { + if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) + return DAG.getNode(ISD::FABS, VT, N0); + } else { + if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) + return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); + } } // copysign(fabs(x), y) -> copysign(x, y) Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63148&r1=63147&r2=63148&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Jan 27 16:47:45 2009 @@ -27,6 +27,7 @@ #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLowering.h" +#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/CommandLine.h" @@ -2376,16 +2377,26 @@ case ISD::UREM: case ISD::MULHU: case ISD::MULHS: - assert(VT.isInteger() && "This operator does not apply to FP types!"); - // fall through case ISD::MUL: case ISD::SDIV: case ISD::SREM: + assert(VT.isInteger() && "This operator does not apply to FP types!"); + // fall through case ISD::FADD: case ISD::FSUB: case ISD::FMUL: case ISD::FDIV: case ISD::FREM: + if (UnsafeFPMath && Opcode == ISD::FADD) { + // 0+x --> x + if (ConstantFPSDNode *CFP = dyn_cast(N1)) + if (CFP->getValueAPF().isZero()) + return N2; + // x+0 --> x + if (ConstantFPSDNode *CFP = dyn_cast(N2)) + if (CFP->getValueAPF().isZero()) + return N1; + } assert(N1.getValueType() == N2.getValueType() && N1.getValueType() == VT && "Binary operator types must match!"); break; Added: llvm/branches/Apple/Dib/test/CodeGen/X86/negate-add-zero.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/negate-add-zero.ll?rev=63148&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/X86/negate-add-zero.ll (added) +++ llvm/branches/Apple/Dib/test/CodeGen/X86/negate-add-zero.ll Tue Jan 27 16:47:45 2009 @@ -0,0 +1,1145 @@ +; RUN: llvm-as < %s | llc -enable-unsafe-fp-math -march=x86 | not grep xor +; PR3374 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i386-apple-darwin7" + %struct.AtomList = type { %"struct.CDSListRep"* } + %struct.AtomTree = type { %struct.IVM*, %"struct.CDSList >" } + %"struct.CDS::DefaultAlloc" = type <{ i8 }> + %"struct.CDS::SingularError" = type { %"struct.CDS::exception" } + %"struct.CDS::auto_ptr" = type { %struct.IVMAtom* } + %"struct.CDS::exception" = type { [300 x i8] } + %"struct.CDSList >" = type { %"struct.CDSListRep >"* } + %"struct.CDSList >" = type { %"struct.CDSListRep >"* } + %"struct.CDSList" = type { %"struct.CDSListRep"* } + %"struct.CDSList" = type { %"struct.CDSListRep"* } + %"struct.CDSList" = type { %"struct.CDSListRep"* } + %"struct.CDSList >" = type { %"struct.CDSListRep >"* } + %"struct.CDSList" = type { %"struct.CDSListRep"* } + %"struct.CDSListRep >" = type opaque + %"struct.CDSListRep >" = type opaque + %"struct.CDSListRep" = type { i32, i32, %struct.HingeNode**, i32 } + %"struct.CDSListRep" = type { i32, i32, %struct.IVMAtom**, i32 } + %"struct.CDSListRep" = type opaque + %"struct.CDSListRep" = type opaque + %"struct.CDSListRep >" = type opaque + %"struct.CDSListRep" = type { i32, i32, i32*, i32 } + %"struct.CDSMatrixBase" = type { %"struct.CDSMatrixRep"* } + %"struct.CDSMatrixRep" = type opaque + %"struct.CDSStringRep" = type { i8*, i32, i32, i32, i32 } + %"struct.CDSVector" = type { %"struct.CDSVectorBase" } + %"struct.CDSVector" = type { %"struct.CDSVectorBase" } + %"struct.CDSVectorBase" = type { %"struct.CDSVectorRep"* } + %"struct.CDSVectorBase" = type { %"struct.CDSVectorRep"* } + %"struct.CDSVectorRep" = type { i32, %"struct.CDS::DefaultAlloc", %struct.Vec3*, i32 } + %"struct.CDSVectorRep" = type { i32, %"struct.CDS::DefaultAlloc", double*, i32 } + %"struct.FixedMatrix" = type { %"struct.FixedMatrixBase" } + %"struct.FixedMatrix" = type { %"struct.FixedMatrixBase" } + %"struct.FixedMatrix" = type { %"struct.FixedMatrixBase" } + %"struct.FixedMatrix" = type { %"struct.FixedMatrixBase" } + %"struct.FixedMatrix" = type { %"struct.FixedMatrixBase" } + %"struct.FixedMatrix" = type { %"struct.FixedMatrixBase" } + %"struct.FixedMatrix" = type { %"struct.FixedMatrixBase" } + %"struct.FixedMatrix" = type { %"struct.FixedMatrixBase" } + %"struct.FixedMatrix" = type { %"struct.FixedMatrixBase" } + %"struct.FixedMatrixBase" = type { [1 x double] } + %"struct.FixedMatrixBase" = type { [3 x double] } + %"struct.FixedMatrixBase" = type { [6 x double] } + %"struct.FixedMatrixBase" = type { [4 x double] } + %"struct.FixedMatrixBase" = type { [12 x double] } + %"struct.FixedMatrixBase" = type { [9 x double] } + %"struct.FixedMatrixBase" = type { [18 x double] } + %"struct.FixedMatrixBase" = type { [25 x double] } + %"struct.FixedMatrixBase" = type { [30 x double] } + %"struct.FixedMatrixBase" = type { [36 x double] } + %"struct.FixedVector" = type { %"struct.FixedVectorBase" } + %"struct.FixedVector" = type { %"struct.FixedVectorBase" } + %"struct.FixedVectorBase" = type { [2 x double] } + %"struct.FixedVectorBase" = type { [5 x double] } + %struct.HNodeOrigin = type { %struct.HingeNode } + %struct.HNodeRotate2 = type { %"struct.HingeNodeSpec<2>", %struct.Vec3, %struct.Vec3, %struct.Vec3, %struct.Vec3, %struct.Vec3, %struct.Mat3, %struct.Mat3, %struct.Vec3, %"struct.CDS::auto_ptr", %"struct.CDSVector" } + %struct.HNodeRotate3 = type { %"struct.HingeNodeSpec<3>", %struct.Vec4, %struct.Vec4, %struct.Vec4, %struct.Vec3, %"struct.CDS::auto_ptr", %"struct.CDSVector", double, double, double, double, double, double, i8 } + %struct.HNodeTorsion = type { %"struct.HingeNodeSpec<1>", %struct.Vec3, %"struct.CDSVector", %struct.Vec3, %struct.Mat3 } + %struct.HNodeTranslate = type { %"struct.HingeNodeSpec<3>", %struct.IVMAtom*, %struct.Vec3, %"struct.CDSVector" } + %struct.HNodeTranslateRotate2 = type { %"struct.HingeNodeSpec<5>", %struct.Vec3, %struct.Vec3, %struct.Vec3, %struct.Vec3, %struct.Vec3, %struct.Mat3, %struct.Mat3, %struct.Vec3, %"struct.CDS::auto_ptr", %"struct.CDSVector" } + %struct.HNodeTranslateRotate3 = type { %"struct.HingeNodeSpec<6>", %struct.Vec4, %struct.Vec4, %struct.Vec4, %struct.Vec3, %"struct.CDS::auto_ptr", %"struct.CDSVector", double, double, double, double, double, double, i8 } + %struct.HingeNode = type { i32 (...)**, %struct.HingeNode*, %"struct.CDSList", i32, %struct.AtomList, %"struct.FixedMatrix", %"struct.FixedMatrix", %struct.PhiMatrix, %struct.Mat6, %struct.Mat6, %"struct.FixedMatrix", %struct.Mat6, %"struct.FixedMatrix", %struct.Mat3, %struct.Mat6, %struct.IVM*, %struct.IVMAtom* } + %"struct.HingeNodeSpec<1>" = type { %struct.HingeNode, i32, double, %struct.InertiaTensor, %struct.Mat6, %struct.Vec3, %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix" } + %"struct.HingeNodeSpec<2>" = type { %struct.HingeNode, i32, double, %struct.InertiaTensor, %struct.Mat6, %struct.Vec3, %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedVector", %"struct.FixedVector", %"struct.FixedVector", %"struct.FixedMatrix", %"struct.FixedVector", %"struct.FixedVector", %"struct.FixedVector", %"struct.FixedMatrix", %"struct.FixedMatrix" } + %"struct.HingeNodeSpec<3>" = type { %struct.HingeNode, i32, double, %struct.InertiaTensor, %struct.Mat6, %struct.Vec3, %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix" } + %"struct.HingeNodeSpec<5>" = type { %struct.HingeNode, i32, double, %struct.InertiaTensor, %struct.Mat6, %struct.Vec3, %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedVector", %"struct.FixedVector", %"struct.FixedVector", %"struct.FixedMatrix", %"struct.FixedVector", %"struct.FixedVector", %"struct.FixedVector", %"struct.FixedMatrix", %"struct.FixedMatrix" } + %"struct.HingeNodeSpec<6>" = type { %struct.HingeNode, i32, double, %struct.InertiaTensor, %struct.Mat6, %struct.Vec3, %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %struct.Mat6, %"struct.FixedMatrix", %"struct.FixedMatrix", %"struct.FixedMatrix", %struct.Mat6, %struct.Mat6 } + %struct.IVM = type { i32 (...)**, %struct.AtomTree*, %struct.Integrator*, %struct.LengthConstraints*, i32, i32, i32, i8, i8, i8, i8, double, double, double, double, double, double, double, double, double, i32, double, double, double, double, double, double, %"struct.CDSList", %"struct.CDSList >", %struct.AtomList, %"struct.CDSList >", %"struct.CDSList", %struct.String, %"struct.CDSList", i32 (%"struct.CDSVector"*)*, double (%"struct.CDSVector"*, %"struct.CDSVector"*)*, i32 (%"struct.CDSVector"*)*, double (%"struct.CDSVector"*, %"struct.CDSVector"*)* } + %struct.IVMAtom = type { i32, %struct.HingeNode*, %struct.AtomList, %struct.Vec3, %struct.Vec3, %struct.Vec3, double, double } + %struct.InertiaTensor = type { %struct.Mat3 } + %struct.Integrator = type { i32 (...)**, %"struct.CDSVector", %"struct.CDSVector", %struct.IVM* } + %"struct.InternalDynamics::HingeSpec" = type { %struct.String, i32, i32, %"struct.CDSList" } + %struct.LengthConstraints = type { double, i32, i32, %struct.IVM*, %struct.LengthConstraintsPrivates* } + %struct.LengthConstraintsPrivates = type opaque + %struct.Mat3 = type { %"struct.FixedMatrix" } + %struct.Mat6 = type { %"struct.FixedMatrixBase" } + %"struct.MatrixTools::InverseResults >" = type { %"struct.CDSVector", i32 } + %struct.PhiMatrix = type { %struct.Vec3 } + %struct.PhiMatrixTranspose = type { %struct.PhiMatrix* } + %struct.RMat = type { %"struct.CDSMatrixBase" } + %struct.String = type { %"struct.CDSStringRep"* } + %"struct.SubMatrix >" = type { %struct.Mat6*, i32, i32, i32, i32 } + %"struct.SubVector >" = type { %"struct.CDSVector"*, i32, i32 } + %"struct.SubVector >" = type { %"struct.FixedMatrix"*, i32, i32 } + %struct.Vec3 = type { %"struct.FixedMatrix" } + %struct.Vec4 = type { %"struct.FixedMatrix" } + %struct.__class_type_info_pseudo = type { %struct.__type_info_pseudo } + %struct.__si_class_type_info_pseudo = type { %struct.__type_info_pseudo, %"struct.std::type_info"* } + %struct.__type_info_pseudo = type { i8*, i8* } + %"struct.std::basic_ios >" = type { %"struct.std::ios_base", %"struct.std::basic_ostream >"*, i8, i8, %"struct.std::basic_streambuf >"*, %"struct.std::ctype"*, %"struct.std::num_get > >"*, %"struct.std::num_get > >"* } + %"struct.std::basic_ostream >" = type { i32 (...)**, %"struct.std::basic_ios >" } + %"struct.std::basic_streambuf >" = type { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, %"struct.std::locale" } + %"struct.std::ctype" = type { %"struct.std::locale::facet", i32*, i8, i32*, i32*, i32*, i8, [256 x i8], [256 x i8], i8 } + %"struct.std::ios_base" = type { i32 (...)**, i32, i32, i32, i32, i32, %"struct.std::ios_base::_Callback_list"*, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, %"struct.std::ios_base::_Words"*, %"struct.std::locale" } + %"struct.std::ios_base::_Callback_list" = type { %"struct.std::ios_base::_Callback_list"*, void (i32, %"struct.std::ios_base"*, i32)*, i32, i32 } + %"struct.std::ios_base::_Words" = type { i8*, i32 } + %"struct.std::locale" = type { %"struct.std::locale::_Impl"* } + %"struct.std::locale::_Impl" = type { i32, %"struct.std::locale::facet"**, i32, %"struct.std::locale::facet"**, i8** } + %"struct.std::locale::facet" = type { i32 (...)**, i32 } + %"struct.std::num_get > >" = type { %"struct.std::locale::facet" } + %"struct.std::type_info" = type { i32 (...)**, i8* } + at _ZN9HingeNode7DEG2RADE = external constant double, align 8 ; [#uses=0] +@"\01LC" = external constant [8 x i8] ; <[8 x i8]*> [#uses=0] +@"\01LC1" = external constant [7 x i8] ; <[7 x i8]*> [#uses=0] +@"\01LC2" = external constant [10 x i8] ; <[10 x i8]*> [#uses=0] +@"\01LC3" = external constant [5 x i8] ; <[5 x i8]*> [#uses=0] +@"\01LC4" = external constant [8 x i8] ; <[8 x i8]*> [#uses=0] +@"\01LC5" = external constant [8 x i8] ; <[8 x i8]*> [#uses=0] +@"\01LC6" = external constant [7 x i8] ; <[7 x i8]*> [#uses=0] +@"\01LC7" = external constant [8 x i8] ; <[8 x i8]*> [#uses=0] +@"\01LC8" = external constant [3 x i8] ; <[3 x i8]*> [#uses=0] +@"\01LC9" = external constant [3 x i8] ; <[3 x i8]*> [#uses=0] +@"\01LC10" = external constant [3 x i8] ; <[3 x i8]*> [#uses=0] + at _ZStL8__ioinit = external global %"struct.CDS::DefaultAlloc" ; <%"struct.CDS::DefaultAlloc"*> [#uses=0] + at __dso_handle = external global i8* ; [#uses=0] + at _ZTIN9HingeNode17VirtualBaseMethodE = external constant %struct.__class_type_info_pseudo ; <%struct.__class_type_info_pseudo*> [#uses=0] + at _ZTVN10__cxxabiv117__class_type_infoE = external constant [0 x i32 (...)*] ; <[0 x i32 (...)*]*> [#uses=0] + at _ZTSN9HingeNode17VirtualBaseMethodE = external constant [32 x i8], align 4 ; <[32 x i8]*> [#uses=0] + at _ZTV9HingeNode = external constant [31 x i32 (...)*], align 32 ; <[31 x i32 (...)*]*> [#uses=0] + at _ZTI9HingeNode = external constant %struct.__class_type_info_pseudo ; <%struct.__class_type_info_pseudo*> [#uses=0] + at _ZTS9HingeNode = external constant [11 x i8] ; <[11 x i8]*> [#uses=0] + at _ZTV11HNodeOrigin = external constant [31 x i32 (...)*], align 32 ; <[31 x i32 (...)*]*> [#uses=0] + at _ZTI11HNodeOrigin = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0] + at _ZTVN10__cxxabiv120__si_class_type_infoE = external constant [0 x i32 (...)*] ; <[0 x i32 (...)*]*> [#uses=0] + at _ZTS11HNodeOrigin = external constant [14 x i8] ; <[14 x i8]*> [#uses=0] + at _ZTV13HingeNodeSpecILi1EE = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0] + at _ZTI13HingeNodeSpecILi1EE = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0] + at _ZTS13HingeNodeSpecILi1EE = external constant [22 x i8] ; <[22 x i8]*> [#uses=0] + at _ZTV13HingeNodeSpecILi3EE = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0] + at _ZTI13HingeNodeSpecILi3EE = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0] + at _ZTS13HingeNodeSpecILi3EE = external constant [22 x i8] ; <[22 x i8]*> [#uses=0] + at _ZTV13HingeNodeSpecILi2EE = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0] + at _ZTI13HingeNodeSpecILi2EE = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0] + at _ZTS13HingeNodeSpecILi2EE = external constant [22 x i8] ; <[22 x i8]*> [#uses=0] + at _ZTV13HingeNodeSpecILi6EE = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0] + at _ZTI13HingeNodeSpecILi6EE = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0] + at _ZTS13HingeNodeSpecILi6EE = external constant [22 x i8] ; <[22 x i8]*> [#uses=0] + at _ZTV13HingeNodeSpecILi5EE = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0] + at _ZTI13HingeNodeSpecILi5EE = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0] + at _ZTS13HingeNodeSpecILi5EE = external constant [22 x i8] ; <[22 x i8]*> [#uses=0] + at _ZSt4cout = external global %"struct.std::basic_ostream >" ; <%"struct.std::basic_ostream >"*> [#uses=0] +@"\01LC11" = external constant [10 x i8] ; <[10 x i8]*> [#uses=0] +@"\01LC12" = external constant [8 x i8] ; <[8 x i8]*> [#uses=0] +@"\01LC13" = external constant [10 x i8] ; <[10 x i8]*> [#uses=0] + at _ZSt4cerr = external global %"struct.std::basic_ostream >" ; <%"struct.std::basic_ostream >"*> [#uses=0] +@"\01LC14" = external constant [29 x i8] ; <[29 x i8]*> [#uses=0] +@"\01LC15" = external constant [11 x i8] ; <[11 x i8]*> [#uses=0] +@"\01LC16" = external constant [13 x i8] ; <[13 x i8]*> [#uses=0] +@"\01LC17" = external constant [21 x i8] ; <[21 x i8]*> [#uses=0] +@"\01LC18" = external constant [8 x i8] ; <[8 x i8]*> [#uses=0] +@"\01LC19" = external constant [4 x i8] ; <[4 x i8]*> [#uses=0] +@"\01LC20" = external constant [42 x i8] ; <[42 x i8]*> [#uses=0] + at _ZTIN16InternalDynamics9ExceptionE = external constant %struct.__class_type_info_pseudo ; <%struct.__class_type_info_pseudo*> [#uses=0] + at _ZTSN16InternalDynamics9ExceptionE = external constant [31 x i8], align 4 ; <[31 x i8]*> [#uses=0] + at _ZTIN3CDS13SingularErrorE = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0] + at _ZTSN3CDS13SingularErrorE = external constant [22 x i8] ; <[22 x i8]*> [#uses=0] + at _ZTIN3CDS9exceptionE = external constant %struct.__class_type_info_pseudo ; <%struct.__class_type_info_pseudo*> [#uses=0] + at _ZTSN3CDS9exceptionE = external constant [17 x i8] ; <[17 x i8]*> [#uses=0] + at _ZTV12HNodeTorsion = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0] + at _ZTI12HNodeTorsion = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0] + at _ZTS12HNodeTorsion = external constant [15 x i8] ; <[15 x i8]*> [#uses=0] + at _ZTV12HNodeRotate3 = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0] + at _ZTI12HNodeRotate3 = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0] + at _ZTS12HNodeRotate3 = external constant [15 x i8] ; <[15 x i8]*> [#uses=0] + at _ZTV12HNodeRotate2 = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0] + at _ZTI12HNodeRotate2 = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0] + at _ZTS12HNodeRotate2 = external constant [15 x i8] ; <[15 x i8]*> [#uses=0] + at _ZTV21HNodeTranslateRotate3 = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0] + at _ZTI21HNodeTranslateRotate3 = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0] + at _ZTS21HNodeTranslateRotate3 = external constant [24 x i8] ; <[24 x i8]*> [#uses=0] + at _ZTV21HNodeTranslateRotate2 = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0] + at _ZTI21HNodeTranslateRotate2 = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0] + at _ZTS21HNodeTranslateRotate2 = external constant [24 x i8] ; <[24 x i8]*> [#uses=0] + at _ZTV14HNodeTranslate = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0] + at _ZTI14HNodeTranslate = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0] + at _ZTS14HNodeTranslate = external constant [17 x i8] ; <[17 x i8]*> [#uses=0] +@"\01LC21" = external constant [31 x i8] ; <[31 x i8]*> [#uses=0] +@"\01LC22" = external constant [6 x i8] ; <[6 x i8]*> [#uses=0] +@"\01LC23" = external constant [12 x i8] ; <[12 x i8]*> [#uses=0] +@"\01LC24" = external constant [5 x i8] ; <[5 x i8]*> [#uses=0] +@"\01LC25" = external constant [7 x i8] ; <[7 x i8]*> [#uses=0] +@"\01LC26" = external constant [7 x i8] ; <[7 x i8]*> [#uses=0] +@"\01LC27" = external constant [43 x i8] ; <[43 x i8]*> [#uses=0] +@"\01LC28" = external constant [15 x i8] ; <[15 x i8]*> [#uses=0] +@"\01LC29" = external constant [20 x i8] ; <[20 x i8]*> [#uses=0] +@"\01LC30" = external constant [41 x i8] ; <[41 x i8]*> [#uses=0] + at llvm.global_ctors = external global [1 x { i32, void ()* }] ; <[1 x { i32, void ()* }]*> [#uses=0] + +declare void @_GLOBAL__I__ZN9HingeNode7DEG2RADE() section "__TEXT,__StaticInit,regular,pure_instructions" + +declare void @_ZN9HingeNode16velFromCartesianEv(%struct.HingeNode*) nounwind + +declare i32 @_ZNK9HingeNode6offsetEv(%struct.HingeNode*) nounwind + +declare i32 @_ZNK9HingeNode6getDOFEv(%struct.HingeNode*) nounwind + +declare i32 @_ZNK9HingeNode6getDimEv(%struct.HingeNode*) nounwind + +declare double @_ZN9HingeNode8kineticEEv(%struct.HingeNode*) nounwind + +declare double @_ZN9HingeNode8approxKEEv(%struct.HingeNode*) nounwind + +declare i8* @_ZN9HingeNode4typeEv(%struct.HingeNode*) nounwind + +declare i8* @_ZN11HNodeOrigin4typeEv(%struct.HNodeOrigin*) nounwind + +declare void @_ZN11HNodeOrigin5calcPEv(%struct.HNodeOrigin*) nounwind + +declare void @_ZN11HNodeOrigin5calcZEv(%struct.HNodeOrigin*) nounwind + +declare void @_ZN11HNodeOrigin9calcPandZEv(%struct.HNodeOrigin*) nounwind + +declare void @_ZN11HNodeOrigin9calcAccelEv(%struct.HNodeOrigin*) nounwind + +declare void @_ZN11HNodeOrigin17calcInternalForceEv(%struct.HNodeOrigin*) nounwind + +declare void @_ZN11HNodeOrigin18prepareVelInternalEv(%struct.HNodeOrigin*) nounwind + +declare void @_ZN11HNodeOrigin13propagateSVelERK11FixedVectorIdLi6ELi0EE(%struct.HNodeOrigin*, %"struct.FixedMatrix"*) nounwind + +declare void @_ZN11HNodeOrigin9setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%struct.HNodeOrigin*, %"struct.CDSVector"*, %"struct.CDSVector"*) nounwind + +declare void @_ZN11HNodeOrigin6setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeOrigin*, %"struct.CDSVector"*) nounwind + +declare void @_ZN11HNodeOrigin14setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%struct.HNodeOrigin*, %"struct.FixedMatrix"*) nounwind + +declare void @_ZN11HNodeOrigin18enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES4_(%struct.HNodeOrigin*, %"struct.CDSVector"*, %"struct.CDSVector"*) nounwind + +declare void @_ZN11HNodeOrigin5printEi(%struct.HNodeOrigin*, i32) nounwind + +declare void @_ZN11HNodeOrigin6getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeOrigin*, %"struct.CDSVector"*) nounwind + +declare void @_ZN11HNodeOrigin6getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeOrigin*, %"struct.CDSVector"*) nounwind + +declare void @_ZN11HNodeOrigin8getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeOrigin*, %"struct.CDSVector"*) nounwind + +declare void @_ZN11HNodeOrigin16getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeOrigin*, %"struct.CDSVector"*) nounwind + +declare void @_ZN11HNodeOrigin5calcYEv(%struct.HNodeOrigin*) nounwind + +declare i8* @_ZN14HNodeTranslate4typeEv(%struct.HNodeTranslate*) nounwind + +declare i8* @_ZN21HNodeTranslateRotate34typeEv(%struct.HNodeTranslateRotate3*) nounwind + +declare i32 @_ZNK21HNodeTranslateRotate36getDimEv(%struct.HNodeTranslateRotate3*) nounwind + +declare i8* @_ZN12HNodeRotate34typeEv(%struct.HNodeRotate3*) nounwind + +declare i32 @_ZNK12HNodeRotate36getDimEv(%struct.HNodeRotate3*) nounwind + +declare i8* @_ZN12HNodeRotate24typeEv(%struct.HNodeRotate2*) nounwind + +declare i32 @_ZNK12HNodeRotate26getDimEv(%struct.HNodeRotate2*) nounwind + +declare i8* @_ZN21HNodeTranslateRotate24typeEv(%struct.HNodeTranslateRotate2*) nounwind + +declare i32 @_ZNK21HNodeTranslateRotate26getDimEv(%struct.HNodeTranslateRotate2*) nounwind + +declare i8* @_ZN12HNodeTorsion4typeEv(%struct.HNodeTorsion*) nounwind + +declare fastcc double @_ZL12sumMassToTipPK9HingeNode(%struct.HingeNode*) + +declare void @_ZN13InertiaTensor4calcERK4Vec3RK7CDSListIP7IVMAtomE(%struct.InertiaTensor*, %struct.Vec3*, %struct.AtomList*) nounwind + +declare fastcc double @_ZL15sumInertiaToTipPK9HingeNodeRK4Vec3S4_(%struct.HingeNode*, %struct.Vec3*, %struct.Vec3*) + +declare %"struct.std::basic_ostream >"* @_ZlsI11FixedVectorIdLi6ELi0EEERSoS2_RK9SubVectorIT_E(%"struct.std::basic_ostream >"*, %"struct.SubVector >"*) + +declare %"struct.std::basic_ostream >"* @_ZStlsIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_St5_Setw(%"struct.std::basic_ostream >"*, i32) + +declare %"struct.std::basic_ostream >"* @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(%"struct.std::basic_ostream >"*, i8*) + +declare %"struct.std::basic_ostream >"* @_ZNSolsEd(%"struct.std::basic_ostream >"*, double) + +declare void @_Z14orthoTransformIdLi3ELi3EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) + +declare void @_ZN12HNodeRotate27calcRotEv(%struct.HNodeRotate2*) + +declare void @_ZN21HNodeTranslateRotate27calcRotEv(%struct.HNodeTranslateRotate2*) + +declare void @_ZmlIdLi6ELi6EE11FixedVectorIT_XT0_ELi0EERK11FixedMatrixIS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_ELi0EE(%"struct.FixedMatrix"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix"*) + +declare void @_ZmlIdLi6ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%struct.Mat6* noalias sret, %struct.Mat6*, %struct.Mat6*) + +declare void @_ZmlIdLi6ELi6ELi3EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix"*) + +declare void @_ZmlIdLi6ELi6ELi2EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix"*) + +declare void @_ZmlIdLi5ELi6EE11FixedVectorIT_XT0_ELi0EERK11FixedMatrixIS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_ELi0EE(%"struct.FixedVector"* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) + +declare void @_ZmlIdLi6ELi6ELi5EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix"*) + +declare void @_ZN12HNodeRotate39setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%struct.HNodeRotate3*, %"struct.CDSVector"*, %"struct.CDSVector"*) + +declare void @_ZN12HNodeRotate29setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%struct.HNodeRotate2*, %"struct.CDSVector"*, %"struct.CDSVector"*) + +declare void @_ZN21HNodeTranslateRotate39setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%struct.HNodeTranslateRotate3*, %"struct.CDSVector"*, %"struct.CDSVector"*) + +declare void @_ZN21HNodeTranslateRotate29setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%struct.HNodeTranslateRotate2*, %"struct.CDSVector"*, %"struct.CDSVector"*) + +declare i32 @_ZNK13HingeNodeSpecILi1EE6offsetEv(%"struct.HingeNodeSpec<1>"*) nounwind + +declare %struct.Vec3* @_ZNK13HingeNodeSpecILi1EE5posCMEv(%"struct.HingeNodeSpec<1>"*) nounwind + +declare double* @_ZNK13HingeNodeSpecILi1EE4massEv(%"struct.HingeNodeSpec<1>"*) nounwind + +declare void @_ZN13HingeNodeSpecILi1EE9calcPandZEv(%"struct.HingeNodeSpec<1>"*) + +declare i32 @_ZNK13HingeNodeSpecILi1EE6getDOFEv(%"struct.HingeNodeSpec<1>"*) nounwind + +declare i32 @_ZNK13HingeNodeSpecILi1EE6getDimEv(%"struct.HingeNodeSpec<1>"*) nounwind + +declare void @_ZN13HingeNodeSpecILi1EE18enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%"struct.HingeNodeSpec<1>"*, %"struct.CDSVector"*, %"struct.CDSVector"*) nounwind + +declare i32 @_ZNK13HingeNodeSpecILi5EE6offsetEv(%"struct.HingeNodeSpec<5>"*) nounwind + +declare %struct.Vec3* @_ZNK13HingeNodeSpecILi5EE5posCMEv(%"struct.HingeNodeSpec<5>"*) nounwind + +declare double* @_ZNK13HingeNodeSpecILi5EE4massEv(%"struct.HingeNodeSpec<5>"*) nounwind + +declare void @_ZN13HingeNodeSpecILi5EE9calcPandZEv(%"struct.HingeNodeSpec<5>"*) + +declare i32 @_ZNK13HingeNodeSpecILi5EE6getDOFEv(%"struct.HingeNodeSpec<5>"*) nounwind + +declare i32 @_ZNK13HingeNodeSpecILi5EE6getDimEv(%"struct.HingeNodeSpec<5>"*) nounwind + +declare void @_ZN13HingeNodeSpecILi5EE18enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%"struct.HingeNodeSpec<5>"*, %"struct.CDSVector"*, %"struct.CDSVector"*) nounwind + +declare i32 @_ZNK13HingeNodeSpecILi2EE6offsetEv(%"struct.HingeNodeSpec<2>"*) nounwind + +declare %struct.Vec3* @_ZNK13HingeNodeSpecILi2EE5posCMEv(%"struct.HingeNodeSpec<2>"*) nounwind + +declare double* @_ZNK13HingeNodeSpecILi2EE4massEv(%"struct.HingeNodeSpec<2>"*) nounwind + +declare void @_ZN13HingeNodeSpecILi2EE9calcPandZEv(%"struct.HingeNodeSpec<2>"*) + +declare i32 @_ZNK13HingeNodeSpecILi2EE6getDOFEv(%"struct.HingeNodeSpec<2>"*) nounwind + +declare i32 @_ZNK13HingeNodeSpecILi2EE6getDimEv(%"struct.HingeNodeSpec<2>"*) nounwind + +declare void @_ZN13HingeNodeSpecILi2EE18enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%"struct.HingeNodeSpec<2>"*, %"struct.CDSVector"*, %"struct.CDSVector"*) nounwind + +declare i32 @_ZNK13HingeNodeSpecILi3EE6offsetEv(%"struct.HingeNodeSpec<3>"*) nounwind + +declare %struct.Vec3* @_ZNK13HingeNodeSpecILi3EE5posCMEv(%"struct.HingeNodeSpec<3>"*) nounwind + +declare double* @_ZNK13HingeNodeSpecILi3EE4massEv(%"struct.HingeNodeSpec<3>"*) nounwind + +declare void @_ZN13HingeNodeSpecILi3EE9calcPandZEv(%"struct.HingeNodeSpec<3>"*) + +declare i32 @_ZNK13HingeNodeSpecILi3EE6getDOFEv(%"struct.HingeNodeSpec<3>"*) nounwind + +declare i32 @_ZNK13HingeNodeSpecILi6EE6offsetEv(%"struct.HingeNodeSpec<6>"*) nounwind + +declare %struct.Vec3* @_ZNK13HingeNodeSpecILi6EE5posCMEv(%"struct.HingeNodeSpec<6>"*) nounwind + +declare double* @_ZNK13HingeNodeSpecILi6EE4massEv(%"struct.HingeNodeSpec<6>"*) nounwind + +declare void @_ZN13HingeNodeSpecILi6EE9calcPandZEv(%"struct.HingeNodeSpec<6>"*) + +declare i32 @_ZNK13HingeNodeSpecILi6EE6getDOFEv(%"struct.HingeNodeSpec<6>"*) nounwind + +declare i32 @_ZNK13HingeNodeSpecILi6EE6getDimEv(%"struct.HingeNodeSpec<6>"*) nounwind + +declare void @_ZN13HingeNodeSpecILi6EE9setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES6_(%"struct.HingeNodeSpec<6>"*, %"struct.CDSVector"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi6EE18enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%"struct.HingeNodeSpec<6>"*, %"struct.CDSVector"*, %"struct.CDSVector"*) nounwind + +declare i32 @_ZNK13HingeNodeSpecILi3EE6getDimEv(%"struct.HingeNodeSpec<3>"*) nounwind + +declare void @_ZN13HingeNodeSpecILi3EE9setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES6_(%"struct.HingeNodeSpec<3>"*, %"struct.CDSVector"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi3EE18enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%"struct.HingeNodeSpec<3>"*, %"struct.CDSVector"*, %"struct.CDSVector"*) nounwind + +declare void @_Z14orthoTransformIdLi6ELi6EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%struct.Mat6* noalias sret, %struct.Mat6*, %struct.Mat6*) + +declare double @_ZN13HingeNodeSpecILi1EE8kineticEEv(%"struct.HingeNodeSpec<1>"*) + +declare double @_ZN13HingeNodeSpecILi3EE8kineticEEv(%"struct.HingeNodeSpec<3>"*) + +declare double @_ZN13HingeNodeSpecILi2EE8kineticEEv(%"struct.HingeNodeSpec<2>"*) + +declare double @_ZN13HingeNodeSpecILi6EE8kineticEEv(%"struct.HingeNodeSpec<6>"*) + +declare double @_ZN13HingeNodeSpecILi5EE8kineticEEv(%"struct.HingeNodeSpec<5>"*) + +declare void @_ZmlIdLi6ELi5ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%struct.Mat6* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) + +declare void @_ZN13HingeNodeSpecILi1EE9setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES6_(%"struct.HingeNodeSpec<1>"*, %"struct.CDSVector"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi5EE9setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES6_(%"struct.HingeNodeSpec<5>"*, %"struct.CDSVector"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi2EE9setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES6_(%"struct.HingeNodeSpec<2>"*, %"struct.CDSVector"*, %"struct.CDSVector"*) + +declare void @_Z14orthoTransformIdLi3ELi6EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%struct.Mat6* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) + +declare void @_ZmlIdLi6ELi1ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%struct.Mat6* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) + +declare void @_ZmlIdLi6ELi5ELi5EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) + +declare void @_Z14orthoTransformIdLi5ELi6EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%struct.Mat6* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) + +declare void @_Z14orthoTransformIdLi2ELi6EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%struct.Mat6* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) + +declare void @_ZmlIdLi1ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %struct.Mat6*) + +declare void @_ZmlIdLi5ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %struct.Mat6*) + +declare void @_Z14orthoTransformIdLi6ELi5EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix"*) + +declare void @_ZmlIdLi2ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %struct.Mat6*) + +declare void @_Z14orthoTransformIdLi6ELi2EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix"*) + +declare void @_ZmlIdLi3ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %struct.Mat6*) + +declare void @_Z14orthoTransformIdLi6ELi3EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix"*) + +declare void @_ZNSt8ios_base4InitC1Ev(%"struct.CDS::DefaultAlloc"*) + +declare i32 @__cxa_atexit(void (i8*)*, i8*, i8*) nounwind + +declare void @__tcf_0(i8* nocapture) + +declare void @_ZNSt8ios_base4InitD1Ev(%"struct.CDS::DefaultAlloc"*) + +declare %"struct.std::basic_ostream >"* @_ZlsRSoRK9HingeNode(%"struct.std::basic_ostream >"*, %struct.HingeNode*) + +declare %"struct.std::basic_ostream >"* @_ZlsRSoPK7IVMAtom(%"struct.std::basic_ostream >"*, %struct.IVMAtom*) + +declare void @_ZN9HingeNode8addChildEPS_(%struct.HingeNode*, %struct.HingeNode*) + +declare void @_ZN7CDSListIP9HingeNodeE6appendES1_(%"struct.CDSList"*, %struct.HingeNode*) + +declare void @_ZN9HingeNode4getHEv(%struct.RMat* noalias sret, %struct.HingeNode*) + +declare i8* @__cxa_allocate_exception(i32) nounwind + +declare void @__cxa_throw(i8*, i8*, void (i8*)*) noreturn + +declare void @_ZN9HingeNode16getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HingeNode*, %"struct.CDSVector"*) + +declare void @_ZN9HingeNode9calcAccelEv(%struct.HingeNode*) + +declare void @_ZN9HingeNode8getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HingeNode*, %"struct.CDSVector"*) + +declare void @_ZN9HingeNode6getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HingeNode*, %"struct.CDSVector"*) + +declare void @_ZN9HingeNode6getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HingeNode*, %"struct.CDSVector"*) + +declare void @_ZN9HingeNode5printEi(%struct.HingeNode*, i32) + +declare void @_ZN9HingeNode18enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES4_(%struct.HingeNode*, %"struct.CDSVector"*, %"struct.CDSVector"*) + +declare void @_ZN9HingeNode14setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%struct.HingeNode*, %"struct.FixedMatrix"*) + +declare void @_ZN9HingeNode6setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HingeNode*, %"struct.CDSVector"*) + +declare void @_ZN9HingeNode9setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%struct.HingeNode*, %"struct.CDSVector"*, %"struct.CDSVector"*) + +declare void @_ZN9HingeNode13propagateSVelERK11FixedVectorIdLi6ELi0EE(%struct.HingeNode*, %"struct.FixedMatrix"*) + +declare void @_ZN9HingeNode18prepareVelInternalEv(%struct.HingeNode*) + +declare void @_ZN9HingeNode17calcInternalForceEv(%struct.HingeNode*) + +declare void @_ZN9HingeNode5calcYEv(%struct.HingeNode*) + +declare void @_ZN9HingeNode9calcPandZEv(%struct.HingeNode*) + +declare void @_ZN9HingeNode5calcZEv(%struct.HingeNode*) + +declare void @_ZN9HingeNode5calcPEv(%struct.HingeNode*) + +declare double* @_ZNK9HingeNode4massEv(%struct.HingeNode*) + +declare %struct.Vec3* @_ZNK9HingeNode5posCMEv(%struct.HingeNode*) + +declare i8* @_Znam(i32) + +declare void @_ZN7CDSListIP9HingeNodeEC1Eii(%"struct.CDSList"*, i32, i32) + +declare i8* @_Znwm(i32) + +declare i8* @llvm.eh.exception() nounwind + +declare i32 @llvm.eh.selector.i32(i8*, i8*, ...) nounwind + +declare i32 @llvm.eh.typeid.for.i32(i8*) nounwind + +declare void @_ZdlPv(i8*) nounwind + +declare i32 @__gxx_personality_v0(...) + +declare void @_Unwind_Resume_or_Rethrow(i8*) + +declare void @_ZN7CDSListIP7IVMAtomEC1Eii(%struct.AtomList*, i32, i32) + +declare void @_ZN13CDSVectorBaseIdN3CDS12DefaultAllocEE8splitRepEv(%"struct.CDSVectorBase"*) + +declare void @_ZN12HNodeTorsion16getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTorsion*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi1EE8getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<1>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi1EE6getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<1>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi1EE6getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<1>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi1EE16getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<1>"*, %"struct.CDSVector"*) + +declare void @_ZN12HNodeRotate316getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate3*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi3EE16getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<3>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi3EE8getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<3>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi3EE6getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<3>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi3EE6getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<3>"*, %"struct.CDSVector"*) + +declare void @_ZN12HNodeRotate216getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate2*, %"struct.CDSVector"*) + +declare void @_ZN12HNodeRotate28getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate2*, %"struct.CDSVector"*) + +declare void @_ZN12HNodeRotate26getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate2*, %"struct.CDSVector"*) + +declare void @_ZN12HNodeRotate26getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate2*, %"struct.CDSVector"*) + +declare void @_ZN12HNodeRotate38getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate3*, %"struct.CDSVector"*) + +declare void @_ZN12HNodeRotate36getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate3*, %"struct.CDSVector"*) + +declare void @_ZN12HNodeRotate36getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate3*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi2EE16getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<2>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi2EE8getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<2>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi2EE6getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<2>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi2EE6getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<2>"*, %"struct.CDSVector"*) + +declare void @_ZN21HNodeTranslateRotate316getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate3*, %"struct.CDSVector"*) + +declare void @_ZN21HNodeTranslateRotate38getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate3*, %"struct.CDSVector"*) + +declare void @_ZN21HNodeTranslateRotate36getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate3*, %"struct.CDSVector"*) + +declare void @_ZN21HNodeTranslateRotate36getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate3*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi6EE16getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<6>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi6EE8getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<6>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi6EE6getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<6>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi6EE6getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<6>"*, %"struct.CDSVector"*) + +declare void @_ZN21HNodeTranslateRotate216getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate2*, %"struct.CDSVector"*) + +declare void @_ZN21HNodeTranslateRotate28getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate2*, %"struct.CDSVector"*) + +declare void @_ZN21HNodeTranslateRotate26getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate2*, %"struct.CDSVector"*) + +declare void @_ZN21HNodeTranslateRotate26getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate2*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi5EE16getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<5>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi5EE8getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<5>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi5EE6getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<5>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi5EE6getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<5>"*, %"struct.CDSVector"*) + +declare void @_ZN13CDSVectorBaseI4Vec3N3CDS12DefaultAllocEE8splitRepEv(%"struct.CDSVectorBase"*) + +declare void @_ZN7CDSListIP7IVMAtomE8splitRepEv(%struct.AtomList*) + +declare void @_ZN7CDSListIP9HingeNodeE8splitRepEv(%"struct.CDSList"*) + +declare void @_ZdaPv(i8*) nounwind + +declare void @_ZSt9terminatev() noreturn nounwind + +declare void @_ZN9HingeNodeC2EPK3IVMP7IVMAtomPKS3_PS_(%struct.HingeNode*, %struct.IVM*, %struct.IVMAtom*, %struct.IVMAtom*, %struct.HingeNode*) + +declare void @_ZN9HingeNodeD1Ev(%struct.HingeNode*) + +declare void @_ZN9HingeNodeD0Ev(%struct.HingeNode*) + +declare void @_ZN7CDSListIP7IVMAtomE6appendES1_(%struct.AtomList*, %struct.IVMAtom*) + +declare void @_ZN9HingeNodeC1EPK3IVMP7IVMAtomPKS3_PS_(%struct.HingeNode*, %struct.IVM*, %struct.IVMAtom*, %struct.IVMAtom*, %struct.HingeNode*) + +declare void @_ZN9HingeNodeD2Ev(%struct.HingeNode*) + +declare void @_ZN11HNodeOriginD0Ev(%struct.HNodeOrigin*) + +declare void @_ZN11HNodeOriginD1Ev(%struct.HNodeOrigin*) + +declare void @_ZN13HingeNodeSpecILi1EED0Ev(%"struct.HingeNodeSpec<1>"*) + +declare void @_ZN13HingeNodeSpecILi1EED1Ev(%"struct.HingeNodeSpec<1>"*) + +declare void @_ZN13HingeNodeSpecILi1EE5calcPEv(%"struct.HingeNodeSpec<1>"*) + +declare void @_ZN13HingeNodeSpecILi1EE5calcZEv(%"struct.HingeNodeSpec<1>"*) + +declare void @_ZN13HingeNodeSpecILi1EE5calcYEv(%"struct.HingeNodeSpec<1>"*) + +declare void @_ZN13HingeNodeSpecILi1EE17calcInternalForceEv(%"struct.HingeNodeSpec<1>"*) + +declare void @_ZN13HingeNodeSpecILi1EE18prepareVelInternalEv(%"struct.HingeNodeSpec<1>"*) + +declare void @_ZN13HingeNodeSpecILi1EE13propagateSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<1>"*, %"struct.FixedMatrix"*) + +declare double @_ZN13HingeNodeSpecILi1EE8approxKEEv(%"struct.HingeNodeSpec<1>"*) + +declare void @_ZN13HingeNodeSpecILi1EE6setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<1>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi1EE14setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<1>"*, %"struct.FixedMatrix"*) + +declare void @_ZN13HingeNodeSpecILi1EE5printEi(%"struct.HingeNodeSpec<1>"*, i32) + +declare void @_ZN13HingeNodeSpecILi1EE9calcAccelEv(%"struct.HingeNodeSpec<1>"*) + +declare void @_ZN13HingeNodeSpecILi1EE4getHEv(%struct.RMat* noalias sret, %"struct.HingeNodeSpec<1>"*) + +declare void @__cxa_pure_virtual() nounwind + +declare void @_ZN13HingeNodeSpecILi3EED0Ev(%"struct.HingeNodeSpec<3>"*) + +declare void @_ZN13HingeNodeSpecILi3EED1Ev(%"struct.HingeNodeSpec<3>"*) + +declare void @_ZN13HingeNodeSpecILi3EE5calcPEv(%"struct.HingeNodeSpec<3>"*) + +declare void @_ZN13HingeNodeSpecILi3EE5calcZEv(%"struct.HingeNodeSpec<3>"*) + +declare void @_ZN13HingeNodeSpecILi3EE5calcYEv(%"struct.HingeNodeSpec<3>"*) + +declare void @_ZN13HingeNodeSpecILi3EE17calcInternalForceEv(%"struct.HingeNodeSpec<3>"*) + +declare void @_ZN13HingeNodeSpecILi3EE18prepareVelInternalEv(%"struct.HingeNodeSpec<3>"*) + +declare void @_ZN13HingeNodeSpecILi3EE13propagateSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<3>"*, %"struct.FixedMatrix"*) + +declare double @_ZN13HingeNodeSpecILi3EE8approxKEEv(%"struct.HingeNodeSpec<3>"*) + +declare void @_ZN13HingeNodeSpecILi3EE6setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<3>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi3EE14setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<3>"*, %"struct.FixedMatrix"*) + +declare void @_ZN13HingeNodeSpecILi3EE5printEi(%"struct.HingeNodeSpec<3>"*, i32) + +declare void @_ZN13HingeNodeSpecILi3EE9calcAccelEv(%"struct.HingeNodeSpec<3>"*) + +declare void @_ZN13HingeNodeSpecILi3EE4getHEv(%struct.RMat* noalias sret, %"struct.HingeNodeSpec<3>"*) + +declare void @_ZN13HingeNodeSpecILi2EED0Ev(%"struct.HingeNodeSpec<2>"*) + +declare void @_ZN13HingeNodeSpecILi2EED1Ev(%"struct.HingeNodeSpec<2>"*) + +declare void @_ZN13HingeNodeSpecILi2EE5calcPEv(%"struct.HingeNodeSpec<2>"*) + +declare void @_ZN13HingeNodeSpecILi2EE5calcZEv(%"struct.HingeNodeSpec<2>"*) + +declare void @_ZN13HingeNodeSpecILi2EE5calcYEv(%"struct.HingeNodeSpec<2>"*) + +declare void @_ZN13HingeNodeSpecILi2EE17calcInternalForceEv(%"struct.HingeNodeSpec<2>"*) + +declare void @_ZN13HingeNodeSpecILi2EE18prepareVelInternalEv(%"struct.HingeNodeSpec<2>"*) + +declare void @_ZN13HingeNodeSpecILi2EE13propagateSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<2>"*, %"struct.FixedMatrix"*) + +declare double @_ZN13HingeNodeSpecILi2EE8approxKEEv(%"struct.HingeNodeSpec<2>"*) + +declare void @_ZN13HingeNodeSpecILi2EE6setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<2>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi2EE14setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<2>"*, %"struct.FixedMatrix"*) + +declare void @_ZN13HingeNodeSpecILi2EE5printEi(%"struct.HingeNodeSpec<2>"*, i32) + +declare void @_ZN13HingeNodeSpecILi2EE9calcAccelEv(%"struct.HingeNodeSpec<2>"*) + +declare void @_ZN13HingeNodeSpecILi2EE4getHEv(%struct.RMat* noalias sret, %"struct.HingeNodeSpec<2>"*) + +declare void @_ZN13HingeNodeSpecILi6EED0Ev(%"struct.HingeNodeSpec<6>"*) + +declare void @_ZN13HingeNodeSpecILi6EED1Ev(%"struct.HingeNodeSpec<6>"*) + +declare void @_ZN13HingeNodeSpecILi6EE5calcPEv(%"struct.HingeNodeSpec<6>"*) + +declare void @_ZN13HingeNodeSpecILi6EE5calcZEv(%"struct.HingeNodeSpec<6>"*) + +declare void @_ZN13HingeNodeSpecILi6EE5calcYEv(%"struct.HingeNodeSpec<6>"*) + +declare void @_ZN13HingeNodeSpecILi6EE17calcInternalForceEv(%"struct.HingeNodeSpec<6>"*) + +declare void @_ZN13HingeNodeSpecILi6EE18prepareVelInternalEv(%"struct.HingeNodeSpec<6>"*) + +declare void @_ZN13HingeNodeSpecILi6EE13propagateSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<6>"*, %"struct.FixedMatrix"*) + +declare double @_ZN13HingeNodeSpecILi6EE8approxKEEv(%"struct.HingeNodeSpec<6>"*) + +declare void @_ZN13HingeNodeSpecILi6EE6setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<6>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi6EE14setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<6>"*, %"struct.FixedMatrix"*) + +declare void @_ZN13HingeNodeSpecILi6EE5printEi(%"struct.HingeNodeSpec<6>"*, i32) + +declare void @_ZN13HingeNodeSpecILi6EE9calcAccelEv(%"struct.HingeNodeSpec<6>"*) + +declare void @_ZN13HingeNodeSpecILi6EE4getHEv(%struct.RMat* noalias sret, %"struct.HingeNodeSpec<6>"*) + +declare void @_ZN13HingeNodeSpecILi5EED0Ev(%"struct.HingeNodeSpec<5>"*) + +declare void @_ZN13HingeNodeSpecILi5EED1Ev(%"struct.HingeNodeSpec<5>"*) + +declare void @_ZN13HingeNodeSpecILi5EE5calcPEv(%"struct.HingeNodeSpec<5>"*) + +declare void @_ZN13HingeNodeSpecILi5EE5calcZEv(%"struct.HingeNodeSpec<5>"*) + +declare void @_ZN13HingeNodeSpecILi5EE5calcYEv(%"struct.HingeNodeSpec<5>"*) + +declare void @_ZN13HingeNodeSpecILi5EE17calcInternalForceEv(%"struct.HingeNodeSpec<5>"*) + +declare void @_ZN13HingeNodeSpecILi5EE18prepareVelInternalEv(%"struct.HingeNodeSpec<5>"*) + +declare void @_ZN13HingeNodeSpecILi5EE13propagateSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<5>"*, %"struct.FixedMatrix"*) + +declare double @_ZN13HingeNodeSpecILi5EE8approxKEEv(%"struct.HingeNodeSpec<5>"*) + +declare void @_ZN13HingeNodeSpecILi5EE6setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<5>"*, %"struct.CDSVector"*) + +declare void @_ZN13HingeNodeSpecILi5EE14setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<5>"*, %"struct.FixedMatrix"*) + +declare void @_ZN13HingeNodeSpecILi5EE5printEi(%"struct.HingeNodeSpec<5>"*, i32) + +declare void @_ZN13HingeNodeSpecILi5EE9calcAccelEv(%"struct.HingeNodeSpec<5>"*) + +declare void @_ZN13HingeNodeSpecILi5EE4getHEv(%struct.RMat* noalias sret, %"struct.HingeNodeSpec<5>"*) + +declare void @_ZN12HNodeTorsion7calcRotEv(%struct.HNodeTorsion*) + +declare double @sin(double) nounwind readnone + +declare double @cos(double) nounwind readnone + +declare void @_ZN12HNodeRotate37calcRotEv(%struct.HNodeRotate3*) + +declare void @_ZN21HNodeTranslateRotate37calcRotEv(%struct.HNodeTranslateRotate3*) + +declare void @_ZN9HingeNodeC2ERKS_(%struct.HingeNode*, %struct.HingeNode*) + +declare void @_ZN7CDSListIP9HingeNodeEC1ERKS2_(%"struct.CDSList"*, %"struct.CDSList"*) + +declare void @_ZN7CDSListIP7IVMAtomEC1ERKS2_(%struct.AtomList*, %struct.AtomList*) + +declare void @_ZN11HNodeOriginC2EPK9HingeNode(%struct.HNodeOrigin*, %struct.HingeNode*) + +declare void @_ZN13HingeNodeSpecILi1EEC2EPK9HingeNodeRi(%"struct.HingeNodeSpec<1>"*, %struct.HingeNode*, i32*) + +declare void @_ZN13HingeNodeSpecILi3EEC2EPK9HingeNodeRi(%"struct.HingeNodeSpec<3>"*, %struct.HingeNode*, i32*) + +declare void @_ZN13HingeNodeSpecILi2EEC2EPK9HingeNodeRi(%"struct.HingeNodeSpec<2>"*, %struct.HingeNode*, i32*) + +declare void @_ZN13HingeNodeSpecILi6EEC2EPK9HingeNodeRi(%"struct.HingeNodeSpec<6>"*, %struct.HingeNode*, i32*) + +declare void @_ZN13HingeNodeSpecILi5EEC2EPK9HingeNodeRi(%"struct.HingeNodeSpec<5>"*, %struct.HingeNode*, i32*) + +declare void @_ZplI4Vec3K11FixedVectorIdLi6ELi0EEET_RK9SubVectorIT0_ERKS4_(%struct.Vec3* noalias sret, %"struct.SubVector >"*, %struct.Vec3*) + +declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi1ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*) + +declare void @_ZN12HNodeRotate314setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%struct.HNodeRotate3*, %"struct.FixedMatrix"*) + +declare void @_ZN12HNodeRotate214setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%struct.HNodeRotate2*, %"struct.FixedMatrix"*) + +declare void @_ZN21HNodeTranslateRotate314setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%struct.HNodeTranslateRotate3*, %"struct.FixedMatrix"*) + +declare void @_ZN21HNodeTranslateRotate214setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%struct.HNodeTranslateRotate2*, %"struct.FixedMatrix"*) + +declare void @_ZN13HingeNodeSpecILi1EE9calcPropsEv(%"struct.HingeNodeSpec<1>"*) + +declare zeroext i8 @_ZNK3IVM12minimizationEv(%struct.IVM*) + +declare void @_Z8blockVecIdLi3ELi3EE11FixedVectorIT_XplT0_T1_ELi0EERKS0_IS1_XT0_ELi0EERKS0_IS1_XT1_ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) + +declare void @_ZN12HNodeTorsion11toCartesianEv(%struct.HNodeTorsion*) + +declare void @_ZN13HingeNodeSpecILi1EE18calcCartesianForceEv(%"struct.HingeNodeSpec<1>"*) + +declare void @_ZN13HingeNodeSpecILi3EE18calcCartesianForceEv(%"struct.HingeNodeSpec<3>"*) + +declare void @_ZN13HingeNodeSpecILi2EE18calcCartesianForceEv(%"struct.HingeNodeSpec<2>"*) + +declare void @_ZN13HingeNodeSpecILi6EE18calcCartesianForceEv(%"struct.HingeNodeSpec<6>"*) + +declare void @_ZN13HingeNodeSpecILi5EE18calcCartesianForceEv(%"struct.HingeNodeSpec<5>"*) + +declare void @_ZN12HNodeTorsion5calcHEv(%struct.HNodeTorsion*) + +declare void @_Z10blockMat12IdLi1ELi3ELi3EE11FixedMatrixIT_XT0_EXplT1_T2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) + +declare void @_ZN13CDSMatrixBaseIdEC2I11FixedMatrixIdLi1ELi6ELi0ELi0EEEERKT_(%"struct.CDSMatrixBase"*, %"struct.FixedMatrix"*) + +declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi1ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*) + +declare %"struct.std::basic_ostream >"* @_ZStlsIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_St13_Setprecision(%"struct.std::basic_ostream >"*, i32) + +declare %"struct.std::basic_ostream >"* @_ZlsIdLi6EERSoS0_RK15FixedVectorBaseIT_XT0_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) + +declare %"struct.std::basic_ostream >"* @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c(%"struct.std::basic_ostream >"*, i8 signext) + +declare %"struct.std::basic_ostream >"* @_ZlsIdLi3EERSoS0_RK15FixedVectorBaseIT_XT0_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) + +declare %"struct.std::basic_ostream >"* @_ZlsIdLi1EERSoS0_RK15FixedVectorBaseIT_XT0_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) + +declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi1ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, i32, i32, i32) + +declare %"struct.FixedMatrixBase"* @_ZN15FixedMatrixBaseIdLi6ELi6EEpLERKS0_(%"struct.FixedMatrixBase"*, %"struct.FixedMatrixBase"*) + +declare void @_ZN13HingeNodeSpecILi6EE9calcPropsEv(%"struct.HingeNodeSpec<6>"*) + +declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%struct.Mat6* noalias sret, %struct.Mat6*) + +declare void @_ZN21HNodeTranslateRotate311toCartesianEv(%struct.HNodeTranslateRotate3*) + +define linkonce void @_ZN21HNodeTranslateRotate36setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate3* %this, %"struct.CDSVector"* %velv) { +entry: + %0 = add i32 0, -1 ; [#uses=1] + %1 = getelementptr double* null, i32 %0 ; [#uses=1] + %2 = load double* %1, align 8 ; [#uses=1] + %3 = load double* null, align 8 ; [#uses=2] + %4 = load double* null, align 8 ; [#uses=2] + %5 = load double* null, align 8 ; [#uses=3] + %6 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 0 ; [#uses=0] + %7 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 1 ; [#uses=0] + %8 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 2 ; [#uses=0] + %9 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 3 ; [#uses=0] + %10 = load double* null, align 8 ; [#uses=2] + %11 = sub double -0.000000e+00, %10 ; [#uses=1] + %12 = load double* null, align 8 ; [#uses=2] + %13 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 1, i32 0, i32 0, i32 0, i32 3 ; [#uses=1] + %14 = load double* %13, align 8 ; [#uses=2] + %15 = sub double -0.000000e+00, %14 ; [#uses=1] + %16 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 1, i32 0, i32 0, i32 0, i32 2 ; [#uses=1] + %17 = load double* %16, align 8 ; [#uses=2] + %18 = sub double -0.000000e+00, %17 ; [#uses=1] + %19 = getelementptr %"struct.FixedMatrix"* null, i32 0, i32 0, i32 0, i32 0 ; [#uses=0] + %20 = getelementptr %"struct.FixedMatrix"* null, i32 0, i32 0, i32 0, i32 3 ; [#uses=0] + %21 = getelementptr %"struct.FixedMatrix"* null, i32 0, i32 0, i32 0, i32 6 ; [#uses=0] + %22 = getelementptr %"struct.FixedMatrix"* null, i32 0, i32 0, i32 0, i32 9 ; [#uses=0] + %23 = getelementptr %"struct.FixedMatrix"* null, i32 0, i32 0, i32 0, i32 1 ; [#uses=0] + %24 = getelementptr %"struct.FixedMatrix"* null, i32 0, i32 0, i32 0, i32 4 ; [#uses=0] + %25 = getelementptr %"struct.FixedMatrix"* null, i32 0, i32 0, i32 0, i32 7 ; [#uses=0] + %26 = getelementptr %"struct.FixedMatrix"* null, i32 0, i32 0, i32 0, i32 10 ; [#uses=0] + %27 = getelementptr %"struct.FixedMatrix"* null, i32 0, i32 0, i32 0, i32 2 ; [#uses=0] + %28 = getelementptr %"struct.FixedMatrix"* null, i32 0, i32 0, i32 0, i32 5 ; [#uses=0] + %29 = getelementptr %"struct.FixedMatrix"* null, i32 0, i32 0, i32 0, i32 8 ; [#uses=0] + %30 = getelementptr %"struct.FixedMatrix"* null, i32 0, i32 0, i32 0, i32 11 ; [#uses=0] + %31 = getelementptr %"struct.FixedMatrix"* null, i32 0, i32 0, i32 0, i32 0 ; [#uses=0] + %32 = getelementptr %"struct.FixedMatrix"* null, i32 0, i32 0, i32 0, i32 1 ; [#uses=1] + %33 = getelementptr %"struct.FixedMatrix"* null, i32 0, i32 0, i32 0, i32 2 ; [#uses=1] + %34 = mul double %17, %5 ; [#uses=1] + %35 = add double 0.000000e+00, %34 ; [#uses=1] + %36 = add double 0.000000e+00, 0.000000e+00 ; [#uses=1] + %37 = mul double %14, %3 ; [#uses=1] + %38 = add double %36, %37 ; [#uses=1] + %39 = mul double %12, %4 ; [#uses=1] + %40 = add double %38, %39 ; [#uses=1] + %41 = mul double %5, %11 ; [#uses=1] + %42 = add double %40, %41 ; [#uses=2] + store double %42, double* %32, align 8 + %43 = mul double %2, %15 ; [#uses=1] + %44 = add double %43, 0.000000e+00 ; [#uses=1] + %45 = mul double %3, %18 ; [#uses=1] + %46 = add double %44, %45 ; [#uses=1] + %47 = mul double %10, %4 ; [#uses=1] + %48 = add double %46, %47 ; [#uses=1] + %49 = mul double %12, %5 ; [#uses=1] + %50 = add double %48, %49 ; [#uses=2] + store double %50, double* %33, align 8 + %51 = mul double %35, 2.000000e+00 ; [#uses=1] + %52 = mul double %42, 2.000000e+00 ; [#uses=1] + %53 = mul double %50, 2.000000e+00 ; [#uses=1] + %54 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 0, i32 10, i32 0, i32 0, i32 0 ; [#uses=1] + store double %51, double* %54, align 8 + %55 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 0, i32 10, i32 0, i32 0, i32 1 ; [#uses=1] + store double %52, double* %55, align 8 + %56 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 0, i32 10, i32 0, i32 0, i32 2 ; [#uses=1] + store double %53, double* %56, align 8 + %57 = add i32 0, 4 ; [#uses=1] + %58 = getelementptr %"struct.SubVector >"* null, i32 0, i32 0 ; <%"struct.CDSVector"**> [#uses=1] + store %"struct.CDSVector"* %velv, %"struct.CDSVector"** %58, align 8 + %59 = getelementptr %"struct.SubVector >"* null, i32 0, i32 1 ; [#uses=1] + store i32 %57, i32* %59, align 4 + %60 = getelementptr %"struct.SubVector >"* null, i32 0, i32 2 ; [#uses=1] + store i32 3, i32* %60, align 8 + unreachable +} + +declare void @_ZmlRK11FixedMatrixIdLi6ELi6ELi0ELi0EERK18PhiMatrixTranspose(%struct.Mat6* noalias sret, %struct.Mat6*, %struct.PhiMatrixTranspose*) + +declare void @_ZmlI4Mat3K11FixedMatrixIdLi6ELi6ELi0ELi0EEET_RK9SubMatrixIT0_ERKS4_(%struct.Mat3* noalias sret, %"struct.SubMatrix >"*, %struct.Mat3*) + +declare void @_ZmiI4Mat3K11FixedMatrixIdLi6ELi6ELi0ELi0EEET_RK9SubMatrixIT0_ERKS4_(%struct.Mat3* noalias sret, %"struct.SubMatrix >"*, %struct.Mat3*) + +declare %"struct.FixedMatrixBase"* @_ZN15FixedMatrixBaseIdLi3ELi3EEmIERKS0_(%"struct.FixedMatrixBase"*, %"struct.FixedMatrixBase"*) + +declare void @_ZplI4Mat311FixedMatrixIdLi6ELi6ELi0ELi0EEET_RKS3_RK9SubMatrixIT0_E(%struct.Mat3* noalias sret, %struct.Mat3*, %"struct.SubMatrix >"*) + +declare void @_ZN13CDSVectorBaseIdN3CDS12DefaultAllocEED2Ev(%"struct.CDSVectorBase"*) + +declare void @_ZN13HingeNodeSpecILi1EE7calcD_GERK11FixedMatrixIdLi6ELi6ELi0ELi0EE(%"struct.HingeNodeSpec<1>"*, %struct.Mat6*) + +declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi1ELi1ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.MatrixTools::InverseResults >"*) + +declare i8* @__cxa_get_exception_ptr(i8*) nounwind + +declare i8* @__cxa_begin_catch(i8*) nounwind + +declare %"struct.std::basic_ostream >"* @_ZlsIdLi1ELi1EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) + +declare %"struct.std::basic_ostream >"* @_ZlsIdLi1ELi6EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) + +declare %"struct.std::basic_ostream >"* @_ZNSolsEi(%"struct.std::basic_ostream >"*, i32) + +declare %"struct.std::basic_ostream >"* @_ZlsIcERSoS0_RK9CDSStringIT_E(%"struct.std::basic_ostream >"*, %struct.String*) + +declare %"struct.std::basic_ostream >"* @_ZNSolsEPFRSoS_E(%"struct.std::basic_ostream >"*, %"struct.std::basic_ostream >"* (%"struct.std::basic_ostream >"*)*) + +declare %"struct.std::basic_ostream >"* @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_(%"struct.std::basic_ostream >"*) + +declare void @__cxa_end_catch() + +declare void @_ZmlI4Mat311FixedMatrixIdLi6ELi6ELi0ELi0EEET_RKS3_RK9SubMatrixIT0_E(%struct.Mat3* noalias sret, %struct.Mat3*, %"struct.SubMatrix >"*) + +declare void @_ZmlI4Mat311FixedMatrixIdLi6ELi6ELi0ELi0EEET_RK9SubMatrixIT0_ERKS3_(%struct.Mat3* noalias sret, %"struct.SubMatrix >"*, %struct.Mat3*) + +declare void @_ZmiI4Mat311FixedMatrixIdLi6ELi6ELi0ELi0EEET_RK9SubMatrixIT0_ERKS3_(%struct.Mat3* noalias sret, %"struct.SubMatrix >"*, %struct.Mat3*) + +declare %"struct.FixedMatrixBase"* @_ZN15FixedMatrixBaseIdLi6ELi6EEmIERKS0_(%"struct.FixedMatrixBase"*, %"struct.FixedMatrixBase"*) + +declare void @_ZN13CDSVectorBaseI4Vec3N3CDS12DefaultAllocEEC2EiS2_(%"struct.CDSVectorBase"*, i32, %"struct.CDS::DefaultAlloc"* byval align 4) + +declare void @_ZN13CDSVectorBaseI4Vec3N3CDS12DefaultAllocEED2Ev(%"struct.CDSVectorBase"*) + +declare void @_ZN12HNodeTorsionD0Ev(%struct.HNodeTorsion*) + +declare void @_ZN12HNodeTorsionD1Ev(%struct.HNodeTorsion*) + +declare void @_ZN12HNodeRotate3D0Ev(%struct.HNodeRotate3*) + +declare void @_ZN12HNodeRotate3D1Ev(%struct.HNodeRotate3*) + +declare void @_ZN12HNodeRotate36setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate3*, %"struct.CDSVector"*) + +declare void @_ZN12HNodeRotate318enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES4_(%struct.HNodeRotate3*, %"struct.CDSVector"*, %"struct.CDSVector"*) + +declare void @_ZN12HNodeRotate35printEi(%struct.HNodeRotate3*, i32) + +declare void @_ZN12HNodeRotate35calcHEv(%struct.HNodeRotate3*) + +declare void @_ZN12HNodeRotate311toCartesianEv(%struct.HNodeRotate3*) + +declare void @_ZN12HNodeRotate2D0Ev(%struct.HNodeRotate2*) + +declare void @_ZN12HNodeRotate2D1Ev(%struct.HNodeRotate2*) + +declare void @_ZN12HNodeRotate26setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate2*, %"struct.CDSVector"*) + +declare void @_ZN12HNodeRotate218enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES4_(%struct.HNodeRotate2*, %"struct.CDSVector"*, %"struct.CDSVector"*) + +declare void @_ZN12HNodeRotate25printEi(%struct.HNodeRotate2*, i32) + +declare void @_ZN12HNodeRotate25calcHEv(%struct.HNodeRotate2*) + +declare void @_ZN12HNodeRotate211toCartesianEv(%struct.HNodeRotate2*) + +declare void @_ZN21HNodeTranslateRotate3D0Ev(%struct.HNodeTranslateRotate3*) + +declare void @_ZN21HNodeTranslateRotate3D1Ev(%struct.HNodeTranslateRotate3*) + +declare void @_ZN21HNodeTranslateRotate318enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES4_(%struct.HNodeTranslateRotate3*, %"struct.CDSVector"*, %"struct.CDSVector"*) + +declare void @_ZN21HNodeTranslateRotate35printEi(%struct.HNodeTranslateRotate3*, i32) + +declare void @_ZN21HNodeTranslateRotate35calcHEv(%struct.HNodeTranslateRotate3*) + +declare void @_ZN21HNodeTranslateRotate2D0Ev(%struct.HNodeTranslateRotate2*) + +declare void @_ZN21HNodeTranslateRotate2D1Ev(%struct.HNodeTranslateRotate2*) + +declare void @_ZN21HNodeTranslateRotate26setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate2*, %"struct.CDSVector"*) + +declare void @_ZN21HNodeTranslateRotate218enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES4_(%struct.HNodeTranslateRotate2*, %"struct.CDSVector"*, %"struct.CDSVector"*) + +declare void @_ZN21HNodeTranslateRotate25printEi(%struct.HNodeTranslateRotate2*, i32) + +declare void @_ZN21HNodeTranslateRotate25calcHEv(%struct.HNodeTranslateRotate2*) + +declare void @_ZN21HNodeTranslateRotate211toCartesianEv(%struct.HNodeTranslateRotate2*) + +declare void @_ZN14HNodeTranslateC2EPK9HingeNodeP7IVMAtomRi(%struct.HNodeTranslate*, %struct.HingeNode*, %struct.IVMAtom*, i32*) + +declare void @_ZN14HNodeTranslateD1Ev(%struct.HNodeTranslate*) + +declare void @_ZN14HNodeTranslateD0Ev(%struct.HNodeTranslate*) + +declare void @_ZN14HNodeTranslate5calcHEv(%struct.HNodeTranslate*) + +declare void @_ZN14HNodeTranslate11toCartesianEv(%struct.HNodeTranslate*) + +declare void @_ZN12HNodeRotate3C2EPK9HingeNodeP7IVMAtomRib(%struct.HNodeRotate3*, %struct.HingeNode*, %struct.IVMAtom*, i32*, i8 zeroext) + +declare void @_ZN8AtomTree6findCMEPK9HingeNode(%struct.Vec3* noalias sret, %struct.HingeNode*) + +declare %struct.IVMAtom** @_ZN7CDSListIP7IVMAtomE7prependERKS1_(%struct.AtomList*, %struct.IVMAtom**) + +declare %"struct.CDSVectorBase"* @_ZN13CDSVectorBaseI4Vec3N3CDS12DefaultAllocEE6resizeEi(%"struct.CDSVectorBase"*, i32) + +declare void @_ZN12HNodeRotate2C2EPK9HingeNodeRK4Vec3Ri(%struct.HNodeRotate2*, %struct.HingeNode*, %struct.Vec3*, i32*) + +declare void @_ZN21HNodeTranslateRotate3C2EPK9HingeNodeP7IVMAtomRib(%struct.HNodeTranslateRotate3*, %struct.HingeNode*, %struct.IVMAtom*, i32*, i8 zeroext) + +declare void @_ZN13HingeNodeSpecILi3EE9calcPropsEv(%"struct.HingeNodeSpec<3>"*) + +declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi3ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*) + +declare void @_ZN11MatrixTools9transposeI4Mat3EENT_13TransposeTypeERKS2_(%struct.Mat3* noalias sret, %struct.Mat3*) + +declare void @_Z10blockMat12IdLi3ELi3ELi3EE11FixedMatrixIT_XT0_EXplT1_T2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) + +declare void @_ZN13CDSMatrixBaseIdEC2I11FixedMatrixIdLi3ELi6ELi0ELi0EEEERKT_(%"struct.CDSMatrixBase"*, %"struct.FixedMatrix"*) + +declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi3ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*) + +declare %"struct.std::basic_ostream >"* @_ZlsIdLi4EERSoS0_RK15FixedVectorBaseIT_XT0_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) + +declare double @_Z4normIdLi4EET_RK11FixedVectorIS0_XT0_ELi0EE(%"struct.FixedMatrix"*) + +declare %"struct.FixedMatrixBase"* @_ZN15FixedVectorBaseIdLi4EEdVERKd(%"struct.FixedMatrixBase"*, double*) + +declare %"struct.FixedMatrixBase"* @_ZN15FixedVectorBaseIdLi4EEmIERKS0_(%"struct.FixedMatrixBase"*, %"struct.FixedMatrixBase"*) + +declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi3ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, i32, i32, i32) + +declare void @_ZN13HingeNodeSpecILi3EE7calcD_GERK11FixedMatrixIdLi6ELi6ELi0ELi0EE(%"struct.HingeNodeSpec<3>"*, %struct.Mat6*) + +declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi3ELi3ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.MatrixTools::InverseResults >"*) + +declare %"struct.std::basic_ostream >"* @_ZlsIdLi3ELi3EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) + +declare %"struct.std::basic_ostream >"* @_ZlsIdLi3ELi6EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) + +declare void @_Z7unitVecRK4Vec3(%struct.Vec3* noalias sret, %struct.Vec3*) + +declare double @_Z4normIdLi3EET_RK11FixedVectorIS0_XT0_ELi0EE(%"struct.FixedMatrix"*) + +declare void @_ZN12HNodeTorsionC2EPK9HingeNodeRK4Vec3Ri(%struct.HNodeTorsion*, %struct.HingeNode*, %struct.Vec3*, i32*) + +declare double @acos(double) nounwind readnone + +declare double @atan2(double, double) nounwind readnone + +declare void @_ZN21HNodeTranslateRotate2C2EPK9HingeNodeRi(%struct.HNodeTranslateRotate2*, %struct.HingeNode*, i32*) + +declare void @_ZN13HingeNodeSpecILi2EE9calcPropsEv(%"struct.HingeNodeSpec<2>"*) + +declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi2ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*) + +declare void @_Z10blockMat21IdLi1ELi3ELi1EE11FixedMatrixIT_XplT0_T2_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT2_EXT1_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) + +declare void @_Z10blockMat12IdLi2ELi3ELi3EE11FixedMatrixIT_XT0_EXplT1_T2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) + +declare void @_ZN13CDSMatrixBaseIdEC2I11FixedMatrixIdLi2ELi6ELi0ELi0EEEERKT_(%"struct.CDSMatrixBase"*, %"struct.FixedMatrix"*) + +declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi2ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*) + +declare %"struct.std::basic_ostream >"* @_ZlsIdLi2EERSoS0_RK15FixedVectorBaseIT_XT0_EE(%"struct.std::basic_ostream >"*, %"struct.FixedVectorBase"*) + +declare %"struct.FixedMatrixBase"* @_ZN15FixedVectorBaseIdLi3EEdVERKd(%"struct.FixedMatrixBase"*, double*) + +declare %"struct.FixedMatrixBase"* @_ZN15FixedVectorBaseIdLi3EEmIERKS0_(%"struct.FixedMatrixBase"*, %"struct.FixedMatrixBase"*) + +declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi2ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, i32, i32, i32) + +declare void @_ZN13HingeNodeSpecILi2EE7calcD_GERK11FixedMatrixIdLi6ELi6ELi0ELi0EE(%"struct.HingeNodeSpec<2>"*, %struct.Mat6*) + +declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi2ELi2ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.MatrixTools::InverseResults >"*) + +declare %"struct.std::basic_ostream >"* @_ZlsIdLi2ELi2EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) + +declare %"struct.std::basic_ostream >"* @_ZlsIdLi2ELi6EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) + +declare zeroext i8 @_ZNK9CDSStringIcE7matchesEPKcb(%struct.String*, i8*, i8 zeroext) + +declare %struct.HingeNode* @_Z9constructP9HingeNodeRKN16InternalDynamics9HingeSpecERi(%struct.HingeNode*, %"struct.InternalDynamics::HingeSpec"*, i32*) + +declare void @_ZN9CDSStringIcEC1ERKS0_(%struct.String*, %struct.String*) + +declare void @_ZN9CDSStringIcE8downcaseEv(%struct.String*) + +declare %struct.String* @_ZN9CDSStringIcEaSEPKc(%struct.String*, i8*) + +declare %"struct.std::basic_ostream >"* @_ZlsIP7IVMAtomERSoS2_RK7CDSListIT_E(%"struct.std::basic_ostream >"*, %struct.AtomList*) + +declare i32 @_ZNK7CDSListIP9HingeNodeE8getIndexERKS1_(%"struct.CDSList"*, %struct.HingeNode**) + +declare void @_ZN13CDSMatrixBaseIdEC2I11FixedMatrixIdLi6ELi6ELi0ELi0EEEERKT_(%"struct.CDSMatrixBase"*, %struct.Mat6*) + +declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi6ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix"* noalias sret, %struct.Mat6*, i32, i32, i32) + +declare void @_ZN13HingeNodeSpecILi6EE7calcD_GERK11FixedMatrixIdLi6ELi6ELi0ELi0EE(%"struct.HingeNodeSpec<6>"*, %struct.Mat6*) + +declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi6ELi6ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%struct.Mat6* noalias sret, %struct.Mat6*, %"struct.MatrixTools::InverseResults >"*) + +declare %"struct.std::basic_ostream >"* @_ZlsIdLi6ELi6EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) + +declare void @_ZN13HingeNodeSpecILi5EE9calcPropsEv(%"struct.HingeNodeSpec<5>"*) + +declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi5ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*) + +declare void @_ZN13CDSMatrixBaseIdEC2I11FixedMatrixIdLi5ELi6ELi0ELi0EEEERKT_(%"struct.CDSMatrixBase"*, %"struct.FixedMatrix"*) + +declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi5ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*) + +declare %"struct.std::basic_ostream >"* @_ZlsIdLi5EERSoS0_RK15FixedVectorBaseIT_XT0_EE(%"struct.std::basic_ostream >"*, %"struct.FixedVectorBase"*) + +declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi5ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, i32, i32, i32) + +declare void @_ZN13HingeNodeSpecILi5EE7calcD_GERK11FixedMatrixIdLi6ELi6ELi0ELi0EE(%"struct.HingeNodeSpec<5>"*, %struct.Mat6*) + +declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi5ELi5ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.MatrixTools::InverseResults >"*) + +declare %"struct.std::basic_ostream >"* @_ZlsIdLi5ELi5EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) + +declare %"struct.std::basic_ostream >"* @_ZlsIdLi5ELi6EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) + +declare void @llvm.memset.i64(i8* nocapture, i8, i64, i32) nounwind From isanbard at gmail.com Tue Jan 27 16:58:54 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 27 Jan 2009 14:58:54 -0800 Subject: [llvm-commits] [llvm] r63142 - in /llvm/trunk/lib/Target: DarwinTargetAsmInfo.cpp ELFTargetAsmInfo.cpp TargetAsmInfo.cpp In-Reply-To: <200901272229.n0RMTPEj024749@zion.cs.uiuc.edu> References: <200901272229.n0RMTPEj024749@zion.cs.uiuc.edu> Message-ID: <16e5fdf90901271458v92d7a35se1c969962da54ecb@mail.gmail.com> On Tue, Jan 27, 2009 at 2:29 PM, Anton Korobeynikov wrote: > Author: asl > Date: Tue Jan 27 16:29:24 2009 > New Revision: 63142 > > URL: http://llvm.org/viewvc/llvm-project?rev=63142&view=rev > Log: > Treat [1 x i8] zeroinitializer as a C string, placing such stuff into > mergeable string section. I don't see any bad impact of such decision > (rather then placing it into mergeable const section, as it was before), > but at least Darwin linker won't complain anymore. > > The problem in LLVM is that we don't have special type for string constants > (like gcc does). Even more, we have two separate types: ConstatArray for non-null > strings and ConstantAggregateZero for null stuff.... It's a bit weird :) > Thanks, Anton! :-) -bw From isanbard at gmail.com Tue Jan 27 17:00:54 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 27 Jan 2009 23:00:54 -0000 Subject: [llvm-commits] [llvm] r63149 - /llvm/trunk/test/CodeGen/X86/2009-01-27-NullStrings.ll Message-ID: <200901272300.n0RN0sbp025962@zion.cs.uiuc.edu> Author: void Date: Tue Jan 27 17:00:53 2009 New Revision: 63149 URL: http://llvm.org/viewvc/llvm-project?rev=63149&view=rev Log: Add testcase for r63142. Added: llvm/trunk/test/CodeGen/X86/2009-01-27-NullStrings.ll Added: llvm/trunk/test/CodeGen/X86/2009-01-27-NullStrings.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-01-27-NullStrings.ll?rev=63149&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-01-27-NullStrings.ll (added) +++ llvm/trunk/test/CodeGen/X86/2009-01-27-NullStrings.ll Tue Jan 27 17:00:53 2009 @@ -0,0 +1,40 @@ +; RUN: llvm-as < %s | llc -march=x86 | grep {\\.cstring} | count 1 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i386-apple-darwin9.6" + %struct.A = type { } + %struct.NSString = type opaque + %struct.__builtin_CFString = type { i32*, i32, i8*, i32 } + %struct._objc_module = type { i32, i32, i8*, %struct._objc_symtab* } + %struct._objc_symtab = type { i32, %struct.objc_selector**, i16, i16 } + %struct.objc_object = type opaque + %struct.objc_selector = type opaque +@"\01L_unnamed_cfstring_0" = internal constant %struct.__builtin_CFString { i32* getelementptr ([0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 1992, i8* getelementptr ([1 x i8]* @"\01LC", i32 0, i32 0), i32 0 }, section "__DATA, __cfstring" ; <%struct.__builtin_CFString*> [#uses=1] + at __CFConstantStringClassReference = external global [0 x i32] ; <[0 x i32]*> [#uses=1] +@"\01LC" = internal constant [1 x i8] zeroinitializer ; <[1 x i8]*> [#uses=1] +@"\01L_OBJC_SELECTOR_REFERENCES_0" = internal global %struct.objc_selector* bitcast ([6 x i8]* @"\01L_OBJC_METH_VAR_NAME_0" to %struct.objc_selector*), section "__OBJC,__message_refs,literal_pointers,no_dead_strip", align 4 ; <%struct.objc_selector**> [#uses=2] +@"\01L_OBJC_SYMBOLS" = internal global %struct._objc_symtab zeroinitializer, section "__OBJC,__symbols,regular,no_dead_strip", align 4 ; <%struct._objc_symtab*> [#uses=2] +@"\01L_OBJC_METH_VAR_NAME_0" = internal global [6 x i8] c"bork:\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[6 x i8]*> [#uses=2] +@"\01L_OBJC_IMAGE_INFO" = internal constant [2 x i32] zeroinitializer, section "__OBJC, __image_info,regular" ; <[2 x i32]*> [#uses=1] +@"\01L_OBJC_CLASS_NAME_0" = internal global [1 x i8] zeroinitializer, section "__TEXT,__cstring,cstring_literals", align 1 ; <[1 x i8]*> [#uses=1] +@"\01L_OBJC_MODULES" = internal global %struct._objc_module { i32 7, i32 16, i8* getelementptr ([1 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), %struct._objc_symtab* @"\01L_OBJC_SYMBOLS" }, section "__OBJC,__module_info,regular,no_dead_strip", align 4 ; <%struct._objc_module*> [#uses=1] + at llvm.used = appending global [6 x i8*] [ i8* bitcast (%struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_0" to i8*), i8* bitcast (%struct._objc_symtab* @"\01L_OBJC_SYMBOLS" to i8*), i8* getelementptr ([6 x i8]* @"\01L_OBJC_METH_VAR_NAME_0", i32 0, i32 0), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*), i8* getelementptr ([1 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), i8* bitcast (%struct._objc_module* @"\01L_OBJC_MODULES" to i8*) ], section "llvm.metadata" ; <[6 x i8*]*> [#uses=0] + +define void @func(%struct.A* %a) nounwind { +entry: + %a_addr = alloca %struct.A* ; <%struct.A**> [#uses=2] + %a.0 = alloca %struct.objc_object* ; <%struct.objc_object**> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store %struct.A* %a, %struct.A** %a_addr + %0 = load %struct.A** %a_addr, align 4 ; <%struct.A*> [#uses=1] + %1 = bitcast %struct.A* %0 to %struct.objc_object* ; <%struct.objc_object*> [#uses=1] + store %struct.objc_object* %1, %struct.objc_object** %a.0, align 4 + %2 = load %struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_0", align 4 ; <%struct.objc_selector*> [#uses=1] + %3 = load %struct.objc_object** %a.0, align 4 ; <%struct.objc_object*> [#uses=1] + call void bitcast (%struct.objc_object* (%struct.objc_object*, %struct.objc_selector*, ...)* @objc_msgSend to void (%struct.objc_object*, %struct.objc_selector*, %struct.NSString*)*)(%struct.objc_object* %3, %struct.objc_selector* %2, %struct.NSString* bitcast (%struct.__builtin_CFString* @"\01L_unnamed_cfstring_0" to %struct.NSString*)) nounwind + br label %return + +return: ; preds = %entry + ret void +} + +declare %struct.objc_object* @objc_msgSend(%struct.objc_object*, %struct.objc_selector*, ...) From dalej at apple.com Tue Jan 27 17:19:41 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 27 Jan 2009 23:19:41 -0000 Subject: [llvm-commits] [llvm] r63151 - /llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Message-ID: <200901272319.n0RNJf59026803@zion.cs.uiuc.edu> Author: johannes Date: Tue Jan 27 17:19:41 2009 New Revision: 63151 URL: http://llvm.org/viewvc/llvm-project?rev=63151&view=rev Log: Reorder args, constify. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=63151&r1=63150&r2=63151&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Tue Jan 27 17:19:41 2009 @@ -902,7 +902,7 @@ inline bool isTargetOpcode() const; inline bool isMachineOpcode() const; inline unsigned getMachineOpcode() const; - inline DebugLoc getDebugLoc() const; + inline const DebugLoc getDebugLoc() const; /// reachesChainWithoutSideEffects - Return true if this operand (which must @@ -1152,10 +1152,10 @@ void setNodeId(int Id) { NodeId = Id; } /// getDebugLoc - Return the source location info. - DebugLoc getDebugLoc() const { return debugLoc; } + const DebugLoc getDebugLoc() const { return debugLoc; } /// setDebugLoc - Set source location info. - void setDebugLoc(DebugLoc sl) { debugLoc = sl; } + void setDebugLoc(const DebugLoc dl) { debugLoc = dl; } /// use_iterator - This class provides iterator support for SDUse /// operands that use a specific SDNode. @@ -1363,10 +1363,10 @@ /// The next two constructors specify DebugLoc explicitly; the intent /// is that they will replace the above two over time, and eventually /// the ones above can be removed. - SDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, unsigned NumOps, - DebugLoc sl) + SDNode(unsigned Opc, const DebugLoc dl, SDVTList VTs, const SDValue *Ops, + unsigned NumOps) : NodeType(Opc), OperandsNeedDelete(true), SubclassData(0), - NodeId(-1), debugLoc(sl), + NodeId(-1), debugLoc(dl), OperandList(NumOps ? new SDUse[NumOps] : 0), ValueList(VTs.VTs), NumOperands(NumOps), NumValues(VTs.NumVTs), @@ -1379,9 +1379,9 @@ /// This constructor adds no operands itself; operands can be /// set later with InitOperands. - SDNode(unsigned Opc, SDVTList VTs, DebugLoc sl) + SDNode(unsigned Opc, const DebugLoc dl, SDVTList VTs) : NodeType(Opc), OperandsNeedDelete(false), SubclassData(0), - NodeId(-1), debugLoc(sl), OperandList(0), + NodeId(-1), debugLoc(dl), OperandList(0), ValueList(VTs.VTs), NumOperands(0), NumValues(VTs.NumVTs), UseList(NULL) {} @@ -1479,7 +1479,7 @@ inline bool SDValue::hasOneUse() const { return Node->hasNUsesOfValue(1, ResNo); } -inline DebugLoc SDValue::getDebugLoc() const { +inline const DebugLoc SDValue::getDebugLoc() const { return Node->getDebugLoc(); } From dalej at apple.com Tue Jan 27 17:20:29 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 27 Jan 2009 23:20:29 -0000 Subject: [llvm-commits] [llvm] r63152 - in /llvm/trunk: include/llvm/CodeGen/MachineInstr.h lib/CodeGen/MachineInstr.cpp Message-ID: <200901272320.n0RNKTLa026851@zion.cs.uiuc.edu> Author: johannes Date: Tue Jan 27 17:20:29 2009 New Revision: 63152 URL: http://llvm.org/viewvc/llvm-project?rev=63152&view=rev Log: Add a DebugLoc field and some simple accessors. Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h llvm/trunk/lib/CodeGen/MachineInstr.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=63152&r1=63151&r2=63152&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Tue Jan 27 17:20:29 2009 @@ -22,6 +22,7 @@ #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/Target/TargetInstrDesc.h" +#include "llvm/CodeGen/DebugLoc.h" #include #include @@ -43,6 +44,7 @@ std::vector Operands; // the operands std::list MemOperands; // information on memory references MachineBasicBlock *Parent; // Pointer to the owning basic block. + DebugLoc debugLoc; // Source line information. // OperandComplete - Return true if it's illegal to add a new operand bool OperandsComplete() const; @@ -64,17 +66,34 @@ /// TID NULL and no operands. MachineInstr(); + // The next two constructors have DebugLoc and non-DebugLoc versions; + // over time, the non-DebugLoc versions should be phased out and eventually + // removed. + /// MachineInstr ctor - This constructor create a MachineInstr and add the /// implicit operands. It reserves space for number of operands specified by - /// TargetInstrDesc. + /// TargetInstrDesc. The version with a DebugLoc should be preferred. explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false); /// MachineInstr ctor - Work exactly the same as the ctor above, except that /// the MachineInstr is created and added to the end of the specified basic - /// block. + /// block. The version with a DebugLoc should be preferred. /// MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID); + /// MachineInstr ctor - This constructor create a MachineInstr and add the + /// implicit operands. It reserves space for number of operands specified by + /// TargetInstrDesc. An explicit DebugLoc is supplied. + explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl, + bool NoImp = false); + + /// MachineInstr ctor - Work exactly the same as the ctor above, except that + /// the MachineInstr is created and added to the end of the specified basic + /// block. + /// + MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, + const TargetInstrDesc &TID); + ~MachineInstr(); // MachineInstrs are pool-allocated and owned by MachineFunction. @@ -83,6 +102,10 @@ public: const MachineBasicBlock* getParent() const { return Parent; } MachineBasicBlock* getParent() { return Parent; } + + /// getDebugLoc - Returns the debug location id of this MachineInstr. + /// + const DebugLoc getDebugLoc() const { return debugLoc; } /// getDesc - Returns the target instruction descriptor of this /// MachineInstr. @@ -289,6 +312,10 @@ /// void setDesc(const TargetInstrDesc &tid) { TID = &tid; } + /// setDebugLoc - Replace current source information with new such. + /// + void setDebugLoc(const DebugLoc dl) { debugLoc = dl; } + /// RemoveOperand - Erase an operand from an instruction, leaving it with one /// fewer operand than it started with. /// Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=63152&r1=63151&r2=63152&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Tue Jan 27 17:20:29 2009 @@ -283,7 +283,7 @@ /// MachineInstr ctor - This constructor creates a dummy MachineInstr with /// TID NULL and no operands. MachineInstr::MachineInstr() - : TID(0), NumImplicitOps(0), Parent(0) { + : TID(0), NumImplicitOps(0), Parent(0), debugLoc(DebugLoc::getUnknownLoc()) { // Make sure that we get added to a machine basicblock LeakDetector::addGarbageObject(this); } @@ -302,7 +302,8 @@ /// TargetInstrDesc or the numOperands if it is not zero. (for /// instructions with variable number of operands). MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp) - : TID(&tid), NumImplicitOps(0), Parent(0) { + : TID(&tid), NumImplicitOps(0), Parent(0), + debugLoc(DebugLoc::getUnknownLoc()) { if (!NoImp && TID->getImplicitDefs()) for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) NumImplicitOps++; @@ -316,12 +317,49 @@ LeakDetector::addGarbageObject(this); } -/// MachineInstr ctor - Work exactly the same as the ctor above, except that the -/// MachineInstr is created and added to the end of the specified basic block. +/// MachineInstr ctor - As above, but with a DebugLoc. +MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl, + bool NoImp) + : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) { + if (!NoImp && TID->getImplicitDefs()) + for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) + NumImplicitOps++; + if (!NoImp && TID->getImplicitUses()) + for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) + NumImplicitOps++; + Operands.reserve(NumImplicitOps + TID->getNumOperands()); + if (!NoImp) + addImplicitDefUseOperands(); + // Make sure that we get added to a machine basicblock + LeakDetector::addGarbageObject(this); +} + +/// MachineInstr ctor - Work exactly the same as the ctor two above, except +/// that the MachineInstr is created and added to the end of the specified +/// basic block. +/// +MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid) + : TID(&tid), NumImplicitOps(0), Parent(0), + debugLoc(DebugLoc::getUnknownLoc()) { + assert(MBB && "Cannot use inserting ctor with null basic block!"); + if (TID->ImplicitDefs) + for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) + NumImplicitOps++; + if (TID->ImplicitUses) + for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) + NumImplicitOps++; + Operands.reserve(NumImplicitOps + TID->getNumOperands()); + addImplicitDefUseOperands(); + // Make sure that we get added to a machine basicblock + LeakDetector::addGarbageObject(this); + MBB->push_back(this); // Add instruction to end of basic block! +} + +/// MachineInstr ctor - As above, but with a DebugLoc. /// -MachineInstr::MachineInstr(MachineBasicBlock *MBB, +MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, const TargetInstrDesc &tid) - : TID(&tid), NumImplicitOps(0), Parent(0) { + : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) { assert(MBB && "Cannot use inserting ctor with null basic block!"); if (TID->ImplicitDefs) for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) @@ -339,7 +377,8 @@ /// MachineInstr ctor - Copies MachineInstr arg exactly /// MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) - : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0) { + : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0), + debugLoc(MI.getDebugLoc()) { Operands.reserve(MI.getNumOperands()); // Add operands From dpatel at apple.com Tue Jan 27 17:22:55 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 27 Jan 2009 23:22:55 -0000 Subject: [llvm-commits] [llvm] r63154 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Message-ID: <200901272322.n0RNMtnf026970@zion.cs.uiuc.edu> Author: dpatel Date: Tue Jan 27 17:22:55 2009 New Revision: 63154 URL: http://llvm.org/viewvc/llvm-project?rev=63154&view=rev Log: Add type DIE into appropriate context DIE. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=63154&r1=63153&r2=63154&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Tue Jan 27 17:22:55 2009 @@ -1687,9 +1687,23 @@ ConstructTypeDIE(DW_Unit, Buffer, DICompositeType(Ty.getGV())); } - // Add debug information entry to entity and unit. - DIE *Die = DW_Unit->AddDie(Buffer); - SetDIEntry(Slot, Die); + // Add debug information entry to entity and appropriate context. + DIE *Die = NULL; + DIDescriptor Context = Ty.getContext(); + if (!Context.isNull()) + Die = DW_Unit->getDieMapSlotFor(Context.getGV()); + + if (Die) { + DIE *Child = new DIE(Buffer); + Die->AddChild(Child); + Buffer.Detach(); + SetDIEntry(Slot, Child); + } + else { + Die = DW_Unit->AddDie(Buffer); + SetDIEntry(Slot, Die); + } + Entity->AddValue(DW_AT_type, DW_FORM_ref4, Slot); } From dalej at apple.com Tue Jan 27 17:32:10 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 27 Jan 2009 23:32:10 -0000 Subject: [llvm-commits] [llvm] r63155 - in /llvm/trunk/include/llvm/CodeGen: MachineInstr.h SelectionDAGNodes.h Message-ID: <200901272332.n0RNWBpM027325@zion.cs.uiuc.edu> Author: johannes Date: Tue Jan 27 17:32:10 2009 New Revision: 63155 URL: http://llvm.org/viewvc/llvm-project?rev=63155&view=rev Log: Embalm my ideas of how things should work. Not that anyone will pay attention. Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=63155&r1=63154&r2=63155&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Tue Jan 27 17:32:10 2009 @@ -313,6 +313,7 @@ void setDesc(const TargetInstrDesc &tid) { TID = &tid; } /// setDebugLoc - Replace current source information with new such. + /// Avoid using this, the constructor argument is preferable. /// void setDebugLoc(const DebugLoc dl) { debugLoc = dl; } Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=63155&r1=63154&r2=63155&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Tue Jan 27 17:32:10 2009 @@ -1154,7 +1154,8 @@ /// getDebugLoc - Return the source location info. const DebugLoc getDebugLoc() const { return debugLoc; } - /// setDebugLoc - Set source location info. + /// setDebugLoc - Set source location info. Try to avoid this, putting + /// it in the constructor is preferable. void setDebugLoc(const DebugLoc dl) { debugLoc = dl; } /// use_iterator - This class provides iterator support for SDUse From isanbard at gmail.com Tue Jan 27 17:47:37 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 27 Jan 2009 23:47:37 -0000 Subject: [llvm-commits] [llvm] r63156 - /llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Message-ID: <200901272347.n0RNlbaT027834@zion.cs.uiuc.edu> Author: void Date: Tue Jan 27 17:47:37 2009 New Revision: 63156 URL: http://llvm.org/viewvc/llvm-project?rev=63156&view=rev Log: Pull r63154 into Dib: Add type DIE into appropriate context DIE. Modified: llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Modified: llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=63156&r1=63155&r2=63156&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Tue Jan 27 17:47:37 2009 @@ -1687,9 +1687,23 @@ ConstructTypeDIE(DW_Unit, Buffer, DICompositeType(Ty.getGV())); } - // Add debug information entry to entity and unit. - DIE *Die = DW_Unit->AddDie(Buffer); - SetDIEntry(Slot, Die); + // Add debug information entry to entity and appropriate context. + DIE *Die = NULL; + DIDescriptor Context = Ty.getContext(); + if (!Context.isNull()) + Die = DW_Unit->getDieMapSlotFor(Context.getGV()); + + if (Die) { + DIE *Child = new DIE(Buffer); + Die->AddChild(Child); + Buffer.Detach(); + SetDIEntry(Slot, Child); + } + else { + Die = DW_Unit->AddDie(Buffer); + SetDIEntry(Slot, Die); + } + Entity->AddValue(DW_AT_type, DW_FORM_ref4, Slot); } From evan.cheng at apple.com Tue Jan 27 18:53:34 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 28 Jan 2009 00:53:34 -0000 Subject: [llvm-commits] [llvm] r63161 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Message-ID: <200901280053.n0S0rYYv030888@zion.cs.uiuc.edu> Author: evancheng Date: Tue Jan 27 18:53:34 2009 New Revision: 63161 URL: http://llvm.org/viewvc/llvm-project?rev=63161&view=rev Log: Suppress a compile time warning. Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=63161&r1=63160&r2=63161&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Tue Jan 27 18:53:34 2009 @@ -701,6 +701,7 @@ return OffsetIsInRange(UserOffset, CPEOffset, MaxDisp, !isThumb); } +#ifndef NDEBUG /// BBIsJumpedOver - Return true of the specified basic block's only predecessor /// unconditionally branches to its only successor. static bool BBIsJumpedOver(MachineBasicBlock *MBB) { @@ -714,6 +715,7 @@ return PredMI->getOperand(0).getMBB() == Succ; return false; } +#endif // NDEBUG void ARMConstantIslands::AdjustBBOffsetsAfter(MachineBasicBlock *BB, int delta) { From isanbard at gmail.com Tue Jan 27 19:19:52 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 28 Jan 2009 01:19:52 -0000 Subject: [llvm-commits] [llvm] r63164 - /llvm/trunk/include/llvm/CodeGen/DebugLoc.h Message-ID: <200901280119.n0S1Jql8032144@zion.cs.uiuc.edu> Author: void Date: Tue Jan 27 19:19:52 2009 New Revision: 63164 URL: http://llvm.org/viewvc/llvm-project?rev=63164&view=rev Log: Comment fixes. Modified: llvm/trunk/include/llvm/CodeGen/DebugLoc.h Modified: llvm/trunk/include/llvm/CodeGen/DebugLoc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DebugLoc.h?rev=63164&r1=63163&r2=63164&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/DebugLoc.h (original) +++ llvm/trunk/include/llvm/CodeGen/DebugLoc.h Tue Jan 27 19:19:52 2009 @@ -9,6 +9,8 @@ // // This file defines a number of light weight data structures used by the code // generator to describe and track debug location information. +// +//===----------------------------------------------------------------------===// #ifndef LLVM_CODEGEN_DEBUGLOC_H #define LLVM_CODEGEN_DEBUGLOC_H @@ -27,8 +29,8 @@ : Src(s), Line(l), Col(c) {}; }; - /// DebugLoc - Debug location id. This is carried by SDNode and - /// MachineInstr to index into a vector of unique debug location tuples. + /// DebugLoc - Debug location id. This is carried by SDNode and MachineInstr + /// to index into a vector of unique debug location tuples. class DebugLoc { unsigned Idx; @@ -38,11 +40,11 @@ static DebugLoc getUnknownLoc() { DebugLoc L; L.Idx = 0; return L; } static DebugLoc get(unsigned idx) { DebugLoc L; L.Idx = idx; return L; } - // isInvalid - Return true if the DebugLoc is invalid. + /// isInvalid - Return true if the DebugLoc is invalid. bool isInvalid() const { return Idx == ~0U; } - // isUnknown - Return true if there is no debug info for the SDNode / - // MachineInstr. + /// isUnknown - Return true if there is no debug info for the SDNode / + /// MachineInstr. bool isUnknown() const { return Idx == 0; } }; @@ -71,12 +73,12 @@ /// DebugLocTracker - This class tracks debug location information. /// struct DebugLocTracker { - // DebugLocations - A vector of unique DebugLocTuple's. - // + /// DebugLocations - A vector of unique DebugLocTuple's. + /// std::vector DebugLocations; - // DebugIdsMap - This maps DebugLocTuple's to indices into - // DebugLocations vector. + /// DebugIdsMap - This maps DebugLocTuple's to indices into DebugLocations + /// vector. DenseMap DebugIdMap; DebugLocTracker() {} From dalej at apple.com Tue Jan 27 19:32:44 2009 From: dalej at apple.com (Dale Johannesen) Date: Wed, 28 Jan 2009 01:32:44 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63165 - in /llvm-gcc-4.2/trunk/gcc: c-parser.c cp/parser.c tree-nested.c Message-ID: <200901280132.n0S1WiJn032621@zion.cs.uiuc.edu> Author: johannes Date: Tue Jan 27 19:32:44 2009 New Revision: 63165 URL: http://llvm.org/viewvc/llvm-project?rev=63165&view=rev Log: Fix block-in_structors.C a different way; put back Duncan's favorite assert. Modified: llvm-gcc-4.2/trunk/gcc/c-parser.c llvm-gcc-4.2/trunk/gcc/cp/parser.c llvm-gcc-4.2/trunk/gcc/tree-nested.c Modified: llvm-gcc-4.2/trunk/gcc/c-parser.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/c-parser.c?rev=63165&r1=63164&r2=63165&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/c-parser.c (original) +++ llvm-gcc-4.2/trunk/gcc/c-parser.c Tue Jan 27 19:32:44 2009 @@ -10201,6 +10201,8 @@ block_helper_function_decl = build_helper_func_decl (build_block_helper_name (0), ftype); DECL_CONTEXT (block_helper_function_decl) = current_function_decl; + /* LLVM LOCAL 6530487 - blocks helper functions never need a static chain */ + DECL_NO_STATIC_CHAIN (block_helper_function_decl) = 1; cur_block->helper_func_decl = block_helper_function_decl; push_function_context (); Modified: llvm-gcc-4.2/trunk/gcc/cp/parser.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/cp/parser.c?rev=63165&r1=63164&r2=63165&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/cp/parser.c (original) +++ llvm-gcc-4.2/trunk/gcc/cp/parser.c Tue Jan 27 19:32:44 2009 @@ -21461,6 +21461,8 @@ block_helper_function_decl = build_helper_func_decl (build_block_helper_name (unique_count), ftype); DECL_CONTEXT (block_helper_function_decl) = current_function_decl; + /* LLVM LOCAL 6530487 - blocks helper functions never need a static chain */ + DECL_NO_STATIC_CHAIN (block_helper_function_decl) = 1; cur_block->helper_func_decl = block_helper_function_decl; DECL_ARGUMENTS (block_helper_function_decl) = arglist; Modified: llvm-gcc-4.2/trunk/gcc/tree-nested.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/tree-nested.c?rev=63165&r1=63164&r2=63165&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/tree-nested.c (original) +++ llvm-gcc-4.2/trunk/gcc/tree-nested.c Tue Jan 27 19:32:44 2009 @@ -1971,11 +1971,20 @@ walk_function (convert_tramp_reference, root); walk_function (convert_call_expr, root); + /* LLVM LOCAL begin */ + /* FIXME: Keep the LLVM-way? */ +#ifdef ENABLE_LLVM + gcc_assert (!root->outer || + DECL_NO_STATIC_CHAIN (root->context) == + !(root->chain_decl || root->chain_field)); +#else /* If the function does not use a static chain, then remember that. */ if (root->outer && !root->chain_decl && !root->chain_field) DECL_NO_STATIC_CHAIN (root->context) = 1; else gcc_assert (!DECL_NO_STATIC_CHAIN (root->context)); +#endif + /* LLVM LOCAL end */ root = root->next; } From gohman at apple.com Tue Jan 27 20:58:31 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 28 Jan 2009 02:58:31 -0000 Subject: [llvm-commits] [llvm] r63169 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp LegalizeVectorTypes.cpp Message-ID: <200901280258.n0S2wWJk003467@zion.cs.uiuc.edu> Author: djg Date: Tue Jan 27 20:58:31 2009 New Revision: 63169 URL: http://llvm.org/viewvc/llvm-project?rev=63169&view=rev Log: Use ZERO_EXTEND instead of ANY_EXTEND when promoting shift amounts, to avoid implicitly assuming that target architectures will ignore the high bits. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63169&r1=63168&r2=63169&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Jan 27 20:58:31 2009 @@ -974,7 +974,7 @@ return DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt); if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType())) - return DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt); + return DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), ShiftAmt); return ShiftAmt; } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=63169&r1=63168&r2=63169&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Jan 27 20:58:31 2009 @@ -114,7 +114,7 @@ if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType())) ShiftAmt = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt); else if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType())) - ShiftAmt = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt); + ShiftAmt = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), ShiftAmt); return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, ShiftAmt); } From gohman at apple.com Tue Jan 27 21:04:03 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 27 Jan 2009 19:04:03 -0800 Subject: [llvm-commits] [llvm] r63079 - /llvm/trunk/test/FrontendC/x86-64-red-zone.c In-Reply-To: <497F6608.50805@gmail.com> References: <200901270059.n0R0xt3h001002@zion.cs.uiuc.edu> <497F6608.50805@gmail.com> Message-ID: <2D79E797-703B-4DEF-809A-A2DED7F9C4D9@apple.com> On Jan 27, 2009, at 11:52 AM, T?r?k Edwin wrote: > On 2009-01-27 02:59, Dan Gohman wrote: >> >> +// This is a test for x86-64, add your target below if it FAILs. >> +// XFAIL: alpha|ia64|arm|powerpc|sparc|x86 > > Hi Dan, > > I get an XPASS on x86_64. It appears that x86_64 == x86 for XFAIL :( Hrm. Anyone have any ideas how to fix this? Dan From gohman at apple.com Tue Jan 27 21:10:52 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 28 Jan 2009 03:10:52 -0000 Subject: [llvm-commits] [llvm] r63170 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp LegalizeVectorTypes.cpp Message-ID: <200901280310.n0S3Aq5J004010@zion.cs.uiuc.edu> Author: djg Date: Tue Jan 27 21:10:52 2009 New Revision: 63170 URL: http://llvm.org/viewvc/llvm-project?rev=63170&view=rev Log: Use ValueType::bitsLT to simplify some code. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63170&r1=63169&r2=63170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Jan 27 21:10:52 2009 @@ -8515,7 +8515,7 @@ // It must be true that we the widen vector type is bigger than where // we need to store. assert(StVT.isVector() && VVT.isVector()); - assert(StVT.getSizeInBits() < VVT.getSizeInBits()); + assert(StVT.bitsLT(VVT)); assert(StVT.getVectorElementType() == VVT.getVectorElementType()); // Store value Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=63170&r1=63169&r2=63170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Jan 27 21:10:52 2009 @@ -1865,7 +1865,7 @@ // It must be true that we the widen vector type is bigger than where // we need to store. assert(StVT.isVector() && ValOp.getValueType().isVector()); - assert(StVT.getSizeInBits() < ValOp.getValueType().getSizeInBits()); + assert(StVT.bitsLT(ValOp.getValueType())); SmallVector StChain; if (ST->isTruncatingStore()) { From foldr at codedgers.com Tue Jan 27 21:46:23 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Wed, 28 Jan 2009 03:46:23 -0000 Subject: [llvm-commits] [llvm] r63171 - /llvm/trunk/lib/Support/CommandLine.cpp Message-ID: <200901280346.n0S3kNuA005873@zion.cs.uiuc.edu> Author: foldr Date: Tue Jan 27 21:46:22 2009 New Revision: 63171 URL: http://llvm.org/viewvc/llvm-project?rev=63171&view=rev Log: Clarify comment. Modified: llvm/trunk/lib/Support/CommandLine.cpp Modified: llvm/trunk/lib/Support/CommandLine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CommandLine.cpp?rev=63171&r1=63170&r2=63171&view=diff ============================================================================== --- llvm/trunk/lib/Support/CommandLine.cpp (original) +++ llvm/trunk/lib/Support/CommandLine.cpp Tue Jan 27 21:46:22 2009 @@ -396,7 +396,12 @@ // If we could open the file, parse its contents, otherwise // pass the @file option verbatim. - // TODO: support recursion. + + // TODO: we should also support recursive loading of response files, + // since this is how gcc behaves. (From their man page: "The file may + // itself contain additional @file options; any such options will be + // processed recursively.") + if (respFilePtr != 0) { ParseCStringVector(newArgv, respFilePtr->getBufferStart()); continue; From foldr at codedgers.com Tue Jan 27 21:47:20 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Wed, 28 Jan 2009 03:47:20 -0000 Subject: [llvm-commits] [llvm] r63172 - in /llvm/trunk: include/llvm/CompilerDriver/Common.td test/LLVMC/ExternOptions.td test/LLVMC/MultiValuedOption.td test/LLVMC/OneOrMore.td tools/llvmc/doc/LLVMC-Reference.rst utils/TableGen/LLVMCConfigurationEmitter.cpp Message-ID: <200901280347.n0S3lKJO005918@zion.cs.uiuc.edu> Author: foldr Date: Tue Jan 27 21:47:20 2009 New Revision: 63172 URL: http://llvm.org/viewvc/llvm-project?rev=63172&view=rev Log: Add three new option properties. Adds new option properties 'multi_val', 'one_or_more' and 'zero_or_one'. Added: llvm/trunk/test/LLVMC/MultiValuedOption.td llvm/trunk/test/LLVMC/OneOrMore.td Modified: llvm/trunk/include/llvm/CompilerDriver/Common.td llvm/trunk/test/LLVMC/ExternOptions.td llvm/trunk/tools/llvmc/doc/LLVMC-Reference.rst llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Modified: llvm/trunk/include/llvm/CompilerDriver/Common.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CompilerDriver/Common.td?rev=63172&r1=63171&r2=63172&view=diff ============================================================================== --- llvm/trunk/include/llvm/CompilerDriver/Common.td (original) +++ llvm/trunk/include/llvm/CompilerDriver/Common.td Tue Jan 27 21:47:20 2009 @@ -36,11 +36,14 @@ // Possible option properties. +def extern; def help; def hidden; +def multi_val; +def one_or_more; def really_hidden; def required; -def extern; +def zero_or_one; // Empty DAG marker. def empty; Modified: llvm/trunk/test/LLVMC/ExternOptions.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/ExternOptions.td?rev=63172&r1=63171&r2=63172&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/ExternOptions.td (original) +++ llvm/trunk/test/LLVMC/ExternOptions.td Tue Jan 27 21:47:20 2009 @@ -1,6 +1,7 @@ // Check that extern options work. // The dummy tool and graph are required to silence warnings. -// RUN: tblgen -I $srcroot/include --gen-llvmc %s | grep {extern .* AutoGeneratedSwitch_Wall} +// RUN: tblgen -I $srcroot/include --gen-llvmc %s -o %t +// RUN: grep {extern .* AutoGeneratedSwitch_Wall} %t include "llvm/CompilerDriver/Common.td" Added: llvm/trunk/test/LLVMC/MultiValuedOption.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/MultiValuedOption.td?rev=63172&view=auto ============================================================================== --- llvm/trunk/test/LLVMC/MultiValuedOption.td (added) +++ llvm/trunk/test/LLVMC/MultiValuedOption.td Tue Jan 27 21:47:20 2009 @@ -0,0 +1,21 @@ +// Check that multivalued options work. +// The dummy tool and graph are required to silence warnings. +// RUN: tblgen -I $srcroot/include --gen-llvmc %s -o %t +// RUN: grep cl::multi_val(2) %t | count 1 + +include "llvm/CompilerDriver/Common.td" + +def OptList : OptionList<[ + (prefix_list_option "foo", (multi_val 2)), + (parameter_list_option "baz", (multi_val 2), (extern))]>; + +def dummy_tool : Tool<[ +(cmd_line "dummy_cmd"), +(in_language "dummy"), +(out_language "dummy"), +(actions (case + (not_empty "foo"), (forward_as "foo", "bar"), + (not_empty "baz"), (forward "baz"))) +]>; + +def DummyGraph : CompilationGraph<[SimpleEdge<"root", "dummy_tool">]>; Added: llvm/trunk/test/LLVMC/OneOrMore.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/OneOrMore.td?rev=63172&view=auto ============================================================================== --- llvm/trunk/test/LLVMC/OneOrMore.td (added) +++ llvm/trunk/test/LLVMC/OneOrMore.td Tue Jan 27 21:47:20 2009 @@ -0,0 +1,22 @@ +// Check that (one_or_more) and (zero_or_one) properties work. +// The dummy tool and graph are required to silence warnings. +// RUN: tblgen -I $srcroot/include --gen-llvmc %s -o %t +// RUN: grep cl::ZeroOrOne %t | count 1 +// RUN: grep cl::OneOrMore %t | count 1 + +include "llvm/CompilerDriver/Common.td" + +def OptList : OptionList<[ + (prefix_list_option "foo", (one_or_more)), + (parameter_list_option "baz", (zero_or_one))]>; + +def dummy_tool : Tool<[ +(cmd_line "dummy_cmd"), +(in_language "dummy"), +(out_language "dummy"), +(actions (case + (not_empty "foo"), (forward_as "foo", "bar"), + (not_empty "baz"), (forward "baz"))) +]>; + +def DummyGraph : CompilationGraph<[SimpleEdge<"root", "dummy_tool">]>; Modified: llvm/trunk/tools/llvmc/doc/LLVMC-Reference.rst URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/doc/LLVMC-Reference.rst?rev=63172&r1=63171&r2=63172&view=diff ============================================================================== --- llvm/trunk/tools/llvmc/doc/LLVMC-Reference.rst (original) +++ llvm/trunk/tools/llvmc/doc/LLVMC-Reference.rst Tue Jan 27 21:47:20 2009 @@ -262,37 +262,47 @@ * Possible option types: - - ``switch_option`` - a simple boolean switch without arguments, - for example ``-O2`` or ``-time``. + - ``switch_option`` - a simple boolean switch without arguments, for example + ``-O2`` or ``-time``. At most one occurrence is allowed. - - ``parameter_option`` - option that takes one argument, for - example ``-std=c99``. It is also allowed to use spaces instead of - the equality sign: ``-std c99``. - - - ``parameter_list_option`` - same as the above, but more than one - option occurence is allowed. - - - ``prefix_option`` - same as the parameter_option, but the option - name and argument do not have to be separated. Example: - ``-ofile``. This can be also specified as ``-o file``; however, - ``-o=file`` will be parsed incorrectly (``=file`` will be - interpreted as option value). - - - ``prefix_list_option`` - same as the above, but more than one - occurence of the option is allowed; example: ``-lm -lpthread``. - - - ``alias_option`` - a special option type for creating - aliases. Unlike other option types, aliases are not allowed to - have any properties besides the aliased option name. Usage - example: ``(alias_option "preprocess", "E")`` + - ``parameter_option`` - option that takes one argument, for example + ``-std=c99``. It is also allowed to use spaces instead of the equality + sign: ``-std c99``. At most one occurrence is allowed. + + - ``parameter_list_option`` - same as the above, but more than one option + occurence is allowed. + + - ``prefix_option`` - same as the parameter_option, but the option name and + argument do not have to be separated. Example: ``-ofile``. This can be also + specified as ``-o file``; however, ``-o=file`` will be parsed incorrectly + (``=file`` will be interpreted as option value). At most one occurrence is + allowed. + + - ``prefix_list_option`` - same as the above, but more than one occurence of + the option is allowed; example: ``-lm -lpthread``. + + - ``alias_option`` - a special option type for creating aliases. Unlike other + option types, aliases are not allowed to have any properties besides the + aliased option name. Usage example: ``(alias_option "preprocess", "E")`` * Possible option properties: - - ``help`` - help string associated with this option. Used for - ``--help`` output. + - ``help`` - help string associated with this option. Used for ``--help`` + output. - - ``required`` - this option is obligatory. + - ``required`` - this option must be specified exactly once (or, in case of + the list options without the ``multi_val`` property, at least + once). Incompatible with ``zero_or_one`` and ``one_or_more``. + + - ``one_or_more`` - the option must be specified at least one time. Useful + only for list options in conjunction with ``multi_val``; for ordinary lists + it is synonymous with ``required``. Incompatible with ``required`` and + ``zero_or_one``. + + - ``zero_or_one`` - the option can be specified zero or one times. Useful + only for list options in conjunction with ``multi_val``. Incompatible with + ``required`` and ``one_or_more``. - ``hidden`` - the description of this option will not appear in the ``--help`` output (but will appear in the ``--help-hidden`` @@ -301,6 +311,11 @@ - ``really_hidden`` - the option will not be mentioned in any help output. + - ``multi_val n`` - this option takes *n* arguments (can be useful in some + special cases). Usage example: ``(parameter_list_option "foo", (multi_val + 3))``. Only list options can have this attribute; you can, however, use + the ``one_or_more`` and ``zero_or_one`` properties. + - ``extern`` - this option is defined in some other plugin, see below. External options Modified: llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp?rev=63172&r1=63171&r2=63172&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Tue Jan 27 21:47:20 2009 @@ -127,13 +127,19 @@ return false; } +template +void checkedIncrement(I& P, I E, S ErrorString) { + ++P; + if (P == E) + throw ErrorString; +} + //===----------------------------------------------------------------------===// /// Back-end specific code /// OptionType - One of six different option types. See the /// documentation for detailed description of differences. -/// Extern* options are those that are defined in some other plugin. namespace OptionType { enum OptionType { Alias, Switch, Parameter, ParameterList, Prefix, PrefixList}; @@ -171,7 +177,8 @@ namespace OptionDescriptionFlags { enum OptionDescriptionFlags { Required = 0x1, Hidden = 0x2, - ReallyHidden = 0x4, Extern = 0x8 }; + ReallyHidden = 0x4, Extern = 0x8, + OneOrMore = 0x10, ZeroOrOne = 0x20 }; } /// OptionDescription - Represents data contained in a single @@ -181,11 +188,12 @@ std::string Name; unsigned Flags; std::string Help; + unsigned MultiVal; OptionDescription(OptionType::OptionType t = OptionType::Switch, const std::string& n = "", const std::string& h = DefaultHelpString) - : Type(t), Name(n), Flags(0x0), Help(h) + : Type(t), Name(n), Flags(0x0), Help(h), MultiVal(1) {} /// GenTypeDeclaration - Returns the C++ variable type of this @@ -203,17 +211,26 @@ bool isAlias() const; + bool isMultiVal() const; + bool isExtern() const; void setExtern(); bool isRequired() const; void setRequired(); + bool isOneOrMore() const; + void setOneOrMore(); + + bool isZeroOrOne() const; + void setZeroOrOne(); + bool isHidden() const; void setHidden(); bool isReallyHidden() const; void setReallyHidden(); + }; void OptionDescription::Merge (const OptionDescription& other) @@ -235,6 +252,10 @@ return Type == OptionType::Alias; } +bool OptionDescription::isMultiVal() const { + return MultiVal == 1; +} + bool OptionDescription::isExtern() const { return Flags & OptionDescriptionFlags::Extern; } @@ -249,6 +270,20 @@ Flags |= OptionDescriptionFlags::Required; } +bool OptionDescription::isOneOrMore() const { + return Flags & OptionDescriptionFlags::OneOrMore; +} +void OptionDescription::setOneOrMore() { + Flags |= OptionDescriptionFlags::OneOrMore; +} + +bool OptionDescription::isZeroOrOne() const { + return Flags & OptionDescriptionFlags::ZeroOrOne; +} +void OptionDescription::setZeroOrOne() { + Flags |= OptionDescriptionFlags::ZeroOrOne; +} + bool OptionDescription::isHidden() const { return Flags & OptionDescriptionFlags::Hidden; } @@ -405,8 +440,11 @@ AddHandler("extern", &CollectOptionProperties::onExtern); AddHandler("help", &CollectOptionProperties::onHelp); AddHandler("hidden", &CollectOptionProperties::onHidden); + AddHandler("multi_val", &CollectOptionProperties::onMultiVal); + AddHandler("one_or_more", &CollectOptionProperties::onOneOrMore); AddHandler("really_hidden", &CollectOptionProperties::onReallyHidden); AddHandler("required", &CollectOptionProperties::onRequired); + AddHandler("zero_or_one", &CollectOptionProperties::onZeroOrOne); staticMembersInitialized_ = true; } @@ -439,9 +477,46 @@ void onRequired (const DagInit* d) { checkNumberOfArguments(d, 0); + if (optDesc_.isOneOrMore()) + throw std::string("An option can't have both (required) " + "and (one_or_more) properties!"); optDesc_.setRequired(); } + void onOneOrMore (const DagInit* d) { + checkNumberOfArguments(d, 0); + if (optDesc_.isRequired() || optDesc_.isZeroOrOne()) + throw std::string("Only one of (required), (zero_or_one) or " + "(one_or_more) properties is allowed!"); + if (!OptionType::IsList(optDesc_.Type)) + llvm::cerr << "Warning: specifying the 'one_or_more' property " + "on a non-list option will have no effect.\n"; + optDesc_.setOneOrMore(); + } + + void onZeroOrOne (const DagInit* d) { + checkNumberOfArguments(d, 0); + if (optDesc_.isRequired() || optDesc_.isOneOrMore()) + throw std::string("Only one of (required), (zero_or_one) or " + "(one_or_more) properties is allowed!"); + if (!OptionType::IsList(optDesc_.Type)) + llvm::cerr << "Warning: specifying the 'zero_or_one' property" + "on a non-list option will have no effect.\n"; + optDesc_.setZeroOrOne(); + } + + void onMultiVal (const DagInit* d) { + checkNumberOfArguments(d, 1); + int val = InitPtrToInt(d->getArg(0)); + if (val < 2) + throw std::string("Error in the 'multi_val' property: " + "the value must be greater than 1!"); + if (!OptionType::IsList(optDesc_.Type)) + throw std::string("The multi_val property is valid only " + "on list options!"); + optDesc_.MultiVal = val; + } + }; /// AddOption - A function object that is applied to every option @@ -639,7 +714,6 @@ }; - /// CollectToolDescriptions - Gather information about tool properties /// from the parsed TableGen data (basically a wrapper for the /// CollectToolProperties function object). @@ -1131,13 +1205,6 @@ } } -template -void checkedIncrement(I& P, I E, S ErrorString) { - ++P; - if (P == E) - throw ErrorString; -} - /// SubstituteSpecialCommands - Perform string substitution for $CALL /// and $ENV. Helper function used by EmitCmdLineVecFill(). StrVector::const_iterator SubstituteSpecialCommands @@ -1308,18 +1375,31 @@ case OptionType::PrefixList: O << Indent << "for (" << D.GenTypeDeclaration() << "::iterator B = " << D.GenVariableName() << ".begin(),\n" - << Indent << "E = " << D.GenVariableName() << ".end(); B != E; ++B)\n" + << Indent << "E = " << D.GenVariableName() << ".end(); B != E;) {\n" << Indent << Indent1 << "vec.push_back(\"" << Name << "\" + " - << "*B);\n"; + << "*B);\n" + << Indent << Indent1 << "++B;\n"; + + for (int i = 1, j = D.MultiVal; i < j; ++i) { + O << Indent << Indent1 << "vec.push_back(*B);\n" + << Indent << Indent1 << "++B;\n"; + } + + O << Indent << "}\n"; break; case OptionType::ParameterList: O << Indent << "for (" << D.GenTypeDeclaration() << "::iterator B = " << D.GenVariableName() << ".begin(),\n" << Indent << "E = " << D.GenVariableName() - << ".end() ; B != E; ++B) {\n" - << Indent << Indent1 << "vec.push_back(\"" << Name << "\");\n" - << Indent << Indent1 << "vec.push_back(*B);\n" - << Indent << "}\n"; + << ".end() ; B != E;) {\n" + << Indent << Indent1 << "vec.push_back(\"" << Name << "\");\n"; + + for (int i = 0, j = D.MultiVal; i < j; ++i) { + O << Indent << Indent1 << "vec.push_back(*B);\n" + << Indent << Indent1 << "++B;\n"; + } + + O << Indent << "}\n"; break; case OptionType::Alias: default: @@ -1376,6 +1456,9 @@ const std::string& Name = InitPtrToString(Dag.getArg(0)); const OptionDescription& D = OptDescs.FindOption(Name); + if (D.isMultiVal()) + throw std::string("Can't use unpack_values with multi-valued options!"); + if (OptionType::IsList(D.Type)) { O << IndentLevel << "for (" << D.GenTypeDeclaration() << "::iterator B = " << D.GenVariableName() << ".begin(),\n" @@ -1599,27 +1682,28 @@ O << ", cl::Prefix"; if (val.isRequired()) { - switch (val.Type) { - case OptionType::PrefixList: - case OptionType::ParameterList: + if (OptionType::IsList(val.Type) && !val.isMultiVal()) O << ", cl::OneOrMore"; - break; - default: + else O << ", cl::Required"; - } + } + else if (val.isOneOrMore() && OptionType::IsList(val.Type)) { + O << ", cl::OneOrMore"; + } + else if (val.isZeroOrOne() && OptionType::IsList(val.Type)) { + O << ", cl::ZeroOrOne"; } - if (val.isReallyHidden() || val.isHidden()) { - if (val.isRequired()) - O << " |"; - else - O << ","; - if (val.isReallyHidden()) - O << " cl::ReallyHidden"; - else - O << " cl::Hidden"; + if (val.isReallyHidden()) { + O << ", cl::ReallyHidden"; + } + else if (val.isHidden()) { + O << ", cl::Hidden"; } + if (val.MultiVal > 1) + O << ", cl::multi_val(" << val.MultiVal << ")"; + if (!val.Help.empty()) O << ", cl::desc(\"" << val.Help << "\")"; From foldr at codedgers.com Tue Jan 27 21:47:39 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Wed, 28 Jan 2009 03:47:39 -0000 Subject: [llvm-commits] [llvm] r63173 - /llvm/trunk/docs/CompilerDriver.html Message-ID: <200901280347.n0S3ldpr005943@zion.cs.uiuc.edu> Author: foldr Date: Tue Jan 27 21:47:38 2009 New Revision: 63173 URL: http://llvm.org/viewvc/llvm-project?rev=63173&view=rev Log: Update the generated docs. Modified: llvm/trunk/docs/CompilerDriver.html Modified: llvm/trunk/docs/CompilerDriver.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CompilerDriver.html?rev=63173&r1=63172&r2=63173&view=diff ============================================================================== --- llvm/trunk/docs/CompilerDriver.html (original) +++ llvm/trunk/docs/CompilerDriver.html Tue Jan 27 21:47:38 2009 @@ -263,38 +263,50 @@

  • Possible option types:

      -
    • switch_option - a simple boolean switch without arguments, -for example -O2 or -time.
      • -
    • parameter_option - option that takes one argument, for -example -std=c99. It is also allowed to use spaces instead of -the equality sign: -std c99.
      • -
    • parameter_list_option - same as the above, but more than one -option occurence is allowed.
      • -
    • prefix_option - same as the parameter_option, but the option -name and argument do not have to be separated. Example: --ofile. This can be also specified as -o file; however, --o=file will be parsed incorrectly (=file will be -interpreted as option value).
      • -
    • prefix_list_option - same as the above, but more than one -occurence of the option is allowed; example: -lm -lpthread.
      • -
    • alias_option - a special option type for creating -aliases. Unlike other option types, aliases are not allowed to -have any properties besides the aliased option name. Usage -example: (alias_option "preprocess", "E")
      • +
    • switch_option - a simple boolean switch without arguments, for example +-O2 or -time. At most one occurrence is allowed.
      • +
    • parameter_option - option that takes one argument, for example +-std=c99. It is also allowed to use spaces instead of the equality +sign: -std c99. At most one occurrence is allowed.
      • +
    • parameter_list_option - same as the above, but more than one option +occurence is allowed.
      • +
    • prefix_option - same as the parameter_option, but the option name and +argument do not have to be separated. Example: -ofile. This can be also +specified as -o file; however, -o=file will be parsed incorrectly +(=file will be interpreted as option value). At most one occurrence is +allowed.
      • +
    • prefix_list_option - same as the above, but more than one occurence of +the option is allowed; example: -lm -lpthread.
      • +
    • alias_option - a special option type for creating aliases. Unlike other +option types, aliases are not allowed to have any properties besides the +aliased option name. Usage example: (alias_option "preprocess", "E")

  • Possible option properties:

      -
    • help - help string associated with this option. Used for ---help output.
      • -
    • required - this option is obligatory.
      • +
    • help - help string associated with this option. Used for --help +output.
      • +
    • required - this option must be specified exactly once (or, in case of +the list options without the multi_val property, at least +once). Incompatible with zero_or_one and one_or_more.
      • +
    • one_or_more - the option must be specified at least one time. Useful +only for list options in conjunction with multi_val; for ordinary lists +it is synonymous with required. Incompatible with required and +zero_or_one.
      • +
    • zero_or_one - the option can be specified zero or one times. Useful +only for list options in conjunction with multi_val. Incompatible with +required and one_or_more.
    • hidden - the description of this option will not appear in the --help output (but will appear in the --help-hidden output).
    • really_hidden - the option will not be mentioned in any help output.
      • +
    • multi_val n - this option takes n arguments (can be useful in some +special cases). Usage example: (parameter_list_option "foo", (multi_val +3)). Only list options can have this attribute; you can, however, use +the one_or_more and zero_or_one properties.
    • extern - this option is defined in some other plugin, see below.
    @@ -526,16 +538,21 @@

    Hooks and environment variables

    Normally, LLVMC executes programs from the system PATH. Sometimes, -this is not sufficient: for example, we may want to specify tool names -in the configuration file. This can be achieved via the mechanism of -hooks - to write your own hooks, just add their definitions to the -PluginMain.cpp or drop a .cpp file into the -$LLVMC_DIR/driver directory. Hooks should live in the hooks -namespace and have the signature std::string hooks::MyHookName -(void). They can be used from the cmd_line tool property:

    +this is not sufficient: for example, we may want to specify tool paths +or names in the configuration file. This can be easily achieved via +the hooks mechanism. To write your own hooks, just add their +definitions to the PluginMain.cpp or drop a .cpp file into the +your plugin directory. Hooks should live in the hooks namespace +and have the signature std::string hooks::MyHookName ([const char* +Arg0 [ const char* Arg2 [, ...]]]). They can be used from the +cmd_line tool property:

     (cmd_line "$CALL(MyHook)/path/to/file -o $CALL(AnotherHook)")
    +

    To pass arguments to hooks, use the following syntax:

    +
    +(cmd_line "$CALL(MyHook, 'Arg1', 'Arg2', 'Arg # 3')/path/to/file -o1 -o2")
+

    It is also possible to use environment variables in the same manner:

     (cmd_line "$ENV(VAR1)/path/to/file -o $ENV(VAR2)")




From foldr at codedgers.com  Tue Jan 27 21:47:59 2009
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Wed, 28 Jan 2009 03:47:59 -0000
Subject: [llvm-commits] [llvm] r63174 -
	/llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp
Message-ID: <200901280347.n0S3lxOG005961@zion.cs.uiuc.edu>

Author: foldr
Date: Tue Jan 27 21:47:58 2009
New Revision: 63174

URL: http://llvm.org/viewvc/llvm-project?rev=63174&view=rev
Log:
Typo.

Modified:
    llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp

Modified: llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp?rev=63174&r1=63173&r2=63174&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Tue Jan 27 21:47:58 2009
@@ -253,7 +253,7 @@
 }
 
 bool OptionDescription::isMultiVal() const {
-  return MultiVal == 1;
+  return MultiVal > 1;
 }
 
 bool OptionDescription::isExtern() const {




From clattner at apple.com  Tue Jan 27 23:31:31 2009
From: clattner at apple.com (Chris Lattner)
Date: Tue, 27 Jan 2009 21:31:31 -0800
Subject: [llvm-commits] [llvm] r63136 -
	/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
In-Reply-To: 
References: <200901272141.n0RLf4rE022850@zion.cs.uiuc.edu>
	
	
Message-ID: 


On Jan 27, 2009, at 2:26 PM, Dale Johannesen wrote:

>
> On Jan 27, 2009, at 2:23 PMPST, Chris Lattner wrote:
>> On Jan 27, 2009, at 1:41 PM, Dale Johannesen wrote:
>>>
>>> +  /// is that they will replace the above two over time, and
>>> eventually
>>> +  /// the ones above can be removed.
>>> +  SDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, unsigned
>>> NumOps,
>>> +         DebugLoc sl)
>>
>> Do you think it would be reasonable to pass DebugLoc immediately  
>> after
>> Opc?  Since all ctor/get methods will eventually convert to passing a
>> location, it would be nice for them to be consistent.  If it is at  
>> the
>> end of the list then we have get(opcode, ...random stuff depending on
>> the accessor... , loc).  It would be nicer to have get(opcode,
>> loc, ... random stuff depending on the accessor...)
>
> OK, and now's the time to do it.

Right!

> Should be a const argument too.


That shouldn't matter since it is passed by-value.

Thanks for working on this!

-Chris



From clattner at apple.com  Tue Jan 27 23:33:52 2009
From: clattner at apple.com (Chris Lattner)
Date: Tue, 27 Jan 2009 21:33:52 -0800
Subject: [llvm-commits] [llvm] r63079 -
	/llvm/trunk/test/FrontendC/x86-64-red-zone.c
In-Reply-To: <2D79E797-703B-4DEF-809A-A2DED7F9C4D9@apple.com>
References: <200901270059.n0R0xt3h001002@zion.cs.uiuc.edu>
	<497F6608.50805@gmail.com>
	<2D79E797-703B-4DEF-809A-A2DED7F9C4D9@apple.com>
Message-ID: 


On Jan 27, 2009, at 7:04 PM, Dan Gohman wrote:

>
> On Jan 27, 2009, at 11:52 AM, T?r?k Edwin wrote:
>
>> On 2009-01-27 02:59, Dan Gohman wrote:
>>>
>>> +// This is a test for x86-64, add your target below if it FAILs.
>>> +// XFAIL: alpha|ia64|arm|powerpc|sparc|x86
>>
>> Hi Dan,
>>
>> I get an XPASS on x86_64. It appears that x86_64 == x86 for XFAIL :(
>
>
> Hrm. Anyone have any ideas how to fix this?

We don't have a good way to do llvm-gcc target-specific regtests.  I  
would just suggest removing the test as "not worth it" or choose to  
improve the test infrastructure.

-Chris


From kremenek at apple.com  Wed Jan 28 00:46:18 2009
From: kremenek at apple.com (Ted Kremenek)
Date: Wed, 28 Jan 2009 06:46:18 -0000
Subject: [llvm-commits] [llvm] r63189 - /llvm/tags/checker/checker-0.146/
Message-ID: <200901280646.n0S6kIwM012909@zion.cs.uiuc.edu>

Author: kremenek
Date: Wed Jan 28 00:46:16 2009
New Revision: 63189

URL: http://llvm.org/viewvc/llvm-project?rev=63189&view=rev
Log:
Tagging checker-0.146.

Added:
    llvm/tags/checker/checker-0.146/
      - copied from r63188, llvm/trunk/



From clattner at apple.com  Wed Jan 28 01:13:01 2009
From: clattner at apple.com (Chris Lattner)
Date: Tue, 27 Jan 2009 23:13:01 -0800
Subject: [llvm-commits] [llvm]	r62045	-
	/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
In-Reply-To: <496FB230.8070702@lip6.fr>
References: <200901112015.n0BKFLnj013960@zion.cs.uiuc.edu>
	<496E0C68.1070209@lip6.fr>
	<98B6F687-3514-4E03-B6BB-6813B2B706D8@apple.com>
	<496FB230.8070702@lip6.fr>
Message-ID: <876D467E-C3C9-4724-9853-2A93A59B0181@apple.com>


On Jan 15, 2009, at 2:01 PM, Nicolas Geoffray wrote:
>> IMO, mid-level optimizations that we want to run from "opt" or "llvm-
>> ld" should never call addRequired/
>> getAnalysis.  Instead, they should call
>> getAnalysisToUpdate().  This method returns a pointer if
>> TargetData is around, or returns null if not.  That would mean that
>> passes (like instcombine) that want to use targetdata would (for
>> xforms that need it) check to see if the pointer is non-null, then  
>> try
>> to do the xform in question.
>>
>> Does this seem reasonable?
>>
>
> Yes it does. VMKit outputs a portable .bc from Java or C#, and it's
> unfortunate opt is changing it to a non-portable .bc file.

Hi Nicolas,

Can you please summarize this discussion in a bugzilla report?  It  
would be nice to track this.  Thanks,

-Chris


From clattner at apple.com  Wed Jan 28 01:15:14 2009
From: clattner at apple.com (Chris Lattner)
Date: Tue, 27 Jan 2009 23:15:14 -0800
Subject: [llvm-commits] [llvm] r62045	-
	/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
In-Reply-To: <200901150946.33395.baldrick@free.fr>
References: <200901112015.n0BKFLnj013960@zion.cs.uiuc.edu>
	<496E0C68.1070209@lip6.fr>
	<98B6F687-3514-4E03-B6BB-6813B2B706D8@apple.com>
	<200901150946.33395.baldrick@free.fr>
Message-ID: <37D4AA39-CB8B-4477-9D4C-1F877D741620@apple.com>


On Jan 15, 2009, at 12:46 AM, Duncan Sands wrote:

> Hi Chris,
>
>> ...Instead, they should call getAnalysisToUpdate().
>
> any objection if I rename getAnalysisToUpdate to  
> getAnalysisIfAvailable?

No, please do.

-Chris


From wangmp at apple.com  Wed Jan 28 02:12:06 2009
From: wangmp at apple.com (Mon P Wang)
Date: Wed, 28 Jan 2009 08:12:06 -0000
Subject: [llvm-commits] [llvm] r63193 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <200901280812.n0S8C6Dh016402@zion.cs.uiuc.edu>

Author: wangmp
Date: Wed Jan 28 02:12:05 2009
New Revision: 63193

URL: http://llvm.org/viewvc/llvm-project?rev=63193&view=rev
Log:
Add shuffle splat pattern for x86 sse shifts.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=63193&r1=63192&r2=63193&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jan 28 02:12:05 2009
@@ -7678,28 +7678,32 @@
   if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
     return SDValue();
     
-  SDValue  ShAmtOp = N->getOperand(1);
-  if (ShAmtOp.getOpcode() != ISD::BUILD_VECTOR)
-    return SDValue();
-
-  unsigned NumElts = VT.getVectorNumElements();
-  unsigned i = 0;
+  SDValue ShAmtOp = N->getOperand(1);
+  MVT EltVT = VT.getVectorElementType();
   SDValue BaseShAmt;
-  for (; i != NumElts; ++i) {
-    SDValue Arg = ShAmtOp.getOperand(i);
-    if (Arg.getOpcode() == ISD::UNDEF) continue;
-    BaseShAmt = Arg;
-    break;
-  }
-  for (; i != NumElts; ++i) {
-    SDValue Arg = ShAmtOp.getOperand(i);
-    if (Arg.getOpcode() == ISD::UNDEF) continue;
-    if (Arg != BaseShAmt) {
-      return SDValue();
+  if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
+    unsigned NumElts = VT.getVectorNumElements();
+    unsigned i = 0;
+    for (; i != NumElts; ++i) {
+      SDValue Arg = ShAmtOp.getOperand(i);
+      if (Arg.getOpcode() == ISD::UNDEF) continue;
+      BaseShAmt = Arg;
+      break;
     }
-  }
+    for (; i != NumElts; ++i) {
+      SDValue Arg = ShAmtOp.getOperand(i);
+      if (Arg.getOpcode() == ISD::UNDEF) continue;
+      if (Arg != BaseShAmt) {
+        return SDValue();
+      }
+    }
+  } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
+             isSplatMask(ShAmtOp.getOperand(2).getNode())) {
+      BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, ShAmtOp,
+                              DAG.getIntPtrConstant(0));
+  } else
+    return SDValue();
 
-  MVT EltVT = VT.getVectorElementType();
   if (EltVT.bitsGT(MVT::i32))
     BaseShAmt = DAG.getNode(ISD::TRUNCATE, MVT::i32, BaseShAmt);
   else if (EltVT.bitsLT(MVT::i32))




From wangmp at apple.com  Wed Jan 28 02:13:57 2009
From: wangmp at apple.com (Mon P Wang)
Date: Wed, 28 Jan 2009 08:13:57 -0000
Subject: [llvm-commits] [llvm] r63194 - in /llvm/trunk/test/CodeGen/X86:
 vshift-1.ll vshift-2.ll vshift-3.ll vshift-4.ll
Message-ID: <200901280813.n0S8DvtA016464@zion.cs.uiuc.edu>

Author: wangmp
Date: Wed Jan 28 02:13:56 2009
New Revision: 63194

URL: http://llvm.org/viewvc/llvm-project?rev=63194&view=rev
Log:
Added sse test patterns for r62979 and r63193.

Added:
    llvm/trunk/test/CodeGen/X86/vshift-1.ll
    llvm/trunk/test/CodeGen/X86/vshift-2.ll
    llvm/trunk/test/CodeGen/X86/vshift-3.ll
    llvm/trunk/test/CodeGen/X86/vshift-4.ll

Added: llvm/trunk/test/CodeGen/X86/vshift-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vshift-1.ll?rev=63194&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/vshift-1.ll (added)
+++ llvm/trunk/test/CodeGen/X86/vshift-1.ll Wed Jan 28 02:13:56 2009
@@ -0,0 +1,65 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -disable-mmx -o %t -f
+; RUN: grep psllq  %t | count 2
+; RUN: grep pslld %t | count 2
+; RUN: grep psllw %t | count 2
+
+; test vector shifts converted to proper SSE2 vector shifts when the shift
+; amounts are the same.
+
+define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
+entry:
+  %shl = shl <2 x i64> %val, < i64 32, i64 32 >
+  store <2 x i64> %shl, <2 x i64>* %dst
+  ret void
+}
+
+define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
+entry:
+  %0 = insertelement <2 x i64> undef, i64 %amt, i32 0
+  %1 = insertelement <2 x i64> %0, i64 %amt, i32 1
+  %shl = shl <2 x i64> %val, %1
+  store <2 x i64> %shl, <2 x i64>* %dst
+  ret void
+}
+
+
+define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
+entry:
+  %shl = shl <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
+  store <4 x i32> %shl, <4 x i32>* %dst
+  ret void
+}
+
+define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
+entry:
+  %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
+  %1 = insertelement <4 x i32> %0, i32 %amt, i32 1
+  %2 = insertelement <4 x i32> %1, i32 %amt, i32 2
+  %3 = insertelement <4 x i32> %2, i32 %amt, i32 3
+  %shl = shl <4 x i32> %val, %3
+  store <4 x i32> %shl, <4 x i32>* %dst
+  ret void
+}
+
+define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
+entry:
+  %shl = shl <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
+  store <8 x i16> %shl, <8 x i16>* %dst
+  ret void
+}
+
+define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
+entry:
+  %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
+  %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
+  %2 = insertelement <8 x i16> %0, i16 %amt, i32 2
+  %3 = insertelement <8 x i16> %0, i16 %amt, i32 3
+  %4 = insertelement <8 x i16> %0, i16 %amt, i32 4
+  %5 = insertelement <8 x i16> %0, i16 %amt, i32 5
+  %6 = insertelement <8 x i16> %0, i16 %amt, i32 6
+  %7 = insertelement <8 x i16> %0, i16 %amt, i32 7
+  %shl = shl <8 x i16> %val, %7
+  store <8 x i16> %shl, <8 x i16>* %dst
+  ret void
+}
+

Added: llvm/trunk/test/CodeGen/X86/vshift-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vshift-2.ll?rev=63194&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/vshift-2.ll (added)
+++ llvm/trunk/test/CodeGen/X86/vshift-2.ll Wed Jan 28 02:13:56 2009
@@ -0,0 +1,64 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -disable-mmx -o %t -f
+; RUN: grep psrlq  %t | count 2
+; RUN: grep psrld %t | count 2
+; RUN: grep psrlw %t | count 2
+
+; test vector shifts converted to proper SSE2 vector shifts when the shift
+; amounts are the same.
+
+define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
+entry:
+  %lshr = lshr <2 x i64> %val, < i64 32, i64 32 >
+  store <2 x i64> %lshr, <2 x i64>* %dst
+  ret void
+}
+
+define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
+entry:
+  %0 = insertelement <2 x i64> undef, i64 %amt, i32 0
+  %1 = insertelement <2 x i64> %0, i64 %amt, i32 1
+  %lshr = lshr <2 x i64> %val, %1
+  store <2 x i64> %lshr, <2 x i64>* %dst
+  ret void
+}
+
+define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
+entry:
+  %lshr = lshr <4 x i32> %val, < i32 17, i32 17, i32 17, i32 17 >
+  store <4 x i32> %lshr, <4 x i32>* %dst
+  ret void
+}
+
+define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
+entry:
+  %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
+  %1 = insertelement <4 x i32> %0, i32 %amt, i32 1
+  %2 = insertelement <4 x i32> %1, i32 %amt, i32 2
+  %3 = insertelement <4 x i32> %2, i32 %amt, i32 3
+  %lshr = lshr <4 x i32> %val, %3
+  store <4 x i32> %lshr, <4 x i32>* %dst
+  ret void
+}
+
+
+define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
+entry:
+  %lshr = lshr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
+  store <8 x i16> %lshr, <8 x i16>* %dst
+  ret void
+}
+
+define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
+entry:
+  %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
+  %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
+  %2 = insertelement <8 x i16> %0, i16 %amt, i32 2
+  %3 = insertelement <8 x i16> %0, i16 %amt, i32 3
+  %4 = insertelement <8 x i16> %0, i16 %amt, i32 4
+  %5 = insertelement <8 x i16> %0, i16 %amt, i32 5
+  %6 = insertelement <8 x i16> %0, i16 %amt, i32 6
+  %7 = insertelement <8 x i16> %0, i16 %amt, i32 7
+  %lshr = lshr <8 x i16> %val, %7
+  store <8 x i16> %lshr, <8 x i16>* %dst
+  ret void
+}
\ No newline at end of file

Added: llvm/trunk/test/CodeGen/X86/vshift-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vshift-3.ll?rev=63194&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/vshift-3.ll (added)
+++ llvm/trunk/test/CodeGen/X86/vshift-3.ll Wed Jan 28 02:13:56 2009
@@ -0,0 +1,54 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -disable-mmx -o %t -f
+; RUN: grep psrad %t | count 2
+; RUN: grep psraw %t | count 2
+
+; test vector shifts converted to proper SSE2 vector shifts when the shift
+; amounts are the same.
+
+; Note that x86 does have ashr 
+define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
+entry:
+  %ashr = ashr <2 x i64> %val, < i64 32, i64 32 >
+  store <2 x i64> %ashr, <2 x i64>* %dst
+  ret void
+}
+
+define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
+entry:
+  %ashr = ashr <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
+  store <4 x i32> %ashr, <4 x i32>* %dst
+  ret void
+}
+
+define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
+entry:
+  %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
+  %1 = insertelement <4 x i32> %0, i32 %amt, i32 1
+  %2 = insertelement <4 x i32> %1, i32 %amt, i32 2
+  %3 = insertelement <4 x i32> %2, i32 %amt, i32 3
+  %ashr = ashr <4 x i32> %val, %3
+  store <4 x i32> %ashr, <4 x i32>* %dst
+  ret void
+}
+
+define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
+entry:
+  %ashr = ashr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
+  store <8 x i16> %ashr, <8 x i16>* %dst
+  ret void
+}
+
+define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
+entry:
+  %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
+  %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
+  %2 = insertelement <8 x i16> %0, i16 %amt, i32 2
+  %3 = insertelement <8 x i16> %0, i16 %amt, i32 3
+  %4 = insertelement <8 x i16> %0, i16 %amt, i32 4
+  %5 = insertelement <8 x i16> %0, i16 %amt, i32 5
+  %6 = insertelement <8 x i16> %0, i16 %amt, i32 6
+  %7 = insertelement <8 x i16> %0, i16 %amt, i32 7
+  %ashr = ashr <8 x i16> %val, %7
+  store <8 x i16> %ashr, <8 x i16>* %dst
+  ret void
+}
\ No newline at end of file

Added: llvm/trunk/test/CodeGen/X86/vshift-4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vshift-4.ll?rev=63194&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/vshift-4.ll (added)
+++ llvm/trunk/test/CodeGen/X86/vshift-4.ll Wed Jan 28 02:13:56 2009
@@ -0,0 +1,71 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -disable-mmx -o %t -f
+; RUN: grep psllq %t | count 1
+; RUN: grep pslld %t | count 3
+; RUN: grep psllw %t | count 2
+
+; test vector shifts converted to proper SSE2 vector shifts when the shift
+; amounts are the same when using a shuffle splat.
+
+define void @shift1a(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
+entry:
+  %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> 
+  %shl = shl <2 x i64> %val, %shamt
+  store <2 x i64> %shl, <2 x i64>* %dst
+  ret void
+}
+
+define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
+entry:
+  %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> 
+  %shl = shl <2 x i64> %val, %shamt
+  store <2 x i64> %shl, <2 x i64>* %dst
+  ret void
+}
+
+define void @shift2a(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
+entry:
+  %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> 
+  %shl = shl <4 x i32> %val, %shamt
+  store <4 x i32> %shl, <4 x i32>* %dst
+  ret void
+}
+
+define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
+entry:
+  %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> 
+  %shl = shl <4 x i32> %val, %shamt
+  store <4 x i32> %shl, <4 x i32>* %dst
+  ret void
+}
+
+define void @shift2c(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
+entry:
+  %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> 
+  %shl = shl <4 x i32> %val, %shamt
+  store <4 x i32> %shl, <4 x i32>* %dst
+  ret void
+}
+
+define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind {
+entry:
+  %shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> 
+  %shl = shl <8 x i16> %val, %shamt
+  store <8 x i16> %shl, <8 x i16>* %dst
+  ret void
+}
+
+define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
+entry:
+  %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
+  %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
+  %2 = insertelement <8 x i16> %0, i16 %amt, i32 2
+  %3 = insertelement <8 x i16> %0, i16 %amt, i32 3
+  %4 = insertelement <8 x i16> %0, i16 %amt, i32 4
+  %5 = insertelement <8 x i16> %0, i16 %amt, i32 5
+  %6 = insertelement <8 x i16> %0, i16 %amt, i32 6
+  %7 = insertelement <8 x i16> %0, i16 %amt, i32 7
+  %shl = shl <8 x i16> %val, %7
+  store <8 x i16> %shl, <8 x i16>* %dst
+  ret void
+}
+




From evan.cheng at apple.com  Wed Jan 28 02:35:06 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 28 Jan 2009 08:35:06 -0000
Subject: [llvm-commits] [llvm] r63195 - in /llvm/trunk:
 lib/Target/X86/README-SSE.txt lib/Target/X86/X86InstrSSE.td
 test/CodeGen/X86/swizzle.ll
Message-ID: <200901280835.n0S8Z6T2017730@zion.cs.uiuc.edu>

Author: evancheng
Date: Wed Jan 28 02:35:02 2009
New Revision: 63195

URL: http://llvm.org/viewvc/llvm-project?rev=63195&view=rev
Log:
The memory alignment requirement on some of the mov{h|l}p{d|s} patterns are 16-byte. That is overly strict. These instructions read / write f64 memory locations without alignment requirement.

Added:
    llvm/trunk/test/CodeGen/X86/swizzle.ll
Modified:
    llvm/trunk/lib/Target/X86/README-SSE.txt
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/README-SSE.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-SSE.txt?rev=63195&r1=63194&r2=63195&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/README-SSE.txt (original)
+++ llvm/trunk/lib/Target/X86/README-SSE.txt Wed Jan 28 02:35:02 2009
@@ -907,3 +907,8 @@
   cvtsi2ss 8($esp), %xmm0
 since we know the stack slot is already zext'd.
 
+//===---------------------------------------------------------------------===//
+
+Consider using movlps instead of movsd to implement (scalar_to_vector (loadf64))
+when code size is critical. movlps is slower than movsd on core2 but it's one
+byte shorter.

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=63195&r1=63194&r2=63195&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jan 28 02:35:02 2009
@@ -3019,62 +3019,60 @@
 let AddedComplexity = 20 in {
 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
-def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
+def : Pat<(v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
                   MOVLP_shuffle_mask)),
           (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
-def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
+def : Pat<(v2f64 (vector_shuffle VR128:$src1, (load addr:$src2),
                   MOVLP_shuffle_mask)),
           (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
-def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
+def : Pat<(v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
                   MOVHP_shuffle_mask)),
           (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
-def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
+def : Pat<(v2f64 (vector_shuffle VR128:$src1, (load addr:$src2),
                   MOVHP_shuffle_mask)),
           (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
 
-def : Pat<(v4i32 (vector_shuffle VR128:$src1,
-                                 (bc_v4i32 (memopv2i64 addr:$src2)),
+def : Pat<(v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
                   MOVLP_shuffle_mask)),
           (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
-def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
+def : Pat<(v2i64 (vector_shuffle VR128:$src1, (load addr:$src2),
                   MOVLP_shuffle_mask)),
           (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
-def : Pat<(v4i32 (vector_shuffle VR128:$src1,
-                                 (bc_v4i32 (memopv2i64 addr:$src2)),
+def : Pat<(v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
                   MOVHP_shuffle_mask)),
           (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
-def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
+def : Pat<(v2i64 (vector_shuffle VR128:$src1, (load addr:$src2),
                   MOVHP_shuffle_mask)),
           (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
 }
 
 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
 // (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS
-def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
+def : Pat<(store (v4f32 (vector_shuffle (load addr:$src1), VR128:$src2,
                          MOVLP_shuffle_mask)), addr:$src1),
           (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
-def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
+def : Pat<(store (v2f64 (vector_shuffle (load addr:$src1), VR128:$src2,
                          MOVLP_shuffle_mask)), addr:$src1),
           (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
-def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
+def : Pat<(store (v4f32 (vector_shuffle (load addr:$src1), VR128:$src2,
                          MOVHP_shuffle_mask)), addr:$src1),
           (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
-def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
+def : Pat<(store (v2f64 (vector_shuffle (load addr:$src1), VR128:$src2,
                          MOVHP_shuffle_mask)), addr:$src1),
           (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
 
 def : Pat<(store (v4i32 (vector_shuffle
-                         (bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
+                         (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2,
                          MOVLP_shuffle_mask)), addr:$src1),
           (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
-def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
+def : Pat<(store (v2i64 (vector_shuffle (load addr:$src1), VR128:$src2,
                          MOVLP_shuffle_mask)), addr:$src1),
           (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
 def : Pat<(store (v4i32 (vector_shuffle
-                         (bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
+                         (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2,
                          MOVHP_shuffle_mask)), addr:$src1),
           (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
-def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
+def : Pat<(store (v2i64 (vector_shuffle (load addr:$src1), VR128:$src2,
                          MOVHP_shuffle_mask)), addr:$src1),
           (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
 

Added: llvm/trunk/test/CodeGen/X86/swizzle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/swizzle.ll?rev=63195&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/swizzle.ll (added)
+++ llvm/trunk/test/CodeGen/X86/swizzle.ll Wed Jan 28 02:35:02 2009
@@ -0,0 +1,19 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movlps
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movsd
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep movups
+; rdar://6523650
+
+	%struct.vector4_t = type { <4 x float> }
+
+define void @swizzle(i8* nocapture %a, %struct.vector4_t* nocapture %b, %struct.vector4_t* nocapture %c) nounwind {
+entry:
+	%0 = getelementptr %struct.vector4_t* %b, i32 0, i32 0		; <<4 x float>*> [#uses=2]
+	%1 = load <4 x float>* %0, align 4		; <<4 x float>> [#uses=1]
+	%tmp.i = bitcast i8* %a to double*		;  [#uses=1]
+	%tmp1.i = load double* %tmp.i		;  [#uses=1]
+	%2 = insertelement <2 x double> undef, double %tmp1.i, i32 0		; <<2 x double>> [#uses=1]
+	%tmp2.i = bitcast <2 x double> %2 to <4 x float>		; <<4 x float>> [#uses=1]
+	%3 = shufflevector <4 x float> %1, <4 x float> %tmp2.i, <4 x i32> < i32 4, i32 5, i32 2, i32 3 >		; <<4 x float>> [#uses=1]
+	store <4 x float> %3, <4 x float>* %0, align 4
+	ret void
+}




From wangmp at apple.com  Wed Jan 28 02:41:58 2009
From: wangmp at apple.com (Mon Ping Wang)
Date: Wed, 28 Jan 2009 00:41:58 -0800
Subject: [llvm-commits] extract vector legalize type patch
Message-ID: <6F1270EE-2D85-42DD-B407-84CF6A3AA5D0@apple.com>

Hi,

This patch is to fixed the following problem.  Consider the following  
code for an architecture where i8 is not a legal type but a vector <4  
x i8) is.
       %shuf = shufflevector <4 x i8> %val1, <4 x i8> undef, <3 x i32>  
; yields <3 x i8>
       %res =  extractelement <3 x i8> %shuf, i32 1;

The shuffle vector will be widen to a 4xi8.  In the extract element,  
we need to promote the i8 to i32 but it uses %shuf instead of the  
widen version of %shuf.  This patch check if the action for the input  
is to widen and if so, uses the widen value.

-- Mon Ping

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From baldrick at free.fr  Wed Jan 28 03:23:43 2009
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 28 Jan 2009 10:23:43 +0100
Subject: [llvm-commits] extract vector legalize type patch
In-Reply-To: <6F1270EE-2D85-42DD-B407-84CF6A3AA5D0@apple.com>
References: <6F1270EE-2D85-42DD-B407-84CF6A3AA5D0@apple.com>
Message-ID: <200901281023.43171.baldrick@free.fr>

Hi Mon Ping, this is OK.

Thanks for fixing it,

Duncan.


From Sanjiv.Gupta at microchip.com  Wed Jan 28 04:13:19 2009
From: Sanjiv.Gupta at microchip.com (Sanjiv.Gupta at microchip.com)
Date: Wed, 28 Jan 2009 03:13:19 -0700
Subject: [llvm-commits] AsmPrinter Patch: handle emitting of constants in
	non-default address space.
Message-ID: 

AsmPrinter currently handles emitting the constants only in the default
data space.

The attached patch enhances those APIs to take address space attribute
and allow emitting of constants in the specified address space.

Please let me know your comments on the same.

 

- Sanjiv

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From baldrick at free.fr  Wed Jan 28 05:34:21 2009
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 28 Jan 2009 11:34:21 -0000
Subject: [llvm-commits] [llvm] r63197 - in /llvm/trunk:
 include/llvm/Analysis/EscapeAnalysis.h include/llvm/LinkAllPasses.h
 lib/Analysis/CMakeLists.txt lib/Analysis/EscapeAnalysis.cpp
 win32/Analysis/Analysis.vcproj
Message-ID: <200901281134.n0SBYQFE001862@zion.cs.uiuc.edu>

Author: baldrick
Date: Wed Jan 28 05:33:59 2009
New Revision: 63197

URL: http://llvm.org/viewvc/llvm-project?rev=63197&view=rev
Log:
Fix PR3415 (infinite loop in EscapeAnalysis) by
deleting the escape analysis pass.

Removed:
    llvm/trunk/include/llvm/Analysis/EscapeAnalysis.h
    llvm/trunk/lib/Analysis/EscapeAnalysis.cpp
Modified:
    llvm/trunk/include/llvm/LinkAllPasses.h
    llvm/trunk/lib/Analysis/CMakeLists.txt
    llvm/trunk/win32/Analysis/Analysis.vcproj

Removed: llvm/trunk/include/llvm/Analysis/EscapeAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/EscapeAnalysis.h?rev=63196&view=auto

==============================================================================
--- llvm/trunk/include/llvm/Analysis/EscapeAnalysis.h (original)
+++ llvm/trunk/include/llvm/Analysis/EscapeAnalysis.h (removed)
@@ -1,55 +0,0 @@
-//===------------- EscapeAnalysis.h - Pointer escape analysis -------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines the interface for the pointer escape analysis.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_ANALYSIS_ESCAPEANALYSIS_H
-#define LLVM_ANALYSIS_ESCAPEANALYSIS_H
-
-#include "llvm/Pass.h"
-#include 
-
-namespace llvm {
-
-class Instruction;
-class Value;
-
-/// EscapeAnalysis - This class determines whether an allocation (a MallocInst 
-/// or an AllocaInst) can escape from the current function.  It performs some
-/// precomputation, with the rest of the work happening on-demand.
-class EscapeAnalysis : public FunctionPass {
-private:
-  std::set EscapePoints;
-
-public:
-  static char ID; // Class identification, replacement for typeinfo
-
-  EscapeAnalysis() : FunctionPass(intptr_t(&ID)) {}
-
-  bool runOnFunction(Function &F);
-  
-  void releaseMemory() {
-    EscapePoints.clear();
-  }
-
-  void getAnalysisUsage(AnalysisUsage &AU) const;
-
-  //===---------------------------------------------------------------------
-  // Client API
-
-  /// escapes - returns true if the value, which must have a pointer type,
-  /// can escape.
-  bool escapes(Value* A);
-};
-
-} // end llvm namespace
-
-#endif

Modified: llvm/trunk/include/llvm/LinkAllPasses.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=63197&r1=63196&r2=63197&view=diff

==============================================================================
--- llvm/trunk/include/llvm/LinkAllPasses.h (original)
+++ llvm/trunk/include/llvm/LinkAllPasses.h Wed Jan 28 05:33:59 2009
@@ -16,7 +16,6 @@
 #define LLVM_LINKALLPASSES_H
 
 #include "llvm/Analysis/AliasSetTracker.h"
-#include "llvm/Analysis/EscapeAnalysis.h"
 #include "llvm/Analysis/FindUsedTypes.h"
 #include "llvm/Analysis/IntervalPartition.h"
 #include "llvm/Analysis/LoopVR.h"
@@ -132,7 +131,6 @@
       (void)new llvm::FindUsedTypes();
       (void)new llvm::ScalarEvolution();
       (void)new llvm::LoopVR();
-      (void)new llvm::EscapeAnalysis();
       ((llvm::Function*)0)->viewCFGOnly();
       llvm::AliasSetTracker X(*(llvm::AliasAnalysis*)0);
       X.add((llvm::Value*)0, 0);  // for -print-alias-sets

Modified: llvm/trunk/lib/Analysis/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CMakeLists.txt?rev=63197&r1=63196&r2=63197&view=diff

==============================================================================
--- llvm/trunk/lib/Analysis/CMakeLists.txt (original)
+++ llvm/trunk/lib/Analysis/CMakeLists.txt Wed Jan 28 05:33:59 2009
@@ -11,7 +11,6 @@
   ConstantFolding.cpp
   DbgInfoPrinter.cpp
   DebugInfo.cpp
-  EscapeAnalysis.cpp
   InstCount.cpp
   Interval.cpp
   IntervalPartition.cpp

Removed: llvm/trunk/lib/Analysis/EscapeAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/EscapeAnalysis.cpp?rev=63196&view=auto

==============================================================================
--- llvm/trunk/lib/Analysis/EscapeAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/EscapeAnalysis.cpp (removed)
@@ -1,158 +0,0 @@
-//===------------- EscapeAnalysis.h - Pointer escape analysis -------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file provides the implementation of the pointer escape analysis.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "escape-analysis"
-#include "llvm/Analysis/EscapeAnalysis.h"
-#include "llvm/Constants.h"
-#include "llvm/Instructions.h"
-#include "llvm/Module.h"
-#include "llvm/Analysis/AliasAnalysis.h"
-#include "llvm/Support/InstIterator.h"
-#include "llvm/Target/TargetData.h"
-#include "llvm/ADT/SmallPtrSet.h"
-#include 
-using namespace llvm;
-
-char EscapeAnalysis::ID = 0;
-static RegisterPass X("escape-analysis",
-                                      "Pointer Escape Analysis", true, true);
-
-
-void EscapeAnalysis::getAnalysisUsage(AnalysisUsage &AU) const {
-  AU.addRequiredTransitive();
-  AU.addRequiredTransitive();
-  AU.setPreservesAll();
-}
-
-/// runOnFunction - Precomputation for escape analysis.  This collects all know
-/// "escape points" in the def-use graph of the function.  These are 
-/// instructions which allow their inputs to escape from the current function.  
-bool EscapeAnalysis::runOnFunction(Function& F) {
-  EscapePoints.clear();
-  
-  TargetData& TD = getAnalysis();
-  AliasAnalysis& AA = getAnalysis();
-  Module* M = F.getParent();
-  
-  // Walk through all instructions in the function, identifying those that
-  // may allow their inputs to escape.
-  for(inst_iterator II = inst_begin(F), IE = inst_end(F); II != IE; ++II) {
-    Instruction* I = &*II;
-    
-    // The most obvious case is stores.  Any store that may write to global
-    // memory or to a function argument potentially allows its input to escape.
-    if (StoreInst* S = dyn_cast(I)) {
-      const Type* StoreType = S->getOperand(0)->getType();
-      unsigned StoreSize = TD.getTypeStoreSize(StoreType);
-      Value* Pointer = S->getPointerOperand();
-      
-      bool inserted = false;
-      for (Function::arg_iterator AI = F.arg_begin(), AE = F.arg_end();
-           AI != AE; ++AI) {
-        if (!isa(AI->getType())) continue;
-        AliasAnalysis::AliasResult R = AA.alias(Pointer, StoreSize, AI, ~0U);
-        if (R != AliasAnalysis::NoAlias) {
-          EscapePoints.insert(S);
-          inserted = true;
-          break;
-        }
-      }
-      
-      if (inserted)
-        continue;
-      
-      for (Module::global_iterator GI = M->global_begin(), GE = M->global_end();
-           GI != GE; ++GI) {
-        AliasAnalysis::AliasResult R = AA.alias(Pointer, StoreSize, GI, ~0U);
-        if (R != AliasAnalysis::NoAlias) {
-          EscapePoints.insert(S);
-          break;
-        }
-      }
-    
-    // Calls and invokes potentially allow their parameters to escape.
-    // FIXME: This can and should be refined.  Intrinsics have known escape
-    // behavior, and alias analysis may be able to tell us more about callees.
-    } else if (isa(I) || isa(I)) {
-      EscapePoints.insert(I);
-    
-    // Returns allow the return value to escape.  This is mostly important
-    // for malloc to alloca promotion.
-    } else if (isa(I)) {
-      EscapePoints.insert(I);
-    
-    // Branching on the value of a pointer may allow the value to escape through
-    // methods not discoverable via def-use chaining.
-    } else if(isa(I) || isa(I)) {
-      EscapePoints.insert(I);
-    }
-    
-    // FIXME: Are there any other possible escape points?
-  }
-  
-  return false;
-}
-
-/// escapes - Determines whether the passed allocation can escape from the 
-/// current function.  It does this by using a simple worklist algorithm to
-/// search for a path in the def-use graph from the allocation to an
-/// escape point.
-/// FIXME: Once we've discovered a path, it would be a good idea to memoize it,
-/// and all of its subpaths, to amortize the cost of future queries.
-bool EscapeAnalysis::escapes(Value* A) {
-  assert(isa(A->getType()) && 
-         "Can't do escape analysis on non-pointer types!");
-  
-  std::vector worklist;
-  worklist.push_back(A);
-  
-  SmallPtrSet visited;
-  visited.insert(A);
-  while (!worklist.empty()) {
-    Value* curr = worklist.back();
-    worklist.pop_back();
-    
-    if (Instruction* I = dyn_cast(curr))
-      if (EscapePoints.count(I)) {
-        BranchInst* B = dyn_cast(I);
-        if (!B) return true;
-        Value* condition = B->getCondition();
-        ICmpInst* C = dyn_cast(condition);
-        if (!C) return true;
-        Value* O1 = C->getOperand(0);
-        Value* O2 = C->getOperand(1);
-        if (isa(O1->stripPointerCasts())) {
-          if (!isa(O2)) return true;
-        } else if(isa(O2->stripPointerCasts())) {
-          if (!isa(O1)) return true;
-        } else
-          return true;
-      }
-    
-    if (StoreInst* S = dyn_cast(curr)) {
-      // We know this must be an instruction, because constant gep's would
-      // have been found to alias a global, so stores to them would have
-      // been in EscapePoints.
-      if (visited.insert(cast(S->getPointerOperand())))
-        worklist.push_back(cast(S->getPointerOperand()));
-    } else {
-      for (Instruction::use_iterator UI = curr->use_begin(),
-           UE = curr->use_end(); UI != UE; ++UI)
-        if (Instruction* U = dyn_cast(UI))
-          if (visited.insert(U))
-            worklist.push_back(U);
-    }
-  }
-  
-  return false;
-}

Modified: llvm/trunk/win32/Analysis/Analysis.vcproj
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/win32/Analysis/Analysis.vcproj?rev=63197&r1=63196&r2=63197&view=diff

==============================================================================
--- llvm/trunk/win32/Analysis/Analysis.vcproj (original)
+++ llvm/trunk/win32/Analysis/Analysis.vcproj Wed Jan 28 05:33:59 2009
@@ -349,10 +349,6 @@
 				>
 			
 			
-			
-			
 			




From baldrick at free.fr  Wed Jan 28 07:14:30 2009
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 28 Jan 2009 13:14:30 -0000
Subject: [llvm-commits] [llvm] r63198 - in /llvm/trunk: docs/ include/llvm/
 lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/
 lib/Target/ARM/AsmPrinter/ lib/Target/CellSPU/AsmPrinter/
 lib/Target/PowerPC/AsmPrinter/ lib/Target/X86/AsmPrinter/ lib/Target/XCore/
 lib/Transforms/IPO/ lib/Transforms/Scalar/ lib/Transforms/Utils/
 lib/VMCore/
Message-ID: <200901281314.n0SDEo7q005443@zion.cs.uiuc.edu>

Author: baldrick
Date: Wed Jan 28 07:14:17 2009
New Revision: 63198

URL: http://llvm.org/viewvc/llvm-project?rev=63198&view=rev
Log:
Rename getAnalysisToUpdate to getAnalysisIfAvailable.

Modified:
    llvm/trunk/docs/CompilerDriver.html
    llvm/trunk/docs/WritingAnLLVMPass.html
    llvm/trunk/include/llvm/Pass.h
    llvm/trunk/include/llvm/PassAnalysisSupport.h
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    llvm/trunk/lib/CodeGen/BranchFolding.cpp
    llvm/trunk/lib/CodeGen/GCMetadata.cpp
    llvm/trunk/lib/CodeGen/GCStrategy.cpp
    llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp
    llvm/trunk/lib/CodeGen/PHIElimination.cpp
    llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
    llvm/trunk/lib/CodeGen/UnreachableBlockElim.cpp
    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
    llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
    llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
    llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
    llvm/trunk/lib/Transforms/IPO/Internalize.cpp
    llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp
    llvm/trunk/lib/Transforms/Scalar/LoopUnroll.cpp
    llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
    llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
    llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
    llvm/trunk/lib/Transforms/Utils/CloneLoop.cpp
    llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp
    llvm/trunk/lib/VMCore/Pass.cpp
    llvm/trunk/lib/VMCore/PassManager.cpp

Modified: llvm/trunk/docs/CompilerDriver.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CompilerDriver.html?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/docs/CompilerDriver.html (original)
+++ llvm/trunk/docs/CompilerDriver.html Wed Jan 28 07:14:17 2009
@@ -611,7 +611,7 @@
 Mikhail Glushenkov
    
 LLVM Compiler Infrastructure
    
 
-Last modified: $Date: 2008-12-11 11:34:48 -0600 (Thu, 11 Dec 2008) $
+Last modified: $Date$
    Modified: llvm/trunk/docs/WritingAnLLVMPass.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/WritingAnLLVMPass.html?rev=63198&r1=63197&r2=63198&view=diff ============================================================================== --- llvm/trunk/docs/WritingAnLLVMPass.html (original) +++ llvm/trunk/docs/WritingAnLLVMPass.html Wed Jan 28 07:14:17 2009 @@ -78,7 +78,8 @@
  • The AnalysisUsage::addRequired<> and AnalysisUsage::addRequiredTransitive<> methods
  • The AnalysisUsage::addPreserved<> method
  • Example implementations of getAnalysisUsage
    • -
  • The getAnalysis<> and getAnalysisToUpdate<> methods
    • +
  • The getAnalysis<> and +getAnalysisIfAvailable<> methods
  • Implementing Analysis Groups
      @@ -1131,7 +1132,8 @@
      - The getAnalysis<> and getAnalysisToUpdate<> methods + The getAnalysis<> and +getAnalysisIfAvailable<> methods
      @@ -1173,12 +1175,12 @@

      If your pass is capable of updating analyses if they exist (e.g., BreakCriticalEdges, as described above), you can use the -getAnalysisToUpdate method, which returns a pointer to the analysis if -it is active. For example:

      +getAnalysisIfAvailable method, which returns a pointer to the analysis +if it is active. For example:

         ...
-  if (DominatorSet *DS = getAnalysisToUpdate<DominatorSet>()) {
+  if (DominatorSet *DS = getAnalysisIfAvailable<DominatorSet>()) {
     // A DominatorSet is active.  This code will update it.
   }
   ...

Modified: llvm/trunk/include/llvm/Pass.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Pass.h?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Pass.h (original)
+++ llvm/trunk/include/llvm/Pass.h Wed Jan 28 07:14:17 2009
@@ -169,22 +169,22 @@
   // or null if it is not known.
   static const PassInfo *lookupPassInfo(intptr_t TI);
 
-  /// getAnalysisToUpdate() - This function is used by subclasses
-  /// to get to the analysis information that might be around that needs to be
-  /// updated.  This is different than getAnalysis in that it can fail (ie the
-  /// analysis results haven't been computed), so should only be used if you
-  /// provide the capability to update an analysis that exists.  This method is
-  /// often used by transformation APIs to update analysis results for a pass
-  /// automatically as the transform is performed.
+  /// getAnalysisIfAvailable() - Subclasses use this function to
+  /// get analysis information that might be around, for example to update it.
+  /// This is different than getAnalysis in that it can fail (if the analysis
+  /// results haven't been computed), so should only be used if you can handle
+  /// the case when the analysis is not available.  This method is often used by
+  /// transformation APIs to update analysis results for a pass automatically as
+  /// the transform is performed.
   ///
-  template
-  AnalysisType *getAnalysisToUpdate() const; // Defined in PassAnalysisSupport.h
+  template AnalysisType *
+    getAnalysisIfAvailable() const; // Defined in PassAnalysisSupport.h
 
   /// mustPreserveAnalysisID - This method serves the same function as
-  /// getAnalysisToUpdate, but works if you just have an AnalysisID.  This
+  /// getAnalysisIfAvailable, but works if you just have an AnalysisID.  This
   /// obviously cannot give you a properly typed instance of the class if you
-  /// don't have the class name available (use getAnalysisToUpdate if you do),
-  /// but it can tell you if you need to preserve the pass at least.
+  /// don't have the class name available (use getAnalysisIfAvailable if you
+  /// do), but it can tell you if you need to preserve the pass at least.
   ///
   bool mustPreserveAnalysisID(const PassInfo *AnalysisID) const;
 

Modified: llvm/trunk/include/llvm/PassAnalysisSupport.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassAnalysisSupport.h?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/include/llvm/PassAnalysisSupport.h (original)
+++ llvm/trunk/include/llvm/PassAnalysisSupport.h Wed Jan 28 07:14:17 2009
@@ -143,8 +143,8 @@
     AnalysisImpls.push_back(pir);
   }
 
-  // getAnalysisToUpdate - Return an analysis result or null if it doesn't exist
-  Pass *getAnalysisToUpdate(AnalysisID ID, bool Direction) const;
+  // getAnalysisIfAvailable - Return analysis result or null if it doesn't exist
+  Pass *getAnalysisIfAvailable(AnalysisID ID, bool Direction) const;
 
   // AnalysisImpls - This keeps track of which passes implements the interfaces
   // that are required by the current pass (to implement getAnalysis()).
@@ -157,22 +157,22 @@
   PMDataManager &PM;
 };
 
-/// getAnalysisToUpdate() - This function is used by subclasses
-/// to get to the analysis information that might be around that needs to be
-/// updated.  This is different than getAnalysis in that it can fail (ie the
-/// analysis results haven't been computed), so should only be used if you
-/// provide the capability to update an analysis that exists.  This method is
-/// often used by transformation APIs to update analysis results for a pass
-/// automatically as the transform is performed.
+/// getAnalysisIfAvailable() - Subclasses use this function to
+/// get analysis information that might be around, for example to update it.
+/// This is different than getAnalysis in that it can fail (if the analysis
+/// results haven't been computed), so should only be used if you can handle
+/// the case when the analysis is not available.  This method is often used by
+/// transformation APIs to update analysis results for a pass automatically as
+/// the transform is performed.
 ///
 template
-AnalysisType *Pass::getAnalysisToUpdate() const {
+AnalysisType *Pass::getAnalysisIfAvailable() const {
   assert(Resolver && "Pass not resident in a PassManager object!");
 
   const PassInfo *PI = getClassPassInfo();
   if (PI == 0) return 0;
   return dynamic_cast
-    (Resolver->getAnalysisToUpdate(PI, true));
+    (Resolver->getAnalysisIfAvailable(PI, true));
 }
 
 /// getAnalysis() - This function is used by subclasses to get

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Jan 28 07:14:17 2009
@@ -141,7 +141,7 @@
 bool AsmPrinter::doInitialization(Module &M) {
   Mang = new Mangler(M, TAI->getGlobalPrefix(), TAI->getPrivateGlobalPrefix());
   
-  GCModuleInfo *MI = getAnalysisToUpdate();
+  GCModuleInfo *MI = getAnalysisIfAvailable();
   assert(MI && "AsmPrinter didn't require GCModuleInfo?");
 
   if (TAI->hasSingleParameterDotFile()) {
@@ -163,9 +163,9 @@
 
   SwitchToDataSection("");   // Reset back to no section.
   
-  MachineModuleInfo *MMI = getAnalysisToUpdate();
+  MachineModuleInfo *MMI = getAnalysisIfAvailable();
   if (MMI) MMI->AnalyzeModule(M);
-  DW = getAnalysisToUpdate();
+  DW = getAnalysisIfAvailable();
   return false;
 }
 
@@ -218,7 +218,7 @@
     }
   }
 
-  GCModuleInfo *MI = getAnalysisToUpdate();
+  GCModuleInfo *MI = getAnalysisIfAvailable();
   assert(MI && "AsmPrinter didn't require GCModuleInfo?");
   for (GCModuleInfo::iterator I = MI->end(), E = MI->begin(); I != E; )
     if (GCMetadataPrinter *MP = GetOrCreateGCPrinter(*--I))

Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original)
+++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Wed Jan 28 07:14:17 2009
@@ -198,7 +198,7 @@
 
   RS = RegInfo->requiresRegisterScavenging(MF) ? new RegScavenger() : NULL;
 
-  MMI = getAnalysisToUpdate();
+  MMI = getAnalysisIfAvailable();
 
   bool MadeChangeThisIteration = true;
   while (MadeChangeThisIteration) {

Modified: llvm/trunk/lib/CodeGen/GCMetadata.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GCMetadata.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/GCMetadata.cpp (original)
+++ llvm/trunk/lib/CodeGen/GCMetadata.cpp Wed Jan 28 07:14:17 2009
@@ -205,7 +205,7 @@
 }
 
 bool Deleter::doFinalization(Module &M) {
-  GCModuleInfo *GMI = getAnalysisToUpdate();
+  GCModuleInfo *GMI = getAnalysisIfAvailable();
   assert(GMI && "Deleter didn't require GCModuleInfo?!");
   GMI->clear();
   return false;

Modified: llvm/trunk/lib/CodeGen/GCStrategy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GCStrategy.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/GCStrategy.cpp (original)
+++ llvm/trunk/lib/CodeGen/GCStrategy.cpp Wed Jan 28 07:14:17 2009
@@ -144,7 +144,7 @@
   //        work against the entire module. But this cannot be done at
   //        runFunction time (initializeCustomLowering likely needs to change
   //        the module).
-  GCModuleInfo *MI = getAnalysisToUpdate();
+  GCModuleInfo *MI = getAnalysisIfAvailable();
   assert(MI && "LowerIntrinsics didn't require GCModuleInfo!?");
   for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
     if (!I->isDeclaration() && I->hasGC())

Modified: llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp Wed Jan 28 07:14:17 2009
@@ -320,7 +320,7 @@
 
 bool DebugLabelFolder::runOnMachineFunction(MachineFunction &MF) {
   // Get machine module info.
-  MachineModuleInfo *MMI = getAnalysisToUpdate();
+  MachineModuleInfo *MMI = getAnalysisIfAvailable();
   if (!MMI) return false;
   
   // Track if change is made.

Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original)
+++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Wed Jan 28 07:14:17 2009
@@ -174,7 +174,7 @@
   }
 
   // Update live variable information if there is any.
-  LiveVariables *LV = getAnalysisToUpdate();
+  LiveVariables *LV = getAnalysisIfAvailable();
   if (LV) {
     MachineInstr *PHICopy = prior(AfterPHIsIt);
 

Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Wed Jan 28 07:14:17 2009
@@ -56,7 +56,7 @@
 
       // Get MachineModuleInfo so that we can track the construction of the
       // frame.
-      if (MachineModuleInfo *MMI = getAnalysisToUpdate())
+      if (MachineModuleInfo *MMI = getAnalysisIfAvailable())
         Fn.getFrameInfo()->setMachineModuleInfo(MMI);
 
       // Allow the target machine to make some adjustments to the function

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Jan 28 07:14:17 2009
@@ -314,8 +314,8 @@
   DOUT << "\n\n\n=== " << Fn.getName() << "\n";
 
   FuncInfo->set(Fn, *MF, EnableFastISel);
-  MachineModuleInfo *MMI = getAnalysisToUpdate();
-  DwarfWriter *DW = getAnalysisToUpdate();
+  MachineModuleInfo *MMI = getAnalysisIfAvailable();
+  DwarfWriter *DW = getAnalysisIfAvailable();
   CurDAG->init(*MF, MMI, DW);
   SDL->init(GFI, *AA);
 

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Wed Jan 28 07:14:17 2009
@@ -379,7 +379,7 @@
   MRI = &MF.getRegInfo();
   TII = TM.getInstrInfo();
   TRI = TM.getRegisterInfo();
-  LV = getAnalysisToUpdate();
+  LV = getAnalysisIfAvailable();
 
   bool MadeChange = false;
 

Modified: llvm/trunk/lib/CodeGen/UnreachableBlockElim.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/UnreachableBlockElim.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/UnreachableBlockElim.cpp (original)
+++ llvm/trunk/lib/CodeGen/UnreachableBlockElim.cpp Wed Jan 28 07:14:17 2009
@@ -105,7 +105,7 @@
 bool UnreachableMachineBlockElim::runOnMachineFunction(MachineFunction &F) {
   SmallPtrSet Reachable;
 
-  MMI = getAnalysisToUpdate();
+  MMI = getAnalysisIfAvailable();
 
   // Mark all reachable blocks.
   for (df_ext_iterator >

Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Wed Jan 28 07:14:17 2009
@@ -782,9 +782,9 @@
   bool Result = AsmPrinter::doInitialization(M);
 
   // Emit initial debug information.
-  MMI = getAnalysisToUpdate();
+  MMI = getAnalysisIfAvailable();
   assert(MMI);
-  DW = getAnalysisToUpdate();
+  DW = getAnalysisIfAvailable();
   assert(DW && "Dwarf Writer is not available");
   DW->BeginModule(&M, MMI, O, this, TAI);
 

Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Wed Jan 28 07:14:17 2009
@@ -491,9 +491,9 @@
   bool Result = AsmPrinter::doInitialization(M);
   SwitchToTextSection("\t.text");
   // Emit initial debug information.
-  DW = getAnalysisToUpdate();
+  DW = getAnalysisIfAvailable();
   assert(DW && "Dwarf Writer is not available");
-  MMI = getAnalysisToUpdate();
+  MMI = getAnalysisIfAvailable();
   DW->BeginModule(&M, MMI, O, this, TAI);
   return Result;
 }

Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Wed Jan 28 07:14:17 2009
@@ -641,9 +641,9 @@
   bool Result = AsmPrinter::doInitialization(M);
 
   // Emit initial debug information.
-  MMI = getAnalysisToUpdate();
+  MMI = getAnalysisIfAvailable();
   assert(MMI);
-  DW = getAnalysisToUpdate();
+  DW = getAnalysisIfAvailable();
   assert(DW && "DwarfWriter is not available");
   DW->BeginModule(&M, MMI, O, this, TAI);
 
@@ -859,9 +859,9 @@
   // Emit initial debug information.
   // We need this for Personality functions.
   // AsmPrinter::doInitialization should have done this analysis.
-  MMI = getAnalysisToUpdate();
+  MMI = getAnalysisIfAvailable();
   assert(MMI);
-  DW = getAnalysisToUpdate();
+  DW = getAnalysisIfAvailable();
   assert(DW && "DwarfWriter is not available");
   DW->BeginModule(&M, MMI, O, this, TAI);
 

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Wed Jan 28 07:14:17 2009
@@ -737,8 +737,8 @@
     // Let PassManager know we need debug information and relay
     // the MachineModuleInfo address on to DwarfWriter.
     // AsmPrinter::doInitialization did this analysis.
-    MMI = getAnalysisToUpdate();
-    DW = getAnalysisToUpdate();
+    MMI = getAnalysisIfAvailable();
+    DW = getAnalysisIfAvailable();
     DW->BeginModule(&M, MMI, O, this, TAI);
   }
 
@@ -975,7 +975,7 @@
     }
 
     // Emit final debug information.
-    DwarfWriter *DW = getAnalysisToUpdate();
+    DwarfWriter *DW = getAnalysisIfAvailable();
     DW->EndModule();
 
     // Funny Darwin hack: This flag tells the linker that no global symbols
@@ -995,11 +995,11 @@
     }
 
     // Emit final debug information.
-    DwarfWriter *DW = getAnalysisToUpdate();
+    DwarfWriter *DW = getAnalysisIfAvailable();
     DW->EndModule();
   } else if (Subtarget->isTargetELF()) {
     // Emit final debug information.
-    DwarfWriter *DW = getAnalysisToUpdate();
+    DwarfWriter *DW = getAnalysisIfAvailable();
     DW->EndModule();
   }
 

Modified: llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp Wed Jan 28 07:14:17 2009
@@ -441,9 +441,9 @@
   }
 
   // Emit initial debug information.
-  DW = getAnalysisToUpdate();
+  DW = getAnalysisIfAvailable();
   assert(DW && "Dwarf Writer is not available");
-  DW->BeginModule(&M, getAnalysisToUpdate(), 
+  DW->BeginModule(&M, getAnalysisIfAvailable(),
                   O, this, TAI);
   return Result;
 }

Modified: llvm/trunk/lib/Transforms/IPO/Internalize.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/Internalize.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/IPO/Internalize.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/Internalize.cpp Wed Jan 28 07:14:17 2009
@@ -99,7 +99,7 @@
 }
 
 bool InternalizePass::runOnModule(Module &M) {
-  CallGraph *CG = getAnalysisToUpdate();
+  CallGraph *CG = getAnalysisIfAvailable();
   CallGraphNode *ExternalNode = CG ? CG->getExternalCallingNode() : 0;
 
   if (ExternalNames.empty()) {

Modified: llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp Wed Jan 28 07:14:17 2009
@@ -457,7 +457,7 @@
            "Expected only one incoming value from Original PreHeader");
   }
 
-  if (DominatorTree *DT = getAnalysisToUpdate()) {
+  if (DominatorTree *DT = getAnalysisIfAvailable()) {
     DT->addNewBlock(NewPreHeader, OrigPreHeader);
     DT->changeImmediateDominator(L->getHeader(), NewPreHeader);
     DT->changeImmediateDominator(Exit, OrigPreHeader);
@@ -473,7 +473,7 @@
     DT->changeImmediateDominator(OrigHeader, OrigLatch);
   }
 
-  if (DominanceFrontier *DF = getAnalysisToUpdate()) {
+  if (DominanceFrontier *DF = getAnalysisIfAvailable()) {
     // New Preheader's dominance frontier is Exit block.
     DominanceFrontier::DomSetType NewPHSet;
     NewPHSet.insert(Exit);
@@ -509,7 +509,7 @@
     // If a loop block dominates new loop latch then its frontier is
     // new header and Exit.
     BasicBlock *NewLatch = L->getLoopLatch();
-    DominatorTree *DT = getAnalysisToUpdate();
+    DominatorTree *DT = getAnalysisIfAvailable();
     for (Loop::block_iterator BI = L->block_begin(), BE = L->block_end();
          BI != BE; ++BI) {
       BasicBlock *B = *BI;

Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnroll.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnroll.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopUnroll.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopUnroll.cpp Wed Jan 28 07:14:17 2009
@@ -170,10 +170,10 @@
     return false;
 
   // FIXME: Reconstruct dom info, because it is not preserved properly.
-  DominatorTree *DT = getAnalysisToUpdate();
+  DominatorTree *DT = getAnalysisIfAvailable();
   if (DT) {
     DT->runOnFunction(*F);
-    DominanceFrontier *DF = getAnalysisToUpdate();
+    DominanceFrontier *DF = getAnalysisIfAvailable();
     if (DF)
       DF->runOnFunction(*F);
   }

Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Wed Jan 28 07:14:17 2009
@@ -188,8 +188,8 @@
 bool LoopUnswitch::runOnLoop(Loop *L, LPPassManager &LPM_Ref) {
   LI = &getAnalysis();
   LPM = &LPM_Ref;
-  DF = getAnalysisToUpdate();
-  DT = getAnalysisToUpdate();
+  DF = getAnalysisIfAvailable();
+  DT = getAnalysisIfAvailable();
   currentLoop = L;
   Function *F = currentLoop->getHeader()->getParent();
   bool Changed = false;

Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Wed Jan 28 07:14:17 2009
@@ -136,7 +136,7 @@
   
   // Finally, erase the old block and update dominator info.
   if (P) {
-    if (DominatorTree* DT = P->getAnalysisToUpdate()) {
+    if (DominatorTree* DT = P->getAnalysisIfAvailable()) {
       DomTreeNode* DTN = DT->getNode(BB);
       DomTreeNode* PredDTN = DT->getNode(PredBB);
   
@@ -299,11 +299,11 @@
   BasicBlock *New = Old->splitBasicBlock(SplitIt, Old->getName()+".split");
 
   // The new block lives in whichever loop the old one did.
-  if (LoopInfo* LI = P->getAnalysisToUpdate())
+  if (LoopInfo* LI = P->getAnalysisIfAvailable())
     if (Loop *L = LI->getLoopFor(Old))
       L->addBasicBlockToLoop(New, LI->getBase());
 
-  if (DominatorTree *DT = P->getAnalysisToUpdate()) 
+  if (DominatorTree *DT = P->getAnalysisIfAvailable())
     {
       // Old dominates New. New node domiantes all other nodes dominated by Old.
       DomTreeNode *OldNode = DT->getNode(Old);
@@ -319,7 +319,7 @@
         DT->changeImmediateDominator(*I, NewNode);
     }
 
-  if (DominanceFrontier *DF = P->getAnalysisToUpdate())
+  if (DominanceFrontier *DF = P->getAnalysisIfAvailable())
     DF->splitBlock(Old);
     
   return New;
@@ -350,12 +350,12 @@
     Preds[i]->getTerminator()->replaceUsesOfWith(BB, NewBB);
   
   // Update dominator tree and dominator frontier if available.
-  DominatorTree *DT = P ? P->getAnalysisToUpdate() : 0;
+  DominatorTree *DT = P ? P->getAnalysisIfAvailable() : 0;
   if (DT)
     DT->splitBlock(NewBB);
-  if (DominanceFrontier *DF = P ? P->getAnalysisToUpdate():0)
+  if (DominanceFrontier *DF = P ? P->getAnalysisIfAvailable():0)
     DF->splitBlock(NewBB);
-  AliasAnalysis *AA = P ? P->getAnalysisToUpdate() : 0;
+  AliasAnalysis *AA = P ? P->getAnalysisIfAvailable() : 0;
   
   
   // Insert a new PHI node into NewBB for every PHI node in BB and that new PHI

Modified: llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Wed Jan 28 07:14:17 2009
@@ -187,7 +187,7 @@
   bool NewBBDominatesDestBB = true;
   
   // Should we update DominatorTree information?
-  if (DominatorTree *DT = P->getAnalysisToUpdate()) {
+  if (DominatorTree *DT = P->getAnalysisIfAvailable()) {
     DomTreeNode *TINode = DT->getNode(TIBB);
 
     // The new block is not the immediate dominator for any other nodes, but
@@ -218,7 +218,7 @@
   }
 
   // Should we update DominanceFrontier information?
-  if (DominanceFrontier *DF = P->getAnalysisToUpdate()) {
+  if (DominanceFrontier *DF = P->getAnalysisIfAvailable()) {
     // If NewBBDominatesDestBB hasn't been computed yet, do so with DF.
     if (!OtherPreds.empty()) {
       // FIXME: IMPLEMENT THIS!
@@ -252,7 +252,7 @@
   }
   
   // Update LoopInfo if it is around.
-  if (LoopInfo *LI = P->getAnalysisToUpdate()) {
+  if (LoopInfo *LI = P->getAnalysisIfAvailable()) {
     // If one or the other blocks were not in a loop, the new block is not
     // either, and thus LI doesn't need to be updated.
     if (Loop *TIL = LI->getLoopFor(TIBB))

Modified: llvm/trunk/lib/Transforms/Utils/CloneLoop.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CloneLoop.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Utils/CloneLoop.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/CloneLoop.cpp Wed Jan 28 07:14:17 2009
@@ -79,8 +79,8 @@
   DominatorTree *DT = NULL;
   DominanceFrontier *DF = NULL;
   if (P) {
-    DT = P->getAnalysisToUpdate();
-    DF = P->getAnalysisToUpdate();
+    DT = P->getAnalysisIfAvailable();
+    DF = P->getAnalysisIfAvailable();
   }
 
   SmallVector NewBlocks;

Modified: llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Wed Jan 28 07:14:17 2009
@@ -112,7 +112,7 @@
 bool LoopSimplify::runOnFunction(Function &F) {
   bool Changed = false;
   LI = &getAnalysis();
-  AA = getAnalysisToUpdate();
+  AA = getAnalysisIfAvailable();
   DT = &getAnalysis();
 
   // Check to see that no blocks (other than the header) in loops have
@@ -595,6 +595,6 @@
 
   // Update dominator information
   DT->splitBlock(BEBlock);
-  if (DominanceFrontier *DF = getAnalysisToUpdate())
+  if (DominanceFrontier *DF = getAnalysisIfAvailable())
     DF->splitBlock(BEBlock);
 }

Modified: llvm/trunk/lib/VMCore/Pass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Pass.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/Pass.cpp (original)
+++ llvm/trunk/lib/VMCore/Pass.cpp Wed Jan 28 07:14:17 2009
@@ -37,7 +37,7 @@
 ModulePass::~ModulePass() { }
 
 bool Pass::mustPreserveAnalysisID(const PassInfo *AnalysisID) const {
-  return Resolver->getAnalysisToUpdate(AnalysisID, true) != 0;
+  return Resolver->getAnalysisIfAvailable(AnalysisID, true) != 0;
 }
 
 // dumpPassStructure - Implement the -debug-passes=Structure option

Modified: llvm/trunk/lib/VMCore/PassManager.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=63198&r1=63197&r2=63198&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/PassManager.cpp (original)
+++ llvm/trunk/lib/VMCore/PassManager.cpp Wed Jan 28 07:14:17 2009
@@ -679,7 +679,7 @@
   if (!VerifyDomInfo || !P.getResolver())
     return;
 
-  DominatorTree *DT = P.getAnalysisToUpdate();
+  DominatorTree *DT = P.getAnalysisIfAvailable();
   if (!DT)
     return;
 
@@ -695,7 +695,7 @@
     assert (0 && "Invalid dominator info");
   }
 
-  DominanceFrontier *DF = P.getAnalysisToUpdate();
+  DominanceFrontier *DF = P.getAnalysisIfAvailable();
   if (!DF) 
     return;
 
@@ -1088,8 +1088,8 @@
 
 //===----------------------------------------------------------------------===//
 // NOTE: Is this the right place to define this method ?
-// getAnalysisToUpdate - Return an analysis result or null if it doesn't exist
-Pass *AnalysisResolver::getAnalysisToUpdate(AnalysisID ID, bool dir) const {
+// getAnalysisIfAvailable - Return analysis result or null if it doesn't exist.
+Pass *AnalysisResolver::getAnalysisIfAvailable(AnalysisID ID, bool dir) const {
   return PM.findAnalysisPass(ID, dir);
 }
 




From baldrick at free.fr  Wed Jan 28 08:43:08 2009
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 28 Jan 2009 14:43:08 -0000
Subject: [llvm-commits] [llvm] r63199 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
Message-ID: <200901281443.n0SEhBFU008538@zion.cs.uiuc.edu>

Author: baldrick
Date: Wed Jan 28 08:42:54 2009
New Revision: 63199

URL: http://llvm.org/viewvc/llvm-project?rev=63199&view=rev
Log:
Formatting.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63199&r1=63198&r2=63199&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Wed Jan 28 08:42:54 2009
@@ -374,12 +374,9 @@
 /// larger then ValueVT then AssertOp can be used to specify whether the extra
 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
 /// (ISD::AssertSext).
-static SDValue getCopyFromParts(SelectionDAG &DAG,
-                                  const SDValue *Parts,
-                                  unsigned NumParts,
-                                  MVT PartVT,
-                                  MVT ValueVT,
-                                  ISD::NodeType AssertOp = ISD::DELETED_NODE) {
+static SDValue getCopyFromParts(SelectionDAG &DAG, const SDValue *Parts,
+                                unsigned NumParts, MVT PartVT, MVT ValueVT,
+                                ISD::NodeType AssertOp = ISD::DELETED_NODE) {
   assert(NumParts > 0 && "No parts to assemble!");
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   SDValue Val = Parts[0];
@@ -587,8 +584,8 @@
       unsigned RoundBits = RoundParts * PartBits;
       unsigned OddParts = NumParts - RoundParts;
       SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
-                                     DAG.getConstant(RoundBits,
-                                                     TLI.getShiftAmountTy()));
+                                   DAG.getConstant(RoundBits,
+                                                   TLI.getShiftAmountTy()));
       getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
       if (TLI.isBigEndian())
         // The odd parts were reversed by getCopyToParts - unreverse them.




From tonic at nondot.org  Wed Jan 28 09:22:28 2009
From: tonic at nondot.org (Tanya Lattner)
Date: Wed, 28 Jan 2009 15:22:28 -0000
Subject: [llvm-commits] [llvm] r63201 -
 /llvm/branches/release_25/lib/Analysis/MemoryDependenceAnalysis.cpp
Message-ID: <200901281522.n0SFMTbV009792@zion.cs.uiuc.edu>

Author: tbrethou
Date: Wed Jan 28 09:22:24 2009
New Revision: 63201

URL: http://llvm.org/viewvc/llvm-project?rev=63201&view=rev
Log:
a minor tweak to my previous patch, handle the invalidation case
when there are multiple iterations of the loop.  This fixes PR3375.


Modified:
    llvm/branches/release_25/lib/Analysis/MemoryDependenceAnalysis.cpp

Modified: llvm/branches/release_25/lib/Analysis/MemoryDependenceAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=63201&r1=63200&r2=63201&view=diff

==============================================================================
--- llvm/branches/release_25/lib/Analysis/MemoryDependenceAnalysis.cpp (original)
+++ llvm/branches/release_25/lib/Analysis/MemoryDependenceAnalysis.cpp Wed Jan 28 09:22:24 2009
@@ -751,9 +751,10 @@
         // cache remains sorted.  Sort it now (if needed) so that recursive
         // invocations of getNonLocalPointerDepFromBB that could reuse the cache
         // value will only see properly sorted cache arrays.
-        if (NumSortedEntries != Cache->size()) {
+        if (Cache && NumSortedEntries != Cache->size()) {
           std::sort(Cache->begin(), Cache->end());
           NumSortedEntries = Cache->size();
+          Cache = 0;
         }
         
         // FIXME: it is entirely possible that PHI translating will end up with
@@ -767,12 +768,12 @@
                                         Result, Visited))
           goto PredTranslationFailure;
       }
-      
+
       // Refresh the CacheInfo/Cache pointer so that it isn't invalidated.
       CacheInfo = &NonLocalPointerDeps[CacheKey];
       Cache = &CacheInfo->second;
       NumSortedEntries = Cache->size();
-
+      
       // Since we did phi translation, the "Cache" set won't contain all of the
       // results for the query.  This is ok (we can still use it to accelerate
       // specific block queries) but we can't do the fastpath "return all




From tonic at nondot.org  Wed Jan 28 09:28:35 2009
From: tonic at nondot.org (Tanya Lattner)
Date: Wed, 28 Jan 2009 15:28:35 -0000
Subject: [llvm-commits] [llvm] r63202 -
 /llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
Message-ID: <200901281528.n0SFSf6I009997@zion.cs.uiuc.edu>

Author: tbrethou
Date: Wed Jan 28 09:28:20 2009
New Revision: 63202

URL: http://llvm.org/viewvc/llvm-project?rev=63202&view=rev
Log:
Merge from mainline.
Set appropriate tag for the composite type.

Modified:
    llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp

Modified: llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=63202&r1=63201&r2=63202&view=diff

==============================================================================
--- llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Wed Jan 28 09:28:20 2009
@@ -1747,6 +1747,7 @@
     const std::string &Name = CTy.getName();
     uint64_t Size = CTy.getSizeInBits() >> 3;
     unsigned Tag = CTy.getTag();
+    Buffer.setTag(Tag);
     switch (Tag) {
     case DW_TAG_vector_type:
     case DW_TAG_array_type:




From tonic at nondot.org  Wed Jan 28 09:35:57 2009
From: tonic at nondot.org (Tanya Lattner)
Date: Wed, 28 Jan 2009 15:35:57 -0000
Subject: [llvm-commits] [llvm] r63203 -
 /llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
Message-ID: <200901281535.n0SFZvLR010316@zion.cs.uiuc.edu>

Author: tbrethou
Date: Wed Jan 28 09:35:55 2009
New Revision: 63203

URL: http://llvm.org/viewvc/llvm-project?rev=63203&view=rev
Log:
Merge from mainline.

Code did not follow associated comment. not a good idea.

Modified:
    llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp

Modified: llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=63203&r1=63202&r2=63203&view=diff

==============================================================================
--- llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Wed Jan 28 09:35:55 2009
@@ -1578,7 +1578,7 @@
   void AddSourceLine(DIE *Die, const DIGlobal *G) {
     unsigned FileID = 0;
     unsigned Line = G->getLineNumber();
-    if (G->getVersion() < LLVMDebugVersion6) {
+    if (G->getVersion() <= LLVMDebugVersion6) {
       // Version6 or earlier. Use compile unit info to get file id.
       CompileUnit *Unit = FindCompileUnit(G->getCompileUnit());
       FileID = Unit->getID();




From tonic at nondot.org  Wed Jan 28 09:39:51 2009
From: tonic at nondot.org (Tanya Lattner)
Date: Wed, 28 Jan 2009 15:39:51 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63204 - in
 /llvm-gcc-4.2/branches/release_25/gcc: llvm-debug.cpp llvm-debug.h
Message-ID: <200901281539.n0SFdqpZ010454@zion.cs.uiuc.edu>

Author: tbrethou
Date: Wed Jan 28 09:39:51 2009
New Revision: 63204

URL: http://llvm.org/viewvc/llvm-project?rev=63204&view=rev
Log:
Merge from mainline.
Refactor code. No functionality change.


Modified:
    llvm-gcc-4.2/branches/release_25/gcc/llvm-debug.cpp
    llvm-gcc-4.2/branches/release_25/gcc/llvm-debug.h

Modified: llvm-gcc-4.2/branches/release_25/gcc/llvm-debug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/release_25/gcc/llvm-debug.cpp?rev=63204&r1=63203&r2=63204&view=diff

==============================================================================
--- llvm-gcc-4.2/branches/release_25/gcc/llvm-debug.cpp (original)
+++ llvm-gcc-4.2/branches/release_25/gcc/llvm-debug.cpp Wed Jan 28 09:39:51 2009
@@ -338,41 +338,319 @@
 
 }
 
-/// getOrCreateType - Get the type from the cache or create a new type if
-/// necessary.
-/// FIXME - I hate jumbo methods - split up.
-DIType DebugInfo::getOrCreateType(tree type) {
-  DEBUGASSERT(type != NULL_TREE && type != error_mark_node &&
-              "Not a type.");
-  if (type == NULL_TREE || type == error_mark_node) return DIType();
+/// createBasicType - Create BasicType.
+DIType DebugInfo::createBasicType(tree type) {
 
-  // Should only be void if a pointer/reference/return type.  Returning NULL
-  // allows the caller to produce a non-derived type.
-  if (TREE_CODE(type) == VOID_TYPE) return DIType();
+  const char *TypeName = GetNodeName(type);
+  uint64_t Size = NodeSizeInBits(type);
+  uint64_t Align = NodeAlignInBits(type);
+
+  unsigned Encoding = 0;
   
-  // Check to see if the compile unit already has created this type.
-  DIType &Slot = TypeCache[type];
-  if (!Slot.isNull())
-    return Slot;
+  switch (TREE_CODE(type)) {
+  case INTEGER_TYPE:
+    if (TYPE_STRING_FLAG (type)) {
+      if (TYPE_UNSIGNED (type))
+        Encoding = DW_ATE_unsigned_char;
+      else
+        Encoding = DW_ATE_signed_char;
+    }
+    else if (TYPE_UNSIGNED (type))
+      Encoding = DW_ATE_unsigned;
+    else
+      Encoding = DW_ATE_signed;
+    break;
+  case REAL_TYPE:
+    Encoding = DW_ATE_float;
+    break;
+  case COMPLEX_TYPE:
+    Encoding = TREE_CODE(TREE_TYPE(type)) == REAL_TYPE ?
+      DW_ATE_complex_float : DW_ATE_lo_user;
+    break;
+  case BOOLEAN_TYPE:
+    Encoding = DW_ATE_boolean;
+    break;
+  default: { 
+    DEBUGASSERT(0 && "Basic type case missing");
+    Encoding = DW_ATE_signed;
+    Size = BITS_PER_WORD;
+    Align = BITS_PER_WORD;
+    break;
+  }
+  }
+  return DebugFactory.CreateBasicType(MainCompileUnit, TypeName, 
+                                      MainCompileUnit, 0, Size, Align,
+                                      0, 0, Encoding);
+}
+
+/// createMethodType - Create MethodType.
+DIType DebugInfo::createMethodType(tree type) {
+
+  llvm::SmallVector EltTys;
   
-  DIType MainTy;
-  if (type != TYPE_MAIN_VARIANT(type)) {
-    if (TYPE_NEXT_VARIANT(type) && type != TYPE_NEXT_VARIANT(type))
-      MainTy = getOrCreateType(TYPE_NEXT_VARIANT(type));
-    else if (TYPE_MAIN_VARIANT(type))
-      MainTy = getOrCreateType(TYPE_MAIN_VARIANT(type));
+  // Add the result type at least.
+  EltTys.push_back(getOrCreateType(TREE_TYPE(type)));
+  
+  // Set up remainder of arguments.
+  for (tree arg = TYPE_ARG_TYPES(type); arg; arg = TREE_CHAIN(arg)) {
+    tree formal_type = TREE_VALUE(arg);
+    if (formal_type == void_type_node) break;
+    EltTys.push_back(getOrCreateType(formal_type));
   }
+  
+  llvm::DIArray EltTypeArray =
+    DebugFactory.GetOrCreateArray(&EltTys[0], EltTys.size());
+  
+  return DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_subroutine_type,
+                                          MainCompileUnit, "", 
+                                          MainCompileUnit, 0, 0, 0, 0, 0,
+                                          llvm::DIType(), EltTypeArray);
+}
 
-  // Get the name and location early to assist debugging.
-  const char *TypeName = GetNodeName(type);
-  expanded_location Loc = GetNodeLocation(type);
+/// createPointerType - Create PointerType.
+DIType DebugInfo::createPointerType(tree type) {
+
+  DIType FromTy = getOrCreateType(TREE_TYPE(type));
+  // type* and type&
+  // FIXME: Should BLOCK_POINTER_TYP have its own DW_TAG?
+  unsigned Tag = (TREE_CODE(type) == POINTER_TYPE ||
+                  TREE_CODE(type) == BLOCK_POINTER_TYPE) ?
+    DW_TAG_pointer_type :
+    DW_TAG_reference_type;
+  return  DebugFactory.CreateDerivedType(Tag, MainCompileUnit, "", 
+                                         MainCompileUnit, 0 /*line no*/, 
+                                         NodeSizeInBits(type),
+                                         NodeAlignInBits(type),
+                                         0 /*offset */, 
+                                         0 /* flags */, 
+                                         FromTy);
+}
+
+/// createArrayType - Create ArrayType.
+DIType DebugInfo::createArrayType(tree type) {
+
+  // type[n][m]...[p]
+  if (TYPE_STRING_FLAG(type) && TREE_CODE(TREE_TYPE(type)) == INTEGER_TYPE){
+    DEBUGASSERT(0 && "Don't support pascal strings");
+    return DIType();
+  }
   
-  // Bit size and align of the type.
-  uint64_t Size = NodeSizeInBits(type);
-  uint64_t Align = NodeAlignInBits(type);
+  unsigned Tag = 0;
+  
+  if (TREE_CODE(type) == VECTOR_TYPE) 
+    Tag = DW_TAG_vector_type;
+  else
+    Tag = DW_TAG_array_type;
+  
+  // Add the dimensions of the array.  FIXME: This loses CV qualifiers from
+  // interior arrays, do we care?  Why aren't nested arrays represented the
+  // obvious/recursive way?
+  llvm::SmallVector Subscripts;
+  
+  // There will be ARRAY_TYPE nodes for each rank.  Followed by the derived
+  // type.
+  tree atype = type;
+  tree EltTy = TREE_TYPE(atype);
+  for (; TREE_CODE(atype) == ARRAY_TYPE; atype = TREE_TYPE(atype)) {
+    tree Domain = TYPE_DOMAIN(atype);
+    if (Domain) {
+      // FIXME - handle dynamic ranges
+      tree MinValue = TYPE_MIN_VALUE(Domain);
+      tree MaxValue = TYPE_MAX_VALUE(Domain);
+      if (MinValue && MaxValue &&
+          isInt64(MinValue, 0) && isInt64(MaxValue, 0)) {
+        uint64_t Low = getInt64(MinValue, 0);
+        uint64_t Hi = getInt64(MaxValue, 0);
+        Subscripts.push_back(DebugFactory.GetOrCreateSubrange(Low, Hi));
+      }
+    }
+    EltTy = TREE_TYPE(atype);
+  }
+  
+  llvm::DIArray SubscriptArray =
+    DebugFactory.GetOrCreateArray(&Subscripts[0], Subscripts.size());
+  
+  return DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_array_type,
+                                          MainCompileUnit, "", 
+                                          MainCompileUnit,
+                                          0, NodeSizeInBits(type), 
+                                          NodeAlignInBits(type), 0, 0,
+                                          getOrCreateType(EltTy),
+                                          SubscriptArray);
+}
+
+/// createEnumType - Create EnumType.
+DIType DebugInfo::createEnumType(tree type) {
+  // enum { a, b, ..., z };
+  llvm::SmallVector Elements;
+  
+  if (TYPE_SIZE(type)) {
+    for (tree Link = TYPE_VALUES(type); Link; Link = TREE_CHAIN(Link)) {
+      tree EnumValue = TREE_VALUE(Link);
+      int64_t Value = getInt64(EnumValue, tree_int_cst_sgn(EnumValue) > 0);
+      const char *EnumName = IDENTIFIER_POINTER(TREE_PURPOSE(Link));
+      Elements.push_back(DebugFactory.CreateEnumerator(EnumName, Value));
+    }
+  }
+  
+  llvm::DIArray EltArray =
+    DebugFactory.GetOrCreateArray(&Elements[0], Elements.size());
+  
+  expanded_location Loc = GetNodeLocation(TREE_CHAIN(type), false);
+  std::string Filename, Directory;
+  DirectoryAndFile(Loc.file, Directory, Filename);
+  return DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_enumeration_type,
+                                          MainCompileUnit, GetNodeName(type), 
+                                          MainCompileUnit, Loc.line,
+                                          NodeSizeInBits(type), 
+                                          NodeAlignInBits(type), 0, 0,
+                                          llvm::DIType(), EltArray,
+                                          &Filename, &Directory);
+}
+
+/// createStructType - Create StructType for struct or union or class.
+DIType DebugInfo::createStructType(tree type) {
 
+  // struct { a; b; ... z; }; | union { a; b; ... z; };
+  unsigned Tag = TREE_CODE(type) == RECORD_TYPE ? DW_TAG_structure_type :
+    DW_TAG_union_type;
+  
+  // Records and classes and unions can all be recursive.  To handle them,
+  // we first generate a debug descriptor for the struct as a forward 
+  // declaration. Then (if it is a definition) we go through and get debug 
+  // info for all of its members.  Finally, we create a descriptor for the
+  // complete type (which may refer to the forward decl if the struct is 
+  // recursive) and replace all  uses of the forward declaration with the 
+  // final definition. 
+  expanded_location Loc = GetNodeLocation(TREE_CHAIN(type), false);
+  std::string Filename, Directory;
+  DirectoryAndFile(Loc.file, Directory, Filename);
+  llvm::DIType FwdDecl =
+    DebugFactory.CreateCompositeType(Tag, MainCompileUnit, GetNodeName(type),
+                                     MainCompileUnit, Loc.line, 
+                                     0, 0, 0, llvm::DIType::FlagFwdDecl,
+                                     llvm::DIType(), llvm::DIArray(),
+                                     &Filename, &Directory);
+  
+  
+  // forward declaration, 
+  if (TYPE_SIZE(type) == 0) 
+    return FwdDecl;
+  
+  // Insert into the TypeCache so that recursive uses will find it.
+  TypeCache[type] =  FwdDecl;
+  
+  // Convert all the elements.
+  llvm::SmallVector EltTys;
+  
+  if (tree binfo = TYPE_BINFO(type)) {
+    VEC (tree, gc) *accesses = BINFO_BASE_ACCESSES (binfo);
+    
+    for (unsigned i = 0, e = BINFO_N_BASE_BINFOS(binfo); i != e; ++i) {
+      tree BInfo = BINFO_BASE_BINFO(binfo, i);
+      tree BInfoType = BINFO_TYPE (BInfo);
+      DIType BaseClass = getOrCreateType(BInfoType);
+      
+      // FIXME : name, size, align etc...
+      DIType DTy = 
+        DebugFactory.CreateDerivedType(DW_TAG_inheritance, 
+                                       MainCompileUnit,"", 
+                                       MainCompileUnit, 0,0,0, 
+                                       getInt64(BINFO_OFFSET(BInfo), 0),
+                                       0, BaseClass);
+      EltTys.push_back(DTy);
+    }
+  }
+  
+  // Now add members of this class.
+  for (tree Member = TYPE_FIELDS(type); Member;
+       Member = TREE_CHAIN(Member)) {
+    // Should we skip.
+    if (DECL_P(Member) && DECL_IGNORED_P(Member)) continue;
+    
+    if (TREE_CODE(Member) == FIELD_DECL) {
+      
+      if (DECL_FIELD_OFFSET(Member) == 0 ||
+          TREE_CODE(DECL_FIELD_OFFSET(Member)) != INTEGER_CST)
+        // FIXME: field with variable position, skip it for now.
+        continue;
+      
+      /* Ignore nameless fields.  */
+      if (DECL_NAME (Member) == NULL_TREE)
+        continue;
+      
+      // Get the location of the member.
+      expanded_location MemLoc = GetNodeLocation(Member, false);
+      std::string MemFilename, MemDirectory;
+      DirectoryAndFile(MemLoc.file, MemDirectory, MemFilename);
+      
+      // Field type is the declared type of the field.
+      tree FieldNodeType = FieldType(Member);
+      DIType MemberType = getOrCreateType(FieldNodeType);
+      const char *MemberName = GetNodeName(Member);
+      unsigned Flags = 0;
+      if (TREE_PROTECTED(Member))
+        Flags = llvm::DIType::FlagProtected;
+      else if (TREE_PRIVATE(Member))
+        Flags = llvm::DIType::FlagPrivate;
+      
+      DIType DTy =
+        DebugFactory.CreateDerivedType(DW_TAG_member, MainCompileUnit, 
+                                       MemberName, MainCompileUnit,
+                                       MemLoc.line, NodeSizeInBits(Member),
+                                       NodeAlignInBits(FieldNodeType),
+                                       int_bit_position(Member), 
+                                       Flags, MemberType,
+                                       &MemFilename, &MemDirectory);
+      EltTys.push_back(DTy);
+    } else {
+      DEBUGASSERT(0 && "Unsupported member tree code!");
+    }
+  }
+  
+  for (tree Member = TYPE_METHODS(type); Member;
+       Member = TREE_CHAIN(Member)) {
+    
+    if (DECL_ABSTRACT_ORIGIN (Member)) continue;
+    
+    // Get the location of the member.
+    expanded_location MemLoc = GetNodeLocation(Member, false);
+    std::string MemFilename, MemDirectory;
+    DirectoryAndFile(MemLoc.file, MemDirectory, MemFilename);
+    
+    const char *MemberName = GetNodeName(Member);                
+    DIType SPTy = getOrCreateType(TREE_TYPE(Member));
+    DISubprogram SP = 
+      DebugFactory.CreateSubprogram(MainCompileUnit, MemberName, MemberName,
+                                    MemberName, MainCompileUnit, 
+                                    MemLoc.line, SPTy, false, false,
+                                    &MemFilename, &MemDirectory);
+    
+    EltTys.push_back(SP);
+  }
+  
+  llvm::DIArray Elements =
+    DebugFactory.GetOrCreateArray(&EltTys[0], EltTys.size());
+  
+  llvm::DIType RealDecl =
+    DebugFactory.CreateCompositeType(Tag, MainCompileUnit, 
+                                     GetNodeName(type),
+                                     MainCompileUnit, Loc.line, 
+                                     NodeSizeInBits(type), NodeAlignInBits(type),
+                                     0, 0, llvm::DIType(), Elements,
+                                     &Filename, &Directory);
+  
+  // Now that we have a real decl for the struct, replace anything using the
+  // old decl with the new one.  This will recursively update the debug info.
+  FwdDecl.getGV()->replaceAllUsesWith(RealDecl.getGV());
+  FwdDecl.getGV()->eraseFromParent();
+  return RealDecl;
+}
+
+/// createVarinatType - Create variant type or return MainTy.
+DIType DebugInfo::createVariantType(tree type, DIType MainTy) {
+  
   DIType Ty;
-  // Do we have a typedef?
   if (tree Name = TYPE_NAME(type)) {
     if (TREE_CODE(Name) == TYPE_DECL &&  DECL_ORIGINAL_TYPE(Name)) {
       expanded_location TypeDefLoc = GetNodeLocation(Name);
@@ -393,7 +671,8 @@
   }
 
   if (TYPE_VOLATILE(type)) {
-    Ty = DebugFactory.CreateDerivedType(DW_TAG_volatile_type, MainCompileUnit, "", 
+    Ty = DebugFactory.CreateDerivedType(DW_TAG_volatile_type, 
+                                        MainCompileUnit, "", 
                                         MainCompileUnit, 0 /*line no*/, 
                                         NodeSizeInBits(type),
                                         NodeAlignInBits(type),
@@ -404,7 +683,8 @@
   }
 
   if (TYPE_READONLY(type)) 
-    Ty =  DebugFactory.CreateDerivedType(DW_TAG_const_type, MainCompileUnit, "", 
+    Ty =  DebugFactory.CreateDerivedType(DW_TAG_const_type, 
+                                         MainCompileUnit, "", 
                                          MainCompileUnit, 0 /*line no*/, 
                                          NodeSizeInBits(type),
                                          NodeAlignInBits(type),
@@ -418,8 +698,36 @@
   }
 
   // If, for some reason, main type varaint type is seen then use it.
-  if (!MainTy.isNull())
-    return MainTy;
+  return MainTy;
+}
+
+/// getOrCreateType - Get the type from the cache or create a new type if
+/// necessary.
+DIType DebugInfo::getOrCreateType(tree type) {
+  DEBUGASSERT(type != NULL_TREE && type != error_mark_node &&
+              "Not a type.");
+  if (type == NULL_TREE || type == error_mark_node) return DIType();
+
+  // Should only be void if a pointer/reference/return type.  Returning NULL
+  // allows the caller to produce a non-derived type.
+  if (TREE_CODE(type) == VOID_TYPE) return DIType();
+  
+  // Check to see if the compile unit already has created this type.
+  DIType &Slot = TypeCache[type];
+  if (!Slot.isNull())
+    return Slot;
+  
+  DIType MainTy;
+  if (type != TYPE_MAIN_VARIANT(type)) {
+    if (TYPE_NEXT_VARIANT(type) && type != TYPE_NEXT_VARIANT(type))
+      MainTy = getOrCreateType(TYPE_NEXT_VARIANT(type));
+    else if (TYPE_MAIN_VARIANT(type))
+      MainTy = getOrCreateType(TYPE_MAIN_VARIANT(type));
+  }
+
+  DIType Ty = createVariantType(type, MainTy);
+  if (!Ty.isNull())
+    return Ty;
 
   // Work out details of type.
   switch (TREE_CODE(type)) {
@@ -433,25 +741,9 @@
     
     case POINTER_TYPE:
     case REFERENCE_TYPE:
-    case BLOCK_POINTER_TYPE: {
-
-      DIType FromTy = getOrCreateType(TREE_TYPE(type));
-      // type* and type&
-      // FIXME: Should BLOCK_POINTER_TYP have its own DW_TAG?
-      unsigned Tag = (TREE_CODE(type) == POINTER_TYPE ||
-                      TREE_CODE(type) == BLOCK_POINTER_TYPE) ?
-        DW_TAG_pointer_type :
-        DW_TAG_reference_type;
-      Ty =  DebugFactory.CreateDerivedType(Tag, MainCompileUnit, "", 
-                                           MainCompileUnit, 0 /*line no*/, 
-                                           NodeSizeInBits(type),
-                                           NodeAlignInBits(type),
-                                           0 /*offset */, 
-                                           0 /* flags */, 
-                                           FromTy);
-      
+    case BLOCK_POINTER_TYPE:
+      Ty = createPointerType(type);
       break;
-    }
     
     case OFFSET_TYPE: {
       // gen_type_die(TYPE_OFFSET_BASETYPE(type), context_die);
@@ -461,292 +753,31 @@
     }
 
     case FUNCTION_TYPE:
-    case METHOD_TYPE: {
-      llvm::SmallVector EltTys;
-    
-      // Add the result type at least.
-      EltTys.push_back(getOrCreateType(TREE_TYPE(type)));
-      
-      // Set up remainder of arguments.
-      for (tree arg = TYPE_ARG_TYPES(type); arg; arg = TREE_CHAIN(arg)) {
-        tree formal_type = TREE_VALUE(arg);
-        if (formal_type == void_type_node) break;
-        EltTys.push_back(getOrCreateType(formal_type));
-      }
-      
-      llvm::DIArray EltTypeArray =
-        DebugFactory.GetOrCreateArray(&EltTys[0], EltTys.size());
-      
-      Ty = DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_subroutine_type,
-                                            MainCompileUnit, "", 
-                                            MainCompileUnit, 0, 0, 0, 0, 0,
-                                            llvm::DIType(), EltTypeArray);
+    case METHOD_TYPE: 
+      Ty = createMethodType(type);
       break;
-    }
       
     case VECTOR_TYPE:
-    case ARRAY_TYPE: {
-      // type[n][m]...[p]
-      if (TYPE_STRING_FLAG(type) && TREE_CODE(TREE_TYPE(type)) == INTEGER_TYPE){
-        DEBUGASSERT(0 && "Don't support pascal strings");
-        return DIType();
-      }
-      
-      unsigned Tag = 0;
-      
-      if (TREE_CODE(type) == VECTOR_TYPE) 
-        Tag = DW_TAG_vector_type;
-      else
-        Tag = DW_TAG_array_type;
-
-      // Add the dimensions of the array.  FIXME: This loses CV qualifiers from
-      // interior arrays, do we care?  Why aren't nested arrays represented the
-      // obvious/recursive way?
-      llvm::SmallVector Subscripts;
-
-      // There will be ARRAY_TYPE nodes for each rank.  Followed by the derived
-      // type.
-      tree atype = type;
-      tree EltTy = TREE_TYPE(atype);
-      for (; TREE_CODE(atype) == ARRAY_TYPE; atype = TREE_TYPE(atype)) {
-        tree Domain = TYPE_DOMAIN(atype);
-        if (Domain) {
-          // FIXME - handle dynamic ranges
-          tree MinValue = TYPE_MIN_VALUE(Domain);
-          tree MaxValue = TYPE_MAX_VALUE(Domain);
-          if (MinValue && MaxValue &&
-              isInt64(MinValue, 0) && isInt64(MaxValue, 0)) {
-            uint64_t Low = getInt64(MinValue, 0);
-            uint64_t Hi = getInt64(MaxValue, 0);
-            Subscripts.push_back(DebugFactory.GetOrCreateSubrange(Low, Hi));
-          }
-        }
-        EltTy = TREE_TYPE(atype);
-      }
-
-      llvm::DIArray SubscriptArray =
-        DebugFactory.GetOrCreateArray(&Subscripts[0], Subscripts.size());
-
-      Ty = DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_array_type,
-                                            MainCompileUnit, "", 
-                                            MainCompileUnit,
-                                            0, Size, Align, 0, 0,
-                                            getOrCreateType(EltTy),
-                                            SubscriptArray);
+    case ARRAY_TYPE: 
+      Ty = createArrayType(type);
       break;
-    }
     
-    case ENUMERAL_TYPE: {
-      // enum { a, b, ..., z };
-      llvm::SmallVector Elements;
-
-      if (TYPE_SIZE(type)) {
-        for (tree Link = TYPE_VALUES(type); Link; Link = TREE_CHAIN(Link)) {
-          tree EnumValue = TREE_VALUE(Link);
-          int64_t Value = getInt64(EnumValue, tree_int_cst_sgn(EnumValue) > 0);
-          const char *EnumName = IDENTIFIER_POINTER(TREE_PURPOSE(Link));
-          Elements.push_back(DebugFactory.CreateEnumerator(EnumName, Value));
-        }
-      }
-
-      llvm::DIArray EltArray =
-        DebugFactory.GetOrCreateArray(&Elements[0], Elements.size());
-
-      expanded_location Loc = GetNodeLocation(TREE_CHAIN(type), false);
-      std::string Filename, Directory;
-      DirectoryAndFile(Loc.file, Directory, Filename);
-      Ty = DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_enumeration_type,
-                                            MainCompileUnit, TypeName, 
-                                            MainCompileUnit, Loc.line,
-                                            Size, Align, 0, 0,
-                                            llvm::DIType(), EltArray,
-                                            &Filename, &Directory);
+    case ENUMERAL_TYPE: 
+      Ty = createEnumType(type);
       break;
-    }
     
     case RECORD_TYPE:
     case QUAL_UNION_TYPE:
-    case UNION_TYPE: {
-      // struct { a; b; ... z; }; | union { a; b; ... z; };
-      unsigned Tag = TREE_CODE(type) == RECORD_TYPE ? DW_TAG_structure_type :
-                                                      DW_TAG_union_type;
-
-      // Records and classes and unions can all be recursive.  To handle them,
-      // we first generate a debug descriptor for the struct as a forward 
-      // declaration. Then (if it is a definition) we go through and get debug 
-      // info for all of its members.  Finally, we create a descriptor for the
-      // complete type (which may refer to the forward decl if the struct is 
-      // recursive) and replace all  uses of the forward declaration with the 
-      // final definition. 
-      expanded_location Loc = GetNodeLocation(TREE_CHAIN(type), false);
-      std::string Filename, Directory;
-      DirectoryAndFile(Loc.file, Directory, Filename);
-      llvm::DIType FwdDecl =
-        DebugFactory.CreateCompositeType(Tag, MainCompileUnit, TypeName, 
-                                         MainCompileUnit, Loc.line, 
-                                         0, 0, 0, llvm::DIType::FlagFwdDecl,
-                                         llvm::DIType(), llvm::DIArray(),
-                                         &Filename, &Directory);
-  
-
-      // forward declaration, 
-      if (TYPE_SIZE(type) == 0) {
-        Ty = FwdDecl;
-        break;
-      }
-
-      // Insert into the TypeCache so that recursive uses will find it.
-      TypeCache[type] =  FwdDecl;
-
-      // Convert all the elements.
-      llvm::SmallVector EltTys;
-
-      if (tree binfo = TYPE_BINFO(type)) {
-        VEC (tree, gc) *accesses = BINFO_BASE_ACCESSES (binfo);
-        
-        for (unsigned i = 0, e = BINFO_N_BASE_BINFOS(binfo); i != e; ++i) {
-          tree BInfo = BINFO_BASE_BINFO(binfo, i);
-          tree BInfoType = BINFO_TYPE (BInfo);
-          DIType BaseClass = getOrCreateType(BInfoType);
-         
-          // FIXME : name, size, align etc...
-          DIType DTy = 
-            DebugFactory.CreateDerivedType(DW_TAG_inheritance, 
-                                           MainCompileUnit,"", 
-                                           MainCompileUnit, 0,0,0, 
-                                           getInt64(BINFO_OFFSET(BInfo), 0),
-                                           0, BaseClass);
-          EltTys.push_back(DTy);
-        }
-      }
-
-      // Now add members of this class.
-      for (tree Member = TYPE_FIELDS(type); Member;
-                Member = TREE_CHAIN(Member)) {
-        // Should we skip.
-        if (DECL_P(Member) && DECL_IGNORED_P(Member)) continue;
-
-        if (TREE_CODE(Member) == FIELD_DECL) {
-
-          if (DECL_FIELD_OFFSET(Member) == 0 ||
-              TREE_CODE(DECL_FIELD_OFFSET(Member)) != INTEGER_CST)
-            // FIXME: field with variable position, skip it for now.
-            continue;
-
-          /* Ignore nameless fields.  */
-          if (DECL_NAME (Member) == NULL_TREE)
-            continue;
-          
-          // Get the location of the member.
-          expanded_location MemLoc = GetNodeLocation(Member, false);
-          std::string MemFilename, MemDirectory;
-          DirectoryAndFile(MemLoc.file, MemDirectory, MemFilename);
-
-          // Field type is the declared type of the field.
-          tree FieldNodeType = FieldType(Member);
-          DIType MemberType = getOrCreateType(FieldNodeType);
-          const char *MemberName = GetNodeName(Member);
-          unsigned Flags = 0;
-          if (TREE_PROTECTED(Member))
-            Flags = llvm::DIType::FlagProtected;
-          else if (TREE_PRIVATE(Member))
-            Flags = llvm::DIType::FlagPrivate;
-
-          DIType DTy =
-            DebugFactory.CreateDerivedType(DW_TAG_member, MainCompileUnit, 
-                                           MemberName, MainCompileUnit,
-                                           MemLoc.line, NodeSizeInBits(Member),
-                                           NodeAlignInBits(FieldNodeType),
-                                           int_bit_position(Member), 
-                                           Flags, MemberType,
-                                           &MemFilename, &MemDirectory);
-          EltTys.push_back(DTy);
-        } else {
-          DEBUGASSERT(0 && "Unsupported member tree code!");
-        }
-      }
-
-      for (tree Member = TYPE_METHODS(type); Member;
-                Member = TREE_CHAIN(Member)) {
-                
-        if (DECL_ABSTRACT_ORIGIN (Member)) continue;
-
-        // Get the location of the member.
-        expanded_location MemLoc = GetNodeLocation(Member, false);
-        std::string MemFilename, MemDirectory;
-        DirectoryAndFile(MemLoc.file, MemDirectory, MemFilename);
-        
-        const char *MemberName = GetNodeName(Member);                
-        DIType SPTy = getOrCreateType(TREE_TYPE(Member));
-        DISubprogram SP = 
-          DebugFactory.CreateSubprogram(MainCompileUnit, MemberName, MemberName,
-                                        MemberName, MainCompileUnit, 
-                                        MemLoc.line, SPTy, false, false,
-                                        &MemFilename, &MemDirectory);
-
-        EltTys.push_back(SP);
-      }
-
-      llvm::DIArray Elements =
-        DebugFactory.GetOrCreateArray(&EltTys[0], EltTys.size());
-      
-      llvm::DIType RealDecl =
-        DebugFactory.CreateCompositeType(Tag, MainCompileUnit, TypeName, 
-                                         MainCompileUnit, Loc.line, Size,
-                                         Align, 0, 0, llvm::DIType(), Elements,
-                                         &Filename, &Directory);
-
-      // Now that we have a real decl for the struct, replace anything using the
-      // old decl with the new one.  This will recursively update the debug info.
-      FwdDecl.getGV()->replaceAllUsesWith(RealDecl.getGV());
-      FwdDecl.getGV()->eraseFromParent();
-      Ty = RealDecl;
-
+    case UNION_TYPE: 
+      Ty = createStructType(type);
       break;
-    }
 
     case INTEGER_TYPE:
     case REAL_TYPE:   
     case COMPLEX_TYPE:
-    case BOOLEAN_TYPE: {
-
-      unsigned Encoding = 0;
-
-      switch (TREE_CODE(type)) {
-        case INTEGER_TYPE:
-          if (TYPE_STRING_FLAG (type)) {
-            if (TYPE_UNSIGNED (type))
-              Encoding = DW_ATE_unsigned_char;
-            else
-              Encoding = DW_ATE_signed_char;
-          }
-          else if (TYPE_UNSIGNED (type))
-            Encoding = DW_ATE_unsigned;
-          else
-            Encoding = DW_ATE_signed;
-          break;
-        case REAL_TYPE:
-          Encoding = DW_ATE_float;
-          break;
-        case COMPLEX_TYPE:
-          Encoding = TREE_CODE(TREE_TYPE(type)) == REAL_TYPE ?
-            DW_ATE_complex_float : DW_ATE_lo_user;
-          break;
-        case BOOLEAN_TYPE:
-          Encoding = DW_ATE_boolean;
-          break;
-        default: { 
-          DEBUGASSERT(0 && "Basic type case missing");
-          Encoding = DW_ATE_signed;
-          Size = BITS_PER_WORD;
-          Align = BITS_PER_WORD;
-          break;
-        }
-      }
-      Ty = DebugFactory.CreateBasicType(MainCompileUnit, TypeName, 
-                                        MainCompileUnit, 0, Size, Align,
-                                        0, 0, Encoding);
-    }
+    case BOOLEAN_TYPE:
+      Ty = createBasicType(type);
+      break;
   }
   TypeCache[type] = Ty;
   return Ty;

Modified: llvm-gcc-4.2/branches/release_25/gcc/llvm-debug.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/release_25/gcc/llvm-debug.h?rev=63204&r1=63203&r2=63204&view=diff

==============================================================================
--- llvm-gcc-4.2/branches/release_25/gcc/llvm-debug.h (original)
+++ llvm-gcc-4.2/branches/release_25/gcc/llvm-debug.h Wed Jan 28 09:39:51 2009
@@ -108,6 +108,27 @@
   /// necessary.
   DIType getOrCreateType(tree_node *type);
 
+  /// createBasicType - Create BasicType.
+  DIType createBasicType(tree_node *type);
+
+  /// createMethodType - Create MethodType.
+  DIType createMethodType(tree_node *type);
+
+  /// createPointerType - Create PointerType.
+  DIType createPointerType(tree_node *type);
+
+  /// createArrayType - Create ArrayType.
+  DIType createArrayType(tree_node *type);
+
+  /// createEnumType - Create EnumType.
+  DIType createEnumType(tree_node *type);
+
+  /// createStructType - Create StructType for struct or union or class.
+  DIType createStructType(tree_node *type);
+
+  /// createVarinatType - Create variant type or return MainTy.
+  DIType createVariantType(tree_node *type, DIType MainTy);
+
   /// createCompileUnit - Create a new compile unit.
   DICompileUnit createCompileUnit(const std::string &FullPath);
   




From tonic at nondot.org  Wed Jan 28 09:40:46 2009
From: tonic at nondot.org (Tanya Lattner)
Date: Wed, 28 Jan 2009 15:40:46 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63205 -
	/llvm-gcc-4.2/branches/release_25/gcc/llvm-debug.cpp
Message-ID: <200901281540.n0SFekFE010505@zion.cs.uiuc.edu>

Author: tbrethou
Date: Wed Jan 28 09:40:46 2009
New Revision: 63205

URL: http://llvm.org/viewvc/llvm-project?rev=63205&view=rev
Log:
Merge from mainline.
Set function linkage name appropriately.
This allows debugger to find fn/methods.

Modified:
    llvm-gcc-4.2/branches/release_25/gcc/llvm-debug.cpp

Modified: llvm-gcc-4.2/branches/release_25/gcc/llvm-debug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/release_25/gcc/llvm-debug.cpp?rev=63205&r1=63204&r2=63205&view=diff

==============================================================================
--- llvm-gcc-4.2/branches/release_25/gcc/llvm-debug.cpp (original)
+++ llvm-gcc-4.2/branches/release_25/gcc/llvm-debug.cpp Wed Jan 28 09:40:46 2009
@@ -216,6 +216,7 @@
   expanded_location Loc = GetNodeLocation(FnDecl, false);
   std::string Filename, Directory;
   DirectoryAndFile(Loc.file, Directory, Filename);
+  const char *FnName = GetNodeName(FnDecl);
   const char *LinkageName = getLinkageName(FnDecl);
 
   tree func_type = TREE_TYPE(FnDecl);
@@ -240,8 +241,7 @@
                                      llvm::DIType(), FnTypeArray);
 
   DISubprogram SP = DebugFactory.CreateSubprogram(MainCompileUnit, 
-                                                  Fn->getNameStr(),
-                                                  Fn->getNameStr(), LinkageName,
+                                                  FnName, FnName, LinkageName,
                                                   MainCompileUnit, CurLineNo, 
                                                   FnTy, 
                                                   Fn->hasInternalLinkage(),
@@ -619,10 +619,11 @@
     DirectoryAndFile(MemLoc.file, MemDirectory, MemFilename);
     
     const char *MemberName = GetNodeName(Member);                
+    const char *LinkageName = getLinkageName(Member);
     DIType SPTy = getOrCreateType(TREE_TYPE(Member));
     DISubprogram SP = 
       DebugFactory.CreateSubprogram(MainCompileUnit, MemberName, MemberName,
-                                    MemberName, MainCompileUnit, 
+                                    LinkageName, MainCompileUnit, 
                                     MemLoc.line, SPTy, false, false,
                                     &MemFilename, &MemDirectory);
     




From tonic at nondot.org  Wed Jan 28 09:41:45 2009
From: tonic at nondot.org (Tanya Lattner)
Date: Wed, 28 Jan 2009 15:41:45 -0000
Subject: [llvm-commits] [llvm] r63206 -
 /llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
Message-ID: <200901281541.n0SFfjMD010551@zion.cs.uiuc.edu>

Author: tbrethou
Date: Wed Jan 28 09:41:45 2009
New Revision: 63206

URL: http://llvm.org/viewvc/llvm-project?rev=63206&view=rev
Log:
Merge from mainline.
Empty DIType represents void. In  this case no need to construct any type DIE.

Modified:
    llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp

Modified: llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=63206&r1=63205&r2=63206&view=diff

==============================================================================
--- llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Wed Jan 28 09:41:45 2009
@@ -1662,10 +1662,8 @@
 
   /// AddType - Add a new type attribute to the specified entity.
   void AddType(CompileUnit *DW_Unit, DIE *Entity, DIType Ty) {
-    if (Ty.isNull()) {
-      AddBasicType(Entity, DW_Unit, "", DW_ATE_signed, sizeof(int32_t));
+    if (Ty.isNull())
       return;
-    }
 
     // Check for pre-existence.
     DIEntry *&Slot = DW_Unit->getDIEntrySlotFor(Ty.getGV());




From tonic at nondot.org  Wed Jan 28 09:43:23 2009
From: tonic at nondot.org (Tanya Lattner)
Date: Wed, 28 Jan 2009 15:43:23 -0000
Subject: [llvm-commits] [llvm] r63207 - in
 /llvm/branches/release_25/lib/CodeGen/SelectionDAG: DAGCombiner.cpp
 SelectionDAG.cpp
Message-ID: <200901281543.n0SFhNMf010637@zion.cs.uiuc.edu>

Author: tbrethou
Date: Wed Jan 28 09:43:23 2009
New Revision: 63207

URL: http://llvm.org/viewvc/llvm-project?rev=63207&view=rev
Log:
Merge from mainline.

Fold x-0 to x in unsafe-fp-math mode. This comes up in the
testcase from PR3376, and in fact is sufficient to completely
avoid the problem in that testcase.

There's an underlying problem though; TLI.isOperationLegal
considers Custom to be Legal, which might be ok in some
cases, but that's what DAGCombiner is using in many places
to test if something is legal when LegalOperations is true.
When DAGCombiner is running after legalize, this isn't
sufficient. I'll address this in a separate commit.

Modified:
    llvm/branches/release_25/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/branches/release_25/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63207&r1=63206&r2=63207&view=diff

==============================================================================
--- llvm/branches/release_25/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/branches/release_25/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Jan 28 09:43:23 2009
@@ -3851,6 +3851,9 @@
   // fold (fsub c1, c2) -> c1-c2
   if (N0CFP && N1CFP && VT != MVT::ppcf128)
     return DAG.getNode(ISD::FSUB, VT, N0, N1);
+  // fold (A-0) -> A
+  if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
+    return N0;
   // fold (0-B) -> -B
   if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
     if (isNegatibleForFree(N1, LegalOperations))

Modified: llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63207&r1=63206&r2=63207&view=diff

==============================================================================
--- llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jan 28 09:43:23 2009
@@ -2387,15 +2387,22 @@
   case ISD::FMUL:
   case ISD::FDIV:
   case ISD::FREM:
-    if (UnsafeFPMath && Opcode == ISD::FADD) {
-      // 0+x --> x
-      if (ConstantFPSDNode *CFP = dyn_cast(N1))
-        if (CFP->getValueAPF().isZero())
-          return N2;
-      // x+0 --> x
-      if (ConstantFPSDNode *CFP = dyn_cast(N2))
-        if (CFP->getValueAPF().isZero())
-          return N1;
+    if (UnsafeFPMath) {
+      if (Opcode == ISD::FADD) {
+        // 0+x --> x
+        if (ConstantFPSDNode *CFP = dyn_cast(N1))
+          if (CFP->getValueAPF().isZero())
+            return N2;
+        // x+0 --> x
+        if (ConstantFPSDNode *CFP = dyn_cast(N2))
+          if (CFP->getValueAPF().isZero())
+            return N1;
+      } else if (Opcode == ISD::FSUB) {
+        // x-0 --> x
+        if (ConstantFPSDNode *CFP = dyn_cast(N2))
+          if (CFP->getValueAPF().isZero())
+            return N1;
+      }
     }
     assert(N1.getValueType() == N2.getValueType() &&
            N1.getValueType() == VT && "Binary operator types must match!");




From tonic at nondot.org  Wed Jan 28 09:53:06 2009
From: tonic at nondot.org (Tanya Lattner)
Date: Wed, 28 Jan 2009 15:53:06 -0000
Subject: [llvm-commits] [llvm] r63209 - in /llvm/branches/release_25:
 lib/CodeGen/AsmPrinter/DwarfWriter.cpp test/DebugInfo/forwardDecl.ll
Message-ID: <200901281553.n0SFr6rg011022@zion.cs.uiuc.edu>

Author: tbrethou
Date: Wed Jan 28 09:53:06 2009
New Revision: 63209

URL: http://llvm.org/viewvc/llvm-project?rev=63209&view=rev
Log:
Merge from mainline.
Assorted debug info fixes.
- DW_AT_bit_size is only suitable for bitfields.
- Encode source location info for derived types.
- Source location and type size info is not useful for subroutine_type (info is included in respective DISubprogram) and array_type.


Modified:
    llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
    llvm/branches/release_25/test/DebugInfo/forwardDecl.ll

Modified: llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=63209&r1=63208&r2=63209&view=diff

==============================================================================
--- llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/branches/release_25/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Wed Jan 28 09:53:06 2009
@@ -1733,8 +1733,8 @@
 
     // Add source line info if available and TyDesc is not a forward
     // declaration.
-    // FIXME - Enable this. if (!DTy.isForwardDecl())
-    // FIXME - Enable this.     AddSourceLine(&Buffer, *DTy);
+    if (!DTy.isForwardDecl())
+      AddSourceLine(&Buffer, &DTy);
   }
 
   /// ConstructTypeDIE - Construct type DIE from DICompositeType.
@@ -1815,20 +1815,23 @@
     // Add name if not anonymous or intermediate type.
     if (!Name.empty()) AddString(&Buffer, DW_AT_name, DW_FORM_string, Name);
 
-    // Add size if non-zero (derived types might be zero-sized.)
-    if (Size)
-      AddUInt(&Buffer, DW_AT_byte_size, 0, Size);
-    else {
-      // Add zero size if it is not a forward declaration.
-      if (CTy.isForwardDecl())
-        AddUInt(&Buffer, DW_AT_declaration, DW_FORM_flag, 1);
-      else
-        AddUInt(&Buffer, DW_AT_byte_size, 0, 0); 
+    if (Tag == DW_TAG_enumeration_type || Tag == DW_TAG_structure_type
+        || Tag == DW_TAG_union_type) {
+      // Add size if non-zero (derived types might be zero-sized.)
+      if (Size)
+        AddUInt(&Buffer, DW_AT_byte_size, 0, Size);
+      else {
+        // Add zero size if it is not a forward declaration.
+        if (CTy.isForwardDecl())
+          AddUInt(&Buffer, DW_AT_declaration, DW_FORM_flag, 1);
+        else
+          AddUInt(&Buffer, DW_AT_byte_size, 0, 0); 
+      }
+      
+      // Add source line info if available.
+      if (!CTy.isForwardDecl())
+        AddSourceLine(&Buffer, &CTy);
     }
-
-    // Add source line info if available.
-    if (!CTy.isForwardDecl())
-      AddSourceLine(&Buffer, &CTy);
   }
   
   // ConstructSubrangeDIE - Construct subrange DIE from DISubrange.
@@ -1853,7 +1856,6 @@
       AddUInt(&Buffer, DW_AT_GNU_vector, DW_FORM_flag, 1);
     
     DIArray Elements = CTy->getTypeArray();
-    AddType(DW_Unit, &Buffer, CTy->getTypeDerivedFrom());
 
     // Construct an anonymous type for index type.
     DIE IdxBuffer(DW_TAG_base_type);
@@ -1906,7 +1908,7 @@
 
     AddSourceLine(MemberDie, &DT);
 
-    AddUInt(MemberDie, DW_AT_bit_size, 0, DT.getSizeInBits());
+    // FIXME _ Handle bitfields
     DIEBlock *Block = new DIEBlock();
     AddUInt(Block, 0, DW_FORM_data1, DW_OP_plus_uconst);
     AddUInt(Block, 0, DW_FORM_udata, DT.getOffsetInBits() >> 3);

Modified: llvm/branches/release_25/test/DebugInfo/forwardDecl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/test/DebugInfo/forwardDecl.ll?rev=63209&r1=63208&r2=63209&view=diff

==============================================================================
--- llvm/branches/release_25/test/DebugInfo/forwardDecl.ll (original)
+++ llvm/branches/release_25/test/DebugInfo/forwardDecl.ll Wed Jan 28 09:53:06 2009
@@ -18,7 +18,7 @@
 @.str3 = internal constant [4 x i8] c"foo\00", section "llvm.metadata"		; <[4 x i8]*> [#uses=1]
 @llvm.dbg.variable = internal constant %llvm.dbg.variable.type { i32 393473, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([2 x i8]* @.str4, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 3, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*) }, section "llvm.metadata"		; <%llvm.dbg.variable.type*> [#uses=1]
 @.str4 = internal constant [2 x i8] c"x\00", section "llvm.metadata"		; <[2 x i8]*> [#uses=1]
- at llvm.dbg.derivedtype = internal constant %llvm.dbg.derivedtype.type { i32 393231, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype to { }*) }, section "llvm.metadata"		; <%llvm.dbg.derivedtype.type*> [#uses=1]
+ at llvm.dbg.derivedtype = internal constant %llvm.dbg.derivedtype.type { i32 393231, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype to { }*) }, section "llvm.metadata"		; <%llvm.dbg.derivedtype.type*> [#uses=1]
 @llvm.dbg.compositetype = internal constant %llvm.dbg.compositetype.type { i32 393235, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([3 x i8]* @.str5, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 1, i64 0, i64 8, i64 0, i32 4, { }* null, { }* bitcast ([0 x { }*]* @llvm.dbg.array to { }*) }, section "llvm.metadata"		; <%llvm.dbg.compositetype.type*> [#uses=1]
 @.str5 = internal constant [3 x i8] c"ST\00", section "llvm.metadata"		; <[3 x i8]*> [#uses=1]
 @llvm.dbg.array = internal constant [0 x { }*] zeroinitializer, section "llvm.metadata"		; <[0 x { }*]*> [#uses=1]




From gohman at apple.com  Wed Jan 28 11:46:26 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 28 Jan 2009 17:46:26 -0000
Subject: [llvm-commits] [llvm] r63212 - in /llvm/trunk:
 include/llvm/Target/TargetLowering.h
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
 lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
 lib/CodeGen/SelectionDAG/TargetLowering.cpp
Message-ID: <200901281746.n0SHkQXZ015196@zion.cs.uiuc.edu>

Author: djg
Date: Wed Jan 28 11:46:25 2009
New Revision: 63212

URL: http://llvm.org/viewvc/llvm-project?rev=63212&view=rev
Log:
Make isOperationLegal do what its name suggests, and introduce a
new isOperationLegalOrCustom, which does what isOperationLegal
previously did.

Update a bunch of callers to use isOperationLegalOrCustom
instead of isOperationLegal. In some case it wasn't obvious
which behavior is desired; when in doubt I changed then to
isOperationLegalOrCustom as that preserves their previous
behavior.

This is for the second half of PR3376.

Modified:
    llvm/trunk/include/llvm/Target/TargetLowering.h
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=63212&r1=63211&r2=63212&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Wed Jan 28 11:46:25 2009
@@ -340,12 +340,20 @@
     return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3);
   }
 
+  /// isOperationLegalOrCustom - Return true if the specified operation is
+  /// legal on this target or can be made legal with custom lowering. This
+  /// is used to help guide high-level lowering decisions.
+  bool isOperationLegalOrCustom(unsigned Op, MVT VT) const {
+    return (VT == MVT::Other || isTypeLegal(VT)) &&
+      (getOperationAction(Op, VT) == Legal ||
+       getOperationAction(Op, VT) == Custom);
+  }
+
   /// isOperationLegal - Return true if the specified operation is legal on this
   /// target.
   bool isOperationLegal(unsigned Op, MVT VT) const {
     return (VT == MVT::Other || isTypeLegal(VT)) &&
-      (getOperationAction(Op, VT) == Legal ||
-       getOperationAction(Op, VT) == Custom);
+           getOperationAction(Op, VT) == Legal;
   }
 
   /// getLoadExtAction - Return how this load with extension should be treated:

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63212&r1=63211&r2=63212&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Jan 28 11:46:25 2009
@@ -2054,8 +2054,8 @@
   if (!TLI.isTypeLegal(VT)) return 0;
 
   // The target must have at least one rotate flavor.
-  bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
-  bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
+  bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
+  bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
   if (!HasROTL && !HasROTR) return 0;
 
   // Match "(X shl/srl V1) & V2" where V2 may not be present.
@@ -2541,8 +2541,8 @@
       // on that type, and the the truncate to that type is both legal and free,
       // perform the transform.
       if (ShiftAmt &&
-          TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) &&
-          TLI.isOperationLegal(ISD::TRUNCATE, VT) &&
+          TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
+          TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
           TLI.isTruncateFree(VT, TruncVT)) {
 
           SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy());
@@ -2795,7 +2795,7 @@
     // Check against MVT::Other for SELECT_CC, which is a workaround for targets
     // having to say they don't support SELECT_CC on every type the DAG knows
     // about, since there is no way to mark an opcode illegal at all value types
-    if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
+    if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other))
       return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
                          N1, N2, N0.getOperand(2));
     else
@@ -4032,8 +4032,8 @@
   
   // If the input is a legal type, and SINT_TO_FP is not legal on this target,
   // but UINT_TO_FP is legal on this target, try to convert.
-  if (!TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT) &&
-      TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT)) {
+  if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
+      TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
     // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 
     if (DAG.SignBitIsZero(N0))
       return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
@@ -4055,8 +4055,8 @@
   
   // If the input is a legal type, and UINT_TO_FP is not legal on this target,
   // but SINT_TO_FP is legal on this target, try to convert.
-  if (!TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT) &&
-      TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT)) {
+  if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
+      TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
     // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 
     if (DAG.SignBitIsZero(N0))
       return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
@@ -4252,7 +4252,7 @@
   // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
   // on the target.
   if (N1.getOpcode() == ISD::SETCC && 
-      TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
+      TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
     return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
                        N1.getOperand(0), N1.getOperand(1), N2);
   }
@@ -4726,7 +4726,7 @@
       getABITypeAlignment(SVT.getTypeForMVT());
     if (Align <= OrigAlign &&
         ((!LegalOperations && !ST->isVolatile()) ||
-         TLI.isOperationLegal(ISD::STORE, SVT)))
+         TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
       return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
                           ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign);
   }
@@ -4747,7 +4747,8 @@
         break;
       case MVT::f32:
         if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations &&
-             !ST->isVolatile()) || TLI.isOperationLegal(ISD::STORE, MVT::i32)) {
+             !ST->isVolatile()) ||
+            TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
           Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
                               bitcastToAPInt().getZExtValue(), MVT::i32);
           return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
@@ -4757,14 +4758,15 @@
         break;
       case MVT::f64:
         if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations &&
-             !ST->isVolatile()) || TLI.isOperationLegal(ISD::STORE, MVT::i64)) {
+             !ST->isVolatile()) ||
+            TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
           Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
                                   getZExtValue(), MVT::i64);
           return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
                               ST->getSrcValueOffset(), ST->isVolatile(),
                               ST->getAlignment());
         } else if (!ST->isVolatile() &&
-                   TLI.isOperationLegal(ISD::STORE, MVT::i32)) {
+                   TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
           // Many FP stores are not made apparent until after legalize, e.g. for
           // argument passing.  Since this is so common, custom legalize the
           // 64-bit integer store into two 32-bit stores.
@@ -4967,7 +4969,7 @@
       // original load.
       unsigned NewAlign = TLI.getTargetData()->
         getABITypeAlignment(LVT.getTypeForMVT());
-      if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT))
+      if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
         return SDValue();
       Align = NewAlign;
     }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63212&r1=63211&r2=63212&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jan 28 11:46:25 2009
@@ -1263,8 +1263,9 @@
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Expand: {
       DwarfWriter *DW = DAG.getDwarfWriter();
-      bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
-      bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
+      bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
+                                                       MVT::Other);
+      bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
       
       const DbgStopPointSDNode *DSP = cast(Node);
       GlobalVariable *CU_GV = cast(DSP->getCompileUnit());
@@ -3065,7 +3066,7 @@
                "Fell off of the edge of the floating point world");
           
         // If the target supports SETCC of this type, use it.
-        if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
+        if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy))
           break;
       }
       if (NewInTy.isInteger())
@@ -3228,10 +3229,10 @@
         // and unsigned forms. If the target supports both SMUL_LOHI and
         // UMUL_LOHI, form a preference by checking which forms of plain
         // MULH it supports.
-        bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
-        bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
-        bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
-        bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
+        bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
+        bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
+        bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
+        bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
         unsigned OpToUse = 0;
         if (HasSMUL_LOHI && !HasMULHS) {
           OpToUse = ISD::SMUL_LOHI;
@@ -3248,25 +3249,25 @@
         }
       }
       if (Node->getOpcode() == ISD::MULHS &&
-          TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
+          TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
         Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
                          1);
         break;
       }
       if (Node->getOpcode() == ISD::MULHU && 
-          TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
+          TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
         Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
                          1);
         break;
       }
       if (Node->getOpcode() == ISD::SDIV &&
-          TLI.isOperationLegal(ISD::SDIVREM, VT)) {
+          TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
         Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(),
                          0);
         break;
       }
       if (Node->getOpcode() == ISD::UDIV &&
-          TLI.isOperationLegal(ISD::UDIVREM, VT)) {
+          TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
         Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(),
                          0);
         break;
@@ -3510,12 +3511,12 @@
       // See if remainder can be lowered using two-result operations.
       SDVTList VTs = DAG.getVTList(VT, VT);
       if (Node->getOpcode() == ISD::SREM &&
-          TLI.isOperationLegal(ISD::SDIVREM, VT)) {
+          TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
         Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
         break;
       }
       if (Node->getOpcode() == ISD::UREM &&
-          TLI.isOperationLegal(ISD::UDIVREM, VT)) {
+          TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
         Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
         break;
       }
@@ -4639,8 +4640,8 @@
     // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
     // legal, such as PowerPC.
     if (Node->getOpcode() == ISD::FP_TO_UINT && 
-        !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
-        (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
+        !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
+        (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) ||
          TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
       Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
     } else {
@@ -5549,7 +5550,8 @@
                                         &MaskVec[0], MaskVec.size());
 
     // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
-    if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
+    if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR,
+                                     Node->getValueType(0)) &&
         isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
       Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
       Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
@@ -6330,8 +6332,8 @@
     SDValue Tmp3 = DAG.getNode(ISD::AND, VT, DAG.getNOT(Op, VT),
                        DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
     // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
-    if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
-        TLI.isOperationLegal(ISD::CTLZ, VT))
+    if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
+        TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
       return DAG.getNode(ISD::SUB, VT,
                          DAG.getConstant(VT.getSizeInBits(), VT),
                          DAG.getNode(ISD::CTLZ, VT, Tmp3));
@@ -6821,8 +6823,9 @@
     // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 
     // this X << 1 as X+X.
     if (ConstantSDNode *ShAmt = dyn_cast(ShiftAmt)) {
-      if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 
-          TLI.isOperationLegal(ISD::ADDE, NVT)) {
+      if (ShAmt->getAPIntValue() == 1 &&
+          TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) && 
+          TLI.isOperationLegalOrCustom(ISD::ADDE, NVT)) {
         SDValue LoOps[2], HiOps[3];
         ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
         SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
@@ -6944,7 +6947,7 @@
     bool hasCarry = false;
     for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
       MVT AVT = MVT::getIntegerVT(BitSize);
-      if (TLI.isOperationLegal(OpV, AVT)) {
+      if (TLI.isOperationLegalOrCustom(OpV, AVT)) {
         hasCarry = true;
         break;
       }
@@ -7041,10 +7044,10 @@
       }
     }
     
-    bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
-    bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
-    bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
-    bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
+    bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
+    bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
+    bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
+    bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
     if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
       SDValue LL, LH, RL, RH;
       ExpandOp(Node->getOperand(0), LL, LH);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=63212&r1=63211&r2=63212&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Wed Jan 28 11:46:25 2009
@@ -345,8 +345,8 @@
   // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
   // legal, such as PowerPC.
   if (N->getOpcode() == ISD::FP_TO_UINT &&
-      !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
-      TLI.isOperationLegal(ISD::FP_TO_SINT, NVT))
+      !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
+      TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
     NewOpc = ISD::FP_TO_SINT;
 
   SDValue Res = DAG.getNode(NewOpc, NVT, N->getOperand(0));
@@ -1008,7 +1008,8 @@
       Lo = DAG.getConstant(0, NVT);
       Hi = InL;
     } else if (Amt == 1 &&
-               TLI.isOperationLegal(ISD::ADDC, TLI.getTypeToExpandTo(NVT))) {
+               TLI.isOperationLegalOrCustom(ISD::ADDC,
+                                            TLI.getTypeToExpandTo(NVT))) {
       // Emit this X << 1 as X+X.
       SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
       SDValue LoOps[2] = { InL, InL };
@@ -1166,8 +1167,9 @@
   // a carry of type MVT::Flag, but there doesn't seem to be any way to
   // generate a value of this type in the expanded code sequence.
   bool hasCarry =
-    TLI.isOperationLegal(N->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC,
-                         TLI.getTypeToExpandTo(NVT));
+    TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
+                                   ISD::ADDC : ISD::SUBC,
+                                 TLI.getTypeToExpandTo(NVT));
 
   if (hasCarry) {
     SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
@@ -1513,10 +1515,10 @@
   MVT VT = N->getValueType(0);
   MVT NVT = TLI.getTypeToTransformTo(VT);
 
-  bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
-  bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
-  bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
-  bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
+  bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
+  bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
+  bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
+  bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
   if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
     SDValue LL, LH, RL, RH;
     GetExpandedInteger(N->getOperand(0), LL, LH);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63212&r1=63211&r2=63212&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Wed Jan 28 11:46:25 2009
@@ -1588,8 +1588,8 @@
 
 static inline bool areJTsAllowed(const TargetLowering &TLI) {
   return !DisableJumpTables &&
-          (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
-           TLI.isOperationLegal(ISD::BRIND, MVT::Other));
+          (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
+           TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
 }
 
 static APInt ComputeRange(const APInt &First, const APInt &Last) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=63212&r1=63211&r2=63212&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Jan 28 11:46:25 2009
@@ -2365,10 +2365,10 @@
   // Multiply the numerator (operand 0) by the magic value
   // FIXME: We should support doing a MUL in a wider type
   SDValue Q;
-  if (isOperationLegal(ISD::MULHS, VT))
+  if (isOperationLegalOrCustom(ISD::MULHS, VT))
     Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
                     DAG.getConstant(magics.m, VT));
-  else if (isOperationLegal(ISD::SMUL_LOHI, VT))
+  else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
     Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT),
                               N->getOperand(0),
                               DAG.getConstant(magics.m, VT)).getNode(), 1);
@@ -2423,10 +2423,10 @@
   // Multiply the numerator (operand 0) by the magic value
   // FIXME: We should support doing a MUL in a wider type
   SDValue Q;
-  if (isOperationLegal(ISD::MULHU, VT))
+  if (isOperationLegalOrCustom(ISD::MULHU, VT))
     Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
                     DAG.getConstant(magics.m, VT));
-  else if (isOperationLegal(ISD::UMUL_LOHI, VT))
+  else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
     Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT),
                               N->getOperand(0),
                               DAG.getConstant(magics.m, VT)).getNode(), 1);




From sabre at nondot.org  Wed Jan 28 11:49:03 2009
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 28 Jan 2009 17:49:03 -0000
Subject: [llvm-commits] [llvm] r63213 - in /llvm/trunk: CMakeLists.txt
 include/llvm/Config/config.h.cmake
Message-ID: <200901281749.n0SHn34W015282@zion.cs.uiuc.edu>

Author: lattner
Date: Wed Jan 28 11:49:03 2009
New Revision: 63213

URL: http://llvm.org/viewvc/llvm-project?rev=63213&view=rev
Log:
Enable PACKAGE_VERSION in cmake builds, this unbreaks the clang build with cmake.
Patch by Piotr Rak!

Modified:
    llvm/trunk/CMakeLists.txt
    llvm/trunk/include/llvm/Config/config.h.cmake

Modified: llvm/trunk/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=63213&r1=63212&r2=63213&view=diff

==============================================================================
--- llvm/trunk/CMakeLists.txt (original)
+++ llvm/trunk/CMakeLists.txt Wed Jan 28 11:49:03 2009
@@ -2,7 +2,8 @@
 cmake_minimum_required(VERSION 2.6.1)
 
 set(PACKAGE_NAME llvm)
-set(PACKAGE_VERSION svn)
+set(PACKAGE_VERSION 2.6svn)
+set(PACKAGE_STRING "${PACKAGE_NAME} ${PACKAGE_VERSION}")
 set(PACKAGE_BUGREPORT "llvmbugs at cs.uiuc.edu")
 
 if( CMAKE_SOURCE_DIR STREQUAL CMAKE_BINARY_DIR AND NOT MSVC_IDE )

Modified: llvm/trunk/include/llvm/Config/config.h.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.cmake?rev=63213&r1=63212&r2=63213&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Config/config.h.cmake (original)
+++ llvm/trunk/include/llvm/Config/config.h.cmake Wed Jan 28 11:49:03 2009
@@ -507,7 +507,7 @@
 #cmakedefine PACKAGE_NAME "${PACKAGE_NAME}"
 
 /* Define to the full name and version of this package. */
-#undef PACKAGE_STRING
+#cmakedefine PACKAGE_STRING "${PACKAGE_STRING}"
 
 /* Define to the one symbol short name of this package. */
 #undef PACKAGE_TARNAME




From gohman at apple.com  Wed Jan 28 12:03:10 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 28 Jan 2009 18:03:10 -0000
Subject: [llvm-commits] [llvm] r63214 -
	/llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h
Message-ID: <200901281803.n0SI3A3q015745@zion.cs.uiuc.edu>

Author: djg
Date: Wed Jan 28 12:03:09 2009
New Revision: 63214

URL: http://llvm.org/viewvc/llvm-project?rev=63214&view=rev
Log:
Delete unnecessary elses.

Modified:
    llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h

Modified: llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h?rev=63214&r1=63213&r2=63214&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h (original)
+++ llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h Wed Jan 28 12:03:09 2009
@@ -31,9 +31,9 @@
 static bool IsChainCompatible(SDNode *Chain, SDNode *Op) {
   if (Chain->getOpcode() == ISD::EntryToken)
     return true;
-  else if (Chain->getOpcode() == ISD::TokenFactor)
+  if (Chain->getOpcode() == ISD::TokenFactor)
     return false;
-  else if (Chain->getNumOperands() > 0) {
+  if (Chain->getNumOperands() > 0) {
     SDValue C0 = Chain->getOperand(0);
     if (C0.getValueType() == MVT::Other)
       return C0.getNode() != Op && IsChainCompatible(C0.getNode(), Op);




From edwintorok at gmail.com  Wed Jan 28 12:21:54 2009
From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=)
Date: Wed, 28 Jan 2009 20:21:54 +0200
Subject: [llvm-commits] Turning off SSE codegen for x86-64?
In-Reply-To: <200901252021.n0PKLO2s029035@zion.cs.uiuc.edu>
References: <200901252021.n0PKLO2s029035@zion.cs.uiuc.edu>
Message-ID: <4980A242.7060401@gmail.com>

On 2009-01-25 22:21, Torok Edwin wrote:
> Author: edwin
> Date: Sun Jan 25 14:21:24 2009
> New Revision: 62972
>
> URL: http://llvm.org/viewvc/llvm-project?rev=62972&view=rev
> Log:
> revert this patch for now, because Codegen does still want to generate SSE code,
> for example in the case of va-args. XFAIL associated tests.
>   

Hi Evan,

Can you please look at these bugreports and see if there is a way to
solve both?
http://llvm.org/bugs/show_bug.cgi?id=3402
http://llvm.org/bugs/show_bug.cgi?id=3403

My attempt to solve PR3402 (by allowing X86SSELevel to be 0 for x86-64)
caused PR3403, so I reverted that patch.
Are there other placesin codegen (other than va_arg I found in PR3403) 
that assume x86sselevel > 0 without actually
checking that flag?

Turning off SSE codegen for x86-64 is needed to compile kernel code,
like the Linux kernel.

Best regards,
--Edwin


From dpatel at apple.com  Wed Jan 28 12:46:54 2009
From: dpatel at apple.com (Devang Patel)
Date: Wed, 28 Jan 2009 18:46:54 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63216 - in
 /llvm-gcc-4.2/branches/Apple/Dib/gcc: llvm-backend.cpp llvm-debug.cpp
Message-ID: <200901281846.n0SIksuY017313@zion.cs.uiuc.edu>

Author: dpatel
Date: Wed Jan 28 12:46:54 2009
New Revision: 63216

URL: http://llvm.org/viewvc/llvm-project?rev=63216&view=rev
Log:
Undo following patch for now.

----
Set DW_AT_APPLE_optimized and DW_AT_APPLE_flags attribute while building
DICompileUnit.

Right now, llvm-gcc does not emit debug info when optimization is ON. However,
emit llvm.dbg.compile_unit and preserve it even when optimization is ON. This
allows DW_AT_APPLE_flags to find its way in final binary.
----


Modified:
    llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-backend.cpp
    llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.cpp

Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-backend.cpp?rev=63216&r1=63215&r2=63216&view=diff

==============================================================================
--- llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-backend.cpp Wed Jan 28 12:46:54 2009
@@ -592,13 +592,6 @@
     writeLLVMValues();
   }
 
-  if (!flag_pch_file 
-      && optimize && debug_info_level > DINFO_LEVEL_NONE && !TheDebugInfo) {
-    DebugInfo DI(TheModule);
-    DICompileUnit CU = DI.createCompileUnit(main_input_filename);
-    AttributeUsedGlobals.insert(CU.getGV());
-  }
-
   // Add an llvm.global_ctors global if needed.
   if (!StaticCtors.empty())
     CreateStructorsList(StaticCtors, "llvm.global_ctors");

Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.cpp?rev=63216&r1=63215&r2=63216&view=diff

==============================================================================
--- llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.cpp (original)
+++ llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-debug.cpp Wed Jan 28 12:46:54 2009
@@ -828,15 +828,8 @@
   else
     LangTag = DW_LANG_C89;
 
-  const char *Flags = "";
-  // Do this only when RC_DEBUG_OPTIONS environment variable is set to 
-  // a nonempty string. This is intended only for internal Apple use. 
-  char * debugopt = getenv("RC_DEBUG_OPTIONS");
-  if (debugopt && debugopt[0])
-    Flags = get_arguments();
-
   return DebugFactory.CreateCompileUnit(LangTag, FileName, Directory, 
-                                        version_string, optimize, Flags);
+                                        version_string);
 }
 
 /* LLVM LOCAL end (ENTIRE FILE!)  */




From wangmp at apple.com  Wed Jan 28 12:53:39 2009
From: wangmp at apple.com (Mon P Wang)
Date: Wed, 28 Jan 2009 18:53:39 -0000
Subject: [llvm-commits] [llvm] r63217 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
Message-ID: <200901281853.n0SIrdjg017535@zion.cs.uiuc.edu>

Author: wangmp
Date: Wed Jan 28 12:53:39 2009
New Revision: 63217

URL: http://llvm.org/viewvc/llvm-project?rev=63217&view=rev
Log:
Fixed extract element when the result needs to be promoted and the input widened.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=63217&r1=63216&r2=63217&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Wed Jan 28 12:53:39 2009
@@ -292,6 +292,8 @@
 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
   MVT OldVT = N->getValueType(0);
   SDValue OldVec = N->getOperand(0);
+  if (getTypeAction(OldVec.getValueType()) == WidenVector)
+    OldVec = GetWidenedVector(N->getOperand(0));
   unsigned OldElts = OldVec.getValueType().getVectorNumElements();
 
   if (OldElts == 1) {




From dpatel at apple.com  Wed Jan 28 13:26:38 2009
From: dpatel at apple.com (Devang Patel)
Date: Wed, 28 Jan 2009 19:26:38 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63221 - in /llvm-gcc-4.2/trunk/gcc:
 llvm-backend.cpp llvm-debug.cpp
Message-ID: <200901281926.n0SJQc3l018684@zion.cs.uiuc.edu>

Author: dpatel
Date: Wed Jan 28 13:26:38 2009
New Revision: 63221

URL: http://llvm.org/viewvc/llvm-project?rev=63221&view=rev
Log:

Undo following patch for now.

----
Set DW_AT_APPLE_optimized and DW_AT_APPLE_flags attribute while building
DICompileUnit.

Right now, llvm-gcc does not emit debug info when optimization is ON. However,
emit llvm.dbg.compile_unit and preserve it even when optimization is ON. This
allows DW_AT_APPLE_flags to find its way in final binary.
----


Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
    llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=63221&r1=63220&r2=63221&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Wed Jan 28 13:26:38 2009
@@ -595,13 +595,6 @@
     writeLLVMValues();
   }
 
-  if (!flag_pch_file 
-      && optimize && debug_info_level > DINFO_LEVEL_NONE && !TheDebugInfo) {
-    DebugInfo DI(TheModule);
-    DICompileUnit CU = DI.createCompileUnit(main_input_filename);
-    AttributeUsedGlobals.insert(CU.getGV());
-  }
-
   // Add an llvm.global_ctors global if needed.
   if (!StaticCtors.empty())
     CreateStructorsList(StaticCtors, "llvm.global_ctors");

Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp?rev=63221&r1=63220&r2=63221&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Wed Jan 28 13:26:38 2009
@@ -828,15 +828,8 @@
   else
     LangTag = DW_LANG_C89;
 
-  const char *Flags = "";
-  // Do this only when RC_DEBUG_OPTIONS environment variable is set to 
-  // a nonempty string. This is intended only for internal Apple use. 
-  char * debugopt = getenv("RC_DEBUG_OPTIONS");
-  if (debugopt && debugopt[0])
-    Flags = get_arguments();
-
   return DebugFactory.CreateCompileUnit(LangTag, FileName, Directory, 
-                                        version_string, optimize, Flags);
+                                        version_string);
 }
 
 /* LLVM LOCAL end (ENTIRE FILE!)  */




From sabre at nondot.org  Wed Jan 28 13:29:31 2009
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 28 Jan 2009 19:29:31 -0000
Subject: [llvm-commits] [llvm] r63222 -
	/llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll
Message-ID: <200901281929.n0SJTVLo018778@zion.cs.uiuc.edu>

Author: lattner
Date: Wed Jan 28 13:29:30 2009
New Revision: 63222

URL: http://llvm.org/viewvc/llvm-project?rev=63222&view=rev
Log:
strengthen this test.

Modified:
    llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll

Modified: llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll?rev=63222&r1=63221&r2=63222&view=diff

==============================================================================
--- llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll (original)
+++ llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll Wed Jan 28 13:29:30 2009
@@ -1,6 +1,5 @@
-; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | \
-; RUN:   not grep alloca
-; END.
+; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | not grep alloca
+; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | grep {load <4 x float>}
 
 define void @test(<4 x float>* %F, float %f) {
 entry:




From isanbard at gmail.com  Wed Jan 28 13:31:24 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 28 Jan 2009 19:31:24 -0000
Subject: [llvm-commits] [llvm] r63224 - /llvm/tags/Apple/llvmCore-2095/
Message-ID: <200901281931.n0SJVOXd018862@zion.cs.uiuc.edu>

Author: void
Date: Wed Jan 28 13:31:24 2009
New Revision: 63224

URL: http://llvm.org/viewvc/llvm-project?rev=63224&view=rev
Log:
Tagging Dib as llvmCore-2095.

Added:
    llvm/tags/Apple/llvmCore-2095/
      - copied from r63223, llvm/branches/Apple/Dib/



From isanbard at gmail.com  Wed Jan 28 13:31:54 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 28 Jan 2009 19:31:54 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63225 -
	/llvm-gcc-4.2/tags/Apple/llvmgcc42-2095/
Message-ID: <200901281931.n0SJVsDx018893@zion.cs.uiuc.edu>

Author: void
Date: Wed Jan 28 13:31:54 2009
New Revision: 63225

URL: http://llvm.org/viewvc/llvm-project?rev=63225&view=rev
Log:
Tagging Dib as llvmgcc42-2095.

Added:
    llvm-gcc-4.2/tags/Apple/llvmgcc42-2095/
      - copied from r63224, llvm-gcc-4.2/branches/Apple/Dib/



From evan.cheng at apple.com  Wed Jan 28 13:34:29 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 28 Jan 2009 11:34:29 -0800
Subject: [llvm-commits] Turning off SSE codegen for x86-64?
In-Reply-To: <4980A242.7060401@gmail.com>
References: <200901252021.n0PKLO2s029035@zion.cs.uiuc.edu>
	<4980A242.7060401@gmail.com>
Message-ID: 


On Jan 28, 2009, at 10:21 AM, T?r?k Edwin wrote:

> On 2009-01-25 22:21, Torok Edwin wrote:
>> Author: edwin
>> Date: Sun Jan 25 14:21:24 2009
>> New Revision: 62972
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=62972&view=rev
>> Log:
>> revert this patch for now, because Codegen does still want to  
>> generate SSE code,
>> for example in the case of va-args. XFAIL associated tests.
>>
>
> Hi Evan,
>
> Can you please look at these bugreports and see if there is a way to
> solve both?
> http://llvm.org/bugs/show_bug.cgi?id=3402
> http://llvm.org/bugs/show_bug.cgi?id=3403
>
> My attempt to solve PR3402 (by allowing X86SSELevel to be 0 for  
> x86-64)
> caused PR3403, so I reverted that patch.
> Are there other placesin codegen (other than va_arg I found in PR3403)
> that assume x86sselevel > 0 without actually
> checking that flag?

Unfortunately there is no trivial fix for this. I think some  
vector_shuffle lowering code (and perhaps more) in X86ISelLowering.cpp  
assumes SSE2 is available in 64-bit mode. This will require someone  
walking through the code to fix all the cases.

Evan

>
>
> Turning off SSE codegen for x86-64 is needed to compile kernel code,
> like the Linux kernel.
>
> Best regards,
> --Edwin




From edwintorok at gmail.com  Wed Jan 28 14:09:44 2009
From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=)
Date: Wed, 28 Jan 2009 22:09:44 +0200
Subject: [llvm-commits] Turning off SSE codegen for x86-64?
In-Reply-To: 
References: <200901252021.n0PKLO2s029035@zion.cs.uiuc.edu>
	<4980A242.7060401@gmail.com>
	
Message-ID: <4980BB88.3080409@gmail.com>

On 2009-01-28 21:34, Evan Cheng wrote:
>
> On Jan 28, 2009, at 10:21 AM, T?r?k Edwin wrote:
>
>> On 2009-01-25 22:21, Torok Edwin wrote:
>>> Author: edwin
>>> Date: Sun Jan 25 14:21:24 2009
>>> New Revision: 62972
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=62972&view=rev
>>> Log:
>>> revert this patch for now, because Codegen does still want to
>>> generate SSE code,
>>> for example in the case of va-args. XFAIL associated tests.
>>>
>>
>> Hi Evan,
>>
>> Can you please look at these bugreports and see if there is a way to
>> solve both?
>> http://llvm.org/bugs/show_bug.cgi?id=3402
>> http://llvm.org/bugs/show_bug.cgi?id=3403
>>
>> My attempt to solve PR3402 (by allowing X86SSELevel to be 0 for x86-64)
>> caused PR3403, so I reverted that patch.
>> Are there other placesin codegen (other than va_arg I found in PR3403)
>> that assume x86sselevel > 0 without actually
>> checking that flag?
>
> Unfortunately there is no trivial fix for this. I think some
> vector_shuffle lowering code (and perhaps more) in X86ISelLowering.cpp
> assumes SSE2 is available in 64-bit mode. This will require someone
> walking through the code to fix all the cases.

Do you think an iterative bugfiling/bugfixing approach would be good?
I can test the code, file bugs where unexpected SSE code is generated,
when they are fixed, compile again, file more bugs, and so on till its done?

So far I found that functions with va-args get SSE registers pushed on
the stack on x86-64/linux.
Could you point me to the place where this happens in llvm codegen? If
its not too complicated I may try to propose a patch when I find some time.


Best regards,
--Edwin


From sabre at nondot.org  Wed Jan 28 14:16:43 2009
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 28 Jan 2009 20:16:43 -0000
Subject: [llvm-commits] [llvm] r63227 - in /llvm/trunk:
 lib/Transforms/Scalar/ScalarReplAggregates.cpp
 test/Transforms/ScalarRepl/volatile.ll
Message-ID: <200901282016.n0SKGh3h020480@zion.cs.uiuc.edu>

Author: lattner
Date: Wed Jan 28 14:16:43 2009
New Revision: 63227

URL: http://llvm.org/viewvc/llvm-project?rev=63227&view=rev
Log:
Fix some issues with volatility, move "CanConvertToScalar" check 
after the others.

Added:
    llvm/trunk/test/Transforms/ScalarRepl/volatile.ll
Modified:
    llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=63227&r1=63226&r2=63227&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Wed Jan 28 14:16:43 2009
@@ -123,7 +123,7 @@
     void RewriteStoreUserOfWholeAlloca(StoreInst *SI, AllocationInst *AI,
                                        SmallVector &NewElts);
     void RewriteLoadUserOfWholeAlloca(LoadInst *LI, AllocationInst *AI,
-                                       SmallVector &NewElts);
+                                      SmallVector &NewElts);
     
     const Type *CanConvertToScalar(Value *V, bool &IsNotTrivial);
     void ConvertToScalar(AllocationInst *AI, const Type *Ty);
@@ -224,16 +224,6 @@
       continue;
     }
     
-    // If we can turn this aggregate value (potentially with casts) into a
-    // simple scalar value that can be mem2reg'd into a register value.
-    bool IsNotTrivial = false;
-    if (const Type *ActualType = CanConvertToScalar(AI, IsNotTrivial))
-      if (IsNotTrivial && ActualType != Type::VoidTy) {
-        ConvertToScalar(AI, ActualType);
-        Changed = true;
-        continue;
-      }
-
     // Check to see if we can perform the core SROA transformation.  We cannot
     // transform the allocation instruction if it is an array allocation
     // (allocations OF arrays are ok though), and an allocation of a scalar
@@ -278,7 +268,17 @@
       Changed = true;
       continue;
     }
-        
+
+    // If we can turn this aggregate value (potentially with casts) into a
+    // simple scalar value that can be mem2reg'd into a register value.
+    bool IsNotTrivial = false;
+    if (const Type *ActualType = CanConvertToScalar(AI, IsNotTrivial))
+      if (IsNotTrivial && ActualType != Type::VoidTy) {
+        ConvertToScalar(AI, ActualType);
+        Changed = true;
+        continue;
+      }
+    
     // Otherwise, couldn't process this.
   }
 
@@ -476,11 +476,13 @@
   if (BitCastInst *C = dyn_cast(User))
     return isSafeUseOfBitCastedAllocation(C, AI, Info);
 
-  if (isa(User))
-    return; // Loads (returning a first class aggregrate) are always rewritable
-
-  if (isa(User) && User->getOperand(0) != AI)
-    return; // Store is ok if storing INTO the pointer, not storing the pointer
+  if (LoadInst *LI = dyn_cast(User))
+    if (!LI->isVolatile())
+      return;// Loads (returning a first class aggregrate) are always rewritable
+
+  if (StoreInst *SI = dyn_cast(User))
+    if (!SI->isVolatile() && SI->getOperand(0) != AI)
+      return;// Store is ok if storing INTO the pointer, not storing the pointer
  
   GetElementPtrInst *GEPI = dyn_cast(User);
   if (GEPI == 0)
@@ -590,6 +592,9 @@
     } else if (MemIntrinsic *MI = dyn_cast(UI)) {
       isSafeMemIntrinsicOnAllocation(MI, AI, UI.getOperandNo(), Info);
     } else if (StoreInst *SI = dyn_cast(UI)) {
+      if (SI->isVolatile())
+        return MarkUnsafe(Info);
+      
       // If storing the entire alloca in one chunk through a bitcasted pointer
       // to integer, we can transform it.  This happens (for example) when you
       // cast a {i32,i32}* to i64* and store through it.  This is similar to the
@@ -602,6 +607,9 @@
       }
       return MarkUnsafe(Info);
     } else if (LoadInst *LI = dyn_cast(UI)) {
+      if (LI->isVolatile())
+        return MarkUnsafe(Info);
+
       // If loading the entire alloca in one chunk through a bitcasted pointer
       // to integer, we can transform it.  This happens (for example) when you
       // cast a {i32,i32}* to i64* and load through it.  This is similar to the
@@ -1234,6 +1242,9 @@
     Instruction *User = cast(*UI);
     
     if (LoadInst *LI = dyn_cast(User)) {
+      if (LI->isVolatile())
+        return 0;
+
       // FIXME: Loads of a first class aggregrate value could be converted to a
       // series of loads and insertvalues
       if (!LI->getType()->isSingleValueType())
@@ -1246,7 +1257,7 @@
     
     if (StoreInst *SI = dyn_cast(User)) {
       // Storing the pointer, not into the value?
-      if (SI->getOperand(0) == V) return 0;
+      if (SI->getOperand(0) == V || SI->isVolatile()) return 0;
 
       // FIXME: Stores of a first class aggregrate value could be converted to a
       // series of extractvalues and stores
@@ -1653,10 +1664,11 @@
 static bool isOnlyCopiedFromConstantGlobal(Value *V, Instruction *&TheCopy,
                                            bool isOffset) {
   for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI!=E; ++UI) {
-    if (isa(*UI)) {
-      // Ignore loads, they are always ok.
-      continue;
-    }
+    if (LoadInst *LI = dyn_cast(*UI))
+      // Ignore non-volatile loads, they are always ok.
+      if (!LI->isVolatile())
+        continue;
+    
     if (BitCastInst *BCI = dyn_cast(*UI)) {
       // If uses of the bitcast are ok, we are ok.
       if (!isOnlyCopiedFromConstantGlobal(BCI, TheCopy, isOffset))

Added: llvm/trunk/test/Transforms/ScalarRepl/volatile.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/volatile.ll?rev=63227&view=auto

==============================================================================
--- llvm/trunk/test/Transforms/ScalarRepl/volatile.ll (added)
+++ llvm/trunk/test/Transforms/ScalarRepl/volatile.ll Wed Jan 28 14:16:43 2009
@@ -0,0 +1,12 @@
+; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | grep {volatile load}
+; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | grep {volatile store}
+
+define i32 @voltest(i32 %T) {
+	%A = alloca {i32, i32}
+	%B = getelementptr {i32,i32}* %A, i32 0, i32 0
+	volatile store i32 %T, i32* %B
+
+	%C = getelementptr {i32,i32}* %A, i32 0, i32 1
+	%X = volatile load i32* %C
+	ret i32 %X
+}




From dpatel at apple.com  Wed Jan 28 15:08:21 2009
From: dpatel at apple.com (Devang Patel)
Date: Wed, 28 Jan 2009 21:08:21 -0000
Subject: [llvm-commits] [llvm] r63233 - in /llvm/trunk:
 lib/CodeGen/AsmPrinter/DwarfWriter.cpp
 test/DebugInfo/2009-01-28-ArrayType.ll
Message-ID: <200901282108.n0SL8LGr022314@zion.cs.uiuc.edu>

Author: dpatel
Date: Wed Jan 28 15:08:20 2009
New Revision: 63233

URL: http://llvm.org/viewvc/llvm-project?rev=63233&view=rev
Log:

Do not forget to derived type while constructing an array type.

Added:
    llvm/trunk/test/DebugInfo/2009-01-28-ArrayType.ll
Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=63233&r1=63232&r2=63233&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Wed Jan 28 15:08:20 2009
@@ -1869,6 +1869,8 @@
     if (CTy->getTag() == DW_TAG_vector_type)
       AddUInt(&Buffer, DW_AT_GNU_vector, DW_FORM_flag, 1);
     
+    // Emit derived type.
+    AddType(DW_Unit, &Buffer, CTy->getTypeDerivedFrom());    
     DIArray Elements = CTy->getTypeArray();
 
     // Construct an anonymous type for index type.

Added: llvm/trunk/test/DebugInfo/2009-01-28-ArrayType.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2009-01-28-ArrayType.ll?rev=63233&view=auto

==============================================================================
--- llvm/trunk/test/DebugInfo/2009-01-28-ArrayType.ll (added)
+++ llvm/trunk/test/DebugInfo/2009-01-28-ArrayType.ll Wed Jan 28 15:08:20 2009
@@ -0,0 +1,93 @@
+; RUN: llvm-as < %s | llc | grep 0x49 | count 7
+; Count number of DW_AT_Type attributes.
+	%llvm.dbg.anchor.type = type { i32, i32 }
+	%llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32, i8*, i8* }
+	%llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i8* }
+	%llvm.dbg.composite.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, { }*, i8*, i8* }
+	%llvm.dbg.derivedtype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, i8*, i8* }
+	%llvm.dbg.subprogram.type = type { i32, { }*, { }*, i8*, i8*, i8*, { }*, i32, { }*, i1, i1, i8*, i8* }
+	%llvm.dbg.subrange.type = type { i32, i64, i64 }
+	%llvm.dbg.variable.type = type { i32, { }*, i8*, { }*, i32, { }*, i8*, i8* }
+ at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata"		; <%llvm.dbg.anchor.type*> [#uses=1]
+ at .str = internal constant [4 x i8] c"a.c\00", section "llvm.metadata"		; <[4 x i8]*> [#uses=1]
+ at .str1 = internal constant [26 x i8] c"/Volumes/Nanpura/dbg.test\00", section "llvm.metadata"		; <[26 x i8]*> [#uses=1]
+ at .str2 = internal constant [52 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build)\00", section "llvm.metadata"		; <[52 x i8]*> [#uses=1]
+ at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([52 x i8]* @.str2, i32 0, i32 0), i1 false, i8* null }, section "llvm.metadata"		; <%llvm.dbg.compile_unit.type*> [#uses=1]
+ at .str3 = internal constant [4 x i8] c"int\00", section "llvm.metadata"		; <[4 x i8]*> [#uses=1]
+ at llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, i32 5, i8* null, i8* null }, section "llvm.metadata"		; <%llvm.dbg.basictype.type*> [#uses=1]
+ at .str4 = internal constant [5 x i8] c"char\00", section "llvm.metadata"		; <[5 x i8]*> [#uses=1]
+ at llvm.dbg.basictype5 = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([5 x i8]* @.str4, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 8, i64 8, i64 0, i32 0, i32 6, i8* null, i8* null }, section "llvm.metadata"		; <%llvm.dbg.basictype.type*> [#uses=1]
+ at llvm.dbg.derivedtype = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype5 to { }*), i8* null, i8* null }, section "llvm.metadata"		; <%llvm.dbg.derivedtype.type*> [#uses=1]
+ at llvm.dbg.derivedtype6 = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*), i8* null, i8* null }, section "llvm.metadata"		; <%llvm.dbg.derivedtype.type*> [#uses=1]
+ at llvm.dbg.array = internal constant [3 x { }*] [ { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype6 to { }*) ], section "llvm.metadata"		; <[3 x { }*]*> [#uses=1]
+ at llvm.dbg.composite = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array to { }*), i8* null, i8* null }, section "llvm.metadata"		; <%llvm.dbg.composite.type*> [#uses=1]
+ at llvm.dbg.subprograms = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 46 }, section "llvm.metadata"		; <%llvm.dbg.anchor.type*> [#uses=1]
+ at .str7 = internal constant [5 x i8] c"main\00", section "llvm.metadata"		; <[5 x i8]*> [#uses=1]
+ at llvm.dbg.subprogram = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([5 x i8]* @.str7, i32 0, i32 0), i8* getelementptr ([5 x i8]* @.str7, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 3, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite to { }*), i1 false, i1 true, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0) }, section "llvm.metadata"		; <%llvm.dbg.subprogram.type*> [#uses=1]
+ at .str8 = internal constant [5 x i8] c"argc\00", section "llvm.metadata"		; <[5 x i8]*> [#uses=1]
+ at llvm.dbg.variable = internal constant %llvm.dbg.variable.type { i32 459009, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([5 x i8]* @.str8, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 2, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0) }, section "llvm.metadata"		; <%llvm.dbg.variable.type*> [#uses=1]
+ at .str9 = internal constant [5 x i8] c"argv\00", section "llvm.metadata"		; <[5 x i8]*> [#uses=1]
+ at llvm.dbg.variable10 = internal constant %llvm.dbg.variable.type { i32 459009, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([5 x i8]* @.str9, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 2, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype6 to { }*), i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0) }, section "llvm.metadata"		; <%llvm.dbg.variable.type*> [#uses=1]
+ at llvm.dbg.subrange = internal constant %llvm.dbg.subrange.type { i32 458785, i64 0, i64 5 }, section "llvm.metadata"		; <%llvm.dbg.subrange.type*> [#uses=1]
+ at llvm.dbg.array11 = internal constant [1 x { }*] [ { }* bitcast (%llvm.dbg.subrange.type* @llvm.dbg.subrange to { }*) ], section "llvm.metadata"		; <[1 x { }*]*> [#uses=1]
+ at llvm.dbg.composite12 = internal constant %llvm.dbg.composite.type { i32 458753, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 48, i64 8, i64 0, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype5 to { }*), { }* bitcast ([1 x { }*]* @llvm.dbg.array11 to { }*), i8* null, i8* null }, section "llvm.metadata"		; <%llvm.dbg.composite.type*> [#uses=1]
+ at .str13 = internal constant [5 x i8] c"str1\00", section "llvm.metadata"		; <[5 x i8]*> [#uses=1]
+ at llvm.dbg.variable14 = internal constant %llvm.dbg.variable.type { i32 459008, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([5 x i8]* @.str13, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 4, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite12 to { }*), i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0) }, section "llvm.metadata"		; <%llvm.dbg.variable.type*> [#uses=1]
+@"\01LC" = internal constant [6 x i8] c"a.out\00"		; <[6 x i8]*> [#uses=6]
+
+define i32 @main(i32 %argc, i8** %argv) nounwind {
+entry:
+	%argc_addr = alloca i32		;  [#uses=2]
+	%argv_addr = alloca i8**		;  [#uses=2]
+	%retval = alloca i32		;  [#uses=2]
+	%str1 = alloca [6 x i8]		; <[6 x i8]*> [#uses=7]
+	%0 = alloca i32		;  [#uses=2]
+	%"alloca point" = bitcast i32 0 to i32		;  [#uses=0]
+	call void @llvm.dbg.func.start({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*))
+	%1 = bitcast i32* %argc_addr to { }*		; <{ }*> [#uses=1]
+	call void @llvm.dbg.declare({ }* %1, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable to { }*))
+	store i32 %argc, i32* %argc_addr
+	%2 = bitcast i8*** %argv_addr to { }*		; <{ }*> [#uses=1]
+	call void @llvm.dbg.declare({ }* %2, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable10 to { }*))
+	store i8** %argv, i8*** %argv_addr
+	%3 = bitcast [6 x i8]* %str1 to { }*		; <{ }*> [#uses=1]
+	call void @llvm.dbg.declare({ }* %3, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable14 to { }*))
+	call void @llvm.dbg.stoppoint(i32 4, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*))
+	%4 = getelementptr [6 x i8]* %str1, i32 0, i32 0		;  [#uses=1]
+	%5 = load i8* getelementptr ([6 x i8]* @"\01LC", i32 0, i32 0), align 1		;  [#uses=1]
+	store i8 %5, i8* %4, align 1
+	%6 = getelementptr [6 x i8]* %str1, i32 0, i32 1		;  [#uses=1]
+	%7 = load i8* getelementptr ([6 x i8]* @"\01LC", i32 0, i32 1), align 1		;  [#uses=1]
+	store i8 %7, i8* %6, align 1
+	%8 = getelementptr [6 x i8]* %str1, i32 0, i32 2		;  [#uses=1]
+	%9 = load i8* getelementptr ([6 x i8]* @"\01LC", i32 0, i32 2), align 1		;  [#uses=1]
+	store i8 %9, i8* %8, align 1
+	%10 = getelementptr [6 x i8]* %str1, i32 0, i32 3		;  [#uses=1]
+	%11 = load i8* getelementptr ([6 x i8]* @"\01LC", i32 0, i32 3), align 1		;  [#uses=1]
+	store i8 %11, i8* %10, align 1
+	%12 = getelementptr [6 x i8]* %str1, i32 0, i32 4		;  [#uses=1]
+	%13 = load i8* getelementptr ([6 x i8]* @"\01LC", i32 0, i32 4), align 1		;  [#uses=1]
+	store i8 %13, i8* %12, align 1
+	%14 = getelementptr [6 x i8]* %str1, i32 0, i32 5		;  [#uses=1]
+	%15 = load i8* getelementptr ([6 x i8]* @"\01LC", i32 0, i32 5), align 1		;  [#uses=1]
+	store i8 %15, i8* %14, align 1
+	call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*))
+	store i32 0, i32* %0, align 4
+	%16 = load i32* %0, align 4		;  [#uses=1]
+	store i32 %16, i32* %retval, align 4
+	br label %return
+
+return:		; preds = %entry
+	%retval1 = load i32* %retval		;  [#uses=1]
+	call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*))
+	call void @llvm.dbg.region.end({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*))
+	ret i32 %retval1
+}
+
+declare void @llvm.dbg.func.start({ }*) nounwind
+
+declare void @llvm.dbg.declare({ }*, { }*) nounwind
+
+declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind
+
+declare void @llvm.dbg.region.end({ }*) nounwind




From gohman at apple.com  Wed Jan 28 15:13:09 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 28 Jan 2009 21:13:09 -0000
Subject: [llvm-commits] [llvm] r63234 -
	/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
Message-ID: <200901282113.n0SLD9p5022491@zion.cs.uiuc.edu>

Author: djg
Date: Wed Jan 28 15:13:08 2009
New Revision: 63234

URL: http://llvm.org/viewvc/llvm-project?rev=63234&view=rev
Log:
Add some comments on ISD::NodeType.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=63234&r1=63233&r2=63234&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Jan 28 15:13:08 2009
@@ -63,6 +63,13 @@
   /// ISD::NodeType enum - This enum defines all of the operators valid in a
   /// SelectionDAG.
   ///
+  /// These are sometimes called the target-independent operators; targets
+  /// may also define target-dependent operators. For example, on x86, these
+  /// are the enum values in the X86ISD namespace. Targets should aim to use
+  /// target-independent operators to model their instruction sets as much
+  /// as possible, and only use target-dependent operators when they have
+  /// special requirements.
+  ///
   enum NodeType {
     // DELETED_NODE - This is an illegal flag value that is used to catch
     // errors.  This opcode is not a legal opcode for any node.




From isanbard at gmail.com  Wed Jan 28 15:14:50 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 28 Jan 2009 21:14:50 -0000
Subject: [llvm-commits] [llvm] r63235 - in /llvm/branches/Apple/Dib:
 lib/CodeGen/AsmPrinter/DwarfWriter.cpp
 test/DebugInfo/2009-01-28-ArrayType.ll
Message-ID: <200901282114.n0SLEo9X022556@zion.cs.uiuc.edu>

Author: void
Date: Wed Jan 28 15:14:50 2009
New Revision: 63235

URL: http://llvm.org/viewvc/llvm-project?rev=63235&view=rev
Log:
Pull r63233 into Dib:

Do not forget to derived type while constructing an array type.

Added:
    llvm/branches/Apple/Dib/test/DebugInfo/2009-01-28-ArrayType.ll
Modified:
    llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp

Modified: llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=63235&r1=63234&r2=63235&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Wed Jan 28 15:14:50 2009
@@ -1869,6 +1869,8 @@
     if (CTy->getTag() == DW_TAG_vector_type)
       AddUInt(&Buffer, DW_AT_GNU_vector, DW_FORM_flag, 1);
     
+    // Emit derived type.
+    AddType(DW_Unit, &Buffer, CTy->getTypeDerivedFrom());    
     DIArray Elements = CTy->getTypeArray();
 
     // Construct an anonymous type for index type.

Added: llvm/branches/Apple/Dib/test/DebugInfo/2009-01-28-ArrayType.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/DebugInfo/2009-01-28-ArrayType.ll?rev=63235&view=auto

==============================================================================
--- llvm/branches/Apple/Dib/test/DebugInfo/2009-01-28-ArrayType.ll (added)
+++ llvm/branches/Apple/Dib/test/DebugInfo/2009-01-28-ArrayType.ll Wed Jan 28 15:14:50 2009
@@ -0,0 +1,93 @@
+; RUN: llvm-as < %s | llc | grep 0x49 | count 7
+; Count number of DW_AT_Type attributes.
+	%llvm.dbg.anchor.type = type { i32, i32 }
+	%llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32, i8*, i8* }
+	%llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i8* }
+	%llvm.dbg.composite.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, { }*, i8*, i8* }
+	%llvm.dbg.derivedtype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, i8*, i8* }
+	%llvm.dbg.subprogram.type = type { i32, { }*, { }*, i8*, i8*, i8*, { }*, i32, { }*, i1, i1, i8*, i8* }
+	%llvm.dbg.subrange.type = type { i32, i64, i64 }
+	%llvm.dbg.variable.type = type { i32, { }*, i8*, { }*, i32, { }*, i8*, i8* }
+ at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata"		; <%llvm.dbg.anchor.type*> [#uses=1]
+ at .str = internal constant [4 x i8] c"a.c\00", section "llvm.metadata"		; <[4 x i8]*> [#uses=1]
+ at .str1 = internal constant [26 x i8] c"/Volumes/Nanpura/dbg.test\00", section "llvm.metadata"		; <[26 x i8]*> [#uses=1]
+ at .str2 = internal constant [52 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build)\00", section "llvm.metadata"		; <[52 x i8]*> [#uses=1]
+ at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([52 x i8]* @.str2, i32 0, i32 0), i1 false, i8* null }, section "llvm.metadata"		; <%llvm.dbg.compile_unit.type*> [#uses=1]
+ at .str3 = internal constant [4 x i8] c"int\00", section "llvm.metadata"		; <[4 x i8]*> [#uses=1]
+ at llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, i32 5, i8* null, i8* null }, section "llvm.metadata"		; <%llvm.dbg.basictype.type*> [#uses=1]
+ at .str4 = internal constant [5 x i8] c"char\00", section "llvm.metadata"		; <[5 x i8]*> [#uses=1]
+ at llvm.dbg.basictype5 = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([5 x i8]* @.str4, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 8, i64 8, i64 0, i32 0, i32 6, i8* null, i8* null }, section "llvm.metadata"		; <%llvm.dbg.basictype.type*> [#uses=1]
+ at llvm.dbg.derivedtype = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype5 to { }*), i8* null, i8* null }, section "llvm.metadata"		; <%llvm.dbg.derivedtype.type*> [#uses=1]
+ at llvm.dbg.derivedtype6 = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*), i8* null, i8* null }, section "llvm.metadata"		; <%llvm.dbg.derivedtype.type*> [#uses=1]
+ at llvm.dbg.array = internal constant [3 x { }*] [ { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype6 to { }*) ], section "llvm.metadata"		; <[3 x { }*]*> [#uses=1]
+ at llvm.dbg.composite = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array to { }*), i8* null, i8* null }, section "llvm.metadata"		; <%llvm.dbg.composite.type*> [#uses=1]
+ at llvm.dbg.subprograms = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 46 }, section "llvm.metadata"		; <%llvm.dbg.anchor.type*> [#uses=1]
+ at .str7 = internal constant [5 x i8] c"main\00", section "llvm.metadata"		; <[5 x i8]*> [#uses=1]
+ at llvm.dbg.subprogram = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([5 x i8]* @.str7, i32 0, i32 0), i8* getelementptr ([5 x i8]* @.str7, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 3, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite to { }*), i1 false, i1 true, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0) }, section "llvm.metadata"		; <%llvm.dbg.subprogram.type*> [#uses=1]
+ at .str8 = internal constant [5 x i8] c"argc\00", section "llvm.metadata"		; <[5 x i8]*> [#uses=1]
+ at llvm.dbg.variable = internal constant %llvm.dbg.variable.type { i32 459009, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([5 x i8]* @.str8, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 2, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0) }, section "llvm.metadata"		; <%llvm.dbg.variable.type*> [#uses=1]
+ at .str9 = internal constant [5 x i8] c"argv\00", section "llvm.metadata"		; <[5 x i8]*> [#uses=1]
+ at llvm.dbg.variable10 = internal constant %llvm.dbg.variable.type { i32 459009, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([5 x i8]* @.str9, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 2, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype6 to { }*), i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0) }, section "llvm.metadata"		; <%llvm.dbg.variable.type*> [#uses=1]
+ at llvm.dbg.subrange = internal constant %llvm.dbg.subrange.type { i32 458785, i64 0, i64 5 }, section "llvm.metadata"		; <%llvm.dbg.subrange.type*> [#uses=1]
+ at llvm.dbg.array11 = internal constant [1 x { }*] [ { }* bitcast (%llvm.dbg.subrange.type* @llvm.dbg.subrange to { }*) ], section "llvm.metadata"		; <[1 x { }*]*> [#uses=1]
+ at llvm.dbg.composite12 = internal constant %llvm.dbg.composite.type { i32 458753, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 48, i64 8, i64 0, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype5 to { }*), { }* bitcast ([1 x { }*]* @llvm.dbg.array11 to { }*), i8* null, i8* null }, section "llvm.metadata"		; <%llvm.dbg.composite.type*> [#uses=1]
+ at .str13 = internal constant [5 x i8] c"str1\00", section "llvm.metadata"		; <[5 x i8]*> [#uses=1]
+ at llvm.dbg.variable14 = internal constant %llvm.dbg.variable.type { i32 459008, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([5 x i8]* @.str13, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 4, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite12 to { }*), i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0) }, section "llvm.metadata"		; <%llvm.dbg.variable.type*> [#uses=1]
+@"\01LC" = internal constant [6 x i8] c"a.out\00"		; <[6 x i8]*> [#uses=6]
+
+define i32 @main(i32 %argc, i8** %argv) nounwind {
+entry:
+	%argc_addr = alloca i32		;  [#uses=2]
+	%argv_addr = alloca i8**		;  [#uses=2]
+	%retval = alloca i32		;  [#uses=2]
+	%str1 = alloca [6 x i8]		; <[6 x i8]*> [#uses=7]
+	%0 = alloca i32		;  [#uses=2]
+	%"alloca point" = bitcast i32 0 to i32		;  [#uses=0]
+	call void @llvm.dbg.func.start({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*))
+	%1 = bitcast i32* %argc_addr to { }*		; <{ }*> [#uses=1]
+	call void @llvm.dbg.declare({ }* %1, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable to { }*))
+	store i32 %argc, i32* %argc_addr
+	%2 = bitcast i8*** %argv_addr to { }*		; <{ }*> [#uses=1]
+	call void @llvm.dbg.declare({ }* %2, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable10 to { }*))
+	store i8** %argv, i8*** %argv_addr
+	%3 = bitcast [6 x i8]* %str1 to { }*		; <{ }*> [#uses=1]
+	call void @llvm.dbg.declare({ }* %3, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable14 to { }*))
+	call void @llvm.dbg.stoppoint(i32 4, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*))
+	%4 = getelementptr [6 x i8]* %str1, i32 0, i32 0		;  [#uses=1]
+	%5 = load i8* getelementptr ([6 x i8]* @"\01LC", i32 0, i32 0), align 1		;  [#uses=1]
+	store i8 %5, i8* %4, align 1
+	%6 = getelementptr [6 x i8]* %str1, i32 0, i32 1		;  [#uses=1]
+	%7 = load i8* getelementptr ([6 x i8]* @"\01LC", i32 0, i32 1), align 1		;  [#uses=1]
+	store i8 %7, i8* %6, align 1
+	%8 = getelementptr [6 x i8]* %str1, i32 0, i32 2		;  [#uses=1]
+	%9 = load i8* getelementptr ([6 x i8]* @"\01LC", i32 0, i32 2), align 1		;  [#uses=1]
+	store i8 %9, i8* %8, align 1
+	%10 = getelementptr [6 x i8]* %str1, i32 0, i32 3		;  [#uses=1]
+	%11 = load i8* getelementptr ([6 x i8]* @"\01LC", i32 0, i32 3), align 1		;  [#uses=1]
+	store i8 %11, i8* %10, align 1
+	%12 = getelementptr [6 x i8]* %str1, i32 0, i32 4		;  [#uses=1]
+	%13 = load i8* getelementptr ([6 x i8]* @"\01LC", i32 0, i32 4), align 1		;  [#uses=1]
+	store i8 %13, i8* %12, align 1
+	%14 = getelementptr [6 x i8]* %str1, i32 0, i32 5		;  [#uses=1]
+	%15 = load i8* getelementptr ([6 x i8]* @"\01LC", i32 0, i32 5), align 1		;  [#uses=1]
+	store i8 %15, i8* %14, align 1
+	call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*))
+	store i32 0, i32* %0, align 4
+	%16 = load i32* %0, align 4		;  [#uses=1]
+	store i32 %16, i32* %retval, align 4
+	br label %return
+
+return:		; preds = %entry
+	%retval1 = load i32* %retval		;  [#uses=1]
+	call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*))
+	call void @llvm.dbg.region.end({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*))
+	ret i32 %retval1
+}
+
+declare void @llvm.dbg.func.start({ }*) nounwind
+
+declare void @llvm.dbg.declare({ }*, { }*) nounwind
+
+declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind
+
+declare void @llvm.dbg.region.end({ }*) nounwind




From dalej at apple.com  Wed Jan 28 15:18:29 2009
From: dalej at apple.com (Dale Johannesen)
Date: Wed, 28 Jan 2009 21:18:29 -0000
Subject: [llvm-commits] [llvm] r63236 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAGNodes.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Message-ID: <200901282118.n0SLITIW022671@zion.cs.uiuc.edu>

Author: johannes
Date: Wed Jan 28 15:18:29 2009
New Revision: 63236

URL: http://llvm.org/viewvc/llvm-project?rev=63236&view=rev
Log:
Add DebugLoc-aware constructors for SDNode derived
classes (those that reasonably have a DebugLoc
associated with them).


Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=63236&r1=63235&r2=63236&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Jan 28 15:18:29 2009
@@ -1519,6 +1519,10 @@
     : SDNode(Opc, VTs) {
     InitOperands(&Op, X);
   }
+  UnarySDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, SDValue X)
+    : SDNode(Opc, dl, VTs) {
+    InitOperands(&Op, X);
+  }
 };
 
 /// BinarySDNode - This class is used for two-operand SDNodes.  This is solely
@@ -1530,6 +1534,10 @@
     : SDNode(Opc, VTs) {
     InitOperands(Ops, X, Y);
   }
+  BinarySDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, SDValue X, SDValue Y)
+    : SDNode(Opc, dl, VTs) {
+    InitOperands(Ops, X, Y);
+  }
 };
 
 /// TernarySDNode - This class is used for three-operand SDNodes. This is solely
@@ -1542,6 +1550,11 @@
     : SDNode(Opc, VTs) {
     InitOperands(Ops, X, Y, Z);
   }
+  TernarySDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, SDValue X, SDValue Y,
+                SDValue Z)
+    : SDNode(Opc, dl, VTs) {
+    InitOperands(Ops, X, Y, Z);
+  }
 };
 
 
@@ -1591,6 +1604,14 @@
             MVT MemoryVT, const Value *srcValue, int SVOff,
             unsigned alignment, bool isvolatile);
 
+  MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT MemoryVT,
+            const Value *srcValue, int SVOff,
+            unsigned alignment, bool isvolatile);
+
+  MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, const SDValue *Ops, 
+            unsigned NumOps, MVT MemoryVT, const Value *srcValue, int SVOff,
+            unsigned alignment, bool isvolatile);
+
   /// Returns alignment and volatility of the memory access
   unsigned getAlignment() const { return (1u << (Flags >> 1)) >> 1; }
   bool isVolatile() const { return Flags & 1; }
@@ -1669,6 +1690,21 @@
                 Align, /*isVolatile=*/true) {
     InitOperands(Ops, Chain, Ptr, Val);
   }
+  AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, MVT MemVT,
+               SDValue Chain, SDValue Ptr,
+               SDValue Cmp, SDValue Swp, const Value* SrcVal,
+               unsigned Align=0)
+    : MemSDNode(Opc, dl, VTL, MemVT, SrcVal, /*SVOffset=*/0,
+                Align, /*isVolatile=*/true) {
+    InitOperands(Ops, Chain, Ptr, Cmp, Swp);
+  }
+  AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, MVT MemVT,
+               SDValue Chain, SDValue Ptr, 
+               SDValue Val, const Value* SrcVal, unsigned Align=0)
+    : MemSDNode(Opc, dl, VTL, MemVT, SrcVal, /*SVOffset=*/0,
+                Align, /*isVolatile=*/true) {
+    InitOperands(Ops, Chain, Ptr, Val);
+  }
   
   const SDValue &getBasePtr() const { return getOperand(1); }
   const SDValue &getVal() const { return getOperand(2); }
@@ -1710,6 +1746,13 @@
     : MemSDNode(Opc, VTs, Ops, NumOps, MemoryVT, srcValue, SVO, Align, Vol),
       ReadMem(ReadMem), WriteMem(WriteMem) {
   }
+  MemIntrinsicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs,
+                     const SDValue *Ops, unsigned NumOps,
+                     MVT MemoryVT, const Value *srcValue, int SVO,
+                     unsigned Align, bool Vol, bool ReadMem, bool WriteMem)
+    : MemSDNode(Opc, dl, VTs, Ops, NumOps, MemoryVT, srcValue, SVO, Align, Vol),
+      ReadMem(ReadMem), WriteMem(WriteMem) {
+  }
 
   bool readMem() const { return ReadMem; }
   bool writeMem() const { return WriteMem; }
@@ -1928,6 +1971,9 @@
   explicit BasicBlockSDNode(MachineBasicBlock *mbb)
     : SDNode(ISD::BasicBlock, getSDVTList(MVT::Other)), MBB(mbb) {
   }
+  explicit BasicBlockSDNode(MachineBasicBlock *mbb, DebugLoc dl)
+    : SDNode(ISD::BasicBlock, dl, getSDVTList(MVT::Other)), MBB(mbb) {
+  }
 public:
 
   MachineBasicBlock *getBasicBlock() const { return MBB; }
@@ -2037,6 +2083,10 @@
     : SDNode(NodeTy, getSDVTList(MVT::Other)), LabelID(id) {
     InitOperands(&Chain, ch);
   }
+  LabelSDNode(unsigned NodeTy, DebugLoc dl, SDValue ch, unsigned id)
+    : SDNode(NodeTy, dl, getSDVTList(MVT::Other)), LabelID(id) {
+    InitOperands(&Chain, ch);
+  }
 public:
   unsigned getLabelID() const { return LabelID; }
 
@@ -2055,6 +2105,10 @@
     : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol,
              getSDVTList(VT)), Symbol(Sym) {
   }
+  ExternalSymbolSDNode(bool isTarget, DebugLoc dl, const char *Sym, MVT VT)
+    : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, dl,
+             getSDVTList(VT)), Symbol(Sym) {
+  }
 public:
 
   const char *getSymbol() const { return Symbol; }
@@ -2221,6 +2275,12 @@
     : SDNode(ISD::CALL, VTs, Operands, numOperands),
       CallingConv(cc), IsVarArg(isvararg), IsTailCall(istailcall),
       Inreg(isinreg) {}
+  CallSDNode(unsigned cc, DebugLoc dl, bool isvararg, bool istailcall, 
+             bool isinreg, SDVTList VTs, const SDValue *Operands, 
+             unsigned numOperands)
+    : SDNode(ISD::CALL, dl, VTs, Operands, numOperands),
+      CallingConv(cc), IsVarArg(isvararg), IsTailCall(istailcall),
+      Inreg(isinreg) {}
 public:
   unsigned getCallingConv() const { return CallingConv; }
   unsigned isVarArg() const { return IsVarArg; }
@@ -2295,6 +2355,16 @@
     assert((getOffset().getOpcode() == ISD::UNDEF || isIndexed()) &&
            "Only indexed loads and stores have a non-undef offset operand");
   }
+  LSBaseSDNode(ISD::NodeType NodeTy, DebugLoc dl, SDValue *Operands, 
+               unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM, 
+               MVT VT, const Value *SV, int SVO, unsigned Align, bool Vol)
+    : MemSDNode(NodeTy, dl, VTs, VT, SV, SVO, Align, Vol) {
+    SubclassData = AM;
+    InitOperands(Ops, Operands, numOperands);
+    assert(Align != 0 && "Loads and stores should have non-zero aligment");
+    assert((getOffset().getOpcode() == ISD::UNDEF || isIndexed()) &&
+           "Only indexed loads and stores have a non-undef offset operand");
+  }
 
   const SDValue &getOffset() const {
     return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
@@ -2331,6 +2401,13 @@
                    VTs, AM, LVT, SV, O, Align, Vol) {
     SubclassData |= (unsigned short)ETy << 3;
   }
+  LoadSDNode(SDValue *ChainPtrOff, DebugLoc dl, SDVTList VTs,
+             ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT LVT,
+             const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
+    : LSBaseSDNode(ISD::LOAD, dl, ChainPtrOff, 3,
+                   VTs, AM, LVT, SV, O, Align, Vol) {
+    SubclassData |= (unsigned short)ETy << 3;
+  }
 public:
 
   /// getExtensionType - Return whether this is a plain node,
@@ -2360,6 +2437,13 @@
                    VTs, AM, SVT, SV, O, Align, Vol) {
     SubclassData |= (unsigned short)isTrunc << 3;
   }
+  StoreSDNode(SDValue *ChainValuePtrOff, DebugLoc dl, SDVTList VTs,
+              ISD::MemIndexedMode AM, bool isTrunc, MVT SVT,
+              const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
+    : LSBaseSDNode(ISD::STORE, dl, ChainValuePtrOff, 4,
+                   VTs, AM, SVT, SV, O, Align, Vol) {
+    SubclassData |= (unsigned short)isTrunc << 3;
+  }
 public:
 
   /// isTruncatingStore - Return true if the op does a truncation before store.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63236&r1=63235&r2=63236&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jan 28 15:18:29 2009
@@ -4766,6 +4766,29 @@
   assert(isVolatile() == vol && "Volatile representation error!");
 }
 
+MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt,
+                     const Value *srcValue, int SVO,
+                     unsigned alignment, bool vol)
+ : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO),
+   Flags(encodeMemSDNodeFlags(vol, alignment)) {
+
+  assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!");
+  assert(getAlignment() == alignment && "Alignment representation error!");
+  assert(isVolatile() == vol && "Volatile representation error!");
+}
+
+MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, 
+                     const SDValue *Ops,
+                     unsigned NumOps, MVT memvt, const Value *srcValue,
+                     int SVO, unsigned alignment, bool vol)
+   : SDNode(Opc, dl, VTs, Ops, NumOps),
+     MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO),
+     Flags(vol | ((Log2_32(alignment) + 1) << 1)) {
+  assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!");
+  assert(getAlignment() == alignment && "Alignment representation error!");
+  assert(isVolatile() == vol && "Volatile representation error!");
+}
+
 /// getMemOperand - Return a MachineMemOperand object describing the memory
 /// reference performed by this memory reference.
 MachineMemOperand MemSDNode::getMemOperand() const {




From dalej at apple.com  Wed Jan 28 15:30:39 2009
From: dalej at apple.com (Dale Johannesen)
Date: Wed, 28 Jan 2009 13:30:39 -0800
Subject: [llvm-commits] Turning off SSE codegen for x86-64?
In-Reply-To: <4980BB88.3080409@gmail.com>
References: <200901252021.n0PKLO2s029035@zion.cs.uiuc.edu>
	<4980A242.7060401@gmail.com>
	
	<4980BB88.3080409@gmail.com>
Message-ID: <40C05783-04B7-43AF-89A6-4BE851FEF22D@apple.com>


> So far I found that functions with va-args get SSE registers pushed on
> the stack on x86-64/linux.
> Could you point me to the place where this happens in llvm codegen? If
> its not too complicated I may try to propose a patch when I find  
> some time.

LowerCALL in X86ISelLowering.cpp, and X86CallingConv.td.  You'll need  
to match up with the
prolog code which is in LowerFORMAL_ARGUMENTS.



From gohman at apple.com  Wed Jan 28 15:34:36 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 28 Jan 2009 21:34:36 -0000
Subject: [llvm-commits] [llvm] r63239 -
	/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
Message-ID: <200901282134.n0SLYaOV023300@zion.cs.uiuc.edu>

Author: djg
Date: Wed Jan 28 15:34:36 2009
New Revision: 63239

URL: http://llvm.org/viewvc/llvm-project?rev=63239&view=rev
Log:
Add more comments describing SDNode operator codes.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=63239&r1=63238&r2=63239&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Jan 28 15:34:36 2009
@@ -60,15 +60,19 @@
 namespace ISD {
 
   //===--------------------------------------------------------------------===//
-  /// ISD::NodeType enum - This enum defines all of the operators valid in a
-  /// SelectionDAG.
+  /// ISD::NodeType enum - This enum defines the target-independent operators
+  /// for a SelectionDAG.
   ///
-  /// These are sometimes called the target-independent operators; targets
-  /// may also define target-dependent operators. For example, on x86, these
-  /// are the enum values in the X86ISD namespace. Targets should aim to use
-  /// target-independent operators to model their instruction sets as much
-  /// as possible, and only use target-dependent operators when they have
-  /// special requirements.
+  /// Targets may also define target-dependent operator codes for SDNodes. For
+  /// example, on x86, these are the enum values in the X86ISD namespace.
+  /// Targets should aim to use target-independent operators to model their
+  /// instruction sets as much as possible, and only use target-dependent
+  /// operators when they have special requirements.
+  ///
+  /// Finally, during and after selection proper, SNodes may use special
+  /// operator codes that correspond directly with MachineInstr opcodes. These
+  /// are used to represent selected instructions. See the isMachineOpcode()
+  /// and getMachineOpcode() member functions of SDNode.
   ///
   enum NodeType {
     // DELETED_NODE - This is an illegal flag value that is used to catch




From gohman at apple.com  Wed Jan 28 15:36:46 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 28 Jan 2009 21:36:46 -0000
Subject: [llvm-commits] [llvm] r63240 -
	/llvm/trunk/docs/WritingAnLLVMBackend.html
Message-ID: <200901282136.n0SLakOL023375@zion.cs.uiuc.edu>

Author: djg
Date: Wed Jan 28 15:36:46 2009
New Revision: 63240

URL: http://llvm.org/viewvc/llvm-project?rev=63240&view=rev
Log:
SDOperand has been renamed to SDValue. SDNode::Val is now
accessed via SDNode::getNode.

Modified:
    llvm/trunk/docs/WritingAnLLVMBackend.html

Modified: llvm/trunk/docs/WritingAnLLVMBackend.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/WritingAnLLVMBackend.html?rev=63240&r1=63239&r2=63240&view=diff

==============================================================================
--- llvm/trunk/docs/WritingAnLLVMBackend.html (original)
+++ llvm/trunk/docs/WritingAnLLVMBackend.html Wed Jan 28 15:36:46 2009
@@ -1349,9 +1349,9 @@
      -
      SDNode *SelectCode(SDOperand N) {
+
      SDNode *SelectCode(SDValue N) {
   ... 
-  MVT::ValueType NVT = N.Val->getValueType(0);
+  MVT::ValueType NVT = N.getNode()->getValueType(0);
   switch (N.getOpcode()) {
   case ISD::STORE: {
     switch (NVT) {
@@ -1372,21 +1372,21 @@
      -
      SDNode *Select_ISD_STORE(const SDOperand &N) {
-  SDOperand Chain = N.getOperand(0);
-  if (Predicate_store(N.Val)) {
-    SDOperand N1 = N.getOperand(1);
-    SDOperand N2 = N.getOperand(2);
-    SDOperand CPTmp0;
-    SDOperand CPTmp1;
+
      SDNode *Select_ISD_STORE(const SDValue &N) {
+  SDValue Chain = N.getOperand(0);
+  if (Predicate_store(N.getNode())) {
+    SDValue N1 = N.getOperand(1);
+    SDValue N2 = N.getOperand(2);
+    SDValue CPTmp0;
+    SDValue CPTmp1;
  
     // Pattern: (st:void IntRegs:i32:$src, 
     //           ADDRrr:i32:$addr)<<P:Predicate_store>>
     // Emits: (STrr:void ADDRrr:i32:$addr, IntRegs:i32:$src)
     // Pattern complexity = 13  cost = 1  size = 0
     if (SelectADDRrr(N, N2, CPTmp0, CPTmp1) &&
-        N1.Val->getValueType(0) == MVT::i32 &&
-        N2.Val->getValueType(0) == MVT::i32) {
+        N1.getNode()->getValueType(0) == MVT::i32 &&
+        N2.getNode()->getValueType(0) == MVT::i32) {
       return Emit_22(N, SP::STrr, CPTmp0, CPTmp1);
     }
 ...
@@ -1520,8 +1520,8 @@
      -
      SDOperand SparcTargetLowering::LowerOperation(
-                               SDOperand Op, SelectionDAG &DAG) {
+
      SDValue SparcTargetLowering::LowerOperation(
+                               SDValue Op, SelectionDAG &DAG) {
   switch (Op.getOpcode()) {
   case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
   ...
@@ -1535,7 +1535,7 @@
      -
      static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
+
      static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
 assert(Op.getValueType() == MVT::i32);
   Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
   return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);




From gohman at apple.com  Wed Jan 28 16:14:58 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 28 Jan 2009 22:14:58 -0000
Subject: [llvm-commits] [llvm] r63244 -
	/llvm/trunk/test/DebugInfo/2009-01-28-ArrayType.ll
Message-ID: <200901282214.n0SMEw9p024835@zion.cs.uiuc.edu>

Author: djg
Date: Wed Jan 28 16:14:58 2009
New Revision: 63244

URL: http://llvm.org/viewvc/llvm-project?rev=63244&view=rev
Log:
Give this test an explicit target, to make it host-independent.

Modified:
    llvm/trunk/test/DebugInfo/2009-01-28-ArrayType.ll

Modified: llvm/trunk/test/DebugInfo/2009-01-28-ArrayType.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2009-01-28-ArrayType.ll?rev=63244&r1=63243&r2=63244&view=diff

==============================================================================
--- llvm/trunk/test/DebugInfo/2009-01-28-ArrayType.ll (original)
+++ llvm/trunk/test/DebugInfo/2009-01-28-ArrayType.ll Wed Jan 28 16:14:58 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep 0x49 | count 7
+; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin | grep 0x49 | count 7
 ; Count number of DW_AT_Type attributes.
 	%llvm.dbg.anchor.type = type { i32, i32 }
 	%llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32, i8*, i8* }




From isanbard at gmail.com  Wed Jan 28 16:17:52 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 28 Jan 2009 22:17:52 -0000
Subject: [llvm-commits] [llvm] r63245 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAG.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Message-ID: <200901282217.n0SMHq5n024981@zion.cs.uiuc.edu>

Author: void
Date: Wed Jan 28 16:17:52 2009
New Revision: 63245

URL: http://llvm.org/viewvc/llvm-project?rev=63245&view=rev
Log:
Add DebugLoc to the getNode() methods.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63245&r1=63244&r2=63245&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Jan 28 16:17:52 2009
@@ -394,35 +394,68 @@
   /// getNode - Gets or creates the specified node.
   ///
   SDValue getNode(unsigned Opcode, MVT VT);
+  SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT);
   SDValue getNode(unsigned Opcode, MVT VT, SDValue N);
+  SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N);
   SDValue getNode(unsigned Opcode, MVT VT, SDValue N1, SDValue N2);
+  SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N1, SDValue N2);
   SDValue getNode(unsigned Opcode, MVT VT,
-                    SDValue N1, SDValue N2, SDValue N3);
+                  SDValue N1, SDValue N2, SDValue N3);
+  SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+                  SDValue N1, SDValue N2, SDValue N3);
   SDValue getNode(unsigned Opcode, MVT VT,
-                    SDValue N1, SDValue N2, SDValue N3, SDValue N4);
+                  SDValue N1, SDValue N2, SDValue N3, SDValue N4);
+  SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+                  SDValue N1, SDValue N2, SDValue N3, SDValue N4);
   SDValue getNode(unsigned Opcode, MVT VT,
-                    SDValue N1, SDValue N2, SDValue N3, SDValue N4,
-                    SDValue N5);
+                  SDValue N1, SDValue N2, SDValue N3, SDValue N4,
+                  SDValue N5);
+  SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+                  SDValue N1, SDValue N2, SDValue N3, SDValue N4,
+                  SDValue N5);
   SDValue getNode(unsigned Opcode, MVT VT,
-                    const SDValue *Ops, unsigned NumOps);
+                  const SDUse *Ops, unsigned NumOps);
+  SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+                  const SDUse *Ops, unsigned NumOps);
   SDValue getNode(unsigned Opcode, MVT VT,
-                    const SDUse *Ops, unsigned NumOps);
+                  const SDValue *Ops, unsigned NumOps);
+  SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+                  const SDValue *Ops, unsigned NumOps);
   SDValue getNode(unsigned Opcode, const std::vector &ResultTys,
-                    const SDValue *Ops, unsigned NumOps);
+                  const SDValue *Ops, unsigned NumOps);
+  SDValue getNode(unsigned Opcode, DebugLoc DL,
+                  const std::vector &ResultTys,
+                  const SDValue *Ops, unsigned NumOps);
   SDValue getNode(unsigned Opcode, const MVT *VTs, unsigned NumVTs,
-                    const SDValue *Ops, unsigned NumOps);
+                  const SDValue *Ops, unsigned NumOps);
+  SDValue getNode(unsigned Opcode, DebugLoc DL, const MVT *VTs, unsigned NumVTs,
+                  const SDValue *Ops, unsigned NumOps);
+  SDValue getNode(unsigned Opcode, SDVTList VTs,
+                  const SDValue *Ops, unsigned NumOps);
+  SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,
+                  const SDValue *Ops, unsigned NumOps);
+
   SDValue getNode(unsigned Opcode, SDVTList VTs);
+  SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs);
   SDValue getNode(unsigned Opcode, SDVTList VTs, SDValue N);
+  SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N);
   SDValue getNode(unsigned Opcode, SDVTList VTs, SDValue N1, SDValue N2);
+  SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,
+                  SDValue N1, SDValue N2);
   SDValue getNode(unsigned Opcode, SDVTList VTs,
                   SDValue N1, SDValue N2, SDValue N3);
+  SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,
+                  SDValue N1, SDValue N2, SDValue N3);
   SDValue getNode(unsigned Opcode, SDVTList VTs,
                   SDValue N1, SDValue N2, SDValue N3, SDValue N4);
+  SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,
+                  SDValue N1, SDValue N2, SDValue N3, SDValue N4);
   SDValue getNode(unsigned Opcode, SDVTList VTs,
                   SDValue N1, SDValue N2, SDValue N3, SDValue N4,
                   SDValue N5);
-  SDValue getNode(unsigned Opcode, SDVTList VTs,
-                  const SDValue *Ops, unsigned NumOps);
+  SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,
+                  SDValue N1, SDValue N2, SDValue N3, SDValue N4,
+                  SDValue N5);
 
   SDValue getMemcpy(SDValue Chain, SDValue Dst, SDValue Src,
                     SDValue Size, unsigned Align, bool AlwaysInline,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63245&r1=63244&r2=63245&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jan 28 16:17:52 2009
@@ -2102,13 +2102,17 @@
 /// getNode - Gets or creates the specified node.
 ///
 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT) {
+  return getNode(Opcode, DebugLoc::getUnknownLoc(), VT);
+}
+
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) {
   FoldingSetNodeID ID;
   AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0);
   void *IP = 0;
   if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
     return SDValue(E, 0);
   SDNode *N = NodeAllocator.Allocate();
-  new (N) SDNode(Opcode, SDNode::getSDVTList(VT));
+  new (N) SDNode(Opcode, DL, SDNode::getSDVTList(VT));
   CSEMap.InsertNode(N, IP);
   
   AllNodes.push_back(N);
@@ -2119,6 +2123,11 @@
 }
 
 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) {
+  return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, Operand);
+}
+
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
+                              MVT VT, SDValue Operand) {
   // Constant fold unary operations with an integer constant operand.
   if (ConstantSDNode *C = dyn_cast(Operand.getNode())) {
     const APInt &Val = C->getAPIntValue();
@@ -2310,11 +2319,11 @@
     if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
       return SDValue(E, 0);
     N = NodeAllocator.Allocate();
-    new (N) UnarySDNode(Opcode, VTs, Operand);
+    new (N) UnarySDNode(Opcode, DL, VTs, Operand);
     CSEMap.InsertNode(N, IP);
   } else {
     N = NodeAllocator.Allocate();
-    new (N) UnarySDNode(Opcode, VTs, Operand);
+    new (N) UnarySDNode(Opcode, DL, VTs, Operand);
   }
 
   AllNodes.push_back(N);
@@ -2362,6 +2371,11 @@
 
 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
                               SDValue N1, SDValue N2) {
+  return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2);
+}
+
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+                              SDValue N1, SDValue N2) {
   ConstantSDNode *N1C = dyn_cast(N1.getNode());
   ConstantSDNode *N2C = dyn_cast(N2.getNode());
   switch (Opcode) {
@@ -2705,11 +2719,11 @@
     if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
       return SDValue(E, 0);
     N = NodeAllocator.Allocate();
-    new (N) BinarySDNode(Opcode, VTs, N1, N2);
+    new (N) BinarySDNode(Opcode, DL, VTs, N1, N2);
     CSEMap.InsertNode(N, IP);
   } else {
     N = NodeAllocator.Allocate();
-    new (N) BinarySDNode(Opcode, VTs, N1, N2);
+    new (N) BinarySDNode(Opcode, DL, VTs, N1, N2);
   }
 
   AllNodes.push_back(N);
@@ -2721,6 +2735,11 @@
 
 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
                               SDValue N1, SDValue N2, SDValue N3) {
+  return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2, N3);
+}
+
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+                              SDValue N1, SDValue N2, SDValue N3) {
   // Perform various simplifications.
   ConstantSDNode *N1C = dyn_cast(N1.getNode());
   ConstantSDNode *N2C = dyn_cast(N2.getNode());
@@ -2787,11 +2806,11 @@
     if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
       return SDValue(E, 0);
     N = NodeAllocator.Allocate();
-    new (N) TernarySDNode(Opcode, VTs, N1, N2, N3);
+    new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3);
     CSEMap.InsertNode(N, IP);
   } else {
     N = NodeAllocator.Allocate();
-    new (N) TernarySDNode(Opcode, VTs, N1, N2, N3);
+    new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3);
   }
   AllNodes.push_back(N);
 #ifndef NDEBUG
@@ -2803,15 +2822,27 @@
 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
                               SDValue N1, SDValue N2, SDValue N3,
                               SDValue N4) {
+  return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2, N3, N4);
+}
+
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+                              SDValue N1, SDValue N2, SDValue N3,
+                              SDValue N4) {
   SDValue Ops[] = { N1, N2, N3, N4 };
-  return getNode(Opcode, VT, Ops, 4);
+  return getNode(Opcode, DL, VT, Ops, 4);
 }
 
 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
                               SDValue N1, SDValue N2, SDValue N3,
                               SDValue N4, SDValue N5) {
+  return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2, N3, N4, N5);
+}
+
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+                              SDValue N1, SDValue N2, SDValue N3,
+                              SDValue N4, SDValue N5) {
   SDValue Ops[] = { N1, N2, N3, N4, N5 };
-  return getNode(Opcode, VT, Ops, 5);
+  return getNode(Opcode, DL, VT, Ops, 5);
 }
 
 /// getMemsetValue - Vectorized representation of the memset value
@@ -3620,27 +3651,37 @@
 
 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
                               const SDUse *Ops, unsigned NumOps) {
+  return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, Ops, NumOps);
+}
+
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+                              const SDUse *Ops, unsigned NumOps) {
   switch (NumOps) {
-  case 0: return getNode(Opcode, VT);
-  case 1: return getNode(Opcode, VT, Ops[0]);
-  case 2: return getNode(Opcode, VT, Ops[0], Ops[1]);
-  case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]);
+  case 0: return getNode(Opcode, DL, VT);
+  case 1: return getNode(Opcode, DL, VT, Ops[0]);
+  case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]);
+  case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]);
   default: break;
   }
 
   // Copy from an SDUse array into an SDValue array for use with
   // the regular getNode logic.
   SmallVector NewOps(Ops, Ops + NumOps);
-  return getNode(Opcode, VT, &NewOps[0], NumOps);
+  return getNode(Opcode, DL, VT, &NewOps[0], NumOps);
 }
 
 SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
                               const SDValue *Ops, unsigned NumOps) {
+  return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, Ops, NumOps);
+}
+
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+                              const SDValue *Ops, unsigned NumOps) {
   switch (NumOps) {
-  case 0: return getNode(Opcode, VT);
-  case 1: return getNode(Opcode, VT, Ops[0]);
-  case 2: return getNode(Opcode, VT, Ops[0], Ops[1]);
-  case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]);
+  case 0: return getNode(Opcode, DL, VT);
+  case 1: return getNode(Opcode, DL, VT, Ops[0]);
+  case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]);
+  case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]);
   default: break;
   }
   
@@ -3667,19 +3708,23 @@
   // Memoize nodes.
   SDNode *N;
   SDVTList VTs = getVTList(VT);
+
   if (VT != MVT::Flag) {
     FoldingSetNodeID ID;
     AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps);
     void *IP = 0;
+
     if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
       return SDValue(E, 0);
+
     N = NodeAllocator.Allocate();
-    new (N) SDNode(Opcode, VTs, Ops, NumOps);
+    new (N) SDNode(Opcode, DL, VTs, Ops, NumOps);
     CSEMap.InsertNode(N, IP);
   } else {
     N = NodeAllocator.Allocate();
-    new (N) SDNode(Opcode, VTs, Ops, NumOps);
+    new (N) SDNode(Opcode, DL, VTs, Ops, NumOps);
   }
+
   AllNodes.push_back(N);
 #ifndef NDEBUG
   VerifyNode(N);
@@ -3690,22 +3735,39 @@
 SDValue SelectionDAG::getNode(unsigned Opcode,
                               const std::vector &ResultTys,
                               const SDValue *Ops, unsigned NumOps) {
-  return getNode(Opcode, getNodeValueTypes(ResultTys), ResultTys.size(),
+  return getNode(Opcode, DebugLoc::getUnknownLoc(), ResultTys, Ops, NumOps);
+}
+
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
+                              const std::vector &ResultTys,
+                              const SDValue *Ops, unsigned NumOps) {
+  return getNode(Opcode, DL, getNodeValueTypes(ResultTys), ResultTys.size(),
                  Ops, NumOps);
 }
 
 SDValue SelectionDAG::getNode(unsigned Opcode,
                               const MVT *VTs, unsigned NumVTs,
                               const SDValue *Ops, unsigned NumOps) {
+  return getNode(Opcode, DebugLoc::getUnknownLoc(), VTs, NumVTs, Ops, NumOps);
+}
+
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
+                              const MVT *VTs, unsigned NumVTs,
+                              const SDValue *Ops, unsigned NumOps) {
   if (NumVTs == 1)
-    return getNode(Opcode, VTs[0], Ops, NumOps);
-  return getNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps);
+    return getNode(Opcode, DL, VTs[0], Ops, NumOps);
+  return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps);
 }  
   
 SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
                               const SDValue *Ops, unsigned NumOps) {
+  return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, Ops, NumOps);
+}
+
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
+                              const SDValue *Ops, unsigned NumOps) {
   if (VTList.NumVTs == 1)
-    return getNode(Opcode, VTList.VTs[0], Ops, NumOps);
+    return getNode(Opcode, DL, VTList.VTs[0], Ops, NumOps);
 
   switch (Opcode) {
   // FIXME: figure out how to safely handle things like
@@ -3717,14 +3779,14 @@
   case ISD::SHL_PARTS:
     if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG &&
         cast(N3.getOperand(1))->getVT() != MVT::i1)
-      return getNode(Opcode, VT, N1, N2, N3.getOperand(0));
+      return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0));
     else if (N3.getOpcode() == ISD::AND)
       if (ConstantSDNode *AndRHS = dyn_cast(N3.getOperand(1))) {
         // If the and is only masking out bits that cannot effect the shift,
         // eliminate the and.
         unsigned NumBits = VT.getSizeInBits()*2;
         if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
-          return getNode(Opcode, VT, N1, N2, N3.getOperand(0));
+          return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0));
       }
     break;
 #endif
@@ -3740,31 +3802,31 @@
       return SDValue(E, 0);
     if (NumOps == 1) {
       N = NodeAllocator.Allocate();
-      new (N) UnarySDNode(Opcode, VTList, Ops[0]);
+      new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]);
     } else if (NumOps == 2) {
       N = NodeAllocator.Allocate();
-      new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]);
+      new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]);
     } else if (NumOps == 3) {
       N = NodeAllocator.Allocate();
-      new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]);
+      new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]);
     } else {
       N = NodeAllocator.Allocate();
-      new (N) SDNode(Opcode, VTList, Ops, NumOps);
+      new (N) SDNode(Opcode, DL, VTList, Ops, NumOps);
     }
     CSEMap.InsertNode(N, IP);
   } else {
     if (NumOps == 1) {
       N = NodeAllocator.Allocate();
-      new (N) UnarySDNode(Opcode, VTList, Ops[0]);
+      new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]);
     } else if (NumOps == 2) {
       N = NodeAllocator.Allocate();
-      new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]);
+      new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]);
     } else if (NumOps == 3) {
       N = NodeAllocator.Allocate();
-      new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]);
+      new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]);
     } else {
       N = NodeAllocator.Allocate();
-      new (N) SDNode(Opcode, VTList, Ops, NumOps);
+      new (N) SDNode(Opcode, DL, VTList, Ops, NumOps);
     }
   }
   AllNodes.push_back(N);
@@ -3775,39 +3837,70 @@
 }
 
 SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) {
-  return getNode(Opcode, VTList, 0, 0);
+  return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList); 
+}
+
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) {
+  return getNode(Opcode, DL, VTList, 0, 0);
 }
 
 SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
-                                SDValue N1) {
+                              SDValue N1) {
+  return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1);
+}
+
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
+                              SDValue N1) {
   SDValue Ops[] = { N1 };
-  return getNode(Opcode, VTList, Ops, 1);
+  return getNode(Opcode, DL, VTList, Ops, 1);
 }
 
 SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
                               SDValue N1, SDValue N2) {
+  return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2);
+}
+
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
+                              SDValue N1, SDValue N2) {
   SDValue Ops[] = { N1, N2 };
-  return getNode(Opcode, VTList, Ops, 2);
+  return getNode(Opcode, DL, VTList, Ops, 2);
 }
 
 SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
                               SDValue N1, SDValue N2, SDValue N3) {
+  return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2, N3);
+}
+
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
+                              SDValue N1, SDValue N2, SDValue N3) {
   SDValue Ops[] = { N1, N2, N3 };
-  return getNode(Opcode, VTList, Ops, 3);
+  return getNode(Opcode, DL, VTList, Ops, 3);
 }
 
 SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
                               SDValue N1, SDValue N2, SDValue N3,
                               SDValue N4) {
+  return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2, N3, N4);
+}
+
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
+                              SDValue N1, SDValue N2, SDValue N3,
+                              SDValue N4) {
   SDValue Ops[] = { N1, N2, N3, N4 };
-  return getNode(Opcode, VTList, Ops, 4);
+  return getNode(Opcode, DL, VTList, Ops, 4);
 }
 
 SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
                               SDValue N1, SDValue N2, SDValue N3,
                               SDValue N4, SDValue N5) {
+  return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2, N3, N4, N5);
+}
+
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
+                              SDValue N1, SDValue N2, SDValue N3,
+                              SDValue N4, SDValue N5) {
   SDValue Ops[] = { N1, N2, N3, N4, N5 };
-  return getNode(Opcode, VTList, Ops, 5);
+  return getNode(Opcode, DL, VTList, Ops, 5);
 }
 
 SDVTList SelectionDAG::getVTList(MVT VT) {




From isanbard at gmail.com  Wed Jan 28 16:20:56 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 28 Jan 2009 22:20:56 -0000
Subject: [llvm-commits] [llvm] r63247 -
	/llvm/trunk/test/CodeGen/X86/2009-01-27-NullStrings.ll
Message-ID: <200901282220.n0SMKuHv025153@zion.cs.uiuc.edu>

Author: void
Date: Wed Jan 28 16:20:56 2009
New Revision: 63247

URL: http://llvm.org/viewvc/llvm-project?rev=63247&view=rev
Log:
Make test platform agnostic.

Modified:
    llvm/trunk/test/CodeGen/X86/2009-01-27-NullStrings.ll

Modified: llvm/trunk/test/CodeGen/X86/2009-01-27-NullStrings.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-01-27-NullStrings.ll?rev=63247&r1=63246&r2=63247&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-01-27-NullStrings.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-01-27-NullStrings.ll Wed Jan 28 16:20:56 2009
@@ -1,6 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {\\.cstring} | count 1
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
-target triple = "i386-apple-darwin9.6"
+; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin | grep {\\.cstring} | count 1
 	%struct.A = type {  }
 	%struct.NSString = type opaque
 	%struct.__builtin_CFString = type { i32*, i32, i8*, i32 }




From wangmp at apple.com  Wed Jan 28 17:11:14 2009
From: wangmp at apple.com (Mon P Wang)
Date: Wed, 28 Jan 2009 23:11:14 -0000
Subject: [llvm-commits] [llvm] r63252 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/vec_shuffle-29.ll
Message-ID: <200901282311.n0SNBEnb026871@zion.cs.uiuc.edu>

Author: wangmp
Date: Wed Jan 28 17:11:14 2009
New Revision: 63252

URL: http://llvm.org/viewvc/llvm-project?rev=63252&view=rev
Log:
Fixed lowering of v816 shuffles.

Added:
    llvm/trunk/test/CodeGen/X86/vec_shuffle-29.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=63252&r1=63251&r2=63252&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jan 28 17:11:14 2009
@@ -3677,7 +3677,7 @@
       ++V2InOrder;
     } else if (EltIdx < 8) {
       V1Elts.push_back(Elt);
-      V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
+      V2Elts.push_back(DAG.getConstant(EltIdx+8, MaskEVT));
       ++V1FromV1;
     } else {
       V1Elts.push_back(Elt);

Added: llvm/trunk/test/CodeGen/X86/vec_shuffle-29.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-29.ll?rev=63252&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle-29.ll (added)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle-29.ll Wed Jan 28 17:11:14 2009
@@ -0,0 +1,14 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 -disable-mmx -o %t -f
+; RUN: not grep pextrw %t
+; RUN: grep pinsrw %t
+
+; Test for v8xi16 lowering where we extract the first element of the vector and
+; placed it in the second element of the result.
+
+define void @test_cl(<8 x i16> addrspace(1)* %dest, <8 x i16> addrspace(1)* %old) nounwind {
+entry:
+	%tmp3 = load <8 x i16> addrspace(1)* %old		; <<8 x i16>> [#uses=1]
+	%tmp6 = shufflevector <8 x i16> %tmp3, <8 x i16> < i16 0, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef >, <8 x i32> < i32 8, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef  >		; <<8 x i16>> [#uses=1]
+	store <8 x i16> %tmp6, <8 x i16> addrspace(1)* %dest
+	ret void
+}
\ No newline at end of file




From evan.cheng at apple.com  Wed Jan 28 18:06:10 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 29 Jan 2009 00:06:10 -0000
Subject: [llvm-commits] [llvm] r63255 - in /llvm/trunk:
 include/llvm/CodeGen/LiveInterval.h lib/CodeGen/LiveInterval.cpp
Message-ID: <200901290006.n0T06AF1028653@zion.cs.uiuc.edu>

Author: evancheng
Date: Wed Jan 28 18:06:09 2009
New Revision: 63255

URL: http://llvm.org/viewvc/llvm-project?rev=63255&view=rev
Log:
Fix comment about removeRange.

Modified:
    llvm/trunk/include/llvm/CodeGen/LiveInterval.h
    llvm/trunk/lib/CodeGen/LiveInterval.cpp

Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=63255&r1=63254&r2=63255&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Wed Jan 28 18:06:09 2009
@@ -378,7 +378,7 @@
               SmallVector &NewVNInfo);
 
     /// removeRange - Remove the specified range from this interval.  Note that
-    /// the range must already be in this interval in its entirety.
+    /// the range must be a single LiveRange in its entirety.
     void removeRange(unsigned Start, unsigned End, bool RemoveDeadValNo = false);
 
     void removeRange(LiveRange LR, bool RemoveDeadValNo = false) {

Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=63255&r1=63254&r2=63255&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Wed Jan 28 18:06:09 2009
@@ -246,7 +246,7 @@
 
 
 /// removeRange - Remove the specified range from this interval.  Note that
-/// the range must already be in this interval in its entirety.
+/// the range must be in a single LiveRange in its entirety.
 void LiveInterval::removeRange(unsigned Start, unsigned End,
                                bool RemoveDeadValNo) {
   // Find the LiveRange containing this span.




From dalej at apple.com  Wed Jan 28 18:47:48 2009
From: dalej at apple.com (Dale Johannesen)
Date: Thu, 29 Jan 2009 00:47:48 -0000
Subject: [llvm-commits] [llvm] r63259 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAG.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Message-ID: <200901290047.n0T0lmXG030099@zion.cs.uiuc.edu>

Author: johannes
Date: Wed Jan 28 18:47:48 2009
New Revision: 63259

URL: http://llvm.org/viewvc/llvm-project?rev=63259&view=rev
Log:
Add DebugLoc-sensitive versions of many node creation
functions.  Currently omitted:  memcpy, memmove, memset.


Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63259&r1=63258&r2=63259&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Jan 28 18:47:48 2009
@@ -307,14 +307,19 @@
     return getConstantPool(C, VT, Align, Offset, true);
   }
   SDValue getBasicBlock(MachineBasicBlock *MBB);
+  SDValue getBasicBlock(MachineBasicBlock *MBB, DebugLoc dl);
   SDValue getExternalSymbol(const char *Sym, MVT VT);
+  SDValue getExternalSymbol(const char *Sym, DebugLoc dl, MVT VT);
   SDValue getTargetExternalSymbol(const char *Sym, MVT VT);
+  SDValue getTargetExternalSymbol(const char *Sym, DebugLoc dl, MVT VT);
   SDValue getArgFlags(ISD::ArgFlagsTy Flags);
   SDValue getValueType(MVT);
   SDValue getRegister(unsigned Reg, MVT VT);
   SDValue getDbgStopPoint(SDValue Root, unsigned Line, unsigned Col,
                           Value *CU);
   SDValue getLabel(unsigned Opcode, SDValue Root, unsigned LabelID);
+  SDValue getLabel(unsigned Opcode, DebugLoc dl, SDValue Root, 
+                   unsigned LabelID);
 
   SDValue getCopyToReg(SDValue Chain, unsigned Reg, SDValue N) {
     return getNode(ISD::CopyToReg, MVT::Other, Chain,
@@ -506,12 +511,18 @@
   SDValue getAtomic(unsigned Opcode, MVT MemVT, SDValue Chain, SDValue Ptr, 
                     SDValue Cmp, SDValue Swp, const Value* PtrVal,
                     unsigned Alignment=0);
+  SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain, 
+                    SDValue Ptr, SDValue Cmp, SDValue Swp, const Value* PtrVal,
+                    unsigned Alignment=0);
 
   /// getAtomic - Gets a node for an atomic op, produces result and chain and
   /// takes 2 operands.
   SDValue getAtomic(unsigned Opcode, MVT MemVT, SDValue Chain, SDValue Ptr, 
                     SDValue Val, const Value* PtrVal,
                     unsigned Alignment = 0);
+  SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain,
+                    SDValue Ptr, SDValue Val, const Value* PtrVal,
+                    unsigned Alignment = 0);
 
   /// getMemIntrinsicNode - Creates a MemIntrinsicNode that may produce a
   /// result and takes a list of operands.
@@ -521,12 +532,23 @@
                               MVT MemVT, const Value *srcValue, int SVOff,
                               unsigned Align = 0, bool Vol = false,
                               bool ReadMem = true, bool WriteMem = true);
+  SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
+                              const MVT *VTs, unsigned NumVTs,
+                              const SDValue *Ops, unsigned NumOps,
+                              MVT MemVT, const Value *srcValue, int SVOff,
+                              unsigned Align = 0, bool Vol = false,
+                              bool ReadMem = true, bool WriteMem = true);
 
   SDValue getMemIntrinsicNode(unsigned Opcode, SDVTList VTList,
                               const SDValue *Ops, unsigned NumOps,
                               MVT MemVT, const Value *srcValue, int SVOff,
                               unsigned Align = 0, bool Vol = false,
                               bool ReadMem = true, bool WriteMem = true);
+  SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList,
+                              const SDValue *Ops, unsigned NumOps,
+                              MVT MemVT, const Value *srcValue, int SVOff,
+                              unsigned Align = 0, bool Vol = false,
+                              bool ReadMem = true, bool WriteMem = true);
 
   /// getMergeValues - Create a MERGE_VALUES node from the given operands.
   SDValue getMergeValues(const SDValue *Ops, unsigned NumOps);
@@ -536,6 +558,9 @@
   SDValue getCall(unsigned CallingConv, bool IsVarArgs, bool IsTailCall,
                   bool isInreg, SDVTList VTs, const SDValue *Operands, 
                   unsigned NumOperands);
+  SDValue getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs,
+                  bool IsTailCall, bool isInreg, SDVTList VTs,
+                  const SDValue *Operands, unsigned NumOperands);
 
   /// getLoad - Loads are not normal binary operators: their result type is not
   /// determined by their operands, and they produce a value AND a token chain.
@@ -543,28 +568,50 @@
   SDValue getLoad(MVT VT, SDValue Chain, SDValue Ptr,
                     const Value *SV, int SVOffset, bool isVolatile=false,
                     unsigned Alignment=0);
+  SDValue getLoad(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
+                    const Value *SV, int SVOffset, bool isVolatile=false,
+                    unsigned Alignment=0);
   SDValue getExtLoad(ISD::LoadExtType ExtType, MVT VT,
                        SDValue Chain, SDValue Ptr, const Value *SV,
                        int SVOffset, MVT EVT, bool isVolatile=false,
                        unsigned Alignment=0);
+  SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT,
+                       SDValue Chain, SDValue Ptr, const Value *SV,
+                       int SVOffset, MVT EVT, bool isVolatile=false,
+                       unsigned Alignment=0);
   SDValue getIndexedLoad(SDValue OrigLoad, SDValue Base,
                            SDValue Offset, ISD::MemIndexedMode AM);
+  SDValue getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
+                           SDValue Offset, ISD::MemIndexedMode AM);
   SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
                     MVT VT, SDValue Chain,
                     SDValue Ptr, SDValue Offset,
                     const Value *SV, int SVOffset, MVT EVT,
                     bool isVolatile=false, unsigned Alignment=0);
+  SDValue getLoad(ISD::MemIndexedMode AM, DebugLoc dl, ISD::LoadExtType ExtType,
+                    MVT VT, SDValue Chain,
+                    SDValue Ptr, SDValue Offset,
+                    const Value *SV, int SVOffset, MVT EVT,
+                    bool isVolatile=false, unsigned Alignment=0);
 
   /// getStore - Helper function to build ISD::STORE nodes.
   ///
   SDValue getStore(SDValue Chain, SDValue Val, SDValue Ptr,
                      const Value *SV, int SVOffset, bool isVolatile=false,
                      unsigned Alignment=0);
+  SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
+                     const Value *SV, int SVOffset, bool isVolatile=false,
+                     unsigned Alignment=0);
   SDValue getTruncStore(SDValue Chain, SDValue Val, SDValue Ptr,
                           const Value *SV, int SVOffset, MVT TVT,
                           bool isVolatile=false, unsigned Alignment=0);
+  SDValue getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
+                          const Value *SV, int SVOffset, MVT TVT,
+                          bool isVolatile=false, unsigned Alignment=0);
   SDValue getIndexedStore(SDValue OrigStoe, SDValue Base,
                            SDValue Offset, ISD::MemIndexedMode AM);
+  SDValue getIndexedStore(SDValue OrigStoe, DebugLoc dl, SDValue Base,
+                           SDValue Offset, ISD::MemIndexedMode AM);
 
   /// getSrcValue - Construct a node to track a Value* through the backend.
   SDValue getSrcValue(const Value *v);
@@ -652,30 +699,72 @@
   /// node of the specified opcode and operands, it returns that node instead of
   /// the current one.
   SDNode *getTargetNode(unsigned Opcode, MVT VT);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1, SDValue Op2);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1, 
+                        SDValue Op2);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT,
                         SDValue Op1, SDValue Op2, SDValue Op3);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+                        SDValue Op1, SDValue Op2, SDValue Op3);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT,
                         const SDValue *Ops, unsigned NumOps);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+                        const SDValue *Ops, unsigned NumOps);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDValue Op1);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, 
+                        SDValue Op1);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT1,
                         MVT VT2, SDValue Op1, SDValue Op2);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
+                        MVT VT2, SDValue Op1, SDValue Op2);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT1,
                         MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
+                        MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
                         const SDValue *Ops, unsigned NumOps);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2,
+                        const SDValue *Ops, unsigned NumOps);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
                         SDValue Op1, SDValue Op2);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
+                        SDValue Op1, SDValue Op2);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
                         SDValue Op1, SDValue Op2, SDValue Op3);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
+                        SDValue Op1, SDValue Op2, SDValue Op3);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
                         const SDValue *Ops, unsigned NumOps);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
+                        const SDValue *Ops, unsigned NumOps);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, MVT VT4,
                         const SDValue *Ops, unsigned NumOps);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
+                        MVT VT4, const SDValue *Ops, unsigned NumOps);
+
   SDNode *getTargetNode(unsigned Opcode, const std::vector &ResultTys,
                         const SDValue *Ops, unsigned NumOps);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl,
+                        const std::vector &ResultTys, const SDValue *Ops,
+                        unsigned NumOps);
 
   /// getNodeIfExists - Get the specified node if it's already available, or
   /// else return NULL.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63259&r1=63258&r2=63259&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jan 28 18:47:48 2009
@@ -1068,6 +1068,20 @@
   return SDValue(N, 0);
 }
 
+SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB, DebugLoc dl) {
+  FoldingSetNodeID ID;
+  AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0);
+  ID.AddPointer(MBB);
+  void *IP = 0;
+  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
+    return SDValue(E, 0);
+  SDNode *N = NodeAllocator.Allocate();
+  new (N) BasicBlockSDNode(MBB, dl);
+  CSEMap.InsertNode(N, IP);
+  AllNodes.push_back(N);
+  return SDValue(N, 0);
+}
+
 SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) {
   FoldingSetNodeID ID;
   AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0);
@@ -1105,6 +1119,15 @@
   return SDValue(N, 0);
 }
 
+SDValue SelectionDAG::getExternalSymbol(const char *Sym, DebugLoc dl, MVT VT) {
+  SDNode *&N = ExternalSymbols[Sym];
+  if (N) return SDValue(N, 0);
+  N = NodeAllocator.Allocate();
+  new (N) ExternalSymbolSDNode(false, dl, Sym, VT);
+  AllNodes.push_back(N);
+  return SDValue(N, 0);
+}
+
 SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) {
   SDNode *&N = TargetExternalSymbols[Sym];
   if (N) return SDValue(N, 0);
@@ -1114,6 +1137,16 @@
   return SDValue(N, 0);
 }
 
+SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, DebugLoc dl, 
+                                              MVT VT) {
+  SDNode *&N = TargetExternalSymbols[Sym];
+  if (N) return SDValue(N, 0);
+  N = NodeAllocator.Allocate();
+  new (N) ExternalSymbolSDNode(true, dl, Sym, VT);
+  AllNodes.push_back(N);
+  return SDValue(N, 0);
+}
+
 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) {
   if ((unsigned)Cond >= CondCodeNodes.size())
     CondCodeNodes.resize(Cond+1);
@@ -1186,6 +1219,23 @@
   return SDValue(N, 0);
 }
 
+SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl,
+                               SDValue Root,
+                               unsigned LabelID) {
+  FoldingSetNodeID ID;
+  SDValue Ops[] = { Root };
+  AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1);
+  ID.AddInteger(LabelID);
+  void *IP = 0;
+  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
+    return SDValue(E, 0);
+  SDNode *N = NodeAllocator.Allocate();
+  new (N) LabelSDNode(Opcode, dl, Root, LabelID);
+  CSEMap.InsertNode(N, IP);
+  AllNodes.push_back(N);
+  return SDValue(N, 0);
+}
+
 SDValue SelectionDAG::getSrcValue(const Value *V) {
   assert((!V || isa(V->getType())) &&
          "SrcValue is not a pointer?");
@@ -3353,6 +3403,34 @@
   return SDValue(N, 0);
 }
 
+SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
+                                SDValue Chain,
+                                SDValue Ptr, SDValue Cmp, 
+                                SDValue Swp, const Value* PtrVal,
+                                unsigned Alignment) {
+  assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op");
+  assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types");
+
+  MVT VT = Cmp.getValueType();
+
+  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
+    Alignment = getMVTAlignment(MemVT);
+
+  SDVTList VTs = getVTList(VT, MVT::Other);
+  FoldingSetNodeID ID;
+  SDValue Ops[] = {Chain, Ptr, Cmp, Swp};
+  AddNodeIDNode(ID, Opcode, VTs, Ops, 4);
+  void* IP = 0;
+  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
+    return SDValue(E, 0);
+  SDNode* N = NodeAllocator.Allocate();
+  new (N) AtomicSDNode(Opcode, dl, VTs, MemVT,
+                       Chain, Ptr, Cmp, Swp, PtrVal, Alignment);
+  CSEMap.InsertNode(N, IP);
+  AllNodes.push_back(N);
+  return SDValue(N, 0);
+}
+
 SDValue SelectionDAG::getAtomic(unsigned Opcode, MVT MemVT,
                                 SDValue Chain,
                                 SDValue Ptr, SDValue Val, 
@@ -3391,6 +3469,44 @@
   return SDValue(N, 0);
 }
 
+SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
+                                SDValue Chain,
+                                SDValue Ptr, SDValue Val, 
+                                const Value* PtrVal,
+                                unsigned Alignment) {
+  assert((Opcode == ISD::ATOMIC_LOAD_ADD ||
+          Opcode == ISD::ATOMIC_LOAD_SUB ||
+          Opcode == ISD::ATOMIC_LOAD_AND ||
+          Opcode == ISD::ATOMIC_LOAD_OR ||
+          Opcode == ISD::ATOMIC_LOAD_XOR ||
+          Opcode == ISD::ATOMIC_LOAD_NAND ||
+          Opcode == ISD::ATOMIC_LOAD_MIN || 
+          Opcode == ISD::ATOMIC_LOAD_MAX ||
+          Opcode == ISD::ATOMIC_LOAD_UMIN || 
+          Opcode == ISD::ATOMIC_LOAD_UMAX ||
+          Opcode == ISD::ATOMIC_SWAP) &&
+         "Invalid Atomic Op");
+
+  MVT VT = Val.getValueType();
+
+  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
+    Alignment = getMVTAlignment(MemVT);
+
+  SDVTList VTs = getVTList(VT, MVT::Other);
+  FoldingSetNodeID ID;
+  SDValue Ops[] = {Chain, Ptr, Val};
+  AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
+  void* IP = 0;
+  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
+    return SDValue(E, 0);
+  SDNode* N = NodeAllocator.Allocate();
+  new (N) AtomicSDNode(Opcode, dl, VTs, MemVT,
+                       Chain, Ptr, Val, PtrVal, Alignment);
+  CSEMap.InsertNode(N, IP);
+  AllNodes.push_back(N);
+  return SDValue(N, 0);
+}
+
 /// getMergeValues - Create a MERGE_VALUES node from the given operands.
 /// Allowed to return something different (and simpler) if Simplify is true.
 SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps) {
@@ -3417,6 +3533,18 @@
 }
 
 SDValue
+SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
+                                  const MVT *VTs, unsigned NumVTs,
+                                  const SDValue *Ops, unsigned NumOps,
+                                  MVT MemVT, const Value *srcValue, int SVOff,
+                                  unsigned Align, bool Vol,
+                                  bool ReadMem, bool WriteMem) {
+  return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps,
+                             MemVT, srcValue, SVOff, Align, Vol,
+                             ReadMem, WriteMem);
+}
+
+SDValue
 SelectionDAG::getMemIntrinsicNode(unsigned Opcode, SDVTList VTList,
                                   const SDValue *Ops, unsigned NumOps,
                                   MVT MemVT, const Value *srcValue, int SVOff,
@@ -3445,6 +3573,34 @@
 }
 
 SDValue
+SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList,
+                                  const SDValue *Ops, unsigned NumOps,
+                                  MVT MemVT, const Value *srcValue, int SVOff,
+                                  unsigned Align, bool Vol,
+                                  bool ReadMem, bool WriteMem) {
+  // Memoize the node unless it returns a flag.
+  MemIntrinsicSDNode *N;
+  if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
+    FoldingSetNodeID ID;
+    AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
+    void *IP = 0;
+    if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
+      return SDValue(E, 0);
+    
+    N = NodeAllocator.Allocate();
+    new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT,
+                               srcValue, SVOff, Align, Vol, ReadMem, WriteMem);
+    CSEMap.InsertNode(N, IP);
+  } else {
+    N = NodeAllocator.Allocate();
+    new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT,
+                               srcValue, SVOff, Align, Vol, ReadMem, WriteMem);
+  }
+  AllNodes.push_back(N);
+  return SDValue(N, 0);
+}
+
+SDValue
 SelectionDAG::getCall(unsigned CallingConv, bool IsVarArgs, bool IsTailCall,
                       bool IsInreg, SDVTList VTs,
                       const SDValue *Operands, unsigned NumOperands) {
@@ -3470,6 +3626,31 @@
 }
 
 SDValue
+SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs,
+                      bool IsTailCall, bool IsInreg, SDVTList VTs,
+                      const SDValue *Operands, unsigned NumOperands) {
+  // Do not include isTailCall in the folding set profile.
+  FoldingSetNodeID ID;
+  AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands);
+  ID.AddInteger(CallingConv);
+  ID.AddInteger(IsVarArgs);
+  void *IP = 0;
+  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) {
+    // Instead of including isTailCall in the folding set, we just
+    // set the flag of the existing node.
+    if (!IsTailCall)
+      cast(E)->setNotTailCall();
+    return SDValue(E, 0);
+  }
+  SDNode *N = NodeAllocator.Allocate();
+  new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall, IsInreg,
+                     VTs, Operands, NumOperands);
+  CSEMap.InsertNode(N, IP);
+  AllNodes.push_back(N);
+  return SDValue(N, 0);
+}
+
+SDValue
 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
                       MVT VT, SDValue Chain,
                       SDValue Ptr, SDValue Offset,
@@ -3520,6 +3701,57 @@
   return SDValue(N, 0);
 }
 
+SDValue
+SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, 
+                      ISD::LoadExtType ExtType, MVT VT, SDValue Chain,
+                      SDValue Ptr, SDValue Offset,
+                      const Value *SV, int SVOffset, MVT EVT,
+                      bool isVolatile, unsigned Alignment) {
+  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
+    Alignment = getMVTAlignment(VT);
+
+  if (VT == EVT) {
+    ExtType = ISD::NON_EXTLOAD;
+  } else if (ExtType == ISD::NON_EXTLOAD) {
+    assert(VT == EVT && "Non-extending load from different memory type!");
+  } else {
+    // Extending load.
+    if (VT.isVector())
+      assert(EVT.getVectorNumElements() == VT.getVectorNumElements() &&
+             "Invalid vector extload!");
+    else
+      assert(EVT.bitsLT(VT) &&
+             "Should only be an extending load, not truncating!");
+    assert((ExtType == ISD::EXTLOAD || VT.isInteger()) &&
+           "Cannot sign/zero extend a FP/Vector load!");
+    assert(VT.isInteger() == EVT.isInteger() &&
+           "Cannot convert from FP to Int or Int -> FP!");
+  }
+
+  bool Indexed = AM != ISD::UNINDEXED;
+  assert((Indexed || Offset.getOpcode() == ISD::UNDEF) &&
+         "Unindexed load with an offset!");
+
+  SDVTList VTs = Indexed ?
+    getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other);
+  SDValue Ops[] = { Chain, Ptr, Offset };
+  FoldingSetNodeID ID;
+  AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
+  ID.AddInteger(AM);
+  ID.AddInteger(ExtType);
+  ID.AddInteger(EVT.getRawBits());
+  ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment));
+  void *IP = 0;
+  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
+    return SDValue(E, 0);
+  SDNode *N = NodeAllocator.Allocate();
+  new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, EVT, SV, SVOffset,
+                     Alignment, isVolatile);
+  CSEMap.InsertNode(N, IP);
+  AllNodes.push_back(N);
+  return SDValue(N, 0);
+}
+
 SDValue SelectionDAG::getLoad(MVT VT,
                               SDValue Chain, SDValue Ptr,
                               const Value *SV, int SVOffset,
@@ -3529,6 +3761,15 @@
                  SV, SVOffset, VT, isVolatile, Alignment);
 }
 
+SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl,
+                              SDValue Chain, SDValue Ptr,
+                              const Value *SV, int SVOffset,
+                              bool isVolatile, unsigned Alignment) {
+  SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
+  return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef,
+                 SV, SVOffset, VT, isVolatile, Alignment);
+}
+
 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT,
                                  SDValue Chain, SDValue Ptr,
                                  const Value *SV,
@@ -3539,6 +3780,16 @@
                  SV, SVOffset, EVT, isVolatile, Alignment);
 }
 
+SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT,
+                                 SDValue Chain, SDValue Ptr,
+                                 const Value *SV,
+                                 int SVOffset, MVT EVT,
+                                 bool isVolatile, unsigned Alignment) {
+  SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
+  return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef,
+                 SV, SVOffset, EVT, isVolatile, Alignment);
+}
+
 SDValue
 SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base,
                              SDValue Offset, ISD::MemIndexedMode AM) {
@@ -3551,6 +3802,18 @@
                  LD->isVolatile(), LD->getAlignment());
 }
 
+SDValue
+SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
+                             SDValue Offset, ISD::MemIndexedMode AM) {
+  LoadSDNode *LD = cast(OrigLoad);
+  assert(LD->getOffset().getOpcode() == ISD::UNDEF &&
+         "Load is already a indexed load!");
+  return getLoad(AM, dl, LD->getExtensionType(), OrigLoad.getValueType(),
+                 LD->getChain(), Base, Offset, LD->getSrcValue(),
+                 LD->getSrcValueOffset(), LD->getMemoryVT(),
+                 LD->isVolatile(), LD->getAlignment());
+}
+
 SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val,
                                SDValue Ptr, const Value *SV, int SVOffset,
                                bool isVolatile, unsigned Alignment) {
@@ -3579,6 +3842,34 @@
   return SDValue(N, 0);
 }
 
+SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val,
+                               SDValue Ptr, const Value *SV, int SVOffset,
+                               bool isVolatile, unsigned Alignment) {
+  MVT VT = Val.getValueType();
+
+  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
+    Alignment = getMVTAlignment(VT);
+
+  SDVTList VTs = getVTList(MVT::Other);
+  SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
+  SDValue Ops[] = { Chain, Val, Ptr, Undef };
+  FoldingSetNodeID ID;
+  AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
+  ID.AddInteger(ISD::UNINDEXED);
+  ID.AddInteger(false);
+  ID.AddInteger(VT.getRawBits());
+  ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment));
+  void *IP = 0;
+  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
+    return SDValue(E, 0);
+  SDNode *N = NodeAllocator.Allocate();
+  new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false,
+                      VT, SV, SVOffset, Alignment, isVolatile);
+  CSEMap.InsertNode(N, IP);
+  AllNodes.push_back(N);
+  return SDValue(N, 0);
+}
+
 SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val,
                                     SDValue Ptr, const Value *SV,
                                     int SVOffset, MVT SVT,
@@ -3615,6 +3906,42 @@
   return SDValue(N, 0);
 }
 
+SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,
+                                    SDValue Ptr, const Value *SV,
+                                    int SVOffset, MVT SVT,
+                                    bool isVolatile, unsigned Alignment) {
+  MVT VT = Val.getValueType();
+
+  if (VT == SVT)
+    return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment);
+
+  assert(VT.bitsGT(SVT) && "Not a truncation?");
+  assert(VT.isInteger() == SVT.isInteger() &&
+         "Can't do FP-INT conversion!");
+
+  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
+    Alignment = getMVTAlignment(VT);
+
+  SDVTList VTs = getVTList(MVT::Other);
+  SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
+  SDValue Ops[] = { Chain, Val, Ptr, Undef };
+  FoldingSetNodeID ID;
+  AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
+  ID.AddInteger(ISD::UNINDEXED);
+  ID.AddInteger(1);
+  ID.AddInteger(SVT.getRawBits());
+  ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment));
+  void *IP = 0;
+  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
+    return SDValue(E, 0);
+  SDNode *N = NodeAllocator.Allocate();
+  new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true,
+                      SVT, SV, SVOffset, Alignment, isVolatile);
+  CSEMap.InsertNode(N, IP);
+  AllNodes.push_back(N);
+  return SDValue(N, 0);
+}
+
 SDValue
 SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base,
                               SDValue Offset, ISD::MemIndexedMode AM) {
@@ -3642,6 +3969,33 @@
   return SDValue(N, 0);
 }
 
+SDValue
+SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base,
+                              SDValue Offset, ISD::MemIndexedMode AM) {
+  StoreSDNode *ST = cast(OrigStore);
+  assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
+         "Store is already a indexed store!");
+  SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
+  SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset };
+  FoldingSetNodeID ID;
+  AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
+  ID.AddInteger(AM);
+  ID.AddInteger(ST->isTruncatingStore());
+  ID.AddInteger(ST->getMemoryVT().getRawBits());
+  ID.AddInteger(ST->getRawFlags());
+  void *IP = 0;
+  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
+    return SDValue(E, 0);
+  SDNode *N = NodeAllocator.Allocate();
+  new (N) StoreSDNode(Ops, dl, VTs, AM,
+                      ST->isTruncatingStore(), ST->getMemoryVT(),
+                      ST->getSrcValue(), ST->getSrcValueOffset(),
+                      ST->getAlignment(), ST->isVolatile());
+  CSEMap.InsertNode(N, IP);
+  AllNodes.push_back(N);
+  return SDValue(N, 0);
+}
+
 SDValue SelectionDAG::getVAArg(MVT VT,
                                SDValue Chain, SDValue Ptr,
                                SDValue SV) {
@@ -4395,32 +4749,70 @@
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) {
   return getNode(~Opcode, VT).getNode();
 }
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) {
+  return getNode(~Opcode, dl, VT).getNode();
+}
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) {
   return getNode(~Opcode, VT, Op1).getNode();
 }
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+                                    SDValue Op1) {
+  return getNode(~Opcode, dl, VT, Op1).getNode();
+}
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
                                     SDValue Op1, SDValue Op2) {
   return getNode(~Opcode, VT, Op1, Op2).getNode();
 }
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+                                    SDValue Op1, SDValue Op2) {
+  return getNode(~Opcode, dl, VT, Op1, Op2).getNode();
+}
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
                                     SDValue Op1, SDValue Op2,
                                     SDValue Op3) {
   return getNode(~Opcode, VT, Op1, Op2, Op3).getNode();
 }
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+                                    SDValue Op1, SDValue Op2,
+                                    SDValue Op3) {
+  return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode();
+}
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
                                     const SDValue *Ops, unsigned NumOps) {
   return getNode(~Opcode, VT, Ops, NumOps).getNode();
 }
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+                                    const SDValue *Ops, unsigned NumOps) {
+  return getNode(~Opcode, dl, VT, Ops, NumOps).getNode();
+}
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2);
   SDValue Op;
   return getNode(~Opcode, VTs, 2, &Op, 0).getNode();
 }
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 
+                                    MVT VT1, MVT VT2) {
+  const MVT *VTs = getNodeValueTypes(VT1, VT2);
+  SDValue Op;
+  return getNode(~Opcode, dl, VTs, 2, &Op, 0).getNode();
+}
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
                                     MVT VT2, SDValue Op1) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2);
   return getNode(~Opcode, VTs, 2, &Op1, 1).getNode();
 }
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
+                                    MVT VT2, SDValue Op1) {
+  const MVT *VTs = getNodeValueTypes(VT1, VT2);
+  return getNode(~Opcode, dl, VTs, 2, &Op1, 1).getNode();
+}
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
                                     MVT VT2, SDValue Op1,
                                     SDValue Op2) {
@@ -4428,6 +4820,14 @@
   SDValue Ops[] = { Op1, Op2 };
   return getNode(~Opcode, VTs, 2, Ops, 2).getNode();
 }
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
+                                    MVT VT2, SDValue Op1,
+                                    SDValue Op2) {
+  const MVT *VTs = getNodeValueTypes(VT1, VT2);
+  SDValue Ops[] = { Op1, Op2 };
+  return getNode(~Opcode, dl, VTs, 2, Ops, 2).getNode();
+}
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
                                     MVT VT2, SDValue Op1,
                                     SDValue Op2, SDValue Op3) {
@@ -4435,17 +4835,40 @@
   SDValue Ops[] = { Op1, Op2, Op3 };
   return getNode(~Opcode, VTs, 2, Ops, 3).getNode();
 }
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
+                                    MVT VT2, SDValue Op1,
+                                    SDValue Op2, SDValue Op3) {
+  const MVT *VTs = getNodeValueTypes(VT1, VT2);
+  SDValue Ops[] = { Op1, Op2, Op3 };
+  return getNode(~Opcode, dl, VTs, 2, Ops, 3).getNode();
+}
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
                                     const SDValue *Ops, unsigned NumOps) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2);
   return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode();
 }
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 
+                                    MVT VT1, MVT VT2,
+                                    const SDValue *Ops, unsigned NumOps) {
+  const MVT *VTs = getNodeValueTypes(VT1, VT2);
+  return getNode(~Opcode, dl, VTs, 2, Ops, NumOps).getNode();
+}
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
                                     SDValue Op1, SDValue Op2) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
   SDValue Ops[] = { Op1, Op2 };
   return getNode(~Opcode, VTs, 3, Ops, 2).getNode();
 }
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
+                                    MVT VT1, MVT VT2, MVT VT3,
+                                    SDValue Op1, SDValue Op2) {
+  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
+  SDValue Ops[] = { Op1, Op2 };
+  return getNode(~Opcode, dl, VTs, 3, Ops, 2).getNode();
+}
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
                                     SDValue Op1, SDValue Op2,
                                     SDValue Op3) {
@@ -4453,11 +4876,27 @@
   SDValue Ops[] = { Op1, Op2, Op3 };
   return getNode(~Opcode, VTs, 3, Ops, 3).getNode();
 }
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
+                                    MVT VT1, MVT VT2, MVT VT3,
+                                    SDValue Op1, SDValue Op2,
+                                    SDValue Op3) {
+  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
+  SDValue Ops[] = { Op1, Op2, Op3 };
+  return getNode(~Opcode, dl, VTs, 3, Ops, 3).getNode();
+}
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
                                     const SDValue *Ops, unsigned NumOps) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
   return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
 }
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
+                                    MVT VT1, MVT VT2, MVT VT3,
+                                    const SDValue *Ops, unsigned NumOps) {
+  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
+  return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
+}
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
                                     MVT VT2, MVT VT3, MVT VT4,
                                     const SDValue *Ops, unsigned NumOps) {
@@ -4469,6 +4908,18 @@
   const MVT *VTs = getNodeValueTypes(VTList);
   return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode();
 }
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
+                                    MVT VT2, MVT VT3, MVT VT4,
+                                    const SDValue *Ops, unsigned NumOps) {
+  std::vector VTList;
+  VTList.push_back(VT1);
+  VTList.push_back(VT2);
+  VTList.push_back(VT3);
+  VTList.push_back(VT4);
+  const MVT *VTs = getNodeValueTypes(VTList);
+  return getNode(~Opcode, dl, VTs, 4, Ops, NumOps).getNode();
+}
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
                                     const std::vector &ResultTys,
                                     const SDValue *Ops, unsigned NumOps) {
@@ -4476,6 +4927,13 @@
   return getNode(~Opcode, VTs, ResultTys.size(),
                  Ops, NumOps).getNode();
 }
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
+                                    const std::vector &ResultTys,
+                                    const SDValue *Ops, unsigned NumOps) {
+  const MVT *VTs = getNodeValueTypes(ResultTys);
+  return getNode(~Opcode, dl, VTs, ResultTys.size(),
+                 Ops, NumOps).getNode();
+}
 
 /// getNodeIfExists - Get the specified node if it's already available, or
 /// else return NULL.




From bob.wilson at apple.com  Wed Jan 28 19:02:41 2009
From: bob.wilson at apple.com (Bob Wilson)
Date: Thu, 29 Jan 2009 01:02:41 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63260 - in
 /llvm-gcc-4.2/trunk/gcc/config/arm: darwin-libgcc.10.4.ver
 darwin-libgcc.10.5.ver
Message-ID: <200901290102.n0T12f3j030618@zion.cs.uiuc.edu>

Author: bwilson
Date: Wed Jan 28 19:02:41 2009
New Revision: 63260

URL: http://llvm.org/viewvc/llvm-project?rev=63260&view=rev
Log:
Delete unused files.

Removed:
    llvm-gcc-4.2/trunk/gcc/config/arm/darwin-libgcc.10.4.ver
    llvm-gcc-4.2/trunk/gcc/config/arm/darwin-libgcc.10.5.ver

Removed: llvm-gcc-4.2/trunk/gcc/config/arm/darwin-libgcc.10.4.ver
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/darwin-libgcc.10.4.ver?rev=63259&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/arm/darwin-libgcc.10.4.ver (original)
+++ llvm-gcc-4.2/trunk/gcc/config/arm/darwin-libgcc.10.4.ver (removed)
@@ -1,123 +0,0 @@
-# APPLE LOCAL file ARM libgcc_s exports
-# For now, this file should include all symbols available in libgcc_s*.dylib,
-#   since a new libgcc_s should be available on the platform with each compiler
-#   release.  Once a platform is released, these files can be stabilized to
-#   match the release.
-
-# The functions that are commented out below (addsf3, subsf3, floatdisf,
-# floatsisf) are actually in the 10.4-based libgcc, but are in the same
-# object file as functions which are new in 10.5 (floatundisf, floatunsisf).
-# So, pulling in floatundisf from the dylib causes linktime duplicate
-# symbol errors because addsf3 and others get pulled in from both the
-# libgcc dylib and archive.
-
-__Unwind_Backtrace
-__Unwind_DeleteException
-__Unwind_FindEnclosingFunction
-__Unwind_Find_FDE
-__Unwind_GetCFA
-__Unwind_GetDataRelBase
-__Unwind_GetGR
-__Unwind_GetIP
-__Unwind_GetLanguageSpecificData
-__Unwind_GetRegionStart
-__Unwind_GetTextRelBase
-__Unwind_SetGR
-__Unwind_SetIP
-__Unwind_SjLj_ForcedUnwind
-__Unwind_SjLj_RaiseException
-__Unwind_SjLj_Register
-__Unwind_SjLj_Resume
-__Unwind_SjLj_Resume_or_Rethrow
-__Unwind_SjLj_Unregister
-___absvdi2
-___absvsi2
-___adddf3
-# ___addsf3
-___addvdi3
-___addvsi3
-___ashldi3
-___ashrdi3
-___clear_cache
-___clzdi2
-___clzsi2
-___cmpdi2
-___ctzdi2
-___ctzsi2
-___deregister_frame
-___deregister_frame_info
-___deregister_frame_info_bases
-___divdc3
-___divdf3
-___divdi3
-___divsc3
-___divsf3
-___divsi3
-___enable_execute_stack
-___eqdf2
-___eqsf2
-___extendsfdf2
-___ffsdi2
-___fixdfdi
-___fixdfsi
-___fixsfdi
-___fixsfsi
-___fixunsdfdi
-___fixunsdfsi
-___fixunssfdi
-___fixunssfsi
-___floatdidf
-# ___floatdisf
-___floatsidf
-# ___floatsisf
-___gcc_personality_sj0
-___gedf2
-___gesf2
-___gtdf2
-___gtsf2
-___ledf2
-___lesf2
-___lshrdi3
-___ltdf2
-___ltsf2
-___moddi3
-___modsi3
-___muldc3
-___muldf3
-___muldi3
-___mulsc3
-___mulsf3
-___mulvdi3
-___mulvsi3
-___nedf2
-___negdf2
-___negdi2
-___negsf2
-___negvdi2
-___negvsi2
-___nesf2
-___paritydi2
-___paritysi2
-___popcountdi2
-___popcountsi2
-___powidf2
-___powisf2
-___register_frame
-___register_frame_info
-___register_frame_info_bases
-___register_frame_info_table
-___register_frame_info_table_bases
-___register_frame_table
-___subdf3
-# ___subsf3
-___subvdi3
-___subvsi3
-___truncdfsf2
-___ucmpdi2
-___udivdi3
-___udivmoddi4
-___udivsi3
-___umoddi3
-___umodsi3
-___unorddf2
-___unordsf2

Removed: llvm-gcc-4.2/trunk/gcc/config/arm/darwin-libgcc.10.5.ver
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/darwin-libgcc.10.5.ver?rev=63259&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/arm/darwin-libgcc.10.5.ver (original)
+++ llvm-gcc-4.2/trunk/gcc/config/arm/darwin-libgcc.10.5.ver (removed)
@@ -1,122 +0,0 @@
-# APPLE LOCAL file ARM libgcc_s exports
-# For now, this file should include all symbols available in libgcc_s*.dylib,
-#   since a new libgcc_s should be available on the platform with each compiler
-#   release.  Once a platform is released, these files can be stabilized to
-#   match the release.
-__Unwind_Backtrace
-__Unwind_DeleteException
-__Unwind_FindEnclosingFunction
-__Unwind_Find_FDE
-__Unwind_GetCFA
-__Unwind_GetDataRelBase
-__Unwind_GetGR
-__Unwind_GetIP
-__Unwind_GetIPInfo
-__Unwind_GetLanguageSpecificData
-__Unwind_GetRegionStart
-__Unwind_GetTextRelBase
-__Unwind_SetGR
-__Unwind_SetIP
-__Unwind_SjLj_ForcedUnwind
-__Unwind_SjLj_RaiseException
-__Unwind_SjLj_Register
-__Unwind_SjLj_Resume
-__Unwind_SjLj_Resume_or_Rethrow
-__Unwind_SjLj_Unregister
-___absvdi2
-___absvsi2
-___adddf3
-___addsf3
-___addvdi3
-___addvsi3
-___ashldi3
-___ashrdi3
-___bswapdi2
-___bswapsi2
-___clear_cache
-___clzdi2
-___clzsi2
-___cmpdi2
-___ctzdi2
-___ctzsi2
-___deregister_frame
-___deregister_frame_info
-___deregister_frame_info_bases
-___divdc3
-___divdf3
-___divdi3
-___divsc3
-___divsf3
-___divsi3
-___enable_execute_stack
-___eqdf2
-___eqsf2
-___extendsfdf2
-___ffsdi2
-___fixdfdi
-___fixdfsi
-___fixsfdi
-___fixsfsi
-___fixunsdfdi
-___fixunsdfsi
-___fixunssfdi
-___fixunssfsi
-___floatdidf
-___floatdisf
-___floatsidf
-___floatsisf
-___floatundidf
-___floatundisf
-___floatunsidf
-___floatunsisf
-___gcc_personality_sj0
-___gedf2
-___gesf2
-___gtdf2
-___gtsf2
-___ledf2
-___lesf2
-___lshrdi3
-___ltdf2
-___ltsf2
-___moddi3
-___modsi3
-___muldc3
-___muldf3
-___muldi3
-___mulsc3
-___mulsf3
-___mulvdi3
-___mulvsi3
-___nedf2
-___negdf2
-___negdi2
-___negsf2
-___negvdi2
-___negvsi2
-___nesf2
-___paritydi2
-___paritysi2
-___popcountdi2
-___popcountsi2
-___powidf2
-___powisf2
-___register_frame
-___register_frame_info
-___register_frame_info_bases
-___register_frame_info_table
-___register_frame_info_table_bases
-___register_frame_table
-___subdf3
-___subsf3
-___subvdi3
-___subvsi3
-___truncdfsf2
-___ucmpdi2
-___udivdi3
-___udivmoddi4
-___udivsi3
-___umoddi3
-___umodsi3
-___unorddf2
-___unordsf2




From gohman at apple.com  Wed Jan 28 19:06:02 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 28 Jan 2009 17:06:02 -0800
Subject: [llvm-commits] [llvm] r63259 - in /llvm/trunk:
	include/llvm/CodeGen/SelectionDAG.h
	lib/CodeGen/SelectionDAG/SelectionDAG.cpp
In-Reply-To: <200901290047.n0T0lmXG030099@zion.cs.uiuc.edu>
References: <200901290047.n0T0lmXG030099@zion.cs.uiuc.edu>
Message-ID: <83C98C61-F72A-4859-9E96-BDB92C6D2C96@apple.com>

Hi Dale,

Instead of duplicating all that code, could you make the non-DebugLoc- 
aware
accessors just thin wrappers around the DebugLoc-aware ones, like this:

SDValue getBasicBlock(MachineBasicBlock *MBB) {
   return getBasicBLock(MBB, DebugLoc::getUnknownLoc());
}

and so on? Thanks,

Dan

On Jan 28, 2009, at 4:47 PM, Dale Johannesen wrote:

> Author: johannes
> Date: Wed Jan 28 18:47:48 2009
> New Revision: 63259
>
> URL: http://llvm.org/viewvc/llvm-project?rev=63259&view=rev
> Log:
> Add DebugLoc-sensitive versions of many node creation
> functions.  Currently omitted:  memcpy, memmove, memset.
>
>
> Modified:
>    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63259&r1=63258&r2=63259&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Jan 28  
> 18:47:48 2009
> @@ -307,14 +307,19 @@
>     return getConstantPool(C, VT, Align, Offset, true);
>   }
>   SDValue getBasicBlock(MachineBasicBlock *MBB);
> +  SDValue getBasicBlock(MachineBasicBlock *MBB, DebugLoc dl);
>   SDValue getExternalSymbol(const char *Sym, MVT VT);
> +  SDValue getExternalSymbol(const char *Sym, DebugLoc dl, MVT VT);
>   SDValue getTargetExternalSymbol(const char *Sym, MVT VT);
> +  SDValue getTargetExternalSymbol(const char *Sym, DebugLoc dl, MVT  
> VT);
>   SDValue getArgFlags(ISD::ArgFlagsTy Flags);
>   SDValue getValueType(MVT);
>   SDValue getRegister(unsigned Reg, MVT VT);
>   SDValue getDbgStopPoint(SDValue Root, unsigned Line, unsigned Col,
>                           Value *CU);
>   SDValue getLabel(unsigned Opcode, SDValue Root, unsigned LabelID);
> +  SDValue getLabel(unsigned Opcode, DebugLoc dl, SDValue Root,
> +                   unsigned LabelID);
>
>   SDValue getCopyToReg(SDValue Chain, unsigned Reg, SDValue N) {
>     return getNode(ISD::CopyToReg, MVT::Other, Chain,
> @@ -506,12 +511,18 @@
>   SDValue getAtomic(unsigned Opcode, MVT MemVT, SDValue Chain,  
> SDValue Ptr,
>                     SDValue Cmp, SDValue Swp, const Value* PtrVal,
>                     unsigned Alignment=0);
> +  SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,  
> SDValue Chain,
> +                    SDValue Ptr, SDValue Cmp, SDValue Swp, const  
> Value* PtrVal,
> +                    unsigned Alignment=0);
>
>   /// getAtomic - Gets a node for an atomic op, produces result and  
> chain and
>   /// takes 2 operands.
>   SDValue getAtomic(unsigned Opcode, MVT MemVT, SDValue Chain,  
> SDValue Ptr,
>                     SDValue Val, const Value* PtrVal,
>                     unsigned Alignment = 0);
> +  SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,  
> SDValue Chain,
> +                    SDValue Ptr, SDValue Val, const Value* PtrVal,
> +                    unsigned Alignment = 0);
>
>   /// getMemIntrinsicNode - Creates a MemIntrinsicNode that may  
> produce a
>   /// result and takes a list of operands.
> @@ -521,12 +532,23 @@
>                               MVT MemVT, const Value *srcValue, int  
> SVOff,
>                               unsigned Align = 0, bool Vol = false,
>                               bool ReadMem = true, bool WriteMem =  
> true);
> +  SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
> +                              const MVT *VTs, unsigned NumVTs,
> +                              const SDValue *Ops, unsigned NumOps,
> +                              MVT MemVT, const Value *srcValue, int  
> SVOff,
> +                              unsigned Align = 0, bool Vol = false,
> +                              bool ReadMem = true, bool WriteMem =  
> true);
>
>   SDValue getMemIntrinsicNode(unsigned Opcode, SDVTList VTList,
>                               const SDValue *Ops, unsigned NumOps,
>                               MVT MemVT, const Value *srcValue, int  
> SVOff,
>                               unsigned Align = 0, bool Vol = false,
>                               bool ReadMem = true, bool WriteMem =  
> true);
> +  SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,  
> SDVTList VTList,
> +                              const SDValue *Ops, unsigned NumOps,
> +                              MVT MemVT, const Value *srcValue, int  
> SVOff,
> +                              unsigned Align = 0, bool Vol = false,
> +                              bool ReadMem = true, bool WriteMem =  
> true);
>
>   /// getMergeValues - Create a MERGE_VALUES node from the given  
> operands.
>   SDValue getMergeValues(const SDValue *Ops, unsigned NumOps);
> @@ -536,6 +558,9 @@
>   SDValue getCall(unsigned CallingConv, bool IsVarArgs, bool  
> IsTailCall,
>                   bool isInreg, SDVTList VTs, const SDValue *Operands,
>                   unsigned NumOperands);
> +  SDValue getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs,
> +                  bool IsTailCall, bool isInreg, SDVTList VTs,
> +                  const SDValue *Operands, unsigned NumOperands);
>
>   /// getLoad - Loads are not normal binary operators: their result  
> type is not
>   /// determined by their operands, and they produce a value AND a  
> token chain.
> @@ -543,28 +568,50 @@
>   SDValue getLoad(MVT VT, SDValue Chain, SDValue Ptr,
>                     const Value *SV, int SVOffset, bool  
> isVolatile=false,
>                     unsigned Alignment=0);
> +  SDValue getLoad(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
> +                    const Value *SV, int SVOffset, bool  
> isVolatile=false,
> +                    unsigned Alignment=0);
>   SDValue getExtLoad(ISD::LoadExtType ExtType, MVT VT,
>                        SDValue Chain, SDValue Ptr, const Value *SV,
>                        int SVOffset, MVT EVT, bool isVolatile=false,
>                        unsigned Alignment=0);
> +  SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT,
> +                       SDValue Chain, SDValue Ptr, const Value *SV,
> +                       int SVOffset, MVT EVT, bool isVolatile=false,
> +                       unsigned Alignment=0);
>   SDValue getIndexedLoad(SDValue OrigLoad, SDValue Base,
>                            SDValue Offset, ISD::MemIndexedMode AM);
> +  SDValue getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
> +                           SDValue Offset, ISD::MemIndexedMode AM);
>   SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
>                     MVT VT, SDValue Chain,
>                     SDValue Ptr, SDValue Offset,
>                     const Value *SV, int SVOffset, MVT EVT,
>                     bool isVolatile=false, unsigned Alignment=0);
> +  SDValue getLoad(ISD::MemIndexedMode AM, DebugLoc dl,  
> ISD::LoadExtType ExtType,
> +                    MVT VT, SDValue Chain,
> +                    SDValue Ptr, SDValue Offset,
> +                    const Value *SV, int SVOffset, MVT EVT,
> +                    bool isVolatile=false, unsigned Alignment=0);
>
>   /// getStore - Helper function to build ISD::STORE nodes.
>   ///
>   SDValue getStore(SDValue Chain, SDValue Val, SDValue Ptr,
>                      const Value *SV, int SVOffset, bool  
> isVolatile=false,
>                      unsigned Alignment=0);
> +  SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue  
> Ptr,
> +                     const Value *SV, int SVOffset, bool  
> isVolatile=false,
> +                     unsigned Alignment=0);
>   SDValue getTruncStore(SDValue Chain, SDValue Val, SDValue Ptr,
>                           const Value *SV, int SVOffset, MVT TVT,
>                           bool isVolatile=false, unsigned  
> Alignment=0);
> +  SDValue getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,  
> SDValue Ptr,
> +                          const Value *SV, int SVOffset, MVT TVT,
> +                          bool isVolatile=false, unsigned  
> Alignment=0);
>   SDValue getIndexedStore(SDValue OrigStoe, SDValue Base,
>                            SDValue Offset, ISD::MemIndexedMode AM);
> +  SDValue getIndexedStore(SDValue OrigStoe, DebugLoc dl, SDValue  
> Base,
> +                           SDValue Offset, ISD::MemIndexedMode AM);
>
>   /// getSrcValue - Construct a node to track a Value* through the  
> backend.
>   SDValue getSrcValue(const Value *v);
> @@ -652,30 +699,72 @@
>   /// node of the specified opcode and operands, it returns that  
> node instead of
>   /// the current one.
>   SDNode *getTargetNode(unsigned Opcode, MVT VT);
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT);
> +
>   SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1);
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,  
> SDValue Op1);
> +
>   SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1,  
> SDValue Op2);
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,  
> SDValue Op1,
> +                        SDValue Op2);
> +
>   SDNode *getTargetNode(unsigned Opcode, MVT VT,
>                         SDValue Op1, SDValue Op2, SDValue Op3);
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
> +                        SDValue Op1, SDValue Op2, SDValue Op3);
> +
>   SDNode *getTargetNode(unsigned Opcode, MVT VT,
>                         const SDValue *Ops, unsigned NumOps);
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
> +                        const SDValue *Ops, unsigned NumOps);
> +
>   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2);
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT  
> VT2);
> +
>   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDValue  
> Op1);
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT  
> VT2,
> +                        SDValue Op1);
> +
>   SDNode *getTargetNode(unsigned Opcode, MVT VT1,
>                         MVT VT2, SDValue Op1, SDValue Op2);
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
> +                        MVT VT2, SDValue Op1, SDValue Op2);
> +
>   SDNode *getTargetNode(unsigned Opcode, MVT VT1,
>                         MVT VT2, SDValue Op1, SDValue Op2, SDValue  
> Op3);
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
> +                        MVT VT2, SDValue Op1, SDValue Op2, SDValue  
> Op3);
> +
>   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
>                         const SDValue *Ops, unsigned NumOps);
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT  
> VT2,
> +                        const SDValue *Ops, unsigned NumOps);
> +
>   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
>                         SDValue Op1, SDValue Op2);
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT  
> VT2, MVT VT3,
> +                        SDValue Op1, SDValue Op2);
> +
>   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
>                         SDValue Op1, SDValue Op2, SDValue Op3);
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT  
> VT2, MVT VT3,
> +                        SDValue Op1, SDValue Op2, SDValue Op3);
> +
>   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
>                         const SDValue *Ops, unsigned NumOps);
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT  
> VT2, MVT VT3,
> +                        const SDValue *Ops, unsigned NumOps);
> +
>   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,  
> MVT VT4,
>                         const SDValue *Ops, unsigned NumOps);
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT  
> VT2, MVT VT3,
> +                        MVT VT4, const SDValue *Ops, unsigned  
> NumOps);
> +
>   SDNode *getTargetNode(unsigned Opcode, const std::vector  
> &ResultTys,
>                         const SDValue *Ops, unsigned NumOps);
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl,
> +                        const std::vector &ResultTys, const  
> SDValue *Ops,
> +                        unsigned NumOps);
>
>   /// getNodeIfExists - Get the specified node if it's already  
> available, or
>   /// else return NULL.
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63259&r1=63258&r2=63259&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jan 28  
> 18:47:48 2009
> @@ -1068,6 +1068,20 @@
>   return SDValue(N, 0);
> }
>
> +SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB,  
> DebugLoc dl) {
> +  FoldingSetNodeID ID;
> +  AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0);
> +  ID.AddPointer(MBB);
> +  void *IP = 0;
> +  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
> +    return SDValue(E, 0);
> +  SDNode *N = NodeAllocator.Allocate();
> +  new (N) BasicBlockSDNode(MBB, dl);
> +  CSEMap.InsertNode(N, IP);
> +  AllNodes.push_back(N);
> +  return SDValue(N, 0);
> +}
> +
> SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) {
>   FoldingSetNodeID ID;
>   AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0);
> @@ -1105,6 +1119,15 @@
>   return SDValue(N, 0);
> }
>
> +SDValue SelectionDAG::getExternalSymbol(const char *Sym, DebugLoc  
> dl, MVT VT) {
> +  SDNode *&N = ExternalSymbols[Sym];
> +  if (N) return SDValue(N, 0);
> +  N = NodeAllocator.Allocate();
> +  new (N) ExternalSymbolSDNode(false, dl, Sym, VT);
> +  AllNodes.push_back(N);
> +  return SDValue(N, 0);
> +}
> +
> SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT  
> VT) {
>   SDNode *&N = TargetExternalSymbols[Sym];
>   if (N) return SDValue(N, 0);
> @@ -1114,6 +1137,16 @@
>   return SDValue(N, 0);
> }
>
> +SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym,  
> DebugLoc dl,
> +                                              MVT VT) {
> +  SDNode *&N = TargetExternalSymbols[Sym];
> +  if (N) return SDValue(N, 0);
> +  N = NodeAllocator.Allocate();
> +  new (N) ExternalSymbolSDNode(true, dl, Sym, VT);
> +  AllNodes.push_back(N);
> +  return SDValue(N, 0);
> +}
> +
> SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) {
>   if ((unsigned)Cond >= CondCodeNodes.size())
>     CondCodeNodes.resize(Cond+1);
> @@ -1186,6 +1219,23 @@
>   return SDValue(N, 0);
> }
>
> +SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl,
> +                               SDValue Root,
> +                               unsigned LabelID) {
> +  FoldingSetNodeID ID;
> +  SDValue Ops[] = { Root };
> +  AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1);
> +  ID.AddInteger(LabelID);
> +  void *IP = 0;
> +  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
> +    return SDValue(E, 0);
> +  SDNode *N = NodeAllocator.Allocate();
> +  new (N) LabelSDNode(Opcode, dl, Root, LabelID);
> +  CSEMap.InsertNode(N, IP);
> +  AllNodes.push_back(N);
> +  return SDValue(N, 0);
> +}
> +
> SDValue SelectionDAG::getSrcValue(const Value *V) {
>   assert((!V || isa(V->getType())) &&
>          "SrcValue is not a pointer?");
> @@ -3353,6 +3403,34 @@
>   return SDValue(N, 0);
> }
>
> +SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT  
> MemVT,
> +                                SDValue Chain,
> +                                SDValue Ptr, SDValue Cmp,
> +                                SDValue Swp, const Value* PtrVal,
> +                                unsigned Alignment) {
> +  assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op");
> +  assert(Cmp.getValueType() == Swp.getValueType() && "Invalid  
> Atomic Op Types");
> +
> +  MVT VT = Cmp.getValueType();
> +
> +  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
> +    Alignment = getMVTAlignment(MemVT);
> +
> +  SDVTList VTs = getVTList(VT, MVT::Other);
> +  FoldingSetNodeID ID;
> +  SDValue Ops[] = {Chain, Ptr, Cmp, Swp};
> +  AddNodeIDNode(ID, Opcode, VTs, Ops, 4);
> +  void* IP = 0;
> +  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
> +    return SDValue(E, 0);
> +  SDNode* N = NodeAllocator.Allocate();
> +  new (N) AtomicSDNode(Opcode, dl, VTs, MemVT,
> +                       Chain, Ptr, Cmp, Swp, PtrVal, Alignment);
> +  CSEMap.InsertNode(N, IP);
> +  AllNodes.push_back(N);
> +  return SDValue(N, 0);
> +}
> +
> SDValue SelectionDAG::getAtomic(unsigned Opcode, MVT MemVT,
>                                 SDValue Chain,
>                                 SDValue Ptr, SDValue Val,
> @@ -3391,6 +3469,44 @@
>   return SDValue(N, 0);
> }
>
> +SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT  
> MemVT,
> +                                SDValue Chain,
> +                                SDValue Ptr, SDValue Val,
> +                                const Value* PtrVal,
> +                                unsigned Alignment) {
> +  assert((Opcode == ISD::ATOMIC_LOAD_ADD ||
> +          Opcode == ISD::ATOMIC_LOAD_SUB ||
> +          Opcode == ISD::ATOMIC_LOAD_AND ||
> +          Opcode == ISD::ATOMIC_LOAD_OR ||
> +          Opcode == ISD::ATOMIC_LOAD_XOR ||
> +          Opcode == ISD::ATOMIC_LOAD_NAND ||
> +          Opcode == ISD::ATOMIC_LOAD_MIN ||
> +          Opcode == ISD::ATOMIC_LOAD_MAX ||
> +          Opcode == ISD::ATOMIC_LOAD_UMIN ||
> +          Opcode == ISD::ATOMIC_LOAD_UMAX ||
> +          Opcode == ISD::ATOMIC_SWAP) &&
> +         "Invalid Atomic Op");
> +
> +  MVT VT = Val.getValueType();
> +
> +  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
> +    Alignment = getMVTAlignment(MemVT);
> +
> +  SDVTList VTs = getVTList(VT, MVT::Other);
> +  FoldingSetNodeID ID;
> +  SDValue Ops[] = {Chain, Ptr, Val};
> +  AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
> +  void* IP = 0;
> +  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
> +    return SDValue(E, 0);
> +  SDNode* N = NodeAllocator.Allocate();
> +  new (N) AtomicSDNode(Opcode, dl, VTs, MemVT,
> +                       Chain, Ptr, Val, PtrVal, Alignment);
> +  CSEMap.InsertNode(N, IP);
> +  AllNodes.push_back(N);
> +  return SDValue(N, 0);
> +}
> +
> /// getMergeValues - Create a MERGE_VALUES node from the given  
> operands.
> /// Allowed to return something different (and simpler) if Simplify  
> is true.
> SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned  
> NumOps) {
> @@ -3417,6 +3533,18 @@
> }
>
> SDValue
> +SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
> +                                  const MVT *VTs, unsigned NumVTs,
> +                                  const SDValue *Ops, unsigned  
> NumOps,
> +                                  MVT MemVT, const Value *srcValue,  
> int SVOff,
> +                                  unsigned Align, bool Vol,
> +                                  bool ReadMem, bool WriteMem) {
> +  return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs),  
> Ops, NumOps,
> +                             MemVT, srcValue, SVOff, Align, Vol,
> +                             ReadMem, WriteMem);
> +}
> +
> +SDValue
> SelectionDAG::getMemIntrinsicNode(unsigned Opcode, SDVTList VTList,
>                                   const SDValue *Ops, unsigned NumOps,
>                                   MVT MemVT, const Value *srcValue,  
> int SVOff,
> @@ -3445,6 +3573,34 @@
> }
>
> SDValue
> +SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,  
> SDVTList VTList,
> +                                  const SDValue *Ops, unsigned  
> NumOps,
> +                                  MVT MemVT, const Value *srcValue,  
> int SVOff,
> +                                  unsigned Align, bool Vol,
> +                                  bool ReadMem, bool WriteMem) {
> +  // Memoize the node unless it returns a flag.
> +  MemIntrinsicSDNode *N;
> +  if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
> +    FoldingSetNodeID ID;
> +    AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
> +    void *IP = 0;
> +    if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
> +      return SDValue(E, 0);
> +
> +    N = NodeAllocator.Allocate();
> +    new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps,  
> MemVT,
> +                               srcValue, SVOff, Align, Vol,  
> ReadMem, WriteMem);
> +    CSEMap.InsertNode(N, IP);
> +  } else {
> +    N = NodeAllocator.Allocate();
> +    new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps,  
> MemVT,
> +                               srcValue, SVOff, Align, Vol,  
> ReadMem, WriteMem);
> +  }
> +  AllNodes.push_back(N);
> +  return SDValue(N, 0);
> +}
> +
> +SDValue
> SelectionDAG::getCall(unsigned CallingConv, bool IsVarArgs, bool  
> IsTailCall,
>                       bool IsInreg, SDVTList VTs,
>                       const SDValue *Operands, unsigned NumOperands) {
> @@ -3470,6 +3626,31 @@
> }
>
> SDValue
> +SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool  
> IsVarArgs,
> +                      bool IsTailCall, bool IsInreg, SDVTList VTs,
> +                      const SDValue *Operands, unsigned  
> NumOperands) {
> +  // Do not include isTailCall in the folding set profile.
> +  FoldingSetNodeID ID;
> +  AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands);
> +  ID.AddInteger(CallingConv);
> +  ID.AddInteger(IsVarArgs);
> +  void *IP = 0;
> +  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) {
> +    // Instead of including isTailCall in the folding set, we just
> +    // set the flag of the existing node.
> +    if (!IsTailCall)
> +      cast(E)->setNotTailCall();
> +    return SDValue(E, 0);
> +  }
> +  SDNode *N = NodeAllocator.Allocate();
> +  new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall, IsInreg,
> +                     VTs, Operands, NumOperands);
> +  CSEMap.InsertNode(N, IP);
> +  AllNodes.push_back(N);
> +  return SDValue(N, 0);
> +}
> +
> +SDValue
> SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType  
> ExtType,
>                       MVT VT, SDValue Chain,
>                       SDValue Ptr, SDValue Offset,
> @@ -3520,6 +3701,57 @@
>   return SDValue(N, 0);
> }
>
> +SDValue
> +SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl,
> +                      ISD::LoadExtType ExtType, MVT VT, SDValue  
> Chain,
> +                      SDValue Ptr, SDValue Offset,
> +                      const Value *SV, int SVOffset, MVT EVT,
> +                      bool isVolatile, unsigned Alignment) {
> +  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
> +    Alignment = getMVTAlignment(VT);
> +
> +  if (VT == EVT) {
> +    ExtType = ISD::NON_EXTLOAD;
> +  } else if (ExtType == ISD::NON_EXTLOAD) {
> +    assert(VT == EVT && "Non-extending load from different memory  
> type!");
> +  } else {
> +    // Extending load.
> +    if (VT.isVector())
> +      assert(EVT.getVectorNumElements() ==  
> VT.getVectorNumElements() &&
> +             "Invalid vector extload!");
> +    else
> +      assert(EVT.bitsLT(VT) &&
> +             "Should only be an extending load, not truncating!");
> +    assert((ExtType == ISD::EXTLOAD || VT.isInteger()) &&
> +           "Cannot sign/zero extend a FP/Vector load!");
> +    assert(VT.isInteger() == EVT.isInteger() &&
> +           "Cannot convert from FP to Int or Int -> FP!");
> +  }
> +
> +  bool Indexed = AM != ISD::UNINDEXED;
> +  assert((Indexed || Offset.getOpcode() == ISD::UNDEF) &&
> +         "Unindexed load with an offset!");
> +
> +  SDVTList VTs = Indexed ?
> +    getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT,  
> MVT::Other);
> +  SDValue Ops[] = { Chain, Ptr, Offset };
> +  FoldingSetNodeID ID;
> +  AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
> +  ID.AddInteger(AM);
> +  ID.AddInteger(ExtType);
> +  ID.AddInteger(EVT.getRawBits());
> +  ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment));
> +  void *IP = 0;
> +  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
> +    return SDValue(E, 0);
> +  SDNode *N = NodeAllocator.Allocate();
> +  new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, EVT, SV, SVOffset,
> +                     Alignment, isVolatile);
> +  CSEMap.InsertNode(N, IP);
> +  AllNodes.push_back(N);
> +  return SDValue(N, 0);
> +}
> +
> SDValue SelectionDAG::getLoad(MVT VT,
>                               SDValue Chain, SDValue Ptr,
>                               const Value *SV, int SVOffset,
> @@ -3529,6 +3761,15 @@
>                  SV, SVOffset, VT, isVolatile, Alignment);
> }
>
> +SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl,
> +                              SDValue Chain, SDValue Ptr,
> +                              const Value *SV, int SVOffset,
> +                              bool isVolatile, unsigned Alignment) {
> +  SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
> +  return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain,  
> Ptr, Undef,
> +                 SV, SVOffset, VT, isVolatile, Alignment);
> +}
> +
> SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT,
>                                  SDValue Chain, SDValue Ptr,
>                                  const Value *SV,
> @@ -3539,6 +3780,16 @@
>                  SV, SVOffset, EVT, isVolatile, Alignment);
> }
>
> +SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc  
> dl, MVT VT,
> +                                 SDValue Chain, SDValue Ptr,
> +                                 const Value *SV,
> +                                 int SVOffset, MVT EVT,
> +                                 bool isVolatile, unsigned  
> Alignment) {
> +  SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
> +  return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef,
> +                 SV, SVOffset, EVT, isVolatile, Alignment);
> +}
> +
> SDValue
> SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base,
>                              SDValue Offset, ISD::MemIndexedMode AM) {
> @@ -3551,6 +3802,18 @@
>                  LD->isVolatile(), LD->getAlignment());
> }
>
> +SDValue
> +SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue  
> Base,
> +                             SDValue Offset, ISD::MemIndexedMode  
> AM) {
> +  LoadSDNode *LD = cast(OrigLoad);
> +  assert(LD->getOffset().getOpcode() == ISD::UNDEF &&
> +         "Load is already a indexed load!");
> +  return getLoad(AM, dl, LD->getExtensionType(),  
> OrigLoad.getValueType(),
> +                 LD->getChain(), Base, Offset, LD->getSrcValue(),
> +                 LD->getSrcValueOffset(), LD->getMemoryVT(),
> +                 LD->isVolatile(), LD->getAlignment());
> +}
> +
> SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val,
>                                SDValue Ptr, const Value *SV, int  
> SVOffset,
>                                bool isVolatile, unsigned Alignment) {
> @@ -3579,6 +3842,34 @@
>   return SDValue(N, 0);
> }
>
> +SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue  
> Val,
> +                               SDValue Ptr, const Value *SV, int  
> SVOffset,
> +                               bool isVolatile, unsigned Alignment) {
> +  MVT VT = Val.getValueType();
> +
> +  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
> +    Alignment = getMVTAlignment(VT);
> +
> +  SDVTList VTs = getVTList(MVT::Other);
> +  SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
> +  SDValue Ops[] = { Chain, Val, Ptr, Undef };
> +  FoldingSetNodeID ID;
> +  AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
> +  ID.AddInteger(ISD::UNINDEXED);
> +  ID.AddInteger(false);
> +  ID.AddInteger(VT.getRawBits());
> +  ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment));
> +  void *IP = 0;
> +  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
> +    return SDValue(E, 0);
> +  SDNode *N = NodeAllocator.Allocate();
> +  new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false,
> +                      VT, SV, SVOffset, Alignment, isVolatile);
> +  CSEMap.InsertNode(N, IP);
> +  AllNodes.push_back(N);
> +  return SDValue(N, 0);
> +}
> +
> SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val,
>                                     SDValue Ptr, const Value *SV,
>                                     int SVOffset, MVT SVT,
> @@ -3615,6 +3906,42 @@
>   return SDValue(N, 0);
> }
>
> +SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl,  
> SDValue Val,
> +                                    SDValue Ptr, const Value *SV,
> +                                    int SVOffset, MVT SVT,
> +                                    bool isVolatile, unsigned  
> Alignment) {
> +  MVT VT = Val.getValueType();
> +
> +  if (VT == SVT)
> +    return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile,  
> Alignment);
> +
> +  assert(VT.bitsGT(SVT) && "Not a truncation?");
> +  assert(VT.isInteger() == SVT.isInteger() &&
> +         "Can't do FP-INT conversion!");
> +
> +  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
> +    Alignment = getMVTAlignment(VT);
> +
> +  SDVTList VTs = getVTList(MVT::Other);
> +  SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
> +  SDValue Ops[] = { Chain, Val, Ptr, Undef };
> +  FoldingSetNodeID ID;
> +  AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
> +  ID.AddInteger(ISD::UNINDEXED);
> +  ID.AddInteger(1);
> +  ID.AddInteger(SVT.getRawBits());
> +  ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment));
> +  void *IP = 0;
> +  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
> +    return SDValue(E, 0);
> +  SDNode *N = NodeAllocator.Allocate();
> +  new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true,
> +                      SVT, SV, SVOffset, Alignment, isVolatile);
> +  CSEMap.InsertNode(N, IP);
> +  AllNodes.push_back(N);
> +  return SDValue(N, 0);
> +}
> +
> SDValue
> SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base,
>                               SDValue Offset, ISD::MemIndexedMode  
> AM) {
> @@ -3642,6 +3969,33 @@
>   return SDValue(N, 0);
> }
>
> +SDValue
> +SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl,  
> SDValue Base,
> +                              SDValue Offset, ISD::MemIndexedMode  
> AM) {
> +  StoreSDNode *ST = cast(OrigStore);
> +  assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
> +         "Store is already a indexed store!");
> +  SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
> +  SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset };
> +  FoldingSetNodeID ID;
> +  AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
> +  ID.AddInteger(AM);
> +  ID.AddInteger(ST->isTruncatingStore());
> +  ID.AddInteger(ST->getMemoryVT().getRawBits());
> +  ID.AddInteger(ST->getRawFlags());
> +  void *IP = 0;
> +  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
> +    return SDValue(E, 0);
> +  SDNode *N = NodeAllocator.Allocate();
> +  new (N) StoreSDNode(Ops, dl, VTs, AM,
> +                      ST->isTruncatingStore(), ST->getMemoryVT(),
> +                      ST->getSrcValue(), ST->getSrcValueOffset(),
> +                      ST->getAlignment(), ST->isVolatile());
> +  CSEMap.InsertNode(N, IP);
> +  AllNodes.push_back(N);
> +  return SDValue(N, 0);
> +}
> +
> SDValue SelectionDAG::getVAArg(MVT VT,
>                                SDValue Chain, SDValue Ptr,
>                                SDValue SV) {
> @@ -4395,32 +4749,70 @@
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) {
>   return getNode(~Opcode, VT).getNode();
> }
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,  
> MVT VT) {
> +  return getNode(~Opcode, dl, VT).getNode();
> +}
> +
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue  
> Op1) {
>   return getNode(~Opcode, VT, Op1).getNode();
> }
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,  
> MVT VT,
> +                                    SDValue Op1) {
> +  return getNode(~Opcode, dl, VT, Op1).getNode();
> +}
> +
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
>                                     SDValue Op1, SDValue Op2) {
>   return getNode(~Opcode, VT, Op1, Op2).getNode();
> }
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,  
> MVT VT,
> +                                    SDValue Op1, SDValue Op2) {
> +  return getNode(~Opcode, dl, VT, Op1, Op2).getNode();
> +}
> +
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
>                                     SDValue Op1, SDValue Op2,
>                                     SDValue Op3) {
>   return getNode(~Opcode, VT, Op1, Op2, Op3).getNode();
> }
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,  
> MVT VT,
> +                                    SDValue Op1, SDValue Op2,
> +                                    SDValue Op3) {
> +  return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode();
> +}
> +
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
>   return getNode(~Opcode, VT, Ops, NumOps).getNode();
> }
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,  
> MVT VT,
> +                                    const SDValue *Ops, unsigned  
> NumOps) {
> +  return getNode(~Opcode, dl, VT, Ops, NumOps).getNode();
> +}
> +
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT  
> VT2) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2);
>   SDValue Op;
>   return getNode(~Opcode, VTs, 2, &Op, 0).getNode();
> }
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
> +                                    MVT VT1, MVT VT2) {
> +  const MVT *VTs = getNodeValueTypes(VT1, VT2);
> +  SDValue Op;
> +  return getNode(~Opcode, dl, VTs, 2, &Op, 0).getNode();
> +}
> +
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>                                     MVT VT2, SDValue Op1) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2);
>   return getNode(~Opcode, VTs, 2, &Op1, 1).getNode();
> }
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,  
> MVT VT1,
> +                                    MVT VT2, SDValue Op1) {
> +  const MVT *VTs = getNodeValueTypes(VT1, VT2);
> +  return getNode(~Opcode, dl, VTs, 2, &Op1, 1).getNode();
> +}
> +
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>                                     MVT VT2, SDValue Op1,
>                                     SDValue Op2) {
> @@ -4428,6 +4820,14 @@
>   SDValue Ops[] = { Op1, Op2 };
>   return getNode(~Opcode, VTs, 2, Ops, 2).getNode();
> }
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,  
> MVT VT1,
> +                                    MVT VT2, SDValue Op1,
> +                                    SDValue Op2) {
> +  const MVT *VTs = getNodeValueTypes(VT1, VT2);
> +  SDValue Ops[] = { Op1, Op2 };
> +  return getNode(~Opcode, dl, VTs, 2, Ops, 2).getNode();
> +}
> +
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>                                     MVT VT2, SDValue Op1,
>                                     SDValue Op2, SDValue Op3) {
> @@ -4435,17 +4835,40 @@
>   SDValue Ops[] = { Op1, Op2, Op3 };
>   return getNode(~Opcode, VTs, 2, Ops, 3).getNode();
> }
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,  
> MVT VT1,
> +                                    MVT VT2, SDValue Op1,
> +                                    SDValue Op2, SDValue Op3) {
> +  const MVT *VTs = getNodeValueTypes(VT1, VT2);
> +  SDValue Ops[] = { Op1, Op2, Op3 };
> +  return getNode(~Opcode, dl, VTs, 2, Ops, 3).getNode();
> +}
> +
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2);
>   return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode();
> }
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
> +                                    MVT VT1, MVT VT2,
> +                                    const SDValue *Ops, unsigned  
> NumOps) {
> +  const MVT *VTs = getNodeValueTypes(VT1, VT2);
> +  return getNode(~Opcode, dl, VTs, 2, Ops, NumOps).getNode();
> +}
> +
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT  
> VT2, MVT VT3,
>                                     SDValue Op1, SDValue Op2) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
>   SDValue Ops[] = { Op1, Op2 };
>   return getNode(~Opcode, VTs, 3, Ops, 2).getNode();
> }
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
> +                                    MVT VT1, MVT VT2, MVT VT3,
> +                                    SDValue Op1, SDValue Op2) {
> +  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
> +  SDValue Ops[] = { Op1, Op2 };
> +  return getNode(~Opcode, dl, VTs, 3, Ops, 2).getNode();
> +}
> +
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT  
> VT2, MVT VT3,
>                                     SDValue Op1, SDValue Op2,
>                                     SDValue Op3) {
> @@ -4453,11 +4876,27 @@
>   SDValue Ops[] = { Op1, Op2, Op3 };
>   return getNode(~Opcode, VTs, 3, Ops, 3).getNode();
> }
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
> +                                    MVT VT1, MVT VT2, MVT VT3,
> +                                    SDValue Op1, SDValue Op2,
> +                                    SDValue Op3) {
> +  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
> +  SDValue Ops[] = { Op1, Op2, Op3 };
> +  return getNode(~Opcode, dl, VTs, 3, Ops, 3).getNode();
> +}
> +
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT  
> VT2, MVT VT3,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
>   return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
> }
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
> +                                    MVT VT1, MVT VT2, MVT VT3,
> +                                    const SDValue *Ops, unsigned  
> NumOps) {
> +  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
> +  return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
> +}
> +
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>                                     MVT VT2, MVT VT3, MVT VT4,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
> @@ -4469,6 +4908,18 @@
>   const MVT *VTs = getNodeValueTypes(VTList);
>   return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode();
> }
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,  
> MVT VT1,
> +                                    MVT VT2, MVT VT3, MVT VT4,
> +                                    const SDValue *Ops, unsigned  
> NumOps) {
> +  std::vector VTList;
> +  VTList.push_back(VT1);
> +  VTList.push_back(VT2);
> +  VTList.push_back(VT3);
> +  VTList.push_back(VT4);
> +  const MVT *VTs = getNodeValueTypes(VTList);
> +  return getNode(~Opcode, dl, VTs, 4, Ops, NumOps).getNode();
> +}
> +
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
>                                     const std::vector &ResultTys,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
> @@ -4476,6 +4927,13 @@
>   return getNode(~Opcode, VTs, ResultTys.size(),
>                  Ops, NumOps).getNode();
> }
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
> +                                    const std::vector  
> &ResultTys,
> +                                    const SDValue *Ops, unsigned  
> NumOps) {
> +  const MVT *VTs = getNodeValueTypes(ResultTys);
> +  return getNode(~Opcode, dl, VTs, ResultTys.size(),
> +                 Ops, NumOps).getNode();
> +}
>
> /// getNodeIfExists - Get the specified node if it's already  
> available, or
> /// else return NULL.
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From dalej at apple.com  Wed Jan 28 19:08:26 2009
From: dalej at apple.com (Dale Johannesen)
Date: Wed, 28 Jan 2009 17:08:26 -0800
Subject: [llvm-commits] [llvm] r63259 - in /llvm/trunk:
	include/llvm/CodeGen/SelectionDAG.h	lib/CodeGen/SelectionDAG/SelectionDAG.cpp
In-Reply-To: <83C98C61-F72A-4859-9E96-BDB92C6D2C96@apple.com>
References: <200901290047.n0T0lmXG030099@zion.cs.uiuc.edu>
	<83C98C61-F72A-4859-9E96-BDB92C6D2C96@apple.com>
Message-ID: 


On Jan 28, 2009, at 5:06 PMPST, Dan Gohman wrote:

> Hi Dale,
>
> Instead of duplicating all that code, could you make the non-DebugLoc-
> aware
> accessors just thin wrappers around the DebugLoc-aware ones, like  
> this:
>
> SDValue getBasicBlock(MachineBasicBlock *MBB) {
>   return getBasicBLock(MBB, DebugLoc::getUnknownLoc());
> }
>
> and so on? Thanks,
>
> Dan

No, I decided not to do that on the grounds that it would encourage  
people to remove references to the old versions faster.

> On Jan 28, 2009, at 4:47 PM, Dale Johannesen wrote:
>
>> Author: johannes
>> Date: Wed Jan 28 18:47:48 2009
>> New Revision: 63259
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=63259&view=rev
>> Log:
>> Add DebugLoc-sensitive versions of many node creation
>> functions.  Currently omitted:  memcpy, memmove, memset.
>>
>>
>> Modified:
>>   llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>>   llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63259&r1=63258&r2=63259&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Jan 28
>> 18:47:48 2009
>> @@ -307,14 +307,19 @@
>>    return getConstantPool(C, VT, Align, Offset, true);
>>  }
>>  SDValue getBasicBlock(MachineBasicBlock *MBB);
>> +  SDValue getBasicBlock(MachineBasicBlock *MBB, DebugLoc dl);
>>  SDValue getExternalSymbol(const char *Sym, MVT VT);
>> +  SDValue getExternalSymbol(const char *Sym, DebugLoc dl, MVT VT);
>>  SDValue getTargetExternalSymbol(const char *Sym, MVT VT);
>> +  SDValue getTargetExternalSymbol(const char *Sym, DebugLoc dl, MVT
>> VT);
>>  SDValue getArgFlags(ISD::ArgFlagsTy Flags);
>>  SDValue getValueType(MVT);
>>  SDValue getRegister(unsigned Reg, MVT VT);
>>  SDValue getDbgStopPoint(SDValue Root, unsigned Line, unsigned Col,
>>                          Value *CU);
>>  SDValue getLabel(unsigned Opcode, SDValue Root, unsigned LabelID);
>> +  SDValue getLabel(unsigned Opcode, DebugLoc dl, SDValue Root,
>> +                   unsigned LabelID);
>>
>>  SDValue getCopyToReg(SDValue Chain, unsigned Reg, SDValue N) {
>>    return getNode(ISD::CopyToReg, MVT::Other, Chain,
>> @@ -506,12 +511,18 @@
>>  SDValue getAtomic(unsigned Opcode, MVT MemVT, SDValue Chain,
>> SDValue Ptr,
>>                    SDValue Cmp, SDValue Swp, const Value* PtrVal,
>>                    unsigned Alignment=0);
>> +  SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
>> SDValue Chain,
>> +                    SDValue Ptr, SDValue Cmp, SDValue Swp, const
>> Value* PtrVal,
>> +                    unsigned Alignment=0);
>>
>>  /// getAtomic - Gets a node for an atomic op, produces result and
>> chain and
>>  /// takes 2 operands.
>>  SDValue getAtomic(unsigned Opcode, MVT MemVT, SDValue Chain,
>> SDValue Ptr,
>>                    SDValue Val, const Value* PtrVal,
>>                    unsigned Alignment = 0);
>> +  SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
>> SDValue Chain,
>> +                    SDValue Ptr, SDValue Val, const Value* PtrVal,
>> +                    unsigned Alignment = 0);
>>
>>  /// getMemIntrinsicNode - Creates a MemIntrinsicNode that may
>> produce a
>>  /// result and takes a list of operands.
>> @@ -521,12 +532,23 @@
>>                              MVT MemVT, const Value *srcValue, int
>> SVOff,
>>                              unsigned Align = 0, bool Vol = false,
>>                              bool ReadMem = true, bool WriteMem =
>> true);
>> +  SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
>> +                              const MVT *VTs, unsigned NumVTs,
>> +                              const SDValue *Ops, unsigned NumOps,
>> +                              MVT MemVT, const Value *srcValue, int
>> SVOff,
>> +                              unsigned Align = 0, bool Vol = false,
>> +                              bool ReadMem = true, bool WriteMem =
>> true);
>>
>>  SDValue getMemIntrinsicNode(unsigned Opcode, SDVTList VTList,
>>                              const SDValue *Ops, unsigned NumOps,
>>                              MVT MemVT, const Value *srcValue, int
>> SVOff,
>>                              unsigned Align = 0, bool Vol = false,
>>                              bool ReadMem = true, bool WriteMem =
>> true);
>> +  SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
>> SDVTList VTList,
>> +                              const SDValue *Ops, unsigned NumOps,
>> +                              MVT MemVT, const Value *srcValue, int
>> SVOff,
>> +                              unsigned Align = 0, bool Vol = false,
>> +                              bool ReadMem = true, bool WriteMem =
>> true);
>>
>>  /// getMergeValues - Create a MERGE_VALUES node from the given
>> operands.
>>  SDValue getMergeValues(const SDValue *Ops, unsigned NumOps);
>> @@ -536,6 +558,9 @@
>>  SDValue getCall(unsigned CallingConv, bool IsVarArgs, bool
>> IsTailCall,
>>                  bool isInreg, SDVTList VTs, const SDValue *Operands,
>>                  unsigned NumOperands);
>> +  SDValue getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs,
>> +                  bool IsTailCall, bool isInreg, SDVTList VTs,
>> +                  const SDValue *Operands, unsigned NumOperands);
>>
>>  /// getLoad - Loads are not normal binary operators: their result
>> type is not
>>  /// determined by their operands, and they produce a value AND a
>> token chain.
>> @@ -543,28 +568,50 @@
>>  SDValue getLoad(MVT VT, SDValue Chain, SDValue Ptr,
>>                    const Value *SV, int SVOffset, bool
>> isVolatile=false,
>>                    unsigned Alignment=0);
>> +  SDValue getLoad(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
>> +                    const Value *SV, int SVOffset, bool
>> isVolatile=false,
>> +                    unsigned Alignment=0);
>>  SDValue getExtLoad(ISD::LoadExtType ExtType, MVT VT,
>>                       SDValue Chain, SDValue Ptr, const Value *SV,
>>                       int SVOffset, MVT EVT, bool isVolatile=false,
>>                       unsigned Alignment=0);
>> +  SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT,
>> +                       SDValue Chain, SDValue Ptr, const Value *SV,
>> +                       int SVOffset, MVT EVT, bool isVolatile=false,
>> +                       unsigned Alignment=0);
>>  SDValue getIndexedLoad(SDValue OrigLoad, SDValue Base,
>>                           SDValue Offset, ISD::MemIndexedMode AM);
>> +  SDValue getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue  
>> Base,
>> +                           SDValue Offset, ISD::MemIndexedMode AM);
>>  SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
>>                    MVT VT, SDValue Chain,
>>                    SDValue Ptr, SDValue Offset,
>>                    const Value *SV, int SVOffset, MVT EVT,
>>                    bool isVolatile=false, unsigned Alignment=0);
>> +  SDValue getLoad(ISD::MemIndexedMode AM, DebugLoc dl,
>> ISD::LoadExtType ExtType,
>> +                    MVT VT, SDValue Chain,
>> +                    SDValue Ptr, SDValue Offset,
>> +                    const Value *SV, int SVOffset, MVT EVT,
>> +                    bool isVolatile=false, unsigned Alignment=0);
>>
>>  /// getStore - Helper function to build ISD::STORE nodes.
>>  ///
>>  SDValue getStore(SDValue Chain, SDValue Val, SDValue Ptr,
>>                     const Value *SV, int SVOffset, bool
>> isVolatile=false,
>>                     unsigned Alignment=0);
>> +  SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue
>> Ptr,
>> +                     const Value *SV, int SVOffset, bool
>> isVolatile=false,
>> +                     unsigned Alignment=0);
>>  SDValue getTruncStore(SDValue Chain, SDValue Val, SDValue Ptr,
>>                          const Value *SV, int SVOffset, MVT TVT,
>>                          bool isVolatile=false, unsigned
>> Alignment=0);
>> +  SDValue getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,
>> SDValue Ptr,
>> +                          const Value *SV, int SVOffset, MVT TVT,
>> +                          bool isVolatile=false, unsigned
>> Alignment=0);
>>  SDValue getIndexedStore(SDValue OrigStoe, SDValue Base,
>>                           SDValue Offset, ISD::MemIndexedMode AM);
>> +  SDValue getIndexedStore(SDValue OrigStoe, DebugLoc dl, SDValue
>> Base,
>> +                           SDValue Offset, ISD::MemIndexedMode AM);
>>
>>  /// getSrcValue - Construct a node to track a Value* through the
>> backend.
>>  SDValue getSrcValue(const Value *v);
>> @@ -652,30 +699,72 @@
>>  /// node of the specified opcode and operands, it returns that
>> node instead of
>>  /// the current one.
>>  SDNode *getTargetNode(unsigned Opcode, MVT VT);
>> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT);
>> +
>>  SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1);
>> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
>> SDValue Op1);
>> +
>>  SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1,
>> SDValue Op2);
>> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
>> SDValue Op1,
>> +                        SDValue Op2);
>> +
>>  SDNode *getTargetNode(unsigned Opcode, MVT VT,
>>                        SDValue Op1, SDValue Op2, SDValue Op3);
>> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
>> +                        SDValue Op1, SDValue Op2, SDValue Op3);
>> +
>>  SDNode *getTargetNode(unsigned Opcode, MVT VT,
>>                        const SDValue *Ops, unsigned NumOps);
>> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
>> +                        const SDValue *Ops, unsigned NumOps);
>> +
>>  SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2);
>> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT
>> VT2);
>> +
>>  SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDValue
>> Op1);
>> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT
>> VT2,
>> +                        SDValue Op1);
>> +
>>  SDNode *getTargetNode(unsigned Opcode, MVT VT1,
>>                        MVT VT2, SDValue Op1, SDValue Op2);
>> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
>> +                        MVT VT2, SDValue Op1, SDValue Op2);
>> +
>>  SDNode *getTargetNode(unsigned Opcode, MVT VT1,
>>                        MVT VT2, SDValue Op1, SDValue Op2, SDValue
>> Op3);
>> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
>> +                        MVT VT2, SDValue Op1, SDValue Op2, SDValue
>> Op3);
>> +
>>  SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
>>                        const SDValue *Ops, unsigned NumOps);
>> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT
>> VT2,
>> +                        const SDValue *Ops, unsigned NumOps);
>> +
>>  SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
>>                        SDValue Op1, SDValue Op2);
>> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT
>> VT2, MVT VT3,
>> +                        SDValue Op1, SDValue Op2);
>> +
>>  SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
>>                        SDValue Op1, SDValue Op2, SDValue Op3);
>> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT
>> VT2, MVT VT3,
>> +                        SDValue Op1, SDValue Op2, SDValue Op3);
>> +
>>  SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
>>                        const SDValue *Ops, unsigned NumOps);
>> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT
>> VT2, MVT VT3,
>> +                        const SDValue *Ops, unsigned NumOps);
>> +
>>  SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
>> MVT VT4,
>>                        const SDValue *Ops, unsigned NumOps);
>> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT
>> VT2, MVT VT3,
>> +                        MVT VT4, const SDValue *Ops, unsigned
>> NumOps);
>> +
>>  SDNode *getTargetNode(unsigned Opcode, const std::vector
>> &ResultTys,
>>                        const SDValue *Ops, unsigned NumOps);
>> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl,
>> +                        const std::vector &ResultTys, const
>> SDValue *Ops,
>> +                        unsigned NumOps);
>>
>>  /// getNodeIfExists - Get the specified node if it's already
>> available, or
>>  /// else return NULL.
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63259&r1=63258&r2=63259&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jan 28
>> 18:47:48 2009
>> @@ -1068,6 +1068,20 @@
>>  return SDValue(N, 0);
>> }
>>
>> +SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB,
>> DebugLoc dl) {
>> +  FoldingSetNodeID ID;
>> +  AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0);
>> +  ID.AddPointer(MBB);
>> +  void *IP = 0;
>> +  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
>> +    return SDValue(E, 0);
>> +  SDNode *N = NodeAllocator.Allocate();
>> +  new (N) BasicBlockSDNode(MBB, dl);
>> +  CSEMap.InsertNode(N, IP);
>> +  AllNodes.push_back(N);
>> +  return SDValue(N, 0);
>> +}
>> +
>> SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) {
>>  FoldingSetNodeID ID;
>>  AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0);
>> @@ -1105,6 +1119,15 @@
>>  return SDValue(N, 0);
>> }
>>
>> +SDValue SelectionDAG::getExternalSymbol(const char *Sym, DebugLoc
>> dl, MVT VT) {
>> +  SDNode *&N = ExternalSymbols[Sym];
>> +  if (N) return SDValue(N, 0);
>> +  N = NodeAllocator.Allocate();
>> +  new (N) ExternalSymbolSDNode(false, dl, Sym, VT);
>> +  AllNodes.push_back(N);
>> +  return SDValue(N, 0);
>> +}
>> +
>> SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT
>> VT) {
>>  SDNode *&N = TargetExternalSymbols[Sym];
>>  if (N) return SDValue(N, 0);
>> @@ -1114,6 +1137,16 @@
>>  return SDValue(N, 0);
>> }
>>
>> +SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym,
>> DebugLoc dl,
>> +                                              MVT VT) {
>> +  SDNode *&N = TargetExternalSymbols[Sym];
>> +  if (N) return SDValue(N, 0);
>> +  N = NodeAllocator.Allocate();
>> +  new (N) ExternalSymbolSDNode(true, dl, Sym, VT);
>> +  AllNodes.push_back(N);
>> +  return SDValue(N, 0);
>> +}
>> +
>> SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) {
>>  if ((unsigned)Cond >= CondCodeNodes.size())
>>    CondCodeNodes.resize(Cond+1);
>> @@ -1186,6 +1219,23 @@
>>  return SDValue(N, 0);
>> }
>>
>> +SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl,
>> +                               SDValue Root,
>> +                               unsigned LabelID) {
>> +  FoldingSetNodeID ID;
>> +  SDValue Ops[] = { Root };
>> +  AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1);
>> +  ID.AddInteger(LabelID);
>> +  void *IP = 0;
>> +  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
>> +    return SDValue(E, 0);
>> +  SDNode *N = NodeAllocator.Allocate();
>> +  new (N) LabelSDNode(Opcode, dl, Root, LabelID);
>> +  CSEMap.InsertNode(N, IP);
>> +  AllNodes.push_back(N);
>> +  return SDValue(N, 0);
>> +}
>> +
>> SDValue SelectionDAG::getSrcValue(const Value *V) {
>>  assert((!V || isa(V->getType())) &&
>>         "SrcValue is not a pointer?");
>> @@ -3353,6 +3403,34 @@
>>  return SDValue(N, 0);
>> }
>>
>> +SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT
>> MemVT,
>> +                                SDValue Chain,
>> +                                SDValue Ptr, SDValue Cmp,
>> +                                SDValue Swp, const Value* PtrVal,
>> +                                unsigned Alignment) {
>> +  assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op");
>> +  assert(Cmp.getValueType() == Swp.getValueType() && "Invalid
>> Atomic Op Types");
>> +
>> +  MVT VT = Cmp.getValueType();
>> +
>> +  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
>> +    Alignment = getMVTAlignment(MemVT);
>> +
>> +  SDVTList VTs = getVTList(VT, MVT::Other);
>> +  FoldingSetNodeID ID;
>> +  SDValue Ops[] = {Chain, Ptr, Cmp, Swp};
>> +  AddNodeIDNode(ID, Opcode, VTs, Ops, 4);
>> +  void* IP = 0;
>> +  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
>> +    return SDValue(E, 0);
>> +  SDNode* N = NodeAllocator.Allocate();
>> +  new (N) AtomicSDNode(Opcode, dl, VTs, MemVT,
>> +                       Chain, Ptr, Cmp, Swp, PtrVal, Alignment);
>> +  CSEMap.InsertNode(N, IP);
>> +  AllNodes.push_back(N);
>> +  return SDValue(N, 0);
>> +}
>> +
>> SDValue SelectionDAG::getAtomic(unsigned Opcode, MVT MemVT,
>>                                SDValue Chain,
>>                                SDValue Ptr, SDValue Val,
>> @@ -3391,6 +3469,44 @@
>>  return SDValue(N, 0);
>> }
>>
>> +SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT
>> MemVT,
>> +                                SDValue Chain,
>> +                                SDValue Ptr, SDValue Val,
>> +                                const Value* PtrVal,
>> +                                unsigned Alignment) {
>> +  assert((Opcode == ISD::ATOMIC_LOAD_ADD ||
>> +          Opcode == ISD::ATOMIC_LOAD_SUB ||
>> +          Opcode == ISD::ATOMIC_LOAD_AND ||
>> +          Opcode == ISD::ATOMIC_LOAD_OR ||
>> +          Opcode == ISD::ATOMIC_LOAD_XOR ||
>> +          Opcode == ISD::ATOMIC_LOAD_NAND ||
>> +          Opcode == ISD::ATOMIC_LOAD_MIN ||
>> +          Opcode == ISD::ATOMIC_LOAD_MAX ||
>> +          Opcode == ISD::ATOMIC_LOAD_UMIN ||
>> +          Opcode == ISD::ATOMIC_LOAD_UMAX ||
>> +          Opcode == ISD::ATOMIC_SWAP) &&
>> +         "Invalid Atomic Op");
>> +
>> +  MVT VT = Val.getValueType();
>> +
>> +  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
>> +    Alignment = getMVTAlignment(MemVT);
>> +
>> +  SDVTList VTs = getVTList(VT, MVT::Other);
>> +  FoldingSetNodeID ID;
>> +  SDValue Ops[] = {Chain, Ptr, Val};
>> +  AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
>> +  void* IP = 0;
>> +  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
>> +    return SDValue(E, 0);
>> +  SDNode* N = NodeAllocator.Allocate();
>> +  new (N) AtomicSDNode(Opcode, dl, VTs, MemVT,
>> +                       Chain, Ptr, Val, PtrVal, Alignment);
>> +  CSEMap.InsertNode(N, IP);
>> +  AllNodes.push_back(N);
>> +  return SDValue(N, 0);
>> +}
>> +
>> /// getMergeValues - Create a MERGE_VALUES node from the given
>> operands.
>> /// Allowed to return something different (and simpler) if Simplify
>> is true.
>> SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned
>> NumOps) {
>> @@ -3417,6 +3533,18 @@
>> }
>>
>> SDValue
>> +SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
>> +                                  const MVT *VTs, unsigned NumVTs,
>> +                                  const SDValue *Ops, unsigned
>> NumOps,
>> +                                  MVT MemVT, const Value *srcValue,
>> int SVOff,
>> +                                  unsigned Align, bool Vol,
>> +                                  bool ReadMem, bool WriteMem) {
>> +  return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs),
>> Ops, NumOps,
>> +                             MemVT, srcValue, SVOff, Align, Vol,
>> +                             ReadMem, WriteMem);
>> +}
>> +
>> +SDValue
>> SelectionDAG::getMemIntrinsicNode(unsigned Opcode, SDVTList VTList,
>>                                  const SDValue *Ops, unsigned NumOps,
>>                                  MVT MemVT, const Value *srcValue,
>> int SVOff,
>> @@ -3445,6 +3573,34 @@
>> }
>>
>> SDValue
>> +SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
>> SDVTList VTList,
>> +                                  const SDValue *Ops, unsigned
>> NumOps,
>> +                                  MVT MemVT, const Value *srcValue,
>> int SVOff,
>> +                                  unsigned Align, bool Vol,
>> +                                  bool ReadMem, bool WriteMem) {
>> +  // Memoize the node unless it returns a flag.
>> +  MemIntrinsicSDNode *N;
>> +  if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
>> +    FoldingSetNodeID ID;
>> +    AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
>> +    void *IP = 0;
>> +    if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
>> +      return SDValue(E, 0);
>> +
>> +    N = NodeAllocator.Allocate();
>> +    new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps,
>> MemVT,
>> +                               srcValue, SVOff, Align, Vol,
>> ReadMem, WriteMem);
>> +    CSEMap.InsertNode(N, IP);
>> +  } else {
>> +    N = NodeAllocator.Allocate();
>> +    new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps,
>> MemVT,
>> +                               srcValue, SVOff, Align, Vol,
>> ReadMem, WriteMem);
>> +  }
>> +  AllNodes.push_back(N);
>> +  return SDValue(N, 0);
>> +}
>> +
>> +SDValue
>> SelectionDAG::getCall(unsigned CallingConv, bool IsVarArgs, bool
>> IsTailCall,
>>                      bool IsInreg, SDVTList VTs,
>>                      const SDValue *Operands, unsigned NumOperands) {
>> @@ -3470,6 +3626,31 @@
>> }
>>
>> SDValue
>> +SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool
>> IsVarArgs,
>> +                      bool IsTailCall, bool IsInreg, SDVTList VTs,
>> +                      const SDValue *Operands, unsigned
>> NumOperands) {
>> +  // Do not include isTailCall in the folding set profile.
>> +  FoldingSetNodeID ID;
>> +  AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands);
>> +  ID.AddInteger(CallingConv);
>> +  ID.AddInteger(IsVarArgs);
>> +  void *IP = 0;
>> +  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) {
>> +    // Instead of including isTailCall in the folding set, we just
>> +    // set the flag of the existing node.
>> +    if (!IsTailCall)
>> +      cast(E)->setNotTailCall();
>> +    return SDValue(E, 0);
>> +  }
>> +  SDNode *N = NodeAllocator.Allocate();
>> +  new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall,  
>> IsInreg,
>> +                     VTs, Operands, NumOperands);
>> +  CSEMap.InsertNode(N, IP);
>> +  AllNodes.push_back(N);
>> +  return SDValue(N, 0);
>> +}
>> +
>> +SDValue
>> SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType
>> ExtType,
>>                      MVT VT, SDValue Chain,
>>                      SDValue Ptr, SDValue Offset,
>> @@ -3520,6 +3701,57 @@
>>  return SDValue(N, 0);
>> }
>>
>> +SDValue
>> +SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl,
>> +                      ISD::LoadExtType ExtType, MVT VT, SDValue
>> Chain,
>> +                      SDValue Ptr, SDValue Offset,
>> +                      const Value *SV, int SVOffset, MVT EVT,
>> +                      bool isVolatile, unsigned Alignment) {
>> +  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
>> +    Alignment = getMVTAlignment(VT);
>> +
>> +  if (VT == EVT) {
>> +    ExtType = ISD::NON_EXTLOAD;
>> +  } else if (ExtType == ISD::NON_EXTLOAD) {
>> +    assert(VT == EVT && "Non-extending load from different memory
>> type!");
>> +  } else {
>> +    // Extending load.
>> +    if (VT.isVector())
>> +      assert(EVT.getVectorNumElements() ==
>> VT.getVectorNumElements() &&
>> +             "Invalid vector extload!");
>> +    else
>> +      assert(EVT.bitsLT(VT) &&
>> +             "Should only be an extending load, not truncating!");
>> +    assert((ExtType == ISD::EXTLOAD || VT.isInteger()) &&
>> +           "Cannot sign/zero extend a FP/Vector load!");
>> +    assert(VT.isInteger() == EVT.isInteger() &&
>> +           "Cannot convert from FP to Int or Int -> FP!");
>> +  }
>> +
>> +  bool Indexed = AM != ISD::UNINDEXED;
>> +  assert((Indexed || Offset.getOpcode() == ISD::UNDEF) &&
>> +         "Unindexed load with an offset!");
>> +
>> +  SDVTList VTs = Indexed ?
>> +    getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT,
>> MVT::Other);
>> +  SDValue Ops[] = { Chain, Ptr, Offset };
>> +  FoldingSetNodeID ID;
>> +  AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
>> +  ID.AddInteger(AM);
>> +  ID.AddInteger(ExtType);
>> +  ID.AddInteger(EVT.getRawBits());
>> +  ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment));
>> +  void *IP = 0;
>> +  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
>> +    return SDValue(E, 0);
>> +  SDNode *N = NodeAllocator.Allocate();
>> +  new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, EVT, SV, SVOffset,
>> +                     Alignment, isVolatile);
>> +  CSEMap.InsertNode(N, IP);
>> +  AllNodes.push_back(N);
>> +  return SDValue(N, 0);
>> +}
>> +
>> SDValue SelectionDAG::getLoad(MVT VT,
>>                              SDValue Chain, SDValue Ptr,
>>                              const Value *SV, int SVOffset,
>> @@ -3529,6 +3761,15 @@
>>                 SV, SVOffset, VT, isVolatile, Alignment);
>> }
>>
>> +SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl,
>> +                              SDValue Chain, SDValue Ptr,
>> +                              const Value *SV, int SVOffset,
>> +                              bool isVolatile, unsigned Alignment) {
>> +  SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
>> +  return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain,
>> Ptr, Undef,
>> +                 SV, SVOffset, VT, isVolatile, Alignment);
>> +}
>> +
>> SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT,
>>                                 SDValue Chain, SDValue Ptr,
>>                                 const Value *SV,
>> @@ -3539,6 +3780,16 @@
>>                 SV, SVOffset, EVT, isVolatile, Alignment);
>> }
>>
>> +SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc
>> dl, MVT VT,
>> +                                 SDValue Chain, SDValue Ptr,
>> +                                 const Value *SV,
>> +                                 int SVOffset, MVT EVT,
>> +                                 bool isVolatile, unsigned
>> Alignment) {
>> +  SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
>> +  return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef,
>> +                 SV, SVOffset, EVT, isVolatile, Alignment);
>> +}
>> +
>> SDValue
>> SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base,
>>                             SDValue Offset, ISD::MemIndexedMode AM) {
>> @@ -3551,6 +3802,18 @@
>>                 LD->isVolatile(), LD->getAlignment());
>> }
>>
>> +SDValue
>> +SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue
>> Base,
>> +                             SDValue Offset, ISD::MemIndexedMode
>> AM) {
>> +  LoadSDNode *LD = cast(OrigLoad);
>> +  assert(LD->getOffset().getOpcode() == ISD::UNDEF &&
>> +         "Load is already a indexed load!");
>> +  return getLoad(AM, dl, LD->getExtensionType(),
>> OrigLoad.getValueType(),
>> +                 LD->getChain(), Base, Offset, LD->getSrcValue(),
>> +                 LD->getSrcValueOffset(), LD->getMemoryVT(),
>> +                 LD->isVolatile(), LD->getAlignment());
>> +}
>> +
>> SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val,
>>                               SDValue Ptr, const Value *SV, int
>> SVOffset,
>>                               bool isVolatile, unsigned Alignment) {
>> @@ -3579,6 +3842,34 @@
>>  return SDValue(N, 0);
>> }
>>
>> +SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue
>> Val,
>> +                               SDValue Ptr, const Value *SV, int
>> SVOffset,
>> +                               bool isVolatile, unsigned  
>> Alignment) {
>> +  MVT VT = Val.getValueType();
>> +
>> +  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
>> +    Alignment = getMVTAlignment(VT);
>> +
>> +  SDVTList VTs = getVTList(MVT::Other);
>> +  SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
>> +  SDValue Ops[] = { Chain, Val, Ptr, Undef };
>> +  FoldingSetNodeID ID;
>> +  AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
>> +  ID.AddInteger(ISD::UNINDEXED);
>> +  ID.AddInteger(false);
>> +  ID.AddInteger(VT.getRawBits());
>> +  ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment));
>> +  void *IP = 0;
>> +  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
>> +    return SDValue(E, 0);
>> +  SDNode *N = NodeAllocator.Allocate();
>> +  new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false,
>> +                      VT, SV, SVOffset, Alignment, isVolatile);
>> +  CSEMap.InsertNode(N, IP);
>> +  AllNodes.push_back(N);
>> +  return SDValue(N, 0);
>> +}
>> +
>> SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val,
>>                                    SDValue Ptr, const Value *SV,
>>                                    int SVOffset, MVT SVT,
>> @@ -3615,6 +3906,42 @@
>>  return SDValue(N, 0);
>> }
>>
>> +SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl,
>> SDValue Val,
>> +                                    SDValue Ptr, const Value *SV,
>> +                                    int SVOffset, MVT SVT,
>> +                                    bool isVolatile, unsigned
>> Alignment) {
>> +  MVT VT = Val.getValueType();
>> +
>> +  if (VT == SVT)
>> +    return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile,
>> Alignment);
>> +
>> +  assert(VT.bitsGT(SVT) && "Not a truncation?");
>> +  assert(VT.isInteger() == SVT.isInteger() &&
>> +         "Can't do FP-INT conversion!");
>> +
>> +  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
>> +    Alignment = getMVTAlignment(VT);
>> +
>> +  SDVTList VTs = getVTList(MVT::Other);
>> +  SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
>> +  SDValue Ops[] = { Chain, Val, Ptr, Undef };
>> +  FoldingSetNodeID ID;
>> +  AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
>> +  ID.AddInteger(ISD::UNINDEXED);
>> +  ID.AddInteger(1);
>> +  ID.AddInteger(SVT.getRawBits());
>> +  ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment));
>> +  void *IP = 0;
>> +  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
>> +    return SDValue(E, 0);
>> +  SDNode *N = NodeAllocator.Allocate();
>> +  new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true,
>> +                      SVT, SV, SVOffset, Alignment, isVolatile);
>> +  CSEMap.InsertNode(N, IP);
>> +  AllNodes.push_back(N);
>> +  return SDValue(N, 0);
>> +}
>> +
>> SDValue
>> SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base,
>>                              SDValue Offset, ISD::MemIndexedMode
>> AM) {
>> @@ -3642,6 +3969,33 @@
>>  return SDValue(N, 0);
>> }
>>
>> +SDValue
>> +SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl,
>> SDValue Base,
>> +                              SDValue Offset, ISD::MemIndexedMode
>> AM) {
>> +  StoreSDNode *ST = cast(OrigStore);
>> +  assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
>> +         "Store is already a indexed store!");
>> +  SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
>> +  SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset };
>> +  FoldingSetNodeID ID;
>> +  AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
>> +  ID.AddInteger(AM);
>> +  ID.AddInteger(ST->isTruncatingStore());
>> +  ID.AddInteger(ST->getMemoryVT().getRawBits());
>> +  ID.AddInteger(ST->getRawFlags());
>> +  void *IP = 0;
>> +  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
>> +    return SDValue(E, 0);
>> +  SDNode *N = NodeAllocator.Allocate();
>> +  new (N) StoreSDNode(Ops, dl, VTs, AM,
>> +                      ST->isTruncatingStore(), ST->getMemoryVT(),
>> +                      ST->getSrcValue(), ST->getSrcValueOffset(),
>> +                      ST->getAlignment(), ST->isVolatile());
>> +  CSEMap.InsertNode(N, IP);
>> +  AllNodes.push_back(N);
>> +  return SDValue(N, 0);
>> +}
>> +
>> SDValue SelectionDAG::getVAArg(MVT VT,
>>                               SDValue Chain, SDValue Ptr,
>>                               SDValue SV) {
>> @@ -4395,32 +4749,70 @@
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) {
>>  return getNode(~Opcode, VT).getNode();
>> }
>> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
>> MVT VT) {
>> +  return getNode(~Opcode, dl, VT).getNode();
>> +}
>> +
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue
>> Op1) {
>>  return getNode(~Opcode, VT, Op1).getNode();
>> }
>> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
>> MVT VT,
>> +                                    SDValue Op1) {
>> +  return getNode(~Opcode, dl, VT, Op1).getNode();
>> +}
>> +
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
>>                                    SDValue Op1, SDValue Op2) {
>>  return getNode(~Opcode, VT, Op1, Op2).getNode();
>> }
>> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
>> MVT VT,
>> +                                    SDValue Op1, SDValue Op2) {
>> +  return getNode(~Opcode, dl, VT, Op1, Op2).getNode();
>> +}
>> +
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
>>                                    SDValue Op1, SDValue Op2,
>>                                    SDValue Op3) {
>>  return getNode(~Opcode, VT, Op1, Op2, Op3).getNode();
>> }
>> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
>> MVT VT,
>> +                                    SDValue Op1, SDValue Op2,
>> +                                    SDValue Op3) {
>> +  return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode();
>> +}
>> +
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
>>                                    const SDValue *Ops, unsigned
>> NumOps) {
>>  return getNode(~Opcode, VT, Ops, NumOps).getNode();
>> }
>> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
>> MVT VT,
>> +                                    const SDValue *Ops, unsigned
>> NumOps) {
>> +  return getNode(~Opcode, dl, VT, Ops, NumOps).getNode();
>> +}
>> +
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT
>> VT2) {
>>  const MVT *VTs = getNodeValueTypes(VT1, VT2);
>>  SDValue Op;
>>  return getNode(~Opcode, VTs, 2, &Op, 0).getNode();
>> }
>> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
>> +                                    MVT VT1, MVT VT2) {
>> +  const MVT *VTs = getNodeValueTypes(VT1, VT2);
>> +  SDValue Op;
>> +  return getNode(~Opcode, dl, VTs, 2, &Op, 0).getNode();
>> +}
>> +
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>>                                    MVT VT2, SDValue Op1) {
>>  const MVT *VTs = getNodeValueTypes(VT1, VT2);
>>  return getNode(~Opcode, VTs, 2, &Op1, 1).getNode();
>> }
>> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
>> MVT VT1,
>> +                                    MVT VT2, SDValue Op1) {
>> +  const MVT *VTs = getNodeValueTypes(VT1, VT2);
>> +  return getNode(~Opcode, dl, VTs, 2, &Op1, 1).getNode();
>> +}
>> +
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>>                                    MVT VT2, SDValue Op1,
>>                                    SDValue Op2) {
>> @@ -4428,6 +4820,14 @@
>>  SDValue Ops[] = { Op1, Op2 };
>>  return getNode(~Opcode, VTs, 2, Ops, 2).getNode();
>> }
>> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
>> MVT VT1,
>> +                                    MVT VT2, SDValue Op1,
>> +                                    SDValue Op2) {
>> +  const MVT *VTs = getNodeValueTypes(VT1, VT2);
>> +  SDValue Ops[] = { Op1, Op2 };
>> +  return getNode(~Opcode, dl, VTs, 2, Ops, 2).getNode();
>> +}
>> +
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>>                                    MVT VT2, SDValue Op1,
>>                                    SDValue Op2, SDValue Op3) {
>> @@ -4435,17 +4835,40 @@
>>  SDValue Ops[] = { Op1, Op2, Op3 };
>>  return getNode(~Opcode, VTs, 2, Ops, 3).getNode();
>> }
>> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
>> MVT VT1,
>> +                                    MVT VT2, SDValue Op1,
>> +                                    SDValue Op2, SDValue Op3) {
>> +  const MVT *VTs = getNodeValueTypes(VT1, VT2);
>> +  SDValue Ops[] = { Op1, Op2, Op3 };
>> +  return getNode(~Opcode, dl, VTs, 2, Ops, 3).getNode();
>> +}
>> +
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT  
>> VT2,
>>                                    const SDValue *Ops, unsigned
>> NumOps) {
>>  const MVT *VTs = getNodeValueTypes(VT1, VT2);
>>  return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode();
>> }
>> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
>> +                                    MVT VT1, MVT VT2,
>> +                                    const SDValue *Ops, unsigned
>> NumOps) {
>> +  const MVT *VTs = getNodeValueTypes(VT1, VT2);
>> +  return getNode(~Opcode, dl, VTs, 2, Ops, NumOps).getNode();
>> +}
>> +
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT
>> VT2, MVT VT3,
>>                                    SDValue Op1, SDValue Op2) {
>>  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
>>  SDValue Ops[] = { Op1, Op2 };
>>  return getNode(~Opcode, VTs, 3, Ops, 2).getNode();
>> }
>> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
>> +                                    MVT VT1, MVT VT2, MVT VT3,
>> +                                    SDValue Op1, SDValue Op2) {
>> +  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
>> +  SDValue Ops[] = { Op1, Op2 };
>> +  return getNode(~Opcode, dl, VTs, 3, Ops, 2).getNode();
>> +}
>> +
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT
>> VT2, MVT VT3,
>>                                    SDValue Op1, SDValue Op2,
>>                                    SDValue Op3) {
>> @@ -4453,11 +4876,27 @@
>>  SDValue Ops[] = { Op1, Op2, Op3 };
>>  return getNode(~Opcode, VTs, 3, Ops, 3).getNode();
>> }
>> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
>> +                                    MVT VT1, MVT VT2, MVT VT3,
>> +                                    SDValue Op1, SDValue Op2,
>> +                                    SDValue Op3) {
>> +  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
>> +  SDValue Ops[] = { Op1, Op2, Op3 };
>> +  return getNode(~Opcode, dl, VTs, 3, Ops, 3).getNode();
>> +}
>> +
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT
>> VT2, MVT VT3,
>>                                    const SDValue *Ops, unsigned
>> NumOps) {
>>  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
>>  return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
>> }
>> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
>> +                                    MVT VT1, MVT VT2, MVT VT3,
>> +                                    const SDValue *Ops, unsigned
>> NumOps) {
>> +  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
>> +  return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
>> +}
>> +
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>>                                    MVT VT2, MVT VT3, MVT VT4,
>>                                    const SDValue *Ops, unsigned
>> NumOps) {
>> @@ -4469,6 +4908,18 @@
>>  const MVT *VTs = getNodeValueTypes(VTList);
>>  return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode();
>> }
>> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
>> MVT VT1,
>> +                                    MVT VT2, MVT VT3, MVT VT4,
>> +                                    const SDValue *Ops, unsigned
>> NumOps) {
>> +  std::vector VTList;
>> +  VTList.push_back(VT1);
>> +  VTList.push_back(VT2);
>> +  VTList.push_back(VT3);
>> +  VTList.push_back(VT4);
>> +  const MVT *VTs = getNodeValueTypes(VTList);
>> +  return getNode(~Opcode, dl, VTs, 4, Ops, NumOps).getNode();
>> +}
>> +
>> SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
>>                                    const std::vector &ResultTys,
>>                                    const SDValue *Ops, unsigned
>> NumOps) {
>> @@ -4476,6 +4927,13 @@
>>  return getNode(~Opcode, VTs, ResultTys.size(),
>>                 Ops, NumOps).getNode();
>> }
>> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
>> +                                    const std::vector
>> &ResultTys,
>> +                                    const SDValue *Ops, unsigned
>> NumOps) {
>> +  const MVT *VTs = getNodeValueTypes(ResultTys);
>> +  return getNode(~Opcode, dl, VTs, ResultTys.size(),
>> +                 Ops, NumOps).getNode();
>> +}
>>
>> /// getNodeIfExists - Get the specified node if it's already
>> available, or
>> /// else return NULL.
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From evan.cheng at apple.com  Wed Jan 28 19:13:00 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 29 Jan 2009 01:13:00 -0000
Subject: [llvm-commits] [llvm] r63263 -
	/llvm/trunk/lib/CodeGen/RegAllocLocal.cpp
Message-ID: <200901290113.n0T1D0Tc030976@zion.cs.uiuc.edu>

Author: evancheng
Date: Wed Jan 28 19:13:00 2009
New Revision: 63263

URL: http://llvm.org/viewvc/llvm-project?rev=63263&view=rev
Log:
A slight compile time optimization. If the caller knows there isn't a free register getReg() should not call getFreeReg().

Modified:
    llvm/trunk/lib/CodeGen/RegAllocLocal.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocLocal.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLocal.cpp?rev=63263&r1=63262&r2=63263&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLocal.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLocal.cpp Wed Jan 28 19:13:00 2009
@@ -220,10 +220,10 @@
     /// getReg - Find a physical register to hold the specified virtual
     /// register.  If all compatible physical registers are used, this method
     /// spills the last used virtual register to the stack, and uses that
-    /// register.
-    ///
+    /// register. If NoFree is true, that means the caller knows there isn't
+    /// a free register, do not call getFreeReg().
     unsigned getReg(MachineBasicBlock &MBB, MachineInstr *MI,
-                    unsigned VirtReg);
+                    unsigned VirtReg, bool NoFree = false);
 
     /// reloadVirtReg - This method transforms the specified specified virtual
     /// register use to refer to a physical register.  This method may do this
@@ -398,11 +398,11 @@
 /// the last used virtual register to the stack, and uses that register.
 ///
 unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I,
-                         unsigned VirtReg) {
+                         unsigned VirtReg, bool NoFree) {
   const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
 
   // First check to see if we have a free register of the requested type...
-  unsigned PhysReg = getFreeReg(RC);
+  unsigned PhysReg = NoFree ? 0 : getFreeReg(RC);
 
   // If we didn't find an unused register, scavenge one now!
   if (PhysReg == 0) {
@@ -498,7 +498,7 @@
   } else {         // No registers available.
     // Force some poor hapless value out of the register file to
     // make room for the new register, and reload it.
-    PhysReg = getReg(MBB, MI, VirtReg);
+    PhysReg = getReg(MBB, MI, VirtReg, true);
   }
 
   markVirtRegModified(VirtReg, false);   // Note that this reg was just reloaded




From gohman at apple.com  Wed Jan 28 19:37:18 2009
From: gohman at apple.com (Dan Gohman)
Date: Thu, 29 Jan 2009 01:37:18 -0000
Subject: [llvm-commits] [llvm] r63265 -
	/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
Message-ID: <200901290137.n0T1bJYP031778@zion.cs.uiuc.edu>

Author: djg
Date: Wed Jan 28 19:37:18 2009
New Revision: 63265

URL: http://llvm.org/viewvc/llvm-project?rev=63265&view=rev
Log:
Move the code that starts printing the Select_* functions
after the code that sorts the patterns. This doesn't
affect the output, but it makes the code a little easier
to follow.

Modified:
    llvm/trunk/utils/TableGen/DAGISelEmitter.cpp

Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=63265&r1=63264&r2=63265&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Wed Jan 28 19:37:18 2009
@@ -1825,9 +1825,6 @@
       } else
         OpVTI->second.push_back(OpVTStr);
 
-      OS << "SDNode *Select_" << getLegalCName(OpName)
-         << OpVTStr << "(const SDValue &N) {\n";    
-
       // We want to emit all of the matching code now.  However, we want to emit
       // the matches in order of minimal cost.  Sort the patterns so the least
       // cost one is at the start.
@@ -1869,6 +1866,9 @@
       // Next, reverse the list of patterns itself for the same reason.
       std::reverse(CodeForPatterns.begin(), CodeForPatterns.end());
     
+      OS << "SDNode *Select_" << getLegalCName(OpName)
+         << OpVTStr << "(const SDValue &N) {\n";    
+
       // Emit all of the patterns now, grouped together to share code.
       EmitPatterns(CodeForPatterns, 2, OS);
     




From gohman at apple.com  Wed Jan 28 19:59:02 2009
From: gohman at apple.com (Dan Gohman)
Date: Thu, 29 Jan 2009 01:59:02 -0000
Subject: [llvm-commits] [llvm] r63266 - in /llvm/trunk:
 include/llvm/Target/TargetLowering.h
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 lib/CodeGen/SelectionDAG/TargetLowering.cpp
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/bt.ll
 test/CodeGen/X86/commute-cmov.ll
Message-ID: <200901290159.n0T1x25H032445@zion.cs.uiuc.edu>

Author: djg
Date: Wed Jan 28 19:59:02 2009
New Revision: 63266

URL: http://llvm.org/viewvc/llvm-project?rev=63266&view=rev
Log:
Make x86's BT instruction matching more thorough, and add some
dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.

Modified:
    llvm/trunk/include/llvm/Target/TargetLowering.h
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/bt.ll
    llvm/trunk/test/CodeGen/X86/commute-cmov.ll

Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=63266&r1=63265&r2=63266&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Wed Jan 28 19:59:02 2009
@@ -780,6 +780,8 @@
     SDValue CombineTo(SDNode *N, const std::vector &To);
     SDValue CombineTo(SDNode *N, SDValue Res);
     SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1);
+
+    void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
   };
 
   /// SimplifySetCC - Try to simplify a setcc built with the specified operands 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63266&r1=63265&r2=63266&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Jan 28 19:59:02 2009
@@ -102,6 +102,8 @@
       SDValue To[] = { Res0, Res1 };
       return CombineTo(N, To, 2, AddTo);
     }
+
+    void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
     
   private:    
     
@@ -298,6 +300,10 @@
   return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
 }
 
+void TargetLowering::DAGCombinerInfo::
+CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
+  return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
+}
 
 //===----------------------------------------------------------------------===//
 // Helper Functions
@@ -539,29 +545,14 @@
   return SDValue(N, 0);
 }
 
-/// SimplifyDemandedBits - Check the specified integer node value to see if
-/// it can be simplified or if things it uses can be simplified by bit
-/// propagation.  If so, return true.
-bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
-  TargetLowering::TargetLoweringOpt TLO(DAG);
-  APInt KnownZero, KnownOne;
-  if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
-    return false;
-  
-  // Revisit the node.
-  AddToWorkList(Op.getNode());
-  
-  // Replace the old value with the new one.
-  ++NodesCombined;
-  DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG));
-  DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
-  DOUT << '\n';
-  
+void
+DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &
+                                                                          TLO) {
   // Replace all uses.  If any nodes become isomorphic to other nodes and 
   // are deleted, make sure to remove them from our worklist.
   WorkListRemover DeadNodes(*this);
   DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
-  
+
   // Push the new node and any (possibly new) users onto the worklist.
   AddToWorkList(TLO.New.getNode());
   AddUsersToWorkList(TLO.New.getNode());
@@ -580,6 +571,27 @@
     
     DAG.DeleteNode(TLO.Old.getNode());
   }
+}
+
+/// SimplifyDemandedBits - Check the specified integer node value to see if
+/// it can be simplified or if things it uses can be simplified by bit
+/// propagation.  If so, return true.
+bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
+  TargetLowering::TargetLoweringOpt TLO(DAG);
+  APInt KnownZero, KnownOne;
+  if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
+    return false;
+  
+  // Revisit the node.
+  AddToWorkList(Op.getNode());
+  
+  // Replace the old value with the new one.
+  ++NodesCombined;
+  DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG));
+  DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
+  DOUT << '\n';
+  
+  CommitTargetLoweringOpt(TLO);
   return true;
 }
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=63266&r1=63265&r2=63266&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Jan 28 19:59:02 2009
@@ -724,7 +724,7 @@
 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 
                                                         const APInt &Demanded) {
   // FIXME: ISD::SELECT, ISD::SELECT_CC
-  switch(Op.getOpcode()) {
+  switch (Op.getOpcode()) {
   default: break;
   case ISD::AND:
   case ISD::OR:
@@ -1054,6 +1054,14 @@
     }
     break;
   case ISD::SRA:
+    // If this is an arithmetic shift right and only the low-bit is set, we can
+    // always convert this into a logical shr, even if the shift amount is
+    // variable.  The low bit of the shift cannot be an input sign bit unless
+    // the shift amount is >= the size of the datatype, which is undefined.
+    if (DemandedMask == 1)
+      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, Op.getValueType(),
+                                               Op.getOperand(0), Op.getOperand(1)));
+
     if (ConstantSDNode *SA = dyn_cast(Op.getOperand(1))) {
       MVT VT = Op.getValueType();
       unsigned ShAmt = SA->getZExtValue();
@@ -1332,6 +1340,21 @@
   return 1;
 }
 
+static bool ValueHasAtMostOneBitSet(SDValue Val, const SelectionDAG &DAG) {
+  // Logical shift right or left won't ever introduce new set bits.
+  // We check for this case because we don't care which bits are
+  // set, but ComputeMaskedBits won't know anything unless it can
+  // determine which specific bits may be set.
+  if (Val.getOpcode() == ISD::SHL || Val.getOpcode() == ISD::SRL)
+    return ValueHasAtMostOneBitSet(Val.getOperand(0), DAG);
+
+  MVT OpVT = Val.getValueType();
+  unsigned BitWidth = OpVT.getSizeInBits();
+  APInt Mask = APInt::getAllOnesValue(BitWidth);
+  APInt KnownZero, KnownOne;
+  DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
+  return KnownZero.countPopulation() == BitWidth - 1;
+}
 
 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 
 /// and cc. If it is unable to simplify it, return a null SDValue.
@@ -1791,6 +1814,24 @@
         }
       }
     }
+
+    // Simpify x&y == y to x&y == 0 if y has exactly one bit set.
+    if (N0.getOpcode() == ISD::AND)
+      if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
+        if (ValueHasAtMostOneBitSet(N1, DAG)) {
+          Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
+          SDValue Zero = DAG.getConstant(0, N1.getValueType());
+          return DAG.getSetCC(VT, N0, Zero, Cond);
+        }
+      }
+    if (N1.getOpcode() == ISD::AND)
+      if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
+        if (ValueHasAtMostOneBitSet(N0, DAG)) {
+          Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
+          SDValue Zero = DAG.getConstant(0, N0.getValueType());
+          return DAG.getSetCC(VT, N1, Zero, Cond);
+        }
+      }
   }
 
   // Fold away ALL boolean setcc's.

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=63266&r1=63265&r2=63266&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jan 28 19:59:02 2009
@@ -5114,22 +5114,39 @@
   SDValue Op1 = Op.getOperand(1);
   ISD::CondCode CC = cast(Op.getOperand(2))->get();
   
-  // Lower (X & (1 << N)) == 0 to BT.
-  // Lower ((X >>u N) & 1) != 0 to BT.
-  // Lower ((X >>s N) & 1) != 0 to BT.
+  // Lower (X & (1 << N)) == 0 to BT(X, N).
+  // Lower ((X >>u N) & 1) != 0 to BT(X, N).
+  // Lower ((X >>s N) & 1) != 0 to BT(X, N).
   if (Op0.getOpcode() == ISD::AND &&
       Op0.hasOneUse() &&
       Op1.getOpcode() == ISD::Constant &&
-      Op0.getOperand(1).getOpcode() == ISD::Constant &&
+      cast(Op1)->getZExtValue() == 0 &&
       (CC == ISD::SETEQ || CC == ISD::SETNE)) {
-    ConstantSDNode *AndRHS = cast(Op0.getOperand(1));
-    ConstantSDNode *CmpRHS = cast(Op1);
-    SDValue AndLHS = Op0.getOperand(0);
-    if (CmpRHS->getZExtValue() == 0 && AndRHS->getZExtValue() == 1 &&
-        AndLHS.getOpcode() == ISD::SRL) {
-      SDValue LHS = AndLHS.getOperand(0);
-      SDValue RHS = AndLHS.getOperand(1);
+    SDValue LHS, RHS;
+    if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
+      if (ConstantSDNode *Op010C =
+            dyn_cast(Op0.getOperand(1).getOperand(0)))
+        if (Op010C->getZExtValue() == 1) {
+          LHS = Op0.getOperand(0);
+          RHS = Op0.getOperand(1).getOperand(1);
+        }
+    } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
+      if (ConstantSDNode *Op000C =
+            dyn_cast(Op0.getOperand(0).getOperand(0)))
+        if (Op000C->getZExtValue() == 1) {
+          LHS = Op0.getOperand(1);
+          RHS = Op0.getOperand(0).getOperand(1);
+        }
+    } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
+      ConstantSDNode *AndRHS = cast(Op0.getOperand(1));
+      SDValue AndLHS = Op0.getOperand(0);
+      if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
+        LHS = AndLHS.getOperand(0);
+        RHS = AndLHS.getOperand(1);
+      }
+    }
 
+    if (LHS.getNode()) {
       // If LHS is i8, promote it to i16 with any_extend.  There is no i8 BT
       // instruction.  Since the shift amount is in-range-or-undefined, we know
       // that doing a bittest on the i16 value is ok.  We extend to i32 because
@@ -5141,10 +5158,10 @@
       // BT ignores high bits (like shifts) we can use anyextend.
       if (LHS.getValueType() != RHS.getValueType())
         RHS = DAG.getNode(ISD::ANY_EXTEND, LHS.getValueType(), RHS);
-      
+
       SDValue BT = DAG.getNode(X86ISD::BT, MVT::i32, LHS, RHS);
       unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
-      return DAG.getNode(X86ISD::SETCC, MVT::i8, 
+      return DAG.getNode(X86ISD::SETCC, MVT::i8,
                          DAG.getConstant(Cond, MVT::i8), BT);
     }
   }
@@ -5295,7 +5312,7 @@
         !isScalarFPTypeInSSEReg(VT))  // FPStack?
       IllegalFPCMov = !hasFPCMov(cast(CC)->getSExtValue());
     
-    if (isX86LogicalCmp(Opc) && !IllegalFPCMov) {
+    if ((isX86LogicalCmp(Opc) && !IllegalFPCMov) || Opc == X86ISD::BT) { // FIXME
       Cond = Cmp;
       addTest = false;
     }
@@ -7547,6 +7564,7 @@
 
 /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
 static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
+                                         TargetLowering::DAGCombinerInfo &DCI,
                                          const X86Subtarget *Subtarget,
                                          const TargetLowering &TLI) {
   unsigned NumOps = N->getNumOperands();
@@ -7587,7 +7605,9 @@
   SDVTList Tys = DAG.getVTList(VT, MVT::Other);
   SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
   SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, Tys, Ops, 2);
-  DAG.ReplaceAllUsesOfValueWith(SDValue(Base, 1), ResNode.getValue(1));
+  TargetLowering::TargetLoweringOpt TLO(DAG);
+  TLO.CombineTo(SDValue(Base, 1), ResNode.getValue(1));
+  DCI.CommitTargetLoweringOpt(TLO);
   return ResNode;
 }                                           
 
@@ -7875,6 +7895,23 @@
   return SDValue();
 }
 
+static SDValue PerformBTCombine(SDNode *N,
+                                SelectionDAG &DAG,
+                                TargetLowering::DAGCombinerInfo &DCI) {
+  // BT ignores high bits in the bit index operand.
+  SDValue Op1 = N->getOperand(1);
+  if (Op1.hasOneUse()) {
+    unsigned BitWidth = Op1.getValueSizeInBits();
+    APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
+    APInt KnownZero, KnownOne;
+    TargetLowering::TargetLoweringOpt TLO(DAG);
+    TargetLowering &TLI = DAG.getTargetLoweringInfo();
+    if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
+        TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
+      DCI.CommitTargetLoweringOpt(TLO);
+  }
+  return SDValue();
+}
 
 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
                                              DAGCombinerInfo &DCI) const {
@@ -7883,7 +7920,7 @@
   default: break;
   case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
   case ISD::BUILD_VECTOR:
-    return PerformBuildVectorCombine(N, DAG, Subtarget, *this);
+    return PerformBuildVectorCombine(N, DAG, DCI, Subtarget, *this);
   case ISD::SELECT:         return PerformSELECTCombine(N, DAG, Subtarget);
   case ISD::SHL:
   case ISD::SRA:
@@ -7892,6 +7929,7 @@
   case X86ISD::FXOR:
   case X86ISD::FOR:         return PerformFORCombine(N, DAG);
   case X86ISD::FAND:        return PerformFANDCombine(N, DAG);
+  case X86ISD::BT:          return PerformBTCombine(N, DAG, DCI);
   }
 
   return SDValue();

Modified: llvm/trunk/test/CodeGen/X86/bt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bt.ll?rev=63266&r1=63265&r2=63266&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/bt.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bt.ll Wed Jan 28 19:59:02 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep btl
+; RUN: llvm-as < %s | llc -march=x86 | grep btl | count 28
 ; RUN: llvm-as < %s | llc -mcpu=pentium4 | grep btl | not grep esp
 ; RUN: llvm-as < %s | llc -mcpu=penryn   | grep btl | not grep esp
 ; PR3253
@@ -7,8 +7,17 @@
 ; pentium4, however it is currently disabled due to the register+memory
 ; form having different semantics than the register+register form.
 
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
-target triple = "i386-apple-darwin8"
+; Test these patterns:
+;    (X & (1 << N))  != 0  -->  BT(X, N).
+;    ((X >>u N) & 1) != 0  -->  BT(X, N).
+; as well as several variations:
+;    - The second form can use an arithmetic shift.
+;    - Either form can use == instead of !=.
+;    - Either form can compare with an operand of the &
+;      instead of with 0.
+;    - The comparison can be commuted (only cases where neither
+;      operand is constant are included).
+;    - The and can be commuted.
 
 define void @test2(i32 %x, i32 %n) nounwind {
 entry:
@@ -25,4 +34,409 @@
 	ret void
 }
 
+define void @test2b(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = lshr i32 %x, %n		;  [#uses=1]
+	%tmp3 = and i32 1, %tmp29
+	%tmp4 = icmp eq i32 %tmp3, 0		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @atest2(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = ashr i32 %x, %n		;  [#uses=1]
+	%tmp3 = and i32 %tmp29, 1		;  [#uses=1]
+	%tmp4 = icmp eq i32 %tmp3, 0		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @atest2b(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = ashr i32 %x, %n		;  [#uses=1]
+	%tmp3 = and i32 1, %tmp29
+	%tmp4 = icmp eq i32 %tmp3, 0		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @test3(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = shl i32 1, %n		;  [#uses=1]
+	%tmp3 = and i32 %tmp29, %x		;  [#uses=1]
+	%tmp4 = icmp eq i32 %tmp3, 0		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @test3b(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = shl i32 1, %n		;  [#uses=1]
+	%tmp3 = and i32 %x, %tmp29
+	%tmp4 = icmp eq i32 %tmp3, 0		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @testne2(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = lshr i32 %x, %n		;  [#uses=1]
+	%tmp3 = and i32 %tmp29, 1		;  [#uses=1]
+	%tmp4 = icmp ne i32 %tmp3, 0		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @testne2b(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = lshr i32 %x, %n		;  [#uses=1]
+	%tmp3 = and i32 1, %tmp29
+	%tmp4 = icmp ne i32 %tmp3, 0		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @atestne2(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = ashr i32 %x, %n		;  [#uses=1]
+	%tmp3 = and i32 %tmp29, 1		;  [#uses=1]
+	%tmp4 = icmp ne i32 %tmp3, 0		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @atestne2b(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = ashr i32 %x, %n		;  [#uses=1]
+	%tmp3 = and i32 1, %tmp29
+	%tmp4 = icmp ne i32 %tmp3, 0		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @testne3(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = shl i32 1, %n		;  [#uses=1]
+	%tmp3 = and i32 %tmp29, %x		;  [#uses=1]
+	%tmp4 = icmp ne i32 %tmp3, 0		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @testne3b(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = shl i32 1, %n		;  [#uses=1]
+	%tmp3 = and i32 %x, %tmp29
+	%tmp4 = icmp ne i32 %tmp3, 0		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @query2(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = lshr i32 %x, %n		;  [#uses=1]
+	%tmp3 = and i32 %tmp29, 1		;  [#uses=1]
+	%tmp4 = icmp eq i32 %tmp3, 1		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @query2b(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = lshr i32 %x, %n		;  [#uses=1]
+	%tmp3 = and i32 1, %tmp29
+	%tmp4 = icmp eq i32 %tmp3, 1		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @aquery2(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = ashr i32 %x, %n		;  [#uses=1]
+	%tmp3 = and i32 %tmp29, 1		;  [#uses=1]
+	%tmp4 = icmp eq i32 %tmp3, 1		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @aquery2b(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = ashr i32 %x, %n		;  [#uses=1]
+	%tmp3 = and i32 1, %tmp29
+	%tmp4 = icmp eq i32 %tmp3, 1		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @query3(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = shl i32 1, %n		;  [#uses=1]
+	%tmp3 = and i32 %tmp29, %x		;  [#uses=1]
+	%tmp4 = icmp eq i32 %tmp3, %tmp29		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @query3b(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = shl i32 1, %n		;  [#uses=1]
+	%tmp3 = and i32 %x, %tmp29
+	%tmp4 = icmp eq i32 %tmp3, %tmp29		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @query3x(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = shl i32 1, %n		;  [#uses=1]
+	%tmp3 = and i32 %tmp29, %x		;  [#uses=1]
+	%tmp4 = icmp eq i32 %tmp29, %tmp3		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @query3bx(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = shl i32 1, %n		;  [#uses=1]
+	%tmp3 = and i32 %x, %tmp29
+	%tmp4 = icmp eq i32 %tmp29, %tmp3		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @queryne2(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = lshr i32 %x, %n		;  [#uses=1]
+	%tmp3 = and i32 %tmp29, 1		;  [#uses=1]
+	%tmp4 = icmp ne i32 %tmp3, 1		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @queryne2b(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = lshr i32 %x, %n		;  [#uses=1]
+	%tmp3 = and i32 1, %tmp29
+	%tmp4 = icmp ne i32 %tmp3, 1		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @aqueryne2(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = ashr i32 %x, %n		;  [#uses=1]
+	%tmp3 = and i32 %tmp29, 1		;  [#uses=1]
+	%tmp4 = icmp ne i32 %tmp3, 1		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @aqueryne2b(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = ashr i32 %x, %n		;  [#uses=1]
+	%tmp3 = and i32 1, %tmp29
+	%tmp4 = icmp ne i32 %tmp3, 1		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @queryne3(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = shl i32 1, %n		;  [#uses=1]
+	%tmp3 = and i32 %tmp29, %x		;  [#uses=1]
+	%tmp4 = icmp ne i32 %tmp3, %tmp29		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @queryne3b(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = shl i32 1, %n		;  [#uses=1]
+	%tmp3 = and i32 %x, %tmp29
+	%tmp4 = icmp ne i32 %tmp3, %tmp29		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @queryne3x(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = shl i32 1, %n		;  [#uses=1]
+	%tmp3 = and i32 %tmp29, %x		;  [#uses=1]
+	%tmp4 = icmp ne i32 %tmp29, %tmp3		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
+define void @queryne3bx(i32 %x, i32 %n) nounwind {
+entry:
+	%tmp29 = shl i32 1, %n		;  [#uses=1]
+	%tmp3 = and i32 %x, %tmp29
+	%tmp4 = icmp ne i32 %tmp29, %tmp3		;  [#uses=1]
+	br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb:		; preds = %entry
+	call void @foo()
+	ret void
+
+UnifiedReturnBlock:		; preds = %entry
+	ret void
+}
+
 declare void @foo()

Modified: llvm/trunk/test/CodeGen/X86/commute-cmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/commute-cmov.ll?rev=63266&r1=63265&r2=63266&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/commute-cmov.ll (original)
+++ llvm/trunk/test/CodeGen/X86/commute-cmov.ll Wed Jan 28 19:59:02 2009
@@ -1,5 +1,20 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {cmove	16(%esp)}
+; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: grep btl %t | count 2
+; RUN: grep cmov %t | count 2
+; RUN: not grep test %t
+; RUN: not grep set %t
+; RUN: not grep j %t
+; RUN: not grep cmovne %t
+; RUN: not grep cmove %t
 
+define i32 @foo(i32 %x, i32 %n, i32 %w, i32 %v) nounwind readnone {
+entry:
+	%0 = lshr i32 %x, %n		;  [#uses=1]
+	%1 = and i32 %0, 1		;  [#uses=1]
+	%toBool = icmp eq i32 %1, 0		;  [#uses=1]
+	%.0 = select i1 %toBool, i32 %v, i32 12		;  [#uses=1]
+	ret i32 %.0
+}
 define i32 @bar(i32 %x, i32 %n, i32 %w, i32 %v) nounwind readnone {
 entry:
 	%0 = lshr i32 %x, %n		;  [#uses=1]




From evan.cheng at apple.com  Wed Jan 28 20:20:59 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 29 Jan 2009 02:20:59 -0000
Subject: [llvm-commits] [llvm] r63267 - in /llvm/trunk:
 include/llvm/CodeGen/LiveInterval.h lib/CodeGen/LiveInterval.cpp
 lib/CodeGen/LiveIntervalAnalysis.cpp lib/CodeGen/RegAllocLocal.cpp
 test/CodeGen/X86/illegal-asm.ll
Message-ID: <200901290220.n0T2KxGM000813@zion.cs.uiuc.edu>

Author: evancheng
Date: Wed Jan 28 20:20:59 2009
New Revision: 63267

URL: http://llvm.org/viewvc/llvm-project?rev=63267&view=rev
Log:
Exit with nice warnings when register allocator run out of registers.

Added:
    llvm/trunk/test/CodeGen/X86/illegal-asm.ll
Modified:
    llvm/trunk/include/llvm/CodeGen/LiveInterval.h
    llvm/trunk/lib/CodeGen/LiveInterval.cpp
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
    llvm/trunk/lib/CodeGen/RegAllocLocal.cpp

Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=63267&r1=63266&r2=63267&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Wed Jan 28 20:20:59 2009
@@ -377,6 +377,10 @@
               const int *RHSValNoAssignments,
               SmallVector &NewVNInfo);
 
+    /// isInOneLiveRange - Return true if the range specified is entirely in the
+    /// a single LiveRange of the live interval.
+    bool isInOneLiveRange(unsigned Start, unsigned End);
+
     /// removeRange - Remove the specified range from this interval.  Note that
     /// the range must be a single LiveRange in its entirety.
     void removeRange(unsigned Start, unsigned End, bool RemoveDeadValNo = false);

Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=63267&r1=63266&r2=63267&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Wed Jan 28 20:20:59 2009
@@ -244,6 +244,16 @@
   return ranges.insert(it, LR);
 }
 
+/// isInOneLiveRange - Return true if the range specified is entirely in the
+/// a single LiveRange of the live interval.
+bool LiveInterval::isInOneLiveRange(unsigned Start, unsigned End) {
+  Ranges::iterator I = std::upper_bound(ranges.begin(), ranges.end(), Start);
+  if (I == ranges.begin())
+    return false;
+  --I;
+  return I->contains(Start) && I->contains(End-1);
+}
+
 
 /// removeRange - Remove the specified range from this interval.  Note that
 /// the range must be in a single LiveRange in its entirety.

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=63267&r1=63266&r2=63267&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Jan 28 20:20:59 2009
@@ -2228,7 +2228,19 @@
     unsigned Index = getInstructionIndex(MI);
     if (pli.liveAt(Index)) {
       vrm.addEmergencySpill(SpillReg, MI);
-      pli.removeRange(getLoadIndex(Index), getStoreIndex(Index)+1);
+      unsigned StartIdx = getLoadIndex(Index);
+      unsigned EndIdx = getStoreIndex(Index)+1;
+      if (pli.isInOneLiveRange(StartIdx, EndIdx))
+        pli.removeRange(StartIdx, EndIdx);
+      else {
+        cerr << "Ran out of registers during register allocation!\n";
+        if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
+          cerr << "Please check your inline asm statement for invalid "
+               << "constraints:\n";
+          MI->print(cerr.stream(), tm_);
+        }
+        exit(1);
+      }
       for (const unsigned* AS = tri_->getSubRegisters(SpillReg); *AS; ++AS) {
         if (!hasInterval(*AS))
           continue;

Modified: llvm/trunk/lib/CodeGen/RegAllocLocal.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLocal.cpp?rev=63267&r1=63266&r2=63267&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLocal.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLocal.cpp Wed Jan 28 20:20:59 2009
@@ -27,6 +27,7 @@
 #include "llvm/Support/Compiler.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/IndexedMap.h"
+#include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/STLExtras.h"
@@ -237,7 +238,7 @@
     /// value.  This method returns the modified instruction.
     ///
     MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
-                                unsigned OpNum);
+                                unsigned OpNum, SmallSet &RRegs);
 
     /// ComputeLocalLiveness - Computes liveness of registers within a basic
     /// block, setting the killed/dead flags as appropriate.
@@ -475,7 +476,8 @@
 /// modified instruction.
 ///
 MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
-                                     unsigned OpNum) {
+                                     unsigned OpNum,
+                                     SmallSet &ReloadedRegs) {
   unsigned VirtReg = MI->getOperand(OpNum).getReg();
 
   // If the virtual register is already available, just update the instruction
@@ -513,6 +515,29 @@
   MF->getRegInfo().setPhysRegUsed(PhysReg);
   MI->getOperand(OpNum).setReg(PhysReg);  // Assign the input register
   getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
+
+  if (!ReloadedRegs.insert(PhysReg)) {
+    cerr << "Ran out of registers during register allocation!\n";
+    if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
+      cerr << "Please check your inline asm statement for invalid "
+           << "constraints:\n";
+      MI->print(cerr.stream(), TM);
+    }
+    exit(1);
+  }
+  for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
+       *SubRegs; ++SubRegs) {
+    if (!ReloadedRegs.insert(*SubRegs)) {
+      cerr << "Ran out of registers during register allocation!\n";
+      if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
+        cerr << "Please check your inline asm statement for invalid "
+             << "constraints:\n";
+        MI->print(cerr.stream(), TM);
+      }
+      exit(1);
+    }
+  }
+
   return MI;
 }
 
@@ -581,17 +606,16 @@
         
         if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) continue;
         
-        const unsigned* subregs = TRI->getAliasSet(MO.getReg());
-        if (subregs) {
-          while (*subregs) {
+        const unsigned* Aliases = TRI->getAliasSet(MO.getReg());
+        if (Aliases) {
+          while (*Aliases) {
             DenseMap >::iterator
-              alias = LastUseDef.find(*subregs);
+              alias = LastUseDef.find(*Aliases);
             
-            if (alias != LastUseDef.end() &&
-                alias->second.first != I)
-              LastUseDef[*subregs] = std::make_pair(I, i);
+            if (alias != LastUseDef.end() && alias->second.first != I)
+              LastUseDef[*Aliases] = std::make_pair(I, i);
             
-            ++subregs;
+            ++Aliases;
           }
         }
       }
@@ -695,12 +719,12 @@
       MF->getRegInfo().setPhysRegUsed(Reg);
       PhysRegsUsed[Reg] = 0;            // It is free and reserved now
       AddToPhysRegsUseOrder(Reg); 
-      for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
-           *AliasSet; ++AliasSet) {
-        if (PhysRegsUsed[*AliasSet] != -2) {
-          AddToPhysRegsUseOrder(*AliasSet); 
-          PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
-          MF->getRegInfo().setPhysRegUsed(*AliasSet);
+      for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
+           *SubRegs; ++SubRegs) {
+        if (PhysRegsUsed[*SubRegs] != -2) {
+          AddToPhysRegsUseOrder(*SubRegs); 
+          PhysRegsUsed[*SubRegs] = 0;  // It is free and reserved now
+          MF->getRegInfo().setPhysRegUsed(*SubRegs);
         }
       }
     }    
@@ -778,12 +802,12 @@
             PhysRegsUsed[Reg] = 0;            // It is free and reserved now
             AddToPhysRegsUseOrder(Reg); 
 
-            for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
-                 *AliasSet; ++AliasSet) {
-              if (PhysRegsUsed[*AliasSet] != -2) {
-                MF->getRegInfo().setPhysRegUsed(*AliasSet);
-                PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
-                AddToPhysRegsUseOrder(*AliasSet); 
+            for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
+                 *SubRegs; ++SubRegs) {
+              if (PhysRegsUsed[*SubRegs] != -2) {
+                MF->getRegInfo().setPhysRegUsed(*SubRegs);
+                PhysRegsUsed[*SubRegs] = 0;  // It is free and reserved now
+                AddToPhysRegsUseOrder(*SubRegs); 
               }
             }
           }
@@ -797,12 +821,13 @@
     // physical register is referenced by the instruction, that it is guaranteed
     // to be live-in, or the input is badly hosed.
     //
+    SmallSet ReloadedRegs;
     for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
       MachineOperand& MO = MI->getOperand(i);
       // here we are looking for only used operands (never def&use)
       if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
           TargetRegisterInfo::isVirtualRegister(MO.getReg()))
-        MI = reloadVirtReg(MBB, MI, i);
+        MI = reloadVirtReg(MBB, MI, i, ReloadedRegs);
     }
 
     // If this instruction is the last user of this register, kill the
@@ -830,13 +855,13 @@
         DOUT << "  Last use of " << TRI->getName(PhysReg)
              << "[%reg" << VirtReg <<"], removing it from live set\n";
         removePhysReg(PhysReg);
-        for (const unsigned *AliasSet = TRI->getSubRegisters(PhysReg);
-             *AliasSet; ++AliasSet) {
-          if (PhysRegsUsed[*AliasSet] != -2) {
+        for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
+             *SubRegs; ++SubRegs) {
+          if (PhysRegsUsed[*SubRegs] != -2) {
             DOUT  << "  Last use of "
-                  << TRI->getName(*AliasSet)
+                  << TRI->getName(*SubRegs)
                   << "[%reg" << VirtReg <<"], removing it from live set\n";
-            removePhysReg(*AliasSet);
+            removePhysReg(*SubRegs);
           }
         }
       }
@@ -861,12 +886,12 @@
         PhysRegsUsed[Reg] = 0;            // It is free and reserved now
         AddToPhysRegsUseOrder(Reg); 
 
-        for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
-             *AliasSet; ++AliasSet) {
-          if (PhysRegsUsed[*AliasSet] != -2) {
-            MF->getRegInfo().setPhysRegUsed(*AliasSet);
-            PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
-            AddToPhysRegsUseOrder(*AliasSet); 
+        for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
+             *SubRegs; ++SubRegs) {
+          if (PhysRegsUsed[*SubRegs] != -2) {
+            MF->getRegInfo().setPhysRegUsed(*SubRegs);
+            PhysRegsUsed[*SubRegs] = 0;  // It is free and reserved now
+            AddToPhysRegsUseOrder(*SubRegs); 
           }
         }
       }
@@ -883,12 +908,12 @@
           PhysRegsUsed[Reg] = 0;            // It is free and reserved now
         }
         MF->getRegInfo().setPhysRegUsed(Reg);
-        for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
-             *AliasSet; ++AliasSet) {
-          if (PhysRegsUsed[*AliasSet] != -2) {
-            AddToPhysRegsUseOrder(*AliasSet); 
-            PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
-            MF->getRegInfo().setPhysRegUsed(*AliasSet);
+        for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
+             *SubRegs; ++SubRegs) {
+          if (PhysRegsUsed[*SubRegs] != -2) {
+            AddToPhysRegsUseOrder(*SubRegs); 
+            PhysRegsUsed[*SubRegs] = 0;  // It is free and reserved now
+            MF->getRegInfo().setPhysRegUsed(*SubRegs);
           }
         }
       }

Added: llvm/trunk/test/CodeGen/X86/illegal-asm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/illegal-asm.ll?rev=63267&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/illegal-asm.ll (added)
+++ llvm/trunk/test/CodeGen/X86/illegal-asm.ll Wed Jan 28 20:20:59 2009
@@ -0,0 +1,32 @@
+; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -disable-fp-elim
+; XFAIL: *
+; Expected to run out of registers during allocation.
+; rdar://6251720
+
+	%struct.CABACContext = type { i32, i32, i8* }
+	%struct.H264Context = type { %struct.CABACContext, [460 x i8] }
+ at coeff_abs_level_m1_offset = common global [6 x i32] zeroinitializer		; <[6 x i32]*> [#uses=1]
+ at coeff_abs_level1_ctx = common global [8 x i8] zeroinitializer		; <[8 x i8]*> [#uses=1]
+
+define i32 @decode_cabac_residual(%struct.H264Context* %h, i32 %cat) nounwind {
+entry:
+	%0 = getelementptr [6 x i32]* @coeff_abs_level_m1_offset, i32 0, i32 %cat		;  [#uses=1]
+	%1 = load i32* %0, align 4		;  [#uses=1]
+	%2 = load i8* getelementptr ([8 x i8]* @coeff_abs_level1_ctx, i32 0, i32 0), align 1		;  [#uses=1]
+	%3 = zext i8 %2 to i32		;  [#uses=1]
+	%.sum = add i32 %3, %1		;  [#uses=1]
+	%4 = getelementptr %struct.H264Context* %h, i32 0, i32 1, i32 %.sum		;  [#uses=2]
+	%5 = getelementptr %struct.H264Context* %h, i32 0, i32 0, i32 0		;  [#uses=2]
+	%6 = getelementptr %struct.H264Context* %h, i32 0, i32 0, i32 1		;  [#uses=2]
+	%7 = getelementptr %struct.H264Context* %h, i32 0, i32 0, i32 2		;  [#uses=2]
+	%8 = load i32* %5, align 4		;  [#uses=1]
+	%9 = load i32* %6, align 4		;  [#uses=1]
+	%10 = load i8* %4, align 4		;  [#uses=1]
+	%asmtmp = tail call { i32, i32, i32, i32 } asm sideeffect "#$0 $1 $2 $3 $4 $5", "=&{di},=r,=r,=*m,=&q,=*imr,1,2,*m,5,~{dirflag},~{fpsr},~{flags},~{cx}"(i8** %7, i8* %4, i32 %8, i32 %9, i8** %7, i8 %10) nounwind		; <{ i32, i32, i32, i32 }> [#uses=3]
+	%asmresult = extractvalue { i32, i32, i32, i32 } %asmtmp, 0		;  [#uses=1]
+	%asmresult1 = extractvalue { i32, i32, i32, i32 } %asmtmp, 1		;  [#uses=1]
+	store i32 %asmresult1, i32* %5
+	%asmresult2 = extractvalue { i32, i32, i32, i32 } %asmtmp, 2		;  [#uses=1]
+	store i32 %asmresult2, i32* %6
+	ret i32 %asmresult
+}




From isanbard at gmail.com  Wed Jan 28 22:17:30 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 29 Jan 2009 04:17:30 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63268 -
	/llvm-gcc-4.2/trunk/gcc/config/darwin.c
Message-ID: <200901290417.n0T4HVWZ004464@zion.cs.uiuc.edu>

Author: void
Date: Wed Jan 28 22:17:25 2009
New Revision: 63268

URL: http://llvm.org/viewvc/llvm-project?rev=63268&view=rev
Log:
Check for 10.6 or greater first so that stack protectors are enabled by default for those machines, instead of disabled as it was the other way.

Modified:
    llvm-gcc-4.2/trunk/gcc/config/darwin.c

Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/darwin.c?rev=63268&r1=63267&r2=63268&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/darwin.c (original)
+++ llvm-gcc-4.2/trunk/gcc/config/darwin.c Wed Jan 28 22:17:25 2009
@@ -2749,10 +2749,10 @@
 #else
   if (flag_stack_protect == -1 && darwin_macosx_version_min)
     {
-      if (strverscmp (darwin_macosx_version_min, "10.5") >= 0)
-        flag_stack_protect = 0;
-      else if (strverscmp (darwin_macosx_version_min, "10.6") >= 0)
+      if (strverscmp (darwin_macosx_version_min, "10.6") >= 0)
         flag_stack_protect = 1;
+      else if (strverscmp (darwin_macosx_version_min, "10.5") >= 0)
+        flag_stack_protect = 0;
     }
 #endif
   /* LLVM LOCAL end - Don't enable stack protectors by default for Leopard. */




From sabre at nondot.org  Wed Jan 28 22:43:42 2009
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 29 Jan 2009 04:43:42 -0000
Subject: [llvm-commits] [llvm] r63269 -
	/llvm/trunk/lib/System/DynamicLibrary.cpp
Message-ID: <200901290443.n0T4hhkf005290@zion.cs.uiuc.edu>

Author: lattner
Date: Wed Jan 28 22:43:42 2009
New Revision: 63269

URL: http://llvm.org/viewvc/llvm-project?rev=63269&view=rev
Log:
Fix PR3424, a static constructor ordering issue.  Patch by Robert Schuster!

Modified:
    llvm/trunk/lib/System/DynamicLibrary.cpp

Modified: llvm/trunk/lib/System/DynamicLibrary.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/DynamicLibrary.cpp?rev=63269&r1=63268&r2=63269&view=diff

==============================================================================
--- llvm/trunk/lib/System/DynamicLibrary.cpp (original)
+++ llvm/trunk/lib/System/DynamicLibrary.cpp Wed Jan 28 22:43:42 2009
@@ -18,11 +18,14 @@
 #include 
 
 // Collection of symbol name/value pairs to be searched prior to any libraries.
-static std::map g_symbols;
+std::map &g_symbols() {
+  static std::map symbols;
+  return symbols;
+}
 
 void llvm::sys::DynamicLibrary::AddSymbol(const char* symbolName,
                                           void *symbolValue) {
-  g_symbols[symbolName] = symbolValue;
+  g_symbols()[symbolName] = symbolValue;
 }
 
 // It is not possible to use ltdl.c on VC++ builds as the terms of its LGPL
@@ -76,8 +79,8 @@
   //  check_ltdl_initialization();
 
   // First check symbols added via AddSymbol().
-  std::map::iterator I = g_symbols.find(symbolName);
-  if (I != g_symbols.end())
+  std::map::iterator I = g_symbols().find(symbolName);
+  if (I != g_symbols().end())
     return I->second;
 
   // Now search the libraries.




From isanbard at gmail.com  Wed Jan 28 23:27:32 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 29 Jan 2009 05:27:32 -0000
Subject: [llvm-commits] [llvm] r63273 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAG.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp utils/TableGen/DAGISelEmitter.cpp
Message-ID: <200901290527.n0T5RWdv006714@zion.cs.uiuc.edu>

Author: void
Date: Wed Jan 28 23:27:31 2009
New Revision: 63273

URL: http://llvm.org/viewvc/llvm-project?rev=63273&view=rev
Log:
- Add DebugLoc to getTargetNode(). 
- Modify TableGen to add the DebugLoc when calling getTargetNode.

(The light-weight wrappers are only temporary. The non-DebugLoc version will be
removed once the whole debug info stuff is finished with.)

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/utils/TableGen/DAGISelEmitter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63273&r1=63272&r2=63273&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Jan 28 23:27:31 2009
@@ -699,72 +699,60 @@
   /// node of the specified opcode and operands, it returns that node instead of
   /// the current one.
   SDNode *getTargetNode(unsigned Opcode, MVT VT);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT);
-
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT);
   SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1);
-
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue Op1);
   SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1, SDValue Op2);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1, 
-                        SDValue Op2);
-
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT,
+                        SDValue Op1, SDValue Op2);
   SDNode *getTargetNode(unsigned Opcode, MVT VT,
                         SDValue Op1, SDValue Op2, SDValue Op3);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT,
                         SDValue Op1, SDValue Op2, SDValue Op3);
-
   SDNode *getTargetNode(unsigned Opcode, MVT VT,
                         const SDValue *Ops, unsigned NumOps);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT,
                         const SDValue *Ops, unsigned NumOps);
-
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2);
-
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1, MVT VT2);
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDValue Op1);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, 
-                        SDValue Op1);
-
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1,
+                        MVT VT2, SDValue Op1);
   SDNode *getTargetNode(unsigned Opcode, MVT VT1,
                         MVT VT2, SDValue Op1, SDValue Op2);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1,
                         MVT VT2, SDValue Op1, SDValue Op2);
-
   SDNode *getTargetNode(unsigned Opcode, MVT VT1,
                         MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1,
                         MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
-
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
                         const SDValue *Ops, unsigned NumOps);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2,
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1, MVT VT2,
                         const SDValue *Ops, unsigned NumOps);
-
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
                         SDValue Op1, SDValue Op2);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL,
+                        MVT VT1, MVT VT2, MVT VT3,
                         SDValue Op1, SDValue Op2);
-
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
                         SDValue Op1, SDValue Op2, SDValue Op3);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1, MVT VT2, MVT VT3,
                         SDValue Op1, SDValue Op2, SDValue Op3);
-
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
                         const SDValue *Ops, unsigned NumOps);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1, MVT VT2, MVT VT3,
                         const SDValue *Ops, unsigned NumOps);
-
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, MVT VT4,
                         const SDValue *Ops, unsigned NumOps);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
-                        MVT VT4, const SDValue *Ops, unsigned NumOps);
-
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL,
+                        MVT VT1, MVT VT2, MVT VT3, MVT VT4,
+                        const SDValue *Ops, unsigned NumOps);
   SDNode *getTargetNode(unsigned Opcode, const std::vector &ResultTys,
                         const SDValue *Ops, unsigned NumOps);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl,
-                        const std::vector &ResultTys, const SDValue *Ops,
-                        unsigned NumOps);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL,
+                        const std::vector &ResultTys,
+                        const SDValue *Ops, unsigned NumOps);
 
   /// getNodeIfExists - Get the specified node if it's already available, or
   /// else return NULL.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63273&r1=63272&r2=63273&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jan 28 23:27:31 2009
@@ -4747,169 +4747,142 @@
 /// node of the specified opcode and operands, it returns that node instead of
 /// the current one.
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) {
-  return getNode(~Opcode, VT).getNode();
+  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT);
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) {
-  return getNode(~Opcode, dl, VT).getNode();
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT) {
+  return getNode(~Opcode, DL, VT).getNode();
 }
-
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) {
-  return getNode(~Opcode, VT, Op1).getNode();
+  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT, Op1);
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
-                                    SDValue Op1) {
-  return getNode(~Opcode, dl, VT, Op1).getNode();
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
+                                    MVT VT, SDValue Op1) {
+  return getNode(~Opcode, DL, VT, Op1).getNode();
 }
-
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
                                     SDValue Op1, SDValue Op2) {
-  return getNode(~Opcode, VT, Op1, Op2).getNode();
+  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT, Op1, Op2);
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT,
                                     SDValue Op1, SDValue Op2) {
-  return getNode(~Opcode, dl, VT, Op1, Op2).getNode();
+  return getNode(~Opcode, DL, VT, Op1, Op2).getNode();
 }
-
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
-                                    SDValue Op1, SDValue Op2,
-                                    SDValue Op3) {
-  return getNode(~Opcode, VT, Op1, Op2, Op3).getNode();
-}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
-                                    SDValue Op1, SDValue Op2,
-                                    SDValue Op3) {
-  return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode();
+                                    SDValue Op1, SDValue Op2, SDValue Op3) {
+  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT, Op1, Op2, Op3);
+}
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT,
+                                    SDValue Op1, SDValue Op2, SDValue Op3) {
+  return getNode(~Opcode, DL, VT, Op1, Op2, Op3).getNode();
 }
-
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
                                     const SDValue *Ops, unsigned NumOps) {
-  return getNode(~Opcode, VT, Ops, NumOps).getNode();
+  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT, Ops, NumOps);
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT,
                                     const SDValue *Ops, unsigned NumOps) {
-  return getNode(~Opcode, dl, VT, Ops, NumOps).getNode();
+  return getNode(~Opcode, DL, VT, Ops, NumOps).getNode();
 }
-
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) {
-  const MVT *VTs = getNodeValueTypes(VT1, VT2);
-  SDValue Op;
-  return getNode(~Opcode, VTs, 2, &Op, 0).getNode();
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
+                                    MVT VT1, MVT VT2) {
+  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2);
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
                                     MVT VT1, MVT VT2) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2);
   SDValue Op;
-  return getNode(~Opcode, dl, VTs, 2, &Op, 0).getNode();
+  return getNode(~Opcode, DL, VTs, 2, &Op, 0).getNode();
 }
-
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
                                     MVT VT2, SDValue Op1) {
-  const MVT *VTs = getNodeValueTypes(VT1, VT2);
-  return getNode(~Opcode, VTs, 2, &Op1, 1).getNode();
+  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2, Op1);
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1,
                                     MVT VT2, SDValue Op1) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2);
-  return getNode(~Opcode, dl, VTs, 2, &Op1, 1).getNode();
+  return getNode(~Opcode, DL, VTs, 2, &Op1, 1).getNode();
 }
-
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
-                                    MVT VT2, SDValue Op1,
-                                    SDValue Op2) {
-  const MVT *VTs = getNodeValueTypes(VT1, VT2);
-  SDValue Ops[] = { Op1, Op2 };
-  return getNode(~Opcode, VTs, 2, Ops, 2).getNode();
+                                    MVT VT2, SDValue Op1, SDValue Op2) {
+  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2, Op1, Op2);
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
-                                    MVT VT2, SDValue Op1,
-                                    SDValue Op2) {
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1,
+                                    MVT VT2, SDValue Op1, SDValue Op2) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2);
   SDValue Ops[] = { Op1, Op2 };
-  return getNode(~Opcode, dl, VTs, 2, Ops, 2).getNode();
+  return getNode(~Opcode, DL, VTs, 2, Ops, 2).getNode();
 }
-
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
                                     MVT VT2, SDValue Op1,
                                     SDValue Op2, SDValue Op3) {
-  const MVT *VTs = getNodeValueTypes(VT1, VT2);
-  SDValue Ops[] = { Op1, Op2, Op3 };
-  return getNode(~Opcode, VTs, 2, Ops, 3).getNode();
+  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2,
+                       Op1, Op2, Op3);
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1,
                                     MVT VT2, SDValue Op1,
                                     SDValue Op2, SDValue Op3) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2);
   SDValue Ops[] = { Op1, Op2, Op3 };
-  return getNode(~Opcode, dl, VTs, 2, Ops, 3).getNode();
+  return getNode(~Opcode, DL, VTs, 2, Ops, 3).getNode();
 }
-
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
+                                    MVT VT1, MVT VT2,
                                     const SDValue *Ops, unsigned NumOps) {
-  const MVT *VTs = getNodeValueTypes(VT1, VT2);
-  return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode();
+  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2,
+                       Ops, NumOps);
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
                                     MVT VT1, MVT VT2,
                                     const SDValue *Ops, unsigned NumOps) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2);
-  return getNode(~Opcode, dl, VTs, 2, Ops, NumOps).getNode();
+  return getNode(~Opcode, DL, VTs, 2, Ops, NumOps).getNode();
 }
-
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
+                                    MVT VT1, MVT VT2, MVT VT3,
                                     SDValue Op1, SDValue Op2) {
-  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
-  SDValue Ops[] = { Op1, Op2 };
-  return getNode(~Opcode, VTs, 3, Ops, 2).getNode();
+  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2, VT3,
+                       Op1, Op2);
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
                                     MVT VT1, MVT VT2, MVT VT3,
                                     SDValue Op1, SDValue Op2) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
   SDValue Ops[] = { Op1, Op2 };
-  return getNode(~Opcode, dl, VTs, 3, Ops, 2).getNode();
+  return getNode(~Opcode, DL, VTs, 3, Ops, 2).getNode();
 }
-
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
-                                    SDValue Op1, SDValue Op2,
-                                    SDValue Op3) {
-  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
-  SDValue Ops[] = { Op1, Op2, Op3 };
-  return getNode(~Opcode, VTs, 3, Ops, 3).getNode();
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
+                                    MVT VT1, MVT VT2, MVT VT3,
+                                    SDValue Op1, SDValue Op2, SDValue Op3) {
+  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2, VT3,
+                       Op1, Op2, Op3);
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
                                     MVT VT1, MVT VT2, MVT VT3,
-                                    SDValue Op1, SDValue Op2,
-                                    SDValue Op3) {
+                                    SDValue Op1, SDValue Op2, SDValue Op3) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
   SDValue Ops[] = { Op1, Op2, Op3 };
-  return getNode(~Opcode, dl, VTs, 3, Ops, 3).getNode();
+  return getNode(~Opcode, DL, VTs, 3, Ops, 3).getNode();
 }
-
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
+                                    MVT VT1, MVT VT2, MVT VT3,
                                     const SDValue *Ops, unsigned NumOps) {
-  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
-  return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
+  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2, VT3,
+                       Ops, NumOps);
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
                                     MVT VT1, MVT VT2, MVT VT3,
                                     const SDValue *Ops, unsigned NumOps) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
-  return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
+  return getNode(~Opcode, DL, VTs, 3, Ops, NumOps).getNode();
 }
-
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
-                                    MVT VT2, MVT VT3, MVT VT4,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
+                                    MVT VT1, MVT VT2, MVT VT3, MVT VT4,
                                     const SDValue *Ops, unsigned NumOps) {
-  std::vector VTList;
-  VTList.push_back(VT1);
-  VTList.push_back(VT2);
-  VTList.push_back(VT3);
-  VTList.push_back(VT4);
-  const MVT *VTs = getNodeValueTypes(VTList);
-  return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode();
+  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(),
+                       VT1, VT2, VT3, VT4, Ops, NumOps);
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
-                                    MVT VT2, MVT VT3, MVT VT4,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
+                                    MVT VT1, MVT VT2, MVT VT3, MVT VT4,
                                     const SDValue *Ops, unsigned NumOps) {
   std::vector VTList;
   VTList.push_back(VT1);
@@ -4917,21 +4890,19 @@
   VTList.push_back(VT3);
   VTList.push_back(VT4);
   const MVT *VTs = getNodeValueTypes(VTList);
-  return getNode(~Opcode, dl, VTs, 4, Ops, NumOps).getNode();
+  return getNode(~Opcode, DL, VTs, 4, Ops, NumOps).getNode();
 }
-
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
                                     const std::vector &ResultTys,
                                     const SDValue *Ops, unsigned NumOps) {
-  const MVT *VTs = getNodeValueTypes(ResultTys);
-  return getNode(~Opcode, VTs, ResultTys.size(),
-                 Ops, NumOps).getNode();
+  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(),
+                       ResultTys, Ops, NumOps);
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
                                     const std::vector &ResultTys,
                                     const SDValue *Ops, unsigned NumOps) {
   const MVT *VTs = getNodeValueTypes(ResultTys);
-  return getNode(~Opcode, dl, VTs, ResultTys.size(),
+  return getNode(~Opcode, DL, VTs, ResultTys.size(),
                  Ops, NumOps).getNode();
 }
 

Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=63273&r1=63272&r2=63273&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Wed Jan 28 23:27:31 2009
@@ -1059,6 +1059,9 @@
 
       std::string Code = "Opc" + utostr(OpcNo);
 
+      if (!isRoot || (InputHasChain && !NodeHasChain))
+        Code += ", N.getDebugLoc()";
+
       emitOpcode(II.Namespace + "::" + II.TheDef->getName());
 
       // Output order: results, chain, flags




From resistor at mac.com  Wed Jan 28 23:28:55 2009
From: resistor at mac.com (Owen Anderson)
Date: Thu, 29 Jan 2009 05:28:55 -0000
Subject: [llvm-commits] [llvm] r63274 -
	/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
Message-ID: <200901290528.n0T5SthK006829@zion.cs.uiuc.edu>

Author: resistor
Date: Wed Jan 28 23:28:55 2009
New Revision: 63274

URL: http://llvm.org/viewvc/llvm-project?rev=63274&view=rev
Log:
Add support for aggressive load-use-store folding.  This takes care of the 
vast majority of code size regressions introduced by pre-alloc-splitting.

Modified:
    llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp

Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=63274&r1=63273&r2=63274&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original)
+++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Wed Jan 28 23:28:55 2009
@@ -37,8 +37,9 @@
 using namespace llvm;
 
 static cl::opt PreSplitLimit("pre-split-limit", cl::init(-1), cl::Hidden);
+static cl::opt DeadSplitLimit("dead-split-limit", cl::init(-1), cl::Hidden);
 
-STATISTIC(NumTotalSplits, "Number of intervals split");
+STATISTIC(NumSplits, "Number of intervals split");
 STATISTIC(NumRemats, "Number of intervals split by rematerialization");
 STATISTIC(NumFolds, "Number of intervals split with spill folding");
 STATISTIC(NumRenumbers, "Number of intervals renumbered into new registers");
@@ -77,8 +78,6 @@
 
     // Def2SpillMap - A map from a def instruction index to spill index.
     DenseMap Def2SpillMap;
-    
-    unsigned NumSplits;
 
   public:
     static char ID;
@@ -162,8 +161,8 @@
     void RenumberValno(VNInfo* VN);
     void ReconstructLiveInterval(LiveInterval* LI);
     bool removeDeadSpills(SmallPtrSet& split);
-    unsigned getNumberOfSpills(SmallPtrSet& MIs,
-                               unsigned Reg, int FrameIndex);
+    unsigned getNumberOfNonSpills(SmallPtrSet& MIs,
+                               unsigned Reg, int FrameIndex, bool& TwoAddr);
     VNInfo* PerformPHIConstruction(MachineBasicBlock::iterator use,
                                    MachineBasicBlock* MBB,
                                    LiveInterval* LI,
@@ -789,6 +788,10 @@
     MO.setReg(NewVReg);
   }
   
+  // The renumbered vreg shares a stack slot with the old register.
+  if (IntervalSSMap.count(CurrLI->reg))
+    IntervalSSMap[NewVReg] = IntervalSSMap[CurrLI->reg];
+  
   NumRenumbers++;
 }
 
@@ -1042,19 +1045,24 @@
   return Change;
 }
 
-unsigned PreAllocSplitting::getNumberOfSpills(
+unsigned PreAllocSplitting::getNumberOfNonSpills(
                                   SmallPtrSet& MIs,
-                                  unsigned Reg, int FrameIndex) {
-  unsigned Spills = 0;
+                                  unsigned Reg, int FrameIndex,
+                                  bool& FeedsTwoAddr) {
+  unsigned NonSpills = 0;
   for (SmallPtrSet::iterator UI = MIs.begin(), UE = MIs.end();
-       UI != UI; ++UI) {
+       UI != UE; ++UI) {
     int StoreFrameIndex;
     unsigned StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
-    if (StoreVReg == Reg && StoreFrameIndex == FrameIndex)
-      Spills++;
+    if (StoreVReg != Reg || StoreFrameIndex != FrameIndex)
+      NonSpills++;
+    
+    int DefIdx = (*UI)->findRegisterDefOperandIdx(Reg);
+    if (DefIdx != -1 && (*UI)->isRegReDefinedByTwoAddr(DefIdx))
+      FeedsTwoAddr = true;
   }
   
-  return Spills;
+  return NonSpills;
 }
 
 /// removeDeadSpills - After doing splitting, filter through all intervals we've
@@ -1077,6 +1085,10 @@
     
     for (LiveInterval::vni_iterator VI = (*LI)->vni_begin(),
          VE = (*LI)->vni_end(); VI != VE; ++VI) {
+      
+      if (DeadSplitLimit != -1 && (int)NumDeadSpills == DeadSplitLimit) 
+        return changed;
+      
       VNInfo* CurrVN = *VI;
       if (CurrVN->hasPHIKill) continue;
       
@@ -1096,9 +1108,67 @@
         continue;
       }
       
-      unsigned SpillCount = getNumberOfSpills(VNUseCount[CurrVN],
-                                              (*LI)->reg, FrameIndex);
-      if (SpillCount != VNUseCount[CurrVN].size()) continue;
+      bool FeedsTwoAddr = false;
+      unsigned NonSpillCount = getNumberOfNonSpills(VNUseCount[CurrVN],
+                                                    (*LI)->reg, FrameIndex,
+                                                    FeedsTwoAddr);
+      
+      if (NonSpillCount == 1 && !FeedsTwoAddr) {
+        SmallPtrSet::iterator UI = VNUseCount[CurrVN].begin();
+        int StoreFrameIndex;
+        unsigned StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
+        while (UI != VNUseCount[CurrVN].end() &&
+               (StoreVReg == (*LI)->reg && StoreFrameIndex == FrameIndex)) {
+          ++UI;
+          if (UI != VNUseCount[CurrVN].end())
+            StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
+        }
+        
+        if (UI == VNUseCount[CurrVN].end()) continue;
+        
+        MachineInstr* use = *UI;
+        
+        int OpIdx = use->findRegisterUseOperandIdx((*LI)->reg, false);
+        if (OpIdx == -1) continue;
+
+        SmallVector Ops;
+        Ops.push_back(OpIdx);
+
+        if (!TII->canFoldMemoryOperand(use, Ops)) continue;
+
+        MachineInstr* NewMI =
+                          TII->foldMemoryOperand(*use->getParent()->getParent(),  
+                                                 use, Ops, FrameIndex);
+
+        if (!NewMI) continue;
+
+        LIs->RemoveMachineInstrFromMaps(DefMI);
+        LIs->ReplaceMachineInstrInMaps(use, NewMI);
+        (*LI)->removeValNo(CurrVN);
+
+        DefMI->eraseFromParent();
+        MachineBasicBlock* MBB = use->getParent();
+        NewMI = MBB->insert(MBB->erase(use), NewMI);
+        VNUseCount[CurrVN].erase(use);
+        
+        for (SmallPtrSet::iterator II = 
+             VNUseCount[CurrVN].begin(), IE = VNUseCount[CurrVN].end();
+             II != IE; ++II) {
+          LIs->RemoveMachineInstrFromMaps(*II);
+          (*II)->eraseFromParent();
+        }
+
+        for (DenseMap >::iterator
+             VI = VNUseCount.begin(), VE = VNUseCount.end(); VI != VE; ++VI)
+          if (VI->second.erase(use))
+            VI->second.insert(NewMI);
+
+        NumDeadSpills++;
+        changed = true;
+        continue;
+      }
+      
+      if (NonSpillCount) continue;
         
       for (SmallPtrSet::iterator UI = 
            VNUseCount[CurrVN].begin(), UE = VNUseCount[CurrVN].end();
@@ -1193,7 +1263,6 @@
   LSs    = &getAnalysis();
 
   bool MadeChange = false;
-  NumSplits = 0;
 
   // Make sure blocks are numbered in order.
   MF.RenumberBlocks();
@@ -1220,9 +1289,6 @@
   }
 
   MadeChange |= removeDeadSpills(Split);
-  
-  if (NumSplits)
-    NumTotalSplits += NumSplits;
 
   return MadeChange;
 }




From isanbard at gmail.com  Wed Jan 28 23:36:52 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 28 Jan 2009 21:36:52 -0800
Subject: [llvm-commits] [llvm] r63273 - in /llvm/trunk:
	include/llvm/CodeGen/SelectionDAG.h
	lib/CodeGen/SelectionDAG/SelectionDAG.cpp
	utils/TableGen/DAGISelEmitter.cpp
In-Reply-To: <200901290527.n0T5RWdv006714@zion.cs.uiuc.edu>
References: <200901290527.n0T5RWdv006714@zion.cs.uiuc.edu>
Message-ID: <81736F01-A8FA-45B3-85DB-3E33437760F3@gmail.com>

Crud! I didn't realize that this change was already checked in.

Sorry for stamping on that patch. :-(

-bw

On Jan 28, 2009, at 9:27 PM, Bill Wendling wrote:

> Author: void
> Date: Wed Jan 28 23:27:31 2009
> New Revision: 63273
>
> URL: http://llvm.org/viewvc/llvm-project?rev=63273&view=rev
> Log:
> - Add DebugLoc to getTargetNode().
> - Modify TableGen to add the DebugLoc when calling getTargetNode.
>
> (The light-weight wrappers are only temporary. The non-DebugLoc  
> version will be
> removed once the whole debug info stuff is finished with.)
>
> Modified:
>    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>    llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63273&r1=63272&r2=63273&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Jan 28  
> 23:27:31 2009
> @@ -699,72 +699,60 @@
>   /// node of the specified opcode and operands, it returns that  
> node instead of
>   /// the current one.
>   SDNode *getTargetNode(unsigned Opcode, MVT VT);
> -  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT);
> -
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT);
>   SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1);
> -  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,  
> SDValue Op1);
> -
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT,  
> SDValue Op1);
>   SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1,  
> SDValue Op2);
> -  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,  
> SDValue Op1,
> -                        SDValue Op2);
> -
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT,
> +                        SDValue Op1, SDValue Op2);
>   SDNode *getTargetNode(unsigned Opcode, MVT VT,
>                         SDValue Op1, SDValue Op2, SDValue Op3);
> -  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT,
>                         SDValue Op1, SDValue Op2, SDValue Op3);
> -
>   SDNode *getTargetNode(unsigned Opcode, MVT VT,
>                         const SDValue *Ops, unsigned NumOps);
> -  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT,
>                         const SDValue *Ops, unsigned NumOps);
> -
>   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2);
> -  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT  
> VT2);
> -
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1, MVT  
> VT2);
>   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDValue  
> Op1);
> -  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT  
> VT2,
> -                        SDValue Op1);
> -
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1,
> +                        MVT VT2, SDValue Op1);
>   SDNode *getTargetNode(unsigned Opcode, MVT VT1,
>                         MVT VT2, SDValue Op1, SDValue Op2);
> -  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1,
>                         MVT VT2, SDValue Op1, SDValue Op2);
> -
>   SDNode *getTargetNode(unsigned Opcode, MVT VT1,
>                         MVT VT2, SDValue Op1, SDValue Op2, SDValue  
> Op3);
> -  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1,
>                         MVT VT2, SDValue Op1, SDValue Op2, SDValue  
> Op3);
> -
>   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
>                         const SDValue *Ops, unsigned NumOps);
> -  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT  
> VT2,
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1, MVT  
> VT2,
>                         const SDValue *Ops, unsigned NumOps);
> -
>   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
>                         SDValue Op1, SDValue Op2);
> -  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT  
> VT2, MVT VT3,
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL,
> +                        MVT VT1, MVT VT2, MVT VT3,
>                         SDValue Op1, SDValue Op2);
> -
>   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
>                         SDValue Op1, SDValue Op2, SDValue Op3);
> -  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT  
> VT2, MVT VT3,
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1, MVT  
> VT2, MVT VT3,
>                         SDValue Op1, SDValue Op2, SDValue Op3);
> -
>   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
>                         const SDValue *Ops, unsigned NumOps);
> -  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT  
> VT2, MVT VT3,
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1, MVT  
> VT2, MVT VT3,
>                         const SDValue *Ops, unsigned NumOps);
> -
>   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,  
> MVT VT4,
>                         const SDValue *Ops, unsigned NumOps);
> -  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT  
> VT2, MVT VT3,
> -                        MVT VT4, const SDValue *Ops, unsigned  
> NumOps);
> -
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL,
> +                        MVT VT1, MVT VT2, MVT VT3, MVT VT4,
> +                        const SDValue *Ops, unsigned NumOps);
>   SDNode *getTargetNode(unsigned Opcode, const std::vector  
> &ResultTys,
>                         const SDValue *Ops, unsigned NumOps);
> -  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl,
> -                        const std::vector &ResultTys, const  
> SDValue *Ops,
> -                        unsigned NumOps);
> +  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL,
> +                        const std::vector &ResultTys,
> +                        const SDValue *Ops, unsigned NumOps);
>
>   /// getNodeIfExists - Get the specified node if it's already  
> available, or
>   /// else return NULL.
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63273&r1=63272&r2=63273&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jan 28  
> 23:27:31 2009
> @@ -4747,169 +4747,142 @@
> /// node of the specified opcode and operands, it returns that node  
> instead of
> /// the current one.
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) {
> -  return getNode(~Opcode, VT).getNode();
> +  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT);
> }
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,  
> MVT VT) {
> -  return getNode(~Opcode, dl, VT).getNode();
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,  
> MVT VT) {
> +  return getNode(~Opcode, DL, VT).getNode();
> }
> -
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue  
> Op1) {
> -  return getNode(~Opcode, VT, Op1).getNode();
> +  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT, Op1);
> }
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,  
> MVT VT,
> -                                    SDValue Op1) {
> -  return getNode(~Opcode, dl, VT, Op1).getNode();
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
> +                                    MVT VT, SDValue Op1) {
> +  return getNode(~Opcode, DL, VT, Op1).getNode();
> }
> -
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
>                                     SDValue Op1, SDValue Op2) {
> -  return getNode(~Opcode, VT, Op1, Op2).getNode();
> +  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT, Op1,  
> Op2);
> }
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,  
> MVT VT,
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,  
> MVT VT,
>                                     SDValue Op1, SDValue Op2) {
> -  return getNode(~Opcode, dl, VT, Op1, Op2).getNode();
> +  return getNode(~Opcode, DL, VT, Op1, Op2).getNode();
> }
> -
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
> -                                    SDValue Op1, SDValue Op2,
> -                                    SDValue Op3) {
> -  return getNode(~Opcode, VT, Op1, Op2, Op3).getNode();
> -}
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,  
> MVT VT,
> -                                    SDValue Op1, SDValue Op2,
> -                                    SDValue Op3) {
> -  return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode();
> +                                    SDValue Op1, SDValue Op2,  
> SDValue Op3) {
> +  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT, Op1,  
> Op2, Op3);
> +}
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,  
> MVT VT,
> +                                    SDValue Op1, SDValue Op2,  
> SDValue Op3) {
> +  return getNode(~Opcode, DL, VT, Op1, Op2, Op3).getNode();
> }
> -
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
> -  return getNode(~Opcode, VT, Ops, NumOps).getNode();
> +  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT, Ops,  
> NumOps);
> }
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,  
> MVT VT,
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,  
> MVT VT,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
> -  return getNode(~Opcode, dl, VT, Ops, NumOps).getNode();
> +  return getNode(~Opcode, DL, VT, Ops, NumOps).getNode();
> }
> -
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT  
> VT2) {
> -  const MVT *VTs = getNodeValueTypes(VT1, VT2);
> -  SDValue Op;
> -  return getNode(~Opcode, VTs, 2, &Op, 0).getNode();
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
> +                                    MVT VT1, MVT VT2) {
> +  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2);
> }
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
>                                     MVT VT1, MVT VT2) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2);
>   SDValue Op;
> -  return getNode(~Opcode, dl, VTs, 2, &Op, 0).getNode();
> +  return getNode(~Opcode, DL, VTs, 2, &Op, 0).getNode();
> }
> -
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>                                     MVT VT2, SDValue Op1) {
> -  const MVT *VTs = getNodeValueTypes(VT1, VT2);
> -  return getNode(~Opcode, VTs, 2, &Op1, 1).getNode();
> +  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2,  
> Op1);
> }
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,  
> MVT VT1,
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,  
> MVT VT1,
>                                     MVT VT2, SDValue Op1) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2);
> -  return getNode(~Opcode, dl, VTs, 2, &Op1, 1).getNode();
> +  return getNode(~Opcode, DL, VTs, 2, &Op1, 1).getNode();
> }
> -
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
> -                                    MVT VT2, SDValue Op1,
> -                                    SDValue Op2) {
> -  const MVT *VTs = getNodeValueTypes(VT1, VT2);
> -  SDValue Ops[] = { Op1, Op2 };
> -  return getNode(~Opcode, VTs, 2, Ops, 2).getNode();
> +                                    MVT VT2, SDValue Op1, SDValue  
> Op2) {
> +  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2,  
> Op1, Op2);
> }
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,  
> MVT VT1,
> -                                    MVT VT2, SDValue Op1,
> -                                    SDValue Op2) {
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,  
> MVT VT1,
> +                                    MVT VT2, SDValue Op1, SDValue  
> Op2) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2);
>   SDValue Ops[] = { Op1, Op2 };
> -  return getNode(~Opcode, dl, VTs, 2, Ops, 2).getNode();
> +  return getNode(~Opcode, DL, VTs, 2, Ops, 2).getNode();
> }
> -
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
>                                     MVT VT2, SDValue Op1,
>                                     SDValue Op2, SDValue Op3) {
> -  const MVT *VTs = getNodeValueTypes(VT1, VT2);
> -  SDValue Ops[] = { Op1, Op2, Op3 };
> -  return getNode(~Opcode, VTs, 2, Ops, 3).getNode();
> +  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2,
> +                       Op1, Op2, Op3);
> }
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,  
> MVT VT1,
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,  
> MVT VT1,
>                                     MVT VT2, SDValue Op1,
>                                     SDValue Op2, SDValue Op3) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2);
>   SDValue Ops[] = { Op1, Op2, Op3 };
> -  return getNode(~Opcode, dl, VTs, 2, Ops, 3).getNode();
> +  return getNode(~Opcode, DL, VTs, 2, Ops, 3).getNode();
> }
> -
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT  
> VT2,
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
> +                                    MVT VT1, MVT VT2,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
> -  const MVT *VTs = getNodeValueTypes(VT1, VT2);
> -  return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode();
> +  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2,
> +                       Ops, NumOps);
> }
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
>                                     MVT VT1, MVT VT2,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2);
> -  return getNode(~Opcode, dl, VTs, 2, Ops, NumOps).getNode();
> +  return getNode(~Opcode, DL, VTs, 2, Ops, NumOps).getNode();
> }
> -
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT  
> VT2, MVT VT3,
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
> +                                    MVT VT1, MVT VT2, MVT VT3,
>                                     SDValue Op1, SDValue Op2) {
> -  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
> -  SDValue Ops[] = { Op1, Op2 };
> -  return getNode(~Opcode, VTs, 3, Ops, 2).getNode();
> +  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2,  
> VT3,
> +                       Op1, Op2);
> }
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
>                                     MVT VT1, MVT VT2, MVT VT3,
>                                     SDValue Op1, SDValue Op2) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
>   SDValue Ops[] = { Op1, Op2 };
> -  return getNode(~Opcode, dl, VTs, 3, Ops, 2).getNode();
> +  return getNode(~Opcode, DL, VTs, 3, Ops, 2).getNode();
> }
> -
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT  
> VT2, MVT VT3,
> -                                    SDValue Op1, SDValue Op2,
> -                                    SDValue Op3) {
> -  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
> -  SDValue Ops[] = { Op1, Op2, Op3 };
> -  return getNode(~Opcode, VTs, 3, Ops, 3).getNode();
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
> +                                    MVT VT1, MVT VT2, MVT VT3,
> +                                    SDValue Op1, SDValue Op2,  
> SDValue Op3) {
> +  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2,  
> VT3,
> +                       Op1, Op2, Op3);
> }
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
>                                     MVT VT1, MVT VT2, MVT VT3,
> -                                    SDValue Op1, SDValue Op2,
> -                                    SDValue Op3) {
> +                                    SDValue Op1, SDValue Op2,  
> SDValue Op3) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
>   SDValue Ops[] = { Op1, Op2, Op3 };
> -  return getNode(~Opcode, dl, VTs, 3, Ops, 3).getNode();
> +  return getNode(~Opcode, DL, VTs, 3, Ops, 3).getNode();
> }
> -
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT  
> VT2, MVT VT3,
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
> +                                    MVT VT1, MVT VT2, MVT VT3,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
> -  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
> -  return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
> +  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2,  
> VT3,
> +                       Ops, NumOps);
> }
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
>                                     MVT VT1, MVT VT2, MVT VT3,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
>   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
> -  return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
> +  return getNode(~Opcode, DL, VTs, 3, Ops, NumOps).getNode();
> }
> -
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
> -                                    MVT VT2, MVT VT3, MVT VT4,
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
> +                                    MVT VT1, MVT VT2, MVT VT3, MVT  
> VT4,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
> -  std::vector VTList;
> -  VTList.push_back(VT1);
> -  VTList.push_back(VT2);
> -  VTList.push_back(VT3);
> -  VTList.push_back(VT4);
> -  const MVT *VTs = getNodeValueTypes(VTList);
> -  return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode();
> +  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(),
> +                       VT1, VT2, VT3, VT4, Ops, NumOps);
> }
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,  
> MVT VT1,
> -                                    MVT VT2, MVT VT3, MVT VT4,
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
> +                                    MVT VT1, MVT VT2, MVT VT3, MVT  
> VT4,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
>   std::vector VTList;
>   VTList.push_back(VT1);
> @@ -4917,21 +4890,19 @@
>   VTList.push_back(VT3);
>   VTList.push_back(VT4);
>   const MVT *VTs = getNodeValueTypes(VTList);
> -  return getNode(~Opcode, dl, VTs, 4, Ops, NumOps).getNode();
> +  return getNode(~Opcode, DL, VTs, 4, Ops, NumOps).getNode();
> }
> -
> SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
>                                     const std::vector &ResultTys,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
> -  const MVT *VTs = getNodeValueTypes(ResultTys);
> -  return getNode(~Opcode, VTs, ResultTys.size(),
> -                 Ops, NumOps).getNode();
> +  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(),
> +                       ResultTys, Ops, NumOps);
> }
> -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
> +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
>                                     const std::vector &ResultTys,
>                                     const SDValue *Ops, unsigned  
> NumOps) {
>   const MVT *VTs = getNodeValueTypes(ResultTys);
> -  return getNode(~Opcode, dl, VTs, ResultTys.size(),
> +  return getNode(~Opcode, DL, VTs, ResultTys.size(),
>                  Ops, NumOps).getNode();
> }
>
>
> Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=63273&r1=63272&r2=63273&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Wed Jan 28 23:27:31  
> 2009
> @@ -1059,6 +1059,9 @@
>
>       std::string Code = "Opc" + utostr(OpcNo);
>
> +      if (!isRoot || (InputHasChain && !NodeHasChain))
> +        Code += ", N.getDebugLoc()";
> +
>       emitOpcode(II.Namespace + "::" + II.TheDef->getName());
>
>       // Output order: results, chain, flags
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From resistor at mac.com  Wed Jan 28 23:41:02 2009
From: resistor at mac.com (Owen Anderson)
Date: Thu, 29 Jan 2009 05:41:02 -0000
Subject: [llvm-commits] [llvm] r63276 -
	/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
Message-ID: <200901290541.n0T5f2Ww007321@zion.cs.uiuc.edu>

Author: resistor
Date: Wed Jan 28 23:41:02 2009
New Revision: 63276

URL: http://llvm.org/viewvc/llvm-project?rev=63276&view=rev
Log:
Comments are good. :-)

Modified:
    llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp

Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=63276&r1=63275&r2=63276&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original)
+++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Wed Jan 28 23:41:02 2009
@@ -1070,10 +1070,14 @@
 bool PreAllocSplitting::removeDeadSpills(SmallPtrSet& split) {
   bool changed = false;
   
+  // Walk over all of the live intervals that were touched by the splitter,
+  // and see if we can do any DCE and/or folding.
   for (SmallPtrSet::iterator LI = split.begin(),
        LE = split.end(); LI != LE; ++LI) {
     DenseMap > VNUseCount;
     
+    // First, collect all the uses of the vreg, and sort them by their
+    // reaching definition (VNInfo).
     for (MachineRegisterInfo::use_iterator UI = MRI->use_begin((*LI)->reg),
          UE = MRI->use_end(); UI != UE; ++UI) {
       unsigned index = LIs->getInstructionIndex(&*UI);
@@ -1083,6 +1087,8 @@
       VNUseCount[LR->valno].insert(&*UI);
     }
     
+    // Now, take the definitions (VNInfo's) one at a time and try to DCE 
+    // and/or fold them away.
     for (LiveInterval::vni_iterator VI = (*LI)->vni_begin(),
          VE = (*LI)->vni_end(); VI != VE; ++VI) {
       
@@ -1090,15 +1096,24 @@
         return changed;
       
       VNInfo* CurrVN = *VI;
+      
+      // We don't currently try to handle definitions with PHI kills, because
+      // it would involve processing more than one VNInfo at once.
       if (CurrVN->hasPHIKill) continue;
       
+      // We also don't try to handle the results of PHI joins, since there's
+      // no defining instruction to analyze.
       unsigned DefIdx = CurrVN->def;
       if (DefIdx == ~0U || DefIdx == ~1U) continue;
     
+      // We're only interested in eliminating cruft introduced by the splitter,
+      // is of the form load-use or load-use-store.  First, check that the
+      // definition is a load, and remember what stack slot we loaded it from.
       MachineInstr* DefMI = LIs->getInstructionFromIndex(DefIdx);
       int FrameIndex;
       if (!TII->isLoadFromStackSlot(DefMI, FrameIndex)) continue;
       
+      // If the definition has no uses at all, just DCE it.
       if (VNUseCount[CurrVN].size() == 0) {
         LIs->RemoveMachineInstrFromMaps(DefMI);
         (*LI)->removeValNo(CurrVN);
@@ -1108,12 +1123,17 @@
         continue;
       }
       
+      // Second, get the number of non-store uses of the definition, as well as
+      // a flag indicating whether it feeds into a later two-address definition.
       bool FeedsTwoAddr = false;
       unsigned NonSpillCount = getNumberOfNonSpills(VNUseCount[CurrVN],
                                                     (*LI)->reg, FrameIndex,
                                                     FeedsTwoAddr);
       
+      // If there's one non-store use and it doesn't feed a two-addr, then
+      // this is a load-use-store case that we can try to fold.
       if (NonSpillCount == 1 && !FeedsTwoAddr) {
+        // Start by finding the non-store use MachineInstr.
         SmallPtrSet::iterator UI = VNUseCount[CurrVN].begin();
         int StoreFrameIndex;
         unsigned StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
@@ -1123,17 +1143,15 @@
           if (UI != VNUseCount[CurrVN].end())
             StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
         }
-        
         if (UI == VNUseCount[CurrVN].end()) continue;
         
         MachineInstr* use = *UI;
         
+        // Attempt to fold it away!
         int OpIdx = use->findRegisterUseOperandIdx((*LI)->reg, false);
         if (OpIdx == -1) continue;
-
         SmallVector Ops;
         Ops.push_back(OpIdx);
-
         if (!TII->canFoldMemoryOperand(use, Ops)) continue;
 
         MachineInstr* NewMI =
@@ -1142,6 +1160,7 @@
 
         if (!NewMI) continue;
 
+        // Update relevant analyses.
         LIs->RemoveMachineInstrFromMaps(DefMI);
         LIs->ReplaceMachineInstrInMaps(use, NewMI);
         (*LI)->removeValNo(CurrVN);
@@ -1151,9 +1170,14 @@
         NewMI = MBB->insert(MBB->erase(use), NewMI);
         VNUseCount[CurrVN].erase(use);
         
+        // Remove deleted instructions.  Note that we need to remove them from 
+        // the VNInfo->use map as well, just to be safe.
         for (SmallPtrSet::iterator II = 
              VNUseCount[CurrVN].begin(), IE = VNUseCount[CurrVN].end();
              II != IE; ++II) {
+          for (DenseMap >::iterator
+               VI = VNUseCount.begin(), VE = VNUseCount.end(); VI != VE; ++VI)
+            VI->second.erase(*II);
           LIs->RemoveMachineInstrFromMaps(*II);
           (*II)->eraseFromParent();
         }
@@ -1168,8 +1192,11 @@
         continue;
       }
       
+      // If there's more than one non-store instruction, we can't profitably
+      // fold it, so bail.
       if (NonSpillCount) continue;
         
+      // Otherwise, this is a load-store case, so DCE them.
       for (SmallPtrSet::iterator UI = 
            VNUseCount[CurrVN].begin(), UE = VNUseCount[CurrVN].end();
            UI != UI; ++UI) {




From echeng at apple.com  Thu Jan 29 00:33:58 2009
From: echeng at apple.com (Evan Cheng)
Date: Wed, 28 Jan 2009 22:33:58 -0800
Subject: [llvm-commits] [llvm-gcc-4.2] r63076 - in
	/llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386-target.h
	llvm-backend.cpp
In-Reply-To: <200901270042.n0R0gBEq000456@zion.cs.uiuc.edu>
References: <200901270042.n0R0gBEq000456@zion.cs.uiuc.edu>
Message-ID: <6DC71425-DB85-4D65-A6A9-55EBB7A340FD@apple.com>

Hi Dan,

This seems to pass --disable-red-zone when target is i386. Obviously  
it causes no harm but it seems a bit strange. Is it intended?

Evan

On Jan 26, 2009, at 4:42 PM, Dan Gohman wrote:

> Author: djg
> Date: Mon Jan 26 18:42:11 2009
> New Revision: 63076
>
> URL: http://llvm.org/viewvc/llvm-project?rev=63076&view=rev
> Log:
> Translate GCC's -mno-red-zone option to LLVM's -disable-red-zone  
> option.
>
> Modified:
>    llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h
>    llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
>
> Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h
> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=63076&r1=63075&r2=63076&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h (original)
> +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Mon Jan 26  
> 18:42:11 2009
> @@ -89,6 +89,10 @@
>     }                                                           \
>   }
>
> +#define LLVM_SET_ARCH_OPTIONS(argvec)                           \
> +  if (TARGET_NO_RED_ZONE)                                       \
> +    argvec.push_back("--disable-red-zone");
> +
> #ifdef LLVM_ABI_H
>
> /* On x86-32 objects containing SSE vectors are 16 byte aligned,  
> everything
>
> Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=63076&r1=63075&r2=63076&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
> +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Mon Jan 26 18:42:11 2009
> @@ -131,6 +131,9 @@
>
>   // Allow targets to specify PIC options and other stuff to the  
> corresponding
>   // LLVM backends.
> +#ifdef LLVM_SET_ARCH_OPTIONS
> +  LLVM_SET_ARCH_OPTIONS(Args);
> +#endif
> #ifdef LLVM_SET_TARGET_OPTIONS
>   LLVM_SET_TARGET_OPTIONS(Args);
> #endif
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From sabre at nondot.org  Thu Jan 29 01:30:04 2009
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 29 Jan 2009 07:30:04 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63284 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Message-ID: <200901290730.n0T7U4R5011644@zion.cs.uiuc.edu>

Author: lattner
Date: Thu Jan 29 01:30:03 2009
New Revision: 63284

URL: http://llvm.org/viewvc/llvm-project?rev=63284&view=rev
Log:
a field being packed doesn't affect its alignment as far as lvalue 
computation is concerned, just its offset from the start of the struct.

A packed field or any other field with 1-byte alignment is just 
MinAlign(base, offset) like anything else.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=63284&r1=63283&r2=63284&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Thu Jan 29 01:30:03 2009
@@ -6090,7 +6090,7 @@
 LValue TreeToLLVM::EmitLV_COMPONENT_REF(tree exp) {
   LValue StructAddrLV = EmitLV(TREE_OPERAND(exp, 0));
   tree FieldDecl = TREE_OPERAND(exp, 1); 
-  unsigned LVAlign = DECL_PACKED(FieldDecl) ? 1 : StructAddrLV.Alignment;
+  unsigned LVAlign = StructAddrLV.Alignment;
  
   assert((TREE_CODE(DECL_CONTEXT(FieldDecl)) == RECORD_TYPE ||
           TREE_CODE(DECL_CONTEXT(FieldDecl)) == UNION_TYPE  ||
@@ -6128,6 +6128,9 @@
       const StructLayout *SL = TD.getStructLayout(cast(StructTy));
       unsigned Offset = SL->getElementOffset(MemberIndex);
       BitStart -= Offset * 8;
+      
+      // If the base is known to be 8-byte aligned, and we're adding a 4-byte
+      // offset, the field is known to be 4-byte aligned.
       LVAlign = MinAlign(LVAlign, Offset);
     }
     
@@ -6214,6 +6217,8 @@
       Offset = Builder.CreateAdd(Offset,
         ConstantInt::get(Offset->getType(), ByteOffset));
       BitStart -= ByteOffset*8;
+      // If the base is known to be 8-byte aligned, and we're adding a 4-byte
+      // offset, the field is known to be 4-byte aligned.
       LVAlign = MinAlign(LVAlign, ByteOffset);
     }
 




From sabre at nondot.org  Thu Jan 29 01:40:14 2009
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 29 Jan 2009 07:40:14 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63287 - in /llvm-gcc-4.2/trunk/gcc:
 llvm-convert.cpp llvm-internal.h
Message-ID: <200901290740.n0T7eE4V012033@zion.cs.uiuc.edu>

Author: lattner
Date: Thu Jan 29 01:40:14 2009
New Revision: 63287

URL: http://llvm.org/viewvc/llvm-project?rev=63287&view=rev
Log:
move field annotation out to its own helper method.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
    llvm-gcc-4.2/trunk/gcc/llvm-internal.h

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=63287&r1=63286&r2=63287&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Thu Jan 29 01:40:14 2009
@@ -6087,6 +6087,70 @@
   return Result;
 }
 
+Value *TreeToLLVM::EmitFieldAnnotation(Value *FieldPtr, tree FieldDecl) {
+  tree AnnotateAttr = lookup_attribute("annotate", DECL_ATTRIBUTES(FieldDecl));
+
+  const Type *OrigPtrTy = FieldPtr->getType();
+  const Type *SBP = PointerType::getUnqual(Type::Int8Ty);
+  
+  Function *Fn = Intrinsic::getDeclaration(TheModule, 
+                                           Intrinsic::ptr_annotation,
+                                           &SBP, 1);
+  
+  // Get file and line number.  FIXME: Should this be for the decl or the
+  // use.  Is there a location info for the use?
+  Constant *LineNo = ConstantInt::get(Type::Int32Ty,
+                                      DECL_SOURCE_LINE(FieldDecl));
+  Constant *File = ConvertMetadataStringToGV(DECL_SOURCE_FILE(FieldDecl));
+  
+  File = TheFolder->CreateBitCast(File, SBP);
+  
+  // There may be multiple annotate attributes. Pass return of lookup_attr 
+  //  to successive lookups.
+  while (AnnotateAttr) {
+    // Each annotate attribute is a tree list.
+    // Get value of list which is our linked list of args.
+    tree args = TREE_VALUE(AnnotateAttr);
+    
+    // Each annotate attribute may have multiple args.
+    // Treat each arg as if it were a separate annotate attribute.
+    for (tree a = args; a; a = TREE_CHAIN(a)) {
+      // Each element of the arg list is a tree list, so get value
+      tree val = TREE_VALUE(a);
+      
+      // Assert its a string, and then get that string.
+      assert(TREE_CODE(val) == STRING_CST &&
+             "Annotate attribute arg should always be a string");
+      
+      Constant *strGV = TreeConstantToLLVM::EmitLV_STRING_CST(val);
+      
+      // We can not use the IRBuilder because it will constant fold away
+      // the GEP that is critical to distinguish between an annotate 
+      // attribute on a whole struct from one on the first element of the
+      // struct.
+      BitCastInst *CastFieldPtr = new BitCastInst(FieldPtr,  SBP, 
+                                                  FieldPtr->getNameStart());
+      Builder.Insert(CastFieldPtr);
+      
+      Value *Ops[4] = {
+        CastFieldPtr, BitCastToType(strGV, SBP), 
+        File,  LineNo
+      };
+      
+      const Type* FieldPtrType = FieldPtr->getType();
+      FieldPtr = Builder.CreateCall(Fn, Ops, Ops+4);
+      FieldPtr = BitCastToType(FieldPtr, FieldPtrType);
+    }
+    
+    // Get next annotate attribute.
+    AnnotateAttr = TREE_CHAIN(AnnotateAttr);
+    if (AnnotateAttr)
+      AnnotateAttr = lookup_attribute("annotate", AnnotateAttr);
+  }
+  return FieldPtr;
+}
+
+
 LValue TreeToLLVM::EmitLV_COMPONENT_REF(tree exp) {
   LValue StructAddrLV = EmitLV(TREE_OPERAND(exp, 0));
   tree FieldDecl = TREE_OPERAND(exp, 1); 
@@ -6137,67 +6201,8 @@
     // If the FIELD_DECL has an annotate attribute on it, emit it.
     
     // Handle annotate attribute on global.
-    if (tree AnnotateAttr = 
-        lookup_attribute("annotate", DECL_ATTRIBUTES(FieldDecl))) {
-      
-      const Type *OrigPtrTy = FieldPtr->getType();
-      const Type *SBP = PointerType::getUnqual(Type::Int8Ty);
-      
-      Function *Fn = Intrinsic::getDeclaration(TheModule, 
-                                               Intrinsic::ptr_annotation,
-                                               &SBP, 1);
-      
-      // Get file and line number.  FIXME: Should this be for the decl or the
-      // use.  Is there a location info for the use?
-      Constant *LineNo = ConstantInt::get(Type::Int32Ty,
-                                          DECL_SOURCE_LINE(FieldDecl));
-      Constant *File = ConvertMetadataStringToGV(DECL_SOURCE_FILE(FieldDecl));
-      
-      File = TheFolder->CreateBitCast(File, SBP);
-      
-      // There may be multiple annotate attributes. Pass return of lookup_attr 
-      //  to successive lookups.
-      while (AnnotateAttr) {
-        // Each annotate attribute is a tree list.
-        // Get value of list which is our linked list of args.
-        tree args = TREE_VALUE(AnnotateAttr);
-        
-        // Each annotate attribute may have multiple args.
-        // Treat each arg as if it were a separate annotate attribute.
-        for (tree a = args; a; a = TREE_CHAIN(a)) {
-          // Each element of the arg list is a tree list, so get value
-          tree val = TREE_VALUE(a);
-          
-          // Assert its a string, and then get that string.
-          assert(TREE_CODE(val) == STRING_CST &&
-                 "Annotate attribute arg should always be a string");
-          
-          Constant *strGV = TreeConstantToLLVM::EmitLV_STRING_CST(val);
-          
-          // We can not use the IRBuilder because it will constant fold away
-          // the GEP that is critical to distinguish between an annotate 
-          // attribute on a whole struct from one on the first element of the
-          // struct.
-          BitCastInst *CastFieldPtr = new BitCastInst(FieldPtr,  SBP, 
-                                                      FieldPtr->getNameStart());
-          Builder.Insert(CastFieldPtr);
-          
-          Value *Ops[4] = {
-            CastFieldPtr, BitCastToType(strGV, SBP), 
-            File,  LineNo
-          };
-          
-          const Type* FieldPtrType = FieldPtr->getType();
-          FieldPtr = Builder.CreateCall(Fn, Ops, Ops+4);
-          FieldPtr = BitCastToType(FieldPtr, FieldPtrType);
-        }
-        
-        // Get next annotate attribute.
-        AnnotateAttr = TREE_CHAIN(AnnotateAttr);
-        if (AnnotateAttr)
-          AnnotateAttr = lookup_attribute("annotate", AnnotateAttr);
-      }
-    }
+    if (lookup_attribute("annotate", DECL_ATTRIBUTES(FieldDecl)))
+      FieldPtr = EmitFieldAnnotation(FieldPtr, FieldDecl);
   } else {
     Value *Offset = Emit(field_offset, 0);
 

Modified: llvm-gcc-4.2/trunk/gcc/llvm-internal.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-internal.h?rev=63287&r1=63286&r2=63287&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-internal.h (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-internal.h Thu Jan 29 01:40:14 2009
@@ -580,6 +580,7 @@
   LValue EmitLV_DECL(tree_node *exp);
   LValue EmitLV_ARRAY_REF(tree_node *exp);
   LValue EmitLV_COMPONENT_REF(tree_node *exp);
+  Value *EmitFieldAnnotation(Value *FieldPtr, tree_node *FieldDecl);
   LValue EmitLV_BIT_FIELD_REF(tree_node *exp);
   LValue EmitLV_XXXXPART_EXPR(tree_node *exp, unsigned Idx);
   LValue EmitLV_VIEW_CONVERT_EXPR(tree_node *exp);




From sabre at nondot.org  Thu Jan 29 01:50:02 2009
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 29 Jan 2009 07:50:02 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63288 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Message-ID: <200901290750.n0T7o2dO012355@zion.cs.uiuc.edu>

Author: lattner
Date: Thu Jan 29 01:50:02 2009
New Revision: 63288

URL: http://llvm.org/viewvc/llvm-project?rev=63288&view=rev
Log:
If a FIELD_DECL says its alignment is 16 bytes, and the base pointer
is only known to be 8-byte aligned, round up to 16 bytes.  I believe 
that this is always safe.  Duncan, I would appreciate the review.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=63288&r1=63287&r2=63288&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Thu Jan 29 01:50:02 2009
@@ -1161,7 +1161,7 @@
   // Constants.
   case LABEL_DECL: {
     Value *Ptr = TreeConstantToLLVM::EmitLV_LABEL_DECL(exp);
-    return LValue(Ptr, DECL_ALIGN(exp) / 8);
+    return LValue(Ptr, DECL_ALIGN_UNIT(exp));
   }
   case COMPLEX_CST: {
     Value *Ptr = TreeConstantToLLVM::EmitLV_COMPLEX_CST(exp);
@@ -6198,9 +6198,15 @@
       LVAlign = MinAlign(LVAlign, Offset);
     }
     
-    // If the FIELD_DECL has an annotate attribute on it, emit it.
+    // If this field is at a constant offset, if the LLVM pointer really points
+    // to it, then we know that the pointer is at least as aligned as the field
+    // is required to be.  Try to round up our alignment info.
+    if (BitStart == 0 && // llvm pointer points to it.
+        !isBitfield(FieldDecl) &&  // bitfield computation might offset pointer.
+        DECL_ALIGN_UNIT(FieldDecl))
+      LVAlign = std::max(LVAlign, unsigned(DECL_ALIGN_UNIT(FieldDecl)));
     
-    // Handle annotate attribute on global.
+    // If the FIELD_DECL has an annotate attribute on it, emit it.
     if (lookup_attribute("annotate", DECL_ATTRIBUTES(FieldDecl)))
       FieldPtr = EmitFieldAnnotation(FieldPtr, FieldDecl);
   } else {




From sabre at nondot.org  Thu Jan 29 01:54:43 2009
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 29 Jan 2009 07:54:43 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63289 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Message-ID: <200901290754.n0T7she9012551@zion.cs.uiuc.edu>

Author: lattner
Date: Thu Jan 29 01:54:43 2009
New Revision: 63289

URL: http://llvm.org/viewvc/llvm-project?rev=63289&view=rev
Log:
The alignment of an indirect ref is the expr_align of the indirect 
ref, not the pointer argument.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=63289&r1=63288&r2=63289&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Thu Jan 29 01:54:43 2009
@@ -1183,11 +1183,10 @@
   case WITH_SIZE_EXPR:
     // The address is the address of the operand.
     return EmitLV(TREE_OPERAND(exp, 0));
-  case INDIRECT_REF: {
+  case INDIRECT_REF:
     // The lvalue is just the address.
-    tree Op = TREE_OPERAND(exp, 0);
-    return LValue(Emit(Op, 0), expr_align(Op) / 8);
-  }
+    return LValue(Emit(TREE_OPERAND(exp, 0), 0),
+                  expr_align(exp) / 8);
   }
 }
 




From sabre at nondot.org  Thu Jan 29 01:55:27 2009
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 29 Jan 2009 07:55:27 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63290 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Message-ID: <200901290755.n0T7tR7q012589@zion.cs.uiuc.edu>

Author: lattner
Date: Thu Jan 29 01:55:27 2009
New Revision: 63290

URL: http://llvm.org/viewvc/llvm-project?rev=63290&view=rev
Log:
increase portability to systems that don't use 8-bit bytes!

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=63290&r1=63289&r2=63290&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Thu Jan 29 01:55:27 2009
@@ -1165,11 +1165,11 @@
   }
   case COMPLEX_CST: {
     Value *Ptr = TreeConstantToLLVM::EmitLV_COMPLEX_CST(exp);
-    return LValue(Ptr, TYPE_ALIGN(TREE_TYPE(exp)) / 8);
+    return LValue(Ptr, TYPE_ALIGN_UNIT(TREE_TYPE(exp)));
   }
   case STRING_CST: {
     Value *Ptr = TreeConstantToLLVM::EmitLV_STRING_CST(exp);
-    return LValue(Ptr, TYPE_ALIGN(TREE_TYPE(exp)) / 8);
+    return LValue(Ptr, TYPE_ALIGN_UNIT(TREE_TYPE(exp)));
   }
 
   // Type Conversion.




From baldrick at free.fr  Wed Jan 28 14:55:05 2009
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 28 Jan 2009 21:55:05 +0100
Subject: [llvm-commits] [llvm-gcc-4.2] r63109 - in
	/llvm-gcc-4.2/trunk/gcc: gimplify.c llvm-backend.cpp
	llvm-convert.cpp tree.h
In-Reply-To: <6E65104D-66C7-497F-A287-BD674D0ED8F9@apple.com>
References: <200901271810.n0RIAmiZ014379@zion.cs.uiuc.edu>
	<200901271948.23083.baldrick@free.fr>
	<6E65104D-66C7-497F-A287-BD674D0ED8F9@apple.com>
Message-ID: <200901282155.05966.baldrick@free.fr>

Hi Stuart, thanks for the explanation.  For what it's worth, the fix
looks correct to me.  However can you please put these kinds of details
in the commit message next time thanks.

Best wishes,

Duncan.

> >> Restoring DECL_LLVM_PRIVATE (rev 62850) with a patch to fix some  
> >> ObjC DejaGNU regressions.
> >
> > What was the fix and what was regressing?
> 
> In llvm-backend.cpp, I added the "CODE_CONTAINS_STRUCT" voodoo around  
> line 1085:
> 
> +  if (CODE_CONTAINS_STRUCT (TREE_CODE (decl), TS_DECL_WITH_VIS)
> +      && DECL_LLVM_PRIVATE(decl)) {
> 
> There were at least three ICEs in the ObjC DejaGNU tests:
> 
> FAIL: objc.dg/const-cfstring-6.m (test for excess errors)
> FAIL: objc.dg/pubtypes-id-test.m (test for excess errors)
> FAIL: obj-c++.dg/const-cfstring-6.mm (test for excess errors)
> 
> While the patch doesn't make all the tests pass, at least the ICE-ing  
> is gone.  (On my dev machine, the const-cfstring-6.{m,mm} tests now  
> fail with a linker error.)
> 
> > Thanks,
> 
> You're very welcome,
> 
> stuart
> 


From baldrick at free.fr  Thu Jan 29 02:10:01 2009
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 29 Jan 2009 08:10:01 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63291 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Message-ID: <200901290810.n0T8A1Ix013088@zion.cs.uiuc.edu>

Author: baldrick
Date: Thu Jan 29 02:10:01 2009
New Revision: 63291

URL: http://llvm.org/viewvc/llvm-project?rev=63291&view=rev
Log:
Better fix for FrontendC/implicit-arg.c.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=63291&r1=63290&r2=63291&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Thu Jan 29 02:10:01 2009
@@ -2821,7 +2821,7 @@
         const FunctionType *ActualFT =
           cast(ActualPT->getElementType());
         if (RealFT->getReturnType() == ActualFT->getReturnType() &&
-            ActualFT->getNumParams() == 0)
+            RealFT->getNumParams() == 0)
           Callee = RealCallee;
       }
     }
@@ -2829,21 +2829,6 @@
   
   Value *Call;
   if (!LandingPad) {
-    if (CallOperands.empty()) {
-      const FunctionType *FTy = cast
-        (cast(Callee->getType())->getElementType());
-      if (!FTy->isVarArg() && FTy->getNumParams() > 0) {
-        // Something like this:
-        // static int func2();
-        // void func1() {
-        //   int a = func2();
-        // }
-        // int func2(unsigned a) {
-        // }
-        // gcc4.2 allows this.
-        CallOperands.push_back(UndefValue::get(FTy->getParamType(0)));
-      }
-    }
     Call = Builder.CreateCall(Callee, CallOperands.begin(), CallOperands.end());
     cast(Call)->setCallingConv(CallingConvention);
     cast(Call)->setAttributes(PAL);




From resistor at mac.com  Thu Jan 29 02:22:06 2009
From: resistor at mac.com (Owen Anderson)
Date: Thu, 29 Jan 2009 08:22:06 -0000
Subject: [llvm-commits] [llvm] r63293 -
	/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
Message-ID: <200901290822.n0T8M63v013465@zion.cs.uiuc.edu>

Author: resistor
Date: Thu Jan 29 02:22:06 2009
New Revision: 63293

URL: http://llvm.org/viewvc/llvm-project?rev=63293&view=rev
Log:
Fix an issue where restores could be inserted after a terminator instruction,
and an iterator invalidation issue.

FreeBench/pifft no longer miscompiles with these fixes!

Modified:
    llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp

Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=63293&r1=63292&r2=63293&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original)
+++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Thu Jan 29 02:22:06 2009
@@ -277,7 +277,7 @@
     MII = ++MII;
     // FIXME: Limit the number of instructions to examine to reduce
     // compile time?
-    while (MII != MBB->end()) {
+    while (MII != MBB->getFirstTerminator()) {
       unsigned Index = LIs->getInstructionIndex(MII);
       if (Index > LastIdx)
         break;
@@ -486,7 +486,8 @@
            IncomingVNs.begin(), E = IncomingVNs.end(); I != E; ++I) {
         I->second->hasPHIKill = true;
         unsigned KillIndex = LIs->getMBBEndIdx(I->first);
-        LI->addKill(I->second, KillIndex);
+        if (!LiveInterval::isKill(I->second, KillIndex))
+          LI->addKill(I->second, KillIndex);
       }
       
       unsigned EndIndex = 0;
@@ -1118,6 +1119,7 @@
         LIs->RemoveMachineInstrFromMaps(DefMI);
         (*LI)->removeValNo(CurrVN);
         DefMI->eraseFromParent();
+        VNUseCount.erase(CurrVN);
         NumDeadSpills++;
         changed = true;
         continue;
@@ -1176,11 +1178,15 @@
              VNUseCount[CurrVN].begin(), IE = VNUseCount[CurrVN].end();
              II != IE; ++II) {
           for (DenseMap >::iterator
-               VI = VNUseCount.begin(), VE = VNUseCount.end(); VI != VE; ++VI)
-            VI->second.erase(*II);
+               VNI = VNUseCount.begin(), VNE = VNUseCount.end(); VNI != VNE; 
+               ++VNI)
+            if (VNI->first != CurrVN)
+              VNI->second.erase(*II);
           LIs->RemoveMachineInstrFromMaps(*II);
           (*II)->eraseFromParent();
         }
+        
+        VNUseCount.erase(CurrVN);
 
         for (DenseMap >::iterator
              VI = VNUseCount.begin(), VE = VNUseCount.end(); VI != VE; ++VI)
@@ -1204,6 +1210,8 @@
         (*UI)->eraseFromParent();
       }
         
+      VNUseCount.erase(CurrVN);
+        
       LIs->RemoveMachineInstrFromMaps(DefMI);
       (*LI)->removeValNo(CurrVN);
       DefMI->eraseFromParent();




From baldrick at free.fr  Thu Jan 29 02:40:46 2009
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 29 Jan 2009 09:40:46 +0100
Subject: [llvm-commits] [llvm] r63266 - in /llvm/trunk:
	include/llvm/Target/TargetLowering.h
	lib/CodeGen/SelectionDAG/DAGCombiner.cpp
	lib/CodeGen/SelectionDAG/TargetLowering.cpp
	lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/bt.ll
	test/CodeGen/X86/commute-cmov.ll
In-Reply-To: <200901290159.n0T1x25H032445@zion.cs.uiuc.edu>
References: <200901290159.n0T1x25H032445@zion.cs.uiuc.edu>
Message-ID: <200901290940.46887.baldrick@free.fr>

Hi Dan,

>    case ISD::SRA:
> +    // If this is an arithmetic shift right and only the low-bit is set, we can
> +    // always convert this into a logical shr, even if the shift amount is
> +    // variable.  The low bit of the shift cannot be an input sign bit unless
> +    // the shift amount is >= the size of the datatype, which is undefined.
> +    if (DemandedMask == 1)
> +      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, Op.getValueType(),
> +                                               Op.getOperand(0), Op.getOperand(1)));

is this correct for MVT::i1?

> +    // Simpify x&y == y to x&y == 0 if y has exactly one bit set.

Simpify -> Simplify.  Also, the transform described in the comment
looks wrong.  For example, suppose x==y.  Then the left version is
equivalent to x == x, while the right version is equivalent to x == 0.
 
Ciao,

Duncan.


From evan.cheng at apple.com  Thu Jan 29 02:59:47 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 29 Jan 2009 08:59:47 -0000
Subject: [llvm-commits] [llvm] r63300 -
	/llvm/trunk/test/FrontendC/union-align.c
Message-ID: <200901290859.n0T8xl0E021635@zion.cs.uiuc.edu>

Author: evancheng
Date: Thu Jan 29 02:59:46 2009
New Revision: 63300

URL: http://llvm.org/viewvc/llvm-project?rev=63300&view=rev
Log:
Add a test case for Chris lvalue alignment fixes.

Added:
    llvm/trunk/test/FrontendC/union-align.c

Added: llvm/trunk/test/FrontendC/union-align.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/union-align.c?rev=63300&view=auto

==============================================================================
--- llvm/trunk/test/FrontendC/union-align.c (added)
+++ llvm/trunk/test/FrontendC/union-align.c Thu Jan 29 02:59:46 2009
@@ -0,0 +1,17 @@
+// RUN: %llvmgcc -S %s -o - | grep load | grep "4 x float" | not grep "align 4"
+// RUN: %llvmgcc -S %s -o - | grep load | grep "4 x float" | grep "align 16"
+// PR3432
+// rdar://6536377
+
+typedef float __m128 __attribute__ ((__vector_size__ (16)));
+
+typedef union
+{
+  int i[4];
+  float f[4];
+  __m128 v;
+} u_t;
+
+__m128 t(u_t *a) {
+  return a->v;
+}




From isanbard at gmail.com  Thu Jan 29 03:01:55 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 29 Jan 2009 09:01:55 -0000
Subject: [llvm-commits] [llvm] r63301 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAG.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Message-ID: <200901290901.n0T91u37021979@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 03:01:55 2009
New Revision: 63301

URL: http://llvm.org/viewvc/llvm-project?rev=63301&view=rev
Log:
Revert r63273. This was already implemented by Dale. There's no need for my
change.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63301&r1=63300&r2=63301&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Thu Jan 29 03:01:55 2009
@@ -699,60 +699,72 @@
   /// node of the specified opcode and operands, it returns that node instead of
   /// the current one.
   SDNode *getTargetNode(unsigned Opcode, MVT VT);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue Op1);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1, SDValue Op2);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT,
-                        SDValue Op1, SDValue Op2);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1, 
+                        SDValue Op2);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT,
                         SDValue Op1, SDValue Op2, SDValue Op3);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT,
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
                         SDValue Op1, SDValue Op2, SDValue Op3);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT,
                         const SDValue *Ops, unsigned NumOps);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT,
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
                         const SDValue *Ops, unsigned NumOps);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1, MVT VT2);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDValue Op1);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1,
-                        MVT VT2, SDValue Op1);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, 
+                        SDValue Op1);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT1,
                         MVT VT2, SDValue Op1, SDValue Op2);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1,
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
                         MVT VT2, SDValue Op1, SDValue Op2);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT1,
                         MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1,
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
                         MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
                         const SDValue *Ops, unsigned NumOps);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1, MVT VT2,
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2,
                         const SDValue *Ops, unsigned NumOps);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
                         SDValue Op1, SDValue Op2);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL,
-                        MVT VT1, MVT VT2, MVT VT3,
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
                         SDValue Op1, SDValue Op2);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
                         SDValue Op1, SDValue Op2, SDValue Op3);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1, MVT VT2, MVT VT3,
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
                         SDValue Op1, SDValue Op2, SDValue Op3);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
                         const SDValue *Ops, unsigned NumOps);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1, MVT VT2, MVT VT3,
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
                         const SDValue *Ops, unsigned NumOps);
+
   SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, MVT VT4,
                         const SDValue *Ops, unsigned NumOps);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL,
-                        MVT VT1, MVT VT2, MVT VT3, MVT VT4,
-                        const SDValue *Ops, unsigned NumOps);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
+                        MVT VT4, const SDValue *Ops, unsigned NumOps);
+
   SDNode *getTargetNode(unsigned Opcode, const std::vector &ResultTys,
                         const SDValue *Ops, unsigned NumOps);
-  SDNode *getTargetNode(unsigned Opcode, DebugLoc DL,
-                        const std::vector &ResultTys,
-                        const SDValue *Ops, unsigned NumOps);
+  SDNode *getTargetNode(unsigned Opcode, DebugLoc dl,
+                        const std::vector &ResultTys, const SDValue *Ops,
+                        unsigned NumOps);
 
   /// getNodeIfExists - Get the specified node if it's already available, or
   /// else return NULL.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63301&r1=63300&r2=63301&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jan 29 03:01:55 2009
@@ -4747,142 +4747,169 @@
 /// node of the specified opcode and operands, it returns that node instead of
 /// the current one.
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) {
-  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT);
+  return getNode(~Opcode, VT).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT) {
-  return getNode(~Opcode, DL, VT).getNode();
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) {
+  return getNode(~Opcode, dl, VT).getNode();
 }
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) {
-  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT, Op1);
+  return getNode(~Opcode, VT, Op1).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
-                                    MVT VT, SDValue Op1) {
-  return getNode(~Opcode, DL, VT, Op1).getNode();
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+                                    SDValue Op1) {
+  return getNode(~Opcode, dl, VT, Op1).getNode();
 }
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
                                     SDValue Op1, SDValue Op2) {
-  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT, Op1, Op2);
+  return getNode(~Opcode, VT, Op1, Op2).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
                                     SDValue Op1, SDValue Op2) {
-  return getNode(~Opcode, DL, VT, Op1, Op2).getNode();
+  return getNode(~Opcode, dl, VT, Op1, Op2).getNode();
 }
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
-                                    SDValue Op1, SDValue Op2, SDValue Op3) {
-  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT, Op1, Op2, Op3);
-}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT,
-                                    SDValue Op1, SDValue Op2, SDValue Op3) {
-  return getNode(~Opcode, DL, VT, Op1, Op2, Op3).getNode();
+                                    SDValue Op1, SDValue Op2,
+                                    SDValue Op3) {
+  return getNode(~Opcode, VT, Op1, Op2, Op3).getNode();
+}
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+                                    SDValue Op1, SDValue Op2,
+                                    SDValue Op3) {
+  return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode();
 }
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
                                     const SDValue *Ops, unsigned NumOps) {
-  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT, Ops, NumOps);
+  return getNode(~Opcode, VT, Ops, NumOps).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
                                     const SDValue *Ops, unsigned NumOps) {
-  return getNode(~Opcode, DL, VT, Ops, NumOps).getNode();
+  return getNode(~Opcode, dl, VT, Ops, NumOps).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
-                                    MVT VT1, MVT VT2) {
-  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2);
+
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) {
+  const MVT *VTs = getNodeValueTypes(VT1, VT2);
+  SDValue Op;
+  return getNode(~Opcode, VTs, 2, &Op, 0).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 
                                     MVT VT1, MVT VT2) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2);
   SDValue Op;
-  return getNode(~Opcode, DL, VTs, 2, &Op, 0).getNode();
+  return getNode(~Opcode, dl, VTs, 2, &Op, 0).getNode();
 }
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
                                     MVT VT2, SDValue Op1) {
-  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2, Op1);
+  const MVT *VTs = getNodeValueTypes(VT1, VT2);
+  return getNode(~Opcode, VTs, 2, &Op1, 1).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
                                     MVT VT2, SDValue Op1) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2);
-  return getNode(~Opcode, DL, VTs, 2, &Op1, 1).getNode();
+  return getNode(~Opcode, dl, VTs, 2, &Op1, 1).getNode();
 }
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
-                                    MVT VT2, SDValue Op1, SDValue Op2) {
-  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2, Op1, Op2);
+                                    MVT VT2, SDValue Op1,
+                                    SDValue Op2) {
+  const MVT *VTs = getNodeValueTypes(VT1, VT2);
+  SDValue Ops[] = { Op1, Op2 };
+  return getNode(~Opcode, VTs, 2, Ops, 2).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1,
-                                    MVT VT2, SDValue Op1, SDValue Op2) {
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
+                                    MVT VT2, SDValue Op1,
+                                    SDValue Op2) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2);
   SDValue Ops[] = { Op1, Op2 };
-  return getNode(~Opcode, DL, VTs, 2, Ops, 2).getNode();
+  return getNode(~Opcode, dl, VTs, 2, Ops, 2).getNode();
 }
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
                                     MVT VT2, SDValue Op1,
                                     SDValue Op2, SDValue Op3) {
-  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2,
-                       Op1, Op2, Op3);
+  const MVT *VTs = getNodeValueTypes(VT1, VT2);
+  SDValue Ops[] = { Op1, Op2, Op3 };
+  return getNode(~Opcode, VTs, 2, Ops, 3).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL, MVT VT1,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
                                     MVT VT2, SDValue Op1,
                                     SDValue Op2, SDValue Op3) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2);
   SDValue Ops[] = { Op1, Op2, Op3 };
-  return getNode(~Opcode, DL, VTs, 2, Ops, 3).getNode();
+  return getNode(~Opcode, dl, VTs, 2, Ops, 3).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
-                                    MVT VT1, MVT VT2,
+
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
                                     const SDValue *Ops, unsigned NumOps) {
-  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2,
-                       Ops, NumOps);
+  const MVT *VTs = getNodeValueTypes(VT1, VT2);
+  return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 
                                     MVT VT1, MVT VT2,
                                     const SDValue *Ops, unsigned NumOps) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2);
-  return getNode(~Opcode, DL, VTs, 2, Ops, NumOps).getNode();
+  return getNode(~Opcode, dl, VTs, 2, Ops, NumOps).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
-                                    MVT VT1, MVT VT2, MVT VT3,
+
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
                                     SDValue Op1, SDValue Op2) {
-  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2, VT3,
-                       Op1, Op2);
+  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
+  SDValue Ops[] = { Op1, Op2 };
+  return getNode(~Opcode, VTs, 3, Ops, 2).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
                                     MVT VT1, MVT VT2, MVT VT3,
                                     SDValue Op1, SDValue Op2) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
   SDValue Ops[] = { Op1, Op2 };
-  return getNode(~Opcode, DL, VTs, 3, Ops, 2).getNode();
+  return getNode(~Opcode, dl, VTs, 3, Ops, 2).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
-                                    MVT VT1, MVT VT2, MVT VT3,
-                                    SDValue Op1, SDValue Op2, SDValue Op3) {
-  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2, VT3,
-                       Op1, Op2, Op3);
+
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
+                                    SDValue Op1, SDValue Op2,
+                                    SDValue Op3) {
+  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
+  SDValue Ops[] = { Op1, Op2, Op3 };
+  return getNode(~Opcode, VTs, 3, Ops, 3).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
                                     MVT VT1, MVT VT2, MVT VT3,
-                                    SDValue Op1, SDValue Op2, SDValue Op3) {
+                                    SDValue Op1, SDValue Op2,
+                                    SDValue Op3) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
   SDValue Ops[] = { Op1, Op2, Op3 };
-  return getNode(~Opcode, DL, VTs, 3, Ops, 3).getNode();
+  return getNode(~Opcode, dl, VTs, 3, Ops, 3).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
-                                    MVT VT1, MVT VT2, MVT VT3,
+
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
                                     const SDValue *Ops, unsigned NumOps) {
-  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(), VT1, VT2, VT3,
-                       Ops, NumOps);
+  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
+  return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
                                     MVT VT1, MVT VT2, MVT VT3,
                                     const SDValue *Ops, unsigned NumOps) {
   const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
-  return getNode(~Opcode, DL, VTs, 3, Ops, NumOps).getNode();
+  return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
-                                    MVT VT1, MVT VT2, MVT VT3, MVT VT4,
+
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
+                                    MVT VT2, MVT VT3, MVT VT4,
                                     const SDValue *Ops, unsigned NumOps) {
-  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(),
-                       VT1, VT2, VT3, VT4, Ops, NumOps);
+  std::vector VTList;
+  VTList.push_back(VT1);
+  VTList.push_back(VT2);
+  VTList.push_back(VT3);
+  VTList.push_back(VT4);
+  const MVT *VTs = getNodeValueTypes(VTList);
+  return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
-                                    MVT VT1, MVT VT2, MVT VT3, MVT VT4,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
+                                    MVT VT2, MVT VT3, MVT VT4,
                                     const SDValue *Ops, unsigned NumOps) {
   std::vector VTList;
   VTList.push_back(VT1);
@@ -4890,19 +4917,21 @@
   VTList.push_back(VT3);
   VTList.push_back(VT4);
   const MVT *VTs = getNodeValueTypes(VTList);
-  return getNode(~Opcode, DL, VTs, 4, Ops, NumOps).getNode();
+  return getNode(~Opcode, dl, VTs, 4, Ops, NumOps).getNode();
 }
+
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
                                     const std::vector &ResultTys,
                                     const SDValue *Ops, unsigned NumOps) {
-  return getTargetNode(Opcode, DebugLoc::getUnknownLoc(),
-                       ResultTys, Ops, NumOps);
+  const MVT *VTs = getNodeValueTypes(ResultTys);
+  return getNode(~Opcode, VTs, ResultTys.size(),
+                 Ops, NumOps).getNode();
 }
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc DL,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
                                     const std::vector &ResultTys,
                                     const SDValue *Ops, unsigned NumOps) {
   const MVT *VTs = getNodeValueTypes(ResultTys);
-  return getNode(~Opcode, DL, VTs, ResultTys.size(),
+  return getNode(~Opcode, dl, VTs, ResultTys.size(),
                  Ops, NumOps).getNode();
 }
 




From echeng at apple.com  Thu Jan 29 03:05:34 2009
From: echeng at apple.com (Evan Cheng)
Date: Thu, 29 Jan 2009 01:05:34 -0800
Subject: [llvm-commits] [llvm-gcc-4.2] r63291 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
In-Reply-To: <200901290810.n0T8A1Ix013088@zion.cs.uiuc.edu>
References: <200901290810.n0T8A1Ix013088@zion.cs.uiuc.edu>
Message-ID: <5BF508D5-A131-4CBD-968A-542B05C912C8@apple.com>

Thanks.

Evan
On Jan 29, 2009, at 12:10 AM, Duncan Sands wrote:

> Author: baldrick
> Date: Thu Jan 29 02:10:01 2009
> New Revision: 63291
>
> URL: http://llvm.org/viewvc/llvm-project?rev=63291&view=rev
> Log:
> Better fix for FrontendC/implicit-arg.c.
>
> Modified:
>    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
>
> Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=63291&r1=63290&r2=63291&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
> +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Thu Jan 29 02:10:01 2009
> @@ -2821,7 +2821,7 @@
>         const FunctionType *ActualFT =
>           cast(ActualPT->getElementType());
>         if (RealFT->getReturnType() == ActualFT->getReturnType() &&
> -            ActualFT->getNumParams() == 0)
> +            RealFT->getNumParams() == 0)
>           Callee = RealCallee;
>       }
>     }
> @@ -2829,21 +2829,6 @@
>
>   Value *Call;
>   if (!LandingPad) {
> -    if (CallOperands.empty()) {
> -      const FunctionType *FTy = cast
> -        (cast(Callee->getType())->getElementType());
> -      if (!FTy->isVarArg() && FTy->getNumParams() > 0) {
> -        // Something like this:
> -        // static int func2();
> -        // void func1() {
> -        //   int a = func2();
> -        // }
> -        // int func2(unsigned a) {
> -        // }
> -        // gcc4.2 allows this.
> -        CallOperands.push_back(UndefValue::get(FTy- 
> >getParamType(0)));
> -      }
> -    }
>     Call = Builder.CreateCall(Callee, CallOperands.begin(),  
> CallOperands.end());
>     cast(Call)->setCallingConv(CallingConvention);
>     cast(Call)->setAttributes(PAL);
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From evan.cheng at apple.com  Thu Jan 29 03:17:55 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 29 Jan 2009 09:17:55 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63302 -
	/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Message-ID: <200901290917.n0T9HuVP025546@zion.cs.uiuc.edu>

Author: evancheng
Date: Thu Jan 29 03:17:55 2009
New Revision: 63302

URL: http://llvm.org/viewvc/llvm-project?rev=63302&view=rev
Log:
llvm-gcc is not inlining functions that are marked always_inline at -O0 and -O1. The bug is the logic to check whether always-inline pass is broken. When createOptimizationPasses() is run, most of the functions are not in the module. It's not possible to tell whether the pass is needed just by scanning the functions.

Unless llvm optimization is explicitly turned off, always run the always-inline pass (-O0 and -O1, or -fno-inline-functions) unless the full inliner is being run (-O2 and above).

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=63302&r1=63301&r2=63302&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Thu Jan 29 03:17:55 2009
@@ -392,87 +392,82 @@
   PerModulePasses = new PassManager();
   PerModulePasses->add(new TargetData(*TheTarget->getTargetData()));
   bool HasPerModulePasses = false;
-  bool NeedAlwaysInliner = false;
-  // Check if AlwaysInliner is needed to handle functions that are 
-  // marked as always_inline.
-  for (Module::iterator I = TheModule->begin(), E = TheModule->end();
-       I != E; ++I)
-    if (I->hasFnAttr(Attribute::AlwaysInline)) {
-      NeedAlwaysInliner = true;
-      break;
-    }
 
-  if (optimize > 0 && !DisableLLVMOptimizations) {
+  if (!DisableLLVMOptimizations) {
     HasPerModulePasses = true;
-    PassManager *PM = PerModulePasses;
-    if (flag_unit_at_a_time)
-      PM->add(createRaiseAllocationsPass());      // call %malloc -> malloc inst
-    PM->add(createCFGSimplificationPass());       // Clean up disgusting code
-    PM->add(createPromoteMemoryToRegisterPass()); // Kill useless allocas
-    if (flag_unit_at_a_time) {
-      PM->add(createGlobalOptimizerPass());       // Optimize out global vars
-      PM->add(createGlobalDCEPass());             // Remove unused fns and globs
-      PM->add(createIPConstantPropagationPass()); // IP Constant Propagation
-      PM->add(createDeadArgEliminationPass());    // Dead argument elimination
-    }
-    PM->add(createInstructionCombiningPass());    // Clean up after IPCP & DAE
-    PM->add(createCFGSimplificationPass());       // Clean up after IPCP & DAE
-    if (flag_unit_at_a_time) {
-      if (flag_exceptions)
-        PM->add(createPruneEHPass());             // Remove dead EH info
-      PM->add(createFunctionAttrsPass());         // Deduce function attrs
-    }
-    if (flag_inline_trees > 1)                    // respect -fno-inline-functions
-      PM->add(createFunctionInliningPass());      // Inline small functions
-    else if (NeedAlwaysInliner)
-      PM->add(createAlwaysInlinerPass());         // Inline always_inline functions
-    if (optimize > 2)
-      PM->add(createArgumentPromotionPass());   // Scalarize uninlined fn args
-    if (!flag_no_simplify_libcalls)
-      PM->add(createSimplifyLibCallsPass());    // Library Call Optimizations
-    PM->add(createInstructionCombiningPass());  // Cleanup for scalarrepl.
-    PM->add(createJumpThreadingPass());         // Thread jumps.
-    PM->add(createCFGSimplificationPass());     // Merge & remove BBs
-    PM->add(createScalarReplAggregatesPass());  // Break up aggregate allocas
-    PM->add(createInstructionCombiningPass());  // Combine silly seq's
-    PM->add(createCondPropagationPass());       // Propagate conditionals
-    PM->add(createTailCallEliminationPass());   // Eliminate tail calls
-    PM->add(createCFGSimplificationPass());     // Merge & remove BBs
-    PM->add(createReassociatePass());           // Reassociate expressions
-    PM->add(createLoopRotatePass());            // Rotate Loop
-    PM->add(createLICMPass());                  // Hoist loop invariants
-    PM->add(createLoopUnswitchPass(optimize_size || optimize < 3));
-    PM->add(createLoopIndexSplitPass());        // Split loop index
-    PM->add(createInstructionCombiningPass());  
-    PM->add(createIndVarSimplifyPass());        // Canonicalize indvars
-    PM->add(createLoopDeletionPass());          // Delete dead loops
-    if (flag_unroll_loops)
-      PM->add(createLoopUnrollPass());          // Unroll small loops
-    PM->add(createInstructionCombiningPass());  // Clean up after the unroller
-    PM->add(createGVNPass());                   // Remove redundancies
-    PM->add(createMemCpyOptPass());             // Remove memcpy / form memset
-    PM->add(createSCCPPass());                  // Constant prop with SCCP
+    if (optimize == 0)
+      // Unless all LLVM optimizations are disabled, always run
+      // always-inline pass.
+      PerModulePasses->add(createAlwaysInlinerPass());
+    else {
+      PassManager *PM = PerModulePasses;
+      if (flag_unit_at_a_time)
+        PM->add(createRaiseAllocationsPass());    // call %malloc -> malloc inst
+      PM->add(createCFGSimplificationPass());     // Clean up disgusting code
+      PM->add(createPromoteMemoryToRegisterPass()); // Kill useless allocas
+      if (flag_unit_at_a_time) {
+        PM->add(createGlobalOptimizerPass());     // Optimize out global vars
+        PM->add(createGlobalDCEPass());           // Remove unused fns and globs
+        PM->add(createIPConstantPropagationPass()); // IP Constant Propagation
+        PM->add(createDeadArgEliminationPass());  // Dead argument elimination
+      }
+      PM->add(createInstructionCombiningPass());  // Clean up after IPCP & DAE
+      PM->add(createCFGSimplificationPass());     // Clean up after IPCP & DAE
+      if (flag_unit_at_a_time) {
+        if (flag_exceptions)
+          PM->add(createPruneEHPass());           // Remove dead EH info
+        PM->add(createFunctionAttrsPass());       // Deduce function attrs
+      }
+      if (flag_inline_trees > 1)                // respect -fno-inline-functions
+        PM->add(createFunctionInliningPass());    // Inline small functions
+      else
+        PM->add(createAlwaysInlinerPass());       // Inline always_inline funcs
+      if (optimize > 2)
+        PM->add(createArgumentPromotionPass());   // Scalarize uninlined fn args
+      if (!flag_no_simplify_libcalls)
+        PM->add(createSimplifyLibCallsPass());    // Library Call Optimizations
+      PM->add(createInstructionCombiningPass());  // Cleanup for scalarrepl.
+      PM->add(createJumpThreadingPass());         // Thread jumps.
+      PM->add(createCFGSimplificationPass());     // Merge & remove BBs
+      PM->add(createScalarReplAggregatesPass());  // Break up aggregate allocas
+      PM->add(createInstructionCombiningPass());  // Combine silly seq's
+      PM->add(createCondPropagationPass());       // Propagate conditionals
+      PM->add(createTailCallEliminationPass());   // Eliminate tail calls
+      PM->add(createCFGSimplificationPass());     // Merge & remove BBs
+      PM->add(createReassociatePass());           // Reassociate expressions
+      PM->add(createLoopRotatePass());            // Rotate Loop
+      PM->add(createLICMPass());                  // Hoist loop invariants
+      // At -O2, loop unswitch should not increase code size.
+      PM->add(createLoopUnswitchPass(optimize_size || optimize < 3));
+      PM->add(createLoopIndexSplitPass());        // Split loop index
+      PM->add(createInstructionCombiningPass());  
+      PM->add(createIndVarSimplifyPass());        // Canonicalize indvars
+      PM->add(createLoopDeletionPass());          // Delete dead loops
+      if (flag_unroll_loops)
+        PM->add(createLoopUnrollPass());          // Unroll small loops
+      PM->add(createInstructionCombiningPass());  // Clean up after the unroller
+      PM->add(createGVNPass());                   // Remove redundancies
+      PM->add(createMemCpyOptPass());             // Remove memcpy / form memset
+      PM->add(createSCCPPass());                  // Constant prop with SCCP
     
-    // Run instcombine after redundancy elimination to exploit opportunities
-    // opened up by them.
-    PM->add(createInstructionCombiningPass());
-    PM->add(createCondPropagationPass());       // Propagate conditionals
-    PM->add(createDeadStoreEliminationPass());  // Delete dead stores
-    PM->add(createAggressiveDCEPass());   // Delete dead instructions
-    PM->add(createCFGSimplificationPass());     // Merge & remove BBs
-
-    if (flag_unit_at_a_time) {
-      PM->add(createStripDeadPrototypesPass());   // Get rid of dead prototypes
-      PM->add(createDeadTypeEliminationPass());   // Eliminate dead types
-    }
+      // Run instcombine after redundancy elimination to exploit opportunities
+      // opened up by them.
+      PM->add(createInstructionCombiningPass());
+      PM->add(createCondPropagationPass());       // Propagate conditionals
+      PM->add(createDeadStoreEliminationPass());  // Delete dead stores
+      PM->add(createAggressiveDCEPass());         // Delete dead instructions
+      PM->add(createCFGSimplificationPass());     // Merge & remove BBs
+
+      if (flag_unit_at_a_time) {
+        PM->add(createStripDeadPrototypesPass()); // Get rid of dead prototypes
+        PM->add(createDeadTypeEliminationPass()); // Eliminate dead types
+      }
 
-    if (optimize > 1 && flag_unit_at_a_time)
-      PM->add(createConstantMergePass());       // Merge dup global constants 
+      if (optimize > 1 && flag_unit_at_a_time)
+        PM->add(createConstantMergePass());       // Merge dup global constants 
+    }
   }
 
-  if (!HasPerModulePasses && NeedAlwaysInliner)
-    PerModulePasses->add(createAlwaysInlinerPass());
-
   if (emit_llvm_bc) {
     // Emit an LLVM .bc file to the output.  This is used when passed
     // -emit-llvm -c to the GCC driver.




From evan.cheng at apple.com  Thu Jan 29 03:31:55 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 29 Jan 2009 09:31:55 -0000
Subject: [llvm-commits] [llvm] r63304 -
	/llvm/trunk/test/FrontendC/always-inline.c
Message-ID: <200901290931.n0T9VtGS026173@zion.cs.uiuc.edu>

Author: evancheng
Date: Thu Jan 29 03:31:54 2009
New Revision: 63304

URL: http://llvm.org/viewvc/llvm-project?rev=63304&view=rev
Log:
Add a always_inline test case.

Added:
    llvm/trunk/test/FrontendC/always-inline.c

Added: llvm/trunk/test/FrontendC/always-inline.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/always-inline.c?rev=63304&view=auto

==============================================================================
--- llvm/trunk/test/FrontendC/always-inline.c (added)
+++ llvm/trunk/test/FrontendC/always-inline.c Thu Jan 29 03:31:54 2009
@@ -0,0 +1,12 @@
+// RUN: %llvmgcc -S %s -o - | grep call | not grep foo
+
+void bar() {
+}
+
+inline void __attribute__((__always_inline__)) foo() {
+  bar();
+}
+
+void i_want_bar() {
+  foo();
+}




From baldrick at free.fr  Thu Jan 29 07:25:10 2009
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 29 Jan 2009 13:25:10 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63306 -
	/llvm-gcc-4.2/trunk/gcc/tree-nested.c
Message-ID: <200901291325.n0TDPAhe001801@zion.cs.uiuc.edu>

Author: baldrick
Date: Thu Jan 29 07:25:08 2009
New Revision: 63306

URL: http://llvm.org/viewvc/llvm-project?rev=63306&view=rev
Log:
Yes, we have to use the LLVM way (of which this
assert is just a small part): using the non-llvm
version just below would instantly reintroduce
the original gcc bug.  This bug is not serious
for gcc, but it is fatal for LLVM: it results
in callers sometimes thinking that the callee
takes a static chain, while in fact the callee
does not.  Since in gcc the static chain is
passed out-of-band in a special register, it
doesn't matter if the chain is passed even
though it is not needed: the register value
is just ignored.  In LLVM the static chain
becomes an explicit extra parameter: the bug
meant that the caller would pass one more
parameter than the callee was expecting, which
results in all parameters getting wrong values
in the callee - very nasty.  This should really
be fixed in gcc too, since it can result in the
caller itself getting a static chain because it
thinks it needs it to pass to the callee.  That
can result in all kinds of serious inefficiences.


Modified:
    llvm-gcc-4.2/trunk/gcc/tree-nested.c

Modified: llvm-gcc-4.2/trunk/gcc/tree-nested.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/tree-nested.c?rev=63306&r1=63305&r2=63306&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/tree-nested.c (original)
+++ llvm-gcc-4.2/trunk/gcc/tree-nested.c Thu Jan 29 07:25:08 2009
@@ -1972,7 +1972,6 @@
       walk_function (convert_call_expr, root);
 
       /* LLVM LOCAL begin */
-      /* FIXME: Keep the LLVM-way? */
 #ifdef ENABLE_LLVM
       gcc_assert (!root->outer ||
                   DECL_NO_STATIC_CHAIN (root->context) ==




From baldrick at free.fr  Thu Jan 29 07:32:56 2009
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 29 Jan 2009 13:32:56 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63307 -
	/llvm-gcc-4.2/trunk/gcc/tree-nested.c
Message-ID: <200901291332.n0TDWucJ002022@zion.cs.uiuc.edu>

Author: baldrick
Date: Thu Jan 29 07:32:56 2009
New Revision: 63307

URL: http://llvm.org/viewvc/llvm-project?rev=63307&view=rev
Log:
LLVM only has one intrinsic (init_trampoline) which
combines gcc's init_trampoline and adjust_trampoline
(Chris asked for this).  These code changes are there
to take account of this.

Modified:
    llvm-gcc-4.2/trunk/gcc/tree-nested.c

Modified: llvm-gcc-4.2/trunk/gcc/tree-nested.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/tree-nested.c?rev=63307&r1=63306&r2=63307&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/tree-nested.c (original)
+++ llvm-gcc-4.2/trunk/gcc/tree-nested.c Thu Jan 29 07:32:56 2009
@@ -527,7 +527,6 @@
       field = make_node (FIELD_DECL);
       DECL_NAME (field) = DECL_NAME (decl);
       /* LLVM LOCAL begin */
-      /* FIXME: Keep the LLVM-way? */
 #ifdef ENABLE_LLVM
       TREE_TYPE (field) = TYPE_POINTER_TO (TREE_TYPE (decl));
 #else
@@ -1831,7 +1830,6 @@
 	continue;
 
       /* LLVM LOCAL begin */
-      /* FIXME: Keep the LLVM-way? */
 #ifdef ENABLE_LLVM
       /* Lookup the trampoline.  */
       x = lookup_tramp_for_decl (i, decl, INSERT);
@@ -2078,7 +2076,6 @@
 	  arg = tree_cons (NULL, x, arg);
 
 	  /* LLVM LOCAL begin */
-          /* FIXME: Keep the LLVM-way? */
 #ifdef ENABLE_LLVM
 	  /* Create a local variable to hold the trampoline code.  */
 	  y = create_tmp_var_for (root, get_trampoline_type(),




From baldrick at free.fr  Thu Jan 29 09:49:38 2009
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 29 Jan 2009 16:49:38 +0100
Subject: [llvm-commits] [llvm-gcc-4.2] r63087 -
	/llvm-gcc-4.2/trunk/gcc/tree-nested.c
In-Reply-To: <200901270202.n0R22aB6002964@zion.cs.uiuc.edu>
References: <200901270202.n0R22aB6002964@zion.cs.uiuc.edu>
Message-ID: <200901291649.38420.baldrick@free.fr>

Thanks for putting my favorite assertion back!

Ciao,

Duncan.

PS: For some reason I didn't see the commit on the mailing list.
Is something wrong with commit mail?


From gohman at apple.com  Thu Jan 29 10:10:47 2009
From: gohman at apple.com (Dan Gohman)
Date: Thu, 29 Jan 2009 16:10:47 -0000
Subject: [llvm-commits] [llvm] r63311 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 test/CodeGen/X86/vec_ins_extract-1.ll
Message-ID: <200901291610.n0TGAlpt007450@zion.cs.uiuc.edu>

Author: djg
Date: Thu Jan 29 10:10:46 2009
New Revision: 63311

URL: http://llvm.org/viewvc/llvm-project?rev=63311&view=rev
Log:
In the case of an extractelement on an insertelement value,
the element indices may be equal if either one is not a
constant.

Added:
    llvm/trunk/test/CodeGen/X86/vec_ins_extract-1.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63311&r1=63310&r2=63311&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jan 29 10:10:46 2009
@@ -2597,9 +2597,13 @@
     // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector
     // operations are lowered to scalars.
     if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) {
+      // If the indices are the same, return the inserted element.
       if (N1.getOperand(2) == N2)
         return N1.getOperand(1);
-      else
+      // If the indices are known different, extract the element from
+      // the original vector.
+      else if (isa(N1.getOperand(2)) &&
+               isa(N2))
         return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2);
     }
     break;

Added: llvm/trunk/test/CodeGen/X86/vec_ins_extract-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_ins_extract-1.ll?rev=63311&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_ins_extract-1.ll (added)
+++ llvm/trunk/test/CodeGen/X86/vec_ins_extract-1.ll Thu Jan 29 10:10:46 2009
@@ -0,0 +1,25 @@
+; RUN: llvm-as < %s | llc -march=x86 | grep {(%esp,%eax,4)} | count 4
+
+; Inserts and extracts with variable indices must be lowered
+; to memory accesses.
+
+define i32 @t0(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
+  %t13 = insertelement <4 x i32> %t8, i32 76, i32 %t7
+  %t9 = extractelement <4 x i32> %t13, i32 0
+  ret i32 %t9
+}
+define i32 @t1(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
+  %t13 = insertelement <4 x i32> %t8, i32 76, i32 0
+  %t9 = extractelement <4 x i32> %t13, i32 %t7
+  ret i32 %t9
+}
+define <4 x i32> @t2(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
+  %t9 = extractelement <4 x i32> %t8, i32 %t7
+  %t13 = insertelement <4 x i32> %t8, i32 %t9, i32 0
+  ret <4 x i32> %t13
+}
+define <4 x i32> @t3(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
+  %t9 = extractelement <4 x i32> %t8, i32 0
+  %t13 = insertelement <4 x i32> %t8, i32 %t9, i32 %t7
+  ret <4 x i32> %t13
+}




From gohman at apple.com  Thu Jan 29 10:18:13 2009
From: gohman at apple.com (Dan Gohman)
Date: Thu, 29 Jan 2009 16:18:13 -0000
Subject: [llvm-commits] [llvm] r63312 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Message-ID: <200901291618.n0TGIDMB007660@zion.cs.uiuc.edu>

Author: djg
Date: Thu Jan 29 10:18:12 2009
New Revision: 63312

URL: http://llvm.org/viewvc/llvm-project?rev=63312&view=rev
Log:
Fix two typos that Duncan spotted in a comment.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=63312&r1=63311&r2=63312&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Jan 29 10:18:12 2009
@@ -1815,7 +1815,7 @@
       }
     }
 
-    // Simpify x&y == y to x&y == 0 if y has exactly one bit set.
+    // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
     if (N0.getOpcode() == ISD::AND)
       if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
         if (ValueHasAtMostOneBitSet(N1, DAG)) {




From dalej at apple.com  Thu Jan 29 11:51:01 2009
From: dalej at apple.com (Dale Johannesen)
Date: Thu, 29 Jan 2009 09:51:01 -0800
Subject: [llvm-commits] [llvm-gcc-4.2] r63087 -
	/llvm-gcc-4.2/trunk/gcc/tree-nested.c
In-Reply-To: <200901291649.38420.baldrick@free.fr>
References: <200901270202.n0R22aB6002964@zion.cs.uiuc.edu>
	<200901291649.38420.baldrick@free.fr>
Message-ID: 


On Jan 29, 2009, at 7:49 AMPST, Duncan Sands wrote:

> Thanks for putting my favorite assertion back!
>
> Ciao,
>
> Duncan.
>
> PS: For some reason I didn't see the commit on the mailing list.
> Is something wrong with commit mail?

I got it, and am getting other commit messages.  I'd look at your end.



From gohman at apple.com  Thu Jan 29 12:06:58 2009
From: gohman at apple.com (Dan Gohman)
Date: Thu, 29 Jan 2009 10:06:58 -0800
Subject: [llvm-commits] [llvm] r63266 - in /llvm/trunk:
	include/llvm/Target/TargetLowering.h
	lib/CodeGen/SelectionDAG/DAGCombiner.cpp
	lib/CodeGen/SelectionDAG/TargetLowering.cpp
	lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/bt.ll
	test/CodeGen/X86/commute-cmov.ll
In-Reply-To: <200901290940.46887.baldrick@free.fr>
References: <200901290159.n0T1x25H032445@zion.cs.uiuc.edu>
	<200901290940.46887.baldrick@free.fr>
Message-ID: <887AA6DA-667F-4687-9A30-15F16CFC01AE@apple.com>


On Jan 29, 2009, at 12:40 AM, Duncan Sands wrote:

> Hi Dan,
>
>>   case ISD::SRA:
>> +    // If this is an arithmetic shift right and only the low-bit  
>> is set, we can
>> +    // always convert this into a logical shr, even if the shift  
>> amount is
>> +    // variable.  The low bit of the shift cannot be an input sign  
>> bit unless
>> +    // the shift amount is >= the size of the datatype, which is  
>> undefined.
>> +    if (DemandedMask == 1)
>> +      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,  
>> Op.getValueType(),
>> +                                               Op.getOperand(0),  
>> Op.getOperand(1)));
>
> is this correct for MVT::i1?

Yes; the only valid shift count for MVT::i1 is 0.

>
>
>> +    // Simpify x&y == y to x&y == 0 if y has exactly one bit set.
>
> Simpify -> Simplify.  Also, the transform described in the comment
> looks wrong.  For example, suppose x==y.  Then the left version is
> equivalent to x == x, while the right version is equivalent to x == 0.

The code was right, but the comment was wrong. Both comment
errors are now fixed.

Thanks!

Dan



From baldrick at free.fr  Thu Jan 29 12:13:54 2009
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 29 Jan 2009 18:13:54 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63321 - in /llvm-gcc-4.2/trunk/gcc:
 llvm-backend.cpp llvm-convert.cpp llvm-types.cpp
Message-ID: <200901291813.n0TIDstJ011978@zion.cs.uiuc.edu>

Author: baldrick
Date: Thu Jan 29 12:13:54 2009
New Revision: 63321

URL: http://llvm.org/viewvc/llvm-project?rev=63321&view=rev
Log:
Workaround for PR1000: changing TYPE_ALIGN to
TYPE_ALIGN_UNIT supposes that BITS_PER_UNIT
is 8.  It's the inverse transform that improves
portability!

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
    llvm-gcc-4.2/trunk/gcc/llvm-types.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=63321&r1=63320&r2=63321&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Thu Jan 29 12:13:54 2009
@@ -1108,14 +1108,14 @@
     }
     
     // Set the alignment for the global if one of the following condition is met
-    // 1) DECL_ALIGN_UNIT is better than the alignment as per ABI specification
+    // 1) DECL_ALIGN is better than the alignment as per ABI specification
     // 2) DECL_ALIGN is set by user.
-    if (DECL_ALIGN_UNIT(decl)) {
+    if (DECL_ALIGN(decl)) {
       unsigned TargetAlign =
         getTargetData().getABITypeAlignment(GV->getType()->getElementType());
       if (DECL_USER_ALIGN(decl) ||
-          TargetAlign < (unsigned)DECL_ALIGN_UNIT(decl))
-        GV->setAlignment(DECL_ALIGN_UNIT(decl));
+          8 * TargetAlign < (unsigned)DECL_ALIGN(decl))
+        GV->setAlignment(DECL_ALIGN(decl) / 8);
     }
 
     // Handle used decls

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=63321&r1=63320&r2=63321&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Thu Jan 29 12:13:54 2009
@@ -1161,15 +1161,15 @@
   // Constants.
   case LABEL_DECL: {
     Value *Ptr = TreeConstantToLLVM::EmitLV_LABEL_DECL(exp);
-    return LValue(Ptr, DECL_ALIGN_UNIT(exp));
+    return LValue(Ptr, DECL_ALIGN(exp) / 8);
   }
   case COMPLEX_CST: {
     Value *Ptr = TreeConstantToLLVM::EmitLV_COMPLEX_CST(exp);
-    return LValue(Ptr, TYPE_ALIGN_UNIT(TREE_TYPE(exp)));
+    return LValue(Ptr, TYPE_ALIGN(TREE_TYPE(exp)) / 8);
   }
   case STRING_CST: {
     Value *Ptr = TreeConstantToLLVM::EmitLV_STRING_CST(exp);
-    return LValue(Ptr, TYPE_ALIGN_UNIT(TREE_TYPE(exp)));
+    return LValue(Ptr, TYPE_ALIGN(TREE_TYPE(exp)) / 8);
   }
 
   // Type Conversion.
@@ -1700,12 +1700,12 @@
   unsigned Alignment = 0; // Alignment in bytes.
 
   // Set the alignment for the local if one of the following condition is met
-  // 1) DECL_ALIGN_UNIT is better than the alignment as per ABI specification
+  // 1) DECL_ALIGN is better than the alignment as per ABI specification
   // 2) DECL_ALIGN is set by user.
-  if (DECL_ALIGN_UNIT(decl)) {
+  if (DECL_ALIGN(decl)) {
     unsigned TargetAlign = getTargetData().getABITypeAlignment(Ty);
-    if (DECL_USER_ALIGN(decl) || TargetAlign < (unsigned)DECL_ALIGN_UNIT(decl))
-      Alignment = DECL_ALIGN_UNIT(decl);
+    if (DECL_USER_ALIGN(decl) || 8 * TargetAlign < (unsigned)DECL_ALIGN(decl))
+      Alignment = DECL_ALIGN(decl) / 8;
   }
 
   const char *Name;      // Name of variable
@@ -5945,9 +5945,9 @@
   if (Ty == Type::VoidTy) Ty = StructType::get(NULL, NULL);
   const PointerType *PTy = PointerType::getUnqual(Ty);
   unsigned Alignment = Ty->isSized() ? TD.getABITypeAlignment(Ty) : 1;
-  if (DECL_ALIGN_UNIT(exp)) {
-    if (DECL_USER_ALIGN(exp) || Alignment < (unsigned)DECL_ALIGN_UNIT(exp))
-      Alignment = DECL_ALIGN_UNIT(exp);
+  if (DECL_ALIGN(exp)) {
+    if (DECL_USER_ALIGN(exp) || 8 * Alignment < (unsigned)DECL_ALIGN(exp))
+      Alignment = DECL_ALIGN(exp) / 8;
   }
 
   return LValue(BitCastToType(Decl, PTy), Alignment);
@@ -6187,8 +6187,8 @@
     // is required to be.  Try to round up our alignment info.
     if (BitStart == 0 && // llvm pointer points to it.
         !isBitfield(FieldDecl) &&  // bitfield computation might offset pointer.
-        DECL_ALIGN_UNIT(FieldDecl))
-      LVAlign = std::max(LVAlign, unsigned(DECL_ALIGN_UNIT(FieldDecl)));
+        DECL_ALIGN(FieldDecl))
+      LVAlign = std::max(LVAlign, unsigned(DECL_ALIGN(FieldDecl)) / 8);
     
     // If the FIELD_DECL has an annotate attribute on it, emit it.
     if (lookup_attribute("annotate", DECL_ATTRIBUTES(FieldDecl)))

Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=63321&r1=63320&r2=63321&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Thu Jan 29 12:13:54 2009
@@ -1834,7 +1834,8 @@
       // then convert to a packed struct and try again.
       if (TYPE_USER_ALIGN(DECL_BIT_FIELD_TYPE(Field))) {
         const Type *Ty = ConvertType(getDeclaredType(Field));
-        if (TYPE_ALIGN_UNIT(DECL_BIT_FIELD_TYPE(Field)) != Info.getTypeAlignment(Ty))
+        if (TYPE_ALIGN(DECL_BIT_FIELD_TYPE(Field)) !=
+            8 * Info.getTypeAlignment(Ty))
           return false;
       }
     }
@@ -1864,7 +1865,7 @@
     return false;
   } 
   else if (TYPE_USER_ALIGN(TREE_TYPE(Field))
-           && (unsigned)DECL_ALIGN_UNIT(Field) != Info.getTypeAlignment(Ty)
+           && (unsigned)DECL_ALIGN(Field) != 8 * Info.getTypeAlignment(Ty)
            && !Info.isPacked()) {
     // If Field has user defined alignment and it does not match Ty alignment
     // then convert to a packed struct and try again.
@@ -2039,8 +2040,8 @@
   ConvertingStruct = true;
   
   StructTypeConversionInfo *Info = 
-    new StructTypeConversionInfo(*TheTarget, TYPE_ALIGN_UNIT(type), 
-                             TYPE_PACKED(type));
+    new StructTypeConversionInfo(*TheTarget, TYPE_ALIGN(type) / 8,
+                                 TYPE_PACKED(type));
 
   // Alter any fields that appear to represent base classes so their lists
   // of fields bear some resemblance to reality.
@@ -2057,8 +2058,7 @@
 
   if (retryAsPackedStruct) {
     delete Info;
-    Info = new StructTypeConversionInfo(*TheTarget, TYPE_ALIGN_UNIT(type),
-                                        true);
+    Info = new StructTypeConversionInfo(*TheTarget, TYPE_ALIGN(type) / 8, true);
     for (tree Field = TYPE_FIELDS(type); Field; Field = TREE_CHAIN(Field)) {
       if (DecodeStructFields(Field, *Info) == false) {
         assert(0 && "Unable to decode struct fields.");
@@ -2330,7 +2330,7 @@
     }
   }
 
-  bool isPacked = EltAlign > TYPE_ALIGN_UNIT(type);
+  bool isPacked = 8 * EltAlign > TYPE_ALIGN(type);
   const Type *ResultTy = StructType::get(UnionElts, isPacked);
   const OpaqueType *OldTy = cast_or_null(GET_TYPE_LLVM(type));
   TypeDB.setType(type, ResultTy);




From sabre at nondot.org  Thu Jan 29 12:16:32 2009
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 29 Jan 2009 18:16:32 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63322 -
	/llvm-gcc-4.2/trunk/gcc/config/i386/i386.c
Message-ID: <200901291816.n0TIGWnk012088@zion.cs.uiuc.edu>

Author: lattner
Date: Thu Jan 29 12:16:31 2009
New Revision: 63322

URL: http://llvm.org/viewvc/llvm-project?rev=63322&view=rev
Log:
Default -fno-math-errno to on with all i386 targets.  This is after discussion
with Anton and Duncan.  -fmath-errno still works to enable it.

Modified:
    llvm-gcc-4.2/trunk/gcc/config/i386/i386.c

Modified: llvm-gcc-4.2/trunk/gcc/config/i386/i386.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/i386.c?rev=63322&r1=63321&r2=63322&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/i386/i386.c (original)
+++ llvm-gcc-4.2/trunk/gcc/config/i386/i386.c Thu Jan 29 12:16:31 2009
@@ -2438,7 +2438,16 @@
   flag_trapping_math = 0;
   /* APPLE LOCAL end pragma fenv */
 
-  if (TARGET_MACHO)
+  /* APPLE LOCAL begin LLVM */
+  /* Enable -fno-math-errno by default, even on systems whose libm functions set
+     errno.  This is a deviation from what mainline GCC does, but it is a) good
+     for performance, b) controllable with -fmath-errno, and c) the default
+     behavior most people want anyway.  Numericists and others who play with or
+     depend on errno and can use -fmath-errno when they want it.  Because errno
+     is not set on all targets anyway, their code is inherently non-portable. */
+  if (TARGET_MACHO || 1)
+  /* APPLE LOCAL end LLVM */
+  
     /* The Darwin libraries never set errno, so we might as well
        avoid calling them when that's the only reason we would.  */
     flag_errno_math = 0;




From dalej at apple.com  Thu Jan 29 12:22:21 2009
From: dalej at apple.com (Dale Johannesen)
Date: Thu, 29 Jan 2009 10:22:21 -0800
Subject: [llvm-commits] [llvm-gcc-4.2] r63322 -
	/llvm-gcc-4.2/trunk/gcc/config/i386/i386.c
In-Reply-To: <200901291816.n0TIGWnk012088@zion.cs.uiuc.edu>
References: <200901291816.n0TIGWnk012088@zion.cs.uiuc.edu>
Message-ID: 


On Jan 29, 2009, at 10:16 AMPST, Chris Lattner wrote:
> URL: http://llvm.org/viewvc/llvm-project?rev=63322&view=rev
> Log:
> Default -fno-math-errno to on with all i386 targets.  This is after  
> discussion
> with Anton and Duncan.  -fmath-errno still works to enable it.

This is a violation of the C89 standard and can break programs that  
are correct under that standard.  It may be the right thing to do  
anyway, but the justification should mention that you've taken this  
into account.

> Modified:
>    llvm-gcc-4.2/trunk/gcc/config/i386/i386.c
>
> Modified: llvm-gcc-4.2/trunk/gcc/config/i386/i386.c
> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/i386.c?rev=63322&r1=63321&r2=63322&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm-gcc-4.2/trunk/gcc/config/i386/i386.c (original)
> +++ llvm-gcc-4.2/trunk/gcc/config/i386/i386.c Thu Jan 29 12:16:31 2009
> @@ -2438,7 +2438,16 @@
>   flag_trapping_math = 0;
>   /* APPLE LOCAL end pragma fenv */
>
> -  if (TARGET_MACHO)
> +  /* APPLE LOCAL begin LLVM */
> +  /* Enable -fno-math-errno by default, even on systems whose libm  
> functions set
> +     errno.  This is a deviation from what mainline GCC does, but  
> it is a) good
> +     for performance, b) controllable with -fmath-errno, and c) the  
> default
> +     behavior most people want anyway.  Numericists and others who  
> play with or
> +     depend on errno and can use -fmath-errno when they want it.   
> Because errno
> +     is not set on all targets anyway, their code is inherently non- 
> portable. */
> +  if (TARGET_MACHO || 1)
> +  /* APPLE LOCAL end LLVM */
> +
>     /* The Darwin libraries never set errno, so we might as well
>        avoid calling them when that's the only reason we would.  */
>     flag_errno_math = 0;
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From evan.cheng at apple.com  Thu Jan 29 12:37:30 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 29 Jan 2009 18:37:30 -0000
Subject: [llvm-commits] [llvm] r63323 - in /llvm/trunk:
 lib/CodeGen/RegAllocLocal.cpp
 test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll
Message-ID: <200901291837.n0TIbUX8013026@zion.cs.uiuc.edu>

Author: evancheng
Date: Thu Jan 29 12:37:30 2009
New Revision: 63323

URL: http://llvm.org/viewvc/llvm-project?rev=63323&view=rev
Log:
Local register allocator shouldn't assume only the entry and landing pad basic blocks have live-ins.

Added:
    llvm/trunk/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll
Modified:
    llvm/trunk/lib/CodeGen/RegAllocLocal.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocLocal.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLocal.cpp?rev=63323&r1=63322&r2=63323&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLocal.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLocal.cpp Thu Jan 29 12:37:30 2009
@@ -710,24 +710,21 @@
   DEBUG(const BasicBlock *LBB = MBB.getBasicBlock();
         if (LBB) DOUT << "\nStarting RegAlloc of BB: " << LBB->getName());
 
-  // If this is the first basic block in the machine function, add live-in
-  // registers as active.
-  if (&MBB == &*MF->begin() || MBB.isLandingPad()) {
-    for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
+  // Add live-in registers as active.
+  for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
          E = MBB.livein_end(); I != E; ++I) {
-      unsigned Reg = *I;
-      MF->getRegInfo().setPhysRegUsed(Reg);
-      PhysRegsUsed[Reg] = 0;            // It is free and reserved now
-      AddToPhysRegsUseOrder(Reg); 
-      for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
-           *SubRegs; ++SubRegs) {
-        if (PhysRegsUsed[*SubRegs] != -2) {
-          AddToPhysRegsUseOrder(*SubRegs); 
-          PhysRegsUsed[*SubRegs] = 0;  // It is free and reserved now
-          MF->getRegInfo().setPhysRegUsed(*SubRegs);
-        }
+    unsigned Reg = *I;
+    MF->getRegInfo().setPhysRegUsed(Reg);
+    PhysRegsUsed[Reg] = 0;            // It is free and reserved now
+    AddToPhysRegsUseOrder(Reg); 
+    for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
+         *SubRegs; ++SubRegs) {
+      if (PhysRegsUsed[*SubRegs] != -2) {
+        AddToPhysRegsUseOrder(*SubRegs); 
+        PhysRegsUsed[*SubRegs] = 0;  // It is free and reserved now
+        MF->getRegInfo().setPhysRegUsed(*SubRegs);
       }
-    }    
+    }
   }
   
   ComputeLocalLiveness(MBB);

Added: llvm/trunk/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll?rev=63323&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll Thu Jan 29 12:37:30 2009
@@ -0,0 +1,38 @@
+; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9.6 -regalloc=local -disable-fp-elim
+; rdar://6538384
+
+	%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+	%struct.Lit = type { i32 }
+	%struct.StreamBuffer = type { %struct.FILE*, [1048576 x i8], i32, i32 }
+	%struct.__sFILEX = type opaque
+	%struct.__sbuf = type { i8*, i32 }
+
+declare fastcc i32 @_Z8parseIntI12StreamBufferEiRT_(%struct.StreamBuffer*)
+
+declare i8* @llvm.eh.exception() nounwind
+
+define i32 @main(i32 %argc, i8** nocapture %argv) noreturn {
+entry:
+	%0 = invoke fastcc i32 @_Z8parseIntI12StreamBufferEiRT_(%struct.StreamBuffer* null)
+			to label %bb1.i16.i.i unwind label %lpad.i.i		;  [#uses=0]
+
+bb1.i16.i.i:		; preds = %entry
+	br i1 false, label %bb.i.i.i.i, label %_ZN3vecI3LitE4pushERKS0_.exit.i.i.i
+
+bb.i.i.i.i:		; preds = %bb1.i16.i.i
+	br label %_ZN3vecI3LitE4pushERKS0_.exit.i.i.i
+
+_ZN3vecI3LitE4pushERKS0_.exit.i.i.i:		; preds = %bb.i.i.i.i, %bb1.i16.i.i
+	%lits.i.i.0.0 = phi %struct.Lit* [ null, %bb1.i16.i.i ], [ null, %bb.i.i.i.i ]		; <%struct.Lit*> [#uses=1]
+	%1 = invoke fastcc i32 @_Z8parseIntI12StreamBufferEiRT_(%struct.StreamBuffer* null)
+			to label %.noexc21.i.i unwind label %lpad.i.i		;  [#uses=0]
+
+.noexc21.i.i:		; preds = %_ZN3vecI3LitE4pushERKS0_.exit.i.i.i
+	unreachable
+
+lpad.i.i:		; preds = %_ZN3vecI3LitE4pushERKS0_.exit.i.i.i, %entry
+	%lits.i.i.0.3 = phi %struct.Lit* [ %lits.i.i.0.0, %_ZN3vecI3LitE4pushERKS0_.exit.i.i.i ], [ null, %entry ]		; <%struct.Lit*> [#uses=1]
+	%eh_ptr.i.i = call i8* @llvm.eh.exception()		;  [#uses=0]
+	free %struct.Lit* %lits.i.i.0.3
+	unreachable
+}




From clattner at apple.com  Thu Jan 29 12:40:46 2009
From: clattner at apple.com (Chris Lattner)
Date: Thu, 29 Jan 2009 10:40:46 -0800
Subject: [llvm-commits] [llvm-gcc-4.2] r63321 - in
	/llvm-gcc-4.2/trunk/gcc: llvm-backend.cpp llvm-convert.cpp
	llvm-types.cpp
In-Reply-To: <200901291813.n0TIDstJ011978@zion.cs.uiuc.edu>
References: <200901291813.n0TIDstJ011978@zion.cs.uiuc.edu>
Message-ID: <6C2FAC53-ABFE-4BE6-AF6C-8ADDAF4BD0D7@apple.com>


On Jan 29, 2009, at 10:13 AM, Duncan Sands wrote:

> Author: baldrick
> Date: Thu Jan 29 12:13:54 2009
> New Revision: 63321
>
> URL: http://llvm.org/viewvc/llvm-project?rev=63321&view=rev
> Log:
> Workaround for PR1000: changing TYPE_ALIGN to
> TYPE_ALIGN_UNIT supposes that BITS_PER_UNIT
> is 8.  It's the inverse transform that improves
> portability!

Thanks Duncan ;-)

-Chris



From clattner at apple.com  Thu Jan 29 12:40:13 2009
From: clattner at apple.com (Chris Lattner)
Date: Thu, 29 Jan 2009 10:40:13 -0800
Subject: [llvm-commits] [llvm-gcc-4.2] r63322 -
	/llvm-gcc-4.2/trunk/gcc/config/i386/i386.c
In-Reply-To: 
References: <200901291816.n0TIGWnk012088@zion.cs.uiuc.edu>
	
Message-ID: 


On Jan 29, 2009, at 10:22 AM, Dale Johannesen wrote:

>
> On Jan 29, 2009, at 10:16 AMPST, Chris Lattner wrote:
>> URL: http://llvm.org/viewvc/llvm-project?rev=63322&view=rev
>> Log:
>> Default -fno-math-errno to on with all i386 targets.  This is after
>> discussion
>> with Anton and Duncan.  -fmath-errno still works to enable it.
>
> This is a violation of the C89 standard and can break programs that
> are correct under that standard.  It may be the right thing to do
> anyway, but the justification should mention that you've taken this
> into account.

I intend to fully document this in the release notes for 2.5.  Since  
the program is already non-portable (at least to macs) and C99 doesn't  
require this, I think it is ok.

Thanks Dale!

-Chris




From eli.friedman at gmail.com  Thu Jan 29 12:51:31 2009
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 29 Jan 2009 10:51:31 -0800
Subject: [llvm-commits] [llvm-gcc-4.2] r63322 -
	/llvm-gcc-4.2/trunk/gcc/config/i386/i386.c
In-Reply-To: 
References: <200901291816.n0TIGWnk012088@zion.cs.uiuc.edu>
	
	
Message-ID: 

On Thu, Jan 29, 2009 at 10:40 AM, Chris Lattner  wrote:
> Since the program is already non-portable (at least to macs) and C99 doesn't
> require this

Sort of... the standard defines a macro "math_errhandling" in math.h
which allows dealing with this portably.  That said, it appears the
glibc math.h doesn't define it, so likely nobody cares...

-Eli


From clattner at apple.com  Thu Jan 29 12:52:39 2009
From: clattner at apple.com (Chris Lattner)
Date: Thu, 29 Jan 2009 10:52:39 -0800
Subject: [llvm-commits] [llvm-gcc-4.2] r63322 -
	/llvm-gcc-4.2/trunk/gcc/config/i386/i386.c
In-Reply-To: 
References: <200901291816.n0TIGWnk012088@zion.cs.uiuc.edu>
	
	
	
Message-ID: <9E6B951E-2DB8-471E-AE7B-79AC24C78ABC@apple.com>


On Jan 29, 2009, at 10:51 AM, Eli Friedman wrote:

> On Thu, Jan 29, 2009 at 10:40 AM, Chris Lattner   
> wrote:
>> Since the program is already non-portable (at least to macs) and  
>> C99 doesn't
>> require this
>
> Sort of... the standard defines a macro "math_errhandling" in math.h
> which allows dealing with this portably.  That said, it appears the
> glibc math.h doesn't define it, so likely nobody cares...

GCC doesn't support most of the interesting C99 numeric control  
pragmas (For declaring rounding mode sensitivity etc).  It would be  
interesting for clang to support this someday though,

-Chris


From sabre at nondot.org  Thu Jan 29 12:53:28 2009
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 29 Jan 2009 18:53:28 -0000
Subject: [llvm-commits] [llvm] r63325 -
	/llvm/trunk/lib/System/Win32/DynamicLibrary.inc
Message-ID: <200901291853.n0TIrSUc013579@zion.cs.uiuc.edu>

Author: lattner
Date: Thu Jan 29 12:53:28 2009
New Revision: 63325

URL: http://llvm.org/viewvc/llvm-project?rev=63325&view=rev
Log:
Fix windows build, patch by Marius Wachtler!

Modified:
    llvm/trunk/lib/System/Win32/DynamicLibrary.inc

Modified: llvm/trunk/lib/System/Win32/DynamicLibrary.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/DynamicLibrary.inc?rev=63325&r1=63324&r2=63325&view=diff

==============================================================================
--- llvm/trunk/lib/System/Win32/DynamicLibrary.inc (original)
+++ llvm/trunk/lib/System/Win32/DynamicLibrary.inc Thu Jan 29 12:53:28 2009
@@ -156,8 +156,8 @@
 
 void* DynamicLibrary::SearchForAddressOfSymbol(const char* symbolName) {
   // First check symbols added via AddSymbol().
-  std::map::iterator I = g_symbols.find(symbolName);
-  if (I != g_symbols.end())
+  std::map::iterator I = g_symbols().find(symbolName);
+  if (I != g_symbols().end())
     return I->second;
 
   // Now search the libraries.




From gohman at apple.com  Thu Jan 29 13:49:28 2009
From: gohman at apple.com (Dan Gohman)
Date: Thu, 29 Jan 2009 19:49:28 -0000
Subject: [llvm-commits] [llvm] r63328 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Message-ID: <200901291949.n0TJnS9B015382@zion.cs.uiuc.edu>

Author: djg
Date: Thu Jan 29 13:49:27 2009
New Revision: 63328

URL: http://llvm.org/viewvc/llvm-project?rev=63328&view=rev
Log:
Make a few things const, fix some comments, and simplify
some assertions.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=63328&r1=63327&r2=63328&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu Jan 29 13:49:27 2009
@@ -91,7 +91,7 @@
     return Topo.IsReachable(SU, TargetSU);
   }
 
-  /// willCreateCycle - Returns true if adding an edge from SU to TargetSU will
+  /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
   /// create a cycle.
   bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
     return Topo.WillCreateCycle(SU, TargetSU);
@@ -114,8 +114,8 @@
   }
 
 private:
-  void ReleasePred(SUnit *SU, SDep *PredEdge);
-  void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
+  void ReleasePred(SUnit *SU, const SDep *PredEdge);
+  void ReleaseSucc(SUnit *SU, const SDep *SuccEdge);
   void CapturePred(SDep *PredEdge);
   void ScheduleNodeBottomUp(SUnit*, unsigned);
   void ScheduleNodeTopDown(SUnit*, unsigned);
@@ -192,7 +192,7 @@
 
 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
 /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
-void ScheduleDAGRRList::ReleasePred(SUnit *SU, SDep *PredEdge) {
+void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {
   SUnit *PredSU = PredEdge->getSUnit();
   --PredSU->NumSuccsLeft;
   
@@ -312,8 +312,7 @@
 }
 
 /// BacktrackBottomUp - Backtrack scheduling to a previous cycle specified in
-/// BTCycle in order to schedule a specific node. Returns the last unscheduled
-/// SUnit. Also returns if a successor is unscheduled in the process.
+/// BTCycle in order to schedule a specific node.
 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, unsigned BtCycle,
                                           unsigned &CurCycle) {
   SUnit *OldSU = NULL;
@@ -327,11 +326,7 @@
     --CurCycle;
   }
 
-      
-  if (SU->isSucc(OldSU)) {
-    assert(false && "Something is wrong!");
-    abort();
-  }
+  assert(!SU->isSucc(OldSU) && "Something is wrong!");
 
   ++NumBacktracks;
 }
@@ -751,10 +746,7 @@
         CurSU = NewDef;
       }
 
-      if (!CurSU) {
-        assert(false && "Unable to resolve live physical register dependencies!");
-        abort();
-      }
+      assert(CurSU && "Unable to resolve live physical register dependencies!");
     }
 
     // Add the nodes that aren't ready back onto the available list.
@@ -785,7 +777,7 @@
 
 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
 /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
-void ScheduleDAGRRList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
+void ScheduleDAGRRList::ReleaseSucc(SUnit *SU, const SDep *SuccEdge) {
   SUnit *SuccSU = SuccEdge->getSUnit();
   --SuccSU->NumPredsLeft;
   




From gohman at apple.com  Thu Jan 29 13:55:21 2009
From: gohman at apple.com (Dan Gohman)
Date: Thu, 29 Jan 2009 11:55:21 -0800
Subject: [llvm-commits] [llvm-gcc-4.2] r63076 -
	in	/llvm-gcc-4.2/trunk/gcc:
	config/i386/llvm-i386-target.h	llvm-backend.cpp
In-Reply-To: <6DC71425-DB85-4D65-A6A9-55EBB7A340FD@apple.com>
References: <200901270042.n0R0gBEq000456@zion.cs.uiuc.edu>
	<6DC71425-DB85-4D65-A6A9-55EBB7A340FD@apple.com>
Message-ID: <305BA886-088A-42D8-9993-9C0BDA21B80F@apple.com>

In GCC there are comments about using the red zone on i386 in
contexts where measures have been taken to guarantee that
it is safe.

Dan

On Jan 28, 2009, at 10:33 PM, Evan Cheng wrote:

> Hi Dan,
>
> This seems to pass --disable-red-zone when target is i386. Obviously
> it causes no harm but it seems a bit strange. Is it intended?
>
> Evan
>
> On Jan 26, 2009, at 4:42 PM, Dan Gohman wrote:
>
>> Author: djg
>> Date: Mon Jan 26 18:42:11 2009
>> New Revision: 63076
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=63076&view=rev
>> Log:
>> Translate GCC's -mno-red-zone option to LLVM's -disable-red-zone
>> option.
>>
>> Modified:
>>   llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h
>>   llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
>>
>> Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=63076&r1=63075&r2=63076&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h (original)
>> +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Mon Jan 26
>> 18:42:11 2009
>> @@ -89,6 +89,10 @@
>>    }                                                           \
>>  }
>>
>> +#define LLVM_SET_ARCH_OPTIONS(argvec)                           \
>> +  if (TARGET_NO_RED_ZONE)                                       \
>> +    argvec.push_back("--disable-red-zone");
>> +
>> #ifdef LLVM_ABI_H
>>
>> /* On x86-32 objects containing SSE vectors are 16 byte aligned,
>> everything
>>
>> Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=63076&r1=63075&r2=63076&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
>> +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Mon Jan 26 18:42:11 2009
>> @@ -131,6 +131,9 @@
>>
>>  // Allow targets to specify PIC options and other stuff to the
>> corresponding
>>  // LLVM backends.
>> +#ifdef LLVM_SET_ARCH_OPTIONS
>> +  LLVM_SET_ARCH_OPTIONS(Args);
>> +#endif
>> #ifdef LLVM_SET_TARGET_OPTIONS
>>  LLVM_SET_TARGET_OPTIONS(Args);
>> #endif
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From isanbard at gmail.com  Thu Jan 29 14:51:37 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 29 Jan 2009 20:51:37 -0000
Subject: [llvm-commits] [llvm] r63331 - /llvm/tags/Apple/llvmCore-2096/
Message-ID: <200901292051.n0TKpbkA017535@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 14:51:37 2009
New Revision: 63331

URL: http://llvm.org/viewvc/llvm-project?rev=63331&view=rev
Log:
Creating llvmCore-2096 branch

Added:
    llvm/tags/Apple/llvmCore-2096/
      - copied from r63330, llvm/trunk/



From isanbard at gmail.com  Thu Jan 29 14:51:46 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 29 Jan 2009 20:51:46 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63332 -
	/llvm-gcc-4.2/tags/Apple/llvmgcc42-2096/
Message-ID: <200901292051.n0TKpkGp017553@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 14:51:46 2009
New Revision: 63332

URL: http://llvm.org/viewvc/llvm-project?rev=63332&view=rev
Log:
Creating llvmgcc42-2096 branch

Added:
    llvm-gcc-4.2/tags/Apple/llvmgcc42-2096/
      - copied from r63331, llvm-gcc-4.2/trunk/



From gohman at apple.com  Thu Jan 29 15:02:43 2009
From: gohman at apple.com (Dan Gohman)
Date: Thu, 29 Jan 2009 21:02:43 -0000
Subject: [llvm-commits] [llvm] r63333 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Message-ID: <200901292102.n0TL2iMU017928@zion.cs.uiuc.edu>

Author: djg
Date: Thu Jan 29 15:02:43 2009
New Revision: 63333

URL: http://llvm.org/viewvc/llvm-project?rev=63333&view=rev
Log:
Explicitly add PseudoSourceValue information when lowering
BUILD_VECTOR and conversions to stack operations.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63333&r1=63332&r2=63333&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Jan 29 15:02:43 2009
@@ -5375,7 +5375,8 @@
   
   FrameIndexSDNode *StackPtrFI = cast(FIPtr);
   int SPFI = StackPtrFI->getIndex();
-  
+  const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
+
   unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
   unsigned SlotSize = SlotVT.getSizeInBits();
   unsigned DestSize = DestVT.getSizeInBits();
@@ -5388,21 +5389,19 @@
   
   if (SrcSize > SlotSize)
     Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
-                              PseudoSourceValue::getFixedStack(SPFI), 0,
-                              SlotVT, false, SrcAlign);
+                              SV, 0, SlotVT, false, SrcAlign);
   else {
     assert(SrcSize == SlotSize && "Invalid store");
     Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
-                         PseudoSourceValue::getFixedStack(SPFI), 0,
-                         false, SrcAlign);
+                         SV, 0, false, SrcAlign);
   }
   
   // Result is a load from the stack slot.
   if (SlotSize == DestSize)
-    return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
+    return DAG.getLoad(DestVT, Store, FIPtr, SV, 0, false, DestAlign);
   
   assert(SlotSize < DestSize && "Unknown extension!");
-  return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
+  return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, SV, 0, SlotVT,
                         false, DestAlign);
 }
 
@@ -5568,7 +5567,9 @@
   MVT VT = Node->getValueType(0);
   // Create the stack frame object.
   SDValue FIPtr = DAG.CreateStackTemporary(VT);
-  
+  int FI = cast(FIPtr.getNode())->getIndex();
+  const Value *SV = PseudoSourceValue::getFixedStack(FI);
+
   // Emit a store of each element to the stack slot.
   SmallVector Stores;
   unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
@@ -5583,7 +5584,7 @@
     Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
     
     Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 
-                                  NULL, 0));
+                                  SV, Offset));
   }
   
   SDValue StoreChain;
@@ -5594,7 +5595,7 @@
     StoreChain = DAG.getEntryNode();
   
   // Result is a load from the stack slot.
-  return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
+  return DAG.getLoad(VT, StoreChain, FIPtr, SV, 0);
 }
 
 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,




From isanbard at gmail.com  Thu Jan 29 15:38:40 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 29 Jan 2009 13:38:40 -0800
Subject: [llvm-commits] [llvm] r63328 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
In-Reply-To: <200901291949.n0TJnS9B015382@zion.cs.uiuc.edu>
References: <200901291949.n0TJnS9B015382@zion.cs.uiuc.edu>
Message-ID: <16e5fdf90901291338g24f53e5fj957363ef3d9ef97c@mail.gmail.com>

On Thu, Jan 29, 2009 at 11:49 AM, Dan Gohman  wrote:
> Author: djg
> Date: Thu Jan 29 13:49:27 2009
> New Revision: 63328
>
> URL: http://llvm.org/viewvc/llvm-project?rev=63328&view=rev
> Log:
> Make a few things const, fix some comments, and simplify
> some assertions.
>
> -
> -  if (SU->isSucc(OldSU)) {
> -    assert(false && "Something is wrong!");
> -    abort();
> -  }
> +  assert(!SU->isSucc(OldSU) && "Something is wrong!");
>
Are you sure you want to get rid of the "abort()" calls? If assertions
are turned off, then the aborts would cause an ICE in this case, which
might have been the original purpose...

-bw


From isanbard at gmail.com  Thu Jan 29 15:53:43 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 29 Jan 2009 21:53:43 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63334 -
	/llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h
Message-ID: <200901292153.n0TLrh8J020148@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 15:53:43 2009
New Revision: 63334

URL: http://llvm.org/viewvc/llvm-project?rev=63334&view=rev
Log:
Now that we acutally support stack protectors, change this to match Apple GCC's
version. Otherwise, we get spurious warnings.

Modified:
    llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h

Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h?rev=63334&r1=63333&r2=63334&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h (original)
+++ llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Thu Jan 29 15:53:43 2009
@@ -1214,13 +1214,7 @@
 
    On the RS/6000, we grow upwards, from the area after the outgoing
    arguments.  */
-/* LLVM LOCAL - begin stack protector */
-#ifdef ENABLE_LLVM
-#define FRAME_GROWS_DOWNWARD 0
-#else
 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0)
-#endif
-/* LLVM LOCAL - end stack protector */
 
 
 /* Size of the outgoing register save area */




From isanbard at gmail.com  Thu Jan 29 15:54:29 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 29 Jan 2009 21:54:29 -0000
Subject: [llvm-commits] [llvm] r63335 - /llvm/tags/Apple/llvmCore-2096/
Message-ID: <200901292154.n0TLsU4U020201@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 15:54:29 2009
New Revision: 63335

URL: http://llvm.org/viewvc/llvm-project?rev=63335&view=rev
Log:
Redo tag.

Removed:
    llvm/tags/Apple/llvmCore-2096/



From isanbard at gmail.com  Thu Jan 29 15:54:42 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 29 Jan 2009 21:54:42 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63336 -
	/llvm-gcc-4.2/tags/Apple/llvmgcc42-2096/
Message-ID: <200901292154.n0TLsguP020234@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 15:54:42 2009
New Revision: 63336

URL: http://llvm.org/viewvc/llvm-project?rev=63336&view=rev
Log:
Redo tag.

Removed:
    llvm-gcc-4.2/tags/Apple/llvmgcc42-2096/



From isanbard at gmail.com  Thu Jan 29 15:59:07 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 29 Jan 2009 21:59:07 -0000
Subject: [llvm-commits] [llvm] r63337 - /llvm/tags/Apple/llvmCore-2096/
Message-ID: <200901292159.n0TLx7v1020415@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 15:59:06 2009
New Revision: 63337

URL: http://llvm.org/viewvc/llvm-project?rev=63337&view=rev
Log:
Creating llvmCore-2096 branch

Added:
    llvm/tags/Apple/llvmCore-2096/
      - copied from r63336, llvm/trunk/



From isanbard at gmail.com  Thu Jan 29 15:59:16 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 29 Jan 2009 21:59:16 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63338 -
	/llvm-gcc-4.2/tags/Apple/llvmgcc42-2096/
Message-ID: <200901292159.n0TLxGLc020430@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 15:59:16 2009
New Revision: 63338

URL: http://llvm.org/viewvc/llvm-project?rev=63338&view=rev
Log:
Creating llvmgcc42-2096 branch

Added:
    llvm-gcc-4.2/tags/Apple/llvmgcc42-2096/
      - copied from r63337, llvm-gcc-4.2/trunk/



From resistor at mac.com  Thu Jan 29 16:13:07 2009
From: resistor at mac.com (Owen Anderson)
Date: Thu, 29 Jan 2009 22:13:07 -0000
Subject: [llvm-commits] [llvm] r63339 -
	/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
Message-ID: <200901292213.n0TMD7h0021158@zion.cs.uiuc.edu>

Author: resistor
Date: Thu Jan 29 16:13:06 2009
New Revision: 63339

URL: http://llvm.org/viewvc/llvm-project?rev=63339&view=rev
Log:
Correct the algorithms for choosing spill and restore points so that we don't try to insert loads/stores between call frame setup and the actual call.

This fixes the last known failure for the pre-alloc-splitter.

Modified:
    llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp

Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=63339&r1=63338&r2=63339&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original)
+++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Thu Jan 29 16:13:06 2009
@@ -50,6 +50,7 @@
     MachineFunction       *CurrMF;
     const TargetMachine   *TM;
     const TargetInstrInfo *TII;
+    const TargetRegisterInfo* TRI;
     MachineFrameInfo      *MFI;
     MachineRegisterInfo   *MRI;
     LiveIntervals         *LIs;
@@ -223,12 +224,21 @@
         Pt = MII;
         SpillIndex = Gap;
         break;
-      }
+      
+      // We can't insert the spill between the barrier (a call), and its
+      // corresponding call frame setup.
+      } else if (prior(MII)->getOpcode() == TRI->getCallFrameSetupOpcode() &&
+                 MII == MachineBasicBlock::iterator(MI))
+        break;
     } while (MII != EndPt);
   } else {
     MachineBasicBlock::iterator MII = MI;
     MachineBasicBlock::iterator EndPt = DefMI
       ? MachineBasicBlock::iterator(DefMI) : MBB->begin();
+    
+    // We can't insert the spill between the barrier (a call), and its
+    // corresponding call frame setup.
+    if (prior(MII)->getOpcode() == TRI->getCallFrameSetupOpcode()) --MII;
     while (MII != EndPt && !RefsInMBB.count(MII)) {
       unsigned Index = LIs->getInstructionIndex(MII);
       if (LIs->hasGapBeforeInstr(Index)) {
@@ -269,12 +279,22 @@
         Pt = MII;
         RestoreIndex = Gap;
         break;
-      }
+      
+      // We can't insert a restore between the barrier (a call) and its 
+      // corresponding call frame teardown.
+      } else if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode() &&
+                 prior(MII) == MachineBasicBlock::iterator(MI))
+        break;
       --MII;
     } while (MII != EndPt);
   } else {
     MachineBasicBlock::iterator MII = MI;
     MII = ++MII;
+    // We can't insert a restore between the barrier (a call) and its 
+    // corresponding call frame teardown.
+    if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode())
+      ++MII;
+    
     // FIXME: Limit the number of instructions to examine to reduce
     // compile time?
     while (MII != MBB->getFirstTerminator()) {
@@ -1291,6 +1311,7 @@
 bool PreAllocSplitting::runOnMachineFunction(MachineFunction &MF) {
   CurrMF = &MF;
   TM     = &MF.getTarget();
+  TRI    = TM->getRegisterInfo();
   TII    = TM->getInstrInfo();
   MFI    = MF.getFrameInfo();
   MRI    = &MF.getRegInfo();




From resistor at mac.com  Thu Jan 29 16:27:56 2009
From: resistor at mac.com (Owen Anderson)
Date: Thu, 29 Jan 2009 22:27:56 -0000
Subject: [llvm-commits] [llvm] r63340 -
	/llvm/trunk/test/CodeGen/X86/pre-split1.ll
Message-ID: <200901292227.n0TMRu3J021891@zion.cs.uiuc.edu>

Author: resistor
Date: Thu Jan 29 16:27:56 2009
New Revision: 63340

URL: http://llvm.org/viewvc/llvm-project?rev=63340&view=rev
Log:
XFAIL this test.  It only worked before because of a bug in the spill point selection code.  Not deleting because 
it should be possible to enhance the selection code to handle this in the future.

Modified:
    llvm/trunk/test/CodeGen/X86/pre-split1.ll

Modified: llvm/trunk/test/CodeGen/X86/pre-split1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split1.ll?rev=63340&r1=63339&r2=63340&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/pre-split1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pre-split1.ll Thu Jan 29 16:27:56 2009
@@ -1,5 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
 ; RUN:   grep {pre-alloc-split} | grep {Number of intervals split} | grep 1
+; XFAIL: *
 
 define void @test(double* %P, i32 %cond) nounwind {
 entry:




From isanbard at gmail.com  Thu Jan 29 17:19:43 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 29 Jan 2009 23:19:43 -0000
Subject: [llvm-commits] [llvm] r63342 -
	/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
Message-ID: <200901292319.n0TNJh9T023625@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 17:19:43 2009
New Revision: 63342

URL: http://llvm.org/viewvc/llvm-project?rev=63342&view=rev
Log:
Explain why this is here.

Modified:
    llvm/trunk/utils/TableGen/DAGISelEmitter.cpp

Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=63342&r1=63341&r2=63342&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Thu Jan 29 17:19:43 2009
@@ -1060,6 +1060,7 @@
       std::string Code = "Opc" + utostr(OpcNo);
 
       if (!isRoot || (InputHasChain && !NodeHasChain))
+        // For call to "getTargetNode()".
         Code += ", N.getDebugLoc()";
 
       emitOpcode(II.Namespace + "::" + II.TheDef->getName());




From clattner at apple.com  Thu Jan 29 17:31:35 2009
From: clattner at apple.com (Chris Lattner)
Date: Thu, 29 Jan 2009 15:31:35 -0800
Subject: [llvm-commits] [llvm] r63328 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
In-Reply-To: <16e5fdf90901291338g24f53e5fj957363ef3d9ef97c@mail.gmail.com>
References: <200901291949.n0TJnS9B015382@zion.cs.uiuc.edu>
	<16e5fdf90901291338g24f53e5fj957363ef3d9ef97c@mail.gmail.com>
Message-ID: <0CBA6CBB-B04D-417E-9FC9-3F09B0EB57E6@apple.com>


On Jan 29, 2009, at 1:38 PM, Bill Wendling wrote:

> On Thu, Jan 29, 2009 at 11:49 AM, Dan Gohman  wrote:
>> Author: djg
>> Date: Thu Jan 29 13:49:27 2009
>> New Revision: 63328
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=63328&view=rev
>> Log:
>> Make a few things const, fix some comments, and simplify
>> some assertions.
>>
>> -
>> -  if (SU->isSucc(OldSU)) {
>> -    assert(false && "Something is wrong!");
>> -    abort();
>> -  }
>> +  assert(!SU->isSucc(OldSU) && "Something is wrong!");
>>
> Are you sure you want to get rid of the "abort()" calls? If assertions
> are turned off, then the aborts would cause an ICE in this case, which
> might have been the original purpose...

I strongly prefer the new code.  assertions "can never fire", so it is  
the right thing to do.

-Chris


From evan.cheng at apple.com  Thu Jan 29 17:39:04 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 29 Jan 2009 23:39:04 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r63344 -
	/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Message-ID: <200901292339.n0TNd46u024251@zion.cs.uiuc.edu>

Author: evancheng
Date: Thu Jan 29 17:39:04 2009
New Revision: 63344

URL: http://llvm.org/viewvc/llvm-project?rev=63344&view=rev
Log:
- Split createOptimizationPasses() into two. Now we initialize the per module pass manager after all the functions are processed. This allows it to scan the list and find out whether always-inline pass is actually needed.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=63344&r1=63343&r2=63344&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Thu Jan 29 17:39:04 2009
@@ -104,8 +104,8 @@
 static PassManager *PerModulePasses = 0;
 static FunctionPassManager *CodeGenPasses = 0;
 
-static void createOptimizationPasses();
-bool OptimizationPassesCreated = false;
+static void createPerFunctionOptimizationPasses();
+static void createPerModuleOptimizationPasses();
 static void destroyOptimizationPasses();
 
 // Forward decl visibility style to global.
@@ -298,7 +298,7 @@
     exit(1);
   }
 
-  if (OptimizationPassesCreated) {
+  if (PerFunctionPasses || PerModulePasses) {
     destroyOptimizationPasses();
 
     // Don't run codegen, when we should output PCH
@@ -321,8 +321,6 @@
   AsmOutRawStream = new raw_os_ostream(*AsmOutStream);
   AsmOutFile = new OStream(*AsmOutStream);
 
-  assert(!OptimizationPassesCreated);
-  OptimizationPassesCreated = true;
   PerModulePasses = new PassManager();
   PerModulePasses->add(new TargetData(*TheTarget->getTargetData()));
 
@@ -344,9 +342,6 @@
 }
 
 static void destroyOptimizationPasses() {
-  assert(OptimizationPassesCreated ||
-         (!PerFunctionPasses && !PerModulePasses && !CodeGenPasses));
-
   delete PerFunctionPasses;
   delete PerModulePasses;
   delete CodeGenPasses;
@@ -354,16 +349,11 @@
   PerFunctionPasses = 0;
   PerModulePasses   = 0;
   CodeGenPasses     = 0;
-  OptimizationPassesCreated = false;
 }
 
-static void createOptimizationPasses() {
-  assert(OptimizationPassesCreated ||
-         (!PerFunctionPasses && !PerModulePasses && !CodeGenPasses));
-
-  if (OptimizationPassesCreated)
+static void createPerFunctionOptimizationPasses() {
+  if (PerFunctionPasses) 
     return;
-  OptimizationPassesCreated = true;
 
   // Create and set up the per-function pass manager.
   // FIXME: Move the code generator to be function-at-a-time.
@@ -388,19 +378,73 @@
     PerFunctionPasses->add(createInstructionCombiningPass());
   }
 
+  // If there are no module-level passes that have to be run, we codegen as
+  // each function is parsed.
+  // FIXME: We can't figure this out until we know there are no always-inline
+  // functions.
+  // FIXME: This is disabled right now until bugs can be worked out.  Reenable
+  // this for fast -O0 compiles!
+  if (!emit_llvm_bc && !emit_llvm && 0) {
+    FunctionPassManager *PM = PerFunctionPasses;    
+    HasPerFunctionPasses = true;
+
+    // Normal mode, emit a .s file by running the code generator.
+    // Note, this also adds codegenerator level optimization passes.
+    switch (TheTarget->addPassesToEmitFile(*PM, *AsmOutRawStream,
+                                           TargetMachine::AssemblyFile,
+                                           /*FAST*/optimize == 0)) {
+    default:
+    case FileModel::Error:
+      cerr << "Error interfacing to target machine!\n";
+      exit(1);
+    case FileModel::AsmFile:
+      break;
+    }
+
+    if (TheTarget->addPassesToEmitFileFinish(*PM, 0, /*Fast*/optimize == 0)) {
+      cerr << "Error interfacing to target machine!\n";
+      exit(1);
+    }
+  }
+  
+  if (HasPerFunctionPasses) {
+    PerFunctionPasses->doInitialization();
+  } else {
+    delete PerFunctionPasses;
+    PerFunctionPasses = 0;
+  }
+}
+
+static void createPerModuleOptimizationPasses() {
+  if (PerModulePasses)
+    // llvm_pch_write_init has already created the per module passes.
+    return;
+
   // FIXME: AT -O0/O1, we should stream out functions at a time.
   PerModulePasses = new PassManager();
   PerModulePasses->add(new TargetData(*TheTarget->getTargetData()));
   bool HasPerModulePasses = false;
+  bool NeedAlwaysInliner = false;
+  if (flag_inline_trees <= 1) {
+    // If full inliner is not run, check if always-inline is needed to handle
+    // functions that are  marked as always_inline.
+    for (Module::iterator I = TheModule->begin(), E = TheModule->end();
+         I != E; ++I)
+      if (I->hasFnAttr(Attribute::AlwaysInline)) {
+        NeedAlwaysInliner = true;
+        break;
+      }
+  }
 
   if (!DisableLLVMOptimizations) {
     HasPerModulePasses = true;
-    if (optimize == 0)
-      // Unless all LLVM optimizations are disabled, always run
-      // always-inline pass.
-      PerModulePasses->add(createAlwaysInlinerPass());
-    else {
-      PassManager *PM = PerModulePasses;
+    PassManager *PM = PerModulePasses;
+    if (optimize == 0) {
+      if (flag_inline_trees > 1)                // respect -fno-inline-functions
+        PM->add(createFunctionInliningPass());    // Inline small functions
+      else if (NeedAlwaysInliner)
+        PM->add(createAlwaysInlinerPass());       // Inline always_inline funcs
+    } else {
       if (flag_unit_at_a_time)
         PM->add(createRaiseAllocationsPass());    // call %malloc -> malloc inst
       PM->add(createCFGSimplificationPass());     // Clean up disgusting code
@@ -420,7 +464,7 @@
       }
       if (flag_inline_trees > 1)                // respect -fno-inline-functions
         PM->add(createFunctionInliningPass());    // Inline small functions
-      else
+      else if (NeedAlwaysInliner)
         PM->add(createAlwaysInlinerPass());       // Inline always_inline funcs
       if (optimize > 2)
         PM->add(createArgumentPromotionPass());   // Scalarize uninlined fn args
@@ -479,55 +523,43 @@
     PerModulePasses->add(createPrintModulePass(AsmOutRawStream));
     HasPerModulePasses = true;
   } else {
-    FunctionPassManager *PM;
-    
     // If there are passes we have to run on the entire module, we do codegen
     // as a separate "pass" after that happens.
+    // However if there are no module-level passes that have to be run, we
+    // codegen as each function is parsed.
     // FIXME: This is disabled right now until bugs can be worked out.  Reenable
     // this for fast -O0 compiles!
-    if (HasPerModulePasses || 1) {
-      CodeGenPasses = PM =
+    if (PerModulePasses || 1) {
+      FunctionPassManager *PM = CodeGenPasses =
         new FunctionPassManager(new ExistingModuleProvider(TheModule));
       PM->add(new TargetData(*TheTarget->getTargetData()));
-    } else {
-      // If there are no module-level passes that have to be run, we codegen as
-      // each function is parsed.
-      PM = PerFunctionPasses;
-      HasPerFunctionPasses = true;
-    }
 
-    // Normal mode, emit a .s file by running the code generator.
-    // Note, this also adds codegenerator level optimization passes.
-    switch (TheTarget->addPassesToEmitFile(*PM, *AsmOutRawStream,
-                                           TargetMachine::AssemblyFile,
-                                           /*FAST*/optimize == 0)) {
-    default:
-    case FileModel::Error:
-      cerr << "Error interfacing to target machine!\n";
-      exit(1);
-    case FileModel::AsmFile:
-      break;
-    }
+      // Normal mode, emit a .s file by running the code generator.
+      // Note, this also adds codegenerator level optimization passes.
+      switch (TheTarget->addPassesToEmitFile(*PM, *AsmOutRawStream,
+                                             TargetMachine::AssemblyFile,
+                                             /*FAST*/optimize == 0)) {
+      default:
+      case FileModel::Error:
+        cerr << "Error interfacing to target machine!\n";
+        exit(1);
+      case FileModel::AsmFile:
+        break;
+      }
 
-    if (TheTarget->addPassesToEmitFileFinish(*PM, 0, /*Fast*/optimize == 0)) {
-      cerr << "Error interfacing to target machine!\n";
-      exit(1);
+      if (TheTarget->addPassesToEmitFileFinish(*PM, 0, /*Fast*/optimize == 0)) {
+        cerr << "Error interfacing to target machine!\n";
+        exit(1);
+      }
     }
   }
-  
-  if (HasPerFunctionPasses) {
-    PerFunctionPasses->doInitialization();
-  } else {
-    delete PerFunctionPasses;
-    PerFunctionPasses = 0;
-  }
+
   if (!HasPerModulePasses) {
     delete PerModulePasses;
     PerModulePasses = 0;
   }
 }
 
-
 // llvm_asm_file_start - Start the .s file.
 void llvm_asm_file_start(void) {
   timevar_push(TV_LLVM_INIT);
@@ -583,7 +615,7 @@
   timevar_push(TV_LLVM_PERFILE);
 
   performLateBackendInitialization();
-  createOptimizationPasses();
+  createPerFunctionOptimizationPasses();
 
   if (flag_pch_file) {
     writeLLVMTypesStringTable();
@@ -677,7 +709,9 @@
     delete AsmIntermediateOutFile;
     AsmIntermediateOutFile = 0;
   }
+
   // Run module-level optimizers, if any are present.
+  createPerModuleOptimizationPasses();
   if (PerModulePasses)
     PerModulePasses->run(*TheModule);
   
@@ -743,7 +777,7 @@
 #endif
 
   performLateBackendInitialization();
-  createOptimizationPasses();
+  createPerFunctionOptimizationPasses();
 
   if (PerFunctionPasses)
     PerFunctionPasses->run(*Fn);




From isanbard at gmail.com  Thu Jan 29 18:45:57 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 30 Jan 2009 00:45:57 -0000
Subject: [llvm-commits] [llvm] r63350 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <200901300045.n0U0jvIJ026501@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 18:45:56 2009
New Revision: 63350

URL: http://llvm.org/viewvc/llvm-project?rev=63350&view=rev
Log:
Add DebugLoc propagation to some of the methods in DAG combiner.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63350&r1=63349&r2=63350&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 29 18:45:56 2009
@@ -196,7 +196,7 @@
     SDValue visitVECTOR_SHUFFLE(SDNode *N);
 
     SDValue XformToShuffleWithZero(SDNode *N);
-    SDValue ReassociateOps(unsigned Opc, SDValue LHS, SDValue RHS);
+    SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
     
     SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
 
@@ -390,12 +390,12 @@
     
     // -(A+B) -> -A - B
     if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
-      return DAG.getNode(ISD::FSUB, Op.getValueType(),
+      return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
                          GetNegatedExpression(Op.getOperand(0), DAG, 
                                               LegalOperations, Depth+1),
                          Op.getOperand(1));
     // -(A+B) -> -B - A
-    return DAG.getNode(ISD::FSUB, Op.getValueType(),
+    return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
                        GetNegatedExpression(Op.getOperand(1), DAG, 
                                             LegalOperations, Depth+1),
                        Op.getOperand(0));
@@ -409,8 +409,8 @@
         return Op.getOperand(1);
     
     // -(A-B) -> B-A
-    return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1),
-                       Op.getOperand(0));
+    return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
+                       Op.getOperand(1), Op.getOperand(0));
     
   case ISD::FMUL:
   case ISD::FDIV:
@@ -418,24 +418,24 @@
     
     // -(X*Y) -> -X * Y
     if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
-      return DAG.getNode(Op.getOpcode(), Op.getValueType(),
+      return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
                          GetNegatedExpression(Op.getOperand(0), DAG, 
                                               LegalOperations, Depth+1),
                          Op.getOperand(1));
       
     // -(X*Y) -> X * -Y
-    return DAG.getNode(Op.getOpcode(), Op.getValueType(),
+    return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
                        Op.getOperand(0),
                        GetNegatedExpression(Op.getOperand(1), DAG,
                                             LegalOperations, Depth+1));
     
   case ISD::FP_EXTEND:
   case ISD::FSIN:
-    return DAG.getNode(Op.getOpcode(), Op.getValueType(),
+    return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
                        GetNegatedExpression(Op.getOperand(0), DAG, 
                                             LegalOperations, Depth+1));
   case ISD::FP_ROUND:
-      return DAG.getNode(ISD::FP_ROUND, Op.getValueType(),
+      return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
                          GetNegatedExpression(Op.getOperand(0), DAG, 
                                               LegalOperations, Depth+1),
                          Op.getOperand(1));
@@ -479,34 +479,41 @@
   return false;
 }
 
-SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDValue N0, SDValue N1){
+SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
+                                    SDValue N0, SDValue N1) {
   MVT VT = N0.getValueType();
-  // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
-  // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
   if (N0.getOpcode() == Opc && isa(N0.getOperand(1))) {
     if (isa(N1)) {
-      SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
+      // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
+      SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
+                                   N0.getOperand(1), N1);
       AddToWorkList(OpNode.getNode());
-      return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
+      return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(0));
     } else if (N0.hasOneUse()) {
-      SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
+      // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
+      SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
+                                   N0.getOperand(0), N1);
       AddToWorkList(OpNode.getNode());
-      return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
+      return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
     }
   }
-  // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
-  // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
+
   if (N1.getOpcode() == Opc && isa(N1.getOperand(1))) {
     if (isa(N0)) {
-      SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
+      // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
+      SDValue OpNode = DAG.getNode(Opc, N1.getDebugLoc(), VT,
+                                   N1.getOperand(1), N0);
       AddToWorkList(OpNode.getNode());
-      return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
+      return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(0));
     } else if (N1.hasOneUse()) {
-      SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
+      // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
+      SDValue OpNode = DAG.getNode(Opc, N1.getDebugLoc(), VT,
+                                   N1.getOperand(0), N0);
       AddToWorkList(OpNode.getNode());
-      return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
+      return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
     }
   }
+
   return SDValue();
 }
 
@@ -1021,7 +1028,7 @@
                                          N0C->getAPIntValue(), VT),
                          N0.getOperand(1));
   // reassociate add
-  SDValue RADD = ReassociateOps(ISD::ADD, N0, N1);
+  SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
   if (RADD.getNode() != 0)
     return RADD;
   // fold ((0-A) + B) -> B-A
@@ -1329,7 +1336,7 @@
   }
   
   // reassociate mul
-  SDValue RMUL = ReassociateOps(ISD::MUL, N0, N1);
+  SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
   if (RMUL.getNode() != 0)
     return RMUL;
 
@@ -1752,7 +1759,7 @@
                                    APInt::getAllOnesValue(BitWidth)))
     return DAG.getConstant(0, VT);
   // reassociate and
-  SDValue RAND = ReassociateOps(ISD::AND, N0, N1);
+  SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
   if (RAND.getNode() != 0)
     return RAND;
   // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
@@ -1952,7 +1959,7 @@
   if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
     return N1;
   // reassociate or
-  SDValue ROR = ReassociateOps(ISD::OR, N0, N1);
+  SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
   if (ROR.getNode() != 0)
     return ROR;
   // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
@@ -2244,7 +2251,7 @@
   if (N1C && N1C->isNullValue())
     return N0;
   // reassociate xor
-  SDValue RXOR = ReassociateOps(ISD::XOR, N0, N1);
+  SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
   if (RXOR.getNode() != 0)
     return RXOR;
 




From dpatel at apple.com  Thu Jan 29 19:03:11 2009
From: dpatel at apple.com (Devang Patel)
Date: Fri, 30 Jan 2009 01:03:11 -0000
Subject: [llvm-commits] [llvm] r63353 - in /llvm/trunk:
 include/llvm/Analysis/DebugInfo.h lib/Analysis/DebugInfo.cpp
Message-ID: <200901300103.n0U13BcR027073@zion.cs.uiuc.edu>

Author: dpatel
Date: Thu Jan 29 19:03:10 2009
New Revision: 63353

URL: http://llvm.org/viewvc/llvm-project?rev=63353&view=rev
Log:
Add dump() routines to help debug debug info :)

Modified:
    llvm/trunk/include/llvm/Analysis/DebugInfo.h
    llvm/trunk/lib/Analysis/DebugInfo.cpp

Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=63353&r1=63352&r2=63353&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Thu Jan 29 19:03:10 2009
@@ -114,6 +114,9 @@
 
     /// Verify - Verify that a compile unit is well formed.
     bool Verify() const;
+
+    /// dump - print compile unit.
+    void dump() const;
   };
 
   /// DIEnumerator - A wrapper for an enumerator (e.g. X and Y in 'enum {X,Y}').
@@ -189,6 +192,9 @@
       assert (0 && "Invalid DIDescriptor");
       return "";
     }
+
+    /// dump - print type.
+    void dump() const;
   };
 
   /// DIBasicType - A basic type, like 'int' or 'float'.
@@ -199,6 +205,9 @@
     unsigned getEncoding() const { return getUnsignedField(9); }
     std::string getFilename() const { return getStringField(10); }
     std::string getDirectory() const { return getStringField(11); }
+
+    /// dump - print basic type.
+    void dump() const;
   };
 
   /// DIDerivedType - A simple derived type, like a const qualified type,
@@ -213,6 +222,9 @@
     DIType getTypeDerivedFrom() const { return getFieldAs(9); }
     std::string getFilename() const { return getStringField(10); }
     std::string getDirectory() const { return getStringField(11); }
+
+    /// dump - print derived type.
+    void dump() const;
   };
 
   /// DICompositeType - This descriptor holds a type that can refer to multiple
@@ -228,6 +240,9 @@
 
     /// Verify - Verify that a composite type descriptor is well formed.
     bool Verify() const;
+
+    /// dump - print composite type.
+    void dump() const;
   };
 
   /// DIGlobal - This is a common class for global variables and subprograms.
@@ -273,6 +288,9 @@
       assert (0 && "Invalid DIDescriptor");
       return "";
     }
+    
+    /// dump - print global.
+    void dump() const;
   };
 
   /// DISubprogram - This is a wrapper for a subprogram (e.g. a function).
@@ -285,6 +303,9 @@
 
     /// Verify - Verify that a subprogram descriptor is well formed.
     bool Verify() const;
+
+    /// dump - print subprogram.
+    void dump() const;
   };
 
   /// DIGlobalVariable - This is a wrapper for a global variable.
@@ -298,6 +319,9 @@
 
     /// Verify - Verify that a global variable descriptor is well formed.
     bool Verify() const;
+
+    /// dump - print global variable.
+    void dump() const;
   };
 
   /// DIVariable - This is a wrapper for a variable (e.g. parameter, local,
@@ -319,6 +343,9 @@
 
     /// Verify - Verify that a variable descriptor is well formed.
     bool Verify() const;
+
+    /// dump - print variable.
+    void dump() const;
   };
 
   /// DIBlock - This is a wrapper for a block (e.g. a function, scope, etc).

Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=63353&r1=63352&r2=63353&view=diff

==============================================================================
--- llvm/trunk/lib/Analysis/DebugInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/DebugInfo.cpp Thu Jan 29 19:03:10 2009
@@ -20,6 +20,7 @@
 #include "llvm/Instructions.h"
 #include "llvm/Module.h"
 #include "llvm/Analysis/ValueTracking.h"
+#include "llvm/Support/Streams.h"
 using namespace llvm;
 
 //===----------------------------------------------------------------------===//
@@ -870,3 +871,103 @@
   }
 }
 
+/// dump - print compile unit.
+void DICompileUnit::dump() const {
+  cerr << " [" << dwarf::LanguageString(getLanguage()) << "] ";
+  cerr << " [" << getDirectory() << "/" << getFilename() << " ]";
+}
+
+/// dump - print type.
+void DIType::dump() const {
+  if (isNull()) return;
+  if (!getName().empty())
+    cerr << " [" << getName() << "] ";
+  unsigned Tag = getTag();
+  cerr << " [" << dwarf::TagString(Tag) << "] ";
+  // TODO : Print context
+  getCompileUnit().dump();
+  cerr << " [" 
+       << getLineNumber() << ", " 
+       << getSizeInBits() << ", "
+       << getAlignInBits() << ", "
+       << getOffsetInBits() 
+       << "] ";
+  if (isPrivate()) 
+    cerr << " [private] ";
+  else if (isProtected())
+    cerr << " [protected] ";
+  if (isForwardDecl())
+    cerr << " [fwd] ";
+
+  if (isBasicType(Tag))
+    DIBasicType(GV).dump();
+  else if (isDerivedType(Tag))
+    DIDerivedType(GV).dump();
+  else if (isCompositeType(Tag))
+    DICompositeType(GV).dump();
+  else {
+    cerr << "Invalid DIType\n";
+    return;
+  }
+  cerr << "\n";
+}
+
+/// dump - print basic type.
+void DIBasicType::dump() const {
+  cerr << " [" << dwarf::AttributeEncodingString(getEncoding()) << "] ";
+
+}
+
+/// dump - print derived type.
+void DIDerivedType::dump() const {
+  cerr << "\n\t Derived From: "; getTypeDerivedFrom().dump();
+}
+
+/// dump - print composite type.
+void DICompositeType::dump() const {
+  DIArray A = getTypeArray();
+  if (A.isNull())
+    return;
+  cerr << " [" << A.getNumElements() << " elements]";
+}
+
+/// dump - print global.
+void DIGlobal::dump() const {
+
+  if (!getName().empty())
+    cerr << " [" << getName() << "] ";
+  unsigned Tag = getTag();
+  cerr << " [" << dwarf::TagString(Tag) << "] ";
+  // TODO : Print context
+  getCompileUnit().dump();
+  cerr << " [" << getLineNumber() << "] ";
+  if (isLocalToUnit())
+    cerr << " [local] ";
+  if (isDefinition())
+    cerr << " [def] ";
+
+  if (isGlobalVariable(Tag))
+    DIGlobalVariable(GV).dump();
+
+  cerr << "\n";
+}
+
+/// dump - print subprogram.
+void DISubprogram::dump() const {
+  DIGlobal::dump();
+}
+
+/// dump - print global variable.
+void DIGlobalVariable::dump() const {
+  cerr << " ["; getGlobal()->dump(); cerr << "] ";
+}
+
+/// dump - print variable.
+void DIVariable::dump() const {
+  if (!getName().empty())
+    cerr << " [" << getName() << "] ";
+  getCompileUnit().dump();
+  cerr << " [" << getLineNumber() << "] ";
+  getType().dump();
+  cerr << "\n";
+}




From isanbard at gmail.com  Thu Jan 29 19:13:17 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 30 Jan 2009 01:13:17 -0000
Subject: [llvm-commits] [llvm] r63355 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <200901300113.n0U1DH6c027375@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 19:13:16 2009
New Revision: 63355

URL: http://llvm.org/viewvc/llvm-project?rev=63355&view=rev
Log:
Propagate debug location info for the token factor.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63355&r1=63354&r2=63355&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 29 19:13:16 2009
@@ -770,7 +770,6 @@
 }
 
 SDValue DAGCombiner::combine(SDNode *N) {
-
   SDValue RV = visit(N);
 
   // If nothing happened, try a target-specific DAG combine.
@@ -796,6 +795,7 @@
       N->getNumValues() == 1) {
     SDValue N0 = N->getOperand(0);
     SDValue N1 = N->getOperand(1);
+
     // Constant operands are canonicalized to RHS.
     if (isa(N0) || !isa(N1)) {
       SDValue Ops[] = { N1, N0 };
@@ -821,7 +821,7 @@
       if (N->getOperand(i).getValueType() == MVT::Other)
         return N->getOperand(i);
   }
-  return SDValue(0, 0);
+  return SDValue();
 }
 
 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
@@ -890,9 +890,10 @@
       Result = DAG.getEntryNode();
     } else {
       // New and improved token factor.
-      Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
+      Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
+                           MVT::Other, &Ops[0], Ops.size());
     }
-    
+
     // Don't add users to work list.
     return CombineTo(N, Result, false);
   }
@@ -911,7 +912,6 @@
   return SDValue(N, 0);   // Return N so it doesn't get rechecked!
 }
 
-
 static
 SDValue combineShlAddConstant(SDValue N0, SDValue N1, SelectionDAG &DAG) {
   MVT VT = N0.getValueType();




From dpatel at apple.com  Thu Jan 29 19:21:46 2009
From: dpatel at apple.com (Devang Patel)
Date: Fri, 30 Jan 2009 01:21:46 -0000
Subject: [llvm-commits] [llvm] r63356 - in /llvm/trunk:
 lib/CodeGen/AsmPrinter/DwarfWriter.cpp
 test/DebugInfo/2009-01-29-MethodDeclaration.ll
Message-ID: <200901300121.n0U1Lln8027637@zion.cs.uiuc.edu>

Author: dpatel
Date: Thu Jan 29 19:21:46 2009
New Revision: 63356

URL: http://llvm.org/viewvc/llvm-project?rev=63356&view=rev
Log:
Add DW_AT_declaration for class methods.

Added:
    llvm/trunk/test/DebugInfo/2009-01-29-MethodDeclaration.ll
Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=63356&r1=63355&r2=63356&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Thu Jan 29 19:21:46 2009
@@ -1965,9 +1965,12 @@
         AddUInt(Arg, DW_AT_artificial, DW_FORM_flag, 1); // ???
         SPDie->AddChild(Arg);
       }
-    
+
+    if (!SP.isDefinition())
+      AddUInt(SPDie, DW_AT_declaration, DW_FORM_flag, 1);
+
     if (!SP.isLocalToUnit())
-      AddUInt(SPDie, DW_AT_external, DW_FORM_flag, 1);                     
+      AddUInt(SPDie, DW_AT_external, DW_FORM_flag, 1);
     return SPDie;
   }
 

Added: llvm/trunk/test/DebugInfo/2009-01-29-MethodDeclaration.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2009-01-29-MethodDeclaration.ll?rev=63356&view=auto

==============================================================================
--- llvm/trunk/test/DebugInfo/2009-01-29-MethodDeclaration.ll (added)
+++ llvm/trunk/test/DebugInfo/2009-01-29-MethodDeclaration.ll Thu Jan 29 19:21:46 2009
@@ -0,0 +1,31 @@
+; RUN: llvm-as < %s | llc | grep 0x3C | count 1
+; Check DW_AT_declaration attribute for class method foo.
+	%llvm.dbg.anchor.type = type { i32, i32 }
+	%llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32, i8*, i8* }
+	%llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i8* }
+	%llvm.dbg.composite.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, { }*, i8*, i8* }
+	%llvm.dbg.derivedtype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, i8*, i8* }
+	%llvm.dbg.global_variable.type = type { i32, { }*, { }*, i8*, i8*, i8*, { }*, i32, { }*, i1, i1, { }*, i8*, i8* }
+	%llvm.dbg.subprogram.type = type { i32, { }*, { }*, i8*, i8*, i8*, { }*, i32, { }*, i1, i1, i8*, i8* }
+	%struct.A = type <{ i8 }>
+ at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata"		; <%llvm.dbg.anchor.type*> [#uses=1]
+ at .str = internal constant [6 x i8] c"cl.cc\00", section "llvm.metadata"		; <[6 x i8]*> [#uses=1]
+ at .str1 = internal constant [26 x i8] c"/Volumes/Nanpura/dbg.test\00", section "llvm.metadata"		; <[26 x i8]*> [#uses=1]
+ at .str2 = internal constant [52 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build)\00", section "llvm.metadata"		; <[52 x i8]*> [#uses=1]
+ at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 4, i8* getelementptr ([6 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([52 x i8]* @.str2, i32 0, i32 0), i1 false, i8* null }, section "llvm.metadata"		; <%llvm.dbg.compile_unit.type*> [#uses=1]
+ at a = global %struct.A zeroinitializer		; <%struct.A*> [#uses=1]
+ at .str3 = internal constant [2 x i8] c"A\00", section "llvm.metadata"		; <[2 x i8]*> [#uses=1]
+ at .str4 = internal constant [4 x i8] c"int\00", section "llvm.metadata"		; <[4 x i8]*> [#uses=1]
+ at llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str4, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, i32 5, i8* null, i8* null }, section "llvm.metadata"		; <%llvm.dbg.basictype.type*> [#uses=1]
+ at llvm.dbg.derivedtype = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite9 to { }*), i8* null, i8* null }, section "llvm.metadata"		; <%llvm.dbg.derivedtype.type*> [#uses=1]
+ at llvm.dbg.array = internal constant [2 x { }*] [ { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*) ], section "llvm.metadata"		; <[2 x { }*]*> [#uses=1]
+ at llvm.dbg.composite5 = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([2 x { }*]* @llvm.dbg.array to { }*), i8* null, i8* null }, section "llvm.metadata"		; <%llvm.dbg.composite.type*> [#uses=1]
+ at llvm.dbg.subprograms = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 46 }, section "llvm.metadata"		; <%llvm.dbg.anchor.type*> [#uses=1]
+ at .str6 = internal constant [4 x i8] c"foo\00", section "llvm.metadata"		; <[4 x i8]*> [#uses=1]
+ at .str7 = internal constant [12 x i8] c"_ZN1A3fooEv\00", section "llvm.metadata"		; <[12 x i8]*> [#uses=1]
+ at llvm.dbg.subprogram = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str6, i32 0, i32 0), i8* getelementptr ([4 x i8]* @.str6, i32 0, i32 0), i8* getelementptr ([12 x i8]* @.str7, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 4, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite5 to { }*), i1 false, i1 false, i8* getelementptr ([6 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0) }, section "llvm.metadata"		; <%llvm.dbg.subprogram.type*> [#uses=1]
+ at llvm.dbg.array8 = internal constant [1 x { }*] [ { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*) ], section "llvm.metadata"		; <[1 x { }*]*> [#uses=1]
+ at llvm.dbg.composite9 = internal constant %llvm.dbg.composite.type { i32 458771, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([2 x i8]* @.str3, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 2, i64 8, i64 8, i64 0, i32 0, { }* null, { }* bitcast ([1 x { }*]* @llvm.dbg.array8 to { }*), i8* getelementptr ([6 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0) }, section "llvm.metadata"		; <%llvm.dbg.composite.type*> [#uses=1]
+ at llvm.dbg.global_variables = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 52 }, section "llvm.metadata"		; <%llvm.dbg.anchor.type*> [#uses=1]
+ at .str10 = internal constant [2 x i8] c"a\00", section "llvm.metadata"		; <[2 x i8]*> [#uses=1]
+ at llvm.dbg.global_variable = internal constant %llvm.dbg.global_variable.type { i32 458804, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.global_variables to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([2 x i8]* @.str10, i32 0, i32 0), i8* getelementptr ([2 x i8]* @.str10, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 7, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite9 to { }*), i1 false, i1 true, { }* bitcast (%struct.A* @a to { }*), i8* getelementptr ([6 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0) }, section "llvm.metadata"		; <%llvm.dbg.global_variable.type*> [#uses=0]




From dpatel at apple.com  Thu Jan 29 19:25:47 2009
From: dpatel at apple.com (Devang Patel)
Date: Fri, 30 Jan 2009 01:25:47 -0000
Subject: [llvm-commits] [llvm] r63357 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
Message-ID: <200901300125.n0U1PlFS027779@zion.cs.uiuc.edu>

Author: dpatel
Date: Thu Jan 29 19:25:47 2009
New Revision: 63357

URL: http://llvm.org/viewvc/llvm-project?rev=63357&view=rev
Log:
Remove dead code.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=63357&r1=63356&r2=63357&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Thu Jan 29 19:25:47 2009
@@ -1650,16 +1650,6 @@
     AddDIEntry(Entity, DW_AT_type, DW_FORM_ref4, BasicTypeDie);
   }
 
-  /// AddPointerType - Add a new pointer type attribute to the specified entity.
-  ///
-  void AddPointerType(DIE *Entity, CompileUnit *Unit, const std::string &Name) {
-    DIE Buffer(DW_TAG_pointer_type);
-    AddUInt(&Buffer, DW_AT_byte_size, 0, TD->getPointerSize());
-    if (!Name.empty()) AddString(&Buffer, DW_AT_name, DW_FORM_string, Name);
-    DIE *PointerTypeDie =  Unit->AddDie(Buffer);
-    AddDIEntry(Entity, DW_AT_type, DW_FORM_ref4, PointerTypeDie);
-  }
-
   /// AddType - Add a new type attribute to the specified entity.
   void AddType(CompileUnit *DW_Unit, DIE *Entity, DIType Ty) {
     if (Ty.isNull())




From dpatel at apple.com  Thu Jan 29 19:27:49 2009
From: dpatel at apple.com (Devang Patel)
Date: Fri, 30 Jan 2009 01:27:49 -0000
Subject: [llvm-commits] [llvm] r63358 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
Message-ID: <200901300127.n0U1Rn83027856@zion.cs.uiuc.edu>

Author: dpatel
Date: Thu Jan 29 19:27:49 2009
New Revision: 63358

URL: http://llvm.org/viewvc/llvm-project?rev=63358&view=rev
Log:
Remove dead code, again.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=63358&r1=63357&r2=63358&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Thu Jan 29 19:27:49 2009
@@ -1636,20 +1636,6 @@
     AddBlock(Die, Attribute, 0, Block);
   }
 
-  /// AddBasicType - Add a new basic type attribute to the specified entity.
-  ///
-  void AddBasicType(DIE *Entity, CompileUnit *Unit,
-                    const std::string &Name,
-                    unsigned Encoding, unsigned Size) {
-
-    DIE Buffer(DW_TAG_base_type);
-    AddUInt(&Buffer, DW_AT_byte_size, 0, Size);
-    AddUInt(&Buffer, DW_AT_encoding, DW_FORM_data1, Encoding);
-    if (!Name.empty()) AddString(&Buffer, DW_AT_name, DW_FORM_string, Name);
-    DIE *BasicTypeDie = Unit->AddDie(Buffer);
-    AddDIEntry(Entity, DW_AT_type, DW_FORM_ref4, BasicTypeDie);
-  }
-
   /// AddType - Add a new type attribute to the specified entity.
   void AddType(CompileUnit *DW_Unit, DIE *Entity, DIType Ty) {
     if (Ty.isNull())




From dalej at apple.com  Thu Jan 29 19:34:22 2009
From: dalej at apple.com (Dale Johannesen)
Date: Fri, 30 Jan 2009 01:34:22 -0000
Subject: [llvm-commits] [llvm] r63359 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAG.h
 lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
Message-ID: <200901300134.n0U1YM1H028081@zion.cs.uiuc.edu>

Author: johannes
Date: Thu Jan 29 19:34:22 2009
New Revision: 63359

URL: http://llvm.org/viewvc/llvm-project?rev=63359&view=rev
Log:
Propagate debug info when building SelectionDAG.


Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63359&r1=63358&r2=63359&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Thu Jan 29 19:34:22 2009
@@ -79,6 +79,9 @@
   MachineModuleInfo *MMI;
   DwarfWriter *DW;
 
+  /// CurDebugLoc - current file + line number.  Changes as we build the DAG.
+  DebugLoc CurDebugLoc;
+
   /// EntryNode - The starting token.
   SDNode EntryNode;
 
@@ -137,6 +140,7 @@
   FunctionLoweringInfo &getFunctionLoweringInfo() const { return FLI; }
   MachineModuleInfo *getMachineModuleInfo() const { return MMI; }
   DwarfWriter *getDwarfWriter() const { return DW; }
+  DebugLoc getCurDebugLoc() const { return CurDebugLoc; }
 
   /// viewGraph - Pop up a GraphViz/gv window with the DAG rendered using 'dot'.
   ///
@@ -195,6 +199,8 @@
     return Root = N;
   }
 
+  void setCurDebugLoc(DebugLoc dl) { CurDebugLoc = dl; }
+
   /// Combine - This iterates over the nodes in the SelectionDAG, folding
   /// certain types of nodes together, or eliminating superfluous nodes.  The
   /// Level argument controls whether Combine is allowed to produce nodes and

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63359&r1=63358&r2=63359&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Thu Jan 29 19:34:22 2009
@@ -404,12 +404,14 @@
         Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
                               PartVT, HalfVT);
       } else {
-        Lo = DAG.getNode(ISD::BIT_CONVERT, HalfVT, Parts[0]);
-        Hi = DAG.getNode(ISD::BIT_CONVERT, HalfVT, Parts[1]);
+        Lo = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(),
+                                           HalfVT, Parts[0]);
+        Hi = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(),
+                                           HalfVT, Parts[1]);
       }
       if (TLI.isBigEndian())
         std::swap(Lo, Hi);
-      Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
+      Val = DAG.getNode(ISD::BUILD_PAIR, DAG.getCurDebugLoc(), RoundVT, Lo, Hi);
 
       if (RoundParts < NumParts) {
         // Assemble the trailing non-power-of-2 part.
@@ -422,12 +424,12 @@
         if (TLI.isBigEndian())
           std::swap(Lo, Hi);
         MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
-        Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
-        Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
+        Hi = DAG.getNode(ISD::ANY_EXTEND, DAG.getCurDebugLoc(), TotalVT, Hi);
+        Hi = DAG.getNode(ISD::SHL, DAG.getCurDebugLoc(), TotalVT, Hi,
                          DAG.getConstant(Lo.getValueType().getSizeInBits(),
                                          TLI.getShiftAmountTy()));
-        Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
-        Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
+        Lo = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), TotalVT, Lo);
+        Val = DAG.getNode(ISD::OR, DAG.getCurDebugLoc(), TotalVT, Lo, Hi);
       }
     } else {
       // Handle a multi-element vector.
@@ -465,6 +467,7 @@
       // operands.
       Val = DAG.getNode(IntermediateVT.isVector() ?
                         ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
+                        DAG.getCurDebugLoc(),
                         ValueVT, &Ops[0], NumIntermediates);
     }
   }
@@ -477,14 +480,14 @@
 
   if (PartVT.isVector()) {
     assert(ValueVT.isVector() && "Unknown vector conversion!");
-    return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
+    return DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), ValueVT, Val);
   }
 
   if (ValueVT.isVector()) {
     assert(ValueVT.getVectorElementType() == PartVT &&
            ValueVT.getVectorNumElements() == 1 &&
            "Only trivial scalar-to-vector conversions should get here!");
-    return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
+    return DAG.getNode(ISD::BUILD_VECTOR, DAG.getCurDebugLoc(), ValueVT, Val);
   }
 
   if (PartVT.isInteger() &&
@@ -494,24 +497,24 @@
       // indicate whether the truncated bits will always be
       // zero or sign-extension.
       if (AssertOp != ISD::DELETED_NODE)
-        Val = DAG.getNode(AssertOp, PartVT, Val,
+        Val = DAG.getNode(AssertOp, DAG.getCurDebugLoc(), PartVT, Val,
                           DAG.getValueType(ValueVT));
-      return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
+      return DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), ValueVT, Val);
     } else {
-      return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
+      return DAG.getNode(ISD::ANY_EXTEND, DAG.getCurDebugLoc(), ValueVT, Val);
     }
   }
 
   if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
     if (ValueVT.bitsLT(Val.getValueType()))
       // FP_ROUND's are always exact here.
-      return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
+      return DAG.getNode(ISD::FP_ROUND, DAG.getCurDebugLoc(), ValueVT, Val,
                          DAG.getIntPtrConstant(1));
-    return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
+    return DAG.getNode(ISD::FP_EXTEND, DAG.getCurDebugLoc(), ValueVT, Val);
   }
 
   if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
-    return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
+    return DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), ValueVT, Val);
 
   assert(0 && "Unknown mismatch!");
   return SDValue();
@@ -543,22 +546,22 @@
       // If the parts cover more bits than the value has, promote the value.
       if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
         assert(NumParts == 1 && "Do not know what to promote to!");
-        Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
+        Val = DAG.getNode(ISD::FP_EXTEND, DAG.getCurDebugLoc(), PartVT, Val);
       } else if (PartVT.isInteger() && ValueVT.isInteger()) {
         ValueVT = MVT::getIntegerVT(NumParts * PartBits);
-        Val = DAG.getNode(ExtendKind, ValueVT, Val);
+        Val = DAG.getNode(ExtendKind, DAG.getCurDebugLoc(), ValueVT, Val);
       } else {
         assert(0 && "Unknown mismatch!");
       }
     } else if (PartBits == ValueVT.getSizeInBits()) {
       // Different types of the same size.
       assert(NumParts == 1 && PartVT != ValueVT);
-      Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
+      Val = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), PartVT, Val);
     } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
       // If the parts cover less bits than value has, truncate the value.
       if (PartVT.isInteger() && ValueVT.isInteger()) {
         ValueVT = MVT::getIntegerVT(NumParts * PartBits);
-        Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
+        Val = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), ValueVT, Val);
       } else {
         assert(0 && "Unknown mismatch!");
       }
@@ -583,7 +586,7 @@
       unsigned RoundParts = 1 << Log2_32(NumParts);
       unsigned RoundBits = RoundParts * PartBits;
       unsigned OddParts = NumParts - RoundParts;
-      SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
+      SDValue OddVal = DAG.getNode(ISD::SRL, DAG.getCurDebugLoc(), ValueVT, Val,
                                    DAG.getConstant(RoundBits,
                                                    TLI.getShiftAmountTy()));
       getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
@@ -592,12 +595,12 @@
         std::reverse(Parts + RoundParts, Parts + NumParts);
       NumParts = RoundParts;
       ValueVT = MVT::getIntegerVT(NumParts * PartBits);
-      Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
+      Val = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), ValueVT, Val);
     }
 
     // The number of parts is a power of 2.  Repeatedly bisect the value using
     // EXTRACT_ELEMENT.
-    Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
+    Parts[0] = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), 
                            MVT::getIntegerVT(ValueVT.getSizeInBits()),
                            Val);
     for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
@@ -607,14 +610,18 @@
         SDValue &Part0 = Parts[i];
         SDValue &Part1 = Parts[i+StepSize/2];
 
-        Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
+        Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DAG.getCurDebugLoc(), 
+                            ThisVT, Part0,
                             DAG.getConstant(1, PtrVT));
-        Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
+        Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DAG.getCurDebugLoc(), 
+                            ThisVT, Part0,
                             DAG.getConstant(0, PtrVT));
 
         if (ThisBits == PartBits && ThisVT != PartVT) {
-          Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
-          Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
+          Part0 = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), 
+                                                PartVT, Part0);
+          Part1 = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), 
+                                                PartVT, Part1);
         }
       }
     }
@@ -629,12 +636,13 @@
   if (NumParts == 1) {
     if (PartVT != ValueVT) {
       if (PartVT.isVector()) {
-        Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
+        Val = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), PartVT, Val);
       } else {
         assert(ValueVT.getVectorElementType() == PartVT &&
                ValueVT.getVectorNumElements() == 1 &&
                "Only trivial vector-to-scalar conversions should get here!");
-        Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
+        Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DAG.getCurDebugLoc(), 
+                          PartVT, Val,
                           DAG.getConstant(0, PtrVT));
       }
     }
@@ -659,12 +667,12 @@
   SmallVector Ops(NumIntermediates);
   for (unsigned i = 0; i != NumIntermediates; ++i)
     if (IntermediateVT.isVector())
-      Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
+      Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DAG.getCurDebugLoc(), 
                            IntermediateVT, Val,
                            DAG.getConstant(i * (NumElements / NumIntermediates),
                                            PtrVT));
     else
-      Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
+      Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DAG.getCurDebugLoc(), 
                            IntermediateVT, Val,
                            DAG.getConstant(i, PtrVT));
 
@@ -722,7 +730,7 @@
   }
 
   // Otherwise, we have to make a token factor node.
-  SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
+  SDValue Root = DAG.getNode(ISD::TokenFactor, DAG.getCurDebugLoc(), MVT::Other,
                                &PendingLoads[0], PendingLoads.size());
   PendingLoads.clear();
   DAG.setRoot(Root);
@@ -752,7 +760,7 @@
       PendingExports.push_back(Root);
   }
 
-  Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
+  Root = DAG.getNode(ISD::TokenFactor, DAG.getCurDebugLoc(), MVT::Other,
                      &PendingExports[0],
                      PendingExports.size());
   PendingExports.clear();
@@ -812,7 +820,7 @@
 
     if (isa(C) && !isa(V->getType()) &&
         !V->getType()->isAggregateType())
-      return N = DAG.getNode(ISD::UNDEF, VT);
+      return N = DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), VT);
 
     if (ConstantExpr *CE = dyn_cast(C)) {
       visit(CE->getOpcode(), *CE);
@@ -845,7 +853,7 @@
       for (unsigned i = 0; i != NumElts; ++i) {
         MVT EltVT = ValueVTs[i];
         if (isa(C))
-          Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
+          Constants[i] = DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), EltVT);
         else if (EltVT.isFloatingPoint())
           Constants[i] = DAG.getConstantFP(0, EltVT);
         else
@@ -870,7 +878,7 @@
 
       SDValue Op;
       if (isa(C))
-        Op = DAG.getNode(ISD::UNDEF, EltVT);
+        Op = DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), EltVT);
       else if (EltVT.isFloatingPoint())
         Op = DAG.getConstantFP(0, EltVT);
       else
@@ -879,7 +887,8 @@
     }
 
     // Create a BUILD_VECTOR node.
-    return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
+    return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, DAG.getCurDebugLoc(), 
+                                    VT, &Ops[0], Ops.size());
   }
 
   // If this is a static alloca, generate it as the frameindex instead of
@@ -902,7 +911,8 @@
 
 void SelectionDAGLowering::visitRet(ReturnInst &I) {
   if (I.getNumOperands() == 0) {
-    DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
+    DAG.setRoot(DAG.getNode(ISD::RET, DAG.getCurDebugLoc(), 
+                            MVT::Other, getControlRoot()));
     return;
   }
 
@@ -951,7 +961,7 @@
       }
     }
   }
-  DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
+  DAG.setRoot(DAG.getNode(ISD::RET, DAG.getCurDebugLoc(), MVT::Other,
                           &NewValues[0], NewValues.size()));
 }
 
@@ -1191,7 +1201,8 @@
 
     // If this is not a fall-through branch, emit the branch.
     if (Succ0MBB != NextBlock)
-      DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
+      DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), 
+                              MVT::Other, getControlRoot(),
                               DAG.getBasicBlock(Succ0MBB)));
     return;
   }
@@ -1270,7 +1281,8 @@
       Cond = CondLHS;
     else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
       SDValue True = DAG.getConstant(1, CondLHS.getValueType());
-      Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
+      Cond = DAG.getNode(ISD::XOR, DAG.getCurDebugLoc(), 
+                         CondLHS.getValueType(), CondLHS, True);
     } else
       Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
   } else {
@@ -1285,7 +1297,8 @@
     if (cast(CB.CmpLHS)->isMinValue(true)) {
       Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
     } else {
-      SDValue SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
+      SDValue SUB = DAG.getNode(ISD::SUB, DAG.getCurDebugLoc(), 
+                                VT, CmpOp, DAG.getConstant(Low, VT));
       Cond = DAG.getSetCC(MVT::i1, SUB,
                           DAG.getConstant(High-Low, VT), ISD::SETULE);
     }
@@ -1307,10 +1320,12 @@
   if (CB.TrueBB == NextBlock) {
     std::swap(CB.TrueBB, CB.FalseBB);
     SDValue True = DAG.getConstant(1, Cond.getValueType());
-    Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
+    Cond = DAG.getNode(ISD::XOR, DAG.getCurDebugLoc(), 
+                       Cond.getValueType(), Cond, True);
   }
-  SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
-                                 DAG.getBasicBlock(CB.TrueBB));
+  SDValue BrCond = DAG.getNode(ISD::BRCOND, DAG.getCurDebugLoc(),
+                               MVT::Other, getControlRoot(), Cond,
+                               DAG.getBasicBlock(CB.TrueBB));
 
   // If the branch was constant folded, fix up the CFG.
   if (BrCond.getOpcode() == ISD::BR) {
@@ -1324,7 +1339,7 @@
     if (CB.FalseBB == NextBlock)
       DAG.setRoot(BrCond);
     else
-      DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
+      DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), MVT::Other, BrCond,
                               DAG.getBasicBlock(CB.FalseBB)));
   }
 }
@@ -1336,7 +1351,8 @@
   MVT PTy = TLI.getPointerTy();
   SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
   SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
-  DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
+  DAG.setRoot(DAG.getNode(ISD::BR_JT, DAG.getCurDebugLoc(), 
+                          MVT::Other, Index.getValue(1),
                           Table, Index));
 }
 
@@ -1349,7 +1365,7 @@
   // difference between smallest and largest cases.
   SDValue SwitchOp = getValue(JTH.SValue);
   MVT VT = SwitchOp.getValueType();
-  SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
+  SDValue SUB = DAG.getNode(ISD::SUB, DAG.getCurDebugLoc(), VT, SwitchOp,
                             DAG.getConstant(JTH.First, VT));
 
   // The SDNode we just created, which holds the value being switched on minus
@@ -1358,9 +1374,11 @@
   // This value may be smaller or larger than the target's pointer type, and
   // therefore require extension or truncating.
   if (VT.bitsGT(TLI.getPointerTy()))
-    SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
+    SwitchOp = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), 
+                           TLI.getPointerTy(), SUB);
   else
-    SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
+    SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), 
+                           TLI.getPointerTy(), SUB);
 
   unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
   SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
@@ -1380,13 +1398,14 @@
   if (++BBI != CurMBB->getParent()->end())
     NextBlock = BBI;
 
-  SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
+  SDValue BrCond = DAG.getNode(ISD::BRCOND, DAG.getCurDebugLoc(),
+                               MVT::Other, CopyTo, CMP,
                                DAG.getBasicBlock(JT.Default));
 
   if (JT.MBB == NextBlock)
     DAG.setRoot(BrCond);
   else
-    DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
+    DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), MVT::Other, BrCond,
                             DAG.getBasicBlock(JT.MBB)));
 }
 
@@ -1396,7 +1415,7 @@
   // Subtract the minimum value
   SDValue SwitchOp = getValue(B.SValue);
   MVT VT = SwitchOp.getValueType();
-  SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
+  SDValue SUB = DAG.getNode(ISD::SUB, DAG.getCurDebugLoc(), VT, SwitchOp,
                             DAG.getConstant(B.First, VT));
 
   // Check range
@@ -1406,9 +1425,11 @@
 
   SDValue ShiftOp;
   if (VT.bitsGT(TLI.getShiftAmountTy()))
-    ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
+    ShiftOp = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), 
+                          TLI.getShiftAmountTy(), SUB);
   else
-    ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
+    ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), 
+                          TLI.getShiftAmountTy(), SUB);
 
   B.Reg = FuncInfo.MakeReg(TLI.getShiftAmountTy());
   SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), B.Reg, ShiftOp);
@@ -1425,13 +1446,14 @@
   CurMBB->addSuccessor(B.Default);
   CurMBB->addSuccessor(MBB);
 
-  SDValue BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
+  SDValue BrRange = DAG.getNode(ISD::BRCOND, DAG.getCurDebugLoc(),
+                                MVT::Other, CopyTo, RangeCmp,
                                 DAG.getBasicBlock(B.Default));
 
   if (MBB == NextBlock)
     DAG.setRoot(BrRange);
   else
-    DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
+    DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), MVT::Other, CopyTo,
                             DAG.getBasicBlock(MBB)));
 }
 
@@ -1442,12 +1464,14 @@
   // Make desired shift
   SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), Reg,
                                        TLI.getShiftAmountTy());
-  SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
+  SDValue SwitchVal = DAG.getNode(ISD::SHL, DAG.getCurDebugLoc(), 
+                                  TLI.getPointerTy(),
                                   DAG.getConstant(1, TLI.getPointerTy()),
                                   ShiftOp);
 
   // Emit bit tests and jumps
-  SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
+  SDValue AndOp = DAG.getNode(ISD::AND, DAG.getCurDebugLoc(), 
+                              TLI.getPointerTy(), SwitchVal,
                               DAG.getConstant(B.Mask, TLI.getPointerTy()));
   SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp.getValueType()),
                                 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
@@ -1456,7 +1480,8 @@
   CurMBB->addSuccessor(B.TargetBB);
   CurMBB->addSuccessor(NextMBB);
 
-  SDValue BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
+  SDValue BrAnd = DAG.getNode(ISD::BRCOND, DAG.getCurDebugLoc(),
+                              MVT::Other, getControlRoot(),
                               AndCmp, DAG.getBasicBlock(B.TargetBB));
 
   // Set NextBlock to be the MBB immediately after the current one, if any.
@@ -1469,7 +1494,7 @@
   if (NextMBB == NextBlock)
     DAG.setRoot(BrAnd);
   else
-    DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
+    DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), MVT::Other, BrAnd,
                             DAG.getBasicBlock(NextMBB)));
 }
 
@@ -1497,7 +1522,8 @@
   CurMBB->addSuccessor(LandingPad);
 
   // Drop into normal successor.
-  DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
+  DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), 
+                          MVT::Other, getControlRoot(),
                           DAG.getBasicBlock(Return)));
 }
 
@@ -2000,7 +2026,8 @@
     // If this is not a fall-through branch, emit the branch.
     CurMBB->addSuccessor(Default);
     if (Default != NextBlock)
-      DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
+      DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(),
+                              MVT::Other, getControlRoot(),
                               DAG.getBasicBlock(Default)));
     return;
   }
@@ -2062,7 +2089,8 @@
         Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
         if (CV == CNZ) {
           SDValue Op2 = getValue(I.getOperand(1));
-          setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
+          setValue(&I, DAG.getNode(ISD::FNEG, DAG.getCurDebugLoc(), 
+                                   Op2.getValueType(), Op2));
           return;
         }
       }
@@ -2072,7 +2100,8 @@
     if (ConstantFP *CFP = dyn_cast(I.getOperand(0)))
       if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
         SDValue Op2 = getValue(I.getOperand(1));
-        setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
+        setValue(&I, DAG.getNode(ISD::FNEG, DAG.getCurDebugLoc(), 
+                                 Op2.getValueType(), Op2));
         return;
       }
   }
@@ -2084,7 +2113,8 @@
   SDValue Op1 = getValue(I.getOperand(0));
   SDValue Op2 = getValue(I.getOperand(1));
 
-  setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
+  setValue(&I, DAG.getNode(OpCode, DAG.getCurDebugLoc(), 
+                           Op1.getValueType(), Op1, Op2));
 }
 
 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
@@ -2092,12 +2122,15 @@
   SDValue Op2 = getValue(I.getOperand(1));
   if (!isa(I.getType())) {
     if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
-      Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
+      Op2 = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), 
+                        TLI.getShiftAmountTy(), Op2);
     else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
-      Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
+      Op2 = DAG.getNode(ISD::ANY_EXTEND, DAG.getCurDebugLoc(), 
+                        TLI.getShiftAmountTy(), Op2);
   }
 
-  setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
+  setValue(&I, DAG.getNode(Opcode, DAG.getCurDebugLoc(), 
+                           Op1.getValueType(), Op1, Op2));
 }
 
 void SelectionDAGLowering::visitICmp(User &I) {
@@ -2161,11 +2194,12 @@
     SDValue FalseVal = getValue(I.getOperand(2));
 
     for (unsigned i = 0; i != NumValues; ++i)
-      Values[i] = DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
+      Values[i] = DAG.getNode(ISD::SELECT, DAG.getCurDebugLoc(), 
+                              TrueVal.getValueType(), Cond,
                               SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
                               SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
 
-    setValue(&I, DAG.getNode(ISD::MERGE_VALUES,
+    setValue(&I, DAG.getNode(ISD::MERGE_VALUES, DAG.getCurDebugLoc(), 
                              DAG.getVTList(&ValueVTs[0], NumValues),
                              &Values[0], NumValues));
   }
@@ -2176,7 +2210,7 @@
   // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
   SDValue N = getValue(I.getOperand(0));
   MVT DestVT = TLI.getValueType(I.getType());
-  setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
+  setValue(&I, DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), DestVT, N));
 }
 
 void SelectionDAGLowering::visitZExt(User &I) {
@@ -2184,7 +2218,7 @@
   // ZExt also can't be a cast to bool for same reason. So, nothing much to do
   SDValue N = getValue(I.getOperand(0));
   MVT DestVT = TLI.getValueType(I.getType());
-  setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
+  setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), DestVT, N));
 }
 
 void SelectionDAGLowering::visitSExt(User &I) {
@@ -2192,49 +2226,50 @@
   // SExt also can't be a cast to bool for same reason. So, nothing much to do
   SDValue N = getValue(I.getOperand(0));
   MVT DestVT = TLI.getValueType(I.getType());
-  setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
+  setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DAG.getCurDebugLoc(), DestVT, N));
 }
 
 void SelectionDAGLowering::visitFPTrunc(User &I) {
   // FPTrunc is never a no-op cast, no need to check
   SDValue N = getValue(I.getOperand(0));
   MVT DestVT = TLI.getValueType(I.getType());
-  setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
+  setValue(&I, DAG.getNode(ISD::FP_ROUND, DAG.getCurDebugLoc(), 
+                           DestVT, N, DAG.getIntPtrConstant(0)));
 }
 
 void SelectionDAGLowering::visitFPExt(User &I){
   // FPTrunc is never a no-op cast, no need to check
   SDValue N = getValue(I.getOperand(0));
   MVT DestVT = TLI.getValueType(I.getType());
-  setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
+  setValue(&I, DAG.getNode(ISD::FP_EXTEND, DAG.getCurDebugLoc(), DestVT, N));
 }
 
 void SelectionDAGLowering::visitFPToUI(User &I) {
   // FPToUI is never a no-op cast, no need to check
   SDValue N = getValue(I.getOperand(0));
   MVT DestVT = TLI.getValueType(I.getType());
-  setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
+  setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DAG.getCurDebugLoc(), DestVT, N));
 }
 
 void SelectionDAGLowering::visitFPToSI(User &I) {
   // FPToSI is never a no-op cast, no need to check
   SDValue N = getValue(I.getOperand(0));
   MVT DestVT = TLI.getValueType(I.getType());
-  setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
+  setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DAG.getCurDebugLoc(), DestVT, N));
 }
 
 void SelectionDAGLowering::visitUIToFP(User &I) {
   // UIToFP is never a no-op cast, no need to check
   SDValue N = getValue(I.getOperand(0));
   MVT DestVT = TLI.getValueType(I.getType());
-  setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
+  setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DAG.getCurDebugLoc(), DestVT, N));
 }
 
 void SelectionDAGLowering::visitSIToFP(User &I){
   // SIToFP is never a no-op cast, no need to check
   SDValue N = getValue(I.getOperand(0));
   MVT DestVT = TLI.getValueType(I.getType());
-  setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
+  setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DAG.getCurDebugLoc(), DestVT, N));
 }
 
 void SelectionDAGLowering::visitPtrToInt(User &I) {
@@ -2245,10 +2280,10 @@
   MVT DestVT = TLI.getValueType(I.getType());
   SDValue Result;
   if (DestVT.bitsLT(SrcVT))
-    Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
+    Result = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), DestVT, N);
   else
     // Note: ZERO_EXTEND can handle cases where the sizes are equal too
-    Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
+    Result = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), DestVT, N);
   setValue(&I, Result);
 }
 
@@ -2259,10 +2294,11 @@
   MVT SrcVT = N.getValueType();
   MVT DestVT = TLI.getValueType(I.getType());
   if (DestVT.bitsLT(SrcVT))
-    setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
+    setValue(&I, DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), DestVT, N));
   else
     // Note: ZERO_EXTEND can handle cases where the sizes are equal too
-    setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
+    setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), 
+                             DestVT, N));
 }
 
 void SelectionDAGLowering::visitBitCast(User &I) {
@@ -2272,7 +2308,8 @@
   // BitCast assures us that source and destination are the same size so this
   // is either a BIT_CONVERT or a no-op.
   if (DestVT != N.getValueType())
-    setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
+    setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), 
+                             DestVT, N)); // convert types
   else
     setValue(&I, N); // noop cast.
 }
@@ -2280,19 +2317,21 @@
 void SelectionDAGLowering::visitInsertElement(User &I) {
   SDValue InVec = getValue(I.getOperand(0));
   SDValue InVal = getValue(I.getOperand(1));
-  SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
+  SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), 
+                                TLI.getPointerTy(),
                                 getValue(I.getOperand(2)));
 
-  setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
+  setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, DAG.getCurDebugLoc(), 
                            TLI.getValueType(I.getType()),
                            InVec, InVal, InIdx));
 }
 
 void SelectionDAGLowering::visitExtractElement(User &I) {
   SDValue InVec = getValue(I.getOperand(0));
-  SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
+  SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), 
+                                TLI.getPointerTy(),
                                 getValue(I.getOperand(1)));
-  setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
+  setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DAG.getCurDebugLoc(),
                            TLI.getValueType(I.getType()), InVec, InIdx));
 }
 
@@ -2322,7 +2361,8 @@
   int SrcNumElts = SrcVT.getVectorNumElements();
 
   if (SrcNumElts == MaskNumElts) {
-    setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Src1, Src2, Mask));
+    setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, DAG.getCurDebugLoc(), 
+                             VT, Src1, Src2, Mask));
     return;
   }
 
@@ -2335,13 +2375,14 @@
     // lengths match.
     if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
       // The shuffle is concatenating two vectors together.
-      setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, VT, Src1, Src2));
+      setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DAG.getCurDebugLoc(), 
+                               VT, Src1, Src2));
       return;
     }
 
     // Pad both vectors with undefs to make them the same length as the mask.
     unsigned NumConcat = MaskNumElts / SrcNumElts;
-    SDValue UndefVal = DAG.getNode(ISD::UNDEF, SrcVT);
+    SDValue UndefVal = DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), SrcVT);
 
     SDValue* MOps1 = new SDValue[NumConcat];
     SDValue* MOps2 = new SDValue[NumConcat];
@@ -2351,8 +2392,10 @@
       MOps1[i] = UndefVal;
       MOps2[i] = UndefVal;
     }
-    Src1 = DAG.getNode(ISD::CONCAT_VECTORS, VT, MOps1, NumConcat);
-    Src2 = DAG.getNode(ISD::CONCAT_VECTORS, VT, MOps2, NumConcat);
+    Src1 = DAG.getNode(ISD::CONCAT_VECTORS, DAG.getCurDebugLoc(), 
+                       VT, MOps1, NumConcat);
+    Src2 = DAG.getNode(ISD::CONCAT_VECTORS, DAG.getCurDebugLoc(), 
+                       VT, MOps2, NumConcat);
 
     delete [] MOps1;
     delete [] MOps2;
@@ -2371,10 +2414,12 @@
                                               MaskEltVT));
       }
     }
-    Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
+    Mask = DAG.getNode(ISD::BUILD_VECTOR, DAG.getCurDebugLoc(), 
+                       Mask.getValueType(),
                        &MappedOps[0], MappedOps.size());
 
-    setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Src1, Src2, Mask));
+    setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, DAG.getCurDebugLoc(), 
+                             VT, Src1, Src2, Mask));
     return;
   }
 
@@ -2439,7 +2484,8 @@
     }
 
     if (RangeUse[0] == 0 && RangeUse[0] == 0) {
-      setValue(&I, DAG.getNode(ISD::UNDEF, VT));  // Vectors are not used.
+      setValue(&I, DAG.getNode(ISD::UNDEF, 
+                          DAG.getCurDebugLoc(), VT));  // Vectors are not used.
       return;
     }
     else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
@@ -2447,10 +2493,10 @@
       for (int Input=0; Input < 2; ++Input) {
         SDValue& Src = Input == 0 ? Src1 : Src2;
         if (RangeUse[Input] == 0) {
-          Src = DAG.getNode(ISD::UNDEF, VT);
+          Src = DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), VT);
         } else {
-          Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, VT, Src,
-                            DAG.getIntPtrConstant(StartIdx[Input]));
+          Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DAG.getCurDebugLoc(), VT,
+                            Src, DAG.getIntPtrConstant(StartIdx[Input]));
         }
       }
       // Calculate new mask.
@@ -2469,9 +2515,11 @@
           }
         }
       }
-      Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
+      Mask = DAG.getNode(ISD::BUILD_VECTOR, DAG.getCurDebugLoc(), 
+                         Mask.getValueType(),
                          &MappedOps[0], MappedOps.size());
-      setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Src1, Src2, Mask));
+      setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, DAG.getCurDebugLoc(), 
+                               VT, Src1, Src2, Mask));
       return;
     }
   }
@@ -2485,19 +2533,21 @@
   for (int i = 0; i != MaskNumElts; ++i) {
     SDValue Arg = Mask.getOperand(i);
     if (Arg.getOpcode() == ISD::UNDEF) {
-      Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
+      Ops.push_back(DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), EltVT));
     } else {
       assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!");
       int Idx = cast(Arg)->getZExtValue();
       if (Idx < SrcNumElts)
-        Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Src1,
-                                  DAG.getConstant(Idx, PtrVT)));
+        Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DAG.getCurDebugLoc(),
+                                  EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
       else
-        Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Src2,
+        Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DAG.getCurDebugLoc(),
+                                  EltVT, Src2, 
                                   DAG.getConstant(Idx - SrcNumElts, PtrVT)));
     }
   }
-  setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()));
+  setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, DAG.getCurDebugLoc(), 
+                           VT, &Ops[0], Ops.size()));
 }
 
 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
@@ -2525,18 +2575,21 @@
   unsigned i = 0;
   // Copy the beginning value(s) from the original aggregate.
   for (; i != LinearIndex; ++i)
-    Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
+    Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), 
+                                        AggValueVTs[i]) :
                 SDValue(Agg.getNode(), Agg.getResNo() + i);
   // Copy values from the inserted value(s).
   for (; i != LinearIndex + NumValValues; ++i)
-    Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
+    Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), 
+                                        AggValueVTs[i]) :
                 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
   // Copy remaining value(s) from the original aggregate.
   for (; i != NumAggValues; ++i)
-    Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
+    Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), 
+                                        AggValueVTs[i]) :
                 SDValue(Agg.getNode(), Agg.getResNo() + i);
 
-  setValue(&I, DAG.getNode(ISD::MERGE_VALUES,
+  setValue(&I, DAG.getNode(ISD::MERGE_VALUES, DAG.getCurDebugLoc(), 
                            DAG.getVTList(&AggValueVTs[0], NumAggValues),
                            &Values[0], NumAggValues));
 }
@@ -2561,11 +2614,11 @@
   for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
     Values[i - LinearIndex] =
       OutOfUndef ?
-        DAG.getNode(ISD::UNDEF,
+        DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), 
                     Agg.getNode()->getValueType(Agg.getResNo() + i)) :
         SDValue(Agg.getNode(), Agg.getResNo() + i);
 
-  setValue(&I, DAG.getNode(ISD::MERGE_VALUES,
+  setValue(&I, DAG.getNode(ISD::MERGE_VALUES, DAG.getCurDebugLoc(), 
                            DAG.getVTList(&ValValueVTs[0], NumValValues),
                            &Values[0], NumValValues));
 }
@@ -2583,7 +2636,7 @@
       if (Field) {
         // N = N + Offset
         uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
-        N = DAG.getNode(ISD::ADD, N.getValueType(), N,
+        N = DAG.getNode(ISD::ADD, DAG.getCurDebugLoc(), N.getValueType(), N,
                         DAG.getIntPtrConstant(Offset));
       }
       Ty = StTy->getElementType(Field);
@@ -2595,7 +2648,7 @@
         if (CI->getZExtValue() == 0) continue;
         uint64_t Offs =
             TD->getTypePaddedSize(Ty)*cast(CI)->getSExtValue();
-        N = DAG.getNode(ISD::ADD, N.getValueType(), N,
+        N = DAG.getNode(ISD::ADD, DAG.getCurDebugLoc(), N.getValueType(), N,
                         DAG.getIntPtrConstant(Offs));
         continue;
       }
@@ -2607,24 +2660,29 @@
       // If the index is smaller or larger than intptr_t, truncate or extend
       // it.
       if (IdxN.getValueType().bitsLT(N.getValueType()))
-        IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
+        IdxN = DAG.getNode(ISD::SIGN_EXTEND, DAG.getCurDebugLoc(), 
+                           N.getValueType(), IdxN);
       else if (IdxN.getValueType().bitsGT(N.getValueType()))
-        IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
+        IdxN = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), 
+                           N.getValueType(), IdxN);
 
       // If this is a multiply by a power of two, turn it into a shl
       // immediately.  This is a very common case.
       if (ElementSize != 1) {
         if (isPowerOf2_64(ElementSize)) {
           unsigned Amt = Log2_64(ElementSize);
-          IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
+          IdxN = DAG.getNode(ISD::SHL, DAG.getCurDebugLoc(), 
+                             N.getValueType(), IdxN,
                              DAG.getConstant(Amt, TLI.getShiftAmountTy()));
         } else {
           SDValue Scale = DAG.getIntPtrConstant(ElementSize);
-          IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
+          IdxN = DAG.getNode(ISD::MUL, DAG.getCurDebugLoc(), 
+                             N.getValueType(), IdxN, Scale);
         }
       }
 
-      N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
+      N = DAG.getNode(ISD::ADD, DAG.getCurDebugLoc(), 
+                      N.getValueType(), N, IdxN);
     }
   }
   setValue(&I, N);
@@ -2645,11 +2703,13 @@
   SDValue AllocSize = getValue(I.getArraySize());
   MVT IntPtr = TLI.getPointerTy();
   if (IntPtr.bitsLT(AllocSize.getValueType()))
-    AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
+    AllocSize = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), 
+                            IntPtr, AllocSize);
   else if (IntPtr.bitsGT(AllocSize.getValueType()))
-    AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
+    AllocSize = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), 
+                            IntPtr, AllocSize);
 
-  AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
+  AllocSize = DAG.getNode(ISD::MUL, DAG.getCurDebugLoc(), IntPtr, AllocSize,
                           DAG.getIntPtrConstant(TySize));
 
   // Handle alignment.  If the requested alignment is less than or equal to
@@ -2662,16 +2722,19 @@
 
   // Round the size of the allocation up to the stack alignment size
   // by add SA-1 to the size.
-  AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
+  AllocSize = DAG.getNode(ISD::ADD, DAG.getCurDebugLoc(), 
+                          AllocSize.getValueType(), AllocSize,
                           DAG.getIntPtrConstant(StackAlign-1));
   // Mask out the low bits for alignment purposes.
-  AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
+  AllocSize = DAG.getNode(ISD::AND, DAG.getCurDebugLoc(), 
+                          AllocSize.getValueType(), AllocSize,
                           DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
 
   SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
   const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
                                                     MVT::Other);
-  SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
+  SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, DAG.getCurDebugLoc(), 
+                            VTs, 2, Ops, 3);
   setValue(&I, DSA);
   DAG.setRoot(DSA.getValue(1));
 
@@ -2713,8 +2776,9 @@
   SmallVector Chains(NumValues);
   MVT PtrVT = Ptr.getValueType();
   for (unsigned i = 0; i != NumValues; ++i) {
-    SDValue L = DAG.getLoad(ValueVTs[i], Root,
-                              DAG.getNode(ISD::ADD, PtrVT, Ptr,
+    SDValue L = DAG.getLoad(ValueVTs[i], DAG.getCurDebugLoc(), Root,
+                              DAG.getNode(ISD::ADD, DAG.getCurDebugLoc(), 
+                                          PtrVT, Ptr,
                                           DAG.getConstant(Offsets[i], PtrVT)),
                               SV, Offsets[i],
                               isVolatile, Alignment);
@@ -2723,7 +2787,8 @@
   }
 
   if (!ConstantMemory) {
-    SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+    SDValue Chain = DAG.getNode(ISD::TokenFactor, DAG.getCurDebugLoc(), 
+                                  MVT::Other,
                                   &Chains[0], NumValues);
     if (isVolatile)
       DAG.setRoot(Chain);
@@ -2731,7 +2796,7 @@
       PendingLoads.push_back(Chain);
   }
 
-  setValue(&I, DAG.getNode(ISD::MERGE_VALUES,
+  setValue(&I, DAG.getNode(ISD::MERGE_VALUES, DAG.getCurDebugLoc(), 
                            DAG.getVTList(&ValueVTs[0], NumValues),
                            &Values[0], NumValues));
 }
@@ -2760,13 +2825,16 @@
   bool isVolatile = I.isVolatile();
   unsigned Alignment = I.getAlignment();
   for (unsigned i = 0; i != NumValues; ++i)
-    Chains[i] = DAG.getStore(Root, SDValue(Src.getNode(), Src.getResNo() + i),
-                             DAG.getNode(ISD::ADD, PtrVT, Ptr,
+    Chains[i] = DAG.getStore(Root, DAG.getCurDebugLoc(),
+                             SDValue(Src.getNode(), Src.getResNo() + i),
+                             DAG.getNode(ISD::ADD, DAG.getCurDebugLoc(), 
+                                         PtrVT, Ptr,
                                          DAG.getConstant(Offsets[i], PtrVT)),
                              PtrV, Offsets[i],
                              isVolatile, Alignment);
 
-  DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues));
+  DAG.setRoot(DAG.getNode(ISD::TokenFactor, DAG.getCurDebugLoc(), 
+                          MVT::Other, &Chains[0], NumValues));
 }
 
 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
@@ -2826,20 +2894,24 @@
   SDValue Result;
   if (IsTgtIntrinsic) {
     // This is target intrinsic that touches memory
-    Result = DAG.getMemIntrinsicNode(Info.opc, VTList, VTs.size(),
+    Result = DAG.getMemIntrinsicNode(Info.opc, DAG.getCurDebugLoc(),
+                                     VTList, VTs.size(),
                                      &Ops[0], Ops.size(),
                                      Info.memVT, Info.ptrVal, Info.offset,
                                      Info.align, Info.vol,
                                      Info.readMem, Info.writeMem);
   }
   else if (!HasChain)
-    Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
+    Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DAG.getCurDebugLoc(), 
+                         VTList, VTs.size(),
                          &Ops[0], Ops.size());
   else if (I.getType() != Type::VoidTy)
-    Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
+    Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DAG.getCurDebugLoc(), 
+                         VTList, VTs.size(),
                          &Ops[0], Ops.size());
   else
-    Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
+    Result = DAG.getNode(ISD::INTRINSIC_VOID, DAG.getCurDebugLoc(), 
+                         VTList, VTs.size(),
                          &Ops[0], Ops.size());
 
   if (HasChain) {
@@ -2852,7 +2924,7 @@
   if (I.getType() != Type::VoidTy) {
     if (const VectorType *PTy = dyn_cast(I.getType())) {
       MVT VT = TLI.getValueType(PTy);
-      Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
+      Result = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), VT, Result);
     }
     setValue(&I, Result);
   }
@@ -2933,11 +3005,11 @@
 /// where Op is the hexidecimal representation of floating point value.
 static SDValue
 GetSignificand(SelectionDAG &DAG, SDValue Op) {
-  SDValue t1 = DAG.getNode(ISD::AND, MVT::i32, Op,
+  SDValue t1 = DAG.getNode(ISD::AND, DAG.getCurDebugLoc(), MVT::i32, Op,
                            DAG.getConstant(0x007fffff, MVT::i32));
-  SDValue t2 = DAG.getNode(ISD::OR, MVT::i32, t1,
+  SDValue t2 = DAG.getNode(ISD::OR, DAG.getCurDebugLoc(), MVT::i32, t1,
                            DAG.getConstant(0x3f800000, MVT::i32));
-  return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t2);
+  return DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), MVT::f32, t2);
 }
 
 /// GetExponent - Get the exponent:
@@ -2947,11 +3019,11 @@
 /// where Op is the hexidecimal representation of floating point value.
 static SDValue
 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI) {
-  SDValue t0 = DAG.getNode(ISD::AND, MVT::i32, Op,
+  SDValue t0 = DAG.getNode(ISD::AND, DAG.getCurDebugLoc(), MVT::i32, Op,
                            DAG.getConstant(0x7f800000, MVT::i32));
-  SDValue t1 = DAG.getNode(ISD::SRL, MVT::i32, t0,
+  SDValue t1 = DAG.getNode(ISD::SRL, DAG.getCurDebugLoc(), MVT::i32, t0,
                            DAG.getConstant(23, TLI.getShiftAmountTy()));
-  SDValue t2 = DAG.getNode(ISD::SUB, MVT::i32, t1,
+  SDValue t2 = DAG.getNode(ISD::SUB, DAG.getCurDebugLoc(), MVT::i32, t1,
                            DAG.getConstant(127, MVT::i32));
   return DAG.getNode(ISD::SINT_TO_FP, MVT::f32, t2);
 }
@@ -2969,7 +3041,8 @@
 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
   SDValue Root = getRoot();
   SDValue L =
-    DAG.getAtomic(Op, getValue(I.getOperand(2)).getValueType().getSimpleVT(),
+    DAG.getAtomic(Op, DAG.getCurDebugLoc(),
+                  getValue(I.getOperand(2)).getValueType().getSimpleVT(),
                   Root,
                   getValue(I.getOperand(1)),
                   getValue(I.getOperand(2)),
@@ -2988,7 +3061,8 @@
   MVT ValueVTs[] = { Op1.getValueType(), MVT::i1 };
   SDValue Ops[] = { Op1, Op2 };
 
-  SDValue Result = DAG.getNode(Op, DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
+  SDValue Result = DAG.getNode(Op, DAG.getCurDebugLoc(), 
+                               DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
 
   setValue(&I, Result);
   return 0;
@@ -2999,6 +3073,7 @@
 void
 SelectionDAGLowering::visitExp(CallInst &I) {
   SDValue result;
+  DebugLoc dl = DAG.getCurDebugLoc();
 
   if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
       LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
@@ -3009,16 +3084,16 @@
     //
     //   #define LOG2OFe 1.4426950f
     //   IntegerPartOfX = ((int32_t)(X * LOG2OFe));
-    SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, Op,
+    SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
                              getF32Constant(DAG, 0x3fb8aa3b));
-    SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, MVT::i32, t0);
+    SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
 
     //   FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
-    SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, MVT::f32, IntegerPartOfX);
-    SDValue X = DAG.getNode(ISD::FSUB, MVT::f32, t0, t1);
+    SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
+    SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
 
     //   IntegerPartOfX <<= 23;
-    IntegerPartOfX = DAG.getNode(ISD::SHL, MVT::i32, IntegerPartOfX,
+    IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
                                  DAG.getConstant(23, TLI.getShiftAmountTy()));
 
     if (LimitFloatPrecision <= 6) {
@@ -3029,20 +3104,20 @@
       //       (0.735607626f + 0.252464424f * x) * x;
       //
       // error 0.0144103317, which is 6 bits
-      SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3e814304));
-      SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3f3c50c8));
-      SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3f7f5e7e));
-      SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t5);
+      SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
 
       // Add the exponent into the result in integer domain.
-      SDValue t6 = DAG.getNode(ISD::ADD, MVT::i32,
+      SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
                                TwoToFracPartOfX, IntegerPartOfX);
 
-      result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t6);
+      result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
     } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
       // For floating-point precision of 12:
       //
@@ -3052,23 +3127,23 @@
       //         (0.224338339f + 0.792043434e-1f * x) * x) * x;
       //
       // 0.000107046256 error, which is 13 to 14 bits
-      SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3da235e3));
-      SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3e65b8f3));
-      SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3f324b07));
-      SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
-      SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
                                getF32Constant(DAG, 0x3f7ff8fd));
-      SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t7);
+      SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
 
       // Add the exponent into the result in integer domain.
-      SDValue t8 = DAG.getNode(ISD::ADD, MVT::i32,
+      SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
                                TwoToFracPartOfX, IntegerPartOfX);
 
-      result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t8);
+      result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
     } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
       // For floating-point precision of 18:
       //
@@ -3081,36 +3156,37 @@
       //               (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
       //
       // error 2.47208000*10^(-7), which is better than 18 bits
-      SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3924b03e));
-      SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3ab24b87));
-      SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3c1d8c17));
-      SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
-      SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
                                getF32Constant(DAG, 0x3d634a1d));
-      SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
-      SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
+      SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+      SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
                                getF32Constant(DAG, 0x3e75fe14));
-      SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
-      SDValue t11 = DAG.getNode(ISD::FADD, MVT::f32, t10,
+      SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+      SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
                                 getF32Constant(DAG, 0x3f317234));
-      SDValue t12 = DAG.getNode(ISD::FMUL, MVT::f32, t11, X);
-      SDValue t13 = DAG.getNode(ISD::FADD, MVT::f32, t12,
+      SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
+      SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
                                 getF32Constant(DAG, 0x3f800000));
-      SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t13);
+      SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl, 
+                                             MVT::i32, t13);
 
       // Add the exponent into the result in integer domain.
-      SDValue t14 = DAG.getNode(ISD::ADD, MVT::i32,
+      SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
                                 TwoToFracPartOfX, IntegerPartOfX);
 
-      result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t14);
+      result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
     }
   } else {
     // No special expansion.
-    result = DAG.getNode(ISD::FEXP,
+    result = DAG.getNode(ISD::FEXP, dl,
                          getValue(I.getOperand(1)).getValueType(),
                          getValue(I.getOperand(1)));
   }
@@ -3123,15 +3199,16 @@
 void
 SelectionDAGLowering::visitLog(CallInst &I) {
   SDValue result;
+  DebugLoc dl = DAG.getCurDebugLoc();
 
   if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
       LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
     SDValue Op = getValue(I.getOperand(1));
-    SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
+    SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
 
     // Scale the exponent by log(2) [0.69314718f].
     SDValue Exp = GetExponent(DAG, Op1, TLI);
-    SDValue LogOfExponent = DAG.getNode(ISD::FMUL, MVT::f32, Exp,
+    SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
                                         getF32Constant(DAG, 0x3f317218));
 
     // Get the significand and build it into a floating-point number with
@@ -3146,15 +3223,16 @@
       //       (1.4034025f - 0.23903021f * x) * x;
       //
       // error 0.0034276066, which is better than 8 bits
-      SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
+      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0xbe74c456));
-      SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
+      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
                                getF32Constant(DAG, 0x3fb3a2b1));
-      SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
-      SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t2,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+      SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
                                           getF32Constant(DAG, 0x3f949a29));
 
-      result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, LogOfMantissa);
+      result = DAG.getNode(ISD::FADD, dl, 
+                           MVT::f32, LogOfExponent, LogOfMantissa);
     } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
       // For floating-point precision of 12:
       //
@@ -3165,21 +3243,22 @@
       //           (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
       //
       // error 0.000061011436, which is 14 bits
-      SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
+      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0xbd67b6d6));
-      SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
+      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
                                getF32Constant(DAG, 0x3ee4f4b8));
-      SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
-      SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+      SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3fbc278b));
-      SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x40348e95));
-      SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
-      SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
                                           getF32Constant(DAG, 0x3fdef31a));
 
-      result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, LogOfMantissa);
+      result = DAG.getNode(ISD::FADD, dl, 
+                           MVT::f32, LogOfExponent, LogOfMantissa);
     } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
       // For floating-point precision of 18:
       //
@@ -3192,31 +3271,32 @@
       //               (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
       //
       // error 0.0000023660568, which is better than 18 bits
-      SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
+      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0xbc91e5ac));
-      SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
+      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
                                getF32Constant(DAG, 0x3e4350aa));
-      SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
-      SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+      SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3f60d3e3));
-      SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x4011cdf0));
-      SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
-      SDValue t7 = DAG.getNode(ISD::FSUB, MVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
                                getF32Constant(DAG, 0x406cfd1c));
-      SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
-      SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
+      SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+      SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
                                getF32Constant(DAG, 0x408797cb));
-      SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
-      SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t10,
+      SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+      SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
                                           getF32Constant(DAG, 0x4006dcab));
 
-      result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, LogOfMantissa);
+      result = DAG.getNode(ISD::FADD, dl, 
+                           MVT::f32, LogOfExponent, LogOfMantissa);
     }
   } else {
     // No special expansion.
-    result = DAG.getNode(ISD::FLOG,
+    result = DAG.getNode(ISD::FLOG, dl,
                          getValue(I.getOperand(1)).getValueType(),
                          getValue(I.getOperand(1)));
   }
@@ -3229,11 +3309,12 @@
 void
 SelectionDAGLowering::visitLog2(CallInst &I) {
   SDValue result;
+  DebugLoc dl = DAG.getCurDebugLoc();
 
   if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
       LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
     SDValue Op = getValue(I.getOperand(1));
-    SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
+    SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
 
     // Get the exponent.
     SDValue LogOfExponent = GetExponent(DAG, Op1, TLI);
@@ -3250,15 +3331,16 @@
       //   Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
       //
       // error 0.0049451742, which is more than 7 bits
-      SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
+      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0xbeb08fe0));
-      SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
+      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
                                getF32Constant(DAG, 0x40019463));
-      SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
-      SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t2,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+      SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
                                            getF32Constant(DAG, 0x3fd6633d));
 
-      result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log2ofMantissa);
+      result = DAG.getNode(ISD::FADD, dl, 
+                           MVT::f32, LogOfExponent, Log2ofMantissa);
     } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
       // For floating-point precision of 12:
       //
@@ -3269,21 +3351,22 @@
       //           (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
       //
       // error 0.0000876136000, which is better than 13 bits
-      SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
+      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0xbda7262e));
-      SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
+      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
                                getF32Constant(DAG, 0x3f25280b));
-      SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
-      SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+      SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x4007b923));
-      SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x40823e2f));
-      SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
-      SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
                                            getF32Constant(DAG, 0x4020d29c));
 
-      result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log2ofMantissa);
+      result = DAG.getNode(ISD::FADD, dl, 
+                           MVT::f32, LogOfExponent, Log2ofMantissa);
     } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
       // For floating-point precision of 18:
       //
@@ -3297,31 +3380,32 @@
       //                 0.25691327e-1f * x) * x) * x) * x) * x) * x;
       //
       // error 0.0000018516, which is better than 18 bits
-      SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
+      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0xbcd2769e));
-      SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
+      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
                                getF32Constant(DAG, 0x3e8ce0b9));
-      SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
-      SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+      SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3fa22ae7));
-      SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x40525723));
-      SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
-      SDValue t7 = DAG.getNode(ISD::FSUB, MVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
                                getF32Constant(DAG, 0x40aaf200));
-      SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
-      SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
+      SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+      SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
                                getF32Constant(DAG, 0x40c39dad));
-      SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
-      SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t10,
+      SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+      SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
                                            getF32Constant(DAG, 0x4042902c));
 
-      result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log2ofMantissa);
+      result = DAG.getNode(ISD::FADD, dl, 
+                           MVT::f32, LogOfExponent, Log2ofMantissa);
     }
   } else {
     // No special expansion.
-    result = DAG.getNode(ISD::FLOG2,
+    result = DAG.getNode(ISD::FLOG2, dl,
                          getValue(I.getOperand(1)).getValueType(),
                          getValue(I.getOperand(1)));
   }
@@ -3334,15 +3418,16 @@
 void
 SelectionDAGLowering::visitLog10(CallInst &I) {
   SDValue result;
+  DebugLoc dl = DAG.getCurDebugLoc();
 
   if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
       LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
     SDValue Op = getValue(I.getOperand(1));
-    SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
+    SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
 
     // Scale the exponent by log10(2) [0.30102999f].
     SDValue Exp = GetExponent(DAG, Op1, TLI);
-    SDValue LogOfExponent = DAG.getNode(ISD::FMUL, MVT::f32, Exp,
+    SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
                                         getF32Constant(DAG, 0x3e9a209a));
 
     // Get the significand and build it into a floating-point number with
@@ -3357,15 +3442,16 @@
       //       (0.60948995f - 0.10380950f * x) * x;
       //
       // error 0.0014886165, which is 6 bits
-      SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
+      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0xbdd49a13));
-      SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0,
+      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
                                getF32Constant(DAG, 0x3f1c0789));
-      SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
-      SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t2,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+      SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
                                             getF32Constant(DAG, 0x3f011300));
 
-      result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log10ofMantissa);
+      result = DAG.getNode(ISD::FADD, dl, 
+                           MVT::f32, LogOfExponent, Log10ofMantissa);
     } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
       // For floating-point precision of 12:
       //
@@ -3375,18 +3461,19 @@
       //         (-0.31664806f + 0.47637168e-1f * x) * x) * x;
       //
       // error 0.00019228036, which is better than 12 bits
-      SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
+      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3d431f31));
-      SDValue t1 = DAG.getNode(ISD::FSUB, MVT::f32, t0,
+      SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
                                getF32Constant(DAG, 0x3ea21fb2));
-      SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
-      SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3f6ae232));
-      SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
-      SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
                                             getF32Constant(DAG, 0x3f25f7c3));
 
-      result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log10ofMantissa);
+      result = DAG.getNode(ISD::FADD, dl, 
+                           MVT::f32, LogOfExponent, Log10ofMantissa);
     } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
       // For floating-point precision of 18:
       //
@@ -3398,28 +3485,29 @@
       //             (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
       //
       // error 0.0000037995730, which is better than 18 bits
-      SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X,
+      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3c5d51ce));
-      SDValue t1 = DAG.getNode(ISD::FSUB, MVT::f32, t0,
+      SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
                                getF32Constant(DAG, 0x3e00685a));
-      SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X);
-      SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3efb6798));
-      SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FSUB, MVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3f88d192));
-      SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
-      SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
                                getF32Constant(DAG, 0x3fc4316c));
-      SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
-      SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t8,
+      SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+      SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
                                             getF32Constant(DAG, 0x3f57ce70));
 
-      result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log10ofMantissa);
+      result = DAG.getNode(ISD::FADD, dl, 
+                           MVT::f32, LogOfExponent, Log10ofMantissa);
     }
   } else {
     // No special expansion.
-    result = DAG.getNode(ISD::FLOG10,
+    result = DAG.getNode(ISD::FLOG10, dl,
                          getValue(I.getOperand(1)).getValueType(),
                          getValue(I.getOperand(1)));
   }
@@ -3432,19 +3520,20 @@
 void
 SelectionDAGLowering::visitExp2(CallInst &I) {
   SDValue result;
+  DebugLoc dl = DAG.getCurDebugLoc();
 
   if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
       LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
     SDValue Op = getValue(I.getOperand(1));
 
-    SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, MVT::i32, Op);
+    SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
 
     //   FractionalPartOfX = x - (float)IntegerPartOfX;
-    SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, MVT::f32, IntegerPartOfX);
-    SDValue X = DAG.getNode(ISD::FSUB, MVT::f32, Op, t1);
+    SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
+    SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
 
     //   IntegerPartOfX <<= 23;
-    IntegerPartOfX = DAG.getNode(ISD::SHL, MVT::i32, IntegerPartOfX,
+    IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
                                  DAG.getConstant(23, TLI.getShiftAmountTy()));
 
     if (LimitFloatPrecision <= 6) {
@@ -3455,18 +3544,19 @@
       //       (0.735607626f + 0.252464424f * x) * x;
       //
       // error 0.0144103317, which is 6 bits
-      SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3e814304));
-      SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3f3c50c8));
-      SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3f7f5e7e));
-      SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t5);
+      SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
       SDValue TwoToFractionalPartOfX =
-        DAG.getNode(ISD::ADD, MVT::i32, t6, IntegerPartOfX);
+        DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
 
-      result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
+      result = DAG.getNode(ISD::BIT_CONVERT, dl, 
+                           MVT::f32, TwoToFractionalPartOfX);
     } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
       // For floating-point precision of 12:
       //
@@ -3476,21 +3566,22 @@
       //         (0.224338339f + 0.792043434e-1f * x) * x) * x;
       //
       // error 0.000107046256, which is 13 to 14 bits
-      SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3da235e3));
-      SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3e65b8f3));
-      SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3f324b07));
-      SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
-      SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
                                getF32Constant(DAG, 0x3f7ff8fd));
-      SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t7);
+      SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
       SDValue TwoToFractionalPartOfX =
-        DAG.getNode(ISD::ADD, MVT::i32, t8, IntegerPartOfX);
+        DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
 
-      result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
+      result = DAG.getNode(ISD::BIT_CONVERT, dl, 
+                           MVT::f32, TwoToFractionalPartOfX);
     } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
       // For floating-point precision of 18:
       //
@@ -3502,34 +3593,35 @@
       //             (0.961591928e-2f +
       //               (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
       // error 2.47208000*10^(-7), which is better than 18 bits
-      SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3924b03e));
-      SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3ab24b87));
-      SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3c1d8c17));
-      SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
-      SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
                                getF32Constant(DAG, 0x3d634a1d));
-      SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
-      SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
+      SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+      SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
                                getF32Constant(DAG, 0x3e75fe14));
-      SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
-      SDValue t11 = DAG.getNode(ISD::FADD, MVT::f32, t10,
+      SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+      SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
                                 getF32Constant(DAG, 0x3f317234));
-      SDValue t12 = DAG.getNode(ISD::FMUL, MVT::f32, t11, X);
-      SDValue t13 = DAG.getNode(ISD::FADD, MVT::f32, t12,
+      SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
+      SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
                                 getF32Constant(DAG, 0x3f800000));
-      SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t13);
+      SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
       SDValue TwoToFractionalPartOfX =
-        DAG.getNode(ISD::ADD, MVT::i32, t14, IntegerPartOfX);
+        DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
 
-      result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
+      result = DAG.getNode(ISD::BIT_CONVERT, dl, 
+                           MVT::f32, TwoToFractionalPartOfX);
     }
   } else {
     // No special expansion.
-    result = DAG.getNode(ISD::FEXP2,
+    result = DAG.getNode(ISD::FEXP2, dl,
                          getValue(I.getOperand(1)).getValueType(),
                          getValue(I.getOperand(1)));
   }
@@ -3543,6 +3635,7 @@
 SelectionDAGLowering::visitPow(CallInst &I) {
   SDValue result;
   Value *Val = I.getOperand(1);
+  DebugLoc dl = DAG.getCurDebugLoc();
   bool IsExp10 = false;
 
   if (getValue(Val).getValueType() == MVT::f32 &&
@@ -3564,16 +3657,16 @@
     //
     //   #define LOG2OF10 3.3219281f
     //   IntegerPartOfX = (int32_t)(x * LOG2OF10);
-    SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, Op,
+    SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
                              getF32Constant(DAG, 0x40549a78));
-    SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, MVT::i32, t0);
+    SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
 
     //   FractionalPartOfX = x - (float)IntegerPartOfX;
-    SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, MVT::f32, IntegerPartOfX);
-    SDValue X = DAG.getNode(ISD::FSUB, MVT::f32, t0, t1);
+    SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
+    SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
 
     //   IntegerPartOfX <<= 23;
-    IntegerPartOfX = DAG.getNode(ISD::SHL, MVT::i32, IntegerPartOfX,
+    IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
                                  DAG.getConstant(23, TLI.getShiftAmountTy()));
 
     if (LimitFloatPrecision <= 6) {
@@ -3584,18 +3677,19 @@
       //       (0.735607626f + 0.252464424f * x) * x;
       //
       // error 0.0144103317, which is 6 bits
-      SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3e814304));
-      SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3f3c50c8));
-      SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3f7f5e7e));
-      SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t5);
+      SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
       SDValue TwoToFractionalPartOfX =
-        DAG.getNode(ISD::ADD, MVT::i32, t6, IntegerPartOfX);
+        DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
 
-      result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
+      result = DAG.getNode(ISD::BIT_CONVERT, dl,
+                           MVT::f32, TwoToFractionalPartOfX);
     } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
       // For floating-point precision of 12:
       //
@@ -3605,21 +3699,22 @@
       //         (0.224338339f + 0.792043434e-1f * x) * x) * x;
       //
       // error 0.000107046256, which is 13 to 14 bits
-      SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3da235e3));
-      SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3e65b8f3));
-      SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3f324b07));
-      SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
-      SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
                                getF32Constant(DAG, 0x3f7ff8fd));
-      SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t7);
+      SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
       SDValue TwoToFractionalPartOfX =
-        DAG.getNode(ISD::ADD, MVT::i32, t8, IntegerPartOfX);
+        DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
 
-      result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
+      result = DAG.getNode(ISD::BIT_CONVERT, dl, 
+                           MVT::f32, TwoToFractionalPartOfX);
     } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
       // For floating-point precision of 18:
       //
@@ -3631,34 +3726,35 @@
       //             (0.961591928e-2f +
       //               (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
       // error 2.47208000*10^(-7), which is better than 18 bits
-      SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3924b03e));
-      SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2,
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3ab24b87));
-      SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3c1d8c17));
-      SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X);
-      SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
                                getF32Constant(DAG, 0x3d634a1d));
-      SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X);
-      SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8,
+      SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+      SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
                                getF32Constant(DAG, 0x3e75fe14));
-      SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X);
-      SDValue t11 = DAG.getNode(ISD::FADD, MVT::f32, t10,
+      SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+      SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
                                 getF32Constant(DAG, 0x3f317234));
-      SDValue t12 = DAG.getNode(ISD::FMUL, MVT::f32, t11, X);
-      SDValue t13 = DAG.getNode(ISD::FADD, MVT::f32, t12,
+      SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
+      SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
                                 getF32Constant(DAG, 0x3f800000));
-      SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t13);
+      SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
       SDValue TwoToFractionalPartOfX =
-        DAG.getNode(ISD::ADD, MVT::i32, t14, IntegerPartOfX);
+        DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
 
-      result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX);
+      result = DAG.getNode(ISD::BIT_CONVERT, dl, 
+                           MVT::f32, TwoToFractionalPartOfX);
     }
   } else {
     // No special expansion.
-    result = DAG.getNode(ISD::FPOW,
+    result = DAG.getNode(ISD::FPOW, dl,
                          getValue(I.getOperand(1)).getValueType(),
                          getValue(I.getOperand(1)),
                          getValue(I.getOperand(2)));
@@ -3672,6 +3768,7 @@
 /// otherwise lower it and return null.
 const char *
 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
+  DebugLoc dl = DAG.getCurDebugLoc();
   switch (Intrinsic) {
   default:
     // By default, turn this into a target intrinsic node.
@@ -3681,11 +3778,11 @@
   case Intrinsic::vaend:    visitVAEnd(I); return 0;
   case Intrinsic::vacopy:   visitVACopy(I); return 0;
   case Intrinsic::returnaddress:
-    setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
+    setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
                              getValue(I.getOperand(1))));
     return 0;
   case Intrinsic::frameaddress:
-    setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
+    setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
                              getValue(I.getOperand(1))));
     return 0;
   case Intrinsic::setjmp:
@@ -3737,11 +3834,19 @@
   case Intrinsic::dbg_stoppoint: {
     DwarfWriter *DW = DAG.getDwarfWriter();
     DbgStopPointInst &SPI = cast(I);
-    if (DW && DW->ValidDebugInfo(SPI.getContext()))
+    if (DW && DW->ValidDebugInfo(SPI.getContext())) {
       DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
                                       SPI.getLine(),
                                       SPI.getColumn(),
                                       SPI.getContext()));
+      DICompileUnit CU(cast(SPI.getContext()));
+      unsigned SrcFile = DW->RecordSource(CU.getDirectory(), CU.getFilename());
+      unsigned idx = DAG.getMachineFunction().
+                         getOrCreateDebugLocID(SrcFile,
+                                               SPI.getLine(), 
+                                               SPI.getColumn());
+      DAG.setCurDebugLoc(DebugLoc::get(idx));
+    }
     return 0;
   }
   case Intrinsic::dbg_region_start: {
@@ -3781,10 +3886,13 @@
       // Record the source line but does not create a label for the normal
       // function start. It will be emitted at asm emission time. However,
       // create a label if this is a beginning of inlined function.
+      unsigned Line = Subprogram.getLineNumber();
       unsigned LabelID =
-        DW->RecordSourceLine(Subprogram.getLineNumber(), 0, SrcFile);
+        DW->RecordSourceLine(Line, 0, SrcFile);
       if (DW->getRecordSourceLineCount() != 1)
         DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
+      DAG.setCurDebugLoc(DebugLoc::get(DAG.getMachineFunction().
+                         getOrCreateDebugLocID(SrcFile, Line, 0)));
     }
 
     return 0;
@@ -3794,7 +3902,7 @@
     DbgDeclareInst &DI = cast(I);
     Value *Variable = DI.getVariable();
     if (DW && DW->ValidDebugInfo(Variable))
-      DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
+      DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
                               getValue(DI.getAddress()), getValue(Variable)));
     return 0;
   }
@@ -3809,7 +3917,7 @@
     SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
     SDValue Ops[1];
     Ops[0] = DAG.getRoot();
-    SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
+    SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
     setValue(&I, Op);
     DAG.setRoot(Op.getValue(1));
     return 0;
@@ -3838,7 +3946,7 @@
       SDValue Ops[2];
       Ops[0] = getValue(I.getOperand(1));
       Ops[1] = getRoot();
-      SDValue Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
+      SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
       setValue(&I, Op);
       DAG.setRoot(Op.getValue(1));
     } else {
@@ -3872,7 +3980,7 @@
   case Intrinsic::eh_return_i64:
     if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
       MMI->setCallsEHReturn(true);
-      DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
+      DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
                               MVT::Other,
                               getControlRoot(),
                               getValue(I.getOperand(1)),
@@ -3893,20 +4001,20 @@
     MVT VT = getValue(I.getOperand(1)).getValueType();
     SDValue CfaArg;
     if (VT.bitsGT(TLI.getPointerTy()))
-      CfaArg = DAG.getNode(ISD::TRUNCATE,
+      CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
                            TLI.getPointerTy(), getValue(I.getOperand(1)));
     else
-      CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
+      CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
                            TLI.getPointerTy(), getValue(I.getOperand(1)));
 
-    SDValue Offset = DAG.getNode(ISD::ADD,
+    SDValue Offset = DAG.getNode(ISD::ADD, dl,
                                  TLI.getPointerTy(),
-                                 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
+                                 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
                                              TLI.getPointerTy()),
                                  CfaArg);
-    setValue(&I, DAG.getNode(ISD::ADD,
+    setValue(&I, DAG.getNode(ISD::ADD, dl,
                              TLI.getPointerTy(),
-                             DAG.getNode(ISD::FRAMEADDR,
+                             DAG.getNode(ISD::FRAMEADDR, dl,
                                          TLI.getPointerTy(),
                                          DAG.getConstant(0,
                                                          TLI.getPointerTy())),
@@ -3947,23 +4055,23 @@
   }
 
   case Intrinsic::sqrt:
-    setValue(&I, DAG.getNode(ISD::FSQRT,
+    setValue(&I, DAG.getNode(ISD::FSQRT, dl,
                              getValue(I.getOperand(1)).getValueType(),
                              getValue(I.getOperand(1))));
     return 0;
   case Intrinsic::powi:
-    setValue(&I, DAG.getNode(ISD::FPOWI,
+    setValue(&I, DAG.getNode(ISD::FPOWI, dl,
                              getValue(I.getOperand(1)).getValueType(),
                              getValue(I.getOperand(1)),
                              getValue(I.getOperand(2))));
     return 0;
   case Intrinsic::sin:
-    setValue(&I, DAG.getNode(ISD::FSIN,
+    setValue(&I, DAG.getNode(ISD::FSIN, dl,
                              getValue(I.getOperand(1)).getValueType(),
                              getValue(I.getOperand(1))));
     return 0;
   case Intrinsic::cos:
-    setValue(&I, DAG.getNode(ISD::FCOS,
+    setValue(&I, DAG.getNode(ISD::FCOS, dl,
                              getValue(I.getOperand(1)).getValueType(),
                              getValue(I.getOperand(1))));
     return 0;
@@ -3987,12 +4095,12 @@
     return 0;
   case Intrinsic::pcmarker: {
     SDValue Tmp = getValue(I.getOperand(1));
-    DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
+    DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
     return 0;
   }
   case Intrinsic::readcyclecounter: {
     SDValue Op = getRoot();
-    SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
+    SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
                                 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
                                 &Op, 1);
     setValue(&I, Tmp);
@@ -4010,34 +4118,34 @@
     abort();
   }
   case Intrinsic::bswap:
-    setValue(&I, DAG.getNode(ISD::BSWAP,
+    setValue(&I, DAG.getNode(ISD::BSWAP, dl,
                              getValue(I.getOperand(1)).getValueType(),
                              getValue(I.getOperand(1))));
     return 0;
   case Intrinsic::cttz: {
     SDValue Arg = getValue(I.getOperand(1));
     MVT Ty = Arg.getValueType();
-    SDValue result = DAG.getNode(ISD::CTTZ, Ty, Arg);
+    SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
     setValue(&I, result);
     return 0;
   }
   case Intrinsic::ctlz: {
     SDValue Arg = getValue(I.getOperand(1));
     MVT Ty = Arg.getValueType();
-    SDValue result = DAG.getNode(ISD::CTLZ, Ty, Arg);
+    SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
     setValue(&I, result);
     return 0;
   }
   case Intrinsic::ctpop: {
     SDValue Arg = getValue(I.getOperand(1));
     MVT Ty = Arg.getValueType();
-    SDValue result = DAG.getNode(ISD::CTPOP, Ty, Arg);
+    SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
     setValue(&I, result);
     return 0;
   }
   case Intrinsic::stacksave: {
     SDValue Op = getRoot();
-    SDValue Tmp = DAG.getNode(ISD::STACKSAVE,
+    SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
               DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
     setValue(&I, Tmp);
     DAG.setRoot(Tmp.getValue(1));
@@ -4045,7 +4153,7 @@
   }
   case Intrinsic::stackrestore: {
     SDValue Tmp = getValue(I.getOperand(1));
-    DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
+    DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
     return 0;
   }
   case Intrinsic::stackprotector: {
@@ -4063,7 +4171,7 @@
     SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
 
     // Store the stack protector onto the stack.
-    SDValue Result = DAG.getStore(getRoot(), Src, FIN,
+    SDValue Result = DAG.getStore(getRoot(), DAG.getCurDebugLoc(), Src, FIN,
                                   PseudoSourceValue::getFixedStack(FI),
                                   0, true);
     setValue(&I, Result);
@@ -4085,7 +4193,7 @@
     Ops[4] = DAG.getSrcValue(I.getOperand(1));
     Ops[5] = DAG.getSrcValue(F);
 
-    SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE,
+    SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
                                 DAG.getNodeValueTypes(TLI.getPointerTy(),
                                                       MVT::Other), 2,
                                 Ops, 6);
@@ -4111,12 +4219,12 @@
     return 0;
 
   case Intrinsic::flt_rounds: {
-    setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
+    setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
     return 0;
   }
 
   case Intrinsic::trap: {
-    DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
+    DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
     return 0;
   }
 
@@ -4139,7 +4247,7 @@
     Ops[1] = getValue(I.getOperand(1));
     Ops[2] = getValue(I.getOperand(2));
     Ops[3] = getValue(I.getOperand(3));
-    DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
+    DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
     return 0;
   }
 
@@ -4149,13 +4257,13 @@
     for (int x = 1; x < 6; ++x)
       Ops[x] = getValue(I.getOperand(x));
 
-    DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
+    DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
     return 0;
   }
   case Intrinsic::atomic_cmp_swap: {
     SDValue Root = getRoot();
     SDValue L =
-      DAG.getAtomic(ISD::ATOMIC_CMP_SWAP,
+      DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, DAG.getCurDebugLoc(),
                     getValue(I.getOperand(2)).getValueType().getSimpleVT(),
                     Root,
                     getValue(I.getOperand(1)),
@@ -4278,8 +4386,8 @@
             I.getType() == I.getOperand(2)->getType()) {
           SDValue LHS = getValue(I.getOperand(1));
           SDValue RHS = getValue(I.getOperand(2));
-          setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
-                                   LHS, RHS));
+          setValue(&I, DAG.getNode(ISD::FCOPYSIGN, DAG.getCurDebugLoc(), 
+                                   LHS.getValueType(), LHS, RHS));
           return;
         }
       } else if (NameStr[0] == 'f' &&
@@ -4290,7 +4398,8 @@
             I.getOperand(1)->getType()->isFloatingPoint() &&
             I.getType() == I.getOperand(1)->getType()) {
           SDValue Tmp = getValue(I.getOperand(1));
-          setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
+          setValue(&I, DAG.getNode(ISD::FABS, DAG.getCurDebugLoc(), 
+                                   Tmp.getValueType(), Tmp));
           return;
         }
       } else if (NameStr[0] == 's' &&
@@ -4301,7 +4410,8 @@
             I.getOperand(1)->getType()->isFloatingPoint() &&
             I.getType() == I.getOperand(1)->getType()) {
           SDValue Tmp = getValue(I.getOperand(1));
-          setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
+          setValue(&I, DAG.getNode(ISD::FSIN, DAG.getCurDebugLoc(), 
+                                   Tmp.getValueType(), Tmp));
           return;
         }
       } else if (NameStr[0] == 'c' &&
@@ -4312,7 +4422,8 @@
             I.getOperand(1)->getType()->isFloatingPoint() &&
             I.getType() == I.getOperand(1)->getType()) {
           SDValue Tmp = getValue(I.getOperand(1));
-          setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
+          setValue(&I, DAG.getNode(ISD::FCOS, DAG.getCurDebugLoc(), 
+                                   Tmp.getValueType(), Tmp));
           return;
         }
       }
@@ -4395,6 +4506,7 @@
 
           if (FromVT != MVT::Other) {
             P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
+                            DAG.getCurDebugLoc(),
                             RegisterVT, P, DAG.getValueType(FromVT));
 
           }
@@ -4410,7 +4522,7 @@
     Parts.clear();
   }
 
-  return DAG.getNode(ISD::MERGE_VALUES,
+  return DAG.getNode(ISD::MERGE_VALUES, DAG.getCurDebugLoc(),
                      DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
                      &Values[0], ValueVTs.size());
 }
@@ -4460,7 +4572,8 @@
     //        = op c3, ..., f2
     Chain = Chains[NumRegs-1];
   else
-    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
+    Chain = DAG.getNode(ISD::TokenFactor, DAG.getCurDebugLoc(),
+                        MVT::Other, &Chains[0], NumRegs);
 }
 
 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
@@ -4672,8 +4785,8 @@
       // vector types).
       MVT RegVT = *PhysReg.second->vt_begin();
       if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
-        OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, RegVT,
-                                         OpInfo.CallOperand);
+        OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(),
+                                         RegVT, OpInfo.CallOperand);
         OpInfo.ConstraintVT = RegVT;
       } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
         // If the input is a FP value and we want it in FP registers, do a
@@ -4681,8 +4794,8 @@
         // into i64, which can be passed with two i32 values on a 32-bit
         // machine.
         RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
-        OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, RegVT,
-                                         OpInfo.CallOperand);
+        OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(),
+                                         RegVT, OpInfo.CallOperand);
         OpInfo.ConstraintVT = RegVT;
       }
     }
@@ -4947,7 +5060,8 @@
         MachineFunction &MF = DAG.getMachineFunction();
         int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
         SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
-        Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
+        Chain = DAG.getStore(Chain, DAG.getCurDebugLoc(),
+                             OpInfo.CallOperand, StackSlot, NULL, 0);
         OpInfo.CallOperand = StackSlot;
       }
 
@@ -5156,7 +5270,7 @@
   AsmNodeOperands[0] = Chain;
   if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
 
-  Chain = DAG.getNode(ISD::INLINEASM,
+  Chain = DAG.getNode(ISD::INLINEASM, DAG.getCurDebugLoc(),
                       DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
                       &AsmNodeOperands[0], AsmNodeOperands.size());
   Flag = Chain.getValue(1);
@@ -5176,14 +5290,15 @@
       // not have the same VT as was expected.  Convert it to the right type
       // with bit_convert.
       if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
-        Val = DAG.getNode(ISD::BIT_CONVERT, ResultType, Val);
+        Val = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(),
+                          ResultType, Val);
 
       } else if (ResultType != Val.getValueType() &&
                  ResultType.isInteger() && Val.getValueType().isInteger()) {
         // If a result value was tied to an input value, the computed result may
         // have a wider width than the expected result.  Extract the relevant
         // portion.
-        Val = DAG.getNode(ISD::TRUNCATE, ResultType, Val);
+        Val = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), ResultType, Val);
       }
 
       assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
@@ -5206,11 +5321,12 @@
   // Emit the non-flagged stores from the physregs.
   SmallVector OutChains;
   for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
-    OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
+    OutChains.push_back(DAG.getStore(Chain, DAG.getCurDebugLoc(),
+                                    StoresToEmit[i].first,
                                     getValue(StoresToEmit[i].second),
                                     StoresToEmit[i].second, 0));
   if (!OutChains.empty())
-    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+    Chain = DAG.getNode(ISD::TokenFactor, DAG.getCurDebugLoc(), MVT::Other,
                         &OutChains[0], OutChains.size());
   DAG.setRoot(Chain);
 }
@@ -5222,13 +5338,13 @@
   MVT IntPtr = TLI.getPointerTy();
 
   if (IntPtr.bitsLT(Src.getValueType()))
-    Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
+    Src = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), IntPtr, Src);
   else if (IntPtr.bitsGT(Src.getValueType()))
-    Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
+    Src = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), IntPtr, Src);
 
   // Scale the source by the type size.
   uint64_t ElementSize = TD->getTypePaddedSize(I.getType()->getElementType());
-  Src = DAG.getNode(ISD::MUL, Src.getValueType(),
+  Src = DAG.getNode(ISD::MUL, DAG.getCurDebugLoc(), Src.getValueType(),
                     Src, DAG.getIntPtrConstant(ElementSize));
 
   TargetLowering::ArgListTy Args;
@@ -5261,7 +5377,8 @@
 }
 
 void SelectionDAGLowering::visitVAStart(CallInst &I) {
-  DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
+  DAG.setRoot(DAG.getNode(ISD::VASTART, DAG.getCurDebugLoc(),
+                          MVT::Other, getRoot(),
                           getValue(I.getOperand(1)),
                           DAG.getSrcValue(I.getOperand(1))));
 }
@@ -5275,13 +5392,15 @@
 }
 
 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
-  DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
+  DAG.setRoot(DAG.getNode(ISD::VAEND, DAG.getCurDebugLoc(),
+                          MVT::Other, getRoot(),
                           getValue(I.getOperand(1)),
                           DAG.getSrcValue(I.getOperand(1))));
 }
 
 void SelectionDAGLowering::visitVACopy(CallInst &I) {
-  DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
+  DAG.setRoot(DAG.getNode(ISD::VACOPY, DAG.getCurDebugLoc(),
+                          MVT::Other, getRoot(),
                           getValue(I.getOperand(1)),
                           getValue(I.getOperand(2)),
                           DAG.getSrcValue(I.getOperand(1)),
@@ -5358,7 +5477,7 @@
   RetVals.push_back(MVT::Other);
 
   // Create the node.
-  SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
+  SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, DAG.getCurDebugLoc(),
                                DAG.getVTList(&RetVals[0], RetVals.size()),
                                &Ops[0], Ops.size()).getNode();
 
@@ -5517,7 +5636,8 @@
   LoweredRetTys.push_back(MVT::Other);  // Always has a chain.
 
   // Create the CALL node.
-  SDValue Res = DAG.getCall(CallingConv, isVarArg, isTailCall, isInreg,
+  SDValue Res = DAG.getCall(CallingConv, DAG.getCurDebugLoc(), 
+                            isVarArg, isTailCall, isInreg,
                             DAG.getVTList(&LoweredRetTys[0],
                                           LoweredRetTys.size()),
                             &Ops[0], Ops.size()
@@ -5548,7 +5668,7 @@
                          AssertOp);
       ReturnValues.push_back(ReturnValue);
     }
-    Res = DAG.getNode(ISD::MERGE_VALUES,
+    Res = DAG.getNode(ISD::MERGE_VALUES, DAG.getCurDebugLoc(),
                       DAG.getVTList(&RetTys[0], RetTys.size()),
                       &ReturnValues[0], ReturnValues.size());
   }




From dpatel at apple.com  Thu Jan 29 19:37:30 2009
From: dpatel at apple.com (Devang Patel)
Date: Fri, 30 Jan 2009 01:37:30 -0000
Subject: [llvm-commits] [llvm] r63360 -
	/llvm/trunk/test/DebugInfo/2009-01-29-MethodDeclaration.ll
Message-ID: <200901300137.n0U1bUW8028218@zion.cs.uiuc.edu>

Author: dpatel
Date: Thu Jan 29 19:37:30 2009
New Revision: 63360

URL: http://llvm.org/viewvc/llvm-project?rev=63360&view=rev
Log:
Linux and other target's  encoding for DW_AT_declaration may not match.

Modified:
    llvm/trunk/test/DebugInfo/2009-01-29-MethodDeclaration.ll

Modified: llvm/trunk/test/DebugInfo/2009-01-29-MethodDeclaration.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2009-01-29-MethodDeclaration.ll?rev=63360&r1=63359&r2=63360&view=diff

==============================================================================
--- llvm/trunk/test/DebugInfo/2009-01-29-MethodDeclaration.ll (original)
+++ llvm/trunk/test/DebugInfo/2009-01-29-MethodDeclaration.ll Thu Jan 29 19:37:30 2009
@@ -1,5 +1,6 @@
 ; RUN: llvm-as < %s | llc | grep 0x3C | count 1
 ; Check DW_AT_declaration attribute for class method foo.
+; target triple = "i386-apple-darwin*"
 	%llvm.dbg.anchor.type = type { i32, i32 }
 	%llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32, i8*, i8* }
 	%llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i8* }




From dpatel at apple.com  Thu Jan 29 19:40:58 2009
From: dpatel at apple.com (Devang Patel)
Date: Fri, 30 Jan 2009 01:40:58 -0000
Subject: [llvm-commits] [llvm] r63361 -
	/llvm/trunk/test/DebugInfo/2009-01-29-MethodDeclaration.ll
Message-ID: <200901300140.n0U1ewKO028386@zion.cs.uiuc.edu>

Author: dpatel
Date: Thu Jan 29 19:40:58 2009
New Revision: 63361

URL: http://llvm.org/viewvc/llvm-project?rev=63361&view=rev
Log:
Enable target tripple.

Modified:
    llvm/trunk/test/DebugInfo/2009-01-29-MethodDeclaration.ll

Modified: llvm/trunk/test/DebugInfo/2009-01-29-MethodDeclaration.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2009-01-29-MethodDeclaration.ll?rev=63361&r1=63360&r2=63361&view=diff

==============================================================================
--- llvm/trunk/test/DebugInfo/2009-01-29-MethodDeclaration.ll (original)
+++ llvm/trunk/test/DebugInfo/2009-01-29-MethodDeclaration.ll Thu Jan 29 19:40:58 2009
@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s | llc | grep 0x3C | count 1
 ; Check DW_AT_declaration attribute for class method foo.
-; target triple = "i386-apple-darwin*"
+target triple = "i386-apple-darwin*"
 	%llvm.dbg.anchor.type = type { i32, i32 }
 	%llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32, i8*, i8* }
 	%llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i8* }




From clattner at apple.com  Thu Jan 29 19:42:29 2009
From: clattner at apple.com (Chris Lattner)
Date: Thu, 29 Jan 2009 17:42:29 -0800
Subject: [llvm-commits] [llvm] r63359 - in /llvm/trunk:
	include/llvm/CodeGen/SelectionDAG.h
	lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
In-Reply-To: <200901300134.n0U1YM1H028081@zion.cs.uiuc.edu>
References: <200901300134.n0U1YM1H028081@zion.cs.uiuc.edu>
Message-ID: 


On Jan 29, 2009, at 5:34 PM, Dale Johannesen wrote:

> Author: johannes
> Date: Thu Jan 29 19:34:22 2009
> New Revision: 63359
>
> URL: http://llvm.org/viewvc/llvm-project?rev=63359&view=rev
> Log:
> Propagate debug info when building SelectionDAG.
>
>

Thanks Dale!  One issue: instead of "getCurDebugLoc()" and friends  
being on the SelectionDAG, please move them to do the dag builder  
class.  This should only be live when LLVM IR is converted to the  
initial dag, not when normal dag->dag xforms happens.  Thanks for the  
great progress!

-Chris


From dalej at apple.com  Thu Jan 29 19:47:45 2009
From: dalej at apple.com (Dale Johannesen)
Date: Thu, 29 Jan 2009 17:47:45 -0800
Subject: [llvm-commits] [llvm] r63359 - in /llvm/trunk:
	include/llvm/CodeGen/SelectionDAG.h
	lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
In-Reply-To: 
References: <200901300134.n0U1YM1H028081@zion.cs.uiuc.edu>
	
Message-ID: <096363F0-D686-47CD-AFDE-AC0D76958E22@apple.com>


On Jan 29, 2009, at 5:42 PMPST, Chris Lattner wrote:

>
> On Jan 29, 2009, at 5:34 PM, Dale Johannesen wrote:
>
>> Author: johannes
>> Date: Thu Jan 29 19:34:22 2009
>> New Revision: 63359
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=63359&view=rev
>> Log:
>> Propagate debug info when building SelectionDAG.
>>
>>
>
> Thanks Dale!  One issue: instead of "getCurDebugLoc()" and friends
> being on the SelectionDAG, please move them to do the dag builder
> class.

What do you mean?  I had it in SelectionDAGLowering originally, which  
looked right to me, but it looked like there wasn't an easy way to get  
there from everywhere that was calling getNode.

> This should only be live when LLVM IR is converted to the
> initial dag, not when normal dag->dag xforms happens.  Thanks for the
> great progress!
>
> -Chris
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From sabre at nondot.org  Thu Jan 29 19:58:19 2009
From: sabre at nondot.org (Chris Lattner)
Date: Fri, 30 Jan 2009 01:58:19 -0000
Subject: [llvm-commits] [llvm] r63362 - /llvm/trunk/include/llvm/ADT/APSInt.h
Message-ID: <200901300158.n0U1wJFG028976@zion.cs.uiuc.edu>

Author: lattner
Date: Thu Jan 29 19:58:19 2009
New Revision: 63362

URL: http://llvm.org/viewvc/llvm-project?rev=63362&view=rev
Log:
Fix a bug in getMaxValue/getMinValue to pass the right signedness the
the constructed APSInt, patch suggested by Ben Laurie!

Modified:
    llvm/trunk/include/llvm/ADT/APSInt.h

Modified: llvm/trunk/include/llvm/ADT/APSInt.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/APSInt.h?rev=63362&r1=63361&r2=63362&view=diff

==============================================================================
--- llvm/trunk/include/llvm/ADT/APSInt.h (original)
+++ llvm/trunk/include/llvm/ADT/APSInt.h Thu Jan 29 19:58:19 2009
@@ -236,16 +236,16 @@
 
   /// getMaxValue - Return the APSInt representing the maximum integer value
   ///  with the given bit width and signedness.
-  static APSInt getMaxValue(uint32_t numBits, bool Signed) {
-    return APSInt(Signed ? APInt::getSignedMaxValue(numBits)
-                         : APInt::getMaxValue(numBits), Signed);
+  static APSInt getMaxValue(uint32_t numBits, bool Unsigned) {
+    return APSInt(Unsigned ? APInt::getMaxValue(numBits)
+                           : APInt::getSignedMaxValue(numBits), Unsigned);
   }
 
   /// getMinValue - Return the APSInt representing the minimum integer value
   ///  with the given bit width and signedness.
-  static APSInt getMinValue(uint32_t numBits, bool Signed) {
-    return APSInt(Signed ? APInt::getSignedMinValue(numBits)
-                         : APInt::getMinValue(numBits), Signed);
+  static APSInt getMinValue(uint32_t numBits, bool Unsigned) {
+    return APSInt(Unsigned ? APInt::getMinValue(numBits)
+                           : APInt::getSignedMinValue(numBits), Unsigned);
   }
 
   /// Profile - Used to insert APSInt objects, or objects that contain APSInt




From foldr at codedgers.com  Thu Jan 29 20:12:57 2009
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Fri, 30 Jan 2009 02:12:57 -0000
Subject: [llvm-commits] [llvm] r63364 -
	/llvm/trunk/tools/llvmc/driver/CompilationGraph.cpp
Message-ID: <200901300212.n0U2CvdK029411@zion.cs.uiuc.edu>

Author: foldr
Date: Thu Jan 29 20:12:57 2009
New Revision: 63364

URL: http://llvm.org/viewvc/llvm-project?rev=63364&view=rev
Log:
Add some comments.

Modified:
    llvm/trunk/tools/llvmc/driver/CompilationGraph.cpp

Modified: llvm/trunk/tools/llvmc/driver/CompilationGraph.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/driver/CompilationGraph.cpp?rev=63364&r1=63363&r2=63364&view=diff

==============================================================================
--- llvm/trunk/tools/llvmc/driver/CompilationGraph.cpp (original)
+++ llvm/trunk/tools/llvmc/driver/CompilationGraph.cpp Thu Jan 29 20:12:57 2009
@@ -390,6 +390,8 @@
   int ret = 0;
   InputLanguagesSet Dummy;
 
+  // For all nodes, just iterate over the outgoing edges and check if there is
+  // more than one edge with maximum weight.
   for (const_nodes_iterator B = this->NodesMap.begin(),
          E = this->NodesMap.end(); B != E; ++B) {
     const Node& N = B->second;
@@ -423,6 +425,9 @@
   std::queue Q;
   Q.push(&getNode("root"));
 
+  // Try to delete all nodes that have no ingoing edges, starting from the
+  // root. If there are any nodes left after this operation, then we have a
+  // cycle. This relies on '--check-graph' not performing the topological sort.
   while (!Q.empty()) {
     Node* A = Q.front();
     Q.pop();
@@ -447,7 +452,6 @@
   return 0;
 }
 
-
 int CompilationGraph::Check () {
   // We try to catch as many errors as we can in one go.
   int ret = 0;




From clattner at apple.com  Thu Jan 29 20:22:08 2009
From: clattner at apple.com (Chris Lattner)
Date: Thu, 29 Jan 2009 18:22:08 -0800
Subject: [llvm-commits] [llvm] r63359 - in /llvm/trunk:
	include/llvm/CodeGen/SelectionDAG.h
	lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
In-Reply-To: <096363F0-D686-47CD-AFDE-AC0D76958E22@apple.com>
References: <200901300134.n0U1YM1H028081@zion.cs.uiuc.edu>
	
	<096363F0-D686-47CD-AFDE-AC0D76958E22@apple.com>
Message-ID: <5A0CC7FC-7F52-45BE-9412-8552034F191C@apple.com>

On Jan 29, 2009, at 5:47 PM, Dale Johannesen wrote:
>> Thanks Dale!  One issue: instead of "getCurDebugLoc()" and friends
>> being on the SelectionDAG, please move them to do the dag builder
>> class.
>
> What do you mean?  I had it in SelectionDAGLowering originally, which
> looked right to me, but it looked like there wasn't an easy way to get
> there from everywhere that was calling getNode.

What places needed it other than SDBuilder?

-Chris


From isanbard at gmail.com  Thu Jan 29 20:23:43 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 30 Jan 2009 02:23:43 -0000
Subject: [llvm-commits] [llvm] r63365 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAG.h
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <200901300223.n0U2NiLQ029776@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 20:23:43 2009
New Revision: 63365

URL: http://llvm.org/viewvc/llvm-project?rev=63365&view=rev
Log:
- Propagate debug loc info in combineSelectAndUse().
- Modify ReassociateOps so that the resulting SDValue is what the comment claims
  it is.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63365&r1=63364&r2=63365&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Thu Jan 29 20:23:43 2009
@@ -487,7 +487,12 @@
   ///
   SDValue getSetCC(MVT VT, SDValue LHS, SDValue RHS,
                    ISD::CondCode Cond) {
-    return getNode(ISD::SETCC, VT, LHS, RHS, getCondCode(Cond));
+    return getNode(ISD::SETCC, DebugLoc::getUnknownLoc(), VT,
+                   LHS, RHS, getCondCode(Cond));
+  }
+  SDValue getSetCC(DebugLoc DL, MVT VT, SDValue LHS, SDValue RHS,
+                   ISD::CondCode Cond) {
+    return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
   }
 
   /// getVSetCC - Helper function to make it easier to build VSetCC's nodes
@@ -495,7 +500,12 @@
   ///
   SDValue getVSetCC(MVT VT, SDValue LHS, SDValue RHS,
                     ISD::CondCode Cond) {
-    return getNode(ISD::VSETCC, VT, LHS, RHS, getCondCode(Cond));
+    return getNode(ISD::VSETCC, DebugLoc::getUnknownLoc(), VT,
+                   LHS, RHS, getCondCode(Cond));
+  }
+  SDValue getVSetCC(DebugLoc DL, MVT VT, SDValue LHS, SDValue RHS,
+                    ISD::CondCode Cond) {
+    return getNode(ISD::VSETCC, DL, VT, LHS, RHS, getCondCode(Cond));
   }
 
   /// getSelectCC - Helper function to make it easier to build SelectCC's if you
@@ -503,8 +513,13 @@
   ///
   SDValue getSelectCC(SDValue LHS, SDValue RHS,
                       SDValue True, SDValue False, ISD::CondCode Cond) {
-    return getNode(ISD::SELECT_CC, True.getValueType(), LHS, RHS, True, False,
-                   getCondCode(Cond));
+    return getNode(ISD::SELECT_CC, DebugLoc::getUnknownLoc(), True.getValueType(),
+                   LHS, RHS, True, False, getCondCode(Cond));
+  }
+  SDValue getSelectCC(DebugLoc DL, SDValue LHS, SDValue RHS,
+                      SDValue True, SDValue False, ISD::CondCode Cond) {
+    return getNode(ISD::SELECT_CC, DL, True.getValueType(),
+                   LHS, RHS, True, False, getCondCode(Cond));
   }
   
   /// getVAArg - VAArg produces a result and token chain, and takes a pointer

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63365&r1=63364&r2=63365&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 29 20:23:43 2009
@@ -485,10 +485,10 @@
   if (N0.getOpcode() == Opc && isa(N0.getOperand(1))) {
     if (isa(N1)) {
       // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
-      SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
+      SDValue OpNode = DAG.getNode(Opc, N1.getDebugLoc(), VT,
                                    N0.getOperand(1), N1);
       AddToWorkList(OpNode.getNode());
-      return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(0));
+      return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
     } else if (N0.hasOneUse()) {
       // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
       SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
@@ -504,10 +504,10 @@
       SDValue OpNode = DAG.getNode(Opc, N1.getDebugLoc(), VT,
                                    N1.getOperand(1), N0);
       AddToWorkList(OpNode.getNode());
-      return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(0));
+      return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
     } else if (N1.hasOneUse()) {
       // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
-      SDValue OpNode = DAG.getNode(Opc, N1.getDebugLoc(), VT,
+      SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
                                    N1.getOperand(0), N0);
       AddToWorkList(OpNode.getNode());
       return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
@@ -913,18 +913,24 @@
 }
 
 static
-SDValue combineShlAddConstant(SDValue N0, SDValue N1, SelectionDAG &DAG) {
+SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
+                              SelectionDAG &DAG) {
   MVT VT = N0.getValueType();
   SDValue N00 = N0.getOperand(0);
   SDValue N01 = N0.getOperand(1);
   ConstantSDNode *N01C = dyn_cast(N01);
+
   if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
       isa(N00.getOperand(1))) {
-    N0 = DAG.getNode(ISD::ADD, VT,
-                     DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
-                     DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
-    return DAG.getNode(ISD::ADD, VT, N0, N1);
+    // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<getDebugLoc(), OtherOp, Result,
                              Slct.getOperand(0), Slct.getOperand(1), CC);
     SDValue CCOp = Slct.getOperand(0);
     if (InvCC)
-      CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0),
-                          CCOp.getOperand(1), CC);
-    return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result);
+      CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
+                          CCOp.getOperand(0), CCOp.getOperand(1), CC);
+    return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
+                       CCOp, OtherOp, Result);
   }
   return SDValue();
 }
@@ -1100,11 +1107,11 @@
 
   // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<hasOneUse()) {
-    SDValue Result = combineShlAddConstant(N0, N1, DAG);
+    SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
     if (Result.getNode()) return Result;
   }
   if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
-    SDValue Result = combineShlAddConstant(N1, N0, DAG);
+    SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
     if (Result.getNode()) return Result;
   }
 




From isanbard at gmail.com  Thu Jan 29 20:31:18 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 30 Jan 2009 02:31:18 -0000
Subject: [llvm-commits] [llvm] r63366 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <200901300231.n0U2VI1i030042@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 20:31:17 2009
New Revision: 63366

URL: http://llvm.org/viewvc/llvm-project?rev=63366&view=rev
Log:
Propagate debug loc info in DAG combine's "ADD".

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63366&r1=63365&r2=63366&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 29 20:31:17 2009
@@ -1016,7 +1016,7 @@
     return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
   // canonicalize constant to RHS
   if (N0C && !N1C)
-    return DAG.getNode(ISD::ADD, VT, N1, N0);
+    return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
   // fold (add x, 0) -> x
   if (N1C && N1C->isNullValue())
     return N0;
@@ -1030,7 +1030,7 @@
   // fold ((c1-A)+c2) -> (c1+c2)-A
   if (N1C && N0.getOpcode() == ISD::SUB)
     if (ConstantSDNode *N0C = dyn_cast(N0.getOperand(0)))
-      return DAG.getNode(ISD::SUB, VT,
+      return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
                          DAG.getConstant(N1C->getAPIntValue()+
                                          N0C->getAPIntValue(), VT),
                          N0.getOperand(1));
@@ -1041,11 +1041,11 @@
   // fold ((0-A) + B) -> B-A
   if (N0.getOpcode() == ISD::SUB && isa(N0.getOperand(0)) &&
       cast(N0.getOperand(0))->isNullValue())
-    return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
+    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
   // fold (A + (0-B)) -> A-B
   if (N1.getOpcode() == ISD::SUB && isa(N1.getOperand(0)) &&
       cast(N1.getOperand(0))->isNullValue())
-    return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
+    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
   // fold (A+(B-A)) -> B
   if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
     return N1.getOperand(0);
@@ -1054,23 +1054,20 @@
     return N0.getOperand(0);
   // fold (A+(B-(A+C))) to (B-C)
   if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
-      N0 == N1.getOperand(1).getOperand(0)) {
-    return DAG.getNode(ISD::SUB, VT, N1.getOperand(0),
+      N0 == N1.getOperand(1).getOperand(0))
+    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
                        N1.getOperand(1).getOperand(1));
-  }
   // fold (A+(B-(C+A))) to (B-C)
   if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
-      N0 == N1.getOperand(1).getOperand(1)) {
-    return DAG.getNode(ISD::SUB, VT, N1.getOperand(0),
+      N0 == N1.getOperand(1).getOperand(1))
+    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
                        N1.getOperand(1).getOperand(0));
-  }
   // fold (A+((B-A)+or-C)) to (B+or-C)
   if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
       N1.getOperand(0).getOpcode() == ISD::SUB &&
-      N0 == N1.getOperand(0).getOperand(1)) {
-    return DAG.getNode(N1.getOpcode(), VT, N1.getOperand(0).getOperand(0),
-                       N1.getOperand(1));
-  }
+      N0 == N1.getOperand(0).getOperand(1))
+    return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
+                       N1.getOperand(0).getOperand(0), N1.getOperand(1));
 
   // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
   if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
@@ -1078,11 +1075,11 @@
     SDValue N01 = N0.getOperand(1);
     SDValue N10 = N1.getOperand(0);
     SDValue N11 = N1.getOperand(1);
-    if (isa(N00) || isa(N10)) {
-      return DAG.getNode(ISD::SUB, VT,
-                 DAG.getNode(ISD::ADD, VT, N00, N10),
-                 DAG.getNode(ISD::ADD, VT, N01, N11));
-    }
+
+    if (isa(N00) || isa(N10))
+      return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
+                         DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
+                         DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
   }
 
   if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
@@ -1094,6 +1091,7 @@
     APInt RHSZero, RHSOne;
     APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
     DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
+
     if (LHSZero.getBoolValue()) {
       DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
       
@@ -1101,7 +1099,7 @@
       // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
       if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
           (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
-        return DAG.getNode(ISD::OR, VT, N0, N1);
+        return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
     }
   }
 




From isanbard at gmail.com  Thu Jan 29 20:38:01 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 30 Jan 2009 02:38:01 -0000
Subject: [llvm-commits] [llvm] r63367 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <200901300238.n0U2c1RK030262@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 20:38:00 2009
New Revision: 63367

URL: http://llvm.org/viewvc/llvm-project?rev=63367&view=rev
Log:
Propagate debug loc info in ADDC and ADDE.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63367&r1=63366&r2=63367&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 29 20:38:00 2009
@@ -1135,22 +1135,25 @@
   
   // If the flag result is dead, turn this into an ADD.
   if (N->hasNUsesOfValue(0, 1))
-    return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
-                     DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
+    return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
+                     DAG.getNode(ISD::CARRY_FALSE,
+                                 N->getDebugLoc(), MVT::Flag));
   
   // canonicalize constant to RHS.
   if (N0C && !N1C)
-    return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0);
+    return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
   
   // fold (addc x, 0) -> x + no carry out
   if (N1C && N1C->isNullValue())
-    return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
+    return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
+                                        N->getDebugLoc(), MVT::Flag));
   
   // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
   APInt LHSZero, LHSOne;
   APInt RHSZero, RHSOne;
   APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
   DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
+
   if (LHSZero.getBoolValue()) {
     DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
     
@@ -1158,8 +1161,9 @@
     // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
     if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
         (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
-      return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
-                       DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
+      return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
+                       DAG.getNode(ISD::CARRY_FALSE,
+                                   N->getDebugLoc(), MVT::Flag));
   }
   
   return SDValue();
@@ -1171,21 +1175,19 @@
   SDValue CarryIn = N->getOperand(2);
   ConstantSDNode *N0C = dyn_cast(N0);
   ConstantSDNode *N1C = dyn_cast(N1);
-  //MVT VT = N0.getValueType();
   
   // canonicalize constant to RHS
   if (N0C && !N1C)
-    return DAG.getNode(ISD::ADDE, N->getVTList(), N1, N0, CarryIn);
+    return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
+                       N1, N0, CarryIn);
   
   // fold (adde x, y, false) -> (addc x, y)
   if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
-    return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0);
+    return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
   
   return SDValue();
 }
 
-
-
 SDValue DAGCombiner::visitSUB(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);




From isanbard at gmail.com  Thu Jan 29 20:42:10 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 30 Jan 2009 02:42:10 -0000
Subject: [llvm-commits] [llvm] r63368 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <200901300242.n0U2gAQP030430@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 20:42:10 2009
New Revision: 63368

URL: http://llvm.org/viewvc/llvm-project?rev=63368&view=rev
Log:
Propagate debug loc info in SUB.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63368&r1=63367&r2=63368&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 29 20:42:10 2009
@@ -1209,7 +1209,7 @@
     return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
   // fold (sub x, c) -> (add x, -c)
   if (N1C)
-    return DAG.getNode(ISD::ADD, VT, N0,
+    return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
                        DAG.getConstant(-N1C->getAPIntValue(), VT));
   // fold (A+B)-A -> B
   if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
@@ -1222,25 +1222,26 @@
       (N0.getOperand(1).getOpcode() == ISD::SUB ||
        N0.getOperand(1).getOpcode() == ISD::ADD) &&
       N0.getOperand(1).getOperand(0) == N1)
-    return DAG.getNode(N0.getOperand(1).getOpcode(), VT, N0.getOperand(0), 
-                                     N0.getOperand(1).getOperand(1));
+    return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
+                       N0.getOperand(0), N0.getOperand(1).getOperand(1));
   // fold ((A+(C+B))-B) -> A+C
   if (N0.getOpcode() == ISD::ADD &&
       N0.getOperand(1).getOpcode() == ISD::ADD &&
       N0.getOperand(1).getOperand(1) == N1)
-    return DAG.getNode(ISD::ADD, VT, N0.getOperand(0), 
-                                     N0.getOperand(1).getOperand(0));
+    return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
+                       N0.getOperand(0), N0.getOperand(1).getOperand(0));
   // fold ((A-(B-C))-C) -> A-B
   if (N0.getOpcode() == ISD::SUB &&
       N0.getOperand(1).getOpcode() == ISD::SUB &&
       N0.getOperand(1).getOperand(1) == N1)
-    return DAG.getNode(ISD::SUB, VT, N0.getOperand(0), 
-                                     N0.getOperand(1).getOperand(0));
+    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
+                       N0.getOperand(0), N0.getOperand(1).getOperand(0));
   // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
   if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
     SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations);
     if (Result.getNode()) return Result;
   }
+
   // If either operand of a sub is undef, the result is undef
   if (N0.getOpcode() == ISD::UNDEF)
     return N0;




From isanbard at gmail.com  Thu Jan 29 20:45:56 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 30 Jan 2009 02:45:56 -0000
Subject: [llvm-commits] [llvm] r63369 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <200901300245.n0U2ju75030589@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 20:45:56 2009
New Revision: 63369

URL: http://llvm.org/viewvc/llvm-project?rev=63369&view=rev
Log:
Propagate debug loc info for MUL.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63369&r1=63368&r2=63369&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 29 20:45:56 2009
@@ -1287,34 +1287,36 @@
     return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
   // canonicalize constant to RHS
   if (N0C && !N1C)
-    return DAG.getNode(ISD::MUL, VT, N1, N0);
+    return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
   // fold (mul x, 0) -> 0
   if (N1C && N1C->isNullValue())
     return N1;
   // fold (mul x, -1) -> 0-x
   if (N1C && N1C->isAllOnesValue())
-    return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
+    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
+                       DAG.getConstant(0, VT), N0);
   // fold (mul x, (1 << c)) -> x << c
   if (N1C && N1C->getAPIntValue().isPowerOf2())
-    return DAG.getNode(ISD::SHL, VT, N0,
+    return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
                        DAG.getConstant(N1C->getAPIntValue().logBase2(),
                                        TLI.getShiftAmountTy()));
   // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
-  if (N1C && isPowerOf2_64(-N1C->getSExtValue())) {
+  if (N1C && isPowerOf2_64(-N1C->getSExtValue()))
     // FIXME: If the input is something that is easily negated (e.g. a 
     // single-use add), we should put the negate there.
-    return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
+    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
+                       DAG.getConstant(0, VT),
                        DAG.getNode(ISD::SHL, VT, N0,
                             DAG.getConstant(Log2_64(-N1C->getSExtValue()),
                                             TLI.getShiftAmountTy())));
-  }
-
   // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
   if (N1C && N0.getOpcode() == ISD::SHL && 
       isa(N0.getOperand(1))) {
-    SDValue C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
+    SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
+                             N1, N0.getOperand(1));
     AddToWorkList(C3.getNode());
-    return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
+    return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
+                       N0.getOperand(0), C3);
   }
   
   // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
@@ -1331,17 +1333,20 @@
       Sh = N1; Y = N0;
     }
     if (Sh.getNode()) {
-      SDValue Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
-      return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
+      SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
+                                Sh.getOperand(0), Y);
+      return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
+                         Mul, Sh.getOperand(1));
     }
   }
   // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
   if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 
-      isa(N0.getOperand(1))) {
-    return DAG.getNode(ISD::ADD, VT, 
-                       DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
-                       DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
-  }
+      isa(N0.getOperand(1)))
+    return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
+                       DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
+                                   N0.getOperand(0), N1),
+                       DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
+                                   N0.getOperand(1), N1));
   
   // reassociate mul
   SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);




From gohman at apple.com  Thu Jan 29 20:49:14 2009
From: gohman at apple.com (Dan Gohman)
Date: Fri, 30 Jan 2009 02:49:14 -0000
Subject: [llvm-commits] [llvm] r63370 - in /llvm/trunk:
 include/llvm/Analysis/AliasAnalysis.h lib/Analysis/BasicAliasAnalysis.cpp
 lib/CodeGen/ScheduleDAGInstrs.cpp
Message-ID: <200901300249.n0U2nFtJ030721@zion.cs.uiuc.edu>

Author: djg
Date: Thu Jan 29 20:49:14 2009
New Revision: 63370

URL: http://llvm.org/viewvc/llvm-project?rev=63370&view=rev
Log:
Fix a post-RA scheduling dependency bug.

If a MachineInstr doesn't have a memoperand but has an opcode that
is known to load or store, assume its memory reference may alias
*anything*, including stack slots which the compiler completely
controls.

To partially compensate for this, teach the ScheduleDAG building
code to do basic getUnderlyingValue analysis. This greatly
reduces the number of instructions that require restrictive
dependencies. This code will need to be revisited when we start
doing real alias analysis, but it should suffice for now.

Modified:
    llvm/trunk/include/llvm/Analysis/AliasAnalysis.h
    llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
    llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp

Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=63370&r1=63369&r2=63370&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original)
+++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Thu Jan 29 20:49:14 2009
@@ -345,6 +345,11 @@
   }
 };
 
+/// isIdentifiedObject - Return true if this pointer refers to a distinct and
+/// identifiable object.
+///
+bool isIdentifiedObject(const Value *V);
+
 } // End llvm namespace
 
 // Because of the way .a files work, we must force the BasicAA implementation to

Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=63370&r1=63369&r2=63370&view=diff

==============================================================================
--- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Thu Jan 29 20:49:14 2009
@@ -80,7 +80,7 @@
 ///    ByVal and NoAlias Arguments
 ///    NoAlias returns
 ///
-static bool isIdentifiedObject(const Value *V) {
+bool llvm::isIdentifiedObject(const Value *V) {
   if (isa(V) || isa(V) || isNoAliasCall(V))
     return true;
   if (const Argument *A = dyn_cast(V))

Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=63370&r1=63369&r2=63370&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Thu Jan 29 20:49:14 2009
@@ -13,6 +13,7 @@
 //===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "sched-instrs"
+#include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
@@ -95,6 +96,82 @@
                                      const MachineDominatorTree &mdt)
   : ScheduleDAG(mf), MLI(mli), MDT(mdt) {}
 
+/// getOpcode - If this is an Instruction or a ConstantExpr, return the
+/// opcode value. Otherwise return UserOp1.
+static unsigned getOpcode(const Value *V) {
+  if (const Instruction *I = dyn_cast(V))
+    return I->getOpcode();
+  if (const ConstantExpr *CE = dyn_cast(V))
+    return CE->getOpcode();
+  // Use UserOp1 to mean there's no opcode.
+  return Instruction::UserOp1;
+}
+
+/// getUnderlyingObjectFromInt - This is the function that does the work of
+/// looking through basic ptrtoint+arithmetic+inttoptr sequences.
+static const Value *getUnderlyingObjectFromInt(const Value *V) {
+  do {
+    if (const User *U = dyn_cast(V)) {
+      // If we find a ptrtoint, we can transfer control back to the
+      // regular getUnderlyingObjectFromInt.
+      if (getOpcode(U) == Instruction::PtrToInt)
+        return U->getOperand(0);
+      // If we find an add of a constant or a multiplied value, it's
+      // likely that the other operand will lead us to the base
+      // object. We don't have to worry about the case where the
+      // object address is somehow being computed bt the multiply,
+      // because our callers only care when the result is an
+      // identifibale object.
+      if (getOpcode(U) != Instruction::Add ||
+          (!isa(U->getOperand(1)) &&
+           getOpcode(U->getOperand(1)) != Instruction::Mul))
+        return V;
+      V = U->getOperand(0);
+    } else {
+      return V;
+    }
+    assert(isa(V->getType()) && "Unexpected operand type!");
+  } while (1);
+}
+
+/// getUnderlyingObject - This is a wrapper around Value::getUnderlyingObject
+/// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
+static const Value *getUnderlyingObject(const Value *V) {
+  // First just call Value::getUnderlyingObject to let it do what it does.
+  do {
+    V = V->getUnderlyingObject();
+    // If it found an inttoptr, use special code to continue climing.
+    if (getOpcode(V) != Instruction::IntToPtr)
+      break;
+    const Value *O = getUnderlyingObjectFromInt(cast(V)->getOperand(0));
+    // If that succeeded in finding a pointer, continue the search.
+    if (!isa(O->getType()))
+      break;
+    V = O;
+  } while (1);
+  return V;
+}
+
+/// getUnderlyingObjectForInstr - If this machine instr has memory reference
+/// information and it can be tracked to a normal reference to a known
+/// object, return the Value for that object. Otherwise return null.
+static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI) {
+  if (!MI->hasOneMemOperand() ||
+      !MI->memoperands_begin()->getValue() ||
+      MI->memoperands_begin()->isVolatile())
+    return 0;
+
+  const Value *V = MI->memoperands_begin()->getValue();
+  if (!V)
+    return 0;
+
+  V = getUnderlyingObject(V);
+  if (!isa(V) && !isIdentifiedObject(V))
+    return 0;
+
+  return V;
+}
+
 void ScheduleDAGInstrs::BuildSchedGraph() {
   SUnits.reserve(BB->size());
 
@@ -313,12 +390,8 @@
         // Unknown memory accesses. Assume the worst.
         ChainMMO = 0;
     } else if (TID.mayStore()) {
-      if (MI->hasOneMemOperand() &&
-          MI->memoperands_begin()->getValue() &&
-          !MI->memoperands_begin()->isVolatile() &&
-          isa(MI->memoperands_begin()->getValue())) {
+      if (const Value *V = getUnderlyingObjectForInstr(MI)) {
         // A store to a specific PseudoSourceValue. Add precise dependencies.
-        const Value *V = MI->memoperands_begin()->getValue();
         // Handle the def in MemDefs, if there is one.
         std::map::iterator I = MemDefs.find(V);
         if (I != MemDefs.end()) {
@@ -337,6 +410,10 @@
                                        /*isNormalMemory=*/true));
           J->second.clear();
         }
+        // Add dependencies from all the PendingLoads, since without
+        // memoperands we must assume they alias anything.
+        for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
+          PendingLoads[k]->addPred(SDep(SU, SDep::Order, SU->Latency));
         // Add a general dependence too, if needed.
         if (Chain)
           Chain->addPred(SDep(SU, SDep::Order, SU->Latency));
@@ -346,12 +423,8 @@
     } else if (TID.mayLoad()) {
       if (TII->isInvariantLoad(MI)) {
         // Invariant load, no chain dependencies needed!
-      } else if (MI->hasOneMemOperand() &&
-                 MI->memoperands_begin()->getValue() &&
-                 !MI->memoperands_begin()->isVolatile() &&
-                 isa(MI->memoperands_begin()->getValue())) {
+      } else if (const Value *V = getUnderlyingObjectForInstr(MI)) {
         // A load from a specific PseudoSourceValue. Add precise dependencies.
-        const Value *V = MI->memoperands_begin()->getValue();
         std::map::iterator I = MemDefs.find(V);
         if (I != MemDefs.end())
           I->second->addPred(SDep(SU, SDep::Order, SU->Latency, /*Reg=*/0,
@@ -367,9 +440,15 @@
         // cases where memoperand information is unavailable.
         goto new_chain;
       } else {
-        // A normal load. Just depend on the general chain.
+        // A normal load. Depend on the general chain, as well as on
+        // all stores. In the absense of MachineMemOperand information,
+        // we can't even assume that the load doesn't alias well-behaved
+        // memory locations.
         if (Chain)
           Chain->addPred(SDep(SU, SDep::Order, SU->Latency));
+        for (std::map::iterator I = MemDefs.begin(),
+             E = MemDefs.end(); I != E; ++I)
+          I->second->addPred(SDep(SU, SDep::Order, SU->Latency));
         PendingLoads.push_back(SU);
       }
     }




From isanbard at gmail.com  Thu Jan 29 20:49:26 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 30 Jan 2009 02:49:26 -0000
Subject: [llvm-commits] [llvm] r63371 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <200901300249.n0U2nQ1T030737@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 20:49:26 2009
New Revision: 63371

URL: http://llvm.org/viewvc/llvm-project?rev=63371&view=rev
Log:
Forgot to propagate debug loc info here.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63371&r1=63370&r2=63371&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 29 20:49:26 2009
@@ -1306,11 +1306,11 @@
     // single-use add), we should put the negate there.
     return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
                        DAG.getConstant(0, VT),
-                       DAG.getNode(ISD::SHL, VT, N0,
+                       DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
                             DAG.getConstant(Log2_64(-N1C->getSExtValue()),
                                             TLI.getShiftAmountTy())));
   // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
-  if (N1C && N0.getOpcode() == ISD::SHL && 
+  if (N1C && N0.getOpcode() == ISD::SHL &&
       isa(N0.getOperand(1))) {
     SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
                              N1, N0.getOperand(1));
@@ -1332,6 +1332,7 @@
                N1.getNode()->hasOneUse()) {
       Sh = N1; Y = N0;
     }
+
     if (Sh.getNode()) {
       SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
                                 Sh.getOperand(0), Y);
@@ -1339,6 +1340,7 @@
                          Mul, Sh.getOperand(1));
     }
   }
+
   // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
   if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 
       isa(N0.getOperand(1)))




From isanbard at gmail.com  Thu Jan 29 20:52:17 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 30 Jan 2009 02:52:17 -0000
Subject: [llvm-commits] [llvm] r63372 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <200901300252.n0U2qIsE030906@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 20:52:17 2009
New Revision: 63372

URL: http://llvm.org/viewvc/llvm-project?rev=63372&view=rev
Log:
Propagate debug loc info for SDIV.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63372&r1=63371&r2=63372&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 29 20:52:17 2009
@@ -1379,12 +1379,14 @@
     return N0;
   // fold (sdiv X, -1) -> 0-X
   if (N1C && N1C->isAllOnesValue())
-    return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
+    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
+                       DAG.getConstant(0, VT), N0);
   // If we know the sign bits of both operands are zero, strength reduce to a
   // udiv instead.  Handles (X&15) /s 4 -> X&15 >> 2
   if (!VT.isVector()) {
     if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
-      return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
+      return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
+                         N0, N1);
   }
   // fold (sdiv X, pow2) -> simple ops after legalize
   if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
@@ -1394,30 +1396,37 @@
     // fold.
     if (TLI.isPow2DivCheap())
       return SDValue();
+
     int64_t pow2 = N1C->getSExtValue();
     int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
     unsigned lg2 = Log2_64(abs2);
+
     // Splat the sign bit into the register
-    SDValue SGN = DAG.getNode(ISD::SRA, VT, N0,
-                                DAG.getConstant(VT.getSizeInBits()-1,
-                                                TLI.getShiftAmountTy()));
+    SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
+                              DAG.getConstant(VT.getSizeInBits()-1,
+                                              TLI.getShiftAmountTy()));
     AddToWorkList(SGN.getNode());
+
     // Add (N0 < 0) ? abs2 - 1 : 0;
-    SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN,
-                                DAG.getConstant(VT.getSizeInBits()-lg2,
-                                                TLI.getShiftAmountTy()));
-    SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
+    SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
+                              DAG.getConstant(VT.getSizeInBits() - lg2,
+                                              TLI.getShiftAmountTy()));
+    SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
     AddToWorkList(SRL.getNode());
     AddToWorkList(ADD.getNode());    // Divide by pow2
-    SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD,
-                                DAG.getConstant(lg2, TLI.getShiftAmountTy()));
+    SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
+                              DAG.getConstant(lg2, TLI.getShiftAmountTy()));
+
     // If we're dividing by a positive value, we're done.  Otherwise, we must
     // negate the result.
     if (pow2 > 0)
       return SRA;
+
     AddToWorkList(SRA.getNode());
-    return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
+    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
+                       DAG.getConstant(0, VT), SRA);
   }
+
   // if integer divide is expensive and we satisfy the requirements, emit an
   // alternate sequence.
   if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 




From isanbard at gmail.com  Thu Jan 29 20:55:26 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 30 Jan 2009 02:55:26 -0000
Subject: [llvm-commits] [llvm] r63373 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <200901300255.n0U2tQ5G031036@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 20:55:25 2009
New Revision: 63373

URL: http://llvm.org/viewvc/llvm-project?rev=63373&view=rev
Log:
Propagate debug loc info for UDIV.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63373&r1=63372&r2=63373&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 29 20:55:25 2009
@@ -1463,7 +1463,7 @@
     return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
   // fold (udiv x, (1 << c)) -> x >>u c
   if (N1C && N1C->getAPIntValue().isPowerOf2())
-    return DAG.getNode(ISD::SRL, VT, N0, 
+    return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 
                        DAG.getConstant(N1C->getAPIntValue().logBase2(),
                                        TLI.getShiftAmountTy()));
   // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
@@ -1471,12 +1471,13 @@
     if (ConstantSDNode *SHC = dyn_cast(N1.getOperand(0))) {
       if (SHC->getAPIntValue().isPowerOf2()) {
         MVT ADDVT = N1.getOperand(1).getValueType();
-        SDValue Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
-                                    DAG.getConstant(SHC->getAPIntValue()
-                                                                    .logBase2(),
-                                                    ADDVT));
+        SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
+                                  N1.getOperand(1),
+                                  DAG.getConstant(SHC->getAPIntValue()
+                                                                  .logBase2(),
+                                                  ADDVT));
         AddToWorkList(Add.getNode());
-        return DAG.getNode(ISD::SRL, VT, N0, Add);
+        return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
       }
     }
   }




From isanbard at gmail.com  Thu Jan 29 20:57:00 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 30 Jan 2009 02:57:00 -0000
Subject: [llvm-commits] [llvm] r63374 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <200901300257.n0U2v1Pb031086@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 20:57:00 2009
New Revision: 63374

URL: http://llvm.org/viewvc/llvm-project?rev=63374&view=rev
Log:
Propagate debug loc info for SREM and UREM.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63374&r1=63373&r2=63374&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 29 20:57:00 2009
@@ -1511,18 +1511,19 @@
   // urem instead.  Handles (X & 0x0FFFFFFF) %s 16 -> X&15
   if (!VT.isVector()) {
     if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
-      return DAG.getNode(ISD::UREM, VT, N0, N1);
+      return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
   }
   
   // If X/C can be simplified by the division-by-constant logic, lower
   // X%C to the equivalent of X-X/C*C.
   if (N1C && !N1C->isNullValue()) {
-    SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
+    SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
     AddToWorkList(Div.getNode());
     SDValue OptimizedDiv = combine(Div.getNode());
     if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
-      SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
-      SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
+      SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
+                                OptimizedDiv, N1);
+      SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
       AddToWorkList(Mul.getNode());
       return Sub;
     }
@@ -1550,18 +1551,18 @@
     return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
   // fold (urem x, pow2) -> (and x, pow2-1)
   if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
-    return DAG.getNode(ISD::AND, VT, N0,
+    return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
                        DAG.getConstant(N1C->getAPIntValue()-1,VT));
   // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
   if (N1.getOpcode() == ISD::SHL) {
     if (ConstantSDNode *SHC = dyn_cast(N1.getOperand(0))) {
       if (SHC->getAPIntValue().isPowerOf2()) {
         SDValue Add =
-          DAG.getNode(ISD::ADD, VT, N1,
+          DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
                  DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
                                  VT));
         AddToWorkList(Add.getNode());
-        return DAG.getNode(ISD::AND, VT, N0, Add);
+        return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
       }
     }
   }
@@ -1569,12 +1570,13 @@
   // If X/C can be simplified by the division-by-constant logic, lower
   // X%C to the equivalent of X-X/C*C.
   if (N1C && !N1C->isNullValue()) {
-    SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
+    SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
     AddToWorkList(Div.getNode());
     SDValue OptimizedDiv = combine(Div.getNode());
     if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
-      SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
-      SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
+      SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
+                                OptimizedDiv, N1);
+      SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
       AddToWorkList(Mul.getNode());
       return Sub;
     }




From isanbard at gmail.com  Thu Jan 29 21:00:18 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 30 Jan 2009 03:00:18 -0000
Subject: [llvm-commits] [llvm] r63375 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <200901300300.n0U30JmT031230@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 21:00:18 2009
New Revision: 63375

URL: http://llvm.org/viewvc/llvm-project?rev=63375&view=rev
Log:
Propagate debug loc info for MULHS.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63375&r1=63374&r2=63375&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 29 21:00:18 2009
@@ -1603,8 +1603,8 @@
     return N1;
   // fold (mulhs x, 1) -> (sra x, size(x)-1)
   if (N1C && N1C->getAPIntValue() == 1)
-    return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 
-                       DAG.getConstant(N0.getValueType().getSizeInBits()-1,
+    return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
+                       DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
                                        TLI.getShiftAmountTy()));
   // fold (mulhs x, undef) -> 0
   if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)




From isanbard at gmail.com  Thu Jan 29 21:08:40 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 30 Jan 2009 03:08:40 -0000
Subject: [llvm-commits] [llvm] r63376 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <200901300308.n0U38ead031475@zion.cs.uiuc.edu>

Author: void
Date: Thu Jan 29 21:08:40 2009
New Revision: 63376

URL: http://llvm.org/viewvc/llvm-project?rev=63376&view=rev
Log:
Propagate debug loc info in SimplifyNodeWithTwoResults.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63376&r1=63375&r2=63376&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 29 21:08:40 2009
@@ -1643,8 +1643,8 @@
   if (!HiExists &&
       (!LegalOperations ||
        TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
-    SDValue Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(),
-                              N->getNumOperands());
+    SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
+                              N->op_begin(), N->getNumOperands());
     return CombineTo(N, Res, Res);
   }
 
@@ -1653,8 +1653,8 @@
   if (!LoExists &&
       (!LegalOperations ||
        TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
-    SDValue Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(),
-                              N->getNumOperands());
+    SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
+                              N->op_begin(), N->getNumOperands());
     return CombineTo(N, Res, Res);
   }
 
@@ -1664,8 +1664,8 @@
 
   // If the two computed results can be simplified separately, separate them.
   if (LoExists) {
-    SDValue Lo = DAG.getNode(LoOp, N->getValueType(0),
-                               N->op_begin(), N->getNumOperands());
+    SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
+                             N->op_begin(), N->getNumOperands());
     AddToWorkList(Lo.getNode());
     SDValue LoOpt = combine(Lo.getNode());
     if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
@@ -1675,7 +1675,7 @@
   }
 
   if (HiExists) {
-    SDValue Hi = DAG.getNode(HiOp, N->getValueType(1),
+    SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
                              N->op_begin(), N->getNumOperands());
     AddToWorkList(Hi.getNode());
     SDValue HiOpt = combine(Hi.getNode());
@@ -1684,6 +1684,7 @@
          TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
       return CombineTo(N, HiOpt, HiOpt);
   }
+
   return SDValue();
 }
 




From sanjiv.gupta at microchip.com  Thu Jan 29 22:25:18 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Fri, 30 Jan 2009 04:25:18 -0000
Subject: [llvm-commits] [llvm] r63377 - in /llvm/trunk:
 include/llvm/CodeGen/AsmPrinter.h include/llvm/Target/TargetAsmInfo.h
 lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/Target/PIC16/PIC16AsmPrinter.cpp
 lib/Target/PIC16/PIC16AsmPrinter.h lib/Target/PIC16/PIC16TargetAsmInfo.cpp
 lib/Target/PIC16/PIC16TargetAsmInfo.h
Message-ID: <200901300425.n0U4PJlC001274@zion.cs.uiuc.edu>

Author: sgupta
Date: Thu Jan 29 22:25:10 2009
New Revision: 63377

URL: http://llvm.org/viewvc/llvm-project?rev=63377&view=rev
Log:
Enable emitting of constant values in non-default address space as well. The APIs emitting constants now take an additional parameter signifying the address space in which to emit. The APIs like getData8BitsDirective() etc are made virtual enabling targets to be able to define appropirate directivers for various sizes and address spaces.

Modified:
    llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
    llvm/trunk/include/llvm/Target/TargetAsmInfo.h
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
    llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.cpp
    llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.h

Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=63377&r1=63376&r2=63377&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Thu Jan 29 22:25:10 2009
@@ -309,7 +309,7 @@
   protected:
     /// EmitZeros - Emit a block of zeros.
     ///
-    void EmitZeros(uint64_t NumZeros) const;
+    void EmitZeros(uint64_t NumZeros, unsigned AddrSpace = 0) const;
 
     /// EmitString - Emit a zero-byte-terminated string constant.
     ///
@@ -320,7 +320,7 @@
     void EmitConstantValueOnly(const Constant *CV);
 
     /// EmitGlobalConstant - Print a general LLVM constant to the .s file.
-    void EmitGlobalConstant(const Constant* CV);
+    void EmitGlobalConstant(const Constant* CV, unsigned AddrSpace = 0);
 
     virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV);
     
@@ -351,7 +351,7 @@
     
     /// printDataDirective - This method prints the asm directive for the
     /// specified type.
-    void printDataDirective(const Type *type);
+    void printDataDirective(const Type *type, unsigned AddrSpace = 0);
 
     /// printSuffixedName - This prints a name with preceding 
     /// getPrivateGlobalPrefix and the specified suffix, handling quoted names
@@ -371,11 +371,12 @@
     const GlobalValue *findGlobalValue(const Constant* CV);
     void EmitLLVMUsedList(Constant *List);
     void EmitXXStructorList(Constant *List);
-    void EmitGlobalConstantStruct(const ConstantStruct* CVS);
+    void EmitGlobalConstantStruct(const ConstantStruct* CVS,
+                                  unsigned AddrSpace);
     void EmitGlobalConstantArray(const ConstantArray* CVA);
     void EmitGlobalConstantVector(const ConstantVector* CP);
-    void EmitGlobalConstantFP(const ConstantFP* CFP);
-    void EmitGlobalConstantLargeInt(const ConstantInt* CI);
+    void EmitGlobalConstantFP(const ConstantFP* CFP, unsigned AddrSpace);
+    void EmitGlobalConstantLargeInt(const ConstantInt* CI, unsigned AddrSpace);
     GCMetadataPrinter *GetOrCreateGCPrinter(GCStrategy *C);
   };
 }

Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=63377&r1=63376&r2=63377&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Thu Jan 29 22:25:10 2009
@@ -598,6 +598,21 @@
 
     static unsigned getULEB128Size(unsigned Value);
 
+    // Data directive accessors
+    //
+    virtual const char *getData8bitsDirective(unsigned AddrSpace = 0) const {
+      return Data8bitsDirective;
+    }
+    virtual const char *getData16bitsDirective(unsigned AddrSpace = 0) const {
+      return Data16bitsDirective;
+    }
+    virtual const char *getData32bitsDirective(unsigned AddrSpace = 0) const {
+      return Data32bitsDirective;
+    }
+    virtual const char *getData64bitsDirective(unsigned AddrSpace = 0) const {
+      return Data64bitsDirective;
+    }
+
     // Accessors.
     //
     const Section *getTextSection() const {
@@ -711,18 +726,6 @@
     const char *getAscizDirective() const {
       return AscizDirective;
     }
-    const char *getData8bitsDirective() const {
-      return Data8bitsDirective;
-    }
-    const char *getData16bitsDirective() const {
-      return Data16bitsDirective;
-    }
-    const char *getData32bitsDirective() const {
-      return Data32bitsDirective;
-    }
-    const char *getData64bitsDirective() const {
-      return Data64bitsDirective;
-    }
     const char *getJumpTableDirective() const {
       return JumpTableDirective;
     }

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=63377&r1=63376&r2=63377&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Jan 29 22:25:10 2009
@@ -770,7 +770,7 @@
     
 /// EmitZeros - Emit a block of zeros.
 ///
-void AsmPrinter::EmitZeros(uint64_t NumZeros) const {
+void AsmPrinter::EmitZeros(uint64_t NumZeros, unsigned AddrSpace) const {
   if (NumZeros) {
     if (TAI->getZeroDirective()) {
       O << TAI->getZeroDirective() << NumZeros;
@@ -779,7 +779,7 @@
       O << '\n';
     } else {
       for (; NumZeros; --NumZeros)
-        O << TAI->getData8bitsDirective() << "0\n";
+        O << TAI->getData8bitsDirective(AddrSpace) << "0\n";
     }
   }
 }
@@ -956,7 +956,8 @@
     EmitGlobalConstant(CP->getOperand(I));
 }
 
-void AsmPrinter::EmitGlobalConstantStruct(const ConstantStruct *CVS) {
+void AsmPrinter::EmitGlobalConstantStruct(const ConstantStruct *CVS,
+                                          unsigned AddrSpace) {
   // Print the fields in successive locations. Pad to align if needed!
   const TargetData *TD = TM.getTargetData();
   unsigned Size = TD->getTypePaddedSize(CVS->getType());
@@ -972,46 +973,47 @@
     sizeSoFar += fieldSize + padSize;
 
     // Now print the actual field value.
-    EmitGlobalConstant(field);
+    EmitGlobalConstant(field, AddrSpace);
 
     // Insert padding - this may include padding to increase the size of the
     // current field up to the ABI size (if the struct is not packed) as well
     // as padding to ensure that the next field starts at the right offset.
-    EmitZeros(padSize);
+    EmitZeros(padSize, AddrSpace);
   }
   assert(sizeSoFar == cvsLayout->getSizeInBytes() &&
          "Layout of constant struct may be incorrect!");
 }
 
-void AsmPrinter::EmitGlobalConstantFP(const ConstantFP *CFP) {
+void AsmPrinter::EmitGlobalConstantFP(const ConstantFP *CFP, 
+                                      unsigned AddrSpace) {
   // FP Constants are printed as integer constants to avoid losing
   // precision...
   const TargetData *TD = TM.getTargetData();
   if (CFP->getType() == Type::DoubleTy) {
     double Val = CFP->getValueAPF().convertToDouble();  // for comment only
     uint64_t i = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
-    if (TAI->getData64bitsDirective())
-      O << TAI->getData64bitsDirective() << i << '\t'
+    if (TAI->getData64bitsDirective(AddrSpace))
+      O << TAI->getData64bitsDirective(AddrSpace) << i << '\t'
         << TAI->getCommentString() << " double value: " << Val << '\n';
     else if (TD->isBigEndian()) {
-      O << TAI->getData32bitsDirective() << unsigned(i >> 32)
+      O << TAI->getData32bitsDirective(AddrSpace) << unsigned(i >> 32)
         << '\t' << TAI->getCommentString()
         << " double most significant word " << Val << '\n';
-      O << TAI->getData32bitsDirective() << unsigned(i)
+      O << TAI->getData32bitsDirective(AddrSpace) << unsigned(i)
         << '\t' << TAI->getCommentString()
         << " double least significant word " << Val << '\n';
     } else {
-      O << TAI->getData32bitsDirective() << unsigned(i)
+      O << TAI->getData32bitsDirective(AddrSpace) << unsigned(i)
         << '\t' << TAI->getCommentString()
         << " double least significant word " << Val << '\n';
-      O << TAI->getData32bitsDirective() << unsigned(i >> 32)
+      O << TAI->getData32bitsDirective(AddrSpace) << unsigned(i >> 32)
         << '\t' << TAI->getCommentString()
         << " double most significant word " << Val << '\n';
     }
     return;
   } else if (CFP->getType() == Type::FloatTy) {
     float Val = CFP->getValueAPF().convertToFloat();  // for comment only
-    O << TAI->getData32bitsDirective()
+    O << TAI->getData32bitsDirective(AddrSpace)
       << CFP->getValueAPF().bitcastToAPInt().getZExtValue()
       << '\t' << TAI->getCommentString() << " float " << Val << '\n';
     return;
@@ -1026,42 +1028,42 @@
     DoubleVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
                       &ignored);
     if (TD->isBigEndian()) {
-      O << TAI->getData16bitsDirective() << uint16_t(p[0] >> 48)
+      O << TAI->getData16bitsDirective(AddrSpace) << uint16_t(p[0] >> 48)
         << '\t' << TAI->getCommentString()
         << " long double most significant halfword of ~"
         << DoubleVal.convertToDouble() << '\n';
-      O << TAI->getData16bitsDirective() << uint16_t(p[0] >> 32)
+      O << TAI->getData16bitsDirective(AddrSpace) << uint16_t(p[0] >> 32)
         << '\t' << TAI->getCommentString()
         << " long double next halfword\n";
-      O << TAI->getData16bitsDirective() << uint16_t(p[0] >> 16)
+      O << TAI->getData16bitsDirective(AddrSpace) << uint16_t(p[0] >> 16)
         << '\t' << TAI->getCommentString()
         << " long double next halfword\n";
-      O << TAI->getData16bitsDirective() << uint16_t(p[0])
+      O << TAI->getData16bitsDirective(AddrSpace) << uint16_t(p[0])
         << '\t' << TAI->getCommentString()
         << " long double next halfword\n";
-      O << TAI->getData16bitsDirective() << uint16_t(p[1])
+      O << TAI->getData16bitsDirective(AddrSpace) << uint16_t(p[1])
         << '\t' << TAI->getCommentString()
         << " long double least significant halfword\n";
      } else {
-      O << TAI->getData16bitsDirective() << uint16_t(p[1])
+      O << TAI->getData16bitsDirective(AddrSpace) << uint16_t(p[1])
         << '\t' << TAI->getCommentString()
         << " long double least significant halfword of ~"
         << DoubleVal.convertToDouble() << '\n';
-      O << TAI->getData16bitsDirective() << uint16_t(p[0])
+      O << TAI->getData16bitsDirective(AddrSpace) << uint16_t(p[0])
         << '\t' << TAI->getCommentString()
         << " long double next halfword\n";
-      O << TAI->getData16bitsDirective() << uint16_t(p[0] >> 16)
+      O << TAI->getData16bitsDirective(AddrSpace) << uint16_t(p[0] >> 16)
         << '\t' << TAI->getCommentString()
         << " long double next halfword\n";
-      O << TAI->getData16bitsDirective() << uint16_t(p[0] >> 32)
+      O << TAI->getData16bitsDirective(AddrSpace) << uint16_t(p[0] >> 32)
         << '\t' << TAI->getCommentString()
         << " long double next halfword\n";
-      O << TAI->getData16bitsDirective() << uint16_t(p[0] >> 48)
+      O << TAI->getData16bitsDirective(AddrSpace) << uint16_t(p[0] >> 48)
         << '\t' << TAI->getCommentString()
         << " long double most significant halfword\n";
     }
     EmitZeros(TD->getTypePaddedSize(Type::X86_FP80Ty) -
-              TD->getTypeStoreSize(Type::X86_FP80Ty));
+              TD->getTypeStoreSize(Type::X86_FP80Ty), AddrSpace);
     return;
   } else if (CFP->getType() == Type::PPC_FP128Ty) {
     // all long double variants are printed as hex
@@ -1069,29 +1071,29 @@
     APInt api = CFP->getValueAPF().bitcastToAPInt();
     const uint64_t *p = api.getRawData();
     if (TD->isBigEndian()) {
-      O << TAI->getData32bitsDirective() << uint32_t(p[0] >> 32)
+      O << TAI->getData32bitsDirective(AddrSpace) << uint32_t(p[0] >> 32)
         << '\t' << TAI->getCommentString()
         << " long double most significant word\n";
-      O << TAI->getData32bitsDirective() << uint32_t(p[0])
+      O << TAI->getData32bitsDirective(AddrSpace) << uint32_t(p[0])
         << '\t' << TAI->getCommentString()
         << " long double next word\n";
-      O << TAI->getData32bitsDirective() << uint32_t(p[1] >> 32)
+      O << TAI->getData32bitsDirective(AddrSpace) << uint32_t(p[1] >> 32)
         << '\t' << TAI->getCommentString()
         << " long double next word\n";
-      O << TAI->getData32bitsDirective() << uint32_t(p[1])
+      O << TAI->getData32bitsDirective(AddrSpace) << uint32_t(p[1])
         << '\t' << TAI->getCommentString()
         << " long double least significant word\n";
      } else {
-      O << TAI->getData32bitsDirective() << uint32_t(p[1])
+      O << TAI->getData32bitsDirective(AddrSpace) << uint32_t(p[1])
         << '\t' << TAI->getCommentString()
         << " long double least significant word\n";
-      O << TAI->getData32bitsDirective() << uint32_t(p[1] >> 32)
+      O << TAI->getData32bitsDirective(AddrSpace) << uint32_t(p[1] >> 32)
         << '\t' << TAI->getCommentString()
         << " long double next word\n";
-      O << TAI->getData32bitsDirective() << uint32_t(p[0])
+      O << TAI->getData32bitsDirective(AddrSpace) << uint32_t(p[0])
         << '\t' << TAI->getCommentString()
         << " long double next word\n";
-      O << TAI->getData32bitsDirective() << uint32_t(p[0] >> 32)
+      O << TAI->getData32bitsDirective(AddrSpace) << uint32_t(p[0] >> 32)
         << '\t' << TAI->getCommentString()
         << " long double most significant word\n";
     }
@@ -1099,7 +1101,8 @@
   } else assert(0 && "Floating point constant type not handled");
 }
 
-void AsmPrinter::EmitGlobalConstantLargeInt(const ConstantInt *CI) {
+void AsmPrinter::EmitGlobalConstantLargeInt(const ConstantInt *CI,
+                                            unsigned AddrSpace) {
   const TargetData *TD = TM.getTargetData();
   unsigned BitWidth = CI->getBitWidth();
   assert(isPowerOf2_32(BitWidth) &&
@@ -1116,20 +1119,20 @@
     else
       Val = RawData[i];
 
-    if (TAI->getData64bitsDirective())
-      O << TAI->getData64bitsDirective() << Val << '\n';
+    if (TAI->getData64bitsDirective(AddrSpace))
+      O << TAI->getData64bitsDirective(AddrSpace) << Val << '\n';
     else if (TD->isBigEndian()) {
-      O << TAI->getData32bitsDirective() << unsigned(Val >> 32)
+      O << TAI->getData32bitsDirective(AddrSpace) << unsigned(Val >> 32)
         << '\t' << TAI->getCommentString()
         << " Double-word most significant word " << Val << '\n';
-      O << TAI->getData32bitsDirective() << unsigned(Val)
+      O << TAI->getData32bitsDirective(AddrSpace) << unsigned(Val)
         << '\t' << TAI->getCommentString()
         << " Double-word least significant word " << Val << '\n';
     } else {
-      O << TAI->getData32bitsDirective() << unsigned(Val)
+      O << TAI->getData32bitsDirective(AddrSpace) << unsigned(Val)
         << '\t' << TAI->getCommentString()
         << " Double-word least significant word " << Val << '\n';
-      O << TAI->getData32bitsDirective() << unsigned(Val >> 32)
+      O << TAI->getData32bitsDirective(AddrSpace) << unsigned(Val >> 32)
         << '\t' << TAI->getCommentString()
         << " Double-word most significant word " << Val << '\n';
     }
@@ -1137,27 +1140,27 @@
 }
 
 /// EmitGlobalConstant - Print a general LLVM constant to the .s file.
-void AsmPrinter::EmitGlobalConstant(const Constant *CV) {
+void AsmPrinter::EmitGlobalConstant(const Constant *CV, unsigned AddrSpace) {
   const TargetData *TD = TM.getTargetData();
   const Type *type = CV->getType();
   unsigned Size = TD->getTypePaddedSize(type);
 
   if (CV->isNullValue() || isa(CV)) {
-    EmitZeros(Size);
+    EmitZeros(Size, AddrSpace);
     return;
   } else if (const ConstantArray *CVA = dyn_cast(CV)) {
     EmitGlobalConstantArray(CVA);
     return;
   } else if (const ConstantStruct *CVS = dyn_cast(CV)) {
-    EmitGlobalConstantStruct(CVS);
+    EmitGlobalConstantStruct(CVS, AddrSpace);
     return;
   } else if (const ConstantFP *CFP = dyn_cast(CV)) {
-    EmitGlobalConstantFP(CFP);
+    EmitGlobalConstantFP(CFP, AddrSpace);
     return;
   } else if (const ConstantInt *CI = dyn_cast(CV)) {
     // Small integers are handled below; large integers are handled here.
     if (Size > 4) {
-      EmitGlobalConstantLargeInt(CI);
+      EmitGlobalConstantLargeInt(CI, AddrSpace);
       return;
     }
   } else if (const ConstantVector *CP = dyn_cast(CV)) {
@@ -1165,7 +1168,7 @@
     return;
   }
 
-  printDataDirective(type);
+  printDataDirective(type, AddrSpace);
   EmitConstantValueOnly(CV);
   if (const ConstantInt *CI = dyn_cast(CV)) {
     SmallString<40> S;
@@ -1491,21 +1494,21 @@
 
 /// printDataDirective - This method prints the asm directive for the
 /// specified type.
-void AsmPrinter::printDataDirective(const Type *type) {
+void AsmPrinter::printDataDirective(const Type *type, unsigned AddrSpace) {
   const TargetData *TD = TM.getTargetData();
   switch (type->getTypeID()) {
   case Type::IntegerTyID: {
     unsigned BitWidth = cast(type)->getBitWidth();
     if (BitWidth <= 8)
-      O << TAI->getData8bitsDirective();
+      O << TAI->getData8bitsDirective(AddrSpace);
     else if (BitWidth <= 16)
-      O << TAI->getData16bitsDirective();
+      O << TAI->getData16bitsDirective(AddrSpace);
     else if (BitWidth <= 32)
-      O << TAI->getData32bitsDirective();
+      O << TAI->getData32bitsDirective(AddrSpace);
     else if (BitWidth <= 64) {
-      assert(TAI->getData64bitsDirective() &&
+      assert(TAI->getData64bitsDirective(AddrSpace) &&
              "Target cannot handle 64-bit constant exprs!");
-      O << TAI->getData64bitsDirective();
+      O << TAI->getData64bitsDirective(AddrSpace);
     } else {
       assert(0 && "Target cannot handle given data directive width!");
     }
@@ -1513,15 +1516,15 @@
   }
   case Type::PointerTyID:
     if (TD->getPointerSize() == 8) {
-      assert(TAI->getData64bitsDirective() &&
+      assert(TAI->getData64bitsDirective(AddrSpace) &&
              "Target cannot handle 64-bit pointer exprs!");
-      O << TAI->getData64bitsDirective();
+      O << TAI->getData64bitsDirective(AddrSpace);
     } else if (TD->getPointerSize() == 2) {
-      O << TAI->getData16bitsDirective();
+      O << TAI->getData16bitsDirective(AddrSpace);
     } else if (TD->getPointerSize() == 1) {
-      O << TAI->getData8bitsDirective();
+      O << TAI->getData8bitsDirective(AddrSpace);
     } else {
-      O << TAI->getData32bitsDirective();
+      O << TAI->getData32bitsDirective(AddrSpace);
     }
     break;
   case Type::FloatTyID: case Type::DoubleTyID:

Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=63377&r1=63376&r2=63377&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Thu Jan 29 22:25:10 2009
@@ -242,48 +242,11 @@
         continue;
 
       O << name;
-      EmitGlobalConstant(C);
+      EmitGlobalConstant(C, AddrSpace);
     }
   }
 }
 
-void PIC16AsmPrinter::EmitConstantValueOnly(const Constant* CV) {
-  if (const ConstantInt *CI = dyn_cast(CV)) {
-    unsigned BitWidth = CI->getBitWidth();
-    int Val = CI->getZExtValue();
-    if (BitWidth == 8) {
-      // Expecting db directive here. In case of romdata we need to pad the
-      // word with zeros.
-      if (IsRomData)
-        O << 0 <<", ";
-      O << Val; 
-    }
-    else if (BitWidth == 16) {
-      unsigned Element1, Element2;
-      Element1 = 0x00ff & Val;
-      Element2 = 0x00ff & (Val >> 8);
-      if (IsRomData)
-        O << 0 <<", "<> 8);
-      Element3 = 0x00ff & (Val >> 16);
-      Element4 = 0x00ff & (Val >> 24);
-      if (IsRomData)
-        O << 0 <<", "<< Element1 <<", "<< 0 <<", "<< Element2 <<", "<< 0 
-          <<", "<< Element3 <<", "<< 0 <<", "<< Element4;
-      else 
-        O << Element1 <<", "<< Element2 <<", "<< Element3 <<", "<< Element4;    
-    }
-    return;
-  }
-  AsmPrinter::EmitConstantValueOnly(CV);
-}
-
 void PIC16AsmPrinter::EmitRomData (Module &M)
 {
   SwitchToSection(TAI->getReadOnlySection());
@@ -308,7 +271,7 @@
         continue;
 
       O << name;
-      EmitGlobalConstant(C);
+      EmitGlobalConstant(C, AddrSpace);
       O << "\n";
     }
   }

Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h?rev=63377&r1=63376&r2=63377&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h Thu Jan 29 22:25:10 2009
@@ -43,7 +43,6 @@
     void EmitInitData (Module &M);
     void EmitUnInitData (Module &M);
     void EmitRomData (Module &M);
-    virtual void EmitConstantValueOnly(const Constant *CV);
     void emitFunctionData(MachineFunction &MF);
     void emitFunctionTempData(MachineFunction &MF, unsigned &FrameSize);
 

Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.cpp?rev=63377&r1=63376&r2=63377&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.cpp Thu Jan 29 22:25:10 2009
@@ -22,8 +22,11 @@
   : TargetAsmInfo(TM) {
   CommentString = ";";
   Data8bitsDirective = " db ";
-  Data16bitsDirective = " db ";
-  Data32bitsDirective = " db ";
+  Data16bitsDirective = " dw ";
+  Data32bitsDirective = " dl ";
+  RomData8bitsDirective = " dw ";
+  RomData16bitsDirective = " rom_di ";
+  RomData8bitsDirective = " rom_dl ";
   ZeroDirective = NULL;
   AsciiDirective = " dt ";
   AscizDirective = NULL;
@@ -33,3 +36,28 @@
   DataSection = getNamedSection("idata.# IDATA", SectionFlags::Writeable);
   SwitchToSectionDirective = "";
 }
+
+const char *PIC16TargetAsmInfo::getData8bitsDirective(unsigned AddrSpace)
+                                                       const {
+      if (AddrSpace == PIC16ISD::ROM_SPACE)
+        return RomData8bitsDirective;
+      else 
+        return Data8bitsDirective; 
+  }
+
+const char *PIC16TargetAsmInfo::getData16bitsDirective(unsigned AddrSpace)
+                                                       const {
+      if (AddrSpace == PIC16ISD::ROM_SPACE)
+        return RomData16bitsDirective;
+      else
+        return Data16bitsDirective;
+  }
+
+const char *PIC16TargetAsmInfo::getData32bitsDirective(unsigned AddrSpace)
+                                                       const {
+      if (AddrSpace == PIC16ISD::ROM_SPACE)
+        return RomData32bitsDirective;
+      else
+        return Data32bitsDirective;
+  }
+

Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.h?rev=63377&r1=63376&r2=63377&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.h Thu Jan 29 22:25:10 2009
@@ -23,7 +23,13 @@
 
   struct PIC16TargetAsmInfo : public TargetAsmInfo {
     PIC16TargetAsmInfo(const PIC16TargetMachine &TM);
+    const char *RomData8bitsDirective;
+    const char *RomData16bitsDirective;
+    const char *RomData32bitsDirective;
     public :
+    virtual const char *getData8bitsDirective(unsigned AddrSpace = 0) const;
+    virtual const char *getData16bitsDirective(unsigned AddrSpace = 0) const;
+    virtual const char *getData32bitsDirective(unsigned AddrSpace = 0) const;
   };
 
 } // namespace llvm




From wangmp at apple.com  Fri Jan 30 01:07:40 2009
From: wangmp at apple.com (Mon P Wang)
Date: Fri, 30 Jan 2009 07:07:40 -0000
Subject: [llvm-commits] [llvm] r63380 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <200901300707.n0U77eu4006263@zion.cs.uiuc.edu>

Author: wangmp
Date: Fri Jan 30 01:07:40 2009
New Revision: 63380

URL: http://llvm.org/viewvc/llvm-project?rev=63380&view=rev
Log:
When PerformBuildVectorCombine, avoid creating a X86ISD::VZEXT_LOAD of
an illegal type.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=63380&r1=63379&r2=63380&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jan 30 01:07:40 2009
@@ -7601,7 +7601,11 @@
   // Load must not be an extload.
   if (LD->getExtensionType() != ISD::NON_EXTLOAD)
     return SDValue();
-  
+
+  // Load type should legal type so we don't have to legalize it.
+  if (!TLI.isTypeLegal(VT))
+    return SDValue();
+
   SDVTList Tys = DAG.getVTList(VT, MVT::Other);
   SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
   SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, Tys, Ops, 2);




From monping at apple.com  Fri Jan 30 01:19:34 2009
From: monping at apple.com (Mon Ping Wang)
Date: Thu, 29 Jan 2009 23:19:34 -0800
Subject: [llvm-commits] Patch: avoid legalization assert
Message-ID: 

Hi,

In the test case below, we will generate an assert
   "Illegal type introduced after type legalization?"

In this test case, when legalizing the divide operation, we end up  
generating a library call with nodes that needs type legalization.   
This patch avoids the legalize assert if we run LegalizeType and then  
run LegalizeDAG.  This is a stop gap fix because we don't want to do  
any  type legalization to be done in LegalizeDAG. When we legalize an  
operation that generates a call to a library function, maybe we should  
call LegalizeType on the call sequence nodes that were created for the  
call.

-- Mon Ping

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From evan.cheng at apple.com  Fri Jan 30 01:47:04 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 30 Jan 2009 07:47:04 -0000
Subject: [llvm-commits] [test-suite] r63381 -
	/test-suite/trunk/Makefile.programs
Message-ID: <200901300747.n0U7l59d007639@zion.cs.uiuc.edu>

Author: evancheng
Date: Fri Jan 30 01:47:04 2009
New Revision: 63381

URL: http://llvm.org/viewvc/llvm-project?rev=63381&view=rev
Log:
Test pre-allocation split as x86 llcbeta.

Modified:
    test-suite/trunk/Makefile.programs

Modified: test-suite/trunk/Makefile.programs
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=63381&r1=63380&r2=63381&view=diff

==============================================================================
--- test-suite/trunk/Makefile.programs (original)
+++ test-suite/trunk/Makefile.programs Fri Jan 30 01:47:04 2009
@@ -226,7 +226,9 @@
 LLCBETAOPTION := -sched=simple 
 endif
 ifeq ($(ARCH),x86)
-LLCBETAOPTION := -disable-post-RA-scheduler=false -machine-licm
+LLCBETAOPTION := -pre-alloc-split
+#-join-cross-class-copies
+#-disable-post-RA-scheduler=false -machine-licm
 #-machine-licm
 #-fast-isel
 #-aggressive-remat




From sanjiv.gupta at microchip.com  Fri Jan 30 01:55:25 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Fri, 30 Jan 2009 07:55:25 -0000
Subject: [llvm-commits] [llvm] r63382 -
	/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
Message-ID: <200901300755.n0U7tPCn007938@zion.cs.uiuc.edu>

Author: sgupta
Date: Fri Jan 30 01:55:25 2009
New Revision: 63382

URL: http://llvm.org/viewvc/llvm-project?rev=63382&view=rev
Log:
Use sublw for comparison with literals instead of subwf.

Modified:
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=63382&r1=63381&r2=63382&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Fri Jan 30 01:55:25 2009
@@ -1288,23 +1288,25 @@
   }
 
   PIC16CC = DAG.getConstant(CondCode, MVT::i8);
-  SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag);
 
   // These are signed comparisons. 
   SDValue Mask = DAG.getConstant(128, MVT::i8);
   if (isSignedComparison(CondCode)) {
-    LHS = DAG.getNode (ISD::XOR, MVT::i8, LHS, Mask); 
+    LHS = DAG.getNode (ISD::XOR, MVT::i8, LHS, Mask);
     RHS = DAG.getNode (ISD::XOR, MVT::i8, RHS, Mask); 
   }
+
+  SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag);
   // We can use a subtract operation to set the condition codes. But
   // we need to put one operand in memory if required.
-  // Nothing to do if the first operand is already a direct load and it has
-  // only one use.
-  if (! (isDirectLoad(LHS) && LHS.hasOneUse()))
-    // Put first operand on stack.
-    LHS = ConvertToMemOperand (LHS, DAG);
+  // Nothing to do if the first operand is already a valid type (direct load 
+  // for subwf and literal for sublw) and it is used by this operation only. 
+  if ((LHS.getOpcode() == ISD::Constant || isDirectLoad(LHS)) 
+      && LHS.hasOneUse())
+    return DAG.getNode(PIC16ISD::SUBCC, VTs, LHS, RHS);
 
-  SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
+  // else convert the first operand to mem.
+  LHS = ConvertToMemOperand (LHS, DAG);
   return DAG.getNode(PIC16ISD::SUBCC, VTs, LHS, RHS);
 }
 




From mrs at apple.com  Fri Jan 30 02:19:46 2009
From: mrs at apple.com (Mike Stump)
Date: Fri, 30 Jan 2009 08:19:46 -0000
Subject: [llvm-commits] [llvm] r63384 - in /llvm/trunk:
 include/llvm/Support/CommandLine.h lib/Support/CommandLine.cpp
Message-ID: <200901300819.n0U8JkUt008727@zion.cs.uiuc.edu>

Author: mrs
Date: Fri Jan 30 02:19:46 2009
New Revision: 63384

URL: http://llvm.org/viewvc/llvm-project?rev=63384&view=rev
Log:
Add opposite_of and inverse_opt to support -fno- style options.  This
is necessary for eventual gcc commmand line compatibility.

Modified:
    llvm/trunk/include/llvm/Support/CommandLine.h
    llvm/trunk/lib/Support/CommandLine.cpp

Modified: llvm/trunk/include/llvm/Support/CommandLine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CommandLine.h?rev=63384&r1=63383&r2=63384&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Support/CommandLine.h (original)
+++ llvm/trunk/include/llvm/Support/CommandLine.h Fri Jan 30 02:19:46 2009
@@ -302,6 +302,12 @@
 template
 LocationClass location(Ty &L) { return LocationClass(L); }
 
+// opposite_of - Allow the user to specify which other option this
+// option is the opposite of.
+//
+template
+LocationClass opposite_of(Ty &O) { return location(O.getValue()); }
+
 
 //===----------------------------------------------------------------------===//
 // Enum valued command line option
@@ -577,6 +583,30 @@
 EXTERN_TEMPLATE_INSTANTIATION(class basic_parser);
 
 //--------------------------------------------------
+// parser
+class boolInverse { };
+template<>
+class parser : public basic_parser {
+public:
+  typedef bool parser_data_type;
+  // parse - Return true on error.
+  bool parse(Option &O, const char *ArgName, const std::string &Arg,
+             bool &Val);
+
+  enum ValueExpected getValueExpectedFlagDefault() const {
+    return ValueOptional;
+  }
+
+  // getValueName - Do not print = at all.
+  virtual const char *getValueName() const { return 0; }
+
+  // An out-of-line virtual method to provide a 'home' for this class.
+  virtual void anchor();
+};
+
+EXTERN_TEMPLATE_INSTANTIATION(class basic_parser);
+
+//--------------------------------------------------
 // parser
 //
 template<>
@@ -917,6 +947,9 @@
 EXTERN_TEMPLATE_INSTANTIATION(class opt);
 EXTERN_TEMPLATE_INSTANTIATION(class opt);
 
+class boolInverse;
+typedef opt > inverse_opt;
+
 //===----------------------------------------------------------------------===//
 // list_storage class
 

Modified: llvm/trunk/lib/Support/CommandLine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CommandLine.cpp?rev=63384&r1=63383&r2=63384&view=diff

==============================================================================
--- llvm/trunk/lib/Support/CommandLine.cpp (original)
+++ llvm/trunk/lib/Support/CommandLine.cpp Fri Jan 30 02:19:46 2009
@@ -40,6 +40,7 @@
 //
 TEMPLATE_INSTANTIATION(class basic_parser);
 TEMPLATE_INSTANTIATION(class basic_parser);
+TEMPLATE_INSTANTIATION(class basic_parser);
 TEMPLATE_INSTANTIATION(class basic_parser);
 TEMPLATE_INSTANTIATION(class basic_parser);
 TEMPLATE_INSTANTIATION(class basic_parser);
@@ -55,6 +56,7 @@
 void basic_parser_impl::anchor() {}
 void parser::anchor() {}
 void parser::anchor() {}
+void parser::anchor() {}
 void parser::anchor() {}
 void parser::anchor() {}
 void parser::anchor() {}
@@ -882,7 +884,8 @@
   if (Arg == "" || Arg == "true" || Arg == "TRUE" || Arg == "True" ||
       Arg == "1") {
     Value = BOU_TRUE;
-  } else if (Arg == "false" || Arg == "FALSE" || Arg == "False" || Arg == "0") {
+  } else if (Arg == "false" || Arg == "FALSE"
+             || Arg == "False" || Arg == "0") {
     Value = BOU_FALSE;
   } else {
     return O.error(": '" + Arg +
@@ -891,6 +894,23 @@
   return false;
 }
 
+// parser implementation
+//
+bool parser::parse(Option &O, const char *ArgName,
+                                const std::string &Arg, bool &Value) {
+  if (Arg == "" || Arg == "true" || Arg == "TRUE" || Arg == "True" ||
+      Arg == "1") {
+    Value = false;
+  } else if (Arg == "false" || Arg == "FALSE"
+             || Arg == "False" || Arg == "0") {
+    Value = true;
+  } else {
+    return O.error(": '" + Arg +
+                   "' is invalid value for boolean argument! Try 0 or 1");
+  }
+  return false;
+}
+
 // parser implementation
 //
 bool parser::parse(Option &O, const char *ArgName,




From zhousheng00 at gmail.com  Fri Jan 30 02:59:51 2009
From: zhousheng00 at gmail.com (Zhou Sheng)
Date: Fri, 30 Jan 2009 08:59:51 -0000
Subject: [llvm-commits] [llvm] r63386 -
	/llvm/trunk/test/ExecutionEngine/2009-01-29-PartSet.ll
Message-ID: <200901300859.n0U8xpbr016531@zion.cs.uiuc.edu>

Author: sheng
Date: Fri Jan 30 02:59:51 2009
New Revision: 63386

URL: http://llvm.org/viewvc/llvm-project?rev=63386&view=rev
Log:
This is case is to uncover the bug in IntrinsicLowering.cpp,
the LowerPartSet(). It didn't handle the situation correctly when 
the low, high argument values are in reverse order (low > high) 
with 'Val' type is i32 (a corner case).

Added:
    llvm/trunk/test/ExecutionEngine/2009-01-29-PartSet.ll

Added: llvm/trunk/test/ExecutionEngine/2009-01-29-PartSet.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/2009-01-29-PartSet.ll?rev=63386&view=auto

==============================================================================
--- llvm/trunk/test/ExecutionEngine/2009-01-29-PartSet.ll (added)
+++ llvm/trunk/test/ExecutionEngine/2009-01-29-PartSet.ll Fri Jan 30 02:59:51 2009
@@ -0,0 +1,17 @@
+; RUN: llvm-as %s -o - | lli -force-interpreter | grep FF8F
+
+; ModuleID = 'partset.c.bc'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+ at .str = internal constant [4 x i8] c"%X\0A\00"      ; <[4 x i8]*> [#uses=1]
+
+define i32 @main() nounwind  {
+entry:
+    %part_set = tail call i32 @llvm.part.set.i32.i8( i32 65535, i8 1, i32 7, i32 4 )        ;  [#uses=1]
+    %tmp4 = tail call i32 (i8*, ...)* @printf( i8* noalias  getelementptr ([4 x i8]* @.str, i32 0, i64 0), i32 %part_set ) nounwind         ;  [#uses=0]
+    ret i32 0
+}
+
+declare i32 @llvm.part.set.i32.i8(i32, i8, i32, i32) nounwind readnone
+
+declare i32 @printf(i8*, ...) nounwind




From sanjiv.gupta at microchip.com  Fri Jan 30 03:01:45 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Fri, 30 Jan 2009 09:01:45 -0000
Subject: [llvm-commits] [llvm] r63387 -
	/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td
Message-ID: <200901300901.n0U91jr7017068@zion.cs.uiuc.edu>

Author: sgupta
Date: Fri Jan 30 03:01:44 2009
New Revision: 63387

URL: http://llvm.org/viewvc/llvm-project?rev=63387&view=rev
Log:
Fixed the comment. No functionality change.

Modified:
    llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td

Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td?rev=63387&r1=63386&r2=63387&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td Fri Jan 30 03:01:44 2009
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file describes the ARM instructions in TableGen format.
+// This file describes the PIC16 instructions in TableGen format.
 //
 //===----------------------------------------------------------------------===//
 




From zhousheng00 at gmail.com  Fri Jan 30 03:02:50 2009
From: zhousheng00 at gmail.com (Zhou Sheng)
Date: Fri, 30 Jan 2009 09:02:50 -0000
Subject: [llvm-commits] [llvm] r63388 -
	/llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp
Message-ID: <200901300902.n0U92oPW017207@zion.cs.uiuc.edu>

Author: sheng
Date: Fri Jan 30 03:02:50 2009
New Revision: 63388

URL: http://llvm.org/viewvc/llvm-project?rev=63388&view=rev
Log:
This is to fix the bug in IntrinsicLowering.cpp,
the LowerPartSet(). It didn't handle the situation correctly when
the low, high argument values are in reverse order (low > high)
with 'Val' type i32 (a corner case).

Modified:
    llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp

Modified: llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp?rev=63388&r1=63387&r2=63388&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp Fri Jan 30 03:02:50 2009
@@ -533,7 +533,8 @@
       Lo = new ZExtInst(Lo_pn, ValTy, "", entry);
     } else if (ValBits < 32) {
       Lo = new TruncInst(Lo_pn, ValTy, "", entry);
-    }
+    } else
+      Lo = Lo_pn;
     // Determine if the replacement bits are larger than the number of bits we
     // are replacing and deal with it.
     ICmpInst* is_large = 




From baldrick at free.fr  Fri Jan 30 03:11:57 2009
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 30 Jan 2009 10:11:57 +0100
Subject: [llvm-commits] [llvm-gcc-4.2] r63344 -
	/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
In-Reply-To: <200901292339.n0TNd46u024251@zion.cs.uiuc.edu>
References: <200901292339.n0TNd46u024251@zion.cs.uiuc.edu>
Message-ID: <200901301011.57185.baldrick@free.fr>

Hi Evan,

> - Split createOptimizationPasses() into two. Now we initialize the per module pass manager after all the functions are processed. This allows it to scan the list and find out whether always-inline pass is actually needed.

can't the "always inline" pass take care of this itself?
i.e. bail out early if no functions are "always inline".

Ciao,

Duncan.


From baldrick at free.fr  Fri Jan 30 03:17:12 2009
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 30 Jan 2009 10:17:12 +0100
Subject: [llvm-commits] Patch: avoid legalization assert
In-Reply-To: 
References: 
Message-ID: <200901301017.12989.baldrick@free.fr>

Hi Mon Ping,

> In this test case, when legalizing the divide operation, we end up  
> generating a library call with nodes that needs type legalization.

how is this possible?

Thanks,

Duncan.


From baldrick at free.fr  Fri Jan 30 03:21:45 2009
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 30 Jan 2009 10:21:45 +0100
Subject: [llvm-commits] [llvm] r63388 -
	/llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp
In-Reply-To: <200901300902.n0U92oPW017207@zion.cs.uiuc.edu>
References: <200901300902.n0U92oPW017207@zion.cs.uiuc.edu>
Message-ID: <200901301021.45531.baldrick@free.fr>

Hi,

>        Lo = new TruncInst(Lo_pn, ValTy, "", entry);
> -    }
> +    } else
> +      Lo = Lo_pn;
>      // Determine if the replacement bits are larger than the number of bits we

the usual style is to use braces for one-liners if other
parts of the "if" use braces:

> -    }
> +    } else {
> +      Lo = Lo_pn;
> +    }

Ciao,

Duncan.


From zhousheng00 at gmail.com  Fri Jan 30 03:44:51 2009
From: zhousheng00 at gmail.com (Zhou Sheng)
Date: Fri, 30 Jan 2009 09:44:51 -0000
Subject: [llvm-commits] [llvm] r63389 -
	/llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp
Message-ID: <200901300944.n0U9iqYV021564@zion.cs.uiuc.edu>

Author: sheng
Date: Fri Jan 30 03:44:49 2009
New Revision: 63389

URL: http://llvm.org/viewvc/llvm-project?rev=63389&view=rev
Log:
As Duncan suggested, add braces for the one-line "else branch".
Thanks, Duncan.

Modified:
    llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp

Modified: llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp?rev=63389&r1=63388&r2=63389&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp Fri Jan 30 03:44:49 2009
@@ -533,8 +533,9 @@
       Lo = new ZExtInst(Lo_pn, ValTy, "", entry);
     } else if (ValBits < 32) {
       Lo = new TruncInst(Lo_pn, ValTy, "", entry);
-    } else
+    } else {
       Lo = Lo_pn;
+    }
     // Determine if the replacement bits are larger than the number of bits we
     // are replacing and deal with it.
     ICmpInst* is_large = 




From baldrick at free.fr  Fri Jan 30 06:32:57 2009
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 30 Jan 2009 13:32:57 +0100
Subject: [llvm-commits] [llvm-gcc-4.2] r63288 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
In-Reply-To: <200901290750.n0T7o2dO012355@zion.cs.uiuc.edu>
References: <200901290750.n0T7o2dO012355@zion.cs.uiuc.edu>
Message-ID: <200901301332.57927.baldrick@free.fr>

Hi Chris,

> If a FIELD_DECL says its alignment is 16 bytes, and the base pointer
> is only known to be 8-byte aligned, round up to 16 bytes.  I believe 
> that this is always safe.  Duncan, I would appreciate the review.

how can this possibly be safe?  My understanding is that the alignment
of a FIELD_DECL gives it's alignment within the surrounding struct.
It does not force anything on how objects of the struct type are aligned.
If an object of that struct type has alignment 1 (examples of this are
easy to create) then in general the field will also have alignment 1
no matter what the field alignment says.  For example, if the numerical
value of the pointer is 7 then the first field will have alignment 1
no matter what the alignment of it's FIELD_DECL says.  I could be wrong
of course (I often am!) but I don't think so :)

Ciao,

Duncan.


From baldrick at free.fr  Fri Jan 30 09:11:35 2009
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 30 Jan 2009 16:11:35 +0100
Subject: [llvm-commits] Patch: avoid legalization assert
In-Reply-To: 
References: 
Message-ID: <200901301611.36038.baldrick@free.fr>

Hi Mon Ping, if I understand right the problem is that v2i64 is legal,
but i64 is not, and that when we try to scalarize this
  0x2b1d9c8: v2i64 = sdiv 0x2b1ddc8, 0x2b1dfc8
into a pair of libcalls, we end up with expressions in terms of the
elements (i.e. of i64 type) but those types aren't legal.  The
point of running llc with -disable-mmx is that there is then no
sdiv vector instruction I suppose.  Hmmm, tricky :)

Ciao,

Duncan.


From mburke at ea.com  Fri Jan 30 01:36:33 2009
From: mburke at ea.com (Burke, Max)
Date: Thu, 29 Jan 2009 23:36:33 -0800
Subject: [llvm-commits] Patch: PPC64 subregister moves
Message-ID: 

This attempts to reduce the number of emitted OR instructions used to
move data in and out of subregisters on the PPC64 target. We've noticed
what looks like many extraneous register moves which in some cases are
harmless, others which may have unintended, though minor, side effects
(ie, mr 30, 30 blocking Cell PPE hardware thread at dispatch for 12
cycles; mr 3, 3 changing the current hardware thread priority to high).
-------------- next part --------------
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From clattner at apple.com  Fri Jan 30 11:20:27 2009
From: clattner at apple.com (Chris Lattner)
Date: Fri, 30 Jan 2009 09:20:27 -0800
Subject: [llvm-commits] [llvm-gcc-4.2] r63288 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
In-Reply-To: <200901301332.57927.baldrick@free.fr>
References: <200901290750.n0T7o2dO012355@zion.cs.uiuc.edu>
	<200901301332.57927.baldrick@free.fr>
Message-ID: <74C16BD0-1151-4DD6-8D3F-CEA8C06D2E21@apple.com>


On Jan 30, 2009, at 4:32 AM, Duncan Sands wrote:

> Hi Chris,
>
>> If a FIELD_DECL says its alignment is 16 bytes, and the base pointer
>> is only known to be 8-byte aligned, round up to 16 bytes.  I believe
>> that this is always safe.  Duncan, I would appreciate the review.
>
> how can this possibly be safe?  My understanding is that the alignment
> of a FIELD_DECL gives it's alignment within the surrounding struct.
> It does not force anything on how objects of the struct type are  
> aligned.
> If an object of that struct type has alignment 1 (examples of this are
> easy to create) then in general the field will also have alignment 1
> no matter what the field alignment says.  For example, if the  
> numerical
> value of the pointer is 7 then the first field will have alignment 1
> no matter what the alignment of it's FIELD_DECL says.  I could be  
> wrong
> of course (I often am!) but I don't think so :)

Hey Duncan,

I completely believe you that this is possible. One random question: I  
don't understand or see the code (which should theoretically be in  
expr.c?) to determine this stuff for the RTL backend, do you know  
where it is?

-Chris


From echeng at apple.com  Fri Jan 30 11:34:58 2009
From: echeng at apple.com (Evan Cheng)
Date: Fri, 30 Jan 2009 09:34:58 -0800
Subject: [llvm-commits] [llvm-gcc-4.2] r63344 -
	/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
In-Reply-To: <200901301011.57185.baldrick@free.fr>
References: <200901292339.n0TNd46u024251@zion.cs.uiuc.edu>
	<200901301011.57185.baldrick@free.fr>
Message-ID: <2AB01407-F786-43DC-8B00-984DA4B3FE96@apple.com>


On Jan 30, 2009, at 1:11 AM, Duncan Sands wrote:

> Hi Evan,
>
>> - Split createOptimizationPasses() into two. Now we initialize the  
>> per module pass manager after all the functions are processed. This  
>> allows it to scan the list and find out whether always-inline pass  
>> is actually needed.
>
> can't the "always inline" pass take care of this itself?
> i.e. bail out early if no functions are "always inline".

It's better to determine this in llvm-gcc. If there are no per module  
passes, we can codegen one function at a time. It's not done yet, but  
that's where we want to go for -O0.

Evan

>
>
> Ciao,
>
> Duncan.



From gohman at apple.com  Fri Jan 30 11:42:04 2009
From: gohman at apple.com (Dan Gohman)
Date: Fri, 30 Jan 2009 17:42:04 -0000
Subject: [llvm-commits] [test-suite] r63397 -
	/test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/
Message-ID: <200901301742.n0UHg4fW006622@zion.cs.uiuc.edu>

Author: djg
Date: Fri Jan 30 11:42:04 2009
New Revision: 63397

URL: http://llvm.org/viewvc/llvm-project?rev=63397&view=rev
Log:
Add an svn:ignore property for the Output directory.

Modified:
    test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/   (props changed)

Propchange: test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/

------------------------------------------------------------------------------
--- svn:ignore (added)
+++ svn:ignore Fri Jan 30 11:42:04 2009
@@ -0,0 +1 @@
+Output




From nicolas.geoffray at lip6.fr  Fri Jan 30 11:51:22 2009
From: nicolas.geoffray at lip6.fr (Nicolas Geoffray)
Date: Fri, 30 Jan 2009 18:51:22 +0100
Subject: [llvm-commits] [llvm]	r62045	-
	/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
In-Reply-To: <876D467E-C3C9-4724-9853-2A93A59B0181@apple.com>
References: <200901112015.n0BKFLnj013960@zion.cs.uiuc.edu>
	<496E0C68.1070209@lip6.fr>
	<98B6F687-3514-4E03-B6BB-6813B2B706D8@apple.com>
	<496FB230.8070702@lip6.fr>
	<876D467E-C3C9-4724-9853-2A93A59B0181@apple.com>
Message-ID: <49833E1A.1060901@lip6.fr>

Chris Lattner wrote:
>
> Hi Nicolas,
>
> Can you please summarize this discussion in a bugzilla report?  It 
> would be nice to track this.  Thanks,
>
Done:

http://llvm.org/bugs/show_bug.cgi?id=3445

Nicolas


From clattner at apple.com  Fri Jan 30 11:56:15 2009
From: clattner at apple.com (Chris Lattner)
Date: Fri, 30 Jan 2009 09:56:15 -0800
Subject: [llvm-commits] [llvm]	r62045	-
	/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
In-Reply-To: <49833E1A.1060901@lip6.fr>
References: <200901112015.n0BKFLnj013960@zion.cs.uiuc.edu>
	<496E0C68.1070209@lip6.fr>
	<98B6F687-3514-4E03-B6BB-6813B2B706D8@apple.com>
	<496FB230.8070702@lip6.fr>
	<876D467E-C3C9-4724-9853-2A93A59B0181@apple.com>
	<49833E1A.1060901@lip6.fr>
Message-ID: <8CB9B7F0-1ED8-478A-AD36-0912E0F02F77@apple.com>


On Jan 30, 2009, at 9:51 AM, Nicolas Geoffray wrote:

> Chris Lattner wrote:
>>
>> Hi Nicolas,
>>
>> Can you please summarize this discussion in a bugzilla report?  It  
>> would be nice to track this.  Thanks,
>>
> Done:
>
> http://llvm.org/bugs/show_bug.cgi?id=3445
>
Thanks!


From dalej at apple.com  Fri Jan 30 12:00:21 2009
From: dalej at apple.com (Dale Johannesen)
Date: Fri, 30 Jan 2009 10:00:21 -0800
Subject: [llvm-commits] [llvm] r63359 - in /llvm/trunk:
	include/llvm/CodeGen/SelectionDAG.h
	lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
In-Reply-To: <5A0CC7FC-7F52-45BE-9412-8552034F191C@apple.com>
References: <200901300134.n0U1YM1H028081@zion.cs.uiuc.edu>
	
	<096363F0-D686-47CD-AFDE-AC0D76958E22@apple.com>
	<5A0CC7FC-7F52-45BE-9412-8552034F191C@apple.com>
Message-ID: 


On Jan 29, 2009, at 6:22 PMPST, Chris Lattner wrote:

> On Jan 29, 2009, at 5:47 PM, Dale Johannesen wrote:
>>> Thanks Dale!  One issue: instead of "getCurDebugLoc()" and friends
>>> being on the SelectionDAG, please move them to do the dag builder
>>> class.
>>
>> What do you mean?  I had it in SelectionDAGLowering originally, which
>> looked right to me, but it looked like there wasn't an easy way to  
>> get
>> there from everywhere that was calling getNode.
>
> What places needed it other than SDBuilder?

I'm thinking of the target-dependent parts of that like  
TargetLowering::LowerCallTo; there are several in the various target  
files.   Doesn't seem to be an easy way to get the  
SelectionDAGLowering object from there.   (btw, I asked Evan's opinion  
of where this should go before doing it this way; he didn't care.)




From clattner at apple.com  Fri Jan 30 12:00:36 2009
From: clattner at apple.com (Chris Lattner)
Date: Fri, 30 Jan 2009 10:00:36 -0800
Subject: [llvm-commits] [llvm] r63384 - in /llvm/trunk:
	include/llvm/Support/CommandLine.h lib/Support/CommandLine.cpp
In-Reply-To: <200901300819.n0U8JkUt008727@zion.cs.uiuc.edu>
References: <200901300819.n0U8JkUt008727@zion.cs.uiuc.edu>
Message-ID: <5F0660E8-D815-494B-A7F3-A6B9B16DD4E3@apple.com>


On Jan 30, 2009, at 12:19 AM, Mike Stump wrote:

> Author: mrs
> Date: Fri Jan 30 02:19:46 2009
> New Revision: 63384
>
> URL: http://llvm.org/viewvc/llvm-project?rev=63384&view=rev
> Log:
> Add opposite_of and inverse_opt to support -fno- style options.  This
> is necessary for eventual gcc commmand line compatibility.

Hi Mike,

This is an interesting approach to fix this problem, but it pushes the  
problem off to the clients.  In the clang code you added, we now have  
two cl::opt's and have to have this sort of thing:

+  if (EnableBlocks.getPosition() || DisableBlocks.getPosition())
     Options.Blocks = EnableBlocks;

which is gross :).

How about adding a new flag that can only be used with cl::opt  
options, maybe named cl::AllowInverse.  This would let us use it like  
this:

static llvm::cl::opt
EnableBlocks("fblocks", llvm::cl::desc("enable the 'blocks' language  
feature"), cl::AllowInverse);

and cause the option to eat either -fblocks or -fno-blocks.

Also, any patches to the CommandLine library should update the dox:
http://llvm.org/docs/CommandLine.html

Please revert this patch in the meantime, thanks!

-Chris



From clattner at apple.com  Fri Jan 30 12:08:30 2009
From: clattner at apple.com (Chris Lattner)
Date: Fri, 30 Jan 2009 10:08:30 -0800
Subject: [llvm-commits] [llvm] r63359 - in /llvm/trunk:
	include/llvm/CodeGen/SelectionDAG.h
	lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
In-Reply-To: 
References: <200901300134.n0U1YM1H028081@zion.cs.uiuc.edu>
	
	<096363F0-D686-47CD-AFDE-AC0D76958E22@apple.com>
	<5A0CC7FC-7F52-45BE-9412-8552034F191C@apple.com>
	
Message-ID: 


On Jan 30, 2009, at 10:00 AM, Dale Johannesen wrote:

>
> On Jan 29, 2009, at 6:22 PMPST, Chris Lattner wrote:
>
>> On Jan 29, 2009, at 5:47 PM, Dale Johannesen wrote:
>>>> Thanks Dale!  One issue: instead of "getCurDebugLoc()" and friends
>>>> being on the SelectionDAG, please move them to do the dag builder
>>>> class.
>>>
>>> What do you mean?  I had it in SelectionDAGLowering originally,  
>>> which
>>> looked right to me, but it looked like there wasn't an easy way to
>>> get
>>> there from everywhere that was calling getNode.
>>
>> What places needed it other than SDBuilder?
>
> I'm thinking of the target-dependent parts of that like
> TargetLowering::LowerCallTo; there are several in the various target
> files.   Doesn't seem to be an easy way to get the
> SelectionDAGLowering object from there.   (btw, I asked Evan's opinion
> of where this should go before doing it this way; he didn't care.)

While annoying, I think it would be better to pass the location to use  
into LowerCallTo.  Putting it in SelectionDAG makes it so that non- 
builder clients could accidentally use it instead of using a proper  
source location.

-Chris


From clattner at apple.com  Fri Jan 30 12:11:57 2009
From: clattner at apple.com (Chris Lattner)
Date: Fri, 30 Jan 2009 10:11:57 -0800
Subject: [llvm-commits] [llvm] r63377 - in /llvm/trunk:
	include/llvm/CodeGen/AsmPrinter.h
	include/llvm/Target/TargetAsmInfo.h
	lib/CodeGen/AsmPrinter/AsmPrinter.cpp
	lib/Target/PIC16/PIC16AsmPrinter.cpp
	lib/Target/PIC16/PIC16AsmPrinter.h
	lib/Target/PIC16/PIC16TargetAsmInfo.cpp
	lib/Target/PIC16/PIC16TargetAsmInfo.h
In-Reply-To: <200901300425.n0U4PJlC001274@zion.cs.uiuc.edu>
References: <200901300425.n0U4PJlC001274@zion.cs.uiuc.edu>
Message-ID: <54D6400B-DB8F-4D8D-AEE9-E68660C9BD24@apple.com>

On Jan 29, 2009, at 8:25 PM, Sanjiv Gupta wrote:
> URL: http://llvm.org/viewvc/llvm-project?rev=63377&view=rev
> Log:
> Enable emitting of constant values in non-default address space as  
> well. The APIs emitting constants now take an additional parameter  
> signifying the address space in which to emit. The APIs like  
> getData8BitsDirective() etc are made virtual enabling targets to be  
> able to define appropirate directivers for various sizes and address  
> spaces.

Hi Sanjiv,

Thank you for working on this.

> +    // Data directive accessors
> +    //
> +    virtual const char *getData8bitsDirective(unsigned AddrSpace =  
> 0) const {
> +      return Data8bitsDirective;
> +    }

Unfortunately, this significantly pessimizes the common case where  
AddrSpace = 0 by making these trivial functions virtual.  How about  
something like this?:

     // virtual, also protected.
     virtual const char *getData8bitsDirectiveV(unsigned AddrSpace)  
const;

     // nonvirtual, public.
     const char *getData16bitsDirective(unsigned AddrSpace = 0) const {
       return AddrSpace == 0 ? Data16bitsDirective :  
getData8bitsDirectiveV(AddrSpace);
     }

I think this should be a pretty straight-forward change.  What do you  
think?

-Chris



From clattner at apple.com  Fri Jan 30 12:13:54 2009
From: clattner at apple.com (Chris Lattner)
Date: Fri, 30 Jan 2009 10:13:54 -0800
Subject: [llvm-commits] [llvm] r63370 - in /llvm/trunk:
	include/llvm/Analysis/AliasAnalysis.h
	lib/Analysis/BasicAliasAnalysis.cpp
	lib/CodeGen/ScheduleDAGInstrs.cpp
In-Reply-To: <200901300249.n0U2nFtJ030721@zion.cs.uiuc.edu>
References: <200901300249.n0U2nFtJ030721@zion.cs.uiuc.edu>
Message-ID: 

On Jan 29, 2009, at 6:49 PM, Dan Gohman wrote:
> Author: djg
> Date: Thu Jan 29 20:49:14 2009
> New Revision: 63370
>
> URL: http://llvm.org/viewvc/llvm-project?rev=63370&view=rev
> Log:
> Fix a post-RA scheduling dependency bug.

Hi Dan,

> +/// isIdentifiedObject - Return true if this pointer refers to a  
> distinct and
> +/// identifiable object.
> +///
> +bool isIdentifiedObject(const Value *V);

the comment in the .cpp file is significantly more useful than this,  
please copy it.

> +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Thu Jan 29  
> 20:49:14 2009
> @@ -80,7 +80,7 @@
> ///    ByVal and NoAlias Arguments
> ///    NoAlias returns
> ///
> -static bool isIdentifiedObject(const Value *V) {
> +bool llvm::isIdentifiedObject(const Value *V) {

Please move this function into AliasAnalysis.cpp.

-Chris



From dpatel at apple.com  Fri Jan 30 12:20:32 2009
From: dpatel at apple.com (Devang Patel)
Date: Fri, 30 Jan 2009 18:20:32 -0000
Subject: [llvm-commits] [llvm] r63400 - in /llvm/trunk:
 docs/SourceLevelDebugging.html include/llvm/Analysis/DebugInfo.h
 lib/Analysis/DebugInfo.cpp lib/CodeGen/AsmPrinter/DwarfWriter.cpp
 test/DebugInfo/2009-01-29-HeaderLocation.ll
Message-ID: <200901301820.n0UIKWdR008456@zion.cs.uiuc.edu>

Author: dpatel
Date: Fri Jan 30 12:20:31 2009
New Revision: 63400

URL: http://llvm.org/viewvc/llvm-project?rev=63400&view=rev
Log:


 Each input file is encoded as a separate compile unit in LLVM debugging
information output. However, many target specific tool chains prefer to encode
only one compile unit in an object file. In this situation, the LLVM code
generator will include  debugging information entities in the compile unit 
that is marked as main compile unit. The code generator accepts maximum one main
compile unit per module. If a module does not contain any main compile unit 
then the code generator will emit multiple compile units in the output object 
file.

[Part 1]

Update DebugInfo APIs to accept optional boolean value while creating DICompileUnit  to mark the unit as "main" unit. By defaults all units are considered  non-main.  Update SourceLevelDebugging.html to document "main" compile unit.

Update DebugInfo APIs to not accept and encode separate source file/directory entries while creating various llvm.dbg.* entities. There was a recent, yet to be documented, change to include this additional information so no documentation changes are required here.

Update DwarfDebug to handle "main" compile unit. If "main" compile unit is seen then all DIEs are inserted into "main" compile unit. All other compile units are used to find source location for llvm.dbg.* values. If there is not any "main" compile unit then create unique compile unit DIEs for each llvm.dbg.compile_unit.

[Part 2]

Create separate llvm.dbg.compile_unit for each input file. Mark compile unit create for main_input_filename as "main" compile unit. Use appropriate compile unit, based on source location information collected from the tree node, while creating llvm.dbg.* values using DebugInfo APIs.

---

This is Part 1.


Added:
    llvm/trunk/test/DebugInfo/2009-01-29-HeaderLocation.ll
Modified:
    llvm/trunk/docs/SourceLevelDebugging.html
    llvm/trunk/include/llvm/Analysis/DebugInfo.h
    llvm/trunk/lib/Analysis/DebugInfo.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp

Modified: llvm/trunk/docs/SourceLevelDebugging.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/SourceLevelDebugging.html?rev=63400&r1=63399&r2=63400&view=diff

==============================================================================
--- llvm/trunk/docs/SourceLevelDebugging.html (original)
+++ llvm/trunk/docs/SourceLevelDebugging.html Fri Jan 30 12:20:31 2009
@@ -378,6 +378,7 @@
     sbyte*, ;; Source file name
     sbyte*, ;; Source file directory (includes trailing slash)
     sbyte*  ;; Producer (ex. "4.0.1 LLVM (LLVM research group)")
+    bool    ;; True if this is a main compile unit. 
   }
 
      
 
@@ -392,6 +393,14 @@
 using this context.  Compile unit descriptors also provide context for source
 line correspondence.
        
 
+
       Each input file is encoded as a separate compile unit in LLVM debugging
+information output. However, many target specific tool chains prefer to encode
+only one compile unit in an object file. In this situation, the LLVM code
+generator will include  debugging information entities in the compile unit 
+that is marked as main compile unit. The code generator accepts maximum one main
+compile unit per module. If a module does not contain any main compile unit 
+then the code generator will emit multiple compile units in the output object 
+file.
      Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=63400&r1=63399&r2=63400&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Fri Jan 30 12:20:31 2009 @@ -109,8 +109,18 @@ std::string getFilename() const { return getStringField(3); } std::string getDirectory() const { return getStringField(4); } std::string getProducer() const { return getStringField(5); } - bool isOptimized() const { return getUnsignedField(6); } - std::string getFlags() const { return getStringField(7); } + + /// isMain - Each input file is encoded as a separate compile unit in LLVM + /// debugging information output. However, many target specific tool chains + /// prefer to encode only one compile unit in an object file. In this + /// situation, the LLVM code generator will include debugging information + /// entities in the compile unit that is marked as main compile unit. The + /// code generator accepts maximum one main compile unit per module. If a + /// module does not contain any main compile unit then the code generator + /// will emit multiple compile units in the output object file. + bool isMain() const { return getUnsignedField(6); } + bool isOptimized() const { return getUnsignedField(7); } + std::string getFlags() const { return getStringField(8); } /// Verify - Verify that a compile unit is well formed. bool Verify() const; @@ -183,16 +193,6 @@ bool isProtected() const { return (getFlags() & FlagProtected) != 0; } bool isForwardDecl() const { return (getFlags() & FlagFwdDecl) != 0; } - virtual std::string getFilename() const { - assert (0 && "Invalid DIDescriptor"); - return ""; - } - - virtual std::string getDirectory() const { - assert (0 && "Invalid DIDescriptor"); - return ""; - } - /// dump - print type. void dump() const; }; @@ -201,10 +201,7 @@ class DIBasicType : public DIType { public: explicit DIBasicType(GlobalVariable *GV); - unsigned getEncoding() const { return getUnsignedField(9); } - std::string getFilename() const { return getStringField(10); } - std::string getDirectory() const { return getStringField(11); } /// dump - print basic type. void dump() const; @@ -218,10 +215,7 @@ : DIType(GV, true, true) {} public: explicit DIDerivedType(GlobalVariable *GV); - DIType getTypeDerivedFrom() const { return getFieldAs(9); } - std::string getFilename() const { return getStringField(10); } - std::string getDirectory() const { return getStringField(11); } /// dump - print derived type. void dump() const; @@ -233,10 +227,7 @@ class DICompositeType : public DIDerivedType { public: explicit DICompositeType(GlobalVariable *GV); - DIArray getTypeArray() const { return getFieldAs(10); } - std::string getFilename() const { return getStringField(11); } - std::string getDirectory() const { return getStringField(12); } /// Verify - Verify that a composite type descriptor is well formed. bool Verify() const; @@ -279,16 +270,6 @@ unsigned isLocalToUnit() const { return getUnsignedField(9); } unsigned isDefinition() const { return getUnsignedField(10); } - virtual std::string getFilename() const { - assert (0 && "Invalid DIDescriptor"); - return ""; - } - - virtual std::string getDirectory() const { - assert (0 && "Invalid DIDescriptor"); - return ""; - } - /// dump - print global. void dump() const; }; @@ -297,8 +278,6 @@ class DISubprogram : public DIGlobal { public: explicit DISubprogram(GlobalVariable *GV = 0); - std::string getFilename() const { return getStringField(11); } - std::string getDirectory() const { return getStringField(12); } DICompositeType getType() const { return getFieldAs(8); } /// Verify - Verify that a subprogram descriptor is well formed. @@ -312,10 +291,7 @@ class DIGlobalVariable : public DIGlobal { public: explicit DIGlobalVariable(GlobalVariable *GV = 0); - GlobalVariable *getGlobal() const { return getGlobalVariableField(11); } - std::string getFilename() const { return getStringField(12); } - std::string getDirectory() const { return getStringField(13); } /// Verify - Verify that a global variable descriptor is well formed. bool Verify() const; @@ -335,8 +311,6 @@ DICompileUnit getCompileUnit() const{ return getFieldAs(3); } unsigned getLineNumber() const { return getUnsignedField(4); } DIType getType() const { return getFieldAs(5); } - std::string getFilename() const { return getStringField(6); } - std::string getDirectory() const { return getStringField(7); } /// isVariable - Return true if the specified tag is legal for DIVariable. static bool isVariable(unsigned Tag); @@ -402,6 +376,7 @@ const std::string &Filename, const std::string &Directory, const std::string &Producer, + bool isMain = false, bool isOptimized = false, const char *Flags = ""); @@ -413,9 +388,7 @@ DICompileUnit CompileUnit, unsigned LineNumber, uint64_t SizeInBits, uint64_t AlignInBits, uint64_t OffsetInBits, unsigned Flags, - unsigned Encoding, - const std::string *FileName = 0, - const std::string *Directory = 0); + unsigned Encoding); /// CreateDerivedType - Create a derived type like const qualified type, /// pointer, typedef, etc. @@ -425,9 +398,7 @@ unsigned LineNumber, uint64_t SizeInBits, uint64_t AlignInBits, uint64_t OffsetInBits, unsigned Flags, - DIType DerivedFrom, - const std::string *FileName = 0, - const std::string *Directory = 0); + DIType DerivedFrom); /// CreateCompositeType - Create a composite type like array, struct, etc. DICompositeType CreateCompositeType(unsigned Tag, DIDescriptor Context, @@ -438,9 +409,7 @@ uint64_t AlignInBits, uint64_t OffsetInBits, unsigned Flags, DIType DerivedFrom, - DIArray Elements, - const std::string *FileName = 0, - const std::string *Directory = 0); + DIArray Elements); /// CreateSubprogram - Create a new descriptor for the specified subprogram. /// See comments in DISubprogram for descriptions of these fields. @@ -449,9 +418,7 @@ const std::string &LinkageName, DICompileUnit CompileUnit, unsigned LineNo, DIType Type, bool isLocalToUnit, - bool isDefinition, - const std::string *FileName = 0, - const std::string *Directory = 0); + bool isDefinition); /// CreateGlobalVariable - Create a new descriptor for the specified global. DIGlobalVariable @@ -460,17 +427,13 @@ const std::string &LinkageName, DICompileUnit CompileUnit, unsigned LineNo, DIType Type, bool isLocalToUnit, - bool isDefinition, llvm::GlobalVariable *GV, - const std::string *FileName = 0, - const std::string *Directory = 0); + bool isDefinition, llvm::GlobalVariable *GV); /// CreateVariable - Create a new descriptor for the specified variable. DIVariable CreateVariable(unsigned Tag, DIDescriptor Context, const std::string &Name, DICompileUnit CompileUnit, unsigned LineNo, - DIType Type, - const std::string *FileName = 0, - const std::string *Directory = 0); + DIType Type); /// CreateBlock - This creates a descriptor for a lexical block with the /// specified parent context. Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=63400&r1=63399&r2=63400&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Fri Jan 30 12:20:31 2009 @@ -442,6 +442,7 @@ const std::string &Filename, const std::string &Directory, const std::string &Producer, + bool isMain, bool isOptimized, const char *Flags) { Constant *Elts[] = { @@ -451,6 +452,7 @@ GetStringConstant(Filename), GetStringConstant(Directory), GetStringConstant(Producer), + ConstantInt::get(Type::Int1Ty, isMain), ConstantInt::get(Type::Int1Ty, isOptimized), GetStringConstant(Flags) }; @@ -492,9 +494,7 @@ uint64_t SizeInBits, uint64_t AlignInBits, uint64_t OffsetInBits, unsigned Flags, - unsigned Encoding, - const std::string *FileName, - const std::string *Directory) { + unsigned Encoding) { Constant *Elts[] = { GetTagConstant(dwarf::DW_TAG_base_type), getCastToEmpty(Context), @@ -505,9 +505,7 @@ ConstantInt::get(Type::Int64Ty, AlignInBits), ConstantInt::get(Type::Int64Ty, OffsetInBits), ConstantInt::get(Type::Int32Ty, Flags), - ConstantInt::get(Type::Int32Ty, Encoding), - GetStringConstant(FileName ? FileName->c_str() : ""), - GetStringConstant(Directory ? Directory->c_str() : "") + ConstantInt::get(Type::Int32Ty, Encoding) }; Constant *Init = ConstantStruct::get(Elts, sizeof(Elts)/sizeof(Elts[0])); @@ -531,9 +529,7 @@ uint64_t AlignInBits, uint64_t OffsetInBits, unsigned Flags, - DIType DerivedFrom, - const std::string *FileName, - const std::string *Directory) { + DIType DerivedFrom) { Constant *Elts[] = { GetTagConstant(Tag), getCastToEmpty(Context), @@ -544,9 +540,7 @@ ConstantInt::get(Type::Int64Ty, AlignInBits), ConstantInt::get(Type::Int64Ty, OffsetInBits), ConstantInt::get(Type::Int32Ty, Flags), - getCastToEmpty(DerivedFrom), - GetStringConstant(FileName ? FileName->c_str() : ""), - GetStringConstant(Directory ? Directory->c_str() : "") + getCastToEmpty(DerivedFrom) }; Constant *Init = ConstantStruct::get(Elts, sizeof(Elts)/sizeof(Elts[0])); @@ -570,9 +564,7 @@ uint64_t OffsetInBits, unsigned Flags, DIType DerivedFrom, - DIArray Elements, - const std::string *FileName, - const std::string *Directory) { + DIArray Elements) { Constant *Elts[] = { GetTagConstant(Tag), @@ -585,9 +577,7 @@ ConstantInt::get(Type::Int64Ty, OffsetInBits), ConstantInt::get(Type::Int32Ty, Flags), getCastToEmpty(DerivedFrom), - getCastToEmpty(Elements), - GetStringConstant(FileName ? FileName->c_str() : ""), - GetStringConstant(Directory ? Directory->c_str() : "") + getCastToEmpty(Elements) }; Constant *Init = ConstantStruct::get(Elts, sizeof(Elts)/sizeof(Elts[0])); @@ -611,9 +601,7 @@ DICompileUnit CompileUnit, unsigned LineNo, DIType Type, bool isLocalToUnit, - bool isDefinition, - const std::string *FileName, - const std::string *Directory) { + bool isDefinition) { Constant *Elts[] = { GetTagConstant(dwarf::DW_TAG_subprogram), @@ -626,9 +614,7 @@ ConstantInt::get(Type::Int32Ty, LineNo), getCastToEmpty(Type), ConstantInt::get(Type::Int1Ty, isLocalToUnit), - ConstantInt::get(Type::Int1Ty, isDefinition), - GetStringConstant(FileName ? FileName->c_str() : ""), - GetStringConstant(Directory ? Directory->c_str() : "") + ConstantInt::get(Type::Int1Ty, isDefinition) }; Constant *Init = ConstantStruct::get(Elts, sizeof(Elts)/sizeof(Elts[0])); @@ -648,9 +634,7 @@ const std::string &LinkageName, DICompileUnit CompileUnit, unsigned LineNo, DIType Type,bool isLocalToUnit, - bool isDefinition, llvm::GlobalVariable *Val, - const std::string *FileName, - const std::string *Directory) { + bool isDefinition, llvm::GlobalVariable *Val) { Constant *Elts[] = { GetTagConstant(dwarf::DW_TAG_variable), getCastToEmpty(GetOrCreateGlobalVariableAnchor()), @@ -663,9 +647,7 @@ getCastToEmpty(Type), ConstantInt::get(Type::Int1Ty, isLocalToUnit), ConstantInt::get(Type::Int1Ty, isDefinition), - ConstantExpr::getBitCast(Val, EmptyStructPtr), - GetStringConstant(FileName ? FileName->c_str() : ""), - GetStringConstant(Directory ? Directory->c_str() : "") + ConstantExpr::getBitCast(Val, EmptyStructPtr) }; Constant *Init = ConstantStruct::get(Elts, sizeof(Elts)/sizeof(Elts[0])); @@ -683,20 +665,14 @@ DIVariable DIFactory::CreateVariable(unsigned Tag, DIDescriptor Context, const std::string &Name, DICompileUnit CompileUnit, unsigned LineNo, - DIType Type, - const std::string *FileName, - const std::string *Directory) { - - + DIType Type) { Constant *Elts[] = { GetTagConstant(Tag), getCastToEmpty(Context), GetStringConstant(Name), getCastToEmpty(CompileUnit), ConstantInt::get(Type::Int32Ty, LineNo), - getCastToEmpty(Type), - GetStringConstant(FileName ? FileName->c_str() : ""), - GetStringConstant(Directory ? Directory->c_str() : "") + getCastToEmpty(Type) }; Constant *Init = ConstantStruct::get(Elts, sizeof(Elts)/sizeof(Elts[0])); Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=63400&r1=63399&r2=63400&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Fri Jan 30 12:20:31 2009 @@ -1274,6 +1274,9 @@ /// of each entry in this vector corresponds to the sources in MMI. DenseMap DW_CUs; + /// MainCU - Some platform prefers one compile unit per .o file. In such + /// cases, all dies are inserted in MainCU. + CompileUnit *MainCU; /// AbbreviationsSet - Used to uniquely define abbreviations. /// FoldingSet AbbreviationsSet; @@ -1559,16 +1562,8 @@ void AddSourceLine(DIE *Die, const DIVariable *V) { unsigned FileID = 0; unsigned Line = V->getLineNumber(); - if (V->getVersion() <= LLVMDebugVersion6) { - // Version6 or earlier. Use compile unit info to get file id. - CompileUnit *Unit = FindCompileUnit(V->getCompileUnit()); - FileID = Unit->getID(); - } else { - // Version7 or newer, use filename and directory info from DIVariable - // directly. - unsigned DID = Directories.idFor(V->getDirectory()); - FileID = SrcFiles.idFor(SrcFileInfo(DID, V->getFilename())); - } + CompileUnit *Unit = FindCompileUnit(V->getCompileUnit()); + FileID = Unit->getID(); AddUInt(Die, DW_AT_decl_file, 0, FileID); AddUInt(Die, DW_AT_decl_line, 0, Line); } @@ -1578,16 +1573,8 @@ void AddSourceLine(DIE *Die, const DIGlobal *G) { unsigned FileID = 0; unsigned Line = G->getLineNumber(); - if (G->getVersion() <= LLVMDebugVersion6) { - // Version6 or earlier. Use compile unit info to get file id. - CompileUnit *Unit = FindCompileUnit(G->getCompileUnit()); - FileID = Unit->getID(); - } else { - // Version7 or newer, use filename and directory info from DIGlobal - // directly. - unsigned DID = Directories.idFor(G->getDirectory()); - FileID = SrcFiles.idFor(SrcFileInfo(DID, G->getFilename())); - } + CompileUnit *Unit = FindCompileUnit(G->getCompileUnit()); + FileID = Unit->getID(); AddUInt(Die, DW_AT_decl_file, 0, FileID); AddUInt(Die, DW_AT_decl_line, 0, Line); } @@ -1595,16 +1582,11 @@ void AddSourceLine(DIE *Die, const DIType *Ty) { unsigned FileID = 0; unsigned Line = Ty->getLineNumber(); - if (Ty->getVersion() <= LLVMDebugVersion6) { - // Version6 or earlier. Use compile unit info to get file id. - CompileUnit *Unit = FindCompileUnit(Ty->getCompileUnit()); - FileID = Unit->getID(); - } else { - // Version7 or newer, use filename and directory info from DIType - // directly. - unsigned DID = Directories.idFor(Ty->getDirectory()); - FileID = SrcFiles.idFor(SrcFileInfo(DID, Ty->getFilename())); - } + DICompileUnit CU = Ty->getCompileUnit(); + if (CU.isNull()) + return; + CompileUnit *Unit = FindCompileUnit(CU); + FileID = Unit->getID(); AddUInt(Die, DW_AT_decl_file, 0, FileID); AddUInt(Die, DW_AT_decl_line, 0, Line); } @@ -2091,7 +2073,9 @@ DISubprogram SPD(Desc.getGV()); // Get the compile unit context. - CompileUnit *Unit = FindCompileUnit(SPD.getCompileUnit()); + CompileUnit *Unit = MainCU; + if (!Unit) + Unit = FindCompileUnit(SPD.getCompileUnit()); // Get the subprogram die. DIE *SPDie = Unit->getDieMapSlotFor(SPD.getGV()); @@ -2122,7 +2106,9 @@ if (SPD.getName() == MF->getFunction()->getName()) { // Get the compile unit context. - CompileUnit *Unit = FindCompileUnit(SPD.getCompileUnit()); + CompileUnit *Unit = MainCU; + if (!Unit) + Unit = FindCompileUnit(SPD.getCompileUnit()); // Get the subprogram die. DIE *SPDie = Unit->getDieMapSlotFor(SPD.getGV()); @@ -2294,6 +2280,15 @@ /// void SizeAndOffsets() { // Process base compile unit. + if (MainCU) { + // Compute size of compile unit header + unsigned Offset = sizeof(int32_t) + // Length of Compilation Unit Info + sizeof(int16_t) + // DWARF version number + sizeof(int32_t) + // Offset Into Abbrev. Section + sizeof(int8_t); // Pointer Size (in bytes) + SizeAndOffsetDie(MainCU->getDie(), Offset, true); + return; + } for (DenseMap::iterator CI = DW_CUs.begin(), CE = DW_CUs.end(); CI != CE; ++CI) { CompileUnit *Unit = CI->second; @@ -2315,6 +2310,8 @@ for (DenseMap::iterator CI = DW_CUs.begin(), CE = DW_CUs.end(); CI != CE; ++CI) { CompileUnit *Unit = CI->second; + if (MainCU) + Unit = MainCU; DIE *Die = Unit->getDie(); // Emit the compile units header. EmitLabel("info_begin", Unit->getID()); @@ -2340,6 +2337,8 @@ EmitLabel("info_end", Unit->getID()); Asm->EOL(); + if (MainCU) + return; } } @@ -2639,6 +2638,8 @@ for (DenseMap::iterator CI = DW_CUs.begin(), CE = DW_CUs.end(); CI != CE; ++CI) { CompileUnit *Unit = CI->second; + if (MainCU) + Unit = MainCU; EmitDifference("pubnames_end", Unit->getID(), "pubnames_begin", Unit->getID(), true); @@ -2672,6 +2673,8 @@ EmitLabel("pubnames_end", Unit->getID()); Asm->EOL(); + if (MainCU) + return; } } @@ -2789,6 +2792,10 @@ AddString(Die, DW_AT_APPLE_flags, DW_FORM_string, Flags); CompileUnit *Unit = new CompileUnit(ID, Die); + if (DIUnit.isMain()) { + assert (!MainCU && "Multiple main compile units are found!"); + MainCU = Unit; + } DW_CUs[DIUnit.getGV()] = Unit; } } @@ -2802,7 +2809,9 @@ for (std::vector::iterator GVI = Result.begin(), GVE = Result.end(); GVI != GVE; ++GVI) { DIGlobalVariable DI_GV(*GVI); - CompileUnit *DW_Unit = FindCompileUnit(DI_GV.getCompileUnit()); + CompileUnit *DW_Unit = MainCU; + if (!DW_Unit) + DW_Unit = FindCompileUnit(DI_GV.getCompileUnit()); // Check for pre-existence. DIE *&Slot = DW_Unit->getDieMapSlotFor(DI_GV.getGV()); @@ -2839,7 +2848,9 @@ RE = Result.end(); RI != RE; ++RI) { DISubprogram SP(*RI); - CompileUnit *Unit = FindCompileUnit(SP.getCompileUnit()); + CompileUnit *Unit = MainCU; + if (!Unit) + Unit = FindCompileUnit(SP.getCompileUnit()); // Check for pre-existence. DIE *&Slot = Unit->getDieMapSlotFor(SP.getGV()); @@ -2862,6 +2873,7 @@ // DwarfDebug(raw_ostream &OS, AsmPrinter *A, const TargetAsmInfo *T) : Dwarf(OS, A, T, "dbg") + , MainCU(NULL) , AbbreviationsSet(InitAbbreviationsSetSize) , Abbreviations() , ValuesSet(InitValuesSetSize) Added: llvm/trunk/test/DebugInfo/2009-01-29-HeaderLocation.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2009-01-29-HeaderLocation.ll?rev=63400&view=auto ============================================================================== --- llvm/trunk/test/DebugInfo/2009-01-29-HeaderLocation.ll (added) +++ llvm/trunk/test/DebugInfo/2009-01-29-HeaderLocation.ll Fri Jan 30 12:20:31 2009 @@ -0,0 +1,46 @@ +; RUN: llvm-as < %s | llc | grep "m.h" | count 1 +target triple = "i386-apple-darwin9.6" + %llvm.dbg.anchor.type = type { i32, i32 } + %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 } + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } + %llvm.dbg.composite.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, { }* } + %llvm.dbg.subprogram.type = type { i32, { }*, { }*, i8*, i8*, i8*, { }*, i32, { }*, i1, i1 } + at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] + at .str = internal constant [4 x i8] c"m.c\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at .str1 = internal constant [26 x i8] c"/Volumes/Nanpura/dbg.test\00", section "llvm.metadata" ; <[26 x i8]*> [#uses=1] + at .str2 = internal constant [52 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build)\00", section "llvm.metadata" ; <[52 x i8]*> [#uses=1] + at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([52 x i8]* @.str2, i32 0, i32 0), i1 true, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] + at .str3 = internal constant [4 x i8] c"int\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, i32 5 }, section "llvm.metadata" ; <%llvm.dbg.basictype.type*> [#uses=1] + at llvm.dbg.array = internal constant [1 x { }*] [ { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) ], section "llvm.metadata" ; <[1 x { }*]*> [#uses=1] + at llvm.dbg.composite = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([1 x { }*]* @llvm.dbg.array to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at .str4 = internal constant [4 x i8] c"m.h\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at llvm.dbg.compile_unit5 = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str4, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([52 x i8]* @.str2, i32 0, i32 0), i1 false, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] + at llvm.dbg.subprograms = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 46 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] + at .str6 = internal constant [5 x i8] c"main\00", section "llvm.metadata" ; <[5 x i8]*> [#uses=1] + at llvm.dbg.subprogram = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([5 x i8]* @.str6, i32 0, i32 0), i8* getelementptr ([5 x i8]* @.str6, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit5 to { }*), i32 2, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite to { }*), i1 false, i1 true }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + +define i32 @main() nounwind { +entry: + %retval = alloca i32 ; [#uses=2] + %0 = alloca i32 ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + call void @llvm.dbg.func.start({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*)) + call void @llvm.dbg.stoppoint(i32 2, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit5 to { }*)) + store i32 0, i32* %0, align 4 + %1 = load i32* %0, align 4 ; [#uses=1] + store i32 %1, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval1 = load i32* %retval ; [#uses=1] + call void @llvm.dbg.stoppoint(i32 2, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit5 to { }*)) + call void @llvm.dbg.region.end({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*)) + ret i32 %retval1 +} + +declare void @llvm.dbg.func.start({ }*) nounwind + +declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind + +declare void @llvm.dbg.region.end({ }*) nounwind From dpatel at apple.com Fri Jan 30 12:21:04 2009 From: dpatel at apple.com (Devang Patel) Date: Fri, 30 Jan 2009 18:21:04 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63401 - in /llvm-gcc-4.2/trunk/gcc: llvm-debug.cpp llvm-debug.h Message-ID: <200901301821.n0UIL4pp008498@zion.cs.uiuc.edu> Author: dpatel Date: Fri Jan 30 12:21:04 2009 New Revision: 63401 URL: http://llvm.org/viewvc/llvm-project?rev=63401&view=rev Log: Each input file is encoded as a separate compile unit in LLVM debugging information output. However, many target specific tool chains prefer to encode only one compile unit in an object file. In this situation, the LLVM code generator will include debugging information entities in the compile unit that is marked as main compile unit. The code generator accepts maximum one main compile unit per module. If a module does not contain any main compile unit then the code generator will emit multiple compile units in the output object file. [Part 1] Update DebugInfo APIs to accept optional boolean value while creating DICompileUnit to mark the unit as "main" unit. By defaults all units are considered non-main. Update SourceLevelDebugging.html to document "main" compile unit. Update DebugInfo APIs to not accept and encode separate source file/directory entries while creating various llvm.dbg.* entities. There was a recent change to include this additional information so no documentation changes are required here. Update DwarfDebug to handle "main" compile unit. If "main" compile unit is seen then all DIEs are inserted into "main" compile unit. All other compile units are used to find source location for llvm.dbg.* values. If there is not any "main" compile unit then create unique compile unit DIEs for each llvm.dbg.compile_unit. [Part 2] Create separate llvm.dbg.compile_unit for each input file. Mark compile unit create for main_input_filename as "main" compile unit. Use appropriate compile unit, based on source location information collected from the tree node, while creating llvm.dbg.* values using DebugInfo APIs. --- This is Part 2. Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp llvm-gcc-4.2/trunk/gcc/llvm-debug.h Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp?rev=63401&r1=63400&r2=63401&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Fri Jan 30 12:21:04 2009 @@ -148,6 +148,9 @@ static expanded_location GetNodeLocation(tree Node, bool UseStub = true) { expanded_location Location = { NULL, 0 }; + if (Node == NULL_TREE) + return Location; + tree Name = NULL; if (DECL_P(Node)) { @@ -200,7 +203,16 @@ , PrevBB(NULL) , RegionStack() { - MainCompileUnit = createCompileUnit(main_input_filename); + + // Each input file is encoded as a separate compile unit in LLVM + // debugging information output. However, many target specific tool chains + // prefer to encode only one compile unit in an object file. In this + // situation, the LLVM code generator will include debugging information + // entities in the compile unit that is marked as main compile unit. The + // code generator accepts maximum one main compile unit per module. If a + // module does not contain any main compile unit then the code generator + // will emit multiple compile units in the output object file. + DICompileUnit M = getOrCreateCompileUnit(main_input_filename, true); } /// EmitFunctionStart - Constructs the debug code for entering a function - @@ -209,19 +221,16 @@ BasicBlock *CurBB) { // Gather location information. expanded_location Loc = GetNodeLocation(FnDecl, false); - std::string Filename, Directory; - DirectoryAndFile(Loc.file, Directory, Filename); const char *FnName = GetNodeName(FnDecl); const char *LinkageName = getLinkageName(FnDecl); DISubprogram SP = DebugFactory.CreateSubprogram(findRegion(FnDecl), FnName, FnName, LinkageName, - MainCompileUnit, CurLineNo, + getOrCreateCompileUnit(Loc.file), CurLineNo, getOrCreateType(TREE_TYPE(FnDecl)), Fn->hasInternalLinkage(), - true /*definition*/, - &Filename, &Directory); + true /*definition*/); DebugFactory.InsertSubprogramStart(SP, CurBB); @@ -233,7 +242,7 @@ /// findRegion - Find tree_node N's region. DIDescriptor DebugInfo::findRegion(tree Node) { if (Node == NULL_TREE) - return MainCompileUnit; + return getOrCreateCompileUnit(main_input_filename); std::map::iterator I = RegionMap.find(Node); if (I != RegionMap.end()) @@ -258,7 +267,7 @@ } // Otherwise main compile unit covers everything. - return MainCompileUnit; + return getOrCreateCompileUnit(main_input_filename); } /// EmitRegionStart- Constructs the debug code for entering a declarative @@ -296,14 +305,12 @@ assert(!RegionStack.empty() && "Region stack mismatch, stack empty!"); expanded_location Loc = GetNodeLocation(decl, false); - std::string Filename, Directory; - DirectoryAndFile(Loc.file, Directory, Filename); // Construct variable. llvm::DIVariable D = - DebugFactory.CreateVariable(Tag, RegionStack.back(), Name, MainCompileUnit, - Loc.line, getOrCreateType(type), &Filename, - &Directory); + DebugFactory.CreateVariable(Tag, RegionStack.back(), Name, + getOrCreateCompileUnit(Loc.file), + Loc.line, getOrCreateType(type)); // Insert an llvm.dbg.declare into the current block. DebugFactory.InsertDeclare(AI, D, CurBB); @@ -324,8 +331,9 @@ PrevLineNo = CurLineNo; PrevBB = CurBB; - DebugFactory.InsertStopPoint(MainCompileUnit, CurLineNo, 0 /*column no. */, - CurBB); + DebugFactory.InsertStopPoint(getOrCreateCompileUnit(CurFullPath), + CurLineNo, 0 /*column no. */, + CurBB); } /// EmitGlobalVariable - Emit information about a global variable. @@ -333,16 +341,13 @@ void DebugInfo::EmitGlobalVariable(GlobalVariable *GV, tree decl) { // Gather location information. expanded_location Loc = expand_location(DECL_SOURCE_LOCATION(decl)); - std::string Filename, Directory; - DirectoryAndFile(Loc.file, Directory, Filename); DIType TyD = getOrCreateType(TREE_TYPE(decl)); - DebugFactory.CreateGlobalVariable(MainCompileUnit, GV->getNameStr(), - GV->getNameStr(), getLinkageName(decl), - MainCompileUnit, Loc.line, - TyD, GV->hasInternalLinkage(), - true/*definition*/, GV, - &Filename, &Directory); - + DebugFactory.CreateGlobalVariable(getOrCreateCompileUnit(Loc.file), + GV->getNameStr(), GV->getNameStr(), + getLinkageName(decl), + getOrCreateCompileUnit(Loc.file), Loc.line, + TyD, GV->hasInternalLinkage(), + true/*definition*/, GV); } /// createBasicType - Create BasicType. @@ -385,9 +390,12 @@ break; } } - return DebugFactory.CreateBasicType(MainCompileUnit, TypeName, - MainCompileUnit, 0, Size, Align, - 0, 0, Encoding); + return + DebugFactory.CreateBasicType(getOrCreateCompileUnit(main_input_filename), + TypeName, + getOrCreateCompileUnit(main_input_filename), + 0, Size, Align, + 0, 0, Encoding); } /// createMethodType - Create MethodType. @@ -407,10 +415,11 @@ llvm::DIArray EltTypeArray = DebugFactory.GetOrCreateArray(&EltTys[0], EltTys.size()); - + return DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_subroutine_type, findRegion(type), "", - MainCompileUnit, 0, 0, 0, 0, 0, + getOrCreateCompileUnit(NULL), + 0, 0, 0, 0, 0, llvm::DIType(), EltTypeArray); } @@ -424,8 +433,10 @@ TREE_CODE(type) == BLOCK_POINTER_TYPE) ? DW_TAG_pointer_type : DW_TAG_reference_type; + expanded_location Loc = GetNodeLocation(type); return DebugFactory.CreateDerivedType(Tag, findRegion(type), "", - MainCompileUnit, 0 /*line no*/, + getOrCreateCompileUnit(NULL), + 0 /*line no*/, NodeSizeInBits(type), NodeAlignInBits(type), 0 /*offset */, @@ -476,11 +487,11 @@ llvm::DIArray SubscriptArray = DebugFactory.GetOrCreateArray(&Subscripts[0], Subscripts.size()); - + expanded_location Loc = GetNodeLocation(type); return DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_array_type, findRegion(type), "", - MainCompileUnit, - 0, NodeSizeInBits(type), + getOrCreateCompileUnit(Loc.file), 0, + NodeSizeInBits(type), NodeAlignInBits(type), 0, 0, getOrCreateType(EltTy), SubscriptArray); @@ -504,20 +515,17 @@ DebugFactory.GetOrCreateArray(&Elements[0], Elements.size()); expanded_location Loc = { NULL, 0 }; - std::string Filename = ""; - std::string Directory= ""; - if (TYPE_SIZE(type)) { + if (TYPE_SIZE(type)) // Incomplete enums do not have any location info. Loc = GetNodeLocation(TREE_CHAIN(type), false); - DirectoryAndFile(Loc.file, Directory, Filename); - } + return DebugFactory.CreateCompositeType(llvm::dwarf::DW_TAG_enumeration_type, findRegion(type), GetNodeName(type), - MainCompileUnit, Loc.line, + getOrCreateCompileUnit(Loc.file), + Loc.line, NodeSizeInBits(type), NodeAlignInBits(type), 0, 0, - llvm::DIType(), EltArray, - &Filename, &Directory); + llvm::DIType(), EltArray); } /// createStructType - Create StructType for struct or union or class. @@ -535,17 +543,14 @@ // recursive) and replace all uses of the forward declaration with the // final definition. expanded_location Loc = GetNodeLocation(TREE_CHAIN(type), false); - std::string Filename, Directory; - DirectoryAndFile(Loc.file, Directory, Filename); llvm::DIType FwdDecl = DebugFactory.CreateCompositeType(Tag, findRegion(type), GetNodeName(type), - MainCompileUnit, Loc.line, + getOrCreateCompileUnit(Loc.file), + Loc.line, 0, 0, 0, llvm::DIType::FlagFwdDecl, - llvm::DIType(), llvm::DIArray(), - &Filename, &Directory); - + llvm::DIType(), llvm::DIArray()); // forward declaration, if (TYPE_SIZE(type) == 0) @@ -565,11 +570,13 @@ tree BInfoType = BINFO_TYPE (BInfo); DIType BaseClass = getOrCreateType(BInfoType); + expanded_location loc = GetNodeLocation(type); // FIXME : name, size, align etc... DIType DTy = DebugFactory.CreateDerivedType(DW_TAG_inheritance, findRegion(type),"", - MainCompileUnit, 0,0,0, + getOrCreateCompileUnit(Loc.file), + 0,0,0, getInt64(BINFO_OFFSET(BInfo), 0), 0, BaseClass); EltTys.push_back(DTy); @@ -595,8 +602,6 @@ // Get the location of the member. expanded_location MemLoc = GetNodeLocation(Member, false); - std::string MemFilename, MemDirectory; - DirectoryAndFile(MemLoc.file, MemDirectory, MemFilename); // Field type is the declared type of the field. tree FieldNodeType = FieldType(Member); @@ -610,12 +615,12 @@ DIType DTy = DebugFactory.CreateDerivedType(DW_TAG_member, findRegion(Member), - MemberName, MainCompileUnit, + MemberName, + getOrCreateCompileUnit(MemLoc.file), MemLoc.line, NodeSizeInBits(Member), NodeAlignInBits(FieldNodeType), int_bit_position(Member), - Flags, MemberType, - &MemFilename, &MemDirectory); + Flags, MemberType); EltTys.push_back(DTy); } else { DEBUGASSERT(0 && "Unsupported member tree code!"); @@ -629,18 +634,15 @@ // Get the location of the member. expanded_location MemLoc = GetNodeLocation(Member, false); - std::string MemFilename, MemDirectory; - DirectoryAndFile(MemLoc.file, MemDirectory, MemFilename); const char *MemberName = GetNodeName(Member); const char *LinkageName = getLinkageName(Member); DIType SPTy = getOrCreateType(TREE_TYPE(Member)); DISubprogram SP = DebugFactory.CreateSubprogram(findRegion(Member), MemberName, MemberName, - LinkageName, MainCompileUnit, - MemLoc.line, SPTy, false, false, - &MemFilename, &MemDirectory); - + LinkageName, + getOrCreateCompileUnit(MemLoc.file), + MemLoc.line, SPTy, false, false); EltTys.push_back(SP); } @@ -650,10 +652,10 @@ llvm::DIType RealDecl = DebugFactory.CreateCompositeType(Tag, findRegion(type), GetNodeName(type), - MainCompileUnit, Loc.line, + getOrCreateCompileUnit(Loc.file), + Loc.line, NodeSizeInBits(type), NodeAlignInBits(type), - 0, 0, llvm::DIType(), Elements, - &Filename, &Directory); + 0, 0, llvm::DIType(), Elements); // Now that we have a real decl for the struct, replace anything using the // old decl with the new one. This will recursively update the debug info. @@ -669,16 +671,15 @@ if (tree Name = TYPE_NAME(type)) { if (TREE_CODE(Name) == TYPE_DECL && DECL_ORIGINAL_TYPE(Name)) { expanded_location TypeDefLoc = GetNodeLocation(Name); - std::string Filename, Directory; - DirectoryAndFile(TypeDefLoc.file, Directory, Filename); Ty = DebugFactory.CreateDerivedType(DW_TAG_typedef, findRegion(type), GetNodeName(Name), - MainCompileUnit, TypeDefLoc.line, + getOrCreateCompileUnit(TypeDefLoc.file), + TypeDefLoc.line, 0 /*size*/, 0 /*align*/, 0 /*offset */, 0 /*flags*/, - MainTy, &Filename, &Directory); + MainTy); // Set the slot early to prevent recursion difficulties. TypeCache[type] = Ty; return Ty; @@ -688,7 +689,8 @@ if (TYPE_VOLATILE(type)) { Ty = DebugFactory.CreateDerivedType(DW_TAG_volatile_type, findRegion(type), "", - MainCompileUnit, 0 /*line no*/, + getOrCreateCompileUnit(NULL), + 0 /*line no*/, NodeSizeInBits(type), NodeAlignInBits(type), 0 /*offset */, @@ -700,7 +702,8 @@ if (TYPE_READONLY(type)) Ty = DebugFactory.CreateDerivedType(DW_TAG_const_type, findRegion(type), "", - MainCompileUnit, 0 /*line no*/, + getOrCreateCompileUnit(NULL), + 0 /*line no*/, NodeSizeInBits(type), NodeAlignInBits(type), 0 /*offset */, @@ -798,9 +801,15 @@ return Ty; } -/// createCompileUnit - Get the compile unit from the cache or create a new -/// one if necessary. -DICompileUnit DebugInfo::createCompileUnit(const std::string &FullPath){ +/// getOrCreateCompileUnit - Get the compile unit from the cache or +/// create a new one if necessary. +DICompileUnit DebugInfo::getOrCreateCompileUnit(const char *FullPath, + bool isMain){ + + GlobalVariable *&CU = CUCache[FullPath ? FullPath : main_input_filename]; + if (CU) + return DICompileUnit(CU); + // Get source file information. std::string Directory; std::string FileName; @@ -828,8 +837,11 @@ else LangTag = DW_LANG_C89; - return DebugFactory.CreateCompileUnit(LangTag, FileName, Directory, - version_string); + DICompileUnit NewCU = DebugFactory.CreateCompileUnit(LangTag, FileName, + Directory, + version_string, isMain); + CU = NewCU.getGV(); + return NewCU; } /* LLVM LOCAL end (ENTIRE FILE!) */ Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.h?rev=63401&r1=63400&r2=63401&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-debug.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-debug.h Fri Jan 30 12:21:04 2009 @@ -59,7 +59,7 @@ const char *PrevFullPath; // Previous location file encountered. int PrevLineNo; // Previous location line# encountered. BasicBlock *PrevBB; // Last basic block encountered. - DICompileUnit MainCompileUnit; + std::map CUCache; std::map TypeCache; // Cache of previously constructed // Types. @@ -125,8 +125,9 @@ /// createVarinatType - Create variant type or return MainTy. DIType createVariantType(tree_node *type, DIType MainTy); - /// createCompileUnit - Create a new compile unit. - DICompileUnit createCompileUnit(const std::string &FullPath); + /// getOrCreateCompileUnit - Create a new compile unit. + DICompileUnit getOrCreateCompileUnit(const char *FullPath, + bool isMain = false); /// findRegion - Find tree_node N's region. DIDescriptor findRegion(tree_node *n); From ggreif at gmail.com Fri Jan 30 12:21:13 2009 From: ggreif at gmail.com (Gabor Greif) Date: Fri, 30 Jan 2009 18:21:13 -0000 Subject: [llvm-commits] [llvm] r63402 - /llvm/trunk/lib/Transforms/Utils/Local.cpp Message-ID: <200901301821.n0UILD3k008516@zion.cs.uiuc.edu> Author: ggreif Date: Fri Jan 30 12:21:13 2009 New Revision: 63402 URL: http://llvm.org/viewvc/llvm-project?rev=63402&view=rev Log: use precise getters Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=63402&r1=63401&r2=63402&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Fri Jan 30 12:21:13 2009 @@ -38,8 +38,8 @@ // Branch - See if we are conditional jumping on constant if (BranchInst *BI = dyn_cast(T)) { if (BI->isUnconditional()) return false; // Can't optimize uncond branch - BasicBlock *Dest1 = cast(BI->getOperand(0)); - BasicBlock *Dest2 = cast(BI->getOperand(1)); + BasicBlock *Dest1 = BI->getSuccessor(0); + BasicBlock *Dest2 = BI->getSuccessor(1); if (ConstantInt *Cond = dyn_cast(BI->getCondition())) { // Are we branching on constant? From ggreif at gmail.com Fri Jan 30 12:27:22 2009 From: ggreif at gmail.com (Gabor Greif) Date: Fri, 30 Jan 2009 18:27:22 -0000 Subject: [llvm-commits] [llvm] r63403 - /llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Message-ID: <200901301827.n0UIRM9s008954@zion.cs.uiuc.edu> Author: ggreif Date: Fri Jan 30 12:27:21 2009 New Revision: 63403 URL: http://llvm.org/viewvc/llvm-project?rev=63403&view=rev Log: use precise getters Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=63403&r1=63402&r2=63403&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original) +++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Fri Jan 30 12:27:21 2009 @@ -811,11 +811,14 @@ } break; case Instruction::Br: - Code = bitc::FUNC_CODE_INST_BR; - Vals.push_back(VE.getValueID(I.getOperand(0))); - if (cast(I).isConditional()) { - Vals.push_back(VE.getValueID(I.getOperand(1))); - Vals.push_back(VE.getValueID(I.getOperand(2))); + { + Code = bitc::FUNC_CODE_INST_BR; + BranchInst &II(cast(I)); + Vals.push_back(VE.getValueID(II.getSuccessor(0))); + if (II.isConditional()) { + Vals.push_back(VE.getValueID(II.getSuccessor(1))); + Vals.push_back(VE.getValueID(II.getCondition())); + } } break; case Instruction::Switch: From mrs at apple.com Fri Jan 30 12:41:15 2009 From: mrs at apple.com (Mike Stump) Date: Fri, 30 Jan 2009 10:41:15 -0800 Subject: [llvm-commits] [llvm] r63384 - in /llvm/trunk: include/llvm/Support/CommandLine.h lib/Support/CommandLine.cpp In-Reply-To: <5F0660E8-D815-494B-A7F3-A6B9B16DD4E3@apple.com> References: <200901300819.n0U8JkUt008727@zion.cs.uiuc.edu> <5F0660E8-D815-494B-A7F3-A6B9B16DD4E3@apple.com> Message-ID: <13E450F0-4D23-43FF-B876-4DBBF8807BC3@apple.com> On Jan 30, 2009, at 10:00 AM, Chris Lattner wrote: > Please revert this patch in the meantime, thanks! Any objection to just fixing it? From dalej at apple.com Fri Jan 30 12:51:38 2009 From: dalej at apple.com (Dale Johannesen) Date: Fri, 30 Jan 2009 10:51:38 -0800 Subject: [llvm-commits] [llvm] r63359 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp In-Reply-To: References: <200901300134.n0U1YM1H028081@zion.cs.uiuc.edu> <096363F0-D686-47CD-AFDE-AC0D76958E22@apple.com> <5A0CC7FC-7F52-45BE-9412-8552034F191C@apple.com> Message-ID: On Jan 30, 2009, at 10:08 AMPST, Chris Lattner wrote: > > On Jan 30, 2009, at 10:00 AM, Dale Johannesen wrote: > >> >> On Jan 29, 2009, at 6:22 PMPST, Chris Lattner wrote: >> >>> On Jan 29, 2009, at 5:47 PM, Dale Johannesen wrote: >>>>> Thanks Dale! One issue: instead of "getCurDebugLoc()" and friends >>>>> being on the SelectionDAG, please move them to do the dag builder >>>>> class. >>>> >>>> What do you mean? I had it in SelectionDAGLowering originally, >>>> which >>>> looked right to me, but it looked like there wasn't an easy way to >>>> get >>>> there from everywhere that was calling getNode. >>> >>> What places needed it other than SDBuilder? >> >> I'm thinking of the target-dependent parts of that like >> TargetLowering::LowerCallTo; there are several in the various target >> files. Doesn't seem to be an easy way to get the >> SelectionDAGLowering object from there. (btw, I asked Evan's >> opinion >> of where this should go before doing it this way; he didn't care.) > > While annoying, I think it would be better to pass the location to use > into LowerCallTo. Putting it in SelectionDAG makes it so that non- > builder clients could accidentally use it instead of using a proper > source location. OK, I'll aim at that. Doing that for all the TargetLowering hooks together involves doing Legalize, so that will take a little while. From monping at apple.com Fri Jan 30 12:52:26 2009 From: monping at apple.com (Mon Ping Wang) Date: Fri, 30 Jan 2009 10:52:26 -0800 Subject: [llvm-commits] Patch: avoid legalization assert In-Reply-To: <200901301611.36038.baldrick@free.fr> References: <200901301611.36038.baldrick@free.fr> Message-ID: Hi Duncan, Yes, you have it right. In general, its better to run vector code using the SSE instructions and avoid using MMX instructions. By using -disable-mmx, we disable MMX registers and make i64 to no longer be a legal type but leave v2i64 as a legal SSE2+ type. Since X86 doesn't have an 64 bit divide instruction and we don't have a vector form for the library function, we end up scalarizing it and calling library routine which introduces those expression nodes with i64 and then hit the assert. It is a tricky case and it is one I wonder could happen in other cases (probably rarely) where we have library routines that uses illegal types that need be promoted. -- Mon Ping On Jan 30, 2009, at 7:11 AM, Duncan Sands wrote: > Hi Mon Ping, if I understand right the problem is that v2i64 is legal, > but i64 is not, and that when we try to scalarize this > 0x2b1d9c8: v2i64 = sdiv 0x2b1ddc8, 0x2b1dfc8 > into a pair of libcalls, we end up with expressions in terms of the > elements (i.e. of i64 type) but those types aren't legal. The > point of running llc with -disable-mmx is that there is then no > sdiv vector instruction I suppose. Hmmm, tricky :) > > Ciao, > > Duncan. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Fri Jan 30 12:54:45 2009 From: clattner at apple.com (Chris Lattner) Date: Fri, 30 Jan 2009 10:54:45 -0800 Subject: [llvm-commits] [llvm] r63384 - in /llvm/trunk: include/llvm/Support/CommandLine.h lib/Support/CommandLine.cpp In-Reply-To: <13E450F0-4D23-43FF-B876-4DBBF8807BC3@apple.com> References: <200901300819.n0U8JkUt008727@zion.cs.uiuc.edu> <5F0660E8-D815-494B-A7F3-A6B9B16DD4E3@apple.com> <13E450F0-4D23-43FF-B876-4DBBF8807BC3@apple.com> Message-ID: On Jan 30, 2009, at 10:41 AM, Mike Stump wrote: > On Jan 30, 2009, at 10:00 AM, Chris Lattner wrote: >> Please revert this patch in the meantime, thanks! > > Any objection to just fixing it? What do you mean? From isanbard at gmail.com Fri Jan 30 13:25:47 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 19:25:47 -0000 Subject: [llvm-commits] [llvm] r63411 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200901301925.n0UJPlLh011400@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 13:25:47 2009 New Revision: 63411 URL: http://llvm.org/viewvc/llvm-project?rev=63411&view=rev Log: Propagate debug loc info in SimplifyBinOpWithSameOpcodeHands. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63411&r1=63410&r2=63411&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 13:25:47 2009 @@ -1731,11 +1731,11 @@ if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { - SDValue ORNode = DAG.getNode(N->getOpcode(), - N0.getOperand(0).getValueType(), - N0.getOperand(0), N1.getOperand(0)); + SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), + N0.getOperand(0).getValueType(), + N0.getOperand(0), N1.getOperand(0)); AddToWorkList(ORNode.getNode()); - return DAG.getNode(N0.getOpcode(), VT, ORNode); + return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); } // For each of OP in SHL/SRL/SRA/AND... @@ -1745,11 +1745,12 @@ if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && N0.getOperand(1) == N1.getOperand(1)) { - SDValue ORNode = DAG.getNode(N->getOpcode(), - N0.getOperand(0).getValueType(), - N0.getOperand(0), N1.getOperand(0)); + SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), + N0.getOperand(0).getValueType(), + N0.getOperand(0), N1.getOperand(0)); AddToWorkList(ORNode.getNode()); - return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); + return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, + ORNode, N0.getOperand(1)); } return SDValue(); From isanbard at gmail.com Fri Jan 30 14:43:18 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 20:43:18 -0000 Subject: [llvm-commits] [llvm] r63416 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200901302043.n0UKhISa014140@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 14:43:18 2009 New Revision: 63416 URL: http://llvm.org/viewvc/llvm-project?rev=63416&view=rev Log: Propagate debug loc info for AND. Also clean up some comments. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63416&r1=63415&r2=63416&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 14:43:18 2009 @@ -1802,8 +1802,8 @@ APInt Mask = ~N1C->getAPIntValue(); Mask.trunc(N0Op0.getValueSizeInBits()); if (DAG.MaskedValueIsZero(N0Op0, Mask)) { - SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), - N0Op0); + SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), + N0.getValueType(), N0Op0); // Replace uses of the AND with uses of the Zero extend node. CombineTo(N, Zext); @@ -1822,23 +1822,26 @@ if (LR == RR && isa(LR) && Op0 == Op1 && LL.getValueType().isInteger()) { - // fold (X == 0) & (Y == 0) -> (X|Y == 0) + // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) if (cast(LR)->isNullValue() && Op1 == ISD::SETEQ) { - SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); + SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), + LR.getValueType(), LL, RL); AddToWorkList(ORNode.getNode()); - return DAG.getSetCC(VT, ORNode, LR, Op1); + return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); } - // fold (X == -1) & (Y == -1) -> (X&Y == -1) + // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) if (cast(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { - SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); + SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), + LR.getValueType(), LL, RL); AddToWorkList(ANDNode.getNode()); - return DAG.getSetCC(VT, ANDNode, LR, Op1); + return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); } - // fold (X > -1) & (Y > -1) -> (X|Y > -1) + // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) if (cast(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { - SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); + SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), + LR.getValueType(), LL, RL); AddToWorkList(ORNode.getNode()); - return DAG.getSetCC(VT, ORNode, LR, Op1); + return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); } } // canonicalize equivalent to ll == rl @@ -1851,11 +1854,12 @@ ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); if (Result != ISD::SETCC_INVALID && (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) - return DAG.getSetCC(N0.getValueType(), LL, LR, Result); + return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), + LL, LR, Result); } } - // Simplify: and (op x...), (op y...) -> (op (and x, y)) + // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) if (N0.getOpcode() == N1.getOpcode()) { SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); if (Tmp.getNode()) return Tmp; @@ -1877,8 +1881,9 @@ BitWidth - EVT.getSizeInBits())) && ((!LegalOperations && !LN0->isVolatile()) || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { - SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), - LN0->getBasePtr(), LN0->getSrcValue(), + SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, + LN0->getChain(), LN0->getBasePtr(), + LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, LN0->isVolatile(), LN0->getAlignment()); AddToWorkList(N); @@ -1898,7 +1903,8 @@ BitWidth - EVT.getSizeInBits())) && ((!LegalOperations && !LN0->isVolatile()) || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { - SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), + SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, + LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, LN0->isVolatile(), LN0->getAlignment()); @@ -1922,11 +1928,13 @@ EVT = MVT::getIntegerVT(ActiveBits); MVT LoadedVT = LN0->getMemoryVT(); + // Do not generate loads of non-round integer types since these can // be expensive (and would be wrong if the type is not byte sized). if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { MVT PtrType = N0.getOperand(1).getValueType(); + // For big endian targets, we need to add an offset to the pointer to // load the correct bytes. For little endian systems, we merely need to // read fewer bytes from the same pointer. @@ -1935,16 +1943,18 @@ unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; unsigned Alignment = LN0->getAlignment(); SDValue NewPtr = LN0->getBasePtr(); + if (TLI.isBigEndian()) { - NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, - DAG.getConstant(PtrOff, PtrType)); + NewPtr = DAG.getNode(ISD::ADD, DebugLoc::getUnknownLoc(), PtrType, + NewPtr, DAG.getConstant(PtrOff, PtrType)); Alignment = MinAlign(Alignment, PtrOff); } + AddToWorkList(NewPtr.getNode()); SDValue Load = - DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, - LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, - LN0->isVolatile(), Alignment); + DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(), + NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(), + EVT, LN0->isVolatile(), Alignment); AddToWorkList(N); CombineTo(N0.getNode(), Load, Load.getValue(1)); return SDValue(N, 0); // Return N so it doesn't get rechecked! From isanbard at gmail.com Fri Jan 30 14:50:00 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 20:50:00 -0000 Subject: [llvm-commits] [llvm] r63417 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200901302050.n0UKo01i014349@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 14:50:00 2009 New Revision: 63417 URL: http://llvm.org/viewvc/llvm-project?rev=63417&view=rev Log: Perform obvious constant arithmetic folding. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63417&r1=63416&r2=63417&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 14:50:00 2009 @@ -485,9 +485,10 @@ if (N0.getOpcode() == Opc && isa(N0.getOperand(1))) { if (isa(N1)) { // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) - SDValue OpNode = DAG.getNode(Opc, N1.getDebugLoc(), VT, - N0.getOperand(1), N1); - AddToWorkList(OpNode.getNode()); + SDValue OpNode = + DAG.FoldConstantArithmetic(Opc, VT, + cast(N0.getOperand(1)), + cast(N1)); return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); } else if (N0.hasOneUse()) { // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use @@ -501,9 +502,10 @@ if (N1.getOpcode() == Opc && isa(N1.getOperand(1))) { if (isa(N0)) { // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) - SDValue OpNode = DAG.getNode(Opc, N1.getDebugLoc(), VT, - N1.getOperand(1), N0); - AddToWorkList(OpNode.getNode()); + SDValue OpNode = + DAG.FoldConstantArithmetic(Opc, VT, + cast(N1.getOperand(1)), + cast(N0)); return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); } else if (N1.hasOneUse()) { // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use From isanbard at gmail.com Fri Jan 30 14:59:35 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 20:59:35 -0000 Subject: [llvm-commits] [llvm] r63419 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200901302059.n0UKxZ3r014715@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 14:59:34 2009 New Revision: 63419 URL: http://llvm.org/viewvc/llvm-project?rev=63419&view=rev Log: Propagate debug loc info for OR. Also clean up some comments. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63419&r1=63418&r2=63419&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 14:59:34 2009 @@ -1989,7 +1989,7 @@ return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); // canonicalize constant to RHS if (N0C && !N1C) - return DAG.getNode(ISD::OR, VT, N1, N0); + return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); // fold (or x, 0) -> x if (N1C && N1C->isNullValue()) return N0; @@ -2007,10 +2007,10 @@ if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && isa(N0.getOperand(1))) { ConstantSDNode *C1 = cast(N0.getOperand(1)); - return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), - N1), - DAG.getConstant(N1C->getAPIntValue() | - C1->getAPIntValue(), VT)); + return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, + DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, + N0.getOperand(0), N1), + DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); } // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ @@ -2019,21 +2019,23 @@ if (LR == RR && isa(LR) && Op0 == Op1 && LL.getValueType().isInteger()) { - // fold (X != 0) | (Y != 0) -> (X|Y != 0) - // fold (X < 0) | (Y < 0) -> (X|Y < 0) + // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) + // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) if (cast(LR)->isNullValue() && (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { - SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); + SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), + LR.getValueType(), LL, RL); AddToWorkList(ORNode.getNode()); - return DAG.getSetCC(VT, ORNode, LR, Op1); + return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); } - // fold (X != -1) | (Y != -1) -> (X&Y != -1) - // fold (X > -1) | (Y > -1) -> (X&Y > -1) + // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) + // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) if (cast(LR)->isAllOnesValue() && (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { - SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); + SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), + LR.getValueType(), LL, RL); AddToWorkList(ANDNode.getNode()); - return DAG.getSetCC(VT, ANDNode, LR, Op1); + return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); } } // canonicalize equivalent to ll == rl @@ -2046,17 +2048,18 @@ ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); if (Result != ISD::SETCC_INVALID && (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) - return DAG.getSetCC(N0.getValueType(), LL, LR, Result); + return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), + LL, LR, Result); } } - // Simplify: or (op x...), (op y...) -> (op (or x, y)) + // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) if (N0.getOpcode() == N1.getOpcode()) { SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); if (Tmp.getNode()) return Tmp; } - // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. + // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND && N0.getOperand(1).getOpcode() == ISD::Constant && @@ -2072,12 +2075,13 @@ if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { - SDValue X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); - return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); + SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, + N0.getOperand(0), N1.getOperand(0)); + return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, + DAG.getConstant(LHSMask | RHSMask, VT)); } } - // See if this is some rotate idiom. if (SDNode *Rot = MatchRotate(N0, N1)) return SDValue(Rot, 0); @@ -2085,7 +2089,6 @@ return SDValue(); } - /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { if (Op.getOpcode() == ISD::AND) { @@ -2101,10 +2104,10 @@ Shift = Op; return true; } + return false; } - // MatchRotate - Handle an 'or' of two operands. If this is one of the many // idioms for rotate, and if the target supports rotation instructions, generate // a rot[lr]. From isanbard at gmail.com Fri Jan 30 15:14:50 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 21:14:50 -0000 Subject: [llvm-commits] [llvm] r63420 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200901302114.n0ULEooe015259@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 15:14:50 2009 New Revision: 63420 URL: http://llvm.org/viewvc/llvm-project?rev=63420&view=rev Log: Propagate debug loc info for XOR and MatchRotate. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63420&r1=63419&r2=63420&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 15:14:50 2009 @@ -214,7 +214,7 @@ SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); SDValue BuildSDIV(SDNode *N); SDValue BuildUDIV(SDNode *N); - SDNode *MatchRotate(SDValue LHS, SDValue RHS); + SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); SDValue ReduceLoadWidth(SDNode *N); SDValue GetDemandedBits(SDValue V, const APInt &Mask); @@ -2083,7 +2083,7 @@ } // See if this is some rotate idiom. - if (SDNode *Rot = MatchRotate(N0, N1)) + if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) return SDValue(Rot, 0); return SDValue(); @@ -2111,7 +2111,7 @@ // MatchRotate - Handle an 'or' of two operands. If this is one of the many // idioms for rotate, and if the target supports rotation instructions, generate // a rot[lr]. -SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) { +SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { // Must be a legal type. Expanded 'n promoted things won't work with rotates. MVT VT = LHS.getValueType(); if (!TLI.isTypeLegal(VT)) return 0; @@ -2161,9 +2161,9 @@ SDValue Rot; if (HasROTL) - Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); + Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); else - Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); + Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); // If there is an AND of either shifted operand, apply it to the result. if (LHSMask.getNode() || RHSMask.getNode()) { @@ -2178,7 +2178,7 @@ Mask &= cast(RHSMask)->getAPIntValue() | LHSBits; } - Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); + Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); } return Rot.getNode(); @@ -2197,9 +2197,11 @@ dyn_cast(RHSShiftAmt.getOperand(0))) { if (SUBC->getAPIntValue() == OpSizeInBits) { if (HasROTL) - return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); + return DAG.getNode(ISD::ROTL, DL, VT, + LHSShiftArg, LHSShiftAmt).getNode(); else - return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); + return DAG.getNode(ISD::ROTR, DL, VT, + LHSShiftArg, RHSShiftAmt).getNode(); } } } @@ -2212,9 +2214,11 @@ dyn_cast(LHSShiftAmt.getOperand(0))) { if (SUBC->getAPIntValue() == OpSizeInBits) { if (HasROTR) - return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); + return DAG.getNode(ISD::ROTR, DL, VT, + LHSShiftArg, RHSShiftAmt).getNode(); else - return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); + return DAG.getNode(ISD::ROTL, DL, VT, + LHSShiftArg, LHSShiftAmt).getNode(); } } } @@ -2239,7 +2243,8 @@ if (ConstantSDNode *SUBC = dyn_cast(RExtOp0.getOperand(0))) { if (SUBC->getAPIntValue() == OpSizeInBits) { - return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, VT, LHSShiftArg, + return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, + LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); } } @@ -2252,7 +2257,8 @@ if (ConstantSDNode *SUBC = dyn_cast(LExtOp0.getOperand(0))) { if (SUBC->getAPIntValue() == OpSizeInBits) { - return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, VT, LHSShiftArg, + return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, + LHSShiftArg, HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); } } @@ -2262,7 +2268,6 @@ return 0; } - SDValue DAGCombiner::visitXOR(SDNode *N) { SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); @@ -2290,7 +2295,7 @@ return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); // canonicalize constant to RHS if (N0C && !N1C) - return DAG.getNode(ISD::XOR, VT, N1, N0); + return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); // fold (xor x, 0) -> x if (N1C && N1C->isNullValue()) return N0; @@ -2311,9 +2316,9 @@ assert(0 && "Unhandled SetCC Equivalent!"); abort(); case ISD::SETCC: - return DAG.getSetCC(VT, LHS, RHS, NotCC); + return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); case ISD::SELECT_CC: - return DAG.getSelectCC(LHS, RHS, N0.getOperand(2), + return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), N0.getOperand(3), NotCC); } } @@ -2324,47 +2329,47 @@ N0.getNode()->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ SDValue V = N0.getOperand(0); - V = DAG.getNode(ISD::XOR, V.getValueType(), V, + V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, DAG.getConstant(1, V.getValueType())); AddToWorkList(V.getNode()); - return DAG.getNode(ISD::ZERO_EXTEND, VT, V); + return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); } - // fold !(x or y) -> (!x and !y) iff x or y are setcc + // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; - LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS - RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS + LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS + RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); - return DAG.getNode(NewOpcode, VT, LHS, RHS); + return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); } } - // fold !(x or y) -> (!x and !y) iff x or y are constants + // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants if (N1C && N1C->isAllOnesValue() && (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); if (isa(RHS) || isa(LHS)) { unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; - LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS - RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS + LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS + RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); - return DAG.getNode(NewOpcode, VT, LHS, RHS); + return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); } } - // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) + // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) if (N1C && N0.getOpcode() == ISD::XOR) { ConstantSDNode *N00C = dyn_cast(N0.getOperand(0)); ConstantSDNode *N01C = dyn_cast(N0.getOperand(1)); if (N00C) - return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), - DAG.getConstant(N1C->getAPIntValue()^ + return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), + DAG.getConstant(N1C->getAPIntValue() ^ N00C->getAPIntValue(), VT)); if (N01C) - return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), - DAG.getConstant(N1C->getAPIntValue()^ + return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), + DAG.getConstant(N1C->getAPIntValue() ^ N01C->getAPIntValue(), VT)); } // fold (xor x, x) -> 0 @@ -2375,7 +2380,8 @@ // Produce a vector of zeros. SDValue El = DAG.getConstant(0, VT.getVectorElementType()); std::vector Ops(VT.getVectorNumElements(), El); - return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); + return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, + &Ops[0], Ops.size()); } } From kremenek at apple.com Fri Jan 30 15:36:57 2009 From: kremenek at apple.com (Ted Kremenek) Date: Fri, 30 Jan 2009 21:36:57 -0000 Subject: [llvm-commits] [llvm] r63422 - /llvm/tags/checker/checker-0.147/ Message-ID: <200901302136.n0ULavYY015947@zion.cs.uiuc.edu> Author: kremenek Date: Fri Jan 30 15:36:57 2009 New Revision: 63422 URL: http://llvm.org/viewvc/llvm-project?rev=63422&view=rev Log: Tagging checker-0.147. Added: llvm/tags/checker/checker-0.147/ - copied from r63421, llvm/trunk/ From isanbard at gmail.com Fri Jan 30 15:37:18 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 21:37:18 -0000 Subject: [llvm-commits] [llvm] r63424 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200901302137.n0ULbIng015982@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 15:37:17 2009 New Revision: 63424 URL: http://llvm.org/viewvc/llvm-project?rev=63424&view=rev Log: Propagate debug loc info for Shifts. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63424&r1=63423&r2=63424&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 15:37:17 2009 @@ -2430,13 +2430,12 @@ // We require the RHS of the binop to be a constant as well. ConstantSDNode *BinOpCst = dyn_cast(LHS->getOperand(1)); if (!BinOpCst) return SDValue(); - - - // FIXME: disable this for unless the input to the binop is a shift by a - // constant. If it is not a shift, it pessimizes some common cases like: + + // FIXME: disable this unless the input to the binop is a shift by a constant. + // If it is not a shift, it pessimizes some common cases like: // - //void foo(int *X, int i) { X[i & 1235] = 1; } - //int bar(int *X, int i) { return X[i & 255]; } + // void foo(int *X, int i) { X[i & 1235] = 1; } + // int bar(int *X, int i) { return X[i & 255]; } SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); if ((BinOpLHSVal->getOpcode() != ISD::SHL && BinOpLHSVal->getOpcode() != ISD::SRA && @@ -2446,11 +2445,10 @@ MVT VT = N->getValueType(0); - // If this is a signed shift right, and the high bit is modified - // by the logical operation, do not perform the transformation. - // The highBitSet boolean indicates the value of the high bit of - // the constant which would cause it to be modified for this - // operation. + // If this is a signed shift right, and the high bit is modified by the + // logical operation, do not perform the transformation. The highBitSet + // boolean indicates the value of the high bit of the constant which would + // cause it to be modified for this operation. if (N->getOpcode() == ISD::SRA) { bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); if (BinOpRHSSignSet != HighBitSet) @@ -2458,18 +2456,18 @@ } // Fold the constants, shifting the binop RHS by the shift amount. - SDValue NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), - LHS->getOperand(1), N->getOperand(1)); + SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), + N->getValueType(0), + LHS->getOperand(1), N->getOperand(1)); // Create the new shift. - SDValue NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), - N->getOperand(1)); + SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), + VT, LHS->getOperand(0), N->getOperand(1)); // Create the new binop. - return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); + return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); } - SDValue DAGCombiner::visitSHL(SDNode *N) { SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); @@ -2486,7 +2484,7 @@ return N0; // fold (shl x, c >= size(x)) -> undef if (N1C && N1C->getZExtValue() >= OpSizeInBits) - return DAG.getNode(ISD::UNDEF, VT); + return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT); // fold (shl x, 0) -> x if (N1C && N1C->isNullValue()) return N0; @@ -2505,7 +2503,7 @@ SDValue N100 = N1.getOperand(0).getOperand(0); uint64_t TruncC = TruncVT.getIntegerVTBitMask() & N101C->getZExtValue(); - return DAG.getNode(ISD::SHL, VT, N0, + return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, DAG.getNode(ISD::AND, TruncVT, DAG.getNode(ISD::TRUNCATE, TruncVT, N100), DAG.getConstant(TruncC, TruncVT))); @@ -2514,34 +2512,35 @@ if (N1C && SimplifyDemandedBits(SDValue(N, 0))) return SDValue(N, 0); - // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) + + // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1).getOpcode() == ISD::Constant) { uint64_t c1 = cast(N0.getOperand(1))->getZExtValue(); uint64_t c2 = N1C->getZExtValue(); if (c1 + c2 > OpSizeInBits) return DAG.getConstant(0, VT); - return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), + return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), DAG.getConstant(c1 + c2, N1.getValueType())); } - // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or - // (srl (and x, -1 << c1), c1-c2) + // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or + // (srl (and x, (shl -1, c1)), (sub c1, c2)) if (N1C && N0.getOpcode() == ISD::SRL && N0.getOperand(1).getOpcode() == ISD::Constant) { uint64_t c1 = cast(N0.getOperand(1))->getZExtValue(); uint64_t c2 = N1C->getZExtValue(); - SDValue Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), - DAG.getConstant(~0ULL << c1, VT)); + SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, N0.getOperand(0), + DAG.getConstant(~0ULL << c1, VT)); if (c2 > c1) - return DAG.getNode(ISD::SHL, VT, Mask, + return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, DAG.getConstant(c2-c1, N1.getValueType())); else - return DAG.getNode(ISD::SRL, VT, Mask, + return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, DAG.getConstant(c1-c2, N1.getValueType())); } - // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) + // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) - return DAG.getNode(ISD::AND, VT, N0.getOperand(0), + return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); @@ -2554,7 +2553,7 @@ ConstantSDNode *N1C = dyn_cast(N1); MVT VT = N0.getValueType(); - // fold (sra c1, c2) -> c1>>c2 + // fold (sra c1, c2) -> (sra c1, c2) if (N0C && N1C) return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); // fold (sra 0, x) -> 0 @@ -2563,9 +2562,9 @@ // fold (sra -1, x) -> -1 if (N0C && N0C->isAllOnesValue()) return N0; - // fold (sra x, c >= size(x)) -> undef + // fold (sra x, (setge c, size(x))) -> undef if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) - return DAG.getNode(ISD::UNDEF, VT); + return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT); // fold (sra x, 0) -> x if (N1C && N1C->isNullValue()) return N0; @@ -2575,22 +2574,22 @@ unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); MVT EVT = MVT::getIntegerVT(LowBits); if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) - return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), - DAG.getValueType(EVT)); + return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, + N0.getOperand(0), DAG.getValueType(EVT)); } - // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) + // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) if (N1C && N0.getOpcode() == ISD::SRA) { if (ConstantSDNode *C1 = dyn_cast(N0.getOperand(1))) { unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; - return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), + return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), DAG.getConstant(Sum, N1C->getValueType(0))); } } - // fold sra (shl X, m), result_size - n - // -> (sign_extend (trunc (shl X, result_size - n - m))) for + // fold (sra (shl X, m), (sub result_size, n)) + // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for // result_size - n != m. // If truncate is free for the target sext(shl) is likely to result in better // code. @@ -2615,9 +2614,12 @@ TLI.isTruncateFree(VT, TruncVT)) { SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); - SDValue Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); - SDValue Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); - return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc); + SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, + N0.getOperand(0), Amt); + SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, + Shift); + return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), + N->getValueType(0), Trunc); } } } @@ -2633,8 +2635,9 @@ SDValue N100 = N1.getOperand(0).getOperand(0); uint64_t TruncC = TruncVT.getIntegerVTBitMask() & N101C->getZExtValue(); - return DAG.getNode(ISD::SRA, VT, N0, - DAG.getNode(ISD::AND, TruncVT, + return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, + DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(), + TruncVT, DAG.getNode(ISD::TRUNCATE, TruncVT, N100), DAG.getConstant(TruncC, TruncVT))); } @@ -2647,7 +2650,7 @@ // If the sign bit is known to be zero, switch this to a SRL. if (DAG.SignBitIsZero(N0)) - return DAG.getNode(ISD::SRL, VT, N0, N1); + return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); } @@ -2668,7 +2671,7 @@ return N0; // fold (srl x, c >= size(x)) -> undef if (N1C && N1C->getZExtValue() >= OpSizeInBits) - return DAG.getNode(ISD::UNDEF, VT); + return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT); // fold (srl x, 0) -> x if (N1C && N1C->isNullValue()) return N0; @@ -2677,14 +2680,14 @@ APInt::getAllOnesValue(OpSizeInBits))) return DAG.getConstant(0, VT); - // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) + // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) if (N1C && N0.getOpcode() == ISD::SRL && N0.getOperand(1).getOpcode() == ISD::Constant) { uint64_t c1 = cast(N0.getOperand(1))->getZExtValue(); uint64_t c2 = N1C->getZExtValue(); if (c1 + c2 > OpSizeInBits) return DAG.getConstant(0, VT); - return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), + return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), DAG.getConstant(c1 + c2, N1.getValueType())); } @@ -2693,18 +2696,19 @@ // Shifting in all undef bits? MVT SmallVT = N0.getOperand(0).getValueType(); if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) - return DAG.getNode(ISD::UNDEF, VT); + return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT); - SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); + SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, + N0.getOperand(0), N1); AddToWorkList(SmallShift.getNode()); - return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); + return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); } // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign // bit, which is unmodified by sra. - if (N1C && N1C->getZExtValue()+1 == VT.getSizeInBits()) { + if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { if (N0.getOpcode() == ISD::SRA) - return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); + return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); } // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). @@ -2724,19 +2728,22 @@ if (UnknownBits == 0) return DAG.getConstant(1, VT); // Otherwise, check to see if there is exactly one bit input to the ctlz. - if ((UnknownBits & (UnknownBits-1)) == 0) { + if ((UnknownBits & (UnknownBits - 1)) == 0) { // Okay, we know that only that the single bit specified by UnknownBits - // could be set on input to the CTLZ node. If this bit is set, the SRL - // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair - // to an SRL,XOR pair, which is likely to simplify more. + // could be set on input to the CTLZ node. If this bit is set, the SRL + // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair + // to an SRL/XOR pair, which is likely to simplify more. unsigned ShAmt = UnknownBits.countTrailingZeros(); SDValue Op = N0.getOperand(0); + if (ShAmt) { - Op = DAG.getNode(ISD::SRL, VT, Op, + Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); AddToWorkList(Op.getNode()); } - return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); + + return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, + Op, DAG.getConstant(1, VT)); } } @@ -2751,8 +2758,9 @@ SDValue N100 = N1.getOperand(0).getOperand(0); uint64_t TruncC = TruncVT.getIntegerVTBitMask() & N101C->getZExtValue(); - return DAG.getNode(ISD::SRL, VT, N0, - DAG.getNode(ISD::AND, TruncVT, + return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, + DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(), + TruncVT, DAG.getNode(ISD::TRUNCATE, TruncVT, N100), DAG.getConstant(TruncC, TruncVT))); } From asl at math.spbu.ru Fri Jan 30 15:50:00 2009 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Fri, 30 Jan 2009 21:50:00 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63425 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Message-ID: <200901302150.n0ULo05o016401@zion.cs.uiuc.edu> Author: asl Date: Fri Jan 30 15:50:00 2009 New Revision: 63425 URL: http://llvm.org/viewvc/llvm-project?rev=63425&view=rev Log: Relax alias-aliasee typechecking code and allow different types for alias and aliasee if one can be bitcasted to another. This fixes PR3446. Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=63425&r1=63424&r2=63425&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Fri Jan 30 15:50:00 2009 @@ -869,8 +869,8 @@ handleVisibility(decl, GA); - if (V->getType() == GA->getType()) - V->replaceAllUsesWith(GA); + if (GA->getType()->canLosslesslyBitCastTo(V->getType())) + V->replaceAllUsesWith(ConstantExpr::getBitCast(GA, V->getType())); else if (!V->use_empty()) { error ("%J Alias %qD used with invalid type!", decl, decl); timevar_pop(TV_LLVM_GLOBALS); From asl at math.spbu.ru Fri Jan 30 15:50:26 2009 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Fri, 30 Jan 2009 21:50:26 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63427 - in /llvm-gcc-4.2/trunk: README.LLVM gcc/config/i386/t-linux64 gcc/config/rs6000/t-linux64 Message-ID: <200901302150.n0ULoQWW016450@zion.cs.uiuc.edu> Author: asl Date: Fri Jan 30 15:50:25 2009 New Revision: 63427 URL: http://llvm.org/viewvc/llvm-project?rev=63427&view=rev Log: Make selection of library dir layout automatically during configure (afair, patch provided by Andrew Pinski). Drop the chunk from the documentation about manual layout selection. Modified: llvm-gcc-4.2/trunk/README.LLVM llvm-gcc-4.2/trunk/gcc/config/i386/t-linux64 llvm-gcc-4.2/trunk/gcc/config/rs6000/t-linux64 Modified: llvm-gcc-4.2/trunk/README.LLVM URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/README.LLVM?rev=63427&r1=63426&r2=63427&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/README.LLVM (original) +++ llvm-gcc-4.2/trunk/README.LLVM Fri Jan 30 15:50:25 2009 @@ -57,41 +57,6 @@ //===----------------------- X86-64/AMD-64/EM64-T for any OS other than Darwin/Mac OS X: -If you want to build multilib-enabled llvm-gcc (so, it will be able to generate -32 and 64 bit executables) you need to consider your system default lib directory -layout. - -Usually, your system uses one of these layouts: - -I. /usr/lib => 32 bit libraries (also in /usr/lib32) - /usr/lib64 => 64 bit libraries - -You're lucky and don't need to do anything, just proceed to usual configure -steps. - -II. /usr/lib => 64 bit libraries (also in /usr/lib64) - /usr/lib32 => 32 bit libraries - -You need to apply the following patch: - -<==cut==> ---- gcc/config/i386/t-linux64 -+++ gcc/config/i386/t-linux64 -@@ -6,7 +6,7 @@ SHLIB_MAPFILES = $(srcdir)/libgcc-std.ver \ - - MULTILIB_OPTIONS = m64/m32 - MULTILIB_DIRNAMES = 64 32 --MULTILIB_OSDIRNAMES = ../lib64 ../lib -+MULTILIB_OSDIRNAMES = ../lib64 ../lib32 - - LIBGCC = stmp-multilib - INSTALL_LIBGCC = install-multilib -<==cut==> - -Note, that usually you don't notice such patching with your native gcc, since -it's done automatically by your favourite system package manager. Maybe we'll -add some layout detection routine in the future. - If you want just pure 64 bit compiler, configure with --disable-multilib. //===----------------------- Modified: llvm-gcc-4.2/trunk/gcc/config/i386/t-linux64 URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/t-linux64?rev=63427&r1=63426&r2=63427&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/t-linux64 (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/t-linux64 Fri Jan 30 15:50:25 2009 @@ -4,9 +4,16 @@ SHLIB_MAPFILES = $(srcdir)/libgcc-std.ver \ $(srcdir)/config/i386/libgcc-x86_64-glibc.ver +# On Debian, Ubuntu and other derivitive distributions, the 32bit libraries +# are found in /lib32 and /usr/lib32, /lib64 and /usr/lib64 are symlinks to +# /lib and /usr/lib, while other distributions install libraries into /lib64 +# and /usr/lib64. The LSB does not enforce the use of /lib64 and /usr/lib64, +# it doesn't tell anything about the 32bit libraries on those systems. Set +# MULTILIB_OSDIRNAMES according to what is found on the target. + MULTILIB_OPTIONS = m64/m32 MULTILIB_DIRNAMES = 64 32 -MULTILIB_OSDIRNAMES = ../lib64 ../lib +MULTILIB_OSDIRNAMES = ../lib64 $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib) LIBGCC = stmp-multilib INSTALL_LIBGCC = install-multilib Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/t-linux64 URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/t-linux64?rev=63427&r1=63426&r2=63427&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/rs6000/t-linux64 (original) +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/t-linux64 Fri Jan 30 15:50:25 2009 @@ -7,12 +7,19 @@ TARGET_LIBGCC2_CFLAGS += -mno-minimal-toc +# On Debian, Ubuntu and other derivitive distributions, the 32bit libraries +# are found in /lib32 and /usr/lib32, /lib64 and /usr/lib64 are symlinks to +# /lib and /usr/lib, while other distributions install libraries into /lib64 +# and /usr/lib64. The LSB does not enforce the use of /lib64 and /usr/lib64, +# it doesn't tell anything about the 32bit libraries on those systems. Set +# MULTILIB_OSDIRNAMES according to what is found on the target. + MULTILIB_OPTIONS = m64/m32 msoft-float MULTILIB_DIRNAMES = 64 32 nof MULTILIB_EXTRA_OPTS = fPIC mstrict-align MULTILIB_EXCEPTIONS = m64/msoft-float MULTILIB_EXCLUSIONS = m64/!m32/msoft-float -MULTILIB_OSDIRNAMES = ../lib64 ../lib nof +MULTILIB_OSDIRNAMES = ../lib64 $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib) nof MULTILIB_MATCHES = $(MULTILIB_MATCHES_FLOAT) softfp_wrap_start := '\#ifndef __powerpc64__' From baldrick at free.fr Fri Jan 30 15:52:41 2009 From: baldrick at free.fr (Duncan Sands) Date: Fri, 30 Jan 2009 22:52:41 +0100 Subject: [llvm-commits] [llvm-gcc-4.2] r63288 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <74C16BD0-1151-4DD6-8D3F-CEA8C06D2E21@apple.com> References: <200901290750.n0T7o2dO012355@zion.cs.uiuc.edu> <200901301332.57927.baldrick@free.fr> <74C16BD0-1151-4DD6-8D3F-CEA8C06D2E21@apple.com> Message-ID: <200901302252.41726.baldrick@free.fr> Hi Chris, > I completely believe you that this is possible. One random question: I > don't understand or see the code (which should theoretically be in > expr.c?) to determine this stuff for the RTL backend, do you know > where it is? I also tried to find it, and failed. I will try again (I also want to go through the lvalue alignment stuff in detail, but didn't have time yet). Ciao, Duncan. From isanbard at gmail.com Fri Jan 30 16:00:12 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 14:00:12 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63427 - in /llvm-gcc-4.2/trunk: README.LLVM gcc/config/i386/t-linux64 gcc/config/rs6000/t-linux64 In-Reply-To: <200901302150.n0ULoQWW016450@zion.cs.uiuc.edu> References: <200901302150.n0ULoQWW016450@zion.cs.uiuc.edu> Message-ID: <16e5fdf90901301400j5b588f9fp1e1629b61e7b8f84@mail.gmail.com> Hi Anton, Could you throw LLVM LOCAL tags around the t-linux64 file changes? :-) -bw On Fri, Jan 30, 2009 at 1:50 PM, Anton Korobeynikov wrote: > Author: asl > Date: Fri Jan 30 15:50:25 2009 > New Revision: 63427 > > URL: http://llvm.org/viewvc/llvm-project?rev=63427&view=rev > Log: > Make selection of library dir layout automatically during configure > (afair, patch provided by Andrew Pinski). > > Drop the chunk from the documentation about manual layout selection. > > Modified: > llvm-gcc-4.2/trunk/README.LLVM > llvm-gcc-4.2/trunk/gcc/config/i386/t-linux64 > llvm-gcc-4.2/trunk/gcc/config/rs6000/t-linux64 > > Modified: llvm-gcc-4.2/trunk/README.LLVM > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/README.LLVM?rev=63427&r1=63426&r2=63427&view=diff > > ============================================================================== > --- llvm-gcc-4.2/trunk/README.LLVM (original) > +++ llvm-gcc-4.2/trunk/README.LLVM Fri Jan 30 15:50:25 2009 > @@ -57,41 +57,6 @@ > //===----------------------- > X86-64/AMD-64/EM64-T for any OS other than Darwin/Mac OS X: > > -If you want to build multilib-enabled llvm-gcc (so, it will be able to generate > -32 and 64 bit executables) you need to consider your system default lib directory > -layout. > - > -Usually, your system uses one of these layouts: > - > -I. /usr/lib => 32 bit libraries (also in /usr/lib32) > - /usr/lib64 => 64 bit libraries > - > -You're lucky and don't need to do anything, just proceed to usual configure > -steps. > - > -II. /usr/lib => 64 bit libraries (also in /usr/lib64) > - /usr/lib32 => 32 bit libraries > - > -You need to apply the following patch: > - > -<==cut==> > ---- gcc/config/i386/t-linux64 > -+++ gcc/config/i386/t-linux64 > -@@ -6,7 +6,7 @@ SHLIB_MAPFILES = $(srcdir)/libgcc-std.ver \ > - > - MULTILIB_OPTIONS = m64/m32 > - MULTILIB_DIRNAMES = 64 32 > --MULTILIB_OSDIRNAMES = ../lib64 ../lib > -+MULTILIB_OSDIRNAMES = ../lib64 ../lib32 > - > - LIBGCC = stmp-multilib > - INSTALL_LIBGCC = install-multilib > -<==cut==> > - > -Note, that usually you don't notice such patching with your native gcc, since > -it's done automatically by your favourite system package manager. Maybe we'll > -add some layout detection routine in the future. > - > If you want just pure 64 bit compiler, configure with --disable-multilib. > > //===----------------------- > > Modified: llvm-gcc-4.2/trunk/gcc/config/i386/t-linux64 > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/t-linux64?rev=63427&r1=63426&r2=63427&view=diff > > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/config/i386/t-linux64 (original) > +++ llvm-gcc-4.2/trunk/gcc/config/i386/t-linux64 Fri Jan 30 15:50:25 2009 > @@ -4,9 +4,16 @@ > SHLIB_MAPFILES = $(srcdir)/libgcc-std.ver \ > $(srcdir)/config/i386/libgcc-x86_64-glibc.ver > > +# On Debian, Ubuntu and other derivitive distributions, the 32bit libraries > +# are found in /lib32 and /usr/lib32, /lib64 and /usr/lib64 are symlinks to > +# /lib and /usr/lib, while other distributions install libraries into /lib64 > +# and /usr/lib64. The LSB does not enforce the use of /lib64 and /usr/lib64, > +# it doesn't tell anything about the 32bit libraries on those systems. Set > +# MULTILIB_OSDIRNAMES according to what is found on the target. > + > MULTILIB_OPTIONS = m64/m32 > MULTILIB_DIRNAMES = 64 32 > -MULTILIB_OSDIRNAMES = ../lib64 ../lib > +MULTILIB_OSDIRNAMES = ../lib64 $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib) > > LIBGCC = stmp-multilib > INSTALL_LIBGCC = install-multilib > > Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/t-linux64 > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/t-linux64?rev=63427&r1=63426&r2=63427&view=diff > > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/config/rs6000/t-linux64 (original) > +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/t-linux64 Fri Jan 30 15:50:25 2009 > @@ -7,12 +7,19 @@ > > TARGET_LIBGCC2_CFLAGS += -mno-minimal-toc > > +# On Debian, Ubuntu and other derivitive distributions, the 32bit libraries > +# are found in /lib32 and /usr/lib32, /lib64 and /usr/lib64 are symlinks to > +# /lib and /usr/lib, while other distributions install libraries into /lib64 > +# and /usr/lib64. The LSB does not enforce the use of /lib64 and /usr/lib64, > +# it doesn't tell anything about the 32bit libraries on those systems. Set > +# MULTILIB_OSDIRNAMES according to what is found on the target. > + > MULTILIB_OPTIONS = m64/m32 msoft-float > MULTILIB_DIRNAMES = 64 32 nof > MULTILIB_EXTRA_OPTS = fPIC mstrict-align > MULTILIB_EXCEPTIONS = m64/msoft-float > MULTILIB_EXCLUSIONS = m64/!m32/msoft-float > -MULTILIB_OSDIRNAMES = ../lib64 ../lib nof > +MULTILIB_OSDIRNAMES = ../lib64 $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib) nof > MULTILIB_MATCHES = $(MULTILIB_MATCHES_FLOAT) > > softfp_wrap_start := '\#ifndef __powerpc64__' > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From isanbard at gmail.com Fri Jan 30 16:02:19 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 22:02:19 -0000 Subject: [llvm-commits] [llvm] r63428 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200901302202.n0UM2Jud016903@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 16:02:18 2009 New Revision: 63428 URL: http://llvm.org/viewvc/llvm-project?rev=63428&view=rev Log: - Propagate debug loc info for SELECT. - Added xform for (select X, 1, Y) and (select X, Y, 0), which was commented on, but missing. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63428&r1=63427&r2=63428&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 16:02:18 2009 @@ -2780,7 +2780,7 @@ // fold (ctlz c1) -> c2 if (isa(N0)) - return DAG.getNode(ISD::CTLZ, VT, N0); + return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); return SDValue(); } @@ -2790,7 +2790,7 @@ // fold (cttz c1) -> c2 if (isa(N0)) - return DAG.getNode(ISD::CTTZ, VT, N0); + return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); return SDValue(); } @@ -2800,7 +2800,7 @@ // fold (ctpop c1) -> c2 if (isa(N0)) - return DAG.getNode(ISD::CTPOP, VT, N0); + return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); return SDValue(); } @@ -2814,53 +2814,58 @@ MVT VT = N->getValueType(0); MVT VT0 = N0.getValueType(); - // fold select C, X, X -> X + // fold (select C, X, X) -> X if (N1 == N2) return N1; - // fold select true, X, Y -> X + // fold (select true, X, Y) -> X if (N0C && !N0C->isNullValue()) return N1; - // fold select false, X, Y -> Y + // fold (select false, X, Y) -> Y if (N0C && N0C->isNullValue()) return N2; - // fold select C, 1, X -> C | X + // fold (select C, 1, X) -> (or C, X) if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) - return DAG.getNode(ISD::OR, VT, N0, N2); - // fold select C, 0, 1 -> C ^ 1 + return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); + // fold (select C, 0, 1) -> (xor C, 1) if (VT.isInteger() && (VT0 == MVT::i1 || (VT0.isInteger() && TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { - SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); + SDValue XORNode; if (VT == VT0) - return XORNode; + return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, + N0, DAG.getConstant(1, VT0)); + XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, + N0, DAG.getConstant(1, VT0)); AddToWorkList(XORNode.getNode()); if (VT.bitsGT(VT0)) - return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); - return DAG.getNode(ISD::TRUNCATE, VT, XORNode); + return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); + return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); } - // fold select C, 0, X -> ~C & X + // fold (select C, 0, X) -> (and (not C), X) if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { SDValue NOTNode = DAG.getNOT(N0, VT); AddToWorkList(NOTNode.getNode()); return DAG.getNode(ISD::AND, VT, NOTNode, N2); } - // fold select C, X, 1 -> ~C | X + // fold (select C, X, 1) -> (or (not C), X) if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { - SDValue NOTNode = DAG.getNOT(N0, VT); + SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); AddToWorkList(NOTNode.getNode()); return DAG.getNode(ISD::OR, VT, NOTNode, N1); } - // fold select C, X, 0 -> C & X + // fold (select C, X, 0) -> (and C, X) if (VT == MVT::i1 && N2C && N2C->isNullValue()) - return DAG.getNode(ISD::AND, VT, N0, N1); - // fold X ? X : Y --> X ? 1 : Y --> X | Y - if (VT == MVT::i1 && N0 == N1) - return DAG.getNode(ISD::OR, VT, N0, N2); - // fold X ? Y : X --> X ? Y : 0 --> X & Y - if (VT == MVT::i1 && N0 == N2) - return DAG.getNode(ISD::AND, VT, N0, N1); + return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); + // fold (select X, X, Y) -> (or X, Y) + // fold (select X, 1, Y) -> (or X, Y) + if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) + return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); + // fold (select X, Y, X) -> (and X, Y) + // fold (select X, Y, 0) -> (and X, Y) + if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) + return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); // If we can fold this based on the true/false value, do so. if (SimplifySelectOps(N, N1, N2)) @@ -2873,11 +2878,13 @@ // having to say they don't support SELECT_CC on every type the DAG knows // about, since there is no way to mark an opcode illegal at all value types if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) - return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), + return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, + N0.getOperand(0), N0.getOperand(1), N1, N2, N0.getOperand(2)); else return SimplifySelect(N0, N1, N2); } + return SDValue(); } From asl at math.spbu.ru Fri Jan 30 16:03:57 2009 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Fri, 30 Jan 2009 22:03:57 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63429 - /llvm-gcc-4.2/trunk/gcc/toplev.c Message-ID: <200901302203.n0UM3vuX016968@zion.cs.uiuc.edu> Author: asl Date: Fri Jan 30 16:03:56 2009 New Revision: 63429 URL: http://llvm.org/viewvc/llvm-project?rev=63429&view=rev Log: Disable -fverbose-asm if -emit-llvm is used: it's totally bogus there Modified: llvm-gcc-4.2/trunk/gcc/toplev.c Modified: llvm-gcc-4.2/trunk/gcc/toplev.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/toplev.c?rev=63429&r1=63428&r2=63429&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/toplev.c (original) +++ llvm-gcc-4.2/trunk/gcc/toplev.c Fri Jan 30 16:03:56 2009 @@ -1841,6 +1841,12 @@ if (flag_value_profile_transformations) flag_profile_values = 1; + /* LLVM LOCAL begin */ + /* Disable verbose_asm flag if -emit-llvm is used, it's totally bogus then */ + if (emit_llvm || emit_llvm_bc) + flag_verbose_asm = 0; + /* LLVM LOCAL end */ + /* Warn about options that are not supported on this machine. */ #ifndef INSN_SCHEDULING if (flag_schedule_insns || flag_schedule_insns_after_reload) From asl at math.spbu.ru Fri Jan 30 16:09:28 2009 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Fri, 30 Jan 2009 22:09:28 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63432 - in /llvm-gcc-4.2/trunk/gcc/config: i386/t-linux64 rs6000/t-linux64 Message-ID: <200901302209.n0UM9TaE017163@zion.cs.uiuc.edu> Author: asl Date: Fri Jan 30 16:09:28 2009 New Revision: 63432 URL: http://llvm.org/viewvc/llvm-project?rev=63432&view=rev Log: Add LLVM LOCAL stuff per Bill's request Modified: llvm-gcc-4.2/trunk/gcc/config/i386/t-linux64 llvm-gcc-4.2/trunk/gcc/config/rs6000/t-linux64 Modified: llvm-gcc-4.2/trunk/gcc/config/i386/t-linux64 URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/t-linux64?rev=63432&r1=63431&r2=63432&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/t-linux64 (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/t-linux64 Fri Jan 30 16:09:28 2009 @@ -4,16 +4,20 @@ SHLIB_MAPFILES = $(srcdir)/libgcc-std.ver \ $(srcdir)/config/i386/libgcc-x86_64-glibc.ver +# LLVM LOCAL begin mainline # On Debian, Ubuntu and other derivitive distributions, the 32bit libraries # are found in /lib32 and /usr/lib32, /lib64 and /usr/lib64 are symlinks to # /lib and /usr/lib, while other distributions install libraries into /lib64 # and /usr/lib64. The LSB does not enforce the use of /lib64 and /usr/lib64, # it doesn't tell anything about the 32bit libraries on those systems. Set # MULTILIB_OSDIRNAMES according to what is found on the target. +# LLVM LOCAL end mainline MULTILIB_OPTIONS = m64/m32 MULTILIB_DIRNAMES = 64 32 +# LLVM LOCAL begin mainline MULTILIB_OSDIRNAMES = ../lib64 $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib) +# LLVM LOCAL end mainline LIBGCC = stmp-multilib INSTALL_LIBGCC = install-multilib Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/t-linux64 URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/t-linux64?rev=63432&r1=63431&r2=63432&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/rs6000/t-linux64 (original) +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/t-linux64 Fri Jan 30 16:09:28 2009 @@ -7,19 +7,23 @@ TARGET_LIBGCC2_CFLAGS += -mno-minimal-toc +# LLVM LOCAL begin mainline # On Debian, Ubuntu and other derivitive distributions, the 32bit libraries # are found in /lib32 and /usr/lib32, /lib64 and /usr/lib64 are symlinks to # /lib and /usr/lib, while other distributions install libraries into /lib64 # and /usr/lib64. The LSB does not enforce the use of /lib64 and /usr/lib64, # it doesn't tell anything about the 32bit libraries on those systems. Set # MULTILIB_OSDIRNAMES according to what is found on the target. +# LLVM LOCAL end mainline MULTILIB_OPTIONS = m64/m32 msoft-float MULTILIB_DIRNAMES = 64 32 nof MULTILIB_EXTRA_OPTS = fPIC mstrict-align MULTILIB_EXCEPTIONS = m64/msoft-float MULTILIB_EXCLUSIONS = m64/!m32/msoft-float +# LLVM LOCAL begin mainline MULTILIB_OSDIRNAMES = ../lib64 $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib) nof +# LLVM LOCAL end mainline MULTILIB_MATCHES = $(MULTILIB_MATCHES_FLOAT) softfp_wrap_start := '\#ifndef __powerpc64__' From anton at korobeynikov.info Fri Jan 30 16:10:08 2009 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Sat, 31 Jan 2009 01:10:08 +0300 Subject: [llvm-commits] [llvm-gcc-4.2] r63427 - in /llvm-gcc-4.2/trunk: README.LLVM gcc/config/i386/t-linux64 gcc/config/rs6000/t-linux64 In-Reply-To: <16e5fdf90901301400j5b588f9fp1e1629b61e7b8f84@mail.gmail.com> References: <200901302150.n0ULoQWW016450@zion.cs.uiuc.edu> <16e5fdf90901301400j5b588f9fp1e1629b61e7b8f84@mail.gmail.com> Message-ID: Hi, Bill > Could you throw LLVM LOCAL tags around the t-linux64 file changes? :-) Done! --- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From isanbard at gmail.com Fri Jan 30 16:11:23 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 22:11:23 -0000 Subject: [llvm-commits] [llvm] r63433 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200901302211.n0UMBNuR017264@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 16:11:22 2009 New Revision: 63433 URL: http://llvm.org/viewvc/llvm-project?rev=63433&view=rev Log: DebugLoc form of getNOT(). Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63433&r1=63432&r2=63433&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Fri Jan 30 16:11:22 2009 @@ -379,6 +379,7 @@ /// getNOT - Create a bitwise NOT operation as (XOR Val, -1). SDValue getNOT(SDValue Val, MVT VT); + SDValue getNOT(DebugLoc DL, SDValue Val, MVT VT); /// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have /// a flag result (to ensure it's not CSE'd). Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63433&r1=63432&r2=63433&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Jan 30 16:11:22 2009 @@ -846,6 +846,23 @@ return getNode(ISD::XOR, VT, Val, NegOne); } +/// getNOT - Create a bitwise NOT operation as (XOR Val, -1). +/// +SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) { + SDValue NegOne; + if (VT.isVector()) { + MVT EltVT = VT.getVectorElementType(); + SDValue NegOneElt = getConstant(EltVT.getIntegerVTBitMask(), EltVT); + std::vector NegOnes(VT.getVectorNumElements(), NegOneElt); + NegOne = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), VT, + &NegOnes[0], NegOnes.size()); + } else { + NegOne = getConstant(VT.getIntegerVTBitMask(), VT); + } + + return getNode(ISD::XOR, DL, VT, Val, NegOne); +} + SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; assert((EltVT.getSizeInBits() >= 64 || From isanbard at gmail.com Fri Jan 30 16:11:49 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 14:11:49 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63427 - in /llvm-gcc-4.2/trunk: README.LLVM gcc/config/i386/t-linux64 gcc/config/rs6000/t-linux64 In-Reply-To: References: <200901302150.n0ULoQWW016450@zion.cs.uiuc.edu> <16e5fdf90901301400j5b588f9fp1e1629b61e7b8f84@mail.gmail.com> Message-ID: <16e5fdf90901301411h704dfbcbl3b4ab090bbf698b8@mail.gmail.com> On Fri, Jan 30, 2009 at 2:10 PM, Anton Korobeynikov wrote: > Hi, Bill > >> Could you throw LLVM LOCAL tags around the t-linux64 file changes? :-) > Done! > Thanks. :o) -bw From clattner at apple.com Fri Jan 30 16:14:40 2009 From: clattner at apple.com (Chris Lattner) Date: Fri, 30 Jan 2009 14:14:40 -0800 Subject: [llvm-commits] [llvm] r63433 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp In-Reply-To: <200901302211.n0UMBNuR017264@zion.cs.uiuc.edu> References: <200901302211.n0UMBNuR017264@zion.cs.uiuc.edu> Message-ID: On Jan 30, 2009, at 2:11 PM, Bill Wendling wrote: > Author: void > Date: Fri Jan 30 16:11:22 2009 > New Revision: 63433 > > URL: http://llvm.org/viewvc/llvm-project?rev=63433&view=rev > Log: > DebugLoc form of getNOT(). getNOT isn't used in many places, it might be easy enough to just update them all now and zap the old form. -Chris From isanbard at gmail.com Fri Jan 30 16:23:15 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 22:23:15 -0000 Subject: [llvm-commits] [llvm] r63434 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200901302223.n0UMNFds017623@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 16:23:15 2009 New Revision: 63434 URL: http://llvm.org/viewvc/llvm-project?rev=63434&view=rev Log: Propagate debug loc info for some of the *_EXTEND functions. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63434&r1=63433&r2=63434&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Fri Jan 30 16:23:15 2009 @@ -376,6 +376,7 @@ /// getZeroExtendInReg - Return the expression required to zero extend the Op /// value assuming it was the smaller SrcTy value. SDValue getZeroExtendInReg(SDValue Op, MVT SrcTy); + SDValue getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT SrcTy); /// getNOT - Create a bitwise NOT operation as (XOR Val, -1). SDValue getNOT(SDValue Val, MVT VT); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63434&r1=63433&r2=63434&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 16:23:15 2009 @@ -2914,7 +2914,7 @@ // Fold to a simpler select_cc if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) - return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), + return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), SCC.getOperand(0), SCC.getOperand(1), N2, N3, SCC.getOperand(2)); @@ -3006,12 +3006,13 @@ // fold (sext c1) -> c1 if (isa(N0)) - return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); + return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); // fold (sext (sext x)) -> (sext x) // fold (sext (aext x)) -> (sext x) if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) - return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); + return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, + N0.getOperand(0)); if (N0.getOpcode() == ISD::TRUNCATE) { // fold (sext (truncate (load x))) -> (sext (smaller load x)) @@ -3020,7 +3021,7 @@ if (NarrowLoad.getNode()) { if (NarrowLoad.getNode() != N0.getNode()) CombineTo(N0.getNode(), NarrowLoad); - return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); + return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, NarrowLoad); } // See if the value being truncated is already sign extended. If so, just @@ -3040,22 +3041,22 @@ // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign // bits, just sext from i32. if (NumSignBits > OpBits-MidBits) - return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); + return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); } else { // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign // bits, just truncate to i32. if (NumSignBits > OpBits-MidBits) - return DAG.getNode(ISD::TRUNCATE, VT, Op); + return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); } // fold (sext (truncate x)) -> (sextinreg x). if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())) { if (Op.getValueType().bitsLT(VT)) - Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); + Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); else if (Op.getValueType().bitsGT(VT)) - Op = DAG.getNode(ISD::TRUNCATE, VT, Op); - return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, + Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); + return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, DAG.getValueType(N0.getValueType())); } } @@ -3070,29 +3071,37 @@ DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); if (DoXform) { LoadSDNode *LN0 = cast(N0); - SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), + SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), + VT, LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), LN0->getSrcValueOffset(), N0.getValueType(), LN0->isVolatile(), LN0->getAlignment()); CombineTo(N, ExtLoad); - SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); + SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), + N0.getValueType(), ExtLoad); CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); + // Extend SetCC uses if necessary. for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { SDNode *SetCC = SetCCs[i]; SmallVector Ops; + for (unsigned j = 0; j != 2; ++j) { SDValue SOp = SetCC->getOperand(j); if (SOp == Trunc) Ops.push_back(ExtLoad); else - Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); - } + Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, DebugLoc::getUnknownLoc(), + VT, SOp)); + } + Ops.push_back(SetCC->getOperand(2)); - CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), + CombineTo(SetCC, DAG.getNode(ISD::SETCC, DebugLoc::getUnknownLoc(), + SetCC->getValueType(0), &Ops[0], Ops.size())); } + return SDValue(N, 0); // Return N so it doesn't get rechecked! } } @@ -3105,19 +3114,21 @@ MVT EVT = LN0->getMemoryVT(); if ((!LegalOperations && !LN0->isVolatile()) || TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { - SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), + SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, + LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, LN0->isVolatile(), LN0->getAlignment()); CombineTo(N, ExtLoad); CombineTo(N0.getNode(), - DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), + DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), + N0.getValueType(), ExtLoad), ExtLoad.getValue(1)); return SDValue(N, 0); // Return N so it doesn't get rechecked! } } - // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc + // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) if (N0.getOpcode() == ISD::SETCC) { SDValue SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), @@ -3129,7 +3140,7 @@ // fold (sext x) -> (zext x) if the sign bit is known zero. if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && DAG.SignBitIsZero(N0)) - return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); + return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); return SDValue(); } @@ -3140,11 +3151,12 @@ // fold (zext c1) -> c1 if (isa(N0)) - return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); + return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); // fold (zext (zext x)) -> (zext x) // fold (zext (aext x)) -> (zext x) if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) - return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); + return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, + N0.getOperand(0)); // fold (zext (truncate (load x))) -> (zext (smaller load x)) // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) @@ -3153,7 +3165,7 @@ if (NarrowLoad.getNode()) { if (NarrowLoad.getNode() != N0.getNode()) CombineTo(N0.getNode(), NarrowLoad); - return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); + return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); } } @@ -3162,11 +3174,11 @@ (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { SDValue Op = N0.getOperand(0); if (Op.getValueType().bitsLT(VT)) { - Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); + Op = DAG.getNode(ISD::ANY_EXTEND, DebugLoc::getUnknownLoc(), VT, Op); } else if (Op.getValueType().bitsGT(VT)) { - Op = DAG.getNode(ISD::TRUNCATE, VT, Op); + Op = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, Op); } - return DAG.getZeroExtendInReg(Op, N0.getValueType()); + return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType()); } // fold (zext (and (trunc x), cst)) -> (and x, cst). @@ -3175,13 +3187,14 @@ N0.getOperand(1).getOpcode() == ISD::Constant) { SDValue X = N0.getOperand(0).getOperand(0); if (X.getValueType().bitsLT(VT)) { - X = DAG.getNode(ISD::ANY_EXTEND, VT, X); + X = DAG.getNode(ISD::ANY_EXTEND, DebugLoc::getUnknownLoc(), VT, X); } else if (X.getValueType().bitsGT(VT)) { - X = DAG.getNode(ISD::TRUNCATE, VT, X); + X = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, X); } APInt Mask = cast(N0.getOperand(1))->getAPIntValue(); Mask.zext(VT.getSizeInBits()); - return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); + return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, + X, DAG.getConstant(Mask, VT)); } // fold (zext (load x)) -> (zext (truncate (zextload x))) @@ -3194,29 +3207,36 @@ DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); if (DoXform) { LoadSDNode *LN0 = cast(N0); - SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), + SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, + LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), LN0->getSrcValueOffset(), N0.getValueType(), LN0->isVolatile(), LN0->getAlignment()); CombineTo(N, ExtLoad); - SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); + SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), + N0.getValueType(), ExtLoad); CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); + // Extend SetCC uses if necessary. for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { SDNode *SetCC = SetCCs[i]; SmallVector Ops; + for (unsigned j = 0; j != 2; ++j) { SDValue SOp = SetCC->getOperand(j); if (SOp == Trunc) Ops.push_back(ExtLoad); else Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); - } + } + Ops.push_back(SetCC->getOperand(2)); - CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), + CombineTo(SetCC, DAG.getNode(ISD::SETCC, DebugLoc::getUnknownLoc(), + SetCC->getValueType(0), &Ops[0], Ops.size())); } + return SDValue(N, 0); // Return N so it doesn't get rechecked! } } @@ -3229,13 +3249,15 @@ MVT EVT = LN0->getMemoryVT(); if ((!LegalOperations && !LN0->isVolatile()) || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { - SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), + SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, + LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, LN0->isVolatile(), LN0->getAlignment()); CombineTo(N, ExtLoad); CombineTo(N0.getNode(), - DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), + DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), + ExtLoad), ExtLoad.getValue(1)); return SDValue(N, 0); // Return N so it doesn't get rechecked! } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63434&r1=63433&r2=63434&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Jan 30 16:23:15 2009 @@ -831,6 +831,14 @@ getConstant(Imm, Op.getValueType())); } +SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) { + if (Op.getValueType() == VT) return Op; + APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), + VT.getSizeInBits()); + return getNode(ISD::AND, DL, Op.getValueType(), Op, + getConstant(Imm, Op.getValueType())); +} + /// getNOT - Create a bitwise NOT operation as (XOR Val, -1). /// SDValue SelectionDAG::getNOT(SDValue Val, MVT VT) { From isanbard at gmail.com Fri Jan 30 16:27:33 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 22:27:33 -0000 Subject: [llvm-commits] [llvm] r63436 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200901302227.n0UMRX4K017785@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 16:27:33 2009 New Revision: 63436 URL: http://llvm.org/viewvc/llvm-project?rev=63436&view=rev Log: Propagate debug loc info for ANY_EXTEND. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63436&r1=63435&r2=63436&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 16:27:33 2009 @@ -3288,7 +3288,7 @@ if (N0.getOpcode() == ISD::ANY_EXTEND || N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND) - return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); + return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); // fold (aext (truncate (load x))) -> (aext (smaller load x)) // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) @@ -3297,7 +3297,7 @@ if (NarrowLoad.getNode()) { if (NarrowLoad.getNode() != N0.getNode()) CombineTo(N0.getNode(), NarrowLoad); - return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); + return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); } } @@ -3307,8 +3307,8 @@ if (TruncOp.getValueType() == VT) return TruncOp; // x iff x size == zext size. if (TruncOp.getValueType().bitsGT(VT)) - return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); - return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); + return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); + return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); } // fold (aext (and (trunc x), cst)) -> (and x, cst). @@ -3317,13 +3317,14 @@ N0.getOperand(1).getOpcode() == ISD::Constant) { SDValue X = N0.getOperand(0).getOperand(0); if (X.getValueType().bitsLT(VT)) { - X = DAG.getNode(ISD::ANY_EXTEND, VT, X); + X = DAG.getNode(ISD::ANY_EXTEND, DebugLoc::getUnknownLoc(), VT, X); } else if (X.getValueType().bitsGT(VT)) { - X = DAG.getNode(ISD::TRUNCATE, VT, X); + X = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, X); } APInt Mask = cast(N0.getOperand(1))->getAPIntValue(); Mask.zext(VT.getSizeInBits()); - return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); + return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, + X, DAG.getConstant(Mask, VT)); } // fold (aext (load x)) -> (aext (truncate (extload x))) @@ -3331,7 +3332,8 @@ ((!LegalOperations && !cast(N0)->isVolatile()) || TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { LoadSDNode *LN0 = cast(N0); - SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), + SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, + LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), LN0->getSrcValueOffset(), N0.getValueType(), @@ -3342,7 +3344,8 @@ SDValue(ExtLoad.getNode(), 1)); // If any node needs the original loaded value, recompute it. if (!LN0->use_empty()) - CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), + CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), + N0.getValueType(), ExtLoad), ExtLoad.getValue(1)); return SDValue(N, 0); // Return N so it doesn't get rechecked! } @@ -3355,14 +3358,15 @@ N0.hasOneUse()) { LoadSDNode *LN0 = cast(N0); MVT EVT = LN0->getMemoryVT(); - SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, - LN0->getChain(), LN0->getBasePtr(), + SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), + VT, LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, LN0->isVolatile(), LN0->getAlignment()); CombineTo(N, ExtLoad); CombineTo(N0.getNode(), - DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), + DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), + N0.getValueType(), ExtLoad), ExtLoad.getValue(1)); return SDValue(N, 0); // Return N so it doesn't get rechecked! } From isanbard at gmail.com Fri Jan 30 16:33:24 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 22:33:24 -0000 Subject: [llvm-commits] [llvm] r63437 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200901302233.n0UMXP5C017993@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 16:33:24 2009 New Revision: 63437 URL: http://llvm.org/viewvc/llvm-project?rev=63437&view=rev Log: Propagate debug loc info for more *_EXTEND methods. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63437&r1=63436&r2=63437&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 16:33:24 2009 @@ -3405,14 +3405,14 @@ if (ConstantSDNode *RHSC = dyn_cast(V.getOperand(1))) { // See if we can recursively simplify the LHS. unsigned Amt = RHSC->getZExtValue(); + // Watch out for shift count overflow though. if (Amt >= Mask.getBitWidth()) break; APInt NewMask = Mask << Amt; SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); - if (SimplifyLHS.getNode()) { - return DAG.getNode(ISD::SRL, V.getValueType(), + if (SimplifyLHS.getNode()) + return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), SimplifyLHS, V.getOperand(1)); - } } } return SDValue(); @@ -3465,6 +3465,7 @@ !cast(N0)->isVolatile()) { LoadSDNode *LN0 = cast(N0); MVT PtrType = N0.getOperand(1).getValueType(); + // For big endian targets, we need to adjust the offset to the pointer to // load the correct bytes. if (TLI.isBigEndian()) { @@ -3472,22 +3473,27 @@ unsigned EVTStoreBits = EVT.getStoreSizeInBits(); ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; } + uint64_t PtrOff = ShAmt / 8; unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); - SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), + SDValue NewPtr = DAG.getNode(ISD::ADD, DebugLoc::getUnknownLoc(), + PtrType, LN0->getBasePtr(), DAG.getConstant(PtrOff, PtrType)); AddToWorkList(NewPtr.getNode()); + SDValue Load = (ExtType == ISD::NON_EXTLOAD) - ? DAG.getLoad(VT, LN0->getChain(), NewPtr, + ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, LN0->isVolatile(), NewAlign) - : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, + : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, EVT, LN0->isVolatile(), NewAlign); + // Replace the old load's chain with the new load's chain. WorkListRemover DeadNodes(*this); DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), &DeadNodes); + // Return the new loaded value. return Load; } @@ -3495,7 +3501,6 @@ return SDValue(); } - SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); @@ -3506,7 +3511,7 @@ // fold (sext_in_reg c1) -> c1 if (isa(N0) || N0.getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); + return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); // If the input is already sign extended, just drop the extension. if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) @@ -3515,7 +3520,8 @@ // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && EVT.bitsLT(cast(N0.getOperand(1))->getVT())) { - return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); + return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, + N0.getOperand(0), N1); } // fold (sext_in_reg (sext x)) -> (sext x) @@ -3524,7 +3530,7 @@ if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { SDValue N00 = N0.getOperand(0); if (N00.getValueType().getSizeInBits() < EVTBits) - return DAG.getNode(ISD::SIGN_EXTEND, VT, N00, N1); + return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); } // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. @@ -3542,8 +3548,8 @@ if (NarrowLoad.getNode()) return NarrowLoad; - // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 - // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. + // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) + // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. if (N0.getOpcode() == ISD::SRL) { if (ConstantSDNode *ShAmt = dyn_cast(N0.getOperand(1))) @@ -3552,7 +3558,8 @@ // extended enough. unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) - return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); + return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, + N0.getOperand(0), N0.getOperand(1)); } } @@ -3563,7 +3570,8 @@ ((!LegalOperations && !cast(N0)->isVolatile()) || TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { LoadSDNode *LN0 = cast(N0); - SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), + SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, + LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, LN0->isVolatile(), LN0->getAlignment()); @@ -3578,7 +3586,8 @@ ((!LegalOperations && !cast(N0)->isVolatile()) || TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { LoadSDNode *LN0 = cast(N0); - SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), + SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, + LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, LN0->isVolatile(), LN0->getAlignment()); From isanbard at gmail.com Fri Jan 30 16:44:24 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 22:44:24 -0000 Subject: [llvm-commits] [llvm] r63439 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200901302244.n0UMiOuk018370@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 16:44:24 2009 New Revision: 63439 URL: http://llvm.org/viewvc/llvm-project?rev=63439&view=rev Log: Propagate debug loc info for BIT_CONVERT. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63439&r1=63438&r2=63439&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 16:44:24 2009 @@ -3607,19 +3607,20 @@ return N0; // fold (truncate c1) -> c1 if (isa(N0)) - return DAG.getNode(ISD::TRUNCATE, VT, N0); + return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); // fold (truncate (truncate x)) -> (truncate x) if (N0.getOpcode() == ISD::TRUNCATE) - return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); + return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); // fold (truncate (ext x)) -> (ext x) or (truncate x) or x if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| N0.getOpcode() == ISD::ANY_EXTEND) { if (N0.getOperand(0).getValueType().bitsLT(VT)) // if the source is smaller than the dest, we still need an extend - return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); + return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, + N0.getOperand(0)); else if (N0.getOperand(0).getValueType().bitsGT(VT)) // if the source is larger than the dest, than we just need the truncate - return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); + return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); else // if the source and dest are the same type, we can drop both the extend // and the truncate @@ -3633,7 +3634,7 @@ GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), VT.getSizeInBits())); if (Shorter.getNode()) - return DAG.getNode(ISD::TRUNCATE, VT, Shorter); + return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); // fold (truncate (load x)) -> (smaller load x) // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) @@ -3658,6 +3659,7 @@ MVT LD1VT = LD1->getValueType(0); SDNode *LD2 = getBuildPairElt(N, 1); const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); + if (ISD::isNON_EXTLoad(LD2) && LD2->hasOneUse() && // If both are volatile this would reduce the number of volatile loads. @@ -3669,12 +3671,14 @@ unsigned Align = LD->getAlignment(); unsigned NewAlign = TLI.getTargetData()-> getABITypeAlignment(VT.getTypeForMVT()); + if (NewAlign <= Align && (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) - return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), + return DAG.getLoad(VT, N->getDebugLoc(), LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), LD->getSrcValueOffset(), false, Align); } + return SDValue(); } @@ -3701,19 +3705,20 @@ MVT DestEltVT = N->getValueType(0).getVectorElementType(); assert(!DestEltVT.isVector() && "Element type of vector ValueType must not be vector!"); - if (isSimple) { + if (isSimple) return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); - } } // If the input is a constant, let getNode fold it. if (isa(N0) || isa(N0)) { - SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); + SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); if (Res.getNode() != N) return Res; } - if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) - return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); + // (conv (conv x, t1), t2) -> (conv x, t2) + if (N0.getOpcode() == ISD::BIT_CONVERT) + return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, + N0.getOperand(0)); // fold (conv (load x)) -> (load (conv*)x) // If the resultant load doesn't need a higher alignment than the original! @@ -3725,69 +3730,81 @@ unsigned Align = TLI.getTargetData()-> getABITypeAlignment(VT.getTypeForMVT()); unsigned OrigAlign = LN0->getAlignment(); + if (Align <= OrigAlign) { - SDValue Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), + SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), + LN0->getBasePtr(), LN0->getSrcValue(), LN0->getSrcValueOffset(), LN0->isVolatile(), OrigAlign); AddToWorkList(N); CombineTo(N0.getNode(), - DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), + DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), + N0.getValueType(), Load), Load.getValue(1)); return Load; } } - // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) - // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) + // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) + // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) // This often reduces constant pool loads. if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { - SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); + SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, + N0.getOperand(0)); AddToWorkList(NewConv.getNode()); APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); if (N0.getOpcode() == ISD::FNEG) - return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); + return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, + NewConv, DAG.getConstant(SignBit, VT)); assert(N0.getOpcode() == ISD::FABS); - return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); + return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, + NewConv, DAG.getConstant(~SignBit, VT)); } - // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' - // Note that we don't handle copysign(x,cst) because this can always be folded - // to an fneg or fabs. + // fold (bitconvert (fcopysign cst, x)) -> + // (or (and (bitconvert x), sign), (and cst, (not sign))) + // Note that we don't handle (copysign x, cst) because this can always be + // folded to an fneg or fabs. if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && isa(N0.getOperand(0)) && VT.isInteger() && !VT.isVector()) { unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); MVT IntXVT = MVT::getIntegerVT(OrigXWidth); if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { - SDValue X = DAG.getNode(ISD::BIT_CONVERT, IntXVT, N0.getOperand(1)); + SDValue X = DAG.getNode(ISD::BIT_CONVERT, DebugLoc::getUnknownLoc(), + IntXVT, N0.getOperand(1)); AddToWorkList(X.getNode()); // If X has a different width than the result/lhs, sext it or truncate it. unsigned VTWidth = VT.getSizeInBits(); if (OrigXWidth < VTWidth) { - X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); + X = DAG.getNode(ISD::SIGN_EXTEND, DebugLoc::getUnknownLoc(), VT, X); AddToWorkList(X.getNode()); } else if (OrigXWidth > VTWidth) { // To get the sign bit in the right place, we have to shift it right // before truncating. - X = DAG.getNode(ISD::SRL, X.getValueType(), X, + X = DAG.getNode(ISD::SRL, DebugLoc::getUnknownLoc(), + X.getValueType(), X, DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); AddToWorkList(X.getNode()); - X = DAG.getNode(ISD::TRUNCATE, VT, X); + X = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, X); AddToWorkList(X.getNode()); } APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); - X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); + X = DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(), VT, + X, DAG.getConstant(SignBit, VT)); AddToWorkList(X.getNode()); - SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); - Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); + SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, DebugLoc::getUnknownLoc(), + VT, N0.getOperand(0)); + Cst = DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(), VT, + Cst, DAG.getConstant(~SignBit, VT)); AddToWorkList(Cst.getNode()); - return DAG.getNode(ISD::OR, VT, X, Cst); + return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); } } From isanbard at gmail.com Fri Jan 30 16:53:48 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 22:53:48 -0000 Subject: [llvm-commits] [llvm] r63440 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200901302253.n0UMrmpx018698@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 16:53:48 2009 New Revision: 63440 URL: http://llvm.org/viewvc/llvm-project?rev=63440&view=rev Log: Propagate debug loc info for some FP arithmetic methods. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63440&r1=63439&r2=63440&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 16:53:48 2009 @@ -3846,7 +3846,8 @@ } MVT VT = MVT::getVectorVT(DstEltVT, BV->getValueType(0).getVectorNumElements()); - return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); + return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, + &Ops[0], Ops.size()); } // Otherwise, we're growing or shrinking the elements. To avoid having to @@ -3896,13 +3897,15 @@ } if (EltIsUndef) - Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); + Ops.push_back(DAG.getNode(ISD::UNDEF, DebugLoc::getUnknownLoc(), + DstEltVT)); else Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); } MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); - return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); + return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, + &Ops[0], Ops.size()); } // Finally, this must be the case where we are shrinking elements: each input @@ -3911,19 +3914,24 @@ unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); SmallVector Ops; + for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { for (unsigned j = 0; j != NumOutputsPerInput; ++j) - Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); + Ops.push_back(DAG.getNode(ISD::UNDEF, DebugLoc::getUnknownLoc(), + DstEltVT)); continue; } + APInt OpVal = cast(BV->getOperand(i))->getAPIntValue(); + for (unsigned j = 0; j != NumOutputsPerInput; ++j) { APInt ThisVal = APInt(OpVal).trunc(DstBitSize); Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) // Simply turn this into a SCALAR_TO_VECTOR of the new type. - return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); + return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, + Ops[0]); OpVal = OpVal.lshr(DstBitSize); } @@ -3931,10 +3939,10 @@ if (TLI.isBigEndian()) std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); } - return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); -} - + return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, + &Ops[0], Ops.size()); +} SDValue DAGCombiner::visitFADD(SDNode *N) { SDValue N0 = N->getOperand(0); @@ -3949,28 +3957,28 @@ if (FoldedVOp.getNode()) return FoldedVOp; } - // fold (fadd c1, c2) -> c1+c2 + // fold (fadd c1, c2) -> (fadd c1, c2) if (N0CFP && N1CFP && VT != MVT::ppcf128) - return DAG.getNode(ISD::FADD, VT, N0, N1); + return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); // canonicalize constant to RHS if (N0CFP && !N1CFP) - return DAG.getNode(ISD::FADD, VT, N1, N0); - // fold (A + 0) -> A + return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); + // fold (fadd A, 0) -> A if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) return N0; - // fold (A + (-B)) -> A-B + // fold (fadd A, (fneg B)) -> (fsub A, B) if (isNegatibleForFree(N1, LegalOperations) == 2) - return DAG.getNode(ISD::FSUB, VT, N0, + return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, GetNegatedExpression(N1, DAG, LegalOperations)); - // fold ((-A) + B) -> B-A + // fold (fadd (fneg A), B) -> (fsub B, A) if (isNegatibleForFree(N0, LegalOperations) == 2) - return DAG.getNode(ISD::FSUB, VT, N1, + return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, GetNegatedExpression(N0, DAG, LegalOperations)); // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && isa(N0.getOperand(1))) - return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), + return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); return SDValue(); @@ -3992,19 +4000,19 @@ // fold (fsub c1, c2) -> c1-c2 if (N0CFP && N1CFP && VT != MVT::ppcf128) return DAG.getNode(ISD::FSUB, VT, N0, N1); - // fold (A-0) -> A + // fold (fsub A, 0) -> A if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) return N0; - // fold (0-B) -> -B + // fold (fsub 0, B) -> -B if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { if (isNegatibleForFree(N1, LegalOperations)) return GetNegatedExpression(N1, DAG, LegalOperations); if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) - return DAG.getNode(ISD::FNEG, VT, N1); + return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); } - // fold (A-(-B)) -> A+B + // fold (fsub A, (fneg B)) -> (fadd A, B) if (isNegatibleForFree(N1, LegalOperations)) - return DAG.getNode(ISD::FADD, VT, N0, + return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, GetNegatedExpression(N1, DAG, LegalOperations)); return SDValue(); From isanbard at gmail.com Fri Jan 30 16:56:50 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 14:56:50 -0800 Subject: [llvm-commits] [llvm] r63433 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp In-Reply-To: References: <200901302211.n0UMBNuR017264@zion.cs.uiuc.edu> Message-ID: <16e5fdf90901301456v46e448a1vb3f2c54ed64a004b@mail.gmail.com> On Fri, Jan 30, 2009 at 2:14 PM, Chris Lattner wrote: > > On Jan 30, 2009, at 2:11 PM, Bill Wendling wrote: > >> Author: void >> Date: Fri Jan 30 16:11:22 2009 >> New Revision: 63433 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=63433&view=rev >> Log: >> DebugLoc form of getNOT(). > > getNOT isn't used in many places, it might be easy enough to just > update them all now and zap the old form. > Okay. -bw From isanbard at gmail.com Fri Jan 30 16:57:07 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 22:57:07 -0000 Subject: [llvm-commits] [llvm] r63441 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200901302257.n0UMv8NI018830@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 16:57:07 2009 New Revision: 63441 URL: http://llvm.org/viewvc/llvm-project?rev=63441&view=rev Log: Propagate debug loc info for some FP arithmetic methods. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63441&r1=63440&r2=63441&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 16:57:07 2009 @@ -4033,28 +4033,28 @@ // fold (fmul c1, c2) -> c1*c2 if (N0CFP && N1CFP && VT != MVT::ppcf128) - return DAG.getNode(ISD::FMUL, VT, N0, N1); + return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); // canonicalize constant to RHS if (N0CFP && !N1CFP) - return DAG.getNode(ISD::FMUL, VT, N1, N0); - // fold (A * 0) -> 0 + return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); + // fold (fmul A, 0) -> 0 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) return N1; // fold (fmul X, 2.0) -> (fadd X, X) if (N1CFP && N1CFP->isExactlyValue(+2.0)) - return DAG.getNode(ISD::FADD, VT, N0, N0); - // fold (fmul X, -1.0) -> (fneg X) + return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); + // fold (fmul X, (fneg 1.0)) -> (fneg X) if (N1CFP && N1CFP->isExactlyValue(-1.0)) if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) - return DAG.getNode(ISD::FNEG, VT, N0); + return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); - // -X * -Y -> X*Y + // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { // Both can be negated for free, check to see if at least one is cheaper // negated. if (LHSNeg == 2 || RHSNeg == 2) - return DAG.getNode(ISD::FMUL, VT, + return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, GetNegatedExpression(N0, DAG, LegalOperations), GetNegatedExpression(N1, DAG, LegalOperations)); } @@ -4063,7 +4063,7 @@ // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && N0.getNode()->hasOneUse() && isa(N0.getOperand(1))) - return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), + return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); return SDValue(); @@ -4084,16 +4084,16 @@ // fold (fdiv c1, c2) -> c1/c2 if (N0CFP && N1CFP && VT != MVT::ppcf128) - return DAG.getNode(ISD::FDIV, VT, N0, N1); + return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); - // -X / -Y -> X*Y + // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { // Both can be negated for free, check to see if at least one is cheaper // negated. if (LHSNeg == 2 || RHSNeg == 2) - return DAG.getNode(ISD::FDIV, VT, + return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, GetNegatedExpression(N0, DAG, LegalOperations), GetNegatedExpression(N1, DAG, LegalOperations)); } @@ -4111,7 +4111,7 @@ // fold (frem c1, c2) -> fmod(c1,c2) if (N0CFP && N1CFP && VT != MVT::ppcf128) - return DAG.getNode(ISD::FREM, VT, N0, N1); + return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); return SDValue(); } From isanbard at gmail.com Fri Jan 30 17:03:19 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 23:03:19 -0000 Subject: [llvm-commits] [llvm] r63442 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Target/X86/X86ISelLowering.cpp Message-ID: <200901302303.n0UN3JqB019029@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 17:03:19 2009 New Revision: 63442 URL: http://llvm.org/viewvc/llvm-project?rev=63442&view=rev Log: Get rid of the non-DebugLoc-ified getNOT() method. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63442&r1=63441&r2=63442&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Fri Jan 30 17:03:19 2009 @@ -379,7 +379,6 @@ SDValue getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT SrcTy); /// getNOT - Create a bitwise NOT operation as (XOR Val, -1). - SDValue getNOT(SDValue Val, MVT VT); SDValue getNOT(DebugLoc DL, SDValue Val, MVT VT); /// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63442&r1=63441&r2=63442&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 17:03:19 2009 @@ -2845,15 +2845,15 @@ } // fold (select C, 0, X) -> (and (not C), X) if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { - SDValue NOTNode = DAG.getNOT(N0, VT); + SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); AddToWorkList(NOTNode.getNode()); - return DAG.getNode(ISD::AND, VT, NOTNode, N2); + return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); } // fold (select C, X, 1) -> (or (not C), X) if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); AddToWorkList(NOTNode.getNode()); - return DAG.getNode(ISD::OR, VT, NOTNode, N1); + return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); } // fold (select C, X, 0) -> (and C, X) if (VT == MVT::i1 && N2C && N2C->isNullValue()) @@ -5739,7 +5739,7 @@ if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), N0); - SDValue NotN0 = DAG.getNOT(N0, XType); + SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); return DAG.getNode(ISD::SRL, XType, DAG.getNode(ISD::AND, XType, NegN0, NotN0), DAG.getConstant(XType.getSizeInBits()-1, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63442&r1=63441&r2=63442&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Jan 30 17:03:19 2009 @@ -6321,7 +6321,7 @@ SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); } - Op = DAG.getNOT(Op, VT); + Op = DAG.getNOT(DebugLoc::getUnknownLoc(), Op, VT); return DAG.getNode(ISD::CTPOP, VT, Op); } case ISD::CTTZ: { @@ -6330,8 +6330,10 @@ // { return 32 - nlz(~x & (x-1)); } // see also http://www.hackersdelight.org/HDcode/ntz.cc MVT VT = Op.getValueType(); - SDValue Tmp3 = DAG.getNode(ISD::AND, VT, DAG.getNOT(Op, VT), - DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); + SDValue Tmp3 = DAG.getNode(ISD::AND, VT, + DAG.getNOT(DebugLoc::getUnknownLoc(), Op, VT), + DAG.getNode(ISD::SUB, VT, Op, + DAG.getConstant(1, VT))); // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63442&r1=63441&r2=63442&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Jan 30 17:03:19 2009 @@ -841,21 +841,6 @@ /// getNOT - Create a bitwise NOT operation as (XOR Val, -1). /// -SDValue SelectionDAG::getNOT(SDValue Val, MVT VT) { - SDValue NegOne; - if (VT.isVector()) { - MVT EltVT = VT.getVectorElementType(); - SDValue NegOneElt = getConstant(EltVT.getIntegerVTBitMask(), EltVT); - std::vector NegOnes(VT.getVectorNumElements(), NegOneElt); - NegOne = getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0], NegOnes.size()); - } else - NegOne = getConstant(VT.getIntegerVTBitMask(), VT); - - return getNode(ISD::XOR, VT, Val, NegOne); -} - -/// getNOT - Create a bitwise NOT operation as (XOR Val, -1). -/// SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) { SDValue NegOne; if (VT.isVector()) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=63442&r1=63441&r2=63442&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Fri Jan 30 17:03:19 2009 @@ -1841,7 +1841,7 @@ default: assert(0 && "Unknown integer setcc!"); case ISD::SETEQ: // X == Y -> ~(X^Y) Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); - N0 = DAG.getNOT(Temp, MVT::i1); + N0 = DAG.getNOT(DebugLoc::getUnknownLoc(), Temp, MVT::i1); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; @@ -1850,28 +1850,28 @@ break; case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y case ISD::SETULT: // X X == 0 & Y == 1 --> ~X & Y - Temp = DAG.getNOT(N0, MVT::i1); + Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N0, MVT::i1); N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETLT: // X X == 1 & Y == 0 --> ~Y & X case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X - Temp = DAG.getNOT(N1, MVT::i1); + Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N1, MVT::i1); N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y - Temp = DAG.getNOT(N0, MVT::i1); + Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N0, MVT::i1); N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X - Temp = DAG.getNOT(N1, MVT::i1); + Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N1, MVT::i1); N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); break; } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=63442&r1=63441&r2=63442&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jan 30 17:03:19 2009 @@ -5280,7 +5280,7 @@ // If the logical-not of the result is required, perform that now. if (Invert) - Result = DAG.getNOT(Result, VT); + Result = DAG.getNOT(Op.getDebugLoc(), Result, VT); return Result; } From isanbard at gmail.com Fri Jan 30 17:10:18 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 23:10:18 -0000 Subject: [llvm-commits] [llvm] r63443 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200901302310.n0UNAICB019457@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 17:10:18 2009 New Revision: 63443 URL: http://llvm.org/viewvc/llvm-project?rev=63443&view=rev Log: Standardize comments about folding xforms. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63443&r1=63442&r2=63443&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 17:10:18 2009 @@ -337,23 +337,23 @@ // FIXME: determine better conditions for this xform. if (!UnsafeFPMath) return 0; - // -(A+B) -> -A - B + // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) return V; - // -(A+B) -> -B - A + // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); case ISD::FSUB: // We can't turn -(A-B) into B-A when we honor signed zeros. if (!UnsafeFPMath) return 0; - // -(A-B) -> B-A + // fold (fneg (fsub A, B)) -> (fsub B, A) return 1; case ISD::FMUL: case ISD::FDIV: if (HonorSignDependentRoundingFPMath()) return 0; - // -(X*Y) -> (-X * Y) or (X*-Y) + // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) return V; @@ -388,13 +388,13 @@ // FIXME: determine better conditions for this xform. assert(UnsafeFPMath); - // -(A+B) -> -A - B + // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), GetNegatedExpression(Op.getOperand(0), DAG, LegalOperations, Depth+1), Op.getOperand(1)); - // -(A+B) -> -B - A + // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), GetNegatedExpression(Op.getOperand(1), DAG, LegalOperations, Depth+1), @@ -403,12 +403,12 @@ // We can't turn -(A-B) into B-A when we honor signed zeros. assert(UnsafeFPMath); - // -(0-B) -> B + // fold (fneg (fsub 0, B)) -> B if (ConstantFPSDNode *N0CFP = dyn_cast(Op.getOperand(0))) if (N0CFP->getValueAPF().isZero()) return Op.getOperand(1); - // -(A-B) -> B-A + // fold (fneg (fsub A, B)) -> (fsub B, A) return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), Op.getOperand(1), Op.getOperand(0)); @@ -416,14 +416,14 @@ case ISD::FDIV: assert(!HonorSignDependentRoundingFPMath()); - // -(X*Y) -> -X * Y + // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), GetNegatedExpression(Op.getOperand(0), DAG, LegalOperations, Depth+1), Op.getOperand(1)); - // -(X*Y) -> X * -Y + // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), Op.getOperand(0), GetNegatedExpression(Op.getOperand(1), DAG, From dalej at apple.com Fri Jan 30 17:11:00 2009 From: dalej at apple.com (Dale Johannesen) Date: Fri, 30 Jan 2009 23:11:00 -0000 Subject: [llvm-commits] [llvm] r63444 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ Message-ID: <200901302311.n0UNB0VA019602@zion.cs.uiuc.edu> Author: johannes Date: Fri Jan 30 17:10:59 2009 New Revision: 63444 URL: http://llvm.org/viewvc/llvm-project?rev=63444&view=rev Log: Make LowerCallTo and LowerArguments take a DebugLoc argument. Adjust all callers and overloaded versions. Modified: llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp llvm/trunk/lib/Target/IA64/IA64ISelLowering.h llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcISelLowering.h llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=63444&r1=63443&r2=63444&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Fri Jan 30 17:10:59 2009 @@ -29,6 +29,7 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/Codegen/DebugLoc.h" #include #include #include @@ -1059,7 +1060,7 @@ /// lower the arguments for the specified function, into the specified DAG. virtual void LowerArguments(Function &F, SelectionDAG &DAG, - SmallVectorImpl& ArgValues); + SmallVectorImpl& ArgValues, DebugLoc dl); /// LowerCallTo - This hook lowers an abstract call to a function into an /// actual call. This returns a pair of operands. The first element is the @@ -1084,7 +1085,7 @@ LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, bool isVarArg, bool isInreg, unsigned CallingConv, bool isTailCall, SDValue Callee, ArgListTy &Args, - SelectionDAG &DAG); + SelectionDAG &DAG, DebugLoc dl); /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a /// memcpy. This can be used by targets to provide code sequences for cases Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63444&r1=63443&r2=63444&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Jan 30 17:10:59 2009 @@ -991,6 +991,7 @@ assert(isTypeLegal(Op.getValueType()) && "Caller should expand or promote operands that are not legal!"); SDNode *Node = Op.getNode(); + DebugLoc dl = Node->getDebugLoc(); // If this operation defines any values that cannot be represented in a // register on this target, make sure to expand or promote them. @@ -4323,7 +4324,7 @@ TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, false, false, CallingConv::C, false, DAG.getExternalSymbol("abort", TLI.getPointerTy()), - Args, DAG); + Args, DAG, dl); Result = CallResult.second; break; } @@ -5791,7 +5792,8 @@ const Type *RetTy = Node->getValueType(0).getTypeForMVT(); std::pair CallInfo = TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, - CallingConv::C, false, Callee, Args, DAG); + CallingConv::C, false, Callee, Args, DAG, + Node->getDebugLoc()); // Legalize the call sequence, starting with the chain. This will advance // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=63444&r1=63443&r2=63444&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Fri Jan 30 17:10:59 2009 @@ -987,9 +987,11 @@ TLI.getPointerTy()); const Type *RetTy = RetVT.getTypeForMVT(); + // FIXME pass in debug loc std::pair CallInfo = TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false, - false, CallingConv::C, false, Callee, Args, DAG); + false, CallingConv::C, false, Callee, Args, DAG, + DebugLoc::getUnknownLoc()); return CallInfo.first; } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63444&r1=63443&r2=63444&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Jan 30 17:10:59 2009 @@ -3285,11 +3285,12 @@ Entry.Node = Dst; Args.push_back(Entry); Entry.Node = Src; Args.push_back(Entry); Entry.Node = Size; Args.push_back(Entry); + // FIXME: pass in DebugLoc std::pair CallResult = TLI.LowerCallTo(Chain, Type::VoidTy, false, false, false, false, CallingConv::C, false, getExternalSymbol("memcpy", TLI.getPointerTy()), - Args, *this); + Args, *this, DebugLoc::getUnknownLoc()); return CallResult.second; } @@ -3330,11 +3331,12 @@ Entry.Node = Dst; Args.push_back(Entry); Entry.Node = Src; Args.push_back(Entry); Entry.Node = Size; Args.push_back(Entry); + // FIXME: pass in DebugLoc std::pair CallResult = TLI.LowerCallTo(Chain, Type::VoidTy, false, false, false, false, CallingConv::C, false, getExternalSymbol("memmove", TLI.getPointerTy()), - Args, *this); + Args, *this, DebugLoc::getUnknownLoc()); return CallResult.second; } @@ -3381,11 +3383,12 @@ Args.push_back(Entry); Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; Args.push_back(Entry); + // FIXME: pass in DebugLoc std::pair CallResult = TLI.LowerCallTo(Chain, Type::VoidTy, false, false, false, false, CallingConv::C, false, getExternalSymbol("memset", TLI.getPointerTy()), - Args, *this); + Args, *this, DebugLoc::getUnknownLoc()); return CallResult.second; } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63444&r1=63443&r2=63444&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Fri Jan 30 17:10:59 2009 @@ -4344,7 +4344,7 @@ CS.paramHasAttr(0, Attribute::InReg), CS.getCallingConv(), IsTailCall && PerformTailCallOpt, - Callee, Args, DAG); + Callee, Args, DAG, DAG.getCurDebugLoc()); if (CS.getType() != Type::VoidTy) setValue(CS.getInstruction(), Result.first); DAG.setRoot(Result.second); @@ -5357,7 +5357,7 @@ TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false, CallingConv::C, PerformTailCallOpt, DAG.getExternalSymbol("malloc", IntPtr), - Args, DAG); + Args, DAG, DAG.getCurDebugLoc()); setValue(&I, Result.first); // Pointers always fit in registers DAG.setRoot(Result.second); } @@ -5372,7 +5372,8 @@ std::pair Result = TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false, CallingConv::C, PerformTailCallOpt, - DAG.getExternalSymbol("free", IntPtr), Args, DAG); + DAG.getExternalSymbol("free", IntPtr), Args, DAG, + DAG.getCurDebugLoc()); DAG.setRoot(Result.second); } @@ -5412,7 +5413,8 @@ /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be /// integrated into SDISel. void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, - SmallVectorImpl &ArgValues) { + SmallVectorImpl &ArgValues, + DebugLoc dl) { // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. SmallVector Ops; Ops.push_back(DAG.getRoot()); @@ -5477,7 +5479,7 @@ RetVals.push_back(MVT::Other); // Create the node. - SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, DAG.getCurDebugLoc(), + SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl, DAG.getVTList(&RetVals[0], RetVals.size()), &Ops[0], Ops.size()).getNode(); @@ -5545,7 +5547,7 @@ bool isInreg, unsigned CallingConv, bool isTailCall, SDValue Callee, - ArgListTy &Args, SelectionDAG &DAG) { + ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) { assert((!isTailCall || PerformTailCallOpt) && "isTailCall set when tail-call optimizations are disabled!"); @@ -5636,7 +5638,7 @@ LoweredRetTys.push_back(MVT::Other); // Always has a chain. // Create the CALL node. - SDValue Res = DAG.getCall(CallingConv, DAG.getCurDebugLoc(), + SDValue Res = DAG.getCall(CallingConv, dl, isVarArg, isTailCall, isInreg, DAG.getVTList(&LoweredRetTys[0], LoweredRetTys.size()), @@ -5668,7 +5670,7 @@ AssertOp); ReturnValues.push_back(ReturnValue); } - Res = DAG.getNode(ISD::MERGE_VALUES, DAG.getCurDebugLoc(), + Res = DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(&RetTys[0], RetTys.size()), &ReturnValues[0], ReturnValues.size()); } @@ -5712,7 +5714,7 @@ Function &F = *LLVMBB->getParent(); SDValue OldRoot = SDL->DAG.getRoot(); SmallVector Args; - TLI.LowerArguments(F, SDL->DAG, Args); + TLI.LowerArguments(F, SDL->DAG, Args, SDL->DAG.getCurDebugLoc()); unsigned a = 0; for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=63444&r1=63443&r2=63444&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jan 30 17:10:59 2009 @@ -740,10 +740,12 @@ Entry.Node = Argument; Entry.Ty = (const Type *) Type::Int32Ty; Args.push_back(Entry); + // FIXME: is there useful debug info available here? std::pair CallResult = LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false, CallingConv::C, false, - DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG); + DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, + DebugLoc::getUnknownLoc()); return CallResult.first; } Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=63444&r1=63443&r2=63444&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Fri Jan 30 17:10:59 2009 @@ -356,7 +356,8 @@ bool RetSExt, bool RetZExt, bool isVarArg, bool isInreg, unsigned CallingConv, bool isTailCall, SDValue Callee, - ArgListTy &Args, SelectionDAG &DAG) { + ArgListTy &Args, SelectionDAG &DAG, + DebugLoc dl) { int NumBytes = 0; if (Args.size() > 6) NumBytes = (Args.size() - 6) * 8; @@ -374,11 +375,13 @@ // Promote the integer to 64 bits. If the input type is signed use a // sign extend, otherwise use a zero extend. if (Args[i].isSExt) - Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].Node); + Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, dl, + MVT::i64, Args[i].Node); else if (Args[i].isZExt) - Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].Node); + Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, dl, + MVT::i64, Args[i].Node); else - Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, MVT::i64, Args[i].Node); + Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, Args[i].Node); break; case MVT::i64: case MVT::f64: @@ -402,7 +405,8 @@ Ops.push_back(Chain); Ops.push_back(Callee); Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end()); - SDValue TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size()); + SDValue TheCall = DAG.getNode(AlphaISD::CALL, dl, + RetVals, &Ops[0], Ops.size()); Chain = TheCall.getValue(RetTyVT != MVT::isVoid); Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), DAG.getIntPtrConstant(0, true), SDValue()); @@ -416,10 +420,10 @@ AssertKind = ISD::AssertZext; if (AssertKind != ISD::DELETED_NODE) - RetVal = DAG.getNode(AssertKind, MVT::i64, RetVal, + RetVal = DAG.getNode(AssertKind, dl, MVT::i64, RetVal, DAG.getValueType(RetTyVT)); - RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); + RetVal = DAG.getNode(ISD::TRUNCATE, dl, RetTyVT, RetVal); } return std::make_pair(RetVal, Chain); Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h?rev=63444&r1=63443&r2=63444&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h Fri Jan 30 17:10:59 2009 @@ -87,7 +87,8 @@ virtual std::pair LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, bool isVarArg, bool isInreg, unsigned CC, bool isTailCall, - SDValue Callee, ArgListTy &Args, SelectionDAG &DAG); + SDValue Callee, ArgListTy &Args, SelectionDAG &DAG, + DebugLoc dl); ConstraintType getConstraintType(const std::string &Constraint) const; Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=63444&r1=63443&r2=63444&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Fri Jan 30 17:10:59 2009 @@ -113,7 +113,8 @@ const Type *RetTy = Op.getNode()->getValueType(0).getTypeForMVT(); std::pair CallInfo = TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, - CallingConv::C, false, Callee, Args, DAG); + CallingConv::C, false, Callee, Args, DAG, + Op.getNode()->getDebugLoc()); return CallInfo.first; } Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp?rev=63444&r1=63443&r2=63444&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp Fri Jan 30 17:10:59 2009 @@ -145,7 +145,8 @@ } void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, - SmallVectorImpl &ArgValues) { + SmallVectorImpl &ArgValues, + DebugLoc dl) { // // add beautiful description of IA64 stack frame format // here (from intel 24535803.pdf most likely) @@ -199,7 +200,7 @@ argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::f64); if (I->getType() == Type::FloatTy) - argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt, + argt = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, argt, DAG.getIntPtrConstant(0)); break; case MVT::i1: // NOTE: as far as C abi stuff goes, @@ -218,7 +219,7 @@ argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64); if ( getValueType(I->getType()) != MVT::i64) - argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()), + argt = DAG.getNode(ISD::TRUNCATE, dl, getValueType(I->getType()), newroot); break; } @@ -230,7 +231,7 @@ // Create the SelectionDAG nodes corresponding to a load //from this parameter SDValue FIN = DAG.getFrameIndex(FI, MVT::i64); - argt = newroot = DAG.getLoad(getValueType(I->getType()), + argt = newroot = DAG.getLoad(getValueType(I->getType()), dl, DAG.getEntryNode(), FIN, NULL, 0); } ++count; @@ -307,7 +308,8 @@ bool RetSExt, bool RetZExt, bool isVarArg, bool isInreg, unsigned CallingConv, bool isTailCall, SDValue Callee, - ArgListTy &Args, SelectionDAG &DAG) { + ArgListTy &Args, SelectionDAG &DAG, + DebugLoc dl) { MachineFunction &MF = DAG.getMachineFunction(); @@ -360,7 +362,7 @@ ExtendKind = ISD::SIGN_EXTEND; else if (Args[i].isZExt) ExtendKind = ISD::ZERO_EXTEND; - Val = DAG.getNode(ExtendKind, MVT::i64, Val); + Val = DAG.getNode(ExtendKind, dl, MVT::i64, Val); // XXX: fall through } case MVT::i64: @@ -373,7 +375,7 @@ break; case MVT::f32: //promote to 64-bits - Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); + Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); // XXX: fall through case MVT::f64: if(RegValuesToPass.size() >= 8) { @@ -392,19 +394,21 @@ StackPtr = DAG.getRegister(IA64::r12, MVT::i64); } SDValue PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); - PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff); - Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); + PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, PtrOff); + Stores.push_back(DAG.getStore(Chain, dl, ValToStore, PtrOff, NULL, 0)); ArgOffset += ObjSize; } if(ValToConvert.getNode()) { - Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert)); + Converts.push_back(DAG.getNode(IA64ISD::GETFD, dl, + MVT::i64, ValToConvert)); } } // Emit all stores, make sure they occur before any copies into physregs. if (!Stores.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size()); + Chain = DAG.getNode(ISD::TokenFactor, dl, + MVT::Other, &Stores[0],Stores.size()); static const unsigned IntArgRegs[] = { IA64::out0, IA64::out1, IA64::out2, IA64::out3, @@ -477,7 +481,7 @@ assert(0 && "this should never happen!\n"); // to make way for a hack: - Chain = DAG.getNode(IA64ISD::BRCALL, NodeTys, + Chain = DAG.getNode(IA64ISD::BRCALL, dl, NodeTys, &CallOperands[0], CallOperands.size()); InFlag = Chain.getValue(1); @@ -508,7 +512,7 @@ InFlag = zeroReg.getValue(2); Chain = zeroReg.getValue(1); - RetVal = DAG.getSetCC(MVT::i1, boolInR8, zeroReg, ISD::SETNE); + RetVal = DAG.getSetCC(dl, MVT::i1, boolInR8, zeroReg, ISD::SETNE); break; } case MVT::i8: @@ -520,9 +524,9 @@ // keep track of whether it is sign or zero extended (todo: bools?) /* XXX RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, - MVT::i64, RetVal, DAG.getValueType(RetTyVT)); + dl, MVT::i64, RetVal, DAG.getValueType(RetTyVT)); */ - RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); + RetVal = DAG.getNode(ISD::TRUNCATE, dl, RetTyVT, RetVal); break; case MVT::i64: RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag); @@ -532,7 +536,7 @@ case MVT::f32: RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag); Chain = RetVal.getValue(1); - RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal, + RetVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, RetVal, DAG.getIntPtrConstant(0)); break; case MVT::f64: Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.h?rev=63444&r1=63443&r2=63444&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64ISelLowering.h (original) +++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.h Fri Jan 30 17:10:59 2009 @@ -54,7 +54,8 @@ /// LowerArguments - This hook must be implemented to indicate how we should /// lower the arguments for the specified function, into the specified DAG. virtual void LowerArguments(Function &F, SelectionDAG &DAG, - SmallVectorImpl &ArgValues); + SmallVectorImpl &ArgValues, + DebugLoc dl); /// LowerCallTo - This hook lowers an abstract call to a function into an /// actual call. @@ -62,7 +63,8 @@ LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, bool isVarArg, bool isInreg, unsigned CC, bool isTailCall, - SDValue Callee, ArgListTy &Args, SelectionDAG &DAG); + SDValue Callee, ArgListTy &Args, SelectionDAG &DAG, + DebugLoc dl); /// LowerOperation - for custom lowering specific ops /// (currently, only "ret void") Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=63444&r1=63443&r2=63444&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Fri Jan 30 17:10:59 2009 @@ -172,7 +172,7 @@ PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call, MVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, - SelectionDAG &DAG) { + SelectionDAG &DAG, DebugLoc dl) { TargetLowering::ArgListTy Args; Args.reserve(NumOps); @@ -190,7 +190,7 @@ const Type *RetTy = RetVT.getTypeForMVT(); std::pair CallInfo = LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false, - false, CallingConv::C, false, Callee, Args, DAG); + false, CallingConv::C, false, Callee, Args, DAG, dl); return CallInfo.first; } @@ -758,7 +758,8 @@ SmallVector Ops(2); Ops[0] = Value; Ops[1] = Amt; - SDValue Call = MakePIC16Libcall(CallCode, N->getValueType(0), &Ops[0], 2, true, DAG); + SDValue Call = MakePIC16Libcall(CallCode, N->getValueType(0), &Ops[0], 2, + true, DAG, N->getDebugLoc()); return Call; } Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h?rev=63444&r1=63443&r2=63444&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h (original) +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h Fri Jan 30 17:10:59 2009 @@ -168,7 +168,7 @@ // Make PIC16 Libcall SDValue MakePIC16Libcall(PIC16ISD::PIC16Libcall Call, MVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, - SelectionDAG &DAG); + SelectionDAG &DAG, DebugLoc dl); // Check if operation has a direct load operand. inline bool isDirectLoad(const SDValue Op); Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=63444&r1=63443&r2=63444&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri Jan 30 17:10:59 2009 @@ -1229,6 +1229,7 @@ SDValue Trmp = Op.getOperand(1); // trampoline SDValue FPtr = Op.getOperand(2); // nested function SDValue Nest = Op.getOperand(3); // 'nest' parameter value + DebugLoc dl = Op.getNode()->getDebugLoc(); MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); bool isPPC64 = (PtrVT == MVT::i64); @@ -1254,7 +1255,7 @@ LowerCallTo(Chain, Op.getValueType().getTypeForMVT(), false, false, false, false, CallingConv::C, false, DAG.getExternalSymbol("__trampoline_setup", PtrVT), - Args, DAG); + Args, DAG, dl); SDValue Ops[] = { CallResult.first, CallResult.second }; Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=63444&r1=63443&r2=63444&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Fri Jan 30 17:10:59 2009 @@ -77,7 +77,8 @@ /// in FP registers for fastcc functions. void SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, - SmallVectorImpl &ArgValues) { + SmallVectorImpl &ArgValues, + DebugLoc dl) { MachineFunction &MF = DAG.getMachineFunction(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.h?rev=63444&r1=63443&r2=63444&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.h Fri Jan 30 17:10:59 2009 @@ -58,7 +58,8 @@ unsigned Depth = 0) const; virtual void LowerArguments(Function &F, SelectionDAG &DAG, - SmallVectorImpl &ArgValues); + SmallVectorImpl &ArgValues, + DebugLoc dl); virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=63444&r1=63443&r2=63444&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jan 30 17:10:59 2009 @@ -5532,10 +5532,12 @@ Args.push_back(Entry); Entry.Node = Size; Args.push_back(Entry); + // FIXME provide DebugLoc info std::pair CallResult = LowerCallTo(Chain, Type::VoidTy, false, false, false, false, CallingConv::C, false, - DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG); + DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, + DebugLoc::getUnknownLoc()); return CallResult.second; } From isanbard at gmail.com Fri Jan 30 17:15:49 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 23:15:49 -0000 Subject: [llvm-commits] [llvm] r63446 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200901302315.n0UNFnJV019801@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 17:15:49 2009 New Revision: 63446 URL: http://llvm.org/viewvc/llvm-project?rev=63446&view=rev Log: More DebugLoc propagation in floating-point methods. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63446&r1=63445&r2=63446&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 17:15:49 2009 @@ -4132,10 +4132,12 @@ // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) if (!V.isNegative()) { if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) - return DAG.getNode(ISD::FABS, VT, N0); + return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); } else { if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) - return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); + return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, + DAG.getNode(ISD::FABS, DebugLoc::getUnknownLoc(), + VT, N0)); } } @@ -4144,20 +4146,23 @@ // copysign(copysign(x,z), y) -> copysign(x, y) if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) - return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); + return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, + N0.getOperand(0), N1); // copysign(x, abs(y)) -> abs(x) if (N1.getOpcode() == ISD::FABS) - return DAG.getNode(ISD::FABS, VT, N0); + return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); // copysign(x, copysign(y,z)) -> copysign(x, z) if (N1.getOpcode() == ISD::FCOPYSIGN) - return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); + return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, + N0, N1.getOperand(1)); // copysign(x, fp_extend(y)) -> copysign(x, y) // copysign(x, fp_round(y)) -> copysign(x, y) if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) - return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); + return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, + N0, N1.getOperand(0)); return SDValue(); } @@ -4172,7 +4177,7 @@ // fold (sint_to_fp c1) -> c1fp if (N0C && OpVT != MVT::ppcf128) - return DAG.getNode(ISD::SINT_TO_FP, VT, N0); + return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); // If the input is a legal type, and SINT_TO_FP is not legal on this target, // but UINT_TO_FP is legal on this target, try to convert. @@ -4180,10 +4185,9 @@ TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { // If the sign bit is known to be zero, we can change this to UINT_TO_FP. if (DAG.SignBitIsZero(N0)) - return DAG.getNode(ISD::UINT_TO_FP, VT, N0); + return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); } - - + return SDValue(); } @@ -4195,7 +4199,7 @@ // fold (uint_to_fp c1) -> c1fp if (N0C && OpVT != MVT::ppcf128) - return DAG.getNode(ISD::UINT_TO_FP, VT, N0); + return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); // If the input is a legal type, and UINT_TO_FP is not legal on this target, // but SINT_TO_FP is legal on this target, try to convert. @@ -4203,7 +4207,7 @@ TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { // If the sign bit is known to be zero, we can change this to SINT_TO_FP. if (DAG.SignBitIsZero(N0)) - return DAG.getNode(ISD::SINT_TO_FP, VT, N0); + return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); } return SDValue(); @@ -4216,7 +4220,8 @@ // fold (fp_to_sint c1fp) -> c1 if (N0CFP) - return DAG.getNode(ISD::FP_TO_SINT, VT, N0); + return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); + return SDValue(); } @@ -4227,7 +4232,8 @@ // fold (fp_to_uint c1fp) -> c1 if (N0CFP && VT != MVT::ppcf128) - return DAG.getNode(ISD::FP_TO_UINT, VT, N0); + return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); + return SDValue(); } @@ -4239,7 +4245,7 @@ // fold (fp_round c1fp) -> c1fp if (N0CFP && N0.getValueType() != MVT::ppcf128) - return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); + return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); // fold (fp_round (fp_extend x)) -> x if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) @@ -4250,15 +4256,17 @@ // This is a value preserving truncation if both round's are. bool IsTrunc = N->getConstantOperandVal(1) == 1 && N0.getNode()->getConstantOperandVal(1) == 1; - return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), + return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), DAG.getIntPtrConstant(IsTrunc)); } // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { - SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); + SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, + N0.getOperand(0), N1); AddToWorkList(Tmp.getNode()); - return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); + return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, + Tmp, N0.getOperand(1)); } return SDValue(); @@ -4273,8 +4281,9 @@ // fold (fp_round_inreg c1fp) -> c1fp if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); - return DAG.getNode(ISD::FP_EXTEND, VT, Round); + return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); } + return SDValue(); } @@ -4290,7 +4299,7 @@ // fold (fp_extend c1fp) -> c1fp if (N0CFP && VT != MVT::ppcf128) - return DAG.getNode(ISD::FP_EXTEND, VT, N0); + return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the // value of X. @@ -4299,8 +4308,9 @@ SDValue In = N0.getOperand(0); if (In.getValueType() == VT) return In; if (VT.bitsLT(In.getValueType())) - return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); - return DAG.getNode(ISD::FP_EXTEND, VT, In); + return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, + In, N0.getOperand(1)); + return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); } // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) @@ -4308,14 +4318,16 @@ ((!LegalOperations && !cast(N0)->isVolatile()) || TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { LoadSDNode *LN0 = cast(N0); - SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), + SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, + LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), LN0->getSrcValueOffset(), N0.getValueType(), LN0->isVolatile(), LN0->getAlignment()); CombineTo(N, ExtLoad); - CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(), - ExtLoad, DAG.getIntPtrConstant(1)), + CombineTo(N0.getNode(), + DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), + N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), ExtLoad.getValue(1)); return SDValue(N, 0); // Return N so it doesn't get rechecked! } @@ -4337,10 +4349,11 @@ SDValue Int = N0.getOperand(0); MVT IntVT = Int.getValueType(); if (IntVT.isInteger() && !IntVT.isVector()) { - Int = DAG.getNode(ISD::XOR, IntVT, Int, + Int = DAG.getNode(ISD::XOR, DebugLoc::getUnknownLoc(), IntVT, Int, DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT)); AddToWorkList(Int.getNode()); - return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); + return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), + N->getValueType(0), Int); } } From dalej at apple.com Fri Jan 30 17:20:42 2009 From: dalej at apple.com (Dale Johannesen) Date: Fri, 30 Jan 2009 23:20:42 -0000 Subject: [llvm-commits] [llvm] r63448 - /llvm/trunk/include/llvm/Target/TargetLowering.h Message-ID: <200901302320.n0UNKgeQ020007@zion.cs.uiuc.edu> Author: johannes Date: Fri Jan 30 17:20:42 2009 New Revision: 63448 URL: http://llvm.org/viewvc/llvm-project?rev=63448&view=rev Log: Fix build on case-sensitive filesystems (i.e. everybody else) Modified: llvm/trunk/include/llvm/Target/TargetLowering.h Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=63448&r1=63447&r2=63448&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Fri Jan 30 17:20:42 2009 @@ -29,7 +29,7 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/STLExtras.h" -#include "llvm/Codegen/DebugLoc.h" +#include "llvm/CodeGen/DebugLoc.h" #include #include #include From isanbard at gmail.com Fri Jan 30 17:27:35 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 23:27:35 -0000 Subject: [llvm-commits] [llvm] r63451 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200901302327.n0UNRZgj020291@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 17:27:35 2009 New Revision: 63451 URL: http://llvm.org/viewvc/llvm-project?rev=63451&view=rev Log: More DebugLoc propagation in LOAD etc. methods. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63451&r1=63450&r2=63451&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 17:27:35 2009 @@ -4367,14 +4367,14 @@ // fold (fabs c1) -> fabs(c1) if (N0CFP && VT != MVT::ppcf128) - return DAG.getNode(ISD::FABS, VT, N0); + return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); // fold (fabs (fabs x)) -> (fabs x) if (N0.getOpcode() == ISD::FABS) return N->getOperand(0); // fold (fabs (fneg x)) -> (fabs x) // fold (fabs (fcopysign x, y)) -> (fabs x) if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) - return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); + return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading // constant pool values. @@ -4384,10 +4384,11 @@ SDValue Int = N0.getOperand(0); MVT IntVT = Int.getValueType(); if (IntVT.isInteger() && !IntVT.isVector()) { - Int = DAG.getNode(ISD::AND, IntVT, Int, + Int = DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(), IntVT, Int, DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT)); AddToWorkList(Int.getNode()); - return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); + return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), + N->getValueType(0), Int); } } @@ -4405,14 +4406,16 @@ return Chain; // unconditional branch if (N1C && N1C->getAPIntValue() == 1) - return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); + return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2); // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal // on the target. if (N1.getOpcode() == ISD::SETCC && TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { - return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), + return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, + Chain, N1.getOperand(2), N1.getOperand(0), N1.getOperand(1), N2); } + return SDValue(); } @@ -4431,21 +4434,22 @@ // fold br_cc true, dest -> br dest (unconditional branch) if (SCCC && !SCCC->isNullValue()) - return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), - N->getOperand(4)); + return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, + N->getOperand(0), N->getOperand(4)); // fold br_cc false, dest -> unconditional fall through if (SCCC && SCCC->isNullValue()) return N->getOperand(0); // fold to a simpler setcc if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) - return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), - Simp.getOperand(2), Simp.getOperand(0), - Simp.getOperand(1), N->getOperand(4)); + return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, + N->getOperand(0), Simp.getOperand(2), + Simp.getOperand(0), Simp.getOperand(1), + N->getOperand(4)); + return SDValue(); } - /// CombineToPreIndexedLoadStore - Try turning a load / store into a /// pre-indexed load / store when the base pointer is an add or subtract /// and it has other uses besides the load / store. After the @@ -4476,8 +4480,9 @@ return false; Ptr = ST->getBasePtr(); isLoad = false; - } else + } else { return false; + } // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail // out. There is no reason to make this a preinc/predec. @@ -4532,14 +4537,17 @@ cast(Use)->getBasePtr() == Ptr))) RealUse = true; } + if (!RealUse) return false; SDValue Result; if (isLoad) - Result = DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM); + Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), + BasePtr, Offset, AM); else - Result = DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); + Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), + BasePtr, Offset, AM); ++PreIndexedNodes; ++NodesCombined; DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); @@ -4597,8 +4605,9 @@ return false; Ptr = ST->getBasePtr(); isLoad = false; - } else + } else { return false; + } if (Ptr.getNode()->hasOneUse()) return false; @@ -4657,14 +4666,17 @@ } } } + if (TryNext) continue; // Check for #2 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { SDValue Result = isLoad - ? DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM) - : DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); + ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), + BasePtr, Offset, AM) + : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), + BasePtr, Offset, AM); ++PostIndexedNodes; ++NodesCombined; DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); @@ -4694,6 +4706,7 @@ } } } + return false; } @@ -4749,13 +4762,13 @@ if (!Fast && LD->isUnindexed()) { if (unsigned Align = InferAlignment(Ptr, DAG)) { if (Align > LD->getAlignment()) - return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), + return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), + LD->getValueType(0), Chain, Ptr, LD->getSrcValue(), LD->getSrcValueOffset(), LD->getMemoryVT(), LD->isVolatile(), Align); } } - // If load is not volatile and there are no uses of the loaded value (and // the updated indexed value in case of indexed loads), change uses of the @@ -4775,10 +4788,12 @@ DOUT << "\n"; WorkListRemover DeadNodes(*this); DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); + if (N->use_empty()) { removeFromWorkList(N); DAG.DeleteNode(N); } + return SDValue(N, 0); // Return N so it doesn't get rechecked! } } else { @@ -4792,7 +4807,8 @@ WorkListRemover DeadNodes(*this); DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), - DAG.getNode(ISD::UNDEF, N->getValueType(1)), + DAG.getNode(ISD::UNDEF, DebugLoc::getUnknownLoc(), + N->getValueType(1)), &DeadNodes); DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); removeFromWorkList(N); @@ -4826,11 +4842,12 @@ // Replace the chain to void dependency. if (LD->getExtensionType() == ISD::NON_EXTLOAD) { - ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, + ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), + BetterChain, Ptr, LD->getSrcValue(), LD->getSrcValueOffset(), LD->isVolatile(), LD->getAlignment()); } else { - ReplLoad = DAG.getExtLoad(LD->getExtensionType(), + ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), LD->getValueType(0), BetterChain, Ptr, LD->getSrcValue(), LD->getSrcValueOffset(), @@ -4840,8 +4857,8 @@ } // Create token factor to keep old chain connected. - SDValue Token = DAG.getNode(ISD::TokenFactor, MVT::Other, - Chain, ReplLoad.getValue(1)); + SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), + MVT::Other, Chain, ReplLoad.getValue(1)); // Replace uses with load result and token factor. Don't add users // to work list. @@ -4856,7 +4873,6 @@ return SDValue(); } - SDValue DAGCombiner::visitSTORE(SDNode *N) { StoreSDNode *ST = cast(N); SDValue Chain = ST->getChain(); From isanbard at gmail.com Fri Jan 30 17:36:47 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 23:36:47 -0000 Subject: [llvm-commits] [llvm] r63452 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200901302336.n0UNal9f020576@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 17:36:47 2009 New Revision: 63452 URL: http://llvm.org/viewvc/llvm-project?rev=63452&view=rev Log: More DebugLoc propagation. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63452&r1=63451&r2=63452&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 17:36:47 2009 @@ -4883,7 +4883,8 @@ if (!Fast && ST->isUnindexed()) { if (unsigned Align = InferAlignment(Ptr, DAG)) { if (Align > ST->getAlignment()) - return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), + return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, + Ptr, ST->getSrcValue(), ST->getSrcValueOffset(), ST->getMemoryVT(), ST->isVolatile(), Align); } @@ -4900,7 +4901,8 @@ if (Align <= OrigAlign && ((!LegalOperations && !ST->isVolatile()) || TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) - return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), + return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), + Ptr, ST->getSrcValue(), ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); } @@ -4924,7 +4926,8 @@ TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). bitcastToAPInt().getZExtValue(), MVT::i32); - return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), + return DAG.getStore(Chain, N->getDebugLoc(), Tmp, + Ptr, ST->getSrcValue(), ST->getSrcValueOffset(), ST->isVolatile(), ST->getAlignment()); } @@ -4934,8 +4937,9 @@ !ST->isVolatile()) || TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). - getZExtValue(), MVT::i64); - return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), + getZExtValue(), MVT::i64); + return DAG.getStore(Chain, N->getDebugLoc(), Tmp, + Ptr, ST->getSrcValue(), ST->getSrcValueOffset(), ST->isVolatile(), ST->getAlignment()); } else if (!ST->isVolatile() && @@ -4952,17 +4956,21 @@ unsigned Alignment = ST->getAlignment(); bool isVolatile = ST->isVolatile(); - SDValue St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), - ST->getSrcValueOffset(), - isVolatile, ST->getAlignment()); - Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, + SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, + Ptr, ST->getSrcValue(), + ST->getSrcValueOffset(), + isVolatile, ST->getAlignment()); + Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, DAG.getConstant(4, Ptr.getValueType())); SVOffset += 4; Alignment = MinAlign(Alignment, 4U); - SDValue St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), - SVOffset, isVolatile, Alignment); - return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); + SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, + Ptr, ST->getSrcValue(), + SVOffset, isVolatile, Alignment); + return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, + St0, St1); } + break; } } @@ -4977,20 +4985,20 @@ // Replace the chain to avoid dependency. SDValue ReplStore; if (ST->isTruncatingStore()) { - ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, + ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, ST->getSrcValue(),ST->getSrcValueOffset(), ST->getMemoryVT(), ST->isVolatile(), ST->getAlignment()); } else { - ReplStore = DAG.getStore(BetterChain, Value, Ptr, + ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, ST->getSrcValue(), ST->getSrcValueOffset(), ST->isVolatile(), ST->getAlignment()); } // Create token to keep both nodes around. - SDValue Token = - DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); - + SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), + MVT::Other, Chain, ReplStore); + // Don't add users to work list. return CombineTo(N, Token, false); } @@ -5008,11 +5016,12 @@ // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" SDValue Shorter = GetDemandedBits(Value, - APInt::getLowBitsSet(Value.getValueSizeInBits(), - ST->getMemoryVT().getSizeInBits())); + APInt::getLowBitsSet(Value.getValueSizeInBits(), + ST->getMemoryVT().getSizeInBits())); AddToWorkList(Value.getNode()); if (Shorter.getNode()) - return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), + return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, + Ptr, ST->getSrcValue(), ST->getSrcValueOffset(), ST->getMemoryVT(), ST->isVolatile(), ST->getAlignment()); @@ -5044,7 +5053,8 @@ && Value.getNode()->hasOneUse() && ST->isUnindexed() && TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), ST->getMemoryVT())) { - return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), + return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), + Ptr, ST->getSrcValue(), ST->getSrcValueOffset(), ST->getMemoryVT(), ST->isVolatile(), ST->getAlignment()); } @@ -5065,8 +5075,8 @@ InVec.getNode()->op_end()); if (Elt < Ops.size()) Ops[Elt] = InVal; - return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), - &Ops[0], Ops.size()); + return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), + InVec.getValueType(), &Ops[0], Ops.size()); } return SDValue(); @@ -5095,6 +5105,7 @@ MVT VT = InVec.getValueType(); MVT EVT = VT.getVectorElementType(); MVT LVT = EVT; + if (InVec.getOpcode() == ISD::BIT_CONVERT) { MVT BCVT = InVec.getOperand(0).getValueType(); if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) @@ -5107,11 +5118,11 @@ } LoadSDNode *LN0 = NULL; - if (ISD::isNormalLoad(InVec.getNode())) + if (ISD::isNormalLoad(InVec.getNode())) { LN0 = cast(InVec); - else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && - InVec.getOperand(0).getValueType() == EVT && - ISD::isNormalLoad(InVec.getOperand(0).getNode())) { + } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && + InVec.getOperand(0).getValueType() == EVT && + ISD::isNormalLoad(InVec.getOperand(0).getNode())) { LN0 = cast(InVec.getOperand(0)); } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) @@ -5133,6 +5144,7 @@ Elt = (Idx < NumElems) ? Idx : Idx - NumElems; } } + if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) return SDValue(); @@ -5140,10 +5152,12 @@ if (NewLoad) { // Check the resultant load doesn't need a higher alignment than the // original load. - unsigned NewAlign = TLI.getTargetData()-> - getABITypeAlignment(LVT.getTypeForMVT()); + unsigned NewAlign = + TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT()); + if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) return SDValue(); + Align = NewAlign; } @@ -5153,16 +5167,17 @@ MVT PtrType = NewPtr.getValueType(); if (TLI.isBigEndian()) PtrOff = VT.getSizeInBits() / 8 - PtrOff; - NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, + NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, DAG.getConstant(PtrOff, PtrType)); } - return DAG.getLoad(LVT, LN0->getChain(), NewPtr, + + return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(), LN0->isVolatile(), Align); } + return SDValue(); } - SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { unsigned NumInScalars = N->getNumOperands(); @@ -5214,7 +5229,9 @@ SmallVector BuildVecIndices; for (unsigned i = 0; i != NumInScalars; ++i) { if (N->getOperand(i).getOpcode() == ISD::UNDEF) { - BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); + BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, + DebugLoc::getUnknownLoc(), + TLI.getPointerTy())); continue; } @@ -5245,15 +5262,15 @@ } else { // Use an undef build_vector as input for the second operand. std::vector UnOps(NumInScalars, - DAG.getNode(ISD::UNDEF, - EltType)); - Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, + DAG.getNode(ISD::UNDEF, EltType)); + Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, &UnOps[0], UnOps.size()); AddToWorkList(Ops[1].getNode()); } - Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, + + Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), BuildVecVT, &BuildVecIndices[0], BuildVecIndices.size()); - return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); + return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), VT, Ops, 3); } return SDValue(); @@ -5266,9 +5283,8 @@ // node. // If we only have one input vector, we don't need to do any concatenation. - if (N->getNumOperands() == 1) { + if (N->getNumOperands() == 1) return N->getOperand(0); - } return SDValue(); } @@ -5381,6 +5397,7 @@ // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the // first operand. SmallVector MappedOps; + for (unsigned i = 0; i != NumElts; ++i) { if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || cast(ShufMask.getOperand(i))->getZExtValue() < @@ -5394,11 +5411,13 @@ ShufMask.getOperand(i).getValueType())); } } - ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), + + ShufMask = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), + ShufMask.getValueType(), &MappedOps[0], MappedOps.size()); AddToWorkList(ShufMask.getNode()); - return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), - N0, + return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), + N->getValueType(0), N0, DAG.getNode(ISD::UNDEF, N->getValueType(0)), ShufMask); } From isanbard at gmail.com Fri Jan 30 17:59:19 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 30 Jan 2009 23:59:19 -0000 Subject: [llvm-commits] [llvm] r63454 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200901302359.n0UNxJLE021292@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 17:59:18 2009 New Revision: 63454 URL: http://llvm.org/viewvc/llvm-project?rev=63454&view=rev Log: More DebugLoc propagation. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63454&r1=63453&r2=63454&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 17:59:18 2009 @@ -202,10 +202,10 @@ bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); - SDValue SimplifySelect(SDValue N0, SDValue N1, SDValue N2); - SDValue SimplifySelectCC(SDValue N0, SDValue N1, SDValue N2, - SDValue N3, ISD::CondCode CC, - bool NotExtCompare = false); + SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); + SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, + SDValue N3, ISD::CondCode CC, + bool NotExtCompare = false); SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans = true); SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, @@ -229,13 +229,13 @@ bool isAlias(SDValue Ptr1, int64_t Size1, const Value *SrcValue1, int SrcValueOffset1, SDValue Ptr2, int64_t Size2, - const Value *SrcValue2, int SrcValueOffset2); + const Value *SrcValue2, int SrcValueOffset2) const; /// FindAliasInfo - Extracts the relevant alias information from the memory /// node. Returns true if the operand was a load. bool FindAliasInfo(SDNode *N, SDValue &Ptr, int64_t &Size, - const Value *&SrcValue, int &SrcValueOffset); + const Value *&SrcValue, int &SrcValueOffset) const; /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, /// looking for a better chain (aliasing node.) @@ -2882,7 +2882,7 @@ N0.getOperand(0), N0.getOperand(1), N1, N2, N0.getOperand(2)); else - return SimplifySelect(N0, N1, N2); + return SimplifySelect(N->getDebugLoc(), N0, N1, N2); } return SDValue(); @@ -2923,7 +2923,7 @@ return SDValue(N, 0); // Don't revisit N. // fold select_cc into other things, such as min/max/abs - return SimplifySelectCC(N0, N1, N2, N3, CC); + return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); } SDValue DAGCombiner::visitSETCC(SDNode *N) { @@ -3131,7 +3131,7 @@ // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) if (N0.getOpcode() == ISD::SETCC) { SDValue SCC = - SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), + SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), cast(N0.getOperand(2))->get(), true); if (SCC.getNode()) return SCC; @@ -3266,7 +3266,7 @@ // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc if (N0.getOpcode() == ISD::SETCC) { SDValue SCC = - SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), + SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), DAG.getConstant(1, VT), DAG.getConstant(0, VT), cast(N0.getOperand(2))->get(), true); if (SCC.getNode()) return SCC; @@ -3374,7 +3374,7 @@ // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc if (N0.getOpcode() == ISD::SETCC) { SDValue SCC = - SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), + SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), DAG.getConstant(1, VT), DAG.getConstant(0, VT), cast(N0.getOperand(2))->get(), true); if (SCC.getNode()) @@ -5460,21 +5460,25 @@ MVT VT = MVT::getVectorVT(EVT, NumElts); MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); std::vector Ops; - LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); + LHS = DAG.getNode(ISD::BIT_CONVERT, DebugLoc::getUnknownLoc(), VT, LHS); Ops.push_back(LHS); AddToWorkList(LHS.getNode()); std::vector ZeroOps(NumElts, DAG.getConstant(0, EVT)); - Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, - &ZeroOps[0], ZeroOps.size())); - Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, MaskVT, - &IdxOps[0], IdxOps.size())); - SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, - &Ops[0], Ops.size()); + Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), + VT, &ZeroOps[0], ZeroOps.size())); + Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), + MaskVT, &IdxOps[0], IdxOps.size())); + SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), + VT, &Ops[0], Ops.size()); + if (VT != N->getValueType(0)) - Result = DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Result); + Result = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), + N->getValueType(0), Result); + return Result; } } + return SDValue(); } @@ -5510,6 +5514,7 @@ RHSOp.getOpcode() != ISD::Constant && RHSOp.getOpcode() != ISD::ConstantFP)) break; + // Can't fold divide by zero. if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || N->getOpcode() == ISD::FDIV) { @@ -5519,7 +5524,9 @@ cast(RHSOp.getNode())->getValueAPF().isZero())) break; } - Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); + + Ops.push_back(DAG.getNode(N->getOpcode(), DebugLoc::getUnknownLoc(), + EltType, LHSOp, RHSOp)); AddToWorkList(Ops.back().getNode()); assert((Ops.back().getOpcode() == ISD::UNDEF || Ops.back().getOpcode() == ISD::Constant || @@ -5529,18 +5536,21 @@ if (Ops.size() == LHS.getNumOperands()) { MVT VT = LHS.getValueType(); - return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); + return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, + &Ops[0], Ops.size()); } } return SDValue(); } -SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){ +SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, + SDValue N1, SDValue N2){ assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); - SDValue SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, + SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, cast(N0.getOperand(2))->get()); + // If we got a simplified select_cc node back from SimplifySelectCC, then // break it down into a new SETCC node, and a new SELECT node, and then return // the SELECT node, since we were called with a SELECT node. @@ -5548,13 +5558,15 @@ // Check to see if we got a select_cc back (to turn into setcc/select). // Otherwise, just return whatever node we got back, like fabs. if (SCC.getOpcode() == ISD::SELECT_CC) { - SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), - SCC.getOperand(0), SCC.getOperand(1), - SCC.getOperand(4)); + SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), + N0.getValueType(), + SCC.getOperand(0), SCC.getOperand(1), + SCC.getOperand(4)); AddToWorkList(SETCC.getNode()); - return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), - SCC.getOperand(3), SETCC); + return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), + SCC.getOperand(2), SCC.getOperand(3), SETCC); } + return SCC; } return SDValue(); @@ -5566,7 +5578,6 @@ /// returns true. As such, they should return the appropriate thing (e.g. the /// node) back to the top-level of the DAG combiner loop to avoid it being /// looked at. -/// bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, SDValue RHS) { @@ -5597,7 +5608,8 @@ // this will induce a cycle into the DAG. if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { - Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), + Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), + LLD->getBasePtr().getValueType(), TheSelect->getOperand(0), LLD->getBasePtr(), RLD->getBasePtr()); } @@ -5608,24 +5620,28 @@ !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { - Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), - TheSelect->getOperand(0), - TheSelect->getOperand(1), - LLD->getBasePtr(), RLD->getBasePtr(), - TheSelect->getOperand(4)); + Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), + LLD->getBasePtr().getValueType(), + TheSelect->getOperand(0), + TheSelect->getOperand(1), + LLD->getBasePtr(), RLD->getBasePtr(), + TheSelect->getOperand(4)); } } if (Addr.getNode()) { SDValue Load; - if (LLD->getExtensionType() == ISD::NON_EXTLOAD) - Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), + if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { + Load = DAG.getLoad(TheSelect->getValueType(0), + TheSelect->getDebugLoc(), + LLD->getChain(), Addr,LLD->getSrcValue(), LLD->getSrcValueOffset(), LLD->isVolatile(), LLD->getAlignment()); - else { + } else { Load = DAG.getExtLoad(LLD->getExtensionType(), + TheSelect->getDebugLoc(), TheSelect->getValueType(0), LLD->getChain(), Addr, LLD->getSrcValue(), LLD->getSrcValueOffset(), @@ -5633,6 +5649,7 @@ LLD->isVolatile(), LLD->getAlignment()); } + // Users of the select now use the result of the load. CombineTo(TheSelect, Load); @@ -5649,10 +5666,9 @@ return false; } -SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1, +SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC, bool NotExtCompare) { - MVT VT = N2.getValueType(); ConstantSDNode *N1C = dyn_cast(N1.getNode()); ConstantSDNode *N2C = dyn_cast(N2.getNode()); @@ -5679,18 +5695,18 @@ if ((CC == ISD::SETGE || CC == ISD::SETGT) && N0 == N2 && N3.getOpcode() == ISD::FNEG && N2 == N3.getOperand(0)) - return DAG.getNode(ISD::FABS, VT, N0); + return DAG.getNode(ISD::FABS, DL, VT, N0); // select (setl[te] X, +/-0.0), fneg(X), X -> fabs if ((CC == ISD::SETLT || CC == ISD::SETLE) && N0 == N3 && N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N3) - return DAG.getNode(ISD::FABS, VT, N3); + return DAG.getNode(ISD::FABS, DL, VT, N3); } } // Check to see if we can perform the "gzip trick", transforming - // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A + // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && N0.getValueType().isInteger() && N2.getValueType().isInteger() && @@ -5705,23 +5721,32 @@ unsigned ShCtV = N2C->getAPIntValue().logBase2(); ShCtV = XType.getSizeInBits()-ShCtV-1; SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); - SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); + SDValue Shift = DAG.getNode(ISD::SRL, DebugLoc::getUnknownLoc(), + XType, N0, ShCt); AddToWorkList(Shift.getNode()); + if (XType.bitsGT(AType)) { - Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); + Shift = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), + AType, Shift); AddToWorkList(Shift.getNode()); } - return DAG.getNode(ISD::AND, AType, Shift, N2); + + return DAG.getNode(ISD::AND, DL, AType, Shift, N2); } - SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, - DAG.getConstant(XType.getSizeInBits()-1, - TLI.getShiftAmountTy())); + + SDValue Shift = DAG.getNode(ISD::SRA, DebugLoc::getUnknownLoc(), + XType, N0, + DAG.getConstant(XType.getSizeInBits()-1, + TLI.getShiftAmountTy())); AddToWorkList(Shift.getNode()); + if (XType.bitsGT(AType)) { - Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); + Shift = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), + AType, Shift); AddToWorkList(Shift.getNode()); } - return DAG.getNode(ISD::AND, AType, Shift, N2); + + return DAG.getNode(ISD::AND, DL, AType, Shift, N2); } } @@ -5740,23 +5765,29 @@ SDValue Temp, SCC; // cast from setcc result type to select result type if (LegalTypes) { - SCC = DAG.getSetCC(TLI.getSetCCResultType(N0.getValueType()), + SCC = DAG.getSetCC(DebugLoc::getUnknownLoc(), + TLI.getSetCCResultType(N0.getValueType()), N0, N1, CC); if (N2.getValueType().bitsLT(SCC.getValueType())) - Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); + Temp = DAG.getZeroExtendInReg(SCC, DebugLoc::getUnknownLoc(), + N2.getValueType()); else - Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); + Temp = DAG.getNode(ISD::ZERO_EXTEND, DebugLoc::getUnknownLoc(), + N2.getValueType(), SCC); } else { - SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); - Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); + SCC = DAG.getSetCC(DebugLoc::getUnknownLoc(), MVT::i1, N0, N1, CC); + Temp = DAG.getNode(ISD::ZERO_EXTEND, DebugLoc::getUnknownLoc(), + N2.getValueType(), SCC); } + AddToWorkList(SCC.getNode()); AddToWorkList(Temp.getNode()); if (N2C->getAPIntValue() == 1) return Temp; + // shl setcc result by log2 n2c - return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, + return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, DAG.getConstant(N2C->getAPIntValue().logBase2(), TLI.getShiftAmountTy())); } @@ -5768,37 +5799,38 @@ MVT XType = N0.getValueType(); if (!LegalOperations || TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { - SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(XType), N0, N1, CC); + SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); if (Res.getValueType() != VT) - Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); + Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); return Res; } - // seteq X, 0 -> srl (ctlz X, log2(size(X))) + // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && (!LegalOperations || TLI.isOperationLegal(ISD::CTLZ, XType))) { - SDValue Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); - return DAG.getNode(ISD::SRL, XType, Ctlz, + SDValue Ctlz = DAG.getNode(ISD::CTLZ, DebugLoc::getUnknownLoc(), + XType, N0); + return DAG.getNode(ISD::SRL, DL, XType, Ctlz, DAG.getConstant(Log2_32(XType.getSizeInBits()), TLI.getShiftAmountTy())); } - // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) + // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { - SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), - N0); + SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), + XType, DAG.getConstant(0, XType), N0); SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); - return DAG.getNode(ISD::SRL, XType, + return DAG.getNode(ISD::SRL, DL, XType, DAG.getNode(ISD::AND, XType, NegN0, NotN0), DAG.getConstant(XType.getSizeInBits()-1, TLI.getShiftAmountTy())); } - // setgt X, -1 -> xor (srl (X, size(X)-1), 1) + // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { - SDValue Sign = DAG.getNode(ISD::SRL, XType, N0, - DAG.getConstant(XType.getSizeInBits()-1, - TLI.getShiftAmountTy())); - return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); + SDValue Sign = DAG.getNode(ISD::SRL, DebugLoc::getUnknownLoc(), XType, N0, + DAG.getConstant(XType.getSizeInBits()-1, + TLI.getShiftAmountTy())); + return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); } } @@ -5808,13 +5840,14 @@ N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { MVT XType = N0.getValueType(); - SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, - DAG.getConstant(XType.getSizeInBits()-1, - TLI.getShiftAmountTy())); - SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); + SDValue Shift = DAG.getNode(ISD::SRA, DebugLoc::getUnknownLoc(), XType, N0, + DAG.getConstant(XType.getSizeInBits()-1, + TLI.getShiftAmountTy())); + SDValue Add = DAG.getNode(ISD::ADD, DebugLoc::getUnknownLoc(), XType, + N0, Shift); AddToWorkList(Shift.getNode()); AddToWorkList(Add.getNode()); - return DAG.getNode(ISD::XOR, XType, Add, Shift); + return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); } // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> // Y = sra (X, size(X)-1); xor (add (X, Y), Y) @@ -5823,13 +5856,15 @@ if (ConstantSDNode *SubC = dyn_cast(N3.getOperand(0))) { MVT XType = N0.getValueType(); if (SubC->isNullValue() && XType.isInteger()) { - SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, - DAG.getConstant(XType.getSizeInBits()-1, - TLI.getShiftAmountTy())); - SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); + SDValue Shift = DAG.getNode(ISD::SRA, DebugLoc::getUnknownLoc(), XType, + N0, + DAG.getConstant(XType.getSizeInBits()-1, + TLI.getShiftAmountTy())); + SDValue Add = DAG.getNode(ISD::ADD, DebugLoc::getUnknownLoc(), + XType, N0, Shift); AddToWorkList(Shift.getNode()); AddToWorkList(Add.getNode()); - return DAG.getNode(ISD::XOR, XType, Add, Shift); + return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); } } } @@ -5899,8 +5934,7 @@ bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, const Value *SrcValue1, int SrcValueOffset1, SDValue Ptr2, int64_t Size2, - const Value *SrcValue2, int SrcValueOffset2) -{ + const Value *SrcValue2, int SrcValueOffset2) const { // If they are the same then they must be aliases. if (Ptr1 == Ptr2) return true; @@ -5911,10 +5945,9 @@ bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); // If they have a same base address then... - if (Base1 == Base2) { + if (Base1 == Base2) // Check to see if the addresses overlap. - return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); - } + return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); // If we know both bases then they can't alias. if (KnownBase1 && KnownBase2) return false; @@ -5938,7 +5971,7 @@ /// node. Returns true if the operand was a load. bool DAGCombiner::FindAliasInfo(SDNode *N, SDValue &Ptr, int64_t &Size, - const Value *&SrcValue, int &SrcValueOffset) { + const Value *&SrcValue, int &SrcValueOffset) const { if (LoadSDNode *LD = dyn_cast(N)) { Ptr = LD->getBasePtr(); Size = LD->getMemoryVT().getSizeInBits() >> 3; From dalej at apple.com Fri Jan 30 18:11:23 2009 From: dalej at apple.com (Dale Johannesen) Date: Sat, 31 Jan 2009 00:11:23 -0000 Subject: [llvm-commits] [llvm] r63456 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeFloatTypes.cpp LegalizeIntegerTypes.cpp LegalizeTypes.cpp LegalizeTypes.h Message-ID: <200901310011.n0V0BNse021686@zion.cs.uiuc.edu> Author: johannes Date: Fri Jan 30 18:11:23 2009 New Revision: 63456 URL: http://llvm.org/viewvc/llvm-project?rev=63456&view=rev Log: Propagate debug info through MakeLibCall and a couple of things that use it. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=63456&r1=63455&r2=63456&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Fri Jan 30 18:11:23 2009 @@ -132,7 +132,7 @@ RTLIB::ADD_F64, RTLIB::ADD_F80, RTLIB::ADD_PPCF128), - NVT, Ops, 2, false); + NVT, Ops, 2, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FCEIL(SDNode *N) { @@ -143,7 +143,7 @@ RTLIB::CEIL_F64, RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128), - NVT, &Op, 1, false); + NVT, &Op, 1, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) { @@ -193,7 +193,7 @@ RTLIB::COS_F64, RTLIB::COS_F80, RTLIB::COS_PPCF128), - NVT, &Op, 1, false); + NVT, &Op, 1, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) { @@ -205,7 +205,7 @@ RTLIB::DIV_F64, RTLIB::DIV_F80, RTLIB::DIV_PPCF128), - NVT, Ops, 2, false); + NVT, Ops, 2, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP(SDNode *N) { @@ -216,7 +216,7 @@ RTLIB::EXP_F64, RTLIB::EXP_F80, RTLIB::EXP_PPCF128), - NVT, &Op, 1, false); + NVT, &Op, 1, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP2(SDNode *N) { @@ -227,7 +227,7 @@ RTLIB::EXP2_F64, RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128), - NVT, &Op, 1, false); + NVT, &Op, 1, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FFLOOR(SDNode *N) { @@ -238,7 +238,7 @@ RTLIB::FLOOR_F64, RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128), - NVT, &Op, 1, false); + NVT, &Op, 1, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG(SDNode *N) { @@ -249,7 +249,7 @@ RTLIB::LOG_F64, RTLIB::LOG_F80, RTLIB::LOG_PPCF128), - NVT, &Op, 1, false); + NVT, &Op, 1, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG2(SDNode *N) { @@ -260,7 +260,7 @@ RTLIB::LOG2_F64, RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128), - NVT, &Op, 1, false); + NVT, &Op, 1, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG10(SDNode *N) { @@ -271,7 +271,7 @@ RTLIB::LOG10_F64, RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128), - NVT, &Op, 1, false); + NVT, &Op, 1, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) { @@ -283,7 +283,7 @@ RTLIB::MUL_F64, RTLIB::MUL_F80, RTLIB::MUL_PPCF128), - NVT, Ops, 2, false); + NVT, Ops, 2, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FNEARBYINT(SDNode *N) { @@ -294,7 +294,7 @@ RTLIB::NEARBYINT_F64, RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128), - NVT, &Op, 1, false); + NVT, &Op, 1, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FNEG(SDNode *N) { @@ -307,7 +307,7 @@ RTLIB::SUB_F64, RTLIB::SUB_F80, RTLIB::SUB_PPCF128), - NVT, Ops, 2, false); + NVT, Ops, 2, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) { @@ -315,7 +315,7 @@ SDValue Op = N->getOperand(0); RTLIB::Libcall LC = RTLIB::getFPEXT(Op.getValueType(), N->getValueType(0)); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!"); - return MakeLibCall(LC, NVT, &Op, 1, false); + return MakeLibCall(LC, NVT, &Op, 1, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(SDNode *N) { @@ -323,7 +323,7 @@ SDValue Op = N->getOperand(0); RTLIB::Libcall LC = RTLIB::getFPROUND(Op.getValueType(), N->getValueType(0)); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!"); - return MakeLibCall(LC, NVT, &Op, 1, false); + return MakeLibCall(LC, NVT, &Op, 1, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FPOW(SDNode *N) { @@ -335,7 +335,7 @@ RTLIB::POW_F64, RTLIB::POW_F80, RTLIB::POW_PPCF128), - NVT, Ops, 2, false); + NVT, Ops, 2, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) { @@ -348,7 +348,7 @@ RTLIB::POWI_F64, RTLIB::POWI_F80, RTLIB::POWI_PPCF128), - NVT, Ops, 2, false); + NVT, Ops, 2, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FRINT(SDNode *N) { @@ -359,7 +359,7 @@ RTLIB::RINT_F64, RTLIB::RINT_F80, RTLIB::RINT_PPCF128), - NVT, &Op, 1, false); + NVT, &Op, 1, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FSIN(SDNode *N) { @@ -370,7 +370,7 @@ RTLIB::SIN_F64, RTLIB::SIN_F80, RTLIB::SIN_PPCF128), - NVT, &Op, 1, false); + NVT, &Op, 1, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FSQRT(SDNode *N) { @@ -381,7 +381,7 @@ RTLIB::SQRT_F64, RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128), - NVT, &Op, 1, false); + NVT, &Op, 1, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) { @@ -393,7 +393,7 @@ RTLIB::SUB_F64, RTLIB::SUB_F80, RTLIB::SUB_PPCF128), - NVT, Ops, 2, false); + NVT, Ops, 2, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_FTRUNC(SDNode *N) { @@ -404,7 +404,7 @@ RTLIB::TRUNC_F64, RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128), - NVT, &Op, 1, false); + NVT, &Op, 1, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) { @@ -455,6 +455,7 @@ MVT SVT = N->getOperand(0).getValueType(); MVT RVT = N->getValueType(0); MVT NVT = MVT(); + DebugLoc dl = N->getDebugLoc(); // If the input is not legal, eg: i1 -> fp, then it needs to be promoted to // a larger type, eg: i8 -> fp. Even if it is legal, no libcall may exactly @@ -472,7 +473,7 @@ // Sign/zero extend the argument if the libcall takes a larger type. SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, NVT, N->getOperand(0)); - return MakeLibCall(LC, TLI.getTypeToTransformTo(RVT), &Op, 1, false); + return MakeLibCall(LC, TLI.getTypeToTransformTo(RVT), &Op, 1, false, dl); } @@ -522,7 +523,7 @@ /// SoftenSetCCOperands - Soften the operands of a comparison. This code is /// shared among BR_CC, SELECT_CC, and SETCC handlers. void DAGTypeLegalizer::SoftenSetCCOperands(SDValue &NewLHS, SDValue &NewRHS, - ISD::CondCode &CCCode) { + ISD::CondCode &CCCode, DebugLoc dl) { SDValue LHSInt = GetSoftenedFloat(NewLHS); SDValue RHSInt = GetSoftenedFloat(NewRHS); MVT VT = NewLHS.getValueType(); @@ -590,13 +591,13 @@ MVT RetVT = MVT::i32; // FIXME: is this the correct return type? SDValue Ops[2] = { LHSInt, RHSInt }; - NewLHS = MakeLibCall(LC1, RetVT, Ops, 2, false/*sign irrelevant*/); + NewLHS = MakeLibCall(LC1, RetVT, Ops, 2, false/*sign irrelevant*/, dl); NewRHS = DAG.getConstant(0, RetVT); CCCode = TLI.getCmpLibcallCC(LC1); if (LC2 != RTLIB::UNKNOWN_LIBCALL) { SDValue Tmp = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(RetVT), NewLHS, NewRHS, DAG.getCondCode(CCCode)); - NewLHS = MakeLibCall(LC2, RetVT, Ops, 2, false/*sign irrelevant*/); + NewLHS = MakeLibCall(LC2, RetVT, Ops, 2, false/*sign irrelevant*/, dl); NewLHS = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(RetVT), NewLHS, NewRHS, DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); NewLHS = DAG.getNode(ISD::OR, Tmp.getValueType(), Tmp, NewLHS); @@ -617,13 +618,13 @@ assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND libcall"); SDValue Op = GetSoftenedFloat(N->getOperand(0)); - return MakeLibCall(LC, RVT, &Op, 1, false); + return MakeLibCall(LC, RVT, &Op, 1, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatOp_BR_CC(SDNode *N) { SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); ISD::CondCode CCCode = cast(N->getOperand(1))->get(); - SoftenSetCCOperands(NewLHS, NewRHS, CCCode); + SoftenSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); // If SoftenSetCCOperands returned a scalar, we need to compare the result // against zero to select between true and false values. @@ -643,7 +644,7 @@ RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!"); SDValue Op = GetSoftenedFloat(N->getOperand(0)); - return MakeLibCall(LC, RVT, &Op, 1, false); + return MakeLibCall(LC, RVT, &Op, 1, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_UINT(SDNode *N) { @@ -651,13 +652,13 @@ RTLIB::Libcall LC = RTLIB::getFPTOUINT(N->getOperand(0).getValueType(), RVT); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_UINT!"); SDValue Op = GetSoftenedFloat(N->getOperand(0)); - return MakeLibCall(LC, RVT, &Op, 1, false); + return MakeLibCall(LC, RVT, &Op, 1, false, N->getDebugLoc()); } SDValue DAGTypeLegalizer::SoftenFloatOp_SELECT_CC(SDNode *N) { SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); ISD::CondCode CCCode = cast(N->getOperand(4))->get(); - SoftenSetCCOperands(NewLHS, NewRHS, CCCode); + SoftenSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); // If SoftenSetCCOperands returned a scalar, we need to compare the result // against zero to select between true and false values. @@ -675,7 +676,7 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_SETCC(SDNode *N) { SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); ISD::CondCode CCCode = cast(N->getOperand(2))->get(); - SoftenSetCCOperands(NewLHS, NewRHS, CCCode); + SoftenSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); // If SoftenSetCCOperands returned a scalar, use it. if (NewRHS.getNode() == 0) { @@ -844,7 +845,8 @@ RTLIB::DIV_F64, RTLIB::DIV_F80, RTLIB::DIV_PPCF128), - N->getValueType(0), Ops, 2, false); + N->getValueType(0), Ops, 2, false, + N->getDebugLoc()); assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!"); Lo = Call.getOperand(0); Hi = Call.getOperand(1); @@ -924,7 +926,8 @@ RTLIB::MUL_F64, RTLIB::MUL_F80, RTLIB::MUL_PPCF128), - N->getValueType(0), Ops, 2, false); + N->getValueType(0), Ops, 2, false, + N->getDebugLoc()); assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!"); Lo = Call.getOperand(0); Hi = Call.getOperand(1); @@ -1020,7 +1023,8 @@ RTLIB::SUB_F64, RTLIB::SUB_F80, RTLIB::SUB_PPCF128), - N->getValueType(0), Ops, 2, false); + N->getValueType(0), Ops, 2, false, + N->getDebugLoc()); assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!"); Lo = Call.getOperand(0); Hi = Call.getOperand(1); @@ -1077,6 +1081,7 @@ SDValue Src = N->getOperand(0); MVT SrcVT = Src.getValueType(); bool isSigned = N->getOpcode() == ISD::SINT_TO_FP; + DebugLoc dl = N->getDebugLoc(); // First do an SINT_TO_FP, whether the original was signed or unsigned. // When promoting partial word types to i32 we must honor the signedness, @@ -1099,7 +1104,7 @@ } assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!"); - Hi = MakeLibCall(LC, VT, &Src, 1, true); + Hi = MakeLibCall(LC, VT, &Src, 1, true, dl); assert(Hi.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!"); Lo = Hi.getOperand(0); Hi = Hi.getOperand(1); @@ -1259,7 +1264,8 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) { MVT RVT = N->getValueType(0); - + DebugLoc dl = N->getDebugLoc(); + // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on // PPC (the libcall is not available). FIXME: Do this in a less hacky way. if (RVT == MVT::i32) { @@ -1273,11 +1279,12 @@ RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!"); - return MakeLibCall(LC, RVT, &N->getOperand(0), 1, false); + return MakeLibCall(LC, RVT, &N->getOperand(0), 1, false, dl); } SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_UINT(SDNode *N) { MVT RVT = N->getValueType(0); + DebugLoc dl = N->getDebugLoc(); // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on // PPC (the libcall is not available). FIXME: Do this in a less hacky way. @@ -1303,7 +1310,7 @@ RTLIB::Libcall LC = RTLIB::getFPTOUINT(N->getOperand(0).getValueType(), RVT); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_UINT!"); - return MakeLibCall(LC, N->getValueType(0), &N->getOperand(0), 1, false); + return MakeLibCall(LC, N->getValueType(0), &N->getOperand(0), 1, false, dl); } SDValue DAGTypeLegalizer::ExpandFloatOp_SELECT_CC(SDNode *N) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=63456&r1=63455&r2=63456&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Fri Jan 30 18:11:23 2009 @@ -1378,20 +1378,22 @@ void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, SDValue &Hi) { + DebugLoc dl = N->getDebugLoc(); MVT VT = N->getValueType(0); SDValue Op = N->getOperand(0); RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); - SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi); + SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi); } void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, SDValue &Hi) { + DebugLoc dl = N->getDebugLoc(); MVT VT = N->getValueType(0); SDValue Op = N->getOperand(0); RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); - SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi); + SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi); } void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, @@ -1516,6 +1518,7 @@ SDValue &Lo, SDValue &Hi) { MVT VT = N->getValueType(0); MVT NVT = TLI.getTypeToTransformTo(VT); + DebugLoc dl = N->getDebugLoc(); bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT); @@ -1598,12 +1601,13 @@ assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; - SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi); + SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi); } void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, SDValue &Lo, SDValue &Hi) { MVT VT = N->getValueType(0); + DebugLoc dl = N->getDebugLoc(); RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; if (VT == MVT::i32) @@ -1615,12 +1619,13 @@ assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; - SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi); + SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); } void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, SDValue &Lo, SDValue &Hi) { MVT VT = N->getValueType(0); + DebugLoc dl = N->getDebugLoc(); // If we can emit an efficient shift operation, do so now. Check to see if // the RHS is a constant. @@ -1698,7 +1703,7 @@ assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!"); SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; - SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi); + SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi); } void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, @@ -1757,6 +1762,7 @@ void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, SDValue &Lo, SDValue &Hi) { MVT VT = N->getValueType(0); + DebugLoc dl = N->getDebugLoc(); RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; if (VT == MVT::i32) @@ -1768,7 +1774,7 @@ assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; - SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi); + SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); } void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, @@ -1784,6 +1790,7 @@ void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, SDValue &Lo, SDValue &Hi) { MVT VT = N->getValueType(0); + DebugLoc dl = N->getDebugLoc(); RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; if (VT == MVT::i32) @@ -1795,12 +1802,13 @@ assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; - SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi); + SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); } void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, SDValue &Lo, SDValue &Hi) { MVT VT = N->getValueType(0); + DebugLoc dl = N->getDebugLoc(); RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; if (VT == MVT::i32) @@ -1812,7 +1820,7 @@ assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; - SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi); + SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); } void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, @@ -1899,7 +1907,8 @@ /// is shared among BR_CC, SELECT_CC, and SETCC handlers. void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS, - ISD::CondCode &CCCode) { + ISD::CondCode &CCCode, + DebugLoc dl) { SDValue LHSLo, LHSHi, RHSLo, RHSHi; GetExpandedInteger(NewLHS, LHSLo, LHSHi); GetExpandedInteger(NewRHS, RHSLo, RHSHi); @@ -1998,7 +2007,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); ISD::CondCode CCCode = cast(N->getOperand(1))->get(); - IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); + IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); // If ExpandSetCCOperands returned a scalar, we need to compare the result // against zero to select between true and false values. @@ -2016,7 +2025,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); ISD::CondCode CCCode = cast(N->getOperand(4))->get(); - IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); + IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); // If ExpandSetCCOperands returned a scalar, we need to compare the result // against zero to select between true and false values. @@ -2034,7 +2043,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); ISD::CondCode CCCode = cast(N->getOperand(2))->get(); - IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); + IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); // If ExpandSetCCOperands returned a scalar, use it. if (NewRHS.getNode() == 0) { @@ -2054,7 +2063,7 @@ RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Don't know how to expand this SINT_TO_FP!"); - return MakeLibCall(LC, DstVT, &Op, 1, true); + return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc()); } SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { @@ -2147,6 +2156,7 @@ SDValue Op = N->getOperand(0); MVT SrcVT = Op.getValueType(); MVT DstVT = N->getValueType(0); + DebugLoc dl = N->getDebugLoc(); if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ // Do a signed conversion then adjust the result. @@ -2205,5 +2215,5 @@ RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Don't know how to expand this UINT_TO_FP!"); - return MakeLibCall(LC, DstVT, &Op, 1, true); + return MakeLibCall(LC, DstVT, &Op, 1, true, dl); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=63456&r1=63455&r2=63456&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Fri Jan 30 18:11:23 2009 @@ -951,27 +951,28 @@ SDValue DAGTypeLegalizer::LibCallify(RTLIB::Libcall LC, SDNode *N, bool isSigned) { unsigned NumOps = N->getNumOperands(); + DebugLoc dl = N->getDebugLoc(); if (NumOps == 0) { - return MakeLibCall(LC, N->getValueType(0), 0, 0, isSigned); + return MakeLibCall(LC, N->getValueType(0), 0, 0, isSigned, dl); } else if (NumOps == 1) { SDValue Op = N->getOperand(0); - return MakeLibCall(LC, N->getValueType(0), &Op, 1, isSigned); + return MakeLibCall(LC, N->getValueType(0), &Op, 1, isSigned, dl); } else if (NumOps == 2) { SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; - return MakeLibCall(LC, N->getValueType(0), Ops, 2, isSigned); + return MakeLibCall(LC, N->getValueType(0), Ops, 2, isSigned, dl); } SmallVector Ops(NumOps); for (unsigned i = 0; i < NumOps; ++i) Ops[i] = N->getOperand(i); - return MakeLibCall(LC, N->getValueType(0), &Ops[0], NumOps, isSigned); + return MakeLibCall(LC, N->getValueType(0), &Ops[0], NumOps, isSigned, dl); } /// MakeLibCall - Generate a libcall taking the given operands as arguments and /// returning a result of type RetVT. SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT, const SDValue *Ops, unsigned NumOps, - bool isSigned) { + bool isSigned, DebugLoc dl) { TargetLowering::ArgListTy Args; Args.reserve(NumOps); @@ -987,11 +988,9 @@ TLI.getPointerTy()); const Type *RetTy = RetVT.getTypeForMVT(); - // FIXME pass in debug loc std::pair CallInfo = TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false, - false, CallingConv::C, false, Callee, Args, DAG, - DebugLoc::getUnknownLoc()); + false, CallingConv::C, false, Callee, Args, DAG, dl); return CallInfo.first; } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=63456&r1=63455&r2=63456&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Fri Jan 30 18:11:23 2009 @@ -196,7 +196,8 @@ SDValue JoinIntegers(SDValue Lo, SDValue Hi); SDValue LibCallify(RTLIB::Libcall LC, SDNode *N, bool isSigned); SDValue MakeLibCall(RTLIB::Libcall LC, MVT RetVT, - const SDValue *Ops, unsigned NumOps, bool isSigned); + const SDValue *Ops, unsigned NumOps, bool isSigned, + DebugLoc dl); SDValue PromoteTargetBoolean(SDValue Bool, MVT VT); void ReplaceValueWith(SDValue From, SDValue To); void ReplaceValueWithHelper(SDValue From, SDValue To); @@ -361,7 +362,7 @@ SDValue ExpandIntOp_UINT_TO_FP(SDNode *N); void IntegerExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS, - ISD::CondCode &CCCode); + ISD::CondCode &CCCode, DebugLoc dl); //===--------------------------------------------------------------------===// // Float to Integer Conversion Support: LegalizeFloatTypes.cpp @@ -426,7 +427,7 @@ SDValue SoftenFloatOp_STORE(SDNode *N, unsigned OpNo); void SoftenSetCCOperands(SDValue &NewLHS, SDValue &NewRHS, - ISD::CondCode &CCCode); + ISD::CondCode &CCCode, DebugLoc dl); //===--------------------------------------------------------------------===// // Float Expansion Support: LegalizeFloatTypes.cpp From dalej at apple.com Fri Jan 30 18:20:43 2009 From: dalej at apple.com (Dale Johannesen) Date: Sat, 31 Jan 2009 00:20:43 -0000 Subject: [llvm-commits] [llvm] r63457 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Message-ID: <200901310020.n0V0Kih0021985@zion.cs.uiuc.edu> Author: johannes Date: Fri Jan 30 18:20:43 2009 New Revision: 63457 URL: http://llvm.org/viewvc/llvm-project?rev=63457&view=rev Log: Propagate debug info. This file complete (modulo bugs) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=63457&r1=63456&r2=63457&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Fri Jan 30 18:20:43 2009 @@ -123,18 +123,21 @@ SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { // Sign-extend the new bits, and continue the assertion. SDValue Op = SExtPromotedInteger(N->getOperand(0)); - return DAG.getNode(ISD::AssertSext, Op.getValueType(), Op, N->getOperand(1)); + return DAG.getNode(ISD::AssertSext, N->getDebugLoc(), + Op.getValueType(), Op, N->getOperand(1)); } SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { // Zero the new bits, and continue the assertion. SDValue Op = ZExtPromotedInteger(N->getOperand(0)); - return DAG.getNode(ISD::AssertZext, Op.getValueType(), Op, N->getOperand(1)); + return DAG.getNode(ISD::AssertZext, N->getDebugLoc(), + Op.getValueType(), Op, N->getOperand(1)); } SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { SDValue Op2 = GetPromotedInteger(N->getOperand(2)); - SDValue Res = DAG.getAtomic(N->getOpcode(), N->getMemoryVT(), + SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), + N->getMemoryVT(), N->getChain(), N->getBasePtr(), Op2, N->getSrcValue(), N->getAlignment()); // Legalized the chain result - switch anything that used the old chain to @@ -161,6 +164,7 @@ MVT NInVT = TLI.getTypeToTransformTo(InVT); MVT OutVT = N->getValueType(0); MVT NOutVT = TLI.getTypeToTransformTo(OutVT); + DebugLoc dl = N->getDebugLoc(); switch (getTypeAction(InVT)) { default: @@ -171,17 +175,18 @@ case PromoteInteger: if (NOutVT.bitsEq(NInVT)) // The input promotes to the same size. Convert the promoted value. - return DAG.getNode(ISD::BIT_CONVERT, NOutVT, GetPromotedInteger(InOp)); + return DAG.getNode(ISD::BIT_CONVERT, dl, + NOutVT, GetPromotedInteger(InOp)); break; case SoftenFloat: // Promote the integer operand by hand. - return DAG.getNode(ISD::ANY_EXTEND, NOutVT, GetSoftenedFloat(InOp)); + return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); case ExpandInteger: case ExpandFloat: break; case ScalarizeVector: // Convert the element to an integer and promote it by hand. - return DAG.getNode(ISD::ANY_EXTEND, NOutVT, + return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, BitConvertToInteger(GetScalarizedVector(InOp))); case SplitVector: { // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split @@ -194,15 +199,15 @@ if (TLI.isBigEndian()) std::swap(Lo, Hi); - InOp = DAG.getNode(ISD::ANY_EXTEND, + InOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::getIntegerVT(NOutVT.getSizeInBits()), JoinIntegers(Lo, Hi)); - return DAG.getNode(ISD::BIT_CONVERT, NOutVT, InOp); + return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp); } case WidenVector: if (OutVT.bitsEq(NInVT)) // The input is widened to the same size. Convert to the widened value. - return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetWidenedVector(InOp)); + return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp)); } // Otherwise, lower the bit-convert to a store/load from the stack. @@ -211,26 +216,27 @@ SDValue FIPtr = DAG.CreateStackTemporary(InVT, OutVT); // Emit a store to the stack slot. - SDValue Store = DAG.getStore(DAG.getEntryNode(), InOp, FIPtr, NULL, 0); + SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, NULL, 0); // Result is an extending load from the stack slot. - return DAG.getExtLoad(ISD::EXTLOAD, NOutVT, Store, FIPtr, NULL, 0, OutVT); + return DAG.getExtLoad(ISD::EXTLOAD, dl, NOutVT, Store, FIPtr, NULL, 0, OutVT); } SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { SDValue Op = GetPromotedInteger(N->getOperand(0)); MVT OVT = N->getValueType(0); MVT NVT = Op.getValueType(); + DebugLoc dl = N->getDebugLoc(); unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); - return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op), + return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); } SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { // The pair element type may be legal, or may not promote to the same type as // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. - return DAG.getNode(ISD::ANY_EXTEND, + return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), TLI.getTypeToTransformTo(N->getValueType(0)), JoinIntegers(N->getOperand(0), N->getOperand(1))); } @@ -265,7 +271,7 @@ MVT NVT = Op.getValueType(); Op = DAG.getNode(ISD::CTLZ, NVT, Op); // Subtract off the extra leading bits in the bigger type. - return DAG.getNode(ISD::SUB, NVT, Op, + return DAG.getNode(ISD::SUB, N->getDebugLoc(), NVT, Op, DAG.getConstant(NVT.getSizeInBits() - OVT.getSizeInBits(), NVT)); } @@ -273,20 +279,21 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { // Zero extend to the promoted type and do the count there. SDValue Op = ZExtPromotedInteger(N->getOperand(0)); - return DAG.getNode(ISD::CTPOP, Op.getValueType(), Op); + return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op); } SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { SDValue Op = GetPromotedInteger(N->getOperand(0)); MVT OVT = N->getValueType(0); MVT NVT = Op.getValueType(); + DebugLoc dl = N->getDebugLoc(); // The count is the same in the promoted type except if the original // value was zero. This can be handled by setting the bit just off // the top of the original type. APInt TopBit(NVT.getSizeInBits(), 0); TopBit.set(OVT.getSizeInBits()); - Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT)); - return DAG.getNode(ISD::CTTZ, NVT, Op); + Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT)); + return DAG.getNode(ISD::CTTZ, dl, NVT, Op); } SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { @@ -295,6 +302,7 @@ if (getTypeAction(OldVec.getValueType()) == WidenVector) OldVec = GetWidenedVector(N->getOperand(0)); unsigned OldElts = OldVec.getValueType().getVectorNumElements(); + DebugLoc dl = N->getDebugLoc(); if (OldElts == 1) { assert(!isTypeLegal(OldVec.getValueType()) && @@ -302,7 +310,7 @@ // It is tempting to follow GetScalarizedVector by a call to // GetPromotedInteger, but this would be wrong because the // scalarized value may not yet have been processed. - return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT), + return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT), GetScalarizedVector(OldVec)); } @@ -312,34 +320,35 @@ MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); assert(OldVT.isSimple() && NewVT.isSimple()); - SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, + SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::getVectorVT(NewVT, OldElts / 2), OldVec); // Extract the element at OldIdx / 2 from the new vector. SDValue OldIdx = N->getOperand(1); - SDValue NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx, + SDValue NewIdx = DAG.getNode(ISD::SRL, dl, OldIdx.getValueType(), OldIdx, DAG.getConstant(1, TLI.getShiftAmountTy())); - SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx); + SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, NewIdx); // Select the appropriate half of the element: Lo if OldIdx was even, // Hi if it was odd. SDValue Lo = Elt; - SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt, + SDValue Hi = DAG.getNode(ISD::SRL, dl, NewVT, Elt, DAG.getConstant(OldVT.getSizeInBits(), TLI.getShiftAmountTy())); if (TLI.isBigEndian()) std::swap(Lo, Hi); // Extend to the promoted type. - SDValue Odd = DAG.getNode(ISD::TRUNCATE, MVT::i1, OldIdx); - SDValue Res = DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo); - return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT), Res); + SDValue Odd = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, OldIdx); + SDValue Res = DAG.getNode(ISD::SELECT, dl, NewVT, Odd, Hi, Lo); + return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT), Res); } SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); unsigned NewOpc = N->getOpcode(); + DebugLoc dl = N->getDebugLoc(); // If we're promoting a UINT to a larger size, check to see if the new node // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since @@ -351,18 +360,19 @@ TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) NewOpc = ISD::FP_TO_SINT; - SDValue Res = DAG.getNode(NewOpc, NVT, N->getOperand(0)); + SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0)); // Assert that the converted value fits in the original type. If it doesn't // (eg: because the value being converted is too big), then the result of the // original operation was undefined anyway, so the assert is still correct. return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? - ISD::AssertZext : ISD::AssertSext, + ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, DAG.getValueType(N->getValueType(0))); } SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + DebugLoc dl = N->getDebugLoc(); if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { SDValue Res = GetPromotedInteger(N->getOperand(0)); @@ -373,7 +383,7 @@ if (NVT == Res.getValueType()) { // The high bits are not guaranteed to be anything. Insert an extend. if (N->getOpcode() == ISD::SIGN_EXTEND) - return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, + return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, DAG.getValueType(N->getOperand(0).getValueType())); if (N->getOpcode() == ISD::ZERO_EXTEND) return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType()); @@ -383,7 +393,7 @@ } // Otherwise, just extend the original operand all the way to the larger type. - return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0)); + return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); } SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { @@ -391,7 +401,8 @@ MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); - SDValue Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(), + DebugLoc dl = N->getDebugLoc(); + SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(), N->getMemoryVT(), N->isVolatile(), N->getAlignment()); @@ -408,7 +419,8 @@ MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); MVT ValueVTs[] = { N->getValueType(0), NVT }; SDValue Ops[] = { N->getOperand(0), N->getOperand(1) }; - SDValue Res = DAG.getNode(N->getOpcode(), DAG.getVTList(ValueVTs, 2), Ops, 2); + SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), + DAG.getVTList(ValueVTs, 2), Ops, 2); // Modified the sum result - switch anything that used the old sum to use // the new one. @@ -427,17 +439,18 @@ SDValue RHS = SExtPromotedInteger(N->getOperand(1)); MVT OVT = N->getOperand(0).getValueType(); MVT NVT = LHS.getValueType(); + DebugLoc dl = N->getDebugLoc(); // Do the arithmetic in the larger type. unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; - SDValue Res = DAG.getNode(Opcode, NVT, LHS, RHS); + SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); // Calculate the overflow flag: sign extend the arithmetic result from // the original type. - SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, + SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, DAG.getValueType(OVT)); // Overflowed if and only if this is not equal to Res. - Ofl = DAG.getSetCC(N->getValueType(1), Ofl, Res, ISD::SETNE); + Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); // Use the calculated overflow everywhere. ReplaceValueWith(SDValue(N, 1), Ofl); @@ -449,45 +462,50 @@ // Sign extend the input. SDValue LHS = SExtPromotedInteger(N->getOperand(0)); SDValue RHS = SExtPromotedInteger(N->getOperand(1)); - return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); + return DAG.getNode(N->getOpcode(), N->getDebugLoc(), + LHS.getValueType(), LHS, RHS); } SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { SDValue LHS = GetPromotedInteger(N->getOperand(1)); SDValue RHS = GetPromotedInteger(N->getOperand(2)); - return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS); + return DAG.getNode(ISD::SELECT, N->getDebugLoc(), + LHS.getValueType(), N->getOperand(0),LHS,RHS); } SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { SDValue LHS = GetPromotedInteger(N->getOperand(2)); SDValue RHS = GetPromotedInteger(N->getOperand(3)); - return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0), + return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), + LHS.getValueType(), N->getOperand(0), N->getOperand(1), LHS, RHS, N->getOperand(4)); } SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType()); assert(isTypeLegal(SVT) && "Illegal SetCC type!"); + DebugLoc dl = N->getDebugLoc(); // Get the SETCC result using the canonical SETCC type. - SDValue SetCC = DAG.getNode(ISD::SETCC, SVT, N->getOperand(0), + SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0), N->getOperand(1), N->getOperand(2)); // Convert to the expected type. MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); - return DAG.getNode(ISD::TRUNCATE, NVT, SetCC); + return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); } SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { - return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)), + return DAG.getNode(ISD::SHL, N->getDebugLoc(), + TLI.getTypeToTransformTo(N->getValueType(0)), GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); } SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { SDValue Op = GetPromotedInteger(N->getOperand(0)); - return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, - N->getOperand(1)); + return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), + Op.getValueType(), Op, N->getOperand(1)); } SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { @@ -496,13 +514,15 @@ // that too is okay if they are integer operations. SDValue LHS = GetPromotedInteger(N->getOperand(0)); SDValue RHS = GetPromotedInteger(N->getOperand(1)); - return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); + return DAG.getNode(N->getOpcode(), N->getDebugLoc(), + LHS.getValueType(), LHS, RHS); } SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { // The input value must be properly sign extended. SDValue Res = SExtPromotedInteger(N->getOperand(0)); - return DAG.getNode(ISD::SRA, Res.getValueType(), Res, N->getOperand(1)); + return DAG.getNode(ISD::SRA, N->getDebugLoc(), + Res.getValueType(), Res, N->getOperand(1)); } SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { @@ -510,7 +530,7 @@ MVT VT = N->getValueType(0); MVT NVT = TLI.getTypeToTransformTo(VT); SDValue Res = ZExtPromotedInteger(N->getOperand(0)); - return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1)); + return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1)); } SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { @@ -529,7 +549,7 @@ } // Truncate to NVT instead of VT - return DAG.getNode(ISD::TRUNCATE, NVT, Res); + return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res); } SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) { @@ -542,16 +562,17 @@ SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); MVT OVT = N->getOperand(0).getValueType(); MVT NVT = LHS.getValueType(); + DebugLoc dl = N->getDebugLoc(); // Do the arithmetic in the larger type. unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; - SDValue Res = DAG.getNode(Opcode, NVT, LHS, RHS); + SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); // Calculate the overflow flag: zero extend the arithmetic result from // the original type. SDValue Ofl = DAG.getZeroExtendInReg(Res, OVT); // Overflowed if and only if this is not equal to Res. - Ofl = DAG.getSetCC(N->getValueType(1), Ofl, Res, ISD::SETNE); + Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); // Use the calculated overflow everywhere. ReplaceValueWith(SDValue(N, 1), Ofl); @@ -563,17 +584,20 @@ // Zero extend the input. SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); - return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); + return DAG.getNode(N->getOpcode(), N->getDebugLoc(), + LHS.getValueType(), LHS, RHS); } SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { - return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0))); + return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), + TLI.getTypeToTransformTo(N->getValueType(0))); } SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { SDValue Chain = N->getOperand(0); // Get the chain. SDValue Ptr = N->getOperand(1); // Get the pointer. MVT VT = N->getValueType(0); + DebugLoc dl = N->getDebugLoc(); MVT RegVT = TLI.getRegisterType(VT); unsigned NumRegs = TLI.getNumRegisters(VT); @@ -591,14 +615,14 @@ // Assemble the parts in the promoted type. MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); - SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[0]); + SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); for (unsigned i = 1; i < NumRegs; ++i) { - SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[i]); + SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); // Shift it to the right position and "or" it in. - Part = DAG.getNode(ISD::SHL, NVT, Part, + Part = DAG.getNode(ISD::SHL, dl, NVT, Part, DAG.getConstant(i * RegVT.getSizeInBits(), TLI.getShiftAmountTy())); - Res = DAG.getNode(ISD::OR, NVT, Res, Part); + Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part); } // Modified the chain result - switch anything that used the old chain to @@ -707,7 +731,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { SDValue Op = GetPromotedInteger(N->getOperand(0)); - return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); + return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); } SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { @@ -741,11 +765,12 @@ SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); SDValue Hi = GetPromotedInteger(N->getOperand(1)); assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); + DebugLoc dl = N->getDebugLoc(); - Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi, + Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, DAG.getConstant(OVT.getSizeInBits(), TLI.getShiftAmountTy())); - return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi); + return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi); } SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { @@ -755,6 +780,7 @@ MVT VecVT = N->getValueType(0); unsigned NumElts = VecVT.getVectorNumElements(); assert(!(NumElts & 1) && "Legal vector of one illegal element?"); + DebugLoc dl = N->getDebugLoc(); // Build a vector of half the length out of elements of twice the bitwidth. // For example <4 x i16> -> <2 x i32>. @@ -774,12 +800,12 @@ NewElts.push_back(JoinIntegers(Lo, Hi)); } - SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, + SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::getVectorVT(NewVT, NewElts.size()), &NewElts[0], NewElts.size()); // Convert the new vector to the old vector type. - return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec); + return DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, NewVec); } SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) { @@ -864,8 +890,9 @@ SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { SDValue Op = GetPromotedInteger(N->getOperand(0)); - Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); - return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), + DebugLoc dl = N->getDebugLoc(); + Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); + return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op, DAG.getValueType(N->getOperand(0).getValueType())); } @@ -880,18 +907,19 @@ int SVOffset = N->getSrcValueOffset(); unsigned Alignment = N->getAlignment(); bool isVolatile = N->isVolatile(); + DebugLoc dl = N->getDebugLoc(); SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. // Truncate the value and store the result. - return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(), + return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(), SVOffset, N->getMemoryVT(), isVolatile, Alignment); } SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { SDValue Op = GetPromotedInteger(N->getOperand(0)); - return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op); + return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op); } SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) { @@ -901,7 +929,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { SDValue Op = GetPromotedInteger(N->getOperand(0)); - Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); + Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType()); } @@ -991,6 +1019,7 @@ /// and the shift amount is a constant 'Amt'. Expand the operation. void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, SDValue &Lo, SDValue &Hi) { + DebugLoc dl = N->getDebugLoc(); // Expand the incoming operand to be shifted, so that we have its parts SDValue InL, InH; GetExpandedInteger(N->getOperand(0), InL, InH); @@ -1005,7 +1034,8 @@ Lo = Hi = DAG.getConstant(0, NVT); } else if (Amt > NVTBits) { Lo = DAG.getConstant(0, NVT); - Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); + Hi = DAG.getNode(ISD::SHL, dl, + NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); } else if (Amt == NVTBits) { Lo = DAG.getConstant(0, NVT); Hi = InL; @@ -1015,15 +1045,15 @@ // Emit this X << 1 as X+X. SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); SDValue LoOps[2] = { InL, InL }; - Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); + Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; - Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); + Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); } else { - Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy)); - Hi = DAG.getNode(ISD::OR, NVT, - DAG.getNode(ISD::SHL, NVT, InH, + Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy)); + Hi = DAG.getNode(ISD::OR, dl, NVT, + DAG.getNode(ISD::SHL, dl, NVT, InH, DAG.getConstant(Amt, ShTy)), - DAG.getNode(ISD::SRL, NVT, InL, + DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(NVTBits-Amt, ShTy))); } return; @@ -1034,42 +1064,43 @@ Lo = DAG.getConstant(0, NVT); Hi = DAG.getConstant(0, NVT); } else if (Amt > NVTBits) { - Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); + Lo = DAG.getNode(ISD::SRL, dl, + NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); Hi = DAG.getConstant(0, NVT); } else if (Amt == NVTBits) { Lo = InH; Hi = DAG.getConstant(0, NVT); } else { - Lo = DAG.getNode(ISD::OR, NVT, - DAG.getNode(ISD::SRL, NVT, InL, + Lo = DAG.getNode(ISD::OR, dl, NVT, + DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Amt, ShTy)), - DAG.getNode(ISD::SHL, NVT, InH, + DAG.getNode(ISD::SHL, dl, NVT, InH, DAG.getConstant(NVTBits-Amt, ShTy))); - Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy)); + Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy)); } return; } assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); if (Amt > VTBits) { - Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, + Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(NVTBits-1, ShTy)); } else if (Amt > NVTBits) { - Lo = DAG.getNode(ISD::SRA, NVT, InH, + Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt-NVTBits, ShTy)); - Hi = DAG.getNode(ISD::SRA, NVT, InH, + Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(NVTBits-1, ShTy)); } else if (Amt == NVTBits) { Lo = InH; - Hi = DAG.getNode(ISD::SRA, NVT, InH, + Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(NVTBits-1, ShTy)); } else { Lo = DAG.getNode(ISD::OR, NVT, - DAG.getNode(ISD::SRL, NVT, InL, + DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Amt, ShTy)), - DAG.getNode(ISD::SHL, NVT, InH, + DAG.getNode(ISD::SHL, dl, NVT, InH, DAG.getConstant(NVTBits-Amt, ShTy))); - Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy)); + Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy)); } } @@ -1086,6 +1117,7 @@ unsigned NVTBits = NVT.getSizeInBits(); assert(isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"); + DebugLoc dl = N->getDebugLoc(); APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); APInt KnownZero, KnownOne; @@ -1103,23 +1135,23 @@ // can do this as a couple of simple shifts. if (KnownOne.intersects(HighBitMask)) { // Mask out the high bit, which we know is set. - Amt = DAG.getNode(ISD::AND, ShTy, Amt, + Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt, DAG.getConstant(~HighBitMask, ShTy)); switch (N->getOpcode()) { default: assert(0 && "Unknown shift"); case ISD::SHL: Lo = DAG.getConstant(0, NVT); // Low part is zero. - Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. + Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. return true; case ISD::SRL: Hi = DAG.getConstant(0, NVT); // Hi part is zero. - Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. + Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. return true; case ISD::SRA: - Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. + Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. DAG.getConstant(NVTBits-1, ShTy)); - Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. + Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. return true; } } @@ -1154,6 +1186,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, SDValue &Lo, SDValue &Hi) { + DebugLoc dl = N->getDebugLoc(); // Expand the subcomponents. SDValue LHSL, LHSH, RHSL, RHSH; GetExpandedInteger(N->getOperand(0), LHSL, LHSH); @@ -1176,38 +1209,38 @@ if (hasCarry) { SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); if (N->getOpcode() == ISD::ADD) { - Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); + Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); HiOps[2] = Lo.getValue(1); - Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); + Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); } else { - Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); + Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); HiOps[2] = Lo.getValue(1); - Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); + Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); } } else { if (N->getOpcode() == ISD::ADD) { - Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2); - Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2); - SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(NVT), Lo, LoOps[0], + Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2); + Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2); + SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0], ISD::SETULT); - SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1, + SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1, DAG.getConstant(1, NVT), DAG.getConstant(0, NVT)); - SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(NVT), Lo, LoOps[1], + SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1], ISD::SETULT); - SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2, + SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2, DAG.getConstant(1, NVT), Carry1); - Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2); + Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2); } else { - Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2); - Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2); + Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); + Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2); SDValue Cmp = DAG.getSetCC(TLI.getSetCCResultType(LoOps[0].getValueType()), LoOps[0], LoOps[1], ISD::SETULT); - SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp, + SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, DAG.getConstant(1, NVT), DAG.getConstant(0, NVT)); - Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow); + Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow); } } } @@ -1216,6 +1249,7 @@ SDValue &Lo, SDValue &Hi) { // Expand the subcomponents. SDValue LHSL, LHSH, RHSL, RHSH; + DebugLoc dl = N->getDebugLoc(); GetExpandedInteger(N->getOperand(0), LHSL, LHSH); GetExpandedInteger(N->getOperand(1), RHSL, RHSH); SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); @@ -1223,13 +1257,13 @@ SDValue HiOps[3] = { LHSH, RHSH }; if (N->getOpcode() == ISD::ADDC) { - Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); + Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); HiOps[2] = Lo.getValue(1); - Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); + Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); } else { - Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); + Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); HiOps[2] = Lo.getValue(1); - Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); + Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); } // Legalized the flag result - switch anything that used the old flag to @@ -1241,15 +1275,16 @@ SDValue &Lo, SDValue &Hi) { // Expand the subcomponents. SDValue LHSL, LHSH, RHSL, RHSH; + DebugLoc dl = N->getDebugLoc(); GetExpandedInteger(N->getOperand(0), LHSL, LHSH); GetExpandedInteger(N->getOperand(1), RHSL, RHSH); SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; SDValue HiOps[3] = { LHSH, RHSH }; - Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3); + Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3); HiOps[2] = Lo.getValue(1); - Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3); + Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); // Legalized the flag result - switch anything that used the old flag to // use the new one. @@ -1259,11 +1294,12 @@ void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) { MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + DebugLoc dl = N->getDebugLoc(); SDValue Op = N->getOperand(0); if (Op.getValueType().bitsLE(NVT)) { // The low part is any extension of the input (which degenerates to a copy). - Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op); - Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined. + Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op); + Hi = DAG.getNode(ISD::UNDEF, dl, NVT); // The high part is undefined. } else { // For example, extension of an i48 to an i64. The operand type necessarily // promotes to the result type, so will end up being expanded too. @@ -1279,6 +1315,7 @@ void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, SDValue &Lo, SDValue &Hi) { + DebugLoc dl = N->getDebugLoc(); GetExpandedInteger(N->getOperand(0), Lo, Hi); MVT NVT = Lo.getValueType(); MVT EVT = cast(N->getOperand(1))->getVT(); @@ -1286,18 +1323,19 @@ unsigned EVTBits = EVT.getSizeInBits(); if (NVTBits < EVTBits) { - Hi = DAG.getNode(ISD::AssertSext, NVT, Hi, + Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); } else { - Lo = DAG.getNode(ISD::AssertSext, NVT, Lo, DAG.getValueType(EVT)); + Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); // The high part replicates the sign bit of Lo, make it explicit. - Hi = DAG.getNode(ISD::SRA, NVT, Lo, + Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy())); } } void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, SDValue &Lo, SDValue &Hi) { + DebugLoc dl = N->getDebugLoc(); GetExpandedInteger(N->getOperand(0), Lo, Hi); MVT NVT = Lo.getValueType(); MVT EVT = cast(N->getOperand(1))->getVT(); @@ -1305,10 +1343,10 @@ unsigned EVTBits = EVT.getSizeInBits(); if (NVTBits < EVTBits) { - Hi = DAG.getNode(ISD::AssertZext, NVT, Hi, + Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); } else { - Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT)); + Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); // The high part must be zero, make it explicit. Hi = DAG.getConstant(0, NVT); } @@ -1316,9 +1354,10 @@ void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, SDValue &Lo, SDValue &Hi) { + DebugLoc dl = N->getDebugLoc(); GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. - Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo); - Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi); + Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo); + Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi); } void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, @@ -1332,46 +1371,49 @@ void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, SDValue &Lo, SDValue &Hi) { + DebugLoc dl = N->getDebugLoc(); // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) GetExpandedInteger(N->getOperand(0), Lo, Hi); MVT NVT = Lo.getValueType(); - SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), Hi, + SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi, DAG.getConstant(0, NVT), ISD::SETNE); - SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo); - SDValue HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); + SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo); + SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi); - Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ, - DAG.getNode(ISD::ADD, NVT, LoLZ, + Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ, + DAG.getNode(ISD::ADD, dl, NVT, LoLZ, DAG.getConstant(NVT.getSizeInBits(), NVT))); Hi = DAG.getConstant(0, NVT); } void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, SDValue &Lo, SDValue &Hi) { + DebugLoc dl = N->getDebugLoc(); // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) GetExpandedInteger(N->getOperand(0), Lo, Hi); MVT NVT = Lo.getValueType(); - Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo), - DAG.getNode(ISD::CTPOP, NVT, Hi)); + Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo), + DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); Hi = DAG.getConstant(0, NVT); } void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, SDValue &Lo, SDValue &Hi) { + DebugLoc dl = N->getDebugLoc(); // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) GetExpandedInteger(N->getOperand(0), Lo, Hi); MVT NVT = Lo.getValueType(); - SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), Lo, + SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, DAG.getConstant(0, NVT), ISD::SETNE); - SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo); - SDValue HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi); + SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo); + SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi); - Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ, - DAG.getNode(ISD::ADD, NVT, HiLZ, + Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ, + DAG.getNode(ISD::ADD, dl, NVT, HiLZ, DAG.getConstant(NVT.getSizeInBits(), NVT))); Hi = DAG.getConstant(0, NVT); } @@ -1413,14 +1455,15 @@ int SVOffset = N->getSrcValueOffset(); unsigned Alignment = N->getAlignment(); bool isVolatile = N->isVolatile(); + DebugLoc dl = N->getDebugLoc(); assert(NVT.isByteSized() && "Expanded type not byte sized!"); if (N->getMemoryVT().bitsLE(NVT)) { MVT EVT = N->getMemoryVT(); - Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT, - isVolatile, Alignment); + Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, + EVT, isVolatile, Alignment); // Remember the chain. Ch = Lo.getValue(1); @@ -1429,7 +1472,7 @@ // The high part is obtained by SRA'ing all but one of the bits of the // lo part. unsigned LoSize = Lo.getValueType().getSizeInBits(); - Hi = DAG.getNode(ISD::SRA, NVT, Lo, + Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); } else if (ExtType == ISD::ZEXTLOAD) { // The high part is just a zero. @@ -1437,11 +1480,11 @@ } else { assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); // The high part is undefined. - Hi = DAG.getNode(ISD::UNDEF, NVT); + Hi = DAG.getNode(ISD::UNDEF, dl, NVT); } } else if (TLI.isLittleEndian()) { // Little-endian - low bits are at low addresses. - Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset, + Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset, isVolatile, Alignment); unsigned ExcessBits = @@ -1450,15 +1493,15 @@ // Increment the pointer to the other half. unsigned IncrementSize = NVT.getSizeInBits()/8; - Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, + Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); - Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), + Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset+IncrementSize, NEVT, isVolatile, MinAlign(Alignment, IncrementSize)); // Build a factor node to remember that this load is independent of the // other one. - Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), + Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), Hi.getValue(1)); } else { // Big-endian - high bits are at low addresses. Favor aligned loads at @@ -1469,32 +1512,33 @@ unsigned ExcessBits = (EBytes - IncrementSize)*8; // Load both the high bits and maybe some of the low bits. - Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, + Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), isVolatile, Alignment); // Increment the pointer to the other half. - Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, + Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); // Load the rest of the low bits. - Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(), + Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset+IncrementSize, MVT::getIntegerVT(ExcessBits), isVolatile, MinAlign(Alignment, IncrementSize)); // Build a factor node to remember that this load is independent of the // other one. - Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), + Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), Hi.getValue(1)); if (ExcessBits < NVT.getSizeInBits()) { // Transfer low bits from the bottom of Hi to the top of Lo. - Lo = DAG.getNode(ISD::OR, NVT, Lo, - DAG.getNode(ISD::SHL, NVT, Hi, + Lo = DAG.getNode(ISD::OR, dl, NVT, Lo, + DAG.getNode(ISD::SHL, dl, NVT, Hi, DAG.getConstant(ExcessBits, TLI.getShiftAmountTy()))); // Move high bits to the right position in Hi. - Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi, + Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, + NVT, Hi, DAG.getConstant(NVT.getSizeInBits() - ExcessBits, TLI.getShiftAmountTy())); } @@ -1507,11 +1551,12 @@ void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, SDValue &Lo, SDValue &Hi) { + DebugLoc dl = N->getDebugLoc(); SDValue LL, LH, RL, RH; GetExpandedInteger(N->getOperand(0), LL, LH); GetExpandedInteger(N->getOperand(1), RL, RH); - Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL); - Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH); + Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL); + Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH); } void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, @@ -1539,14 +1584,14 @@ // The inputs are both zero-extended. if (HasUMUL_LOHI) { // We can emit a umul_lohi. - Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); + Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); Hi = SDValue(Lo.getNode(), 1); return; } if (HasMULHU) { // We can emit a mulhu+mul. - Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); - Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); + Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); + Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); return; } } @@ -1554,36 +1599,36 @@ // The input values are both sign-extended. if (HasSMUL_LOHI) { // We can emit a smul_lohi. - Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); + Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); Hi = SDValue(Lo.getNode(), 1); return; } if (HasMULHS) { // We can emit a mulhs+mul. - Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); - Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); + Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); + Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL); return; } } if (HasUMUL_LOHI) { // Lo,Hi = umul LHS, RHS. - SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, + SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); Lo = UMulLOHI; Hi = UMulLOHI.getValue(1); - RH = DAG.getNode(ISD::MUL, NVT, LL, RH); - LH = DAG.getNode(ISD::MUL, NVT, LH, RL); - Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); - Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); + RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); + LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); + Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); + Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); return; } if (HasMULHU) { - Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); - Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); - RH = DAG.getNode(ISD::MUL, NVT, LL, RH); - LH = DAG.getNode(ISD::MUL, NVT, LH, RL); - Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); - Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); + Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); + Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); + RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); + LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); + Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); + Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); return; } } @@ -1660,7 +1705,7 @@ SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; MVT VT = LHSL.getValueType(); - Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); + Lo = DAG.getNode(PartsOpc, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); Hi = Lo.getValue(1); return; } @@ -1709,13 +1754,14 @@ void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) { MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + DebugLoc dl = N->getDebugLoc(); SDValue Op = N->getOperand(0); if (Op.getValueType().bitsLE(NVT)) { // The low part is sign extension of the input (degenerates to a copy). - Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0)); + Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0)); // The high part is obtained by SRA'ing all but one of the bits of low part. unsigned LoSize = NVT.getSizeInBits(); - Hi = DAG.getNode(ISD::SRA, NVT, Lo, + Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); } else { // For example, extension of an i48 to an i64. The operand type necessarily @@ -1729,24 +1775,25 @@ SplitInteger(Res, Lo, Hi); unsigned ExcessBits = Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); - Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, + Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, DAG.getValueType(MVT::getIntegerVT(ExcessBits))); } } void DAGTypeLegalizer:: ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { + DebugLoc dl = N->getDebugLoc(); GetExpandedInteger(N->getOperand(0), Lo, Hi); MVT EVT = cast(N->getOperand(1))->getVT(); if (EVT.bitsLE(Lo.getValueType())) { // sext_inreg the low part if needed. - Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo, + Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, N->getOperand(1)); // The high part gets the sign extension from the lo-part. This handles // things like sextinreg V:i64 from i8. - Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo, + Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo, DAG.getConstant(Hi.getValueType().getSizeInBits()-1, TLI.getShiftAmountTy())); } else { @@ -1754,7 +1801,7 @@ // sext_inreg the high part. unsigned ExcessBits = EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); - Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, + Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, DAG.getValueType(MVT::getIntegerVT(ExcessBits))); } } @@ -1780,11 +1827,13 @@ void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, SDValue &Lo, SDValue &Hi) { MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); - Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0)); - Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0), + DebugLoc dl = N->getDebugLoc(); + Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); + Hi = DAG.getNode(ISD::SRL, dl, + N->getOperand(0).getValueType(), N->getOperand(0), DAG.getConstant(NVT.getSizeInBits(), TLI.getShiftAmountTy())); - Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi); + Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); } void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, @@ -1826,10 +1875,11 @@ void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) { MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + DebugLoc dl = N->getDebugLoc(); SDValue Op = N->getOperand(0); if (Op.getValueType().bitsLE(NVT)) { // The low part is zero extension of the input (degenerates to a copy). - Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0)); + Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0)); Hi = DAG.getConstant(0, NVT); // The high part is just a zero. } else { // For example, extension of an i48 to an i64. The operand type necessarily @@ -1920,16 +1970,17 @@ if (ConstantSDNode *RHSCST = dyn_cast(RHSLo)) { if (RHSCST->isAllOnesValue()) { // Equality comparison to -1. - NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); + NewLHS = DAG.getNode(ISD::AND, dl, + LHSLo.getValueType(), LHSLo, LHSHi); NewRHS = RHSLo; return; } } } - NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); - NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); - NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS); + NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo); + NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi); + NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS); NewRHS = DAG.getConstant(0, NewLHS.getValueType()); return; } @@ -1969,12 +2020,13 @@ Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()), LHSLo, RHSLo, LowCC, false, DagCombineInfo); if (!Tmp1.getNode()) - Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()), + Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), LHSLo, RHSLo, LowCC); Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), LHSHi, RHSHi, CCCode, false, DagCombineInfo); if (!Tmp2.getNode()) - Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi.getValueType()), + Tmp2 = DAG.getNode(ISD::SETCC, dl, + TLI.getSetCCResultType(LHSHi.getValueType()), LHSHi, RHSHi, DAG.getCondCode(CCCode)); ConstantSDNode *Tmp1C = dyn_cast(Tmp1.getNode()); @@ -1997,9 +2049,9 @@ NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), LHSHi, RHSHi, ISD::SETEQ, false, DagCombineInfo); if (!NewLHS.getNode()) - NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()), + NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), LHSHi, RHSHi, ISD::SETEQ); - NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(), + NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(), NewLHS, Tmp1, Tmp2); NewRHS = SDValue(); } @@ -2080,19 +2132,20 @@ int SVOffset = N->getSrcValueOffset(); unsigned Alignment = N->getAlignment(); bool isVolatile = N->isVolatile(); + DebugLoc dl = N->getDebugLoc(); SDValue Lo, Hi; assert(NVT.isByteSized() && "Expanded type not byte sized!"); if (N->getMemoryVT().bitsLE(NVT)) { GetExpandedInteger(N->getValue(), Lo, Hi); - return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, + return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset, N->getMemoryVT(), isVolatile, Alignment); } else if (TLI.isLittleEndian()) { // Little-endian - low bits are at low addresses. GetExpandedInteger(N->getValue(), Lo, Hi); - Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, + Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset, isVolatile, Alignment); unsigned ExcessBits = @@ -2101,12 +2154,12 @@ // Increment the pointer to the other half. unsigned IncrementSize = NVT.getSizeInBits()/8; - Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, + Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); - Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), + Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize, NEVT, isVolatile, MinAlign(Alignment, IncrementSize)); - return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); } else { // Big-endian - high bits are at low addresses. Favor aligned stores at // the cost of some bit-fiddling. @@ -2120,28 +2173,28 @@ if (ExcessBits < NVT.getSizeInBits()) { // Transfer high bits from the top of Lo to the bottom of Hi. - Hi = DAG.getNode(ISD::SHL, NVT, Hi, + Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi, DAG.getConstant(NVT.getSizeInBits() - ExcessBits, TLI.getShiftAmountTy())); - Hi = DAG.getNode(ISD::OR, NVT, Hi, + Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, DAG.getNode(ISD::SRL, NVT, Lo, DAG.getConstant(ExcessBits, TLI.getShiftAmountTy()))); } // Store both the high bits and maybe some of the low bits. - Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), + Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset, HiVT, isVolatile, Alignment); // Increment the pointer to the other half. - Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, + Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); // Store the lowest ExcessBits bits in the second half. - Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), + Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset+IncrementSize, MVT::getIntegerVT(ExcessBits), isVolatile, MinAlign(Alignment, IncrementSize)); - return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); } } @@ -2149,7 +2202,7 @@ SDValue InL, InH; GetExpandedInteger(N->getOperand(0), InL, InH); // Just truncate the low part of the source. - return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL); + return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL); } SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { @@ -2160,7 +2213,7 @@ if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ // Do a signed conversion then adjust the result. - SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op); + SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); SignedConv = TLI.LowerOperation(SignedConv, DAG); // The result of the signed conversion needs adjusting if the 'sign bit' of @@ -2184,7 +2237,8 @@ // Check whether the sign bit is set. SDValue Lo, Hi; GetExpandedInteger(Op, Lo, Hi); - SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi.getValueType()), + SDValue SignSet = DAG.getSetCC(dl, + TLI.getSetCCResultType(Hi.getValueType()), Hi, DAG.getConstant(0, Hi.getValueType()), ISD::SETLT); @@ -2196,19 +2250,19 @@ SDValue Zero = DAG.getIntPtrConstant(0); SDValue Four = DAG.getIntPtrConstant(4); if (TLI.isBigEndian()) std::swap(Zero, Four); - SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet, + SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, Zero, Four); unsigned Alignment = 1 << cast(FudgePtr)->getAlignment(); - FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset); + FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset); Alignment = std::min(Alignment, 4u); // Load the value out, extending it from f32 to the destination float type. // FIXME: Avoid the extend by constructing the right constant pool? - SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(), + SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), FudgePtr, NULL, 0, MVT::f32, false, Alignment); - return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge); + return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); } // Otherwise, use a libcall. From dalej at apple.com Fri Jan 30 18:43:08 2009 From: dalej at apple.com (Dale Johannesen) Date: Sat, 31 Jan 2009 00:43:08 -0000 Subject: [llvm-commits] [llvm] r63458 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeFloatTypes.cpp LegalizeTypes.h Message-ID: <200901310043.n0V0h86N022577@zion.cs.uiuc.edu> Author: johannes Date: Fri Jan 30 18:43:08 2009 New Revision: 63458 URL: http://llvm.org/viewvc/llvm-project?rev=63458&view=rev Log: Propagate debug info in LegalizeFloatTypes. Complete (modulo bugs). Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=63458&r1=63457&r2=63458&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Fri Jan 30 18:43:08 2009 @@ -101,7 +101,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) { // Convert the inputs to integers, and build a new pair out of them. - return DAG.getNode(ISD::BUILD_PAIR, + return DAG.getNode(ISD::BUILD_PAIR, N->getDebugLoc(), TLI.getTypeToTransformTo(N->getValueType(0)), BitConvertToInteger(N->getOperand(0)), BitConvertToInteger(N->getOperand(1))); @@ -120,7 +120,7 @@ SDValue Mask = DAG.getConstant(APInt::getAllOnesValue(Size).clear(Size-1), NVT); SDValue Op = GetSoftenedFloat(N->getOperand(0)); - return DAG.getNode(ISD::AND, NVT, Op, Mask); + return DAG.getNode(ISD::AND, N->getDebugLoc(), NVT, Op, Mask); } SDValue DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) { @@ -149,6 +149,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) { SDValue LHS = GetSoftenedFloat(N->getOperand(0)); SDValue RHS = BitConvertToInteger(N->getOperand(1)); + DebugLoc dl = N->getDebugLoc(); MVT LVT = LHS.getValueType(); MVT RVT = RHS.getValueType(); @@ -157,32 +158,32 @@ unsigned RSize = RVT.getSizeInBits(); // First get the sign bit of second operand. - SDValue SignBit = DAG.getNode(ISD::SHL, RVT, DAG.getConstant(1, RVT), + SDValue SignBit = DAG.getNode(ISD::SHL, dl, RVT, DAG.getConstant(1, RVT), DAG.getConstant(RSize - 1, TLI.getShiftAmountTy())); - SignBit = DAG.getNode(ISD::AND, RVT, RHS, SignBit); + SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit); // Shift right or sign-extend it if the two operands have different types. int SizeDiff = RVT.getSizeInBits() - LVT.getSizeInBits(); if (SizeDiff > 0) { - SignBit = DAG.getNode(ISD::SRL, RVT, SignBit, + SignBit = DAG.getNode(ISD::SRL, dl, RVT, SignBit, DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); - SignBit = DAG.getNode(ISD::TRUNCATE, LVT, SignBit); + SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit); } else if (SizeDiff < 0) { - SignBit = DAG.getNode(ISD::ANY_EXTEND, LVT, SignBit); - SignBit = DAG.getNode(ISD::SHL, LVT, SignBit, + SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit); + SignBit = DAG.getNode(ISD::SHL, dl, LVT, SignBit, DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy())); } // Clear the sign bit of the first operand. - SDValue Mask = DAG.getNode(ISD::SHL, LVT, DAG.getConstant(1, LVT), + SDValue Mask = DAG.getNode(ISD::SHL, dl, LVT, DAG.getConstant(1, LVT), DAG.getConstant(LSize - 1, TLI.getShiftAmountTy())); - Mask = DAG.getNode(ISD::SUB, LVT, Mask, DAG.getConstant(1, LVT)); - LHS = DAG.getNode(ISD::AND, LVT, LHS, Mask); + Mask = DAG.getNode(ISD::SUB, dl, LVT, Mask, DAG.getConstant(1, LVT)); + LHS = DAG.getNode(ISD::AND, dl, LVT, LHS, Mask); // Or the value with the sign bit. - return DAG.getNode(ISD::OR, LVT, LHS, SignBit); + return DAG.getNode(ISD::OR, dl, LVT, LHS, SignBit); } SDValue DAGTypeLegalizer::SoftenFloatRes_FCOS(SDNode *N) { @@ -411,10 +412,11 @@ LoadSDNode *L = cast(N); MVT VT = N->getValueType(0); MVT NVT = TLI.getTypeToTransformTo(VT); + DebugLoc dl = N->getDebugLoc(); SDValue NewL; if (L->getExtensionType() == ISD::NON_EXTLOAD) { - NewL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), + NewL = DAG.getLoad(L->getAddressingMode(), dl, L->getExtensionType(), NVT, L->getChain(), L->getBasePtr(), L->getOffset(), L->getSrcValue(), L->getSrcValueOffset(), NVT, L->isVolatile(), L->getAlignment()); @@ -425,7 +427,7 @@ } // Do a non-extending load followed by FP_EXTEND. - NewL = DAG.getLoad(L->getAddressingMode(), ISD::NON_EXTLOAD, + NewL = DAG.getLoad(L->getAddressingMode(), dl, ISD::NON_EXTLOAD, L->getMemoryVT(), L->getChain(), L->getBasePtr(), L->getOffset(), L->getSrcValue(), L->getSrcValueOffset(), @@ -434,19 +436,21 @@ // Legalized the chain result - switch anything that used the old chain to // use the new one. ReplaceValueWith(SDValue(N, 1), NewL.getValue(1)); - return BitConvertToInteger(DAG.getNode(ISD::FP_EXTEND, VT, NewL)); + return BitConvertToInteger(DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL)); } SDValue DAGTypeLegalizer::SoftenFloatRes_SELECT(SDNode *N) { SDValue LHS = GetSoftenedFloat(N->getOperand(1)); SDValue RHS = GetSoftenedFloat(N->getOperand(2)); - return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS); + return DAG.getNode(ISD::SELECT, N->getDebugLoc(), + LHS.getValueType(), N->getOperand(0),LHS,RHS); } SDValue DAGTypeLegalizer::SoftenFloatRes_SELECT_CC(SDNode *N) { SDValue LHS = GetSoftenedFloat(N->getOperand(2)); SDValue RHS = GetSoftenedFloat(N->getOperand(3)); - return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0), + return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), + LHS.getValueType(), N->getOperand(0), N->getOperand(1), LHS, RHS, N->getOperand(4)); } @@ -471,7 +475,7 @@ assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!"); // Sign/zero extend the argument if the libcall takes a larger type. - SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, + SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0)); return MakeLibCall(LC, TLI.getTypeToTransformTo(RVT), &Op, 1, false, dl); } @@ -595,18 +599,18 @@ NewRHS = DAG.getConstant(0, RetVT); CCCode = TLI.getCmpLibcallCC(LC1); if (LC2 != RTLIB::UNKNOWN_LIBCALL) { - SDValue Tmp = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(RetVT), + SDValue Tmp = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT), NewLHS, NewRHS, DAG.getCondCode(CCCode)); NewLHS = MakeLibCall(LC2, RetVT, Ops, 2, false/*sign irrelevant*/, dl); - NewLHS = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(RetVT), NewLHS, + NewLHS = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT), NewLHS, NewRHS, DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); - NewLHS = DAG.getNode(ISD::OR, Tmp.getValueType(), Tmp, NewLHS); + NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS); NewRHS = SDValue(); } } SDValue DAGTypeLegalizer::SoftenFloatOp_BIT_CONVERT(SDNode *N) { - return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), + return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), N->getValueType(0), GetSoftenedFloat(N->getOperand(0))); } @@ -695,15 +699,16 @@ assert(OpNo == 1 && "Can only soften the stored value!"); StoreSDNode *ST = cast(N); SDValue Val = ST->getValue(); + DebugLoc dl = N->getDebugLoc(); if (ST->isTruncatingStore()) // Do an FP_ROUND followed by a non-truncating store. - Val = BitConvertToInteger(DAG.getNode(ISD::FP_ROUND, ST->getMemoryVT(), + Val = BitConvertToInteger(DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(), Val, DAG.getIntPtrConstant(0))); else Val = GetSoftenedFloat(Val); - return DAG.getStore(ST->getChain(), Val, ST->getBasePtr(), + return DAG.getStore(ST->getChain(), dl, Val, ST->getBasePtr(), ST->getSrcValue(), ST->getSrcValueOffset(), ST->isVolatile(), ST->getAlignment()); } @@ -795,12 +800,13 @@ SDValue &Hi) { assert(N->getValueType(0) == MVT::ppcf128 && "Logic only correct for ppcf128!"); + DebugLoc dl = N->getDebugLoc(); SDValue Tmp; GetExpandedFloat(N->getOperand(0), Lo, Tmp); - Hi = DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp); + Hi = DAG.getNode(ISD::FABS, dl, Tmp.getValueType(), Tmp); // Lo = Hi==fabs(Hi) ? Lo : -Lo; - Lo = DAG.getNode(ISD::SELECT_CC, Lo.getValueType(), Tmp, Hi, Lo, - DAG.getNode(ISD::FNEG, Lo.getValueType(), Lo), + Lo = DAG.getNode(ISD::SELECT_CC, dl, Lo.getValueType(), Tmp, Hi, Lo, + DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo), DAG.getCondCode(ISD::SETEQ)); } @@ -948,15 +954,16 @@ void DAGTypeLegalizer::ExpandFloatRes_FNEG(SDNode *N, SDValue &Lo, SDValue &Hi) { + DebugLoc dl = N->getDebugLoc(); GetExpandedFloat(N->getOperand(0), Lo, Hi); - Lo = DAG.getNode(ISD::FNEG, Lo.getValueType(), Lo); - Hi = DAG.getNode(ISD::FNEG, Hi.getValueType(), Hi); + Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo); + Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi); } void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) { MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); - Hi = DAG.getNode(ISD::FP_EXTEND, NVT, N->getOperand(0)); + Hi = DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), NVT, N->getOperand(0)); Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT); } @@ -1052,12 +1059,13 @@ LoadSDNode *LD = cast(N); SDValue Chain = LD->getChain(); SDValue Ptr = LD->getBasePtr(); + DebugLoc dl = N->getDebugLoc(); MVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0)); assert(NVT.isByteSized() && "Expanded type not byte sized!"); assert(LD->getMemoryVT().bitsLE(NVT) && "Float type not round?"); - Hi = DAG.getExtLoad(LD->getExtensionType(), NVT, Chain, Ptr, + Hi = DAG.getExtLoad(LD->getExtensionType(), dl, NVT, Chain, Ptr, LD->getSrcValue(), LD->getSrcValueOffset(), LD->getMemoryVT(), LD->isVolatile(), LD->getAlignment()); @@ -1088,14 +1096,14 @@ // though. if (SrcVT.bitsLE(MVT::i32)) { // The integer can be represented exactly in an f64. - Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, + Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, MVT::i32, Src); Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT); - Hi = DAG.getNode(ISD::SINT_TO_FP, NVT, Src); + Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src); } else { RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; if (SrcVT.bitsLE(MVT::i64)) { - Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, + Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, MVT::i64, Src); LC = RTLIB::SINTTOFP_I64_PPCF128; } else if (SrcVT.bitsLE(MVT::i128)) { @@ -1114,7 +1122,7 @@ return; // Unsigned - fix up the SINT_TO_FP value just calculated. - Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); + Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi); SrcVT = Src.getValueType(); // x>=0 ? (ppcf128)(iN)x : (ppcf128)(iN)x + 2^N; N=32,64,128. @@ -1137,13 +1145,13 @@ break; } - Lo = DAG.getNode(ISD::FADD, VT, Hi, + Lo = DAG.getNode(ISD::FADD, dl, VT, Hi, DAG.getConstantFP(APFloat(APInt(128, 2, Parts)), MVT::ppcf128)); - Lo = DAG.getNode(ISD::SELECT_CC, VT, Src, DAG.getConstant(0, SrcVT), Lo, Hi, - DAG.getCondCode(ISD::SETLT)); - Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Lo, DAG.getIntPtrConstant(1)); - Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Lo, DAG.getIntPtrConstant(0)); + Lo = DAG.getNode(ISD::SELECT_CC, dl, VT, Src, DAG.getConstant(0, SrcVT), + Lo, Hi, DAG.getCondCode(ISD::SETLT)); + Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Lo, DAG.getIntPtrConstant(1)); + Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Lo, DAG.getIntPtrConstant(0)); } @@ -1207,7 +1215,8 @@ /// is shared among BR_CC, SELECT_CC, and SETCC handlers. void DAGTypeLegalizer::FloatExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS, - ISD::CondCode &CCCode) { + ISD::CondCode &CCCode, + DebugLoc dl) { SDValue LHSLo, LHSHi, RHSLo, RHSHi; GetExpandedFloat(NewLHS, LHSLo, LHSHi); GetExpandedFloat(NewRHS, RHSLo, RHSHi); @@ -1221,24 +1230,24 @@ // FCMPU crN, lo1, lo2 // The following can be improved, but not that much. SDValue Tmp1, Tmp2, Tmp3; - Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()), + Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), LHSHi, RHSHi, ISD::SETOEQ); - Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()), + Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), LHSLo, RHSLo, CCCode); - Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); - Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()), + Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); + Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), LHSHi, RHSHi, ISD::SETUNE); - Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()), + Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), LHSHi, RHSHi, CCCode); - Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); - NewLHS = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); + Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); + NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3); NewRHS = SDValue(); // LHS is the result, not a compare. } SDValue DAGTypeLegalizer::ExpandFloatOp_BR_CC(SDNode *N) { SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); ISD::CondCode CCCode = cast(N->getOperand(1))->get(); - FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode); + FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); // If ExpandSetCCOperands returned a scalar, we need to compare the result // against zero to select between true and false values. @@ -1259,7 +1268,8 @@ SDValue Lo, Hi; GetExpandedFloat(N->getOperand(0), Lo, Hi); // Round it the rest of the way (e.g. to f32) if needed. - return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Hi, N->getOperand(1)); + return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), + N->getValueType(0), Hi, N->getOperand(1)); } SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) { @@ -1271,10 +1281,11 @@ if (RVT == MVT::i32) { assert(N->getOperand(0).getValueType() == MVT::ppcf128 && "Logic only correct for ppcf128!"); - SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, + SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128, N->getOperand(0), DAG.getValueType(MVT::f64)); - Res = DAG.getNode(ISD::FP_ROUND, MVT::f64, Res, DAG.getIntPtrConstant(1)); - return DAG.getNode(ISD::FP_TO_SINT, MVT::i32, Res); + Res = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Res, + DAG.getIntPtrConstant(1)); + return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res); } RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT); @@ -1296,15 +1307,16 @@ SDValue Tmp = DAG.getConstantFP(APF, MVT::ppcf128); // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X // FIXME: generated code sucks. - return DAG.getNode(ISD::SELECT_CC, MVT::i32, N->getOperand(0), Tmp, - DAG.getNode(ISD::ADD, MVT::i32, - DAG.getNode(ISD::FP_TO_SINT, MVT::i32, - DAG.getNode(ISD::FSUB, + return DAG.getNode(ISD::SELECT_CC, dl, MVT::i32, N->getOperand(0), Tmp, + DAG.getNode(ISD::ADD, dl, MVT::i32, + DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, + DAG.getNode(ISD::FSUB, dl, MVT::ppcf128, N->getOperand(0), Tmp)), DAG.getConstant(0x80000000, MVT::i32)), - DAG.getNode(ISD::FP_TO_SINT, MVT::i32, N->getOperand(0)), + DAG.getNode(ISD::FP_TO_SINT, dl, + MVT::i32, N->getOperand(0)), DAG.getCondCode(ISD::SETGE)); } @@ -1316,7 +1328,7 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_SELECT_CC(SDNode *N) { SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); ISD::CondCode CCCode = cast(N->getOperand(4))->get(); - FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode); + FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); // If ExpandSetCCOperands returned a scalar, we need to compare the result // against zero to select between true and false values. @@ -1334,7 +1346,7 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_SETCC(SDNode *N) { SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); ISD::CondCode CCCode = cast(N->getOperand(2))->get(); - FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode); + FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); // If ExpandSetCCOperands returned a scalar, use it. if (NewRHS.getNode() == 0) { @@ -1366,7 +1378,7 @@ SDValue Lo, Hi; GetExpandedOp(ST->getValue(), Lo, Hi); - return DAG.getTruncStore(Chain, Hi, Ptr, + return DAG.getTruncStore(Chain, N->getDebugLoc(), Hi, Ptr, ST->getSrcValue(), ST->getSrcValueOffset(), ST->getMemoryVT(), ST->isVolatile(), ST->getAlignment()); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=63458&r1=63457&r2=63458&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Fri Jan 30 18:43:08 2009 @@ -481,7 +481,7 @@ SDValue ExpandFloatOp_STORE(SDNode *N, unsigned OpNo); void FloatExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS, - ISD::CondCode &CCCode); + ISD::CondCode &CCCode, DebugLoc dl); //===--------------------------------------------------------------------===// // Scalarization Support: LegalizeVectorTypes.cpp From ggreif at gmail.com Fri Jan 30 18:58:14 2009 From: ggreif at gmail.com (Gabor Greif) Date: Sat, 31 Jan 2009 00:58:14 -0000 Subject: [llvm-commits] [llvm] r63459 - /llvm/trunk/lib/VMCore/AsmWriter.cpp Message-ID: <200901310058.n0V0wFM9023038@zion.cs.uiuc.edu> Author: ggreif Date: Fri Jan 30 18:58:14 2009 New Revision: 63459 URL: http://llvm.org/viewvc/llvm-project?rev=63459&view=rev Log: use precise accessors Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=63459&r1=63458&r2=63459&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Fri Jan 30 18:58:14 2009 @@ -1505,13 +1505,14 @@ const Value *Operand = I.getNumOperands() ? I.getOperand(0) : 0; // Special case conditional branches to swizzle the condition out to the front - if (isa(I) && I.getNumOperands() > 1) { + if (isa(I) && cast(I).isConditional()) { + BranchInst &BI(cast(I)); Out << ' '; - writeOperand(I.getOperand(2), true); + writeOperand(BI.getCondition(), true); Out << ", "; - writeOperand(Operand, true); + writeOperand(BI.getSuccessor(0), true); Out << ", "; - writeOperand(I.getOperand(1), true); + writeOperand(BI.getSuccessor(1), true); } else if (isa(I)) { // Special case switch statement to get formatting nice and correct... From mrs at apple.com Fri Jan 30 19:05:28 2009 From: mrs at apple.com (Mike Stump) Date: Fri, 30 Jan 2009 17:05:28 -0800 Subject: [llvm-commits] [llvm] r63384 - in /llvm/trunk: include/llvm/Support/CommandLine.h lib/Support/CommandLine.cpp In-Reply-To: References: <200901300819.n0U8JkUt008727@zion.cs.uiuc.edu> <5F0660E8-D815-494B-A7F3-A6B9B16DD4E3@apple.com> <13E450F0-4D23-43FF-B876-4DBBF8807BC3@apple.com> Message-ID: <2D103AC2-3298-401B-9822-72E5502ADAEF@apple.com> On Jan 30, 2009, at 10:54 AM, Chris Lattner wrote: >> On Jan 30, 2009, at 10:00 AM, Chris Lattner wrote: >>> Please revert this patch in the meantime, thanks! >> >> Any objection to just fixing it? > > What do you mean? Tweaking the interface to be as you requested.... The typical usage would look like: static llvm::cl::opt EnableBlocks("fblocks", llvm::cl::desc("enable the 'blocks' language feature"), llvm::cl::ValueDisallowed, llvm::cl::AllowInverse); How about the below? I think the usage side is nicer. I can do up the doc changes for consideration, if the patches are reasonable enough. -------------- next part -------------- A non-text attachment was scrubbed... Name: opt-1.patch Type: application/octet-stream Size: 5112 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090130/88342c26/attachment.obj -------------- next part -------------- From ggreif at gmail.com Fri Jan 30 19:31:59 2009 From: ggreif at gmail.com (Gabor Greif) Date: Sat, 31 Jan 2009 01:31:59 -0000 Subject: [llvm-commits] [llvm] r63463 - /llvm/trunk/lib/VMCore/AsmWriter.cpp Message-ID: <200901310131.n0V1VxWc024051@zion.cs.uiuc.edu> Author: ggreif Date: Fri Jan 30 19:31:59 2009 New Revision: 63463 URL: http://llvm.org/viewvc/llvm-project?rev=63463&view=rev Log: back out my previous change, it exposes a latent bug. investigating Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=63463&r1=63462&r2=63463&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Fri Jan 30 19:31:59 2009 @@ -1505,14 +1505,13 @@ const Value *Operand = I.getNumOperands() ? I.getOperand(0) : 0; // Special case conditional branches to swizzle the condition out to the front - if (isa(I) && cast(I).isConditional()) { - BranchInst &BI(cast(I)); + if (isa(I) && I.getNumOperands() > 1) { Out << ' '; - writeOperand(BI.getCondition(), true); + writeOperand(I.getOperand(2), true); Out << ", "; - writeOperand(BI.getSuccessor(0), true); + writeOperand(Operand, true); Out << ", "; - writeOperand(BI.getSuccessor(1), true); + writeOperand(I.getOperand(1), true); } else if (isa(I)) { // Special case switch statement to get formatting nice and correct... From gohman at apple.com Fri Jan 30 19:39:00 2009 From: gohman at apple.com (Dan Gohman) Date: Sat, 31 Jan 2009 01:39:00 -0000 Subject: [llvm-commits] [test-suite] r63465 - /test-suite/trunk/Makefile.programs Message-ID: <200901310139.n0V1d0PP024261@zion.cs.uiuc.edu> Author: djg Date: Fri Jan 30 19:39:00 2009 New Revision: 63465 URL: http://llvm.org/viewvc/llvm-project?rev=63465&view=rev Log: Test disable-post-RA scheduler with LLCBETA. Modified: test-suite/trunk/Makefile.programs Modified: test-suite/trunk/Makefile.programs URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=63465&r1=63464&r2=63465&view=diff ============================================================================== --- test-suite/trunk/Makefile.programs (original) +++ test-suite/trunk/Makefile.programs Fri Jan 30 19:39:00 2009 @@ -226,9 +226,9 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86) -LLCBETAOPTION := -pre-alloc-split +LLCBETAOPTION := -disable-post-RA-scheduler=false +#-pre-alloc-split #-join-cross-class-copies -#-disable-post-RA-scheduler=false -machine-licm #-machine-licm #-fast-isel #-aggressive-remat From dalej at apple.com Fri Jan 30 20:22:37 2009 From: dalej at apple.com (Dale Johannesen) Date: Sat, 31 Jan 2009 02:22:37 -0000 Subject: [llvm-commits] [llvm] r63468 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Message-ID: <200901310222.n0V2MbS6025448@zion.cs.uiuc.edu> Author: johannes Date: Fri Jan 30 20:22:37 2009 New Revision: 63468 URL: http://llvm.org/viewvc/llvm-project?rev=63468&view=rev Log: Move CurDebugLoc into SelectionDAGLowering. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63468&r1=63467&r2=63468&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Fri Jan 30 20:22:37 2009 @@ -79,9 +79,6 @@ MachineModuleInfo *MMI; DwarfWriter *DW; - /// CurDebugLoc - current file + line number. Changes as we build the DAG. - DebugLoc CurDebugLoc; - /// EntryNode - The starting token. SDNode EntryNode; @@ -140,7 +137,6 @@ FunctionLoweringInfo &getFunctionLoweringInfo() const { return FLI; } MachineModuleInfo *getMachineModuleInfo() const { return MMI; } DwarfWriter *getDwarfWriter() const { return DW; } - DebugLoc getCurDebugLoc() const { return CurDebugLoc; } /// viewGraph - Pop up a GraphViz/gv window with the DAG rendered using 'dot'. /// @@ -199,8 +195,6 @@ return Root = N; } - void setCurDebugLoc(DebugLoc dl) { CurDebugLoc = dl; } - /// Combine - This iterates over the nodes in the SelectionDAG, folding /// certain types of nodes together, or eliminating superfluous nodes. The /// Level argument controls whether Combine is allowed to produce nodes and Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63468&r1=63467&r2=63468&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Fri Jan 30 20:22:37 2009 @@ -216,14 +216,14 @@ /// this value and returns the result as a ValueVTs value. This uses /// Chain/Flag as the input and updates them for the output Chain/Flag. /// If the Flag pointer is NULL, no flag is used. - SDValue getCopyFromRegs(SelectionDAG &DAG, + SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, SDValue &Chain, SDValue *Flag) const; /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the /// specified value into the registers specified by this object. This uses /// Chain/Flag as the input and updates them for the output Chain/Flag. /// If the Flag pointer is NULL, no flag is used. - void getCopyToRegs(SDValue Val, SelectionDAG &DAG, + void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, SDValue &Chain, SDValue *Flag) const; /// AddInlineAsmOperands - Add this value to the specified inlineasm node @@ -374,7 +374,8 @@ /// larger then ValueVT then AssertOp can be used to specify whether the extra /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT /// (ISD::AssertSext). -static SDValue getCopyFromParts(SelectionDAG &DAG, const SDValue *Parts, +static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, + const SDValue *Parts, unsigned NumParts, MVT PartVT, MVT ValueVT, ISD::NodeType AssertOp = ISD::DELETED_NODE) { assert(NumParts > 0 && "No parts to assemble!"); @@ -400,36 +401,35 @@ MVT::getFloatingPointVT(RoundBits/2); if (RoundParts > 2) { - Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT); - Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2, + Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT); + Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2, PartVT, HalfVT); } else { - Lo = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), - HalfVT, Parts[0]); - Hi = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), - HalfVT, Parts[1]); + Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]); + Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]); } if (TLI.isBigEndian()) std::swap(Lo, Hi); - Val = DAG.getNode(ISD::BUILD_PAIR, DAG.getCurDebugLoc(), RoundVT, Lo, Hi); + Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi); if (RoundParts < NumParts) { // Assemble the trailing non-power-of-2 part. unsigned OddParts = NumParts - RoundParts; MVT OddVT = MVT::getIntegerVT(OddParts * PartBits); - Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT); + Hi = getCopyFromParts(DAG, dl, + Parts+RoundParts, OddParts, PartVT, OddVT); // Combine the round and odd parts. Lo = Val; if (TLI.isBigEndian()) std::swap(Lo, Hi); MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits); - Hi = DAG.getNode(ISD::ANY_EXTEND, DAG.getCurDebugLoc(), TotalVT, Hi); - Hi = DAG.getNode(ISD::SHL, DAG.getCurDebugLoc(), TotalVT, Hi, + Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi); + Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi, DAG.getConstant(Lo.getValueType().getSizeInBits(), TLI.getShiftAmountTy())); - Lo = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), TotalVT, Lo); - Val = DAG.getNode(ISD::OR, DAG.getCurDebugLoc(), TotalVT, Lo, Hi); + Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo); + Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi); } } else { // Handle a multi-element vector. @@ -450,7 +450,7 @@ // If the register was not expanded, truncate or copy the value, // as appropriate. for (unsigned i = 0; i != NumParts; ++i) - Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, + Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1, PartVT, IntermediateVT); } else if (NumParts > 0) { // If the intermediate type was expanded, build the intermediate operands @@ -459,15 +459,14 @@ "Must expand into a divisible number of parts!"); unsigned Factor = NumParts / NumIntermediates; for (unsigned i = 0; i != NumIntermediates; ++i) - Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, + Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor, PartVT, IntermediateVT); } // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate // operands. Val = DAG.getNode(IntermediateVT.isVector() ? - ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, - DAG.getCurDebugLoc(), + ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl, ValueVT, &Ops[0], NumIntermediates); } } @@ -480,14 +479,14 @@ if (PartVT.isVector()) { assert(ValueVT.isVector() && "Unknown vector conversion!"); - return DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), ValueVT, Val); + return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val); } if (ValueVT.isVector()) { assert(ValueVT.getVectorElementType() == PartVT && ValueVT.getVectorNumElements() == 1 && "Only trivial scalar-to-vector conversions should get here!"); - return DAG.getNode(ISD::BUILD_VECTOR, DAG.getCurDebugLoc(), ValueVT, Val); + return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val); } if (PartVT.isInteger() && @@ -497,24 +496,24 @@ // indicate whether the truncated bits will always be // zero or sign-extension. if (AssertOp != ISD::DELETED_NODE) - Val = DAG.getNode(AssertOp, DAG.getCurDebugLoc(), PartVT, Val, + Val = DAG.getNode(AssertOp, dl, PartVT, Val, DAG.getValueType(ValueVT)); - return DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), ValueVT, Val); + return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); } else { - return DAG.getNode(ISD::ANY_EXTEND, DAG.getCurDebugLoc(), ValueVT, Val); + return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val); } } if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { if (ValueVT.bitsLT(Val.getValueType())) // FP_ROUND's are always exact here. - return DAG.getNode(ISD::FP_ROUND, DAG.getCurDebugLoc(), ValueVT, Val, + return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val, DAG.getIntPtrConstant(1)); - return DAG.getNode(ISD::FP_EXTEND, DAG.getCurDebugLoc(), ValueVT, Val); + return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val); } if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) - return DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), ValueVT, Val); + return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val); assert(0 && "Unknown mismatch!"); return SDValue(); @@ -523,7 +522,7 @@ /// getCopyToParts - Create a series of nodes that contain the specified value /// split into legal parts. If the parts contain more bits than Val, then, for /// integers, ExtendKind can be used to specify how to generate the extra bits. -static void getCopyToParts(SelectionDAG &DAG, SDValue Val, +static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { const TargetLowering &TLI = DAG.getTargetLoweringInfo(); @@ -546,22 +545,22 @@ // If the parts cover more bits than the value has, promote the value. if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { assert(NumParts == 1 && "Do not know what to promote to!"); - Val = DAG.getNode(ISD::FP_EXTEND, DAG.getCurDebugLoc(), PartVT, Val); + Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val); } else if (PartVT.isInteger() && ValueVT.isInteger()) { ValueVT = MVT::getIntegerVT(NumParts * PartBits); - Val = DAG.getNode(ExtendKind, DAG.getCurDebugLoc(), ValueVT, Val); + Val = DAG.getNode(ExtendKind, dl, ValueVT, Val); } else { assert(0 && "Unknown mismatch!"); } } else if (PartBits == ValueVT.getSizeInBits()) { // Different types of the same size. assert(NumParts == 1 && PartVT != ValueVT); - Val = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), PartVT, Val); + Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val); } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { // If the parts cover less bits than value has, truncate the value. if (PartVT.isInteger() && ValueVT.isInteger()) { ValueVT = MVT::getIntegerVT(NumParts * PartBits); - Val = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), ValueVT, Val); + Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); } else { assert(0 && "Unknown mismatch!"); } @@ -586,21 +585,21 @@ unsigned RoundParts = 1 << Log2_32(NumParts); unsigned RoundBits = RoundParts * PartBits; unsigned OddParts = NumParts - RoundParts; - SDValue OddVal = DAG.getNode(ISD::SRL, DAG.getCurDebugLoc(), ValueVT, Val, + SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val, DAG.getConstant(RoundBits, TLI.getShiftAmountTy())); - getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT); + getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT); if (TLI.isBigEndian()) // The odd parts were reversed by getCopyToParts - unreverse them. std::reverse(Parts + RoundParts, Parts + NumParts); NumParts = RoundParts; ValueVT = MVT::getIntegerVT(NumParts * PartBits); - Val = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), ValueVT, Val); + Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); } // The number of parts is a power of 2. Repeatedly bisect the value using // EXTRACT_ELEMENT. - Parts[0] = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), + Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::getIntegerVT(ValueVT.getSizeInBits()), Val); for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { @@ -610,17 +609,17 @@ SDValue &Part0 = Parts[i]; SDValue &Part1 = Parts[i+StepSize/2]; - Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DAG.getCurDebugLoc(), + Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, ThisVT, Part0, DAG.getConstant(1, PtrVT)); - Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DAG.getCurDebugLoc(), + Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, ThisVT, Part0, DAG.getConstant(0, PtrVT)); if (ThisBits == PartBits && ThisVT != PartVT) { - Part0 = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), + Part0 = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Part0); - Part1 = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), + Part1 = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Part1); } } @@ -636,12 +635,12 @@ if (NumParts == 1) { if (PartVT != ValueVT) { if (PartVT.isVector()) { - Val = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), PartVT, Val); + Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val); } else { assert(ValueVT.getVectorElementType() == PartVT && ValueVT.getVectorNumElements() == 1 && "Only trivial vector-to-scalar conversions should get here!"); - Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DAG.getCurDebugLoc(), + Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, PartVT, Val, DAG.getConstant(0, PtrVT)); } @@ -667,12 +666,12 @@ SmallVector Ops(NumIntermediates); for (unsigned i = 0; i != NumIntermediates; ++i) if (IntermediateVT.isVector()) - Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DAG.getCurDebugLoc(), + Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, IntermediateVT, Val, DAG.getConstant(i * (NumElements / NumIntermediates), PtrVT)); else - Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DAG.getCurDebugLoc(), + Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, IntermediateVT, Val, DAG.getConstant(i, PtrVT)); @@ -681,7 +680,7 @@ // If the register was not expanded, promote or copy the value, // as appropriate. for (unsigned i = 0; i != NumParts; ++i) - getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); + getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT); } else if (NumParts > 0) { // If the intermediate type was expanded, split each the value into // legal parts. @@ -689,7 +688,7 @@ "Must expand into a divisible number of parts!"); unsigned Factor = NumParts / NumIntermediates; for (unsigned i = 0; i != NumIntermediates; ++i) - getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); + getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT); } } @@ -730,7 +729,7 @@ } // Otherwise, we have to make a token factor node. - SDValue Root = DAG.getNode(ISD::TokenFactor, DAG.getCurDebugLoc(), MVT::Other, + SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, &PendingLoads[0], PendingLoads.size()); PendingLoads.clear(); DAG.setRoot(Root); @@ -760,7 +759,7 @@ PendingExports.push_back(Root); } - Root = DAG.getNode(ISD::TokenFactor, DAG.getCurDebugLoc(), MVT::Other, + Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, &PendingExports[0], PendingExports.size()); PendingExports.clear(); @@ -820,7 +819,7 @@ if (isa(C) && !isa(V->getType()) && !V->getType()->isAggregateType()) - return N = DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), VT); + return N = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT); if (ConstantExpr *CE = dyn_cast(C)) { visit(CE->getOpcode(), *CE); @@ -853,7 +852,7 @@ for (unsigned i = 0; i != NumElts; ++i) { MVT EltVT = ValueVTs[i]; if (isa(C)) - Constants[i] = DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), EltVT); + Constants[i] = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT); else if (EltVT.isFloatingPoint()) Constants[i] = DAG.getConstantFP(0, EltVT); else @@ -878,7 +877,7 @@ SDValue Op; if (isa(C)) - Op = DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), EltVT); + Op = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT); else if (EltVT.isFloatingPoint()) Op = DAG.getConstantFP(0, EltVT); else @@ -887,7 +886,7 @@ } // Create a BUILD_VECTOR node. - return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, DAG.getCurDebugLoc(), + return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), VT, &Ops[0], Ops.size()); } @@ -905,13 +904,13 @@ RegsForValue RFV(TLI, InReg, V->getType()); SDValue Chain = DAG.getEntryNode(); - return RFV.getCopyFromRegs(DAG, Chain, NULL); + return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL); } void SelectionDAGLowering::visitRet(ReturnInst &I) { if (I.getNumOperands() == 0) { - DAG.setRoot(DAG.getNode(ISD::RET, DAG.getCurDebugLoc(), + DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other, getControlRoot())); return; } @@ -948,7 +947,8 @@ else if (F->paramHasAttr(0, Attribute::ZExt)) ExtendKind = ISD::ZERO_EXTEND; - getCopyToParts(DAG, SDValue(RetOp.getNode(), RetOp.getResNo() + j), + getCopyToParts(DAG, getCurDebugLoc(), + SDValue(RetOp.getNode(), RetOp.getResNo() + j), &Parts[0], NumParts, PartVT, ExtendKind); // 'inreg' on function refers to return value @@ -961,7 +961,7 @@ } } } - DAG.setRoot(DAG.getNode(ISD::RET, DAG.getCurDebugLoc(), MVT::Other, + DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other, &NewValues[0], NewValues.size())); } @@ -1201,7 +1201,7 @@ // If this is not a fall-through branch, emit the branch. if (Succ0MBB != NextBlock) - DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, getControlRoot(), DAG.getBasicBlock(Succ0MBB))); return; @@ -1281,7 +1281,7 @@ Cond = CondLHS; else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { SDValue True = DAG.getConstant(1, CondLHS.getValueType()); - Cond = DAG.getNode(ISD::XOR, DAG.getCurDebugLoc(), + Cond = DAG.getNode(ISD::XOR, getCurDebugLoc(), CondLHS.getValueType(), CondLHS, True); } else Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); @@ -1297,7 +1297,7 @@ if (cast(CB.CmpLHS)->isMinValue(true)) { Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); } else { - SDValue SUB = DAG.getNode(ISD::SUB, DAG.getCurDebugLoc(), + SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, CmpOp, DAG.getConstant(Low, VT)); Cond = DAG.getSetCC(MVT::i1, SUB, DAG.getConstant(High-Low, VT), ISD::SETULE); @@ -1320,10 +1320,10 @@ if (CB.TrueBB == NextBlock) { std::swap(CB.TrueBB, CB.FalseBB); SDValue True = DAG.getConstant(1, Cond.getValueType()); - Cond = DAG.getNode(ISD::XOR, DAG.getCurDebugLoc(), + Cond = DAG.getNode(ISD::XOR, getCurDebugLoc(), Cond.getValueType(), Cond, True); } - SDValue BrCond = DAG.getNode(ISD::BRCOND, DAG.getCurDebugLoc(), + SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), MVT::Other, getControlRoot(), Cond, DAG.getBasicBlock(CB.TrueBB)); @@ -1339,7 +1339,7 @@ if (CB.FalseBB == NextBlock) DAG.setRoot(BrCond); else - DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), MVT::Other, BrCond, + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, DAG.getBasicBlock(CB.FalseBB))); } } @@ -1351,7 +1351,7 @@ MVT PTy = TLI.getPointerTy(); SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy); SDValue Table = DAG.getJumpTable(JT.JTI, PTy); - DAG.setRoot(DAG.getNode(ISD::BR_JT, DAG.getCurDebugLoc(), + DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(), MVT::Other, Index.getValue(1), Table, Index)); } @@ -1365,7 +1365,7 @@ // difference between smallest and largest cases. SDValue SwitchOp = getValue(JTH.SValue); MVT VT = SwitchOp.getValueType(); - SDValue SUB = DAG.getNode(ISD::SUB, DAG.getCurDebugLoc(), VT, SwitchOp, + SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, DAG.getConstant(JTH.First, VT)); // The SDNode we just created, which holds the value being switched on minus @@ -1374,10 +1374,10 @@ // This value may be smaller or larger than the target's pointer type, and // therefore require extension or truncating. if (VT.bitsGT(TLI.getPointerTy())) - SwitchOp = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), + SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), TLI.getPointerTy(), SUB); else - SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), + SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), TLI.getPointerTy(), SUB); unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); @@ -1398,14 +1398,14 @@ if (++BBI != CurMBB->getParent()->end()) NextBlock = BBI; - SDValue BrCond = DAG.getNode(ISD::BRCOND, DAG.getCurDebugLoc(), + SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), MVT::Other, CopyTo, CMP, DAG.getBasicBlock(JT.Default)); if (JT.MBB == NextBlock) DAG.setRoot(BrCond); else - DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), MVT::Other, BrCond, + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, DAG.getBasicBlock(JT.MBB))); } @@ -1415,7 +1415,7 @@ // Subtract the minimum value SDValue SwitchOp = getValue(B.SValue); MVT VT = SwitchOp.getValueType(); - SDValue SUB = DAG.getNode(ISD::SUB, DAG.getCurDebugLoc(), VT, SwitchOp, + SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, DAG.getConstant(B.First, VT)); // Check range @@ -1425,10 +1425,10 @@ SDValue ShiftOp; if (VT.bitsGT(TLI.getShiftAmountTy())) - ShiftOp = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), + ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), TLI.getShiftAmountTy(), SUB); else - ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), + ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), TLI.getShiftAmountTy(), SUB); B.Reg = FuncInfo.MakeReg(TLI.getShiftAmountTy()); @@ -1446,14 +1446,14 @@ CurMBB->addSuccessor(B.Default); CurMBB->addSuccessor(MBB); - SDValue BrRange = DAG.getNode(ISD::BRCOND, DAG.getCurDebugLoc(), + SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), MVT::Other, CopyTo, RangeCmp, DAG.getBasicBlock(B.Default)); if (MBB == NextBlock) DAG.setRoot(BrRange); else - DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), MVT::Other, CopyTo, + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, DAG.getBasicBlock(MBB))); } @@ -1464,13 +1464,13 @@ // Make desired shift SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), Reg, TLI.getShiftAmountTy()); - SDValue SwitchVal = DAG.getNode(ISD::SHL, DAG.getCurDebugLoc(), + SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), TLI.getPointerTy(), DAG.getConstant(1, TLI.getPointerTy()), ShiftOp); // Emit bit tests and jumps - SDValue AndOp = DAG.getNode(ISD::AND, DAG.getCurDebugLoc(), + SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), TLI.getPointerTy(), SwitchVal, DAG.getConstant(B.Mask, TLI.getPointerTy())); SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp.getValueType()), @@ -1480,7 +1480,7 @@ CurMBB->addSuccessor(B.TargetBB); CurMBB->addSuccessor(NextMBB); - SDValue BrAnd = DAG.getNode(ISD::BRCOND, DAG.getCurDebugLoc(), + SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), MVT::Other, getControlRoot(), AndCmp, DAG.getBasicBlock(B.TargetBB)); @@ -1494,7 +1494,7 @@ if (NextMBB == NextBlock) DAG.setRoot(BrAnd); else - DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), MVT::Other, BrAnd, + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, DAG.getBasicBlock(NextMBB))); } @@ -1522,7 +1522,7 @@ CurMBB->addSuccessor(LandingPad); // Drop into normal successor. - DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, getControlRoot(), DAG.getBasicBlock(Return))); } @@ -2026,7 +2026,7 @@ // If this is not a fall-through branch, emit the branch. CurMBB->addSuccessor(Default); if (Default != NextBlock) - DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, getControlRoot(), DAG.getBasicBlock(Default))); return; @@ -2089,7 +2089,7 @@ Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); if (CV == CNZ) { SDValue Op2 = getValue(I.getOperand(1)); - setValue(&I, DAG.getNode(ISD::FNEG, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), Op2.getValueType(), Op2)); return; } @@ -2100,7 +2100,7 @@ if (ConstantFP *CFP = dyn_cast(I.getOperand(0))) if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { SDValue Op2 = getValue(I.getOperand(1)); - setValue(&I, DAG.getNode(ISD::FNEG, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), Op2.getValueType(), Op2)); return; } @@ -2113,7 +2113,7 @@ SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); - setValue(&I, DAG.getNode(OpCode, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), Op1.getValueType(), Op1, Op2)); } @@ -2122,14 +2122,14 @@ SDValue Op2 = getValue(I.getOperand(1)); if (!isa(I.getType())) { if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType())) - Op2 = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), + Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), TLI.getShiftAmountTy(), Op2); else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType())) - Op2 = DAG.getNode(ISD::ANY_EXTEND, DAG.getCurDebugLoc(), + Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), TLI.getShiftAmountTy(), Op2); } - setValue(&I, DAG.getNode(Opcode, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), Op1.getValueType(), Op1, Op2)); } @@ -2194,12 +2194,12 @@ SDValue FalseVal = getValue(I.getOperand(2)); for (unsigned i = 0; i != NumValues; ++i) - Values[i] = DAG.getNode(ISD::SELECT, DAG.getCurDebugLoc(), + Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), TrueVal.getValueType(), Cond, SDValue(TrueVal.getNode(), TrueVal.getResNo() + i), SDValue(FalseVal.getNode(), FalseVal.getResNo() + i)); - setValue(&I, DAG.getNode(ISD::MERGE_VALUES, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), DAG.getVTList(&ValueVTs[0], NumValues), &Values[0], NumValues)); } @@ -2210,7 +2210,7 @@ // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), DestVT, N)); + setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitZExt(User &I) { @@ -2218,7 +2218,7 @@ // ZExt also can't be a cast to bool for same reason. So, nothing much to do SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), DestVT, N)); + setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitSExt(User &I) { @@ -2226,14 +2226,14 @@ // SExt also can't be a cast to bool for same reason. So, nothing much to do SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DAG.getCurDebugLoc(), DestVT, N)); + setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitFPTrunc(User &I) { // FPTrunc is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::FP_ROUND, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), DestVT, N, DAG.getIntPtrConstant(0))); } @@ -2241,35 +2241,35 @@ // FPTrunc is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::FP_EXTEND, DAG.getCurDebugLoc(), DestVT, N)); + setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitFPToUI(User &I) { // FPToUI is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DAG.getCurDebugLoc(), DestVT, N)); + setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitFPToSI(User &I) { // FPToSI is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DAG.getCurDebugLoc(), DestVT, N)); + setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitUIToFP(User &I) { // UIToFP is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DAG.getCurDebugLoc(), DestVT, N)); + setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitSIToFP(User &I){ // SIToFP is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DAG.getCurDebugLoc(), DestVT, N)); + setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitPtrToInt(User &I) { @@ -2280,10 +2280,10 @@ MVT DestVT = TLI.getValueType(I.getType()); SDValue Result; if (DestVT.bitsLT(SrcVT)) - Result = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), DestVT, N); + Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N); else // Note: ZERO_EXTEND can handle cases where the sizes are equal too - Result = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), DestVT, N); + Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N); setValue(&I, Result); } @@ -2294,10 +2294,10 @@ MVT SrcVT = N.getValueType(); MVT DestVT = TLI.getValueType(I.getType()); if (DestVT.bitsLT(SrcVT)) - setValue(&I, DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), DestVT, N)); + setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); else // Note: ZERO_EXTEND can handle cases where the sizes are equal too - setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); } @@ -2308,7 +2308,7 @@ // BitCast assures us that source and destination are the same size so this // is either a BIT_CONVERT or a no-op. if (DestVT != N.getValueType()) - setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), DestVT, N)); // convert types else setValue(&I, N); // noop cast. @@ -2317,21 +2317,21 @@ void SelectionDAGLowering::visitInsertElement(User &I) { SDValue InVec = getValue(I.getOperand(0)); SDValue InVal = getValue(I.getOperand(1)); - SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), + SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), TLI.getPointerTy(), getValue(I.getOperand(2))); - setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), TLI.getValueType(I.getType()), InVec, InVal, InIdx)); } void SelectionDAGLowering::visitExtractElement(User &I) { SDValue InVec = getValue(I.getOperand(0)); - SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), + SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), TLI.getPointerTy(), getValue(I.getOperand(1))); - setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), TLI.getValueType(I.getType()), InVec, InIdx)); } @@ -2361,7 +2361,7 @@ int SrcNumElts = SrcVT.getVectorNumElements(); if (SrcNumElts == MaskNumElts) { - setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(), VT, Src1, Src2, Mask)); return; } @@ -2375,14 +2375,14 @@ // lengths match. if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { // The shuffle is concatenating two vectors together. - setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), VT, Src1, Src2)); return; } // Pad both vectors with undefs to make them the same length as the mask. unsigned NumConcat = MaskNumElts / SrcNumElts; - SDValue UndefVal = DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), SrcVT); + SDValue UndefVal = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), SrcVT); SDValue* MOps1 = new SDValue[NumConcat]; SDValue* MOps2 = new SDValue[NumConcat]; @@ -2392,9 +2392,9 @@ MOps1[i] = UndefVal; MOps2[i] = UndefVal; } - Src1 = DAG.getNode(ISD::CONCAT_VECTORS, DAG.getCurDebugLoc(), + Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), VT, MOps1, NumConcat); - Src2 = DAG.getNode(ISD::CONCAT_VECTORS, DAG.getCurDebugLoc(), + Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), VT, MOps2, NumConcat); delete [] MOps1; @@ -2414,11 +2414,11 @@ MaskEltVT)); } } - Mask = DAG.getNode(ISD::BUILD_VECTOR, DAG.getCurDebugLoc(), + Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), Mask.getValueType(), &MappedOps[0], MappedOps.size()); - setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(), VT, Src1, Src2, Mask)); return; } @@ -2485,7 +2485,7 @@ if (RangeUse[0] == 0 && RangeUse[0] == 0) { setValue(&I, DAG.getNode(ISD::UNDEF, - DAG.getCurDebugLoc(), VT)); // Vectors are not used. + getCurDebugLoc(), VT)); // Vectors are not used. return; } else if (RangeUse[0] < 2 && RangeUse[1] < 2) { @@ -2493,9 +2493,9 @@ for (int Input=0; Input < 2; ++Input) { SDValue& Src = Input == 0 ? Src1 : Src2; if (RangeUse[Input] == 0) { - Src = DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), VT); + Src = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT); } else { - Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DAG.getCurDebugLoc(), VT, + Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, Src, DAG.getIntPtrConstant(StartIdx[Input])); } } @@ -2515,10 +2515,10 @@ } } } - Mask = DAG.getNode(ISD::BUILD_VECTOR, DAG.getCurDebugLoc(), + Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), Mask.getValueType(), &MappedOps[0], MappedOps.size()); - setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(), VT, Src1, Src2, Mask)); return; } @@ -2533,20 +2533,20 @@ for (int i = 0; i != MaskNumElts; ++i) { SDValue Arg = Mask.getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) { - Ops.push_back(DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), EltVT)); + Ops.push_back(DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT)); } else { assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); int Idx = cast(Arg)->getZExtValue(); if (Idx < SrcNumElts) - Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DAG.getCurDebugLoc(), + Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), EltVT, Src1, DAG.getConstant(Idx, PtrVT))); else - Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DAG.getCurDebugLoc(), + Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), EltVT, Src2, DAG.getConstant(Idx - SrcNumElts, PtrVT))); } } - setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), VT, &Ops[0], Ops.size())); } @@ -2575,21 +2575,21 @@ unsigned i = 0; // Copy the beginning value(s) from the original aggregate. for (; i != LinearIndex; ++i) - Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), + Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(), AggValueVTs[i]) : SDValue(Agg.getNode(), Agg.getResNo() + i); // Copy values from the inserted value(s). for (; i != LinearIndex + NumValValues; ++i) - Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), + Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(), AggValueVTs[i]) : SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); // Copy remaining value(s) from the original aggregate. for (; i != NumAggValues; ++i) - Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), + Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(), AggValueVTs[i]) : SDValue(Agg.getNode(), Agg.getResNo() + i); - setValue(&I, DAG.getNode(ISD::MERGE_VALUES, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), DAG.getVTList(&AggValueVTs[0], NumAggValues), &Values[0], NumAggValues)); } @@ -2614,11 +2614,11 @@ for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) Values[i - LinearIndex] = OutOfUndef ? - DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), + DAG.getNode(ISD::UNDEF, getCurDebugLoc(), Agg.getNode()->getValueType(Agg.getResNo() + i)) : SDValue(Agg.getNode(), Agg.getResNo() + i); - setValue(&I, DAG.getNode(ISD::MERGE_VALUES, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), DAG.getVTList(&ValValueVTs[0], NumValValues), &Values[0], NumValValues)); } @@ -2636,7 +2636,7 @@ if (Field) { // N = N + Offset uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); - N = DAG.getNode(ISD::ADD, DAG.getCurDebugLoc(), N.getValueType(), N, + N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, DAG.getIntPtrConstant(Offset)); } Ty = StTy->getElementType(Field); @@ -2648,7 +2648,7 @@ if (CI->getZExtValue() == 0) continue; uint64_t Offs = TD->getTypePaddedSize(Ty)*cast(CI)->getSExtValue(); - N = DAG.getNode(ISD::ADD, DAG.getCurDebugLoc(), N.getValueType(), N, + N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, DAG.getIntPtrConstant(Offs)); continue; } @@ -2660,10 +2660,10 @@ // If the index is smaller or larger than intptr_t, truncate or extend // it. if (IdxN.getValueType().bitsLT(N.getValueType())) - IdxN = DAG.getNode(ISD::SIGN_EXTEND, DAG.getCurDebugLoc(), + IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), N.getValueType(), IdxN); else if (IdxN.getValueType().bitsGT(N.getValueType())) - IdxN = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), + IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), N.getValueType(), IdxN); // If this is a multiply by a power of two, turn it into a shl @@ -2671,17 +2671,17 @@ if (ElementSize != 1) { if (isPowerOf2_64(ElementSize)) { unsigned Amt = Log2_64(ElementSize); - IdxN = DAG.getNode(ISD::SHL, DAG.getCurDebugLoc(), + IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), N.getValueType(), IdxN, DAG.getConstant(Amt, TLI.getShiftAmountTy())); } else { SDValue Scale = DAG.getIntPtrConstant(ElementSize); - IdxN = DAG.getNode(ISD::MUL, DAG.getCurDebugLoc(), + IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), N.getValueType(), IdxN, Scale); } } - N = DAG.getNode(ISD::ADD, DAG.getCurDebugLoc(), + N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, IdxN); } } @@ -2703,13 +2703,13 @@ SDValue AllocSize = getValue(I.getArraySize()); MVT IntPtr = TLI.getPointerTy(); if (IntPtr.bitsLT(AllocSize.getValueType())) - AllocSize = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), + AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, AllocSize); else if (IntPtr.bitsGT(AllocSize.getValueType())) - AllocSize = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), + AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, AllocSize); - AllocSize = DAG.getNode(ISD::MUL, DAG.getCurDebugLoc(), IntPtr, AllocSize, + AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, AllocSize, DAG.getIntPtrConstant(TySize)); // Handle alignment. If the requested alignment is less than or equal to @@ -2722,18 +2722,18 @@ // Round the size of the allocation up to the stack alignment size // by add SA-1 to the size. - AllocSize = DAG.getNode(ISD::ADD, DAG.getCurDebugLoc(), + AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), AllocSize.getValueType(), AllocSize, DAG.getIntPtrConstant(StackAlign-1)); // Mask out the low bits for alignment purposes. - AllocSize = DAG.getNode(ISD::AND, DAG.getCurDebugLoc(), + AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), AllocSize.getValueType(), AllocSize, DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), MVT::Other); - SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, DAG.getCurDebugLoc(), + SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), VTs, 2, Ops, 3); setValue(&I, DSA); DAG.setRoot(DSA.getValue(1)); @@ -2776,8 +2776,8 @@ SmallVector Chains(NumValues); MVT PtrVT = Ptr.getValueType(); for (unsigned i = 0; i != NumValues; ++i) { - SDValue L = DAG.getLoad(ValueVTs[i], DAG.getCurDebugLoc(), Root, - DAG.getNode(ISD::ADD, DAG.getCurDebugLoc(), + SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, + DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, DAG.getConstant(Offsets[i], PtrVT)), SV, Offsets[i], @@ -2787,7 +2787,7 @@ } if (!ConstantMemory) { - SDValue Chain = DAG.getNode(ISD::TokenFactor, DAG.getCurDebugLoc(), + SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, &Chains[0], NumValues); if (isVolatile) @@ -2796,7 +2796,7 @@ PendingLoads.push_back(Chain); } - setValue(&I, DAG.getNode(ISD::MERGE_VALUES, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), DAG.getVTList(&ValueVTs[0], NumValues), &Values[0], NumValues)); } @@ -2825,15 +2825,15 @@ bool isVolatile = I.isVolatile(); unsigned Alignment = I.getAlignment(); for (unsigned i = 0; i != NumValues; ++i) - Chains[i] = DAG.getStore(Root, DAG.getCurDebugLoc(), + Chains[i] = DAG.getStore(Root, getCurDebugLoc(), SDValue(Src.getNode(), Src.getResNo() + i), - DAG.getNode(ISD::ADD, DAG.getCurDebugLoc(), + DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, DAG.getConstant(Offsets[i], PtrVT)), PtrV, Offsets[i], isVolatile, Alignment); - DAG.setRoot(DAG.getNode(ISD::TokenFactor, DAG.getCurDebugLoc(), + DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, &Chains[0], NumValues)); } @@ -2894,7 +2894,7 @@ SDValue Result; if (IsTgtIntrinsic) { // This is target intrinsic that touches memory - Result = DAG.getMemIntrinsicNode(Info.opc, DAG.getCurDebugLoc(), + Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), VTList, VTs.size(), &Ops[0], Ops.size(), Info.memVT, Info.ptrVal, Info.offset, @@ -2902,15 +2902,15 @@ Info.readMem, Info.writeMem); } else if (!HasChain) - Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DAG.getCurDebugLoc(), + Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), VTList, VTs.size(), &Ops[0], Ops.size()); else if (I.getType() != Type::VoidTy) - Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DAG.getCurDebugLoc(), + Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), VTList, VTs.size(), &Ops[0], Ops.size()); else - Result = DAG.getNode(ISD::INTRINSIC_VOID, DAG.getCurDebugLoc(), + Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), VTList, VTs.size(), &Ops[0], Ops.size()); @@ -2924,7 +2924,7 @@ if (I.getType() != Type::VoidTy) { if (const VectorType *PTy = dyn_cast(I.getType())) { MVT VT = TLI.getValueType(PTy); - Result = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), VT, Result); + Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result); } setValue(&I, Result); } @@ -3004,12 +3004,12 @@ /// /// where Op is the hexidecimal representation of floating point value. static SDValue -GetSignificand(SelectionDAG &DAG, SDValue Op) { - SDValue t1 = DAG.getNode(ISD::AND, DAG.getCurDebugLoc(), MVT::i32, Op, +GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { + SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, DAG.getConstant(0x007fffff, MVT::i32)); - SDValue t2 = DAG.getNode(ISD::OR, DAG.getCurDebugLoc(), MVT::i32, t1, + SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, DAG.getConstant(0x3f800000, MVT::i32)); - return DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), MVT::f32, t2); + return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2); } /// GetExponent - Get the exponent: @@ -3018,14 +3018,15 @@ /// /// where Op is the hexidecimal representation of floating point value. static SDValue -GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI) { - SDValue t0 = DAG.getNode(ISD::AND, DAG.getCurDebugLoc(), MVT::i32, Op, +GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, + DebugLoc dl) { + SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, DAG.getConstant(0x7f800000, MVT::i32)); - SDValue t1 = DAG.getNode(ISD::SRL, DAG.getCurDebugLoc(), MVT::i32, t0, + SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, DAG.getConstant(23, TLI.getShiftAmountTy())); - SDValue t2 = DAG.getNode(ISD::SUB, DAG.getCurDebugLoc(), MVT::i32, t1, + SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, DAG.getConstant(127, MVT::i32)); - return DAG.getNode(ISD::SINT_TO_FP, MVT::f32, t2); + return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); } /// getF32Constant - Get 32-bit floating point constant. @@ -3041,7 +3042,7 @@ SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) { SDValue Root = getRoot(); SDValue L = - DAG.getAtomic(Op, DAG.getCurDebugLoc(), + DAG.getAtomic(Op, getCurDebugLoc(), getValue(I.getOperand(2)).getValueType().getSimpleVT(), Root, getValue(I.getOperand(1)), @@ -3061,7 +3062,7 @@ MVT ValueVTs[] = { Op1.getValueType(), MVT::i1 }; SDValue Ops[] = { Op1, Op2 }; - SDValue Result = DAG.getNode(Op, DAG.getCurDebugLoc(), + SDValue Result = DAG.getNode(Op, getCurDebugLoc(), DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2); setValue(&I, Result); @@ -3073,7 +3074,7 @@ void SelectionDAGLowering::visitExp(CallInst &I) { SDValue result; - DebugLoc dl = DAG.getCurDebugLoc(); + DebugLoc dl = getCurDebugLoc(); if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { @@ -3199,7 +3200,7 @@ void SelectionDAGLowering::visitLog(CallInst &I) { SDValue result; - DebugLoc dl = DAG.getCurDebugLoc(); + DebugLoc dl = getCurDebugLoc(); if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { @@ -3207,13 +3208,13 @@ SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); // Scale the exponent by log(2) [0.69314718f]. - SDValue Exp = GetExponent(DAG, Op1, TLI); + SDValue Exp = GetExponent(DAG, Op1, TLI, dl); SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, getF32Constant(DAG, 0x3f317218)); // Get the significand and build it into a floating-point number with // exponent of 1. - SDValue X = GetSignificand(DAG, Op1); + SDValue X = GetSignificand(DAG, Op1, dl); if (LimitFloatPrecision <= 6) { // For floating-point precision of 6: @@ -3309,7 +3310,7 @@ void SelectionDAGLowering::visitLog2(CallInst &I) { SDValue result; - DebugLoc dl = DAG.getCurDebugLoc(); + DebugLoc dl = getCurDebugLoc(); if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { @@ -3317,11 +3318,11 @@ SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); // Get the exponent. - SDValue LogOfExponent = GetExponent(DAG, Op1, TLI); + SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); // Get the significand and build it into a floating-point number with // exponent of 1. - SDValue X = GetSignificand(DAG, Op1); + SDValue X = GetSignificand(DAG, Op1, dl); // Different possible minimax approximations of significand in // floating-point for various degrees of accuracy over [1,2]. @@ -3418,7 +3419,7 @@ void SelectionDAGLowering::visitLog10(CallInst &I) { SDValue result; - DebugLoc dl = DAG.getCurDebugLoc(); + DebugLoc dl = getCurDebugLoc(); if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { @@ -3426,13 +3427,13 @@ SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); // Scale the exponent by log10(2) [0.30102999f]. - SDValue Exp = GetExponent(DAG, Op1, TLI); + SDValue Exp = GetExponent(DAG, Op1, TLI, dl); SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, getF32Constant(DAG, 0x3e9a209a)); // Get the significand and build it into a floating-point number with // exponent of 1. - SDValue X = GetSignificand(DAG, Op1); + SDValue X = GetSignificand(DAG, Op1, dl); if (LimitFloatPrecision <= 6) { // For floating-point precision of 6: @@ -3520,7 +3521,7 @@ void SelectionDAGLowering::visitExp2(CallInst &I) { SDValue result; - DebugLoc dl = DAG.getCurDebugLoc(); + DebugLoc dl = getCurDebugLoc(); if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { @@ -3635,7 +3636,7 @@ SelectionDAGLowering::visitPow(CallInst &I) { SDValue result; Value *Val = I.getOperand(1); - DebugLoc dl = DAG.getCurDebugLoc(); + DebugLoc dl = getCurDebugLoc(); bool IsExp10 = false; if (getValue(Val).getValueType() == MVT::f32 && @@ -3768,7 +3769,7 @@ /// otherwise lower it and return null. const char * SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { - DebugLoc dl = DAG.getCurDebugLoc(); + DebugLoc dl = getCurDebugLoc(); switch (Intrinsic) { default: // By default, turn this into a target intrinsic node. @@ -3845,7 +3846,7 @@ getOrCreateDebugLocID(SrcFile, SPI.getLine(), SPI.getColumn()); - DAG.setCurDebugLoc(DebugLoc::get(idx)); + setCurDebugLoc(DebugLoc::get(idx)); } return 0; } @@ -3891,7 +3892,7 @@ DW->RecordSourceLine(Line, 0, SrcFile); if (DW->getRecordSourceLineCount() != 1) DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); - DAG.setCurDebugLoc(DebugLoc::get(DAG.getMachineFunction(). + setCurDebugLoc(DebugLoc::get(DAG.getMachineFunction(). getOrCreateDebugLocID(SrcFile, Line, 0))); } @@ -4171,7 +4172,7 @@ SDValue FIN = DAG.getFrameIndex(FI, PtrTy); // Store the stack protector onto the stack. - SDValue Result = DAG.getStore(getRoot(), DAG.getCurDebugLoc(), Src, FIN, + SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, PseudoSourceValue::getFixedStack(FI), 0, true); setValue(&I, Result); @@ -4263,7 +4264,7 @@ case Intrinsic::atomic_cmp_swap: { SDValue Root = getRoot(); SDValue L = - DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, DAG.getCurDebugLoc(), + DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), getValue(I.getOperand(2)).getValueType().getSimpleVT(), Root, getValue(I.getOperand(1)), @@ -4344,7 +4345,7 @@ CS.paramHasAttr(0, Attribute::InReg), CS.getCallingConv(), IsTailCall && PerformTailCallOpt, - Callee, Args, DAG, DAG.getCurDebugLoc()); + Callee, Args, DAG, getCurDebugLoc()); if (CS.getType() != Type::VoidTy) setValue(CS.getInstruction(), Result.first); DAG.setRoot(Result.second); @@ -4386,7 +4387,7 @@ I.getType() == I.getOperand(2)->getType()) { SDValue LHS = getValue(I.getOperand(1)); SDValue RHS = getValue(I.getOperand(2)); - setValue(&I, DAG.getNode(ISD::FCOPYSIGN, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), LHS.getValueType(), LHS, RHS)); return; } @@ -4398,7 +4399,7 @@ I.getOperand(1)->getType()->isFloatingPoint() && I.getType() == I.getOperand(1)->getType()) { SDValue Tmp = getValue(I.getOperand(1)); - setValue(&I, DAG.getNode(ISD::FABS, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), Tmp.getValueType(), Tmp)); return; } @@ -4410,7 +4411,7 @@ I.getOperand(1)->getType()->isFloatingPoint() && I.getType() == I.getOperand(1)->getType()) { SDValue Tmp = getValue(I.getOperand(1)); - setValue(&I, DAG.getNode(ISD::FSIN, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), Tmp.getValueType(), Tmp)); return; } @@ -4422,7 +4423,7 @@ I.getOperand(1)->getType()->isFloatingPoint() && I.getType() == I.getOperand(1)->getType()) { SDValue Tmp = getValue(I.getOperand(1)); - setValue(&I, DAG.getNode(ISD::FCOS, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), Tmp.getValueType(), Tmp)); return; } @@ -4447,7 +4448,7 @@ /// this value and returns the result as a ValueVT value. This uses /// Chain/Flag as the input and updates them for the output Chain/Flag. /// If the Flag pointer is NULL, no flag is used. -SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, +SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, SDValue &Chain, SDValue *Flag) const { // Assemble the legal parts into the final values. @@ -4505,8 +4506,7 @@ isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 if (FromVT != MVT::Other) { - P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, - DAG.getCurDebugLoc(), + P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, RegisterVT, P, DAG.getValueType(FromVT)); } @@ -4516,13 +4516,13 @@ Parts[i] = P; } - Values[Value] = getCopyFromParts(DAG, Parts.begin(), NumRegs, RegisterVT, - ValueVT); + Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), + NumRegs, RegisterVT, ValueVT); Part += NumRegs; Parts.clear(); } - return DAG.getNode(ISD::MERGE_VALUES, DAG.getCurDebugLoc(), + return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(&ValueVTs[0], ValueVTs.size()), &Values[0], ValueVTs.size()); } @@ -4531,7 +4531,7 @@ /// specified value into the registers specified by this object. This uses /// Chain/Flag as the input and updates them for the output Chain/Flag. /// If the Flag pointer is NULL, no flag is used. -void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, +void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, SDValue &Chain, SDValue *Flag) const { // Get the list of the values's legal parts. unsigned NumRegs = Regs.size(); @@ -4541,7 +4541,7 @@ unsigned NumParts = TLI->getNumRegisters(ValueVT); MVT RegisterVT = RegVTs[Value]; - getCopyToParts(DAG, Val.getValue(Val.getResNo() + Value), + getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part], NumParts, RegisterVT); Part += NumParts; } @@ -4572,8 +4572,7 @@ // = op c3, ..., f2 Chain = Chains[NumRegs-1]; else - Chain = DAG.getNode(ISD::TokenFactor, DAG.getCurDebugLoc(), - MVT::Other, &Chains[0], NumRegs); + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); } /// AddInlineAsmOperands - Add this value to the specified inlineasm node @@ -4785,7 +4784,7 @@ // vector types). MVT RegVT = *PhysReg.second->vt_begin(); if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { - OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), + OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), RegVT, OpInfo.CallOperand); OpInfo.ConstraintVT = RegVT; } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { @@ -4794,7 +4793,7 @@ // into i64, which can be passed with two i32 values on a 32-bit // machine. RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits()); - OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), + OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), RegVT, OpInfo.CallOperand); OpInfo.ConstraintVT = RegVT; } @@ -5060,7 +5059,7 @@ MachineFunction &MF = DAG.getMachineFunction(); int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); - Chain = DAG.getStore(Chain, DAG.getCurDebugLoc(), + Chain = DAG.getStore(Chain, getCurDebugLoc(), OpInfo.CallOperand, StackSlot, NULL, 0); OpInfo.CallOperand = StackSlot; } @@ -5190,7 +5189,8 @@ } // Use the produced MatchedRegs object to - MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); + MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), + Chain, &Flag); MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); break; } else { @@ -5249,7 +5249,8 @@ exit(1); } - OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); + OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), + Chain, &Flag); OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands); @@ -5270,7 +5271,7 @@ AsmNodeOperands[0] = Chain; if (Flag.getNode()) AsmNodeOperands.push_back(Flag); - Chain = DAG.getNode(ISD::INLINEASM, DAG.getCurDebugLoc(), + Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, &AsmNodeOperands[0], AsmNodeOperands.size()); Flag = Chain.getValue(1); @@ -5278,7 +5279,8 @@ // If this asm returns a register value, copy the result from that register // and set it as the value of the call. if (!RetValRegs.Regs.empty()) { - SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag); + SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(), + Chain, &Flag); // FIXME: Why don't we do this for inline asms with MRVs? if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { @@ -5290,7 +5292,7 @@ // not have the same VT as was expected. Convert it to the right type // with bit_convert. if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { - Val = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), + Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), ResultType, Val); } else if (ResultType != Val.getValueType() && @@ -5298,7 +5300,7 @@ // If a result value was tied to an input value, the computed result may // have a wider width than the expected result. Extract the relevant // portion. - Val = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), ResultType, Val); + Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); } assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); @@ -5314,19 +5316,20 @@ for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { RegsForValue &OutRegs = IndirectStoresToEmit[i].first; Value *Ptr = IndirectStoresToEmit[i].second; - SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag); + SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(), + Chain, &Flag); StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); } // Emit the non-flagged stores from the physregs. SmallVector OutChains; for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) - OutChains.push_back(DAG.getStore(Chain, DAG.getCurDebugLoc(), + OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(), StoresToEmit[i].first, getValue(StoresToEmit[i].second), StoresToEmit[i].second, 0)); if (!OutChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, DAG.getCurDebugLoc(), MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, &OutChains[0], OutChains.size()); DAG.setRoot(Chain); } @@ -5338,13 +5341,13 @@ MVT IntPtr = TLI.getPointerTy(); if (IntPtr.bitsLT(Src.getValueType())) - Src = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), IntPtr, Src); + Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src); else if (IntPtr.bitsGT(Src.getValueType())) - Src = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), IntPtr, Src); + Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src); // Scale the source by the type size. uint64_t ElementSize = TD->getTypePaddedSize(I.getType()->getElementType()); - Src = DAG.getNode(ISD::MUL, DAG.getCurDebugLoc(), Src.getValueType(), + Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(), Src, DAG.getIntPtrConstant(ElementSize)); TargetLowering::ArgListTy Args; @@ -5357,7 +5360,7 @@ TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false, CallingConv::C, PerformTailCallOpt, DAG.getExternalSymbol("malloc", IntPtr), - Args, DAG, DAG.getCurDebugLoc()); + Args, DAG, getCurDebugLoc()); setValue(&I, Result.first); // Pointers always fit in registers DAG.setRoot(Result.second); } @@ -5373,12 +5376,12 @@ TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false, CallingConv::C, PerformTailCallOpt, DAG.getExternalSymbol("free", IntPtr), Args, DAG, - DAG.getCurDebugLoc()); + getCurDebugLoc()); DAG.setRoot(Result.second); } void SelectionDAGLowering::visitVAStart(CallInst &I) { - DAG.setRoot(DAG.getNode(ISD::VASTART, DAG.getCurDebugLoc(), + DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), MVT::Other, getRoot(), getValue(I.getOperand(1)), DAG.getSrcValue(I.getOperand(1)))); @@ -5393,14 +5396,14 @@ } void SelectionDAGLowering::visitVAEnd(CallInst &I) { - DAG.setRoot(DAG.getNode(ISD::VAEND, DAG.getCurDebugLoc(), + DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), MVT::Other, getRoot(), getValue(I.getOperand(1)), DAG.getSrcValue(I.getOperand(1)))); } void SelectionDAGLowering::visitVACopy(CallInst &I) { - DAG.setRoot(DAG.getNode(ISD::VACOPY, DAG.getCurDebugLoc(), + DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), MVT::Other, getRoot(), getValue(I.getOperand(1)), getValue(I.getOperand(2)), @@ -5529,8 +5532,8 @@ else if (F.paramHasAttr(Idx, Attribute::ZExt)) AssertOp = ISD::AssertZext; - ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT, - AssertOp)); + ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts, + PartVT, VT, AssertOp)); } } assert(i == NumArgRegs && "Argument register count mismatch!"); @@ -5604,7 +5607,7 @@ else if (Args[i].isZExt) ExtendKind = ISD::ZERO_EXTEND; - getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind); + getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind); for (unsigned i = 0; i != NumParts; ++i) { // if it isn't first piece, alignment must be 1 @@ -5666,7 +5669,7 @@ for (; RegNo != RegNoEnd; ++RegNo) Results.push_back(Res.getValue(RegNo)); SDValue ReturnValue = - getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, + getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT, AssertOp); ReturnValues.push_back(ReturnValue); } @@ -5702,7 +5705,7 @@ RegsForValue RFV(TLI, Reg, V->getType()); SDValue Chain = DAG.getEntryNode(); - RFV.getCopyToRegs(Op, DAG, Chain, 0); + RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); PendingExports.push_back(Chain); } @@ -5714,7 +5717,7 @@ Function &F = *LLVMBB->getParent(); SDValue OldRoot = SDL->DAG.getRoot(); SmallVector Args; - TLI.LowerArguments(F, SDL->DAG, Args, SDL->DAG.getCurDebugLoc()); + TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc()); unsigned a = 0; for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h?rev=63468&r1=63467&r2=63468&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Fri Jan 30 20:22:37 2009 @@ -164,6 +164,9 @@ class SelectionDAGLowering { MachineBasicBlock *CurMBB; + /// CurDebugLoc - current file + line number. Changes as we build the DAG. + DebugLoc CurDebugLoc; + DenseMap NodeMap; /// PendingLoads - Loads are not emitted to the program immediately. We bunch @@ -356,7 +359,8 @@ SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, FunctionLoweringInfo &funcinfo) - : TLI(tli), DAG(dag), FuncInfo(funcinfo) { + : CurDebugLoc(DebugLoc::getUnknownLoc()), + TLI(tli), DAG(dag), FuncInfo(funcinfo) { } void init(GCFunctionInfo *gfi, AliasAnalysis &aa); @@ -382,6 +386,8 @@ /// SDValue getControlRoot(); + DebugLoc getCurDebugLoc() const { return CurDebugLoc; } + void CopyValueToVirtualRegister(Value *V, unsigned Reg); void visit(Instruction &I); @@ -531,6 +537,8 @@ const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op); const char *implVisitAluOverflow(CallInst &I, ISD::NodeType Op); + + void setCurDebugLoc(DebugLoc dl) { CurDebugLoc = dl; } }; /// AddCatchInfo - Extract the personality and type infos from an eh.selector From sabre at nondot.org Fri Jan 30 20:28:54 2009 From: sabre at nondot.org (Chris Lattner) Date: Sat, 31 Jan 2009 02:28:54 -0000 Subject: [llvm-commits] [llvm] r63469 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll test/Transforms/ScalarRepl/2006-11-07-InvalidArrayPromote.ll test/Transforms/ScalarRepl/badarray.ll test/Transforms/ScalarRepl/bitfield-sroa.ll Message-ID: <200901310228.n0V2Ssue025605@zion.cs.uiuc.edu> Author: lattner Date: Fri Jan 30 20:28:54 2009 New Revision: 63469 URL: http://llvm.org/viewvc/llvm-project?rev=63469&view=rev Log: Simplify and generalize the SROA "convert to scalar" transformation to be able to handle *ANY* alloca that is poked by loads and stores of bitcasts and GEPs with constant offsets. Before the code had a number of annoying limitations and caused it to miss cases such as storing into holes in structs and complex casts (as in bitfield-sroa) where we had unions of bitfields etc. This also handles a number of important cases that are exposed due to the ABI lowering stuff we do to pass stuff by value. One case that is pretty great is that we compile 2006-11-07-InvalidArrayPromote.ll into: define i32 @func(<4 x float> %v0, <4 x float> %v1) nounwind { %tmp10 = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %v1) %tmp105 = bitcast <4 x i32> %tmp10 to i128 %tmp1056 = zext i128 %tmp105 to i256 %tmp.upgrd.43 = lshr i256 %tmp1056, 96 %tmp.upgrd.44 = trunc i256 %tmp.upgrd.43 to i32 ret i32 %tmp.upgrd.44 } which turns into: _func: subl $28, %esp cvttps2dq %xmm1, %xmm0 movaps %xmm0, (%esp) movl 12(%esp), %eax addl $28, %esp ret Which is pretty good code all things considering :). One effect of this is that SROA will start generating arbitrary bitwidth integers that are a multiple of 8 bits. In the case above, we got a 256 bit integer, but the codegen guys assure me that it can handle the simple and/or/shift/zext stuff that we're doing on these operations. This addresses rdar://6532315 Added: llvm/trunk/test/Transforms/ScalarRepl/bitfield-sroa.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/trunk/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll llvm/trunk/test/Transforms/ScalarRepl/2006-11-07-InvalidArrayPromote.ll llvm/trunk/test/Transforms/ScalarRepl/badarray.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=63469&r1=63468&r2=63469&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Fri Jan 30 20:28:54 2009 @@ -125,13 +125,14 @@ void RewriteLoadUserOfWholeAlloca(LoadInst *LI, AllocationInst *AI, SmallVector &NewElts); - const Type *CanConvertToScalar(Value *V, bool &IsNotTrivial); + bool CanConvertToScalar(Value *V, bool &IsNotTrivial, const Type *&ResTy, + uint64_t Offset); void ConvertToScalar(AllocationInst *AI, const Type *Ty); - void ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, unsigned Offset); + void ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, uint64_t Offset); Value *ConvertUsesOfLoadToScalar(LoadInst *LI, AllocaInst *NewAI, - unsigned Offset); + uint64_t Offset); Value *ConvertUsesOfStoreToScalar(StoreInst *SI, AllocaInst *NewAI, - unsigned Offset); + uint64_t Offset); static Instruction *isOnlyCopiedFromConstantGlobal(AllocationInst *AI); }; } @@ -271,9 +272,15 @@ // If we can turn this aggregate value (potentially with casts) into a // simple scalar value that can be mem2reg'd into a register value. + // IsNotTrivial tracks whether this is something that mem2reg could have + // promoted itself. If so, we don't want to transform it needlessly. Note + // that we can't just check based on the type: the alloca may be of an i32 + // but that has pointer arithmetic to set byte 3 of it or something. bool IsNotTrivial = false; - if (const Type *ActualType = CanConvertToScalar(AI, IsNotTrivial)) - if (IsNotTrivial && ActualType != Type::VoidTy) { + const Type *ActualType = 0; + if (CanConvertToScalar(AI, IsNotTrivial, ActualType, 0)) + if (IsNotTrivial && ActualType && + TD->getTypeSizeInBits(ActualType) < SRThreshold*8) { ConvertToScalar(AI, ActualType); Changed = true; continue; @@ -1145,229 +1152,124 @@ } } -/// MergeInType - Add the 'In' type to the accumulated type so far. If the -/// types are incompatible, return true, otherwise update Accum and return -/// false. +/// MergeInType - Add the 'In' type to the accumulated type (Accum) so far at +/// the offset specified by Offset (which is specified in bytes). /// -/// There are three cases we handle here: -/// 1) An effectively-integer union, where the pieces are stored into as -/// smaller integers (common with byte swap and other idioms). -/// 2) A union of vector types of the same size and potentially its elements. +/// There are two cases we handle here: +/// 1) A union of vector types of the same size and potentially its elements. /// Here we turn element accesses into insert/extract element operations. -/// 3) A union of scalar types, such as int/float or int/pointer. Here we -/// merge together into integers, allowing the xform to work with #1 as -/// well. -static bool MergeInType(const Type *In, const Type *&Accum, +/// This promotes a <4 x float> with a store of float to the third element +/// into a <4 x float> that uses insert element. +/// 2) A fully general blob of memory, which we turn into some (potentially +/// large) integer type with extract and insert operations where the loads +/// and stores would mutate the memory. +static void MergeInType(const Type *In, uint64_t Offset, const Type *&Accum, const TargetData &TD) { // If this is our first type, just use it. - const VectorType *PTy; - if (Accum == Type::VoidTy || In == Accum) { + if (Accum == 0 || In == Type::VoidTy || + // Or if this is a same type, keep it. + (In == Accum && Offset == 0)) { Accum = In; - } else if (In == Type::VoidTy) { - // Noop. - } else if (In->isInteger() && Accum->isInteger()) { // integer union. - // Otherwise pick whichever type is larger. - if (cast(In)->getBitWidth() > - cast(Accum)->getBitWidth()) - Accum = In; - } else if (isa(In) && isa(Accum)) { - // Pointer unions just stay as one of the pointers. - } else if (isa(In) || isa(Accum)) { - if ((PTy = dyn_cast(Accum)) && - PTy->getElementType() == In) { - // Accum is a vector, and we are accessing an element: ok. - } else if ((PTy = dyn_cast(In)) && - PTy->getElementType() == Accum) { - // In is a vector, and accum is an element: ok, remember In. - Accum = In; - } else if ((PTy = dyn_cast(In)) && isa(Accum) && - PTy->getBitWidth() == cast(Accum)->getBitWidth()) { - // Two vectors of the same size: keep Accum. - } else { - // Cannot insert an short into a <4 x int> or handle - // <2 x int> -> <4 x int> - return true; - } - } else { - // Pointer/FP/Integer unions merge together as integers. - switch (Accum->getTypeID()) { - case Type::PointerTyID: Accum = TD.getIntPtrType(); break; - case Type::FloatTyID: Accum = Type::Int32Ty; break; - case Type::DoubleTyID: Accum = Type::Int64Ty; break; - case Type::X86_FP80TyID: return true; - case Type::FP128TyID: return true; - case Type::PPC_FP128TyID: return true; - default: - assert(Accum->isInteger() && "Unknown FP type!"); - break; - } - - switch (In->getTypeID()) { - case Type::PointerTyID: In = TD.getIntPtrType(); break; - case Type::FloatTyID: In = Type::Int32Ty; break; - case Type::DoubleTyID: In = Type::Int64Ty; break; - case Type::X86_FP80TyID: return true; - case Type::FP128TyID: return true; - case Type::PPC_FP128TyID: return true; - default: - assert(In->isInteger() && "Unknown FP type!"); - break; + return; + } + + if (const VectorType *VATy = dyn_cast(Accum)) { + if (VATy->getElementType() == In && + Offset % TD.getTypePaddedSize(In) == 0 && + Offset < TD.getTypePaddedSize(VATy)) + return; // Accum is a vector, and we are accessing an element: ok. + if (const VectorType *VInTy = dyn_cast(In)) + if (VInTy->getBitWidth() == VATy->getBitWidth() && Offset == 0) + return; // Two vectors of the same size: keep either one of them. + } + + if (const VectorType *VInTy = dyn_cast(In)) { + // In is a vector, and we are accessing an element: keep V. + if (VInTy->getElementType() == Accum && + Offset % TD.getTypePaddedSize(Accum) == 0 && + Offset < TD.getTypePaddedSize(VInTy)) { + Accum = VInTy; + return; } - return MergeInType(In, Accum, TD); } - return false; -} - -/// getIntAtLeastAsBigAs - Return an integer type that is at least as big as the -/// specified type. If there is no suitable type, this returns null. -const Type *getIntAtLeastAsBigAs(unsigned NumBits) { - if (NumBits > 64) return 0; - if (NumBits > 32) return Type::Int64Ty; - if (NumBits > 16) return Type::Int32Ty; - if (NumBits > 8) return Type::Int16Ty; - return Type::Int8Ty; -} - -/// CanConvertToScalar - V is a pointer. If we can convert the pointee to a -/// single scalar integer type, return that type. Further, if the use is not -/// a completely trivial use that mem2reg could promote, set IsNotTrivial. If -/// there are no uses of this pointer, return Type::VoidTy to differentiate from -/// failure. + + // Otherwise, we have a case that we can't handle with an optimized form. + // Convert the alloca to an integer that is as large as the largest store size + // of the value values. + uint64_t InSize = TD.getTypeStoreSizeInBits(In)+8*Offset; + uint64_t ASize = TD.getTypeStoreSizeInBits(Accum); + if (InSize > ASize) ASize = InSize; + Accum = IntegerType::get(ASize); +} + +/// CanConvertToScalar - V is a pointer. If we can convert the pointee and all +/// its accesses to use a to single scalar type, return true, and set ResTy to +/// the new type. Further, if the use is not a completely trivial use that +/// mem2reg could promote, set IsNotTrivial. Offset is the current offset from +/// the base of the alloca being analyzed. /// -const Type *SROA::CanConvertToScalar(Value *V, bool &IsNotTrivial) { - const Type *UsedType = Type::VoidTy; // No uses, no forced type. - const PointerType *PTy = cast(V->getType()); - +bool SROA::CanConvertToScalar(Value *V, bool &IsNotTrivial, + const Type *&ResTy, uint64_t Offset) { for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI!=E; ++UI) { Instruction *User = cast(*UI); if (LoadInst *LI = dyn_cast(User)) { + // Don't break volatile loads. if (LI->isVolatile()) - return 0; - - // FIXME: Loads of a first class aggregrate value could be converted to a - // series of loads and insertvalues - if (!LI->getType()->isSingleValueType()) - return 0; - - if (MergeInType(LI->getType(), UsedType, *TD)) - return 0; + return false; + MergeInType(LI->getType(), Offset, ResTy, *TD); continue; } if (StoreInst *SI = dyn_cast(User)) { // Storing the pointer, not into the value? if (SI->getOperand(0) == V || SI->isVolatile()) return 0; - - // FIXME: Stores of a first class aggregrate value could be converted to a - // series of extractvalues and stores - if (!SI->getOperand(0)->getType()->isSingleValueType()) - return 0; - - // NOTE: We could handle storing of FP imms into integers here! - - if (MergeInType(SI->getOperand(0)->getType(), UsedType, *TD)) - return 0; + MergeInType(SI->getOperand(0)->getType(), Offset, ResTy, *TD); continue; } - if (BitCastInst *CI = dyn_cast(User)) { + + if (BitCastInst *BCI = dyn_cast(User)) { + if (!CanConvertToScalar(BCI, IsNotTrivial, ResTy, Offset)) + return false; IsNotTrivial = true; - const Type *SubTy = CanConvertToScalar(CI, IsNotTrivial); - if (!SubTy || MergeInType(SubTy, UsedType, *TD)) return 0; continue; } if (GetElementPtrInst *GEP = dyn_cast(User)) { - // Check to see if this is stepping over an element: GEP Ptr, int C - if (GEP->getNumOperands() == 2 && isa(GEP->getOperand(1))) { - unsigned Idx = cast(GEP->getOperand(1))->getZExtValue(); - unsigned ElSize = TD->getTypePaddedSize(PTy->getElementType()); - unsigned BitOffset = Idx*ElSize*8; - if (BitOffset > 64 || !isPowerOf2_32(ElSize)) return 0; - - IsNotTrivial = true; - const Type *SubElt = CanConvertToScalar(GEP, IsNotTrivial); - if (SubElt == 0) return 0; - if (SubElt != Type::VoidTy && SubElt->isInteger()) { - const Type *NewTy = - getIntAtLeastAsBigAs(TD->getTypePaddedSizeInBits(SubElt)+BitOffset); - if (NewTy == 0 || MergeInType(NewTy, UsedType, *TD)) return 0; - continue; - } - // Cannot handle this! - return 0; - } + // If this is a GEP with a variable indices, we can't handle it. + if (!GEP->hasAllConstantIndices()) + return false; - if (GEP->getNumOperands() == 3 && - isa(GEP->getOperand(1)) && - isa(GEP->getOperand(2)) && - cast(GEP->getOperand(1))->isZero()) { - // We are stepping into an element, e.g. a structure or an array: - // GEP Ptr, i32 0, i32 Cst - const Type *AggTy = PTy->getElementType(); - unsigned Idx = cast(GEP->getOperand(2))->getZExtValue(); - - if (const ArrayType *ATy = dyn_cast(AggTy)) { - if (Idx >= ATy->getNumElements()) return 0; // Out of range. - } else if (const VectorType *VectorTy = dyn_cast(AggTy)) { - // Getting an element of the vector. - if (Idx >= VectorTy->getNumElements()) return 0; // Out of range. - - // Merge in the vector type. - if (MergeInType(VectorTy, UsedType, *TD)) return 0; - - const Type *SubTy = CanConvertToScalar(GEP, IsNotTrivial); - if (SubTy == 0) return 0; - - if (SubTy != Type::VoidTy && MergeInType(SubTy, UsedType, *TD)) - return 0; - - // We'll need to change this to an insert/extract element operation. - IsNotTrivial = true; - continue; // Everything looks ok - - } else if (isa(AggTy)) { - // Structs are always ok. - } else { - return 0; - } - const Type *NTy = - getIntAtLeastAsBigAs(TD->getTypePaddedSizeInBits(AggTy)); - if (NTy == 0 || MergeInType(NTy, UsedType, *TD)) return 0; - const Type *SubTy = CanConvertToScalar(GEP, IsNotTrivial); - if (SubTy == 0) return 0; - if (SubTy != Type::VoidTy && MergeInType(SubTy, UsedType, *TD)) - return 0; - continue; // Everything looks ok - } - return 0; + // Compute the offset that this GEP adds to the pointer. + SmallVector Indices(GEP->op_begin()+1, GEP->op_end()); + uint64_t GEPOffset = TD->getIndexedOffset(GEP->getOperand(0)->getType(), + &Indices[0], Indices.size()); + // See if all uses can be converted. + if (!CanConvertToScalar(GEP, IsNotTrivial, ResTy, Offset+GEPOffset)) + return false; + IsNotTrivial = true; + continue; } - // Cannot handle this! - return 0; + // Otherwise, we cannot handle this! + return false; } - return UsedType; + return true; } /// ConvertToScalar - The specified alloca passes the CanConvertToScalar /// predicate and is non-trivial. Convert it to something that can be trivially /// promoted into a register by mem2reg. void SROA::ConvertToScalar(AllocationInst *AI, const Type *ActualTy) { - DOUT << "CONVERT TO SCALAR: " << *AI << " TYPE = " - << *ActualTy << "\n"; + DOUT << "CONVERT TO SCALAR: " << *AI << " TYPE = " << *ActualTy << "\n"; ++NumConverted; - BasicBlock *EntryBlock = AI->getParent(); - assert(EntryBlock == &EntryBlock->getParent()->getEntryBlock() && - "Not in the entry block!"); - EntryBlock->getInstList().remove(AI); // Take the alloca out of the program. - // Create and insert the alloca. AllocaInst *NewAI = new AllocaInst(ActualTy, 0, AI->getName(), - EntryBlock->begin()); + AI->getParent()->begin()); ConvertUsesToScalar(AI, NewAI, 0); - delete AI; + AI->eraseFromParent(); } @@ -1378,22 +1280,19 @@ /// /// Offset is an offset from the original alloca, in bits that need to be /// shifted to the right. By the end of this, there should be no uses of Ptr. -void SROA::ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, unsigned Offset) { +void SROA::ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, uint64_t Offset) { while (!Ptr->use_empty()) { Instruction *User = cast(Ptr->use_back()); if (LoadInst *LI = dyn_cast(User)) { - Value *NV = ConvertUsesOfLoadToScalar(LI, NewAI, Offset); - LI->replaceAllUsesWith(NV); + LI->replaceAllUsesWith(ConvertUsesOfLoadToScalar(LI, NewAI, Offset)); LI->eraseFromParent(); continue; } if (StoreInst *SI = dyn_cast(User)) { assert(SI->getOperand(0) != Ptr && "Consistency error!"); - - Value *SV = ConvertUsesOfStoreToScalar(SI, NewAI, Offset); - new StoreInst(SV, NewAI, SI); + new StoreInst(ConvertUsesOfStoreToScalar(SI, NewAI, Offset), NewAI, SI); SI->eraseFromParent(); continue; } @@ -1405,45 +1304,14 @@ } if (GetElementPtrInst *GEP = dyn_cast(User)) { - const PointerType *AggPtrTy = - cast(GEP->getOperand(0)->getType()); - unsigned AggSizeInBits = - TD->getTypePaddedSizeInBits(AggPtrTy->getElementType()); - - // Check to see if this is stepping over an element: GEP Ptr, int C - unsigned NewOffset = Offset; - if (GEP->getNumOperands() == 2) { - unsigned Idx = cast(GEP->getOperand(1))->getZExtValue(); - unsigned BitOffset = Idx*AggSizeInBits; - - NewOffset += BitOffset; - ConvertUsesToScalar(GEP, NewAI, NewOffset); - GEP->eraseFromParent(); - continue; - } - - assert(GEP->getNumOperands() == 3 && "Unsupported operation"); - - // We know that operand #2 is zero. - unsigned Idx = cast(GEP->getOperand(2))->getZExtValue(); - const Type *AggTy = AggPtrTy->getElementType(); - if (const SequentialType *SeqTy = dyn_cast(AggTy)) { - unsigned ElSizeBits = - TD->getTypePaddedSizeInBits(SeqTy->getElementType()); - - NewOffset += ElSizeBits*Idx; - } else { - const StructType *STy = cast(AggTy); - unsigned EltBitOffset = - TD->getStructLayout(STy)->getElementOffsetInBits(Idx); - - NewOffset += EltBitOffset; - } - ConvertUsesToScalar(GEP, NewAI, NewOffset); + // Compute the offset that this GEP adds to the pointer. + SmallVector Indices(GEP->op_begin()+1, GEP->op_end()); + uint64_t GEPOffset = TD->getIndexedOffset(GEP->getOperand(0)->getType(), + &Indices[0], Indices.size()); + ConvertUsesToScalar(GEP, NewAI, Offset+GEPOffset*8); GEP->eraseFromParent(); continue; } - assert(0 && "Unsupported operation!"); abort(); } @@ -1455,28 +1323,20 @@ /// single integer scalar, or when we are converting a "vector union" to a /// vector with insert/extractelement instructions. /// -/// Offset is an offset from the original alloca, in bits that need to be +/// Offset is an offset from the original alloca, in bytes that need to be /// shifted to the right. By the end of this, there should be no uses of Ptr. Value *SROA::ConvertUsesOfLoadToScalar(LoadInst *LI, AllocaInst *NewAI, - unsigned Offset) { + uint64_t Offset) { // The load is a bit extract from NewAI shifted right by Offset bits. Value *NV = new LoadInst(NewAI, LI->getName(), LI); - if (NV->getType() == LI->getType() && Offset == 0) { - // We win, no conversion needed. + // If the load is of the whole new alloca, no conversion is needed. + if (NV->getType() == LI->getType() && Offset == 0) return NV; - } - // If the result type of the 'union' is a pointer, then this must be ptr->ptr - // cast. Anything else would result in NV being an integer. - if (isa(NV->getType())) { - assert(isa(LI->getType())); - return new BitCastInst(NV, LI->getType(), LI->getName(), LI); - } - + // If the result alloca is a vector type, this is either an element + // access or a bitcast to another vector type of the same size. if (const VectorType *VTy = dyn_cast(NV->getType())) { - // If the result alloca is a vector type, this is either an element - // access or a bitcast to another vector type. if (isa(LI->getType())) return new BitCastInst(NV, LI->getType(), LI->getName(), LI); @@ -1485,16 +1345,14 @@ if (Offset) { unsigned EltSize = TD->getTypePaddedSizeInBits(VTy->getElementType()); Elt = Offset/EltSize; - Offset -= EltSize*Elt; + assert(EltSize*Elt == Offset && "Invalid modulus in validity checking"); } - NV = new ExtractElementInst(NV, ConstantInt::get(Type::Int32Ty, Elt), - "tmp", LI); - - // If we're done, return this element. - if (NV->getType() == LI->getType() && Offset == 0) - return NV; + // Return the element extracted out of it. + return new ExtractElementInst(NV, ConstantInt::get(Type::Int32Ty, Elt), + "tmp", LI); } + // Otherwise, this must be a union that was converted to an integer value. const IntegerType *NTy = cast(NV->getType()); // If this is a big-endian system and the load is narrower than the @@ -1514,12 +1372,12 @@ // We do this to support (f.e.) loads off the end of a structure where // only some bits are used. if (ShAmt > 0 && (unsigned)ShAmt < NTy->getBitWidth()) - NV = BinaryOperator::CreateLShr(NV, - ConstantInt::get(NV->getType(),ShAmt), + NV = BinaryOperator::CreateLShr(NV, + ConstantInt::get(NV->getType(), ShAmt), LI->getName(), LI); else if (ShAmt < 0 && (unsigned)-ShAmt < NTy->getBitWidth()) - NV = BinaryOperator::CreateShl(NV, - ConstantInt::get(NV->getType(),-ShAmt), + NV = BinaryOperator::CreateShl(NV, + ConstantInt::get(NV->getType(), -ShAmt), LI->getName(), LI); // Finally, unconditionally truncate the integer to the right width. @@ -1531,7 +1389,8 @@ // If the result is an integer, this is a trunc or bitcast. if (isa(LI->getType())) { // Should be done. - } else if (LI->getType()->isFloatingPoint()) { + } else if (LI->getType()->isFloatingPoint() || + isa(LI->getType())) { // Just do a bitcast, we know the sizes match up. NV = new BitCastInst(NV, LI->getType(), LI->getName(), LI); } else { @@ -1552,15 +1411,17 @@ /// Offset is an offset from the original alloca, in bits that need to be /// shifted to the right. By the end of this, there should be no uses of Ptr. Value *SROA::ConvertUsesOfStoreToScalar(StoreInst *SI, AllocaInst *NewAI, - unsigned Offset) { + uint64_t Offset) { // Convert the stored type to the actual type, shift it left to insert // then 'or' into place. Value *SV = SI->getOperand(0); const Type *AllocaType = NewAI->getType()->getElementType(); if (SV->getType() == AllocaType && Offset == 0) { - // All is well. - } else if (const VectorType *PTy = dyn_cast(AllocaType)) { + return SV; + } + + if (const VectorType *VTy = dyn_cast(AllocaType)) { Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", SI); // If the result alloca is a vector type, this is either an element @@ -1569,72 +1430,68 @@ SV = new BitCastInst(SV, AllocaType, SV->getName(), SI); } else { // Must be an element insertion. - unsigned Elt = Offset/TD->getTypePaddedSizeInBits(PTy->getElementType()); + unsigned Elt = Offset/TD->getTypePaddedSizeInBits(VTy->getElementType()); SV = InsertElementInst::Create(Old, SV, ConstantInt::get(Type::Int32Ty, Elt), "tmp", SI); } - } else if (isa(AllocaType)) { - // If the alloca type is a pointer, then all the elements must be - // pointers. - if (SV->getType() != AllocaType) - SV = new BitCastInst(SV, AllocaType, SV->getName(), SI); + return SV; + } + + + Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", SI); + + // If SV is a float, convert it to the appropriate integer type. + // If it is a pointer, do the same, and also handle ptr->ptr casts + // here. + unsigned SrcWidth = TD->getTypeSizeInBits(SV->getType()); + unsigned DestWidth = TD->getTypeSizeInBits(AllocaType); + unsigned SrcStoreWidth = TD->getTypeStoreSizeInBits(SV->getType()); + unsigned DestStoreWidth = TD->getTypeStoreSizeInBits(AllocaType); + if (SV->getType()->isFloatingPoint() || isa(SV->getType())) + SV = new BitCastInst(SV, IntegerType::get(SrcWidth), SV->getName(), SI); + else if (isa(SV->getType())) + SV = new PtrToIntInst(SV, TD->getIntPtrType(), SV->getName(), SI); + + // Always zero extend the value if needed. + if (SV->getType() != AllocaType) + SV = new ZExtInst(SV, AllocaType, SV->getName(), SI); + + // If this is a big-endian system and the store is narrower than the + // full alloca type, we need to do a shift to get the right bits. + int ShAmt = 0; + if (TD->isBigEndian()) { + // On big-endian machines, the lowest bit is stored at the bit offset + // from the pointer given by getTypeStoreSizeInBits. This matters for + // integers with a bitwidth that is not a multiple of 8. + ShAmt = DestStoreWidth - SrcStoreWidth - Offset; } else { - Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", SI); - - // If SV is a float, convert it to the appropriate integer type. - // If it is a pointer, do the same, and also handle ptr->ptr casts - // here. - unsigned SrcWidth = TD->getTypeSizeInBits(SV->getType()); - unsigned DestWidth = TD->getTypeSizeInBits(AllocaType); - unsigned SrcStoreWidth = TD->getTypeStoreSizeInBits(SV->getType()); - unsigned DestStoreWidth = TD->getTypeStoreSizeInBits(AllocaType); - if (SV->getType()->isFloatingPoint()) - SV = new BitCastInst(SV, IntegerType::get(SrcWidth), - SV->getName(), SI); - else if (isa(SV->getType())) - SV = new PtrToIntInst(SV, TD->getIntPtrType(), SV->getName(), SI); - - // Always zero extend the value if needed. - if (SV->getType() != AllocaType) - SV = new ZExtInst(SV, AllocaType, SV->getName(), SI); - - // If this is a big-endian system and the store is narrower than the - // full alloca type, we need to do a shift to get the right bits. - int ShAmt = 0; - if (TD->isBigEndian()) { - // On big-endian machines, the lowest bit is stored at the bit offset - // from the pointer given by getTypeStoreSizeInBits. This matters for - // integers with a bitwidth that is not a multiple of 8. - ShAmt = DestStoreWidth - SrcStoreWidth - Offset; - } else { - ShAmt = Offset; - } - - // Note: we support negative bitwidths (with shr) which are not defined. - // We do this to support (f.e.) stores off the end of a structure where - // only some bits in the structure are set. - APInt Mask(APInt::getLowBitsSet(DestWidth, SrcWidth)); - if (ShAmt > 0 && (unsigned)ShAmt < DestWidth) { - SV = BinaryOperator::CreateShl(SV, - ConstantInt::get(SV->getType(), ShAmt), - SV->getName(), SI); - Mask <<= ShAmt; - } else if (ShAmt < 0 && (unsigned)-ShAmt < DestWidth) { - SV = BinaryOperator::CreateLShr(SV, - ConstantInt::get(SV->getType(),-ShAmt), - SV->getName(), SI); - Mask = Mask.lshr(ShAmt); - } - - // Mask out the bits we are about to insert from the old value, and or - // in the new bits. - if (SrcWidth != DestWidth) { - assert(DestWidth > SrcWidth); - Old = BinaryOperator::CreateAnd(Old, ConstantInt::get(~Mask), - Old->getName()+".mask", SI); - SV = BinaryOperator::CreateOr(Old, SV, SV->getName()+".ins", SI); - } + ShAmt = Offset; + } + + // Note: we support negative bitwidths (with shr) which are not defined. + // We do this to support (f.e.) stores off the end of a structure where + // only some bits in the structure are set. + APInt Mask(APInt::getLowBitsSet(DestWidth, SrcWidth)); + if (ShAmt > 0 && (unsigned)ShAmt < DestWidth) { + SV = BinaryOperator::CreateShl(SV, + ConstantInt::get(SV->getType(), ShAmt), + SV->getName(), SI); + Mask <<= ShAmt; + } else if (ShAmt < 0 && (unsigned)-ShAmt < DestWidth) { + SV = BinaryOperator::CreateLShr(SV, + ConstantInt::get(SV->getType(),-ShAmt), + SV->getName(), SI); + Mask = Mask.lshr(ShAmt); + } + + // Mask out the bits we are about to insert from the old value, and or + // in the new bits. + if (SrcWidth != DestWidth) { + assert(DestWidth > SrcWidth); + Old = BinaryOperator::CreateAnd(Old, ConstantInt::get(~Mask), + Old->getName()+".mask", SI); + SV = BinaryOperator::CreateOr(Old, SV, SV->getName()+".ins", SI); } return SV; } Modified: llvm/trunk/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll?rev=63469&r1=63468&r2=63469&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll Fri Jan 30 20:28:54 2009 @@ -1,9 +1,8 @@ -; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | \ -; RUN: grep alloca | grep {4 x} +; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | grep {ret i32 undef} -; Test that an array is not incorrectly deconstructed... +; Test that an array is not incorrectly deconstructed. -define i32 @test() { +define i32 @test() nounwind { %X = alloca [4 x i32] ; <[4 x i32]*> [#uses=1] %Y = getelementptr [4 x i32]* %X, i64 0, i64 0 ; [#uses=1] ; Must preserve arrayness! Modified: llvm/trunk/test/Transforms/ScalarRepl/2006-11-07-InvalidArrayPromote.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/2006-11-07-InvalidArrayPromote.ll?rev=63469&r1=63468&r2=63469&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/2006-11-07-InvalidArrayPromote.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/2006-11-07-InvalidArrayPromote.ll Fri Jan 30 20:28:54 2009 @@ -1,7 +1,6 @@ -; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | \ -; RUN: grep -F {alloca \[2 x <4 x i32>\]} +; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | not grep alloca -define i32 @func(<4 x float> %v0, <4 x float> %v1) { +define i32 @func(<4 x float> %v0, <4 x float> %v1) nounwind { %vsiidx = alloca [2 x <4 x i32>], align 16 ; <[2 x <4 x i32>]*> [#uses=3] %tmp = call <4 x i32> @llvm.x86.sse2.cvttps2dq( <4 x float> %v0 ) ; <<4 x i32>> [#uses=2] %tmp.upgrd.1 = bitcast <4 x i32> %tmp to <2 x i64> ; <<2 x i64>> [#uses=0] Modified: llvm/trunk/test/Transforms/ScalarRepl/badarray.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/badarray.ll?rev=63469&r1=63468&r2=63469&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/badarray.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/badarray.ll Fri Jan 30 20:28:54 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | opt -scalarrepl -mem2reg | llvm-dis | grep alloca +; RUN: llvm-as < %s | opt -scalarrepl -instcombine | llvm-dis | grep {ret i32 0} define i32 @test() { %X = alloca [4 x i32] ; <[4 x i32]*> [#uses=1] Added: llvm/trunk/test/Transforms/ScalarRepl/bitfield-sroa.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/bitfield-sroa.ll?rev=63469&view=auto ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/bitfield-sroa.ll (added) +++ llvm/trunk/test/Transforms/ScalarRepl/bitfield-sroa.ll Fri Jan 30 20:28:54 2009 @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | not grep alloca +; rdar://6532315 +%t = type { { i32, i16, i8, i8 } } + +define i8 @foo(i64 %A) { + %ALL = alloca %t, align 8 + %tmp59172 = bitcast %t* %ALL to i64* + store i64 %A, i64* %tmp59172, align 8 + %C = getelementptr %t* %ALL, i32 0, i32 0, i32 1 + %D = bitcast i16* %C to i32* + %E = load i32* %D, align 4 + %F = bitcast %t* %ALL to i8* + %G = load i8* %F, align 8 + ret i8 %G +} + From isanbard at gmail.com Fri Jan 30 21:12:48 2009 From: isanbard at gmail.com (Bill Wendling) Date: Sat, 31 Jan 2009 03:12:48 -0000 Subject: [llvm-commits] [llvm] r63473 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200901310312.n0V3CmJl026851@zion.cs.uiuc.edu> Author: void Date: Fri Jan 30 21:12:48 2009 New Revision: 63473 URL: http://llvm.org/viewvc/llvm-project?rev=63473&view=rev Log: Don't use DebugLoc::getUnknownLoc(). Default to something hopefully sensible. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63473&r1=63472&r2=63473&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 30 21:12:48 2009 @@ -1947,7 +1947,7 @@ SDValue NewPtr = LN0->getBasePtr(); if (TLI.isBigEndian()) { - NewPtr = DAG.getNode(ISD::ADD, DebugLoc::getUnknownLoc(), PtrType, + NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, NewPtr, DAG.getConstant(PtrOff, PtrType)); Alignment = MinAlign(Alignment, PtrOff); } @@ -2636,9 +2636,11 @@ uint64_t TruncC = TruncVT.getIntegerVTBitMask() & N101C->getZExtValue(); return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, - DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(), + DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, - DAG.getNode(ISD::TRUNCATE, TruncVT, N100), + DAG.getNode(ISD::TRUNCATE, + N->getDebugLoc(), + TruncVT, N100), DAG.getConstant(TruncC, TruncVT))); } } @@ -2759,9 +2761,11 @@ uint64_t TruncC = TruncVT.getIntegerVTBitMask() & N101C->getZExtValue(); return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, - DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(), + DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, - DAG.getNode(ISD::TRUNCATE, TruncVT, N100), + DAG.getNode(ISD::TRUNCATE, + N->getDebugLoc(), + TruncVT, N100), DAG.getConstant(TruncC, TruncVT))); } } @@ -3092,12 +3096,12 @@ if (SOp == Trunc) Ops.push_back(ExtLoad); else - Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, DebugLoc::getUnknownLoc(), + Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, SOp)); } Ops.push_back(SetCC->getOperand(2)); - CombineTo(SetCC, DAG.getNode(ISD::SETCC, DebugLoc::getUnknownLoc(), + CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), SetCC->getValueType(0), &Ops[0], Ops.size())); } @@ -3174,9 +3178,9 @@ (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { SDValue Op = N0.getOperand(0); if (Op.getValueType().bitsLT(VT)) { - Op = DAG.getNode(ISD::ANY_EXTEND, DebugLoc::getUnknownLoc(), VT, Op); + Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); } else if (Op.getValueType().bitsGT(VT)) { - Op = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, Op); + Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); } return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType()); } @@ -3187,9 +3191,9 @@ N0.getOperand(1).getOpcode() == ISD::Constant) { SDValue X = N0.getOperand(0).getOperand(0); if (X.getValueType().bitsLT(VT)) { - X = DAG.getNode(ISD::ANY_EXTEND, DebugLoc::getUnknownLoc(), VT, X); + X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); } else if (X.getValueType().bitsGT(VT)) { - X = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, X); + X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); } APInt Mask = cast(N0.getOperand(1))->getAPIntValue(); Mask.zext(VT.getSizeInBits()); @@ -3228,11 +3232,12 @@ if (SOp == Trunc) Ops.push_back(ExtLoad); else - Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); + Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, + N->getDebugLoc(), VT, SOp)); } Ops.push_back(SetCC->getOperand(2)); - CombineTo(SetCC, DAG.getNode(ISD::SETCC, DebugLoc::getUnknownLoc(), + CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), SetCC->getValueType(0), &Ops[0], Ops.size())); } @@ -3317,9 +3322,9 @@ N0.getOperand(1).getOpcode() == ISD::Constant) { SDValue X = N0.getOperand(0).getOperand(0); if (X.getValueType().bitsLT(VT)) { - X = DAG.getNode(ISD::ANY_EXTEND, DebugLoc::getUnknownLoc(), VT, X); + X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); } else if (X.getValueType().bitsGT(VT)) { - X = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, X); + X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); } APInt Mask = cast(N0.getOperand(1))->getAPIntValue(); Mask.zext(VT.getSizeInBits()); @@ -3476,7 +3481,7 @@ uint64_t PtrOff = ShAmt / 8; unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); - SDValue NewPtr = DAG.getNode(ISD::ADD, DebugLoc::getUnknownLoc(), + SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, LN0->getBasePtr(), DAG.getConstant(PtrOff, PtrType)); AddToWorkList(NewPtr.getNode()); @@ -3773,34 +3778,34 @@ unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); MVT IntXVT = MVT::getIntegerVT(OrigXWidth); if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { - SDValue X = DAG.getNode(ISD::BIT_CONVERT, DebugLoc::getUnknownLoc(), + SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), IntXVT, N0.getOperand(1)); AddToWorkList(X.getNode()); // If X has a different width than the result/lhs, sext it or truncate it. unsigned VTWidth = VT.getSizeInBits(); if (OrigXWidth < VTWidth) { - X = DAG.getNode(ISD::SIGN_EXTEND, DebugLoc::getUnknownLoc(), VT, X); + X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); AddToWorkList(X.getNode()); } else if (OrigXWidth > VTWidth) { // To get the sign bit in the right place, we have to shift it right // before truncating. - X = DAG.getNode(ISD::SRL, DebugLoc::getUnknownLoc(), + X = DAG.getNode(ISD::SRL, X.getDebugLoc(), X.getValueType(), X, DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); AddToWorkList(X.getNode()); - X = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, X); + X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); AddToWorkList(X.getNode()); } APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); - X = DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(), VT, + X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, X, DAG.getConstant(SignBit, VT)); AddToWorkList(X.getNode()); - SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, DebugLoc::getUnknownLoc(), + SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, N0.getOperand(0)); - Cst = DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(), VT, + Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, Cst, DAG.getConstant(~SignBit, VT)); AddToWorkList(Cst.getNode()); @@ -3897,8 +3902,7 @@ } if (EltIsUndef) - Ops.push_back(DAG.getNode(ISD::UNDEF, DebugLoc::getUnknownLoc(), - DstEltVT)); + Ops.push_back(DAG.getNode(ISD::UNDEF, BV->getDebugLoc(), DstEltVT)); else Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); } @@ -3918,8 +3922,7 @@ for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { for (unsigned j = 0; j != NumOutputsPerInput; ++j) - Ops.push_back(DAG.getNode(ISD::UNDEF, DebugLoc::getUnknownLoc(), - DstEltVT)); + Ops.push_back(DAG.getNode(ISD::UNDEF, BV->getDebugLoc(), DstEltVT)); continue; } @@ -4136,8 +4139,7 @@ } else { if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, - DAG.getNode(ISD::FABS, DebugLoc::getUnknownLoc(), - VT, N0)); + DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); } } @@ -4349,7 +4351,7 @@ SDValue Int = N0.getOperand(0); MVT IntVT = Int.getValueType(); if (IntVT.isInteger() && !IntVT.isVector()) { - Int = DAG.getNode(ISD::XOR, DebugLoc::getUnknownLoc(), IntVT, Int, + Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT)); AddToWorkList(Int.getNode()); return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), @@ -4384,7 +4386,7 @@ SDValue Int = N0.getOperand(0); MVT IntVT = Int.getValueType(); if (IntVT.isInteger() && !IntVT.isVector()) { - Int = DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(), IntVT, Int, + Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT)); AddToWorkList(Int.getNode()); return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), @@ -4807,8 +4809,8 @@ WorkListRemover DeadNodes(*this); DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), - DAG.getNode(ISD::UNDEF, DebugLoc::getUnknownLoc(), - N->getValueType(1)), + DAG.getNode(ISD::UNDEF, N->getDebugLoc(), + N->getValueType(1)), &DeadNodes); DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); removeFromWorkList(N); @@ -5230,7 +5232,7 @@ for (unsigned i = 0; i != NumInScalars; ++i) { if (N->getOperand(i).getOpcode() == ISD::UNDEF) { BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, - DebugLoc::getUnknownLoc(), + N->getDebugLoc(), TLI.getPointerTy())); continue; } @@ -5460,13 +5462,13 @@ MVT VT = MVT::getVectorVT(EVT, NumElts); MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); std::vector Ops; - LHS = DAG.getNode(ISD::BIT_CONVERT, DebugLoc::getUnknownLoc(), VT, LHS); + LHS = DAG.getNode(ISD::BIT_CONVERT, LHS.getDebugLoc(), VT, LHS); Ops.push_back(LHS); AddToWorkList(LHS.getNode()); std::vector ZeroOps(NumElts, DAG.getConstant(0, EVT)); - Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), + Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, &ZeroOps[0], ZeroOps.size())); - Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), + Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MaskVT, &IdxOps[0], IdxOps.size())); SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), VT, &Ops[0], Ops.size()); @@ -5525,7 +5527,7 @@ break; } - Ops.push_back(DAG.getNode(N->getOpcode(), DebugLoc::getUnknownLoc(), + Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), EltType, LHSOp, RHSOp)); AddToWorkList(Ops.back().getNode()); assert((Ops.back().getOpcode() == ISD::UNDEF || @@ -5721,28 +5723,26 @@ unsigned ShCtV = N2C->getAPIntValue().logBase2(); ShCtV = XType.getSizeInBits()-ShCtV-1; SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); - SDValue Shift = DAG.getNode(ISD::SRL, DebugLoc::getUnknownLoc(), + SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, ShCt); AddToWorkList(Shift.getNode()); if (XType.bitsGT(AType)) { - Shift = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), - AType, Shift); + Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); AddToWorkList(Shift.getNode()); } return DAG.getNode(ISD::AND, DL, AType, Shift, N2); } - SDValue Shift = DAG.getNode(ISD::SRA, DebugLoc::getUnknownLoc(), + SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, DAG.getConstant(XType.getSizeInBits()-1, TLI.getShiftAmountTy())); AddToWorkList(Shift.getNode()); if (XType.bitsGT(AType)) { - Shift = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), - AType, Shift); + Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); AddToWorkList(Shift.getNode()); } @@ -5765,18 +5765,16 @@ SDValue Temp, SCC; // cast from setcc result type to select result type if (LegalTypes) { - SCC = DAG.getSetCC(DebugLoc::getUnknownLoc(), - TLI.getSetCCResultType(N0.getValueType()), + SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), N0, N1, CC); if (N2.getValueType().bitsLT(SCC.getValueType())) - Temp = DAG.getZeroExtendInReg(SCC, DebugLoc::getUnknownLoc(), - N2.getValueType()); + Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); else - Temp = DAG.getNode(ISD::ZERO_EXTEND, DebugLoc::getUnknownLoc(), + Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), N2.getValueType(), SCC); } else { - SCC = DAG.getSetCC(DebugLoc::getUnknownLoc(), MVT::i1, N0, N1, CC); - Temp = DAG.getNode(ISD::ZERO_EXTEND, DebugLoc::getUnknownLoc(), + SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); + Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), N2.getValueType(), SCC); } @@ -5809,8 +5807,7 @@ if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && (!LegalOperations || TLI.isOperationLegal(ISD::CTLZ, XType))) { - SDValue Ctlz = DAG.getNode(ISD::CTLZ, DebugLoc::getUnknownLoc(), - XType, N0); + SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); return DAG.getNode(ISD::SRL, DL, XType, Ctlz, DAG.getConstant(Log2_32(XType.getSizeInBits()), TLI.getShiftAmountTy())); @@ -5827,7 +5824,7 @@ } // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { - SDValue Sign = DAG.getNode(ISD::SRL, DebugLoc::getUnknownLoc(), XType, N0, + SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, DAG.getConstant(XType.getSizeInBits()-1, TLI.getShiftAmountTy())); return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); @@ -5840,10 +5837,10 @@ N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { MVT XType = N0.getValueType(); - SDValue Shift = DAG.getNode(ISD::SRA, DebugLoc::getUnknownLoc(), XType, N0, + SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, DAG.getConstant(XType.getSizeInBits()-1, TLI.getShiftAmountTy())); - SDValue Add = DAG.getNode(ISD::ADD, DebugLoc::getUnknownLoc(), XType, + SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, N0, Shift); AddToWorkList(Shift.getNode()); AddToWorkList(Add.getNode()); @@ -5856,11 +5853,11 @@ if (ConstantSDNode *SubC = dyn_cast(N3.getOperand(0))) { MVT XType = N0.getValueType(); if (SubC->isNullValue() && XType.isInteger()) { - SDValue Shift = DAG.getNode(ISD::SRA, DebugLoc::getUnknownLoc(), XType, + SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, DAG.getConstant(XType.getSizeInBits()-1, TLI.getShiftAmountTy())); - SDValue Add = DAG.getNode(ISD::ADD, DebugLoc::getUnknownLoc(), + SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, N0, Shift); AddToWorkList(Shift.getNode()); AddToWorkList(Add.getNode()); From eli.friedman at gmail.com Fri Jan 30 21:49:54 2009 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 30 Jan 2009 19:49:54 -0800 Subject: [llvm-commits] [llvm] r63469 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll test/Transforms/ScalarRepl/2006-11-07-InvalidArrayPromote.ll test/Transforms/ScalarRepl/badarray.ll t Message-ID: On Fri, Jan 30, 2009 at 6:28 PM, Chris Lattner wrote: > In the case above, we got a > 256 bit integer, but the codegen guys assure me that it can handle the > simple and/or/shift/zext stuff that we're doing on these operations. Until instcombine starts combining them into 256-bit mul operations? -Eli From nicholas at mxc.ca Sat Jan 31 00:01:34 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Fri, 30 Jan 2009 22:01:34 -0800 Subject: [llvm-commits] configure flag to find include/plugin-api.h Message-ID: <4983E93E.7090302@mxc.ca> Would someone kindly commit this patch to configure.ac and Makefile.config.in, and regenerate configure with the appropriate versions of auto*? Log message: New option --with-binutils-include to point to the binutils source include directory to find the plugin header for gold. Thanks in advance! Nick Lewycky -------------- next part -------------- A non-text attachment was scrubbed... Name: detect-binutils.patch Type: text/x-diff Size: 1532 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090130/5124ea20/attachment.bin From wangmp at apple.com Sat Jan 31 00:07:51 2009 From: wangmp at apple.com (Mon P Wang) Date: Sat, 31 Jan 2009 06:07:51 -0000 Subject: [llvm-commits] [llvm] r63474 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/X86/neg_fp.ll Message-ID: <200901310607.n0V67qTW000761@zion.cs.uiuc.edu> Author: wangmp Date: Sat Jan 31 00:07:45 2009 New Revision: 63474 URL: http://llvm.org/viewvc/llvm-project?rev=63474&view=rev Log: If unsafe FP optimization is not set, don't allow -(A-B) => B-A because when A==B, -0.0 != +0.0. Added: llvm/trunk/test/CodeGen/X86/neg_fp.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63474&r1=63473&r2=63474&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat Jan 31 00:07:45 2009 @@ -2357,7 +2357,8 @@ return Operand.getOperand(0); break; case ISD::FNEG: - if (OpOpcode == ISD::FSUB) // -(X-Y) -> (Y-X) + // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0 + if (UnsafeFPMath && OpOpcode == ISD::FSUB) return getNode(ISD::FSUB, VT, Operand.getNode()->getOperand(1), Operand.getNode()->getOperand(0)); if (OpOpcode == ISD::FNEG) // --X -> X Added: llvm/trunk/test/CodeGen/X86/neg_fp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/neg_fp.ll?rev=63474&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/neg_fp.ll (added) +++ llvm/trunk/test/CodeGen/X86/neg_fp.ll Sat Jan 31 00:07:45 2009 @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse41 -o %t -f +; RUN: grep xorps %t | count 1 + +; Test that when we don't -enable-unsafe-fp-math, we don't do the optimization +; -0 - (A - B) to (B - A) because A==B, -0 != 0 + +define float @negfp(float %a, float %b) { +entry: + %sub = sub float %a, %b ; [#uses=1] + %neg = sub float -0.000000e+00, %sub ; [#uses=1] + ret float %neg +} \ No newline at end of file From clattner at apple.com Sat Jan 31 00:18:21 2009 From: clattner at apple.com (Chris Lattner) Date: Fri, 30 Jan 2009 22:18:21 -0800 Subject: [llvm-commits] [llvm] r63469 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll test/Transforms/ScalarRepl/2006-11-07-InvalidArrayPromote.ll test/Transforms/ScalarRepl/badarray.ll t In-Reply-To: References: Message-ID: On Jan 30, 2009, at 7:49 PM, Eli Friedman wrote: > On Fri, Jan 30, 2009 at 6:28 PM, Chris Lattner > wrote: >> In the case above, we got a >> 256 bit integer, but the codegen guys assure me that it can handle >> the >> simple and/or/shift/zext stuff that we're doing on these operations. > > Until instcombine starts combining them into 256-bit mul operations? That'll be fun! :) In almost all real cases, instcombine will end up zapping the extend/ and/or/truncate pairs completely, eliminating the craziness. -Chris From clattner at apple.com Sat Jan 31 00:20:46 2009 From: clattner at apple.com (Chris Lattner) Date: Fri, 30 Jan 2009 22:20:46 -0800 Subject: [llvm-commits] [llvm] r63468 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuild.h In-Reply-To: <200901310222.n0V2MbS6025448@zion.cs.uiuc.edu> References: <200901310222.n0V2MbS6025448@zion.cs.uiuc.edu> Message-ID: <629B776D-C9A1-49F6-A8A9-C2516D5B4789@apple.com> On Jan 30, 2009, at 6:22 PM, Dale Johannesen wrote: > Author: johannes > Date: Fri Jan 30 20:22:37 2009 > New Revision: 63468 > > URL: http://llvm.org/viewvc/llvm-project?rev=63468&view=rev > Log: > Move CurDebugLoc into SelectionDAGLowering. Thanks Dale!! -Chris From wangmp at apple.com Sat Jan 31 00:50:54 2009 From: wangmp at apple.com (Mon P Wang) Date: Sat, 31 Jan 2009 06:50:54 -0000 Subject: [llvm-commits] [llvm] r63475 - /llvm/trunk/test/CodeGen/CellSPU/sp_farith.ll Message-ID: <200901310650.n0V6osIM002634@zion.cs.uiuc.edu> Author: wangmp Date: Sat Jan 31 00:50:54 2009 New Revision: 63475 URL: http://llvm.org/viewvc/llvm-project?rev=63475&view=rev Log: Used "-enable-unsafe-fp-math" to allow this transformation - (a * b -c) = c - a *b. Modified: llvm/trunk/test/CodeGen/CellSPU/sp_farith.ll Modified: llvm/trunk/test/CodeGen/CellSPU/sp_farith.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/sp_farith.ll?rev=63475&r1=63474&r2=63475&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/sp_farith.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/sp_farith.ll Sat Jan 31 00:50:54 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s +; RUN: llvm-as -o - %s | llc -march=cellspu -enable-unsafe-fp-math > %t1.s ; RUN: grep fa %t1.s | count 2 ; RUN: grep fs %t1.s | count 2 ; RUN: grep fm %t1.s | count 6 From wangmp at apple.com Sat Jan 31 00:59:32 2009 From: wangmp at apple.com (Mon Ping Wang) Date: Fri, 30 Jan 2009 22:59:32 -0800 Subject: [llvm-commits] [llvm] r63474/r63475 In-Reply-To: <200901310607.n0V67qTW000761@zion.cs.uiuc.edu> References: <200901310607.n0V67qTW000761@zion.cs.uiuc.edu> Message-ID: <0B8108B6-0CDF-46F3-AE1B-D38FB0EA5338@apple.com> Hi, My change in r63474 broke llvm/test/CodeGen/CellSPU/sp_arith.ll because it is testing for the floating point transformation - (a * b -c) = c - a *b. If a*b == c, this transformation is illegal since -0.0 is not the same as +0.0. To avoid this test failing, I have changed the test in r63475 to use "- enable-unsafe-fp-math" that would allow that transformation. Please let me know if someone has a problem with changing the test in this way. Sorry that I didn't notice this before checking in as I didn't build the cell backend before running the basic test. I have corrected that oversight. -- Mon Ping On Jan 30, 2009, at 10:07 PM, Mon P Wang wrote: > Author: wangmp > Date: Sat Jan 31 00:07:45 2009 > New Revision: 63474 > > URL: http://llvm.org/viewvc/llvm-project?rev=63474&view=rev > Log: > If unsafe FP optimization is not set, don't allow -(A-B) => B-A > because > when A==B, -0.0 != +0.0. > > Added: > llvm/trunk/test/CodeGen/X86/neg_fp.ll > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63474&r1=63473&r2=63474&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat Jan 31 > 00:07:45 2009 > @@ -2357,7 +2357,8 @@ > return Operand.getOperand(0); > break; > case ISD::FNEG: > - if (OpOpcode == ISD::FSUB) // -(X-Y) -> (Y-X) > + // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0 > + if (UnsafeFPMath && OpOpcode == ISD::FSUB) > return getNode(ISD::FSUB, VT, Operand.getNode()->getOperand(1), > Operand.getNode()->getOperand(0)); > if (OpOpcode == ISD::FNEG) // --X -> X > > Added: llvm/trunk/test/CodeGen/X86/neg_fp.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/neg_fp.ll?rev=63474&view=auto > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/test/CodeGen/X86/neg_fp.ll (added) > +++ llvm/trunk/test/CodeGen/X86/neg_fp.ll Sat Jan 31 00:07:45 2009 > @@ -0,0 +1,12 @@ > +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse41 -o %t -f > +; RUN: grep xorps %t | count 1 > + > +; Test that when we don't -enable-unsafe-fp-math, we don't do the > optimization > +; -0 - (A - B) to (B - A) because A==B, -0 != 0 > + > +define float @negfp(float %a, float %b) { > +entry: > + %sub = sub float %a, %b ; [#uses=1] > + %neg = sub float -0.000000e+00, %sub ; [#uses=1] > + ret float %neg > +} > \ No newline at end of file > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From sabre at nondot.org Sat Jan 31 01:04:22 2009 From: sabre at nondot.org (Chris Lattner) Date: Sat, 31 Jan 2009 07:04:22 -0000 Subject: [llvm-commits] [llvm] r63476 - in /llvm/trunk: lib/Transforms/Scalar/InstructionCombining.cpp test/Transforms/InstCombine/dce-iterate.ll Message-ID: <200901310704.n0V74MXw003101@zion.cs.uiuc.edu> Author: lattner Date: Sat Jan 31 01:04:22 2009 New Revision: 63476 URL: http://llvm.org/viewvc/llvm-project?rev=63476&view=rev Log: make sure to set Changed=true when instcombine hacks on the code, not doing so prevents it from properly iterating and prevents it from deleting the entire body of dce-iterate.ll Added: llvm/trunk/test/Transforms/InstCombine/dce-iterate.ll Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=63476&r1=63475&r2=63476&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Sat Jan 31 01:04:22 2009 @@ -12356,6 +12356,7 @@ if (!I->use_empty()) I->replaceAllUsesWith(UndefValue::get(I->getType())); I->eraseFromParent(); + Changed = true; } } } @@ -12375,6 +12376,7 @@ I->eraseFromParent(); RemoveFromWorkList(I); + Changed = true; continue; } @@ -12389,17 +12391,19 @@ ++NumConstProp; I->eraseFromParent(); RemoveFromWorkList(I); + Changed = true; continue; } if (TD && I->getType()->getTypeID() == Type::VoidTyID) { // See if we can constant fold its operands. - for (User::op_iterator i = I->op_begin(), e = I->op_end(); i != e; ++i) { - if (ConstantExpr *CE = dyn_cast(i)) { + for (User::op_iterator i = I->op_begin(), e = I->op_end(); i != e; ++i) + if (ConstantExpr *CE = dyn_cast(i)) if (Constant *NewC = ConstantFoldConstantExpression(CE, TD)) - i->set(NewC); - } - } + if (NewC != CE) { + i->set(NewC); + Changed = true; + } } // See if we can trivially sink this instruction to a successor basic block. Added: llvm/trunk/test/Transforms/InstCombine/dce-iterate.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/dce-iterate.ll?rev=63476&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/dce-iterate.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/dce-iterate.ll Sat Jan 31 01:04:22 2009 @@ -0,0 +1,24 @@ +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep {ret double .sy} + +define internal double @ScaleObjectAdd(double %sx, double %sy, double %sz) nounwind { +entry: + %sx34 = bitcast double %sx to i64 ; [#uses=1] + %sx3435 = zext i64 %sx34 to i960 ; [#uses=1] + %sy22 = bitcast double %sy to i64 ; [#uses=1] + %sy2223 = zext i64 %sy22 to i960 ; [#uses=1] + %sy222324 = shl i960 %sy2223, 320 ; [#uses=1] + %sy222324.ins = or i960 %sx3435, %sy222324 ; [#uses=1] + %sz10 = bitcast double %sz to i64 ; [#uses=1] + %sz1011 = zext i64 %sz10 to i960 ; [#uses=1] + %sz101112 = shl i960 %sz1011, 640 ; [#uses=1] + %sz101112.ins = or i960 %sy222324.ins, %sz101112 + + %a = trunc i960 %sz101112.ins to i64 ; [#uses=1] + %b = bitcast i64 %a to double ; [#uses=1] + %c = lshr i960 %sz101112.ins, 320 ; [#uses=1] + %d = trunc i960 %c to i64 ; [#uses=1] + %e = bitcast i64 %d to double ; [#uses=1] + %f = add double %b, %e + + ret double %e +} From sabre at nondot.org Sat Jan 31 01:26:06 2009 From: sabre at nondot.org (Chris Lattner) Date: Sat, 31 Jan 2009 07:26:06 -0000 Subject: [llvm-commits] [llvm] r63477 - /llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200901310726.n0V7Q6M2003770@zion.cs.uiuc.edu> Author: lattner Date: Sat Jan 31 01:26:06 2009 New Revision: 63477 URL: http://llvm.org/viewvc/llvm-project?rev=63477&view=rev Log: minor cleanups Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=63477&r1=63476&r2=63477&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Sat Jan 31 01:26:06 2009 @@ -766,7 +766,7 @@ /// in DemandedMask. Note also that the bitwidth of V, DemandedMask, KnownZero /// and KnownOne must all be the same. bool InstCombiner::SimplifyDemandedBits(Value *V, APInt DemandedMask, - APInt& KnownZero, APInt& KnownOne, + APInt &KnownZero, APInt &KnownOne, unsigned Depth) { assert(V != 0 && "Null pointer of Value???"); assert(Depth <= 6 && "Limit Search Depth"); @@ -784,7 +784,7 @@ return false; } - KnownZero.clear(); + KnownZero.clear(); KnownOne.clear(); if (!V->hasOneUse()) { // Other users may use these bits. if (Depth != 0) { // Not at the root. @@ -796,7 +796,7 @@ // just set the DemandedMask to all bits. DemandedMask = APInt::getAllOnesValue(BitWidth); } else if (DemandedMask == 0) { // Not demanding any bits from V. - if (V != UndefValue::get(VTy)) + if (!isa(V)) return UpdateValueUsesWith(V, UndefValue::get(VTy)); return false; } else if (Depth == 6) { // Limit search depth. From sabre at nondot.org Sat Jan 31 01:34:19 2009 From: sabre at nondot.org (Chris Lattner) Date: Sat, 31 Jan 2009 07:34:19 -0000 Subject: [llvm-commits] [llvm] r63478 - /llvm/trunk/include/llvm/User.h Message-ID: <200901310734.n0V7YJOL004043@zion.cs.uiuc.edu> Author: lattner Date: Sat Jan 31 01:34:19 2009 New Revision: 63478 URL: http://llvm.org/viewvc/llvm-project?rev=63478&view=rev Log: add accessors Modified: llvm/trunk/include/llvm/User.h Modified: llvm/trunk/include/llvm/User.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/User.h?rev=63478&r1=63477&r2=63478&view=diff ============================================================================== --- llvm/trunk/include/llvm/User.h (original) +++ llvm/trunk/include/llvm/User.h Sat Jan 31 01:34:19 2009 @@ -100,6 +100,15 @@ "Cannot mutate a constant with setOperand!"); OperandList[i] = Val; } + const Use &getOperandUse(unsigned i) const { + assert(i < NumOperands && "getOperand() out of range!"); + return OperandList[i]; + } + Use &getOperandUse(unsigned i) { + assert(i < NumOperands && "getOperand() out of range!"); + return OperandList[i]; + } + unsigned getNumOperands() const { return NumOperands; } // --------------------------------------------------------------------------- From sabre at nondot.org Sat Jan 31 02:15:22 2009 From: sabre at nondot.org (Chris Lattner) Date: Sat, 31 Jan 2009 08:15:22 -0000 Subject: [llvm-commits] [llvm] r63479 - /llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200901310815.n0V8FO6k005360@zion.cs.uiuc.edu> Author: lattner Date: Sat Jan 31 02:15:18 2009 New Revision: 63479 URL: http://llvm.org/viewvc/llvm-project?rev=63479&view=rev Log: make some fairly meaty internal changes to how SimplifyDemandedBits works. Now, if it detects that "V" is the same as some other value, SimplifyDemandedBits returns the new value instead of RAUW'ing it immediately. This has two benefits: 1) simpler code in the recursive SimplifyDemandedBits routine. 2) it allows future fun stuff in instcombine where an operation has multiple uses and can be simplified in one context, but not all. #2 isn't implemented yet, this patch should have no functionality change. Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=63479&r1=63478&r2=63479&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Sat Jan 31 02:15:18 2009 @@ -303,23 +303,6 @@ } } - // UpdateValueUsesWith - This method is to be used when an value is - // found to be replacable with another preexisting expression or was - // updated. Here we add all uses of I to the worklist, replace all uses of - // I with the new value (unless the instruction was just updated), then - // return true, so that the inst combiner will know that I was modified. - // - bool UpdateValueUsesWith(Value *Old, Value *New) { - AddUsersToWorkList(*Old); // Add all modified instrs to worklist - if (Old != New) - Old->replaceAllUsesWith(New); - if (Instruction *I = dyn_cast(Old)) - AddToWorkList(I); - if (Instruction *I = dyn_cast(New)) - AddToWorkList(I); - return true; - } - // EraseInstFromFunction - When dealing with an instruction that has side // effects or produces a void value, we can't rely on DCE to delete the // instruction. Instead, visit methods should return the value returned by @@ -355,12 +338,20 @@ /// most-complex to least-complex order. bool SimplifyCompare(CmpInst &I); - /// SimplifyDemandedBits - Attempts to replace V with a simpler value based - /// on the demanded bits. - bool SimplifyDemandedBits(Value *V, APInt DemandedMask, + /// SimplifyDemandedUseBits - Attempts to replace V with a simpler value + /// based on the demanded bits. + Value *SimplifyDemandedUseBits(Value *V, APInt DemandedMask, + APInt& KnownZero, APInt& KnownOne, + unsigned Depth); + bool SimplifyDemandedBits(Use &U, APInt DemandedMask, APInt& KnownZero, APInt& KnownOne, - unsigned Depth = 0); - + unsigned Depth=0); + + /// SimplifyDemandedInstructionBits - Inst is an integer instruction that + /// SimplifyDemandedBits knows about. See if the instruction has any + /// properties that allow us to simplify its operands. + bool SimplifyDemandedInstructionBits(Instruction &Inst); + Value *SimplifyDemandedVectorElts(Value *V, uint64_t DemandedElts, uint64_t &UndefElts, unsigned Depth = 0); @@ -750,14 +741,44 @@ Max = KnownOne|UnknownBits; } -/// SimplifyDemandedBits - This function attempts to replace V with a simpler -/// value based on the demanded bits. When this function is called, it is known +/// SimplifyDemandedInstructionBits - Inst is an integer instruction that +/// SimplifyDemandedBits knows about. See if the instruction has any +/// properties that allow us to simplify its operands. +bool InstCombiner::SimplifyDemandedInstructionBits(Instruction &Inst) { + unsigned BitWidth = cast(Inst.getType())->getBitWidth(); + APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0); + APInt DemandedMask(APInt::getAllOnesValue(BitWidth)); + + Value *V = SimplifyDemandedUseBits(&Inst, DemandedMask, + KnownZero, KnownOne, 0); + if (V == 0) return false; + if (V == &Inst) return true; + ReplaceInstUsesWith(Inst, V); + return true; +} + +/// SimplifyDemandedBits - This form of SimplifyDemandedBits simplifies the +/// specified instruction operand if possible, updating it in place. It returns +/// true if it made any change and false otherwise. +bool InstCombiner::SimplifyDemandedBits(Use &U, APInt DemandedMask, + APInt &KnownZero, APInt &KnownOne, + unsigned Depth) { + Value *NewVal = SimplifyDemandedUseBits(U.get(), DemandedMask, + KnownZero, KnownOne, Depth); + if (NewVal == 0) return false; + U.set(NewVal); + return true; +} + + +/// SimplifyDemandedUseBits - This function attempts to replace V with a simpler +/// value based on the demanded bits. When this function is called, it is known /// that only the bits set in DemandedMask of the result of V are ever used /// downstream. Consequently, depending on the mask and V, it may be possible /// to replace V with a constant or one of its operands. In such cases, this /// function does the replacement and returns true. In all other cases, it /// returns false after analyzing the expression and setting KnownOne and known -/// to be one in the expression. KnownZero contains all the bits that are known +/// to be one in the expression. KnownZero contains all the bits that are known /// to be zero in the expression. These are provided to potentially allow the /// caller (which might recursively be SimplifyDemandedBits itself) to simplify /// the expression. KnownOne and KnownZero always follow the invariant that @@ -765,9 +786,15 @@ /// the bits in KnownOne and KnownZero may only be accurate for those bits set /// in DemandedMask. Note also that the bitwidth of V, DemandedMask, KnownZero /// and KnownOne must all be the same. -bool InstCombiner::SimplifyDemandedBits(Value *V, APInt DemandedMask, - APInt &KnownZero, APInt &KnownOne, - unsigned Depth) { +/// +/// This returns null if it did not change anything and it permits no +/// simplification. This returns V itself if it did some simplification of V's +/// operands based on the information about what bits are demanded. This returns +/// some other non-null value if it found out that V is equal to another value +/// in the context where the specified bits are demanded, but not for all users. +Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask, + APInt &KnownZero, APInt &KnownOne, + unsigned Depth) { assert(V != 0 && "Null pointer of Value???"); assert(Depth <= 6 && "Limit Search Depth"); uint32_t BitWidth = DemandedMask.getBitWidth(); @@ -781,69 +808,63 @@ // We know all of the bits for a constant! KnownOne = CI->getValue() & DemandedMask; KnownZero = ~KnownOne & DemandedMask; - return false; + return 0; } KnownZero.clear(); KnownOne.clear(); - if (!V->hasOneUse()) { // Other users may use these bits. + if (DemandedMask == 0) { // Not demanding any bits from V. + if (isa(V)) + return 0; + return UndefValue::get(VTy); + } else if (!V->hasOneUse()) { // Other users may use these bits. if (Depth != 0) { // Not at the root. // Just compute the KnownZero/KnownOne bits to simplify things downstream. ComputeMaskedBits(V, DemandedMask, KnownZero, KnownOne, Depth); - return false; + return 0; } // If this is the root being simplified, allow it to have multiple uses, // just set the DemandedMask to all bits. DemandedMask = APInt::getAllOnesValue(BitWidth); - } else if (DemandedMask == 0) { // Not demanding any bits from V. - if (!isa(V)) - return UpdateValueUsesWith(V, UndefValue::get(VTy)); - return false; } else if (Depth == 6) { // Limit search depth. - return false; + return 0; } Instruction *I = dyn_cast(V); - if (!I) return false; // Only analyze instructions. + if (!I) return 0; // Only analyze instructions. APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0); APInt &RHSKnownZero = KnownZero, &RHSKnownOne = KnownOne; switch (I->getOpcode()) { default: - ComputeMaskedBits(V, DemandedMask, RHSKnownZero, RHSKnownOne, Depth); + ComputeMaskedBits(I, DemandedMask, RHSKnownZero, RHSKnownOne, Depth); break; case Instruction::And: // If either the LHS or the RHS are Zero, the result is zero. - if (SimplifyDemandedBits(I->getOperand(1), DemandedMask, - RHSKnownZero, RHSKnownOne, Depth+1)) - return true; - assert((RHSKnownZero & RHSKnownOne) == 0 && - "Bits known to be one AND zero?"); - - // If something is known zero on the RHS, the bits aren't demanded on the - // LHS. - if (SimplifyDemandedBits(I->getOperand(0), DemandedMask & ~RHSKnownZero, + if (SimplifyDemandedBits(I->getOperandUse(1), DemandedMask, + RHSKnownZero, RHSKnownOne, Depth+1) || + SimplifyDemandedBits(I->getOperandUse(0), DemandedMask & ~RHSKnownZero, LHSKnownZero, LHSKnownOne, Depth+1)) - return true; - assert((LHSKnownZero & LHSKnownOne) == 0 && - "Bits known to be one AND zero?"); + return I; + assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); + assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?"); // If all of the demanded bits are known 1 on one side, return the other. // These bits cannot contribute to the result of the 'and'. if ((DemandedMask & ~LHSKnownZero & RHSKnownOne) == (DemandedMask & ~LHSKnownZero)) - return UpdateValueUsesWith(I, I->getOperand(0)); + return I->getOperand(0); if ((DemandedMask & ~RHSKnownZero & LHSKnownOne) == (DemandedMask & ~RHSKnownZero)) - return UpdateValueUsesWith(I, I->getOperand(1)); + return I->getOperand(1); // If all of the demanded bits in the inputs are known zeros, return zero. if ((DemandedMask & (RHSKnownZero|LHSKnownZero)) == DemandedMask) - return UpdateValueUsesWith(I, Constant::getNullValue(VTy)); + return Constant::getNullValue(VTy); // If the RHS is a constant, see if we can simplify it. if (ShrinkDemandedConstant(I, 1, DemandedMask & ~LHSKnownZero)) - return UpdateValueUsesWith(I, I); + return I; // Output known-1 bits are only known if set in both the LHS & RHS. RHSKnownOne &= LHSKnownOne; @@ -852,40 +873,35 @@ break; case Instruction::Or: // If either the LHS or the RHS are One, the result is One. - if (SimplifyDemandedBits(I->getOperand(1), DemandedMask, - RHSKnownZero, RHSKnownOne, Depth+1)) - return true; - assert((RHSKnownZero & RHSKnownOne) == 0 && - "Bits known to be one AND zero?"); - // If something is known one on the RHS, the bits aren't demanded on the - // LHS. - if (SimplifyDemandedBits(I->getOperand(0), DemandedMask & ~RHSKnownOne, + if (SimplifyDemandedBits(I->getOperandUse(1), DemandedMask, + RHSKnownZero, RHSKnownOne, Depth+1) || + SimplifyDemandedBits(I->getOperandUse(0), DemandedMask & ~RHSKnownOne, LHSKnownZero, LHSKnownOne, Depth+1)) - return true; - assert((LHSKnownZero & LHSKnownOne) == 0 && - "Bits known to be one AND zero?"); + return I; + assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); + assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?"); // If all of the demanded bits are known zero on one side, return the other. // These bits cannot contribute to the result of the 'or'. if ((DemandedMask & ~LHSKnownOne & RHSKnownZero) == (DemandedMask & ~LHSKnownOne)) - return UpdateValueUsesWith(I, I->getOperand(0)); + return I->getOperand(0); if ((DemandedMask & ~RHSKnownOne & LHSKnownZero) == (DemandedMask & ~RHSKnownOne)) - return UpdateValueUsesWith(I, I->getOperand(1)); + return I->getOperand(1); // If all of the potentially set bits on one side are known to be set on // the other side, just use the 'other' side. if ((DemandedMask & (~RHSKnownZero) & LHSKnownOne) == (DemandedMask & (~RHSKnownZero))) - return UpdateValueUsesWith(I, I->getOperand(0)); + return I->getOperand(0); if ((DemandedMask & (~LHSKnownZero) & RHSKnownOne) == (DemandedMask & (~LHSKnownZero))) - return UpdateValueUsesWith(I, I->getOperand(1)); + return I->getOperand(1); // If the RHS is a constant, see if we can simplify it. if (ShrinkDemandedConstant(I, 1, DemandedMask)) - return UpdateValueUsesWith(I, I); + return I; // Output known-0 bits are only known if clear in both the LHS & RHS. RHSKnownZero &= LHSKnownZero; @@ -893,23 +909,20 @@ RHSKnownOne |= LHSKnownOne; break; case Instruction::Xor: { - if (SimplifyDemandedBits(I->getOperand(1), DemandedMask, - RHSKnownZero, RHSKnownOne, Depth+1)) - return true; - assert((RHSKnownZero & RHSKnownOne) == 0 && - "Bits known to be one AND zero?"); - if (SimplifyDemandedBits(I->getOperand(0), DemandedMask, + if (SimplifyDemandedBits(I->getOperandUse(1), DemandedMask, + RHSKnownZero, RHSKnownOne, Depth+1) || + SimplifyDemandedBits(I->getOperandUse(0), DemandedMask, LHSKnownZero, LHSKnownOne, Depth+1)) - return true; - assert((LHSKnownZero & LHSKnownOne) == 0 && - "Bits known to be one AND zero?"); + return I; + assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); + assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?"); // If all of the demanded bits are known zero on one side, return the other. // These bits cannot contribute to the result of the 'xor'. if ((DemandedMask & RHSKnownZero) == DemandedMask) - return UpdateValueUsesWith(I, I->getOperand(0)); + return I->getOperand(0); if ((DemandedMask & LHSKnownZero) == DemandedMask) - return UpdateValueUsesWith(I, I->getOperand(1)); + return I->getOperand(1); // Output known-0 bits are known if clear or set in both the LHS & RHS. APInt KnownZeroOut = (RHSKnownZero & LHSKnownZero) | @@ -925,8 +938,7 @@ Instruction *Or = BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1), I->getName()); - InsertNewInstBefore(Or, *I); - return UpdateValueUsesWith(I, Or); + return InsertNewInstBefore(Or, *I); } // If all of the demanded bits on one side are known, and all of the set @@ -939,92 +951,80 @@ Constant *AndC = ConstantInt::get(~RHSKnownOne & DemandedMask); Instruction *And = BinaryOperator::CreateAnd(I->getOperand(0), AndC, "tmp"); - InsertNewInstBefore(And, *I); - return UpdateValueUsesWith(I, And); + return InsertNewInstBefore(And, *I); } } // If the RHS is a constant, see if we can simplify it. // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1. if (ShrinkDemandedConstant(I, 1, DemandedMask)) - return UpdateValueUsesWith(I, I); + return I; RHSKnownZero = KnownZeroOut; RHSKnownOne = KnownOneOut; break; } case Instruction::Select: - if (SimplifyDemandedBits(I->getOperand(2), DemandedMask, - RHSKnownZero, RHSKnownOne, Depth+1)) - return true; - if (SimplifyDemandedBits(I->getOperand(1), DemandedMask, + if (SimplifyDemandedBits(I->getOperandUse(2), DemandedMask, + RHSKnownZero, RHSKnownOne, Depth+1) || + SimplifyDemandedBits(I->getOperandUse(1), DemandedMask, LHSKnownZero, LHSKnownOne, Depth+1)) - return true; - assert((RHSKnownZero & RHSKnownOne) == 0 && - "Bits known to be one AND zero?"); - assert((LHSKnownZero & LHSKnownOne) == 0 && - "Bits known to be one AND zero?"); + return I; + assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); + assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?"); // If the operands are constants, see if we can simplify them. - if (ShrinkDemandedConstant(I, 1, DemandedMask)) - return UpdateValueUsesWith(I, I); - if (ShrinkDemandedConstant(I, 2, DemandedMask)) - return UpdateValueUsesWith(I, I); + if (ShrinkDemandedConstant(I, 1, DemandedMask) || + ShrinkDemandedConstant(I, 2, DemandedMask)) + return I; // Only known if known in both the LHS and RHS. RHSKnownOne &= LHSKnownOne; RHSKnownZero &= LHSKnownZero; break; case Instruction::Trunc: { - uint32_t truncBf = - cast(I->getOperand(0)->getType())->getBitWidth(); + unsigned truncBf = I->getOperand(0)->getType()->getPrimitiveSizeInBits(); DemandedMask.zext(truncBf); RHSKnownZero.zext(truncBf); RHSKnownOne.zext(truncBf); - if (SimplifyDemandedBits(I->getOperand(0), DemandedMask, + if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMask, RHSKnownZero, RHSKnownOne, Depth+1)) - return true; + return I; DemandedMask.trunc(BitWidth); RHSKnownZero.trunc(BitWidth); RHSKnownOne.trunc(BitWidth); - assert((RHSKnownZero & RHSKnownOne) == 0 && - "Bits known to be one AND zero?"); + assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); break; } case Instruction::BitCast: if (!I->getOperand(0)->getType()->isInteger()) - return false; - - if (SimplifyDemandedBits(I->getOperand(0), DemandedMask, + return false; // vector->int or fp->int? + if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMask, RHSKnownZero, RHSKnownOne, Depth+1)) - return true; - assert((RHSKnownZero & RHSKnownOne) == 0 && - "Bits known to be one AND zero?"); + return I; + assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); break; case Instruction::ZExt: { // Compute the bits in the result that are not present in the input. - const IntegerType *SrcTy = cast(I->getOperand(0)->getType()); - uint32_t SrcBitWidth = SrcTy->getBitWidth(); + unsigned SrcBitWidth =I->getOperand(0)->getType()->getPrimitiveSizeInBits(); DemandedMask.trunc(SrcBitWidth); RHSKnownZero.trunc(SrcBitWidth); RHSKnownOne.trunc(SrcBitWidth); - if (SimplifyDemandedBits(I->getOperand(0), DemandedMask, + if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMask, RHSKnownZero, RHSKnownOne, Depth+1)) - return true; + return I; DemandedMask.zext(BitWidth); RHSKnownZero.zext(BitWidth); RHSKnownOne.zext(BitWidth); - assert((RHSKnownZero & RHSKnownOne) == 0 && - "Bits known to be one AND zero?"); + assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); // The top bits are known to be zero. RHSKnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - SrcBitWidth); break; } case Instruction::SExt: { // Compute the bits in the result that are not present in the input. - const IntegerType *SrcTy = cast(I->getOperand(0)->getType()); - uint32_t SrcBitWidth = SrcTy->getBitWidth(); + unsigned SrcBitWidth =I->getOperand(0)->getType()->getPrimitiveSizeInBits(); APInt InputDemandedBits = DemandedMask & APInt::getLowBitsSet(BitWidth, SrcBitWidth); @@ -1038,25 +1038,23 @@ InputDemandedBits.trunc(SrcBitWidth); RHSKnownZero.trunc(SrcBitWidth); RHSKnownOne.trunc(SrcBitWidth); - if (SimplifyDemandedBits(I->getOperand(0), InputDemandedBits, + if (SimplifyDemandedBits(I->getOperandUse(0), InputDemandedBits, RHSKnownZero, RHSKnownOne, Depth+1)) - return true; + return I; InputDemandedBits.zext(BitWidth); RHSKnownZero.zext(BitWidth); RHSKnownOne.zext(BitWidth); - assert((RHSKnownZero & RHSKnownOne) == 0 && - "Bits known to be one AND zero?"); + assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); // If the sign bit of the input is known set or clear, then we know the // top bits of the result. // If the input sign bit is known zero, or if the NewBits are not demanded // convert this into a zero extension. - if (RHSKnownZero[SrcBitWidth-1] || (NewBits & ~DemandedMask) == NewBits) - { + if (RHSKnownZero[SrcBitWidth-1] || (NewBits & ~DemandedMask) == NewBits) { // Convert to ZExt cast - CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy, I->getName(), I); - return UpdateValueUsesWith(I, NewCast); + CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy, I->getName()); + return InsertNewInstBefore(NewCast, *I); } else if (RHSKnownOne[SrcBitWidth-1]) { // Input sign bit known set RHSKnownOne |= NewBits; } @@ -1066,7 +1064,7 @@ // Figure out what the input bits are. If the top bits of the and result // are not demanded, then the add doesn't demand them from its input // either. - uint32_t NLZ = DemandedMask.countLeadingZeros(); + unsigned NLZ = DemandedMask.countLeadingZeros(); // If there is a constant on the RHS, there are a variety of xformations // we can do. @@ -1081,14 +1079,14 @@ APInt InDemandedBits(APInt::getLowBitsSet(BitWidth, BitWidth - NLZ)); // Find information about known zero/one bits in the input. - if (SimplifyDemandedBits(I->getOperand(0), InDemandedBits, + if (SimplifyDemandedBits(I->getOperandUse(0), InDemandedBits, LHSKnownZero, LHSKnownOne, Depth+1)) - return true; + return I; // If the RHS of the add has bits set that can't affect the input, reduce // the constant. if (ShrinkDemandedConstant(I, 1, InDemandedBits)) - return UpdateValueUsesWith(I, I); + return I; // Avoid excess work. if (LHSKnownZero == 0 && LHSKnownOne == 0) @@ -1099,8 +1097,7 @@ Instruction *Or = BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1), I->getName()); - InsertNewInstBefore(Or, *I); - return UpdateValueUsesWith(I, Or); + return InsertNewInstBefore(Or, *I); } // We can say something about the output known-zero and known-one bits, @@ -1112,7 +1109,7 @@ // To compute this, we first compute the potential carry bits. These are // the bits which may be modified. I'm not aware of a better way to do // this scan. - const APInt& RHSVal = RHS->getValue(); + const APInt &RHSVal = RHS->getValue(); APInt CarryBits((~LHSKnownZero + RHSVal) ^ (~LHSKnownZero ^ RHSVal)); // Now that we know which bits have carries, compute the known-1/0 sets. @@ -1132,12 +1129,11 @@ // Right fill the mask of bits for this ADD to demand the most // significant bit and all those below it. APInt DemandedFromOps(APInt::getLowBitsSet(BitWidth, BitWidth-NLZ)); - if (SimplifyDemandedBits(I->getOperand(0), DemandedFromOps, + if (SimplifyDemandedBits(I->getOperandUse(0), DemandedFromOps, + LHSKnownZero, LHSKnownOne, Depth+1) || + SimplifyDemandedBits(I->getOperandUse(1), DemandedFromOps, LHSKnownZero, LHSKnownOne, Depth+1)) - return true; - if (SimplifyDemandedBits(I->getOperand(1), DemandedFromOps, - LHSKnownZero, LHSKnownOne, Depth+1)) - return true; + return I; } } break; @@ -1150,12 +1146,11 @@ // significant bit and all those below it. uint32_t NLZ = DemandedMask.countLeadingZeros(); APInt DemandedFromOps(APInt::getLowBitsSet(BitWidth, BitWidth-NLZ)); - if (SimplifyDemandedBits(I->getOperand(0), DemandedFromOps, + if (SimplifyDemandedBits(I->getOperandUse(0), DemandedFromOps, + LHSKnownZero, LHSKnownOne, Depth+1) || + SimplifyDemandedBits(I->getOperandUse(1), DemandedFromOps, LHSKnownZero, LHSKnownOne, Depth+1)) - return true; - if (SimplifyDemandedBits(I->getOperand(1), DemandedFromOps, - LHSKnownZero, LHSKnownOne, Depth+1)) - return true; + return I; } // Otherwise just hand the sub off to ComputeMaskedBits to fill in // the known zeros and ones. @@ -1165,11 +1160,10 @@ if (ConstantInt *SA = dyn_cast(I->getOperand(1))) { uint64_t ShiftAmt = SA->getLimitedValue(BitWidth); APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt)); - if (SimplifyDemandedBits(I->getOperand(0), DemandedMaskIn, + if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn, RHSKnownZero, RHSKnownOne, Depth+1)) - return true; - assert((RHSKnownZero & RHSKnownOne) == 0 && - "Bits known to be one AND zero?"); + return I; + assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); RHSKnownZero <<= ShiftAmt; RHSKnownOne <<= ShiftAmt; // low bits known zero. @@ -1184,11 +1178,10 @@ // Unsigned shift right. APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt)); - if (SimplifyDemandedBits(I->getOperand(0), DemandedMaskIn, + if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn, RHSKnownZero, RHSKnownOne, Depth+1)) - return true; - assert((RHSKnownZero & RHSKnownOne) == 0 && - "Bits known to be one AND zero?"); + return I; + assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); RHSKnownZero = APIntOps::lshr(RHSKnownZero, ShiftAmt); RHSKnownOne = APIntOps::lshr(RHSKnownOne, ShiftAmt); if (ShiftAmt) { @@ -1205,16 +1198,15 @@ // the shift amount is >= the size of the datatype, which is undefined. if (DemandedMask == 1) { // Perform the logical shift right. - Value *NewVal = BinaryOperator::CreateLShr( + Instruction *NewVal = BinaryOperator::CreateLShr( I->getOperand(0), I->getOperand(1), I->getName()); - InsertNewInstBefore(cast(NewVal), *I); - return UpdateValueUsesWith(I, NewVal); + return InsertNewInstBefore(NewVal, *I); } // If the sign bit is the only bit demanded by this ashr, then there is no // need to do it, the shift doesn't change the high bit. if (DemandedMask.isSignBit()) - return UpdateValueUsesWith(I, I->getOperand(0)); + return I->getOperand(0); if (ConstantInt *SA = dyn_cast(I->getOperand(1))) { uint32_t ShiftAmt = SA->getLimitedValue(BitWidth); @@ -1225,12 +1217,10 @@ // demanded. if (DemandedMask.countLeadingZeros() <= ShiftAmt) DemandedMaskIn.set(BitWidth-1); - if (SimplifyDemandedBits(I->getOperand(0), - DemandedMaskIn, + if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn, RHSKnownZero, RHSKnownOne, Depth+1)) - return true; - assert((RHSKnownZero & RHSKnownOne) == 0 && - "Bits known to be one AND zero?"); + return I; + assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); // Compute the new bits that are at the top now. APInt HighBits(APInt::getHighBitsSet(BitWidth, ShiftAmt)); RHSKnownZero = APIntOps::lshr(RHSKnownZero, ShiftAmt); @@ -1246,10 +1236,9 @@ if (BitWidth <= ShiftAmt || RHSKnownZero[BitWidth-ShiftAmt-1] || (HighBits & ~DemandedMask) == HighBits) { // Perform the logical shift right. - Value *NewVal = BinaryOperator::CreateLShr( + Instruction *NewVal = BinaryOperator::CreateLShr( I->getOperand(0), SA, I->getName()); - InsertNewInstBefore(cast(NewVal), *I); - return UpdateValueUsesWith(I, NewVal); + return InsertNewInstBefore(NewVal, *I); } else if ((RHSKnownOne & SignBit) != 0) { // New bits are known one. RHSKnownOne |= HighBits; } @@ -1260,35 +1249,33 @@ APInt RA = Rem->getValue().abs(); if (RA.isPowerOf2()) { if (DemandedMask.ule(RA)) // srem won't affect demanded bits - return UpdateValueUsesWith(I, I->getOperand(0)); + return I->getOperand(0); APInt LowBits = RA - 1; APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); - if (SimplifyDemandedBits(I->getOperand(0), Mask2, + if (SimplifyDemandedBits(I->getOperandUse(0), Mask2, LHSKnownZero, LHSKnownOne, Depth+1)) - return true; + return I; if (LHSKnownZero[BitWidth-1] || ((LHSKnownZero & LowBits) == LowBits)) LHSKnownZero |= ~LowBits; KnownZero |= LHSKnownZero & DemandedMask; - assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); + assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?"); } } break; case Instruction::URem: { APInt KnownZero2(BitWidth, 0), KnownOne2(BitWidth, 0); APInt AllOnes = APInt::getAllOnesValue(BitWidth); - if (SimplifyDemandedBits(I->getOperand(0), AllOnes, + if (SimplifyDemandedBits(I->getOperandUse(0), AllOnes, + KnownZero2, KnownOne2, Depth+1) || + SimplifyDemandedBits(I->getOperandUse(1), AllOnes, KnownZero2, KnownOne2, Depth+1)) - return true; + return I; unsigned Leaders = KnownZero2.countLeadingOnes(); - if (SimplifyDemandedBits(I->getOperand(1), AllOnes, - KnownZero2, KnownOne2, Depth+1)) - return true; - Leaders = std::max(Leaders, KnownZero2.countLeadingOnes()); KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & DemandedMask; @@ -1324,8 +1311,7 @@ NewVal = BinaryOperator::CreateShl(I->getOperand(1), ConstantInt::get(I->getType(), ResultBit-InputBit)); NewVal->takeName(I); - InsertNewInstBefore(NewVal, *I); - return UpdateValueUsesWith(I, NewVal); + return InsertNewInstBefore(NewVal, *I); } // TODO: Could compute known zero/one bits based on the input. @@ -1340,7 +1326,7 @@ // If the client is only demanding bits that we know, return the known // constant. if ((DemandedMask & (RHSKnownZero|RHSKnownOne)) == DemandedMask) - return UpdateValueUsesWith(I, ConstantInt::get(RHSKnownOne)); + return ConstantInt::get(RHSKnownOne); return false; } @@ -1993,12 +1979,8 @@ // See if SimplifyDemandedBits can simplify this. This handles stuff like // (X & 254)+1 -> (X&254)|1 - if (!isa(I.getType())) { - APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0); - if (SimplifyDemandedBits(&I, APInt::getAllOnesValue(BitWidth), - KnownZero, KnownOne)) - return &I; - } + if (!isa(I.getType()) && SimplifyDemandedInstructionBits(I)) + return &I; // zext(i1) - 1 -> select i1, 0, -1 if (ZExtInst *ZI = dyn_cast(LHS)) @@ -3002,10 +2984,7 @@ } // See if we can fold away this rem instruction. - uint32_t BitWidth = cast(I.getType())->getBitWidth(); - APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0); - if (SimplifyDemandedBits(&I, APInt::getAllOnesValue(BitWidth), - KnownZero, KnownOne)) + if (SimplifyDemandedInstructionBits(I)) return &I; } } @@ -3786,10 +3765,7 @@ // See if we can simplify any instructions used by the instruction whose sole // purpose is to compute bits we don't care about. if (!isa(I.getType())) { - uint32_t BitWidth = cast(I.getType())->getBitWidth(); - APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0); - if (SimplifyDemandedBits(&I, APInt::getAllOnesValue(BitWidth), - KnownZero, KnownOne)) + if (SimplifyDemandedInstructionBits(I)) return &I; } else { if (ConstantVector *CP = dyn_cast(Op1)) { @@ -4496,10 +4472,7 @@ // See if we can simplify any instructions used by the instruction whose sole // purpose is to compute bits we don't care about. if (!isa(I.getType())) { - uint32_t BitWidth = cast(I.getType())->getBitWidth(); - APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0); - if (SimplifyDemandedBits(&I, APInt::getAllOnesValue(BitWidth), - KnownZero, KnownOne)) + if (SimplifyDemandedInstructionBits(I)) return &I; } else if (isa(Op1)) { return ReplaceInstUsesWith(I, Op0); // X | <0,0> -> X @@ -4837,10 +4810,7 @@ // See if we can simplify any instructions used by the instruction whose sole // purpose is to compute bits we don't care about. if (!isa(I.getType())) { - uint32_t BitWidth = cast(I.getType())->getBitWidth(); - APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0); - if (SimplifyDemandedBits(&I, APInt::getAllOnesValue(BitWidth), - KnownZero, KnownOne)) + if (SimplifyDemandedInstructionBits(I)) return &I; } else if (isa(Op1)) { return ReplaceInstUsesWith(I, Op0); // X ^ <0,0> -> X @@ -5826,7 +5796,7 @@ bool UnusedBit; bool isSignBit = isSignBitCheck(I.getPredicate(), CI, UnusedBit); - if (SimplifyDemandedBits(Op0, + if (SimplifyDemandedBits(I.getOperandUse(0), isSignBit ? APInt::getSignBit(BitWidth) : APInt::getAllOnesValue(BitWidth), KnownZero, KnownOne, 0)) @@ -6995,9 +6965,7 @@ // See if we can simplify any instructions used by the instruction whose sole // purpose is to compute bits we don't care about. uint32_t TypeBits = Op0->getType()->getPrimitiveSizeInBits(); - APInt KnownZero(TypeBits, 0), KnownOne(TypeBits, 0); - if (SimplifyDemandedBits(&I, APInt::getAllOnesValue(TypeBits), - KnownZero, KnownOne)) + if (SimplifyDemandedInstructionBits(I)) return &I; // shl uint X, 32 = 0 and shr ubyte Y, 9 = 0, ... just don't eliminate shr @@ -7828,9 +7796,7 @@ // See if we can simplify any instructions used by the LHS whose sole // purpose is to compute bits we don't care about. - APInt KnownZero(DestBitSize, 0), KnownOne(DestBitSize, 0); - if (SimplifyDemandedBits(&CI, APInt::getAllOnesValue(DestBitSize), - KnownZero, KnownOne)) + if (SimplifyDemandedInstructionBits(CI)) return &CI; // If the source isn't an instruction or has more than one use then we From sabre at nondot.org Sat Jan 31 02:24:16 2009 From: sabre at nondot.org (Chris Lattner) Date: Sat, 31 Jan 2009 08:24:16 -0000 Subject: [llvm-commits] [llvm] r63480 - /llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200901310824.n0V8OHou005718@zion.cs.uiuc.edu> Author: lattner Date: Sat Jan 31 02:24:16 2009 New Revision: 63480 URL: http://llvm.org/viewvc/llvm-project?rev=63480&view=rev Log: simplify/clarify control flow and improve comments, no functionality change. Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=63480&r1=63479&r2=63480&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Sat Jan 31 02:24:16 2009 @@ -817,22 +817,30 @@ if (isa(V)) return 0; return UndefValue::get(VTy); - } else if (!V->hasOneUse()) { // Other users may use these bits. - if (Depth != 0) { // Not at the root. - // Just compute the KnownZero/KnownOne bits to simplify things downstream. - ComputeMaskedBits(V, DemandedMask, KnownZero, KnownOne, Depth); - return 0; - } - // If this is the root being simplified, allow it to have multiple uses, - // just set the DemandedMask to all bits. - DemandedMask = APInt::getAllOnesValue(BitWidth); - } else if (Depth == 6) { // Limit search depth. - return 0; } + if (Depth == 6) // Limit search depth. + return 0; + Instruction *I = dyn_cast(V); if (!I) return 0; // Only analyze instructions. - + + // If there are multiple uses of this value and we aren't at the root, then + // we can't do any simplifications of the operands, because DemandedMask + // only reflects the bits demanded by *one* of the users. + if (Depth != 0 && !I->hasOneUse()) { + // Compute the KnownZero/KnownOne bits to simplify things downstream. + ComputeMaskedBits(I, DemandedMask, KnownZero, KnownOne, Depth); + return 0; + } + + // If this is the root being simplified, allow it to have multiple uses, + // just set the DemandedMask to all bits so that we can try to simplify the + // operands. This allows visitTruncInst (for example) to simplify the + // operand of a trunc without duplicating all the logic below. + if (Depth == 0 && !V->hasOneUse()) + DemandedMask = APInt::getAllOnesValue(BitWidth); + APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0); APInt &RHSKnownZero = KnownZero, &RHSKnownOne = KnownOne; switch (I->getOpcode()) { @@ -6960,7 +6968,7 @@ Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, ConstantInt *Op1, BinaryOperator &I) { - bool isLeftShift = I.getOpcode() == Instruction::Shl; + bool isLeftShift = I.getOpcode() == Instruction::Shl; // See if we can simplify any instructions used by the instruction whose sole // purpose is to compute bits we don't care about. From sabre at nondot.org Sat Jan 31 02:40:04 2009 From: sabre at nondot.org (Chris Lattner) Date: Sat, 31 Jan 2009 08:40:04 -0000 Subject: [llvm-commits] [llvm] r63481 - in /llvm/trunk: lib/Transforms/Scalar/InstructionCombining.cpp test/Transforms/InstCombine/multi-use-or.ll Message-ID: <200901310840.n0V8e4YT007663@zion.cs.uiuc.edu> Author: lattner Date: Sat Jan 31 02:40:03 2009 New Revision: 63481 URL: http://llvm.org/viewvc/llvm-project?rev=63481&view=rev Log: now that all the pieces are in place, teach instcombine's simplifydemandedbits to simplify instructions with *multiple uses* in contexts where it can get away with it. This allows it to simplify the code in multi-use-or.ll into a single 'add double'. This change is particularly interesting because it will cover up for some common codegen bugs with large integers created due to the recent SROA patch. When working on fixing those bugs, this should be disabled. Added: llvm/trunk/test/Transforms/InstCombine/multi-use-or.ll Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=63481&r1=63480&r2=63481&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Sat Jan 31 02:40:03 2009 @@ -825,10 +825,68 @@ Instruction *I = dyn_cast(V); if (!I) return 0; // Only analyze instructions. + APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0); + APInt &RHSKnownZero = KnownZero, &RHSKnownOne = KnownOne; + // If there are multiple uses of this value and we aren't at the root, then // we can't do any simplifications of the operands, because DemandedMask // only reflects the bits demanded by *one* of the users. if (Depth != 0 && !I->hasOneUse()) { + // Despite the fact that we can't simplify this instruction in all User's + // context, we can at least compute the knownzero/knownone bits, and we can + // do simplifications that apply to *just* the one user if we know that + // this instruction has a simpler value in that context. + if (I->getOpcode() == Instruction::And) { + // If either the LHS or the RHS are Zero, the result is zero. + ComputeMaskedBits(I->getOperand(1), DemandedMask, + RHSKnownZero, RHSKnownOne, Depth+1); + ComputeMaskedBits(I->getOperand(0), DemandedMask & ~RHSKnownZero, + LHSKnownZero, LHSKnownOne, Depth+1); + + // If all of the demanded bits are known 1 on one side, return the other. + // These bits cannot contribute to the result of the 'and' in this + // context. + if ((DemandedMask & ~LHSKnownZero & RHSKnownOne) == + (DemandedMask & ~LHSKnownZero)) + return I->getOperand(0); + if ((DemandedMask & ~RHSKnownZero & LHSKnownOne) == + (DemandedMask & ~RHSKnownZero)) + return I->getOperand(1); + + // If all of the demanded bits in the inputs are known zeros, return zero. + if ((DemandedMask & (RHSKnownZero|LHSKnownZero)) == DemandedMask) + return Constant::getNullValue(VTy); + + } else if (I->getOpcode() == Instruction::Or) { + // We can simplify (X|Y) -> X or Y in the user's context if we know that + // only bits from X or Y are demanded. + + // If either the LHS or the RHS are One, the result is One. + ComputeMaskedBits(I->getOperand(1), DemandedMask, + RHSKnownZero, RHSKnownOne, Depth+1); + ComputeMaskedBits(I->getOperand(0), DemandedMask & ~RHSKnownOne, + LHSKnownZero, LHSKnownOne, Depth+1); + + // If all of the demanded bits are known zero on one side, return the + // other. These bits cannot contribute to the result of the 'or' in this + // context. + if ((DemandedMask & ~LHSKnownOne & RHSKnownZero) == + (DemandedMask & ~LHSKnownOne)) + return I->getOperand(0); + if ((DemandedMask & ~RHSKnownOne & LHSKnownZero) == + (DemandedMask & ~RHSKnownOne)) + return I->getOperand(1); + + // If all of the potentially set bits on one side are known to be set on + // the other side, just use the 'other' side. + if ((DemandedMask & (~RHSKnownZero) & LHSKnownOne) == + (DemandedMask & (~RHSKnownZero))) + return I->getOperand(0); + if ((DemandedMask & (~LHSKnownZero) & RHSKnownOne) == + (DemandedMask & (~LHSKnownZero))) + return I->getOperand(1); + } + // Compute the KnownZero/KnownOne bits to simplify things downstream. ComputeMaskedBits(I, DemandedMask, KnownZero, KnownOne, Depth); return 0; @@ -841,8 +899,6 @@ if (Depth == 0 && !V->hasOneUse()) DemandedMask = APInt::getAllOnesValue(BitWidth); - APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0); - APInt &RHSKnownZero = KnownZero, &RHSKnownOne = KnownOne; switch (I->getOpcode()) { default: ComputeMaskedBits(I, DemandedMask, RHSKnownZero, RHSKnownOne, Depth); Added: llvm/trunk/test/Transforms/InstCombine/multi-use-or.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/multi-use-or.ll?rev=63481&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/multi-use-or.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/multi-use-or.ll Sat Jan 31 02:40:03 2009 @@ -0,0 +1,24 @@ +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep {add double .sx, .sy} +; The 'or' has multiple uses, make sure that this doesn't prevent instcombine +; from propagating the extends to the truncs. + +define double @ScaleObjectAdd(double %sx, double %sy, double %sz) nounwind { +entry: + %sx34 = bitcast double %sx to i64 ; [#uses=1] + %sx3435 = zext i64 %sx34 to i192 ; [#uses=1] + %sy22 = bitcast double %sy to i64 ; [#uses=1] + %sy2223 = zext i64 %sy22 to i192 ; [#uses=1] + %sy222324 = shl i192 %sy2223, 128 ; [#uses=1] + %sy222324.ins = or i192 %sx3435, %sy222324 ; [#uses=1] + + + %a = trunc i192 %sy222324.ins to i64 ; [#uses=1] + %b = bitcast i64 %a to double ; [#uses=1] + %c = lshr i192 %sy222324.ins, 128 ; [#uses=1] + %d = trunc i192 %c to i64 ; [#uses=1] + %e = bitcast i64 %d to double ; [#uses=1] + %f = add double %b, %e + +; ret double %e + ret double %f +} From baldrick at free.fr Sat Jan 31 03:07:10 2009 From: baldrick at free.fr (Duncan Sands) Date: Sat, 31 Jan 2009 10:07:10 +0100 Subject: [llvm-commits] [llvm-gcc-4.2] r63427 - in /llvm-gcc-4.2/trunk: README.LLVM gcc/config/i386/t-linux64 gcc/config/rs6000/t-linux64 In-Reply-To: <200901302150.n0ULoQWW016450@zion.cs.uiuc.edu> References: <200901302150.n0ULoQWW016450@zion.cs.uiuc.edu> Message-ID: <200901311007.10611.baldrick@free.fr> Hi Anton, > +# On Debian, Ubuntu and other derivitive distributions, the 32bit libraries derivitive -> derivative Ciao, Duncan. From sanjiv.gupta at microchip.com Sat Jan 31 09:31:58 2009 From: sanjiv.gupta at microchip.com (sanjiv gupta) Date: Sat, 31 Jan 2009 21:01:58 +0530 Subject: [llvm-commits] [llvm] r63377 - in /llvm/trunk: include/llvm/CodeGen/AsmPrinter.h include/llvm/Target/TargetAsmInfo.h lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/Target/PIC16/PIC16AsmPrinter.cpp lib/Target/PIC16/PIC16AsmPrinter.h lib/Target/PIC16/PIC16TargetAsmInfo.cpp lib/Target/PIC16/PIC16TargetAsmInfo.h In-Reply-To: <54D6400B-DB8F-4D8D-AEE9-E68660C9BD24@apple.com> References: <200901300425.n0U4PJlC001274@zion.cs.uiuc.edu> <54D6400B-DB8F-4D8D-AEE9-E68660C9BD24@apple.com> Message-ID: <1233415918.4001.0.camel@idc-lt-i00171.microchip.com> On Fri, 2009-01-30 at 10:11 -0800, Chris Lattner wrote: > On Jan 29, 2009, at 8:25 PM, Sanjiv Gupta wrote: > > URL: http://llvm.org/viewvc/llvm-project?rev=63377&view=rev > > Log: > > Enable emitting of constant values in non-default address space as > > well. The APIs emitting constants now take an additional parameter > > signifying the address space in which to emit. The APIs like > > getData8BitsDirective() etc are made virtual enabling targets to be > > able to define appropirate directivers for various sizes and address > > spaces. > > Hi Sanjiv, > > Thank you for working on this. > > > + // Data directive accessors > > + // > > + virtual const char *getData8bitsDirective(unsigned AddrSpace = > > 0) const { > > + return Data8bitsDirective; > > + } > > Unfortunately, this significantly pessimizes the common case where > AddrSpace = 0 by making these trivial functions virtual. How about > something like this?: > > // virtual, also protected. > virtual const char *getData8bitsDirectiveV(unsigned AddrSpace) > const; > > // nonvirtual, public. > const char *getData16bitsDirective(unsigned AddrSpace = 0) const { > return AddrSpace == 0 ? Data16bitsDirective : > getData8bitsDirectiveV(AddrSpace); > } > > I think this should be a pretty straight-forward change. What do you > think? > Makes sense. Will rework. - Sanjiv > -Chris > From baldrick at free.fr Sat Jan 31 09:50:13 2009 From: baldrick at free.fr (Duncan Sands) Date: Sat, 31 Jan 2009 15:50:13 -0000 Subject: [llvm-commits] [llvm] r63482 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ test/CodeGen/X86/ Message-ID: <200901311550.n0VFoEW5029548@zion.cs.uiuc.edu> Author: baldrick Date: Sat Jan 31 09:50:11 2009 New Revision: 63482 URL: http://llvm.org/viewvc/llvm-project?rev=63482&view=rev Log: Fix PR3401: when using large integers, the type returned by getShiftAmountTy may be too small to hold shift values (it is an i8 on x86-32). Before and during type legalization, use a large but legal type for shift amounts: getPointerTy; afterwards use getShiftAmountTy, fixing up any shift amounts with a big type during operation legalization. Thanks to Dan for writing the original patch (which I shamelessly pillaged). Added: llvm/trunk/test/CodeGen/X86/2009-01-31-BigShift.ll llvm/trunk/test/CodeGen/X86/2009-01-31-BigShift2.ll llvm/trunk/test/CodeGen/X86/2009-01-31-BigShift3.ll Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63482&r1=63481&r2=63482&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Sat Jan 31 09:50:11 2009 @@ -636,6 +636,10 @@ /// through the backend. SDValue getMemOperand(const MachineMemOperand &MO); + /// getShiftAmountOperand - Return the specified value casted to + /// the target's desired shift amount type. + SDValue getShiftAmountOperand(SDValue Op); + /// UpdateNodeOperands - *Mutate* the specified node in-place to have the /// specified operands. If the resultant node already exists in the DAG, /// this does not modify the specified node, instead it returns the node that Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63482&r1=63481&r2=63482&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Jan 31 09:50:11 2009 @@ -240,7 +240,13 @@ /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, /// looking for a better chain (aliasing node.) SDValue FindBetterChain(SDNode *N, SDValue Chain); - + + /// getShiftAmountTy - Returns a type large enough to hold any valid + /// shift amount - before type legalization these can be huge. + MVT getShiftAmountTy() { + return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); + } + public: DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) : DAG(D), @@ -1301,7 +1307,7 @@ if (N1C && N1C->getAPIntValue().isPowerOf2()) return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, DAG.getConstant(N1C->getAPIntValue().logBase2(), - TLI.getShiftAmountTy())); + getShiftAmountTy())); // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c if (N1C && isPowerOf2_64(-N1C->getSExtValue())) // FIXME: If the input is something that is easily negated (e.g. a @@ -1310,7 +1316,7 @@ DAG.getConstant(0, VT), DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, DAG.getConstant(Log2_64(-N1C->getSExtValue()), - TLI.getShiftAmountTy()))); + getShiftAmountTy()))); // (mul (shl X, c1), c2) -> (mul X, c2 << c1) if (N1C && N0.getOpcode() == ISD::SHL && isa(N0.getOperand(1))) { @@ -1406,18 +1412,18 @@ // Splat the sign bit into the register SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, DAG.getConstant(VT.getSizeInBits()-1, - TLI.getShiftAmountTy())); + getShiftAmountTy())); AddToWorkList(SGN.getNode()); // Add (N0 < 0) ? abs2 - 1 : 0; SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, DAG.getConstant(VT.getSizeInBits() - lg2, - TLI.getShiftAmountTy())); + getShiftAmountTy())); SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); AddToWorkList(SRL.getNode()); AddToWorkList(ADD.getNode()); // Divide by pow2 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, - DAG.getConstant(lg2, TLI.getShiftAmountTy())); + DAG.getConstant(lg2, getShiftAmountTy())); // If we're dividing by a positive value, we're done. Otherwise, we must // negate the result. @@ -1467,7 +1473,7 @@ if (N1C && N1C->getAPIntValue().isPowerOf2()) return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, DAG.getConstant(N1C->getAPIntValue().logBase2(), - TLI.getShiftAmountTy())); + getShiftAmountTy())); // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 if (N1.getOpcode() == ISD::SHL) { if (ConstantSDNode *SHC = dyn_cast(N1.getOperand(0))) { @@ -1607,7 +1613,7 @@ if (N1C && N1C->getAPIntValue() == 1) return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, DAG.getConstant(N0.getValueType().getSizeInBits() - 1, - TLI.getShiftAmountTy())); + getShiftAmountTy())); // fold (mulhs x, undef) -> 0 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) return DAG.getConstant(0, VT); @@ -2613,7 +2619,7 @@ TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && TLI.isTruncateFree(VT, TruncVT)) { - SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); + SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, N0.getOperand(0), Amt); SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, @@ -2740,7 +2746,7 @@ if (ShAmt) { Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, - DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); + DAG.getConstant(ShAmt, getShiftAmountTy())); AddToWorkList(Op.getNode()); } @@ -5722,7 +5728,7 @@ if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { unsigned ShCtV = N2C->getAPIntValue().logBase2(); ShCtV = XType.getSizeInBits()-ShCtV-1; - SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); + SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, ShCt); AddToWorkList(Shift.getNode()); @@ -5738,7 +5744,7 @@ SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, DAG.getConstant(XType.getSizeInBits()-1, - TLI.getShiftAmountTy())); + getShiftAmountTy())); AddToWorkList(Shift.getNode()); if (XType.bitsGT(AType)) { @@ -5787,7 +5793,7 @@ // shl setcc result by log2 n2c return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, DAG.getConstant(N2C->getAPIntValue().logBase2(), - TLI.getShiftAmountTy())); + getShiftAmountTy())); } // Check to see if this is the equivalent of setcc @@ -5810,7 +5816,7 @@ SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); return DAG.getNode(ISD::SRL, DL, XType, Ctlz, DAG.getConstant(Log2_32(XType.getSizeInBits()), - TLI.getShiftAmountTy())); + getShiftAmountTy())); } // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { @@ -5820,13 +5826,13 @@ return DAG.getNode(ISD::SRL, DL, XType, DAG.getNode(ISD::AND, XType, NegN0, NotN0), DAG.getConstant(XType.getSizeInBits()-1, - TLI.getShiftAmountTy())); + getShiftAmountTy())); } // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, DAG.getConstant(XType.getSizeInBits()-1, - TLI.getShiftAmountTy())); + getShiftAmountTy())); return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); } } @@ -5839,7 +5845,7 @@ MVT XType = N0.getValueType(); SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, DAG.getConstant(XType.getSizeInBits()-1, - TLI.getShiftAmountTy())); + getShiftAmountTy())); SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, N0, Shift); AddToWorkList(Shift.getNode()); @@ -5856,7 +5862,7 @@ SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, DAG.getConstant(XType.getSizeInBits()-1, - TLI.getShiftAmountTy())); + getShiftAmountTy())); SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, N0, Shift); AddToWorkList(Shift.getNode()); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63482&r1=63481&r2=63482&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Jan 31 09:50:11 2009 @@ -301,9 +301,6 @@ SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op); SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op); - - // Returns the legalized (truncated or extended) shift amount. - SDValue LegalizeShiftAmount(SDValue ShiftAmt); }; } @@ -903,8 +900,10 @@ case ISD::SHL: case ISD::SRA: case ISD::SRL: + case ISD::ROTL: + case ISD::ROTR: Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, Operands[0], - LegalizeShiftAmount(Operands[1]))); + DAG.getShiftAmountOperand(Operands[1]))); break; } } @@ -969,16 +968,6 @@ PseudoSourceValue::getFixedStack(SPFI), 0); } -SDValue SelectionDAGLegalize::LegalizeShiftAmount(SDValue ShiftAmt) { - if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType())) - return DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt); - - if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType())) - return DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), ShiftAmt); - - return ShiftAmt; -} - /// LegalizeOp - We know that the specified value has a legal type, and /// that its operands are legal. Now ensure that the operation itself @@ -3137,10 +3126,13 @@ case ISD::SRL_PARTS: { SmallVector Ops; bool Changed = false; - for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { + unsigned N = Node->getNumOperands(); + for (unsigned i = 0; i + 1 < N; ++i) { Ops.push_back(LegalizeOp(Node->getOperand(i))); Changed |= Ops.back() != Node->getOperand(i); } + Ops.push_back(LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(N-1)))); + Changed |= Ops.back() != Node->getOperand(N-1); if (Changed) Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); @@ -3191,23 +3183,24 @@ case ISD::FDIV: case ISD::FPOW: Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS - switch (getTypeAction(Node->getOperand(1).getValueType())) { + Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS + + if ((Node->getOpcode() == ISD::SHL || + Node->getOpcode() == ISD::SRL || + Node->getOpcode() == ISD::SRA) && + !Node->getValueType(0).isVector()) + Tmp2 = DAG.getShiftAmountOperand(Tmp2); + + switch (getTypeAction(Tmp2.getValueType())) { case Expand: assert(0 && "Not possible"); case Legal: - Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. + Tmp2 = LegalizeOp(Tmp2); // Legalize the RHS. break; case Promote: - Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. + Tmp2 = PromoteOp(Tmp2); // Promote the RHS. break; } - if ((Node->getOpcode() == ISD::SHL || - Node->getOpcode() == ISD::SRL || - Node->getOpcode() == ISD::SRA) && - !Node->getValueType(0).isVector()) { - Tmp2 = LegalizeShiftAmount(Tmp2); - } - Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { @@ -3673,7 +3666,7 @@ case ISD::ROTL: case ISD::ROTR: Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS - Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS + Tmp2 = LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(1))); // RHS Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { default: Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=63482&r1=63481&r2=63482&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Sat Jan 31 09:50:11 2009 @@ -230,7 +230,7 @@ unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), - DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); + DAG.getConstant(DiffBits, TLI.getPointerTy())); } SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { @@ -327,7 +327,7 @@ // Extract the element at OldIdx / 2 from the new vector. SDValue OldIdx = N->getOperand(1); SDValue NewIdx = DAG.getNode(ISD::SRL, dl, OldIdx.getValueType(), OldIdx, - DAG.getConstant(1, TLI.getShiftAmountTy())); + DAG.getConstant(1, TLI.getPointerTy())); SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, NewIdx); // Select the appropriate half of the element: Lo if OldIdx was even, @@ -335,7 +335,7 @@ SDValue Lo = Elt; SDValue Hi = DAG.getNode(ISD::SRL, dl, NewVT, Elt, DAG.getConstant(OldVT.getSizeInBits(), - TLI.getShiftAmountTy())); + TLI.getPointerTy())); if (TLI.isBigEndian()) std::swap(Lo, Hi); @@ -621,7 +621,7 @@ // Shift it to the right position and "or" it in. Part = DAG.getNode(ISD::SHL, dl, NVT, Part, DAG.getConstant(i * RegVT.getSizeInBits(), - TLI.getShiftAmountTy())); + TLI.getPointerTy())); Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part); } @@ -768,8 +768,7 @@ DebugLoc dl = N->getDebugLoc(); Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, - DAG.getConstant(OVT.getSizeInBits(), - TLI.getShiftAmountTy())); + DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy())); return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi); } @@ -1329,7 +1328,7 @@ Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); // The high part replicates the sign bit of Lo, make it explicit. Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, - DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy())); + DAG.getConstant(NVTBits-1, TLI.getPointerTy())); } } @@ -1473,7 +1472,7 @@ // lo part. unsigned LoSize = Lo.getValueType().getSizeInBits(); Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, - DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); + DAG.getConstant(LoSize-1, TLI.getPointerTy())); } else if (ExtType == ISD::ZEXTLOAD) { // The high part is just a zero. Hi = DAG.getConstant(0, NVT); @@ -1535,12 +1534,12 @@ Lo = DAG.getNode(ISD::OR, dl, NVT, Lo, DAG.getNode(ISD::SHL, dl, NVT, Hi, DAG.getConstant(ExcessBits, - TLI.getShiftAmountTy()))); + TLI.getPointerTy()))); // Move high bits to the right position in Hi. Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT, Hi, DAG.getConstant(NVT.getSizeInBits() - ExcessBits, - TLI.getShiftAmountTy())); + TLI.getPointerTy())); } } @@ -1762,7 +1761,7 @@ // The high part is obtained by SRA'ing all but one of the bits of low part. unsigned LoSize = NVT.getSizeInBits(); Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, - DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); + DAG.getConstant(LoSize-1, TLI.getPointerTy())); } else { // For example, extension of an i48 to an i64. The operand type necessarily // promotes to the result type, so will end up being expanded too. @@ -1795,7 +1794,7 @@ // things like sextinreg V:i64 from i8. Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo, DAG.getConstant(Hi.getValueType().getSizeInBits()-1, - TLI.getShiftAmountTy())); + TLI.getPointerTy())); } else { // For example, extension of an i48 to an i64. Leave the low part alone, // sext_inreg the high part. @@ -1831,8 +1830,7 @@ Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); Hi = DAG.getNode(ISD::SRL, dl, N->getOperand(0).getValueType(), N->getOperand(0), - DAG.getConstant(NVT.getSizeInBits(), - TLI.getShiftAmountTy())); + DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy())); Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); } @@ -1922,20 +1920,18 @@ assert(0 && "Do not know how to expand this operator's operand!"); abort(); - case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; + case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; + case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; - - case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; - case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; - case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; - case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; - case ISD::STORE: Res = ExpandIntOp_STORE(cast(N), OpNo); - break; - case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; - case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; + case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; + case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; + case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; + case ISD::STORE: Res = ExpandIntOp_STORE(cast(N), OpNo); break; + case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; + case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; } // If the result is null, the sub-method took care of registering results etc. @@ -2175,11 +2171,11 @@ // Transfer high bits from the top of Lo to the bottom of Hi. Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi, DAG.getConstant(NVT.getSizeInBits() - ExcessBits, - TLI.getShiftAmountTy())); + TLI.getPointerTy())); Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, DAG.getNode(ISD::SRL, NVT, Lo, DAG.getConstant(ExcessBits, - TLI.getShiftAmountTy()))); + TLI.getPointerTy()))); } // Store both the high bits and maybe some of the low bits. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=63482&r1=63481&r2=63482&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Sat Jan 31 09:50:11 2009 @@ -942,8 +942,8 @@ Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Lo); Hi = DAG.getNode(ISD::ANY_EXTEND, NVT, Hi); - Hi = DAG.getNode(ISD::SHL, NVT, Hi, DAG.getConstant(LVT.getSizeInBits(), - TLI.getShiftAmountTy())); + Hi = DAG.getNode(ISD::SHL, NVT, Hi, + DAG.getConstant(LVT.getSizeInBits(), TLI.getPointerTy())); return DAG.getNode(ISD::OR, NVT, Lo, Hi); } @@ -1028,8 +1028,7 @@ Op.getValueType().getSizeInBits() && "Invalid integer splitting!"); Lo = DAG.getNode(ISD::TRUNCATE, LoVT, Op); Hi = DAG.getNode(ISD::SRL, Op.getValueType(), Op, - DAG.getConstant(LoVT.getSizeInBits(), - TLI.getShiftAmountTy())); + DAG.getConstant(LoVT.getSizeInBits(), TLI.getPointerTy())); Hi = DAG.getNode(ISD::TRUNCATE, HiVT, Hi); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=63482&r1=63481&r2=63482&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Sat Jan 31 09:50:11 2009 @@ -111,11 +111,6 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_ShiftOp(SDNode *N) { SDValue LHS = GetScalarizedVector(N->getOperand(0)); SDValue ShiftAmt = GetScalarizedVector(N->getOperand(1)); - if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType())) - ShiftAmt = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt); - else if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType())) - ShiftAmt = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), ShiftAmt); - return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, ShiftAmt); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63482&r1=63481&r2=63482&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat Jan 31 09:50:11 2009 @@ -1287,6 +1287,17 @@ return SDValue(N, 0); } +/// getShiftAmountOperand - Return the specified value casted to +/// the target's desired shift amount type. +SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) { + MVT OpTy = Op.getValueType(); + MVT ShTy = TLI.getShiftAmountTy(); + if (OpTy == ShTy || OpTy.isVector()) return Op; + + ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; + return getNode(Opcode, ShTy, Op); +} + /// CreateStackTemporary - Create a stack temporary, suitable for holding the /// specified value type. SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { @@ -2529,9 +2540,6 @@ "Shift operators return type must be the same as their first arg"); assert(VT.isInteger() && N2.getValueType().isInteger() && "Shifts only work on integers"); - assert((N2.getValueType() == TLI.getShiftAmountTy() || - (N2.getValueType().isVector() && N2.getValueType().isInteger())) && - "Wrong type for shift amount"); // Always fold shifts of i1 values so the code generator doesn't need to // handle them. Since we know the size of the shift has to be less than the Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63482&r1=63481&r2=63482&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Sat Jan 31 09:50:11 2009 @@ -427,7 +427,7 @@ Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi); Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi, DAG.getConstant(Lo.getValueType().getSizeInBits(), - TLI.getShiftAmountTy())); + TLI.getPointerTy())); Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo); Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi); } @@ -587,7 +587,7 @@ unsigned OddParts = NumParts - RoundParts; SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val, DAG.getConstant(RoundBits, - TLI.getShiftAmountTy())); + TLI.getPointerTy())); getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT); if (TLI.isBigEndian()) // The odd parts were reversed by getCopyToParts - unreverse them. @@ -1424,14 +1424,14 @@ ISD::SETUGT); SDValue ShiftOp; - if (VT.bitsGT(TLI.getShiftAmountTy())) + if (VT.bitsGT(TLI.getPointerTy())) ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), - TLI.getShiftAmountTy(), SUB); + TLI.getPointerTy(), SUB); else ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), - TLI.getShiftAmountTy(), SUB); + TLI.getPointerTy(), SUB); - B.Reg = FuncInfo.MakeReg(TLI.getShiftAmountTy()); + B.Reg = FuncInfo.MakeReg(TLI.getPointerTy()); SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), B.Reg, ShiftOp); // Set NextBlock to be the MBB immediately after the current one, if any. @@ -1463,7 +1463,7 @@ BitTestCase &B) { // Make desired shift SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), Reg, - TLI.getShiftAmountTy()); + TLI.getPointerTy()); SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), TLI.getPointerTy(), DAG.getConstant(1, TLI.getPointerTy()), @@ -2121,12 +2121,12 @@ SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); if (!isa(I.getType())) { - if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType())) + if (TLI.getPointerTy().bitsLT(Op2.getValueType())) Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), - TLI.getShiftAmountTy(), Op2); - else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType())) + TLI.getPointerTy(), Op2); + else if (TLI.getPointerTy().bitsGT(Op2.getValueType())) Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), - TLI.getShiftAmountTy(), Op2); + TLI.getPointerTy(), Op2); } setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), @@ -2673,7 +2673,7 @@ unsigned Amt = Log2_64(ElementSize); IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), N.getValueType(), IdxN, - DAG.getConstant(Amt, TLI.getShiftAmountTy())); + DAG.getConstant(Amt, TLI.getPointerTy())); } else { SDValue Scale = DAG.getIntPtrConstant(ElementSize); IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), @@ -3023,7 +3023,7 @@ SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, DAG.getConstant(0x7f800000, MVT::i32)); SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, - DAG.getConstant(23, TLI.getShiftAmountTy())); + DAG.getConstant(23, TLI.getPointerTy())); SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, DAG.getConstant(127, MVT::i32)); return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); @@ -3095,7 +3095,7 @@ // IntegerPartOfX <<= 23; IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, - DAG.getConstant(23, TLI.getShiftAmountTy())); + DAG.getConstant(23, TLI.getPointerTy())); if (LimitFloatPrecision <= 6) { // For floating-point precision of 6: @@ -3535,7 +3535,7 @@ // IntegerPartOfX <<= 23; IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, - DAG.getConstant(23, TLI.getShiftAmountTy())); + DAG.getConstant(23, TLI.getPointerTy())); if (LimitFloatPrecision <= 6) { // For floating-point precision of 6: @@ -3668,7 +3668,7 @@ // IntegerPartOfX <<= 23; IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, - DAG.getConstant(23, TLI.getShiftAmountTy())); + DAG.getConstant(23, TLI.getPointerTy())); if (LimitFloatPrecision <= 6) { // For floating-point precision of 6: Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=63482&r1=63481&r2=63482&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sat Jan 31 09:50:11 2009 @@ -1651,19 +1651,21 @@ VT == N0.getValueType() && N0.getOpcode() == ISD::AND) if (ConstantSDNode *AndRHS = dyn_cast(N0.getOperand(1))) { + MVT ShiftTy = DCI.isBeforeLegalize() ? + getPointerTy() : getShiftAmountTy(); if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 // Perform the xform if the AND RHS is a single bit. if (isPowerOf2_64(AndRHS->getZExtValue())) { return DAG.getNode(ISD::SRL, VT, N0, - DAG.getConstant(Log2_64(AndRHS->getZExtValue()), - getShiftAmountTy())); + DAG.getConstant(Log2_64(AndRHS->getZExtValue()), + ShiftTy)); } } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) { // (X & 8) == 8 --> (X & 8) >> 3 // Perform the xform if C1 is a single bit. if (C1.isPowerOf2()) { return DAG.getNode(ISD::SRL, VT, N0, - DAG.getConstant(C1.logBase2(), getShiftAmountTy())); + DAG.getConstant(C1.logBase2(), ShiftTy)); } } } Added: llvm/trunk/test/CodeGen/X86/2009-01-31-BigShift.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-01-31-BigShift.ll?rev=63482&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-01-31-BigShift.ll (added) +++ llvm/trunk/test/CodeGen/X86/2009-01-31-BigShift.ll Sat Jan 31 09:50:11 2009 @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=x86 | not grep and +; PR3401 + +define void @x(i288 %i) nounwind { + call void @add(i288 %i) + ret void +} + +declare void @add(i288) Added: llvm/trunk/test/CodeGen/X86/2009-01-31-BigShift2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-01-31-BigShift2.ll?rev=63482&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-01-31-BigShift2.ll (added) +++ llvm/trunk/test/CodeGen/X86/2009-01-31-BigShift2.ll Sat Jan 31 09:50:11 2009 @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -march=x86 | grep {mov.*56} +; PR3449 + +define void @test(<8 x double>* %P, i64* %Q) nounwind { + %A = load <8 x double>* %P ; <<8 x double>> [#uses=1] + %B = bitcast <8 x double> %A to i512 ; [#uses=1] + %C = lshr i512 %B, 448 ; [#uses=1] + %D = trunc i512 %C to i64 ; [#uses=1] + volatile store i64 %D, i64* %Q + ret void +} Added: llvm/trunk/test/CodeGen/X86/2009-01-31-BigShift3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-01-31-BigShift3.ll?rev=63482&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-01-31-BigShift3.ll (added) +++ llvm/trunk/test/CodeGen/X86/2009-01-31-BigShift3.ll Sat Jan 31 09:50:11 2009 @@ -0,0 +1,31 @@ +; RUN: llvm-as < %s | llc -march=x86 +; PR3450 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i386-apple-darwin7" + %struct.BitMap = type { i8* } + %struct.BitMapListStruct = type { %struct.BitMap, %struct.BitMapListStruct*, %struct.BitMapListStruct* } + %struct.Material = type { float, float, float, %struct.Material*, %struct.Material* } + %struct.ObjPoint = type { double, double, double, double, double, double } + %struct.ObjectStruct = type { [57 x i8], %struct.PointListStruct*, %struct.Poly3Struct*, %struct.Poly4Struct*, %struct.Texture*, %struct.Material*, %struct.Point, i32, i32, %struct.Point, %struct.Point, %struct.Point, %struct.ObjectStruct*, %struct.ObjectStruct*, i32, i32, i32, i32, i32, i32, i32, %struct.ObjectStruct*, %struct.ObjectStruct* } + %struct.Point = type { double, double, double } + %struct.PointListStruct = type { %struct.ObjPoint*, %struct.PointListStruct*, %struct.PointListStruct* } + %struct.Poly3Struct = type { [3 x %struct.ObjPoint*], %struct.Material*, %struct.Texture*, %struct.Poly3Struct*, %struct.Poly3Struct* } + %struct.Poly4Struct = type { [4 x %struct.ObjPoint*], %struct.Material*, %struct.Texture*, %struct.Poly4Struct*, %struct.Poly4Struct* } + %struct.Texture = type { %struct.Point, %struct.BitMapListStruct*, %struct.Point, %struct.Point, %struct.Point, %struct.Texture*, %struct.Texture* } + +define fastcc void @ScaleObjectAdd(%struct.ObjectStruct* %o, double %sx, double %sy, double %sz) nounwind { +entry: + %sz101112.ins = or i960 0, 0 ; [#uses=1] + br i1 false, label %return, label %bb1.preheader + +bb1.preheader: ; preds = %entry + %0 = lshr i960 %sz101112.ins, 640 ; [#uses=0] + br label %bb1 + +bb1: ; preds = %bb1, %bb1.preheader + br label %bb1 + +return: ; preds = %entry + ret void +} From sanjiv.gupta at microchip.com Sat Jan 31 13:01:00 2009 From: sanjiv.gupta at microchip.com (sanjiv gupta) Date: Sun, 01 Feb 2009 00:31:00 +0530 Subject: [llvm-commits] [llvm] r63482 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ test/CodeGen/X86/ In-Reply-To: <200901311550.n0VFoEW5029548@zion.cs.uiuc.edu> References: <200901311550.n0VFoEW5029548@zion.cs.uiuc.edu> Message-ID: <1233428460.5926.12.camel@idc-lt-i00171.microchip.com> On Sat, 2009-01-31 at 15:50 +0000, Duncan Sands wrote: > Author: baldrick > Date: Sat Jan 31 09:50:11 2009 > New Revision: 63482 > > URL: http://llvm.org/viewvc/llvm-project?rev=63482&view=rev > Log: > Fix PR3401: when using large integers, the type > returned by getShiftAmountTy may be too small > to hold shift values (it is an i8 on x86-32). > Before and during type legalization, use a large > but legal type for shift amounts: getPointerTy; For PIC16 getPointerTy returns i16 which is illegal. And probably this revision broke shift operations test cases in our auto-testing framework. Looks like we have to do some additional work here. - Sanjiv From sabre at nondot.org Sat Jan 31 13:05:29 2009 From: sabre at nondot.org (Chris Lattner) Date: Sat, 31 Jan 2009 19:05:29 -0000 Subject: [llvm-commits] [llvm] r63483 - in /llvm/trunk: lib/Transforms/Scalar/InstructionCombining.cpp test/Transforms/InstCombine/2009-01-31-InfIterate.ll test/Transforms/InstCombine/cast-sext-zext.ll Message-ID: <200901311905.n0VJ5TFf004748@zion.cs.uiuc.edu> Author: lattner Date: Sat Jan 31 13:05:27 2009 New Revision: 63483 URL: http://llvm.org/viewvc/llvm-project?rev=63483&view=rev Log: Fix PR3452 (an infinite loop bootstrapping) by disabling the recent improvements to the EvaluateInDifferentType code. This code works by just inserted a bunch of new code and then seeing if it is useful. Instcombine is not allowed to do this: it can only insert new code if it is useful, and only when it is converging to a more canonical fixed point. Now that we iterate when DCE makes progress, this causes an infinite loop when the code ends up not being used. Added: llvm/trunk/test/Transforms/InstCombine/2009-01-31-InfIterate.ll Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp llvm/trunk/test/Transforms/InstCombine/cast-sext-zext.ll Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=63483&r1=63482&r2=63483&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Sat Jan 31 13:05:27 2009 @@ -7892,15 +7892,15 @@ break; case Instruction::ZExt: { DoXForm = NumCastsRemoved >= 1; - if (!DoXForm) { + if (!DoXForm && 0) { // If it's unnecessary to issue an AND to clear the high bits, it's // always profitable to do this xform. - Value *TryRes = EvaluateInDifferentType(SrcI, DestTy, - CI.getOpcode() == Instruction::SExt); + Value *TryRes = EvaluateInDifferentType(SrcI, DestTy, false); APInt Mask(APInt::getBitsSet(DestBitSize, SrcBitSize, DestBitSize)); if (MaskedValueIsZero(TryRes, Mask)) return ReplaceInstUsesWith(CI, TryRes); - else if (Instruction *TryI = dyn_cast(TryRes)) + + if (Instruction *TryI = dyn_cast(TryRes)) if (TryI->use_empty()) EraseInstFromFunction(*TryI); } @@ -7908,7 +7908,7 @@ } case Instruction::SExt: { DoXForm = NumCastsRemoved >= 2; - if (!DoXForm && !isa(SrcI)) { + if (!DoXForm && !isa(SrcI) && 0) { // If we do not have to emit the truncate + sext pair, then it's always // profitable to do this xform. // @@ -7918,12 +7918,12 @@ // t3 = sext i16 t2 to i32 // != // i32 t1 - Value *TryRes = EvaluateInDifferentType(SrcI, DestTy, - CI.getOpcode() == Instruction::SExt); + Value *TryRes = EvaluateInDifferentType(SrcI, DestTy, true); unsigned NumSignBits = ComputeNumSignBits(TryRes); if (NumSignBits > (DestBitSize - SrcBitSize)) return ReplaceInstUsesWith(CI, TryRes); - else if (Instruction *TryI = dyn_cast(TryRes)) + + if (Instruction *TryI = dyn_cast(TryRes)) if (TryI->use_empty()) EraseInstFromFunction(*TryI); } @@ -7932,11 +7932,13 @@ } if (DoXForm) { + DOUT << "ICE: EvaluateInDifferentType converting expression type to avoid" + << " cast: " << CI; Value *Res = EvaluateInDifferentType(SrcI, DestTy, CI.getOpcode() == Instruction::SExt); if (JustReplace) - // Just replace this cast with the result. - return ReplaceInstUsesWith(CI, Res); + // Just replace this cast with the result. + return ReplaceInstUsesWith(CI, Res); assert(Res->getType() == DestTy); switch (CI.getOpcode()) { Added: llvm/trunk/test/Transforms/InstCombine/2009-01-31-InfIterate.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2009-01-31-InfIterate.ll?rev=63483&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/2009-01-31-InfIterate.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/2009-01-31-InfIterate.ll Sat Jan 31 13:05:27 2009 @@ -0,0 +1,484 @@ +; RUN: llvm-as < %s | opt -instcombine | llvm-dis +; PR3452 +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-unknown-linux-gnu" + at __clz_tab = external constant [256 x i8] ; <[256 x i8]*> [#uses=3] + at llvm.used = appending global [1 x i8*] [ i8* bitcast (void (i128, i128, i128*)* @__udivmodti4 to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] + +define fastcc void @__udivmodti4(i128 %n, i128 %d, i128* %rp) nounwind alwaysinline { +entry: + %tmp1 = trunc i128 %n to i64 ; [#uses=12] + %sroa.store.elt = lshr i128 %n, 64 ; [#uses=1] + %tmp2 = trunc i128 %sroa.store.elt to i64 ; [#uses=12] + %tmp3 = trunc i128 %d to i64 ; [#uses=12] + %sroa.store.elt16 = lshr i128 %d, 64 ; [#uses=1] + %tmp4 = trunc i128 %sroa.store.elt16 to i64 ; [#uses=7] + %tmp5 = icmp eq i64 %tmp4, 0 ; [#uses=1] + br i1 %tmp5, label %bb, label %bb86 + +bb: ; preds = %entry + %tmp6 = icmp ugt i64 %tmp3, %tmp2 ; [#uses=1] + br i1 %tmp6, label %bb33.thread, label %bb50 + +bb33.thread: ; preds = %bb + br label %bb31 + +bb31: ; preds = %bb33, %bb33.thread + %__a28.0.reg2mem.0 = phi i64 [ 56, %bb33.thread ], [ %tmp9, %bb33 ] ; [#uses=3] + %.cast = and i64 %__a28.0.reg2mem.0, 4294967288 ; [#uses=1] + %tmp = shl i64 255, %.cast ; [#uses=1] + %tmp7 = and i64 %tmp3, %tmp ; [#uses=1] + %tmp8 = icmp eq i64 %tmp7, 0 ; [#uses=1] + br i1 %tmp8, label %bb33, label %bb34 + +bb33: ; preds = %bb31 + %tmp9 = add i64 %__a28.0.reg2mem.0, -8 ; [#uses=3] + %tmp10 = icmp eq i64 %tmp9, 0 ; [#uses=1] + br i1 %tmp10, label %bb34, label %bb31 + +bb34: ; preds = %bb33, %bb31 + %__a28.0.reg2mem.1 = phi i64 [ %__a28.0.reg2mem.0, %bb31 ], [ %tmp9, %bb33 ] ; [#uses=2] + %.cast35 = and i64 %__a28.0.reg2mem.1, 4294967288 ; [#uses=1] + %tmp11 = lshr i64 %tmp3, %.cast35 ; [#uses=1] + %tmp12 = getelementptr [256 x i8]* @__clz_tab, i64 0, i64 %tmp11 ; [#uses=1] + %tmp13 = load i8* %tmp12, align 1 ; [#uses=1] + %tmp14 = zext i8 %tmp13 to i64 ; [#uses=1] + %tmp15 = add i64 %tmp14, %__a28.0.reg2mem.1 ; [#uses=2] + %tmp16 = sub i64 64, %tmp15 ; [#uses=7] + %tmp17 = icmp eq i64 %tmp15, 64 ; [#uses=1] + br i1 %tmp17, label %bb41, label %bb36 + +bb36: ; preds = %bb34 + %.cast37 = and i64 %tmp16, 4294967295 ; [#uses=1] + %tmp18 = shl i64 %tmp3, %.cast37 ; [#uses=1] + %.cast38 = and i64 %tmp16, 4294967295 ; [#uses=1] + %tmp19 = shl i64 %tmp2, %.cast38 ; [#uses=1] + %tmp20 = sub i64 64, %tmp16 ; [#uses=1] + %.cast39 = and i64 %tmp20, 4294967295 ; [#uses=1] + %tmp21 = lshr i64 %tmp1, %.cast39 ; [#uses=1] + %tmp22 = or i64 %tmp19, %tmp21 ; [#uses=1] + %.cast40 = and i64 %tmp16, 4294967295 ; [#uses=1] + %tmp23 = shl i64 %tmp1, %.cast40 ; [#uses=1] + br label %bb41 + +bb41: ; preds = %bb36, %bb34 + %n1.0 = phi i64 [ %tmp2, %bb34 ], [ %tmp22, %bb36 ] ; [#uses=2] + %n0.0 = phi i64 [ %tmp1, %bb34 ], [ %tmp23, %bb36 ] ; [#uses=2] + %d0.0 = phi i64 [ %tmp3, %bb34 ], [ %tmp18, %bb36 ] ; [#uses=8] + %tmp24 = lshr i64 %d0.0, 32 ; [#uses=4] + %tmp25 = and i64 %d0.0, 4294967295 ; [#uses=2] + %tmp26 = urem i64 %n1.0, %tmp24 ; [#uses=1] + %tmp27 = udiv i64 %n1.0, %tmp24 ; [#uses=1] + %tmp28 = mul i64 %tmp27, %tmp25 ; [#uses=3] + %tmp29 = shl i64 %tmp26, 32 ; [#uses=1] + %tmp30 = lshr i64 %n0.0, 32 ; [#uses=1] + %tmp31 = or i64 %tmp29, %tmp30 ; [#uses=3] + %tmp32 = icmp ult i64 %tmp31, %tmp28 ; [#uses=1] + br i1 %tmp32, label %bb42, label %bb45 + +bb42: ; preds = %bb41 + %tmp33 = add i64 %tmp31, %d0.0 ; [#uses=4] + %.not = icmp uge i64 %tmp33, %d0.0 ; [#uses=1] + %tmp34 = icmp ult i64 %tmp33, %tmp28 ; [#uses=1] + %or.cond = and i1 %tmp34, %.not ; [#uses=1] + br i1 %or.cond, label %bb44, label %bb45 + +bb44: ; preds = %bb42 + %tmp35 = add i64 %tmp33, %d0.0 ; [#uses=1] + br label %bb45 + +bb45: ; preds = %bb44, %bb42, %bb41 + %__r123.0 = phi i64 [ %tmp31, %bb41 ], [ %tmp33, %bb42 ], [ %tmp35, %bb44 ] ; [#uses=1] + %tmp36 = sub i64 %__r123.0, %tmp28 ; [#uses=2] + %tmp37 = urem i64 %tmp36, %tmp24 ; [#uses=1] + %tmp38 = udiv i64 %tmp36, %tmp24 ; [#uses=1] + %tmp39 = mul i64 %tmp38, %tmp25 ; [#uses=5] + %tmp40 = shl i64 %tmp37, 32 ; [#uses=1] + %tmp41 = and i64 %n0.0, 4294967295 ; [#uses=1] + %tmp42 = or i64 %tmp40, %tmp41 ; [#uses=3] + %tmp43 = icmp ult i64 %tmp42, %tmp39 ; [#uses=1] + br i1 %tmp43, label %bb46, label %bb83 + +bb46: ; preds = %bb45 + %tmp44 = add i64 %tmp42, %d0.0 ; [#uses=4] + %.not137 = icmp uge i64 %tmp44, %d0.0 ; [#uses=1] + %tmp45 = icmp ult i64 %tmp44, %tmp39 ; [#uses=1] + %or.cond138 = and i1 %tmp45, %.not137 ; [#uses=1] + br i1 %or.cond138, label %bb48, label %bb83 + +bb48: ; preds = %bb46 + %tmp46 = add i64 %tmp44, %d0.0 ; [#uses=1] + br label %bb83 + +bb50: ; preds = %bb + %tmp47 = icmp eq i64 %tmp3, 0 ; [#uses=1] + br i1 %tmp47, label %bb51, label %bb56.thread + +bb51: ; preds = %bb50 + %tmp48 = udiv i64 1, %tmp3 ; [#uses=1] + br label %bb56.thread + +bb53: ; preds = %bb56, %bb56.thread + %__a19.0.reg2mem.0 = phi i64 [ 56, %bb56.thread ], [ %tmp51, %bb56 ] ; [#uses=3] + %.cast54 = and i64 %__a19.0.reg2mem.0, 4294967288 ; [#uses=1] + %tmp133 = shl i64 255, %.cast54 ; [#uses=1] + %tmp49 = and i64 %d0.1.ph, %tmp133 ; [#uses=1] + %tmp50 = icmp eq i64 %tmp49, 0 ; [#uses=1] + br i1 %tmp50, label %bb56, label %bb57 + +bb56.thread: ; preds = %bb51, %bb50 + %d0.1.ph = phi i64 [ %tmp48, %bb51 ], [ %tmp3, %bb50 ] ; [#uses=5] + br label %bb53 + +bb56: ; preds = %bb53 + %tmp51 = add i64 %__a19.0.reg2mem.0, -8 ; [#uses=3] + %tmp52 = icmp eq i64 %tmp51, 0 ; [#uses=1] + br i1 %tmp52, label %bb57, label %bb53 + +bb57: ; preds = %bb56, %bb53 + %__a19.0.reg2mem.1 = phi i64 [ %__a19.0.reg2mem.0, %bb53 ], [ %tmp51, %bb56 ] ; [#uses=2] + %.cast58 = and i64 %__a19.0.reg2mem.1, 4294967288 ; [#uses=1] + %tmp53 = lshr i64 %d0.1.ph, %.cast58 ; [#uses=1] + %tmp54 = getelementptr [256 x i8]* @__clz_tab, i64 0, i64 %tmp53 ; [#uses=1] + %tmp55 = load i8* %tmp54, align 1 ; [#uses=1] + %tmp56 = zext i8 %tmp55 to i64 ; [#uses=1] + %tmp57 = add i64 %tmp56, %__a19.0.reg2mem.1 ; [#uses=2] + %tmp58 = sub i64 64, %tmp57 ; [#uses=7] + %tmp59 = icmp eq i64 %tmp57, 64 ; [#uses=1] + br i1 %tmp59, label %bb74, label %bb60 + +bb60: ; preds = %bb57 + %tmp60 = sub i64 64, %tmp58 ; [#uses=2] + %.cast61 = and i64 %tmp58, 4294967295 ; [#uses=1] + %tmp61 = shl i64 %d0.1.ph, %.cast61 ; [#uses=9] + %.cast62 = and i64 %tmp60, 4294967295 ; [#uses=1] + %tmp62 = lshr i64 %tmp2, %.cast62 ; [#uses=2] + %.cast63 = and i64 %tmp58, 4294967295 ; [#uses=1] + %tmp63 = shl i64 %tmp2, %.cast63 ; [#uses=1] + %.cast64 = and i64 %tmp60, 4294967295 ; [#uses=1] + %tmp64 = lshr i64 %tmp1, %.cast64 ; [#uses=1] + %tmp65 = or i64 %tmp63, %tmp64 ; [#uses=2] + %.cast65 = and i64 %tmp58, 4294967295 ; [#uses=1] + %tmp66 = shl i64 %tmp1, %.cast65 ; [#uses=1] + %tmp67 = lshr i64 %tmp61, 32 ; [#uses=4] + %tmp68 = and i64 %tmp61, 4294967295 ; [#uses=2] + %tmp69 = urem i64 %tmp62, %tmp67 ; [#uses=1] + %tmp70 = udiv i64 %tmp62, %tmp67 ; [#uses=1] + %tmp71 = mul i64 %tmp70, %tmp68 ; [#uses=3] + %tmp72 = shl i64 %tmp69, 32 ; [#uses=1] + %tmp73 = lshr i64 %tmp65, 32 ; [#uses=1] + %tmp74 = or i64 %tmp72, %tmp73 ; [#uses=3] + %tmp75 = icmp ult i64 %tmp74, %tmp71 ; [#uses=1] + br i1 %tmp75, label %bb66, label %bb69 + +bb66: ; preds = %bb60 + %tmp76 = add i64 %tmp74, %tmp61 ; [#uses=4] + %.not139 = icmp uge i64 %tmp76, %tmp61 ; [#uses=1] + %tmp77 = icmp ult i64 %tmp76, %tmp71 ; [#uses=1] + %or.cond140 = and i1 %tmp77, %.not139 ; [#uses=1] + br i1 %or.cond140, label %bb68, label %bb69 + +bb68: ; preds = %bb66 + %tmp78 = add i64 %tmp76, %tmp61 ; [#uses=1] + br label %bb69 + +bb69: ; preds = %bb68, %bb66, %bb60 + %__r114.0 = phi i64 [ %tmp74, %bb60 ], [ %tmp76, %bb66 ], [ %tmp78, %bb68 ] ; [#uses=1] + %tmp79 = sub i64 %__r114.0, %tmp71 ; [#uses=2] + %tmp80 = urem i64 %tmp79, %tmp67 ; [#uses=1] + %tmp81 = udiv i64 %tmp79, %tmp67 ; [#uses=1] + %tmp82 = mul i64 %tmp81, %tmp68 ; [#uses=3] + %tmp83 = shl i64 %tmp80, 32 ; [#uses=1] + %tmp84 = and i64 %tmp65, 4294967295 ; [#uses=1] + %tmp85 = or i64 %tmp83, %tmp84 ; [#uses=3] + %tmp86 = icmp ult i64 %tmp85, %tmp82 ; [#uses=1] + br i1 %tmp86, label %bb70, label %bb73 + +bb70: ; preds = %bb69 + %tmp87 = add i64 %tmp85, %tmp61 ; [#uses=4] + %.not141 = icmp uge i64 %tmp87, %tmp61 ; [#uses=1] + %tmp88 = icmp ult i64 %tmp87, %tmp82 ; [#uses=1] + %or.cond142 = and i1 %tmp88, %.not141 ; [#uses=1] + br i1 %or.cond142, label %bb72, label %bb73 + +bb72: ; preds = %bb70 + %tmp89 = add i64 %tmp87, %tmp61 ; [#uses=1] + br label %bb73 + +bb73: ; preds = %bb72, %bb70, %bb69 + %__r013.0 = phi i64 [ %tmp85, %bb69 ], [ %tmp87, %bb70 ], [ %tmp89, %bb72 ] ; [#uses=1] + br label %bb74 + +bb74: ; preds = %bb73, %bb57 + %__r013.0.pn = phi i64 [ %__r013.0, %bb73 ], [ %tmp2, %bb57 ] ; [#uses=1] + %.pn135 = phi i64 [ %tmp82, %bb73 ], [ %d0.1.ph, %bb57 ] ; [#uses=1] + %n0.2 = phi i64 [ %tmp66, %bb73 ], [ %tmp1, %bb57 ] ; [#uses=2] + %d0.2 = phi i64 [ %tmp61, %bb73 ], [ %d0.1.ph, %bb57 ] ; [#uses=8] + %n1.1 = sub i64 %__r013.0.pn, %.pn135 ; [#uses=2] + %tmp90 = lshr i64 %d0.2, 32 ; [#uses=4] + %tmp91 = and i64 %d0.2, 4294967295 ; [#uses=2] + %tmp92 = urem i64 %n1.1, %tmp90 ; [#uses=1] + %tmp93 = udiv i64 %n1.1, %tmp90 ; [#uses=1] + %tmp94 = mul i64 %tmp93, %tmp91 ; [#uses=3] + %tmp95 = shl i64 %tmp92, 32 ; [#uses=1] + %tmp96 = lshr i64 %n0.2, 32 ; [#uses=1] + %tmp97 = or i64 %tmp95, %tmp96 ; [#uses=3] + %tmp98 = icmp ult i64 %tmp97, %tmp94 ; [#uses=1] + br i1 %tmp98, label %bb75, label %bb78 + +bb75: ; preds = %bb74 + %tmp99 = add i64 %tmp97, %d0.2 ; [#uses=4] + %.not143 = icmp uge i64 %tmp99, %d0.2 ; [#uses=1] + %tmp100 = icmp ult i64 %tmp99, %tmp94 ; [#uses=1] + %or.cond144 = and i1 %tmp100, %.not143 ; [#uses=1] + br i1 %or.cond144, label %bb77, label %bb78 + +bb77: ; preds = %bb75 + %tmp101 = add i64 %tmp99, %d0.2 ; [#uses=1] + br label %bb78 + +bb78: ; preds = %bb77, %bb75, %bb74 + %__r17.0 = phi i64 [ %tmp97, %bb74 ], [ %tmp99, %bb75 ], [ %tmp101, %bb77 ] ; [#uses=1] + %tmp102 = sub i64 %__r17.0, %tmp94 ; [#uses=2] + %tmp103 = urem i64 %tmp102, %tmp90 ; [#uses=1] + %tmp104 = udiv i64 %tmp102, %tmp90 ; [#uses=1] + %tmp105 = mul i64 %tmp104, %tmp91 ; [#uses=5] + %tmp106 = shl i64 %tmp103, 32 ; [#uses=1] + %tmp107 = and i64 %n0.2, 4294967295 ; [#uses=1] + %tmp108 = or i64 %tmp106, %tmp107 ; [#uses=3] + %tmp109 = icmp ult i64 %tmp108, %tmp105 ; [#uses=1] + br i1 %tmp109, label %bb79, label %bb83 + +bb79: ; preds = %bb78 + %tmp110 = add i64 %tmp108, %d0.2 ; [#uses=4] + %.not145 = icmp uge i64 %tmp110, %d0.2 ; [#uses=1] + %tmp111 = icmp ult i64 %tmp110, %tmp105 ; [#uses=1] + %or.cond146 = and i1 %tmp111, %.not145 ; [#uses=1] + br i1 %or.cond146, label %bb81, label %bb83 + +bb81: ; preds = %bb79 + %tmp112 = add i64 %tmp110, %d0.2 ; [#uses=1] + br label %bb83 + +bb83: ; preds = %bb81, %bb79, %bb78, %bb48, %bb46, %bb45 + %bm.0 = phi i64 [ %tmp16, %bb46 ], [ %tmp16, %bb48 ], [ %tmp16, %bb45 ], [ %tmp58, %bb79 ], [ %tmp58, %bb81 ], [ %tmp58, %bb78 ] ; [#uses=1] + %__r06.0.pn = phi i64 [ %tmp42, %bb45 ], [ %tmp44, %bb46 ], [ %tmp46, %bb48 ], [ %tmp108, %bb78 ], [ %tmp110, %bb79 ], [ %tmp112, %bb81 ] ; [#uses=1] + %.pn = phi i64 [ %tmp39, %bb46 ], [ %tmp39, %bb48 ], [ %tmp39, %bb45 ], [ %tmp105, %bb79 ], [ %tmp105, %bb81 ], [ %tmp105, %bb78 ] ; [#uses=1] + %tmp113 = icmp eq i128* %rp, null ; [#uses=1] + br i1 %tmp113, label %bb131, label %bb84 + +bb84: ; preds = %bb83 + %n0.1 = sub i64 %__r06.0.pn, %.pn ; [#uses=1] + %.cast85 = and i64 %bm.0, 4294967295 ; [#uses=1] + %tmp114 = lshr i64 %n0.1, %.cast85 ; [#uses=1] + %tmp115 = zext i64 %tmp114 to i128 ; [#uses=1] + store i128 %tmp115, i128* %rp, align 16 + br label %bb131 + +bb86: ; preds = %entry + %tmp116 = icmp ugt i64 %tmp4, %tmp2 ; [#uses=1] + br i1 %tmp116, label %bb87, label %bb93.thread + +bb93.thread: ; preds = %bb86 + br label %bb90 + +bb87: ; preds = %bb86 + %tmp117 = icmp eq i128* %rp, null ; [#uses=1] + br i1 %tmp117, label %bb131, label %bb88 + +bb88: ; preds = %bb87 + store i128 %n, i128* %rp, align 16 + br label %bb131 + +bb90: ; preds = %bb93, %bb93.thread + %__a.0.reg2mem.0 = phi i64 [ 56, %bb93.thread ], [ %tmp120, %bb93 ] ; [#uses=3] + %.cast91 = and i64 %__a.0.reg2mem.0, 4294967288 ; [#uses=1] + %tmp136 = shl i64 255, %.cast91 ; [#uses=1] + %tmp118 = and i64 %tmp4, %tmp136 ; [#uses=1] + %tmp119 = icmp eq i64 %tmp118, 0 ; [#uses=1] + br i1 %tmp119, label %bb93, label %bb94 + +bb93: ; preds = %bb90 + %tmp120 = add i64 %__a.0.reg2mem.0, -8 ; [#uses=3] + %tmp121 = icmp eq i64 %tmp120, 0 ; [#uses=1] + br i1 %tmp121, label %bb94, label %bb90 + +bb94: ; preds = %bb93, %bb90 + %__a.0.reg2mem.1 = phi i64 [ %__a.0.reg2mem.0, %bb90 ], [ %tmp120, %bb93 ] ; [#uses=2] + %.cast95 = and i64 %__a.0.reg2mem.1, 4294967288 ; [#uses=1] + %tmp122 = lshr i64 %tmp4, %.cast95 ; [#uses=1] + %tmp123 = getelementptr [256 x i8]* @__clz_tab, i64 0, i64 %tmp122 ; [#uses=1] + %tmp124 = load i8* %tmp123, align 1 ; [#uses=1] + %tmp125 = zext i8 %tmp124 to i64 ; [#uses=1] + %tmp126 = add i64 %tmp125, %__a.0.reg2mem.1 ; [#uses=2] + %tmp127 = sub i64 64, %tmp126 ; [#uses=7] + %tmp128 = icmp eq i64 %tmp126, 64 ; [#uses=1] + br i1 %tmp128, label %bb96, label %bb103 + +bb96: ; preds = %bb94 + %tmp129 = icmp ugt i64 %tmp2, %tmp4 ; [#uses=1] + %tmp130 = icmp uge i64 %tmp1, %tmp3 ; [#uses=1] + %tmp131 = or i1 %tmp129, %tmp130 ; [#uses=1] + br i1 %tmp131, label %bb99, label %bb101 + +bb99: ; preds = %bb96 + %tmp132 = sub i64 %tmp1, %tmp3 ; [#uses=2] + %tmp134 = sub i64 %tmp2, %tmp4 ; [#uses=1] + %tmp135 = icmp ugt i64 %tmp132, %tmp1 ; [#uses=1] + %tmp137 = zext i1 %tmp135 to i64 ; [#uses=1] + %tmp138 = sub i64 %tmp134, %tmp137 ; [#uses=1] + br label %bb101 + +bb101: ; preds = %bb99, %bb96 + %tmp139 = phi i64 [ %tmp138, %bb99 ], [ %tmp2, %bb96 ] ; [#uses=1] + %n0.3 = phi i64 [ %tmp132, %bb99 ], [ %tmp1, %bb96 ] ; [#uses=1] + %tmp140 = icmp eq i128* %rp, null ; [#uses=1] + br i1 %tmp140, label %bb131, label %bb102 + +bb102: ; preds = %bb101 + %tmp141 = zext i64 %n0.3 to i128 ; [#uses=1] + %tmp142 = zext i64 %tmp139 to i128 ; [#uses=1] + %tmp143 = shl i128 %tmp142, 64 ; [#uses=1] + %tmp144 = or i128 %tmp143, %tmp141 ; [#uses=1] + store i128 %tmp144, i128* %rp, align 16 + br label %bb131 + +bb103: ; preds = %bb94 + %tmp145 = sub i64 64, %tmp127 ; [#uses=4] + %.cast104 = and i64 %tmp127, 4294967295 ; [#uses=1] + %tmp146 = shl i64 %tmp4, %.cast104 ; [#uses=1] + %.cast105 = and i64 %tmp145, 4294967295 ; [#uses=1] + %tmp147 = lshr i64 %tmp3, %.cast105 ; [#uses=1] + %tmp148 = or i64 %tmp146, %tmp147 ; [#uses=9] + %.cast106 = and i64 %tmp127, 4294967295 ; [#uses=1] + %tmp149 = shl i64 %tmp3, %.cast106 ; [#uses=3] + %.cast107 = and i64 %tmp145, 4294967295 ; [#uses=1] + %tmp150 = lshr i64 %tmp2, %.cast107 ; [#uses=2] + %.cast108 = and i64 %tmp127, 4294967295 ; [#uses=1] + %tmp151 = shl i64 %tmp2, %.cast108 ; [#uses=1] + %.cast109 = and i64 %tmp145, 4294967295 ; [#uses=1] + %tmp152 = lshr i64 %tmp1, %.cast109 ; [#uses=1] + %tmp153 = or i64 %tmp151, %tmp152 ; [#uses=2] + %.cast110 = and i64 %tmp127, 4294967295 ; [#uses=1] + %tmp154 = shl i64 %tmp1, %.cast110 ; [#uses=3] + %tmp155 = lshr i64 %tmp148, 32 ; [#uses=4] + %tmp156 = and i64 %tmp148, 4294967295 ; [#uses=2] + %tmp157 = urem i64 %tmp150, %tmp155 ; [#uses=1] + %tmp158 = udiv i64 %tmp150, %tmp155 ; [#uses=4] + %tmp159 = mul i64 %tmp158, %tmp156 ; [#uses=3] + %tmp160 = shl i64 %tmp157, 32 ; [#uses=1] + %tmp161 = lshr i64 %tmp153, 32 ; [#uses=1] + %tmp162 = or i64 %tmp160, %tmp161 ; [#uses=3] + %tmp163 = icmp ult i64 %tmp162, %tmp159 ; [#uses=1] + br i1 %tmp163, label %bb111, label %bb114 + +bb111: ; preds = %bb103 + %tmp164 = add i64 %tmp158, -1 ; [#uses=1] + %tmp165 = add i64 %tmp162, %tmp148 ; [#uses=4] + %.not147 = icmp uge i64 %tmp165, %tmp148 ; [#uses=1] + %tmp166 = icmp ult i64 %tmp165, %tmp159 ; [#uses=1] + %or.cond148 = and i1 %tmp166, %.not147 ; [#uses=1] + br i1 %or.cond148, label %bb113, label %bb114 + +bb113: ; preds = %bb111 + %tmp167 = add i64 %tmp158, -2 ; [#uses=1] + %tmp168 = add i64 %tmp165, %tmp148 ; [#uses=1] + br label %bb114 + +bb114: ; preds = %bb113, %bb111, %bb103 + %__q1.0 = phi i64 [ %tmp158, %bb103 ], [ %tmp164, %bb111 ], [ %tmp167, %bb113 ] ; [#uses=1] + %__r1.0 = phi i64 [ %tmp162, %bb103 ], [ %tmp165, %bb111 ], [ %tmp168, %bb113 ] ; [#uses=1] + %tmp169 = sub i64 %__r1.0, %tmp159 ; [#uses=2] + %tmp170 = urem i64 %tmp169, %tmp155 ; [#uses=1] + %tmp171 = udiv i64 %tmp169, %tmp155 ; [#uses=4] + %tmp172 = mul i64 %tmp171, %tmp156 ; [#uses=3] + %tmp173 = shl i64 %tmp170, 32 ; [#uses=1] + %tmp174 = and i64 %tmp153, 4294967295 ; [#uses=1] + %tmp175 = or i64 %tmp173, %tmp174 ; [#uses=3] + %tmp176 = icmp ult i64 %tmp175, %tmp172 ; [#uses=1] + br i1 %tmp176, label %bb115, label %bb118 + +bb115: ; preds = %bb114 + %tmp177 = add i64 %tmp171, -1 ; [#uses=1] + %tmp178 = add i64 %tmp175, %tmp148 ; [#uses=4] + %.not149 = icmp uge i64 %tmp178, %tmp148 ; [#uses=1] + %tmp179 = icmp ult i64 %tmp178, %tmp172 ; [#uses=1] + %or.cond150 = and i1 %tmp179, %.not149 ; [#uses=1] + br i1 %or.cond150, label %bb117, label %bb118 + +bb117: ; preds = %bb115 + %tmp180 = add i64 %tmp171, -2 ; [#uses=1] + %tmp181 = add i64 %tmp178, %tmp148 ; [#uses=1] + br label %bb118 + +bb118: ; preds = %bb117, %bb115, %bb114 + %__q0.0 = phi i64 [ %tmp171, %bb114 ], [ %tmp177, %bb115 ], [ %tmp180, %bb117 ] ; [#uses=2] + %__r0.0 = phi i64 [ %tmp175, %bb114 ], [ %tmp178, %bb115 ], [ %tmp181, %bb117 ] ; [#uses=1] + %tmp182 = sub i64 %__r0.0, %tmp172 ; [#uses=3] + %tmp183 = shl i64 %__q1.0, 32 ; [#uses=1] + %tmp184 = or i64 %tmp183, %__q0.0 ; [#uses=1] + %tmp185 = and i64 %__q0.0, 4294967295 ; [#uses=2] + %tmp186 = lshr i64 %tmp184, 32 ; [#uses=2] + %tmp187 = and i64 %tmp149, 4294967295 ; [#uses=2] + %tmp188 = lshr i64 %tmp149, 32 ; [#uses=2] + %tmp189 = mul i64 %tmp185, %tmp187 ; [#uses=2] + %tmp190 = mul i64 %tmp185, %tmp188 ; [#uses=1] + %tmp191 = mul i64 %tmp186, %tmp187 ; [#uses=2] + %tmp192 = mul i64 %tmp186, %tmp188 ; [#uses=1] + %tmp193 = lshr i64 %tmp189, 32 ; [#uses=1] + %tmp194 = add i64 %tmp193, %tmp190 ; [#uses=1] + %tmp195 = add i64 %tmp194, %tmp191 ; [#uses=3] + %tmp196 = icmp ult i64 %tmp195, %tmp191 ; [#uses=1] + %tmp197 = select i1 %tmp196, i64 4294967296, i64 0 ; [#uses=1] + %__x3.0 = add i64 %tmp192, %tmp197 ; [#uses=1] + %tmp198 = lshr i64 %tmp195, 32 ; [#uses=1] + %tmp199 = add i64 %tmp198, %__x3.0 ; [#uses=4] + %tmp200 = shl i64 %tmp195, 32 ; [#uses=1] + %tmp201 = and i64 %tmp189, 4294967295 ; [#uses=1] + %tmp202 = or i64 %tmp200, %tmp201 ; [#uses=4] + %tmp203 = icmp ugt i64 %tmp199, %tmp182 ; [#uses=1] + br i1 %tmp203, label %bb125, label %bb121 + +bb121: ; preds = %bb118 + %tmp204 = icmp eq i64 %tmp199, %tmp182 ; [#uses=1] + %tmp205 = icmp ugt i64 %tmp202, %tmp154 ; [#uses=1] + %tmp206 = and i1 %tmp204, %tmp205 ; [#uses=1] + br i1 %tmp206, label %bb125, label %bb126 + +bb125: ; preds = %bb121, %bb118 + %tmp207 = sub i64 %tmp202, %tmp149 ; [#uses=2] + %tmp208 = sub i64 %tmp199, %tmp148 ; [#uses=1] + %tmp209 = icmp ugt i64 %tmp207, %tmp202 ; [#uses=1] + %tmp210 = zext i1 %tmp209 to i64 ; [#uses=1] + %tmp211 = sub i64 %tmp208, %tmp210 ; [#uses=1] + br label %bb126 + +bb126: ; preds = %bb125, %bb121 + %m1.0 = phi i64 [ %tmp199, %bb121 ], [ %tmp211, %bb125 ] ; [#uses=1] + %m0.0 = phi i64 [ %tmp202, %bb121 ], [ %tmp207, %bb125 ] ; [#uses=1] + %tmp212 = icmp eq i128* %rp, null ; [#uses=1] + br i1 %tmp212, label %bb131, label %bb127 + +bb127: ; preds = %bb126 + %tmp213 = sub i64 %tmp154, %m0.0 ; [#uses=2] + %tmp214 = sub i64 %tmp182, %m1.0 ; [#uses=1] + %tmp215 = icmp ugt i64 %tmp213, %tmp154 ; [#uses=1] + %tmp216 = zext i1 %tmp215 to i64 ; [#uses=1] + %tmp217 = sub i64 %tmp214, %tmp216 ; [#uses=2] + %.cast128 = and i64 %tmp145, 4294967295 ; [#uses=1] + %tmp218 = shl i64 %tmp217, %.cast128 ; [#uses=1] + %.cast129 = and i64 %tmp127, 4294967295 ; [#uses=1] + %tmp219 = lshr i64 %tmp213, %.cast129 ; [#uses=1] + %tmp220 = or i64 %tmp218, %tmp219 ; [#uses=1] + %.cast130 = and i64 %tmp127, 4294967295 ; [#uses=1] + %tmp221 = lshr i64 %tmp217, %.cast130 ; [#uses=1] + %tmp222 = zext i64 %tmp220 to i128 ; [#uses=1] + %tmp223 = zext i64 %tmp221 to i128 ; [#uses=1] + %tmp224 = shl i128 %tmp223, 64 ; [#uses=1] + %tmp225 = or i128 %tmp224, %tmp222 ; [#uses=1] + store i128 %tmp225, i128* %rp, align 16 + br label %bb131 + +bb131: ; preds = %bb127, %bb126, %bb102, %bb101, %bb88, %bb87, %bb84, %bb83 + ret void +} Modified: llvm/trunk/test/Transforms/InstCombine/cast-sext-zext.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/cast-sext-zext.ll?rev=63483&r1=63482&r2=63483&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/cast-sext-zext.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/cast-sext-zext.ll Sat Jan 31 13:05:27 2009 @@ -1,4 +1,5 @@ ; RUN: llvm-as < %s | opt -instcombine | llvm-dis | not grep sext +; XFAIL: * define zeroext i16 @t(i8 zeroext %on_off, i16* nocapture %puls) nounwind readonly { entry: From dalej at apple.com Sat Jan 31 14:01:02 2009 From: dalej at apple.com (Dale Johannesen) Date: Sat, 31 Jan 2009 20:01:02 -0000 Subject: [llvm-commits] [llvm] r63485 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Message-ID: <200901312001.n0VK12nC006854@zion.cs.uiuc.edu> Author: johannes Date: Sat Jan 31 14:01:02 2009 New Revision: 63485 URL: http://llvm.org/viewvc/llvm-project?rev=63485&view=rev Log: DebugLoc propagation. Done with file. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=63485&r1=63484&r2=63485&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Sat Jan 31 14:01:02 2009 @@ -852,18 +852,20 @@ /// BitConvertToInteger - Convert to an integer of the same size. SDValue DAGTypeLegalizer::BitConvertToInteger(SDValue Op) { unsigned BitWidth = Op.getValueType().getSizeInBits(); - return DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerVT(BitWidth), Op); + return DAG.getNode(ISD::BIT_CONVERT, Op.getNode()->getDebugLoc(), + MVT::getIntegerVT(BitWidth), Op); } SDValue DAGTypeLegalizer::CreateStackStoreLoad(SDValue Op, MVT DestVT) { + DebugLoc dl = Op.getNode()->getDebugLoc(); // Create the stack frame object. Make sure it is aligned for both // the source and destination types. SDValue StackPtr = DAG.CreateStackTemporary(Op.getValueType(), DestVT); // Emit a store to the stack slot. - SDValue Store = DAG.getStore(DAG.getEntryNode(), Op, StackPtr, NULL, 0); + SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op, StackPtr, NULL, 0); // Result is a load from the stack slot. - return DAG.getLoad(DestVT, Store, StackPtr, NULL, 0); + return DAG.getLoad(DestVT, dl, Store, StackPtr, NULL, 0); } /// CustomLowerResults - Replace the node's results with custom code provided @@ -920,31 +922,35 @@ SDValue DAGTypeLegalizer::GetVectorElementPointer(SDValue VecPtr, MVT EltVT, SDValue Index) { + DebugLoc dl = Index.getNode()->getDebugLoc(); // Make sure the index type is big enough to compute in. if (Index.getValueType().bitsGT(TLI.getPointerTy())) - Index = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Index); + Index = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Index); else - Index = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Index); + Index = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Index); // Calculate the element offset and add it to the pointer. unsigned EltSize = EltVT.getSizeInBits() / 8; // FIXME: should be ABI size. - Index = DAG.getNode(ISD::MUL, Index.getValueType(), Index, + Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index, DAG.getConstant(EltSize, Index.getValueType())); - return DAG.getNode(ISD::ADD, Index.getValueType(), Index, VecPtr); + return DAG.getNode(ISD::ADD, dl, Index.getValueType(), Index, VecPtr); } /// JoinIntegers - Build an integer with low bits Lo and high bits Hi. SDValue DAGTypeLegalizer::JoinIntegers(SDValue Lo, SDValue Hi) { + // Arbitrarily use dlHi for result DebugLoc + DebugLoc dlHi = Hi.getNode()->getDebugLoc(); + DebugLoc dlLo = Lo.getNode()->getDebugLoc(); MVT LVT = Lo.getValueType(); MVT HVT = Hi.getValueType(); MVT NVT = MVT::getIntegerVT(LVT.getSizeInBits() + HVT.getSizeInBits()); - Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Lo); - Hi = DAG.getNode(ISD::ANY_EXTEND, NVT, Hi); - Hi = DAG.getNode(ISD::SHL, NVT, Hi, + Lo = DAG.getNode(ISD::ZERO_EXTEND, dlLo, NVT, Lo); + Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi); + Hi = DAG.getNode(ISD::SHL, dlHi, NVT, Hi, DAG.getConstant(LVT.getSizeInBits(), TLI.getPointerTy())); - return DAG.getNode(ISD::OR, NVT, Lo, Hi); + return DAG.getNode(ISD::OR, dlHi, NVT, Lo, Hi); } /// LibCallify - Convert the node into a libcall with the same prototype. @@ -998,6 +1004,7 @@ /// of the given type. A target boolean is an integer value, not necessarily of /// type i1, the bits of which conform to getBooleanContents. SDValue DAGTypeLegalizer::PromoteTargetBoolean(SDValue Bool, MVT VT) { + DebugLoc dl = Bool.getNode()->getDebugLoc(); ISD::NodeType ExtendCode; switch (TLI.getBooleanContents()) { default: @@ -1016,7 +1023,7 @@ break; } } - return DAG.getNode(ExtendCode, VT, Bool); + return DAG.getNode(ExtendCode, dl, VT, Bool); } /// SplitInteger - Return the lower LoVT bits of Op in Lo and the upper HiVT @@ -1024,12 +1031,13 @@ void DAGTypeLegalizer::SplitInteger(SDValue Op, MVT LoVT, MVT HiVT, SDValue &Lo, SDValue &Hi) { + DebugLoc dl = Op.getNode()->getDebugLoc(); assert(LoVT.getSizeInBits() + HiVT.getSizeInBits() == Op.getValueType().getSizeInBits() && "Invalid integer splitting!"); - Lo = DAG.getNode(ISD::TRUNCATE, LoVT, Op); - Hi = DAG.getNode(ISD::SRL, Op.getValueType(), Op, + Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Op); + Hi = DAG.getNode(ISD::SRL, dl, Op.getValueType(), Op, DAG.getConstant(LoVT.getSizeInBits(), TLI.getPointerTy())); - Hi = DAG.getNode(ISD::TRUNCATE, HiVT, Hi); + Hi = DAG.getNode(ISD::TRUNCATE, dl, HiVT, Hi); } /// SplitInteger - Return the lower and upper halves of Op's bits in a value From baldrick at free.fr Sat Jan 31 14:25:13 2009 From: baldrick at free.fr (Duncan Sands) Date: Sat, 31 Jan 2009 21:25:13 +0100 Subject: [llvm-commits] =?iso-8859-1?q?=5Bllvm=5D_r63482_-_in_/llvm/trunk?= =?iso-8859-1?q?=3A=09include/llvm/CodeGen/_lib/CodeGen/SelectionDAG/_test?= =?iso-8859-1?q?/CodeGen/X86/?= In-Reply-To: <1233428460.5926.12.camel@idc-lt-i00171.microchip.com> References: <200901311550.n0VFoEW5029548@zion.cs.uiuc.edu> <1233428460.5926.12.camel@idc-lt-i00171.microchip.com> Message-ID: <200901312125.14525.baldrick@free.fr> Hi Sanjiv, > For PIC16 getPointerTy returns i16 which is illegal. try the attached patch. Ciao, Duncan. -------------- next part -------------- A non-text attachment was scrubbed... Name: pr3401.diff Type: text/x-patch Size: 3375 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090131/e9c3fa81/attachment.bin From dalej at apple.com Sat Jan 31 15:04:25 2009 From: dalej at apple.com (Dale Johannesen) Date: Sat, 31 Jan 2009 21:04:25 -0000 Subject: [llvm-commits] [llvm] r63486 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Message-ID: <200901312104.n0VL4P4x008990@zion.cs.uiuc.edu> Author: johannes Date: Sat Jan 31 15:04:24 2009 New Revision: 63486 URL: http://llvm.org/viewvc/llvm-project?rev=63486&view=rev Log: DebugLoc propagation. Done with file. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=63486&r1=63485&r2=63486&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Sat Jan 31 15:04:24 2009 @@ -36,6 +36,7 @@ MVT NOutVT = TLI.getTypeToTransformTo(OutVT); SDValue InOp = N->getOperand(0); MVT InVT = InOp.getValueType(); + DebugLoc dl = N->getDebugLoc(); // Handle some special cases efficiently. switch (getTypeAction(InVT)) { @@ -47,15 +48,15 @@ case SoftenFloat: // Convert the integer operand instead. SplitInteger(GetSoftenedFloat(InOp), Lo, Hi); - Lo = DAG.getNode(ISD::BIT_CONVERT, NOutVT, Lo); - Hi = DAG.getNode(ISD::BIT_CONVERT, NOutVT, Hi); + Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, Lo); + Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, Hi); return; case ExpandInteger: case ExpandFloat: // Convert the expanded pieces of the input. GetExpandedOp(InOp, Lo, Hi); - Lo = DAG.getNode(ISD::BIT_CONVERT, NOutVT, Lo); - Hi = DAG.getNode(ISD::BIT_CONVERT, NOutVT, Hi); + Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, Lo); + Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, Hi); return; case SplitVector: // Convert the split parts of the input if it was split in two. @@ -63,16 +64,16 @@ if (Lo.getValueType() == Hi.getValueType()) { if (TLI.isBigEndian()) std::swap(Lo, Hi); - Lo = DAG.getNode(ISD::BIT_CONVERT, NOutVT, Lo); - Hi = DAG.getNode(ISD::BIT_CONVERT, NOutVT, Hi); + Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, Lo); + Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, Hi); return; } break; case ScalarizeVector: // Convert the element instead. SplitInteger(BitConvertToInteger(GetScalarizedVector(InOp)), Lo, Hi); - Lo = DAG.getNode(ISD::BIT_CONVERT, NOutVT, Lo); - Hi = DAG.getNode(ISD::BIT_CONVERT, NOutVT, Hi); + Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, Lo); + Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, Hi); return; } @@ -88,18 +89,18 @@ const Value *SV = PseudoSourceValue::getFixedStack(SPFI); // Emit a store to the stack slot. - SDValue Store = DAG.getStore(DAG.getEntryNode(), InOp, StackPtr, SV, 0); + SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, StackPtr, SV, 0); // Load the first half from the stack slot. - Lo = DAG.getLoad(NOutVT, Store, StackPtr, SV, 0); + Lo = DAG.getLoad(NOutVT, dl, Store, StackPtr, SV, 0); // Increment the pointer to the other half. unsigned IncrementSize = NOutVT.getSizeInBits() / 8; - StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr, + StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, DAG.getIntPtrConstant(IncrementSize)); // Load the second half from the stack slot. - Hi = DAG.getLoad(NOutVT, Store, StackPtr, SV, IncrementSize, false, + Hi = DAG.getLoad(NOutVT, dl, Store, StackPtr, SV, IncrementSize, false, MinAlign(Alignment, IncrementSize)); // Handle endianness of the load. @@ -119,14 +120,15 @@ GetExpandedOp(N->getOperand(0), Lo, Hi); SDValue Part = cast(N->getOperand(1))->getZExtValue() ? Hi : Lo; + DebugLoc dl = N->getDebugLoc(); assert(Part.getValueType() == N->getValueType(0) && "Type twice as big as expanded type not itself expanded!"); MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); - Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Part, + Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Part, DAG.getConstant(0, TLI.getPointerTy())); - Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Part, + Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Part, DAG.getConstant(1, TLI.getPointerTy())); } @@ -134,13 +136,14 @@ SDValue &Hi) { SDValue OldVec = N->getOperand(0); unsigned OldElts = OldVec.getValueType().getVectorNumElements(); + DebugLoc dl = N->getDebugLoc(); // Convert to a vector of the expanded element type, for example // <3 x i64> -> <6 x i32>. MVT OldVT = N->getValueType(0); MVT NewVT = TLI.getTypeToTransformTo(OldVT); - SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, + SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::getVectorVT(NewVT, 2*OldElts), OldVec); @@ -149,14 +152,14 @@ // Make sure the type of Idx is big enough to hold the new values. if (Idx.getValueType().bitsLT(TLI.getPointerTy())) - Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); + Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); Idx = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, Idx); - Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, Idx); + Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); - Idx = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, + Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, DAG.getConstant(1, Idx.getValueType())); - Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, Idx); + Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); if (TLI.isBigEndian()) std::swap(Lo, Hi); @@ -165,6 +168,7 @@ void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo, SDValue &Hi) { assert(ISD::isNormalLoad(N) && "This routine only for normal loads!"); + DebugLoc dl = N->getDebugLoc(); LoadSDNode *LD = cast(N); MVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0)); @@ -176,19 +180,20 @@ assert(NVT.isByteSized() && "Expanded type not byte sized!"); - Lo = DAG.getLoad(NVT, Chain, Ptr, LD->getSrcValue(), SVOffset, + Lo = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getSrcValue(), SVOffset, isVolatile, Alignment); // Increment the pointer to the other half. unsigned IncrementSize = NVT.getSizeInBits() / 8; - Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, + Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); - Hi = DAG.getLoad(NVT, Chain, Ptr, LD->getSrcValue(), SVOffset+IncrementSize, + Hi = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getSrcValue(), + SVOffset+IncrementSize, isVolatile, MinAlign(Alignment, IncrementSize)); // Build a factor node to remember that this load is independent of the // other one. - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), Hi.getValue(1)); // Handle endianness of the load. @@ -223,6 +228,7 @@ //===--------------------------------------------------------------------===// SDValue DAGTypeLegalizer::ExpandOp_BIT_CONVERT(SDNode *N) { + DebugLoc dl = N->getDebugLoc(); if (N->getValueType(0).isVector()) { // An illegal expanding type is being converted to a legal vector type. // Make a two element vector out of the expanded parts and convert that @@ -239,8 +245,8 @@ if (TLI.isBigEndian()) std::swap(Parts[0], Parts[1]); - SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, NVT, Parts, 2); - return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Vec); + SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Parts, 2); + return DAG.getNode(ISD::BIT_CONVERT, dl, N->getValueType(0), Vec); } } @@ -254,6 +260,7 @@ unsigned NumElts = VecVT.getVectorNumElements(); MVT OldVT = N->getOperand(0).getValueType(); MVT NewVT = TLI.getTypeToTransformTo(OldVT); + DebugLoc dl = N->getDebugLoc(); // Build a vector of twice the length out of the expanded elements. // For example <3 x i64> -> <6 x i32>. @@ -269,12 +276,12 @@ NewElts.push_back(Hi); } - SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, + SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::getVectorVT(NewVT, NewElts.size()), &NewElts[0], NewElts.size()); // Convert the new vector to the old vector type. - return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec); + return DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, NewVec); } SDValue DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(SDNode *N) { @@ -287,6 +294,7 @@ // The vector type is legal but the element type needs expansion. MVT VecVT = N->getValueType(0); unsigned NumElts = VecVT.getVectorNumElements(); + DebugLoc dl = N->getDebugLoc(); SDValue Val = N->getOperand(1); MVT OldEVT = Val.getValueType(); @@ -298,7 +306,8 @@ // Bitconvert to a vector of twice the length with elements of the expanded // type, insert the expanded vector elements, and then convert back. MVT NewVecVT = MVT::getVectorVT(NewEVT, NumElts*2); - SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, NewVecVT, N->getOperand(0)); + SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl, + NewVecVT, N->getOperand(0)); SDValue Lo, Hi; GetExpandedOp(Val, Lo, Hi); @@ -306,29 +315,32 @@ std::swap(Lo, Hi); SDValue Idx = N->getOperand(2); - Idx = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, Idx); - NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVecVT, NewVec, Lo, Idx); - Idx = DAG.getNode(ISD::ADD,Idx.getValueType(), Idx, DAG.getIntPtrConstant(1)); - NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVecVT, NewVec, Hi, Idx); + Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, Idx); + NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx); + Idx = DAG.getNode(ISD::ADD, dl, + Idx.getValueType(), Idx, DAG.getIntPtrConstant(1)); + NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx); // Convert the new vector to the old vector type. - return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec); + return DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, NewVec); } SDValue DAGTypeLegalizer::ExpandOp_SCALAR_TO_VECTOR(SDNode *N) { + DebugLoc dl = N->getDebugLoc(); MVT VT = N->getValueType(0); unsigned NumElts = VT.getVectorNumElements(); SmallVector Ops(NumElts); Ops[0] = N->getOperand(0); - SDValue UndefVal = DAG.getNode(ISD::UNDEF, Ops[0].getValueType()); + SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, Ops[0].getValueType()); for (unsigned i = 1; i < NumElts; ++i) Ops[i] = UndefVal; - return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], NumElts); + return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); } SDValue DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) { assert(ISD::isNormalStore(N) && "This routine only for normal stores!"); assert(OpNo == 1 && "Can only expand the stored value so far"); + DebugLoc dl = N->getDebugLoc(); StoreSDNode *St = cast(N); MVT NVT = TLI.getTypeToTransformTo(St->getValue().getValueType()); @@ -347,16 +359,17 @@ if (TLI.isBigEndian()) std::swap(Lo, Hi); - Lo = DAG.getStore(Chain, Lo, Ptr, St->getSrcValue(), SVOffset, + Lo = DAG.getStore(Chain, dl, Lo, Ptr, St->getSrcValue(), SVOffset, isVolatile, Alignment); - Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, + Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); assert(isTypeLegal(Ptr.getValueType()) && "Pointers must be legal!"); - Hi = DAG.getStore(Chain, Hi, Ptr, St->getSrcValue(), SVOffset + IncrementSize, + Hi = DAG.getStore(Chain, dl, Hi, Ptr, St->getSrcValue(), + SVOffset + IncrementSize, isVolatile, MinAlign(Alignment, IncrementSize)); - return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); } @@ -393,29 +406,32 @@ void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDValue &Lo, SDValue &Hi) { SDValue LL, LH, RL, RH; + DebugLoc dl = N->getDebugLoc(); GetSplitOp(N->getOperand(1), LL, LH); GetSplitOp(N->getOperand(2), RL, RH); SDValue Cond = N->getOperand(0); - Lo = DAG.getNode(ISD::SELECT, LL.getValueType(), Cond, LL, RL); - Hi = DAG.getNode(ISD::SELECT, LH.getValueType(), Cond, LH, RH); + Lo = DAG.getNode(ISD::SELECT, dl, LL.getValueType(), Cond, LL, RL); + Hi = DAG.getNode(ISD::SELECT, dl, LH.getValueType(), Cond, LH, RH); } void DAGTypeLegalizer::SplitRes_SELECT_CC(SDNode *N, SDValue &Lo, SDValue &Hi) { SDValue LL, LH, RL, RH; + DebugLoc dl = N->getDebugLoc(); GetSplitOp(N->getOperand(2), LL, LH); GetSplitOp(N->getOperand(3), RL, RH); - Lo = DAG.getNode(ISD::SELECT_CC, LL.getValueType(), N->getOperand(0), + Lo = DAG.getNode(ISD::SELECT_CC, dl, LL.getValueType(), N->getOperand(0), N->getOperand(1), LL, RL, N->getOperand(4)); - Hi = DAG.getNode(ISD::SELECT_CC, LH.getValueType(), N->getOperand(0), + Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0), N->getOperand(1), LH, RH, N->getOperand(4)); } void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi) { MVT LoVT, HiVT; + DebugLoc dl = N->getDebugLoc(); GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); - Lo = DAG.getNode(ISD::UNDEF, LoVT); - Hi = DAG.getNode(ISD::UNDEF, HiVT); + Lo = DAG.getNode(ISD::UNDEF, dl, LoVT); + Hi = DAG.getNode(ISD::UNDEF, dl, HiVT); } From nicholas at mxc.ca Sat Jan 31 15:30:05 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Sat, 31 Jan 2009 21:30:05 -0000 Subject: [llvm-commits] [llvm] r63487 - in /llvm/trunk: lib/Transforms/Scalar/InstructionCombining.cpp test/Transforms/InstCombine/2008-08-17-ICmpXorSignbit.ll test/Transforms/InstCombine/2009-01-31-Pressure.ll Message-ID: <200901312130.n0VLU5MH009895@zion.cs.uiuc.edu> Author: nicholas Date: Sat Jan 31 15:30:05 2009 New Revision: 63487 URL: http://llvm.org/viewvc/llvm-project?rev=63487&view=rev Log: Reinstate this optimization to fold icmp of xor when possible. Don't try to turn icmp eq a+x, b+x into icmp eq a, b if a+x or b+x has other uses. This may have been increasing register pressure leading to the bzip2 slowdown. Added: llvm/trunk/test/Transforms/InstCombine/2009-01-31-Pressure.ll Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp llvm/trunk/test/Transforms/InstCombine/2008-08-17-ICmpXorSignbit.ll Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=63487&r1=63486&r2=63487&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Sat Jan 31 15:30:05 2009 @@ -6095,18 +6095,40 @@ if (BinaryOperator *Op0I = dyn_cast(Op0)) { if (BinaryOperator *Op1I = dyn_cast(Op1)) { if (Op0I->getOpcode() == Op1I->getOpcode() && Op0I->hasOneUse() && - Op1I->hasOneUse() && Op0I->getOperand(1) == Op1I->getOperand(1) && - I.isEquality()) { + Op1I->hasOneUse() && Op0I->getOperand(1) == Op1I->getOperand(1)) { switch (Op0I->getOpcode()) { default: break; case Instruction::Add: case Instruction::Sub: case Instruction::Xor: - // a+x icmp eq/ne b+x --> a icmp b - return new ICmpInst(I.getPredicate(), Op0I->getOperand(0), - Op1I->getOperand(0)); + if (I.isEquality()) { + // a+x icmp eq/ne b+x --> a icmp b + return new ICmpInst(I.getPredicate(), Op0I->getOperand(0), + Op1I->getOperand(0)); + } else { + // icmp u/s (a ^ signbit), (b ^ signbit) --> icmp s/u a, b + if (ConstantInt *CI = dyn_cast(Op0I->getOperand(1))) { + if (CI->getValue().isSignBit()) { + ICmpInst::Predicate Pred = I.isSignedPredicate() + ? I.getUnsignedPredicate() + : I.getSignedPredicate(); + return new ICmpInst(Pred, Op0I->getOperand(0), + Op1I->getOperand(0)); + } else if ((~CI->getValue()).isSignBit()) { + ICmpInst::Predicate Pred = I.isSignedPredicate() + ? I.getUnsignedPredicate() + : I.getSignedPredicate(); + Pred = I.getSwappedPredicate(Pred); + return new ICmpInst(Pred, Op0I->getOperand(0), + Op1I->getOperand(0)); + } + } + } break; case Instruction::Mul: + if (!I.isEquality()) + break; + if (ConstantInt *CI = dyn_cast(Op0I->getOperand(1))) { // a * Cst icmp eq/ne b * Cst --> a & Mask icmp b & Mask // Mask = -1 >> count-trailing-zeros(Cst). @@ -6425,6 +6447,29 @@ else return new ICmpInst(ICmpInst::ICMP_SLT, CompareVal, AddOne(RHS)); } + + if (LHSI->hasOneUse()) { + // (icmp u/s (xor A SignBit), C) -> (icmp s/u A, (xor C SignBit)) + if (!ICI.isEquality() && XorCST->getValue().isSignBit()) { + const APInt &SignBit = XorCST->getValue(); + ICmpInst::Predicate Pred = ICI.isSignedPredicate() + ? ICI.getUnsignedPredicate() + : ICI.getSignedPredicate(); + return new ICmpInst(Pred, LHSI->getOperand(0), + ConstantInt::get(RHSV ^ SignBit)); + } + + // (icmp u/s (xor A ~SignBit), C) -> (icmp s/u (xor C ~SignBit), A) + if (!ICI.isEquality() && (~XorCST->getValue()).isSignBit()) { + const APInt &NotSignBit = XorCST->getValue(); + ICmpInst::Predicate Pred = ICI.isSignedPredicate() + ? ICI.getUnsignedPredicate() + : ICI.getSignedPredicate(); + Pred = ICI.getSwappedPredicate(Pred); + return new ICmpInst(Pred, LHSI->getOperand(0), + ConstantInt::get(RHSV ^ NotSignBit)); + } + } } break; case Instruction::And: // (icmp pred (and X, AndCST), RHS) Modified: llvm/trunk/test/Transforms/InstCombine/2008-08-17-ICmpXorSignbit.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2008-08-17-ICmpXorSignbit.ll?rev=63487&r1=63486&r2=63487&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/2008-08-17-ICmpXorSignbit.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/2008-08-17-ICmpXorSignbit.ll Sat Jan 31 15:30:05 2009 @@ -1,5 +1,4 @@ ; RUN: llvm-as < %s | opt -instcombine | llvm-dis | not grep xor -; XFAIL: * define i1 @test1(i8 %x, i8 %y) { %X = xor i8 %x, 128 Added: llvm/trunk/test/Transforms/InstCombine/2009-01-31-Pressure.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2009-01-31-Pressure.ll?rev=63487&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/2009-01-31-Pressure.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/2009-01-31-Pressure.ll Sat Jan 31 15:30:05 2009 @@ -0,0 +1,22 @@ +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep {%B = add i8 %b, %x} +; PR2698 + +declare void @use1(i1) +declare void @use8(i8) + +define void @test1(i8 %a, i8 %b, i8 %x) { + %A = add i8 %a, %x + %B = add i8 %b, %x + %C = icmp eq i8 %A, %B + call void @use1(i1 %C) + ret void +} + +define void @test2(i8 %a, i8 %b, i8 %x) { + %A = add i8 %a, %x + %B = add i8 %b, %x + %C = icmp eq i8 %A, %B + call void @use1(i1 %C) + call void @use8(i8 %A) + ret void +} From dalej at apple.com Sat Jan 31 16:04:51 2009 From: dalej at apple.com (Dale Johannesen) Date: Sat, 31 Jan 2009 22:04:51 -0000 Subject: [llvm-commits] [llvm] r63488 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeTypes.h LegalizeVectorTypes.cpp Message-ID: <200901312204.n0VM4pep011196@zion.cs.uiuc.edu> Author: johannes Date: Sat Jan 31 16:04:51 2009 New Revision: 63488 URL: http://llvm.org/viewvc/llvm-project?rev=63488&view=rev Log: DebugLoc propagation. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=63488&r1=63487&r2=63488&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Sat Jan 31 16:04:51 2009 @@ -631,11 +631,12 @@ /// isVolatile: volatile load. /// LdWidth: width of memory that we want to load. /// ResType: the wider result result type for the resulting vector. + /// dl: DebugLoc to be applied to new nodes SDValue GenWidenVectorLoads(SmallVector& LdChain, SDValue Chain, SDValue BasePtr, const Value *SV, int SVOffset, unsigned Alignment, bool isVolatile, unsigned LdWidth, - MVT ResType); + MVT ResType, DebugLoc dl); /// Helper genWidenVectorStores - Helper function to generate a set of /// stores to store a widen vector into non widen memory @@ -649,11 +650,12 @@ /// isVolatile: volatile lod /// ValOp: value to store /// StWidth: width of memory that we want to store + /// dl: DebugLoc to be applied to new nodes void GenWidenVectorStores(SmallVector& StChain, SDValue Chain, SDValue BasePtr, const Value *SV, int SVOffset, unsigned Alignment, bool isVolatile, SDValue ValOp, - unsigned StWidth); + unsigned StWidth, DebugLoc dl); /// Modifies a vector input (widen or narrows) to a vector of NVT. The /// input vector must have the same element type as NVT. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=63488&r1=63487&r2=63488&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Sat Jan 31 16:04:51 2009 @@ -105,18 +105,21 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) { SDValue LHS = GetScalarizedVector(N->getOperand(0)); SDValue RHS = GetScalarizedVector(N->getOperand(1)); - return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); + return DAG.getNode(N->getOpcode(), N->getDebugLoc(), + LHS.getValueType(), LHS, RHS); } SDValue DAGTypeLegalizer::ScalarizeVecRes_ShiftOp(SDNode *N) { SDValue LHS = GetScalarizedVector(N->getOperand(0)); SDValue ShiftAmt = GetScalarizedVector(N->getOperand(1)); - return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, ShiftAmt); + return DAG.getNode(N->getOpcode(), N->getDebugLoc(), + LHS.getValueType(), LHS, ShiftAmt); } SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) { MVT NewVT = N->getValueType(0).getVectorElementType(); - return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0)); + return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), + NewVT, N->getOperand(0)); } SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) { @@ -130,14 +133,15 @@ } SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) { - return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), N->getValueType(0).getVectorElementType(), N->getOperand(0), N->getOperand(1)); } SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) { SDValue Op = GetScalarizedVector(N->getOperand(0)); - return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1)); + return DAG.getNode(ISD::FPOWI, N->getDebugLoc(), + Op.getValueType(), Op, N->getOperand(1)); } SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) { @@ -147,17 +151,18 @@ MVT EltVT = N->getValueType(0).getVectorElementType(); if (Op.getValueType() != EltVT) // FIXME: Can this happen for floating point types? - Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op); + Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op); return Op; } SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) { assert(N->isUnindexed() && "Indexed vector load?"); - SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getExtensionType(), + SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getDebugLoc(), + N->getExtensionType(), N->getValueType(0).getVectorElementType(), N->getChain(), N->getBasePtr(), - DAG.getNode(ISD::UNDEF, + DAG.getNode(ISD::UNDEF, N->getDebugLoc(), N->getBasePtr().getValueType()), N->getSrcValue(), N->getSrcValueOffset(), N->getMemoryVT().getVectorElementType(), @@ -173,7 +178,7 @@ // Get the dest type - it doesn't always match the input type, e.g. int_to_fp. MVT DestVT = N->getValueType(0).getVectorElementType(); SDValue Op = GetScalarizedVector(N->getOperand(0)); - return DAG.getNode(N->getOpcode(), DestVT, Op); + return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op); } SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) { @@ -182,27 +187,30 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) { SDValue LHS = GetScalarizedVector(N->getOperand(1)); - return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0), LHS, + return DAG.getNode(ISD::SELECT, N->getDebugLoc(), + LHS.getValueType(), N->getOperand(0), LHS, GetScalarizedVector(N->getOperand(2))); } SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) { SDValue LHS = GetScalarizedVector(N->getOperand(2)); - return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), + return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(), N->getOperand(0), N->getOperand(1), LHS, GetScalarizedVector(N->getOperand(3)), N->getOperand(4)); } SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) { - return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType()); + return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), + N->getValueType(0).getVectorElementType()); } SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) { // Figure out if the scalar is the LHS or RHS and return it. SDValue Arg = N->getOperand(2).getOperand(0); if (Arg.getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType()); + return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), + N->getValueType(0).getVectorElementType()); unsigned Op = !cast(Arg)->isNullValue(); return GetScalarizedVector(N->getOperand(Op)); } @@ -212,9 +220,10 @@ SDValue RHS = GetScalarizedVector(N->getOperand(1)); MVT NVT = N->getValueType(0).getVectorElementType(); MVT SVT = TLI.getSetCCResultType(LHS.getValueType()); + DebugLoc dl = N->getDebugLoc(); // Turn it into a scalar SETCC. - SDValue Res = DAG.getNode(ISD::SETCC, SVT, LHS, RHS, N->getOperand(2)); + SDValue Res = DAG.getNode(ISD::SETCC, dl, SVT, LHS, RHS, N->getOperand(2)); // VSETCC always returns a sign-extended value, while SETCC may not. The // SETCC result type may not match the vector element type. Correct these. @@ -223,18 +232,18 @@ // Ensure the SETCC result is sign-extended. if (TLI.getBooleanContents() != TargetLowering::ZeroOrNegativeOneBooleanContent) - Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, SVT, Res, + Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, SVT, Res, DAG.getValueType(MVT::i1)); // Truncate to the final type. - return DAG.getNode(ISD::TRUNCATE, NVT, Res); + return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res); } else { // The SETCC result type is smaller than the vector element type. // If the SetCC result is not sign-extended, chop it down to MVT::i1. if (TLI.getBooleanContents() != TargetLowering::ZeroOrNegativeOneBooleanContent) - Res = DAG.getNode(ISD::TRUNCATE, MVT::i1, Res); + Res = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Res); // Sign extend to the final type. - return DAG.getNode(ISD::SIGN_EXTEND, NVT, Res); + return DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Res); } } @@ -291,7 +300,8 @@ /// to be scalarized, it must be <1 x ty>. Convert the element instead. SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) { SDValue Elt = GetScalarizedVector(N->getOperand(0)); - return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt); + return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), + N->getValueType(0), Elt); } /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one - @@ -300,7 +310,7 @@ SmallVector Ops(N->getNumOperands()); for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) Ops[i] = GetScalarizedVector(N->getOperand(i)); - return DAG.getNode(ISD::BUILD_VECTOR, N->getValueType(0), + return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0), &Ops[0], Ops.size()); } @@ -316,16 +326,17 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){ assert(N->isUnindexed() && "Indexed store of one-element vector?"); assert(OpNo == 1 && "Do not know how to scalarize this operand!"); + DebugLoc dl = N->getDebugLoc(); if (N->isTruncatingStore()) - return DAG.getTruncStore(N->getChain(), + return DAG.getTruncStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)), N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(), N->getMemoryVT().getVectorElementType(), N->isVolatile(), N->getAlignment()); - return DAG.getStore(N->getChain(), GetScalarizedVector(N->getOperand(1)), + return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)), N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(), N->isVolatile(), N->getAlignment()); } @@ -421,9 +432,10 @@ GetSplitVector(N->getOperand(0), LHSLo, LHSHi); SDValue RHSLo, RHSHi; GetSplitVector(N->getOperand(1), RHSLo, RHSHi); + DebugLoc dl = N->getDebugLoc(); - Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo); - Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi); + Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo); + Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi); } void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo, @@ -432,6 +444,7 @@ // scalar value. MVT LoVT, HiVT; GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); + DebugLoc dl = N->getDebugLoc(); SDValue InOp = N->getOperand(0); MVT InVT = InOp.getValueType(); @@ -454,8 +467,8 @@ GetExpandedOp(InOp, Lo, Hi); if (TLI.isBigEndian()) std::swap(Lo, Hi); - Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo); - Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi); + Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo); + Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi); return; } break; @@ -463,8 +476,8 @@ // If the input is a vector that needs to be split, convert each split // piece of the input now. GetSplitVector(InOp, Lo, Hi); - Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo); - Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi); + Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo); + Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi); return; } @@ -478,25 +491,27 @@ if (TLI.isBigEndian()) std::swap(Lo, Hi); - Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo); - Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi); + Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo); + Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi); } void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi) { MVT LoVT, HiVT; + DebugLoc dl = N->getDebugLoc(); GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); unsigned LoNumElts = LoVT.getVectorNumElements(); SmallVector LoOps(N->op_begin(), N->op_begin()+LoNumElts); - Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size()); + Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size()); SmallVector HiOps(N->op_begin()+LoNumElts, N->op_end()); - Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size()); + Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size()); } void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi) { assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS"); + DebugLoc dl = N->getDebugLoc(); unsigned NumSubvectors = N->getNumOperands() / 2; if (NumSubvectors == 1) { Lo = N->getOperand(0); @@ -508,10 +523,10 @@ GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); SmallVector LoOps(N->op_begin(), N->op_begin()+NumSubvectors); - Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size()); + Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size()); SmallVector HiOps(N->op_begin()+NumSubvectors, N->op_end()); - Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size()); + Hi =