From sabre at nondot.org Mon Feb 2 00:28:50 2009 From: sabre at nondot.org (Chris Lattner) Date: Mon, 02 Feb 2009 06:28:50 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63497 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <200902020628.n126So9m009223@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 2 00:28:48 2009 New Revision: 63497 URL: http://llvm.org/viewvc/llvm-project?rev=63497&view=rev Log: it is unclear whether this code was really safe or not, and it seems unlikely that it is. #if 0 it out for llvm 2.5 until we get resolution. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=63497&r1=63496&r2=63497&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Feb 2 00:28:48 2009 @@ -6181,7 +6181,10 @@ // offset, the field is known to be 4-byte aligned. LVAlign = MinAlign(LVAlign, Offset); } - + + // There is debate about whether this is really safe or not, be conservative + // in the meantime. +#if 0 // If this field is at a constant offset, if the LLVM pointer really points // to it, then we know that the pointer is at least as aligned as the field // is required to be. Try to round up our alignment info. @@ -6189,6 +6192,7 @@ !isBitfield(FieldDecl) && // bitfield computation might offset pointer. DECL_ALIGN(FieldDecl)) LVAlign = std::max(LVAlign, unsigned(DECL_ALIGN(FieldDecl)) / 8); +#endif // If the FIELD_DECL has an annotate attribute on it, emit it. if (lookup_attribute("annotate", DECL_ATTRIBUTES(FieldDecl))) From wangmp at apple.com Mon Feb 2 00:37:55 2009 From: wangmp at apple.com (Mon P Wang) Date: Mon, 02 Feb 2009 06:37:55 -0000 Subject: [llvm-commits] [llvm] r63498 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeIntegerTypes.cpp LegalizeVectorTypes.cpp Message-ID: <200902020637.n126btpr009499@zion.cs.uiuc.edu> Author: wangmp Date: Mon Feb 2 00:37:55 2009 New Revision: 63498 URL: http://llvm.org/viewvc/llvm-project?rev=63498&view=rev Log: Preserve more SourceValue information. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=63498&r1=63497&r2=63498&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon Feb 2 00:37:55 2009 @@ -19,6 +19,7 @@ //===----------------------------------------------------------------------===// #include "LegalizeTypes.h" +#include "llvm/CodeGen/PseudoSourceValue.h" using namespace llvm; //===----------------------------------------------------------------------===// @@ -214,12 +215,14 @@ // Create the stack frame object. Make sure it is aligned for both // the source and destination types. SDValue FIPtr = DAG.CreateStackTemporary(InVT, OutVT); + int FI = cast(FIPtr.getNode())->getIndex(); + const Value *SV = PseudoSourceValue::getFixedStack(FI); // Emit a store to the stack slot. - SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, NULL, 0); + SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0); // Result is an extending load from the stack slot. - return DAG.getExtLoad(ISD::EXTLOAD, dl, NOutVT, Store, FIPtr, NULL, 0, OutVT); + return DAG.getExtLoad(ISD::EXTLOAD, dl, NOutVT, Store, FIPtr, SV, 0, OutVT); } SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=63498&r1=63497&r2=63498&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Mon Feb 2 00:37:55 2009 @@ -21,6 +21,7 @@ //===----------------------------------------------------------------------===// #include "LegalizeTypes.h" +#include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Target/TargetData.h" using namespace llvm; @@ -976,11 +977,13 @@ MVT EltVT = VecVT.getVectorElementType(); DebugLoc dl = N->getDebugLoc(); SDValue StackPtr = DAG.CreateStackTemporary(VecVT); - SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0); + int SPFI = cast(StackPtr.getNode())->getIndex(); + const Value *SV = PseudoSourceValue::getFixedStack(SPFI); + SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, SV, 0); // Load back the required element. StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); - return DAG.getLoad(EltVT, dl, Store, StackPtr, NULL, 0); + return DAG.getLoad(EltVT, dl, Store, StackPtr, SV, 0); } SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { @@ -1350,12 +1353,14 @@ // from the stack. Create the stack frame object. Make sure it is aligned // for both the source and destination types. SDValue FIPtr = DAG.CreateStackTemporary(InVT, WidenVT); + int FI = cast(FIPtr.getNode())->getIndex(); + const Value *SV = PseudoSourceValue::getFixedStack(FI); // Emit a store to the stack slot. - SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, NULL, 0); + SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0); // Result is a load from the stack slot. - return DAG.getLoad(WidenVT, dl, Store, FIPtr, NULL, 0); + return DAG.getLoad(WidenVT, dl, Store, FIPtr, SV, 0); } SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) { @@ -1849,12 +1854,14 @@ // frame object. Make sure it is aligned for both the source and destination // types. SDValue FIPtr = DAG.CreateStackTemporary(InWidenVT, VT); + int FI = cast(FIPtr.getNode())->getIndex(); + const Value *SV = PseudoSourceValue::getFixedStack(FI); // Emit a store to the stack slot. - SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, NULL, 0); + SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0); // Result is a load from the stack slot. - return DAG.getLoad(VT, dl, Store, FIPtr, NULL, 0); + return DAG.getLoad(VT, dl, Store, FIPtr, SV, 0); } SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) { From clattner at apple.com Mon Feb 2 00:41:46 2009 From: clattner at apple.com (Chris Lattner) Date: Sun, 1 Feb 2009 22:41:46 -0800 Subject: [llvm-commits] [llvm] r63384 - in /llvm/trunk: include/llvm/Support/CommandLine.h lib/Support/CommandLine.cpp In-Reply-To: <2D103AC2-3298-401B-9822-72E5502ADAEF@apple.com> References: <200901300819.n0U8JkUt008727@zion.cs.uiuc.edu> <5F0660E8-D815-494B-A7F3-A6B9B16DD4E3@apple.com> <13E450F0-4D23-43FF-B876-4DBBF8807BC3@apple.com> <2D103AC2-3298-401B-9822-72E5502ADAEF@apple.com> Message-ID: <77834334-5B8A-42A5-9DBB-B1DD311570D6@apple.com> On Jan 30, 2009, at 5:05 PM, Mike Stump wrote: > On Jan 30, 2009, at 10:54 AM, Chris Lattner wrote: >>> On Jan 30, 2009, at 10:00 AM, Chris Lattner wrote: >>>> Please revert this patch in the meantime, thanks! >>> >>> Any objection to just fixing it? >> >> What do you mean? > > Tweaking the interface to be as you requested.... The typical usage > would look like: > > static llvm::cl::opt > EnableBlocks("fblocks", llvm::cl::desc("enable the 'blocks' language > feature"), > llvm::cl::ValueDisallowed, llvm::cl::AllowInverse); > > > How about the below? I think the usage side is nicer. > > I can do up the doc changes for consideration, if the patches are > reasonable enough. The patch looks great, some minor style requests: class parser : public basic_parser { + bool invertable; // Should we synthezise a -xno- style option? Please name this Invertible or IsInvertible. virtual void getExtraOptionNames(std::vector &OptionNames) { + if (this->getMiscFlags() & llvm::cl::AllowInverse) + { + char *s = new char [strlen(ArgStr) + 3 + 1]; + s[0] = ArgStr[0]; + s[1] = 'n'; + s[2] = 'o'; + s[3] = '-'; + strcpy (&s[4], ArgStr+1); + OptionNames.push_back (s); + } + return Parser.getExtraOptionNames(OptionNames); Invertibility should only apply to bool options, right? If so, please move this to parser. Also, please follow the normal llvm conventions: brace on preceeding line, no space before '(' in function/ method call or before the [ in "new char [". + if (invertable && strncmp (ArgName+1, "no-", 3) == 0) No space before (. Incidentally, it was more difficult than necessary to review your patch because you did not revert the old one separately. This means that two separate things are both present in your patch, which is annoying. Please commit this and the docs for it after making the updates, thanks Mike! -Chris From sabre at nondot.org Mon Feb 2 00:55:45 2009 From: sabre at nondot.org (Chris Lattner) Date: Mon, 02 Feb 2009 06:55:45 -0000 Subject: [llvm-commits] [llvm] r63499 - /llvm/trunk/test/Transforms/InstCombine/2009-01-31-InfIterate.ll Message-ID: <200902020655.n126tkJb010111@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 2 00:55:45 2009 New Revision: 63499 URL: http://llvm.org/viewvc/llvm-project?rev=63499&view=rev Log: reduce testcase. Modified: llvm/trunk/test/Transforms/InstCombine/2009-01-31-InfIterate.ll Modified: llvm/trunk/test/Transforms/InstCombine/2009-01-31-InfIterate.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2009-01-31-InfIterate.ll?rev=63499&r1=63498&r2=63499&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/2009-01-31-InfIterate.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/2009-01-31-InfIterate.ll Mon Feb 2 00:55:45 2009 @@ -1,484 +1,22 @@ ; RUN: llvm-as < %s | opt -instcombine | llvm-dis ; PR3452 -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-unknown-linux-gnu" - at __clz_tab = external constant [256 x i8] ; <[256 x i8]*> [#uses=3] - at llvm.used = appending global [1 x i8*] [ i8* bitcast (void (i128, i128, i128*)* @__udivmodti4 to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] - -define fastcc void @__udivmodti4(i128 %n, i128 %d, i128* %rp) nounwind alwaysinline { +define i128 @test(i64 %A, i64 %B, i1 %C, i128 %Z, i128 %Y, i64* %P, i64* %Q) { entry: - %tmp1 = trunc i128 %n to i64 ; [#uses=12] - %sroa.store.elt = lshr i128 %n, 64 ; [#uses=1] - %tmp2 = trunc i128 %sroa.store.elt to i64 ; [#uses=12] - %tmp3 = trunc i128 %d to i64 ; [#uses=12] - %sroa.store.elt16 = lshr i128 %d, 64 ; [#uses=1] - %tmp4 = trunc i128 %sroa.store.elt16 to i64 ; [#uses=7] - %tmp5 = icmp eq i64 %tmp4, 0 ; [#uses=1] - br i1 %tmp5, label %bb, label %bb86 - -bb: ; preds = %entry - %tmp6 = icmp ugt i64 %tmp3, %tmp2 ; [#uses=1] - br i1 %tmp6, label %bb33.thread, label %bb50 - -bb33.thread: ; preds = %bb - br label %bb31 - -bb31: ; preds = %bb33, %bb33.thread - %__a28.0.reg2mem.0 = phi i64 [ 56, %bb33.thread ], [ %tmp9, %bb33 ] ; [#uses=3] - %.cast = and i64 %__a28.0.reg2mem.0, 4294967288 ; [#uses=1] - %tmp = shl i64 255, %.cast ; [#uses=1] - %tmp7 = and i64 %tmp3, %tmp ; [#uses=1] - %tmp8 = icmp eq i64 %tmp7, 0 ; [#uses=1] - br i1 %tmp8, label %bb33, label %bb34 - -bb33: ; preds = %bb31 - %tmp9 = add i64 %__a28.0.reg2mem.0, -8 ; [#uses=3] - %tmp10 = icmp eq i64 %tmp9, 0 ; [#uses=1] - br i1 %tmp10, label %bb34, label %bb31 - -bb34: ; preds = %bb33, %bb31 - %__a28.0.reg2mem.1 = phi i64 [ %__a28.0.reg2mem.0, %bb31 ], [ %tmp9, %bb33 ] ; [#uses=2] - %.cast35 = and i64 %__a28.0.reg2mem.1, 4294967288 ; [#uses=1] - %tmp11 = lshr i64 %tmp3, %.cast35 ; [#uses=1] - %tmp12 = getelementptr [256 x i8]* @__clz_tab, i64 0, i64 %tmp11 ; [#uses=1] - %tmp13 = load i8* %tmp12, align 1 ; [#uses=1] - %tmp14 = zext i8 %tmp13 to i64 ; [#uses=1] - %tmp15 = add i64 %tmp14, %__a28.0.reg2mem.1 ; [#uses=2] - %tmp16 = sub i64 64, %tmp15 ; [#uses=7] - %tmp17 = icmp eq i64 %tmp15, 64 ; [#uses=1] - br i1 %tmp17, label %bb41, label %bb36 - -bb36: ; preds = %bb34 - %.cast37 = and i64 %tmp16, 4294967295 ; [#uses=1] - %tmp18 = shl i64 %tmp3, %.cast37 ; [#uses=1] - %.cast38 = and i64 %tmp16, 4294967295 ; [#uses=1] - %tmp19 = shl i64 %tmp2, %.cast38 ; [#uses=1] - %tmp20 = sub i64 64, %tmp16 ; [#uses=1] - %.cast39 = and i64 %tmp20, 4294967295 ; [#uses=1] - %tmp21 = lshr i64 %tmp1, %.cast39 ; [#uses=1] - %tmp22 = or i64 %tmp19, %tmp21 ; [#uses=1] - %.cast40 = and i64 %tmp16, 4294967295 ; [#uses=1] - %tmp23 = shl i64 %tmp1, %.cast40 ; [#uses=1] - br label %bb41 - -bb41: ; preds = %bb36, %bb34 - %n1.0 = phi i64 [ %tmp2, %bb34 ], [ %tmp22, %bb36 ] ; [#uses=2] - %n0.0 = phi i64 [ %tmp1, %bb34 ], [ %tmp23, %bb36 ] ; [#uses=2] - %d0.0 = phi i64 [ %tmp3, %bb34 ], [ %tmp18, %bb36 ] ; [#uses=8] - %tmp24 = lshr i64 %d0.0, 32 ; [#uses=4] - %tmp25 = and i64 %d0.0, 4294967295 ; [#uses=2] - %tmp26 = urem i64 %n1.0, %tmp24 ; [#uses=1] - %tmp27 = udiv i64 %n1.0, %tmp24 ; [#uses=1] - %tmp28 = mul i64 %tmp27, %tmp25 ; [#uses=3] - %tmp29 = shl i64 %tmp26, 32 ; [#uses=1] - %tmp30 = lshr i64 %n0.0, 32 ; [#uses=1] - %tmp31 = or i64 %tmp29, %tmp30 ; [#uses=3] - %tmp32 = icmp ult i64 %tmp31, %tmp28 ; [#uses=1] - br i1 %tmp32, label %bb42, label %bb45 - -bb42: ; preds = %bb41 - %tmp33 = add i64 %tmp31, %d0.0 ; [#uses=4] - %.not = icmp uge i64 %tmp33, %d0.0 ; [#uses=1] - %tmp34 = icmp ult i64 %tmp33, %tmp28 ; [#uses=1] - %or.cond = and i1 %tmp34, %.not ; [#uses=1] - br i1 %or.cond, label %bb44, label %bb45 - -bb44: ; preds = %bb42 - %tmp35 = add i64 %tmp33, %d0.0 ; [#uses=1] - br label %bb45 - -bb45: ; preds = %bb44, %bb42, %bb41 - %__r123.0 = phi i64 [ %tmp31, %bb41 ], [ %tmp33, %bb42 ], [ %tmp35, %bb44 ] ; [#uses=1] - %tmp36 = sub i64 %__r123.0, %tmp28 ; [#uses=2] - %tmp37 = urem i64 %tmp36, %tmp24 ; [#uses=1] - %tmp38 = udiv i64 %tmp36, %tmp24 ; [#uses=1] - %tmp39 = mul i64 %tmp38, %tmp25 ; [#uses=5] - %tmp40 = shl i64 %tmp37, 32 ; [#uses=1] - %tmp41 = and i64 %n0.0, 4294967295 ; [#uses=1] - %tmp42 = or i64 %tmp40, %tmp41 ; [#uses=3] - %tmp43 = icmp ult i64 %tmp42, %tmp39 ; [#uses=1] - br i1 %tmp43, label %bb46, label %bb83 - -bb46: ; preds = %bb45 - %tmp44 = add i64 %tmp42, %d0.0 ; [#uses=4] - %.not137 = icmp uge i64 %tmp44, %d0.0 ; [#uses=1] - %tmp45 = icmp ult i64 %tmp44, %tmp39 ; [#uses=1] - %or.cond138 = and i1 %tmp45, %.not137 ; [#uses=1] - br i1 %or.cond138, label %bb48, label %bb83 - -bb48: ; preds = %bb46 - %tmp46 = add i64 %tmp44, %d0.0 ; [#uses=1] - br label %bb83 - -bb50: ; preds = %bb - %tmp47 = icmp eq i64 %tmp3, 0 ; [#uses=1] - br i1 %tmp47, label %bb51, label %bb56.thread - -bb51: ; preds = %bb50 - %tmp48 = udiv i64 1, %tmp3 ; [#uses=1] - br label %bb56.thread - -bb53: ; preds = %bb56, %bb56.thread - %__a19.0.reg2mem.0 = phi i64 [ 56, %bb56.thread ], [ %tmp51, %bb56 ] ; [#uses=3] - %.cast54 = and i64 %__a19.0.reg2mem.0, 4294967288 ; [#uses=1] - %tmp133 = shl i64 255, %.cast54 ; [#uses=1] - %tmp49 = and i64 %d0.1.ph, %tmp133 ; [#uses=1] - %tmp50 = icmp eq i64 %tmp49, 0 ; [#uses=1] - br i1 %tmp50, label %bb56, label %bb57 - -bb56.thread: ; preds = %bb51, %bb50 - %d0.1.ph = phi i64 [ %tmp48, %bb51 ], [ %tmp3, %bb50 ] ; [#uses=5] - br label %bb53 - -bb56: ; preds = %bb53 - %tmp51 = add i64 %__a19.0.reg2mem.0, -8 ; [#uses=3] - %tmp52 = icmp eq i64 %tmp51, 0 ; [#uses=1] - br i1 %tmp52, label %bb57, label %bb53 - -bb57: ; preds = %bb56, %bb53 - %__a19.0.reg2mem.1 = phi i64 [ %__a19.0.reg2mem.0, %bb53 ], [ %tmp51, %bb56 ] ; [#uses=2] - %.cast58 = and i64 %__a19.0.reg2mem.1, 4294967288 ; [#uses=1] - %tmp53 = lshr i64 %d0.1.ph, %.cast58 ; [#uses=1] - %tmp54 = getelementptr [256 x i8]* @__clz_tab, i64 0, i64 %tmp53 ; [#uses=1] - %tmp55 = load i8* %tmp54, align 1 ; [#uses=1] - %tmp56 = zext i8 %tmp55 to i64 ; [#uses=1] - %tmp57 = add i64 %tmp56, %__a19.0.reg2mem.1 ; [#uses=2] - %tmp58 = sub i64 64, %tmp57 ; [#uses=7] - %tmp59 = icmp eq i64 %tmp57, 64 ; [#uses=1] - br i1 %tmp59, label %bb74, label %bb60 - -bb60: ; preds = %bb57 - %tmp60 = sub i64 64, %tmp58 ; [#uses=2] - %.cast61 = and i64 %tmp58, 4294967295 ; [#uses=1] - %tmp61 = shl i64 %d0.1.ph, %.cast61 ; [#uses=9] - %.cast62 = and i64 %tmp60, 4294967295 ; [#uses=1] - %tmp62 = lshr i64 %tmp2, %.cast62 ; [#uses=2] - %.cast63 = and i64 %tmp58, 4294967295 ; [#uses=1] - %tmp63 = shl i64 %tmp2, %.cast63 ; [#uses=1] - %.cast64 = and i64 %tmp60, 4294967295 ; [#uses=1] - %tmp64 = lshr i64 %tmp1, %.cast64 ; [#uses=1] - %tmp65 = or i64 %tmp63, %tmp64 ; [#uses=2] - %.cast65 = and i64 %tmp58, 4294967295 ; [#uses=1] - %tmp66 = shl i64 %tmp1, %.cast65 ; [#uses=1] - %tmp67 = lshr i64 %tmp61, 32 ; [#uses=4] - %tmp68 = and i64 %tmp61, 4294967295 ; [#uses=2] - %tmp69 = urem i64 %tmp62, %tmp67 ; [#uses=1] - %tmp70 = udiv i64 %tmp62, %tmp67 ; [#uses=1] - %tmp71 = mul i64 %tmp70, %tmp68 ; [#uses=3] - %tmp72 = shl i64 %tmp69, 32 ; [#uses=1] - %tmp73 = lshr i64 %tmp65, 32 ; [#uses=1] - %tmp74 = or i64 %tmp72, %tmp73 ; [#uses=3] - %tmp75 = icmp ult i64 %tmp74, %tmp71 ; [#uses=1] - br i1 %tmp75, label %bb66, label %bb69 - -bb66: ; preds = %bb60 - %tmp76 = add i64 %tmp74, %tmp61 ; [#uses=4] - %.not139 = icmp uge i64 %tmp76, %tmp61 ; [#uses=1] - %tmp77 = icmp ult i64 %tmp76, %tmp71 ; [#uses=1] - %or.cond140 = and i1 %tmp77, %.not139 ; [#uses=1] - br i1 %or.cond140, label %bb68, label %bb69 - -bb68: ; preds = %bb66 - %tmp78 = add i64 %tmp76, %tmp61 ; [#uses=1] - br label %bb69 - -bb69: ; preds = %bb68, %bb66, %bb60 - %__r114.0 = phi i64 [ %tmp74, %bb60 ], [ %tmp76, %bb66 ], [ %tmp78, %bb68 ] ; [#uses=1] - %tmp79 = sub i64 %__r114.0, %tmp71 ; [#uses=2] - %tmp80 = urem i64 %tmp79, %tmp67 ; [#uses=1] - %tmp81 = udiv i64 %tmp79, %tmp67 ; [#uses=1] - %tmp82 = mul i64 %tmp81, %tmp68 ; [#uses=3] - %tmp83 = shl i64 %tmp80, 32 ; [#uses=1] - %tmp84 = and i64 %tmp65, 4294967295 ; [#uses=1] - %tmp85 = or i64 %tmp83, %tmp84 ; [#uses=3] - %tmp86 = icmp ult i64 %tmp85, %tmp82 ; [#uses=1] - br i1 %tmp86, label %bb70, label %bb73 - -bb70: ; preds = %bb69 - %tmp87 = add i64 %tmp85, %tmp61 ; [#uses=4] - %.not141 = icmp uge i64 %tmp87, %tmp61 ; [#uses=1] - %tmp88 = icmp ult i64 %tmp87, %tmp82 ; [#uses=1] - %or.cond142 = and i1 %tmp88, %.not141 ; [#uses=1] - br i1 %or.cond142, label %bb72, label %bb73 - -bb72: ; preds = %bb70 - %tmp89 = add i64 %tmp87, %tmp61 ; [#uses=1] - br label %bb73 - -bb73: ; preds = %bb72, %bb70, %bb69 - %__r013.0 = phi i64 [ %tmp85, %bb69 ], [ %tmp87, %bb70 ], [ %tmp89, %bb72 ] ; [#uses=1] - br label %bb74 - -bb74: ; preds = %bb73, %bb57 - %__r013.0.pn = phi i64 [ %__r013.0, %bb73 ], [ %tmp2, %bb57 ] ; [#uses=1] - %.pn135 = phi i64 [ %tmp82, %bb73 ], [ %d0.1.ph, %bb57 ] ; [#uses=1] - %n0.2 = phi i64 [ %tmp66, %bb73 ], [ %tmp1, %bb57 ] ; [#uses=2] - %d0.2 = phi i64 [ %tmp61, %bb73 ], [ %d0.1.ph, %bb57 ] ; [#uses=8] - %n1.1 = sub i64 %__r013.0.pn, %.pn135 ; [#uses=2] - %tmp90 = lshr i64 %d0.2, 32 ; [#uses=4] - %tmp91 = and i64 %d0.2, 4294967295 ; [#uses=2] - %tmp92 = urem i64 %n1.1, %tmp90 ; [#uses=1] - %tmp93 = udiv i64 %n1.1, %tmp90 ; [#uses=1] - %tmp94 = mul i64 %tmp93, %tmp91 ; [#uses=3] - %tmp95 = shl i64 %tmp92, 32 ; [#uses=1] - %tmp96 = lshr i64 %n0.2, 32 ; [#uses=1] - %tmp97 = or i64 %tmp95, %tmp96 ; [#uses=3] - %tmp98 = icmp ult i64 %tmp97, %tmp94 ; [#uses=1] - br i1 %tmp98, label %bb75, label %bb78 - -bb75: ; preds = %bb74 - %tmp99 = add i64 %tmp97, %d0.2 ; [#uses=4] - %.not143 = icmp uge i64 %tmp99, %d0.2 ; [#uses=1] - %tmp100 = icmp ult i64 %tmp99, %tmp94 ; [#uses=1] - %or.cond144 = and i1 %tmp100, %.not143 ; [#uses=1] - br i1 %or.cond144, label %bb77, label %bb78 - -bb77: ; preds = %bb75 - %tmp101 = add i64 %tmp99, %d0.2 ; [#uses=1] - br label %bb78 - -bb78: ; preds = %bb77, %bb75, %bb74 - %__r17.0 = phi i64 [ %tmp97, %bb74 ], [ %tmp99, %bb75 ], [ %tmp101, %bb77 ] ; [#uses=1] - %tmp102 = sub i64 %__r17.0, %tmp94 ; [#uses=2] - %tmp103 = urem i64 %tmp102, %tmp90 ; [#uses=1] - %tmp104 = udiv i64 %tmp102, %tmp90 ; [#uses=1] - %tmp105 = mul i64 %tmp104, %tmp91 ; [#uses=5] - %tmp106 = shl i64 %tmp103, 32 ; [#uses=1] - %tmp107 = and i64 %n0.2, 4294967295 ; [#uses=1] - %tmp108 = or i64 %tmp106, %tmp107 ; [#uses=3] - %tmp109 = icmp ult i64 %tmp108, %tmp105 ; [#uses=1] - br i1 %tmp109, label %bb79, label %bb83 - -bb79: ; preds = %bb78 - %tmp110 = add i64 %tmp108, %d0.2 ; [#uses=4] - %.not145 = icmp uge i64 %tmp110, %d0.2 ; [#uses=1] - %tmp111 = icmp ult i64 %tmp110, %tmp105 ; [#uses=1] - %or.cond146 = and i1 %tmp111, %.not145 ; [#uses=1] - br i1 %or.cond146, label %bb81, label %bb83 - -bb81: ; preds = %bb79 - %tmp112 = add i64 %tmp110, %d0.2 ; [#uses=1] - br label %bb83 - -bb83: ; preds = %bb81, %bb79, %bb78, %bb48, %bb46, %bb45 - %bm.0 = phi i64 [ %tmp16, %bb46 ], [ %tmp16, %bb48 ], [ %tmp16, %bb45 ], [ %tmp58, %bb79 ], [ %tmp58, %bb81 ], [ %tmp58, %bb78 ] ; [#uses=1] - %__r06.0.pn = phi i64 [ %tmp42, %bb45 ], [ %tmp44, %bb46 ], [ %tmp46, %bb48 ], [ %tmp108, %bb78 ], [ %tmp110, %bb79 ], [ %tmp112, %bb81 ] ; [#uses=1] - %.pn = phi i64 [ %tmp39, %bb46 ], [ %tmp39, %bb48 ], [ %tmp39, %bb45 ], [ %tmp105, %bb79 ], [ %tmp105, %bb81 ], [ %tmp105, %bb78 ] ; [#uses=1] - %tmp113 = icmp eq i128* %rp, null ; [#uses=1] - br i1 %tmp113, label %bb131, label %bb84 - -bb84: ; preds = %bb83 - %n0.1 = sub i64 %__r06.0.pn, %.pn ; [#uses=1] - %.cast85 = and i64 %bm.0, 4294967295 ; [#uses=1] - %tmp114 = lshr i64 %n0.1, %.cast85 ; [#uses=1] - %tmp115 = zext i64 %tmp114 to i128 ; [#uses=1] - store i128 %tmp115, i128* %rp, align 16 - br label %bb131 - -bb86: ; preds = %entry - %tmp116 = icmp ugt i64 %tmp4, %tmp2 ; [#uses=1] - br i1 %tmp116, label %bb87, label %bb93.thread - -bb93.thread: ; preds = %bb86 - br label %bb90 - -bb87: ; preds = %bb86 - %tmp117 = icmp eq i128* %rp, null ; [#uses=1] - br i1 %tmp117, label %bb131, label %bb88 - -bb88: ; preds = %bb87 - store i128 %n, i128* %rp, align 16 - br label %bb131 - -bb90: ; preds = %bb93, %bb93.thread - %__a.0.reg2mem.0 = phi i64 [ 56, %bb93.thread ], [ %tmp120, %bb93 ] ; [#uses=3] - %.cast91 = and i64 %__a.0.reg2mem.0, 4294967288 ; [#uses=1] - %tmp136 = shl i64 255, %.cast91 ; [#uses=1] - %tmp118 = and i64 %tmp4, %tmp136 ; [#uses=1] - %tmp119 = icmp eq i64 %tmp118, 0 ; [#uses=1] - br i1 %tmp119, label %bb93, label %bb94 - -bb93: ; preds = %bb90 - %tmp120 = add i64 %__a.0.reg2mem.0, -8 ; [#uses=3] - %tmp121 = icmp eq i64 %tmp120, 0 ; [#uses=1] - br i1 %tmp121, label %bb94, label %bb90 - -bb94: ; preds = %bb93, %bb90 - %__a.0.reg2mem.1 = phi i64 [ %__a.0.reg2mem.0, %bb90 ], [ %tmp120, %bb93 ] ; [#uses=2] - %.cast95 = and i64 %__a.0.reg2mem.1, 4294967288 ; [#uses=1] - %tmp122 = lshr i64 %tmp4, %.cast95 ; [#uses=1] - %tmp123 = getelementptr [256 x i8]* @__clz_tab, i64 0, i64 %tmp122 ; [#uses=1] - %tmp124 = load i8* %tmp123, align 1 ; [#uses=1] - %tmp125 = zext i8 %tmp124 to i64 ; [#uses=1] - %tmp126 = add i64 %tmp125, %__a.0.reg2mem.1 ; [#uses=2] - %tmp127 = sub i64 64, %tmp126 ; [#uses=7] - %tmp128 = icmp eq i64 %tmp126, 64 ; [#uses=1] - br i1 %tmp128, label %bb96, label %bb103 - -bb96: ; preds = %bb94 - %tmp129 = icmp ugt i64 %tmp2, %tmp4 ; [#uses=1] - %tmp130 = icmp uge i64 %tmp1, %tmp3 ; [#uses=1] - %tmp131 = or i1 %tmp129, %tmp130 ; [#uses=1] - br i1 %tmp131, label %bb99, label %bb101 - -bb99: ; preds = %bb96 - %tmp132 = sub i64 %tmp1, %tmp3 ; [#uses=2] - %tmp134 = sub i64 %tmp2, %tmp4 ; [#uses=1] - %tmp135 = icmp ugt i64 %tmp132, %tmp1 ; [#uses=1] - %tmp137 = zext i1 %tmp135 to i64 ; [#uses=1] - %tmp138 = sub i64 %tmp134, %tmp137 ; [#uses=1] - br label %bb101 - -bb101: ; preds = %bb99, %bb96 - %tmp139 = phi i64 [ %tmp138, %bb99 ], [ %tmp2, %bb96 ] ; [#uses=1] - %n0.3 = phi i64 [ %tmp132, %bb99 ], [ %tmp1, %bb96 ] ; [#uses=1] - %tmp140 = icmp eq i128* %rp, null ; [#uses=1] - br i1 %tmp140, label %bb131, label %bb102 - -bb102: ; preds = %bb101 - %tmp141 = zext i64 %n0.3 to i128 ; [#uses=1] - %tmp142 = zext i64 %tmp139 to i128 ; [#uses=1] - %tmp143 = shl i128 %tmp142, 64 ; [#uses=1] - %tmp144 = or i128 %tmp143, %tmp141 ; [#uses=1] - store i128 %tmp144, i128* %rp, align 16 - br label %bb131 - -bb103: ; preds = %bb94 - %tmp145 = sub i64 64, %tmp127 ; [#uses=4] - %.cast104 = and i64 %tmp127, 4294967295 ; [#uses=1] - %tmp146 = shl i64 %tmp4, %.cast104 ; [#uses=1] - %.cast105 = and i64 %tmp145, 4294967295 ; [#uses=1] - %tmp147 = lshr i64 %tmp3, %.cast105 ; [#uses=1] - %tmp148 = or i64 %tmp146, %tmp147 ; [#uses=9] - %.cast106 = and i64 %tmp127, 4294967295 ; [#uses=1] - %tmp149 = shl i64 %tmp3, %.cast106 ; [#uses=3] - %.cast107 = and i64 %tmp145, 4294967295 ; [#uses=1] - %tmp150 = lshr i64 %tmp2, %.cast107 ; [#uses=2] - %.cast108 = and i64 %tmp127, 4294967295 ; [#uses=1] - %tmp151 = shl i64 %tmp2, %.cast108 ; [#uses=1] - %.cast109 = and i64 %tmp145, 4294967295 ; [#uses=1] - %tmp152 = lshr i64 %tmp1, %.cast109 ; [#uses=1] - %tmp153 = or i64 %tmp151, %tmp152 ; [#uses=2] - %.cast110 = and i64 %tmp127, 4294967295 ; [#uses=1] - %tmp154 = shl i64 %tmp1, %.cast110 ; [#uses=3] - %tmp155 = lshr i64 %tmp148, 32 ; [#uses=4] - %tmp156 = and i64 %tmp148, 4294967295 ; [#uses=2] - %tmp157 = urem i64 %tmp150, %tmp155 ; [#uses=1] - %tmp158 = udiv i64 %tmp150, %tmp155 ; [#uses=4] - %tmp159 = mul i64 %tmp158, %tmp156 ; [#uses=3] - %tmp160 = shl i64 %tmp157, 32 ; [#uses=1] - %tmp161 = lshr i64 %tmp153, 32 ; [#uses=1] - %tmp162 = or i64 %tmp160, %tmp161 ; [#uses=3] - %tmp163 = icmp ult i64 %tmp162, %tmp159 ; [#uses=1] - br i1 %tmp163, label %bb111, label %bb114 - -bb111: ; preds = %bb103 - %tmp164 = add i64 %tmp158, -1 ; [#uses=1] - %tmp165 = add i64 %tmp162, %tmp148 ; [#uses=4] - %.not147 = icmp uge i64 %tmp165, %tmp148 ; [#uses=1] - %tmp166 = icmp ult i64 %tmp165, %tmp159 ; [#uses=1] - %or.cond148 = and i1 %tmp166, %.not147 ; [#uses=1] - br i1 %or.cond148, label %bb113, label %bb114 - -bb113: ; preds = %bb111 - %tmp167 = add i64 %tmp158, -2 ; [#uses=1] - %tmp168 = add i64 %tmp165, %tmp148 ; [#uses=1] - br label %bb114 - -bb114: ; preds = %bb113, %bb111, %bb103 - %__q1.0 = phi i64 [ %tmp158, %bb103 ], [ %tmp164, %bb111 ], [ %tmp167, %bb113 ] ; [#uses=1] - %__r1.0 = phi i64 [ %tmp162, %bb103 ], [ %tmp165, %bb111 ], [ %tmp168, %bb113 ] ; [#uses=1] - %tmp169 = sub i64 %__r1.0, %tmp159 ; [#uses=2] - %tmp170 = urem i64 %tmp169, %tmp155 ; [#uses=1] - %tmp171 = udiv i64 %tmp169, %tmp155 ; [#uses=4] - %tmp172 = mul i64 %tmp171, %tmp156 ; [#uses=3] - %tmp173 = shl i64 %tmp170, 32 ; [#uses=1] - %tmp174 = and i64 %tmp153, 4294967295 ; [#uses=1] - %tmp175 = or i64 %tmp173, %tmp174 ; [#uses=3] - %tmp176 = icmp ult i64 %tmp175, %tmp172 ; [#uses=1] - br i1 %tmp176, label %bb115, label %bb118 - -bb115: ; preds = %bb114 - %tmp177 = add i64 %tmp171, -1 ; [#uses=1] - %tmp178 = add i64 %tmp175, %tmp148 ; [#uses=4] - %.not149 = icmp uge i64 %tmp178, %tmp148 ; [#uses=1] - %tmp179 = icmp ult i64 %tmp178, %tmp172 ; [#uses=1] - %or.cond150 = and i1 %tmp179, %.not149 ; [#uses=1] - br i1 %or.cond150, label %bb117, label %bb118 - -bb117: ; preds = %bb115 - %tmp180 = add i64 %tmp171, -2 ; [#uses=1] - %tmp181 = add i64 %tmp178, %tmp148 ; [#uses=1] - br label %bb118 - -bb118: ; preds = %bb117, %bb115, %bb114 - %__q0.0 = phi i64 [ %tmp171, %bb114 ], [ %tmp177, %bb115 ], [ %tmp180, %bb117 ] ; [#uses=2] - %__r0.0 = phi i64 [ %tmp175, %bb114 ], [ %tmp178, %bb115 ], [ %tmp181, %bb117 ] ; [#uses=1] - %tmp182 = sub i64 %__r0.0, %tmp172 ; [#uses=3] - %tmp183 = shl i64 %__q1.0, 32 ; [#uses=1] - %tmp184 = or i64 %tmp183, %__q0.0 ; [#uses=1] - %tmp185 = and i64 %__q0.0, 4294967295 ; [#uses=2] - %tmp186 = lshr i64 %tmp184, 32 ; [#uses=2] - %tmp187 = and i64 %tmp149, 4294967295 ; [#uses=2] - %tmp188 = lshr i64 %tmp149, 32 ; [#uses=2] - %tmp189 = mul i64 %tmp185, %tmp187 ; [#uses=2] - %tmp190 = mul i64 %tmp185, %tmp188 ; [#uses=1] - %tmp191 = mul i64 %tmp186, %tmp187 ; [#uses=2] - %tmp192 = mul i64 %tmp186, %tmp188 ; [#uses=1] - %tmp193 = lshr i64 %tmp189, 32 ; [#uses=1] - %tmp194 = add i64 %tmp193, %tmp190 ; [#uses=1] - %tmp195 = add i64 %tmp194, %tmp191 ; [#uses=3] - %tmp196 = icmp ult i64 %tmp195, %tmp191 ; [#uses=1] - %tmp197 = select i1 %tmp196, i64 4294967296, i64 0 ; [#uses=1] - %__x3.0 = add i64 %tmp192, %tmp197 ; [#uses=1] - %tmp198 = lshr i64 %tmp195, 32 ; [#uses=1] - %tmp199 = add i64 %tmp198, %__x3.0 ; [#uses=4] - %tmp200 = shl i64 %tmp195, 32 ; [#uses=1] - %tmp201 = and i64 %tmp189, 4294967295 ; [#uses=1] - %tmp202 = or i64 %tmp200, %tmp201 ; [#uses=4] - %tmp203 = icmp ugt i64 %tmp199, %tmp182 ; [#uses=1] - br i1 %tmp203, label %bb125, label %bb121 - -bb121: ; preds = %bb118 - %tmp204 = icmp eq i64 %tmp199, %tmp182 ; [#uses=1] - %tmp205 = icmp ugt i64 %tmp202, %tmp154 ; [#uses=1] - %tmp206 = and i1 %tmp204, %tmp205 ; [#uses=1] - br i1 %tmp206, label %bb125, label %bb126 - -bb125: ; preds = %bb121, %bb118 - %tmp207 = sub i64 %tmp202, %tmp149 ; [#uses=2] - %tmp208 = sub i64 %tmp199, %tmp148 ; [#uses=1] - %tmp209 = icmp ugt i64 %tmp207, %tmp202 ; [#uses=1] - %tmp210 = zext i1 %tmp209 to i64 ; [#uses=1] - %tmp211 = sub i64 %tmp208, %tmp210 ; [#uses=1] - br label %bb126 - -bb126: ; preds = %bb125, %bb121 - %m1.0 = phi i64 [ %tmp199, %bb121 ], [ %tmp211, %bb125 ] ; [#uses=1] - %m0.0 = phi i64 [ %tmp202, %bb121 ], [ %tmp207, %bb125 ] ; [#uses=1] - %tmp212 = icmp eq i128* %rp, null ; [#uses=1] - br i1 %tmp212, label %bb131, label %bb127 - -bb127: ; preds = %bb126 - %tmp213 = sub i64 %tmp154, %m0.0 ; [#uses=2] - %tmp214 = sub i64 %tmp182, %m1.0 ; [#uses=1] - %tmp215 = icmp ugt i64 %tmp213, %tmp154 ; [#uses=1] - %tmp216 = zext i1 %tmp215 to i64 ; [#uses=1] - %tmp217 = sub i64 %tmp214, %tmp216 ; [#uses=2] - %.cast128 = and i64 %tmp145, 4294967295 ; [#uses=1] - %tmp218 = shl i64 %tmp217, %.cast128 ; [#uses=1] - %.cast129 = and i64 %tmp127, 4294967295 ; [#uses=1] - %tmp219 = lshr i64 %tmp213, %.cast129 ; [#uses=1] - %tmp220 = or i64 %tmp218, %tmp219 ; [#uses=1] - %.cast130 = and i64 %tmp127, 4294967295 ; [#uses=1] - %tmp221 = lshr i64 %tmp217, %.cast130 ; [#uses=1] - %tmp222 = zext i64 %tmp220 to i128 ; [#uses=1] - %tmp223 = zext i64 %tmp221 to i128 ; [#uses=1] - %tmp224 = shl i128 %tmp223, 64 ; [#uses=1] - %tmp225 = or i128 %tmp224, %tmp222 ; [#uses=1] - store i128 %tmp225, i128* %rp, align 16 - br label %bb131 + %tmp2 = trunc i128 %Z to i64 + %tmp4 = trunc i128 %Y to i64 + store i64 %tmp2, i64* %P + store i64 %tmp4, i64* %Q + %x = sub i64 %tmp2, %tmp4 + %c = sub i64 %tmp2, %tmp4 + %tmp137 = zext i1 %C to i64 + %tmp138 = sub i64 %c, %tmp137 + br label %T + +T: + %G = phi i64 [%tmp138, %entry], [%tmp2, %Fal] + %F = zext i64 %G to i128 + ret i128 %F -bb131: ; preds = %bb127, %bb126, %bb102, %bb101, %bb88, %bb87, %bb84, %bb83 - ret void +Fal: + br label %T } From sabre at nondot.org Mon Feb 2 01:15:30 2009 From: sabre at nondot.org (Chris Lattner) Date: Mon, 02 Feb 2009 07:15:30 -0000 Subject: [llvm-commits] [llvm] r63500 - /llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200902020715.n127FUYA010750@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 2 01:15:30 2009 New Revision: 63500 URL: http://llvm.org/viewvc/llvm-project?rev=63500&view=rev Log: reduce indentation, (~XorCST->getValue()).isSignBit() -> isMaxSignedValue() Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=63500&r1=63499&r2=63500&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Mon Feb 2 01:15:30 2009 @@ -6101,27 +6101,26 @@ case Instruction::Add: case Instruction::Sub: case Instruction::Xor: - if (I.isEquality()) { - // a+x icmp eq/ne b+x --> a icmp b + if (I.isEquality()) // a+x icmp eq/ne b+x --> a icmp b return new ICmpInst(I.getPredicate(), Op0I->getOperand(0), Op1I->getOperand(0)); - } else { - // icmp u/s (a ^ signbit), (b ^ signbit) --> icmp s/u a, b - if (ConstantInt *CI = dyn_cast(Op0I->getOperand(1))) { - if (CI->getValue().isSignBit()) { - ICmpInst::Predicate Pred = I.isSignedPredicate() - ? I.getUnsignedPredicate() - : I.getSignedPredicate(); - return new ICmpInst(Pred, Op0I->getOperand(0), - Op1I->getOperand(0)); - } else if ((~CI->getValue()).isSignBit()) { - ICmpInst::Predicate Pred = I.isSignedPredicate() - ? I.getUnsignedPredicate() - : I.getSignedPredicate(); - Pred = I.getSwappedPredicate(Pred); - return new ICmpInst(Pred, Op0I->getOperand(0), - Op1I->getOperand(0)); - } + // icmp u/s (a ^ signbit), (b ^ signbit) --> icmp s/u a, b + if (ConstantInt *CI = dyn_cast(Op0I->getOperand(1))) { + if (CI->getValue().isSignBit()) { + ICmpInst::Predicate Pred = I.isSignedPredicate() + ? I.getUnsignedPredicate() + : I.getSignedPredicate(); + return new ICmpInst(Pred, Op0I->getOperand(0), + Op1I->getOperand(0)); + } + + if (CI->getValue().isMaxSignedValue()) { + ICmpInst::Predicate Pred = I.isSignedPredicate() + ? I.getUnsignedPredicate() + : I.getSignedPredicate(); + Pred = I.getSwappedPredicate(Pred); + return new ICmpInst(Pred, Op0I->getOperand(0), + Op1I->getOperand(0)); } } break; @@ -6460,7 +6459,7 @@ } // (icmp u/s (xor A ~SignBit), C) -> (icmp s/u (xor C ~SignBit), A) - if (!ICI.isEquality() && (~XorCST->getValue()).isSignBit()) { + if (!ICI.isEquality() && XorCST->getValue().isMaxSignedValue()) { const APInt &NotSignBit = XorCST->getValue(); ICmpInst::Predicate Pred = ICI.isSignedPredicate() ? ICI.getUnsignedPredicate() From sabre at nondot.org Mon Feb 2 01:24:28 2009 From: sabre at nondot.org (Chris Lattner) Date: Mon, 02 Feb 2009 07:24:28 -0000 Subject: [llvm-commits] [llvm] r63501 - in /llvm/trunk: lib/AsmParser/LLParser.cpp test/Assembler/2009-02-01-UnnamedForwardRef.ll Message-ID: <200902020724.n127OS90011034@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 2 01:24:28 2009 New Revision: 63501 URL: http://llvm.org/viewvc/llvm-project?rev=63501&view=rev Log: Fix PR3372 Added: llvm/trunk/test/Assembler/2009-02-01-UnnamedForwardRef.ll Modified: llvm/trunk/lib/AsmParser/LLParser.cpp Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=63501&r1=63500&r2=63501&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Mon Feb 2 01:24:28 2009 @@ -471,8 +471,9 @@ GlobalVariable *GV = 0; // See if the global was forward referenced, if so, use the global. - if (!Name.empty() && (GV = M->getGlobalVariable(Name, true))) { - if (!ForwardRefVals.erase(Name)) + if (!Name.empty()) { + if ((GV = M->getGlobalVariable(Name, true)) && + !ForwardRefVals.erase(Name)) return Error(NameLoc, "redefinition of global '@" + Name + "'"); } else { std::map >::iterator Added: llvm/trunk/test/Assembler/2009-02-01-UnnamedForwardRef.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/2009-02-01-UnnamedForwardRef.ll?rev=63501&view=auto ============================================================================== --- llvm/trunk/test/Assembler/2009-02-01-UnnamedForwardRef.ll (added) +++ llvm/trunk/test/Assembler/2009-02-01-UnnamedForwardRef.ll Mon Feb 2 01:24:28 2009 @@ -0,0 +1,6 @@ +; RUN: llvm-as < %s | llvm-dis +; PR3372 + + at X = global i32* @0 +global i32 4 + From sabre at nondot.org Mon Feb 2 01:32:36 2009 From: sabre at nondot.org (Chris Lattner) Date: Mon, 02 Feb 2009 07:32:36 -0000 Subject: [llvm-commits] [llvm] r63502 - /llvm/trunk/docs/LangRef.html Message-ID: <200902020732.n127Wadv011329@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 2 01:32:36 2009 New Revision: 63502 URL: http://llvm.org/viewvc/llvm-project?rev=63502&view=rev Log: Document type upreferences (PR3380), patch by Stein Roger Skafl?tten with enhancements and corrections by me. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=63502&r1=63501&r2=63502&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Mon Feb 2 01:32:36 2009 @@ -55,6 +55,7 @@
  • Opaque Type
    • +
  • Type Up-references
  • Constants @@ -722,7 +723,6 @@ -
    Global Variables @@ -1646,6 +1646,58 @@
    + +
    + Type Up-references +
    + +
    +
    Overview:
    +

    +An "up reference" allows you to refer to a lexically enclosing type without +requiring it to have a name. For instance, a structure declaration may contain a +pointer to any of the types it is lexically a member of. Example of up +references (with their equivalent as named type declarations) include:

    + +
    +   { \2 * }                %x = type { %t* }
+   { \2 }*                 %y = type { %y }*
+   \1*                     %z = type %z*
+
    + +

    +An up reference is needed by the asmprinter for printing out cyclic types when +there is no declared name for a type in the cycle. Because the asmprinter does +not want to print out an infinite type string, it needs a syntax to handle +recursive types that have no names (all names are optional in llvm IR). +

    + +
    Syntax:
    +
    +   \<level>
+
    + +

    +The level is the count of the lexical type that is being referred to. +

    + +
    Examples:
    + + + + + + + + + + +
    \1*Self-referential pointer.
    { { \3*, i8 }, i32 }Recursive structure where the upref refers to the out-most + structure.
    +
    + + +
    Constants
    From sabre at nondot.org Mon Feb 2 01:33:15 2009 From: sabre at nondot.org (Chris Lattner) Date: Mon, 02 Feb 2009 07:33:15 -0000 Subject: [llvm-commits] [llvm] r63503 - /llvm/trunk/docs/LangRef.html Message-ID: <200902020733.n127XFIB011357@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 2 01:33:15 2009 New Revision: 63503 URL: http://llvm.org/viewvc/llvm-project?rev=63503&view=rev Log: validation error fix. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=63503&r1=63502&r2=63503&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Mon Feb 2 01:33:15 2009 @@ -1696,8 +1696,6 @@ - -
    Constants
    From sabre at nondot.org Mon Feb 2 01:40:18 2009 From: sabre at nondot.org (Chris Lattner) Date: Mon, 02 Feb 2009 07:40:18 -0000 Subject: [llvm-commits] [llvm] r63504 - /llvm/trunk/lib/VMCore/Verifier.cpp Message-ID: <200902020740.n127eIq2011602@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 2 01:40:17 2009 New Revision: 63504 URL: http://llvm.org/viewvc/llvm-project?rev=63504&view=rev Log: reject things like: zext <4 x i32> %tmp to i256 Modified: llvm/trunk/lib/VMCore/Verifier.cpp Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=63504&r1=63503&r2=63504&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Mon Feb 2 01:40:17 2009 @@ -715,6 +715,8 @@ Assert1(SrcTy->isIntOrIntVector(), "Trunc only operates on integer", &I); Assert1(DestTy->isIntOrIntVector(), "Trunc only produces integer", &I); + Assert1(isa(SrcTy) == isa(DestTy), + "trunc source and destination must both be a vector or neither", &I); Assert1(SrcBitSize > DestBitSize,"DestTy too big for Trunc", &I); visitInstruction(I); @@ -728,6 +730,8 @@ // Get the size of the types in bits, we'll need this later Assert1(SrcTy->isIntOrIntVector(), "ZExt only operates on integer", &I); Assert1(DestTy->isIntOrIntVector(), "ZExt only produces an integer", &I); + Assert1(isa(SrcTy) == isa(DestTy), + "zext source and destination must both be a vector or neither", &I); unsigned SrcBitSize = SrcTy->getPrimitiveSizeInBits(); unsigned DestBitSize = DestTy->getPrimitiveSizeInBits(); @@ -747,6 +751,8 @@ Assert1(SrcTy->isIntOrIntVector(), "SExt only operates on integer", &I); Assert1(DestTy->isIntOrIntVector(), "SExt only produces an integer", &I); + Assert1(isa(SrcTy) == isa(DestTy), + "sext source and destination must both be a vector or neither", &I); Assert1(SrcBitSize < DestBitSize,"Type too small for SExt", &I); visitInstruction(I); @@ -762,6 +768,8 @@ Assert1(SrcTy->isFPOrFPVector(),"FPTrunc only operates on FP", &I); Assert1(DestTy->isFPOrFPVector(),"FPTrunc only produces an FP", &I); + Assert1(isa(SrcTy) == isa(DestTy), + "fptrunc source and destination must both be a vector or neither",&I); Assert1(SrcBitSize > DestBitSize,"DestTy too big for FPTrunc", &I); visitInstruction(I); @@ -778,6 +786,8 @@ Assert1(SrcTy->isFPOrFPVector(),"FPExt only operates on FP", &I); Assert1(DestTy->isFPOrFPVector(),"FPExt only produces an FP", &I); + Assert1(isa(SrcTy) == isa(DestTy), + "fpext source and destination must both be a vector or neither", &I); Assert1(SrcBitSize < DestBitSize,"DestTy too small for FPExt", &I); visitInstruction(I); From nicholas at mxc.ca Mon Feb 2 01:59:39 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 2 Feb 2009 01:59:39 -0600 Subject: [llvm-commits] CVS: llvm-www/demo/index.cgi Message-ID: <200902020759.n127xdGo012808@zion.cs.uiuc.edu> Changes in directory llvm-www/demo: index.cgi updated: 1.92 -> 1.93 --- Log message: Update the syntax highlighting. --- Diffs of the changes: (+2 -2) index.cgi | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm-www/demo/index.cgi diff -u llvm-www/demo/index.cgi:1.92 llvm-www/demo/index.cgi:1.93 --- llvm-www/demo/index.cgi:1.92 Sun Feb 1 23:56:20 2009 +++ llvm-www/demo/index.cgi Mon Feb 2 01:58:40 2009 @@ -95,8 +95,8 @@ sub syntaxHighlightLLVM { my ($input) = @_; - $input =~ s@\b(void|i8|i1|i16|i32|i64|float|double|type|label|opaque)\b@$1@g; - $input =~ s@\b(add|sub|mul|div|rem|and|or|xor|setne|seteq|setlt|setgt|setle|setge|phi|tail|call|cast|to|shl|shr|vaarg|vanext|ret|br|switch|invoke|unwind|malloc|alloca|free|load|store|getelementptr|begin|end|true|false|declare|global|constant|const|internal|uninitialized|external|implementation|linkonce|weak|appending|null|to|except|not|target|endian|pointersize|big|little|volatile)\b@$1@g; + $input =~ s@\b(void|i\d+|float|double|x86_fp80|fp128|ppc_fp128|type|label|opaque)\b@$1@g; + $input =~ s@\b(ret|br|switch|invoke|unwind|unreachable|add|sub|mul|udiv|sdiv|fdiv|urem|srem|frem|shl|lshr|ashr|and|or|xor|extractelement|insertelement|shufflevector|extractvalue|insertvalue|malloc|free|alloca|load|store|getelementptr|trunc|zext|sext|fptrunc|fpext|fptoui|fptosi|uitofp|sitofp|ptrtoint|inttoptr|bitcast|to|icmp|fcmp|phi|select|call|va_arg|eq|ne|ugt|uge|ult|ule|sgt|sge|slt|sle|oeq|ogt|oge|olt|ole|one|ord|ueq|une|uno|tail|begin|end|true|false|declare|global|constant|const|private|internal|linkonce|common|weak|appending|extern_weak|dllimport|dllexport|ccc|fastcc|coldcc|uninitialized|external|implementation|linkonce|weak|appending|null|except|not|target|endian|pointersize|big|little|volatile|zeroinitializer|define|protected|hidden|addrspace|section|align|alias|signext|zeroext|inreg|byval|sret|noalias|nocapture|nest|gc|alwaysinline|noinline|optsize|noreturn|nounwind|readnone|readonly|ssp|sspreq|module|asm|sideeffect)\b@$1@g; # Add links to the FAQ. $input =~ s@(_ZNSt8ios_base4Init[DC]1Ev)@$1@g; From evan.cheng at apple.com Mon Feb 2 02:07:37 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 02 Feb 2009 08:07:37 -0000 Subject: [llvm-commits] [llvm] r63505 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/smul-with-overflow-3.ll Message-ID: <200902020807.n1287beu013393@zion.cs.uiuc.edu> Author: evancheng Date: Mon Feb 2 02:07:36 2009 New Revision: 63505 URL: http://llvm.org/viewvc/llvm-project?rev=63505&view=rev Log: Teach LowerBRCOND to recognize (xor (setcc x), 1). The xor inverts the condition. It's normally transformed by the dag combiner, unless the condition is set by a arithmetic op with overflow. Added: llvm/trunk/test/CodeGen/X86/smul-with-overflow-3.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=63505&r1=63504&r2=63505&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Feb 2 02:07:36 2009 @@ -5366,6 +5366,17 @@ Op.getOperand(1).hasOneUse()); } +static bool isXor1OfSetCC(SDValue Op) { + if (Op.getOpcode() != ISD::XOR) + return false; + ConstantSDNode *N1C = dyn_cast(Op.getOperand(1)); + if (N1C && N1C->getAPIntValue() == 1) { + return Op.getOperand(0).getOpcode() == X86ISD::SETCC && + Op.getOperand(0).hasOneUse(); + } + return false; +} + SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) { bool addTest = true; SDValue Chain = Op.getOperand(0); @@ -5460,6 +5471,16 @@ } } } + } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { + // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. + // It should be transformed during dag combiner except when the condition + // is set by a arithmetics with overflow node. + X86::CondCode CCode = + (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); + CCode = X86::GetOppositeBranchCondition(CCode); + CC = DAG.getConstant(CCode, MVT::i8); + Cond = Cond.getOperand(0).getOperand(1); + addTest = false; } } Added: llvm/trunk/test/CodeGen/X86/smul-with-overflow-3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/smul-with-overflow-3.ll?rev=63505&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/smul-with-overflow-3.ll (added) +++ llvm/trunk/test/CodeGen/X86/smul-with-overflow-3.ll Mon Feb 2 02:07:36 2009 @@ -0,0 +1,23 @@ +; RUN: llvm-as < %s | llc -march=x86 | grep {jno} | count 1 + + at ok = internal constant [4 x i8] c"%d\0A\00" + at no = internal constant [4 x i8] c"no\0A\00" + +define i1 @func1(i32 %v1, i32 %v2) nounwind { +entry: + %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2) + %sum = extractvalue {i32, i1} %t, 0 + %obit = extractvalue {i32, i1} %t, 1 + br i1 %obit, label %overflow, label %normal + +overflow: + %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind + ret i1 false + +normal: + %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind + ret i1 true +} + +declare i32 @printf(i8*, ...) nounwind +declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) From evan.cheng at apple.com Mon Feb 2 02:19:07 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 02 Feb 2009 08:19:07 -0000 Subject: [llvm-commits] [llvm] r63506 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200902020819.n128J7dc013896@zion.cs.uiuc.edu> Author: evancheng Date: Mon Feb 2 02:19:07 2009 New Revision: 63506 URL: http://llvm.org/viewvc/llvm-project?rev=63506&view=rev Log: Add comment. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=63506&r1=63505&r2=63506&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Feb 2 02:19:07 2009 @@ -5366,6 +5366,8 @@ Op.getOperand(1).hasOneUse()); } +// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and +// 1 and that the SETCC node has a single use. static bool isXor1OfSetCC(SDValue Op) { if (Op.getOpcode() != ISD::XOR) return false; From baldrick at free.fr Mon Feb 2 03:07:13 2009 From: baldrick at free.fr (Duncan Sands) Date: Mon, 02 Feb 2009 09:07:13 -0000 Subject: [llvm-commits] [llvm] r63507 - /llvm/trunk/test/FrontendC/x86-64-red-zone.c Message-ID: <200902020907.n1297EJp024943@zion.cs.uiuc.edu> Author: baldrick Date: Mon Feb 2 03:07:13 2009 New Revision: 63507 URL: http://llvm.org/viewvc/llvm-project?rev=63507&view=rev Log: Make the XFAIL line actually match x86-32 targets. Modified: llvm/trunk/test/FrontendC/x86-64-red-zone.c Modified: llvm/trunk/test/FrontendC/x86-64-red-zone.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/x86-64-red-zone.c?rev=63507&r1=63506&r2=63507&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/x86-64-red-zone.c (original) +++ llvm/trunk/test/FrontendC/x86-64-red-zone.c Mon Feb 2 03:07:13 2009 @@ -6,6 +6,6 @@ // RUN: grep subq %t | count 1 // RUN: grep addq %t | count 1 // This is a test for x86-64, add your target below if it FAILs. -// XFAIL: alpha|ia64|arm|powerpc|sparc|x86 +// XFAIL: alpha|ia64|arm|powerpc|sparc|i.86 long double f0(float f) { return f; } From baldrick at free.fr Mon Feb 2 03:10:57 2009 From: baldrick at free.fr (Duncan Sands) Date: Mon, 02 Feb 2009 09:10:57 -0000 Subject: [llvm-commits] [llvm] r63508 - /llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp Message-ID: <200902020910.n129AvjA025479@zion.cs.uiuc.edu> Author: baldrick Date: Mon Feb 2 03:10:57 2009 New Revision: 63508 URL: http://llvm.org/viewvc/llvm-project?rev=63508&view=rev Log: This passes on x86-32 linux at least. Modified: llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp Modified: llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-11-30-Pubnames.cpp?rev=63508&r1=63507&r2=63508&view=diff ============================================================================== --- llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp (original) +++ llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp Mon Feb 2 03:10:57 2009 @@ -7,7 +7,6 @@ // RUN: echo {break main\nrun\np Pubnames::pubname} > %t.in // RUN: gdb -q -batch -n -x %t.in %t.exe | tee %t.out | grep {\$1 = 10} // XFAIL: alpha|ia64|arm -// XFAIL: * struct Pubnames { static int pubname; }; From evan.cheng at apple.com Mon Feb 2 03:15:04 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 02 Feb 2009 09:15:04 -0000 Subject: [llvm-commits] [llvm] r63509 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200902020915.n129F43W025610@zion.cs.uiuc.edu> Author: evancheng Date: Mon Feb 2 03:15:04 2009 New Revision: 63509 URL: http://llvm.org/viewvc/llvm-project?rev=63509&view=rev Log: ADD / SUB / SMUL / UMUL with overflow second result top bits must be zero. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=63509&r1=63508&r2=63509&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Feb 2 03:15:04 2009 @@ -7515,6 +7515,14 @@ KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. switch (Opc) { default: break; + case X86ISD::ADD: + case X86ISD::SUB: + case X86ISD::SMUL: + case X86ISD::UMUL: + // These nodes' second result is a boolean. + if (Op.getResNo() == 0) + break; + // Fallthrough case X86ISD::SETCC: KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), Mask.getBitWidth() - 1); From baldrick at free.fr Mon Feb 2 03:53:20 2009 From: baldrick at free.fr (Duncan Sands) Date: Mon, 02 Feb 2009 09:53:20 -0000 Subject: [llvm-commits] [llvm] r63510 - /llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Message-ID: <200902020953.n129rLCQ027026@zion.cs.uiuc.edu> Author: baldrick Date: Mon Feb 2 03:53:14 2009 New Revision: 63510 URL: http://llvm.org/viewvc/llvm-project?rev=63510&view=rev Log: Fix an obvious thinko. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=63510&r1=63509&r2=63510&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Mon Feb 2 03:53:14 2009 @@ -1482,7 +1482,7 @@ SV = BinaryOperator::CreateLShr(SV, ConstantInt::get(SV->getType(),-ShAmt), SV->getName(), SI); - Mask = Mask.lshr(ShAmt); + Mask = Mask.lshr(-ShAmt); } // Mask out the bits we are about to insert from the old value, and or From baldrick at free.fr Mon Feb 2 04:06:31 2009 From: baldrick at free.fr (Duncan Sands) Date: Mon, 02 Feb 2009 10:06:31 -0000 Subject: [llvm-commits] [llvm] r63511 - /llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Message-ID: <200902021006.n12A6Y9M027654@zion.cs.uiuc.edu> Author: baldrick Date: Mon Feb 2 04:06:20 2009 New Revision: 63511 URL: http://llvm.org/viewvc/llvm-project?rev=63511&view=rev Log: Fix a comment (bytes -> bits), reformat a comment and remove trailing whitespace. No functionality change. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=63511&r1=63510&r2=63511&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Mon Feb 2 04:06:20 2009 @@ -1283,26 +1283,26 @@ void SROA::ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, uint64_t Offset) { while (!Ptr->use_empty()) { Instruction *User = cast(Ptr->use_back()); - + if (LoadInst *LI = dyn_cast(User)) { LI->replaceAllUsesWith(ConvertUsesOfLoadToScalar(LI, NewAI, Offset)); LI->eraseFromParent(); continue; } - + if (StoreInst *SI = dyn_cast(User)) { assert(SI->getOperand(0) != Ptr && "Consistency error!"); new StoreInst(ConvertUsesOfStoreToScalar(SI, NewAI, Offset), NewAI, SI); SI->eraseFromParent(); continue; } - + if (BitCastInst *CI = dyn_cast(User)) { ConvertUsesToScalar(CI, NewAI, Offset); CI->eraseFromParent(); continue; } - + if (GetElementPtrInst *GEP = dyn_cast(User)) { // Compute the offset that this GEP adds to the pointer. SmallVector Indices(GEP->op_begin()+1, GEP->op_end()); @@ -1317,19 +1317,19 @@ } } -/// ConvertUsesOfLoadToScalar - Convert all of the users the specified load to -/// use the new alloca directly, returning the value that should replace the -/// load. This happens when we are converting an "integer union" to a -/// single integer scalar, or when we are converting a "vector union" to a -/// vector with insert/extractelement instructions. +/// ConvertUsesOfLoadToScalar - Convert all of the users of the specified load +/// to use the new alloca directly, returning the value that should replace the +/// load. This happens when we are converting an "integer union" to a single +/// integer scalar, or when we are converting a "vector union" to a vector with +/// insert/extractelement instructions. /// -/// Offset is an offset from the original alloca, in bytes that need to be +/// Offset is an offset from the original alloca, in bits that need to be /// shifted to the right. By the end of this, there should be no uses of Ptr. -Value *SROA::ConvertUsesOfLoadToScalar(LoadInst *LI, AllocaInst *NewAI, +Value *SROA::ConvertUsesOfLoadToScalar(LoadInst *LI, AllocaInst *NewAI, uint64_t Offset) { // The load is a bit extract from NewAI shifted right by Offset bits. Value *NV = new LoadInst(NewAI, LI->getName(), LI); - + // If the load is of the whole new alloca, no conversion is needed. if (NV->getType() == LI->getType() && Offset == 0) return NV; @@ -1351,10 +1351,10 @@ return new ExtractElementInst(NV, ConstantInt::get(Type::Int32Ty, Elt), "tmp", LI); } - + // Otherwise, this must be a union that was converted to an integer value. const IntegerType *NTy = cast(NV->getType()); - + // If this is a big-endian system and the load is narrower than the // full alloca type, we need to do a shift to get the right bits. int ShAmt = 0; @@ -1367,7 +1367,7 @@ } else { ShAmt = Offset; } - + // Note: we support negative bitwidths (with shl) which are not defined. // We do this to support (f.e.) loads off the end of a structure where // only some bits are used. @@ -1379,13 +1379,13 @@ NV = BinaryOperator::CreateShl(NV, ConstantInt::get(NV->getType(), -ShAmt), LI->getName(), LI); - + // Finally, unconditionally truncate the integer to the right width. unsigned LIBitWidth = TD->getTypeSizeInBits(LI->getType()); if (LIBitWidth < NTy->getBitWidth()) NV = new TruncInst(NV, IntegerType::get(LIBitWidth), LI->getName(), LI); - + // If the result is an integer, this is a trunc or bitcast. if (isa(LI->getType())) { // Should be done. @@ -1410,9 +1410,9 @@ /// /// Offset is an offset from the original alloca, in bits that need to be /// shifted to the right. By the end of this, there should be no uses of Ptr. -Value *SROA::ConvertUsesOfStoreToScalar(StoreInst *SI, AllocaInst *NewAI, +Value *SROA::ConvertUsesOfStoreToScalar(StoreInst *SI, AllocaInst *NewAI, uint64_t Offset) { - + // Convert the stored type to the actual type, shift it left to insert // then 'or' into place. Value *SV = SI->getOperand(0); @@ -1420,10 +1420,10 @@ if (SV->getType() == AllocaType && Offset == 0) { return SV; } - + if (const VectorType *VTy = dyn_cast(AllocaType)) { Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", SI); - + // If the result alloca is a vector type, this is either an element // access or a bitcast to another vector type. if (isa(SV->getType())) { @@ -1437,10 +1437,10 @@ } return SV; } - - + + Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", SI); - + // If SV is a float, convert it to the appropriate integer type. // If it is a pointer, do the same, and also handle ptr->ptr casts // here. @@ -1452,11 +1452,11 @@ SV = new BitCastInst(SV, IntegerType::get(SrcWidth), SV->getName(), SI); else if (isa(SV->getType())) SV = new PtrToIntInst(SV, TD->getIntPtrType(), SV->getName(), SI); - + // Always zero extend the value if needed. if (SV->getType() != AllocaType) SV = new ZExtInst(SV, AllocaType, SV->getName(), SI); - + // If this is a big-endian system and the store is narrower than the // full alloca type, we need to do a shift to get the right bits. int ShAmt = 0; @@ -1468,13 +1468,13 @@ } else { ShAmt = Offset; } - + // Note: we support negative bitwidths (with shr) which are not defined. // We do this to support (f.e.) stores off the end of a structure where // only some bits in the structure are set. APInt Mask(APInt::getLowBitsSet(DestWidth, SrcWidth)); if (ShAmt > 0 && (unsigned)ShAmt < DestWidth) { - SV = BinaryOperator::CreateShl(SV, + SV = BinaryOperator::CreateShl(SV, ConstantInt::get(SV->getType(), ShAmt), SV->getName(), SI); Mask <<= ShAmt; @@ -1484,7 +1484,7 @@ SV->getName(), SI); Mask = Mask.lshr(-ShAmt); } - + // Mask out the bits we are about to insert from the old value, and or // in the new bits. if (SrcWidth != DestWidth) { From edwintorok at gmail.com Mon Feb 2 04:07:07 2009 From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=) Date: Mon, 02 Feb 2009 12:07:07 +0200 Subject: [llvm-commits] [llvm] r63090 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/smul-with-overflow-2.ll In-Reply-To: <200901270330.n0R3UgVN005529@zion.cs.uiuc.edu> References: <200901270330.n0R3UgVN005529@zion.cs.uiuc.edu> Message-ID: <4986C5CB.5070204@gmail.com> On 2009-01-27 05:30, Evan Cheng wrote: > Author: evancheng > Date: Mon Jan 26 21:30:42 2009 > New Revision: 63090 > > URL: http://llvm.org/viewvc/llvm-project?rev=63090&view=rev > Log: > Implement multiple with overflow by 2 with an add instruction. > > + %tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 2) > On 2008-12-03 04:43, Bill Wendling wrote: > Author: void > Date: Tue Dec 2 20:43:12 2008 > New Revision: 60460 > > URL: http://llvm.org/viewvc/llvm-project?rev=60460&view=rev > Log: > Change label to 'carry' for unsigned adds. > %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2) What are the semantics of llvm.OP.with.overflow intrinsics that I keep seeing lately? LangRef makes no mention of them. For example how does llvm.uadd.with.overflow differ from a simple add? According to LangRef overflow is defined for add: "If an integer sum has unsigned overflow, the result returned is the mathematical result modulo 2^n , where n is the bit width of the result" Best regards, --Edwin From sanjiv.gupta at microchip.com Mon Feb 2 10:53:06 2009 From: sanjiv.gupta at microchip.com (Sanjiv Gupta) Date: Mon, 02 Feb 2009 16:53:06 -0000 Subject: [llvm-commits] [llvm] r63521 - in /llvm/trunk: include/llvm/Target/TargetAsmInfo.h lib/Target/PIC16/PIC16TargetAsmInfo.cpp lib/Target/PIC16/PIC16TargetAsmInfo.h Message-ID: <200902021653.n12Gr7nn009604@zion.cs.uiuc.edu> Author: sgupta Date: Mon Feb 2 10:53:06 2009 New Revision: 63521 URL: http://llvm.org/viewvc/llvm-project?rev=63521&view=rev Log: Made the common case of default address space directive as non-virtual for performance reasons. Provide a single virtual interface for directives of all sizes in non-default address spaces. Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.cpp llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.h Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=63521&r1=63520&r2=63521&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Mon Feb 2 10:53:06 2009 @@ -298,6 +298,15 @@ const char *Data32bitsDirective; // Defaults to "\t.long\t" const char *Data64bitsDirective; // Defaults to "\t.quad\t" + /// getASDirective - Targets can override it to provide different data + /// directives for various sizes and non-default address spaces. + virtual const char *getASDirective(unsigned size, + unsigned AS) const { + assert (AS > 0 + && "Dont know the directives for default addr space"); + return NULL; + } + //===--- Alignment Information ----------------------------------------===// /// AlignDirective - The directive used to emit round up to an alignment @@ -600,19 +609,20 @@ // Data directive accessors // - virtual const char *getData8bitsDirective(unsigned AddrSpace = 0) const { - return Data8bitsDirective; + const char *getData8bitsDirective(unsigned AS = 0) const { + return AS == 0 ? Data8bitsDirective : getASDirective(8, AS); } - virtual const char *getData16bitsDirective(unsigned AddrSpace = 0) const { - return Data16bitsDirective; + const char *getData16bitsDirective(unsigned AS = 0) const { + return AS == 0 ? Data16bitsDirective : getASDirective(16, AS); } - virtual const char *getData32bitsDirective(unsigned AddrSpace = 0) const { - return Data32bitsDirective; + const char *getData32bitsDirective(unsigned AS = 0) const { + return AS == 0 ? Data32bitsDirective : getASDirective(32, AS); } - virtual const char *getData64bitsDirective(unsigned AddrSpace = 0) const { - return Data64bitsDirective; + const char *getData64bitsDirective(unsigned AS = 0) const { + return AS == 0 ? Data64bitsDirective : getASDirective(64, AS); } + // Accessors. // const Section *getTextSection() const { Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.cpp?rev=63521&r1=63520&r2=63521&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.cpp Mon Feb 2 10:53:06 2009 @@ -26,7 +26,7 @@ Data32bitsDirective = " dl "; RomData8bitsDirective = " dw "; RomData16bitsDirective = " rom_di "; - RomData8bitsDirective = " rom_dl "; + RomData32bitsDirective = " rom_dl "; ZeroDirective = NULL; AsciiDirective = " dt "; AscizDirective = NULL; @@ -37,27 +37,24 @@ SwitchToSectionDirective = ""; } -const char *PIC16TargetAsmInfo::getData8bitsDirective(unsigned AddrSpace) - const { - if (AddrSpace == PIC16ISD::ROM_SPACE) - return RomData8bitsDirective; - else - return Data8bitsDirective; - } +const char *PIC16TargetAsmInfo::getRomDirective(unsigned size) const +{ + if (size == 8) + return RomData8bitsDirective; + else if (size == 16) + return RomData16bitsDirective; + else if (size == 32) + return RomData32bitsDirective; + else + return NULL; +} -const char *PIC16TargetAsmInfo::getData16bitsDirective(unsigned AddrSpace) - const { - if (AddrSpace == PIC16ISD::ROM_SPACE) - return RomData16bitsDirective; - else - return Data16bitsDirective; - } -const char *PIC16TargetAsmInfo::getData32bitsDirective(unsigned AddrSpace) - const { - if (AddrSpace == PIC16ISD::ROM_SPACE) - return RomData32bitsDirective; - else - return Data32bitsDirective; - } +const char *PIC16TargetAsmInfo::getASDirective(unsigned size, + unsigned AS) const { + if (AS == PIC16ISD::ROM_SPACE) + return getRomDirective(size); + else + return NULL; +} Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.h?rev=63521&r1=63520&r2=63521&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.h (original) +++ llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.h Mon Feb 2 10:53:06 2009 @@ -23,13 +23,12 @@ struct PIC16TargetAsmInfo : public TargetAsmInfo { PIC16TargetAsmInfo(const PIC16TargetMachine &TM); + private: const char *RomData8bitsDirective; const char *RomData16bitsDirective; const char *RomData32bitsDirective; - public : - virtual const char *getData8bitsDirective(unsigned AddrSpace = 0) const; - virtual const char *getData16bitsDirective(unsigned AddrSpace = 0) const; - virtual const char *getData32bitsDirective(unsigned AddrSpace = 0) const; + const char *getRomDirective(unsigned size) const; + virtual const char *getASDirective(unsigned size, unsigned AS) const; }; } // namespace llvm From sanjiv.gupta at microchip.com Mon Feb 2 11:19:39 2009 From: sanjiv.gupta at microchip.com (Sanjiv Gupta) Date: Mon, 02 Feb 2009 17:19:39 -0000 Subject: [llvm-commits] [llvm] r63523 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeIntegerTypes.cpp LegalizeTypes.h Message-ID: <200902021719.n12HJdSi010581@zion.cs.uiuc.edu> Author: sgupta Date: Mon Feb 2 11:19:39 2009 New Revision: 63523 URL: http://llvm.org/viewvc/llvm-project?rev=63523&view=rev Log: Duncan's patch. Further to 64382. Takes care of illegal types for shift amount. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=63523&r1=63522&r2=63523&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon Feb 2 11:19:39 2009 @@ -684,6 +684,12 @@ case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break; case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; + + case ISD::SHL: + case ISD::SRA: + case ISD::SRL: + case ISD::ROTL: + case ISD::ROTR: Res = PromoteIntOp_Shift(N); break; } // If the result is null, the sub-method took care of registering results etc. @@ -890,6 +896,11 @@ return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2)); } +SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) { + return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), + ZExtPromotedInteger(N->getOperand(1))); +} + SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { SDValue Op = GetPromotedInteger(N->getOperand(0)); DebugLoc dl = N->getDebugLoc(); @@ -1935,6 +1946,12 @@ case ISD::STORE: Res = ExpandIntOp_STORE(cast(N), OpNo); break; case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; + + case ISD::SHL: + case ISD::SRA: + case ISD::SRL: + case ISD::ROTL: + case ISD::ROTR: Res = ExpandIntOp_Shift(N); break; } // If the result is null, the sub-method took care of registering results etc. @@ -2108,6 +2125,15 @@ DAG.getCondCode(CCCode)); } +SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) { + // The value being shifted is legal, but the shift amount is too big. + // It follows that either the result of the shift is undefined, or the + // upper half of the shift amount is zero. Just use the lower half. + SDValue Lo, Hi; + GetExpandedInteger(N->getOperand(1), Lo, Hi); + return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo); +} + SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { SDValue Op = N->getOperand(0); MVT DstVT = N->getValueType(0); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=63523&r1=63522&r2=63523&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Mon Feb 2 11:19:39 2009 @@ -293,6 +293,7 @@ SDValue PromoteIntOp_SELECT(SDNode *N, unsigned OpNo); SDValue PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo); SDValue PromoteIntOp_SETCC(SDNode *N, unsigned OpNo); + SDValue PromoteIntOp_Shift(SDNode *N); SDValue PromoteIntOp_SIGN_EXTEND(SDNode *N); SDValue PromoteIntOp_SINT_TO_FP(SDNode *N); SDValue PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo); @@ -356,6 +357,7 @@ SDValue ExpandIntOp_EXTRACT_ELEMENT(SDNode *N); SDValue ExpandIntOp_SELECT_CC(SDNode *N); SDValue ExpandIntOp_SETCC(SDNode *N); + SDValue ExpandIntOp_Shift(SDNode *N); SDValue ExpandIntOp_SINT_TO_FP(SDNode *N); SDValue ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo); SDValue ExpandIntOp_TRUNCATE(SDNode *N); From dpatel at apple.com Mon Feb 2 11:50:44 2009 From: dpatel at apple.com (Devang Patel) Date: Mon, 02 Feb 2009 17:50:44 -0000 Subject: [llvm-commits] [llvm] r63526 - /llvm/trunk/test/DebugInfo/2009-01-28-ArrayType.ll Message-ID: <200902021750.n12Hoi8c011972@zion.cs.uiuc.edu> Author: dpatel Date: Mon Feb 2 11:50:43 2009 New Revision: 63526 URL: http://llvm.org/viewvc/llvm-project?rev=63526&view=rev Log: Make this test case smaller. Modified: llvm/trunk/test/DebugInfo/2009-01-28-ArrayType.ll Modified: llvm/trunk/test/DebugInfo/2009-01-28-ArrayType.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2009-01-28-ArrayType.ll?rev=63526&r1=63525&r2=63526&view=diff ============================================================================== --- llvm/trunk/test/DebugInfo/2009-01-28-ArrayType.ll (original) +++ llvm/trunk/test/DebugInfo/2009-01-28-ArrayType.ll Mon Feb 2 11:50:43 2009 @@ -1,93 +1,23 @@ -; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin | grep 0x49 | count 7 +; RUN: llvm-as < %s | llc | grep 0x49 | count 3 ; Count number of DW_AT_Type attributes. +target triple = "i386-apple-darwin*" %llvm.dbg.anchor.type = type { i32, i32 } - %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32, i8*, i8* } - %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i8* } - %llvm.dbg.composite.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, { }*, i8*, i8* } - %llvm.dbg.derivedtype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, i8*, i8* } - %llvm.dbg.subprogram.type = type { i32, { }*, { }*, i8*, i8*, i8*, { }*, i32, { }*, i1, i1, i8*, i8* } + %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 } + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } + %llvm.dbg.composite.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, { }* } + %llvm.dbg.global_variable.type = type { i32, { }*, { }*, i8*, i8*, i8*, { }*, i32, { }*, i1, i1, { }* } %llvm.dbg.subrange.type = type { i32, i64, i64 } - %llvm.dbg.variable.type = type { i32, { }*, i8*, { }*, i32, { }*, i8*, i8* } @llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] - at .str = internal constant [4 x i8] c"a.c\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at .str = internal constant [8 x i8] c"array.c\00", section "llvm.metadata" ; <[8 x i8]*> [#uses=1] @.str1 = internal constant [26 x i8] c"/Volumes/Nanpura/dbg.test\00", section "llvm.metadata" ; <[26 x i8]*> [#uses=1] @.str2 = internal constant [52 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build)\00", section "llvm.metadata" ; <[52 x i8]*> [#uses=1] - at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([52 x i8]* @.str2, i32 0, i32 0), i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] + at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([8 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([52 x i8]* @.str2, i32 0, i32 0), i1 true, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] + at c = common global [3 x i32] zeroinitializer ; <[3 x i32]*> [#uses=1] + at llvm.dbg.subrange = internal constant %llvm.dbg.subrange.type { i32 458785, i64 0, i64 2 }, section "llvm.metadata" ; <%llvm.dbg.subrange.type*> [#uses=1] + at llvm.dbg.array = internal constant [1 x { }*] [ { }* bitcast (%llvm.dbg.subrange.type* @llvm.dbg.subrange to { }*) ], section "llvm.metadata" ; <[1 x { }*]*> [#uses=1] @.str3 = internal constant [4 x i8] c"int\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] - at llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, i32 5, i8* null, i8* null }, section "llvm.metadata" ; <%llvm.dbg.basictype.type*> [#uses=1] - at .str4 = internal constant [5 x i8] c"char\00", section "llvm.metadata" ; <[5 x i8]*> [#uses=1] - at llvm.dbg.basictype5 = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([5 x i8]* @.str4, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 8, i64 8, i64 0, i32 0, i32 6, i8* null, i8* null }, section "llvm.metadata" ; <%llvm.dbg.basictype.type*> [#uses=1] - at llvm.dbg.derivedtype = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype5 to { }*), i8* null, i8* null }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] - at llvm.dbg.derivedtype6 = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*), i8* null, i8* null }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] - at llvm.dbg.array = internal constant [3 x { }*] [ { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype6 to { }*) ], section "llvm.metadata" ; <[3 x { }*]*> [#uses=1] - at llvm.dbg.composite = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array to { }*), i8* null, i8* null }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] - at llvm.dbg.subprograms = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 46 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] - at .str7 = internal constant [5 x i8] c"main\00", section "llvm.metadata" ; <[5 x i8]*> [#uses=1] - at llvm.dbg.subprogram = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([5 x i8]* @.str7, i32 0, i32 0), i8* getelementptr ([5 x i8]* @.str7, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 3, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite to { }*), i1 false, i1 true, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0) }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] - at .str8 = internal constant [5 x i8] c"argc\00", section "llvm.metadata" ; <[5 x i8]*> [#uses=1] - at llvm.dbg.variable = internal constant %llvm.dbg.variable.type { i32 459009, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([5 x i8]* @.str8, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 2, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=1] - at .str9 = internal constant [5 x i8] c"argv\00", section "llvm.metadata" ; <[5 x i8]*> [#uses=1] - at llvm.dbg.variable10 = internal constant %llvm.dbg.variable.type { i32 459009, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([5 x i8]* @.str9, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 2, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype6 to { }*), i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=1] - at llvm.dbg.subrange = internal constant %llvm.dbg.subrange.type { i32 458785, i64 0, i64 5 }, section "llvm.metadata" ; <%llvm.dbg.subrange.type*> [#uses=1] - at llvm.dbg.array11 = internal constant [1 x { }*] [ { }* bitcast (%llvm.dbg.subrange.type* @llvm.dbg.subrange to { }*) ], section "llvm.metadata" ; <[1 x { }*]*> [#uses=1] - at llvm.dbg.composite12 = internal constant %llvm.dbg.composite.type { i32 458753, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 48, i64 8, i64 0, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype5 to { }*), { }* bitcast ([1 x { }*]* @llvm.dbg.array11 to { }*), i8* null, i8* null }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] - at .str13 = internal constant [5 x i8] c"str1\00", section "llvm.metadata" ; <[5 x i8]*> [#uses=1] - at llvm.dbg.variable14 = internal constant %llvm.dbg.variable.type { i32 459008, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([5 x i8]* @.str13, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 4, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite12 to { }*), i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([26 x i8]* @.str1, i32 0, i32 0) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=1] -@"\01LC" = internal constant [6 x i8] c"a.out\00" ; <[6 x i8]*> [#uses=6] - -define i32 @main(i32 %argc, i8** %argv) nounwind { -entry: - %argc_addr = alloca i32 ; [#uses=2] - %argv_addr = alloca i8** ; [#uses=2] - %retval = alloca i32 ; [#uses=2] - %str1 = alloca [6 x i8] ; <[6 x i8]*> [#uses=7] - %0 = alloca i32 ; [#uses=2] - %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call void @llvm.dbg.func.start({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*)) - %1 = bitcast i32* %argc_addr to { }* ; <{ }*> [#uses=1] - call void @llvm.dbg.declare({ }* %1, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable to { }*)) - store i32 %argc, i32* %argc_addr - %2 = bitcast i8*** %argv_addr to { }* ; <{ }*> [#uses=1] - call void @llvm.dbg.declare({ }* %2, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable10 to { }*)) - store i8** %argv, i8*** %argv_addr - %3 = bitcast [6 x i8]* %str1 to { }* ; <{ }*> [#uses=1] - call void @llvm.dbg.declare({ }* %3, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable14 to { }*)) - call void @llvm.dbg.stoppoint(i32 4, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) - %4 = getelementptr [6 x i8]* %str1, i32 0, i32 0 ; [#uses=1] - %5 = load i8* getelementptr ([6 x i8]* @"\01LC", i32 0, i32 0), align 1 ; [#uses=1] - store i8 %5, i8* %4, align 1 - %6 = getelementptr [6 x i8]* %str1, i32 0, i32 1 ; [#uses=1] - %7 = load i8* getelementptr ([6 x i8]* @"\01LC", i32 0, i32 1), align 1 ; [#uses=1] - store i8 %7, i8* %6, align 1 - %8 = getelementptr [6 x i8]* %str1, i32 0, i32 2 ; [#uses=1] - %9 = load i8* getelementptr ([6 x i8]* @"\01LC", i32 0, i32 2), align 1 ; [#uses=1] - store i8 %9, i8* %8, align 1 - %10 = getelementptr [6 x i8]* %str1, i32 0, i32 3 ; [#uses=1] - %11 = load i8* getelementptr ([6 x i8]* @"\01LC", i32 0, i32 3), align 1 ; [#uses=1] - store i8 %11, i8* %10, align 1 - %12 = getelementptr [6 x i8]* %str1, i32 0, i32 4 ; [#uses=1] - %13 = load i8* getelementptr ([6 x i8]* @"\01LC", i32 0, i32 4), align 1 ; [#uses=1] - store i8 %13, i8* %12, align 1 - %14 = getelementptr [6 x i8]* %str1, i32 0, i32 5 ; [#uses=1] - %15 = load i8* getelementptr ([6 x i8]* @"\01LC", i32 0, i32 5), align 1 ; [#uses=1] - store i8 %15, i8* %14, align 1 - call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) - store i32 0, i32* %0, align 4 - %16 = load i32* %0, align 4 ; [#uses=1] - store i32 %16, i32* %retval, align 4 - br label %return - -return: ; preds = %entry - %retval1 = load i32* %retval ; [#uses=1] - call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) - call void @llvm.dbg.region.end({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*)) - ret i32 %retval1 -} - -declare void @llvm.dbg.func.start({ }*) nounwind - -declare void @llvm.dbg.declare({ }*, { }*) nounwind - -declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind - -declare void @llvm.dbg.region.end({ }*) nounwind + at llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, i32 5 }, section "llvm.metadata" ; <%llvm.dbg.basictype.type*> [#uses=1] + at llvm.dbg.composite = internal constant %llvm.dbg.composite.type { i32 458753, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 96, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast ([1 x { }*]* @llvm.dbg.array to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at llvm.dbg.global_variables = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 52 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] + at .str4 = internal constant [2 x i8] c"c\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1] + at llvm.dbg.global_variable = internal constant %llvm.dbg.global_variable.type { i32 458804, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.global_variables to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([2 x i8]* @.str4, i32 0, i32 0), i8* getelementptr ([2 x i8]* @.str4, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 2, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite to { }*), i1 false, i1 true, { }* bitcast ([3 x i32]* @c to { }*) }, section "llvm.metadata" ; <%llvm.dbg.global_variable.type*> [#uses=0] From dpatel at apple.com Mon Feb 2 11:51:42 2009 From: dpatel at apple.com (Devang Patel) Date: Mon, 02 Feb 2009 17:51:42 -0000 Subject: [llvm-commits] [llvm] r63527 - in /llvm/trunk: lib/CodeGen/AsmPrinter/DwarfWriter.cpp test/DebugInfo/2009-01-30-Method.ll Message-ID: <200902021751.n12HpgJd012009@zion.cs.uiuc.edu> Author: dpatel Date: Mon Feb 2 11:51:41 2009 New Revision: 63527 URL: http://llvm.org/viewvc/llvm-project?rev=63527&view=rev Log: Do not add redundant arguments in a method definition DIE. Added: llvm/trunk/test/DebugInfo/2009-01-30-Method.ll Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=63527&r1=63526&r2=63527&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Mon Feb 2 11:51:41 2009 @@ -1914,18 +1914,20 @@ // Add Return Type. if (!IsConstructor) AddType(DW_Unit, SPDie, DIType(Args.getElement(0).getGV())); - - // Add arguments. - if (!Args.isNull()) - for (unsigned i = 1, N = Args.getNumElements(); i < N; ++i) { - DIE *Arg = new DIE(DW_TAG_formal_parameter); - AddType(DW_Unit, Arg, DIType(Args.getElement(i).getGV())); - AddUInt(Arg, DW_AT_artificial, DW_FORM_flag, 1); // ??? - SPDie->AddChild(Arg); - } - if (!SP.isDefinition()) - AddUInt(SPDie, DW_AT_declaration, DW_FORM_flag, 1); + if (!SP.isDefinition()) { + AddUInt(SPDie, DW_AT_declaration, DW_FORM_flag, 1); + // Add arguments. + // Do not add arguments for subprogram definition. They will be + // handled through RecordVariable. + if (!Args.isNull()) + for (unsigned i = 1, N = Args.getNumElements(); i < N; ++i) { + DIE *Arg = new DIE(DW_TAG_formal_parameter); + AddType(DW_Unit, Arg, DIType(Args.getElement(i).getGV())); + AddUInt(Arg, DW_AT_artificial, DW_FORM_flag, 1); // ??? + SPDie->AddChild(Arg); + } + } if (!SP.isLocalToUnit()) AddUInt(SPDie, DW_AT_external, DW_FORM_flag, 1); @@ -2856,6 +2858,11 @@ DIE *&Slot = Unit->getDieMapSlotFor(SP.getGV()); if (Slot) continue; + if (!SP.isDefinition()) + // This is a method declaration which will be handled while + // constructing class type. + continue; + DIE *SubprogramDie = CreateSubprogramDIE(Unit, SP); //Add to map. Added: llvm/trunk/test/DebugInfo/2009-01-30-Method.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2009-01-30-Method.ll?rev=63527&view=auto ============================================================================== --- llvm/trunk/test/DebugInfo/2009-01-30-Method.ll (added) +++ llvm/trunk/test/DebugInfo/2009-01-30-Method.ll Mon Feb 2 11:51:41 2009 @@ -0,0 +1,103 @@ +; RUN: llvm-as < %s | llc | grep "\\"foo" | count 3 +; 1 declaration, 1 definition and 1 pubnames entry. +target triple = "i386-apple-darwin*" + %llvm.dbg.anchor.type = type { i32, i32 } + %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 } + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } + %llvm.dbg.composite.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, { }* } + %llvm.dbg.derivedtype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }* } + %llvm.dbg.subprogram.type = type { i32, { }*, { }*, i8*, i8*, i8*, { }*, i32, { }*, i1, i1 } + %llvm.dbg.variable.type = type { i32, { }*, i8*, { }*, i32, { }* } + %struct.Fibonancci = type { i32 } + at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] + at .str = internal constant [10 x i8] c"method.cc\00", section "llvm.metadata" ; <[10 x i8]*> [#uses=1] + at .str1 = internal constant [64 x i8] c"/Volumes/Nanpura/mainline/llvmgcc42.build/gcc/../../../dbg.test\00", section "llvm.metadata" ; <[64 x i8]*> [#uses=1] + at .str2 = internal constant [52 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build)\00", section "llvm.metadata" ; <[52 x i8]*> [#uses=1] + at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 4, i8* getelementptr ([10 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([64 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([52 x i8]* @.str2, i32 0, i32 0), i1 true, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] + at .str3 = internal constant [11 x i8] c"Fibonancci\00", section "llvm.metadata" ; <[11 x i8]*> [#uses=1] + at .str4 = internal constant [4 x i8] c"int\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str4, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, i32 5 }, section "llvm.metadata" ; <%llvm.dbg.basictype.type*> [#uses=1] + at .str5 = internal constant [2 x i8] c"N\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1] + at llvm.dbg.derivedtype = internal constant %llvm.dbg.derivedtype.type { i32 458765, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([2 x i8]* @.str5, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 5, i64 32, i64 32, i64 0, i32 1, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.derivedtype6 = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite11 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.array = internal constant [3 x { }*] [ { }* null, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype6 to { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) ], section "llvm.metadata" ; <[3 x { }*]*> [#uses=1] + at llvm.dbg.composite7 = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at llvm.dbg.subprograms = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 46 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] + at .str8 = internal constant [4 x i8] c"foo\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at .str9 = internal constant [22 x i8] c"_ZN10Fibonancci3fooEi\00", section "llvm.metadata" ; <[22 x i8]*> [#uses=1] + at llvm.dbg.subprogram = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str8, i32 0, i32 0), i8* getelementptr ([4 x i8]* @.str8, i32 0, i32 0), i8* getelementptr ([22 x i8]* @.str9, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 10, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite7 to { }*), i1 false, i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at llvm.dbg.array10 = internal constant [2 x { }*] [ { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*), { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*) ], section "llvm.metadata" ; <[2 x { }*]*> [#uses=1] + at llvm.dbg.composite11 = internal constant %llvm.dbg.composite.type { i32 458771, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([11 x i8]* @.str3, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 3, i64 32, i64 32, i64 0, i32 0, { }* null, { }* bitcast ([2 x { }*]* @llvm.dbg.array10 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at llvm.dbg.derivedtype12 = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite11 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.array13 = internal constant [3 x { }*] [ { }* null, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype12 to { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) ], section "llvm.metadata" ; <[3 x { }*]*> [#uses=1] + at llvm.dbg.composite = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array13 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at llvm.dbg.subprogram14 = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str8, i32 0, i32 0), i8* getelementptr ([4 x i8]* @.str8, i32 0, i32 0), i8* getelementptr ([22 x i8]* @.str9, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 10, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite to { }*), i1 false, i1 true }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at llvm.dbg.derivedtype15 = internal constant %llvm.dbg.derivedtype.type { i32 458790, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype12 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at .str16 = internal constant [5 x i8] c"this\00", section "llvm.metadata" ; <[5 x i8]*> [#uses=1] + at llvm.dbg.variable = internal constant %llvm.dbg.variable.type { i32 459009, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram14 to { }*), i8* getelementptr ([5 x i8]* @.str16, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 10, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype15 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=1] + at .str17 = internal constant [2 x i8] c"i\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1] + at llvm.dbg.variable18 = internal constant %llvm.dbg.variable.type { i32 459009, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram14 to { }*), i8* getelementptr ([2 x i8]* @.str17, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 10, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=1] + at llvm.dbg.array19 = internal constant [1 x { }*] [ { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) ], section "llvm.metadata" ; <[1 x { }*]*> [#uses=1] + at llvm.dbg.composite20 = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([1 x { }*]* @llvm.dbg.array19 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at .str21 = internal constant [5 x i8] c"main\00", section "llvm.metadata" ; <[5 x i8]*> [#uses=1] + at llvm.dbg.subprogram22 = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([5 x i8]* @.str21, i32 0, i32 0), i8* getelementptr ([5 x i8]* @.str21, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 14, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite20 to { }*), i1 false, i1 true }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at .str23 = internal constant [4 x i8] c"fib\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at llvm.dbg.variable24 = internal constant %llvm.dbg.variable.type { i32 459008, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram22 to { }*), i8* getelementptr ([4 x i8]* @.str23, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 15, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite11 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=1] + +define void @_ZN10Fibonancci3fooEi(%struct.Fibonancci* %this, i32 %i) nounwind { +entry: + %this_addr = alloca %struct.Fibonancci* ; <%struct.Fibonancci**> [#uses=3] + %i_addr = alloca i32 ; [#uses=3] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + call void @llvm.dbg.func.start({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram14 to { }*)) + %0 = bitcast %struct.Fibonancci** %this_addr to { }* ; <{ }*> [#uses=1] + call void @llvm.dbg.declare({ }* %0, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable to { }*)) + store %struct.Fibonancci* %this, %struct.Fibonancci** %this_addr + %1 = bitcast i32* %i_addr to { }* ; <{ }*> [#uses=1] + call void @llvm.dbg.declare({ }* %1, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable18 to { }*)) + store i32 %i, i32* %i_addr + call void @llvm.dbg.stoppoint(i32 11, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %2 = load %struct.Fibonancci** %this_addr, align 4 ; <%struct.Fibonancci*> [#uses=1] + %3 = getelementptr %struct.Fibonancci* %2, i32 0, i32 0 ; [#uses=1] + %4 = load i32* %i_addr, align 4 ; [#uses=1] + store i32 %4, i32* %3, align 4 + call void @llvm.dbg.stoppoint(i32 12, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br label %return + +return: ; preds = %entry + call void @llvm.dbg.stoppoint(i32 12, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + call void @llvm.dbg.region.end({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram14 to { }*)) + ret void +} + +declare void @llvm.dbg.func.start({ }*) nounwind + +declare void @llvm.dbg.declare({ }*, { }*) nounwind + +declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind + +declare void @llvm.dbg.region.end({ }*) nounwind + +define i32 @main() nounwind { +entry: + %retval = alloca i32 ; [#uses=2] + %fib = alloca %struct.Fibonancci ; <%struct.Fibonancci*> [#uses=2] + %0 = alloca i32 ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + call void @llvm.dbg.func.start({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram22 to { }*)) + %1 = bitcast %struct.Fibonancci* %fib to { }* ; <{ }*> [#uses=1] + call void @llvm.dbg.declare({ }* %1, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable24 to { }*)) + call void @llvm.dbg.stoppoint(i32 16, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + call void @_ZN10Fibonancci3fooEi(%struct.Fibonancci* %fib, i32 42) nounwind + call void @llvm.dbg.stoppoint(i32 17, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + store i32 0, i32* %0, align 4 + %2 = load i32* %0, align 4 ; [#uses=1] + store i32 %2, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval1 = load i32* %retval ; [#uses=1] + call void @llvm.dbg.stoppoint(i32 17, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + call void @llvm.dbg.region.end({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram22 to { }*)) + ret i32 %retval1 +} From sabre at nondot.org Mon Feb 2 12:02:59 2009 From: sabre at nondot.org (Chris Lattner) Date: Mon, 02 Feb 2009 18:02:59 -0000 Subject: [llvm-commits] [llvm] r63529 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/2009-02-02-ScalarPromoteOutOfRange.ll Message-ID: <200902021803.n12I30pm012367@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 2 12:02:59 2009 New Revision: 63529 URL: http://llvm.org/viewvc/llvm-project?rev=63529&view=rev Log: Fix a bug which caused us to miscompile a couple of Ada tests. Thanks for the beautiful reduced testcase Duncan! Added: llvm/trunk/test/Transforms/ScalarRepl/2009-02-02-ScalarPromoteOutOfRange.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=63529&r1=63528&r2=63529&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Mon Feb 2 12:02:59 2009 @@ -1166,12 +1166,17 @@ static void MergeInType(const Type *In, uint64_t Offset, const Type *&Accum, const TargetData &TD) { // If this is our first type, just use it. - if (Accum == 0 || In == Type::VoidTy || + if ((Accum == 0 && Offset == 0) || In == Type::VoidTy || // Or if this is a same type, keep it. (In == Accum && Offset == 0)) { Accum = In; return; } + + // Merging something like i32 into offset 8 means that a "field" is merged in + // before the basic type is. Make sure to consider the offset below. + if (Accum == 0) + Accum = Type::Int8Ty; if (const VectorType *VATy = dyn_cast(Accum)) { if (VATy->getElementType() == In && Added: llvm/trunk/test/Transforms/ScalarRepl/2009-02-02-ScalarPromoteOutOfRange.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/2009-02-02-ScalarPromoteOutOfRange.ll?rev=63529&view=auto ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/2009-02-02-ScalarPromoteOutOfRange.ll (added) +++ llvm/trunk/test/Transforms/ScalarRepl/2009-02-02-ScalarPromoteOutOfRange.ll Mon Feb 2 12:02:59 2009 @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | opt -scalarrepl -instcombine | llvm-dis | grep {ret i32 %x} +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" +target triple = "i386-pc-linux-gnu" + +%pair = type { [1 x i32], i32 } + +define i32 @f(i32 %x, i32 %y) { + %instance = alloca %pair + %first = getelementptr %pair* %instance, i32 0, i32 0 + %cast = bitcast [1 x i32]* %first to i32* + store i32 %x, i32* %cast + %second = getelementptr %pair* %instance, i32 0, i32 1 + store i32 %y, i32* %second + %v = load i32* %cast + ret i32 %v +} From gohman at apple.com Mon Feb 2 12:04:24 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 02 Feb 2009 18:04:24 -0000 Subject: [llvm-commits] [llvm] r63530 - /llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Message-ID: <200902021804.n12I4OdM012422@zion.cs.uiuc.edu> Author: djg Date: Mon Feb 2 12:04:24 2009 New Revision: 63530 URL: http://llvm.org/viewvc/llvm-project?rev=63530&view=rev Log: Reposition the DebugLoc field to reduce padding space on LP64 hosts. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=63530&r1=63529&r2=63530&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Mon Feb 2 12:04:24 2009 @@ -1090,9 +1090,6 @@ /// NodeId - Unique id per SDNode in the DAG. int NodeId; - /// debugLoc - source line information. - DebugLoc debugLoc; - /// OperandList - The values that are used by this operation. /// SDUse *OperandList; @@ -1101,12 +1098,15 @@ /// define multiple values simultaneously. const MVT *ValueList; - /// NumOperands/NumValues - The number of entries in the Operand/Value list. - unsigned short NumOperands, NumValues; - /// UseList - List of uses for this SDNode. SDUse *UseList; + /// NumOperands/NumValues - The number of entries in the Operand/Value list. + unsigned short NumOperands, NumValues; + + /// debugLoc - source line information. + DebugLoc debugLoc; + /// getValueTypeList - Return a pointer to the specified value type. static const MVT *getValueTypeList(MVT VT); @@ -1353,11 +1353,12 @@ /// for new code. SDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, unsigned NumOps) : NodeType(Opc), OperandsNeedDelete(true), SubclassData(0), - NodeId(-1), debugLoc(DebugLoc::getUnknownLoc()), + NodeId(-1), OperandList(NumOps ? new SDUse[NumOps] : 0), ValueList(VTs.VTs), + UseList(NULL), NumOperands(NumOps), NumValues(VTs.NumVTs), - UseList(NULL) { + debugLoc(DebugLoc::getUnknownLoc()) { for (unsigned i = 0; i != NumOps; ++i) { OperandList[i].setUser(this); OperandList[i].setInitial(Ops[i]); @@ -1368,9 +1369,9 @@ /// set later with InitOperands. SDNode(unsigned Opc, SDVTList VTs) : NodeType(Opc), OperandsNeedDelete(false), SubclassData(0), - NodeId(-1), debugLoc(DebugLoc::getUnknownLoc()), OperandList(0), - ValueList(VTs.VTs), NumOperands(0), NumValues(VTs.NumVTs), - UseList(NULL) {} + NodeId(-1), OperandList(0), ValueList(VTs.VTs), UseList(NULL), + NumOperands(0), NumValues(VTs.NumVTs), + debugLoc(DebugLoc::getUnknownLoc()) {} /// The next two constructors specify DebugLoc explicitly; the intent /// is that they will replace the above two over time, and eventually @@ -1378,11 +1379,11 @@ SDNode(unsigned Opc, const DebugLoc dl, SDVTList VTs, const SDValue *Ops, unsigned NumOps) : NodeType(Opc), OperandsNeedDelete(true), SubclassData(0), - NodeId(-1), debugLoc(dl), + NodeId(-1), OperandList(NumOps ? new SDUse[NumOps] : 0), - ValueList(VTs.VTs), + ValueList(VTs.VTs), UseList(NULL), NumOperands(NumOps), NumValues(VTs.NumVTs), - UseList(NULL) { + debugLoc(dl) { for (unsigned i = 0; i != NumOps; ++i) { OperandList[i].setUser(this); OperandList[i].setInitial(Ops[i]); @@ -1393,9 +1394,9 @@ /// set later with InitOperands. SDNode(unsigned Opc, const DebugLoc dl, SDVTList VTs) : NodeType(Opc), OperandsNeedDelete(false), SubclassData(0), - NodeId(-1), debugLoc(dl), OperandList(0), - ValueList(VTs.VTs), NumOperands(0), NumValues(VTs.NumVTs), - UseList(NULL) {} + NodeId(-1), OperandList(0), ValueList(VTs.VTs), UseList(NULL), + NumOperands(0), NumValues(VTs.NumVTs), + debugLoc(dl) {} /// InitOperands - Initialize the operands list of this with 1 operand. void InitOperands(SDUse *Ops, const SDValue &Op0) { From sabre at nondot.org Mon Feb 2 12:12:58 2009 From: sabre at nondot.org (Chris Lattner) Date: Mon, 02 Feb 2009 18:12:58 -0000 Subject: [llvm-commits] [llvm] r63532 - /llvm/trunk/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll Message-ID: <200902021812.n12ICwmu012789@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 2 12:12:58 2009 New Revision: 63532 URL: http://llvm.org/viewvc/llvm-project?rev=63532&view=rev Log: update test Modified: llvm/trunk/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll Modified: llvm/trunk/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll?rev=63532&r1=63531&r2=63532&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll Mon Feb 2 12:12:58 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | grep {ret i32 undef} +; RUN: llvm-as < %s | opt -scalarrepl -instcombine | llvm-dis | grep {ret i32 undef} ; Test that an array is not incorrectly deconstructed. From sabre at nondot.org Mon Feb 2 12:15:33 2009 From: sabre at nondot.org (Chris Lattner) Date: Mon, 02 Feb 2009 18:15:33 -0000 Subject: [llvm-commits] [llvm] r63533 - /llvm/trunk/test/CodeGen/X86/vec_ins_extract.ll Message-ID: <200902021815.n12IFXKv012959@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 2 12:15:33 2009 New Revision: 63533 URL: http://llvm.org/viewvc/llvm-project?rev=63533&view=rev Log: xfail this for now, will fix shortly. Modified: llvm/trunk/test/CodeGen/X86/vec_ins_extract.ll Modified: llvm/trunk/test/CodeGen/X86/vec_ins_extract.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_ins_extract.ll?rev=63533&r1=63532&r2=63533&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_ins_extract.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_ins_extract.ll Mon Feb 2 12:15:33 2009 @@ -1,5 +1,6 @@ ; RUN: llvm-as < %s | opt -scalarrepl -instcombine | \ ; RUN: llc -march=x86 -mcpu=yonah | not grep sub.*esp +; XFAIL: * ; This checks that various insert/extract idiom work without going to the ; stack. From evan.cheng at apple.com Mon Feb 2 12:33:18 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 02 Feb 2009 18:33:18 -0000 Subject: [llvm-commits] [llvm] r63536 - /llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Message-ID: <200902021833.n12IXJqi013557@zion.cs.uiuc.edu> Author: evancheng Date: Mon Feb 2 12:33:18 2009 New Revision: 63536 URL: http://llvm.org/viewvc/llvm-project?rev=63536&view=rev Log: Refactor PerformPHIConstruction, no functionality changes. Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=63536&r1=63535&r2=63536&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original) +++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Mon Feb 2 12:33:18 2009 @@ -164,16 +164,24 @@ bool removeDeadSpills(SmallPtrSet& split); unsigned getNumberOfNonSpills(SmallPtrSet& MIs, unsigned Reg, int FrameIndex, bool& TwoAddr); - VNInfo* PerformPHIConstruction(MachineBasicBlock::iterator use, - MachineBasicBlock* MBB, - LiveInterval* LI, + VNInfo* PerformPHIConstruction(MachineBasicBlock::iterator Use, + MachineBasicBlock* MBB, LiveInterval* LI, SmallPtrSet& Visited, DenseMap >& Defs, DenseMap >& Uses, DenseMap& NewVNs, DenseMap& LiveOut, DenseMap& Phis, - bool toplevel, bool intrablock); + bool IsTopLevel, bool IsIntraBlock); + VNInfo* PerformPHIConstructionFallBack(MachineBasicBlock::iterator Use, + MachineBasicBlock* MBB, LiveInterval* LI, + SmallPtrSet& Visited, + DenseMap >& Defs, + DenseMap >& Uses, + DenseMap& NewVNs, + DenseMap& LiveOut, + DenseMap& Phis, + bool IsTopLevel, bool IsIntraBlock); }; } // end anonymous namespace @@ -431,83 +439,35 @@ /// PerformPHIConstruction - From properly set up use and def lists, use a PHI /// construction algorithm to compute the ranges and valnos for an interval. -VNInfo* PreAllocSplitting::PerformPHIConstruction( - MachineBasicBlock::iterator use, - MachineBasicBlock* MBB, - LiveInterval* LI, +VNInfo* +PreAllocSplitting::PerformPHIConstruction(MachineBasicBlock::iterator UseI, + MachineBasicBlock* MBB, LiveInterval* LI, SmallPtrSet& Visited, DenseMap >& Defs, DenseMap >& Uses, DenseMap& NewVNs, DenseMap& LiveOut, DenseMap& Phis, - bool toplevel, bool intrablock) { + bool IsTopLevel, bool IsIntraBlock) { // Return memoized result if it's available. - if (toplevel && Visited.count(use) && NewVNs.count(use)) - return NewVNs[use]; - else if (!toplevel && intrablock && NewVNs.count(use)) - return NewVNs[use]; - else if (!intrablock && LiveOut.count(MBB)) + if (IsTopLevel && Visited.count(UseI) && NewVNs.count(UseI)) + return NewVNs[UseI]; + else if (!IsTopLevel && IsIntraBlock && NewVNs.count(UseI)) + return NewVNs[UseI]; + else if (!IsIntraBlock && LiveOut.count(MBB)) return LiveOut[MBB]; - typedef DenseMap > RegMap; - // Check if our block contains any uses or defs. bool ContainsDefs = Defs.count(MBB); bool ContainsUses = Uses.count(MBB); - VNInfo* ret = 0; + VNInfo* RetVNI = 0; // Enumerate the cases of use/def contaning blocks. if (!ContainsDefs && !ContainsUses) { - Fallback: - // NOTE: Because this is the fallback case from other cases, we do NOT - // assume that we are not intrablock here. - if (Phis.count(MBB)) return Phis[MBB]; - - unsigned StartIndex = LIs->getMBBStartIdx(MBB); - - Phis[MBB] = ret = LI->getNextValue(~0U, /*FIXME*/ 0, - LIs->getVNInfoAllocator()); - if (!intrablock) LiveOut[MBB] = ret; - - // If there are no uses or defs between our starting point and the - // beginning of the block, then recursive perform phi construction - // on our predecessors. - DenseMap IncomingVNs; - for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(), - PE = MBB->pred_end(); PI != PE; ++PI) { - VNInfo* Incoming = PerformPHIConstruction((*PI)->end(), *PI, LI, - Visited, Defs, Uses, NewVNs, - LiveOut, Phis, false, false); - if (Incoming != 0) - IncomingVNs[*PI] = Incoming; - } - - if (MBB->pred_size() == 1 && !ret->hasPHIKill) { - LI->MergeValueNumberInto(ret, IncomingVNs.begin()->second); - Phis[MBB] = ret = IncomingVNs.begin()->second; - } else { - // Otherwise, merge the incoming VNInfos with a phi join. Create a new - // VNInfo to represent the joined value. - for (DenseMap::iterator I = - IncomingVNs.begin(), E = IncomingVNs.end(); I != E; ++I) { - I->second->hasPHIKill = true; - unsigned KillIndex = LIs->getMBBEndIdx(I->first); - if (!LiveInterval::isKill(I->second, KillIndex)) - LI->addKill(I->second, KillIndex); - } - } - - unsigned EndIndex = 0; - if (intrablock) { - EndIndex = LIs->getInstructionIndex(use); - EndIndex = LiveIntervals::getUseIndex(EndIndex); - } else - EndIndex = LIs->getMBBEndIdx(MBB); - LI->addRange(LiveRange(StartIndex, EndIndex+1, ret)); - if (intrablock) - LI->addKill(ret, EndIndex); + return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs, Uses, + NewVNs, LiveOut, Phis, + IsTopLevel, IsIntraBlock); } else if (ContainsDefs && !ContainsUses) { SmallPtrSet& BlockDefs = Defs[MBB]; @@ -515,71 +475,75 @@ // instruction we care about, go to the fallback case. Note that that // should never happen: this cannot be intrablock, so use should // always be an end() iterator. - assert(use == MBB->end() && "No use marked in intrablock"); + assert(UseI == MBB->end() && "No use marked in intrablock"); - MachineBasicBlock::iterator walker = use; - --walker; - while (walker != MBB->begin()) - if (BlockDefs.count(walker)) { + MachineBasicBlock::iterator Walker = UseI; + --Walker; + while (Walker != MBB->begin()) { + if (BlockDefs.count(Walker)) break; - } else - --walker; + --Walker; + } // Once we've found it, extend its VNInfo to our instruction. - unsigned DefIndex = LIs->getInstructionIndex(walker); + unsigned DefIndex = LIs->getInstructionIndex(Walker); DefIndex = LiveIntervals::getDefIndex(DefIndex); unsigned EndIndex = LIs->getMBBEndIdx(MBB); - ret = NewVNs[walker]; - LI->addRange(LiveRange(DefIndex, EndIndex+1, ret)); + RetVNI = NewVNs[Walker]; + LI->addRange(LiveRange(DefIndex, EndIndex+1, RetVNI)); } else if (!ContainsDefs && ContainsUses) { SmallPtrSet& BlockUses = Uses[MBB]; // Search for the use in this block that precedes the instruction we care - // about, going to the fallback case if we don't find it. + // about, going to the fallback case if we don't find it. + if (UseI == MBB->begin()) + return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs, + Uses, NewVNs, LiveOut, Phis, + IsTopLevel, IsIntraBlock); - if (use == MBB->begin()) - goto Fallback; - - MachineBasicBlock::iterator walker = use; - --walker; + MachineBasicBlock::iterator Walker = UseI; + --Walker; bool found = false; - while (walker != MBB->begin()) - if (BlockUses.count(walker)) { + while (Walker != MBB->begin()) { + if (BlockUses.count(Walker)) { found = true; break; - } else - --walker; + } + --Walker; + } // Must check begin() too. if (!found) { - if (BlockUses.count(walker)) + if (BlockUses.count(Walker)) found = true; else - goto Fallback; + return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs, + Uses, NewVNs, LiveOut, Phis, + IsTopLevel, IsIntraBlock); } - unsigned UseIndex = LIs->getInstructionIndex(walker); + unsigned UseIndex = LIs->getInstructionIndex(Walker); UseIndex = LiveIntervals::getUseIndex(UseIndex); unsigned EndIndex = 0; - if (intrablock) { - EndIndex = LIs->getInstructionIndex(use); + if (IsIntraBlock) { + EndIndex = LIs->getInstructionIndex(UseI); EndIndex = LiveIntervals::getUseIndex(EndIndex); } else EndIndex = LIs->getMBBEndIdx(MBB); // Now, recursively phi construct the VNInfo for the use we found, // and then extend it to include the instruction we care about - ret = PerformPHIConstruction(walker, MBB, LI, Visited, Defs, Uses, - NewVNs, LiveOut, Phis, false, true); + RetVNI = PerformPHIConstruction(Walker, MBB, LI, Visited, Defs, Uses, + NewVNs, LiveOut, Phis, false, true); - LI->addRange(LiveRange(UseIndex, EndIndex+1, ret)); + LI->addRange(LiveRange(UseIndex, EndIndex+1, RetVNI)); // FIXME: Need to set kills properly for inter-block stuff. - if (LI->isKill(ret, UseIndex)) LI->removeKill(ret, UseIndex); - if (intrablock) - LI->addKill(ret, EndIndex); - } else if (ContainsDefs && ContainsUses){ + if (LI->isKill(RetVNI, UseIndex)) LI->removeKill(RetVNI, UseIndex); + if (IsIntraBlock) + LI->addKill(RetVNI, EndIndex); + } else if (ContainsDefs && ContainsUses) { SmallPtrSet& BlockDefs = Defs[MBB]; SmallPtrSet& BlockUses = Uses[MBB]; @@ -587,67 +551,143 @@ // special note that checking for defs must take precedence over checking // for uses, because of two-address instructions. - if (use == MBB->begin()) - goto Fallback; + if (UseI == MBB->begin()) + return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs, Uses, + NewVNs, LiveOut, Phis, + IsTopLevel, IsIntraBlock); - MachineBasicBlock::iterator walker = use; - --walker; + MachineBasicBlock::iterator Walker = UseI; + --Walker; bool foundDef = false; bool foundUse = false; - while (walker != MBB->begin()) - if (BlockDefs.count(walker)) { + while (Walker != MBB->begin()) { + if (BlockDefs.count(Walker)) { foundDef = true; break; - } else if (BlockUses.count(walker)) { + } else if (BlockUses.count(Walker)) { foundUse = true; break; - } else - --walker; + } + --Walker; + } // Must check begin() too. if (!foundDef && !foundUse) { - if (BlockDefs.count(walker)) + if (BlockDefs.count(Walker)) foundDef = true; - else if (BlockUses.count(walker)) + else if (BlockUses.count(Walker)) foundUse = true; else - goto Fallback; + return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs, + Uses, NewVNs, LiveOut, Phis, + IsTopLevel, IsIntraBlock); } - unsigned StartIndex = LIs->getInstructionIndex(walker); + unsigned StartIndex = LIs->getInstructionIndex(Walker); StartIndex = foundDef ? LiveIntervals::getDefIndex(StartIndex) : LiveIntervals::getUseIndex(StartIndex); unsigned EndIndex = 0; - if (intrablock) { - EndIndex = LIs->getInstructionIndex(use); + if (IsIntraBlock) { + EndIndex = LIs->getInstructionIndex(UseI); EndIndex = LiveIntervals::getUseIndex(EndIndex); } else EndIndex = LIs->getMBBEndIdx(MBB); if (foundDef) - ret = NewVNs[walker]; + RetVNI = NewVNs[Walker]; else - ret = PerformPHIConstruction(walker, MBB, LI, Visited, Defs, Uses, - NewVNs, LiveOut, Phis, false, true); + RetVNI = PerformPHIConstruction(Walker, MBB, LI, Visited, Defs, Uses, + NewVNs, LiveOut, Phis, false, true); - LI->addRange(LiveRange(StartIndex, EndIndex+1, ret)); + LI->addRange(LiveRange(StartIndex, EndIndex+1, RetVNI)); - if (foundUse && LI->isKill(ret, StartIndex)) - LI->removeKill(ret, StartIndex); - if (intrablock) { - LI->addKill(ret, EndIndex); + if (foundUse && LI->isKill(RetVNI, StartIndex)) + LI->removeKill(RetVNI, StartIndex); + if (IsIntraBlock) { + LI->addKill(RetVNI, EndIndex); } } // Memoize results so we don't have to recompute them. - if (!intrablock) LiveOut[MBB] = ret; + if (!IsIntraBlock) LiveOut[MBB] = RetVNI; + else { + if (!NewVNs.count(UseI)) + NewVNs[UseI] = RetVNI; + Visited.insert(UseI); + } + + return RetVNI; +} + +/// PerformPHIConstructionFallBack - PerformPHIConstruction fall back path. +/// +VNInfo* +PreAllocSplitting::PerformPHIConstructionFallBack(MachineBasicBlock::iterator UseI, + MachineBasicBlock* MBB, LiveInterval* LI, + SmallPtrSet& Visited, + DenseMap >& Defs, + DenseMap >& Uses, + DenseMap& NewVNs, + DenseMap& LiveOut, + DenseMap& Phis, + bool IsTopLevel, bool IsIntraBlock) { + // NOTE: Because this is the fallback case from other cases, we do NOT + // assume that we are not intrablock here. + if (Phis.count(MBB)) return Phis[MBB]; + + unsigned StartIndex = LIs->getMBBStartIdx(MBB); + VNInfo *RetVNI = Phis[MBB] = LI->getNextValue(~0U, /*FIXME*/ 0, + LIs->getVNInfoAllocator()); + if (!IsIntraBlock) LiveOut[MBB] = RetVNI; + + // If there are no uses or defs between our starting point and the + // beginning of the block, then recursive perform phi construction + // on our predecessors. + DenseMap IncomingVNs; + for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(), + PE = MBB->pred_end(); PI != PE; ++PI) { + VNInfo* Incoming = PerformPHIConstruction((*PI)->end(), *PI, LI, + Visited, Defs, Uses, NewVNs, + LiveOut, Phis, false, false); + if (Incoming != 0) + IncomingVNs[*PI] = Incoming; + } + + if (MBB->pred_size() == 1 && !RetVNI->hasPHIKill) { + LI->MergeValueNumberInto(RetVNI, IncomingVNs.begin()->second); + Phis[MBB] = RetVNI = IncomingVNs.begin()->second; + } else { + // Otherwise, merge the incoming VNInfos with a phi join. Create a new + // VNInfo to represent the joined value. + for (DenseMap::iterator I = + IncomingVNs.begin(), E = IncomingVNs.end(); I != E; ++I) { + I->second->hasPHIKill = true; + unsigned KillIndex = LIs->getMBBEndIdx(I->first); + if (!LiveInterval::isKill(I->second, KillIndex)) + LI->addKill(I->second, KillIndex); + } + } + + unsigned EndIndex = 0; + if (IsIntraBlock) { + EndIndex = LIs->getInstructionIndex(UseI); + EndIndex = LiveIntervals::getUseIndex(EndIndex); + } else + EndIndex = LIs->getMBBEndIdx(MBB); + LI->addRange(LiveRange(StartIndex, EndIndex+1, RetVNI)); + if (IsIntraBlock) + LI->addKill(RetVNI, EndIndex); + + // Memoize results so we don't have to recompute them. + if (!IsIntraBlock) + LiveOut[MBB] = RetVNI; else { - if (!NewVNs.count(use)) - NewVNs[use] = ret; - Visited.insert(use); + if (!NewVNs.count(UseI)) + NewVNs[UseI] = RetVNI; + Visited.insert(UseI); } - return ret; + return RetVNI; } /// ReconstructLiveInterval - Recompute a live interval from scratch. From dalej at apple.com Mon Feb 2 13:03:57 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 02 Feb 2009 19:03:57 -0000 Subject: [llvm-commits] [llvm] r63537 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200902021903.n12J3vIW014553@zion.cs.uiuc.edu> Author: johannes Date: Mon Feb 2 13:03:57 2009 New Revision: 63537 URL: http://llvm.org/viewvc/llvm-project?rev=63537&view=rev Log: DebugLoc propagation for int<->fp conversions. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63537&r1=63536&r2=63537&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Feb 2 13:03:57 2009 @@ -282,15 +282,19 @@ SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, SDValue &Hi); - SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source); + SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl); SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT); SDValue ExpandBUILD_VECTOR(SDNode *Node); SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); - SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op); - SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT); - SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned); - SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned); + SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, + SDValue Op, DebugLoc dl); + SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT, + DebugLoc dl); + SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned, + DebugLoc dl); + SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned, + DebugLoc dl); SDValue ExpandBSWAP(SDValue Op); SDValue ExpandBitCount(unsigned Opc, SDValue Op); @@ -4004,7 +4008,7 @@ case ISD::UINT_TO_FP: { bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; Result = LegalizeINT_TO_FP(Result, isSigned, - Node->getValueType(0), Node->getOperand(0)); + Node->getValueType(0), Node->getOperand(0), dl); break; } case ISD::TRUNCATE: @@ -4063,7 +4067,8 @@ break; case TargetLowering::Promote: Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), - Node->getOpcode() == ISD::FP_TO_SINT); + Node->getOpcode() == ISD::FP_TO_SINT, + dl); break; case TargetLowering::Expand: if (Node->getOpcode() == ISD::FP_TO_UINT) { @@ -4075,15 +4080,16 @@ APInt x = APInt::getSignBit(NVT.getSizeInBits()); (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); Tmp2 = DAG.getConstantFP(apf, VT); - Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(VT), Node->getOperand(0), + Tmp3 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), + Node->getOperand(0), Tmp2, ISD::SETLT); - True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); - False = DAG.getNode(ISD::FP_TO_SINT, NVT, - DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), - Tmp2)); - False = DAG.getNode(ISD::XOR, NVT, False, + True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); + False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, + DAG.getNode(ISD::FSUB, dl, VT, + Node->getOperand(0), Tmp2)); + False = DAG.getNode(ISD::XOR, dl, NVT, False, DAG.getConstant(x, NVT)); - Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); + Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp3, True, False); break; } else { assert(0 && "Do not know how to expand FP_TO_SINT yet!"); @@ -4097,24 +4103,25 @@ // Convert ppcf128 to i32 if (OVT == MVT::ppcf128 && VT == MVT::i32) { if (Node->getOpcode() == ISD::FP_TO_SINT) { - Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, + Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128, Node->getOperand(0), DAG.getValueType(MVT::f64)); - Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result, + Result = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Result, DAG.getIntPtrConstant(1)); - Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result); + Result = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Result); } else { const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; APFloat apf = APFloat(APInt(128, 2, TwoE31)); Tmp2 = DAG.getConstantFP(apf, OVT); // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X // FIXME: generated code sucks. - Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, - DAG.getNode(ISD::ADD, MVT::i32, - DAG.getNode(ISD::FP_TO_SINT, VT, - DAG.getNode(ISD::FSUB, OVT, + Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Node->getOperand(0), + Tmp2, + DAG.getNode(ISD::ADD, dl, MVT::i32, + DAG.getNode(ISD::FP_TO_SINT, dl, VT, + DAG.getNode(ISD::FSUB, dl, OVT, Node->getOperand(0), Tmp2)), DAG.getConstant(0x80000000, MVT::i32)), - DAG.getNode(ISD::FP_TO_SINT, VT, + DAG.getNode(ISD::FP_TO_SINT, dl, VT, Node->getOperand(0)), DAG.getCondCode(ISD::SETGE)); } @@ -4601,7 +4608,7 @@ break; case Expand: Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, - Node->getOperand(0)); + Node->getOperand(0), Node->getDebugLoc()); // Round if we cannot tolerate excess precision. if (NoExcessFPPrecision) Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, @@ -5808,7 +5815,8 @@ /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation. /// SDValue SelectionDAGLegalize:: -LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) { +LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op, + DebugLoc dl) { bool isCustom = false; SDValue Tmp1; switch (getTypeAction(Op.getValueType())) { @@ -5824,7 +5832,7 @@ if (Result.getNode()) Result = DAG.UpdateNodeOperands(Result, Tmp1); else - Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, + Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl, DestTy, Tmp1); if (isCustom) { Tmp1 = TLI.LowerOperation(Result, DAG); @@ -5832,29 +5840,29 @@ } break; case TargetLowering::Expand: - Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy); + Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy, dl); break; case TargetLowering::Promote: - Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned); + Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned, dl); break; } break; case Expand: - Result = ExpandIntToFP(isSigned, DestTy, Op); + Result = ExpandIntToFP(isSigned, DestTy, Op, dl) ; break; case Promote: Tmp1 = PromoteOp(Op); if (isSigned) { - Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), + Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(), Tmp1, DAG.getValueType(Op.getValueType())); } else { - Tmp1 = DAG.getZeroExtendInReg(Tmp1, + Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, Op.getValueType()); } if (Result.getNode()) Result = DAG.UpdateNodeOperands(Result, Tmp1); else - Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, + Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl, DestTy, Tmp1); Result = LegalizeOp(Result); // The 'op' is not necessarily legal! break; @@ -5865,7 +5873,7 @@ /// ExpandIntToFP - Expand a [US]INT_TO_FP operation. /// SDValue SelectionDAGLegalize:: -ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) { +ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl) { MVT SourceVT = Source.getValueType(); bool ExpandSource = getTypeAction(SourceVT) == Expand; @@ -5877,16 +5885,18 @@ if (DestTy.getVectorNumElements() == 1) { SDValue Scalar = ScalarizeVectorOp(Source); SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned, - DestEltTy, Scalar); - return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result); + DestEltTy, Scalar, dl); + return DAG.getNode(ISD::BUILD_VECTOR, dl, DestTy, Result); } SDValue Lo, Hi; SplitVectorOp(Source, Lo, Hi); MVT SplitDestTy = MVT::getVectorVT(DestEltTy, DestTy.getVectorNumElements() / 2); - SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo); - SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi); - return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult, + SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, + Lo, dl); + SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, + Hi, dl); + return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, DestTy, LoResult, HiResult)); } @@ -5899,7 +5909,7 @@ if (ExpandSource) { SDValue Lo; ExpandOp(Source, Lo, Hi); - Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi); + Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, Lo, Hi); } else { // The comparison for the sign bit will use the entire operand. Hi = Source; @@ -5923,13 +5933,14 @@ // If this is unsigned, and not supported, first perform the conversion to // signed, then adjust the result if the sign bit is set. - SDValue SignedConv = ExpandIntToFP(true, DestTy, Source); + SDValue SignedConv = ExpandIntToFP(true, DestTy, Source, dl); - SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi.getValueType()), + SDValue SignSet = DAG.getSetCC(dl, + TLI.getSetCCResultType(Hi.getValueType()), Hi, DAG.getConstant(0, Hi.getValueType()), ISD::SETLT); SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); - SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), + SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, Four, Zero); uint64_t FF = 0x5f800000ULL; if (TLI.isLittleEndian()) FF <<= 32; @@ -5937,16 +5948,16 @@ SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); unsigned Alignment = 1 << cast(CPIdx)->getAlignment(); - CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); + CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); Alignment = std::min(Alignment, 4u); SDValue FudgeInReg; if (DestTy == MVT::f32) - FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, + FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, false, Alignment); else if (DestTy.bitsGT(MVT::f32)) // FIXME: Avoid the extend by construction the right constantpool? - FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), + FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, dl, DestTy, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, MVT::f32, false, Alignment); @@ -5959,12 +5970,12 @@ // constructing will be expanded into a libcall. if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) { assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits()); - SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy, + SignedConv = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy, SignedConv, SignedConv.getValue(1)); } - SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); + SignedConv = DAG.getNode(ISD::BIT_CONVERT, dl, DestTy, SignedConv); } - return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); + return DAG.getNode(ISD::FADD, dl, DestTy, SignedConv, FudgeInReg); } // Check to see if the target has a custom way to lower this. If so, use it. @@ -5974,7 +5985,7 @@ case TargetLowering::Expand: break; // This case is handled below. case TargetLowering::Custom: { - SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, + SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, dl, DestTy, Source), DAG); if (NV.getNode()) return LegalizeOp(NV); @@ -5987,7 +5998,7 @@ if (ExpandSource) { SDValue SrcLo, SrcHi; ExpandOp(Source, SrcLo, SrcHi); - Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi); + Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, SrcLo, SrcHi); } RTLIB::Libcall LC = isSigned ? @@ -5995,11 +6006,11 @@ RTLIB::getUINTTOFP(SourceVT, DestTy); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type"); - Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); + Source = DAG.getNode(ISD::SINT_TO_FP, dl, DestTy, Source); SDValue HiPart; SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart); if (Result.getValueType() != DestTy && HiPart.getNode()) - Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart); + Result = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy, Result, HiPart); return Result; } @@ -6009,7 +6020,8 @@ /// legal for the target. SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0, - MVT DestVT) { + MVT DestVT, + DebugLoc dl) { if (Op0.getValueType() == MVT::i32) { // simple 32-bit [signed|unsigned] integer to float/double expansion @@ -6020,7 +6032,8 @@ SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); // set up Hi and Lo (into buffer) address based on endian SDValue Hi = StackSlot; - SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); + SDValue Lo = DAG.getNode(ISD::ADD, dl, + TLI.getPointerTy(), StackSlot,WordOff); if (TLI.isLittleEndian()) std::swap(Hi, Lo); @@ -6029,26 +6042,26 @@ if (isSigned) { // constant used to invert sign bit (signed to unsigned mapping) SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); - Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); + Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); } else { Op0Mapped = Op0; } // store the lo of the constructed double - based on integer input - SDValue Store1 = DAG.getStore(DAG.getEntryNode(), + SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op0Mapped, Lo, NULL, 0); // initial hi portion of constructed double SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); // store the hi of the constructed double - biased exponent - SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); + SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0); // load the constructed double - SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); + SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0); // FP constant to bias correct the final result SDValue Bias = DAG.getConstantFP(isSigned ? BitsToDouble(0x4330000080000000ULL) : BitsToDouble(0x4330000000000000ULL), MVT::f64); // subtract the bias - SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); + SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); // final result SDValue Result; // handle final rounding @@ -6056,21 +6069,21 @@ // do nothing Result = Sub; } else if (DestVT.bitsLT(MVT::f64)) { - Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, + Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, DAG.getIntPtrConstant(0)); } else if (DestVT.bitsGT(MVT::f64)) { - Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); + Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); } return Result; } assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); - SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); + SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); - SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0.getValueType()), + SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), Op0, DAG.getConstant(0, Op0.getValueType()), ISD::SETLT); SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); - SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), + SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, Four, Zero); // If the sign bit of the integer is set, the large number will be treated @@ -6089,22 +6102,22 @@ SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); unsigned Alignment = 1 << cast(CPIdx)->getAlignment(); - CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); + CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); Alignment = std::min(Alignment, 4u); SDValue FudgeInReg; if (DestVT == MVT::f32) - FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, + FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, false, Alignment); else { FudgeInReg = - LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, + LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, MVT::f32, false, Alignment)); } - return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); + return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); } /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a @@ -6114,7 +6127,8 @@ /// operation that takes a larger input. SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, - bool isSigned) { + bool isSigned, + DebugLoc dl) { // First step, figure out the appropriate *INT_TO_FP operation to use. MVT NewInTy = LegalOp.getValueType(); @@ -6157,9 +6171,9 @@ // Okay, we found the operation and type to use. Zero extend our input to the // desired type then run the operation on it. - return DAG.getNode(OpToUse, DestVT, + return DAG.getNode(OpToUse, dl, DestVT, DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, - NewInTy, LegalOp)); + dl, NewInTy, LegalOp)); } /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a @@ -6169,7 +6183,8 @@ /// operation that returns a larger result. SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, - bool isSigned) { + bool isSigned, + DebugLoc dl) { // First step, figure out the appropriate FP_TO*INT operation to use. MVT NewOutTy = DestVT; @@ -6211,7 +6226,7 @@ // Okay, we found the operation and type to use. - SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); + SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); // If the operation produces an invalid type, it must be custom lowered. Use // the target lowering hooks to expand it. Just keep the low part of the @@ -6225,7 +6240,7 @@ // Truncate the result of the extended FP_TO_*INT operation to the desired // size. - return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); + return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); } /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. @@ -7368,7 +7383,7 @@ } Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, - Node->getOperand(0)); + Node->getOperand(0), Node->getDebugLoc()); if (getTypeAction(Lo.getValueType()) == Expand) // float to i32 etc. can be 'expanded' to a single node. ExpandOp(Lo, Lo, Hi); From snaroff at apple.com Mon Feb 2 13:22:03 2009 From: snaroff at apple.com (Steve Naroff) Date: Mon, 02 Feb 2009 19:22:03 -0000 Subject: [llvm-commits] [llvm] r63539 - /llvm/trunk/win32/config.h Message-ID: <200902021922.n12JM3W7015508@zion.cs.uiuc.edu> Author: snaroff Date: Mon Feb 2 13:22:02 2009 New Revision: 63539 URL: http://llvm.org/viewvc/llvm-project?rev=63539&view=rev Log: Update hand-crafted VC++ build. - Add PACKAGE_STRING definition to Windows config.h. Modified: llvm/trunk/win32/config.h Modified: llvm/trunk/win32/config.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/win32/config.h?rev=63539&r1=63538&r2=63539&view=diff ============================================================================== --- llvm/trunk/win32/config.h (original) +++ llvm/trunk/win32/config.h Mon Feb 2 13:22:02 2009 @@ -3,6 +3,7 @@ #define PACKAGE_NAME "LLVM (win32 vc8.0)" #define PACKAGE_VERSION 2.4 +#define PACKAGE_STRING "llvm 2.6svn" #define LLVM_HOSTTRIPLE "i686-pc-win32" #define HAVE_WINDOWS_H 1 #define HAVE_LIMITS_H 1 From baldrick at free.fr Mon Feb 2 13:46:41 2009 From: baldrick at free.fr (Duncan Sands) Date: Mon, 02 Feb 2009 19:46:41 -0000 Subject: [llvm-commits] [llvm] r63540 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeFloatTypes.cpp LegalizeIntegerTypes.cpp LegalizeTypesGeneric.cpp Message-ID: <200902021946.n12JkgOE017037@zion.cs.uiuc.edu> Author: baldrick Date: Mon Feb 2 13:46:41 2009 New Revision: 63540 URL: http://llvm.org/viewvc/llvm-project?rev=63540&view=rev Log: Remove trailing spaces. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=63540&r1=63539&r2=63540&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Mon Feb 2 13:46:41 2009 @@ -851,7 +851,7 @@ RTLIB::DIV_F64, RTLIB::DIV_F80, RTLIB::DIV_PPCF128), - N->getValueType(0), Ops, 2, false, + N->getValueType(0), Ops, 2, false, N->getDebugLoc()); assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!"); @@ -932,7 +932,7 @@ RTLIB::MUL_F64, RTLIB::MUL_F80, RTLIB::MUL_PPCF128), - N->getValueType(0), Ops, 2, false, + N->getValueType(0), Ops, 2, false, N->getDebugLoc()); assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR && "Call lowered wrongly!"); @@ -1148,7 +1148,7 @@ Lo = DAG.getNode(ISD::FADD, dl, VT, Hi, DAG.getConstantFP(APFloat(APInt(128, 2, Parts)), MVT::ppcf128)); - Lo = DAG.getNode(ISD::SELECT_CC, dl, VT, Src, DAG.getConstant(0, SrcVT), + Lo = DAG.getNode(ISD::SELECT_CC, dl, VT, Src, DAG.getConstant(0, SrcVT), Lo, Hi, DAG.getCondCode(ISD::SETLT)); Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Lo, DAG.getIntPtrConstant(1)); Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Lo, DAG.getIntPtrConstant(0)); @@ -1275,7 +1275,7 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) { MVT RVT = N->getValueType(0); DebugLoc dl = N->getDebugLoc(); - + // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on // PPC (the libcall is not available). FIXME: Do this in a less hacky way. if (RVT == MVT::i32) { @@ -1283,7 +1283,7 @@ "Logic only correct for ppcf128!"); SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128, N->getOperand(0), DAG.getValueType(MVT::f64)); - Res = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Res, + Res = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Res, DAG.getIntPtrConstant(1)); return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=63540&r1=63539&r2=63540&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon Feb 2 13:46:41 2009 @@ -137,7 +137,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { SDValue Op2 = GetPromotedInteger(N->getOperand(2)); - SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), + SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), N->getMemoryVT(), N->getChain(), N->getBasePtr(), Op2, N->getSrcValue(), N->getAlignment()); @@ -176,7 +176,7 @@ case PromoteInteger: if (NOutVT.bitsEq(NInVT)) // The input promotes to the same size. Convert the promoted value. - return DAG.getNode(ISD::BIT_CONVERT, dl, + return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, GetPromotedInteger(InOp)); break; case SoftenFloat: @@ -1047,7 +1047,7 @@ Lo = Hi = DAG.getConstant(0, NVT); } else if (Amt > NVTBits) { Lo = DAG.getConstant(0, NVT); - Hi = DAG.getNode(ISD::SHL, dl, + Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); } else if (Amt == NVTBits) { Lo = DAG.getConstant(0, NVT); @@ -1077,7 +1077,7 @@ Lo = DAG.getConstant(0, NVT); Hi = DAG.getConstant(0, NVT); } else if (Amt > NVTBits) { - Lo = DAG.getNode(ISD::SRL, dl, + Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); Hi = DAG.getConstant(0, NVT); } else if (Amt == NVTBits) { @@ -1550,7 +1550,7 @@ DAG.getConstant(ExcessBits, TLI.getPointerTy()))); // Move high bits to the right position in Hi. - Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, + Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT, Hi, DAG.getConstant(NVT.getSizeInBits() - ExcessBits, TLI.getPointerTy())); @@ -1986,7 +1986,7 @@ if (ConstantSDNode *RHSCST = dyn_cast(RHSLo)) { if (RHSCST->isAllOnesValue()) { // Equality comparison to -1. - NewLHS = DAG.getNode(ISD::AND, dl, + NewLHS = DAG.getNode(ISD::AND, dl, LHSLo.getValueType(), LHSLo, LHSHi); NewRHS = RHSLo; return; @@ -2262,7 +2262,7 @@ // Check whether the sign bit is set. SDValue Lo, Hi; GetExpandedInteger(Op, Lo, Hi); - SDValue SignSet = DAG.getSetCC(dl, + SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Hi.getValueType()), Hi, DAG.getConstant(0, Hi.getValueType()), ISD::SETLT); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=63540&r1=63539&r2=63540&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Mon Feb 2 13:46:41 2009 @@ -187,7 +187,7 @@ unsigned IncrementSize = NVT.getSizeInBits() / 8; Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); - Hi = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getSrcValue(), + Hi = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getSrcValue(), SVOffset+IncrementSize, isVolatile, MinAlign(Alignment, IncrementSize)); @@ -306,7 +306,7 @@ // Bitconvert to a vector of twice the length with elements of the expanded // type, insert the expanded vector elements, and then convert back. MVT NewVecVT = MVT::getVectorVT(NewEVT, NumElts*2); - SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl, + SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, N->getOperand(0)); SDValue Lo, Hi; @@ -365,7 +365,7 @@ Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); assert(isTypeLegal(Ptr.getValueType()) && "Pointers must be legal!"); - Hi = DAG.getStore(Chain, dl, Hi, Ptr, St->getSrcValue(), + Hi = DAG.getStore(Chain, dl, Hi, Ptr, St->getSrcValue(), SVOffset + IncrementSize, isVolatile, MinAlign(Alignment, IncrementSize)); From anton at korobeynikov.info Mon Feb 2 13:50:07 2009 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Mon, 2 Feb 2009 22:50:07 +0300 Subject: [llvm-commits] Turning off SSE codegen for x86-64? In-Reply-To: <7C6E5A97-AC05-4C37-8952-564AD7EEF209@apple.com> References: <200901252021.n0PKLO2s029035@zion.cs.uiuc.edu> <4980A242.7060401@gmail.com> <4980BB88.3080409@gmail.com> <40C05783-04B7-43AF-89A6-4BE851FEF22D@apple.com> <4985796B.6030903@gmail.com> <7C6E5A97-AC05-4C37-8952-564AD7EEF209@apple.com> Message-ID: <1C80BEF6-8653-46CD-9C45-6A20B4B8B279@korobeynikov.info> Hi, Chris > "SSE register cannot be used when SSE is disabled!"); > > Please change these into something like this: > if (..) { > cerr << "user message here"; > exit(1); > } > > assuming that you can trigger it with the right input. No, you cannot. CC lowering code should promote stuff to x87 FP math, so this assert checks whether this is indeed so :) --- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From isanbard at gmail.com Mon Feb 2 14:18:57 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 2 Feb 2009 12:18:57 -0800 Subject: [llvm-commits] [llvm] r63495 - in /llvm/trunk: lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86Subtarget.cpp test/CodeGen/X86/2009-01-25-NoSSE.ll test/CodeGen/X86/nosse-varargs.ll In-Reply-To: <200902011815.n11IFvlY018701@zion.cs.uiuc.edu> References: <200902011815.n11IFvlY018701@zion.cs.uiuc.edu> Message-ID: <16e5fdf90902021218y3202522h69c21aceaba4f5c9@mail.gmail.com> On Sun, Feb 1, 2009 at 10:15 AM, Torok Edwin wrote: > Author: edwin > Date: Sun Feb 1 12:15:56 2009 > New Revision: 63495 > > URL: http://llvm.org/viewvc/llvm-project?rev=63495&view=rev > Log: > Implement -mno-sse: if SSE is disabled on x86-64, don't store XMM on stack for > var-args, and don't allow FP return values > > --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Sun Feb 1 12:15:56 2009 > @@ -331,7 +331,7 @@ > // are enabled. These are available on all x86-64 CPUs. > if (Is64Bit) { > HasX86_64 = true; > -#if 1 > +#if 0 > if (X86SSELevel < SSE2) > X86SSELevel = SSE2; > #endif Could you just remove the code instead of commenting it out? :-) -bw From edwintorok at gmail.com Mon Feb 2 14:23:02 2009 From: edwintorok at gmail.com (Torok Edwin) Date: Mon, 02 Feb 2009 20:23:02 -0000 Subject: [llvm-commits] [llvm] r63542 - /llvm/trunk/lib/Target/X86/X86Subtarget.cpp Message-ID: <200902022023.n12KN2ob018325@zion.cs.uiuc.edu> Author: edwin Date: Mon Feb 2 14:23:02 2009 New Revision: 63542 URL: http://llvm.org/viewvc/llvm-project?rev=63542&view=rev Log: remove #if 0 code on Bill's request. Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=63542&r1=63541&r2=63542&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon Feb 2 14:23:02 2009 @@ -331,10 +331,6 @@ // are enabled. These are available on all x86-64 CPUs. if (Is64Bit) { HasX86_64 = true; -#if 0 - if (X86SSELevel < SSE2) - X86SSELevel = SSE2; -#endif } DOUT << "Subtarget features: SSELevel " << X86SSELevel << ", 3DNowLevel " << X863DNowLevel From edwintorok at gmail.com Mon Feb 2 14:23:34 2009 From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=) Date: Mon, 02 Feb 2009 22:23:34 +0200 Subject: [llvm-commits] [llvm] r63495 - in /llvm/trunk: lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86Subtarget.cpp test/CodeGen/X86/2009-01-25-NoSSE.ll test/CodeGen/X86/nosse-varargs.ll In-Reply-To: <16e5fdf90902021218y3202522h69c21aceaba4f5c9@mail.gmail.com> References: <200902011815.n11IFvlY018701@zion.cs.uiuc.edu> <16e5fdf90902021218y3202522h69c21aceaba4f5c9@mail.gmail.com> Message-ID: <49875646.30907@gmail.com> On 2009-02-02 22:18, Bill Wendling wrote: > On Sun, Feb 1, 2009 at 10:15 AM, Torok Edwin wrote: > >> Author: edwin >> Date: Sun Feb 1 12:15:56 2009 >> New Revision: 63495 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=63495&view=rev >> Log: >> Implement -mno-sse: if SSE is disabled on x86-64, don't store XMM on stack for >> var-args, and don't allow FP return values >> >> --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) >> +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Sun Feb 1 12:15:56 2009 >> @@ -331,7 +331,7 @@ >> // are enabled. These are available on all x86-64 CPUs. >> if (Is64Bit) { >> HasX86_64 = true; >> -#if 1 >> +#if 0 >> if (X86SSELevel < SSE2) >> X86SSELevel = SSE2; >> #endif >> > > Could you just remove the code instead of commenting it out? :-) Done. Best regards, --Edwin From clattner at apple.com Mon Feb 2 14:29:19 2009 From: clattner at apple.com (Chris Lattner) Date: Mon, 2 Feb 2009 12:29:19 -0800 Subject: [llvm-commits] [llvm] r63521 - in /llvm/trunk: include/llvm/Target/TargetAsmInfo.h lib/Target/PIC16/PIC16TargetAsmInfo.cpp lib/Target/PIC16/PIC16TargetAsmInfo.h In-Reply-To: <200902021653.n12Gr7nn009604@zion.cs.uiuc.edu> References: <200902021653.n12Gr7nn009604@zion.cs.uiuc.edu> Message-ID: <4303358F-4591-4B0A-95B3-40838F05716E@apple.com> On Feb 2, 2009, at 8:53 AM, Sanjiv Gupta wrote: > Author: sgupta > Date: Mon Feb 2 10:53:06 2009 > New Revision: 63521 > > URL: http://llvm.org/viewvc/llvm-project?rev=63521&view=rev > Log: > Made the common case of default address space directive as non- > virtual for performance reasons. Provide a single virtual interface > for directives of all sizes in non-default address spaces. Thanks Sanjiv! -Chris From clattner at apple.com Mon Feb 2 14:30:56 2009 From: clattner at apple.com (Chris Lattner) Date: Mon, 2 Feb 2009 12:30:56 -0800 Subject: [llvm-commits] Turning off SSE codegen for x86-64? In-Reply-To: <1C80BEF6-8653-46CD-9C45-6A20B4B8B279@korobeynikov.info> References: <200901252021.n0PKLO2s029035@zion.cs.uiuc.edu> <4980A242.7060401@gmail.com> <4980BB88.3080409@gmail.com> <40C05783-04B7-43AF-89A6-4BE851FEF22D@apple.com> <4985796B.6030903@gmail.com> <7C6E5A97-AC05-4C37-8952-564AD7EEF209@apple.com> <1C80BEF6-8653-46CD-9C45-6A20B4B8B279@korobeynikov.info> Message-ID: On Feb 2, 2009, at 11:50 AM, Anton Korobeynikov wrote: > Hi, Chris > >> "SSE register cannot be used when SSE is disabled!"); >> >> Please change these into something like this: >> if (..) { >> cerr << "user message here"; >> exit(1); >> } >> >> assuming that you can trigger it with the right input. > No, you cannot. CC lowering code should promote stuff to x87 FP math, > so this assert checks whether this is indeed so :) ok! From isanbard at gmail.com Mon Feb 2 14:32:54 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 2 Feb 2009 12:32:54 -0800 Subject: [llvm-commits] [llvm] r63542 - /llvm/trunk/lib/Target/X86/X86Subtarget.cpp In-Reply-To: <200902022023.n12KN2ob018325@zion.cs.uiuc.edu> References: <200902022023.n12KN2ob018325@zion.cs.uiuc.edu> Message-ID: <16e5fdf90902021232m4b64ae0t26f121f5880ca9d2@mail.gmail.com> Thanks! :) -bw On Mon, Feb 2, 2009 at 12:23 PM, Torok Edwin wrote: > Author: edwin > Date: Mon Feb 2 14:23:02 2009 > New Revision: 63542 > > URL: http://llvm.org/viewvc/llvm-project?rev=63542&view=rev > Log: > remove #if 0 code on Bill's request. > > Modified: > llvm/trunk/lib/Target/X86/X86Subtarget.cpp > > Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=63542&r1=63541&r2=63542&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon Feb 2 14:23:02 2009 > @@ -331,10 +331,6 @@ > // are enabled. These are available on all x86-64 CPUs. > if (Is64Bit) { > HasX86_64 = true; > -#if 0 > - if (X86SSELevel < SSE2) > - X86SSELevel = SSE2; > -#endif > } > DOUT << "Subtarget features: SSELevel " << X86SSELevel > << ", 3DNowLevel " << X863DNowLevel > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From clattner at apple.com Mon Feb 2 14:33:40 2009 From: clattner at apple.com (Chris Lattner) Date: Mon, 2 Feb 2009 12:33:40 -0800 Subject: [llvm-commits] [PATCH] -fno-strict-overflow/-fwrapv: allow pointer arithmetic to be defined as wrapping instead of undefined on overflow In-Reply-To: <498606DD.2060703@gmail.com> References: <498606DD.2060703@gmail.com> Message-ID: <403AC459-A1FE-4F57-9CBA-65CA25259D63@apple.com> On Feb 1, 2009, at 12:32 PM, T?r?k Edwin wrote: > Hi, > > gcc provides -fwrapv and -fno-strict-overflow that allows pointer + > unsigned to be treated as possibly wrapping, instead of undefined -> > can't happen (the default with -fstrict-overflow, -O2, -O3 or -Os). I think the right way to handle this is to add a "overflow characteristic" field to the integer operations. Each integer operation could be "2's complement on overflow" "undefined on overflow" "trapping on overflow" or "saturating on overflow". I think it makes sense to capture this directly in the IR on a per-operation basis instead of trying to disable optimizations based on a global flag. If you're interested in tackling this, the first place to start would be to split up add into add/fadd and any other operations that work on both int/fp that do arithmetic. -Chris From ggreif at gmail.com Mon Feb 2 14:39:17 2009 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 2 Feb 2009 12:39:17 -0800 (PST) Subject: [llvm-commits] [llvm] r63539 - /llvm/trunk/win32/config.h In-Reply-To: <200902021922.n12JM3W7015508@zion.cs.uiuc.edu> References: <200902021922.n12JM3W7015508@zion.cs.uiuc.edu> Message-ID: <49ea1292-789b-48bf-9c6c-95fb73d71511@w1g2000prm.googlegroups.com> On 2 Feb., 20:22, Steve Naroff wrote: > Author: snaroff > Date: Mon Feb ?2 13:22:02 2009 > New Revision: 63539 > > URL:http://llvm.org/viewvc/llvm-project?rev=63539&view=rev > Log: > Update hand-crafted VC++ build. > - Add PACKAGE_STRING definition to Windows config.h. > > Modified: > ? ? llvm/trunk/win32/config.h > > Modified: llvm/trunk/win32/config.h > URL:http://llvm.org/viewvc/llvm-project/llvm/trunk/win32/config.h?rev=635... > > =========================================================================== === > --- llvm/trunk/win32/config.h (original) > +++ llvm/trunk/win32/config.h Mon Feb ?2 13:22:02 2009 > @@ -3,6 +3,7 @@ > > ?#define PACKAGE_NAME "LLVM (win32 vc8.0)" > ?#define PACKAGE_VERSION 2.4 Bill, this ^^^^^^ does not seem right. Cheers, Gabor > +#define PACKAGE_STRING "llvm 2.6svn" > ?#define LLVM_HOSTTRIPLE "i686-pc-win32" > ?#define HAVE_WINDOWS_H 1 > ?#define HAVE_LIMITS_H 1 > > _______________________________________________ > llvm-commits mailing list > llvm-comm... at cs.uiuc.eduhttp://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gohman at apple.com Mon Feb 2 14:39:56 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 2 Feb 2009 12:39:56 -0800 Subject: [llvm-commits] [llvm] r63495 - in /llvm/trunk: lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86Subtarget.cpp test/CodeGen/X86/2009-01-25-NoSSE.ll test/CodeGen/X86/nosse-varargs.ll In-Reply-To: <200902011815.n11IFvlY018701@zion.cs.uiuc.edu> References: <200902011815.n11IFvlY018701@zion.cs.uiuc.edu> Message-ID: <6A755BA8-4308-4238-A143-4332545A8F91@apple.com> Hello Edwin, Dan On Feb 1, 2009, at 10:15 AM, Torok Edwin wrote: > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Sun Feb 1 12:15:56 > 2009 > @@ -331,7 +331,7 @@ > // are enabled. These are available on all x86-64 CPUs. > if (Is64Bit) { > HasX86_64 = true; > -#if 1 > +#if 0 > if (X86SSELevel < SSE2) > X86SSELevel = SSE2; > #endif Can you fix the comment immediately above this to reflect what the code now does? Also, without this code, does -march=x86-64 default to having SSE2 disabled (or dependent on the host)? Since all known x86-64 hardware supports SSE2, it's convenient to have SSE2 enabled by default on x86-64. Thanks, Dan From dalej at apple.com Mon Feb 2 14:41:05 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 02 Feb 2009 20:41:05 -0000 Subject: [llvm-commits] [llvm] r63543 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200902022041.n12Kf5qC019110@zion.cs.uiuc.edu> Author: johannes Date: Mon Feb 2 14:41:04 2009 New Revision: 63543 URL: http://llvm.org/viewvc/llvm-project?rev=63543&view=rev Log: More DebugLoc propagation. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63543&r1=63542&r2=63543&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Feb 2 14:41:04 2009 @@ -169,7 +169,7 @@ /// is necessary to spill the vector being inserted into to memory, perform /// the insert there, and then read the result back. SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, - SDValue Idx); + SDValue Idx, DebugLoc dl); /// PromoteOp - Given an operation that produces a value in an invalid type, /// promote it to compute the value into a larger type. The produced value @@ -273,11 +273,14 @@ bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, SmallPtrSet &NodesLeadingTo); - void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC); - void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC); - void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC) { - LegalizeSetCCOperands(LHS, RHS, CC); - LegalizeSetCCCondCode(VT, LHS, RHS, CC); + void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC, + DebugLoc dl); + void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, + DebugLoc dl); + void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, + DebugLoc dl) { + LegalizeSetCCOperands(LHS, RHS, CC, dl); + LegalizeSetCCCondCode(VT, LHS, RHS, CC, dl); } SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, @@ -337,14 +340,16 @@ SDValue InOp = Mask.getOperand(i); for (unsigned j = 0; j != NumEltsGrowth; ++j) { if (InOp.getOpcode() == ISD::UNDEF) - Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); + Ops.push_back(DAG.getNode(ISD::UNDEF, + InOp.getNode()->getDebugLoc(), EltVT)); else { unsigned InEltNo = cast(InOp)->getZExtValue(); Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT)); } } } - Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); + Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getNode()->getDebugLoc(), + NVT, &Ops[0], Ops.size()); } VT = NVT; break; @@ -594,6 +599,7 @@ SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, SelectionDAG &DAG, const TargetLowering &TLI) { + DebugLoc dl = Node->getDebugLoc(); MVT VT = Node->getValueType(0); MVT SrcVT = Node->getOperand(1).getValueType(); assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && @@ -604,18 +610,19 @@ SDValue Mask1 = (SrcVT == MVT::f64) ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); - Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); - SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); - SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); + Mask1 = DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, Mask1); + SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, + Node->getOperand(1)); + SignBit = DAG.getNode(ISD::AND, dl, SrcNVT, SignBit, Mask1); // Shift right or sign-extend it if the two operands have different types. int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits(); if (SizeDiff > 0) { - SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, + SignBit = DAG.getNode(ISD::SRL, dl, SrcNVT, SignBit, DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); - SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); + SignBit = DAG.getNode(ISD::TRUNCATE, dl, NVT, SignBit); } else if (SizeDiff < 0) { - SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit); - SignBit = DAG.getNode(ISD::SHL, NVT, SignBit, + SignBit = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, SignBit); + SignBit = DAG.getNode(ISD::SHL, dl, NVT, SignBit, DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy())); } @@ -623,12 +630,12 @@ SDValue Mask2 = (VT == MVT::f64) ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); - Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); - SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); - Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); + Mask2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask2); + SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); + Result = DAG.getNode(ISD::AND, dl, NVT, Result, Mask2); // Or the value with the sign bit. - Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); + Result = DAG.getNode(ISD::OR, dl, NVT, Result, SignBit); return Result; } @@ -642,6 +649,7 @@ MVT VT = Val.getValueType(); int Alignment = ST->getAlignment(); int SVOffset = ST->getSrcValueOffset(); + DebugLoc dl = ST->getDebugLoc(); if (ST->getMemoryVT().isFloatingPoint() || ST->getMemoryVT().isVector()) { MVT intVT = MVT::getIntegerVT(VT.getSizeInBits()); @@ -649,8 +657,8 @@ // Expand to a bitconvert of the value to the integer type of the // same size, then a (misaligned) int store. // FIXME: Does not handle truncating floating point stores! - SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); - return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), + SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); + return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), SVOffset, ST->isVolatile(), Alignment); } else { // Do a (aligned) store to a stack slot, then copy from the stack slot @@ -666,7 +674,8 @@ SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); // Perform the original store, only redirected to the stack slot. - SDValue Store = DAG.getTruncStore(Chain, Val, StackPtr, NULL, 0,StoredVT); + SDValue Store = DAG.getTruncStore(Chain, dl, + Val, StackPtr, NULL, 0,StoredVT); SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); SmallVector Stores; unsigned Offset = 0; @@ -674,17 +683,17 @@ // Do all but one copies using the full register width. for (unsigned i = 1; i < NumRegs; i++) { // Load one integer register's worth from the stack slot. - SDValue Load = DAG.getLoad(RegVT, Store, StackPtr, NULL, 0); + SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0); // Store it to the final location. Remember the store. - Stores.push_back(DAG.getStore(Load.getValue(1), Load, Ptr, + Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, ST->getSrcValue(), SVOffset + Offset, ST->isVolatile(), MinAlign(ST->getAlignment(), Offset))); // Increment the pointers. Offset += RegBytes; - StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr, + StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, Increment); - Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, Increment); + Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); } // The last store may be partial. Do a truncating store. On big-endian @@ -693,15 +702,15 @@ MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset)); // Load from the stack slot. - SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, Store, StackPtr, + SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, NULL, 0, MemVT); - Stores.push_back(DAG.getTruncStore(Load.getValue(1), Load, Ptr, + Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, ST->getSrcValue(), SVOffset + Offset, MemVT, ST->isVolatile(), MinAlign(ST->getAlignment(), Offset))); // The order of the stores doesn't matter - say it with a TokenFactor. - return DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], Stores.size()); } } @@ -717,21 +726,21 @@ // Divide the stored value in two parts. SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); SDValue Lo = Val; - SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); + SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); // Store the two parts SDValue Store1, Store2; - Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, + Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, ST->getSrcValue(), SVOffset, NewStoredVT, ST->isVolatile(), Alignment); - Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, + Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, DAG.getConstant(IncrementSize, TLI.getPointerTy())); Alignment = MinAlign(Alignment, IncrementSize); - Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, + Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, ST->getSrcValue(), SVOffset + IncrementSize, NewStoredVT, ST->isVolatile(), Alignment); - return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); } /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. @@ -743,20 +752,21 @@ SDValue Ptr = LD->getBasePtr(); MVT VT = LD->getValueType(0); MVT LoadedVT = LD->getMemoryVT(); + DebugLoc dl = LD->getDebugLoc(); if (VT.isFloatingPoint() || VT.isVector()) { MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits()); if (TLI.isTypeLegal(intVT)) { // Expand to a (misaligned) integer load of the same size, // then bitconvert to floating point or vector. - SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), + SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(), SVOffset, LD->isVolatile(), LD->getAlignment()); - SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); + SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); if (VT.isFloatingPoint() && LoadedVT != VT) - Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); + Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); SDValue Ops[] = { Result, Chain }; - return DAG.getMergeValues(Ops, 2); + return DAG.getMergeValues(Ops, 2, dl); } else { // Copy the value to a (aligned) stack slot using (unaligned) integer // loads and stores, then do a (aligned) load from the stack slot. @@ -776,42 +786,42 @@ // Do all but one copies using the full register width. for (unsigned i = 1; i < NumRegs; i++) { // Load one integer register's worth from the original location. - SDValue Load = DAG.getLoad(RegVT, Chain, Ptr, LD->getSrcValue(), + SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(), SVOffset + Offset, LD->isVolatile(), MinAlign(LD->getAlignment(), Offset)); // Follow the load with a store to the stack slot. Remember the store. - Stores.push_back(DAG.getStore(Load.getValue(1), Load, StackPtr, + Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, NULL, 0)); // Increment the pointers. Offset += RegBytes; - Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, Increment); - StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr, + Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); + StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, Increment); } // The last copy may be partial. Do an extending load. MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset)); - SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, Chain, Ptr, + SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, LD->getSrcValue(), SVOffset + Offset, MemVT, LD->isVolatile(), MinAlign(LD->getAlignment(), Offset)); // Follow the load with a store to the stack slot. Remember the store. // On big-endian machines this requires a truncating store to ensure // that the bits end up in the right place. - Stores.push_back(DAG.getTruncStore(Load.getValue(1), Load, StackPtr, + Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, NULL, 0, MemVT)); // The order of the stores doesn't matter - say it with a TokenFactor. - SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], + SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], Stores.size()); // Finally, perform the original load only redirected to the stack slot. - Load = DAG.getExtLoad(LD->getExtensionType(), VT, TF, StackBase, + Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, NULL, 0, LoadedVT); // Callers expect a MERGE_VALUES node. SDValue Ops[] = { Load, TF }; - return DAG.getMergeValues(Ops, 2); + return DAG.getMergeValues(Ops, 2, dl); } } assert(LoadedVT.isInteger() && !LoadedVT.isVector() && @@ -835,33 +845,33 @@ // Load the value in two parts SDValue Lo, Hi; if (TLI.isLittleEndian()) { - Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), + Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); - Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, + Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, DAG.getConstant(IncrementSize, TLI.getPointerTy())); - Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), + Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), MinAlign(Alignment, IncrementSize)); } else { - Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, - NewLoadedVT,LD->isVolatile(), Alignment); - Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, + Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), + SVOffset, NewLoadedVT,LD->isVolatile(), Alignment); + Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, DAG.getConstant(IncrementSize, TLI.getPointerTy())); - Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), + Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), MinAlign(Alignment, IncrementSize)); } // aggregate the two parts SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); - SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); - Result = DAG.getNode(ISD::OR, VT, Result, Lo); + SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); + Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); - SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), + SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), Hi.getValue(1)); SDValue Ops[] = { Result, TF }; - return DAG.getMergeValues(Ops, 2); + return DAG.getMergeValues(Ops, 2, dl); } /// UnrollVectorOp - We know that the given vector has a legal type, however @@ -876,6 +886,7 @@ "Can't unroll a vector with multiple results!"); unsigned NE = VT.getVectorNumElements(); MVT EltVT = VT.getVectorElementType(); + DebugLoc dl = Op.getNode()->getDebugLoc(); SmallVector Scalars; SmallVector Operands(Op.getNumOperands()); @@ -886,7 +897,7 @@ if (OperandVT.isVector()) { // A vector operand; extract a single element. MVT OperandEltVT = OperandVT.getVectorElementType(); - Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, + Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, OperandEltVT, Operand, DAG.getConstant(i, MVT::i32)); @@ -898,7 +909,7 @@ switch (Op.getOpcode()) { default: - Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, + Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, &Operands[0], Operands.size())); break; case ISD::SHL: @@ -906,13 +917,13 @@ case ISD::SRL: case ISD::ROTL: case ISD::ROTR: - Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, Operands[0], + Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, Operands[0], DAG.getShiftAmountOperand(Operands[1]))); break; } } - return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); + return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Scalars[0], Scalars.size()); } /// GetFPLibCall - Return the right libcall for the given floating point type. @@ -934,7 +945,8 @@ /// is necessary to spill the vector being inserted into to memory, perform /// the insert there, and then read the result back. SDValue SelectionDAGLegalize:: -PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) { +PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, + DebugLoc dl) { SDValue Tmp1 = Vec; SDValue Tmp2 = Val; SDValue Tmp3 = Idx; @@ -954,21 +966,21 @@ int SPFI = cast(StackPtr.getNode())->getIndex(); // Store the vector. - SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, + SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, PseudoSourceValue::getFixedStack(SPFI), 0); // Truncate or zero extend offset to target pointer type. unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; - Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); + Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); // Add the offset to the index. unsigned EltSize = EltVT.getSizeInBits()/8; - Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); - SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); + Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); + SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); // Store the scalar value. - Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2, + Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, PseudoSourceValue::getFixedStack(SPFI), 0, EltVT); // Load the updated vector. - return DAG.getLoad(VT, Ch, StackPtr, + return DAG.getLoad(VT, dl, Ch, StackPtr, PseudoSourceValue::getFixedStack(SPFI), 0); } @@ -1657,7 +1669,7 @@ break; } } - Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3); + Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3, dl); break; } } @@ -2093,7 +2105,8 @@ Tmp3 = Node->getOperand(3); // RHS Tmp4 = Node->getOperand(1); // CC - LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()), Tmp2, Tmp3,Tmp4); + LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()), + Tmp2, Tmp3, Tmp4, dl); LastCALLSEQ_END = DAG.getEntryNode(); // If we didn't get both a LHS and RHS back from LegalizeSetCC, @@ -2995,7 +3008,8 @@ Tmp4 = LegalizeOp(Node->getOperand(3)); // False SDValue CC = Node->getOperand(4); - LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC); + LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), + Tmp1, Tmp2, CC, dl); // If we didn't get both a LHS and RHS back from LegalizeSetCC, // the LHS is a legal SETCC itself. In this case, we need to compare @@ -3021,7 +3035,7 @@ Tmp1 = Node->getOperand(0); Tmp2 = Node->getOperand(1); Tmp3 = Node->getOperand(2); - LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3); + LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); // If we had to Expand the SetCC operands into a SELECT node, then it may // not always be possible to return a true LHS & RHS. In this case, just @@ -4953,6 +4967,7 @@ // lower to a store then an indexed load. SDValue Vec = Op.getOperand(0); SDValue Idx = Op.getOperand(1); + DebugLoc dl = Op.getNode()->getDebugLoc(); MVT TVT = Vec.getValueType(); unsigned NumElems = TVT.getVectorNumElements(); @@ -5004,21 +5019,21 @@ // Store the value to a temporary stack slot, then LOAD the scalar // element back out. SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); - SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); + SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0); // Add the offset to the index. unsigned EltSize = Op.getValueType().getSizeInBits()/8; - Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, + Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, DAG.getConstant(EltSize, Idx.getValueType())); if (Idx.getValueType().bitsGT(TLI.getPointerTy())) - Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); + Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); else - Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); + Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); - StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); + StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); - Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); + Op = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0); } return Op; } @@ -5062,7 +5077,8 @@ /// LHS, and the SDValue returned in RHS has a nil SDNode value. void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, - SDValue &CC) { + SDValue &CC, + DebugLoc dl) { SDValue Tmp1, Tmp2, Tmp3, Result; switch (getTypeAction(LHS.getValueType())) { @@ -5094,16 +5110,16 @@ // ALL of these operations will work if we either sign or zero extend // the operands (including the unsigned comparisons!). Zero extend is // usually a simpler/cheaper operation, so prefer it. - Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); - Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); + Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT); + Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT); break; case ISD::SETGE: case ISD::SETGT: case ISD::SETLT: case ISD::SETLE: - Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, + Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1, DAG.getValueType(VT)); - Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, + Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2, DAG.getValueType(VT)); Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes. Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes. @@ -5175,20 +5191,20 @@ SDValue Dummy; SDValue Ops[2] = { LHS, RHS }; - Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(), + Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2, dl).getNode(), false /*sign irrelevant*/, Dummy); Tmp2 = DAG.getConstant(0, MVT::i32); CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); if (LC2 != RTLIB::UNKNOWN_LIBCALL) { - Tmp1 = DAG.getNode(ISD::SETCC, + Tmp1 = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC); - LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(), + LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2, dl).getNode(), false /*sign irrelevant*/, Dummy); - Tmp2 = DAG.getNode(ISD::SETCC, + Tmp2 = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(LHS.getValueType()), LHS, Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); - Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); + Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2); Tmp2 = SDValue(); } LHS = LegalizeOp(Tmp1); @@ -5207,17 +5223,17 @@ // BNE crN, L: // FCMPU crN, lo1, lo2 // The following can be improved, but not that much. - Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()), + Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), LHSHi, RHSHi, ISD::SETOEQ); - Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()), + Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), LHSLo, RHSLo, CCCode); - Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); - Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()), + Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); + Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), LHSHi, RHSHi, ISD::SETUNE); - Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()), + Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), LHSHi, RHSHi, CCCode); - Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); - Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); + Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); + Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3); Tmp2 = SDValue(); break; } @@ -5229,14 +5245,14 @@ if (ConstantSDNode *RHSCST = dyn_cast(RHSLo)) if (RHSCST->isAllOnesValue()) { // Comparison to -1. - Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); + Tmp1 = DAG.getNode(ISD::AND, dl,LHSLo.getValueType(), LHSLo, LHSHi); Tmp2 = RHSLo; break; } - Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); - Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); - Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); + Tmp1 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo); + Tmp2 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi); + Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2); Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); break; default: @@ -5276,12 +5292,12 @@ Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()), LHSLo, RHSLo, LowCC, false, DagCombineInfo); if (!Tmp1.getNode()) - Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()), + Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), LHSLo, RHSLo, LowCC); Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), LHSHi, RHSHi, CCCode, false, DagCombineInfo); if (!Tmp2.getNode()) - Tmp2 = DAG.getNode(ISD::SETCC, + Tmp2 = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(LHSHi.getValueType()), LHSHi, RHSHi,CC); @@ -5304,9 +5320,9 @@ LHSHi, RHSHi, ISD::SETEQ, false, DagCombineInfo); if (!Result.getNode()) - Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()), + Result=DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), LHSHi, RHSHi, ISD::SETEQ); - Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), + Result = LegalizeOp(DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(), Result, Tmp1, Tmp2)); Tmp1 = Result; Tmp2 = SDValue(); @@ -5324,7 +5340,8 @@ /// illegal condition code into AND / OR of multiple SETCC values. void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, - SDValue &CC) { + SDValue &CC, + DebugLoc dl) { MVT OpVT = LHS.getValueType(); ISD::CondCode CCCode = cast(CC)->get(); switch (TLI.getCondCodeAction(CCCode, OpVT)) { @@ -5352,9 +5369,9 @@ // FIXME: Implement more expansions. } - SDValue SetCC1 = DAG.getSetCC(VT, LHS, RHS, CC1); - SDValue SetCC2 = DAG.getSetCC(VT, LHS, RHS, CC2); - LHS = DAG.getNode(Opc, VT, SetCC1, SetCC2); + SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); + SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); + LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); RHS = SDValue(); CC = SDValue(); break; @@ -7413,6 +7430,7 @@ SDValue &Hi) { assert(Op.getValueType().isVector() && "Cannot split non-vector type!"); SDNode *Node = Op.getNode(); + DebugLoc dl = Node->getDebugLoc(); unsigned NumElements = Op.getValueType().getVectorNumElements(); assert(NumElements > 1 && "Cannot split a single element vector!"); @@ -7462,7 +7480,7 @@ } SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0), Node->getOperand(1), - Node->getOperand(2)); + Node->getOperand(2), dl); SplitVectorOp(Tmp, Lo, Hi); break; } From sabre at nondot.org Mon Feb 2 14:44:46 2009 From: sabre at nondot.org (Chris Lattner) Date: Mon, 02 Feb 2009 20:44:46 -0000 Subject: [llvm-commits] [llvm] r63544 - /llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Message-ID: <200902022044.n12Kiksp019238@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 2 14:44:45 2009 New Revision: 63544 URL: http://llvm.org/viewvc/llvm-project?rev=63544&view=rev Log: inline SROA::ConvertToScalar, no functionality change. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=63544&r1=63543&r2=63544&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Mon Feb 2 14:44:45 2009 @@ -127,7 +127,6 @@ bool CanConvertToScalar(Value *V, bool &IsNotTrivial, const Type *&ResTy, uint64_t Offset); - void ConvertToScalar(AllocationInst *AI, const Type *Ty); void ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, uint64_t Offset); Value *ConvertUsesOfLoadToScalar(LoadInst *LI, AllocaInst *NewAI, uint64_t Offset); @@ -269,6 +268,8 @@ Changed = true; continue; } + + // If we can turn this aggregate value (potentially with casts) into a // simple scalar value that can be mem2reg'd into a register value. @@ -277,11 +278,18 @@ // that we can't just check based on the type: the alloca may be of an i32 // but that has pointer arithmetic to set byte 3 of it or something. bool IsNotTrivial = false; - const Type *ActualType = 0; - if (CanConvertToScalar(AI, IsNotTrivial, ActualType, 0)) - if (IsNotTrivial && ActualType && - TD->getTypeSizeInBits(ActualType) < SRThreshold*8) { - ConvertToScalar(AI, ActualType); + const Type *ActualTy = 0; + if (CanConvertToScalar(AI, IsNotTrivial, ActualTy, 0)) + if (IsNotTrivial && ActualTy && + TD->getTypeSizeInBits(ActualTy) < SRThreshold*8) { + DOUT << "CONVERT TO SCALAR: " << *AI << " TYPE = " << *ActualTy <<"\n"; + ++NumConverted; + + // Create and insert the alloca. + AllocaInst *NewAI = new AllocaInst(ActualTy, 0, AI->getName(), + AI->getParent()->begin()); + ConvertUsesToScalar(AI, NewAI, 0); + AI->eraseFromParent(); Changed = true; continue; } @@ -1263,20 +1271,6 @@ return true; } -/// ConvertToScalar - The specified alloca passes the CanConvertToScalar -/// predicate and is non-trivial. Convert it to something that can be trivially -/// promoted into a register by mem2reg. -void SROA::ConvertToScalar(AllocationInst *AI, const Type *ActualTy) { - DOUT << "CONVERT TO SCALAR: " << *AI << " TYPE = " << *ActualTy << "\n"; - ++NumConverted; - - // Create and insert the alloca. - AllocaInst *NewAI = new AllocaInst(ActualTy, 0, AI->getName(), - AI->getParent()->begin()); - ConvertUsesToScalar(AI, NewAI, 0); - AI->eraseFromParent(); -} - /// ConvertUsesToScalar - Convert all of the users of Ptr to use the new alloca /// directly. This happens when we are converting an "integer union" to a From dalej at apple.com Mon Feb 2 14:47:49 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 02 Feb 2009 20:47:49 -0000 Subject: [llvm-commits] [llvm] r63545 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200902022047.n12Klnmm019338@zion.cs.uiuc.edu> Author: johannes Date: Mon Feb 2 14:47:48 2009 New Revision: 63545 URL: http://llvm.org/viewvc/llvm-project?rev=63545&view=rev Log: Commit missing files. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63545&r1=63544&r2=63545&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Feb 2 14:47:48 2009 @@ -568,6 +568,7 @@ /// getMergeValues - Create a MERGE_VALUES node from the given operands. SDValue getMergeValues(const SDValue *Ops, unsigned NumOps); + SDValue getMergeValues(const SDValue *Ops, unsigned NumOps, DebugLoc dl); /// getCall - Create a CALL node from the given information. /// Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63545&r1=63544&r2=63545&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Feb 2 14:47:48 2009 @@ -3547,6 +3547,20 @@ return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps); } +/// DebugLoc-aware version. +SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, + DebugLoc dl) { + if (NumOps == 1) + return Ops[0]; + + SmallVector VTs; + VTs.reserve(NumOps); + for (unsigned i = 0; i < NumOps; ++i) + VTs.push_back(Ops[i].getValueType()); + return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps), + Ops, NumOps); +} + SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, const MVT *VTs, unsigned NumVTs, From edwintorok at gmail.com Mon Feb 2 14:55:16 2009 From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=) Date: Mon, 02 Feb 2009 22:55:16 +0200 Subject: [llvm-commits] [llvm] r63495 - in /llvm/trunk: lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86Subtarget.cpp test/CodeGen/X86/2009-01-25-NoSSE.ll test/CodeGen/X86/nosse-varargs.ll In-Reply-To: <6A755BA8-4308-4238-A143-4332545A8F91@apple.com> References: <200902011815.n11IFvlY018701@zion.cs.uiuc.edu> <6A755BA8-4308-4238-A143-4332545A8F91@apple.com> Message-ID: <49875DB4.4050600@gmail.com> On 2009-02-02 22:39, Dan Gohman wrote: > Hello Edwin, > Hi Dan > On Feb 1, 2009, at 10:15 AM, Torok Edwin wrote: > > >> ====================================================================== >> --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) >> +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Sun Feb 1 12:15:56 >> 2009 >> @@ -331,7 +331,7 @@ >> // are enabled. These are available on all x86-64 CPUs. >> if (Is64Bit) { >> HasX86_64 = true; >> -#if 1 >> +#if 0 >> if (X86SSELevel < SSE2) >> X86SSELevel = SSE2; >> #endif >> > > > Can you fix the comment immediately above this to reflect > what the code now does? > See below for patch. > Also, without this code, does -march=x86-64 default to having > SSE2 disabled (or dependent on the host)? In my tests it defaulted to being enabled, but I think that is due to CPU features autodetection. If you supply it with a CPU it should default to SSE2, because there is something in parsesubtargetfeatures that turns on implied features of a CPU. I have a testcase that checks that by default llc -march=x86-64 generates SSE2, and with -mattr=-sse it doesn't (sse-novarargs.ll). > Since all known > x86-64 hardware supports SSE2, it's convenient to have SSE2 > enabled by default on x86-64. > To be safe [1], we can force the SSE level to be 2 only when autodetecting features. If user supplied CPU/features we don't force: [1] if you're cross-compiling from a non-SSE capable x86-32 CPU to x86-64 Is this patch OK to go in? Index: lib/Target/X86/X86Subtarget.cpp =================================================================== --- lib/Target/X86/X86Subtarget.cpp (revision 63542) +++ lib/Target/X86/X86Subtarget.cpp (working copy) @@ -322,13 +322,19 @@ // If feature string is not empty, parse features string. std::string CPU = GetCurrentX86CPU(); ParseSubtargetFeatures(FS, CPU); + // All X86-64 CPUs also have SSE2, however user might request no SSE via + // -mattr, so don't force SSELevel here. } else { // Otherwise, use CPUID to auto-detect feature set. AutoDetectSubtargetFeatures(); + if (Is64Bit) { + // Make sure SSE2 is enabled, it is available on all X86-64 CPUs. + X86SSELevel = SSE2; + } } - // If requesting codegen for X86-64, make sure that 64-bit and SSE2 features - // are enabled. These are available on all x86-64 CPUs. + // If requesting codegen for X86-64, make sure that 64-bit features + // are enabled. if (Is64Bit) { HasX86_64 = true; } From criswell at uiuc.edu Mon Feb 2 15:02:07 2009 From: criswell at uiuc.edu (John Criswell) Date: Mon, 02 Feb 2009 21:02:07 -0000 Subject: [llvm-commits] [poolalloc] r63547 - /poolalloc/branches/SVA/lib/DSA/Local.cpp Message-ID: <200902022102.n12L27l3019944@zion.cs.uiuc.edu> Author: criswell Date: Mon Feb 2 15:02:07 2009 New Revision: 63547 URL: http://llvm.org/viewvc/llvm-project?rev=63547&view=rev Log: Fix recognition of allocators. Make all kernel allocators and I/O allocators except kmem_cache_alloc() allocate type-unknown memory objects. Modified: poolalloc/branches/SVA/lib/DSA/Local.cpp Modified: poolalloc/branches/SVA/lib/DSA/Local.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/branches/SVA/lib/DSA/Local.cpp?rev=63547&r1=63546&r2=63547&view=diff ============================================================================== --- poolalloc/branches/SVA/lib/DSA/Local.cpp (original) +++ poolalloc/branches/SVA/lib/DSA/Local.cpp Mon Feb 2 15:02:07 2009 @@ -1513,10 +1513,23 @@ RetNH = getValueDest(*CS.getInstruction()); RetNH.getNode()->setHeapNodeMarker()->setModifiedMarker(); RetNH.getNode()->getMP()->addCallSite(CS); + + // + // Anything that is not a pool allocator must mark objects as + // type-unknown. + // + if (F->getName() != "kmem_cache_alloc") + RetNH.getNode()->foldNodeCompletely(); return; } #ifdef SVA_IO + // + // Determine whether this is a call to a function that allocates an I/O + // object. If so, then make it with the I/O flags and make it + // type-unknown (as the I/O device may treat the memory as a type different + // than what we infer). + // if (IOAllocList.end() != std::find(IOAllocList.begin(), IOAllocList.end(), F->getName())) { DSNodeHandle RetNH; if (F->getName() == "pseudo_alloc") @@ -1525,6 +1538,7 @@ RetNH = getValueDest(*CS.getInstruction()); RetNH.getNode()->setIONodeMarker()->setModifiedMarker(); RetNH.getNode()->getMP()->addCallSite(CS); + RetNH.getNode()->foldNodeCompletely(); return; } #endif @@ -1815,7 +1829,7 @@ AllocList.push_back("__vmalloc"); AllocList.push_back("kmem_cache_alloc"); AllocList.push_back("__alloc_bootmem"); - AllocList.push_back(" __get_free_pages"); + AllocList.push_back("__get_free_pages"); AllocList.push_back("pseudo_alloc"); AllocList.push_back("malloc"); From edwintorok at gmail.com Mon Feb 2 15:02:53 2009 From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=) Date: Mon, 02 Feb 2009 23:02:53 +0200 Subject: [llvm-commits] [PATCH] -fno-strict-overflow/-fwrapv: allow pointer arithmetic to be defined as wrapping instead of undefined on overflow In-Reply-To: <403AC459-A1FE-4F57-9CBA-65CA25259D63@apple.com> References: <498606DD.2060703@gmail.com> <403AC459-A1FE-4F57-9CBA-65CA25259D63@apple.com> Message-ID: <49875F7D.9060302@gmail.com> On 2009-02-02 22:33, Chris Lattner wrote: > On Feb 1, 2009, at 12:32 PM, T?r?k Edwin wrote: > > >> Hi, >> >> gcc provides -fwrapv and -fno-strict-overflow that allows pointer + >> unsigned to be treated as possibly wrapping, instead of undefined -> >> can't happen (the default with -fstrict-overflow, -O2, -O3 or -Os). >> > > I think the right way to handle this is to add a "overflow > characteristic" field to the integer operations. Each integer > operation could be "2's complement on overflow" "undefined on > overflow" "trapping on overflow" or "saturating on overflow". I think > it makes sense to capture this directly in the IR on a per-operation > basis instead of trying to disable optimizations based on a global flag. > > If you're interested in tackling this, the first place to start would > be to split up add into add/fadd and any other operations that work on > both int/fp that do arithmetic. Added to my TODOlist, we'll see if I have time to implement it. FYI here's my TODO for 2.6: 1. IRBuilder constantfolding patch (2.5/2.6) 2. assert/abort error handling starting point: unsupported inline asm shouldn't abort(), set "error occured" flag notes: make sure we don't generate any code (e.g. output .fail) 3. RangeSet to reduce O(M*N) memory usage of Codegen/LiveVariables 4. overflow behaviour 5. LLVM passes that are able to emit warnings optionally (for e.g. when encountering undefined behaviour instead of silently outputting code that might break allow it to print a warning message) <-- this'll need some discussion Best regards, --Edwin From dpatel at apple.com Mon Feb 2 15:09:36 2009 From: dpatel at apple.com (Devang Patel) Date: Mon, 02 Feb 2009 21:09:36 -0000 Subject: [llvm-commits] [llvm] r63548 - in /llvm/trunk/test: FrontendC++/2006-11-30-Pubnames.cpp Makefile lib/llvm.exp Message-ID: <200902022109.n12L9aAG020243@zion.cs.uiuc.edu> Author: dpatel Date: Mon Feb 2 15:09:36 2009 New Revision: 63548 URL: http://llvm.org/viewvc/llvm-project?rev=63548&view=rev Log: Run dsymutil on darwin, when it is expected, before running gdb test. Modified: llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp llvm/trunk/test/Makefile llvm/trunk/test/lib/llvm.exp Modified: llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-11-30-Pubnames.cpp?rev=63548&r1=63547&r2=63548&view=diff ============================================================================== --- llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp (original) +++ llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp Mon Feb 2 15:09:36 2009 @@ -4,6 +4,7 @@ // RUN: llc --disable-fp-elim -o %t.s -f // RUN: %compile_c %t.s -o %t.o // RUN: %link %t.o -o %t.exe +// RUN: %llvmdsymutil %t.exe // RUN: echo {break main\nrun\np Pubnames::pubname} > %t.in // RUN: gdb -q -batch -n -x %t.in %t.exe | tee %t.out | grep {\$1 = 10} // XFAIL: alpha|ia64|arm Modified: llvm/trunk/test/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Makefile?rev=63548&r1=63547&r2=63548&view=diff ============================================================================== --- llvm/trunk/test/Makefile (original) +++ llvm/trunk/test/Makefile Mon Feb 2 15:09:36 2009 @@ -81,6 +81,13 @@ clean:: $(RM) -rf `find $(LLVM_OBJ_ROOT)/test -name Output -type d -print` +# dsymutil is used on the Darwin to manipulate DWARF debugging information. +ifeq ($(OS),Darwin) +DSYMUTIL=dsymutil +else +DSYMUTIL=true +endif + FORCE: site.exp: FORCE @@ -112,6 +119,7 @@ @echo 'set valgrind "$(VALGRIND)"' >> site.tmp @echo 'set grep "$(GREP)"' >>site.tmp @echo 'set gas "$(GAS)"' >>site.tmp + @echo 'set llvmdsymutil "$(DSYMUTIL)"' >>site.tmp @echo '## All variables above are generated by configure. Do Not Edit ## ' >>site.tmp @test ! -f site.exp || \ sed '1,/^## All variables above are.*##/ d' site.exp >> site.tmp Modified: llvm/trunk/test/lib/llvm.exp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/lib/llvm.exp?rev=63548&r1=63547&r2=63548&view=diff ============================================================================== --- llvm/trunk/test/lib/llvm.exp (original) +++ llvm/trunk/test/lib/llvm.exp Mon Feb 2 15:09:36 2009 @@ -48,7 +48,7 @@ proc substitute { line test tmpFile } { global srcroot objroot srcdir objdir subdir target_triplet prcontext global llvmgcc llvmgxx llvmgcc_version llvmgccmajvers ocamlc - global gccpath gxxpath compile_c compile_cxx link shlibext llvmlibsdir + global gccpath gxxpath compile_c compile_cxx link shlibext llvmlibsdir llvmdsymutil global valgrind grep gas set path [file join $srcdir $subdir] @@ -73,6 +73,8 @@ regsub -all {%shlibext} $new_line "$shlibext" new_line #replace %ocamlc with ocaml compiler command regsub -all {%ocamlc} $new_line "$ocamlc" new_line + #replace %llvmdsymutil with dsymutil command + regsub -all {%llvmdsymutil} $new_line "$llvmdsymutil" new_line #replace %llvmlibsdir with configure library directory regsub -all {%llvmlibsdir} $new_line "$llvmlibsdir" new_line #replace %p with path to source, From dalej at apple.com Mon Feb 2 15:16:30 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 2 Feb 2009 13:16:30 -0800 Subject: [llvm-commits] [llvm] r63548 - in /llvm/trunk/test: FrontendC++/2006-11-30-Pubnames.cpp Makefile lib/llvm.exp In-Reply-To: <200902022109.n12L9aAG020243@zion.cs.uiuc.edu> References: <200902022109.n12L9aAG020243@zion.cs.uiuc.edu> Message-ID: On Feb 2, 2009, at 1:09 PMPST, Devang Patel wrote: > Author: dpatel > Date: Mon Feb 2 15:09:36 2009 > New Revision: 63548 > > URL: http://llvm.org/viewvc/llvm-project?rev=63548&view=rev > Log: > Run dsymutil on darwin, when it is expected, before running gdb test. Wouldn't it be better to do this in the gcc driver? It's been told -g and to produce an executable, that ought to be enough info. From eli.friedman at gmail.com Mon Feb 2 15:24:24 2009 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 2 Feb 2009 13:24:24 -0800 Subject: [llvm-commits] [llvm] r63090 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/smul-with-overflow-2.ll In-Reply-To: <4986C5CB.5070204@gmail.com> References: <200901270330.n0R3UgVN005529@zion.cs.uiuc.edu> <4986C5CB.5070204@gmail.com> Message-ID: On Mon, Feb 2, 2009 at 2:07 AM, T?r?k Edwin wrote: > What are the semantics of llvm.OP.with.overflow intrinsics that I keep > seeing lately? The first result is the same as a regular OP. The second result is whether there was an overflow while calculating the result; for example, llvm.smul.with.overflow returns whether there was a signed overflow in computing the product. > LangRef makes no mention of them. They're still a work in progress... I'm sure they'll get added eventually. -Eli From eli.friedman at gmail.com Mon Feb 2 15:30:09 2009 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 2 Feb 2009 13:30:09 -0800 Subject: [llvm-commits] [PATCH] -fno-strict-overflow/-fwrapv: allow pointer arithmetic to be defined as wrapping instead of undefined on overflow In-Reply-To: <403AC459-A1FE-4F57-9CBA-65CA25259D63@apple.com> References: <498606DD.2060703@gmail.com> <403AC459-A1FE-4F57-9CBA-65CA25259D63@apple.com> Message-ID: On Mon, Feb 2, 2009 at 12:33 PM, Chris Lattner wrote: > > On Feb 1, 2009, at 12:32 PM, T?r?k Edwin wrote: > >> Hi, >> >> gcc provides -fwrapv and -fno-strict-overflow that allows pointer + >> unsigned to be treated as possibly wrapping, instead of undefined -> >> can't happen (the default with -fstrict-overflow, -O2, -O3 or -Os). > > I think the right way to handle this is to add a "overflow > characteristic" field to the integer operations. We already implement -fwrapv behavior for integers... the issue at hand is GEP. -Eli From clattner at apple.com Mon Feb 2 15:31:01 2009 From: clattner at apple.com (Chris Lattner) Date: Mon, 2 Feb 2009 13:31:01 -0800 Subject: [llvm-commits] [llvm] r63090 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/smul-with-overflow-2.ll In-Reply-To: References: <200901270330.n0R3UgVN005529@zion.cs.uiuc.edu> <4986C5CB.5070204@gmail.com> Message-ID: <8D6D5F3B-EA1B-46DD-8EBB-F8298F62993F@apple.com> On Feb 2, 2009, at 1:24 PM, Eli Friedman wrote: > On Mon, Feb 2, 2009 at 2:07 AM, T?r?k Edwin > wrote: >> What are the semantics of llvm.OP.with.overflow intrinsics that I >> keep >> seeing lately? > > The first result is the same as a regular OP. The second result is > whether there was an overflow while calculating the result; for > example, llvm.smul.with.overflow returns whether there was a signed > overflow in computing the product. > >> LangRef makes no mention of them. > > They're still a work in progress... I'm sure they'll get added > eventually. actually, this is a pretty bad oversight. Bill can you please add these to LangRef? -Chris From clattner at apple.com Mon Feb 2 15:31:31 2009 From: clattner at apple.com (Chris Lattner) Date: Mon, 2 Feb 2009 13:31:31 -0800 Subject: [llvm-commits] [PATCH] -fno-strict-overflow/-fwrapv: allow pointer arithmetic to be defined as wrapping instead of undefined on overflow In-Reply-To: References: <498606DD.2060703@gmail.com> <403AC459-A1FE-4F57-9CBA-65CA25259D63@apple.com> Message-ID: On Feb 2, 2009, at 1:30 PM, Eli Friedman wrote: > On Mon, Feb 2, 2009 at 12:33 PM, Chris Lattner > wrote: >> >> On Feb 1, 2009, at 12:32 PM, T?r?k Edwin wrote: >> >>> Hi, >>> >>> gcc provides -fwrapv and -fno-strict-overflow that allows pointer + >>> unsigned to be treated as possibly wrapping, instead of undefined -> >>> can't happen (the default with -fstrict-overflow, -O2, -O3 or -Os). >> >> I think the right way to handle this is to add a "overflow >> characteristic" field to the integer operations. > > We already implement -fwrapv behavior for integers... the issue at > hand is GEP. GEP is currently always undefined, add is currently always defined. Both should get the same set of flags IMO. -Chris From wendling at apple.com Mon Feb 2 15:31:42 2009 From: wendling at apple.com (Bill Wendling) Date: Mon, 2 Feb 2009 13:31:42 -0800 Subject: [llvm-commits] [llvm] r63090 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/smul-with-overflow-2.ll In-Reply-To: <8D6D5F3B-EA1B-46DD-8EBB-F8298F62993F@apple.com> References: <200901270330.n0R3UgVN005529@zion.cs.uiuc.edu> <4986C5CB.5070204@gmail.com> <8D6D5F3B-EA1B-46DD-8EBB-F8298F62993F@apple.com> Message-ID: <31A1FC8C-CC4F-4002-A9F4-8A42333F0BDD@apple.com> On Feb 2, 2009, at 1:31 PM, Chris Lattner wrote: > On Feb 2, 2009, at 1:24 PM, Eli Friedman wrote: > >> On Mon, Feb 2, 2009 at 2:07 AM, T?r?k Edwin >> wrote: >>> What are the semantics of llvm.OP.with.overflow intrinsics that I >>> keep >>> seeing lately? >> >> The first result is the same as a regular OP. The second result is >> whether there was an overflow while calculating the result; for >> example, llvm.smul.with.overflow returns whether there was a signed >> overflow in computing the product. >> >>> LangRef makes no mention of them. >> >> They're still a work in progress... I'm sure they'll get added >> eventually. > > actually, this is a pretty bad oversight. Bill can you please add > these to LangRef? > Okay. -bw From gohman at apple.com Mon Feb 2 15:43:41 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 2 Feb 2009 13:43:41 -0800 Subject: [llvm-commits] [llvm] r63495 - in /llvm/trunk: lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86Subtarget.cpp test/CodeGen/X86/2009-01-25-NoSSE.ll test/CodeGen/X86/nosse-varargs.ll In-Reply-To: <49875DB4.4050600@gmail.com> References: <200902011815.n11IFvlY018701@zion.cs.uiuc.edu> <6A755BA8-4308-4238-A143-4332545A8F91@apple.com> <49875DB4.4050600@gmail.com> Message-ID: <8BAA0D72-F5D7-49B2-81A5-5DAC116887E0@apple.com> On Feb 2, 2009, at 12:55 PM, T?r?k Edwin wrote: > >> On Feb 1, 2009, at 10:15 AM, Torok Edwin wrote: >> >> >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) >>> +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Sun Feb 1 12:15:56 >>> 2009 >>> @@ -331,7 +331,7 @@ >>> // are enabled. These are available on all x86-64 CPUs. >>> if (Is64Bit) { >>> HasX86_64 = true; >>> -#if 1 >>> +#if 0 >>> if (X86SSELevel < SSE2) >>> X86SSELevel = SSE2; >>> #endif >>> >> >> >> Can you fix the comment immediately above this to reflect >> what the code now does? >> > > See below for patch. > >> Also, without this code, does -march=x86-64 default to having >> SSE2 disabled (or dependent on the host)? > > In my tests it defaulted to being enabled, but I think that is due to > CPU features autodetection. > If you supply it with a CPU it should default to SSE2, because there > is > something in parsesubtargetfeatures that turns on implied features > of a CPU. > > I have a testcase that checks that by default llc -march=x86-64 > generates SSE2, and with -mattr=-sse it doesn't (sse-novarargs.ll). > >> Since all known >> x86-64 hardware supports SSE2, it's convenient to have SSE2 >> enabled by default on x86-64. >> > > To be safe [1], we can force the SSE level to be 2 only when > autodetecting features. If user supplied CPU/features we don't force: > > [1] if you're cross-compiling from a non-SSE capable x86-32 CPU to > x86-64 > > Is this patch OK to go in? > > Index: lib/Target/X86/X86Subtarget.cpp > =================================================================== > --- lib/Target/X86/X86Subtarget.cpp (revision 63542) > +++ lib/Target/X86/X86Subtarget.cpp (working copy) > @@ -322,13 +322,19 @@ > // If feature string is not empty, parse features string. > std::string CPU = GetCurrentX86CPU(); > ParseSubtargetFeatures(FS, CPU); > + // All X86-64 CPUs also have SSE2, however user might request no > SSE via > + // -mattr, so don't force SSELevel here. > } else { > // Otherwise, use CPUID to auto-detect feature set. > AutoDetectSubtargetFeatures(); > + if (Is64Bit) { > + // Make sure SSE2 is enabled, it is available on all X86-64 > CPUs. > + X86SSELevel = SSE2; > + } It looks like this should also check if (X86SSELevel < SSE2) so that it doesn't override when AutoDetectSubtargetFeatures detects an SSE level greater than SSE2. With that fixed, this looks good. > > } > > - // If requesting codegen for X86-64, make sure that 64-bit and SSE2 > features > - // are enabled. These are available on all x86-64 CPUs. > + // If requesting codegen for X86-64, make sure that 64-bit features > + // are enabled. > if (Is64Bit) { > HasX86_64 = true; > } Do you think it would make sense to move this up into the else clause above too? I'm wondering if an assert(!Is64Bit || HasX86_64) after the else would be a sane sanity check. Thanks, Dan From edwintorok at gmail.com Mon Feb 2 15:57:34 2009 From: edwintorok at gmail.com (Torok Edwin) Date: Mon, 02 Feb 2009 21:57:34 -0000 Subject: [llvm-commits] [llvm] r63552 - /llvm/trunk/lib/Target/X86/X86Subtarget.cpp Message-ID: <200902022157.n12LvYHj021948@zion.cs.uiuc.edu> Author: edwin Date: Mon Feb 2 15:57:34 2009 New Revision: 63552 URL: http://llvm.org/viewvc/llvm-project?rev=63552&view=rev Log: Only force SSE level if it is not correct. Add an assert to check HasX86_64 status. Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=63552&r1=63551&r2=63552&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon Feb 2 15:57:34 2009 @@ -322,16 +322,23 @@ // If feature string is not empty, parse features string. std::string CPU = GetCurrentX86CPU(); ParseSubtargetFeatures(FS, CPU); + // All X86-64 CPUs also have SSE2, however user might request no SSE via + // -mattr, so don't force SSELevel here. } else { // Otherwise, use CPUID to auto-detect feature set. AutoDetectSubtargetFeatures(); + if (Is64Bit && X86SSELevel < SSE2) { + // Make sure SSE2 is enabled, it is available on all X86-64 CPUs. + X86SSELevel = SSE2; + } } - // If requesting codegen for X86-64, make sure that 64-bit and SSE2 features - // are enabled. These are available on all x86-64 CPUs. + // If requesting codegen for X86-64, make sure that 64-bit features + // are enabled. if (Is64Bit) { - HasX86_64 = true; + HasX86_64 = true; } + assert(!Is64Bit || HasX86_64); DOUT << "Subtarget features: SSELevel " << X86SSELevel << ", 3DNowLevel " << X863DNowLevel << ", 64bit " << HasX86_64 << "\n"; From edwintorok at gmail.com Mon Feb 2 15:57:50 2009 From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=) Date: Mon, 02 Feb 2009 23:57:50 +0200 Subject: [llvm-commits] [llvm] r63495 - in /llvm/trunk: lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86Subtarget.cpp test/CodeGen/X86/2009-01-25-NoSSE.ll test/CodeGen/X86/nosse-varargs.ll In-Reply-To: <8BAA0D72-F5D7-49B2-81A5-5DAC116887E0@apple.com> References: <200902011815.n11IFvlY018701@zion.cs.uiuc.edu> <6A755BA8-4308-4238-A143-4332545A8F91@apple.com> <49875DB4.4050600@gmail.com> <8BAA0D72-F5D7-49B2-81A5-5DAC116887E0@apple.com> Message-ID: <49876C5E.9030408@gmail.com> On 2009-02-02 23:43, Dan Gohman wrote: > On Feb 2, 2009, at 12:55 PM, T?r?k Edwin wrote: > >> + if (Is64Bit) { >> + // Make sure SSE2 is enabled, it is available on all X86-64 >> CPUs. >> + X86SSELevel = SSE2; >> + } >> > > It looks like this should also check if (X86SSELevel < SSE2) so that > it doesn't override when AutoDetectSubtargetFeatures detects an SSE > level greater than SSE2. With that fixed, this looks good. > Fixed. > >> } >> >> - // If requesting codegen for X86-64, make sure that 64-bit and SSE2 >> features >> - // are enabled. These are available on all x86-64 CPUs. >> + // If requesting codegen for X86-64, make sure that 64-bit features >> + // are enabled. >> if (Is64Bit) { >> HasX86_64 = true; >> } >> > > > Do you think it would make sense to move this up into the else clause > above too? I'm wondering if an assert(!Is64Bit || HasX86_64) after the > else would be a sane sanity check. > I tried that, but the assertion failed with llc -mcpu=yonah in one of the codegen tests, so I didn't move the if for now (added the assert though). I've committed r63552. Best regards, --Edwin From dalej at apple.com Mon Feb 2 16:12:51 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 02 Feb 2009 22:12:51 -0000 Subject: [llvm-commits] [llvm] r63555 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200902022212.n12MCppk022461@zion.cs.uiuc.edu> Author: johannes Date: Mon Feb 2 16:12:50 2009 New Revision: 63555 URL: http://llvm.org/viewvc/llvm-project?rev=63555&view=rev Log: DebugLoc propagation. ExpandOp and PromoteOp, among others. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63555&r1=63554&r2=63555&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Feb 2 16:12:50 2009 @@ -287,7 +287,7 @@ SDValue &Hi); SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl); - SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT); + SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl); SDValue ExpandBUILD_VECTOR(SDNode *Node); SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, @@ -299,12 +299,12 @@ SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned, DebugLoc dl); - SDValue ExpandBSWAP(SDValue Op); - SDValue ExpandBitCount(unsigned Opc, SDValue Op); + SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); + SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt, - SDValue &Lo, SDValue &Hi); + SDValue &Lo, SDValue &Hi, DebugLoc dl); void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt, - SDValue &Lo, SDValue &Hi); + SDValue &Lo, SDValue &Hi, DebugLoc dl); SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op); SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op); @@ -3725,7 +3725,7 @@ break; } case TargetLowering::Expand: - Result = ExpandBSWAP(Tmp1); + Result = ExpandBSWAP(Tmp1, dl); break; } break; @@ -3776,7 +3776,7 @@ break; } case TargetLowering::Expand: - Result = ExpandBitCount(Node->getOpcode(), Tmp1); + Result = ExpandBitCount(Node->getOpcode(), Tmp1, dl); break; } break; @@ -3933,7 +3933,7 @@ case ISD::BIT_CONVERT: if (!isTypeLegal(Node->getOperand(0).getValueType())) { Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), - Node->getValueType(0)); + Node->getValueType(0), dl); } else if (Op.getOperand(0).getValueType().isVector()) { // The input has to be a vector type, we have to either scalarize it, pack // it, or convert it based on whether the input vector type is legal. @@ -3965,7 +3965,7 @@ default: assert(0 && "Unknown operation action!"); case TargetLowering::Expand: Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), - Node->getValueType(0)); + Node->getValueType(0), dl); break; case TargetLowering::Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); @@ -4163,7 +4163,7 @@ if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { // The only other way we can lower this is to turn it into a STORE, // LOAD pair, targetting a temporary location (a stack slot). - Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); + Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT, dl); break; } switch (getTypeAction(Node->getOperand(0).getValueType())) { @@ -4193,7 +4193,7 @@ } // The only other way we can lower this is to turn it into a STORE, // LOAD pair, targetting a temporary location (a stack slot). - Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); + Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT, dl); break; } switch (getTypeAction(Node->getOperand(0).getValueType())) { @@ -4278,7 +4278,7 @@ // slots and always reusing the same one. We currently always create // new ones, as reuse may inhibit scheduling. Result = EmitStackConvert(Node->getOperand(0), ExtraVT, - Node->getValueType(0)); + Node->getValueType(0), dl); } else { assert(0 && "Unknown op"); } @@ -4483,6 +4483,7 @@ SDValue Tmp1, Tmp2, Tmp3; SDValue Result; SDNode *Node = Op.getNode(); + DebugLoc dl = Node->getDebugLoc(); DenseMap::iterator I = PromotedNodes.find(Op); if (I != PromotedNodes.end()) return I->second; @@ -4497,17 +4498,17 @@ assert(0 && "Do not know how to promote this operator!"); abort(); case ISD::UNDEF: - Result = DAG.getNode(ISD::UNDEF, NVT); + Result = DAG.getNode(ISD::UNDEF, dl, NVT); break; case ISD::Constant: if (VT != MVT::i1) - Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); + Result = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Op); else - Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); + Result = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Op); assert(isa(Result) && "Didn't constant fold zext?"); break; case ISD::ConstantFP: - Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); + Result = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op); assert(isa(Result) && "Didn't constant fold fp_extend?"); break; @@ -4515,7 +4516,7 @@ MVT VT0 = Node->getOperand(0).getValueType(); assert(isTypeLegal(TLI.getSetCCResultType(VT0)) && "SetCC type is not legal??"); - Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(VT0), + Result = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(VT0), Node->getOperand(0), Node->getOperand(1), Node->getOperand(2)); break; @@ -4527,7 +4528,7 @@ assert(Result.getValueType().bitsGE(NVT) && "This truncation doesn't make sense!"); if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT - Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); + Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Result); break; case Promote: // The truncation is not required, because we don't guarantee anything @@ -4537,7 +4538,7 @@ case Expand: ExpandOp(Node->getOperand(0), Tmp1, Tmp2); // Truncate the low part of the expanded value to the result type - Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); + Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Tmp1); } break; case ISD::SIGN_EXTEND: @@ -4547,17 +4548,17 @@ case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); case Legal: // Input is legal? Just do extend all the way to the larger type. - Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0)); break; case Promote: // Promote the reg if it's smaller. Result = PromoteOp(Node->getOperand(0)); // The high bits are not guaranteed to be anything. Insert an extend. if (Node->getOpcode() == ISD::SIGN_EXTEND) - Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, + Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result, DAG.getValueType(Node->getOperand(0).getValueType())); else if (Node->getOpcode() == ISD::ZERO_EXTEND) - Result = DAG.getZeroExtendInReg(Result, + Result = DAG.getZeroExtendInReg(Result, dl, Node->getOperand(0).getValueType()); break; } @@ -4577,7 +4578,7 @@ } case ISD::BIT_CONVERT: Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), - Node->getValueType(0)); + Node->getValueType(0), dl); Result = PromoteOp(Result); break; @@ -4590,11 +4591,11 @@ case Legal: if (Node->getConstantOperandVal(1) == 0) { // Input is legal? Do an FP_ROUND_INREG. - Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), + Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Node->getOperand(0), DAG.getValueType(VT)); } else { // Just remove the truncate, it isn't affecting the value. - Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), + Result = DAG.getNode(ISD::FP_ROUND, dl, NVT, Node->getOperand(0), Node->getOperand(1)); } break; @@ -4605,27 +4606,27 @@ switch (getTypeAction(Node->getOperand(0).getValueType())) { case Legal: // No extra round required here. - Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0)); break; case Promote: Result = PromoteOp(Node->getOperand(0)); if (Node->getOpcode() == ISD::SINT_TO_FP) - Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), + Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(), Result, DAG.getValueType(Node->getOperand(0).getValueType())); else - Result = DAG.getZeroExtendInReg(Result, + Result = DAG.getZeroExtendInReg(Result, dl, Node->getOperand(0).getValueType()); // No extra round required here. - Result = DAG.getNode(Node->getOpcode(), NVT, Result); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Result); break; case Expand: Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, - Node->getOperand(0), Node->getDebugLoc()); + Node->getOperand(0), dl); // Round if we cannot tolerate excess precision. if (NoExcessFPPrecision) - Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, + Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, DAG.getValueType(VT)); break; } @@ -4633,7 +4634,7 @@ case ISD::SIGN_EXTEND_INREG: Result = PromoteOp(Node->getOperand(0)); - Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, + Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result, Node->getOperand(1)); break; case ISD::FP_TO_SINT: @@ -4658,9 +4659,9 @@ !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) && (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) || TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ - Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); + Result = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Tmp1); } else { - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); } break; @@ -4668,7 +4669,7 @@ case ISD::FNEG: Tmp1 = PromoteOp(Node->getOperand(0)); assert(Tmp1.getValueType() == NVT); - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); // NOTE: we do not have to do any extra rounding here for // NoExcessFPPrecision, because we know the input will have the appropriate // precision, and these operations don't modify precision at all. @@ -4689,9 +4690,9 @@ case ISD::FNEARBYINT: Tmp1 = PromoteOp(Node->getOperand(0)); assert(Tmp1.getValueType() == NVT); - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); if (NoExcessFPPrecision) - Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, + Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, DAG.getValueType(VT)); break; @@ -4704,9 +4705,9 @@ if (Node->getOpcode() == ISD::FPOW) Tmp2 = PromoteOp(Tmp2); assert(Tmp1.getValueType() == NVT); - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); if (NoExcessFPPrecision) - Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, + Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, DAG.getValueType(VT)); break; } @@ -4715,7 +4716,7 @@ AtomicSDNode* AtomNode = cast(Node); Tmp2 = PromoteOp(Node->getOperand(2)); Tmp3 = PromoteOp(Node->getOperand(3)); - Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getMemoryVT(), + Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(), AtomNode->getChain(), AtomNode->getBasePtr(), Tmp2, Tmp3, AtomNode->getSrcValue(), @@ -4737,7 +4738,7 @@ case ISD::ATOMIC_SWAP: { AtomicSDNode* AtomNode = cast(Node); Tmp2 = PromoteOp(Node->getOperand(2)); - Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getMemoryVT(), + Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(), AtomNode->getChain(), AtomNode->getBasePtr(), Tmp2, AtomNode->getSrcValue(), @@ -4759,7 +4760,7 @@ Tmp1 = PromoteOp(Node->getOperand(0)); Tmp2 = PromoteOp(Node->getOperand(1)); assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); break; case ISD::FADD: case ISD::FSUB: @@ -4767,7 +4768,7 @@ Tmp1 = PromoteOp(Node->getOperand(0)); Tmp2 = PromoteOp(Node->getOperand(1)); assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); // Floating point operations will give excess precision that we may not be // able to tolerate. If we DO allow excess precision, just leave it, @@ -4775,7 +4776,7 @@ // FIXME: Why would we need to round FP ops more than integer ones? // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) if (NoExcessFPPrecision) - Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, + Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, DAG.getValueType(VT)); break; @@ -4785,16 +4786,16 @@ Tmp1 = PromoteOp(Node->getOperand(0)); Tmp2 = PromoteOp(Node->getOperand(1)); if (NVT.isInteger()) { - Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, + Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1, DAG.getValueType(VT)); - Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, + Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2, DAG.getValueType(VT)); } - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); // Perform FP_ROUND: this is probably overly pessimistic. if (NVT.isFloatingPoint() && NoExcessFPPrecision) - Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, + Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, DAG.getValueType(VT)); break; case ISD::FDIV: @@ -4811,11 +4812,11 @@ case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; } - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); // Perform FP_ROUND: this is probably overly pessimistic. if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) - Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, + Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, DAG.getValueType(VT)); break; @@ -4825,27 +4826,27 @@ Tmp1 = PromoteOp(Node->getOperand(0)); Tmp2 = PromoteOp(Node->getOperand(1)); assert(NVT.isInteger() && "Operators don't apply to FP!"); - Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); - Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); + Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT); + Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); break; case ISD::SHL: Tmp1 = PromoteOp(Node->getOperand(0)); - Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); + Result = DAG.getNode(ISD::SHL, dl, NVT, Tmp1, Node->getOperand(1)); break; case ISD::SRA: // The input value must be properly sign extended. Tmp1 = PromoteOp(Node->getOperand(0)); - Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, + Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1, DAG.getValueType(VT)); - Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); + Result = DAG.getNode(ISD::SRA, dl, NVT, Tmp1, Node->getOperand(1)); break; case ISD::SRL: // The input value must be properly zero extended. Tmp1 = PromoteOp(Node->getOperand(0)); - Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); - Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); + Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT); + Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, Node->getOperand(1)); break; case ISD::VAARG: @@ -4858,13 +4859,13 @@ const Value *V = cast(Node->getOperand(2))->getValue(); SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); // Increment the pointer, VAList, to the next vaarg - Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, + Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, DAG.getConstant(VT.getSizeInBits()/8, TLI.getPointerTy())); // Store the incremented VAList to the legalized pointer - Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); + Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0); // Load the actual argument out of the pointer VAList - Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); + Result = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Tmp3, VAList, NULL, 0, VT); } // Remember that we legalized the chain. AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); @@ -4874,7 +4875,7 @@ LoadSDNode *LD = cast(Node); ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) ? ISD::EXTLOAD : LD->getExtensionType(); - Result = DAG.getExtLoad(ExtType, NVT, + Result = DAG.getExtLoad(ExtType, dl, NVT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), LD->getSrcValueOffset(), LD->getMemoryVT(), @@ -4894,20 +4895,20 @@ // Ensure that the resulting node is at least the same size as the operands' // value types, because we cannot assume that TLI.getSetCCValueType() is // constant. - Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3); + Result = DAG.getNode(ISD::SELECT, dl, VT2, Node->getOperand(0), Tmp2, Tmp3); break; } case ISD::SELECT_CC: Tmp2 = PromoteOp(Node->getOperand(2)); // True Tmp3 = PromoteOp(Node->getOperand(3)); // False - Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), + Result = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0), Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); break; case ISD::BSWAP: Tmp1 = Node->getOperand(0); - Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); - Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); - Result = DAG.getNode(ISD::SRL, NVT, Tmp1, + Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); + Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); + Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, DAG.getConstant(NVT.getSizeInBits() - VT.getSizeInBits(), TLI.getShiftAmountTy())); @@ -4916,24 +4917,24 @@ case ISD::CTTZ: case ISD::CTLZ: // Zero extend the argument - Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); + Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); // Perform the larger operation, then subtract if needed. - Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); + Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); switch(Node->getOpcode()) { case ISD::CTPOP: Result = Tmp1; break; case ISD::CTTZ: // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) - Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1, + Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), ISD::SETEQ); - Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, + Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1); break; case ISD::CTLZ: //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) - Result = DAG.getNode(ISD::SUB, NVT, Tmp1, + Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, DAG.getConstant(NVT.getSizeInBits() - VT.getSizeInBits(), NVT)); break; @@ -5385,7 +5386,8 @@ /// The resultant code need not be legal. SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, MVT SlotVT, - MVT DestVT) { + MVT DestVT, + DebugLoc dl) { // Create the stack frame object. unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment( SrcOp.getValueType().getTypeForMVT()); @@ -5406,24 +5408,25 @@ SDValue Store; if (SrcSize > SlotSize) - Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, + Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, SV, 0, SlotVT, false, SrcAlign); else { assert(SrcSize == SlotSize && "Invalid store"); - Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, + Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, SV, 0, false, SrcAlign); } // Result is a load from the stack slot. if (SlotSize == DestSize) - return DAG.getLoad(DestVT, Store, FIPtr, SV, 0, false, DestAlign); + return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign); assert(SlotSize < DestSize && "Unknown extension!"); - return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, SV, 0, SlotVT, + return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT, false, DestAlign); } SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { + DebugLoc dl = Node->getDebugLoc(); // Create a vector sized/aligned stack slot, store the value to element #0, // then load the whole vector back out. SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); @@ -5431,9 +5434,10 @@ FrameIndexSDNode *StackPtrFI = cast(StackPtr); int SPFI = StackPtrFI->getIndex(); - SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, + SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(0), + StackPtr, PseudoSourceValue::getFixedStack(SPFI), 0); - return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, + return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, PseudoSourceValue::getFixedStack(SPFI), 0); } @@ -5447,6 +5451,7 @@ unsigned NumElems = Node->getNumOperands(); bool isOnlyLowElement = true; SDValue SplatValue = Node->getOperand(0); + DebugLoc dl = Node->getDebugLoc(); // FIXME: it would be far nicer to change this into map // and use a bitmask instead of a list of elements. @@ -5475,9 +5480,9 @@ if (isOnlyLowElement) { // If the low element is an undef too, then this whole things is an undef. if (Node->getOperand(0).getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); + return DAG.getNode(ISD::UNDEF, dl, Node->getValueType(0)); // Otherwise, turn this into a scalar_to_vector node. - return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), + return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, Node->getValueType(0), Node->getOperand(0)); } @@ -5502,7 +5507,7 @@ Constant *CP = ConstantVector::get(CV); SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); unsigned Alignment = 1 << cast(CPIdx)->getAlignment(); - return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, + return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, false, Alignment); } @@ -5512,17 +5517,19 @@ MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType()); std::vector ZeroVec(NumElems, Zero); - SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &ZeroVec[0], ZeroVec.size()); // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. if (isShuffleLegal(Node->getValueType(0), SplatMask)) { // Get the splatted value into the low element of a vector register. SDValue LowValVec = - DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); + DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, + Node->getValueType(0), SplatValue); // Return shuffle(LowValVec, undef, <0,0,0,0>) - return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, + return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, + Node->getValueType(0), LowValVec, DAG.getNode(ISD::UNDEF, Node->getValueType(0)), SplatMask); } @@ -5561,21 +5568,21 @@ if (Val2.getOpcode() != ISD::UNDEF) MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT); else - MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT); + MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, dl, MaskEltVT); - SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], MaskVec.size()); // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && isShuffleLegal(Node->getValueType(0), ShuffleMask)) { - Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1); - Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2); + Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val1); + Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val2); SDValue Ops[] = { Val1, Val2, ShuffleMask }; // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) - return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3); + return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,Node->getValueType(0), Ops, 3); } } @@ -5599,33 +5606,34 @@ unsigned Offset = TypeByteSize*i; SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); - Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); + Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); - Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, - SV, Offset)); + Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i), + Idx, SV, Offset)); } SDValue StoreChain; if (!Stores.empty()) // Not all undef elements? - StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, + StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], Stores.size()); else StoreChain = DAG.getEntryNode(); // Result is a load from the stack slot. - return DAG.getLoad(VT, StoreChain, FIPtr, SV, 0); + return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0); } void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt, - SDValue &Lo, SDValue &Hi) { + SDValue &Lo, SDValue &Hi, + DebugLoc dl) { // Expand the subcomponents. SDValue LHSL, LHSH; ExpandOp(Op, LHSL, LHSH); SDValue Ops[] = { LHSL, LHSH, Amt }; MVT VT = LHSL.getValueType(); - Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); + Lo = DAG.getNode(NodeOp, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); Hi = Lo.getValue(1); } @@ -5635,7 +5643,8 @@ /// libcall on this target, return false. Otherwise, return true with the /// low-parts expanded into Lo and Hi. bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt, - SDValue &Lo, SDValue &Hi) { + SDValue &Lo, SDValue &Hi, + DebugLoc dl) { assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && "This is not a shift!"); @@ -5659,15 +5668,17 @@ Hi = DAG.getConstant(0, NVT); } else if (Cst > NVTBits) { Lo = DAG.getConstant(0, NVT); - Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); + Hi = DAG.getNode(ISD::SHL, dl, + NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); } else if (Cst == NVTBits) { Lo = DAG.getConstant(0, NVT); Hi = InL; } else { - Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); - Hi = DAG.getNode(ISD::OR, NVT, - DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), - DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); + Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)); + Hi = DAG.getNode(ISD::OR, dl, NVT, + DAG.getNode(ISD::SHL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)), + DAG.getNode(ISD::SRL, dl, NVT, InL, + DAG.getConstant(NVTBits-Cst, ShTy))); } return true; case ISD::SRL: @@ -5675,36 +5686,39 @@ Lo = DAG.getConstant(0, NVT); Hi = DAG.getConstant(0, NVT); } else if (Cst > NVTBits) { - Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); + Lo = DAG.getNode(ISD::SRL, dl, NVT, + InH, DAG.getConstant(Cst-NVTBits,ShTy)); Hi = DAG.getConstant(0, NVT); } else if (Cst == NVTBits) { Lo = InH; Hi = DAG.getConstant(0, NVT); } else { - Lo = DAG.getNode(ISD::OR, NVT, - DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), - DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); - Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); + Lo = DAG.getNode(ISD::OR, dl, NVT, + DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)), + DAG.getNode(ISD::SHL, dl, NVT, InH, + DAG.getConstant(NVTBits-Cst, ShTy))); + Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)); } return true; case ISD::SRA: if (Cst > VTBits) { - Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, + Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(NVTBits-1, ShTy)); } else if (Cst > NVTBits) { - Lo = DAG.getNode(ISD::SRA, NVT, InH, + Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Cst-NVTBits, ShTy)); - Hi = DAG.getNode(ISD::SRA, NVT, InH, + Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(NVTBits-1, ShTy)); } else if (Cst == NVTBits) { Lo = InH; - Hi = DAG.getNode(ISD::SRA, NVT, InH, + Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(NVTBits-1, ShTy)); } else { - Lo = DAG.getNode(ISD::OR, NVT, - DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), - DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); - Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); + Lo = DAG.getNode(ISD::OR, dl, NVT, + DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)), + DAG.getNode(ISD::SHL, dl, + NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); + Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Cst, ShTy)); } return true; } @@ -5720,7 +5734,7 @@ // we can do this as a couple of simple shifts. if (KnownOne.intersects(Mask)) { // Mask out the high bit, which we know is set. - Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, + Amt = DAG.getNode(ISD::AND, dl, Amt.getValueType(), Amt, DAG.getConstant(~Mask, Amt.getValueType())); // Expand the incoming operand to be shifted, so that we have its parts @@ -5729,16 +5743,16 @@ switch(Opc) { case ISD::SHL: Lo = DAG.getConstant(0, NVT); // Low part is zero. - Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. + Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. return true; case ISD::SRL: Hi = DAG.getConstant(0, NVT); // Hi part is zero. - Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. + Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. return true; case ISD::SRA: - Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. + Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. DAG.getConstant(NVTBits-1, Amt.getValueType())); - Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. + Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. return true; } } @@ -5747,7 +5761,7 @@ // do this as a couple of simple shifts. if ((KnownZero & Mask) == Mask) { // Compute 32-amt. - SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), + SDValue Amt2 = DAG.getNode(ISD::SUB, dl, Amt.getValueType(), DAG.getConstant(NVTBits, Amt.getValueType()), Amt); @@ -5756,22 +5770,22 @@ ExpandOp(Op, InL, InH); switch(Opc) { case ISD::SHL: - Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); - Hi = DAG.getNode(ISD::OR, NVT, - DAG.getNode(ISD::SHL, NVT, InH, Amt), - DAG.getNode(ISD::SRL, NVT, InL, Amt2)); + Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); + Hi = DAG.getNode(ISD::OR, dl, NVT, + DAG.getNode(ISD::SHL, dl, NVT, InH, Amt), + DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2)); return true; case ISD::SRL: - Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); - Lo = DAG.getNode(ISD::OR, NVT, - DAG.getNode(ISD::SRL, NVT, InL, Amt), - DAG.getNode(ISD::SHL, NVT, InH, Amt2)); + Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); + Lo = DAG.getNode(ISD::OR, dl, NVT, + DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), + DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2)); return true; case ISD::SRA: - Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); - Lo = DAG.getNode(ISD::OR, NVT, - DAG.getNode(ISD::SRL, NVT, InL, Amt), - DAG.getNode(ISD::SHL, NVT, InH, Amt2)); + Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); + Lo = DAG.getNode(ISD::OR, dl, NVT, + DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), + DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2)); return true; } } @@ -6262,54 +6276,55 @@ /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. /// -SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) { +SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { MVT VT = Op.getValueType(); MVT SHVT = TLI.getShiftAmountTy(); SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; switch (VT.getSimpleVT()) { default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); case MVT::i16: - Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); - Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); - return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); + Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); + Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); + return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); case MVT::i32: - Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); - Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); - Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); - Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); - Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); - Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); - Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); - Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); - return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); + Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); + Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); + Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); + Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); + Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); + Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); + Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); + Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); + return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); case MVT::i64: - Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); - Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); - Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); - Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); - Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); - Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); - Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); - Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); - Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); - Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); - Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); - Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); - Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); - Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); - Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); - Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); - Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); - Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); - Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); - Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); - return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); + Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); + Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); + Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); + Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); + Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); + Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); + Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); + Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); + Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); + Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); + Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); + Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); + Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); + Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); + Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); + Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); + Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); + Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); + Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); + Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); + return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); } } /// ExpandBitCount - Expand the specified bitcount instruction into operations. /// -SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) { +SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, + DebugLoc dl) { switch (Opc) { default: assert(0 && "Cannot expand this yet!"); case ISD::CTPOP: { @@ -6327,9 +6342,10 @@ VT.getVectorElementType().getSizeInBits() : len; SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); - Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), - DAG.getNode(ISD::AND, VT, - DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); + Op = DAG.getNode(ISD::ADD, dl, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), + DAG.getNode(ISD::AND, dl, VT, + DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), + Tmp2)); } return Op; } @@ -6348,10 +6364,11 @@ unsigned len = VT.getSizeInBits(); for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); - Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); + Op = DAG.getNode(ISD::OR, dl, VT, Op, + DAG.getNode(ISD::SRL, VT, Op, Tmp3)); } - Op = DAG.getNOT(DebugLoc::getUnknownLoc(), Op, VT); - return DAG.getNode(ISD::CTPOP, VT, Op); + Op = DAG.getNOT(dl, Op, VT); + return DAG.getNode(ISD::CTPOP, dl, VT, Op); } case ISD::CTTZ: { // for now, we use: { return popcount(~x & (x - 1)); } @@ -6359,17 +6376,17 @@ // { return 32 - nlz(~x & (x-1)); } // see also http://www.hackersdelight.org/HDcode/ntz.cc MVT VT = Op.getValueType(); - SDValue Tmp3 = DAG.getNode(ISD::AND, VT, - DAG.getNOT(DebugLoc::getUnknownLoc(), Op, VT), - DAG.getNode(ISD::SUB, VT, Op, + SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, + DAG.getNOT(dl, Op, VT), + DAG.getNode(ISD::SUB, dl, VT, Op, DAG.getConstant(1, VT))); // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) - return DAG.getNode(ISD::SUB, VT, + return DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(VT.getSizeInBits(), VT), - DAG.getNode(ISD::CTLZ, VT, Tmp3)); - return DAG.getNode(ISD::CTPOP, VT, Tmp3); + DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); + return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); } } } @@ -6383,6 +6400,7 @@ MVT VT = Op.getValueType(); MVT NVT = TLI.getTypeToTransformTo(VT); SDNode *Node = Op.getNode(); + DebugLoc dl = Node->getDebugLoc(); assert(getTypeAction(VT) == Expand && "Not an expanded type!"); assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() || VT.isVector()) && "Cannot expand to FP value or to larger int value!"); @@ -6405,9 +6423,9 @@ TargetLowering::Custom) { SDValue SrcLo, SrcHi, Src; ExpandOp(Op.getOperand(0), SrcLo, SrcHi); - Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); + Src = DAG.getNode(ISD::BUILD_PAIR, dl, VT, SrcLo, SrcHi); SDValue Result = TLI.LowerOperation( - DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); + DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src, Op.getOperand(1)), DAG); assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR); Lo = Result.getNode()->getOperand(0); Hi = Result.getNode()->getOperand(1); @@ -6430,8 +6448,8 @@ Lo = ExpandEXTRACT_VECTOR_ELT(Op); return ExpandOp(Lo, Lo, Hi); case ISD::UNDEF: - Lo = DAG.getNode(ISD::UNDEF, NVT); - Hi = DAG.getNode(ISD::UNDEF, NVT); + Lo = DAG.getNode(ISD::UNDEF, dl, NVT); + Hi = DAG.getNode(ISD::UNDEF, dl, NVT); break; case ISD::Constant: { unsigned NVTBits = NVT.getSizeInBits(); @@ -6478,28 +6496,28 @@ case ISD::SIGN_EXTEND_INREG: ExpandOp(Node->getOperand(0), Lo, Hi); // sext_inreg the low part if needed. - Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); + Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Lo, Node->getOperand(1)); // The high part gets the sign extension from the lo-part. This handles // things like sextinreg V:i64 from i8. - Hi = DAG.getNode(ISD::SRA, NVT, Lo, + Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, DAG.getConstant(NVT.getSizeInBits()-1, TLI.getShiftAmountTy())); break; case ISD::BSWAP: { ExpandOp(Node->getOperand(0), Lo, Hi); - SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); - Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); + SDValue TempLo = DAG.getNode(ISD::BSWAP, dl, NVT, Hi); + Hi = DAG.getNode(ISD::BSWAP, dl, NVT, Lo); Lo = TempLo; break; } case ISD::CTPOP: ExpandOp(Node->getOperand(0), Lo, Hi); - Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) - DAG.getNode(ISD::CTPOP, NVT, Lo), - DAG.getNode(ISD::CTPOP, NVT, Hi)); + Lo = DAG.getNode(ISD::ADD, dl, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) + DAG.getNode(ISD::CTPOP, dl, NVT, Lo), + DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); Hi = DAG.getConstant(0, NVT); break; @@ -6507,13 +6525,13 @@ // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) ExpandOp(Node->getOperand(0), Lo, Hi); SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); - SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); - SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), HLZ, BitsC, - ISD::SETNE); - SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); - LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); + SDValue HLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi); + SDValue TopNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), HLZ, + BitsC, ISD::SETNE); + SDValue LowPart = DAG.getNode(ISD::CTLZ, dl, NVT, Lo); + LowPart = DAG.getNode(ISD::ADD, dl, NVT, LowPart, BitsC); - Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); + Lo = DAG.getNode(ISD::SELECT, dl, NVT, TopNotZero, HLZ, LowPart); Hi = DAG.getConstant(0, NVT); break; } @@ -6522,13 +6540,13 @@ // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) ExpandOp(Node->getOperand(0), Lo, Hi); SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); - SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); - SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), LTZ, BitsC, - ISD::SETNE); - SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); - HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); + SDValue LTZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo); + SDValue BotNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), LTZ, + BitsC, ISD::SETNE); + SDValue HiPart = DAG.getNode(ISD::CTTZ, dl, NVT, Hi); + HiPart = DAG.getNode(ISD::ADD, dl, NVT, HiPart, BitsC); - Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); + Lo = DAG.getNode(ISD::SELECT, dl, NVT, BotNotZero, LTZ, HiPart); Hi = DAG.getConstant(0, NVT); break; } @@ -6558,7 +6576,7 @@ bool isVolatile = LD->isVolatile(); if (ExtType == ISD::NON_EXTLOAD) { - Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset, + Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); if (VT == MVT::f32 || VT == MVT::f64) { // f32->i32 or f64->i64 one to one expansion. @@ -6572,16 +6590,16 @@ // Increment the pointer to the other half. unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; - Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, + Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); SVOffset += IncrementSize; Alignment = MinAlign(Alignment, IncrementSize); - Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset, + Hi = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); // Build a factor node to remember that this load is independent of the // other one. - SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), + SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), Hi.getValue(1)); // Remember that we legalized the chain. @@ -6594,19 +6612,19 @@ if ((VT == MVT::f64 && EVT == MVT::f32) || (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND - SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV, + SDValue Load = DAG.getLoad(EVT, dl, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); // Remember that we legalized the chain. AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1))); - ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); + ExpandOp(DAG.getNode(ISD::FP_EXTEND, dl, VT, Load), Lo, Hi); break; } if (EVT == NVT) - Lo = DAG.getLoad(NVT, Ch, Ptr, SV, + Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); else - Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV, + Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, SV, SVOffset, EVT, isVolatile, Alignment); @@ -6617,14 +6635,14 @@ // The high part is obtained by SRA'ing all but one of the bits of the // lo part. unsigned LoSize = Lo.getValueType().getSizeInBits(); - Hi = DAG.getNode(ISD::SRA, NVT, Lo, + Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); } else if (ExtType == ISD::ZEXTLOAD) { // The high part is just a zero. Hi = DAG.getConstant(0, NVT); } else /* if (ExtType == ISD::EXTLOAD) */ { // The high part is undefined. - Hi = DAG.getNode(ISD::UNDEF, NVT); + Hi = DAG.getNode(ISD::UNDEF, dl, NVT); } } break; @@ -6635,8 +6653,8 @@ SDValue LL, LH, RL, RH; ExpandOp(Node->getOperand(0), LL, LH); ExpandOp(Node->getOperand(1), RL, RH); - Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); - Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); + Lo = DAG.getNode(Node->getOpcode(), dl, NVT, LL, RL); + Hi = DAG.getNode(Node->getOpcode(), dl, NVT, LH, RH); break; } case ISD::SELECT: { @@ -6645,9 +6663,9 @@ ExpandOp(Node->getOperand(2), RL, RH); if (getTypeAction(NVT) == Expand) NVT = TLI.getTypeToExpandTo(NVT); - Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); + Lo = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LL, RL); if (VT != MVT::f32) - Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); + Hi = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LH, RH); break; } case ISD::SELECT_CC: { @@ -6656,35 +6674,35 @@ ExpandOp(Node->getOperand(3), FL, FH); if (getTypeAction(NVT) == Expand) NVT = TLI.getTypeToExpandTo(NVT); - Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), + Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0), Node->getOperand(1), TL, FL, Node->getOperand(4)); if (VT != MVT::f32) - Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), + Hi = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0), Node->getOperand(1), TH, FH, Node->getOperand(4)); break; } case ISD::ANY_EXTEND: // The low part is any extension of the input (which degenerates to a copy). - Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); + Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0)); // The high part is undefined. - Hi = DAG.getNode(ISD::UNDEF, NVT); + Hi = DAG.getNode(ISD::UNDEF, dl, NVT); break; case ISD::SIGN_EXTEND: { // The low part is just a sign extension of the input (which degenerates to // a copy). - Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); + Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Node->getOperand(0)); // The high part is obtained by SRA'ing all but one of the bits of the lo // part. unsigned LoSize = Lo.getValueType().getSizeInBits(); - Hi = DAG.getNode(ISD::SRA, NVT, Lo, + Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); break; } case ISD::ZERO_EXTEND: // The low part is just a zero extension of the input (which degenerates to // a copy). - Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); + Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); // The high part is just a zero. Hi = DAG.getConstant(0, NVT); @@ -6698,7 +6716,7 @@ // The low part is now either the right size, or it is closer. If not the // right size, make an illegal truncate so we recursively expand it. if (NewLo.getValueType() != Node->getValueType(0)) - NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); + NewLo = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), NewLo); ExpandOp(NewLo, Lo, Hi); break; } @@ -6712,12 +6730,12 @@ case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; } - Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); + Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp), DAG); } // f32 / f64 must be expanded to i32 / i64. if (VT == MVT::f32 || VT == MVT::f64) { - Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); + Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); if (getTypeAction(NVT) == Expand) ExpandOp(Lo, Lo, Hi); break; @@ -6733,7 +6751,7 @@ // Turn this into a load/store pair by default. if (Tmp.getNode() == 0) - Tmp = EmitStackConvert(Node->getOperand(0), VT, VT); + Tmp = EmitStackConvert(Node->getOperand(0), VT, VT, dl); ExpandOp(Tmp, Lo, Hi); break; @@ -6772,10 +6790,10 @@ // so substitute a target-dependent pseudo and expand that later. SDValue In2Lo, In2Hi, In2; ExpandOp(Op.getOperand(2), In2Lo, In2Hi); - In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi); + In2 = DAG.getNode(ISD::BUILD_PAIR, dl, VT, In2Lo, In2Hi); AtomicSDNode* Anode = cast(Node); SDValue Replace = - DAG.getAtomic(Op.getOpcode(), Anode->getMemoryVT(), + DAG.getAtomic(Op.getOpcode(), dl, Anode->getMemoryVT(), Op.getOperand(0), Op.getOperand(1), In2, Anode->getSrcValue(), Anode->getAlignment()); SDValue Result = TLI.LowerOperation(Replace, DAG); @@ -6796,7 +6814,7 @@ case Promote: Op = PromoteOp (Node->getOperand(0)); break; } - Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); + Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op), DAG); // Now that the custom expander is done, expand the result, which is still // VT. @@ -6822,7 +6840,7 @@ case Promote: Op = PromoteOp (Node->getOperand(0)); break; } - Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); + Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op), DAG); // Now that the custom expander is done, expand the result. if (Op.getNode()) { @@ -6842,7 +6860,7 @@ // If the target wants custom lowering, do so. SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { - SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); + SDValue Op = DAG.getNode(ISD::SHL, dl, VT, Node->getOperand(0), ShiftAmt); Op = TLI.LowerOperation(Op, DAG); if (Op.getNode()) { // Now that the custom expander is done, expand the result, which is @@ -6862,17 +6880,17 @@ ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); LoOps[1] = LoOps[0]; - Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); + Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); HiOps[1] = HiOps[0]; HiOps[2] = Lo.getValue(1); - Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); + Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); break; } } // If we can emit an efficient shift operation, do so now. - if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) + if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl)) break; // If this target supports SHL_PARTS, use it. @@ -6880,7 +6898,8 @@ TLI.getOperationAction(ISD::SHL_PARTS, NVT); if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || Action == TargetLowering::Custom) { - ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); + ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), + ShiftAmt, Lo, Hi, dl); break; } @@ -6904,7 +6923,7 @@ } // If we can emit an efficient shift operation, do so now. - if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) + if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi, dl)) break; // If this target supports SRA_PARTS, use it. @@ -6912,7 +6931,8 @@ TLI.getOperationAction(ISD::SRA_PARTS, NVT); if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || Action == TargetLowering::Custom) { - ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); + ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), + ShiftAmt, Lo, Hi, dl); break; } @@ -6925,7 +6945,7 @@ // If the target wants custom lowering, do so. SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { - SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); + SDValue Op = DAG.getNode(ISD::SRL, dl, VT, Node->getOperand(0), ShiftAmt); Op = TLI.LowerOperation(Op, DAG); if (Op.getNode()) { // Now that the custom expander is done, expand the result, which is @@ -6936,7 +6956,7 @@ } // If we can emit an efficient shift operation, do so now. - if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) + if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl)) break; // If this target supports SRL_PARTS, use it. @@ -6944,7 +6964,8 @@ TLI.getOperationAction(ISD::SRL_PARTS, NVT); if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || Action == TargetLowering::Custom) { - ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); + ExpandShiftParts(ISD::SRL_PARTS, + Node->getOperand(0), ShiftAmt, Lo, Hi, dl); break; } @@ -6988,38 +7009,38 @@ if(hasCarry) { SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); if (Node->getOpcode() == ISD::ADD) { - Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); + Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); HiOps[2] = Lo.getValue(1); - Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); + Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); } else { - Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); + Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); HiOps[2] = Lo.getValue(1); - Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); + Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); } break; } else { if (Node->getOpcode() == ISD::ADD) { - Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2); - Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2); - SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(NVT), + Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2); + Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2); + SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0], ISD::SETULT); - SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1, + SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1, DAG.getConstant(1, NVT), DAG.getConstant(0, NVT)); - SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(NVT), + SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1], ISD::SETULT); - SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2, + SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2, DAG.getConstant(1, NVT), Carry1); - Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2); + Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2); } else { - Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2); - Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2); - SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT); - SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp, + Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); + Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2); + SDValue Cmp = DAG.getSetCC(dl, NVT, LoOps[0], LoOps[1], ISD::SETULT); + SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, DAG.getConstant(1, NVT), DAG.getConstant(0, NVT)); - Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow); + Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow); } break; } @@ -7036,13 +7057,13 @@ SDValue HiOps[3] = { LHSH, RHSH }; if (Node->getOpcode() == ISD::ADDC) { - Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); + Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); HiOps[2] = Lo.getValue(1); - Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); + Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); } else { - Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); + Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); HiOps[2] = Lo.getValue(1); - Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); + Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); } // Remember that we legalized the flag. AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); @@ -7058,9 +7079,9 @@ SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; SDValue HiOps[3] = { LHSH, RHSH }; - Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); + Lo = DAG.getNode(Node->getOpcode(), dl, VTList, LoOps, 3); HiOps[2] = Lo.getValue(1); - Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); + Hi = DAG.getNode(Node->getOpcode(), dl, VTList, HiOps, 3); // Remember that we legalized the flag. AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); @@ -7094,14 +7115,14 @@ // The inputs are both zero-extended. if (HasUMUL_LOHI) { // We can emit a umul_lohi. - Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); + Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); Hi = SDValue(Lo.getNode(), 1); break; } if (HasMULHU) { // We can emit a mulhu+mul. - Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); - Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); + Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); + Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); break; } } @@ -7109,36 +7130,36 @@ // The input values are both sign-extended. if (HasSMUL_LOHI) { // We can emit a smul_lohi. - Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); + Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); Hi = SDValue(Lo.getNode(), 1); break; } if (HasMULHS) { // We can emit a mulhs+mul. - Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); - Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); + Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); + Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL); break; } } if (HasUMUL_LOHI) { // Lo,Hi = umul LHS, RHS. - SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, + SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); Lo = UMulLOHI; Hi = UMulLOHI.getValue(1); - RH = DAG.getNode(ISD::MUL, NVT, LL, RH); - LH = DAG.getNode(ISD::MUL, NVT, LH, RL); - Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); - Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); + RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); + LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); + Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); + Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); break; } if (HasMULHU) { - Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); - Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); - RH = DAG.getNode(ISD::MUL, NVT, LL, RH); - LH = DAG.getNode(ISD::MUL, NVT, LH, RL); - Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); - Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); + Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); + Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); + RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); + LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); + Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); + Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); break; } } @@ -7194,7 +7215,7 @@ Node->getOperand(0).getValueType()==MVT::f64); const uint64_t zero = 0; if (Node->getOperand(0).getValueType()==MVT::f32) - Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); + Hi = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Node->getOperand(0)); else Hi = Node->getOperand(0); Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); @@ -7298,19 +7319,19 @@ if (VT == MVT::ppcf128) { SDValue Tmp; ExpandOp(Node->getOperand(0), Lo, Tmp); - Hi = DAG.getNode(ISD::FABS, NVT, Tmp); + Hi = DAG.getNode(ISD::FABS, dl, NVT, Tmp); // lo = hi==fabs(hi) ? lo : -lo; - Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, - Lo, DAG.getNode(ISD::FNEG, NVT, Lo), + Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Hi, Tmp, + Lo, DAG.getNode(ISD::FNEG, dl, NVT, Lo), DAG.getCondCode(ISD::SETEQ)); break; } SDValue Mask = (VT == MVT::f64) ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); - Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); - Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); - Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); + Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask); + Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); + Lo = DAG.getNode(ISD::AND, dl, NVT, Lo, Mask); if (getTypeAction(NVT) == Expand) ExpandOp(Lo, Lo, Hi); break; @@ -7318,16 +7339,16 @@ case ISD::FNEG: { if (VT == MVT::ppcf128) { ExpandOp(Node->getOperand(0), Lo, Hi); - Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); - Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); + Lo = DAG.getNode(ISD::FNEG, dl, MVT::f64, Lo); + Hi = DAG.getNode(ISD::FNEG, dl, MVT::f64, Hi); break; } SDValue Mask = (VT == MVT::f64) ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) : DAG.getConstantFP(BitsToFloat(1U << 31), VT); - Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); - Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); - Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); + Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask); + Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); + Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Mask); if (getTypeAction(NVT) == Expand) ExpandOp(Lo, Lo, Hi); break; @@ -7348,9 +7369,9 @@ if (getTypeAction(SrcVT) == Promote) { SDValue Tmp = PromoteOp(Node->getOperand(0)); Tmp = isSigned - ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, + ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp.getValueType(), Tmp, DAG.getValueType(SrcVT)) - : DAG.getZeroExtendInReg(Tmp, SrcVT); + : DAG.getZeroExtendInReg(Tmp, dl, SrcVT); Node = DAG.UpdateNodeOperands(Op, Tmp).getNode(); SrcVT = Node->getOperand(0).getValueType(); } @@ -7358,19 +7379,20 @@ if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { static const uint64_t zero = 0; if (isSigned) { - Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, + Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64, Node->getOperand(0))); Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); } else { static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; - Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, + Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64, Node->getOperand(0))); Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); - Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); + Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi); // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 - ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), + ExpandOp(DAG.getNode(ISD::SELECT_CC, dl, + MVT::ppcf128, Node->getOperand(0), DAG.getConstant(0, MVT::i32), - DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, + DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi, DAG.getConstantFP( APFloat(APInt(128, 2, TwoE32)), MVT::ppcf128)), @@ -7383,13 +7405,14 @@ if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { // si64->ppcf128 done by libcall, below static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; - ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), - Lo, Hi); - Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); + ExpandOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::ppcf128, + Node->getOperand(0)), Lo, Hi); + Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi); // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 - ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), + ExpandOp(DAG.getNode(ISD::SELECT_CC, dl, MVT::ppcf128, + Node->getOperand(0), DAG.getConstant(0, MVT::i64), - DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, + DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi, DAG.getConstantFP( APFloat(APInt(128, 2, TwoE64)), MVT::ppcf128)), @@ -7400,7 +7423,7 @@ } Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, - Node->getOperand(0), Node->getDebugLoc()); + Node->getOperand(0), dl); if (getTypeAction(Lo.getValueType()) == Expand) // float to i32 etc. can be 'expanded' to a single node. ExpandOp(Lo, Lo, Hi); From resistor at mac.com Mon Feb 2 16:42:01 2009 From: resistor at mac.com (Owen Anderson) Date: Mon, 02 Feb 2009 22:42:01 -0000 Subject: [llvm-commits] [llvm] r63558 - in /llvm/trunk: include/llvm/CodeGen/LiveInterval.h lib/CodeGen/LiveInterval.cpp lib/CodeGen/PreAllocSplitting.cpp Message-ID: <200902022242.n12Mg2ct023436@zion.cs.uiuc.edu> Author: resistor Date: Mon Feb 2 16:42:01 2009 New Revision: 63558 URL: http://llvm.org/viewvc/llvm-project?rev=63558&view=rev Log: MergeValueInto is too smart: it might choose to do the merge the opposite direction. Live interval reconstruction needs to account for this, and scour its maps to prevent dangling references. Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h llvm/trunk/lib/CodeGen/LiveInterval.cpp llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=63558&r1=63557&r2=63558&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Mon Feb 2 16:42:01 2009 @@ -276,7 +276,7 @@ /// are found to be equivalent. This eliminates V1, replacing all /// LiveRanges with the V1 value number with the V2 value number. This can /// cause merging of V1/V2 values numbers and compaction of the value space. - void MergeValueNumberInto(VNInfo *V1, VNInfo *V2); + VNInfo* MergeValueNumberInto(VNInfo *V1, VNInfo *V2); /// MergeInClobberRanges - For any live ranges that are not defined in the /// current interval, but are defined in the Clobbers interval, mark them Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=63558&r1=63557&r2=63558&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Mon Feb 2 16:42:01 2009 @@ -591,7 +591,7 @@ /// are found to be equivalent. This eliminates V1, replacing all /// LiveRanges with the V1 value number with the V2 value number. This can /// cause merging of V1/V2 values numbers and compaction of the value space. -void LiveInterval::MergeValueNumberInto(VNInfo *V1, VNInfo *V2) { +VNInfo* LiveInterval::MergeValueNumberInto(VNInfo *V1, VNInfo *V2) { assert(V1 != V2 && "Identical value#'s are always equivalent!"); // This code actually merges the (numerically) larger value number into the @@ -652,6 +652,8 @@ } else { V1->def = ~1U; } + + return V2; } void LiveInterval::Copy(const LiveInterval &RHS, Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=63558&r1=63557&r2=63558&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original) +++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Mon Feb 2 16:42:01 2009 @@ -654,8 +654,24 @@ } if (MBB->pred_size() == 1 && !RetVNI->hasPHIKill) { - LI->MergeValueNumberInto(RetVNI, IncomingVNs.begin()->second); - Phis[MBB] = RetVNI = IncomingVNs.begin()->second; + VNInfo* OldVN = RetVNI; + VNInfo* NewVN = IncomingVNs.begin()->second; + VNInfo* MergedVN = LI->MergeValueNumberInto(OldVN, NewVN); + if (MergedVN == OldVN) std::swap(OldVN, NewVN); + + for (DenseMap::iterator LOI = LiveOut.begin(), + LOE = LiveOut.end(); LOI != LOE; ++LOI) + if (LOI->second == OldVN) + LOI->second = MergedVN; + for (DenseMap::iterator NVI = NewVNs.begin(), + NVE = NewVNs.end(); NVI != NVE; ++NVI) + if (NVI->second == OldVN) + NVI->second = MergedVN; + for (DenseMap::iterator PI = Phis.begin(), + PE = Phis.end(); PI != PE; ++PI) + if (PI->second == OldVN) + PI->second = MergedVN; + RetVNI = MergedVN; } else { // Otherwise, merge the incoming VNInfos with a phi join. Create a new // VNInfo to represent the joined value. From mrs at apple.com Mon Feb 2 16:48:49 2009 From: mrs at apple.com (Mike Stump) Date: Mon, 02 Feb 2009 22:48:49 -0000 Subject: [llvm-commits] [llvm] r63559 - in /llvm/trunk: docs/CommandLine.html include/llvm/Support/CommandLine.h lib/Support/CommandLine.cpp Message-ID: <200902022248.n12Mmn72023628@zion.cs.uiuc.edu> Author: mrs Date: Mon Feb 2 16:48:49 2009 New Revision: 63559 URL: http://llvm.org/viewvc/llvm-project?rev=63559&view=rev Log: Improve -fno-opt style option processing to not require an extra option to make the -fno- form on the option. We also document the new form in the CommandLine documentation. Modified: llvm/trunk/docs/CommandLine.html llvm/trunk/include/llvm/Support/CommandLine.h llvm/trunk/lib/Support/CommandLine.cpp Modified: llvm/trunk/docs/CommandLine.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CommandLine.html?rev=63559&r1=63558&r2=63559&view=diff ============================================================================== --- llvm/trunk/docs/CommandLine.html (original) +++ llvm/trunk/docs/CommandLine.html Mon Feb 2 16:48:49 2009 @@ -1447,6 +1447,16 @@ error. As with cl::CommaSeparated, this modifier only makes sense with a cl::list option.
    • +
  • The cl::AllowInverse +modifier can be used on options that have the form -fopt to +automatically create a corresponding +-fno-opt option. The f can be any single +character, and the opt can be any one or more characters. +The value of the created option is the logical complement of the value +that would have been used if the base form of the option was used. +This modifier only makes sense with an option that uses +a bool parser.
    • + @@ -1745,7 +1755,11 @@
  • The parser<bool> specialization is used to convert boolean strings to a boolean value. Currently accepted strings are "true", "TRUE", "True", "1", -"false", "FALSE", "False", and "0".
    • +"false", "FALSE", "False", and "0". The +cl::AllowInverse modifier can be used on an option of the form +-fopt that uses the parser<bool> specialization +to create a corresponding option with the form -fno-opt. See +cl::AllowInverse for details.
  • The parser<boolOrDefault> specialization is used for cases where the value is boolean, Modified: llvm/trunk/include/llvm/Support/CommandLine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CommandLine.h?rev=63559&r1=63558&r2=63559&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/CommandLine.h (original) +++ llvm/trunk/include/llvm/Support/CommandLine.h Mon Feb 2 16:48:49 2009 @@ -126,7 +126,8 @@ CommaSeparated = 0x200, // Should this cl::list split between commas? PositionalEatsArgs = 0x400, // Should this positional cl::list eat -args? Sink = 0x800, // Should this cl::list eat all unknown options? - MiscMask = 0xE00 // Union of the above flags. + AllowInverse = 0x1000, // Can this option take a -Xno- form? + MiscMask = 0x1E00 // Union of the above flags. }; @@ -302,12 +303,6 @@ template LocationClass location(Ty &L) { return LocationClass(L); } -// opposite_of - Allow the user to specify which other option this -// option is the opposite of. -// -template -LocationClass opposite_of(Ty &O) { return location(O.getValue()); } - //===----------------------------------------------------------------------===// // Enum valued command line option @@ -542,10 +537,33 @@ // template<> class parser : public basic_parser { + bool IsInvertable; // Should we synthezise a -xno- style option? + const char *ArgStr; public: + void getExtraOptionNames(std::vector &OptionNames) { + if (IsInvertable) { + char *s = new char [strlen(ArgStr) + 3 + 1]; + s[0] = ArgStr[0]; + s[1] = 'n'; + s[2] = 'o'; + s[3] = '-'; + strcpy(&s[4], ArgStr+1); + OptionNames.push_back(s); + } + } + // parse - Return true on error. bool parse(Option &O, const char *ArgName, const std::string &Arg, bool &Val); + template + void initialize(Opt &O) { + if (O.getMiscFlags() & llvm::cl::AllowInverse) + IsInvertable = true; + else + IsInvertable = false; + ArgStr = O.ArgStr; + } + enum ValueExpected getValueExpectedFlagDefault() const { return ValueOptional; } @@ -583,30 +601,6 @@ EXTERN_TEMPLATE_INSTANTIATION(class basic_parser); //-------------------------------------------------- -// parser -class boolInverse { }; -template<> -class parser : public basic_parser { -public: - typedef bool parser_data_type; - // parse - Return true on error. - bool parse(Option &O, const char *ArgName, const std::string &Arg, - bool &Val); - - enum ValueExpected getValueExpectedFlagDefault() const { - return ValueOptional; - } - - // getValueName - Do not print = at all. - virtual const char *getValueName() const { return 0; } - - // An out-of-line virtual method to provide a 'home' for this class. - virtual void anchor(); -}; - -EXTERN_TEMPLATE_INSTANTIATION(class basic_parser); - -//-------------------------------------------------- // parser // template<> @@ -947,9 +941,6 @@ EXTERN_TEMPLATE_INSTANTIATION(class opt); EXTERN_TEMPLATE_INSTANTIATION(class opt); -class boolInverse; -typedef opt > inverse_opt; - //===----------------------------------------------------------------------===// // list_storage class Modified: llvm/trunk/lib/Support/CommandLine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CommandLine.cpp?rev=63559&r1=63558&r2=63559&view=diff ============================================================================== --- llvm/trunk/lib/Support/CommandLine.cpp (original) +++ llvm/trunk/lib/Support/CommandLine.cpp Mon Feb 2 16:48:49 2009 @@ -40,7 +40,6 @@ // TEMPLATE_INSTANTIATION(class basic_parser); TEMPLATE_INSTANTIATION(class basic_parser); -TEMPLATE_INSTANTIATION(class basic_parser); TEMPLATE_INSTANTIATION(class basic_parser); TEMPLATE_INSTANTIATION(class basic_parser); TEMPLATE_INSTANTIATION(class basic_parser); @@ -56,7 +55,6 @@ void basic_parser_impl::anchor() {} void parser::anchor() {} void parser::anchor() {} -void parser::anchor() {} void parser::anchor() {} void parser::anchor() {} void parser::anchor() {} @@ -874,6 +872,8 @@ return O.error(": '" + Arg + "' is invalid value for boolean argument! Try 0 or 1"); } + if (IsInvertable && strncmp(ArgName+1, "no-", 3) == 0) + Value = !Value; return false; } @@ -894,23 +894,6 @@ return false; } -// parser implementation -// -bool parser::parse(Option &O, const char *ArgName, - const std::string &Arg, bool &Value) { - if (Arg == "" || Arg == "true" || Arg == "TRUE" || Arg == "True" || - Arg == "1") { - Value = false; - } else if (Arg == "false" || Arg == "FALSE" - || Arg == "False" || Arg == "0") { - Value = true; - } else { - return O.error(": '" + Arg + - "' is invalid value for boolean argument! Try 0 or 1"); - } - return false; -} - // parser implementation // bool parser::parse(Option &O, const char *ArgName, From dalej at apple.com Mon Feb 2 16:49:46 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 02 Feb 2009 22:49:46 -0000 Subject: [llvm-commits] [llvm] r63560 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200902022249.n12Mnl03023665@zion.cs.uiuc.edu> Author: johannes Date: Mon Feb 2 16:49:46 2009 New Revision: 63560 URL: http://llvm.org/viewvc/llvm-project?rev=63560&view=rev Log: More DebugLoc propagation. This should be everything except LegalizeOp itself. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63560&r1=63559&r2=63560&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Feb 2 16:49:46 2009 @@ -231,7 +231,7 @@ SDValue BasePtr, const Value *SV, int SVOffset, unsigned Alignment, bool isVolatile, unsigned LdWidth, - MVT ResType); + MVT ResType, DebugLoc dl); /// StoreWidenVectorOp - Stores a widen vector into non widen memory /// location. It takes @@ -257,7 +257,7 @@ SDValue BasePtr, const Value *SV, int SVOffset, unsigned Alignment, bool isVolatile, SDValue ValOp, - unsigned StWidth); + unsigned StWidth, DebugLoc dl); /// isShuffleLegal - Return non-null if a vector shuffle is legal with the /// specified mask and type. Targets can specify exactly which masks they @@ -7481,8 +7481,8 @@ #endif assert(0 && "Unhandled operation in SplitVectorOp!"); case ISD::UNDEF: - Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); - Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); + Lo = DAG.getNode(ISD::UNDEF, dl, NewVT_Lo); + Hi = DAG.getNode(ISD::UNDEF, dl, NewVT_Hi); break; case ISD::BUILD_PAIR: Lo = Node->getOperand(0); @@ -7494,10 +7494,10 @@ unsigned Index = Idx->getZExtValue(); SDValue ScalarOp = Node->getOperand(1); if (Index < NewNumElts_Lo) - Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, + Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Lo, Lo, ScalarOp, DAG.getIntPtrConstant(Index)); else - Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, + Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Hi, Hi, ScalarOp, DAG.getIntPtrConstant(Index - NewNumElts_Lo)); break; } @@ -7519,7 +7519,7 @@ for (unsigned i = 0; i != NewNumElts_Lo; ++i) { SDValue IdxNode = Mask.getOperand(i); if (IdxNode.getOpcode() == ISD::UNDEF) { - Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); + Ops.push_back(DAG.getNode(ISD::UNDEF, dl, NewEltVT)); continue; } unsigned Idx = cast(IdxNode)->getZExtValue(); @@ -7528,16 +7528,16 @@ InVec = Node->getOperand(1); Idx -= NumElements; } - Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, + Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec, DAG.getConstant(Idx, PtrVT))); } - Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); + Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &Ops[0], Ops.size()); Ops.clear(); for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { SDValue IdxNode = Mask.getOperand(i); if (IdxNode.getOpcode() == ISD::UNDEF) { - Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); + Ops.push_back(DAG.getNode(ISD::UNDEF, dl, NewEltVT)); continue; } unsigned Idx = cast(IdxNode)->getZExtValue(); @@ -7546,20 +7546,20 @@ InVec = Node->getOperand(1); Idx -= NumElements; } - Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, + Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec, DAG.getConstant(Idx, PtrVT))); } - Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size()); + Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &Ops[0], Ops.size()); break; } case ISD::BUILD_VECTOR: { SmallVector LoOps(Node->op_begin(), Node->op_begin()+NewNumElts_Lo); - Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); + Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &LoOps[0], LoOps.size()); SmallVector HiOps(Node->op_begin()+NewNumElts_Lo, Node->op_end()); - Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); + Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &HiOps[0], HiOps.size()); break; } case ISD::CONCAT_VECTORS: { @@ -7571,11 +7571,13 @@ } else { SmallVector LoOps(Node->op_begin(), Node->op_begin()+NewNumSubvectors); - Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); + Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Lo, + &LoOps[0], LoOps.size()); SmallVector HiOps(Node->op_begin()+NewNumSubvectors, Node->op_end()); - Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); + Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Hi, + &HiOps[0], HiOps.size()); } break; } @@ -7584,16 +7586,16 @@ SDValue Idx = Op.getOperand(1); MVT IdxVT = Idx.getValueType(); - Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Lo, Vec, Idx); + Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Lo, Vec, Idx); ConstantSDNode *CIdx = dyn_cast(Idx); if (CIdx) { - Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec, + Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec, DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo, IdxVT)); } else { - Idx = DAG.getNode(ISD::ADD, IdxVT, Idx, + Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx, DAG.getConstant(NewNumElts_Lo, IdxVT)); - Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec, Idx); + Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec, Idx); } break; } @@ -7608,12 +7610,12 @@ // Handle a vector merge. SDValue CL, CH; SplitVectorOp(Cond, CL, CH); - Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); - Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); + Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, CL, LL, RL); + Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, CH, LH, RH); } else { // Handle a simple select with vector operands. - Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); - Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); + Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, Cond, LL, RL); + Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, Cond, LH, RH); } break; } @@ -7627,9 +7629,9 @@ SplitVectorOp(Node->getOperand(3), RL, RH); // Handle a simple select with vector operands. - Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS, + Lo = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Lo, CondLHS, CondRHS, LL, RL, CondCode); - Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS, + Hi = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Hi, CondLHS, CondRHS, LH, RH, CondCode); break; } @@ -7637,8 +7639,8 @@ SDValue LL, LH, RL, RH; SplitVectorOp(Node->getOperand(0), LL, LH); SplitVectorOp(Node->getOperand(1), RL, RH); - Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2)); - Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2)); + Lo = DAG.getNode(ISD::VSETCC, dl, NewVT_Lo, LL, RL, Node->getOperand(2)); + Hi = DAG.getNode(ISD::VSETCC, dl, NewVT_Hi, LH, RH, Node->getOperand(2)); break; } case ISD::ADD: @@ -7664,8 +7666,8 @@ SplitVectorOp(Node->getOperand(0), LL, LH); SplitVectorOp(Node->getOperand(1), RL, RH); - Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); - Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); + Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, LL, RL); + Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, LH, RH); break; } case ISD::FP_ROUND: @@ -7673,8 +7675,8 @@ SDValue L, H; SplitVectorOp(Node->getOperand(0), L, H); - Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); - Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); + Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L, Node->getOperand(1)); + Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H, Node->getOperand(1)); break; } case ISD::CTTZ: @@ -7702,8 +7704,8 @@ SDValue L, H; SplitVectorOp(Node->getOperand(0), L, H); - Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); - Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); + Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L); + Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H); break; } case ISD::CONVERT_RNDSAT: { @@ -7736,27 +7738,27 @@ bool isVolatile = LD->isVolatile(); assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); - SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType()); + SDValue Offset = DAG.getNode(ISD::UNDEF, dl, Ptr.getValueType()); MVT MemNewEltVT = MemoryVT.getVectorElementType(); MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo); MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi); - Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, + Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, NewVT_Lo, Ch, Ptr, Offset, SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment); unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8; - Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, + Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); SVOffset += IncrementSize; Alignment = MinAlign(Alignment, IncrementSize); - Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, + Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, NewVT_Hi, Ch, Ptr, Offset, SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment); // Build a factor node to remember that this load is independent of the // other one. - SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), + SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), Hi.getValue(1)); // Remember that we legalized the chain. @@ -7777,16 +7779,16 @@ SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign); int FI = cast(Ptr.getNode())->getIndex(); - SDValue St = DAG.getStore(DAG.getEntryNode(), + SDValue St = DAG.getStore(DAG.getEntryNode(), dl, InOp, Ptr, PseudoSourceValue::getFixedStack(FI), 0); - InOp = DAG.getLoad(Op.getValueType(), St, Ptr, + InOp = DAG.getLoad(Op.getValueType(), dl, St, Ptr, PseudoSourceValue::getFixedStack(FI), 0); } // Split the vector and convert each of the pieces now. SplitVectorOp(InOp, Lo, Hi); - Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); - Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); + Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Lo, Lo); + Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Hi, Hi); break; } } @@ -7805,6 +7807,7 @@ SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) { assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!"); SDNode *Node = Op.getNode(); + DebugLoc dl = Node->getDebugLoc(); MVT NewVT = Op.getValueType().getVectorElementType(); assert(Op.getValueType().getVectorNumElements() == 1); @@ -7835,7 +7838,7 @@ case ISD::AND: case ISD::OR: case ISD::XOR: - Result = DAG.getNode(Node->getOpcode(), + Result = DAG.getNode(Node->getOpcode(), dl, NewVT, ScalarizeVectorOp(Node->getOperand(0)), ScalarizeVectorOp(Node->getOperand(1))); @@ -7859,7 +7862,7 @@ case ISD::ANY_EXTEND: case ISD::TRUNCATE: case ISD::FP_EXTEND: - Result = DAG.getNode(Node->getOpcode(), + Result = DAG.getNode(Node->getOpcode(), dl, NewVT, ScalarizeVectorOp(Node->getOperand(0))); break; @@ -7875,7 +7878,7 @@ } case ISD::FPOWI: case ISD::FP_ROUND: - Result = DAG.getNode(Node->getOpcode(), + Result = DAG.getNode(Node->getOpcode(), dl, NewVT, ScalarizeVectorOp(Node->getOperand(0)), Node->getOperand(1)); @@ -7892,9 +7895,9 @@ bool isVolatile = LD->isVolatile(); assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); - SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType()); + SDValue Offset = DAG.getNode(ISD::UNDEF, dl, Ptr.getValueType()); - Result = DAG.getLoad(ISD::UNINDEXED, ExtType, + Result = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, NewVT, Ch, Ptr, Offset, SV, SVOffset, MemoryVT.getVectorElementType(), isVolatile, Alignment); @@ -7925,23 +7928,23 @@ break; } case ISD::EXTRACT_SUBVECTOR: - Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, Node->getOperand(0), - Node->getOperand(1)); + Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, + Node->getOperand(0), Node->getOperand(1)); break; case ISD::BIT_CONVERT: { SDValue Op0 = Op.getOperand(0); if (Op0.getValueType().getVectorNumElements() == 1) Op0 = ScalarizeVectorOp(Op0); - Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0); + Result = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, Op0); break; } case ISD::SELECT: - Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), + Result = DAG.getNode(ISD::SELECT, dl, NewVT, Op.getOperand(0), ScalarizeVectorOp(Op.getOperand(1)), ScalarizeVectorOp(Op.getOperand(2))); break; case ISD::SELECT_CC: - Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0), + Result = DAG.getNode(ISD::SELECT_CC, dl, NewVT, Node->getOperand(0), Node->getOperand(1), ScalarizeVectorOp(Op.getOperand(2)), ScalarizeVectorOp(Op.getOperand(3)), @@ -7950,9 +7953,10 @@ case ISD::VSETCC: { SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0)); SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1)); - Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0.getValueType()), + Result = DAG.getNode(ISD::SETCC, dl, + TLI.getSetCCResultType(Op0.getValueType()), Op0, Op1, Op.getOperand(2)); - Result = DAG.getNode(ISD::SELECT, NewVT, Result, + Result = DAG.getNode(ISD::SELECT, dl, NewVT, Result, DAG.getConstant(-1ULL, NewVT), DAG.getConstant(0ULL, NewVT)); break; @@ -7977,6 +7981,7 @@ SDValue Result; SDNode *Node = Op.getNode(); + DebugLoc dl = Node->getDebugLoc(); MVT EVT = VT.getVectorElementType(); unsigned NumElts = VT.getVectorNumElements(); @@ -8012,20 +8017,21 @@ assert(0 && "Unexpected operation in WidenVectorOp!"); break; case ISD::UNDEF: - Result = DAG.getNode(ISD::UNDEF, WidenVT); + Result = DAG.getNode(ISD::UNDEF, dl, WidenVT); break; case ISD::BUILD_VECTOR: { // Build a vector with undefined for the new nodes SDValueVector NewOps(Node->op_begin(), Node->op_end()); for (unsigned i = NumElts; i < NewNumElts; ++i) { - NewOps.push_back(DAG.getNode(ISD::UNDEF,EVT)); + NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, EVT)); } - Result = DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &NewOps[0], NewOps.size()); + Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, + &NewOps[0], NewOps.size()); break; } case ISD::INSERT_VECTOR_ELT: { SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); - Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, WidenVT, Tmp1, + Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WidenVT, Tmp1, Node->getOperand(1), Node->getOperand(2)); break; } @@ -8054,14 +8060,14 @@ } } for (unsigned i = NumElts; i < NewNumElts; ++i) { - NewOps.push_back(DAG.getNode(ISD::UNDEF,PVT)); + NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, PVT)); } - SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR, + SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::getVectorVT(PVT, NewOps.size()), &NewOps[0], NewOps.size()); - Result = DAG.getNode(ISD::VECTOR_SHUFFLE, WidenVT, Tmp1, Tmp2, Tmp3); + Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT, Tmp1, Tmp2, Tmp3); break; } case ISD::LOAD: { @@ -8090,7 +8096,7 @@ MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize); Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT); assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits()); - Result = DAG.getNode(ISD::BIT_CONVERT, WidenVT, Tmp1); + Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Tmp1); } else { // If the result size is a multiple of the input size, widen the input // and then convert. @@ -8099,14 +8105,14 @@ "can not widen bit convert that are not multiple of element type"); unsigned NewNumElts = WidenSize / InSize; SmallVector Ops(NewNumElts); - SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT); + SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT); Ops[0] = Tmp1; for (unsigned i = 1; i < NewNumElts; ++i) Ops[i] = UndefVal; MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts); - Result = DAG.getNode(ISD::BUILD_VECTOR, NewInVT, &Ops[0], NewNumElts); - Result = DAG.getNode(ISD::BIT_CONVERT, WidenVT, Result); + Result = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, &Ops[0], NewNumElts); + Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Result); } break; } @@ -8125,7 +8131,7 @@ MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts); Tmp1 = WidenVectorOp(Tmp1, TWidenVT); assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts); - Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1); + Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1); break; } @@ -8148,7 +8154,7 @@ SDValue Tmp1; Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); assert(Tmp1.getValueType() == WidenVT); - Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1); + Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1); break; } case ISD::CONVERT_RNDSAT: { @@ -8198,7 +8204,7 @@ SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT); assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT); - Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2); + Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2); break; } @@ -8213,14 +8219,14 @@ WidenVT.getVectorNumElements()); ShOp = WidenVectorOp(ShOp, NewShVT); assert(ShOp.getValueType() == NewShVT); - Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, ShOp); + Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, ShOp); break; } case ISD::EXTRACT_VECTOR_ELT: { SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); assert(Tmp1.getValueType() == WidenVT); - Result = DAG.getNode(Node->getOpcode(), EVT, Tmp1, Node->getOperand(1)); + Result = DAG.getNode(Node->getOpcode(), dl, EVT, Tmp1, Node->getOperand(1)); break; } case ISD::CONCAT_VECTORS: { @@ -8228,13 +8234,13 @@ // We could widen on a multiple of the incoming operand if necessary. unsigned NumConcat = NewNumElts / NumElts; assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector"); - SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT); + SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, VT); SmallVector MOps; MOps.push_back(Op); for (unsigned i = 1; i != NumConcat; ++i) { MOps.push_back(UndefVal); } - Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT, + Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &MOps[0], MOps.size())); break; } @@ -8253,18 +8259,18 @@ if (Tmp1VTNumElts < NewNumElts) Result = WidenVectorOp(Tmp1, WidenVT); else - Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, WidenVT, Tmp1, Idx); + Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, Tmp1, Idx); } } else if (NewNumElts % NumElts == 0) { // Widen the extracted subvector. unsigned NumConcat = NewNumElts / NumElts; - SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT); + SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, VT); SmallVector MOps; MOps.push_back(Op); for (unsigned i = 1; i != NumConcat; ++i) { MOps.push_back(UndefVal); } - Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT, + Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &MOps[0], MOps.size())); } else { assert(0 && "can not widen extract subvector"); @@ -8287,7 +8293,7 @@ SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT); SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT); assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT); - Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Tmp1, Tmp2); + Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Tmp1, Tmp2); break; } @@ -8309,7 +8315,7 @@ SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT); assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT && "operands not widen"); - Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Cond2, Tmp1, + Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Cond2, Tmp1, Tmp2, Node->getOperand(4)); break; } @@ -8322,7 +8328,7 @@ MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts); Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT); SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT); - Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2, + Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2, Node->getOperand(2)); break; } @@ -8389,7 +8395,8 @@ unsigned Alignment, bool isVolatile, unsigned LdWidth, - MVT ResType) { + MVT ResType, + DebugLoc dl) { // We assume that we have good rules to handle loading power of two loads so // we break down the operations to power of 2 loads. The strategy is to // load the largest power of 2 that we can easily transform to a legal vector @@ -8403,14 +8410,14 @@ FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT); EVTWidth = EVT.getSizeInBits(); - SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, SVOffset, + SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, SVOffset, isVolatile, Alignment); - SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecEVT, LdOp); + SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecEVT, LdOp); LdChain.push_back(LdOp.getValue(1)); // Check if we can load the element with one instruction if (LdWidth == EVTWidth) { - return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp); + return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp); } // The vector element order is endianness dependent. @@ -8421,7 +8428,7 @@ while (LdWidth > 0) { unsigned Increment = EVTWidth / 8; Offset += Increment; - BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr, + BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, DAG.getIntPtrConstant(Increment)); if (LdWidth < EVTWidth) { @@ -8432,20 +8439,20 @@ EVTWidth = EVT.getSizeInBits(); // Readjust position and vector position based on new load type Idx = Idx * (oEVTWidth/EVTWidth); - VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp); + VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp); } - SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, + SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, SVOffset+Offset, isVolatile, MinAlign(Alignment, Offset)); LdChain.push_back(LdOp.getValue(1)); - VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, VecEVT, VecOp, LdOp, + VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecEVT, VecOp, LdOp, DAG.getIntPtrConstant(Idx++)); LdWidth -= EVTWidth; } - return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp); + return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp); } bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result, @@ -8461,6 +8468,7 @@ // we need to load from. LoadSDNode *LD = cast(Op.getNode()); MVT LdVT = LD->getMemoryVT(); + DebugLoc dl = LD->getDebugLoc(); assert(LdVT.isVector() && NVT.isVector()); assert(LdVT.getVectorElementType() == NVT.getVectorElementType()); @@ -8476,14 +8484,15 @@ // Load value as a large register SDValueVector LdChain; Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset, - Alignment, isVolatile, LdWidth, NVT); + Alignment, isVolatile, LdWidth, NVT, dl); if (LdChain.size() == 1) { TFOp = LdChain[0]; return true; } else { - TFOp=DAG.getNode(ISD::TokenFactor, MVT::Other, &LdChain[0], LdChain.size()); + TFOp=DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + &LdChain[0], LdChain.size()); return false; } } @@ -8497,7 +8506,8 @@ unsigned Alignment, bool isVolatile, SDValue ValOp, - unsigned StWidth) { + unsigned StWidth, + DebugLoc dl) { // Breaks the stores into a series of power of 2 width stores. For any // width, we convert the vector to the vector of element size that we // want to store. This avoids requiring a stack convert. @@ -8509,10 +8519,10 @@ FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT); EVTWidth = EVT.getSizeInBits(); - SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, ValOp); - SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp, + SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, ValOp); + SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp, DAG.getIntPtrConstant(0)); - SDValue StOp = DAG.getStore(Chain, EOp, BasePtr, SV, SVOffset, + SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset, isVolatile, Alignment); StChain.push_back(StOp); @@ -8528,7 +8538,7 @@ while (StWidth > 0) { unsigned Increment = EVTWidth / 8; Offset += Increment; - BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr, + BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, DAG.getIntPtrConstant(Increment)); if (StWidth < EVTWidth) { @@ -8539,12 +8549,12 @@ EVTWidth = EVT.getSizeInBits(); // Readjust position and vector position based on new load type Idx = Idx * (oEVTWidth/EVTWidth); - VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp); + VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp); } - EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp, + EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp, DAG.getIntPtrConstant(Idx++)); - StChain.push_back(DAG.getStore(Chain, EOp, BasePtr, SV, + StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset + Offset, isVolatile, MinAlign(Alignment, Offset))); StWidth -= EVTWidth; @@ -8563,6 +8573,7 @@ MVT StVT = ST->getMemoryVT(); SDValue ValOp = ST->getValue(); + DebugLoc dl = ST->getDebugLoc(); // Check if we have widen this node with another value std::map::iterator I = WidenNodes.find(ValOp); @@ -8581,11 +8592,12 @@ SDValueVector StChain; genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(), ST->getSrcValueOffset(), ST->getAlignment(), - ST->isVolatile(), ValOp, StVT.getSizeInBits()); + ST->isVolatile(), ValOp, StVT.getSizeInBits(), dl); if (StChain.size() == 1) return StChain[0]; else - return DAG.getNode(ISD::TokenFactor, MVT::Other,&StChain[0],StChain.size()); + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + &StChain[0], StChain.size()); } From gohman at apple.com Mon Feb 2 16:50:08 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 02 Feb 2009 22:50:08 -0000 Subject: [llvm-commits] [llvm] r63561 - /llvm/trunk/test/CodeGen/X86/extractelement-load.ll Message-ID: <200902022250.n12Mo8U3023687@zion.cs.uiuc.edu> Author: djg Date: Mon Feb 2 16:50:08 2009 New Revision: 63561 URL: http://llvm.org/viewvc/llvm-project?rev=63561&view=rev Log: Yonah does not support x86-64. Change the -mcpu value to one that does. Modified: llvm/trunk/test/CodeGen/X86/extractelement-load.ll Modified: llvm/trunk/test/CodeGen/X86/extractelement-load.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extractelement-load.ll?rev=63561&r1=63560&r2=63561&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/extractelement-load.ll (original) +++ llvm/trunk/test/CodeGen/X86/extractelement-load.ll Mon Feb 2 16:50:08 2009 @@ -1,5 +1,5 @@ ; RUN: llvm-as %s -o - | llc -march=x86 -mattr=+sse2 -mcpu=yonah | not grep movd -; RUN: llvm-as %s -o - | llc -march=x86-64 -mattr=+sse2 -mcpu=yonah | not grep movd +; RUN: llvm-as %s -o - | llc -march=x86-64 -mattr=+sse2 -mcpu=core2 | not grep movd define i32 @t(<2 x i64>* %val) nounwind { %tmp2 = load <2 x i64>* %val, align 16 ; <<2 x i64>> [#uses=1] From gohman at apple.com Mon Feb 2 16:54:45 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 2 Feb 2009 14:54:45 -0800 Subject: [llvm-commits] [llvm] r63495 - in /llvm/trunk: lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86Subtarget.cpp test/CodeGen/X86/2009-01-25-NoSSE.ll test/CodeGen/X86/nosse-varargs.ll In-Reply-To: <49876C5E.9030408@gmail.com> References: <200902011815.n11IFvlY018701@zion.cs.uiuc.edu> <6A755BA8-4308-4238-A143-4332545A8F91@apple.com> <49875DB4.4050600@gmail.com> <8BAA0D72-F5D7-49B2-81A5-5DAC116887E0@apple.com> <49876C5E.9030408@gmail.com> Message-ID: <48AEE04E-B252-42D3-A1A0-462BC7A13CA4@apple.com> On Feb 2, 2009, at 1:57 PM, T?r?k Edwin wrote: > On 2009-02-02 23:43, Dan Gohman wrote: >> On Feb 2, 2009, at 12:55 PM, T?r?k Edwin wrote: >> >>> + if (Is64Bit) { >>> + // Make sure SSE2 is enabled, it is available on all X86-64 >>> CPUs. >>> + X86SSELevel = SSE2; >>> + } >>> >> >> It looks like this should also check if (X86SSELevel < SSE2) so that >> it doesn't override when AutoDetectSubtargetFeatures detects an SSE >> level greater than SSE2. With that fixed, this looks good. >> > > Fixed. Thanks! > > >> >>> } >>> >>> - // If requesting codegen for X86-64, make sure that 64-bit and >>> SSE2 >>> features >>> - // are enabled. These are available on all x86-64 CPUs. >>> + // If requesting codegen for X86-64, make sure that 64-bit >>> features >>> + // are enabled. >>> if (Is64Bit) { >>> HasX86_64 = true; >>> } >>> >> >> >> Do you think it would make sense to move this up into the else clause >> above too? I'm wondering if an assert(!Is64Bit || HasX86_64) after >> the >> else would be a sane sanity check. >> > > I tried that, but the assertion failed with llc -mcpu=yonah in one of > the codegen tests, so I didn't move the if for now (added the assert > though). > I've committed r63552. Thanks. Was the failure you saw test/CodeGen/X86/extractelement-load.ll? That's actually a bug in the test, and I just fixed it. I'll finish up moving the above code. Dan From gohman at apple.com Mon Feb 2 17:43:59 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 02 Feb 2009 23:43:59 -0000 Subject: [llvm-commits] [llvm] r63572 - /llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll Message-ID: <200902022343.n12NhxSC025559@zion.cs.uiuc.edu> Author: djg Date: Mon Feb 2 17:43:59 2009 New Revision: 63572 URL: http://llvm.org/viewvc/llvm-project?rev=63572&view=rev Log: Fix another test to not use -mcpu=yonah with 64-bit code. Modified: llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll Modified: llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll?rev=63572&r1=63571&r2=63572&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll Mon Feb 2 17:43:59 2009 @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -mcpu=yonah | grep pxor | count 2 -; RUN: llvm-as < %s | llc -mcpu=yonah | not grep movapd +; RUN: llvm-as < %s | llc -mcpu=core2 | grep pxor | count 2 +; RUN: llvm-as < %s | llc -mcpu=core2 | not grep movapd ; PR2715 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" From dalej at apple.com Mon Feb 2 17:46:54 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 02 Feb 2009 23:46:54 -0000 Subject: [llvm-commits] [llvm] r63574 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200902022346.n12NksYR025663@zion.cs.uiuc.edu> Author: johannes Date: Mon Feb 2 17:46:53 2009 New Revision: 63574 URL: http://llvm.org/viewvc/llvm-project?rev=63574&view=rev Log: Last DebugLoc propagation for this file. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63574&r1=63573&r2=63574&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Feb 2 17:46:53 2009 @@ -1117,7 +1117,7 @@ // Fall Thru case TargetLowering::Legal: { SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 }; - Result = DAG.getMergeValues(Ops, 2); + Result = DAG.getMergeValues(Ops, 2, dl); break; } } @@ -1151,7 +1151,7 @@ // Fall Thru case TargetLowering::Legal: { SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 }; - Result = DAG.getMergeValues(Ops, 2); + Result = DAG.getMergeValues(Ops, 2, dl); break; } } @@ -1283,14 +1283,16 @@ unsigned Line = DSP->getLine(); unsigned Col = DSP->getColumn(); + // A bit self-referential to have DebugLoc on Debug_Loc nodes, but + // it won't hurt anything. if (useDEBUG_LOC) { SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32), DAG.getConstant(Col, MVT::i32), DAG.getConstant(SrcFile, MVT::i32) }; - Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4); + Result = DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Ops, 4); } else { unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile); - Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID); + Result = DAG.getLabel(ISD::DBG_LABEL, dl, Tmp1, ID); } } else { Result = Tmp1; // chain @@ -1642,7 +1644,7 @@ // match the element type of the vector being created. if (Tmp2.getValueType() == Op.getValueType().getVectorElementType()) { - SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, + SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, Tmp1.getValueType(), Tmp2); unsigned NumElts = Tmp1.getValueType().getVectorNumElements(); @@ -1660,10 +1662,10 @@ else ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); } - SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, + SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, ShufMaskVT, &ShufOps[0], ShufOps.size()); - Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), + Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Tmp1.getValueType(), Tmp1, ScVec, ShufMask); Result = LegalizeOp(Result); break; @@ -1728,19 +1730,19 @@ for (unsigned i = 0; i != NumElems; ++i) { SDValue Arg = Mask.getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) { - Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); + Ops.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT)); } else { assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); unsigned Idx = cast(Arg)->getZExtValue(); if (Idx < NumElems) - Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, + Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp1, DAG.getConstant(Idx, PtrVT))); else - Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, + Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp2, DAG.getConstant(Idx - NumElems, PtrVT))); } } - Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); + Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); break; } case TargetLowering::Promote: { @@ -1749,14 +1751,14 @@ MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); // Cast the two input vectors. - Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); - Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); + Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1); + Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2); // Convert the shuffle mask to the right # elements. Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0); assert(Tmp3.getNode() && "Shuffle not legal?"); - Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); - Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); + Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NVT, Tmp1, Tmp2, Tmp3); + Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result); break; } } @@ -1788,11 +1790,11 @@ MVT EltVT = VVT.getVectorElementType(); unsigned NumSubElem = VVT.getVectorNumElements(); for (unsigned j=0; j < NumSubElem; ++j) { - Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, SubOp, + Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp, DAG.getConstant(j, PtrVT))); } } - return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), + return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), &Ops[0], Ops.size())); } @@ -1815,7 +1817,8 @@ // Merge in the last call, to ensure that this call start after the last // call ended. if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { - Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); + Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Tmp1, LastCALLSEQ_END); Tmp1 = LegalizeOp(Tmp1); } @@ -1914,12 +1917,12 @@ unsigned StackAlign = TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); if (Align > StackAlign) - SP = DAG.getNode(ISD::AND, VT, SP, + SP = DAG.getNode(ISD::AND, dl, VT, SP, DAG.getConstant(-(uint64_t)Align, VT)); - Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value + Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain - Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), + Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), DAG.getIntPtrConstant(0, true), SDValue()); Tmp1 = LegalizeOp(Tmp1); @@ -1981,7 +1984,7 @@ case ISD::BR: Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. // Ensure that libcalls are emitted before a branch. - Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); + Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); Tmp1 = LegalizeOp(Tmp1); LastCALLSEQ_END = DAG.getEntryNode(); @@ -1990,7 +1993,7 @@ case ISD::BRIND: Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. // Ensure that libcalls are emitted before a branch. - Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); + Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); Tmp1 = LegalizeOp(Tmp1); LastCALLSEQ_END = DAG.getEntryNode(); @@ -2005,7 +2008,7 @@ case ISD::BR_JT: Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. // Ensure that libcalls are emitted before a branch. - Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); + Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); Tmp1 = LegalizeOp(Tmp1); LastCALLSEQ_END = DAG.getEntryNode(); @@ -2027,28 +2030,29 @@ MVT PTy = TLI.getPointerTy(); MachineFunction &MF = DAG.getMachineFunction(); unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); - Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); - SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); + Index= DAG.getNode(ISD::MUL, dl, PTy, + Index, DAG.getConstant(EntrySize, PTy)); + SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); MVT MemVT = MVT::getIntegerVT(EntrySize * 8); - SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, Chain, Addr, + SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, PseudoSourceValue::getJumpTable(), 0, MemVT); Addr = LD; if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { // For PIC, the sequence is: // BRIND(load(Jumptable + index) + RelocBase) // RelocBase can be JumpTable, GOT or some sort of global base. - Addr = DAG.getNode(ISD::ADD, PTy, Addr, + Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, TLI.getPICJumpTableRelocBase(Table, DAG)); } - Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); + Result = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); } } break; case ISD::BRCOND: Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. // Ensure that libcalls are emitted before a return. - Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); + Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); Tmp1 = LegalizeOp(Tmp1); LastCALLSEQ_END = DAG.getEntryNode(); @@ -2065,7 +2069,7 @@ unsigned BitWidth = Tmp2.getValueSizeInBits(); if (!DAG.MaskedValueIsZero(Tmp2, APInt::getHighBitsSet(BitWidth, BitWidth-1))) - Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); + Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, MVT::i1); break; } } @@ -2084,11 +2088,12 @@ // Expand brcond's setcc into its constituent parts and create a BR_CC // Node. if (Tmp2.getOpcode() == ISD::SETCC) { - Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), + Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, + Tmp1, Tmp2.getOperand(2), Tmp2.getOperand(0), Tmp2.getOperand(1), Node->getOperand(2)); } else { - Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, + Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, DAG.getConstant(0, Tmp2.getValueType()), Node->getOperand(2)); @@ -2099,7 +2104,7 @@ case ISD::BR_CC: Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. // Ensure that libcalls are emitted before a branch. - Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); + Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); Tmp1 = LegalizeOp(Tmp1); Tmp2 = Node->getOperand(2); // LHS Tmp3 = Node->getOperand(3); // RHS @@ -2172,7 +2177,7 @@ // Change base type to a different vector type. MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); - Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), + Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), LD->getSrcValueOffset(), LD->isVolatile(), LD->getAlignment()); Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); @@ -2214,7 +2219,7 @@ ISD::LoadExtType NewExtType = ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; - Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), + Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), Tmp1, Tmp2, LD->getSrcValue(), SVOffset, NVT, isVolatile, Alignment); @@ -2222,11 +2227,13 @@ if (ExtType == ISD::SEXTLOAD) // Having the top bits zero doesn't help when sign extending. - Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), + Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, + Result.getValueType(), Result, DAG.getValueType(SrcVT)); else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) // All the top bits are guaranteed to be zero - inform the optimizers. - Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result, + Result = DAG.getNode(ISD::AssertZext, dl, + Result.getValueType(), Result, DAG.getValueType(SrcVT)); Tmp1 = LegalizeOp(Result); @@ -2249,58 +2256,60 @@ if (TLI.isLittleEndian()) { // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD at +2:i8, 16) // Load the bottom RoundWidth bits. - Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, + Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, + Node->getValueType(0), Tmp1, Tmp2, LD->getSrcValue(), SVOffset, RoundVT, isVolatile, Alignment); // Load the remaining ExtraWidth bits. IncrementSize = RoundWidth / 8; - Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, + Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, DAG.getIntPtrConstant(IncrementSize)); - Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, + Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, LD->getSrcValue(), SVOffset + IncrementSize, ExtraVT, isVolatile, MinAlign(Alignment, IncrementSize)); // Build a factor node to remember that this load is independent of the // other one. - Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), + Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), Hi.getValue(1)); // Move the top bits to the right place. - Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, + Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); // Join the hi and lo parts. - Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); + Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); } else { // Big endian - avoid unaligned loads. // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD at +2:i8 // Load the top RoundWidth bits. - Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, + Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, LD->getSrcValue(), SVOffset, RoundVT, isVolatile, Alignment); // Load the remaining ExtraWidth bits. IncrementSize = RoundWidth / 8; - Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, + Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, DAG.getIntPtrConstant(IncrementSize)); - Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, + Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, + Node->getValueType(0), Tmp1, Tmp2, LD->getSrcValue(), SVOffset + IncrementSize, ExtraVT, isVolatile, MinAlign(Alignment, IncrementSize)); // Build a factor node to remember that this load is independent of the // other one. - Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), + Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), Hi.getValue(1)); // Move the top bits to the right place. - Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, + Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); // Join the hi and lo parts. - Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); + Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); } Tmp1 = LegalizeOp(Result); @@ -2342,10 +2351,11 @@ case TargetLowering::Expand: // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { - SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), + SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), LD->getSrcValueOffset(), LD->isVolatile(), LD->getAlignment()); - Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); + Result = DAG.getNode(ISD::FP_EXTEND, dl, + Node->getValueType(0), Load); Tmp1 = LegalizeOp(Result); // Relegalize new nodes. Tmp2 = LegalizeOp(Load.getValue(1)); break; @@ -2353,16 +2363,17 @@ assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); // Turn the unsupported load into an EXTLOAD followed by an explicit // zero/sign extend inreg. - Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), + Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), Tmp1, Tmp2, LD->getSrcValue(), LD->getSrcValueOffset(), SrcVT, LD->isVolatile(), LD->getAlignment()); SDValue ValRes; if (ExtType == ISD::SEXTLOAD) - ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), + ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, + Result.getValueType(), Result, DAG.getValueType(SrcVT)); else - ValRes = DAG.getZeroExtendInReg(Result, SrcVT); + ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. break; @@ -2383,13 +2394,13 @@ case Legal: if (cast(Node->getOperand(1))->getZExtValue()) { // 1 -> Hi - Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), + Result = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), DAG.getConstant(OpTy.getSizeInBits()/2, TLI.getShiftAmountTy())); - Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); + Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Result); } else { // 0 -> Lo - Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), + Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Node->getOperand(0)); } break; @@ -2436,7 +2447,7 @@ Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. // Ensure that libcalls are emitted before a return. - Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); + Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); Tmp1 = LegalizeOp(Tmp1); LastCALLSEQ_END = DAG.getEntryNode(); @@ -2458,9 +2469,10 @@ std::swap(Lo, Hi); if (Hi.getNode()) - Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); + Result = DAG.getNode(ISD::RET, dl, MVT::Other, + Tmp1, Lo, Tmp3, Hi,Tmp3); else - Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); + Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3); Result = LegalizeOp(Result); } else { SDNode *InVal = Tmp2.getNode(); @@ -2492,7 +2504,8 @@ // type should be returned by reference! SDValue Lo, Hi; SplitVectorOp(Tmp2, Lo, Hi); - Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); + Result = DAG.getNode(ISD::RET, dl, MVT::Other, + Tmp1, Lo, Tmp3, Hi,Tmp3); Result = LegalizeOp(Result); } } @@ -2536,7 +2549,7 @@ if (NewValues.size() == Node->getNumOperands()) Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); else - Result = DAG.getNode(ISD::RET, MVT::Other, + Result = DAG.getNode(ISD::RET, dl, MVT::Other, &NewValues[0], NewValues.size()); break; } @@ -2575,7 +2588,7 @@ Tmp3 = DAG.getConstant(CFP->getValueAPF(). bitcastToAPInt().zextOrTrunc(32), MVT::i32); - Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), + Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, isVolatile, Alignment); break; } else if (CFP->getValueType(0) == MVT::f64) { @@ -2583,7 +2596,7 @@ if (getTypeAction(MVT::i64) == Legal) { Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). zextOrTrunc(64), MVT::i64); - Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), + Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, isVolatile, Alignment); break; } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { @@ -2595,14 +2608,14 @@ SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); if (TLI.isBigEndian()) std::swap(Lo, Hi); - Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), + Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), SVOffset, isVolatile, Alignment); - Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, + Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, DAG.getIntPtrConstant(4)); - Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, + Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, isVolatile, MinAlign(Alignment, 4U)); - Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); + Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); break; } } @@ -2634,9 +2647,9 @@ break; case TargetLowering::Promote: assert(VT.isVector() && "Unknown legal promote case!"); - Tmp3 = DAG.getNode(ISD::BIT_CONVERT, + Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); - Result = DAG.getStore(Tmp1, Tmp3, Tmp2, + Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, isVolatile, Alignment); break; @@ -2647,7 +2660,7 @@ if (!ST->getMemoryVT().isVector()) { // Truncate the value and store the result. Tmp3 = PromoteOp(ST->getValue()); - Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), + Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, ST->getMemoryVT(), isVolatile, Alignment); break; @@ -2673,14 +2686,14 @@ if (TLI.isTypeLegal(TVT)) { // Turn this into a normal store of the vector type. Tmp3 = LegalizeOp(ST->getValue()); - Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), + Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, isVolatile, Alignment); Result = LegalizeOp(Result); break; } else if (NumElems == 1) { // Turn this into a normal store of the scalar type. Tmp3 = ScalarizeVectorOp(ST->getValue()); - Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), + Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, isVolatile, Alignment); // The scalarized value type may not be legal, e.g. it might require // promotion or expansion. Relegalize the scalar store. @@ -2708,7 +2721,7 @@ std::swap(Lo, Hi); } - Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), + Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), SVOffset, isVolatile, Alignment); if (Hi.getNode() == NULL) { @@ -2717,15 +2730,15 @@ break; } - Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, + Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, DAG.getIntPtrConstant(IncrementSize)); assert(isTypeLegal(Tmp2.getValueType()) && "Pointers must be legal!"); SVOffset += IncrementSize; Alignment = MinAlign(Alignment, IncrementSize); - Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), + Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset, isVolatile, Alignment); - Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); + Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); break; } // case Expand } @@ -2745,7 +2758,7 @@ // Just store the low part. This may become a non-trunc store, so make // sure to use getTruncStore, not UpdateNodeOperands below. ExpandOp(ST->getValue(), Tmp3, Tmp4); - return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), + return DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, MVT::i8, isVolatile, Alignment); } @@ -2757,8 +2770,8 @@ // storing an integral number of bytes. For example, promote // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); - Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); - Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), + Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); + Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, NVT, isVolatile, Alignment); } else if (StWidth & (StWidth - 1)) { // If not storing a power-of-2 number of bits, expand as two stores. @@ -2778,39 +2791,39 @@ if (TLI.isLittleEndian()) { // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE at +2:i8 (srl X, 16) // Store the bottom RoundWidth bits. - Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), + Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, RoundVT, isVolatile, Alignment); // Store the remaining ExtraWidth bits. IncrementSize = RoundWidth / 8; - Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, + Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, DAG.getIntPtrConstant(IncrementSize)); - Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, + Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); - Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), + Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset + IncrementSize, ExtraVT, isVolatile, MinAlign(Alignment, IncrementSize)); } else { // Big endian - avoid unaligned stores. // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE at +2:i8 X // Store the top RoundWidth bits. - Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, + Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); - Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset, - RoundVT, isVolatile, Alignment); + Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), + SVOffset, RoundVT, isVolatile, Alignment); // Store the remaining ExtraWidth bits. IncrementSize = RoundWidth / 8; - Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, + Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, DAG.getIntPtrConstant(IncrementSize)); - Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), + Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), SVOffset + IncrementSize, ExtraVT, isVolatile, MinAlign(Alignment, IncrementSize)); } // The order of the stores doesn't matter. - Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); + Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); } else { if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || Tmp2 != ST->getBasePtr()) @@ -2836,9 +2849,9 @@ case Expand: // TRUNCSTORE:i16 i32 -> STORE i16 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); - Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3); - Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, - isVolatile, Alignment); + Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); + Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), + SVOffset, isVolatile, Alignment); break; } } @@ -2873,7 +2886,7 @@ Node->getValueType(0)); Tmp2 = Tmp1.getValue(1); } else { - Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); + Tmp1 = DAG.getNode(ISD::UNDEF, dl, Node->getValueType(0)); Tmp2 = Node->getOperand(0); } break; @@ -2945,7 +2958,7 @@ unsigned BitWidth = Tmp1.getValueSizeInBits(); if (!DAG.MaskedValueIsZero(Tmp1, APInt::getHighBitsSet(BitWidth, BitWidth-1))) - Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); + Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, MVT::i1); break; } } @@ -2964,11 +2977,11 @@ } case TargetLowering::Expand: if (Tmp1.getOpcode() == ISD::SETCC) { - Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), + Result = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), Tmp2, Tmp3, cast(Tmp1.getOperand(2))->get()); } else { - Result = DAG.getSelectCC(Tmp1, + Result = DAG.getSelectCC(dl, Tmp1, DAG.getConstant(0, Tmp1.getValueType()), Tmp2, Tmp3, ISD::SETNE); } @@ -2988,14 +3001,14 @@ TruncOp = ISD::FP_ROUND; } // Promote each of the values to the new type. - Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); - Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); + Tmp2 = DAG.getNode(ExtOp, dl, NVT, Tmp2); + Tmp3 = DAG.getNode(ExtOp, dl, NVT, Tmp3); // Perform the larger operation, then round down. - Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); + Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2,Tmp3); if (TruncOp != ISD::FP_ROUND) - Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); + Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result); else - Result = DAG.getNode(TruncOp, Node->getValueType(0), Result, + Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result, DAG.getIntPtrConstant(0)); break; } @@ -3080,8 +3093,8 @@ if (NewInTy.isInteger()) assert(0 && "Cannot promote Legal Integer SETCC yet"); else { - Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); - Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); + Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1); + Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2); } Tmp1 = LegalizeOp(Tmp1); Tmp2 = LegalizeOp(Tmp2); @@ -3093,7 +3106,7 @@ // Expand a setcc node into a select_cc of the same condition, lhs, and // rhs that selects between const 1 (true) and const 0 (false). MVT VT = Node->getValueType(0); - Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, + Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); break; @@ -3122,17 +3135,18 @@ MVT TmpEltVT = Tmp1.getValueType().getVectorElementType(); SmallVector Ops(NumElems); for (unsigned i = 0; i < NumElems; ++i) { - SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT, + SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, Tmp1, DAG.getIntPtrConstant(i)); - Ops[i] = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(TmpEltVT), In1, - DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT, - Tmp2, DAG.getIntPtrConstant(i)), + Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT), + In1, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, + TmpEltVT, Tmp2, + DAG.getIntPtrConstant(i)), CC); - Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i], DAG.getConstant( + Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i], DAG.getConstant( APInt::getAllOnesValue(EltVT.getSizeInBits()), EltVT), DAG.getConstant(0, EltVT)); } - Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], NumElems); + Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems); break; } } @@ -3256,31 +3270,36 @@ OpToUse = ISD::UMUL_LOHI; } if (OpToUse) { - Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0); + Result = SDValue(DAG.getNode(OpToUse, dl, VTs, Tmp1, Tmp2).getNode(), + 0); break; } } if (Node->getOpcode() == ISD::MULHS && TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) { - Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), + Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, + VTs, Tmp1, Tmp2).getNode(), 1); break; } if (Node->getOpcode() == ISD::MULHU && TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) { - Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), + Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, + VTs, Tmp1, Tmp2).getNode(), 1); break; } if (Node->getOpcode() == ISD::SDIV && TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) { - Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), + Result = SDValue(DAG.getNode(ISD::SDIVREM, dl, + VTs, Tmp1, Tmp2).getNode(), 0); break; } if (Node->getOpcode() == ISD::UDIV && TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) { - Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), + Result = SDValue(DAG.getNode(ISD::UDIVREM, dl, + VTs, Tmp1, Tmp2).getNode(), 0); break; } @@ -3335,11 +3354,11 @@ MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); assert(OVT.isVector() && "Cannot promote this BinOp!"); // Bit convert each of the values to the new type. - Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); - Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); + Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1); + Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); // Bit convert the result back the original type. - Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); + Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result); break; } } @@ -3393,14 +3412,14 @@ // Get the sign bit of the RHS. MVT IVT = Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; - SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); - SignBit = DAG.getSetCC(TLI.getSetCCResultType(IVT), + SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); + SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(IVT), SignBit, DAG.getConstant(0, IVT), ISD::SETLT); // Get the absolute value of the result. - SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); + SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); // Select between the nabs and abs value based on the sign bit of // the input. - Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, + Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, DAG.getNode(ISD::FNEG, AbsVal.getValueType(), AbsVal), AbsVal); @@ -3412,7 +3431,7 @@ MVT NVT = Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); - Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); + Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Result); Result = LegalizeOp(Result); break; } @@ -3483,15 +3502,15 @@ assert(0 && "Cannot promote/custom this yet!"); case TargetLowering::Legal: if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) - Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); + Result = DAG.getNode(ISD::BUILD_PAIR, dl, PairTy, Tmp1, Tmp2); break; case TargetLowering::Expand: - Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); - Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); - Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, + Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Tmp1); + Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Tmp2); + Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, DAG.getConstant(PairTy.getSizeInBits()/2, TLI.getShiftAmountTy())); - Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); + Result = DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2); break; } break; @@ -3524,12 +3543,14 @@ SDVTList VTs = DAG.getVTList(VT, VT); if (Node->getOpcode() == ISD::SREM && TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) { - Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1); + Result = SDValue(DAG.getNode(ISD::SDIVREM, dl, + VTs, Tmp1, Tmp2).getNode(), 1); break; } if (Node->getOpcode() == ISD::UREM && TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) { - Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1); + Result = SDValue(DAG.getNode(ISD::UDIVREM, dl, + VTs, Tmp1, Tmp2).getNode(), 1); break; } @@ -3537,9 +3558,9 @@ if (TLI.getOperationAction(DivOpc, VT) == TargetLowering::Legal) { // X % Y -> X-X/Y*Y - Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); - Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); - Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); + Result = DAG.getNode(DivOpc, dl, VT, Tmp1, Tmp2); + Result = DAG.getNode(ISD::MUL, dl, VT, Result, Tmp2); + Result = DAG.getNode(ISD::SUB, dl, VT, Tmp1, Result); } else if (VT.isVector()) { Result = LegalizeOp(UnrollVectorOp(Op)); } else { @@ -3592,16 +3613,16 @@ break; case TargetLowering::Expand: { const Value *V = cast(Node->getOperand(2))->getValue(); - SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); + SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0); // Increment the pointer, VAList, to the next vaarg - Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, + Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, DAG.getConstant(TLI.getTargetData()-> getTypePaddedSize(VT.getTypeForMVT()), TLI.getPointerTy())); // Store the incremented VAList to the legalized pointer - Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); + Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0); // Load the actual argument out of the pointer VAList - Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); + Result = DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0); Tmp1 = LegalizeOp(Result.getValue(1)); Result = LegalizeOp(Result); break; @@ -3637,8 +3658,8 @@ // output, returning the chain. const Value *VD = cast(Node->getOperand(3))->getValue(); const Value *VS = cast(Node->getOperand(4))->getValue(); - Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0); - Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0); + Tmp4 = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp3, VS, 0); + Result = DAG.getStore(Tmp4.getValue(1), dl, Tmp4, Tmp2, VD, 0); break; } break; @@ -3718,9 +3739,9 @@ MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); - Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); - Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); - Result = DAG.getNode(ISD::SRL, NVT, Tmp1, + Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); + Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); + Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); break; } @@ -3751,24 +3772,24 @@ MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); // Zero extend the argument. - Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); + Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); // Perform the larger operation, then subtract if needed. - Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); + Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1); switch (Node->getOpcode()) { case ISD::CTPOP: Result = Tmp1; break; case ISD::CTTZ: //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) - Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1, - DAG.getConstant(NVT.getSizeInBits(), NVT), + Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), + Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), ISD::SETEQ); - Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, + Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); break; case ISD::CTLZ: // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) - Result = DAG.getNode(ISD::SUB, NVT, Tmp1, + Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, DAG.getConstant(NVT.getSizeInBits() - OVT.getSizeInBits(), NVT)); break; @@ -3816,16 +3837,16 @@ case ISD::FNEG: // Expand Y = FNEG(X) -> Y = SUB -0.0, X Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); - Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); + Result = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp2, Tmp1); break; case ISD::FABS: { // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). MVT VT = Node->getValueType(0); Tmp2 = DAG.getConstantFP(0.0, VT); - Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), + Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, ISD::SETUGT); - Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); - Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); + Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); + Result = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); break; } case ISD::FSQRT: @@ -3947,12 +3968,12 @@ MVT TVT = MVT::getVectorVT(EVT, NumElems); if (TLI.isTypeLegal(TVT)) { // Turn this into a bit convert of the vector input. - Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), + Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), LegalizeOp(Node->getOperand(0))); break; } else if (NumElems == 1) { // Turn this into a bit convert of the scalar input. - Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), + Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), ScalarizeVectorOp(Node->getOperand(0))); break; } else { @@ -4052,11 +4073,11 @@ // Since the result is legal, we should just be able to truncate the low // part of the source. - Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); + Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); break; case Promote: Result = PromoteOp(Node->getOperand(0)); - Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); + Result = DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Result); break; } break; @@ -4174,7 +4195,7 @@ break; case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); - Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); + Result = DAG.getNode(ISD::FP_EXTEND, dl, Op.getValueType(), Tmp1); break; } break; @@ -4188,7 +4209,8 @@ ExpandOp(Node->getOperand(0), Lo, Result); // Round it the rest of the way (e.g. to f32) if needed. if (DstVT!=MVT::f64) - Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1)); + Result = DAG.getNode(ISD::FP_ROUND, dl, + DstVT, Result, Op.getOperand(1)); break; } // The only other way we can lower this is to turn it into a STORE, @@ -4204,7 +4226,7 @@ break; case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); - Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1, + Result = DAG.getNode(ISD::FP_ROUND, dl, Op.getValueType(), Tmp1, Node->getOperand(1)); break; } @@ -4228,18 +4250,18 @@ switch (Node->getOpcode()) { case ISD::ANY_EXTEND: Tmp1 = PromoteOp(Node->getOperand(0)); - Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); + Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Tmp1); break; case ISD::ZERO_EXTEND: Result = PromoteOp(Node->getOperand(0)); - Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); - Result = DAG.getZeroExtendInReg(Result, + Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result); + Result = DAG.getZeroExtendInReg(Result, dl, Node->getOperand(0).getValueType()); break; case ISD::SIGN_EXTEND: Result = PromoteOp(Node->getOperand(0)); - Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); - Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), + Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result); + Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(), Result, DAG.getValueType(Node->getOperand(0).getValueType())); break; @@ -4266,9 +4288,9 @@ unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - ExtraVT.getSizeInBits(); SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); - Result = DAG.getNode(ISD::SHL, Node->getValueType(0), + Result = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), Node->getOperand(0), ShiftCst); - Result = DAG.getNode(ISD::SRA, Node->getValueType(0), + Result = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Result, ShiftCst); } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { // The only way we can lower this is to turn it into a TRUNCSTORE, @@ -4359,7 +4381,7 @@ SDValue RHS = LegalizeOp(Node->getOperand(1)); SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? - ISD::ADD : ISD::SUB, LHS.getValueType(), + ISD::ADD : ISD::SUB, dl, LHS.getValueType(), LHS, RHS); MVT OType = Node->getValueType(1); @@ -4374,21 +4396,22 @@ // Sub: // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) // - SDValue LHSSign = DAG.getSetCC(OType, LHS, Zero, ISD::SETGE); - SDValue RHSSign = DAG.getSetCC(OType, RHS, Zero, ISD::SETGE); - SDValue SignsMatch = DAG.getSetCC(OType, LHSSign, RHSSign, + SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); + SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); + SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, Node->getOpcode() == ISD::SADDO ? ISD::SETEQ : ISD::SETNE); - SDValue SumSign = DAG.getSetCC(OType, Sum, Zero, ISD::SETGE); - SDValue SumSignNE = DAG.getSetCC(OType, LHSSign, SumSign, ISD::SETNE); + SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); + SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); - SDValue Cmp = DAG.getNode(ISD::AND, OType, SignsMatch, SumSignNE); + SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); MVT ValueVTs[] = { LHS.getValueType(), OType }; SDValue Ops[] = { Sum, Cmp }; - Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2), + Result = DAG.getNode(ISD::MERGE_VALUES, dl, + DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2); SDNode *RNode = Result.getNode(); DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0)); @@ -4413,17 +4436,18 @@ SDValue RHS = LegalizeOp(Node->getOperand(1)); SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? - ISD::ADD : ISD::SUB, LHS.getValueType(), + ISD::ADD : ISD::SUB, dl, LHS.getValueType(), LHS, RHS); MVT OType = Node->getValueType(1); - SDValue Cmp = DAG.getSetCC(OType, Sum, LHS, + SDValue Cmp = DAG.getSetCC(dl, OType, Sum, LHS, Node->getOpcode () == ISD::UADDO ? ISD::SETULT : ISD::SETUGT); MVT ValueVTs[] = { LHS.getValueType(), OType }; SDValue Ops[] = { Sum, Cmp }; - Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2), + Result = DAG.getNode(ISD::MERGE_VALUES, dl, + DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2); SDNode *RNode = Result.getNode(); DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0)); From gohman at apple.com Mon Feb 2 18:04:44 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 03 Feb 2009 00:04:44 -0000 Subject: [llvm-commits] [llvm] r63575 - in /llvm/trunk/lib/Target/X86: X86.td X86Subtarget.cpp Message-ID: <200902030004.n1304ilT026295@zion.cs.uiuc.edu> Author: djg Date: Mon Feb 2 18:04:43 2009 New Revision: 63575 URL: http://llvm.org/viewvc/llvm-project?rev=63575&view=rev Log: Change Feature64Bit to not imply FeatureSSE2. All x86-64 hardware has SSE2, however it's possible to disable SSE2, and the subtarget support code thinks that if 64-bit implies SSE2 and SSE2 is disabled then 64-bit should also be disabled. Instead, just mark all the 64-bit subtargets as explicitly supporting SSE2. Also, move the code that makes -march=x86-64 enable 64-bit support by default to only apply when there is no explicit subtarget. If you need to specify a subtarget and you want 64-bit code, you'll need to select a subtarget that supports 64-bit code. Modified: llvm/trunk/lib/Target/X86/X86.td llvm/trunk/lib/Target/X86/X86Subtarget.cpp Modified: llvm/trunk/lib/Target/X86/X86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=63575&r1=63574&r2=63575&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86.td (original) +++ llvm/trunk/lib/Target/X86/X86.td Mon Feb 2 18:04:43 2009 @@ -45,9 +45,11 @@ def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", "Enable 3DNow! Athlon instructions", [Feature3DNow]>; +// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied +// feature, because SSE2 can be disabled (e.g. for compiling OS kernels) +// without disabling 64-bit mode. def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", - "Support 64-bit instructions", - [FeatureSSE2]>; + "Support 64-bit instructions">; def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true", "Bit testing of memory is slow">; @@ -70,7 +72,7 @@ def : Proc<"pentium3", [FeatureSSE1]>; def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>; def : Proc<"pentium4", [FeatureSSE2]>; -def : Proc<"x86-64", [Feature64Bit, FeatureSlowBTMem]>; +def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>; def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>; def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>; def : Proc<"nocona", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>; @@ -87,10 +89,14 @@ def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; -def : Proc<"k8", [Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>; -def : Proc<"opteron", [Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>; -def : Proc<"athlon64", [Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>; -def : Proc<"athlon-fx", [Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>; +def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit, + FeatureSlowBTMem]>; +def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit, + FeatureSlowBTMem]>; +def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit, + FeatureSlowBTMem]>; +def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit, + FeatureSlowBTMem]>; def : Proc<"winchip-c6", [FeatureMMX]>; def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>; Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=63575&r1=63574&r2=63575&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon Feb 2 18:04:43 2009 @@ -327,21 +327,20 @@ } else { // Otherwise, use CPUID to auto-detect feature set. AutoDetectSubtargetFeatures(); - if (Is64Bit && X86SSELevel < SSE2) { - // Make sure SSE2 is enabled, it is available on all X86-64 CPUs. - X86SSELevel = SSE2; - } - } - - // If requesting codegen for X86-64, make sure that 64-bit features - // are enabled. - if (Is64Bit) { + // If requesting codegen for X86-64, make sure that 64-bit features + // are enabled. + if (Is64Bit) HasX86_64 = true; + // Make sure SSE2 is enabled; it is available on all X86-64 CPUs. + if (Is64Bit && X86SSELevel < SSE2) + X86SSELevel = SSE2; } - assert(!Is64Bit || HasX86_64); + DOUT << "Subtarget features: SSELevel " << X86SSELevel << ", 3DNowLevel " << X863DNowLevel << ", 64bit " << HasX86_64 << "\n"; + assert((!Is64Bit || HasX86_64) && + "64-bit code requested on a subtarget that doesn't support it!"); // Set the boolean corresponding to the current target triple, or the default // if one cannot be determined, to true. From gohman at apple.com Mon Feb 2 18:08:45 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 03 Feb 2009 00:08:45 -0000 Subject: [llvm-commits] [llvm] r63577 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200902030008.n1308jTp026477@zion.cs.uiuc.edu> Author: djg Date: Mon Feb 2 18:08:45 2009 New Revision: 63577 URL: http://llvm.org/viewvc/llvm-project?rev=63577&view=rev Log: Use the SubclassData field to hold ExtType, isTrunc, and MemIndexedMode information. This eliminates the need for the Flags field in MemSDNode, so this makes LoadSDNode and StoreSDNode smaller. Also, it makes FoldingSetNodeIDs for loads and stores two AddIntegers smaller. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=63577&r1=63576&r2=63577&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Mon Feb 2 18:08:45 2009 @@ -1596,10 +1596,6 @@ //! SVOffset - Memory location offset. Note that base is defined in MemSDNode int SVOffset; - /// Flags - the low bit indicates whether this is a volatile reference; - /// the remainder is a log2 encoding of the alignment in bytes. - unsigned Flags; - public: MemSDNode(unsigned Opc, SDVTList VTs, MVT MemoryVT, const Value *srcValue, int SVOff, @@ -1618,9 +1614,17 @@ unsigned alignment, bool isvolatile); /// Returns alignment and volatility of the memory access - unsigned getAlignment() const { return (1u << (Flags >> 1)) >> 1; } - bool isVolatile() const { return Flags & 1; } + unsigned getAlignment() const { return (1u << (SubclassData >> 6)) >> 1; } + bool isVolatile() const { return (SubclassData >> 5) & 1; } + /// getRawSubclassData - Return the SubclassData value, which contains an + /// encoding of the alignment and volatile information, as well as bits + /// used by subclasses. This function should only be used to compute a + /// FoldingSetNodeID value. + unsigned getRawSubclassData() const { + return SubclassData; + } + /// Returns the SrcValue and offset that describes the location of the access const Value *getSrcValue() const { return SrcValue; } int getSrcValueOffset() const { return SVOffset; } @@ -1637,10 +1641,6 @@ return getOperand(getOpcode() == ISD::STORE ? 2 : 1); } - /// getRawFlags - Represent the flags as a bunch of bits. - /// - unsigned getRawFlags() const { return Flags; } - // Methods to support isa and dyn_cast static bool classof(const MemSDNode *) { return true; } static bool classof(const SDNode *N) { @@ -2354,9 +2354,10 @@ SDVTList VTs, ISD::MemIndexedMode AM, MVT VT, const Value *SV, int SVO, unsigned Align, bool Vol) : MemSDNode(NodeTy, VTs, VT, SV, SVO, Align, Vol) { - SubclassData = AM; - InitOperands(Ops, Operands, numOperands); assert(Align != 0 && "Loads and stores should have non-zero aligment"); + SubclassData |= AM << 2; + assert(getAddressingMode() == AM && "MemIndexedMode encoding error!"); + InitOperands(Ops, Operands, numOperands); assert((getOffset().getOpcode() == ISD::UNDEF || isIndexed()) && "Only indexed loads and stores have a non-undef offset operand"); } @@ -2364,9 +2365,10 @@ unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM, MVT VT, const Value *SV, int SVO, unsigned Align, bool Vol) : MemSDNode(NodeTy, dl, VTs, VT, SV, SVO, Align, Vol) { - SubclassData = AM; - InitOperands(Ops, Operands, numOperands); assert(Align != 0 && "Loads and stores should have non-zero aligment"); + SubclassData |= AM << 2; + assert(getAddressingMode() == AM && "MemIndexedMode encoding error!"); + InitOperands(Ops, Operands, numOperands); assert((getOffset().getOpcode() == ISD::UNDEF || isIndexed()) && "Only indexed loads and stores have a non-undef offset operand"); } @@ -2378,7 +2380,7 @@ /// getAddressingMode - Return the addressing mode for this load or store: /// unindexed, pre-inc, pre-dec, post-inc, or post-dec. ISD::MemIndexedMode getAddressingMode() const { - return ISD::MemIndexedMode(SubclassData & 7); + return ISD::MemIndexedMode((SubclassData >> 2) & 7); } /// isIndexed - Return true if this is a pre/post inc/dec load/store. @@ -2404,21 +2406,23 @@ const Value *SV, int O=0, unsigned Align=0, bool Vol=false) : LSBaseSDNode(ISD::LOAD, ChainPtrOff, 3, VTs, AM, LVT, SV, O, Align, Vol) { - SubclassData |= (unsigned short)ETy << 3; + SubclassData |= (unsigned short)ETy; + assert(getExtensionType() == ETy && "LoadExtType encoding error!"); } LoadSDNode(SDValue *ChainPtrOff, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT LVT, const Value *SV, int O=0, unsigned Align=0, bool Vol=false) : LSBaseSDNode(ISD::LOAD, dl, ChainPtrOff, 3, VTs, AM, LVT, SV, O, Align, Vol) { - SubclassData |= (unsigned short)ETy << 3; + SubclassData |= (unsigned short)ETy; + assert(getExtensionType() == ETy && "LoadExtType encoding error!"); } public: /// getExtensionType - Return whether this is a plain node, /// or one of the varieties of value-extending loads. ISD::LoadExtType getExtensionType() const { - return ISD::LoadExtType((SubclassData >> 3) & 3); + return ISD::LoadExtType(SubclassData & 3); } const SDValue &getBasePtr() const { return getOperand(1); } @@ -2440,21 +2444,23 @@ const Value *SV, int O=0, unsigned Align=0, bool Vol=false) : LSBaseSDNode(ISD::STORE, ChainValuePtrOff, 4, VTs, AM, SVT, SV, O, Align, Vol) { - SubclassData |= (unsigned short)isTrunc << 3; + SubclassData |= (unsigned short)isTrunc; + assert(isTruncatingStore() == isTrunc && "isTrunc encoding error!"); } StoreSDNode(SDValue *ChainValuePtrOff, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, MVT SVT, const Value *SV, int O=0, unsigned Align=0, bool Vol=false) : LSBaseSDNode(ISD::STORE, dl, ChainValuePtrOff, 4, VTs, AM, SVT, SV, O, Align, Vol) { - SubclassData |= (unsigned short)isTrunc << 3; + SubclassData |= (unsigned short)isTrunc; + assert(isTruncatingStore() == isTrunc && "isTrunc encoding error!"); } public: /// isTruncatingStore - Return true if the op does a truncation before store. /// For integers this is the same as doing a TRUNCATE and storing the result. /// For floats, it is the same as doing an FP_ROUND and storing the result. - bool isTruncatingStore() const { return (SubclassData >> 3) & 1; } + bool isTruncatingStore() const { return SubclassData & 1; } const SDValue &getValue() const { return getOperand(1); } const SDValue &getBasePtr() const { return getOperand(2); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63577&r1=63576&r2=63577&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Feb 2 18:08:45 2009 @@ -429,18 +429,14 @@ } case ISD::LOAD: { const LoadSDNode *LD = cast(N); - ID.AddInteger(LD->getAddressingMode()); - ID.AddInteger(LD->getExtensionType()); ID.AddInteger(LD->getMemoryVT().getRawBits()); - ID.AddInteger(LD->getRawFlags()); + ID.AddInteger(LD->getRawSubclassData()); break; } case ISD::STORE: { const StoreSDNode *ST = cast(N); - ID.AddInteger(ST->getAddressingMode()); - ID.AddInteger(ST->isTruncatingStore()); ID.AddInteger(ST->getMemoryVT().getRawBits()); - ID.AddInteger(ST->getRawFlags()); + ID.AddInteger(ST->getRawSubclassData()); break; } case ISD::ATOMIC_CMP_SWAP: @@ -456,7 +452,8 @@ case ISD::ATOMIC_LOAD_UMIN: case ISD::ATOMIC_LOAD_UMAX: { const AtomicSDNode *AT = cast(N); - ID.AddInteger(AT->getRawFlags()); + ID.AddInteger(AT->getMemoryVT().getRawBits()); + ID.AddInteger(AT->getRawSubclassData()); break; } } // end switch (N->getOpcode()) @@ -476,11 +473,20 @@ } /// encodeMemSDNodeFlags - Generic routine for computing a value for use in -/// the CSE map that carries both alignment and volatility information. +/// the CSE map that carries alignment, volatility, indexing mode, and +/// extension/truncation information. /// static inline unsigned -encodeMemSDNodeFlags(bool isVolatile, unsigned Alignment) { - return isVolatile | ((Log2_32(Alignment) + 1) << 1); +encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, + bool isVolatile, unsigned Alignment) { + assert((ConvType & 3) == ConvType && + "ConvType may not require more than 2 bits!"); + assert((AM & 7) == AM && + "AM may not require more than 3 bits!"); + return ConvType | + (AM << 2) | + (isVolatile << 5) | + ((Log2_32(Alignment) + 1) << 6); } //===----------------------------------------------------------------------===// @@ -853,7 +859,6 @@ } else { NegOne = getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); } - return getNode(ISD::XOR, DL, VT, Val, NegOne); } @@ -3417,6 +3422,7 @@ SDVTList VTs = getVTList(VT, MVT::Other); FoldingSetNodeID ID; + ID.AddInteger(MemVT.getRawBits()); SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; AddNodeIDNode(ID, Opcode, VTs, Ops, 4); void* IP = 0; @@ -3445,6 +3451,7 @@ SDVTList VTs = getVTList(VT, MVT::Other); FoldingSetNodeID ID; + ID.AddInteger(MemVT.getRawBits()); SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; AddNodeIDNode(ID, Opcode, VTs, Ops, 4); void* IP = 0; @@ -3483,6 +3490,7 @@ SDVTList VTs = getVTList(VT, MVT::Other); FoldingSetNodeID ID; + ID.AddInteger(MemVT.getRawBits()); SDValue Ops[] = {Chain, Ptr, Val}; AddNodeIDNode(ID, Opcode, VTs, Ops, 3); void* IP = 0; @@ -3521,6 +3529,7 @@ SDVTList VTs = getVTList(VT, MVT::Other); FoldingSetNodeID ID; + ID.AddInteger(MemVT.getRawBits()); SDValue Ops[] = {Chain, Ptr, Val}; AddNodeIDNode(ID, Opcode, VTs, Ops, 3); void* IP = 0; @@ -3727,10 +3736,8 @@ SDValue Ops[] = { Chain, Ptr, Offset }; FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); - ID.AddInteger(AM); - ID.AddInteger(ExtType); ID.AddInteger(EVT.getRawBits()); - ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); + ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment)); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); @@ -3778,10 +3785,8 @@ SDValue Ops[] = { Chain, Ptr, Offset }; FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); - ID.AddInteger(AM); - ID.AddInteger(ExtType); ID.AddInteger(EVT.getRawBits()); - ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); + ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment)); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); @@ -3868,10 +3873,9 @@ SDValue Ops[] = { Chain, Val, Ptr, Undef }; FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); - ID.AddInteger(ISD::UNINDEXED); - ID.AddInteger(false); ID.AddInteger(VT.getRawBits()); - ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); + ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, + isVolatile, Alignment)); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); @@ -3896,10 +3900,9 @@ SDValue Ops[] = { Chain, Val, Ptr, Undef }; FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); - ID.AddInteger(ISD::UNINDEXED); - ID.AddInteger(false); ID.AddInteger(VT.getRawBits()); - ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); + ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, + isVolatile, Alignment)); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); @@ -3932,10 +3935,9 @@ SDValue Ops[] = { Chain, Val, Ptr, Undef }; FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); - ID.AddInteger(ISD::UNINDEXED); - ID.AddInteger(1); ID.AddInteger(SVT.getRawBits()); - ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); + ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, + isVolatile, Alignment)); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); @@ -3968,10 +3970,9 @@ SDValue Ops[] = { Chain, Val, Ptr, Undef }; FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); - ID.AddInteger(ISD::UNINDEXED); - ID.AddInteger(1); ID.AddInteger(SVT.getRawBits()); - ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); + ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, + isVolatile, Alignment)); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); @@ -3993,10 +3994,8 @@ SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); - ID.AddInteger(AM); - ID.AddInteger(ST->isTruncatingStore()); ID.AddInteger(ST->getMemoryVT().getRawBits()); - ID.AddInteger(ST->getRawFlags()); + ID.AddInteger(ST->getRawSubclassData()); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); @@ -4020,10 +4019,8 @@ SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); - ID.AddInteger(AM); - ID.AddInteger(ST->isTruncatingStore()); ID.AddInteger(ST->getMemoryVT().getRawBits()); - ID.AddInteger(ST->getRawFlags()); + ID.AddInteger(ST->getRawSubclassData()); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); @@ -5339,9 +5336,8 @@ MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, MVT memvt, const Value *srcValue, int SVO, unsigned alignment, bool vol) - : SDNode(Opc, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), - Flags(encodeMemSDNodeFlags(vol, alignment)) { - + : SDNode(Opc, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { + SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); assert(getAlignment() == alignment && "Alignment representation error!"); assert(isVolatile() == vol && "Volatile representation error!"); @@ -5351,8 +5347,8 @@ unsigned NumOps, MVT memvt, const Value *srcValue, int SVO, unsigned alignment, bool vol) : SDNode(Opc, VTs, Ops, NumOps), - MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), - Flags(vol | ((Log2_32(alignment) + 1) << 1)) { + MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { + SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); assert(getAlignment() == alignment && "Alignment representation error!"); assert(isVolatile() == vol && "Volatile representation error!"); @@ -5361,9 +5357,8 @@ MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt, const Value *srcValue, int SVO, unsigned alignment, bool vol) - : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), - Flags(encodeMemSDNodeFlags(vol, alignment)) { - + : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { + SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); assert(getAlignment() == alignment && "Alignment representation error!"); assert(isVolatile() == vol && "Volatile representation error!"); @@ -5374,8 +5369,8 @@ unsigned NumOps, MVT memvt, const Value *srcValue, int SVO, unsigned alignment, bool vol) : SDNode(Opc, dl, VTs, Ops, NumOps), - MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), - Flags(vol | ((Log2_32(alignment) + 1) << 1)) { + MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { + SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); assert(getAlignment() == alignment && "Alignment representation error!"); assert(isVolatile() == vol && "Volatile representation error!"); From gohman at apple.com Mon Feb 2 18:20:22 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 03 Feb 2009 00:20:22 -0000 Subject: [llvm-commits] [llvm] r63579 - /llvm/trunk/test/CodeGen/X86/bt.ll Message-ID: <200902030020.n130KMpN026852@zion.cs.uiuc.edu> Author: djg Date: Mon Feb 2 18:20:22 2009 New Revision: 63579 URL: http://llvm.org/viewvc/llvm-project?rev=63579&view=rev Log: Add explicit -march=x86 to these tests so that they don't default to -march=x86-64 on 64-bit hosts. Modified: llvm/trunk/test/CodeGen/X86/bt.ll Modified: llvm/trunk/test/CodeGen/X86/bt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bt.ll?rev=63579&r1=63578&r2=63579&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/bt.ll (original) +++ llvm/trunk/test/CodeGen/X86/bt.ll Mon Feb 2 18:20:22 2009 @@ -1,6 +1,6 @@ ; RUN: llvm-as < %s | llc -march=x86 | grep btl | count 28 -; RUN: llvm-as < %s | llc -mcpu=pentium4 | grep btl | not grep esp -; RUN: llvm-as < %s | llc -mcpu=penryn | grep btl | not grep esp +; RUN: llvm-as < %s | llc -march=x86 -mcpu=pentium4 | grep btl | not grep esp +; RUN: llvm-as < %s | llc -march=x86 -mcpu=penryn | grep btl | not grep esp ; PR3253 ; The register+memory form of the BT instruction should be usable on From isanbard at gmail.com Mon Feb 2 18:27:10 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 03 Feb 2009 00:27:10 -0000 Subject: [llvm-commits] [llvm] r63580 - /llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c Message-ID: <200902030027.n130RAXL027073@zion.cs.uiuc.edu> Author: void Date: Mon Feb 2 18:27:09 2009 New Revision: 63580 URL: http://llvm.org/viewvc/llvm-project?rev=63580&view=rev Log: This is passing for us. Should it have been reenabled? Modified: llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c Modified: llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c?rev=63580&r1=63579&r2=63580&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c (original) +++ llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c Mon Feb 2 18:27:09 2009 @@ -2,8 +2,7 @@ // PR3402 // This is a test for x86/x86-64, add your target below if it FAILs. // XFAIL: alpha|ia64|arm|powerpc|sparc -// reverted -// XFAIL: * + typedef unsigned long __kernel_size_t; typedef __kernel_size_t size_t; void *memset(void *s, int c, size_t n); From isanbard at gmail.com Mon Feb 2 18:35:12 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 03 Feb 2009 00:35:12 -0000 Subject: [llvm-commits] [llvm] r63582 - /llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c Message-ID: <200902030035.n130ZCtY027381@zion.cs.uiuc.edu> Author: void Date: Mon Feb 2 18:35:11 2009 New Revision: 63582 URL: http://llvm.org/viewvc/llvm-project?rev=63582&view=rev Log: It fails on Linux. XFAIL that machine. Modified: llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c Modified: llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c?rev=63582&r1=63581&r2=63582&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c (original) +++ llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c Mon Feb 2 18:35:11 2009 @@ -1,8 +1,8 @@ // RUN: $llvmgcc -m64 -O1 -march=core2 -mno-sse %s -S -o - | not grep xmm // PR3402 // This is a test for x86/x86-64, add your target below if it FAILs. -// XFAIL: alpha|ia64|arm|powerpc|sparc - +// FIXME: Revert "linux" when fixed. +// XFAIL: alpha|ia64|arm|powerpc|sparc|linux typedef unsigned long __kernel_size_t; typedef __kernel_size_t size_t; void *memset(void *s, int c, size_t n); From isanbard at gmail.com Mon Feb 2 18:41:30 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 2 Feb 2009 16:41:30 -0800 Subject: [llvm-commits] [llvm] r63539 - /llvm/trunk/win32/config.h In-Reply-To: <49ea1292-789b-48bf-9c6c-95fb73d71511@w1g2000prm.googlegroups.com> References: <200902021922.n12JM3W7015508@zion.cs.uiuc.edu> <49ea1292-789b-48bf-9c6c-95fb73d71511@w1g2000prm.googlegroups.com> Message-ID: <16e5fdf90902021641h7dfd7779v736716e6e5f119b@mail.gmail.com> On Mon, Feb 2, 2009 at 12:39 PM, Gabor Greif wrote: > On 2 Feb., 20:22, Steve Naroff wrote: >> Author: snaroff >> Date: Mon Feb 2 13:22:02 2009 >> New Revision: 63539 >> >> URL:http://llvm.org/viewvc/llvm-project?rev=63539&view=rev >> Log: >> Update hand-crafted VC++ build. >> - Add PACKAGE_STRING definition to Windows config.h. >> >> Modified: >> llvm/trunk/win32/config.h >> >> Modified: llvm/trunk/win32/config.h >> URL:http://llvm.org/viewvc/llvm-project/llvm/trunk/win32/config.h?rev=635... >> >> =========================================================================== === >> --- llvm/trunk/win32/config.h (original) >> +++ llvm/trunk/win32/config.h Mon Feb 2 13:22:02 2009 >> @@ -3,6 +3,7 @@ >> >> #define PACKAGE_NAME "LLVM (win32 vc8.0)" >> #define PACKAGE_VERSION 2.4 > > Bill, this ^^^^^^ does not seem right. > Bill? :-) -bw From dalej at apple.com Mon Feb 2 18:47:48 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 03 Feb 2009 00:47:48 -0000 Subject: [llvm-commits] [llvm] r63583 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/TargetLowering.cpp Message-ID: <200902030047.n130ln7p027822@zion.cs.uiuc.edu> Author: johannes Date: Mon Feb 2 18:47:48 2009 New Revision: 63583 URL: http://llvm.org/viewvc/llvm-project?rev=63583&view=rev Log: Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63583&r1=63582&r2=63583&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Feb 2 18:47:48 2009 @@ -904,7 +904,7 @@ /// FoldSetCC - Constant fold a setcc to true or false. SDValue FoldSetCC(MVT VT, SDValue N1, - SDValue N2, ISD::CondCode Cond); + SDValue N2, ISD::CondCode Cond, DebugLoc dl); /// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We /// use this predicate to simplify operations downstream. Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=63583&r1=63582&r2=63583&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon Feb 2 18:47:48 2009 @@ -789,7 +789,7 @@ /// and cc. If it is unable to simplify it, return a null SDValue. SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, - DAGCombinerInfo &DCI) const; + DAGCombinerInfo &DCI, DebugLoc dl) const; /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the /// node is a GlobalAddress + offset. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63583&r1=63582&r2=63583&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Feb 2 18:47:48 2009 @@ -207,7 +207,7 @@ SDValue N3, ISD::CondCode CC, bool NotExtCompare = false); SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, - bool foldBooleans = true); + DebugLoc DL, bool foldBooleans = true); SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, unsigned HiOp); SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); @@ -2911,7 +2911,7 @@ // Determine if the condition we're dealing with is constant SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), - N0, N1, CC, false); + N0, N1, CC, N->getDebugLoc(), false); if (SCC.getNode()) AddToWorkList(SCC.getNode()); if (ConstantSDNode *SCCC = dyn_cast_or_null(SCC.getNode())) { @@ -2937,7 +2937,8 @@ SDValue DAGCombiner::visitSETCC(SDNode *N) { return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), - cast(N->getOperand(2))->get()); + cast(N->getOperand(2))->get(), + N->getDebugLoc()); } // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: @@ -4434,7 +4435,8 @@ // Use SimplifySetCC to simplify SETCC's. SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), - CondLHS, CondRHS, CC->get(), false); + CondLHS, CondRHS, CC->get(), N->getDebugLoc(), + false); if (Simp.getNode()) AddToWorkList(Simp.getNode()); ConstantSDNode *SCCC = dyn_cast_or_null(Simp.getNode()); @@ -5686,7 +5688,7 @@ // Determine if the condition we're dealing with is constant SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), - N0, N1, CC, false); + N0, N1, CC, DL, false); if (SCC.getNode()) AddToWorkList(SCC.getNode()); ConstantSDNode *SCCC = dyn_cast_or_null(SCC.getNode()); @@ -5880,10 +5882,10 @@ /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, - bool foldBooleans) { + DebugLoc DL, bool foldBooleans) { TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, Level == Unrestricted, false, this); - return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); + return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); } /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63583&r1=63582&r2=63583&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Feb 2 18:47:48 2009 @@ -5315,12 +5315,12 @@ // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()), - LHSLo, RHSLo, LowCC, false, DagCombineInfo); + LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl); if (!Tmp1.getNode()) Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), LHSLo, RHSLo, LowCC); Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), - LHSHi, RHSHi, CCCode, false, DagCombineInfo); + LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl); if (!Tmp2.getNode()) Tmp2 = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(LHSHi.getValueType()), @@ -5343,7 +5343,7 @@ } else { Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), LHSHi, RHSHi, ISD::SETEQ, false, - DagCombineInfo); + DagCombineInfo, dl); if (!Result.getNode()) Result=DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), LHSHi, RHSHi, ISD::SETEQ); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=63583&r1=63582&r2=63583&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon Feb 2 18:47:48 2009 @@ -2034,12 +2034,12 @@ TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); SDValue Tmp1, Tmp2; Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()), - LHSLo, RHSLo, LowCC, false, DagCombineInfo); + LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl); if (!Tmp1.getNode()) Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), LHSLo, RHSLo, LowCC); Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), - LHSHi, RHSHi, CCCode, false, DagCombineInfo); + LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl); if (!Tmp2.getNode()) Tmp2 = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(LHSHi.getValueType()), @@ -2063,7 +2063,8 @@ } NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), - LHSHi, RHSHi, ISD::SETEQ, false, DagCombineInfo); + LHSHi, RHSHi, ISD::SETEQ, false, + DagCombineInfo, dl); if (!NewLHS.getNode()) NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), LHSHi, RHSHi, ISD::SETEQ); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63583&r1=63582&r2=63583&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Feb 2 18:47:48 2009 @@ -1334,7 +1334,7 @@ } SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, - SDValue N2, ISD::CondCode Cond) { + SDValue N2, ISD::CondCode Cond, DebugLoc dl) { // These setcc operations always fold. switch (Cond) { default: break; @@ -1387,29 +1387,29 @@ switch (Cond) { default: break; case ISD::SETEQ: if (R==APFloat::cmpUnordered) - return getNode(ISD::UNDEF, VT); + return getNode(ISD::UNDEF, dl, VT); // fall through case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); case ISD::SETNE: if (R==APFloat::cmpUnordered) - return getNode(ISD::UNDEF, VT); + return getNode(ISD::UNDEF, dl, VT); // fall through case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || R==APFloat::cmpLessThan, VT); case ISD::SETLT: if (R==APFloat::cmpUnordered) - return getNode(ISD::UNDEF, VT); + return getNode(ISD::UNDEF, dl, VT); // fall through case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); case ISD::SETGT: if (R==APFloat::cmpUnordered) - return getNode(ISD::UNDEF, VT); + return getNode(ISD::UNDEF, dl, VT); // fall through case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); case ISD::SETLE: if (R==APFloat::cmpUnordered) - return getNode(ISD::UNDEF, VT); + return getNode(ISD::UNDEF, dl, VT); // fall through case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || R==APFloat::cmpEqual, VT); case ISD::SETGE: if (R==APFloat::cmpUnordered) - return getNode(ISD::UNDEF, VT); + return getNode(ISD::UNDEF, dl, VT); // fall through case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || R==APFloat::cmpEqual, VT); @@ -1427,7 +1427,7 @@ } } else { // Ensure that the constant occurs on the RHS. - return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); + return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); } } @@ -2832,12 +2832,12 @@ SmallVector Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); - return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); + return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); } break; case ISD::SETCC: { // Use FoldSetCC to simplify SETCC's. - SDValue Simp = FoldSetCC(VT, N1, N2, cast(N3)->get()); + SDValue Simp = FoldSetCC(VT, N1, N2, cast(N3)->get(), DL); if (Simp.getNode()) return Simp; break; } @@ -2854,7 +2854,7 @@ case ISD::BRCOND: if (N2C) { if (N2C->getZExtValue()) // Unconditional branch - return getNode(ISD::BR, MVT::Other, N1, N3); + return getNode(ISD::BR, DL, MVT::Other, N1, N3); else return N1; // Never-taken branch } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=63583&r1=63582&r2=63583&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon Feb 2 18:47:48 2009 @@ -760,6 +760,7 @@ assert(Op.getValueSizeInBits() == BitWidth && "Mask size mismatches value type size!"); APInt NewMask = DemandedMask; + DebugLoc dl = Op.getNode()->getDebugLoc(); // Don't know anything. KnownZero = KnownOne = APInt(BitWidth, 0); @@ -778,7 +779,8 @@ } else if (DemandedMask == 0) { // Not demanding any bits from Op. if (Op.getOpcode() != ISD::UNDEF) - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); + return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, dl, + Op.getValueType())); return false; } else if (Depth == 6) { // Limit search depth. return false; @@ -905,8 +907,8 @@ if ((KnownOne & KnownOne2) == KnownOne) { MVT VT = Op.getValueType(); SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), - ANDC)); + return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, + Op.getOperand(0), ANDC)); } } @@ -919,7 +921,7 @@ if (Expanded.isAllOnesValue()) { if (Expanded != C->getAPIntValue()) { MVT VT = Op.getValueType(); - SDValue New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), + SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), TLO.DAG.getConstant(Expanded, VT)); return TLO.CombineTo(Op, New); } @@ -995,7 +997,7 @@ SDValue NewSA = TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); MVT VT = Op.getValueType(); - return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, + return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, InOp.getOperand(0), NewSA)); } } @@ -1036,7 +1038,7 @@ SDValue NewSA = TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); - return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, + return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, InOp.getOperand(0), NewSA)); } } @@ -1059,7 +1061,7 @@ // variable. The low bit of the shift cannot be an input sign bit unless // the shift amount is >= the size of the datatype, which is undefined. if (DemandedMask == 1) - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, Op.getValueType(), + return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), Op.getOperand(0), Op.getOperand(1))); if (ConstantSDNode *SA = dyn_cast(Op.getOperand(1))) { @@ -1091,7 +1093,8 @@ // If the input sign bit is known to be zero, or if none of the top bits // are demanded, turn this into an unsigned shift right. if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), + return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, + Op.getOperand(0), Op.getOperand(1))); } else if (KnownOne.intersects(SignBit)) { // New bits are known one. KnownOne |= HighBits; @@ -1132,7 +1135,7 @@ // If the input sign bit is known zero, convert this into a zero extension. if (KnownZero.intersects(InSignBit)) return TLO.CombineTo(Op, - TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); + TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); if (KnownOne.intersects(InSignBit)) { // Input sign bit known set KnownOne |= NewBits; @@ -1152,7 +1155,7 @@ APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; if (!NewBits.intersects(NewMask)) - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, + return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Op.getOperand(0))); @@ -1174,8 +1177,9 @@ // If none of the top bits are demanded, convert this into an any_extend. if (NewBits == 0) - return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), - Op.getOperand(0))); + return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, + Op.getValueType(), + Op.getOperand(0))); // Since some of the sign extended bits are demanded, we know that the sign // bit is demanded. @@ -1191,7 +1195,7 @@ // If the sign bit is known zero, convert this to a zero extend. if (KnownZero.intersects(InSignBit)) - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, + return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Op.getOperand(0))); @@ -1247,11 +1251,13 @@ if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { // None of the shifted in bits are needed. Add a truncate of the // shift input, then shift it. - SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, + SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), In.getOperand(0)); - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(), - NewTrunc, In.getOperand(1))); + return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, + Op.getValueType(), + NewTrunc, + In.getOperand(1))); } } break; @@ -1361,7 +1367,7 @@ SDValue TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, - DAGCombinerInfo &DCI) const { + DAGCombinerInfo &DCI, DebugLoc dl) const { SelectionDAG &DAG = DCI.DAG; // These setcc operations always fold. @@ -1376,7 +1382,7 @@ if (ConstantSDNode *N1C = dyn_cast(N1.getNode())) { const APInt &C1 = N1C->getAPIntValue(); if (isa(N0.getNode())) { - return DAG.FoldSetCC(VT, N0, N1, Cond); + return DAG.FoldSetCC(VT, N0, N1, Cond, dl); } else { // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an // equality comparison, then we're just comparing whether X itself is @@ -1397,7 +1403,7 @@ Cond = ISD::SETEQ; } SDValue Zero = DAG.getConstant(0, N0.getValueType()); - return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), + return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), Zero, Cond); } } @@ -1442,16 +1448,17 @@ MVT PtrType = Lod->getOperand(1).getValueType(); SDValue Ptr = Lod->getBasePtr(); if (bestOffset != 0) - Ptr = DAG.getNode(ISD::ADD, PtrType, Lod->getBasePtr(), + Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), DAG.getConstant(bestOffset, PtrType)); unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); - SDValue NewLoad = DAG.getLoad(newVT, Lod->getChain(), Ptr, + SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, Lod->getSrcValue(), Lod->getSrcValueOffset() + bestOffset, false, NewAlign); - return DAG.getSetCC(VT, DAG.getNode(ISD::AND, newVT, NewLoad, + return DAG.getSetCC(dl, VT, + DAG.getNode(ISD::AND, dl, newVT, NewLoad, DAG.getConstant(bestMask, newVT)), - DAG.getConstant(0LL, newVT), Cond); + DAG.getConstant(0LL, newVT), Cond); } } } @@ -1492,7 +1499,7 @@ case ISD::SETUGE: case ISD::SETULT: case ISD::SETULE: - return DAG.getSetCC(VT, N0.getOperand(0), + return DAG.getSetCC(dl, VT, N0.getOperand(0), DAG.getConstant(APInt(C1).trunc(InSize), N0.getOperand(0).getValueType()), Cond); @@ -1520,13 +1527,13 @@ ZextOp = N0.getOperand(0); } else { APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); - ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), + ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), DAG.getConstant(Imm, Op0Ty)); } if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(ZextOp.getNode()); // Otherwise, make this a use of a zext. - return DAG.getSetCC(VT, ZextOp, + return DAG.getSetCC(dl, VT, ZextOp, DAG.getConstant(C1 & APInt::getLowBitsSet( ExtDstTyBits, ExtSrcTyBits), @@ -1545,7 +1552,7 @@ ISD::CondCode CC = cast(N0.getOperand(2))->get(); CC = ISD::getSetCCInverse(CC, N0.getOperand(0).getValueType().isInteger()); - return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC); + return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); } if ((N0.getOpcode() == ISD::XOR || @@ -1568,11 +1575,11 @@ assert(N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::XOR); // ((X^1)&1)^1 -> X & 1 - Val = DAG.getNode(ISD::AND, N0.getValueType(), + Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), N0.getOperand(0).getOperand(0), N0.getOperand(1)); } - return DAG.getSetCC(VT, Val, N1, + return DAG.getSetCC(dl, VT, Val, N1, Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); } } @@ -1592,15 +1599,17 @@ if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true // X >= C0 --> X > (C0-1) - return DAG.getSetCC(VT, N0, DAG.getConstant(C1-1, N1.getValueType()), - (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); + return DAG.getSetCC(dl, VT, N0, + DAG.getConstant(C1-1, N1.getValueType()), + (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); } if (Cond == ISD::SETLE || Cond == ISD::SETULE) { if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true // X <= C0 --> X < (C0+1) - return DAG.getSetCC(VT, N0, DAG.getConstant(C1+1, N1.getValueType()), - (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); + return DAG.getSetCC(dl, VT, N0, + DAG.getConstant(C1+1, N1.getValueType()), + (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); } if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) @@ -1614,19 +1623,21 @@ // Canonicalize setgt X, Min --> setne X, Min if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) - return DAG.getSetCC(VT, N0, N1, ISD::SETNE); + return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); // Canonicalize setlt X, Max --> setne X, Max if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) - return DAG.getSetCC(VT, N0, N1, ISD::SETNE); + return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); // If we have setult X, 1, turn it into seteq X, 0 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) - return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), - ISD::SETEQ); + return DAG.getSetCC(dl, VT, N0, + DAG.getConstant(MinVal, N0.getValueType()), + ISD::SETEQ); // If we have setugt X, Max-1, turn it into seteq X, Max else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) - return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), - ISD::SETEQ); + return DAG.getSetCC(dl, VT, N0, + DAG.getConstant(MaxVal, N0.getValueType()), + ISD::SETEQ); // If we have "setcc X, C0", check to see if we can shrink the immediate // by changing cc. @@ -1634,7 +1645,8 @@ // SETUGT X, SINTMAX -> SETLT X, 0 if (Cond == ISD::SETUGT && C1 == APInt::getSignedMaxValue(OperandBitSize)) - return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), + return DAG.getSetCC(dl, VT, N0, + DAG.getConstant(0, N1.getValueType()), ISD::SETLT); // SETULT X, SINTMIN -> SETGT X, -1 @@ -1643,7 +1655,7 @@ SDValue ConstMinusOne = DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), N1.getValueType()); - return DAG.getSetCC(VT, N0, ConstMinusOne, ISD::SETGT); + return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); } // Fold bit comparisons when we can. @@ -1656,7 +1668,7 @@ if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 // Perform the xform if the AND RHS is a single bit. if (isPowerOf2_64(AndRHS->getZExtValue())) { - return DAG.getNode(ISD::SRL, VT, N0, + return DAG.getNode(ISD::SRL, dl, VT, N0, DAG.getConstant(Log2_64(AndRHS->getZExtValue()), ShiftTy)); } @@ -1664,7 +1676,7 @@ // (X & 8) == 8 --> (X & 8) >> 3 // Perform the xform if C1 is a single bit. if (C1.isPowerOf2()) { - return DAG.getNode(ISD::SRL, VT, N0, + return DAG.getNode(ISD::SRL, dl, VT, N0, DAG.getConstant(C1.logBase2(), ShiftTy)); } } @@ -1672,12 +1684,12 @@ } } else if (isa(N0.getNode())) { // Ensure that the constant occurs on the RHS. - return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); + return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); } if (isa(N0.getNode())) { // Constant fold or commute setcc. - SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond); + SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); if (O.getNode()) return O; } else if (ConstantFPSDNode *CFP = dyn_cast(N1.getNode())) { // If the RHS of an FP comparison is a constant, simplify it away in @@ -1700,7 +1712,7 @@ // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to // materialize 0.0. if (Cond == ISD::SETO || Cond == ISD::SETUO) - return DAG.getSetCC(VT, N0, N0, Cond); + return DAG.getSetCC(dl, VT, N0, N0, Cond); } if (N0 == N1) { @@ -1716,7 +1728,7 @@ // if it is not already. ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; if (NewCond != Cond) - return DAG.getSetCC(VT, N0, N1, NewCond); + return DAG.getSetCC(dl, VT, N0, N1, NewCond); } if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && @@ -1726,15 +1738,17 @@ // Simplify (X+Y) == (X+Z) --> Y == Z if (N0.getOpcode() == N1.getOpcode()) { if (N0.getOperand(0) == N1.getOperand(0)) - return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); + return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); if (N0.getOperand(1) == N1.getOperand(1)) - return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); + return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); if (DAG.isCommutativeBinOp(N0.getOpcode())) { // If X op Y == Y op X, try other combinations. if (N0.getOperand(0) == N1.getOperand(1)) - return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); + return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), + Cond); if (N0.getOperand(1) == N1.getOperand(0)) - return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); + return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), + Cond); } } @@ -1742,7 +1756,7 @@ if (ConstantSDNode *LHSR = dyn_cast(N0.getOperand(1))) { // Turn (X+C1) == C2 --> X == C2-C1 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { - return DAG.getSetCC(VT, N0.getOperand(0), + return DAG.getSetCC(dl, VT, N0.getOperand(0), DAG.getConstant(RHSC->getAPIntValue()- LHSR->getAPIntValue(), N0.getValueType()), Cond); @@ -1754,7 +1768,7 @@ // performing the inversion. if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) return - DAG.getSetCC(VT, N0.getOperand(0), + DAG.getSetCC(dl, VT, N0.getOperand(0), DAG.getConstant(LHSR->getAPIntValue() ^ RHSC->getAPIntValue(), N0.getValueType()), @@ -1765,7 +1779,7 @@ if (ConstantSDNode *SUBC = dyn_cast(N0.getOperand(0))) { if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { return - DAG.getSetCC(VT, N0.getOperand(1), + DAG.getSetCC(dl, VT, N0.getOperand(1), DAG.getConstant(SUBC->getAPIntValue() - RHSC->getAPIntValue(), N0.getValueType()), @@ -1776,21 +1790,21 @@ // Simplify (X+Z) == X --> Z == 0 if (N0.getOperand(0) == N1) - return DAG.getSetCC(VT, N0.getOperand(1), + return DAG.getSetCC(dl, VT, N0.getOperand(1), DAG.getConstant(0, N0.getValueType()), Cond); if (N0.getOperand(1) == N1) { if (DAG.isCommutativeBinOp(N0.getOpcode())) - return DAG.getSetCC(VT, N0.getOperand(0), + return DAG.getSetCC(dl, VT, N0.getOperand(0), DAG.getConstant(0, N0.getValueType()), Cond); else if (N0.getNode()->hasOneUse()) { assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); // (Z-X) == X --> Z == X<<1 - SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), + SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1, DAG.getConstant(1, getShiftAmountTy())); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(SH.getNode()); - return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); + return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); } } } @@ -1799,20 +1813,20 @@ N1.getOpcode() == ISD::XOR) { // Simplify X == (X+Z) --> Z == 0 if (N1.getOperand(0) == N0) { - return DAG.getSetCC(VT, N1.getOperand(1), + return DAG.getSetCC(dl, VT, N1.getOperand(1), DAG.getConstant(0, N1.getValueType()), Cond); } else if (N1.getOperand(1) == N0) { if (DAG.isCommutativeBinOp(N1.getOpcode())) { - return DAG.getSetCC(VT, N1.getOperand(0), + return DAG.getSetCC(dl, VT, N1.getOperand(0), DAG.getConstant(0, N1.getValueType()), Cond); } else if (N1.getNode()->hasOneUse()) { assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); // X == (Z-X) --> X<<1 == Z - SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, + SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, DAG.getConstant(1, getShiftAmountTy())); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(SH.getNode()); - return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); + return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); } } } @@ -1823,7 +1837,7 @@ if (ValueHasAtMostOneBitSet(N1, DAG)) { Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); SDValue Zero = DAG.getConstant(0, N1.getValueType()); - return DAG.getSetCC(VT, N0, Zero, Cond); + return DAG.getSetCC(dl, VT, N0, Zero, Cond); } } if (N1.getOpcode() == ISD::AND) @@ -1831,7 +1845,7 @@ if (ValueHasAtMostOneBitSet(N0, DAG)) { Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); SDValue Zero = DAG.getConstant(0, N0.getValueType()); - return DAG.getSetCC(VT, N1, Zero, Cond); + return DAG.getSetCC(dl, VT, N1, Zero, Cond); } } } @@ -1842,46 +1856,46 @@ switch (Cond) { default: assert(0 && "Unknown integer setcc!"); case ISD::SETEQ: // X == Y -> ~(X^Y) - Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); - N0 = DAG.getNOT(DebugLoc::getUnknownLoc(), Temp, MVT::i1); + Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); + N0 = DAG.getNOT(dl, Temp, MVT::i1); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETNE: // X != Y --> (X^Y) - N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); + N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); break; case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y case ISD::SETULT: // X X == 0 & Y == 1 --> ~X & Y - Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N0, MVT::i1); + Temp = DAG.getNOT(dl, N0, MVT::i1); N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETLT: // X X == 1 & Y == 0 --> ~Y & X case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X - Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N1, MVT::i1); - N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); + Temp = DAG.getNOT(dl, N1, MVT::i1); + N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y - Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N0, MVT::i1); - N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); + Temp = DAG.getNOT(dl, N0, MVT::i1); + N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X - Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N1, MVT::i1); - N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); + Temp = DAG.getNOT(dl, N1, MVT::i1); + N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); break; } if (VT != MVT::i1) { if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(N0.getNode()); // FIXME: If running after legalize, we probably can't do this. - N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); + N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); } return N0; } @@ -2396,6 +2410,7 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, std::vector* Created) const { MVT VT = N->getValueType(0); + DebugLoc dl= N->getDebugLoc(); // Check to see if we can do this. // FIXME: We should be more aggressive here. @@ -2409,40 +2424,40 @@ // FIXME: We should support doing a MUL in a wider type SDValue Q; if (isOperationLegalOrCustom(ISD::MULHS, VT)) - Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), + Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), DAG.getConstant(magics.m, VT)); else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) - Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT), + Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), N->getOperand(0), DAG.getConstant(magics.m, VT)).getNode(), 1); else return SDValue(); // No mulhs or equvialent // If d > 0 and m < 0, add the numerator if (d.isStrictlyPositive() && magics.m.isNegative()) { - Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); + Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); if (Created) Created->push_back(Q.getNode()); } // If d < 0 and m > 0, subtract the numerator. if (d.isNegative() && magics.m.isStrictlyPositive()) { - Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); + Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); if (Created) Created->push_back(Q.getNode()); } // Shift right algebraic if shift value is nonzero if (magics.s > 0) { - Q = DAG.getNode(ISD::SRA, VT, Q, + Q = DAG.getNode(ISD::SRA, dl, VT, Q, DAG.getConstant(magics.s, getShiftAmountTy())); if (Created) Created->push_back(Q.getNode()); } // Extract the sign bit and add it to the quotient SDValue T = - DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, + DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, getShiftAmountTy())); if (Created) Created->push_back(T.getNode()); - return DAG.getNode(ISD::ADD, VT, Q, T); + return DAG.getNode(ISD::ADD, dl, VT, Q, T); } /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, @@ -2452,6 +2467,7 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, std::vector* Created) const { MVT VT = N->getValueType(0); + DebugLoc dl = N->getDebugLoc(); // Check to see if we can do this. // FIXME: We should be more aggressive here. @@ -2467,10 +2483,10 @@ // FIXME: We should support doing a MUL in a wider type SDValue Q; if (isOperationLegalOrCustom(ISD::MULHU, VT)) - Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), + Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), DAG.getConstant(magics.m, VT)); else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) - Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT), + Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), N->getOperand(0), DAG.getConstant(magics.m, VT)).getNode(), 1); else @@ -2481,20 +2497,20 @@ if (magics.a == 0) { assert(magics.s < N1C->getAPIntValue().getBitWidth() && "We shouldn't generate an undefined shift!"); - return DAG.getNode(ISD::SRL, VT, Q, + return DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(magics.s, getShiftAmountTy())); } else { - SDValue NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); + SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); if (Created) Created->push_back(NPQ.getNode()); - NPQ = DAG.getNode(ISD::SRL, VT, NPQ, + NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, DAG.getConstant(1, getShiftAmountTy())); if (Created) Created->push_back(NPQ.getNode()); - NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); + NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); if (Created) Created->push_back(NPQ.getNode()); - return DAG.getNode(ISD::SRL, VT, NPQ, + return DAG.getNode(ISD::SRL, dl, VT, NPQ, DAG.getConstant(magics.s-1, getShiftAmountTy())); } } From isanbard at gmail.com Mon Feb 2 18:55:04 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 03 Feb 2009 00:55:04 -0000 Subject: [llvm-commits] [llvm] r63584 - in /llvm/trunk: include/llvm/CodeGen/FastISel.h include/llvm/CodeGen/MachineFunction.h include/llvm/CodeGen/MachineInstrBuilder.h lib/CodeGen/MachineFunction.cpp lib/CodeGen/SelectionDAG/FastISel.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp lib/Target/ARM/ARMInstrInfo.cpp lib/Target/X86/X86InstrInfo.cpp Message-ID: <200902030055.n130t563028031@zion.cs.uiuc.edu> Author: void Date: Mon Feb 2 18:55:04 2009 New Revision: 63584 URL: http://llvm.org/viewvc/llvm-project?rev=63584&view=rev Log: Create DebugLoc information in FastISel. Several temporary methods were created. Specifically, those BuildMIs which use "DebugLoc::getUnknownLoc()". I'll remove them soon. Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h llvm/trunk/include/llvm/CodeGen/MachineFunction.h llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h llvm/trunk/lib/CodeGen/MachineFunction.cpp llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=63584&r1=63583&r2=63584&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/FastISel.h (original) +++ llvm/trunk/include/llvm/CodeGen/FastISel.h Mon Feb 2 18:55:04 2009 @@ -16,6 +16,7 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallSet.h" +#include "llvm/CodeGen/DebugLoc.h" #include "llvm/CodeGen/SelectionDAGNodes.h" namespace llvm { @@ -55,28 +56,33 @@ MachineRegisterInfo &MRI; MachineFrameInfo &MFI; MachineConstantPool &MCP; + DebugLoc DL; const TargetMachine &TM; const TargetData &TD; const TargetInstrInfo &TII; const TargetLowering &TLI; public: - /// startNewBlock - Set the current block, to which generated - /// machine instructions will be appended, and clear the local - /// CSE map. + /// startNewBlock - Set the current block to which generated machine + /// instructions will be appended, and clear the local CSE map. /// void startNewBlock(MachineBasicBlock *mbb) { setCurrentBlock(mbb); LocalValueMap.clear(); } - /// setCurrentBlock - Set the current block, to which generated - /// machine instructions will be appended. + /// setCurrentBlock - Set the current block to which generated machine + /// instructions will be appended. /// void setCurrentBlock(MachineBasicBlock *mbb) { MBB = mbb; } + /// setCurDebugLoc - Set the current debug location information, which is used + /// when creating a machine instruction. + /// + void setCurDebugLoc(DebugLoc dl) { DL = dl; } + /// SelectInstruction - Do "fast" instruction selection for the given /// LLVM IR instruction, and append generated machine instructions to /// the current block. Return true if selection was successful. Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=63584&r1=63583&r2=63584&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Mon Feb 2 18:55:04 2009 @@ -286,6 +286,7 @@ /// of `new MachineInstr'. /// MachineInstr *CreateMachineInstr(const TargetInstrDesc &TID, + DebugLoc DL, bool NoImp = false); /// CloneMachineInstr - Create a new MachineInstr which is a copy of the Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=63584&r1=63583&r2=63584&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Mon Feb 2 18:55:04 2009 @@ -100,16 +100,31 @@ /// inline MachineInstrBuilder BuildMI(MachineFunction &MF, const TargetInstrDesc &TID) { - return MachineInstrBuilder(MF.CreateMachineInstr(TID)); + return MachineInstrBuilder(MF.CreateMachineInstr(TID, + DebugLoc::getUnknownLoc())); +} +inline MachineInstrBuilder BuildMI(MachineFunction &MF, + DebugLoc DL, + const TargetInstrDesc &TID) { + return MachineInstrBuilder(MF.CreateMachineInstr(TID, DL)); } /// BuildMI - This version of the builder sets up the first operand as a /// destination virtual register. /// -inline MachineInstrBuilder BuildMI(MachineFunction &MF, - const TargetInstrDesc &TID, - unsigned DestReg) { - return MachineInstrBuilder(MF.CreateMachineInstr(TID)).addReg(DestReg, true); +inline MachineInstrBuilder BuildMI(MachineFunction &MF, + const TargetInstrDesc &TID, + unsigned DestReg) { + return MachineInstrBuilder(MF.CreateMachineInstr(TID, + DebugLoc::getUnknownLoc())) + .addReg(DestReg, true); +} +inline MachineInstrBuilder BuildMI(MachineFunction &MF, + DebugLoc DL, + const TargetInstrDesc &TID, + unsigned DestReg) { + return MachineInstrBuilder(MF.CreateMachineInstr(TID, DL)) + .addReg(DestReg, true); } /// BuildMI - This version of the builder inserts the newly-built @@ -120,7 +135,17 @@ MachineBasicBlock::iterator I, const TargetInstrDesc &TID, unsigned DestReg) { - MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID); + MachineInstr *MI = + BB.getParent()->CreateMachineInstr(TID, DebugLoc::getUnknownLoc()); + BB.insert(I, MI); + return MachineInstrBuilder(MI).addReg(DestReg, true); +} +inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, + MachineBasicBlock::iterator I, + DebugLoc DL, + const TargetInstrDesc &TID, + unsigned DestReg) { + MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID, DL); BB.insert(I, MI); return MachineInstrBuilder(MI).addReg(DestReg, true); } @@ -132,7 +157,16 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const TargetInstrDesc &TID) { - MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID); + MachineInstr *MI = + BB.getParent()->CreateMachineInstr(TID, DebugLoc::getUnknownLoc()); + BB.insert(I, MI); + return MachineInstrBuilder(MI); +} +inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, + MachineBasicBlock::iterator I, + DebugLoc DL, + const TargetInstrDesc &TID) { + MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID, DL); BB.insert(I, MI); return MachineInstrBuilder(MI); } @@ -145,6 +179,11 @@ const TargetInstrDesc &TID) { return BuildMI(*BB, BB->end(), TID); } +inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, + DebugLoc DL, + const TargetInstrDesc &TID) { + return BuildMI(*BB, BB->end(), DL, TID); +} /// BuildMI - This version of the builder inserts the newly-built /// instruction at the end of the given MachineBasicBlock, and sets up the first @@ -155,6 +194,12 @@ unsigned DestReg) { return BuildMI(*BB, BB->end(), TID, DestReg); } +inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, + DebugLoc DL, + const TargetInstrDesc &TID, + unsigned DestReg) { + return BuildMI(*BB, BB->end(), DL, TID, DestReg); +} } // End llvm namespace Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=63584&r1=63583&r2=63584&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Mon Feb 2 18:55:04 2009 @@ -192,9 +192,10 @@ /// of `new MachineInstr'. /// MachineInstr * -MachineFunction::CreateMachineInstr(const TargetInstrDesc &TID, bool NoImp) { +MachineFunction::CreateMachineInstr(const TargetInstrDesc &TID, + DebugLoc DL, bool NoImp) { return new (InstructionRecycler.Allocate(Allocator)) - MachineInstr(TID, NoImp); + MachineInstr(TID, DL, NoImp); } /// CloneMachineInstr - Create a new MachineInstr which is a copy of the Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=63584&r1=63583&r2=63584&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Feb 2 18:55:04 2009 @@ -114,7 +114,7 @@ Reg = LocalValueMap[CE]; } else if (isa(V)) { Reg = createResultReg(TLI.getRegClassFor(VT)); - BuildMI(MBB, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg); + BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg); } // If target-independent code couldn't handle the value, give target-specific @@ -324,8 +324,10 @@ unsigned Line = SPI->getLine(); unsigned Col = SPI->getColumn(); unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile); + unsigned Idx = MF.getOrCreateDebugLocID(SrcFile, Line, Col); + setCurDebugLoc(DebugLoc::get(Idx)); const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); - BuildMI(MBB, II).addImm(ID); + BuildMI(MBB, DL, II).addImm(ID); } return true; } @@ -335,7 +337,7 @@ unsigned ID = DW->RecordRegionStart(cast(RSI->getContext())); const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); - BuildMI(MBB, II).addImm(ID); + BuildMI(MBB, DL, II).addImm(ID); } return true; } @@ -345,7 +347,7 @@ unsigned ID = DW->RecordRegionEnd(cast(REI->getContext())); const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); - BuildMI(MBB, II).addImm(ID); + BuildMI(MBB, DL, II).addImm(ID); } return true; } @@ -353,23 +355,28 @@ if (!DW) return true; DbgFuncStartInst *FSI = cast(I); Value *SP = FSI->getSubprogram(); + if (DW->ValidDebugInfo(SP)) { - // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is - // what (most?) gdb expects. + // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what + // (most?) gdb expects. DISubprogram Subprogram(cast(SP)); DICompileUnit CompileUnit = Subprogram.getCompileUnit(); unsigned SrcFile = DW->RecordSource(CompileUnit.getDirectory(), CompileUnit.getFilename()); + // Record the source line but does not create a label for the normal // function start. It will be emitted at asm emission time. However, // create a label if this is a beginning of inlined function. - unsigned LabelID = - DW->RecordSourceLine(Subprogram.getLineNumber(), 0, SrcFile); + unsigned Line = Subprogram.getLineNumber(); + unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile); + setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0))); + if (DW->getRecordSourceLineCount() != 1) { const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); - BuildMI(MBB, II).addImm(LabelID); + BuildMI(MBB, DL, II).addImm(LabelID); } } + return true; } case Intrinsic::dbg_declare: { @@ -393,7 +400,7 @@ // Build the DECLARE instruction. const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE); - BuildMI(MBB, II).addFrameIndex(FI).addGlobalAddress(GV); + BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV); } return true; } @@ -830,7 +837,7 @@ unsigned ResultReg = createResultReg(RC); const TargetInstrDesc &II = TII.get(MachineInstOpcode); - BuildMI(MBB, II, ResultReg); + BuildMI(MBB, DL, II, ResultReg); return ResultReg; } @@ -841,9 +848,9 @@ const TargetInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) - BuildMI(MBB, II, ResultReg).addReg(Op0); + BuildMI(MBB, DL, II, ResultReg).addReg(Op0); else { - BuildMI(MBB, II).addReg(Op0); + BuildMI(MBB, DL, II).addReg(Op0); bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, II.ImplicitDefs[0], RC, RC); if (!InsertedCopy) @@ -860,9 +867,9 @@ const TargetInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) - BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1); + BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1); else { - BuildMI(MBB, II).addReg(Op0).addReg(Op1); + BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1); bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, II.ImplicitDefs[0], RC, RC); if (!InsertedCopy) @@ -878,9 +885,9 @@ const TargetInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) - BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm); + BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm); else { - BuildMI(MBB, II).addReg(Op0).addImm(Imm); + BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm); bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, II.ImplicitDefs[0], RC, RC); if (!InsertedCopy) @@ -896,9 +903,9 @@ const TargetInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) - BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm); + BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm); else { - BuildMI(MBB, II).addReg(Op0).addFPImm(FPImm); + BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm); bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, II.ImplicitDefs[0], RC, RC); if (!InsertedCopy) @@ -914,9 +921,9 @@ const TargetInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) - BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); + BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); else { - BuildMI(MBB, II).addReg(Op0).addReg(Op1).addImm(Imm); + BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm); bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, II.ImplicitDefs[0], RC, RC); if (!InsertedCopy) @@ -932,9 +939,9 @@ const TargetInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) - BuildMI(MBB, II, ResultReg).addImm(Imm); + BuildMI(MBB, DL, II, ResultReg).addImm(Imm); else { - BuildMI(MBB, II).addImm(Imm); + BuildMI(MBB, DL, II).addImm(Imm); bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, II.ImplicitDefs[0], RC, RC); if (!InsertedCopy) @@ -951,9 +958,9 @@ const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG); if (II.getNumDefs() >= 1) - BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx); + BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx); else { - BuildMI(MBB, II).addReg(Op0).addImm(Idx); + BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx); bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, II.ImplicitDefs[0], RC, RC); if (!InsertedCopy) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63584&r1=63583&r2=63584&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon Feb 2 18:55:04 2009 @@ -3884,14 +3884,16 @@ DICompileUnit CompileUnit = Subprogram.getCompileUnit(); unsigned SrcFile = DW->RecordSource(CompileUnit.getDirectory(), CompileUnit.getFilename()); + // Record the source line but does not create a label for the normal // function start. It will be emitted at asm emission time. However, // create a label if this is a beginning of inlined function. unsigned Line = Subprogram.getLineNumber(); - unsigned LabelID = - DW->RecordSourceLine(Line, 0, SrcFile); + unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile); + if (DW->getRecordSourceLineCount() != 1) DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); + setCurDebugLoc(DebugLoc::get(DAG.getMachineFunction(). getOrCreateDebugLocID(SrcFile, Line, 0))); } Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=63584&r1=63583&r2=63584&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Mon Feb 2 18:55:04 2009 @@ -649,7 +649,7 @@ return false; bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; - MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP)); + MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc()); MBB.insert(MI, PopMI); for (unsigned i = CSI.size(); i != 0; --i) { unsigned Reg = CSI[i-1].getReg(); Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=63584&r1=63583&r2=63584&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Feb 2 18:55:04 2009 @@ -1938,9 +1938,11 @@ static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, const SmallVectorImpl &MOs, - MachineInstr *MI, const TargetInstrInfo &TII) { + MachineInstr *MI, + const TargetInstrInfo &TII) { // Create the base instruction with the memory operand as the first part. - MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true); + MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), + MI->getDebugLoc(), true); MachineInstrBuilder MIB(NewMI); unsigned NumAddrOps = MOs.size(); for (unsigned i = 0; i != NumAddrOps; ++i) @@ -1965,7 +1967,8 @@ unsigned Opcode, unsigned OpNo, const SmallVectorImpl &MOs, MachineInstr *MI, const TargetInstrInfo &TII) { - MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true); + MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), + MI->getDebugLoc(), true); MachineInstrBuilder MIB(NewMI); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { @@ -2298,7 +2301,7 @@ } // Emit the data processing instruction. - MachineInstr *DataMI = MF.CreateMachineInstr(TID, true); + MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true); MachineInstrBuilder MIB(DataMI); if (FoldedStore) From gohman at apple.com Mon Feb 2 18:57:59 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 2 Feb 2009 16:57:59 -0800 Subject: [llvm-commits] [llvm] r63582 - /llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c In-Reply-To: <200902030035.n130ZCtY027381@zion.cs.uiuc.edu> References: <200902030035.n130ZCtY027381@zion.cs.uiuc.edu> Message-ID: <0170FA28-76DB-409A-9802-C736372F9C8E@apple.com> On Feb 2, 2009, at 4:35 PM, Bill Wendling wrote: > Author: void > Date: Mon Feb 2 18:35:11 2009 > New Revision: 63582 > > URL: http://llvm.org/viewvc/llvm-project?rev=63582&view=rev > Log: > It fails on Linux. XFAIL that machine. Hi Bill, this test now XPASSes on an x86-64 Ubuntu box. This test and test/FrontendC/x86-64-red-zone.c have needs that aren't adaquately met by the current testing infrastructure. It's been suggested that we just remove these tests, to avoid the trouble. I've been hoping to find a better solution, though none has surfaced so far. Dan From isanbard at gmail.com Mon Feb 2 19:02:39 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 03 Feb 2009 01:02:39 -0000 Subject: [llvm-commits] [llvm] r63585 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp Message-ID: <200902030102.n1312di1028288@zion.cs.uiuc.edu> Author: void Date: Mon Feb 2 19:02:39 2009 New Revision: 63585 URL: http://llvm.org/viewvc/llvm-project?rev=63585&view=rev Log: Propagate debug loc info during SDNode -> machine instr creation. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp?rev=63585&r1=63584&r2=63585&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp Mon Feb 2 19:02:39 2009 @@ -219,7 +219,7 @@ const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); VReg = MRI.createVirtualRegister(RC); } - BuildMI(BB, TII->get(TargetInstrInfo::IMPLICIT_DEF), VReg); + BuildMI(BB, Op.getDebugLoc(), TII->get(TargetInstrInfo::IMPLICIT_DEF),VReg); return VReg; } @@ -359,7 +359,8 @@ unsigned SubIdx = cast(Node->getOperand(1))->getZExtValue(); // Create the extract_subreg machine instruction. - MachineInstr *MI = BuildMI(MF, TII->get(TargetInstrInfo::EXTRACT_SUBREG)); + MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(), + TII->get(TargetInstrInfo::EXTRACT_SUBREG)); // Figure out the register class to create for the destreg. const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getValueType(0)); @@ -401,7 +402,7 @@ } // Create the insert_subreg or subreg_to_reg machine instruction. - MachineInstr *MI = BuildMI(MF, TII->get(Opc)); + MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(), TII->get(Opc)); MI->addOperand(MachineOperand::CreateReg(VRBase, true)); // If creating a subreg_to_reg, then the first input operand @@ -458,7 +459,7 @@ #endif // Create the new machine instruction. - MachineInstr *MI = BuildMI(MF, II); + MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(), II); // Add result register values for things that are defined by this // instruction. @@ -479,8 +480,9 @@ // specific inserter which may returns a new basic block. BB = TLI->EmitInstrWithCustomInserter(MI, BB); Begin = End = BB->end(); - } else + } else { BB->insert(End, MI); + } // Additional results must be an physical register def. if (HasPhysRegOuts) { @@ -543,7 +545,8 @@ --NumOps; // Ignore the flag operand. // Create the inline asm machine instruction. - MachineInstr *MI = BuildMI(MF, TII->get(TargetInstrInfo::INLINEASM)); + MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(), + TII->get(TargetInstrInfo::INLINEASM)); // Add the asm string as an external symbol operand. const char *AsmStr = From isanbard at gmail.com Mon Feb 2 19:08:52 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 2 Feb 2009 17:08:52 -0800 Subject: [llvm-commits] [llvm] r63582 - /llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c In-Reply-To: <0170FA28-76DB-409A-9802-C736372F9C8E@apple.com> References: <200902030035.n130ZCtY027381@zion.cs.uiuc.edu> <0170FA28-76DB-409A-9802-C736372F9C8E@apple.com> Message-ID: <16e5fdf90902021708v5aeb43cbjb244242d4f45b04c@mail.gmail.com> On Mon, Feb 2, 2009 at 4:57 PM, Dan Gohman wrote: > > On Feb 2, 2009, at 4:35 PM, Bill Wendling wrote: > >> Author: void >> Date: Mon Feb 2 18:35:11 2009 >> New Revision: 63582 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=63582&view=rev >> Log: >> It fails on Linux. XFAIL that machine. > > Hi Bill, this test now XPASSes on an x86-64 Ubuntu box. > > This test and test/FrontendC/x86-64-red-zone.c have needs that > aren't adaquately met by the current testing infrastructure. > It's been suggested that we just remove these tests, to avoid > the trouble. I've been hoping to find a better solution, > though none has surfaced so far. > Oy. Well, if we can't get all of the platforms to agree, then maybe they should be removed? At least until a solution is found. Otherwise, it's just needless noise from the buildbots... -bw From sabre at nondot.org Mon Feb 2 19:13:52 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Feb 2009 01:13:52 -0000 Subject: [llvm-commits] [llvm] r63587 - /llvm/trunk/test/Transforms/ScalarRepl/badarray.ll Message-ID: <200902030113.n131Dqa2028708@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 2 19:13:52 2009 New Revision: 63587 URL: http://llvm.org/viewvc/llvm-project?rev=63587&view=rev Log: this test produces an undefined value, we don't care what it is, but we do want the alloca promoted. Modified: llvm/trunk/test/Transforms/ScalarRepl/badarray.ll Modified: llvm/trunk/test/Transforms/ScalarRepl/badarray.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/badarray.ll?rev=63587&r1=63586&r2=63587&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/badarray.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/badarray.ll Mon Feb 2 19:13:52 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | opt -scalarrepl -instcombine | llvm-dis | grep {ret i32 0} +; RUN: llvm-as < %s | opt -scalarrepl -instcombine | llvm-dis | not grep alloca define i32 @test() { %X = alloca [4 x i32] ; <[4 x i32]*> [#uses=1] From gohman at apple.com Mon Feb 2 19:16:56 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 2 Feb 2009 17:16:56 -0800 Subject: [llvm-commits] Patch: PPC64 subregister moves In-Reply-To: References: Message-ID: On Jan 29, 2009, at 11:36 PM, Burke, Max wrote: > This attempts to reduce the number of emitted OR instructions used to > move data in and out of subregisters on the PPC64 target. We've > noticed > what looks like many extraneous register moves which in some cases are > harmless, others which may have unintended, though minor, side effects > (ie, mr 30, 30 blocking Cell PPE hardware thread at dispatch for 12 > cycles; mr 3, 3 changing the current hardware thread priority to > high). > _______________________________________________ I'm not very familiar with PowerPC, but this patch seems like a reasonably good idea to me. I do have a few comments on it. In this change: def : Pat<(i64 (zext GPRC:$in)), - (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>; + (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, ppc_subreg_32bit), 0, 32)>; For a zext, if this is really what the hardware provides, this should use SUBREG_TO_REG with an (i64 0) for the first operand. See how this is done on x86-64, for example. In the *RegisterInfo.td file, registers that have subregs should be declared with RegisterWithSubRegs, instead of just Register. This may require changing some of the PPC-specific code at the top of the file. Dan From clattner at apple.com Mon Feb 2 19:20:53 2009 From: clattner at apple.com (Chris Lattner) Date: Mon, 2 Feb 2009 17:20:53 -0800 Subject: [llvm-commits] [llvm] r63582 - /llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c In-Reply-To: <0170FA28-76DB-409A-9802-C736372F9C8E@apple.com> References: <200902030035.n130ZCtY027381@zion.cs.uiuc.edu> <0170FA28-76DB-409A-9802-C736372F9C8E@apple.com> Message-ID: On Feb 2, 2009, at 4:57 PM, Dan Gohman wrote: > > On Feb 2, 2009, at 4:35 PM, Bill Wendling wrote: > >> Author: void >> Date: Mon Feb 2 18:35:11 2009 >> New Revision: 63582 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=63582&view=rev >> Log: >> It fails on Linux. XFAIL that machine. > > Hi Bill, this test now XPASSes on an x86-64 Ubuntu box. > > This test and test/FrontendC/x86-64-red-zone.c have needs that > aren't adaquately met by the current testing infrastructure. > It's been suggested that we just remove these tests, to avoid > the trouble. I've been hoping to find a better solution, > though none has surfaced so far. Yes, I'd just remove it. -Chris From gohman at apple.com Mon Feb 2 19:28:32 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 03 Feb 2009 01:28:32 -0000 Subject: [llvm-commits] [llvm] r63589 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/BasicAliasAnalysis.cpp Message-ID: <200902030128.n131SXHR029523@zion.cs.uiuc.edu> Author: djg Date: Mon Feb 2 19:28:32 2009 New Revision: 63589 URL: http://llvm.org/viewvc/llvm-project?rev=63589&view=rev Log: Move isIdentifiedObject and isNoAliasCall into AliasAnalysis.cpp since they are useful to analyses other than BasicAliasAnalysis.cpp. Include the full comment for isIdentifiedObject in the header file. Thanks to Chris for suggeseting this. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h llvm/trunk/lib/Analysis/AliasAnalysis.cpp llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=63589&r1=63588&r2=63589&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Mon Feb 2 19:28:32 2009 @@ -345,8 +345,16 @@ } }; +/// isNoAliasCall - Return true if this pointer is returned by a noalias +/// function. +bool isNoAliasCall(const Value *V); + /// isIdentifiedObject - Return true if this pointer refers to a distinct and -/// identifiable object. +/// identifiable object. This returns true for: +/// Global Variables and Functions +/// Allocas and Mallocs +/// ByVal and NoAlias Arguments +/// NoAlias returns /// bool isIdentifiedObject(const Value *V); Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=63589&r1=63588&r2=63589&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Mon Feb 2 19:28:32 2009 @@ -207,6 +207,30 @@ return false; } +/// isNoAliasCall - Return true if this pointer is returned by a noalias +/// function. +bool llvm::isNoAliasCall(const Value *V) { + if (isa(V) || isa(V)) + return CallSite(const_cast(cast(V))) + .paramHasAttr(0, Attribute::NoAlias); + return false; +} + +/// isIdentifiedObject - Return true if this pointer refers to a distinct and +/// identifiable object. This returns true for: +/// Global Variables and Functions +/// Allocas and Mallocs +/// ByVal and NoAlias Arguments +/// NoAlias returns +/// +bool llvm::isIdentifiedObject(const Value *V) { + if (isa(V) || isa(V) || isNoAliasCall(V)) + return true; + if (const Argument *A = dyn_cast(V)) + return A->hasNoAliasAttr() || A->hasByValAttr(); + return false; +} + // Because of the way .a files work, we must force the BasicAA implementation to // be pulled in if the AliasAnalysis classes are pulled in. Otherwise we run // the risk of AliasAnalysis being used, but the default implementation not Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=63589&r1=63588&r2=63589&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Mon Feb 2 19:28:32 2009 @@ -64,30 +64,6 @@ return V; } -/// isNoAliasCall - Return true if this pointer is returned by a noalias -/// function. -static bool isNoAliasCall(const Value *V) { - if (isa(V) || isa(V)) - return CallSite(const_cast(cast(V))) - .paramHasAttr(0, Attribute::NoAlias); - return false; -} - -/// isIdentifiedObject - Return true if this pointer refers to a distinct and -/// identifiable object. This returns true for: -/// Global Variables and Functions -/// Allocas and Mallocs -/// ByVal and NoAlias Arguments -/// NoAlias returns -/// -bool llvm::isIdentifiedObject(const Value *V) { - if (isa(V) || isa(V) || isNoAliasCall(V)) - return true; - if (const Argument *A = dyn_cast(V)) - return A->hasNoAliasAttr() || A->hasByValAttr(); - return false; -} - /// isKnownNonNull - Return true if we know that the specified value is never /// null. static bool isKnownNonNull(const Value *V) { From sabre at nondot.org Mon Feb 2 19:30:10 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Feb 2009 01:30:10 -0000 Subject: [llvm-commits] [llvm] r63590 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/CodeGen/X86/vec_ins_extract.ll test/Transforms/ScalarRepl/vector_promote.ll Message-ID: <200902030130.n131UASH029601@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 2 19:30:09 2009 New Revision: 63590 URL: http://llvm.org/viewvc/llvm-project?rev=63590&view=rev Log: rearrange how SRoA handles promotion of allocas to vectors. With the new world order, it can handle cases where the first store into the alloca is an element of the vector, instead of requiring the first analyzed store to have the vector type itself. This allows us to un-xfail test/CodeGen/X86/vec_ins_extract.ll. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/trunk/test/CodeGen/X86/vec_ins_extract.ll llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=63590&r1=63589&r2=63590&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Mon Feb 2 19:30:09 2009 @@ -125,8 +125,8 @@ void RewriteLoadUserOfWholeAlloca(LoadInst *LI, AllocationInst *AI, SmallVector &NewElts); - bool CanConvertToScalar(Value *V, bool &IsNotTrivial, const Type *&ResTy, - uint64_t Offset); + bool CanConvertToScalar(Value *V, bool &IsNotTrivial, const Type *&VecTy, + uint64_t Offset, unsigned AllocaSize); void ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, uint64_t Offset); Value *ConvertUsesOfLoadToScalar(LoadInst *LI, AllocaInst *NewAI, uint64_t Offset); @@ -223,17 +223,38 @@ AI->eraseFromParent(); continue; } + + // If this alloca is impossible for us to promote, reject it early. + if (AI->isArrayAllocation() || !AI->getAllocatedType()->isSized()) + continue; + + // Check to see if this allocation is only modified by a memcpy/memmove from + // a constant global. If this is the case, we can change all users to use + // the constant global instead. This is commonly produced by the CFE by + // constructs like "void foo() { int A[] = {1,2,3,4,5,6,7,8,9...}; }" if 'A' + // is only subsequently read. + if (Instruction *TheCopy = isOnlyCopiedFromConstantGlobal(AI)) { + DOUT << "Found alloca equal to global: " << *AI; + DOUT << " memcpy = " << *TheCopy; + Constant *TheSrc = cast(TheCopy->getOperand(2)); + AI->replaceAllUsesWith(ConstantExpr::getBitCast(TheSrc, AI->getType())); + TheCopy->eraseFromParent(); // Don't mutate the global. + AI->eraseFromParent(); + ++NumGlobals; + Changed = true; + continue; + } // Check to see if we can perform the core SROA transformation. We cannot // transform the allocation instruction if it is an array allocation // (allocations OF arrays are ok though), and an allocation of a scalar // value cannot be decomposed at all. - if (!AI->isArrayAllocation() && - (isa(AI->getAllocatedType()) || + uint64_t AllocaSize = TD->getTypePaddedSize(AI->getAllocatedType()); + + if ((isa(AI->getAllocatedType()) || isa(AI->getAllocatedType())) && - AI->getAllocatedType()->isSized() && - // Do not promote any struct whose size is larger than "128" bytes. - TD->getTypePaddedSize(AI->getAllocatedType()) < SRThreshold && + // Do not promote any struct whose size is too big. + AllocaSize < SRThreshold && // Do not promote any struct into more than "32" separate vars. getNumSAElements(AI->getAllocatedType()) < SRThreshold/4) { // Check that all of the users of the allocation are capable of being @@ -251,25 +272,6 @@ continue; } } - - // Check to see if this allocation is only modified by a memcpy/memmove from - // a constant global. If this is the case, we can change all users to use - // the constant global instead. This is commonly produced by the CFE by - // constructs like "void foo() { int A[] = {1,2,3,4,5,6,7,8,9...}; }" if 'A' - // is only subsequently read. - if (Instruction *TheCopy = isOnlyCopiedFromConstantGlobal(AI)) { - DOUT << "Found alloca equal to global: " << *AI; - DOUT << " memcpy = " << *TheCopy; - Constant *TheSrc = cast(TheCopy->getOperand(2)); - AI->replaceAllUsesWith(ConstantExpr::getBitCast(TheSrc, AI->getType())); - TheCopy->eraseFromParent(); // Don't mutate the global. - AI->eraseFromParent(); - ++NumGlobals; - Changed = true; - continue; - } - - // If we can turn this aggregate value (potentially with casts) into a // simple scalar value that can be mem2reg'd into a register value. @@ -278,23 +280,32 @@ // that we can't just check based on the type: the alloca may be of an i32 // but that has pointer arithmetic to set byte 3 of it or something. bool IsNotTrivial = false; - const Type *ActualTy = 0; - if (CanConvertToScalar(AI, IsNotTrivial, ActualTy, 0)) - if (IsNotTrivial && ActualTy && - TD->getTypeSizeInBits(ActualTy) < SRThreshold*8) { - DOUT << "CONVERT TO SCALAR: " << *AI << " TYPE = " << *ActualTy <<"\n"; - ++NumConverted; + const Type *VectorTy = 0; + if (CanConvertToScalar(AI, IsNotTrivial, VectorTy, + 0, unsigned(AllocaSize)) && IsNotTrivial) { + AllocaInst *NewAI; + if (VectorTy && isa(VectorTy)) { + DOUT << "CONVERT TO VECTOR: " << *AI << " TYPE = " << *VectorTy <<"\n"; - // Create and insert the alloca. - AllocaInst *NewAI = new AllocaInst(ActualTy, 0, AI->getName(), - AI->getParent()->begin()); + // Create and insert the vector alloca. + NewAI = new AllocaInst(VectorTy, 0, "", AI->getParent()->begin()); + ConvertUsesToScalar(AI, NewAI, 0); + } else { + DOUT << "CONVERT TO SCALAR INTEGER: " << *AI << "\n"; + + // Create and insert the integer alloca. + const Type *NewTy = IntegerType::get(AllocaSize*8); + NewAI = new AllocaInst(NewTy, 0, "", AI->getParent()->begin()); ConvertUsesToScalar(AI, NewAI, 0); - AI->eraseFromParent(); - Changed = true; - continue; } + NewAI->takeName(AI); + AI->eraseFromParent(); + ++NumConverted; + Changed = true; + continue; + } - // Otherwise, couldn't process this. + // Otherwise, couldn't process this alloca. } return Changed; @@ -1171,58 +1182,56 @@ /// 2) A fully general blob of memory, which we turn into some (potentially /// large) integer type with extract and insert operations where the loads /// and stores would mutate the memory. -static void MergeInType(const Type *In, uint64_t Offset, const Type *&Accum, - const TargetData &TD) { - // If this is our first type, just use it. - if ((Accum == 0 && Offset == 0) || In == Type::VoidTy || - // Or if this is a same type, keep it. - (In == Accum && Offset == 0)) { - Accum = In; - return; - } - - // Merging something like i32 into offset 8 means that a "field" is merged in - // before the basic type is. Make sure to consider the offset below. - if (Accum == 0) - Accum = Type::Int8Ty; - - if (const VectorType *VATy = dyn_cast(Accum)) { - if (VATy->getElementType() == In && - Offset % TD.getTypePaddedSize(In) == 0 && - Offset < TD.getTypePaddedSize(VATy)) - return; // Accum is a vector, and we are accessing an element: ok. - if (const VectorType *VInTy = dyn_cast(In)) - if (VInTy->getBitWidth() == VATy->getBitWidth() && Offset == 0) - return; // Two vectors of the same size: keep either one of them. - } - - if (const VectorType *VInTy = dyn_cast(In)) { - // In is a vector, and we are accessing an element: keep V. - if (VInTy->getElementType() == Accum && - Offset % TD.getTypePaddedSize(Accum) == 0 && - Offset < TD.getTypePaddedSize(VInTy)) { - Accum = VInTy; - return; +static void MergeInType(const Type *In, uint64_t Offset, const Type *&VecTy, + unsigned AllocaSize, const TargetData &TD) { + // If this could be contributing to a vector, analyze it. + if (VecTy != Type::VoidTy) { // either null or a vector type. + + // If the In type is a vector that is the same size as the alloca, see if it + // matches the existing VecTy. + if (const VectorType *VInTy = dyn_cast(In)) { + if (VInTy->getBitWidth()/8 == AllocaSize && Offset == 0) { + // If we're storing/loading a vector of the right size, allow it as a + // vector. If this the first vector we see, remember the type so that + // we know the element size. + if (VecTy == 0) + VecTy = VInTy; + return; + } + } else if (In == Type::FloatTy || In == Type::DoubleTy || + (isa(In) && In->getPrimitiveSizeInBits() >= 8 && + isPowerOf2_32(In->getPrimitiveSizeInBits()))) { + // If we're accessing something that could be an element of a vector, see + // if the implied vector agrees with what we already have and if Offset is + // compatible with it. + unsigned EltSize = In->getPrimitiveSizeInBits()/8; + if (Offset % EltSize == 0 && + AllocaSize % EltSize == 0 && + (VecTy == 0 || + cast(VecTy)->getElementType() + ->getPrimitiveSizeInBits()/8 == EltSize)) { + if (VecTy == 0) + VecTy = VectorType::get(In, AllocaSize/EltSize); + return; + } } } - // Otherwise, we have a case that we can't handle with an optimized form. - // Convert the alloca to an integer that is as large as the largest store size - // of the value values. - uint64_t InSize = TD.getTypeStoreSizeInBits(In)+8*Offset; - uint64_t ASize = TD.getTypeStoreSizeInBits(Accum); - if (InSize > ASize) ASize = InSize; - Accum = IntegerType::get(ASize); + // Otherwise, we have a case that we can't handle with an optimized vector + // form. We can still turn this into a large integer. + VecTy = Type::VoidTy; } /// CanConvertToScalar - V is a pointer. If we can convert the pointee and all -/// its accesses to use a to single scalar type, return true, and set ResTy to -/// the new type. Further, if the use is not a completely trivial use that -/// mem2reg could promote, set IsNotTrivial. Offset is the current offset from -/// the base of the alloca being analyzed. +/// its accesses to use a to single vector type, return true, and set VecTy to +/// the new type. If we could convert the alloca into a single promotable +/// integer, return true but set VecTy to VoidTy. Further, if the use is not a +/// completely trivial use that mem2reg could promote, set IsNotTrivial. Offset +/// is the current offset from the base of the alloca being analyzed. /// bool SROA::CanConvertToScalar(Value *V, bool &IsNotTrivial, - const Type *&ResTy, uint64_t Offset) { + const Type *&VecTy, uint64_t Offset, + unsigned AllocaSize) { for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI!=E; ++UI) { Instruction *User = cast(*UI); @@ -1230,19 +1239,19 @@ // Don't break volatile loads. if (LI->isVolatile()) return false; - MergeInType(LI->getType(), Offset, ResTy, *TD); + MergeInType(LI->getType(), Offset, VecTy, AllocaSize, *TD); continue; } if (StoreInst *SI = dyn_cast(User)) { // Storing the pointer, not into the value? if (SI->getOperand(0) == V || SI->isVolatile()) return 0; - MergeInType(SI->getOperand(0)->getType(), Offset, ResTy, *TD); + MergeInType(SI->getOperand(0)->getType(), Offset, VecTy, AllocaSize, *TD); continue; } if (BitCastInst *BCI = dyn_cast(User)) { - if (!CanConvertToScalar(BCI, IsNotTrivial, ResTy, Offset)) + if (!CanConvertToScalar(BCI, IsNotTrivial, VecTy, Offset, AllocaSize)) return false; IsNotTrivial = true; continue; @@ -1258,7 +1267,8 @@ uint64_t GEPOffset = TD->getIndexedOffset(GEP->getOperand(0)->getType(), &Indices[0], Indices.size()); // See if all uses can be converted. - if (!CanConvertToScalar(GEP, IsNotTrivial, ResTy, Offset+GEPOffset)) + if (!CanConvertToScalar(GEP, IsNotTrivial, VecTy, Offset+GEPOffset, + AllocaSize)) return false; IsNotTrivial = true; continue; @@ -1347,8 +1357,11 @@ assert(EltSize*Elt == Offset && "Invalid modulus in validity checking"); } // Return the element extracted out of it. - return new ExtractElementInst(NV, ConstantInt::get(Type::Int32Ty, Elt), - "tmp", LI); + Value *V = new ExtractElementInst(NV, ConstantInt::get(Type::Int32Ty, Elt), + "tmp", LI); + if (V->getType() != LI->getType()) + V = new BitCastInst(V, LI->getType(), "tmp", LI); + return V; } // Otherwise, this must be a union that was converted to an integer value. @@ -1430,6 +1443,10 @@ } else { // Must be an element insertion. unsigned Elt = Offset/TD->getTypePaddedSizeInBits(VTy->getElementType()); + + if (SV->getType() != VTy->getElementType()) + SV = new BitCastInst(SV, VTy->getElementType(), "tmp", SI); + SV = InsertElementInst::Create(Old, SV, ConstantInt::get(Type::Int32Ty, Elt), "tmp", SI); @@ -1452,9 +1469,19 @@ else if (isa(SV->getType())) SV = new PtrToIntInst(SV, TD->getIntPtrType(), SV->getName(), SI); - // Always zero extend the value if needed. - if (SV->getType() != AllocaType) - SV = new ZExtInst(SV, AllocaType, SV->getName(), SI); + // Zero extend or truncate the value if needed. + if (SV->getType() != AllocaType) { + if (SV->getType()->getPrimitiveSizeInBits() < + AllocaType->getPrimitiveSizeInBits()) + SV = new ZExtInst(SV, AllocaType, SV->getName(), SI); + else { + // Truncation may be needed if storing more than the alloca can hold + // (undefined behavior). + SV = new TruncInst(SV, AllocaType, SV->getName(), SI); + SrcWidth = DestWidth; + SrcStoreWidth = DestStoreWidth; + } + } // If this is a big-endian system and the store is narrower than the // full alloca type, we need to do a shift to get the right bits. @@ -1479,7 +1506,7 @@ Mask <<= ShAmt; } else if (ShAmt < 0 && (unsigned)-ShAmt < DestWidth) { SV = BinaryOperator::CreateLShr(SV, - ConstantInt::get(SV->getType(),-ShAmt), + ConstantInt::get(SV->getType(), -ShAmt), SV->getName(), SI); Mask = Mask.lshr(-ShAmt); } Modified: llvm/trunk/test/CodeGen/X86/vec_ins_extract.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_ins_extract.ll?rev=63590&r1=63589&r2=63590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_ins_extract.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_ins_extract.ll Mon Feb 2 19:30:09 2009 @@ -1,6 +1,5 @@ ; RUN: llvm-as < %s | opt -scalarrepl -instcombine | \ ; RUN: llc -march=x86 -mcpu=yonah | not grep sub.*esp -; XFAIL: * ; This checks that various insert/extract idiom work without going to the ; stack. Modified: llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll?rev=63590&r1=63589&r2=63590&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll Mon Feb 2 19:30:09 2009 @@ -52,3 +52,13 @@ store float %tmp.upgrd.6, float* %f ret void } + +define i32 @test5(float %X) { ;; should turn into bitcast. + %X_addr = alloca [4 x float] + %X1 = getelementptr [4 x float]* %X_addr, i32 0, i32 2 + store float %X, float* %X1 + %a = bitcast float* %X1 to i32* + %tmp = load i32* %a + ret i32 %tmp +} + From isanbard at gmail.com Mon Feb 2 19:32:22 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 03 Feb 2009 01:32:22 -0000 Subject: [llvm-commits] [llvm] r63591 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Message-ID: <200902030132.n131WMsL029730@zion.cs.uiuc.edu> Author: void Date: Mon Feb 2 19:32:22 2009 New Revision: 63591 URL: http://llvm.org/viewvc/llvm-project?rev=63591&view=rev Log: Alphabetize includes. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h?rev=63591&r1=63590&r2=63591&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Mon Feb 2 19:32:22 2009 @@ -20,8 +20,8 @@ #ifndef NDEBUG #include "llvm/ADT/SmallSet.h" #endif -#include "llvm/CodeGen/ValueTypes.h" #include "llvm/CodeGen/SelectionDAGNodes.h" +#include "llvm/CodeGen/ValueTypes.h" #include "llvm/Support/CallSite.h" #include #include From gohman at apple.com Mon Feb 2 19:33:27 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 03 Feb 2009 01:33:27 -0000 Subject: [llvm-commits] [llvm] r63592 - in /llvm/trunk/test/FrontendC: 2009-01-25-NoSSE.c x86-64-red-zone.c Message-ID: <200902030133.n131XRhD029771@zion.cs.uiuc.edu> Author: djg Date: Mon Feb 2 19:33:26 2009 New Revision: 63592 URL: http://llvm.org/viewvc/llvm-project?rev=63592&view=rev Log: Delete these two tests. They are specific to x86-64, and there's no reliable way to do this with the current dejagnu infrastructure. If someone can figure out how to fix these tests so that they test what they are intended to test without spuriously failing on any popular platforms, they are invited to reinstate them. Removed: llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c llvm/trunk/test/FrontendC/x86-64-red-zone.c Removed: llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c?rev=63591&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c (original) +++ llvm/trunk/test/FrontendC/2009-01-25-NoSSE.c (removed) @@ -1,31 +0,0 @@ -// RUN: $llvmgcc -m64 -O1 -march=core2 -mno-sse %s -S -o - | not grep xmm -// PR3402 -// This is a test for x86/x86-64, add your target below if it FAILs. -// FIXME: Revert "linux" when fixed. -// XFAIL: alpha|ia64|arm|powerpc|sparc|linux -typedef unsigned long __kernel_size_t; -typedef __kernel_size_t size_t; -void *memset(void *s, int c, size_t n); - -typedef unsigned char cc_t; -typedef unsigned int speed_t; -typedef unsigned int tcflag_t; - -struct ktermios { - tcflag_t c_iflag; - tcflag_t c_oflag; - tcflag_t c_cflag; - tcflag_t c_lflag; - cc_t c_line; - cc_t c_cc[19]; - speed_t c_ispeed; - speed_t c_ospeed; -}; -void bar(struct ktermios*); -void foo() -{ - struct ktermios termios; - memset(&termios, 0, sizeof(termios)); - bar(&termios); -} - Removed: llvm/trunk/test/FrontendC/x86-64-red-zone.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/x86-64-red-zone.c?rev=63591&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/x86-64-red-zone.c (original) +++ llvm/trunk/test/FrontendC/x86-64-red-zone.c (removed) @@ -1,11 +0,0 @@ -// RUN: $llvmgcc -m64 -fomit-frame-pointer -O2 %s -S -o - > %t -// RUN: not grep subq %t -// RUN: not grep addq %t -// RUN: grep {\\-4(%%rsp)} %t | count 2 -// RUN: $llvmgcc -m64 -fomit-frame-pointer -O2 %s -S -o - -mno-red-zone > %t -// RUN: grep subq %t | count 1 -// RUN: grep addq %t | count 1 -// This is a test for x86-64, add your target below if it FAILs. -// XFAIL: alpha|ia64|arm|powerpc|sparc|i.86 - -long double f0(float f) { return f; } From isanbard at gmail.com Mon Feb 2 19:33:28 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 03 Feb 2009 01:33:28 -0000 Subject: [llvm-commits] [llvm] r63593 - in /llvm/trunk/lib/CodeGen/SelectionDAG: SelectionDAGBuild.cpp SelectionDAGISel.cpp Message-ID: <200902030133.n131XSXj029785@zion.cs.uiuc.edu> Author: void Date: Mon Feb 2 19:33:28 2009 New Revision: 63593 URL: http://llvm.org/viewvc/llvm-project?rev=63593&view=rev Log: Explicitly pass in the "unknown" debug location. This is probably not correct. We need more infrastructure before we can get the DebugLoc info for these instructions. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63593&r1=63592&r2=63593&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon Feb 2 19:33:28 2009 @@ -333,7 +333,8 @@ unsigned NumRegisters = TLI.getNumRegisters(VT); const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); for (unsigned i = 0; i != NumRegisters; ++i) - BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); + BuildMI(MBB, DebugLoc::getUnknownLoc(), + TII->get(TargetInstrInfo::PHI), PHIReg + i); PHIReg += NumRegisters; } } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=63593&r1=63592&r2=63593&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Feb 2 19:33:28 2009 @@ -743,7 +743,7 @@ unsigned LabelID = MMI->addLandingPad(BB); const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL); - BuildMI(BB, II).addImm(LabelID); + BuildMI(BB, DebugLoc::getUnknownLoc(), II).addImm(LabelID); // Mark exception register as live in. unsigned Reg = TLI.getExceptionAddressRegister(); From evan.cheng at apple.com Mon Feb 2 19:49:19 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 2 Feb 2009 17:49:19 -0800 Subject: [llvm-commits] [llvm] r63593 - in /llvm/trunk/lib/CodeGen/SelectionDAG: SelectionDAGBuild.cpp SelectionDAGISel.cpp In-Reply-To: <200902030133.n131XSXj029785@zion.cs.uiuc.edu> References: <200902030133.n131XSXj029785@zion.cs.uiuc.edu> Message-ID: <09190D26-DA2F-433F-A40F-2DAEF7D84A4E@apple.com> On Feb 2, 2009, at 5:33 PM, Bill Wendling wrote: > Author: void > Date: Mon Feb 2 19:33:28 2009 > New Revision: 63593 > > URL: http://llvm.org/viewvc/llvm-project?rev=63593&view=rev > Log: > Explicitly pass in the "unknown" debug location. This is probably not > correct. We need more infrastructure before we can get the DebugLoc > info for > these instructions. > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63593&r1=63592&r2=63593&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp > (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon > Feb 2 19:33:28 2009 > @@ -333,7 +333,8 @@ > unsigned NumRegisters = TLI.getNumRegisters(VT); > const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); > for (unsigned i = 0; i != NumRegisters; ++i) > - BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); > + BuildMI(MBB, DebugLoc::getUnknownLoc(), > + TII->get(TargetInstrInfo::PHI), PHIReg + i); > PHIReg += NumRegisters; Perhaps these should have the same location as the first instruction in the basic block? If there are no instructions, it has to traverse up the predecessor chain. Evan > > } > } > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=63593&r1=63592&r2=63593&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp > (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon > Feb 2 19:33:28 2009 > @@ -743,7 +743,7 @@ > unsigned LabelID = MMI->addLandingPad(BB); > > const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL); > - BuildMI(BB, II).addImm(LabelID); > + BuildMI(BB, DebugLoc::getUnknownLoc(), II).addImm(LabelID); > > // Mark exception register as live in. > unsigned Reg = TLI.getExceptionAddressRegister(); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dalej at apple.com Mon Feb 2 19:51:24 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 2 Feb 2009 17:51:24 -0800 Subject: [llvm-commits] [llvm] r63593 - in /llvm/trunk/lib/CodeGen/SelectionDAG: SelectionDAGBuild.cpp SelectionDAGISel.cpp In-Reply-To: <200902030133.n131XSXj029785@zion.cs.uiuc.edu> References: <200902030133.n131XSXj029785@zion.cs.uiuc.edu> Message-ID: <9B8983E0-69F3-48E7-9A05-05705905F212@apple.com> On Feb 2, 2009, at 5:33 PMPST, Bill Wendling wrote: > Author: void > Date: Mon Feb 2 19:33:28 2009 > New Revision: 63593 > > URL: http://llvm.org/viewvc/llvm-project?rev=63593&view=rev > Log: > Explicitly pass in the "unknown" debug location. This is probably not > correct. We need more infrastructure before we can get the DebugLoc > info for > these instructions. > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp I don't think we need this for PHIs, they don't survive to the output. > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp The "current" debug info loc, based on reading the stoppoint nodes as they go by, is available here as SDL->getCurDebugLoc(). Not sure how accurate that will be for landing pads but it's probably better than nothing. > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63593&r1=63592&r2=63593&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp > (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon > Feb 2 19:33:28 2009 > @@ -333,7 +333,8 @@ > unsigned NumRegisters = TLI.getNumRegisters(VT); > const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); > for (unsigned i = 0; i != NumRegisters; ++i) > - BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); > + BuildMI(MBB, DebugLoc::getUnknownLoc(), > + TII->get(TargetInstrInfo::PHI), PHIReg + i); > PHIReg += NumRegisters; > } > } > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=63593&r1=63592&r2=63593&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp > (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon > Feb 2 19:33:28 2009 > @@ -743,7 +743,7 @@ > unsigned LabelID = MMI->addLandingPad(BB); > > const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL); > - BuildMI(BB, II).addImm(LabelID); > + BuildMI(BB, DebugLoc::getUnknownLoc(), II).addImm(LabelID); > > // Mark exception register as live in. > unsigned Reg = TLI.getExceptionAddressRegister(); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Mon Feb 2 19:55:43 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 03 Feb 2009 01:55:43 -0000 Subject: [llvm-commits] [llvm] r63594 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200902030155.n131thjb030549@zion.cs.uiuc.edu> Author: void Date: Mon Feb 2 19:55:42 2009 New Revision: 63594 URL: http://llvm.org/viewvc/llvm-project?rev=63594&view=rev Log: Use SDL->getCurDebugLoc() instead of unknown loc for landing pads. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=63594&r1=63593&r2=63594&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Feb 2 19:55:42 2009 @@ -743,7 +743,7 @@ unsigned LabelID = MMI->addLandingPad(BB); const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL); - BuildMI(BB, DebugLoc::getUnknownLoc(), II).addImm(LabelID); + BuildMI(BB, SDL->getCurDebugLoc(), II).addImm(LabelID); // Mark exception register as live in. unsigned Reg = TLI.getExceptionAddressRegister(); From dalej at apple.com Mon Feb 2 19:55:45 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 03 Feb 2009 01:55:45 -0000 Subject: [llvm-commits] [llvm] r63595 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200902030155.n131tjl0030563@zion.cs.uiuc.edu> Author: johannes Date: Mon Feb 2 19:55:44 2009 New Revision: 63595 URL: http://llvm.org/viewvc/llvm-project?rev=63595&view=rev Log: Fill in some missing DL propagation in getNode()s. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63595&r1=63594&r2=63595&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Feb 2 19:55:44 2009 @@ -854,8 +854,7 @@ SDValue NegOneElt = getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), EltVT); std::vector NegOnes(VT.getVectorNumElements(), NegOneElt); - NegOne = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), VT, - &NegOnes[0], NegOnes.size()); + NegOne = getNode(ISD::BUILD_VECTOR, DL, VT, &NegOnes[0], NegOnes.size()); } else { NegOne = getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); } @@ -2150,10 +2149,11 @@ /// element of the result of the vector shuffle. SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { MVT VT = N->getValueType(0); + DebugLoc dl = N->getDebugLoc(); SDValue PermMask = N->getOperand(2); SDValue Idx = PermMask.getOperand(i); if (Idx.getOpcode() == ISD::UNDEF) - return getNode(ISD::UNDEF, VT.getVectorElementType()); + return getNode(ISD::UNDEF, dl, VT.getVectorElementType()); unsigned Index = cast(Idx)->getZExtValue(); unsigned NumElems = PermMask.getNumOperands(); SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); @@ -2167,7 +2167,7 @@ } if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) return (Index == 0) ? V.getOperand(0) - : getNode(ISD::UNDEF, VT.getVectorElementType()); + : getNode(ISD::UNDEF, dl, VT.getVectorElementType()); if (V.getOpcode() == ISD::BUILD_VECTOR) return V.getOperand(Index); if (V.getOpcode() == ISD::VECTOR_SHUFFLE) @@ -2301,7 +2301,7 @@ Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); if (Operand.getValueType() == VT) return Operand; // noop conversion. if (Operand.getOpcode() == ISD::UNDEF) - return getNode(ISD::UNDEF, VT); + return getNode(ISD::UNDEF, DL, VT); break; case ISD::SIGN_EXTEND: assert(VT.isInteger() && Operand.getValueType().isInteger() && @@ -2310,7 +2310,7 @@ assert(Operand.getValueType().bitsLT(VT) && "Invalid sext node, dst < src!"); if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) - return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); + return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); break; case ISD::ZERO_EXTEND: assert(VT.isInteger() && Operand.getValueType().isInteger() && @@ -2319,7 +2319,8 @@ assert(Operand.getValueType().bitsLT(VT) && "Invalid zext node, dst < src!"); if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) - return getNode(ISD::ZERO_EXTEND, VT, Operand.getNode()->getOperand(0)); + return getNode(ISD::ZERO_EXTEND, DL, VT, + Operand.getNode()->getOperand(0)); break; case ISD::ANY_EXTEND: assert(VT.isInteger() && Operand.getValueType().isInteger() && @@ -2329,7 +2330,7 @@ && "Invalid anyext node, dst < src!"); if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) - return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); + return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); break; case ISD::TRUNCATE: assert(VT.isInteger() && Operand.getValueType().isInteger() && @@ -2338,14 +2339,14 @@ assert(Operand.getValueType().bitsGT(VT) && "Invalid truncate node, src < dst!"); if (OpOpcode == ISD::TRUNCATE) - return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); + return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ANY_EXTEND) { // If the source is smaller than the dest, we still need an extend. if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) - return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); + return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) - return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); + return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); else return Operand.getNode()->getOperand(0); } @@ -2356,16 +2357,16 @@ && "Cannot BIT_CONVERT between types of different sizes!"); if (VT == Operand.getValueType()) return Operand; // noop conversion. if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) - return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0)); + return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0)); if (OpOpcode == ISD::UNDEF) - return getNode(ISD::UNDEF, VT); + return getNode(ISD::UNDEF, DL, VT); break; case ISD::SCALAR_TO_VECTOR: assert(VT.isVector() && !Operand.getValueType().isVector() && VT.getVectorElementType() == Operand.getValueType() && "Illegal SCALAR_TO_VECTOR node!"); if (OpOpcode == ISD::UNDEF) - return getNode(ISD::UNDEF, VT); + return getNode(ISD::UNDEF, DL, VT); // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && isa(Operand.getOperand(1)) && @@ -2376,14 +2377,14 @@ case ISD::FNEG: // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0 if (UnsafeFPMath && OpOpcode == ISD::FSUB) - return getNode(ISD::FSUB, VT, Operand.getNode()->getOperand(1), + return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1), Operand.getNode()->getOperand(0)); if (OpOpcode == ISD::FNEG) // --X -> X return Operand.getNode()->getOperand(0); break; case ISD::FABS: if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) - return getNode(ISD::FABS, VT, Operand.getNode()->getOperand(0)); + return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0)); break; } @@ -2473,7 +2474,7 @@ N2.getOpcode() == ISD::BUILD_VECTOR) { SmallVector Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); - return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); + return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); } break; case ISD::AND: @@ -2599,7 +2600,7 @@ case ISD::EXTRACT_VECTOR_ELT: // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. if (N1.getOpcode() == ISD::UNDEF) - return getNode(ISD::UNDEF, VT); + return getNode(ISD::UNDEF, DL, VT); // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is // expanding copies of large vectors from registers. @@ -2608,7 +2609,7 @@ N1.getNumOperands() > 0) { unsigned Factor = N1.getOperand(0).getValueType().getVectorNumElements(); - return getNode(ISD::EXTRACT_VECTOR_ELT, VT, + return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(N2C->getZExtValue() / Factor), getConstant(N2C->getZExtValue() % Factor, N2.getValueType())); @@ -2629,7 +2630,7 @@ // the original vector. else if (isa(N1.getOperand(2)) && isa(N2)) - return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2); + return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2); } break; case ISD::EXTRACT_ELEMENT: @@ -2990,7 +2991,8 @@ static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, SelectionDAG &DAG) { MVT VT = Base.getValueType(); - return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); + return DAG.getNode(ISD::ADD, Base.getNode()->getDebugLoc(), + VT, Base, DAG.getConstant(Offset, VT)); } /// isMemSrcFromString - Returns true if memcpy source is a string constant. @@ -4932,7 +4934,7 @@ MVT VT1, MVT VT2, MVT VT3, const SDValue *Ops, unsigned NumOps) { const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); - return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode(); + return getNode(~Opcode, dl, VTs, 3, Ops, NumOps).getNode(); } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, From evan.cheng at apple.com Mon Feb 2 19:56:41 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 2 Feb 2009 17:56:41 -0800 Subject: [llvm-commits] [llvm] r63593 - in /llvm/trunk/lib/CodeGen/SelectionDAG: SelectionDAGBuild.cpp SelectionDAGISel.cpp In-Reply-To: <9B8983E0-69F3-48E7-9A05-05705905F212@apple.com> References: <200902030133.n131XSXj029785@zion.cs.uiuc.edu> <9B8983E0-69F3-48E7-9A05-05705905F212@apple.com> Message-ID: <5AABD479-2A83-4C48-B712-7364473707AB@apple.com> On Feb 2, 2009, at 5:51 PM, Dale Johannesen wrote: > > On Feb 2, 2009, at 5:33 PMPST, Bill Wendling wrote: > >> Author: void >> Date: Mon Feb 2 19:33:28 2009 >> New Revision: 63593 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=63593&view=rev >> Log: >> Explicitly pass in the "unknown" debug location. This is probably not >> correct. We need more infrastructure before we can get the DebugLoc >> info for >> these instructions. >> >> Modified: >> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp > > I don't think we need this for PHIs, they don't survive to the output. They can become copies which are not always coalesced away. Evan > > >> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp > > The "current" debug info loc, based on reading the stoppoint nodes as > they go by, is available here as SDL->getCurDebugLoc(). > Not sure how accurate that will be for landing pads but it's probably > better than nothing. > >> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63593&r1=63592&r2=63593&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp >> (original) >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon >> Feb 2 19:33:28 2009 >> @@ -333,7 +333,8 @@ >> unsigned NumRegisters = TLI.getNumRegisters(VT); >> const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); >> for (unsigned i = 0; i != NumRegisters; ++i) >> - BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); >> + BuildMI(MBB, DebugLoc::getUnknownLoc(), >> + TII->get(TargetInstrInfo::PHI), PHIReg + i); >> PHIReg += NumRegisters; >> } >> } >> >> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=63593&r1=63592&r2=63593&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp >> (original) >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon >> Feb 2 19:33:28 2009 >> @@ -743,7 +743,7 @@ >> unsigned LabelID = MMI->addLandingPad(BB); >> >> const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL); >> - BuildMI(BB, II).addImm(LabelID); >> + BuildMI(BB, DebugLoc::getUnknownLoc(), II).addImm(LabelID); >> >> // Mark exception register as live in. >> unsigned Reg = TLI.getExceptionAddressRegister(); >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Mon Feb 2 19:57:07 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 2 Feb 2009 17:57:07 -0800 Subject: [llvm-commits] [llvm] r63593 - in /llvm/trunk/lib/CodeGen/SelectionDAG: SelectionDAGBuild.cpp SelectionDAGISel.cpp In-Reply-To: <9B8983E0-69F3-48E7-9A05-05705905F212@apple.com> References: <200902030133.n131XSXj029785@zion.cs.uiuc.edu> <9B8983E0-69F3-48E7-9A05-05705905F212@apple.com> Message-ID: <16e5fdf90902021757n6696c897s971ffab4034f3301@mail.gmail.com> On Mon, Feb 2, 2009 at 5:51 PM, Dale Johannesen wrote: > > On Feb 2, 2009, at 5:33 PMPST, Bill Wendling wrote: > >> Author: void >> Date: Mon Feb 2 19:33:28 2009 >> New Revision: 63593 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=63593&view=rev >> Log: >> Explicitly pass in the "unknown" debug location. This is probably not >> correct. We need more infrastructure before we can get the DebugLoc >> info for >> these instructions. >> >> Modified: >> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp > > I don't think we need this for PHIs, they don't survive to the output. > >> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp > > The "current" debug info loc, based on reading the stoppoint nodes as > they go by, is available here as SDL->getCurDebugLoc(). > Not sure how accurate that will be for landing pads but it's probably > better than nothing. > I made this change. Thanks! -bw From isanbard at gmail.com Mon Feb 2 19:59:10 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 2 Feb 2009 17:59:10 -0800 Subject: [llvm-commits] [llvm] r63593 - in /llvm/trunk/lib/CodeGen/SelectionDAG: SelectionDAGBuild.cpp SelectionDAGISel.cpp In-Reply-To: <09190D26-DA2F-433F-A40F-2DAEF7D84A4E@apple.com> References: <200902030133.n131XSXj029785@zion.cs.uiuc.edu> <09190D26-DA2F-433F-A40F-2DAEF7D84A4E@apple.com> Message-ID: <16e5fdf90902021759p3c8a3999o3407637ebd4950d8@mail.gmail.com> On Mon, Feb 2, 2009 at 5:49 PM, Evan Cheng wrote: > > On Feb 2, 2009, at 5:33 PM, Bill Wendling wrote: > >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon >> Feb 2 19:33:28 2009 >> @@ -333,7 +333,8 @@ >> unsigned NumRegisters = TLI.getNumRegisters(VT); >> const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); >> for (unsigned i = 0; i != NumRegisters; ++i) >> - BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); >> + BuildMI(MBB, DebugLoc::getUnknownLoc(), >> + TII->get(TargetInstrInfo::PHI), PHIReg + i); >> PHIReg += NumRegisters; > > Perhaps these should have the same location as the first instruction > in the basic block? If there are no instructions, it has to traverse > up the predecessor chain. > At this point, there aren't any instructions in the BB (they're all being created, and only PHI nodes will be in the blocks after it's done). The only way I can think of to get information is to look for the "llvm.dbg.stoppoint" calls and get the info that way. But that involves having DAG around, which I don't think is available at this point... -bw From sabre at nondot.org Mon Feb 2 20:01:43 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Feb 2009 02:01:43 -0000 Subject: [llvm-commits] [llvm] r63596 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/memset-aggregate.ll Message-ID: <200902030201.n1321ixj030751@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 2 20:01:43 2009 New Revision: 63596 URL: http://llvm.org/viewvc/llvm-project?rev=63596&view=rev Log: Teach ConvertUsesToScalar to handle memset, allowing it to handle crazy cases like: struct f { int A, B, C, D, E, F; }; short test4() { struct f A; A.A = 1; memset(&A.B, 2, 12); return A.C; } Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/trunk/test/Transforms/ScalarRepl/memset-aggregate.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=63596&r1=63595&r2=63596&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Mon Feb 2 20:01:43 2009 @@ -130,8 +130,8 @@ void ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, uint64_t Offset); Value *ConvertUsesOfLoadToScalar(LoadInst *LI, AllocaInst *NewAI, uint64_t Offset); - Value *ConvertUsesOfStoreToScalar(StoreInst *SI, AllocaInst *NewAI, - uint64_t Offset); + Value *ConvertUsesOfStoreToScalar(Value *StoredVal, AllocaInst *NewAI, + uint64_t Offset, Instruction *InsertPt); static Instruction *isOnlyCopiedFromConstantGlobal(AllocationInst *AI); }; } @@ -1274,6 +1274,18 @@ continue; } + // If this is a constant sized memset of a constant value (e.g. 0) we can + // handle it. + if (isa(User) && + // Store of constant value. + isa(User->getOperand(2)) && + // Store with constant size. + isa(User->getOperand(3))) { + VecTy = Type::VoidTy; + IsNotTrivial = true; + continue; + } + // Otherwise, we cannot handle this! return false; } @@ -1301,7 +1313,8 @@ if (StoreInst *SI = dyn_cast(User)) { assert(SI->getOperand(0) != Ptr && "Consistency error!"); - new StoreInst(ConvertUsesOfStoreToScalar(SI, NewAI, Offset), NewAI, SI); + new StoreInst(ConvertUsesOfStoreToScalar(SI->getOperand(0), NewAI, + Offset, SI), NewAI, SI); SI->eraseFromParent(); continue; } @@ -1321,6 +1334,29 @@ GEP->eraseFromParent(); continue; } + + // If this is a constant sized memset of a constant value (e.g. 0) we can + // transform it into a store of the expanded constant value. + if (MemSetInst *MSI = dyn_cast(User)) { + assert(MSI->getRawDest() == Ptr && "Consistency error!"); + unsigned NumBytes = cast(MSI->getLength())->getZExtValue(); + unsigned Val = cast(MSI->getValue())->getZExtValue(); + + // Compute the value replicated the right number of times. + APInt APVal(NumBytes*8, Val); + + // Splat the value if non-zero. + if (Val) + for (unsigned i = 1; i != NumBytes; ++i) + APVal |= APVal << 8; + + new StoreInst(ConvertUsesOfStoreToScalar(ConstantInt::get(APVal), NewAI, + Offset, MSI), NewAI, MSI); + MSI->eraseFromParent(); + continue; + } + + assert(0 && "Unsupported operation!"); abort(); } @@ -1422,40 +1458,38 @@ /// /// Offset is an offset from the original alloca, in bits that need to be /// shifted to the right. By the end of this, there should be no uses of Ptr. -Value *SROA::ConvertUsesOfStoreToScalar(StoreInst *SI, AllocaInst *NewAI, - uint64_t Offset) { +Value *SROA::ConvertUsesOfStoreToScalar(Value *SV, AllocaInst *NewAI, + uint64_t Offset, Instruction *IP) { // Convert the stored type to the actual type, shift it left to insert // then 'or' into place. - Value *SV = SI->getOperand(0); const Type *AllocaType = NewAI->getType()->getElementType(); - if (SV->getType() == AllocaType && Offset == 0) { + if (SV->getType() == AllocaType && Offset == 0) return SV; - } if (const VectorType *VTy = dyn_cast(AllocaType)) { - Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", SI); + Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", IP); // If the result alloca is a vector type, this is either an element // access or a bitcast to another vector type. if (isa(SV->getType())) { - SV = new BitCastInst(SV, AllocaType, SV->getName(), SI); + SV = new BitCastInst(SV, AllocaType, SV->getName(), IP); } else { // Must be an element insertion. unsigned Elt = Offset/TD->getTypePaddedSizeInBits(VTy->getElementType()); if (SV->getType() != VTy->getElementType()) - SV = new BitCastInst(SV, VTy->getElementType(), "tmp", SI); + SV = new BitCastInst(SV, VTy->getElementType(), "tmp", IP); SV = InsertElementInst::Create(Old, SV, ConstantInt::get(Type::Int32Ty, Elt), - "tmp", SI); + "tmp", IP); } return SV; } - Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", SI); + Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", IP); // If SV is a float, convert it to the appropriate integer type. // If it is a pointer, do the same, and also handle ptr->ptr casts @@ -1465,19 +1499,19 @@ unsigned SrcStoreWidth = TD->getTypeStoreSizeInBits(SV->getType()); unsigned DestStoreWidth = TD->getTypeStoreSizeInBits(AllocaType); if (SV->getType()->isFloatingPoint() || isa(SV->getType())) - SV = new BitCastInst(SV, IntegerType::get(SrcWidth), SV->getName(), SI); + SV = new BitCastInst(SV, IntegerType::get(SrcWidth), SV->getName(), IP); else if (isa(SV->getType())) - SV = new PtrToIntInst(SV, TD->getIntPtrType(), SV->getName(), SI); + SV = new PtrToIntInst(SV, TD->getIntPtrType(), SV->getName(), IP); // Zero extend or truncate the value if needed. if (SV->getType() != AllocaType) { if (SV->getType()->getPrimitiveSizeInBits() < AllocaType->getPrimitiveSizeInBits()) - SV = new ZExtInst(SV, AllocaType, SV->getName(), SI); + SV = new ZExtInst(SV, AllocaType, SV->getName(), IP); else { // Truncation may be needed if storing more than the alloca can hold // (undefined behavior). - SV = new TruncInst(SV, AllocaType, SV->getName(), SI); + SV = new TruncInst(SV, AllocaType, SV->getName(), IP); SrcWidth = DestWidth; SrcStoreWidth = DestStoreWidth; } @@ -1502,12 +1536,12 @@ if (ShAmt > 0 && (unsigned)ShAmt < DestWidth) { SV = BinaryOperator::CreateShl(SV, ConstantInt::get(SV->getType(), ShAmt), - SV->getName(), SI); + SV->getName(), IP); Mask <<= ShAmt; } else if (ShAmt < 0 && (unsigned)-ShAmt < DestWidth) { SV = BinaryOperator::CreateLShr(SV, ConstantInt::get(SV->getType(), -ShAmt), - SV->getName(), SI); + SV->getName(), IP); Mask = Mask.lshr(-ShAmt); } @@ -1516,8 +1550,8 @@ if (SrcWidth != DestWidth) { assert(DestWidth > SrcWidth); Old = BinaryOperator::CreateAnd(Old, ConstantInt::get(~Mask), - Old->getName()+".mask", SI); - SV = BinaryOperator::CreateOr(Old, SV, SV->getName()+".ins", SI); + Old->getName()+".mask", IP); + SV = BinaryOperator::CreateOr(Old, SV, SV->getName()+".ins", IP); } return SV; } Modified: llvm/trunk/test/Transforms/ScalarRepl/memset-aggregate.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/memset-aggregate.ll?rev=63596&r1=63595&r2=63596&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/memset-aggregate.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/memset-aggregate.ll Mon Feb 2 20:01:43 2009 @@ -1,6 +1,7 @@ ; PR1226 ; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | grep {ret i32 16843009} ; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | not grep alloca +; RUN: llvm-as < %s | opt -scalarrepl -instcombine | llvm-dis | grep {ret i16 514} target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" target triple = "i686-apple-darwin8" @@ -46,3 +47,20 @@ %tmp7 = load i32* %tmp6 ; [#uses=1] ret i32 %tmp7 } + + + %struct.f = type { i32, i32, i32, i32, i32, i32 } + +define i16 @test4() nounwind { +entry: + %A = alloca %struct.f, align 8 ; <%struct.f*> [#uses=3] + %0 = getelementptr %struct.f* %A, i32 0, i32 0 ; [#uses=1] + store i32 1, i32* %0, align 8 + %1 = getelementptr %struct.f* %A, i32 0, i32 1 ; [#uses=1] + %2 = bitcast i32* %1 to i8* ; [#uses=1] + call void @llvm.memset.i32(i8* %2, i8 2, i32 12, i32 4) + %3 = getelementptr %struct.f* %A, i32 0, i32 2 ; [#uses=1] + %4 = load i32* %3, align 8 ; [#uses=1] + %retval12 = trunc i32 %4 to i16 ; [#uses=1] + ret i16 %retval12 +} From dalej at apple.com Mon Feb 2 20:09:11 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 2 Feb 2009 18:09:11 -0800 Subject: [llvm-commits] [llvm] r63593 - in /llvm/trunk/lib/CodeGen/SelectionDAG: SelectionDAGBuild.cpp SelectionDAGISel.cpp In-Reply-To: <5AABD479-2A83-4C48-B712-7364473707AB@apple.com> References: <200902030133.n131XSXj029785@zion.cs.uiuc.edu> <9B8983E0-69F3-48E7-9A05-05705905F212@apple.com> <5AABD479-2A83-4C48-B712-7364473707AB@apple.com> Message-ID: On Feb 2, 2009, at 5:56 PMPST, Evan Cheng wrote: > > On Feb 2, 2009, at 5:51 PM, Dale Johannesen wrote: > >> >> On Feb 2, 2009, at 5:33 PMPST, Bill Wendling wrote: >> >>> Author: void >>> Date: Mon Feb 2 19:33:28 2009 >>> New Revision: 63593 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=63593&view=rev >>> Log: >>> Explicitly pass in the "unknown" debug location. This is probably >>> not >>> correct. We need more infrastructure before we can get the DebugLoc >>> info for >>> these instructions. >>> >>> Modified: >>> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp >> >> I don't think we need this for PHIs, they don't survive to the >> output. > > They can become copies which are not always coalesced away. > > Evan OK. There's a DL in the BasicBlock SDNode's, then, I guess PHIs could use that if it's been created at this point. Not sure offhand how you get at it from inside FunctionLoweringInfo. From sabre at nondot.org Mon Feb 2 20:11:28 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Feb 2009 02:11:28 -0000 Subject: [llvm-commits] [llvm] r63597 - in /llvm/trunk: lib/Bitcode/Reader/BitcodeReader.cpp test/Bitcode/extractelement.ll Message-ID: <200902030211.n132BSP3031250@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 2 20:11:28 2009 New Revision: 63597 URL: http://llvm.org/viewvc/llvm-project?rev=63597&view=rev Log: fix a bitcode reader bug where it can't handle extractelement correctly: the index of the value being extracted is always an i32. This fixes PR3465 Added: llvm/trunk/test/Bitcode/extractelement.ll Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=63597&r1=63596&r2=63597&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Mon Feb 2 20:11:28 2009 @@ -915,8 +915,7 @@ dyn_cast_or_null(getTypeByID(Record[0])); if (OpTy == 0) return Error("Invalid CE_EXTRACTELT record"); Constant *Op0 = ValueList.getConstantFwdRef(Record[1], OpTy); - Constant *Op1 = ValueList.getConstantFwdRef(Record[2], - OpTy->getElementType()); + Constant *Op1 = ValueList.getConstantFwdRef(Record[2], Type::Int32Ty); V = ConstantExpr::getExtractElement(Op0, Op1); break; } Added: llvm/trunk/test/Bitcode/extractelement.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/extractelement.ll?rev=63597&view=auto ============================================================================== --- llvm/trunk/test/Bitcode/extractelement.ll (added) +++ llvm/trunk/test/Bitcode/extractelement.ll Mon Feb 2 20:11:28 2009 @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | opt -constprop | llvm-dis +; PR3465 + +define double @test() { + %tmp24 = extractelement <2 x double> bitcast (<1 x i128> < i128 85070591730234615870450834276742070272 > to <2 x double>), i32 0 + ret double %tmp24 +} + From evan.cheng at apple.com Mon Feb 2 20:15:50 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 2 Feb 2009 18:15:50 -0800 Subject: [llvm-commits] [llvm] r63593 - in /llvm/trunk/lib/CodeGen/SelectionDAG: SelectionDAGBuild.cpp SelectionDAGISel.cpp In-Reply-To: <16e5fdf90902021759p3c8a3999o3407637ebd4950d8@mail.gmail.com> References: <200902030133.n131XSXj029785@zion.cs.uiuc.edu> <09190D26-DA2F-433F-A40F-2DAEF7D84A4E@apple.com> <16e5fdf90902021759p3c8a3999o3407637ebd4950d8@mail.gmail.com> Message-ID: <44D8F43D-1A94-4237-BB37-5328CF016305@apple.com> We can refine these later. It's easy to grep for getUnknonwLoc. :-) Evan On Feb 2, 2009, at 5:59 PM, Bill Wendling wrote: > On Mon, Feb 2, 2009 at 5:49 PM, Evan Cheng > wrote: >> >> On Feb 2, 2009, at 5:33 PM, Bill Wendling wrote: >> >>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon >>> Feb 2 19:33:28 2009 >>> @@ -333,7 +333,8 @@ >>> unsigned NumRegisters = TLI.getNumRegisters(VT); >>> const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); >>> for (unsigned i = 0; i != NumRegisters; ++i) >>> - BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); >>> + BuildMI(MBB, DebugLoc::getUnknownLoc(), >>> + TII->get(TargetInstrInfo::PHI), PHIReg + i); >>> PHIReg += NumRegisters; >> >> Perhaps these should have the same location as the first instruction >> in the basic block? If there are no instructions, it has to traverse >> up the predecessor chain. >> > At this point, there aren't any instructions in the BB (they're all > being created, and only PHI nodes will be in the blocks after it's > done). The only way I can think of to get information is to look for > the "llvm.dbg.stoppoint" calls and get the info that way. But that > involves having DAG around, which I don't think is available at this > point... > > -bw > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Mon Feb 2 20:20:52 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 03 Feb 2009 02:20:52 -0000 Subject: [llvm-commits] [llvm] r63598 - in /llvm/trunk/lib/CodeGen/SelectionDAG: SelectionDAGBuild.cpp SelectionDAGBuild.h SelectionDAGISel.cpp Message-ID: <200902030220.n132KqSo031594@zion.cs.uiuc.edu> Author: void Date: Mon Feb 2 20:20:52 2009 New Revision: 63598 URL: http://llvm.org/viewvc/llvm-project?rev=63598&view=rev Log: Pass in something sensible for the debug location information when creating the initial PHI nodes of the machine function. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63598&r1=63597&r2=63598&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon Feb 2 20:20:52 2009 @@ -271,6 +271,7 @@ } void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf, + SelectionDAG &DAG, bool EnableFastISel) { Fn = &fn; MF = &mf; @@ -320,8 +321,53 @@ // Create Machine PHI nodes for LLVM PHI nodes, lowering them as // appropriate. PHINode *PN; - for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast(I)); ++I){ - if (PN->use_empty()) continue; + DebugLoc DL; + for (BasicBlock::iterator + I = BB->begin(), E = BB->end(); I != E; ++I) { + if (CallInst *CI = dyn_cast(I)) { + if (Function *F = CI->getCalledFunction()) { + switch (F->getIntrinsicID()) { + default: break; + case Intrinsic::dbg_stoppoint: { + DwarfWriter *DW = DAG.getDwarfWriter(); + DbgStopPointInst *SPI = cast(I); + + if (DW && DW->ValidDebugInfo(SPI->getContext())) { + DICompileUnit CU(cast(SPI->getContext())); + unsigned SrcFile = DW->RecordSource(CU.getDirectory(), + CU.getFilename()); + unsigned idx = MF->getOrCreateDebugLocID(SrcFile, + SPI->getLine(), + SPI->getColumn()); + DL = DebugLoc::get(idx); + } + + break; + } + case Intrinsic::dbg_func_start: { + DwarfWriter *DW = DAG.getDwarfWriter(); + if (DW) { + DbgFuncStartInst *FSI = cast(I); + Value *SP = FSI->getSubprogram(); + + if (DW->ValidDebugInfo(SP)) { + DISubprogram Subprogram(cast(SP)); + DICompileUnit CU(Subprogram.getCompileUnit()); + unsigned SrcFile = DW->RecordSource(CU.getDirectory(), + CU.getFilename()); + unsigned Line = Subprogram.getLineNumber(); + DL = DebugLoc::get(MF->getOrCreateDebugLocID(SrcFile, Line, 0)); + } + } + + break; + } + } + } + } + + PN = dyn_cast(I); + if (!PN || PN->use_empty()) continue; unsigned PHIReg = ValueMap[PN]; assert(PHIReg && "PHI node does not have an assigned virtual register!"); @@ -333,8 +379,7 @@ unsigned NumRegisters = TLI.getNumRegisters(VT); const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); for (unsigned i = 0; i != NumRegisters; ++i) - BuildMI(MBB, DebugLoc::getUnknownLoc(), - TII->get(TargetInstrInfo::PHI), PHIReg + i); + BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i); PHIReg += NumRegisters; } } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h?rev=63598&r1=63597&r2=63598&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Mon Feb 2 20:20:52 2009 @@ -95,7 +95,8 @@ /// set - Initialize this FunctionLoweringInfo with the given Function /// and its associated MachineFunction. /// - void set(Function &Fn, MachineFunction &MF, bool EnableFastISel); + void set(Function &Fn, MachineFunction &MF, SelectionDAG &DAG, + bool EnableFastISel); /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. DenseMap MBBMap; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=63598&r1=63597&r2=63598&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Feb 2 20:20:52 2009 @@ -313,7 +313,7 @@ RegInfo = &MF->getRegInfo(); DOUT << "\n\n\n=== " << Fn.getName() << "\n"; - FuncInfo->set(Fn, *MF, EnableFastISel); + FuncInfo->set(Fn, *MF, *CurDAG, EnableFastISel); MachineModuleInfo *MMI = getAnalysisIfAvailable(); DwarfWriter *DW = getAnalysisIfAvailable(); CurDAG->init(*MF, MMI, DW); From isanbard at gmail.com Mon Feb 2 20:21:26 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 2 Feb 2009 18:21:26 -0800 Subject: [llvm-commits] [llvm] r63593 - in /llvm/trunk/lib/CodeGen/SelectionDAG: SelectionDAGBuild.cpp SelectionDAGISel.cpp In-Reply-To: <44D8F43D-1A94-4237-BB37-5328CF016305@apple.com> References: <200902030133.n131XSXj029785@zion.cs.uiuc.edu> <09190D26-DA2F-433F-A40F-2DAEF7D84A4E@apple.com> <16e5fdf90902021759p3c8a3999o3407637ebd4950d8@mail.gmail.com> <44D8F43D-1A94-4237-BB37-5328CF016305@apple.com> Message-ID: <16e5fdf90902021821m3e3c29d3ve36e47611150f757@mail.gmail.com> On Mon, Feb 2, 2009 at 6:15 PM, Evan Cheng wrote: > We can refine these later. It's easy to grep for getUnknonwLoc. :-) > It was easier to fix than I'd first imagined. I think the next commit is something sensible. :-) -bw From isanbard at gmail.com Mon Feb 2 20:29:34 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 03 Feb 2009 02:29:34 -0000 Subject: [llvm-commits] [llvm] r63599 - in /llvm/trunk/lib/CodeGen: GCStrategy.cpp PHIElimination.cpp TargetInstrInfoImpl.cpp VirtRegMap.cpp Message-ID: <200902030229.n132TY63031878@zion.cs.uiuc.edu> Author: void Date: Mon Feb 2 20:29:34 2009 New Revision: 63599 URL: http://llvm.org/viewvc/llvm-project?rev=63599&view=rev Log: Explicitly pass in debug location information to BuildMI. Modified: llvm/trunk/lib/CodeGen/GCStrategy.cpp llvm/trunk/lib/CodeGen/PHIElimination.cpp llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp llvm/trunk/lib/CodeGen/VirtRegMap.cpp Modified: llvm/trunk/lib/CodeGen/GCStrategy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GCStrategy.cpp?rev=63599&r1=63598&r2=63599&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/GCStrategy.cpp (original) +++ llvm/trunk/lib/CodeGen/GCStrategy.cpp Mon Feb 2 20:29:34 2009 @@ -329,7 +329,8 @@ unsigned MachineCodeAnalysis::InsertLabel(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { unsigned Label = MMI->NextLabelID(); - BuildMI(MBB, MI, TII->get(TargetInstrInfo::GC_LABEL)).addImm(Label); + BuildMI(MBB, MI, MI->getDebugLoc(), + TII->get(TargetInstrInfo::GC_LABEL)).addImm(Label); return Label; } Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=63599&r1=63598&r2=63599&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Mon Feb 2 20:29:34 2009 @@ -166,7 +166,7 @@ if (isSourceDefinedByImplicitDef(MPhi, MRI)) // If all sources of a PHI node are implicit_def, just emit an // implicit_def instead of a copy. - BuildMI(MBB, AfterPHIsIt, + BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(), TII->get(TargetInstrInfo::IMPLICIT_DEF), DestReg); else { IncomingReg = MF.getRegInfo().createVirtualRegister(RC); Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=63599&r1=63598&r2=63599&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original) +++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Mon Feb 2 20:29:34 2009 @@ -44,7 +44,7 @@ unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); bool Reg0IsDead = MI->getOperand(0).isDead(); MachineFunction &MF = *MI->getParent()->getParent(); - return BuildMI(MF, MI->getDesc()) + return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) .addReg(Reg0, true, false, false, Reg0IsDead) .addReg(Reg2, false, false, Reg2IsKill) .addReg(Reg1, false, false, Reg1IsKill); Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=63599&r1=63598&r2=63599&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Mon Feb 2 20:29:34 2009 @@ -1360,7 +1360,8 @@ unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys; MI.getOperand(i).setReg(RReg); if (VRM.isImplicitlyDefined(VirtReg)) - BuildMI(MBB, &MI, TII->get(TargetInstrInfo::IMPLICIT_DEF), RReg); + BuildMI(MBB, &MI, MI.getDebugLoc(), + TII->get(TargetInstrInfo::IMPLICIT_DEF), RReg); continue; } From nicholas at mxc.ca Mon Feb 2 22:34:42 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 03 Feb 2009 04:34:42 -0000 Subject: [llvm-commits] [llvm] r63600 - in /llvm/trunk: lib/Transforms/Utils/InlineFunction.cpp test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll Message-ID: <200902030434.n134Ygig003459@zion.cs.uiuc.edu> Author: nicholas Date: Mon Feb 2 22:34:40 2009 New Revision: 63600 URL: http://llvm.org/viewvc/llvm-project?rev=63600&view=rev Log: Update the callgraph when replacing InvokeInst with CallInst when inlining. Added: llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=63600&r1=63599&r2=63600&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Mon Feb 2 22:34:40 2009 @@ -37,11 +37,12 @@ /// in the body of the inlined function into invokes and turn unwind /// instructions into branches to the invoke unwind dest. /// -/// II is the invoke instruction begin inlined. FirstNewBlock is the first +/// II is the invoke instruction being inlined. FirstNewBlock is the first /// block of the inlined code (the last block is the end of the function), /// and InlineCodeInfo is information about the code that got inlined. static void HandleInlinedInvoke(InvokeInst *II, BasicBlock *FirstNewBlock, - ClonedCodeInfo &InlinedCodeInfo) { + ClonedCodeInfo &InlinedCodeInfo, + CallGraph *CG) { BasicBlock *InvokeDest = II->getUnwindDest(); std::vector InvokeDestPHIValues; @@ -93,6 +94,10 @@ // Make sure that anything using the call now uses the invoke! CI->replaceAllUsesWith(II); + // Update the callgraph. + if (CG) + (*CG)[Caller]->replaceCallSite(CI, II); + // Delete the unconditional branch inserted by splitBasicBlock BB->getInstList().pop_back(); Split->getInstList().pop_front(); // Delete the original call @@ -433,7 +438,7 @@ // any inlined 'unwind' instructions into branches to the invoke exception // destination, and call instructions into invoke instructions. if (InvokeInst *II = dyn_cast(TheCall)) - HandleInlinedInvoke(II, FirstNewBlock, InlinedFunctionInfo); + HandleInlinedInvoke(II, FirstNewBlock, InlinedFunctionInfo, CG); // If we cloned in _exactly one_ basic block, and if that block ends in a // return instruction, we splice the body of the inlined callee directly into Added: llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll?rev=63600&view=auto ============================================================================== --- llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll (added) +++ llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll Mon Feb 2 22:34:40 2009 @@ -0,0 +1,32 @@ +; RUN: llvm-as < %s | opt -inline -prune-eh +; PR3367 + +define void @f2() { + invoke void @f6() + to label %ok1 unwind label %lpad1 + +ok1: + ret void + +lpad1: + invoke void @f4() + to label %ok2 unwind label %lpad2 + +ok2: + call void @f8() + unreachable + +lpad2: + unreachable +} + +declare void @f3() + +define void @f4() { + call void @f3() + ret void +} + +declare void @f6() nounwind + +declare void @f8() From tonic at nondot.org Mon Feb 2 22:52:45 2009 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 03 Feb 2009 04:52:45 -0000 Subject: [llvm-commits] [llvm] r63601 - /llvm/branches/release_25/ Message-ID: <200902030452.n134qj8Z004136@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Feb 2 22:52:45 2009 New Revision: 63601 URL: http://llvm.org/viewvc/llvm-project?rev=63601&view=rev Log: Deleting 2.5 branch. Removed: llvm/branches/release_25/ From tonic at nondot.org Mon Feb 2 22:53:40 2009 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 03 Feb 2009 04:53:40 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63602 - /llvm-gcc-4.2/branches/release_25/ Message-ID: <200902030453.n134reOC004193@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Feb 2 22:53:40 2009 New Revision: 63602 URL: http://llvm.org/viewvc/llvm-project?rev=63602&view=rev Log: Delete 2.5 branch Removed: llvm-gcc-4.2/branches/release_25/ From tonic at nondot.org Mon Feb 2 22:54:00 2009 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 03 Feb 2009 04:54:00 -0000 Subject: [llvm-commits] [test-suite] r63603 - /test-suite/branches/release_25/ Message-ID: <200902030454.n134s0I3004217@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Feb 2 22:54:00 2009 New Revision: 63603 URL: http://llvm.org/viewvc/llvm-project?rev=63603&view=rev Log: Deleting 2.5 branch Removed: test-suite/branches/release_25/ From tonic at nondot.org Mon Feb 2 23:07:11 2009 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 03 Feb 2009 05:07:11 -0000 Subject: [llvm-commits] [llvm] r63604 - /llvm/branches/release_25/ Message-ID: <200902030507.n1357BEu004713@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Feb 2 23:07:10 2009 New Revision: 63604 URL: http://llvm.org/viewvc/llvm-project?rev=63604&view=rev Log: Create 2.5 branch. Added: llvm/branches/release_25/ - copied from r63603, llvm/trunk/ From tonic at nondot.org Mon Feb 2 23:07:33 2009 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 03 Feb 2009 05:07:33 -0000 Subject: [llvm-commits] [test-suite] r63605 - /test-suite/branches/release_25/ Message-ID: <200902030507.n1357XkA004758@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Feb 2 23:07:33 2009 New Revision: 63605 URL: http://llvm.org/viewvc/llvm-project?rev=63605&view=rev Log: Create 2.5 branch Added: test-suite/branches/release_25/ - copied from r63604, test-suite/trunk/ From tonic at nondot.org Mon Feb 2 23:08:18 2009 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 03 Feb 2009 05:08:18 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63606 - /llvm-gcc-4.2/branches/release_25/ Message-ID: <200902030508.n1358IPa004812@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Feb 2 23:08:18 2009 New Revision: 63606 URL: http://llvm.org/viewvc/llvm-project?rev=63606&view=rev Log: Creating 2.5 branch Added: llvm-gcc-4.2/branches/release_25/ - copied from r63605, llvm-gcc-4.2/trunk/ From tonic at nondot.org Mon Feb 2 23:28:08 2009 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 03 Feb 2009 05:28:08 -0000 Subject: [llvm-commits] [llvm] r63607 - /llvm/branches/release_25/autoconf/configure.ac Message-ID: <200902030528.n135S8ar005569@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Feb 2 23:28:07 2009 New Revision: 63607 URL: http://llvm.org/viewvc/llvm-project?rev=63607&view=rev Log: Update version number to 2.5. Modified: llvm/branches/release_25/autoconf/configure.ac Modified: llvm/branches/release_25/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/autoconf/configure.ac?rev=63607&r1=63606&r2=63607&view=diff ============================================================================== --- llvm/branches/release_25/autoconf/configure.ac (original) +++ llvm/branches/release_25/autoconf/configure.ac Mon Feb 2 23:28:07 2009 @@ -31,7 +31,7 @@ dnl===-----------------------------------------------------------------------=== dnl Initialize autoconf and define the package name, version number and dnl email address for reporting bugs. -AC_INIT([[llvm]],[[2.6svn]],[llvmbugs at cs.uiuc.edu]) +AC_INIT([[llvm]],[[2.5]],[llvmbugs at cs.uiuc.edu]) dnl Provide a copyright substitution and ensure the copyright notice is included dnl in the output of --version option of the generated configure script. From tonic at nondot.org Mon Feb 2 23:29:49 2009 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 03 Feb 2009 05:29:49 -0000 Subject: [llvm-commits] [llvm] r63608 - /llvm/branches/release_25/configure Message-ID: <200902030529.n135TovH005904@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Feb 2 23:29:49 2009 New Revision: 63608 URL: http://llvm.org/viewvc/llvm-project?rev=63608&view=rev Log: Regenerate configure. Modified: llvm/branches/release_25/configure Modified: llvm/branches/release_25/configure URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/configure?rev=63608&r1=63607&r2=63608&view=diff ============================================================================== --- llvm/branches/release_25/configure (original) +++ llvm/branches/release_25/configure Mon Feb 2 23:29:49 2009 @@ -1,6 +1,6 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.60 for llvm 2.6svn. +# Generated by GNU Autoconf 2.60 for llvm 2.5. # # Report bugs to . # @@ -715,8 +715,8 @@ # Identity of this package. PACKAGE_NAME='llvm' PACKAGE_TARNAME='-llvm-' -PACKAGE_VERSION='2.6svn' -PACKAGE_STRING='llvm 2.6svn' +PACKAGE_VERSION='2.5' +PACKAGE_STRING='llvm 2.5' PACKAGE_BUGREPORT='llvmbugs at cs.uiuc.edu' ac_unique_file="lib/VMCore/Module.cpp" @@ -1463,7 +1463,7 @@ # Omit some internal or obsolete options to make the list less imposing. # This message is too long to be a string in the A/UX 3.1 sh. cat <<_ACEOF -\`configure' configures llvm 2.6svn to adapt to many kinds of systems. +\`configure' configures llvm 2.5 to adapt to many kinds of systems. Usage: $0 [OPTION]... [VAR=VALUE]... @@ -1529,7 +1529,7 @@ if test -n "$ac_init_help"; then case $ac_init_help in - short | recursive ) echo "Configuration of llvm 2.6svn:";; + short | recursive ) echo "Configuration of llvm 2.5:";; esac cat <<\_ACEOF @@ -1664,7 +1664,7 @@ test -n "$ac_init_help" && exit $ac_status if $ac_init_version; then cat <<\_ACEOF -llvm configure 2.6svn +llvm configure 2.5 generated by GNU Autoconf 2.60 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, @@ -1680,7 +1680,7 @@ This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. -It was created by llvm $as_me 2.6svn, which was +It was created by llvm $as_me 2.5, which was generated by GNU Autoconf 2.60. Invocation command line was $ $0 $@ @@ -35005,7 +35005,7 @@ # report actual input values of CONFIG_FILES etc. instead of their # values after options handling. ac_log=" -This file was extended by llvm $as_me 2.6svn, which was +This file was extended by llvm $as_me 2.5, which was generated by GNU Autoconf 2.60. Invocation command line was CONFIG_FILES = $CONFIG_FILES @@ -35058,7 +35058,7 @@ _ACEOF cat >>$CONFIG_STATUS <<_ACEOF ac_cs_version="\\ -llvm config.status 2.6svn +llvm config.status 2.5 configured by $0, generated by GNU Autoconf 2.60, with options \\"`echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" From tonic at nondot.org Mon Feb 2 23:30:46 2009 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 03 Feb 2009 05:30:46 -0000 Subject: [llvm-commits] [test-suite] r63609 - /test-suite/branches/release_25/autoconf/configure.ac Message-ID: <200902030530.n135Uk9j005951@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Feb 2 23:30:45 2009 New Revision: 63609 URL: http://llvm.org/viewvc/llvm-project?rev=63609&view=rev Log: Update version to 2.5. Modified: test-suite/branches/release_25/autoconf/configure.ac Modified: test-suite/branches/release_25/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/test-suite/branches/release_25/autoconf/configure.ac?rev=63609&r1=63608&r2=63609&view=diff ============================================================================== --- test-suite/branches/release_25/autoconf/configure.ac (original) +++ test-suite/branches/release_25/autoconf/configure.ac Mon Feb 2 23:30:45 2009 @@ -1,5 +1,5 @@ dnl Initialize autoconf -AC_INIT([[LLVM-TEST]],[[2.6svn]],[llvmbugs at cs.uiuc.edu]) +AC_INIT([[LLVM-TEST]],[[2.5]],[llvmbugs at cs.uiuc.edu]) dnl Place all of the extra autoconf files into the config subdirectory AC_CONFIG_AUX_DIR([autoconf]) From tonic at nondot.org Mon Feb 2 23:31:31 2009 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 03 Feb 2009 05:31:31 -0000 Subject: [llvm-commits] [test-suite] r63611 - /test-suite/branches/release_25/configure Message-ID: <200902030531.n135VVSK006201@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Feb 2 23:31:31 2009 New Revision: 63611 URL: http://llvm.org/viewvc/llvm-project?rev=63611&view=rev Log: Regenerate configure Modified: test-suite/branches/release_25/configure Modified: test-suite/branches/release_25/configure URL: http://llvm.org/viewvc/llvm-project/test-suite/branches/release_25/configure?rev=63611&r1=63610&r2=63611&view=diff ============================================================================== --- test-suite/branches/release_25/configure (original) +++ test-suite/branches/release_25/configure Mon Feb 2 23:31:31 2009 @@ -1,6 +1,6 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.60 for LLVM-TEST 2.6svn. +# Generated by GNU Autoconf 2.60 for LLVM-TEST 2.5. # # Report bugs to . # @@ -713,8 +713,8 @@ # Identity of this package. PACKAGE_NAME='LLVM-TEST' PACKAGE_TARNAME='-llvm-test-' -PACKAGE_VERSION='2.6svn' -PACKAGE_STRING='LLVM-TEST 2.6svn' +PACKAGE_VERSION='2.5' +PACKAGE_STRING='LLVM-TEST 2.5' PACKAGE_BUGREPORT='llvmbugs at cs.uiuc.edu' ac_unique_file="SingleSource/Benchmarks/Makefile" @@ -1389,7 +1389,7 @@ # Omit some internal or obsolete options to make the list less imposing. # This message is too long to be a string in the A/UX 3.1 sh. cat <<_ACEOF -\`configure' configures LLVM-TEST 2.6svn to adapt to many kinds of systems. +\`configure' configures LLVM-TEST 2.5 to adapt to many kinds of systems. Usage: $0 [OPTION]... [VAR=VALUE]... @@ -1454,7 +1454,7 @@ if test -n "$ac_init_help"; then case $ac_init_help in - short | recursive ) echo "Configuration of LLVM-TEST 2.6svn:";; + short | recursive ) echo "Configuration of LLVM-TEST 2.5:";; esac cat <<\_ACEOF @@ -1576,7 +1576,7 @@ test -n "$ac_init_help" && exit $ac_status if $ac_init_version; then cat <<\_ACEOF -LLVM-TEST configure 2.6svn +LLVM-TEST configure 2.5 generated by GNU Autoconf 2.60 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, @@ -1590,7 +1590,7 @@ This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. -It was created by LLVM-TEST $as_me 2.6svn, which was +It was created by LLVM-TEST $as_me 2.5, which was generated by GNU Autoconf 2.60. Invocation command line was $ $0 $@ @@ -21257,7 +21257,7 @@ # report actual input values of CONFIG_FILES etc. instead of their # values after options handling. ac_log=" -This file was extended by LLVM-TEST $as_me 2.6svn, which was +This file was extended by LLVM-TEST $as_me 2.5, which was generated by GNU Autoconf 2.60. Invocation command line was CONFIG_FILES = $CONFIG_FILES @@ -21304,7 +21304,7 @@ _ACEOF cat >>$CONFIG_STATUS <<_ACEOF ac_cs_version="\\ -LLVM-TEST config.status 2.6svn +LLVM-TEST config.status 2.5 configured by $0, generated by GNU Autoconf 2.60, with options \\"`echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" From tonic at nondot.org Mon Feb 2 23:38:39 2009 From: tonic at nondot.org (Tanya Lattner) Date: Mon, 2 Feb 2009 23:38:39 -0600 Subject: [llvm-commits] CVS: llvm-www/www-index.html Message-ID: <200902030538.n135cd6G006443@zion.cs.uiuc.edu> Changes in directory llvm-www: www-index.html updated: 1.173 -> 1.174 --- Log message: Update release schedule. --- Diffs of the changes: (+6 -6) www-index.html | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) Index: llvm-www/www-index.html diff -u llvm-www/www-index.html:1.173 llvm-www/www-index.html:1.174 --- llvm-www/www-index.html:1.173 Sun Jan 25 23:12:30 2009 +++ llvm-www/www-index.html Mon Feb 2 23:37:37 2009 @@ -106,12 +106,12 @@

    LLVM 2.5 release schedule:

      -
    • Jan 21 - Code Freeze/Branch Creation (9PM PST).
      • -
    • Jan 30 - Pre-release 1 testing begins.
      • -
    • Feb 6 - Pre-release 1 testing ends.
      • -
    • Feb 8 - Pre-release 2 testing begins.
      • -
    • Feb 14 - Pre-release 2 testing ends.
      • -
    • Feb 16 - Release.
      • +
    • Feb 2 - Code Freeze/Branch Creation (9PM PST).
      • +
    • Feb 5 - Pre-release 1 testing begins.
      • +
    • Feb 12 - Pre-release 1 testing ends.
      • +
    • Feb 16 - Pre-release 2 testing begins.
      • +
    • Feb 23 - Pre-release 2 testing ends.
      • +
    • Feb 25 - Release.
    From nicholas at mxc.ca Mon Feb 2 23:53:35 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 02 Feb 2009 21:53:35 -0800 Subject: [llvm-commits] [llvm] r63600 - in /llvm/trunk: lib/Transforms/Utils/InlineFunction.cpp test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll In-Reply-To: <200902030434.n134Ygig003459@zion.cs.uiuc.edu> References: <200902030434.n134Ygig003459@zion.cs.uiuc.edu> Message-ID: <4987DBDF.2090109@mxc.ca> Hi Tanya, Please remove this from the 2.5 branch. It breaks minisat. Nick Lewycky wrote: > Author: nicholas > Date: Mon Feb 2 22:34:40 2009 > New Revision: 63600 > > URL: http://llvm.org/viewvc/llvm-project?rev=63600&view=rev > Log: > Update the callgraph when replacing InvokeInst with CallInst when inlining. > > Added: > llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll > Modified: > llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp > > Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=63600&r1=63599&r2=63600&view=diff > > ============================================================================== > --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) > +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Mon Feb 2 22:34:40 2009 > @@ -37,11 +37,12 @@ > /// in the body of the inlined function into invokes and turn unwind > /// instructions into branches to the invoke unwind dest. > /// > -/// II is the invoke instruction begin inlined. FirstNewBlock is the first > +/// II is the invoke instruction being inlined. FirstNewBlock is the first > /// block of the inlined code (the last block is the end of the function), > /// and InlineCodeInfo is information about the code that got inlined. > static void HandleInlinedInvoke(InvokeInst *II, BasicBlock *FirstNewBlock, > - ClonedCodeInfo &InlinedCodeInfo) { > + ClonedCodeInfo &InlinedCodeInfo, > + CallGraph *CG) { > BasicBlock *InvokeDest = II->getUnwindDest(); > std::vector InvokeDestPHIValues; > > @@ -93,6 +94,10 @@ > // Make sure that anything using the call now uses the invoke! > CI->replaceAllUsesWith(II); > > + // Update the callgraph. > + if (CG) > + (*CG)[Caller]->replaceCallSite(CI, II); > + > // Delete the unconditional branch inserted by splitBasicBlock > BB->getInstList().pop_back(); > Split->getInstList().pop_front(); // Delete the original call > @@ -433,7 +438,7 @@ > // any inlined 'unwind' instructions into branches to the invoke exception > // destination, and call instructions into invoke instructions. > if (InvokeInst *II = dyn_cast(TheCall)) > - HandleInlinedInvoke(II, FirstNewBlock, InlinedFunctionInfo); > + HandleInlinedInvoke(II, FirstNewBlock, InlinedFunctionInfo, CG); > > // If we cloned in _exactly one_ basic block, and if that block ends in a > // return instruction, we splice the body of the inlined callee directly into > > Added: llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll?rev=63600&view=auto > > ============================================================================== > --- llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll (added) > +++ llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll Mon Feb 2 22:34:40 2009 > @@ -0,0 +1,32 @@ > +; RUN: llvm-as < %s | opt -inline -prune-eh > +; PR3367 > + > +define void @f2() { > + invoke void @f6() > + to label %ok1 unwind label %lpad1 > + > +ok1: > + ret void > + > +lpad1: > + invoke void @f4() > + to label %ok2 unwind label %lpad2 > + > +ok2: > + call void @f8() > + unreachable > + > +lpad2: > + unreachable > +} > + > +declare void @f3() > + > +define void @f4() { > + call void @f3() > + ret void > +} > + > +declare void @f6() nounwind > + > +declare void @f8() > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From clattner at apple.com Mon Feb 2 23:56:15 2009 From: clattner at apple.com (Chris Lattner) Date: Mon, 2 Feb 2009 21:56:15 -0800 Subject: [llvm-commits] [llvm] r63600 - in /llvm/trunk: lib/Transforms/Utils/InlineFunction.cpp test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll In-Reply-To: <4987DBDF.2090109@mxc.ca> References: <200902030434.n134Ygig003459@zion.cs.uiuc.edu> <4987DBDF.2090109@mxc.ca> Message-ID: On Feb 2, 2009, at 9:53 PM, Nick Lewycky wrote: > Hi Tanya, > > Please remove this from the 2.5 branch. It breaks minisat. Please revert it from mainline first. -Chris > > > Nick Lewycky wrote: >> Author: nicholas >> Date: Mon Feb 2 22:34:40 2009 >> New Revision: 63600 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=63600&view=rev >> Log: >> Update the callgraph when replacing InvokeInst with CallInst when >> inlining. >> >> Added: >> llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll >> Modified: >> llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp >> >> Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=63600&r1=63599&r2=63600&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) >> +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Mon Feb 2 >> 22:34:40 2009 >> @@ -37,11 +37,12 @@ >> /// in the body of the inlined function into invokes and turn unwind >> /// instructions into branches to the invoke unwind dest. >> /// >> -/// II is the invoke instruction begin inlined. FirstNewBlock is >> the first >> +/// II is the invoke instruction being inlined. FirstNewBlock is >> the first >> /// block of the inlined code (the last block is the end of the >> function), >> /// and InlineCodeInfo is information about the code that got >> inlined. >> static void HandleInlinedInvoke(InvokeInst *II, BasicBlock >> *FirstNewBlock, >> - ClonedCodeInfo &InlinedCodeInfo) { >> + ClonedCodeInfo &InlinedCodeInfo, >> + CallGraph *CG) { >> BasicBlock *InvokeDest = II->getUnwindDest(); >> std::vector InvokeDestPHIValues; >> >> @@ -93,6 +94,10 @@ >> // Make sure that anything using the call now uses the >> invoke! >> CI->replaceAllUsesWith(II); >> >> + // Update the callgraph. >> + if (CG) >> + (*CG)[Caller]->replaceCallSite(CI, II); >> + >> // Delete the unconditional branch inserted by >> splitBasicBlock >> BB->getInstList().pop_back(); >> Split->getInstList().pop_front(); // Delete the original >> call >> @@ -433,7 +438,7 @@ >> // any inlined 'unwind' instructions into branches to the invoke >> exception >> // destination, and call instructions into invoke instructions. >> if (InvokeInst *II = dyn_cast(TheCall)) >> - HandleInlinedInvoke(II, FirstNewBlock, InlinedFunctionInfo); >> + HandleInlinedInvoke(II, FirstNewBlock, InlinedFunctionInfo, CG); >> >> // If we cloned in _exactly one_ basic block, and if that block >> ends in a >> // return instruction, we splice the body of the inlined callee >> directly into >> >> Added: llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll?rev=63600&view=auto >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll >> (added) >> +++ llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll >> Mon Feb 2 22:34:40 2009 >> @@ -0,0 +1,32 @@ >> +; RUN: llvm-as < %s | opt -inline -prune-eh >> +; PR3367 >> + >> +define void @f2() { >> + invoke void @f6() >> + to label %ok1 unwind label %lpad1 >> + >> +ok1: >> + ret void >> + >> +lpad1: >> + invoke void @f4() >> + to label %ok2 unwind label %lpad2 >> + >> +ok2: >> + call void @f8() >> + unreachable >> + >> +lpad2: >> + unreachable >> +} >> + >> +declare void @f3() >> + >> +define void @f4() { >> + call void @f3() >> + ret void >> +} >> + >> +declare void @f6() nounwind >> + >> +declare void @f8() >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From mburke at ea.com Tue Feb 3 00:16:14 2009 From: mburke at ea.com (Burke, Max) Date: Mon, 2 Feb 2009 22:16:14 -0800 Subject: [llvm-commits] Patch: PPC64 subregister moves In-Reply-To: References: Message-ID: >From PPCRegisterInfo.td, a 64-bit GPR is defined as: def X1 : GP8< R1, "r1">, DwarfRegNum<[1]>; With GP8 being: class GP8 : PPCReg { field bits<5> Num = SubReg.Num; let SubRegs = [SubReg]; } So it does look like each 64-bit register has an associated subregister. Do you foresee this still requiring the RegisterWithSubRegs notation that you described below? Thanks for the SUBREG_TO_REG tip: def : Pat<(i64 (zext GPRC:$in)), - (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>; + (SUBREG_TO_REG (i64 0), GPRC:$in, ppc_subreg_32bit)>; This cut down the size of the generated code even more! -Max -----Original Message----- From: Dan Gohman [mailto:gohman at apple.com] Sent: Monday, February 02, 2009 5:17 PM To: Commit Messages and Patches for LLVM Cc: Burke, Max Subject: Re: [llvm-commits] Patch: PPC64 subregister moves On Jan 29, 2009, at 11:36 PM, Burke, Max wrote: > This attempts to reduce the number of emitted OR instructions used to > move data in and out of subregisters on the PPC64 target. We've > noticed > what looks like many extraneous register moves which in some cases are > harmless, others which may have unintended, though minor, side effects > (ie, mr 30, 30 blocking Cell PPE hardware thread at dispatch for 12 > cycles; mr 3, 3 changing the current hardware thread priority to > high). > _______________________________________________ I'm not very familiar with PowerPC, but this patch seems like a reasonably good idea to me. I do have a few comments on it. In this change: def : Pat<(i64 (zext GPRC:$in)), - (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>; + (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, ppc_subreg_32bit), 0, 32)>; For a zext, if this is really what the hardware provides, this should use SUBREG_TO_REG with an (i64 0) for the first operand. See how this is done on x86-64, for example. In the *RegisterInfo.td file, registers that have subregs should be declared with RegisterWithSubRegs, instead of just Register. This may require changing some of the PPC-specific code at the top of the file. Dan From resistor at mac.com Tue Feb 3 00:27:22 2009 From: resistor at mac.com (Owen Anderson) Date: Tue, 03 Feb 2009 06:27:22 -0000 Subject: [llvm-commits] [llvm] r63616 - /llvm/trunk/lib/Analysis/AliasAnalysis.cpp Message-ID: <200902030627.n136RMOA008068@zion.cs.uiuc.edu> Author: resistor Date: Tue Feb 3 00:27:22 2009 New Revision: 63616 URL: http://llvm.org/viewvc/llvm-project?rev=63616&view=rev Log: Teach AliasAnalysis that a bunch of the atomic intrinsics only dereference their arguments. Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=63616&r1=63615&r2=63616&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Tue Feb 3 00:27:22 2009 @@ -28,6 +28,7 @@ #include "llvm/Pass.h" #include "llvm/BasicBlock.h" #include "llvm/Function.h" +#include "llvm/IntrinsicInst.h" #include "llvm/Instructions.h" #include "llvm/Type.h" #include "llvm/Target/TargetData.h" @@ -114,6 +115,27 @@ AliasAnalysis::ModRefBehavior AliasAnalysis::getModRefBehavior(CallSite CS, std::vector *Info) { + if (IntrinsicInst* II = dyn_cast(CS.getInstruction())) { + switch (II->getIntrinsicID()) { + case Intrinsic::atomic_cmp_swap: + case Intrinsic::atomic_load_add: + case Intrinsic::atomic_load_and: + case Intrinsic::atomic_load_max: + case Intrinsic::atomic_load_min: + case Intrinsic::atomic_load_nand: + case Intrinsic::atomic_load_or: + case Intrinsic::atomic_load_sub: + case Intrinsic::atomic_load_umax: + case Intrinsic::atomic_load_umin: + case Intrinsic::atomic_load_xor: + case Intrinsic::atomic_swap: + // CAS and related intrinsics only access their arguments. + return AliasAnalysis::AccessesArguments; + default: + break; + } + } + if (CS.doesNotAccessMemory()) // Can't do better than this. return DoesNotAccessMemory; From nicholas at mxc.ca Tue Feb 3 00:30:37 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 03 Feb 2009 06:30:37 -0000 Subject: [llvm-commits] [llvm] r63618 - in /llvm/trunk: lib/Transforms/Utils/InlineFunction.cpp test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll Message-ID: <200902030630.n136UbUl008194@zion.cs.uiuc.edu> Author: nicholas Date: Tue Feb 3 00:30:37 2009 New Revision: 63618 URL: http://llvm.org/viewvc/llvm-project?rev=63618&view=rev Log: Revert r63600. It didn't fix the bug, it just moved it a bit. Removed: llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=63618&r1=63617&r2=63618&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Tue Feb 3 00:30:37 2009 @@ -41,8 +41,7 @@ /// block of the inlined code (the last block is the end of the function), /// and InlineCodeInfo is information about the code that got inlined. static void HandleInlinedInvoke(InvokeInst *II, BasicBlock *FirstNewBlock, - ClonedCodeInfo &InlinedCodeInfo, - CallGraph *CG) { + ClonedCodeInfo &InlinedCodeInfo) { BasicBlock *InvokeDest = II->getUnwindDest(); std::vector InvokeDestPHIValues; @@ -94,10 +93,6 @@ // Make sure that anything using the call now uses the invoke! CI->replaceAllUsesWith(II); - // Update the callgraph. - if (CG) - (*CG)[Caller]->replaceCallSite(CI, II); - // Delete the unconditional branch inserted by splitBasicBlock BB->getInstList().pop_back(); Split->getInstList().pop_front(); // Delete the original call @@ -438,7 +433,7 @@ // any inlined 'unwind' instructions into branches to the invoke exception // destination, and call instructions into invoke instructions. if (InvokeInst *II = dyn_cast(TheCall)) - HandleInlinedInvoke(II, FirstNewBlock, InlinedFunctionInfo, CG); + HandleInlinedInvoke(II, FirstNewBlock, InlinedFunctionInfo); // If we cloned in _exactly one_ basic block, and if that block ends in a // return instruction, we splice the body of the inlined callee directly into Removed: llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll?rev=63617&view=auto ============================================================================== --- llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll (original) +++ llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll (removed) @@ -1,32 +0,0 @@ -; RUN: llvm-as < %s | opt -inline -prune-eh -; PR3367 - -define void @f2() { - invoke void @f6() - to label %ok1 unwind label %lpad1 - -ok1: - ret void - -lpad1: - invoke void @f4() - to label %ok2 unwind label %lpad2 - -ok2: - call void @f8() - unreachable - -lpad2: - unreachable -} - -declare void @f3() - -define void @f4() { - call void @f3() - ret void -} - -declare void @f6() nounwind - -declare void @f8() From nicholas at mxc.ca Tue Feb 3 00:30:50 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 02 Feb 2009 22:30:50 -0800 Subject: [llvm-commits] [llvm] r63600 - in /llvm/trunk: lib/Transforms/Utils/InlineFunction.cpp test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll In-Reply-To: References: <200902030434.n134Ygig003459@zion.cs.uiuc.edu> <4987DBDF.2090109@mxc.ca> Message-ID: <4987E49A.4060009@mxc.ca> Chris Lattner wrote: > On Feb 2, 2009, at 9:53 PM, Nick Lewycky wrote: > >> Hi Tanya, >> >> Please remove this from the 2.5 branch. It breaks minisat. > > Please revert it from mainline first. Done in r63618. > -Chris > >> >> Nick Lewycky wrote: >>> Author: nicholas >>> Date: Mon Feb 2 22:34:40 2009 >>> New Revision: 63600 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=63600&view=rev >>> Log: >>> Update the callgraph when replacing InvokeInst with CallInst when >>> inlining. >>> >>> Added: >>> llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll >>> Modified: >>> llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp >>> >>> Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=63600&r1=63599&r2=63600&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ===================================================================== >>> --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) >>> +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Mon Feb 2 >>> 22:34:40 2009 >>> @@ -37,11 +37,12 @@ >>> /// in the body of the inlined function into invokes and turn unwind >>> /// instructions into branches to the invoke unwind dest. >>> /// >>> -/// II is the invoke instruction begin inlined. FirstNewBlock is >>> the first >>> +/// II is the invoke instruction being inlined. FirstNewBlock is >>> the first >>> /// block of the inlined code (the last block is the end of the >>> function), >>> /// and InlineCodeInfo is information about the code that got >>> inlined. >>> static void HandleInlinedInvoke(InvokeInst *II, BasicBlock >>> *FirstNewBlock, >>> - ClonedCodeInfo &InlinedCodeInfo) { >>> + ClonedCodeInfo &InlinedCodeInfo, >>> + CallGraph *CG) { >>> BasicBlock *InvokeDest = II->getUnwindDest(); >>> std::vector InvokeDestPHIValues; >>> >>> @@ -93,6 +94,10 @@ >>> // Make sure that anything using the call now uses the >>> invoke! >>> CI->replaceAllUsesWith(II); >>> >>> + // Update the callgraph. >>> + if (CG) >>> + (*CG)[Caller]->replaceCallSite(CI, II); >>> + >>> // Delete the unconditional branch inserted by >>> splitBasicBlock >>> BB->getInstList().pop_back(); >>> Split->getInstList().pop_front(); // Delete the original >>> call >>> @@ -433,7 +438,7 @@ >>> // any inlined 'unwind' instructions into branches to the invoke >>> exception >>> // destination, and call instructions into invoke instructions. >>> if (InvokeInst *II = dyn_cast(TheCall)) >>> - HandleInlinedInvoke(II, FirstNewBlock, InlinedFunctionInfo); >>> + HandleInlinedInvoke(II, FirstNewBlock, InlinedFunctionInfo, CG); >>> >>> // If we cloned in _exactly one_ basic block, and if that block >>> ends in a >>> // return instruction, we splice the body of the inlined callee >>> directly into >>> >>> Added: llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll?rev=63600&view=auto >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ===================================================================== >>> --- llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll >>> (added) >>> +++ llvm/trunk/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll >>> Mon Feb 2 22:34:40 2009 >>> @@ -0,0 +1,32 @@ >>> +; RUN: llvm-as < %s | opt -inline -prune-eh >>> +; PR3367 >>> + >>> +define void @f2() { >>> + invoke void @f6() >>> + to label %ok1 unwind label %lpad1 >>> + >>> +ok1: >>> + ret void >>> + >>> +lpad1: >>> + invoke void @f4() >>> + to label %ok2 unwind label %lpad2 >>> + >>> +ok2: >>> + call void @f8() >>> + unreachable >>> + >>> +lpad2: >>> + unreachable >>> +} >>> + >>> +declare void @f3() >>> + >>> +define void @f4() { >>> + call void @f3() >>> + ret void >>> +} >>> + >>> +declare void @f6() nounwind >>> + >>> +declare void @f8() >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From sabre at nondot.org Tue Feb 3 01:08:57 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Feb 2009 07:08:57 -0000 Subject: [llvm-commits] [llvm] r63620 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/badarray.ll Message-ID: <200902030708.n1378vIZ009515@zion.cs.uiuc.edu> Author: lattner Date: Tue Feb 3 01:08:57 2009 New Revision: 63620 URL: http://llvm.org/viewvc/llvm-project?rev=63620&view=rev Log: add another case of undefined behavior without crashing, PR3466. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/trunk/test/Transforms/ScalarRepl/badarray.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=63620&r1=63619&r2=63620&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Tue Feb 3 01:08:57 2009 @@ -1431,8 +1431,9 @@ // Finally, unconditionally truncate the integer to the right width. unsigned LIBitWidth = TD->getTypeSizeInBits(LI->getType()); if (LIBitWidth < NTy->getBitWidth()) - NV = new TruncInst(NV, IntegerType::get(LIBitWidth), - LI->getName(), LI); + NV = new TruncInst(NV, IntegerType::get(LIBitWidth), LI->getName(), LI); + else if (LIBitWidth > NTy->getBitWidth()) + NV = new ZExtInst(NV, IntegerType::get(LIBitWidth), LI->getName(), LI); // If the result is an integer, this is a trunc or bitcast. if (isa(LI->getType())) { Modified: llvm/trunk/test/Transforms/ScalarRepl/badarray.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/badarray.ll?rev=63620&r1=63619&r2=63620&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/badarray.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/badarray.ll Tue Feb 3 01:08:57 2009 @@ -1,4 +1,5 @@ ; RUN: llvm-as < %s | opt -scalarrepl -instcombine | llvm-dis | not grep alloca +; PR3466 define i32 @test() { %X = alloca [4 x i32] ; <[4 x i32]*> [#uses=1] @@ -9,3 +10,11 @@ ret i32 %Z } + +define i32 @test2() nounwind { +entry: + %yx2.i = alloca float, align 4 ; [#uses=1] + %yx26.i = bitcast float* %yx2.i to i64* ; [#uses=1] + %0 = load i64* %yx26.i, align 8 ; [#uses=0] + unreachable +} From nicholas at mxc.ca Tue Feb 3 01:10:08 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 03 Feb 2009 07:10:08 -0000 Subject: [llvm-commits] [llvm] r63621 - in /llvm/trunk: Makefile.config.in autoconf/configure.ac Message-ID: <200902030710.n137A8KE009584@zion.cs.uiuc.edu> Author: nicholas Date: Tue Feb 3 01:10:08 2009 New Revision: 63621 URL: http://llvm.org/viewvc/llvm-project?rev=63621&view=rev Log: Add the ability to pass the path to binutils source to configure. This is needed to build the LLVM gold plugin. Modified: llvm/trunk/Makefile.config.in llvm/trunk/autoconf/configure.ac Modified: llvm/trunk/Makefile.config.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.config.in?rev=63621&r1=63620&r2=63621&view=diff ============================================================================== --- llvm/trunk/Makefile.config.in (original) +++ llvm/trunk/Makefile.config.in Tue Feb 3 01:10:08 2009 @@ -283,3 +283,6 @@ else SYSPATH = $(1) endif + +# Location of the plugin header file for gold. +BINUTILS_INCDIR := @BINUTILS_INCDIR@ Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=63621&r1=63620&r2=63621&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Tue Feb 3 01:10:08 2009 @@ -514,6 +514,24 @@ *) AC_MSG_ERROR([Invalid path for --with-ocaml-libdir. Provide full path]) ;; esac +dnl Allow linking of LLVM with GPLv3 binutils code. +AC_ARG_WITH(binutils-include, + AS_HELP_STRING([--with-binutils-include], + [Specify path to binutils/include/ containing plugin-api.h file for gold plugin.]),, + withval=default) +case "$withval" in + default) WITH_BINUTILS_INCDIR=default ;; + /* | [[A-Za-z]]:[[\\/]]*) WITH_BINUTILS_INCDIR=$withval ;; + *) AC_MSG_ERROR([Invalid path for --with-binutils-include. Provide full path]) ;; +esac +if test "x$WITH_BINUTILS_INCDIR" != xdefault ; then + AC_SUBST(BINUTILS_INCDIR,$WITH_BINUTILS_INCDIR) + if test ! -f "$WITH_BINUTILS_INCDIR/plugin-api.h"; then + echo "$WITH_BINUTILS_INCDIR/plugin-api.h" + AC_MSG_ERROR([Invalid path to directory containing plugin-api.h.]); + fi +fi + dnl===-----------------------------------------------------------------------=== dnl=== dnl=== SECTION 4: Check for programs we need and that they are the right version From nicholas at mxc.ca Tue Feb 3 01:10:30 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 03 Feb 2009 07:10:30 -0000 Subject: [llvm-commits] [llvm] r63622 - /llvm/trunk/configure Message-ID: <200902030710.n137AVZh009609@zion.cs.uiuc.edu> Author: nicholas Date: Tue Feb 3 01:10:30 2009 New Revision: 63622 URL: http://llvm.org/viewvc/llvm-project?rev=63622&view=rev Log: Regenerate configure. Modified: llvm/trunk/configure Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=63622&r1=63621&r2=63622&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Tue Feb 3 01:10:30 2009 @@ -842,6 +842,7 @@ TARGETS_TO_BUILD ENABLE_CBE_PRINTF_A EXTRA_OPTIONS +BINUTILS_INCDIR CXX CXXFLAGS ac_ct_CXX @@ -1574,6 +1575,8 @@ --with-extra-options Specify addtional options to compile LLVM with --with-ocaml-libdir Specify install location for ocaml bindings (default is stdlib) + --with-binutils-include Specify path to binutils/include/ containing + plugin-api.h file for gold plugin. --with-tclinclude directory where tcl headers are --with-gnu-ld assume the C compiler uses GNU ld [default=no] --with-pic try to use only PIC/non-PIC objects [default=use @@ -5063,6 +5066,32 @@ esac +# Check whether --with-binutils-include was given. +if test "${with_binutils_include+set}" = set; then + withval=$with_binutils_include; +else + withval=default +fi + +case "$withval" in + default) WITH_BINUTILS_INCDIR=default ;; + /* | [A-Za-z]:[\\/]*) WITH_BINUTILS_INCDIR=$withval ;; + *) { { echo "$as_me:$LINENO: error: Invalid path for --with-binutils-include. Provide full path" >&5 +echo "$as_me: error: Invalid path for --with-binutils-include. Provide full path" >&2;} + { (exit 1); exit 1; }; } ;; +esac +if test "x$WITH_BINUTILS_INCDIR" != xdefault ; then + BINUTILS_INCDIR=$WITH_BINUTILS_INCDIR + + if test ! -f "$WITH_BINUTILS_INCDIR/plugin-api.h"; then + echo "$WITH_BINUTILS_INCDIR/plugin-api.h" + { { echo "$as_me:$LINENO: error: Invalid path to directory containing plugin-api.h." >&5 +echo "$as_me: error: Invalid path to directory containing plugin-api.h." >&2;} + { (exit 1); exit 1; }; }; + fi +fi + + ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' @@ -10832,7 +10861,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext + echo '#line 13008 "configure"' > conftest.$ac_ext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 (eval $ac_compile) 2>&5 ac_status=$? @@ -14694,11 +14723,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:14697: $lt_compile\"" >&5) + (eval echo "\"\$as_me:14726: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:14701: \$? = $ac_status" >&5 + echo "$as_me:14730: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -14962,11 +14991,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:14965: $lt_compile\"" >&5) + (eval echo "\"\$as_me:14994: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:14969: \$? = $ac_status" >&5 + echo "$as_me:14998: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -15066,11 +15095,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:15069: $lt_compile\"" >&5) + (eval echo "\"\$as_me:15098: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:15073: \$? = $ac_status" >&5 + echo "$as_me:15102: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -17518,7 +17547,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext <&5) + (eval echo "\"\$as_me:20018: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:19993: \$? = $ac_status" >&5 + echo "$as_me:20022: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -20090,11 +20119,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:20093: $lt_compile\"" >&5) + (eval echo "\"\$as_me:20122: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:20097: \$? = $ac_status" >&5 + echo "$as_me:20126: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -21660,11 +21689,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21663: $lt_compile\"" >&5) + (eval echo "\"\$as_me:21692: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:21667: \$? = $ac_status" >&5 + echo "$as_me:21696: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -21764,11 +21793,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21767: $lt_compile\"" >&5) + (eval echo "\"\$as_me:21796: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:21771: \$? = $ac_status" >&5 + echo "$as_me:21800: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -23999,11 +24028,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:24002: $lt_compile\"" >&5) + (eval echo "\"\$as_me:24031: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:24006: \$? = $ac_status" >&5 + echo "$as_me:24035: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -24267,11 +24296,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:24270: $lt_compile\"" >&5) + (eval echo "\"\$as_me:24299: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:24274: \$? = $ac_status" >&5 + echo "$as_me:24303: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -24371,11 +24400,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:24374: $lt_compile\"" >&5) + (eval echo "\"\$as_me:24403: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:24378: \$? = $ac_status" >&5 + echo "$as_me:24407: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -35342,6 +35371,7 @@ TARGETS_TO_BUILD!$TARGETS_TO_BUILD$ac_delim ENABLE_CBE_PRINTF_A!$ENABLE_CBE_PRINTF_A$ac_delim EXTRA_OPTIONS!$EXTRA_OPTIONS$ac_delim +BINUTILS_INCDIR!$BINUTILS_INCDIR$ac_delim CXX!$CXX$ac_delim CXXFLAGS!$CXXFLAGS$ac_delim ac_ct_CXX!$ac_ct_CXX$ac_delim @@ -35352,7 +35382,6 @@ YACC!$YACC$ac_delim YFLAGS!$YFLAGS$ac_delim BISON!$BISON$ac_delim -NM!$NM$ac_delim _ACEOF if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 97; then @@ -35394,6 +35423,7 @@ ac_delim='%!_!# ' for ac_last_try in false false false false false :; do cat >conf$$subs.sed <<_ACEOF +NM!$NM$ac_delim ifGNUmake!$ifGNUmake$ac_delim LN_S!$LN_S$ac_delim CMP!$CMP$ac_delim @@ -35476,7 +35506,7 @@ LTLIBOBJS!$LTLIBOBJS$ac_delim _ACEOF - if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 80; then + if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 81; then break elif $ac_last_try; then { { echo "$as_me:$LINENO: error: could not make $CONFIG_STATUS" >&5 From nicholas at mxc.ca Tue Feb 3 01:13:25 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 03 Feb 2009 07:13:25 -0000 Subject: [llvm-commits] [llvm] r63623 - in /llvm/trunk/tools: Makefile gold/ gold/Makefile gold/README.txt gold/gold-plugin.cpp Message-ID: <200902030713.n137DP9o009780@zion.cs.uiuc.edu> Author: nicholas Date: Tue Feb 3 01:13:24 2009 New Revision: 63623 URL: http://llvm.org/viewvc/llvm-project?rev=63623&view=rev Log: Add LLVM plugin for gold. Added: llvm/trunk/tools/gold/ llvm/trunk/tools/gold/Makefile llvm/trunk/tools/gold/README.txt llvm/trunk/tools/gold/gold-plugin.cpp Modified: llvm/trunk/tools/Makefile Modified: llvm/trunk/tools/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/Makefile?rev=63623&r1=63622&r2=63623&view=diff ============================================================================== --- llvm/trunk/tools/Makefile (original) +++ llvm/trunk/tools/Makefile Tue Feb 3 01:13:24 2009 @@ -27,6 +27,10 @@ ifeq ($(ENABLE_PIC),1) PARALLEL_DIRS += lto + +ifdef BINUTILS_INCDIR +PARALLEL_DIRS += gold +endif endif include $(LEVEL)/Makefile.common Added: llvm/trunk/tools/gold/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/Makefile?rev=63623&view=auto ============================================================================== --- llvm/trunk/tools/gold/Makefile (added) +++ llvm/trunk/tools/gold/Makefile Tue Feb 3 01:13:24 2009 @@ -0,0 +1,29 @@ +#===- tools/gold/Makefile ----------------------------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../.. +LIBRARYNAME = LLVMgold + +# Include this here so we can get the configuration of the targets +# that have been configured for construction. We have to do this +# early so we can set up LINK_COMPONENTS before including Makefile.rules +include $(LEVEL)/Makefile.config + +LINK_LIBS_IN_SHARED=1 +SHARED_LIBRARY = 1 +BUILD_ARCHIVE = 0 +DONT_BUILD_RELINKED = 1 + +LINK_COMPONENTS := + +include $(LEVEL)/Makefile.common + +# Because off_t is used in the public API, the largefile parts are required for +# ABI compatibility. +CXXFLAGS+=-I$(BINUTILS_INCDIR) -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -lLTO Added: llvm/trunk/tools/gold/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/README.txt?rev=63623&view=auto ============================================================================== --- llvm/trunk/tools/gold/README.txt (added) +++ llvm/trunk/tools/gold/README.txt Tue Feb 3 01:13:24 2009 @@ -0,0 +1,17 @@ +This directory contains a plugin that is designed to work with binutils +gold linker. At present time, this is not the default linker in +binutils, and the default build of gold does not support plugins. + +Obtaining binutils: + + cvs -z 9 -d :pserver:anoncvs at sourceware.org:/cvs/src login + {enter "anoncvs" as the password} + cvs -z 9 -d :pserver:anoncvs at sourceware.org:/cvs/src co binutils + +This will create a src/ directory. Make a build/ directory and from +there configure binutils with "../src/configure --enable-gold --enable-plugins". +Then build binutils with "make all-gold". + +To build the LLVMgold plugin, configure LLVM with the option +--with-binutils-include=/path/to/binutils/src/include/ . To use the +plugin, run "ld-new --plugin /path/to/libLLVMgold.so". Added: llvm/trunk/tools/gold/gold-plugin.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/gold-plugin.cpp?rev=63623&view=auto ============================================================================== --- llvm/trunk/tools/gold/gold-plugin.cpp (added) +++ llvm/trunk/tools/gold/gold-plugin.cpp Tue Feb 3 01:13:24 2009 @@ -0,0 +1,327 @@ +//===-- gold-plugin.cpp - Plugin to gold for Link Time Optimization ------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This is a gold plugin for LLVM. It provides an LLVM implementation of the +// interface described in http://gcc.gnu.org/wiki/whopr/driver . +// +//===----------------------------------------------------------------------===// + +#include "plugin-api.h" + +#include "llvm-c/lto.h" + +#include "llvm/Support/raw_ostream.h" +#include "llvm/System/Path.h" + +#include +#include +#include +#include + +using namespace llvm; + +namespace { + ld_plugin_status discard_message(int level, const char *format, ...) { + // Die loudly. Recent versions of Gold pass ld_plugin_message as the first + // callback in the transfer vector. This should never be called. + abort(); + } + + ld_plugin_add_symbols add_symbols = NULL; + ld_plugin_get_symbols get_symbols = NULL; + ld_plugin_add_input_file add_input_file = NULL; + ld_plugin_message message = discard_message; + + int api_version = 0; + int gold_version = 0; + + struct claimed_file { + lto_module_t M; + void *handle; + std::vector syms; + }; + + lto_codegen_model output_type = LTO_CODEGEN_PIC_MODEL_STATIC; + std::list Modules; + std::vector Cleanup; +} + +ld_plugin_status claim_file_hook(const ld_plugin_input_file *file, + int *claimed); +ld_plugin_status all_symbols_read_hook(void); +ld_plugin_status cleanup_hook(void); + +extern "C" ld_plugin_status onload(ld_plugin_tv *tv); +ld_plugin_status onload(ld_plugin_tv *tv) { + // We're given a pointer to the first transfer vector. We read through them + // until we find one where tv_tag == LDPT_NULL. The REGISTER_* tagged values + // contain pointers to functions that we need to call to register our own + // hooks. The others are addresses of functions we can use to call into gold + // for services. + + bool registeredClaimFile = false; + bool registeredAllSymbolsRead = false; + bool registeredCleanup = false; + + for (; tv->tv_tag != LDPT_NULL; ++tv) { + switch (tv->tv_tag) { + case LDPT_API_VERSION: + api_version = tv->tv_u.tv_val; + break; + case LDPT_GOLD_VERSION: // major * 100 + minor + gold_version = tv->tv_u.tv_val; + break; + case LDPT_LINKER_OUTPUT: + switch (tv->tv_u.tv_val) { + case LDPO_REL: // .o + case LDPO_DYN: // .so + output_type = LTO_CODEGEN_PIC_MODEL_DYNAMIC; + break; + case LDPO_EXEC: // .exe + output_type = LTO_CODEGEN_PIC_MODEL_STATIC; + break; + default: + (*message)(LDPL_ERROR, "Unknown output file type %d", + tv->tv_u.tv_val); + return LDPS_ERR; + } + // TODO: add an option to disable PIC. + //output_type = LTO_CODEGEN_PIC_MODEL_DYNAMIC_NO_PIC; + break; + case LDPT_OPTION: + (*message)(LDPL_WARNING, "Ignoring flag %s", tv->tv_u.tv_string); + break; + case LDPT_REGISTER_CLAIM_FILE_HOOK: { + ld_plugin_register_claim_file callback; + callback = tv->tv_u.tv_register_claim_file; + + if ((*callback)(claim_file_hook) != LDPS_OK) + return LDPS_ERR; + + registeredClaimFile = true; + } break; + case LDPT_REGISTER_ALL_SYMBOLS_READ_HOOK: { + ld_plugin_register_all_symbols_read callback; + callback = tv->tv_u.tv_register_all_symbols_read; + + if ((*callback)(all_symbols_read_hook) != LDPS_OK) + return LDPS_ERR; + + registeredAllSymbolsRead = true; + } break; + case LDPT_REGISTER_CLEANUP_HOOK: { + ld_plugin_register_cleanup callback; + callback = tv->tv_u.tv_register_cleanup; + + if ((*callback)(cleanup_hook) != LDPS_OK) + return LDPS_ERR; + + registeredCleanup = true; + } break; + case LDPT_ADD_SYMBOLS: + add_symbols = tv->tv_u.tv_add_symbols; + break; + case LDPT_GET_SYMBOLS: + get_symbols = tv->tv_u.tv_get_symbols; + break; + case LDPT_ADD_INPUT_FILE: + add_input_file = tv->tv_u.tv_add_input_file; + break; + case LDPT_MESSAGE: + message = tv->tv_u.tv_message; + break; + default: + break; + } + } + + if (!registeredClaimFile || !registeredAllSymbolsRead || !registeredCleanup || + !add_symbols || !get_symbols || !add_input_file) { + (*message)(LDPL_ERROR, "Not all hooks registered for LLVMgold."); + return LDPS_ERR; + } + + return LDPS_OK; +} + +/// claim_file_hook - called by gold to see whether this file is one that +/// our plugin can handle. We'll try to open it and register all the symbols +/// with add_symbol if possible. +ld_plugin_status claim_file_hook(const ld_plugin_input_file *file, + int *claimed) { + // If set, this means gold found IR in an ELF section. LLVM doesn't wrap its + // IR in ELF, so we know it's not us. + if (file->offset) + return LDPS_OK; + + if (!lto_module_is_object_file(file->name)) + return LDPS_OK; + + *claimed = 1; + Modules.resize(Modules.size() + 1); + claimed_file &cf = Modules.back(); + + cf.M = lto_module_create(file->name); + if (!cf.M) { + (*message)(LDPL_ERROR, "Failed to create LLVM module: %s", + lto_get_error_message()); + return LDPS_ERR; + } + cf.handle = file->handle; + unsigned sym_count = lto_module_get_num_symbols(cf.M); + cf.syms.reserve(sym_count); + + for (unsigned i = 0; i != sym_count; ++i) { + lto_symbol_attributes attrs = lto_module_get_symbol_attribute(cf.M, i); + if ((attrs & LTO_SYMBOL_SCOPE_MASK) == LTO_SYMBOL_SCOPE_INTERNAL) + continue; + + cf.syms.push_back(ld_plugin_symbol()); + ld_plugin_symbol &sym = cf.syms.back(); + sym.name = const_cast(lto_module_get_symbol_name(cf.M, i)); + sym.version = NULL; + + int scope = attrs & LTO_SYMBOL_SCOPE_MASK; + switch (scope) { + case LTO_SYMBOL_SCOPE_HIDDEN: + sym.visibility = LDPV_HIDDEN; + break; + case LTO_SYMBOL_SCOPE_PROTECTED: + sym.visibility = LDPV_PROTECTED; + break; + case 0: // extern + case LTO_SYMBOL_SCOPE_DEFAULT: + sym.visibility = LDPV_DEFAULT; + break; + default: + (*message)(LDPL_ERROR, "Unknown scope attribute: %d", scope); + return LDPS_ERR; + } + + int definition = attrs & LTO_SYMBOL_DEFINITION_MASK; + switch (definition) { + case LTO_SYMBOL_DEFINITION_REGULAR: + sym.def = LDPK_DEF; + break; + case LTO_SYMBOL_DEFINITION_UNDEFINED: + sym.def = LDPK_UNDEF; + break; + case LTO_SYMBOL_DEFINITION_TENTATIVE: + sym.def = LDPK_COMMON; + break; + case LTO_SYMBOL_DEFINITION_WEAK: + sym.def = LDPK_WEAKDEF; + break; + default: + (*message)(LDPL_ERROR, "Unknown definition attribute: %d", definition); + return LDPS_ERR; + } + + // LLVM never emits COMDAT. + sym.size = 0; + sym.comdat_key = NULL; + + sym.resolution = LDPR_UNKNOWN; + } + + cf.syms.reserve(cf.syms.size()); + + if (!cf.syms.empty()) { + if ((*add_symbols)(cf.handle, cf.syms.size(), &cf.syms[0]) != LDPS_OK) { + (*message)(LDPL_ERROR, "Unable to add symbols!"); + return LDPS_ERR; + } + } + + return LDPS_OK; +} + +/// all_symbols_read_hook - gold informs us that all symbols have been read. +/// At this point, we use get_symbols to see if any of our definitions have +/// been overridden by a native object file. Then, perform optimization and +/// codegen. +ld_plugin_status all_symbols_read_hook(void) { + lto_code_gen_t cg = lto_codegen_create(); + + for (std::list::iterator I = Modules.begin(), + E = Modules.end(); I != E; ++I) + lto_codegen_add_module(cg, I->M); + + // If we don't preserve any symbols, libLTO will assume that all symbols are + // needed. Keep all symbols unless we're producing a final executable. + if (output_type == LTO_CODEGEN_PIC_MODEL_STATIC) { + bool anySymbolsPreserved = false; + for (std::list::iterator I = Modules.begin(), + E = Modules.end(); I != E; ++I) { + (*get_symbols)(I->handle, I->syms.size(), &I->syms[0]); + for (unsigned i = 0, e = I->syms.size(); i != e; i++) { + (*message)(LDPL_WARNING, "def: %d visibility: %d resolution %d", + I->syms[i].def, I->syms[i].visibility, I->syms[i].resolution); + if (I->syms[i].resolution == LDPR_PREVAILING_DEF) { + lto_codegen_add_must_preserve_symbol(cg, I->syms[i].name); + anySymbolsPreserved = true; + } + } + } + + if (!anySymbolsPreserved) { + // This entire file is unnecessary! + lto_codegen_dispose(cg); + return LDPS_OK; + } + } + + lto_codegen_set_pic_model(cg, output_type); + lto_codegen_set_debug_model(cg, LTO_DEBUG_MODEL_DWARF); + + size_t bufsize = 0; + const char *buffer = static_cast(lto_codegen_compile(cg, + &bufsize)); + + std::string ErrMsg; + + sys::Path uniqueObjPath("/tmp/llvmgold.o"); + if (uniqueObjPath.createTemporaryFileOnDisk(true, &ErrMsg)) { + (*message)(LDPL_ERROR, "%s", ErrMsg.c_str()); + return LDPS_ERR; + } + raw_fd_ostream *objFile = new raw_fd_ostream(uniqueObjPath.c_str(), true, + ErrMsg); + if (!ErrMsg.empty()) { + delete objFile; + (*message)(LDPL_ERROR, "%s", ErrMsg.c_str()); + return LDPS_ERR; + } + + objFile->write(buffer, bufsize); + objFile->close(); + + lto_codegen_dispose(cg); + + if ((*add_input_file)(const_cast(uniqueObjPath.c_str())) != LDPS_OK) { + (*message)(LDPL_ERROR, "Unable to add .o file to the link."); + (*message)(LDPL_ERROR, "File left behind in: %s", uniqueObjPath.c_str()); + return LDPS_ERR; + } + + Cleanup.push_back(uniqueObjPath); + + return LDPS_OK; +} + +ld_plugin_status cleanup_hook(void) { + std::string ErrMsg; + + for (int i = 0, e = Cleanup.size(); i != e; ++i) + if (Cleanup[i].eraseFromDisk(false, &ErrMsg)) + (*message)(LDPL_ERROR, "Failed to delete '%s': %s", Cleanup[i].c_str(), + ErrMsg.c_str()); + + return LDPS_OK; +} From sabre at nondot.org Tue Feb 3 01:39:50 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Feb 2009 07:39:50 -0000 Subject: [llvm-commits] [llvm] r63629 - /llvm/trunk/include/llvm/Support/Allocator.h Message-ID: <200902030739.n137dowP010835@zion.cs.uiuc.edu> Author: lattner Date: Tue Feb 3 01:39:50 2009 New Revision: 63629 URL: http://llvm.org/viewvc/llvm-project?rev=63629&view=rev Log: add a method to BumpPtrAllocator that allows allocating elements with a specified alignment. Modified: llvm/trunk/include/llvm/Support/Allocator.h Modified: llvm/trunk/include/llvm/Support/Allocator.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Allocator.h?rev=63629&r1=63628&r2=63629&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Allocator.h (original) +++ llvm/trunk/include/llvm/Support/Allocator.h Tue Feb 3 01:39:50 2009 @@ -58,16 +58,30 @@ void *Allocate(size_t Size, size_t Alignment); + /// Allocate space, but do not construct, one object. + /// template T *Allocate() { return static_cast(Allocate(sizeof(T),AlignOf::Alignment)); } + /// Allocate space for an array of objects. This does not construct the + /// objects though. template T *Allocate(size_t Num) { return static_cast(Allocate(Num * sizeof(T), AlignOf::Alignment)); } + /// Allocate space for a specific count of elements and with a specified + /// alignment. + template + T *Allocate(size_t Num, unsigned Alignment) { + // Round EltSize up to the specified alignment. + unsigned EltSize = (sizeof(T)+Alignment-1)&~Alignment; + return static_cast(Allocate(Num * EltSize, Alignment)); + } + + void Deallocate(void * /*Ptr*/) {} void PrintStats() const; From edwintorok at gmail.com Tue Feb 3 02:19:52 2009 From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=) Date: Tue, 03 Feb 2009 10:19:52 +0200 Subject: [llvm-commits] [llvm] r63495 - in /llvm/trunk: lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86Subtarget.cpp test/CodeGen/X86/2009-01-25-NoSSE.ll test/CodeGen/X86/nosse-varargs.ll In-Reply-To: <48AEE04E-B252-42D3-A1A0-462BC7A13CA4@apple.com> References: <200902011815.n11IFvlY018701@zion.cs.uiuc.edu> <6A755BA8-4308-4238-A143-4332545A8F91@apple.com> <49875DB4.4050600@gmail.com> <8BAA0D72-F5D7-49B2-81A5-5DAC116887E0@apple.com> <49876C5E.9030408@gmail.com> <48AEE04E-B252-42D3-A1A0-462BC7A13CA4@apple.com> Message-ID: <4987FE28.9070409@gmail.com> On 2009-02-03 00:54, Dan Gohman wrote: > Thanks. Was the failure you saw test/CodeGen/X86/extractelement-load.ll? > Probably. I just updated to TOT and I see no more failures. > That's actually a bug in the test, and I just fixed it. I'll finish up > moving the above code. Thanks for taking care of this! Best regards, --Edwin From baldrick at free.fr Tue Feb 3 03:42:11 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 3 Feb 2009 10:42:11 +0100 Subject: [llvm-commits] [llvm] r63623 - in /llvm/trunk/tools: Makefile gold/ gold/Makefile gold/README.txt gold/gold-plugin.cpp In-Reply-To: <200902030713.n137DP9o009780@zion.cs.uiuc.edu> References: <200902030713.n137DP9o009780@zion.cs.uiuc.edu> Message-ID: <200902031042.11251.baldrick@free.fr> Hey Nick, > Add LLVM plugin for gold. this is great! It's like Christmas a second time :) Ciao, Duncan. From evan.cheng at apple.com Tue Feb 3 04:05:19 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 03 Feb 2009 10:05:19 -0000 Subject: [llvm-commits] [llvm] r63631 - in /llvm/trunk: lib/Transforms/Scalar/InstructionCombining.cpp test/Transforms/InstCombine/vec_demanded_elts-2.ll Message-ID: <200902031005.n13A5LD5025221@zion.cs.uiuc.edu> Author: evancheng Date: Tue Feb 3 04:05:09 2009 New Revision: 63631 URL: http://llvm.org/viewvc/llvm-project?rev=63631&view=rev Log: APInt'fy SimplifyDemandedVectorElts so it can analyze vectors with more than 64 elements. Added: llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts-2.ll Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=63631&r1=63630&r2=63631&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Tue Feb 3 04:05:09 2009 @@ -352,8 +352,8 @@ /// properties that allow us to simplify its operands. bool SimplifyDemandedInstructionBits(Instruction &Inst); - Value *SimplifyDemandedVectorElts(Value *V, uint64_t DemandedElts, - uint64_t &UndefElts, unsigned Depth = 0); + Value *SimplifyDemandedVectorElts(Value *V, APInt DemandedElts, + APInt& UndefElts, unsigned Depth = 0); // FoldOpIntoPhi - Given a binary operator or cast instruction which has a // PHI node as operand #0, see if we can fold the instruction into the PHI @@ -1396,19 +1396,18 @@ /// SimplifyDemandedVectorElts - The specified value produces a vector with -/// 64 or fewer elements. DemandedElts contains the set of elements that are +/// any number of elements. DemandedElts contains the set of elements that are /// actually used by the caller. This method analyzes which elements of the /// operand are undef and returns that information in UndefElts. /// /// If the information about demanded elements can be used to simplify the /// operation, the operation is simplified, then the resultant value is /// returned. This returns null if no change was made. -Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, uint64_t DemandedElts, - uint64_t &UndefElts, +Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts, + APInt& UndefElts, unsigned Depth) { unsigned VWidth = cast(V->getType())->getNumElements(); - assert(VWidth <= 64 && "Vector too wide to analyze!"); - uint64_t EltMask = ~0ULL >> (64-VWidth); + APInt EltMask(APInt::getAllOnesValue(VWidth)); assert((DemandedElts & ~EltMask) == 0 && "Invalid DemandedElts!"); if (isa(V)) { @@ -1427,12 +1426,12 @@ std::vector Elts; for (unsigned i = 0; i != VWidth; ++i) - if (!(DemandedElts & (1ULL << i))) { // If not demanded, set to undef. + if (!DemandedElts[i]) { // If not demanded, set to undef. Elts.push_back(Undef); - UndefElts |= (1ULL << i); + UndefElts.set(i); } else if (isa(CP->getOperand(i))) { // Already undef. Elts.push_back(Undef); - UndefElts |= (1ULL << i); + UndefElts.set(i); } else { // Otherwise, defined. Elts.push_back(CP->getOperand(i)); } @@ -1453,8 +1452,10 @@ Constant *Zero = Constant::getNullValue(EltTy); Constant *Undef = UndefValue::get(EltTy); std::vector Elts; - for (unsigned i = 0; i != VWidth; ++i) - Elts.push_back((DemandedElts & (1ULL << i)) ? Zero : Undef); + for (unsigned i = 0; i != VWidth; ++i) { + Constant *Elt = DemandedElts[i] ? Zero : Undef; + Elts.push_back(Elt); + } UndefElts = DemandedElts ^ EltMask; return ConstantVector::get(Elts); } @@ -1482,7 +1483,7 @@ if (!I) return false; // Only analyze instructions. bool MadeChange = false; - uint64_t UndefElts2; + APInt UndefElts2(VWidth, 0); Value *TmpV; switch (I->getOpcode()) { default: break; @@ -1503,35 +1504,36 @@ // If this is inserting an element that isn't demanded, remove this // insertelement. unsigned IdxNo = Idx->getZExtValue(); - if (IdxNo >= VWidth || (DemandedElts & (1ULL << IdxNo)) == 0) + if (IdxNo >= VWidth || !DemandedElts[IdxNo]) return AddSoonDeadInstToWorklist(*I, 0); // Otherwise, the element inserted overwrites whatever was there, so the // input demanded set is simpler than the output set. - TmpV = SimplifyDemandedVectorElts(I->getOperand(0), - DemandedElts & ~(1ULL << IdxNo), + APInt DemandedElts2 = DemandedElts; + DemandedElts2.clear(IdxNo); + TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts2, UndefElts, Depth+1); if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; } // The inserted element is defined. - UndefElts &= ~(1ULL << IdxNo); + UndefElts.clear(IdxNo); break; } case Instruction::ShuffleVector: { ShuffleVectorInst *Shuffle = cast(I); uint64_t LHSVWidth = cast(Shuffle->getOperand(0)->getType())->getNumElements(); - uint64_t LeftDemanded = 0, RightDemanded = 0; + APInt LeftDemanded(LHSVWidth, 0), RightDemanded(LHSVWidth, 0); for (unsigned i = 0; i < VWidth; i++) { - if (DemandedElts & (1ULL << i)) { + if (DemandedElts[i]) { unsigned MaskVal = Shuffle->getMaskValue(i); if (MaskVal != -1u) { assert(MaskVal < LHSVWidth * 2 && "shufflevector mask index out of range!"); if (MaskVal < LHSVWidth) - LeftDemanded |= 1ULL << MaskVal; + LeftDemanded.set(MaskVal); else - RightDemanded |= 1ULL << (MaskVal - LHSVWidth); + RightDemanded.set(MaskVal - LHSVWidth); } } } @@ -1540,7 +1542,7 @@ UndefElts2, Depth+1); if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; } - uint64_t UndefElts3; + APInt UndefElts3(VWidth, 0); TmpV = SimplifyDemandedVectorElts(I->getOperand(1), RightDemanded, UndefElts3, Depth+1); if (TmpV) { I->setOperand(1, TmpV); MadeChange = true; } @@ -1549,16 +1551,17 @@ for (unsigned i = 0; i < VWidth; i++) { unsigned MaskVal = Shuffle->getMaskValue(i); if (MaskVal == -1u) { - uint64_t NewBit = 1ULL << i; - UndefElts |= NewBit; + UndefElts.set(i); } else if (MaskVal < LHSVWidth) { - uint64_t NewBit = ((UndefElts2 >> MaskVal) & 1) << i; - NewUndefElts |= NewBit; - UndefElts |= NewBit; + if (UndefElts2[MaskVal]) { + NewUndefElts = true; + UndefElts.set(i); + } } else { - uint64_t NewBit = ((UndefElts3 >> (MaskVal - LHSVWidth)) & 1) << i; - NewUndefElts |= NewBit; - UndefElts |= NewBit; + if (UndefElts3[MaskVal - LHSVWidth]) { + NewUndefElts = true; + UndefElts.set(i); + } } } @@ -1566,7 +1569,7 @@ // Add additional discovered undefs. std::vector Elts; for (unsigned i = 0; i < VWidth; ++i) { - if (UndefElts & (1ULL << i)) + if (UndefElts[i]) Elts.push_back(UndefValue::get(Type::Int32Ty)); else Elts.push_back(ConstantInt::get(Type::Int32Ty, @@ -1582,7 +1585,7 @@ const VectorType *VTy = dyn_cast(I->getOperand(0)->getType()); if (!VTy) break; unsigned InVWidth = VTy->getNumElements(); - uint64_t InputDemandedElts = 0; + APInt InputDemandedElts(InVWidth, 0); unsigned Ratio; if (VWidth == InVWidth) { @@ -1599,8 +1602,8 @@ // elements are live. Ratio = VWidth/InVWidth; for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) { - if (DemandedElts & (1ULL << OutIdx)) - InputDemandedElts |= 1ULL << (OutIdx/Ratio); + if (DemandedElts[OutIdx]) + InputDemandedElts.set(OutIdx/Ratio); } } else { // Untested so far. @@ -1611,8 +1614,8 @@ // live. Ratio = InVWidth/VWidth; for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx) - if (DemandedElts & (1ULL << InIdx/Ratio)) - InputDemandedElts |= 1ULL << InIdx; + if (DemandedElts[InIdx/Ratio]) + InputDemandedElts.set(InIdx); } // div/rem demand all inputs, because they don't want divide by zero. @@ -1630,8 +1633,8 @@ // then an output element is undef if the corresponding input element is // undef. for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) - if (UndefElts2 & (1ULL << (OutIdx/Ratio))) - UndefElts |= 1ULL << OutIdx; + if (UndefElts2[OutIdx/Ratio]) + UndefElts.set(OutIdx); } else if (VWidth < InVWidth) { assert(0 && "Unimp"); // If there are more elements in the source than there are in the result, @@ -1639,8 +1642,8 @@ // elements are undef. UndefElts = ~0ULL >> (64-VWidth); // Start out all undef. for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx) - if ((UndefElts2 & (1ULL << InIdx)) == 0) // Not undef? - UndefElts &= ~(1ULL << (InIdx/Ratio)); // Clear undef bit. + if (!UndefElts2[InIdx]) // Not undef? + UndefElts.clear(InIdx/Ratio); // Clear undef bit. } break; } @@ -9493,8 +9496,11 @@ case Intrinsic::x86_sse_cvttss2si: { // These intrinsics only demands the 0th element of its input vector. If // we can simplify the input based on that, do so now. - uint64_t UndefElts; - if (Value *V = SimplifyDemandedVectorElts(II->getOperand(1), 1, + unsigned VWidth = + cast(II->getOperand(1)->getType())->getNumElements(); + APInt DemandedElts(VWidth, 1); + APInt UndefElts(VWidth, 0); + if (Value *V = SimplifyDemandedVectorElts(II->getOperand(1), DemandedElts, UndefElts)) { II->setOperand(1, V); return II; @@ -11868,10 +11874,10 @@ // If the input vector has a single use, simplify it based on this use // property. if (EI.getOperand(0)->hasOneUse() && VectorWidth != 1) { - uint64_t UndefElts; + APInt UndefElts(VectorWidth, 0); + APInt DemandedMask(VectorWidth, 1 << IndexVal); if (Value *V = SimplifyDemandedVectorElts(EI.getOperand(0), - 1 << IndexVal, - UndefElts)) { + DemandedMask, UndefElts)) { EI.setOperand(0, V); return &EI; } @@ -12170,15 +12176,14 @@ if (isa(SVI.getOperand(2))) return ReplaceInstUsesWith(SVI, UndefValue::get(SVI.getType())); - uint64_t UndefElts; unsigned VWidth = cast(SVI.getType())->getNumElements(); if (VWidth != cast(LHS->getType())->getNumElements()) return 0; - uint64_t AllOnesEltMask = ~0ULL >> (64-VWidth); - if (VWidth <= 64 && - SimplifyDemandedVectorElts(&SVI, AllOnesEltMask, UndefElts)) { + APInt UndefElts(VWidth, 0); + APInt AllOnesEltMask(APInt::getAllOnesValue(VWidth)); + if (SimplifyDemandedVectorElts(&SVI, AllOnesEltMask, UndefElts)) { LHS = SVI.getOperand(0); RHS = SVI.getOperand(1); MadeChange = true; Added: llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts-2.ll?rev=63631&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts-2.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts-2.ll Tue Feb 3 04:05:09 2009 @@ -0,0 +1,19 @@ +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | not grep extractelement + +define void @get_image() nounwind { +entry: + %0 = call i32 @fgetc(i8* null) nounwind ; [#uses=1] + %1 = trunc i32 %0 to i8 ; [#uses=1] + %tmp2 = insertelement <100 x i8> zeroinitializer, i8 %1, i32 1 ; <<100 x i8>> [#uses=1] + %tmp1 = extractelement <100 x i8> %tmp2, i32 0 ; [#uses=1] + %2 = icmp eq i8 %tmp1, 80 ; [#uses=1] + br i1 %2, label %bb2, label %bb3 + +bb2: ; preds = %entry + br label %bb3 + +bb3: ; preds = %bb2, %entry + unreachable +} + +declare i32 @fgetc(i8*) From baldrick at free.fr Tue Feb 3 04:23:44 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 03 Feb 2009 10:23:44 -0000 Subject: [llvm-commits] [llvm] r63632 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeTypes.cpp test/CodeGen/X86/2009-02-03-AnalyzedTwice.ll Message-ID: <200902031023.n13ANjg0026134@zion.cs.uiuc.edu> Author: baldrick Date: Tue Feb 3 04:23:33 2009 New Revision: 63632 URL: http://llvm.org/viewvc/llvm-project?rev=63632&view=rev Log: Fix PR3411. When replacing values, nodes are analyzed in any old order. Since analyzing a node analyzes its operands also, this can mean that when we pop a node off the list of nodes to be analyzed, it may already have been analyzed. Added: llvm/trunk/test/CodeGen/X86/2009-02-03-AnalyzedTwice.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=63632&r1=63631&r2=63632&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Tue Feb 3 04:23:33 2009 @@ -651,7 +651,7 @@ DTL.NoteDeletion(N, E); // In theory the deleted node could also have been scheduled for analysis. - // So add it to the set of nodes which will not be analyzed. + // So remove it from the set of nodes which will be analyzed. NodesToAnalyze.remove(N); // In general nothing needs to be done for E, since it didn't change but @@ -669,6 +669,7 @@ assert(N->getNodeId() != DAGTypeLegalizer::ReadyToProcess && N->getNodeId() != DAGTypeLegalizer::Processed && "Invalid node ID for RAUW deletion!"); + N->setNodeId(DAGTypeLegalizer::NewNode); NodesToAnalyze.insert(N); } }; @@ -695,12 +696,13 @@ while (!NodesToAnalyze.empty()) { SDNode *N = NodesToAnalyze.back(); NodesToAnalyze.pop_back(); + if (N->getNodeId() != DAGTypeLegalizer::NewNode) + // The node was analyzed while reanalyzing an earlier node - it is safe to + // skip. Note that this is not a morphing node - otherwise it would still + // be marked NewNode. + continue; // Analyze the node's operands and recalculate the node ID. - assert(N->getNodeId() != DAGTypeLegalizer::ReadyToProcess && - N->getNodeId() != DAGTypeLegalizer::Processed && - "Invalid node ID for RAUW analysis!"); - N->setNodeId(NewNode); SDNode *M = AnalyzeNewNode(N); if (M != N) { // The node morphed into a different node. Make everyone use the new node Added: llvm/trunk/test/CodeGen/X86/2009-02-03-AnalyzedTwice.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-02-03-AnalyzedTwice.ll?rev=63632&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-02-03-AnalyzedTwice.ll (added) +++ llvm/trunk/test/CodeGen/X86/2009-02-03-AnalyzedTwice.ll Tue Feb 3 04:23:33 2009 @@ -0,0 +1,30 @@ +; RUN: llvm-as < %s | llc -march=x86 +; PR3411 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" +target triple = "i386-pc-linux-gnu" + at g_3 = external global i32 ; [#uses=1] + +define void @bar(i64 %p_66) nounwind { +entry: + br i1 false, label %bb, label %bb1 + +bb: ; preds = %entry + unreachable + +bb1: ; preds = %entry + %0 = load i32* @g_3, align 4 ; [#uses=2] + %1 = sext i32 %0 to i64 ; [#uses=1] + %2 = or i64 %1, %p_66 ; [#uses=1] + %3 = shl i64 %2, 0 ; [#uses=1] + %4 = and i64 %3, %p_66 ; [#uses=1] + %5 = icmp eq i64 %4, 1 ; [#uses=1] + %6 = trunc i64 %p_66 to i32 ; [#uses=2] + %7 = or i32 %0, %6 ; [#uses=2] + %8 = sub i32 %7, %6 ; [#uses=1] + %iftmp.0.0 = select i1 %5, i32 %8, i32 %7 ; [#uses=1] + %9 = tail call i32 @foo(i32 %iftmp.0.0) nounwind ; [#uses=0] + ret void +} + +declare i32 @foo(i32) From rafael.espindola at gmail.com Tue Feb 3 10:20:22 2009 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 03 Feb 2009 16:20:22 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63633 - /llvm-gcc-4.2/trunk/gcc/gcc.c Message-ID: <200902031620.n13GKM9K005714@zion.cs.uiuc.edu> Author: rafael Date: Tue Feb 3 10:20:19 2009 New Revision: 63633 URL: http://llvm.org/viewvc/llvm-project?rev=63633&view=rev Log: One difference of the way the Apple ld and gold implement plugins is that gold doesn't search for the plugin. It must be passed with the -plugin option. This patch makes gcc search for the plugin in the same way it searches for cc1. The search only happens if the -use-gold-plugin option is used. If the plugin is found, it is passed to gold. Modified: llvm-gcc-4.2/trunk/gcc/gcc.c Modified: llvm-gcc-4.2/trunk/gcc/gcc.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gcc.c?rev=63633&r1=63632&r2=63633&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/gcc.c (original) +++ llvm-gcc-4.2/trunk/gcc/gcc.c Tue Feb 3 10:20:19 2009 @@ -713,10 +713,12 @@ scripts which exist in user specified directories, or in standard directories. */ /* APPLE LOCAL begin add fcreate-profile */ +/* LLVM LOCAL begin add use-gold-plugin */ #ifndef LINK_COMMAND_SPEC #define LINK_COMMAND_SPEC "\ %{!fsyntax-only:%{!c:%{!M:%{!MM:%{!E:%{!S:\ - %(linker) %l " LINK_PIE_SPEC "%X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r}\ + %(linker) %{use-gold-plugin: -plugin %(gold_plugin_file)} \ + %l " LINK_PIE_SPEC "%X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r}\ %{s} %{t} %{u*} %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles:%S}}}\ %{static:} %{L*} %(mfwrap) %(link_libgcc) %o\ %{fopenmp:%:include(libgomp.spec)%(link_gomp)} %(mflib)\ @@ -765,6 +767,7 @@ static const char *startfile_spec = STARTFILE_SPEC; static const char *switches_need_spaces = SWITCHES_NEED_SPACES; static const char *linker_name_spec = LINKER_NAME; +static const char *gold_plugin_file_spec = ""; static const char *link_command_spec = LINK_COMMAND_SPEC; static const char *link_libgcc_spec = LINK_LIBGCC_SPEC; static const char *startfile_prefix_spec = STARTFILE_PREFIX_SPEC; @@ -1637,6 +1640,7 @@ INIT_STATIC_SPEC ("linker", &linker_name_spec), INIT_STATIC_SPEC ("link_libgcc", &link_libgcc_spec), /* LLVM LOCAL */ + INIT_STATIC_SPEC ("gold_plugin_file", &gold_plugin_file_spec), INIT_STATIC_SPEC ("llvm_options", &llvm_options), INIT_STATIC_SPEC ("md_exec_prefix", &md_exec_prefix), INIT_STATIC_SPEC ("md_startfile_prefix", &md_startfile_prefix), @@ -7138,6 +7142,7 @@ if (num_linker_inputs > 0 && error_count == 0) { int tmp = execution_count; + const char *use_gold_plugin = "use-gold-plugin"; /* We'll use ld if we can't find collect2. */ if (! strcmp (linker_name_spec, "collect2")) @@ -7146,6 +7151,17 @@ if (s == NULL) linker_name_spec = "ld"; } + + if (switch_matches (use_gold_plugin, + use_gold_plugin + strlen (use_gold_plugin), 0)) + { + gold_plugin_file_spec = find_a_file (&exec_prefixes, + "libLLVMgold.so", X_OK, + false); + if (!gold_plugin_file_spec) + fatal ("-use-gold-plugin, but libLLVMgold.so not found."); + } + /* Rebuild the COMPILER_PATH and LIBRARY_PATH environment variables for collect. */ putenv_from_prefixes (&exec_prefixes, "COMPILER_PATH", false); From sabre at nondot.org Tue Feb 3 12:13:00 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Feb 2009 18:13:00 -0000 Subject: [llvm-commits] [llvm] r63637 - /llvm/trunk/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll Message-ID: <200902031813.n13ID0Jn009682@zion.cs.uiuc.edu> Author: lattner Date: Tue Feb 3 12:13:00 2009 New Revision: 63637 URL: http://llvm.org/viewvc/llvm-project?rev=63637&view=rev Log: this produces an undefined result, just check that the alloca is gone and that sroa doesn't crash. Modified: llvm/trunk/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll Modified: llvm/trunk/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll?rev=63637&r1=63636&r2=63637&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll Tue Feb 3 12:13:00 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | opt -scalarrepl -instcombine | llvm-dis | grep {ret i32 undef} +; RUN: llvm-as < %s | opt -scalarrepl -instcombine | llvm-dis | not grep alloca ; Test that an array is not incorrectly deconstructed. From sabre at nondot.org Tue Feb 3 12:15:05 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Feb 2009 18:15:05 -0000 Subject: [llvm-commits] [llvm] r63638 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/not-a-vector.ll Message-ID: <200902031815.n13IF5Zu009756@zion.cs.uiuc.edu> Author: lattner Date: Tue Feb 3 12:15:05 2009 New Revision: 63638 URL: http://llvm.org/viewvc/llvm-project?rev=63638&view=rev Log: Make SROA produce a vector only when the alloca is actually accessed at least once as a vector. This prevents it from compiling the example in not-a-vector into: define double @test(double %A, double %B) { %tmp4 = insertelement <7 x double> undef, double %A, i32 0 %tmp = insertelement <7 x double> %tmp4, double %B, i32 4 %tmp2 = extractelement <7 x double> %tmp, i32 4 ret double %tmp2 } instead, producing the integer code. Producing vectors when they aren't otherwise in the program is dangerous because a lot of other code treats them carefully and doesn't want to break them down. OTOH, many things want to break down tasty i448's. Added: llvm/trunk/test/Transforms/ScalarRepl/not-a-vector.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=63638&r1=63637&r2=63638&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Tue Feb 3 12:15:05 2009 @@ -126,7 +126,7 @@ SmallVector &NewElts); bool CanConvertToScalar(Value *V, bool &IsNotTrivial, const Type *&VecTy, - uint64_t Offset, unsigned AllocaSize); + bool &SawVec, uint64_t Offset, unsigned AllocaSize); void ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, uint64_t Offset); Value *ConvertUsesOfLoadToScalar(LoadInst *LI, AllocaInst *NewAI, uint64_t Offset); @@ -281,10 +281,17 @@ // but that has pointer arithmetic to set byte 3 of it or something. bool IsNotTrivial = false; const Type *VectorTy = 0; - if (CanConvertToScalar(AI, IsNotTrivial, VectorTy, + bool HadAVector = false; + if (CanConvertToScalar(AI, IsNotTrivial, VectorTy, HadAVector, 0, unsigned(AllocaSize)) && IsNotTrivial) { AllocaInst *NewAI; - if (VectorTy && isa(VectorTy)) { + // If we were able to find a vector type that can handle this with + // insert/extract elements, and if there was at least one use that had + // a vector type, promote this to a vector. We don't want to promote + // random stuff that doesn't use vectors (e.g. <9 x double>) because then + // we just get a lot of insert/extracts. If at least one vector is + // involved, then we probably really do have a union of vector/array. + if (VectorTy && isa(VectorTy) && HadAVector) { DOUT << "CONVERT TO VECTOR: " << *AI << " TYPE = " << *VectorTy <<"\n"; // Create and insert the vector alloca. @@ -1229,8 +1236,11 @@ /// completely trivial use that mem2reg could promote, set IsNotTrivial. Offset /// is the current offset from the base of the alloca being analyzed. /// -bool SROA::CanConvertToScalar(Value *V, bool &IsNotTrivial, - const Type *&VecTy, uint64_t Offset, +/// If we see at least one access to the value that is as a vector type, set the +/// SawVec flag. +/// +bool SROA::CanConvertToScalar(Value *V, bool &IsNotTrivial, const Type *&VecTy, + bool &SawVec, uint64_t Offset, unsigned AllocaSize) { for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI!=E; ++UI) { Instruction *User = cast(*UI); @@ -1240,6 +1250,7 @@ if (LI->isVolatile()) return false; MergeInType(LI->getType(), Offset, VecTy, AllocaSize, *TD); + SawVec |= isa(LI->getType()); continue; } @@ -1247,11 +1258,13 @@ // Storing the pointer, not into the value? if (SI->getOperand(0) == V || SI->isVolatile()) return 0; MergeInType(SI->getOperand(0)->getType(), Offset, VecTy, AllocaSize, *TD); + SawVec |= isa(SI->getOperand(0)->getType()); continue; } if (BitCastInst *BCI = dyn_cast(User)) { - if (!CanConvertToScalar(BCI, IsNotTrivial, VecTy, Offset, AllocaSize)) + if (!CanConvertToScalar(BCI, IsNotTrivial, VecTy, SawVec, Offset, + AllocaSize)) return false; IsNotTrivial = true; continue; @@ -1267,7 +1280,7 @@ uint64_t GEPOffset = TD->getIndexedOffset(GEP->getOperand(0)->getType(), &Indices[0], Indices.size()); // See if all uses can be converted. - if (!CanConvertToScalar(GEP, IsNotTrivial, VecTy, Offset+GEPOffset, + if (!CanConvertToScalar(GEP, IsNotTrivial, VecTy, SawVec,Offset+GEPOffset, AllocaSize)) return false; IsNotTrivial = true; Added: llvm/trunk/test/Transforms/ScalarRepl/not-a-vector.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/not-a-vector.ll?rev=63638&view=auto ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/not-a-vector.ll (added) +++ llvm/trunk/test/Transforms/ScalarRepl/not-a-vector.ll Tue Feb 3 12:15:05 2009 @@ -0,0 +1,19 @@ +; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | not grep alloca +; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | not grep {7 x double} +; RUN: llvm-as < %s | opt -scalarrepl -instcombine | llvm-dis | grep {ret double %B} + +define double @test(double %A, double %B) { + %ARR = alloca [7 x i64] + %C = bitcast [7 x i64]* %ARR to double* + store double %A, double* %C + + %D = getelementptr [7 x i64]* %ARR, i32 0, i32 4 + %E = bitcast i64* %D to double* + store double %B, double* %E + + %F = getelementptr double* %C, i32 4 + %G = load double* %F + ret double %G +} + + From dpatel at apple.com Tue Feb 3 12:20:27 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 03 Feb 2009 18:20:27 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63639 - in /llvm-gcc-4.2/trunk/gcc: config/darwin.h llvm-backend.cpp llvm-debug.cpp Message-ID: <200902031820.n13IKR4H009989@zion.cs.uiuc.edu> Author: dpatel Date: Tue Feb 3 12:20:26 2009 New Revision: 63639 URL: http://llvm.org/viewvc/llvm-project?rev=63639&view=rev Log: Enable debug info at -O1+. However, for now, do not emit variable and line number info at -O1+. Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.h llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/darwin.h?rev=63639&r1=63638&r2=63639&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/darwin.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/darwin.h Tue Feb 3 12:20:26 2009 @@ -340,7 +340,6 @@ specifying the handling of options understood by generic Unix linkers, and for positional arguments like libraries. */ /* APPLE LOCAL begin mainline */ -#ifdef ENABLE_LLVM #define LINK_COMMAND_SPEC "\ %{!fdump=*:%{!fsyntax-only:%{!precomp:%{!c:%{!M:%{!MM:%{!E:%{!S:\ %(linker) %l %X %{d} %{s} %{t} %{Z} %{u*} \ @@ -359,29 +358,7 @@ %{!fdump=*:%{!fsyntax-only:%{!c:%{!M:%{!MM:%{!E:%{!S:\ "/* APPLE LOCAL end mainline 4.3 2006-10-31 4370146 */"\ %{.c|.cc|.C|.cpp|.cp|.c++|.cxx|.CPP|.m|.mm: \ - %{!O: %{!O1: %{!O2: %{!O3: %{!O4: %{!Os: \ -"/* LLVM LOCAL do not use dsymutil with -O1 or higher */"\ - %{g*:%{!gstabs*:%{!g0: dsymutil %{o*:%*}%{!o:a.out}}}}}}}}}}}}}}}}}}" -#else -#define LINK_COMMAND_SPEC "\ -%{!fdump=*:%{!fsyntax-only:%{!precomp:%{!c:%{!M:%{!MM:%{!E:%{!S:\ - %(linker) %l %X %{d} %{s} %{t} %{Z} %{u*} \ - %{A} %{e*} %{m} %{r} %{x} \ - %{o*}%{!o:-o a.out} \ - %{!A:%{!nostdlib:%{!nostartfiles:%S}}} \ - %{L*} %{fopenmp:%:include(libgomp.spec)%(link_gomp)} \ -"/* APPLE LOCAL add fcreate-profile */"\ - %(link_libgcc) %o %{fprofile-arcs|fprofile-generate|fcreate-profile|coverage:-lgcov} \ -"/* APPLE LOCAL nested functions 4357979 */"\ - %{fnested-functions: -allow_stack_execute} \ - %{!nostdlib:%{!nodefaultlibs:%(link_ssp) %G %L}} \ -"/* APPLE LOCAL begin mainline 4.3 2006-10-31 4370146 */"\ - %{!A:%{!nostdlib:%{!nostartfiles:%E}}} %{T*} %{F*} }}}}}}}}\n\ -%{!fdump=*:%{!fsyntax-only:%{!c:%{!M:%{!MM:%{!E:%{!S:\ -"/* APPLE LOCAL end mainline 4.3 2006-10-31 4370146 */"\ - %{.c|.cc|.C|.cpp|.cp|.c++|.cxx|.CPP|.m|.mm: \ %{g*:%{!gstabs*:%{!g0: dsymutil %{o*:%*}%{!o:a.out}}}}}}}}}}}}" -#endif /* APPLE LOCAL end mainline */ #ifdef TARGET_SYSTEM_ROOT Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=63639&r1=63638&r2=63639&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Tue Feb 3 12:20:26 2009 @@ -251,7 +251,7 @@ // FIXME - Do not disable debug info while writing pch. if (!flag_pch_file && - !optimize && debug_info_level > DINFO_LEVEL_NONE) + debug_info_level > DINFO_LEVEL_NONE) TheDebugInfo = new DebugInfo(TheModule); } @@ -288,8 +288,7 @@ delete MB; // FIXME - Do not disable debug info while writing pch. - if (!flag_pch_file && - !optimize && debug_info_level > DINFO_LEVEL_NONE) + if (!flag_pch_file && debug_info_level > DINFO_LEVEL_NONE) TheDebugInfo = new DebugInfo(TheModule); if (!TheModule) { Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp?rev=63639&r1=63638&r2=63639&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Tue Feb 3 12:20:26 2009 @@ -298,6 +298,11 @@ /// region - "llvm.dbg.declare." void DebugInfo::EmitDeclare(tree decl, unsigned Tag, const char *Name, tree type, Value *AI, BasicBlock *CurBB) { + + // Do not emit variable declaration info, for now. + if (optimize) + return; + // Ignore compiler generated temporaries. if (DECL_IGNORED_P(decl)) return; @@ -319,6 +324,11 @@ /// EmitStopPoint - Emit a call to llvm.dbg.stoppoint to indicate a change of /// source line - "llvm.dbg.stoppoint." void DebugInfo::EmitStopPoint(Function *Fn, BasicBlock *CurBB) { + + // Do not emit line number info, for now. + if (optimize) + return; + // Don't bother if things are the same as last time. if (PrevLineNo == CurLineNo && PrevBB == CurBB && From dpatel at apple.com Tue Feb 3 12:21:26 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 03 Feb 2009 18:21:26 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63640 - /llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Message-ID: <200902031821.n13ILQpg010039@zion.cs.uiuc.edu> Author: dpatel Date: Tue Feb 3 12:21:25 2009 New Revision: 63640 URL: http://llvm.org/viewvc/llvm-project?rev=63640&view=rev Log: Encode command line flags in the main compile unit. Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp?rev=63640&r1=63639&r2=63640&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Tue Feb 3 12:21:25 2009 @@ -847,9 +847,17 @@ else LangTag = DW_LANG_C89; + const char *Flags = ""; + // Do this only when RC_DEBUG_OPTIONS environment variable is set to + // a nonempty string. This is intended only for internal Apple use. + char * debugopt = getenv("RC_DEBUG_OPTIONS"); + if (debugopt && debugopt[0]) + Flags = get_arguments(); + DICompileUnit NewCU = DebugFactory.CreateCompileUnit(LangTag, FileName, Directory, - version_string, isMain); + version_string, isMain, + optimize, Flags); CU = NewCU.getGV(); return NewCU; } From dpatel at apple.com Tue Feb 3 12:46:32 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 03 Feb 2009 18:46:32 -0000 Subject: [llvm-commits] [llvm] r63641 - in /llvm/trunk/lib/CodeGen/SelectionDAG: SelectionDAG.cpp SelectionDAGISel.cpp Message-ID: <200902031846.n13IkXcH010986@zion.cs.uiuc.edu> Author: dpatel Date: Tue Feb 3 12:46:32 2009 New Revision: 63641 URL: http://llvm.org/viewvc/llvm-project?rev=63641&view=rev Log: First initialize DAG otherwise dwarf writer is used uninitialized. Duncan spotted this. Thanks! Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63641&r1=63640&r2=63641&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Feb 3 12:46:32 2009 @@ -787,7 +787,7 @@ } SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) - : TLI(tli), FLI(fli), + : TLI(tli), FLI(fli), DW(0), EntryNode(ISD::EntryToken, getVTList(MVT::Other)), Root(getEntryNode()) { AllNodes.push_back(&EntryNode); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=63641&r1=63640&r2=63641&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Feb 3 12:46:32 2009 @@ -313,10 +313,10 @@ RegInfo = &MF->getRegInfo(); DOUT << "\n\n\n=== " << Fn.getName() << "\n"; - FuncInfo->set(Fn, *MF, *CurDAG, EnableFastISel); MachineModuleInfo *MMI = getAnalysisIfAvailable(); DwarfWriter *DW = getAnalysisIfAvailable(); CurDAG->init(*MF, MMI, DW); + FuncInfo->set(Fn, *MF, *CurDAG, EnableFastISel); SDL->init(GFI, *AA); for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) From gohman at apple.com Tue Feb 3 12:53:21 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 03 Feb 2009 18:53:21 -0000 Subject: [llvm-commits] [llvm] r63642 - /llvm/trunk/lib/Target/X86/X86Subtarget.cpp Message-ID: <200902031853.n13IrL3d011185@zion.cs.uiuc.edu> Author: djg Date: Tue Feb 3 12:53:21 2009 New Revision: 63642 URL: http://llvm.org/viewvc/llvm-project?rev=63642&view=rev Log: Tevert part of the x86 subtarget logic changes: when -march=x86-64 is given, override the subtarget settings and enable 64-bit support. This restores the earlier behavior, and fixes regressions on Non-64-bit-capable x86-32 hosts. This isn't necessarily the best approach, but the most obvious alternative is to require -mcpu=x86-64 or -mattr=+64bit to be used with -march=x86-64 when the host doesn't have 64-bit support. This makes things little more consistent, but it's less convenient, and it has the practical drawback of requiring lots of test changes, so I opted for the above approach for now. Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=63642&r1=63641&r2=63642&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Tue Feb 3 12:53:21 2009 @@ -327,15 +327,16 @@ } else { // Otherwise, use CPUID to auto-detect feature set. AutoDetectSubtargetFeatures(); - // If requesting codegen for X86-64, make sure that 64-bit features - // are enabled. - if (Is64Bit) - HasX86_64 = true; // Make sure SSE2 is enabled; it is available on all X86-64 CPUs. if (Is64Bit && X86SSELevel < SSE2) X86SSELevel = SSE2; } + // If requesting codegen for X86-64, make sure that 64-bit features + // are enabled. + if (Is64Bit) + HasX86_64 = true; + DOUT << "Subtarget features: SSELevel " << X86SSELevel << ", 3DNowLevel " << X863DNowLevel << ", 64bit " << HasX86_64 << "\n"; From gohman at apple.com Tue Feb 3 12:57:45 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 03 Feb 2009 18:57:45 -0000 Subject: [llvm-commits] [llvm] r63643 - /llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Message-ID: <200902031857.n13IvjOM011336@zion.cs.uiuc.edu> Author: djg Date: Tue Feb 3 12:57:45 2009 New Revision: 63643 URL: http://llvm.org/viewvc/llvm-project?rev=63643&view=rev Log: Change the post-RA scheduler to iterate through the basic-block segments bottom-up instead of top down. This is the first step in a general restructuring of the way register liveness is tracked in the post-RA scheduler. Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=63643&r1=63642&r2=63643&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original) +++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Tue Feb 3 12:57:45 2009 @@ -189,15 +189,17 @@ MBB != MBBe; ++MBB) { // Schedule each sequence of instructions not interrupted by a label // or anything else that effectively needs to shut down scheduling. - MachineBasicBlock::iterator Current = MBB->begin(), End = MBB->end(); - for (MachineBasicBlock::iterator MI = Current; MI != End; ++MI) + MachineBasicBlock::iterator Current = MBB->end(), Top = MBB->begin(); + for (MachineBasicBlock::iterator I = Current; I != Top; ) { + MachineInstr *MI = --I; if (MI->getDesc().isTerminator() || MI->isLabel()) { - Scheduler.Run(0, MBB, Current, MI); + Scheduler.Run(0, MBB, next(I), Current); Scheduler.EmitSchedule(); - Current = next(MI); + Current = I; } + } - Scheduler.Run(0, MBB, Current, End); + Scheduler.Run(0, MBB, Top, Current); Scheduler.EmitSchedule(); } @@ -415,10 +417,10 @@ // instructions from the bottom up, tracking information about liveness // as we go to help determine which registers are available. bool Changed = false; - unsigned Count = BB->size() - 1; - for (MachineBasicBlock::reverse_iterator I = BB->rbegin(), E = BB->rend(); - I != E; ++I, --Count) { - MachineInstr *MI = &*I; + unsigned Count = SUnits.size() - 1; + for (MachineBasicBlock::iterator I = End, E = Begin; + I != E; --Count) { + MachineInstr *MI = --I; // After regalloc, IMPLICIT_DEF instructions aren't safe to treat as // dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF From dalej at apple.com Tue Feb 3 12:58:24 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 3 Feb 2009 10:58:24 -0800 Subject: [llvm-commits] [llvm] r63642 - /llvm/trunk/lib/Target/X86/X86Subtarget.cpp In-Reply-To: <200902031853.n13IrL3d011185@zion.cs.uiuc.edu> References: <200902031853.n13IrL3d011185@zion.cs.uiuc.edu> Message-ID: <9AC57CE1-D557-4D27-97A5-5806D629DB80@apple.com> On Feb 3, 2009, at 10:53 AMPST, Dan Gohman wrote: > Author: djg > Date: Tue Feb 3 12:53:21 2009 > New Revision: 63642 > > URL: http://llvm.org/viewvc/llvm-project?rev=63642&view=rev > Log: > Tevert part of the x86 subtarget logic changes: when -march=x86-64 > is given, override the subtarget settings and enable 64-bit support. > This restores the earlier behavior, and fixes regressions on > Non-64-bit-capable x86-32 hosts. > > This isn't necessarily the best approach, but the most obvious > alternative is to require -mcpu=x86-64 or -mattr=+64bit to be used > with -march=x86-64 when the host doesn't have 64-bit support. This > makes things little more consistent, but it's less convenient, and > it has the practical drawback of requiring lots of test changes, so > I opted for the above approach for now. btw, is the interaction of -mcpu, -mattr and -march documented anywhere? It should be. > Modified: > llvm/trunk/lib/Target/X86/X86Subtarget.cpp > > Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=63642&r1=63641&r2=63642&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Tue Feb 3 12:53:21 > 2009 > @@ -327,15 +327,16 @@ > } else { > // Otherwise, use CPUID to auto-detect feature set. > AutoDetectSubtargetFeatures(); > - // If requesting codegen for X86-64, make sure that 64-bit > features > - // are enabled. > - if (Is64Bit) > - HasX86_64 = true; > // Make sure SSE2 is enabled; it is available on all X86-64 CPUs. > if (Is64Bit && X86SSELevel < SSE2) > X86SSELevel = SSE2; > } > > + // If requesting codegen for X86-64, make sure that 64-bit features > + // are enabled. > + if (Is64Bit) > + HasX86_64 = true; > + > DOUT << "Subtarget features: SSELevel " << X86SSELevel > << ", 3DNowLevel " << X863DNowLevel > << ", 64bit " << HasX86_64 << "\n"; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Tue Feb 3 13:12:26 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 3 Feb 2009 11:12:26 -0800 Subject: [llvm-commits] [llvm] r63641 - in /llvm/trunk/lib/CodeGen/SelectionDAG: SelectionDAG.cpp SelectionDAGISel.cpp In-Reply-To: <200902031846.n13IkXcH010986@zion.cs.uiuc.edu> References: <200902031846.n13IkXcH010986@zion.cs.uiuc.edu> Message-ID: <16e5fdf90902031112l292338cdg38e98b5306fce846@mail.gmail.com> On Tue, Feb 3, 2009 at 10:46 AM, Devang Patel wrote: > Author: dpatel > Date: Tue Feb 3 12:46:32 2009 > New Revision: 63641 > > URL: http://llvm.org/viewvc/llvm-project?rev=63641&view=rev > Log: > First initialize DAG otherwise dwarf writer is used uninitialized. > Duncan spotted this. Thanks! > Thanks, Devang! I suggest that this be pulled into the 2.5 release branch. -bw From sabre at nondot.org Tue Feb 3 13:30:11 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Feb 2009 19:30:11 -0000 Subject: [llvm-commits] [llvm] r63649 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/sroa-fca.ll Message-ID: <200902031930.n13JUBQ9012598@zion.cs.uiuc.edu> Author: lattner Date: Tue Feb 3 13:30:11 2009 New Revision: 63649 URL: http://llvm.org/viewvc/llvm-project?rev=63649&view=rev Log: make scalar conversion handle stores of first class aggregate values. loads are not yet handled (coming soon to an sroa near you). Added: llvm/trunk/test/Transforms/ScalarRepl/sroa-fca.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=63649&r1=63648&r2=63649&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Tue Feb 3 13:30:11 2009 @@ -130,8 +130,8 @@ void ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, uint64_t Offset); Value *ConvertUsesOfLoadToScalar(LoadInst *LI, AllocaInst *NewAI, uint64_t Offset); - Value *ConvertUsesOfStoreToScalar(Value *StoredVal, AllocaInst *NewAI, - uint64_t Offset, Instruction *InsertPt); + Value *ConvertScalar_InsertValue(Value *StoredVal, Value *ExistingVal, + uint64_t Offset, Instruction *InsertPt); static Instruction *isOnlyCopiedFromConstantGlobal(AllocationInst *AI); }; } @@ -1326,8 +1326,9 @@ if (StoreInst *SI = dyn_cast(User)) { assert(SI->getOperand(0) != Ptr && "Consistency error!"); - new StoreInst(ConvertUsesOfStoreToScalar(SI->getOperand(0), NewAI, - Offset, SI), NewAI, SI); + Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", SI); + Value *New = ConvertScalar_InsertValue(SI->getOperand(0), Old, Offset,SI); + new StoreInst(New, NewAI, SI); SI->eraseFromParent(); continue; } @@ -1363,8 +1364,10 @@ for (unsigned i = 1; i != NumBytes; ++i) APVal |= APVal << 8; - new StoreInst(ConvertUsesOfStoreToScalar(ConstantInt::get(APVal), NewAI, - Offset, MSI), NewAI, MSI); + Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", MSI); + Value *New = ConvertScalar_InsertValue(ConstantInt::get(APVal), Old, + Offset, MSI); + new StoreInst(New, NewAI, MSI); MSI->eraseFromParent(); continue; } @@ -1464,26 +1467,23 @@ } -/// ConvertUsesOfStoreToScalar - Convert the specified store to a load+store -/// pair of the new alloca directly, returning the value that should be stored -/// to the alloca. This happens when we are converting an "integer union" to a +/// ConvertScalar_InsertValue - Insert the value "SV" into the existing integer +/// or vector value "Old" at the offset specified by Offset. +/// +/// This happens when we are converting an "integer union" to a /// single integer scalar, or when we are converting a "vector union" to a /// vector with insert/extractelement instructions. /// /// Offset is an offset from the original alloca, in bits that need to be -/// shifted to the right. By the end of this, there should be no uses of Ptr. -Value *SROA::ConvertUsesOfStoreToScalar(Value *SV, AllocaInst *NewAI, - uint64_t Offset, Instruction *IP) { +/// shifted to the right. +Value *SROA::ConvertScalar_InsertValue(Value *SV, Value *Old, + uint64_t Offset, Instruction *IP) { // Convert the stored type to the actual type, shift it left to insert // then 'or' into place. - const Type *AllocaType = NewAI->getType()->getElementType(); - if (SV->getType() == AllocaType && Offset == 0) - return SV; + const Type *AllocaType = Old->getType(); if (const VectorType *VTy = dyn_cast(AllocaType)) { - Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", IP); - // If the result alloca is a vector type, this is either an element // access or a bitcast to another vector type. if (isa(SV->getType())) { @@ -1501,13 +1501,29 @@ } return SV; } - - - Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", IP); + + // If SV is a first-class aggregate value, insert each value recursively. + if (const StructType *ST = dyn_cast(SV->getType())) { + const StructLayout &Layout = *TD->getStructLayout(ST); + for (unsigned i = 0, e = ST->getNumElements(); i != e; ++i) { + Value *Elt = ExtractValueInst::Create(SV, i, "tmp", IP); + Old = ConvertScalar_InsertValue(Elt, Old, + Offset+Layout.getElementOffset(i), IP); + } + return Old; + } + + if (const ArrayType *AT = dyn_cast(SV->getType())) { + uint64_t EltSize = TD->getTypePaddedSizeInBits(AT->getElementType()); + for (unsigned i = 0, e = AT->getNumElements(); i != e; ++i) { + Value *Elt = ExtractValueInst::Create(SV, i, "tmp", IP); + Old = ConvertScalar_InsertValue(Elt, Old, Offset+i*EltSize, IP); + } + return Old; + } // If SV is a float, convert it to the appropriate integer type. - // If it is a pointer, do the same, and also handle ptr->ptr casts - // here. + // If it is a pointer, do the same. unsigned SrcWidth = TD->getTypeSizeInBits(SV->getType()); unsigned DestWidth = TD->getTypeSizeInBits(AllocaType); unsigned SrcStoreWidth = TD->getTypeStoreSizeInBits(SV->getType()); Added: llvm/trunk/test/Transforms/ScalarRepl/sroa-fca.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/sroa-fca.ll?rev=63649&view=auto ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/sroa-fca.ll (added) +++ llvm/trunk/test/Transforms/ScalarRepl/sroa-fca.ll Tue Feb 3 13:30:11 2009 @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis +; Make sure that SROA "scalar conversion" can handle first class aggregates. + +define i64 @test({i32, i32} %A) { + %X = alloca i64 + %Y = bitcast i64* %X to {i32,i32}* + store {i32,i32} %A, {i32,i32}* %Y + + %Q = load i64* %X + ret i64 %Q +} + From dalej at apple.com Tue Feb 3 13:33:06 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 03 Feb 2009 19:33:06 -0000 Subject: [llvm-commits] [llvm] r63650 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h Message-ID: <200902031933.n13JX6RJ012814@zion.cs.uiuc.edu> Author: johannes Date: Tue Feb 3 13:33:06 2009 New Revision: 63650 URL: http://llvm.org/viewvc/llvm-project?rev=63650&view=rev Log: DebugLoc propagation. 2/3 through file. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=63650&r1=63649&r2=63650&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Feb 3 13:33:06 2009 @@ -45,7 +45,7 @@ DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX")); // Forward declarations. -static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG); +static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG, DebugLoc dl); X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) : TargetLowering(TM) { @@ -914,6 +914,7 @@ /// LowerRET - Lower an ISD::RET node. SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args"); SmallVector RVLocs; @@ -955,7 +956,7 @@ for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) { Operands.push_back(Chain.getOperand(i)); } - return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0], + return DAG.getNode(X86ISD::TC_RETURN, dl, MVT::Other, &Operands[0], Operands.size()); } @@ -980,7 +981,7 @@ // If this is a copy from an xmm register to ST(0), use an FPExtend to // change the value to the FP stack register class. if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) - ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy); + ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); RetOps.push_back(ValToCopy); // Don't emit a copytoreg. continue; @@ -1015,7 +1016,8 @@ if (Flag.getNode()) RetOps.push_back(Flag); - return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size()); + return DAG.getNode(X86ISD::RET_FLAG, dl, + MVT::Other, &RetOps[0], RetOps.size()); } @@ -1027,7 +1029,8 @@ SDNode *X86TargetLowering:: LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall, unsigned CallingConv, SelectionDAG &DAG) { - + + DebugLoc dl = TheCall->getDebugLoc(); // Assign locations to each value returned by this call. SmallVector RVLocs; bool isVarArg = TheCall->isVarArg(); @@ -1065,7 +1068,7 @@ if (CopyVT != RVLocs[i].getValVT()) { // Round the F80 the right size, which also moves to the appropriate xmm // register. - Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val, + Val = DAG.getNode(ISD::FP_ROUND, dl, RVLocs[i].getValVT(), Val, // This truncation won't change the value. DAG.getIntPtrConstant(1)); } @@ -1075,8 +1078,8 @@ // Merge everything together with a MERGE_VALUES node. ResultVals.push_back(Chain); - return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), &ResultVals[0], - ResultVals.size()).getNode(); + return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(), + &ResultVals[0], ResultVals.size()).getNode(); } @@ -1222,7 +1225,7 @@ SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); if (Flags.isByVal()) return FIN; - return DAG.getLoad(VA.getValVT(), Root, FIN, + return DAG.getLoad(VA.getValVT(), Op.getNode()->getDebugLoc(), Root, FIN, PseudoSourceValue::getFixedStack(FI), 0); } @@ -1230,6 +1233,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { MachineFunction &MF = DAG.getMachineFunction(); X86MachineFunctionInfo *FuncInfo = MF.getInfo(); + DebugLoc dl = Op.getNode()->getDebugLoc(); const Function* Fn = MF.getFunction(); if (Fn->hasExternalLinkage() && @@ -1304,23 +1308,23 @@ // bits. Insert an assert[sz]ext to capture this, then truncate to the // right size. if (VA.getLocInfo() == CCValAssign::SExt) - ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue, + ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, DAG.getValueType(VA.getValVT())); else if (VA.getLocInfo() == CCValAssign::ZExt) - ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue, + ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, DAG.getValueType(VA.getValVT())); if (VA.getLocInfo() != CCValAssign::Full) - ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue); + ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); // Handle MMX values passed in GPRs. if (Is64Bit && RegVT != VA.getLocVT()) { if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass) - ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue); + ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue); else if (RC == X86::VR128RegisterClass) { - ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue, - DAG.getConstant(0, MVT::i64)); - ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue); + ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, + ArgValue, DAG.getConstant(0, MVT::i64)); + ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue); } } @@ -1343,7 +1347,7 @@ FuncInfo->setSRetReturnReg(Reg); } SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]); - Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root); + Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root); } unsigned StackSize = CCInfo.getNextStackOffset(); @@ -1408,36 +1412,36 @@ // Store the integer parameter registers. SmallVector MemOps; SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); - SDValue FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, + SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, DAG.getIntPtrConstant(VarArgsGPOffset)); for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs], X86::GR64RegisterClass); SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64); SDValue Store = - DAG.getStore(Val.getValue(1), Val, FIN, + DAG.getStore(Val.getValue(1), dl, Val, FIN, PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0); MemOps.push_back(Store); - FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, + FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, DAG.getIntPtrConstant(8)); } // Now store the XMM (fp + vector) parameter registers. - FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, + FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, DAG.getIntPtrConstant(VarArgsFPOffset)); for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass); SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32); SDValue Store = - DAG.getStore(Val.getValue(1), Val, FIN, + DAG.getStore(Val.getValue(1), dl, Val, FIN, PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0); MemOps.push_back(Store); - FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, + FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, DAG.getIntPtrConstant(16)); } if (!MemOps.empty()) - Root = DAG.getNode(ISD::TokenFactor, MVT::Other, + Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0], MemOps.size()); } } @@ -1465,7 +1469,7 @@ FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn); // Return the new list of results. - return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), &ArgValues[0], ArgValues.size()).getValue(Op.getResNo()); } @@ -1475,13 +1479,14 @@ const CCValAssign &VA, SDValue Chain, SDValue Arg, ISD::ArgFlagsTy Flags) { + DebugLoc dl = TheCall->getDebugLoc(); unsigned LocMemOffset = VA.getLocMemOffset(); SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); - PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); + PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); if (Flags.isByVal()) { return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG); } - return DAG.getStore(Chain, Arg, PtrOff, + return DAG.getStore(Chain, dl, Arg, PtrOff, PseudoSourceValue::getStack(), LocMemOffset); } @@ -1493,7 +1498,8 @@ SDValue Chain, bool IsTailCall, bool Is64Bit, - int FPDiff) { + int FPDiff, + DebugLoc dl) { if (!IsTailCall || FPDiff==0) return Chain; // Adjust the Return address stack slot. @@ -1501,7 +1507,7 @@ OutRetAddr = getReturnAddressFrameIndex(DAG); // Load the "old" Return address. - OutRetAddr = DAG.getLoad(VT, Chain, OutRetAddr, NULL, 0); + OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0); return SDValue(OutRetAddr.getNode(), 1); } @@ -1510,7 +1516,7 @@ static SDValue EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, SDValue Chain, SDValue RetAddrFrIdx, - bool Is64Bit, int FPDiff) { + bool Is64Bit, int FPDiff, DebugLoc dl) { // Store the return address to the appropriate stack slot. if (!FPDiff) return Chain; // Calculate the new stack slot for the return address. @@ -1519,7 +1525,7 @@ MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize); MVT VT = Is64Bit ? MVT::i64 : MVT::i32; SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); - Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx, + Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0); return Chain; } @@ -1535,6 +1541,7 @@ SDValue Callee = TheCall->getCallee(); bool Is64Bit = Subtarget->is64Bit(); bool IsStructRet = CallIsStructReturn(TheCall); + DebugLoc dl = TheCall->getDebugLoc(); assert(!(isVarArg && CC == CallingConv::Fast) && "Var args not supported with calling convention fastcc"); @@ -1567,7 +1574,7 @@ SDValue RetAddrFrIdx; // Load return adress for tail calls. Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit, - FPDiff); + FPDiff, dl); SmallVector, 8> RegsToPass; SmallVector MemOpChains; @@ -1586,13 +1593,13 @@ default: assert(0 && "Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: - Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); + Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); break; case CCValAssign::ZExt: - Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); + Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); break; case CCValAssign::AExt: - Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); + Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); break; } @@ -1606,17 +1613,17 @@ case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX: case X86::R8: { // Special case: passing MMX values in GPR registers. - Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg); + Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); break; } case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3: case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: { // Special case: passing MMX values in XMM registers. - Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg); - Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg); - Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64, - DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg, - getMOVLMask(2, DAG)); + Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); + Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); + Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2i64, + DAG.getNode(ISD::UNDEF, dl, MVT::v2i64), Arg, + getMOVLMask(2, DAG, dl)); break; } } @@ -1635,7 +1642,7 @@ } if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token chain @@ -1723,21 +1730,21 @@ SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); if (StackPtr.getNode() == 0) StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy()); - Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source); + Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain, Flags, DAG)); } else { // Store relative to framepointer. MemOpChains2.push_back( - DAG.getStore(Chain, Arg, FIN, + DAG.getStore(Chain, dl, Arg, FIN, PseudoSourceValue::getFixedStack(FI), 0)); } } } if (!MemOpChains2.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains2[0], MemOpChains2.size()); // Copy arguments to their registers. @@ -1750,7 +1757,7 @@ // Store the return address to the appropriate stack slot. Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, - FPDiff); + FPDiff, dl); } // If the callee is a GlobalAddress node (quite common, every direct call is) @@ -1821,13 +1828,13 @@ if (IsTailCall) { assert(InFlag.getNode() && "Flag must be set. Depend on flag being set in LowerRET"); - Chain = DAG.getNode(X86ISD::TAILCALL, + Chain = DAG.getNode(X86ISD::TAILCALL, dl, TheCall->getVTList(), &Ops[0], Ops.size()); return SDValue(Chain.getNode(), Op.getResNo()); } - Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size()); + Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); InFlag = Chain.getValue(1); // Create the CALLSEQ_END node. @@ -2714,11 +2721,12 @@ MVT EltVT = MaskVT.getVectorElementType(); unsigned NumElems = Mask.getNumOperands(); SmallVector MaskVec; + DebugLoc dl = Op.getNode()->getDebugLoc(); for (unsigned i = 0; i != NumElems; ++i) { SDValue Arg = Mask.getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) { - MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT)); + MaskVec.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT)); continue; } assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); @@ -2730,14 +2738,14 @@ } std::swap(V1, V2); - Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems); - return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); + Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], NumElems); + return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, Mask); } /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming /// the two vector operands have swapped position. static -SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG) { +SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG, DebugLoc dl) { MVT MaskVT = Mask.getValueType(); MVT EltVT = MaskVT.getVectorElementType(); unsigned NumElems = Mask.getNumOperands(); @@ -2745,7 +2753,7 @@ for (unsigned i = 0; i != NumElems; ++i) { SDValue Arg = Mask.getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) { - MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT)); + MaskVec.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT)); continue; } assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); @@ -2755,7 +2763,7 @@ else MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT)); } - return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems); + return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], NumElems); } @@ -2897,7 +2905,8 @@ /// getZeroVector - Returns a vector of specified type with all zero elements. /// -static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) { +static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG, + DebugLoc dl) { assert(VT.isVector() && "Expected a vector type"); // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest @@ -2905,20 +2914,20 @@ SDValue Vec; if (VT.getSizeInBits() == 64) { // MMX SDValue Cst = DAG.getTargetConstant(0, MVT::i32); - Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); } else if (HasSSE2) { // SSE2 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); - Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst); + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); } else { // SSE1 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); - Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst); + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); } - return DAG.getNode(ISD::BIT_CONVERT, VT, Vec); + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); } /// getOnesVector - Returns a vector of specified type with all bits set. /// -static SDValue getOnesVector(MVT VT, SelectionDAG &DAG) { +static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) { assert(VT.isVector() && "Expected a vector type"); // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest @@ -2926,10 +2935,10 @@ SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); SDValue Vec; if (VT.getSizeInBits() == 64) // MMX - Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); else // SSE - Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst); - return DAG.getNode(ISD::BIT_CONVERT, VT, Vec); + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); } @@ -2954,14 +2963,15 @@ } if (Changed) - Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), + Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getNode()->getDebugLoc(), + Mask.getValueType(), &MaskVec[0], MaskVec.size()); return Mask; } /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd /// operation of specified width. -static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG) { +static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG, DebugLoc dl) { MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); MVT BaseVT = MaskVT.getVectorElementType(); @@ -2969,12 +2979,14 @@ MaskVec.push_back(DAG.getConstant(NumElems, BaseVT)); for (unsigned i = 1; i != NumElems; ++i) MaskVec.push_back(DAG.getConstant(i, BaseVT)); - return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); + return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, + &MaskVec[0], MaskVec.size()); } /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation /// of specified width. -static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) { +static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG, + DebugLoc dl) { MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); MVT BaseVT = MaskVT.getVectorElementType(); SmallVector MaskVec; @@ -2982,12 +2994,14 @@ MaskVec.push_back(DAG.getConstant(i, BaseVT)); MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT)); } - return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); + return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, + &MaskVec[0], MaskVec.size()); } /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation /// of specified width. -static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) { +static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG, + DebugLoc dl) { MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); MVT BaseVT = MaskVT.getVectorElementType(); unsigned Half = NumElems/2; @@ -2996,14 +3010,15 @@ MaskVec.push_back(DAG.getConstant(i + Half, BaseVT)); MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT)); } - return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); + return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, + &MaskVec[0], MaskVec.size()); } /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps /// element #0 of a vector with the specified index, leaving the rest of the /// elements in place. static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt, - SelectionDAG &DAG) { + SelectionDAG &DAG, DebugLoc dl) { MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); MVT BaseVT = MaskVT.getVectorElementType(); SmallVector MaskVec; @@ -3011,7 +3026,8 @@ MaskVec.push_back(DAG.getConstant(DestElt, BaseVT)); for (unsigned i = 1; i != NumElems; ++i) MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT)); - return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); + return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, + &MaskVec[0], MaskVec.size()); } /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32. @@ -3024,6 +3040,7 @@ SDValue Mask = Op.getOperand(2); unsigned MaskNumElems = Mask.getNumOperands(); unsigned NumElems = MaskNumElems; + DebugLoc dl = Op.getNode()->getDebugLoc(); // Special handling of v4f32 -> v4i32. if (VT != MVT::v4f32) { // Find which element we want to splat. @@ -3032,22 +3049,22 @@ // unpack elements to the correct location while (NumElems > 4) { if (EltNo < NumElems/2) { - Mask = getUnpacklMask(MaskNumElems, DAG); + Mask = getUnpacklMask(MaskNumElems, DAG, dl); } else { - Mask = getUnpackhMask(MaskNumElems, DAG); + Mask = getUnpackhMask(MaskNumElems, DAG, dl); EltNo -= NumElems/2; } - V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask); + V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V1, Mask); NumElems >>= 1; } SDValue Cst = DAG.getConstant(EltNo, MVT::i32); - Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst); + Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); } - V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1); - SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1, + V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1); + SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, PVT, V1, DAG.getNode(ISD::UNDEF, PVT), Mask); - return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle); + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuffle); } /// isVectorLoad - Returns true if the node is a vector load, a scalar @@ -3073,21 +3090,23 @@ MVT VT = Op.getValueType(); if (VT == PVT) return Op; + DebugLoc dl = Op.getNode()->getDebugLoc(); unsigned NumElems = PVT.getVectorNumElements(); if (NumElems == 2) { SDValue Cst = DAG.getTargetConstant(0, MVT::i32); - Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); + Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); } else { assert(NumElems == 4); SDValue Cst0 = DAG.getTargetConstant(0, MVT::i32); SDValue Cst1 = DAG.getTargetConstant(1, MVT::i32); - Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst0, Cst1, Cst0, Cst1); + Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + Cst0, Cst1, Cst0, Cst1); } - V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1); - SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1, - DAG.getNode(ISD::UNDEF, PVT), Mask); - return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle); + V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1); + SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, PVT, V1, + DAG.getNode(ISD::UNDEF, dl, PVT), Mask); + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuffle); } /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified @@ -3097,9 +3116,10 @@ static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, bool isZero, bool HasSSE2, SelectionDAG &DAG) { + DebugLoc dl = V2.getNode()->getDebugLoc(); MVT VT = V2.getValueType(); SDValue V1 = isZero - ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT); + ? getZeroVector(VT, HasSSE2, DAG, dl) : DAG.getNode(ISD::UNDEF, dl, VT); unsigned NumElems = V2.getValueType().getVectorNumElements(); MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); MVT EVT = MaskVT.getVectorElementType(); @@ -3109,9 +3129,9 @@ MaskVec.push_back(DAG.getConstant(NumElems, EVT)); else MaskVec.push_back(DAG.getConstant(i, EVT)); - SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], MaskVec.size()); - return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); + return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, Mask); } /// getNumOfConsecutiveZeros - Return the number of elements in a result of @@ -3186,15 +3206,16 @@ if (NumNonZero > 8) return SDValue(); + DebugLoc dl = Op.getNode()->getDebugLoc(); SDValue V(0, 0); bool First = true; for (unsigned i = 0; i < 16; ++i) { bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; if (ThisIsNonZero && First) { if (NumZero) - V = getZeroVector(MVT::v8i16, true, DAG); + V = getZeroVector(MVT::v8i16, true, DAG, dl); else - V = DAG.getNode(ISD::UNDEF, MVT::v8i16); + V = DAG.getNode(ISD::UNDEF, dl, MVT::v8i16); First = false; } @@ -3202,24 +3223,25 @@ SDValue ThisElt(0, 0), LastElt(0, 0); bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; if (LastIsNonZero) { - LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1)); + LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, + MVT::i16, Op.getOperand(i-1)); } if (ThisIsNonZero) { - ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i)); - ThisElt = DAG.getNode(ISD::SHL, MVT::i16, + ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); + ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, ThisElt, DAG.getConstant(8, MVT::i8)); if (LastIsNonZero) - ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt); + ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); } else ThisElt = LastElt; if (ThisElt.getNode()) - V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt, + V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, DAG.getIntPtrConstant(i/2)); } } - return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V); + return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V); } /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. @@ -3230,6 +3252,7 @@ if (NumNonZero > 4) return SDValue(); + DebugLoc dl = Op.getNode()->getDebugLoc(); SDValue V(0, 0); bool First = true; for (unsigned i = 0; i < 8; ++i) { @@ -3237,12 +3260,13 @@ if (isNonZero) { if (First) { if (NumZero) - V = getZeroVector(MVT::v8i16, true, DAG); + V = getZeroVector(MVT::v8i16, true, DAG, dl); else - V = DAG.getNode(ISD::UNDEF, MVT::v8i16); + V = DAG.getNode(ISD::UNDEF, dl, MVT::v8i16); First = false; } - V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i), + V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, + MVT::v8i16, V, Op.getOperand(i), DAG.getIntPtrConstant(i)); } } @@ -3254,18 +3278,19 @@ /// static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp, unsigned NumBits, SelectionDAG &DAG, - const TargetLowering &TLI) { + const TargetLowering &TLI, DebugLoc dl) { bool isMMX = VT.getSizeInBits() == 64; MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; - SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp); - return DAG.getNode(ISD::BIT_CONVERT, VT, - DAG.getNode(Opc, ShVT, SrcOp, + SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp); + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, + DAG.getNode(Opc, dl, ShVT, SrcOp, DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); } SDValue X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); // All zero's are handled with pxor, all one's are handled with pcmpeqd. if (ISD::isBuildVectorAllZeros(Op.getNode()) || ISD::isBuildVectorAllOnes(Op.getNode())) { @@ -3276,8 +3301,8 @@ return Op; if (ISD::isBuildVectorAllOnes(Op.getNode())) - return getOnesVector(Op.getValueType(), DAG); - return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG); + return getOnesVector(Op.getValueType(), DAG, dl); + return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); } MVT VT = Op.getValueType(); @@ -3308,7 +3333,7 @@ if (NumNonZero == 0) { // All undef vector. Return an UNDEF. All zero vectors were handled above. - return DAG.getNode(ISD::UNDEF, VT); + return DAG.getNode(ISD::UNDEF, dl, VT); } // Special case for single non-zero, non-undef, element. @@ -3330,8 +3355,8 @@ // Truncate the value (which may itself be a constant) to i32, and // convert it to a vector with movd (S2V+shuffle to zero extend). - Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item); - Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item); + Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); + Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), DAG); @@ -3339,12 +3364,12 @@ // a vector. If Idx != 0, swizzle it into place. if (Idx != 0) { SDValue Ops[] = { - Item, DAG.getNode(ISD::UNDEF, Item.getValueType()), - getSwapEltZeroMask(VecElts, Idx, DAG) + Item, DAG.getNode(ISD::UNDEF, dl, Item.getValueType()), + getSwapEltZeroMask(VecElts, Idx, DAG, dl) }; - Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3); + Item = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VecVT, Ops, 3); } - return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item); + return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item); } } @@ -3356,7 +3381,7 @@ if (Idx == 0 && // Don't do this for i64 values on x86-32. (EVT != MVT::i64 || Subtarget->is64Bit())) { - Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item); + Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget->hasSSE2(), DAG); @@ -3368,7 +3393,7 @@ unsigned NumBits = VT.getSizeInBits(); return getVShift(true, VT, DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)), - NumBits/2, DAG, *this); + NumBits/2, DAG, *this, dl); } if (IsAllConstants) // Otherwise, it's better to do a constpool load. @@ -3380,7 +3405,7 @@ // movd/movss) to move this into the low element, then shuffle it into // place. if (EVTBits == 32) { - Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item); + Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); // Turn it into a shuffle of zero and zero-extended scalar to vector. Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, @@ -3390,9 +3415,9 @@ SmallVector MaskVec; for (unsigned i = 0; i < NumElems; i++) MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT)); - SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], MaskVec.size()); - return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item, + return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, Item, DAG.getNode(ISD::UNDEF, VT), Mask); } } @@ -3411,7 +3436,7 @@ if (NumNonZero == 1) { // One half is zero or undef. unsigned Idx = CountTrailingZeros_32(NonZeros); - SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, + SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(Idx)); return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget->hasSSE2(), DAG); @@ -3439,9 +3464,9 @@ for (unsigned i = 0; i < 4; ++i) { bool isZero = !(NonZeros & (1 << i)); if (isZero) - V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG); + V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); else - V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); + V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); } for (unsigned i = 0; i < 2; ++i) { @@ -3451,16 +3476,16 @@ V[i] = V[i*2]; // Must be a zero vector. break; case 1: - V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2], - getMOVLMask(NumElems, DAG)); + V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2+1], V[i*2], + getMOVLMask(NumElems, DAG, dl)); break; case 2: - V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1], - getMOVLMask(NumElems, DAG)); + V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2], V[i*2+1], + getMOVLMask(NumElems, DAG, dl)); break; case 3: - V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1], - getUnpacklMask(NumElems, DAG)); + V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2], V[i*2+1], + getUnpacklMask(NumElems, DAG, dl)); break; } } @@ -3480,9 +3505,9 @@ MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT)); else MaskVec.push_back(DAG.getConstant(i+NumElems, EVT)); - SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], MaskVec.size()); - return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask); + return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[0], V[1], ShufMask); } if (Values.size() > 2) { @@ -3491,13 +3516,13 @@ // Step 1: unpcklps 0, 2 ==> X: // : unpcklps 1, 3 ==> Y: // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> - SDValue UnpckMask = getUnpacklMask(NumElems, DAG); + SDValue UnpckMask = getUnpacklMask(NumElems, DAG, dl); for (unsigned i = 0; i < NumElems; ++i) - V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); + V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); NumElems >>= 1; while (NumElems != 0) { for (unsigned i = 0; i < NumElems; ++i) - V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems], + V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i], V[i + NumElems], UnpckMask); NumElems >>= 1; } @@ -3510,7 +3535,7 @@ static SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2, SDValue PermMask, SelectionDAG &DAG, - TargetLowering &TLI) { + TargetLowering &TLI, DebugLoc dl) { SDValue NewV; MVT MaskVT = MVT::getIntVectorWithNumElements(8); MVT MaskEVT = MaskVT.getVectorElementType(); @@ -3573,11 +3598,11 @@ else MaskVec.push_back(DAG.getConstant(1, MVT::i32)); - SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2); - NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64, - DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1), - DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask); - NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV); + SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, &MaskVec[0],2); + NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2i64, + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1), + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), Mask); + NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV); // Now sort high and low parts separately. BitVector InOrder(8); @@ -3607,8 +3632,10 @@ if (AnyOutOrder) { for (unsigned i = 4; i != 8; ++i) MaskVec.push_back(DAG.getConstant(i, MaskEVT)); - SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); - NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask); + SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, + &MaskVec[0], 8); + NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, + NewV, NewV, Mask); } } @@ -3640,8 +3667,10 @@ } if (AnyOutOrder) { - SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); - NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask); + SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, + MaskVT, &MaskVec[0], 8); + NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, + NewV, NewV, Mask); } } @@ -3654,11 +3683,11 @@ continue; unsigned EltIdx = cast(Elt)->getZExtValue(); SDValue ExtOp = (EltIdx < 8) - ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1, + ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, DAG.getConstant(EltIdx, PtrVT)) - : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2, + : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, DAG.getConstant(EltIdx - 8, PtrVT)); - NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, + NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, DAG.getConstant(i, PtrVT)); } @@ -3704,7 +3733,7 @@ } if (V2InOrder > V1InOrder) { - PermMask = CommuteVectorShuffleMask(PermMask, DAG); + PermMask = CommuteVectorShuffleMask(PermMask, DAG, dl); std::swap(V1, V2); std::swap(V1Elts, V2Elts); std::swap(V1FromV1, V2FromV2); @@ -3719,17 +3748,17 @@ for (unsigned i = 0; i < 8; ++i) { SDValue Elt = V1Elts[i]; if (Elt.getOpcode() == ISD::UNDEF) { - MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); + MaskVec.push_back(DAG.getNode(ISD::UNDEF, dl, MaskEVT)); continue; } unsigned EltIdx = cast(Elt)->getZExtValue(); if (EltIdx >= 8) - MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); + MaskVec.push_back(DAG.getNode(ISD::UNDEF, dl, MaskEVT)); else MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT)); } - SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); - V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask); + SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], 8); + V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, V1, V1, Mask); } NewV = V1; @@ -3740,9 +3769,9 @@ unsigned EltIdx = cast(Elt)->getZExtValue(); if (EltIdx < 8) continue; - SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2, + SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, DAG.getConstant(EltIdx - 8, PtrVT)); - NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, + NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, DAG.getConstant(i, PtrVT)); } return NewV; @@ -3754,9 +3783,9 @@ if (Elt.getOpcode() == ISD::UNDEF) continue; unsigned EltIdx = cast(Elt)->getZExtValue(); - SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1, + SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, DAG.getConstant(EltIdx, PtrVT)); - NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, + NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, DAG.getConstant(i, PtrVT)); } return NewV; @@ -3772,7 +3801,7 @@ SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2, MVT VT, SDValue PermMask, SelectionDAG &DAG, - TargetLowering &TLI) { + TargetLowering &TLI, DebugLoc dl) { unsigned NumElems = PermMask.getNumOperands(); unsigned NewWidth = (NumElems == 4) ? 2 : 4; MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth); @@ -3807,15 +3836,15 @@ return SDValue(); } if (StartIdx == ~0U) - MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEltVT)); + MaskVec.push_back(DAG.getNode(ISD::UNDEF, dl, MaskEltVT)); else MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT)); } - V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1); - V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2); - return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2, - DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1); + V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2); + return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NewVT, V1, V2, + DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], MaskVec.size())); } @@ -3823,7 +3852,7 @@ /// static SDValue getVZextMovL(MVT VT, MVT OpVT, SDValue SrcOp, SelectionDAG &DAG, - const X86Subtarget *Subtarget) { + const X86Subtarget *Subtarget, DebugLoc dl) { if (VT == MVT::v2f64 || VT == MVT::v4f32) { LoadSDNode *LD = NULL; if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) @@ -3838,30 +3867,33 @@ SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) { // PR2108 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; - return DAG.getNode(ISD::BIT_CONVERT, VT, - DAG.getNode(X86ISD::VZEXT_MOVL, OpVT, - DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT, + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, + DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, + DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, + OpVT, SrcOp.getOperand(0) .getOperand(0)))); } } } - return DAG.getNode(ISD::BIT_CONVERT, VT, - DAG.getNode(X86ISD::VZEXT_MOVL, OpVT, - DAG.getNode(ISD::BIT_CONVERT, OpVT, SrcOp))); + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, + DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, + DAG.getNode(ISD::BIT_CONVERT, dl, + OpVT, SrcOp))); } /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of /// shuffles. static SDValue LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2, - SDValue PermMask, MVT VT, SelectionDAG &DAG) { + SDValue PermMask, MVT VT, SelectionDAG &DAG, + DebugLoc dl) { MVT MaskVT = PermMask.getValueType(); MVT MaskEVT = MaskVT.getVectorElementType(); SmallVector, 8> Locs; Locs.resize(4); - SmallVector Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT)); + SmallVector Mask1(4, DAG.getNode(ISD::UNDEF, dl, MaskEVT)); unsigned NumHi = 0; unsigned NumLo = 0; for (unsigned i = 0; i != 4; ++i) { @@ -3889,11 +3921,11 @@ // implemented with two shuffles. First shuffle gather the elements. // The second shuffle, which takes the first shuffle as both of its // vector operands, put the elements into the right order. - V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, - DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, + DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &Mask1[0], Mask1.size())); - SmallVector Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT)); + SmallVector Mask2(4, DAG.getNode(ISD::UNDEF, dl, MaskEVT)); for (unsigned i = 0; i != 4; ++i) { if (Locs[i].first == -1) continue; @@ -3904,8 +3936,8 @@ } } - return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, - DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V1, + DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &Mask2[0], Mask2.size())); } else if (NumLo == 3 || NumHi == 3) { // Otherwise, we must have three elements from one vector, call it X, and @@ -3917,7 +3949,7 @@ // from X. if (NumHi == 3) { // Normalize it so the 3 elements come from V1. - PermMask = CommuteVectorShuffleMask(PermMask, DAG); + PermMask = CommuteVectorShuffleMask(PermMask, DAG, dl); std::swap(V1, V2); } @@ -3933,10 +3965,10 @@ } Mask1[0] = PermMask.getOperand(HiIndex); - Mask1[1] = DAG.getNode(ISD::UNDEF, MaskEVT); + Mask1[1] = DAG.getNode(ISD::UNDEF, dl, MaskEVT); Mask1[2] = PermMask.getOperand(HiIndex^1); - Mask1[3] = DAG.getNode(ISD::UNDEF, MaskEVT); - V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, + Mask1[3] = DAG.getNode(ISD::UNDEF, dl, MaskEVT); + V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4)); if (HiIndex >= 2) { @@ -3944,8 +3976,9 @@ Mask1[1] = PermMask.getOperand(1); Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT); Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT); - return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, - DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4)); + return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, + DAG.getNode(ISD::BUILD_VECTOR, dl, + MaskVT, &Mask1[0], 4)); } else { Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT); Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT); @@ -3959,8 +3992,9 @@ Mask1[3] = DAG.getConstant(cast(Mask1[3])->getZExtValue()+4, MaskEVT); - return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1, - DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4)); + return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V2, V1, + DAG.getNode(ISD::BUILD_VECTOR, dl, + MaskVT, &Mask1[0], 4)); } } @@ -3993,23 +4027,23 @@ } } - SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, - DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, + DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &LoMask[0], LoMask.size())); - SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, - DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, + DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &HiMask[0], HiMask.size())); SmallVector MaskOps; for (unsigned i = 0; i != 4; ++i) { if (Locs[i].first == -1) { - MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); + MaskOps.push_back(DAG.getNode(ISD::UNDEF, dl, MaskEVT)); } else { unsigned Idx = Locs[i].first * 4 + Locs[i].second; MaskOps.push_back(DAG.getConstant(Idx, MaskEVT)); } } - return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle, - DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, LoShuffle, HiShuffle, + DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskOps[0], MaskOps.size())); } @@ -4019,6 +4053,7 @@ SDValue V2 = Op.getOperand(1); SDValue PermMask = Op.getOperand(2); MVT VT = Op.getValueType(); + DebugLoc dl = Op.getNode()->getDebugLoc(); unsigned NumElems = PermMask.getNumOperands(); bool isMMX = VT.getSizeInBits() == 64; bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; @@ -4027,10 +4062,10 @@ bool V2IsSplat = false; if (isUndefShuffle(Op.getNode())) - return DAG.getNode(ISD::UNDEF, VT); + return DAG.getNode(ISD::UNDEF, dl, VT); if (isZeroShuffle(Op.getNode())) - return getZeroVector(VT, Subtarget->hasSSE2(), DAG); + return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); if (isIdentityMask(PermMask.getNode())) return V1; @@ -4052,30 +4087,33 @@ // If the shuffle can be profitably rewritten as a narrower shuffle, then // do it! if (VT == MVT::v8i16 || VT == MVT::v16i8) { - SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this); + SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, + *this, dl); if (NewOp.getNode()) - return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG)); + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, + LowerVECTOR_SHUFFLE(NewOp, DAG)); } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { // FIXME: Figure out a cleaner way to do this. // Try to make use of movq to zero out the top part. if (ISD::isBuildVectorAllZeros(V2.getNode())) { SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, - DAG, *this); + DAG, *this, dl); if (NewOp.getNode()) { SDValue NewV1 = NewOp.getOperand(0); SDValue NewV2 = NewOp.getOperand(1); SDValue NewMask = NewOp.getOperand(2); if (isCommutedMOVL(NewMask.getNode(), true, false)) { NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG); - return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget); + return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget, + dl); } } } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, - DAG, *this); + DAG, *this, dl); if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode())) return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), - DAG, Subtarget); + DAG, Subtarget, dl); } } @@ -4089,14 +4127,14 @@ // v_set0 + movlhps or movhlps, etc. MVT EVT = VT.getVectorElementType(); ShAmt *= EVT.getSizeInBits(); - return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this); + return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); } if (X86::isMOVLMask(PermMask.getNode())) { if (V1IsUndef) return V2; if (ISD::isBuildVectorAllZeros(V1.getNode())) - return getVZextMovL(VT, VT, V2, DAG, Subtarget); + return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); if (!isMMX) return Op; } @@ -4116,7 +4154,7 @@ // No better options. Use a vshl / vsrl. MVT EVT = VT.getVectorElementType(); ShAmt *= EVT.getSizeInBits(); - return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this); + return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); } bool Commuted = false; @@ -4141,9 +4179,9 @@ // V2 is a splat, so the mask may be malformed. That is, it may point // to any V2 element. The instruction selectior won't like this. Get // a corrected mask and commute to form a proper MOVS{S|D}. - SDValue NewMask = getMOVLMask(NumElems, DAG); + SDValue NewMask = getMOVLMask(NumElems, DAG, dl); if (NewMask.getNode() != PermMask.getNode()) - Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); + Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask); } return Op; } @@ -4161,11 +4199,11 @@ SDValue NewMask = NormalizeMask(PermMask, DAG); if (NewMask.getNode() != PermMask.getNode()) { if (X86::isUNPCKLMask(PermMask.getNode(), true)) { - SDValue NewMask = getUnpacklMask(NumElems, DAG); - return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); + SDValue NewMask = getUnpacklMask(NumElems, DAG, dl); + return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask); } else if (X86::isUNPCKHMask(PermMask.getNode(), true)) { - SDValue NewMask = getUnpackhMask(NumElems, DAG); - return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); + SDValue NewMask = getUnpackhMask(NumElems, DAG, dl); + return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask); } } } @@ -4189,7 +4227,7 @@ // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented. if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) { if (V2.getOpcode() != ISD::UNDEF) - return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, + return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, DAG.getNode(ISD::UNDEF, VT), PermMask); return Op; } @@ -4202,14 +4240,14 @@ MVT RVT = VT; if (VT == MVT::v4f32) { RVT = MVT::v4i32; - Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, - DAG.getNode(ISD::BIT_CONVERT, RVT, V1), - DAG.getNode(ISD::UNDEF, RVT), PermMask); + Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, RVT, + DAG.getNode(ISD::BIT_CONVERT, dl, RVT, V1), + DAG.getNode(ISD::UNDEF, dl, RVT), PermMask); } else if (V2.getOpcode() != ISD::UNDEF) - Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1, - DAG.getNode(ISD::UNDEF, RVT), PermMask); + Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, RVT, V1, + DAG.getNode(ISD::UNDEF, dl, RVT), PermMask); if (RVT != VT) - Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op); + Op = DAG.getNode(ISD::BIT_CONVERT, dl, VT, Op); return Op; } @@ -4221,14 +4259,14 @@ // Handle v8i16 specifically since SSE can do byte extraction and insertion. if (VT == MVT::v8i16) { - SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this); + SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this, dl); if (NewOp.getNode()) return NewOp; } // Handle all 4 wide cases with a number of shuffles except for MMX. if (NumElems == 4 && !isMMX) - return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG); + return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG, dl); return SDValue(); } @@ -4237,26 +4275,28 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); + DebugLoc dl = Op.getNode()->getDebugLoc(); if (VT.getSizeInBits() == 8) { - SDValue Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32, + SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, Op.getOperand(0), Op.getOperand(1)); - SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, + SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, DAG.getValueType(VT)); - return DAG.getNode(ISD::TRUNCATE, VT, Assert); + return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); } else if (VT.getSizeInBits() == 16) { unsigned Idx = cast(Op.getOperand(1))->getZExtValue(); // If Idx is 0, it's cheaper to do a move instead of a pextrw. if (Idx == 0) - return DAG.getNode(ISD::TRUNCATE, MVT::i16, - DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, - DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, + return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, + DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, + DAG.getNode(ISD::BIT_CONVERT, dl, + MVT::v4i32, Op.getOperand(0)), Op.getOperand(1))); - SDValue Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32, + SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, Op.getOperand(0), Op.getOperand(1)); - SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, + SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, DAG.getValueType(VT)); - return DAG.getNode(ISD::TRUNCATE, VT, Assert); + return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); } else if (VT == MVT::f32) { // EXTRACTPS outputs to a GPR32 register which will require a movd to copy // the result back to FR32 register. It's only worth matching if the @@ -4272,10 +4312,11 @@ (User->getOpcode() != ISD::BIT_CONVERT || User->getValueType(0) != MVT::i32)) return SDValue(); - SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, - DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)), - Op.getOperand(1)); - return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract); + SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, + Op.getOperand(0)), + Op.getOperand(1)); + return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract); } else if (VT == MVT::i32) { // ExtractPS works with constant index. if (isa(Op.getOperand(1))) @@ -4297,22 +4338,24 @@ } MVT VT = Op.getValueType(); + DebugLoc dl = Op.getNode()->getDebugLoc(); // TODO: handle v16i8. if (VT.getSizeInBits() == 16) { SDValue Vec = Op.getOperand(0); unsigned Idx = cast(Op.getOperand(1))->getZExtValue(); if (Idx == 0) - return DAG.getNode(ISD::TRUNCATE, MVT::i16, - DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, - DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec), + return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, + DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, + DAG.getNode(ISD::BIT_CONVERT, dl, + MVT::v4i32, Vec), Op.getOperand(1))); // Transform it so it match pextrw which produces a 32-bit result. MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1); - SDValue Extract = DAG.getNode(X86ISD::PEXTRW, EVT, + SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT, Op.getOperand(0), Op.getOperand(1)); - SDValue Assert = DAG.getNode(ISD::AssertZext, EVT, Extract, + SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract, DAG.getValueType(VT)); - return DAG.getNode(ISD::TRUNCATE, VT, Assert); + return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); } else if (VT.getSizeInBits() == 32) { unsigned Idx = cast(Op.getOperand(1))->getZExtValue(); if (Idx == 0) @@ -4323,17 +4366,18 @@ IdxVec. push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType())); IdxVec. - push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); + push_back(DAG.getNode(ISD::UNDEF, dl, MaskVT.getVectorElementType())); IdxVec. - push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); + push_back(DAG.getNode(ISD::UNDEF, dl, MaskVT.getVectorElementType())); IdxVec. - push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); - SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + push_back(DAG.getNode(ISD::UNDEF, dl, MaskVT.getVectorElementType())); + SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &IdxVec[0], IdxVec.size()); SDValue Vec = Op.getOperand(0); - Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), - Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); - return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, + Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(), + Vec, DAG.getNode(ISD::UNDEF, dl, Vec.getValueType()), + Mask); + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, DAG.getIntPtrConstant(0)); } else if (VT.getSizeInBits() == 64) { // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b @@ -4350,13 +4394,14 @@ SmallVector IdxVec; IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType())); IdxVec. - push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); - SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + push_back(DAG.getNode(ISD::UNDEF, dl, MaskVT.getVectorElementType())); + SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &IdxVec[0], IdxVec.size()); SDValue Vec = Op.getOperand(0); - Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), - Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); - return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, + Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(), + Vec, DAG.getNode(ISD::UNDEF, dl, Vec.getValueType()), + Mask); + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, DAG.getIntPtrConstant(0)); } @@ -4367,6 +4412,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ MVT VT = Op.getValueType(); MVT EVT = VT.getVectorElementType(); + DebugLoc dl = Op.getNode()->getDebugLoc(); SDValue N0 = Op.getOperand(0); SDValue N1 = Op.getOperand(1); @@ -4379,10 +4425,10 @@ // Transform it so it match pinsr{b,w} which expects a GR32 as its second // argument. if (N1.getValueType() != MVT::i32) - N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1); + N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); if (N2.getValueType() != MVT::i32) N2 = DAG.getIntPtrConstant(cast(N2)->getZExtValue()); - return DAG.getNode(Opc, VT, N0, N1, N2); + return DAG.getNode(Opc, dl, VT, N0, N1, N2); } else if (EVT == MVT::f32 && isa(N2)) { // Bits [7:6] of the constant are the source select. This will always be // zero here. The DAG Combiner may combine an extract_elt index into these @@ -4393,7 +4439,7 @@ // Bits [3:0] of the constant are the zero mask. The DAG Combiner may // combine either bitwise AND or insert of float 0.0 to set these bits. N2 = DAG.getIntPtrConstant(cast(N2)->getZExtValue() << 4); - return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2); + return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); } else if (EVT == MVT::i32) { // InsertPS works with constant index. if (isa(N2)) @@ -4413,6 +4459,7 @@ if (EVT == MVT::i8) return SDValue(); + DebugLoc dl = Op.getNode()->getDebugLoc(); SDValue N0 = Op.getOperand(0); SDValue N1 = Op.getOperand(1); SDValue N2 = Op.getOperand(2); @@ -4421,23 +4468,24 @@ // Transform it so it match pinsrw which expects a 16-bit value in a GR32 // as its second argument. if (N1.getValueType() != MVT::i32) - N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1); + N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); if (N2.getValueType() != MVT::i32) N2 = DAG.getIntPtrConstant(cast(N2)->getZExtValue()); - return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2); + return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); } return SDValue(); } SDValue X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); if (Op.getValueType() == MVT::v2f32) - return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f32, - DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i32, - DAG.getNode(ISD::BIT_CONVERT, MVT::i32, + return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32, + DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32, + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op.getOperand(0)))); - SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0)); + SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); MVT VT = MVT::v2i32; switch (Op.getValueType().getSimpleVT()) { default: break; @@ -4446,8 +4494,8 @@ VT = MVT::v4i32; break; } - return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), - DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt)); + return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), + DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt)); } // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as @@ -4673,26 +4721,28 @@ assert(Op.getNumOperands() == 3 && "Not a double-shift!"); MVT VT = Op.getValueType(); unsigned VTBits = VT.getSizeInBits(); + DebugLoc dl = Op.getNode()->getDebugLoc(); bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; SDValue ShOpLo = Op.getOperand(0); SDValue ShOpHi = Op.getOperand(1); SDValue ShAmt = Op.getOperand(2); SDValue Tmp1 = isSRA ? - DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) : + DAG.getNode(ISD::SRA, dl, VT, ShOpHi, + DAG.getConstant(VTBits - 1, MVT::i8)) : DAG.getConstant(0, VT); SDValue Tmp2, Tmp3; if (Op.getOpcode() == ISD::SHL_PARTS) { - Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt); - Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt); + Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); + Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); } else { - Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt); - Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt); + Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); + Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); } - SDValue AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt, + SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, DAG.getConstant(VTBits, MVT::i8)); - SDValue Cond = DAG.getNode(X86ISD::CMP, VT, + SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT, AndNode, DAG.getConstant(0, MVT::i8)); SDValue Hi, Lo; @@ -4701,15 +4751,15 @@ SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; if (Op.getOpcode() == ISD::SHL_PARTS) { - Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4); - Lo = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4); + Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); + Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); } else { - Lo = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4); - Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4); + Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); + Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); } SDValue Ops[2] = { Lo, Hi }; - return DAG.getMergeValues(Ops, 2); + return DAG.getMergeValues(Ops, 2, dl); } SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { @@ -4724,11 +4774,12 @@ Subtarget->is64Bit()) return SDValue(); + DebugLoc dl = Op.getNode()->getDebugLoc(); unsigned Size = SrcVT.getSizeInBits()/8; MachineFunction &MF = DAG.getMachineFunction(); int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); - SDValue Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0), + SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot, PseudoSourceValue::getFixedStack(SSFI), 0); @@ -4743,7 +4794,7 @@ Ops.push_back(Chain); Ops.push_back(StackSlot); Ops.push_back(DAG.getValueType(SrcVT)); - SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, + SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl, Tys, &Ops[0], Ops.size()); if (useSSE) { @@ -4763,8 +4814,8 @@ Ops.push_back(StackSlot); Ops.push_back(DAG.getValueType(Op.getValueType())); Ops.push_back(InFlag); - Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); - Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, + Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size()); + Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot, PseudoSourceValue::getFixedStack(SSFI), 0); } @@ -4807,6 +4858,8 @@ } */ + DebugLoc dl = Op.getNode()->getDebugLoc(); + // Build some magic constants. std::vector CV0; CV0.push_back(ConstantInt::get(APInt(32, 0x45300000))); @@ -4827,82 +4880,83 @@ MaskVec.push_back(DAG.getConstant(4, MVT::i32)); MaskVec.push_back(DAG.getConstant(1, MVT::i32)); MaskVec.push_back(DAG.getConstant(5, MVT::i32)); - SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, &MaskVec[0], - MaskVec.size()); + SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + &MaskVec[0], MaskVec.size()); SmallVector MaskVec2; MaskVec2.push_back(DAG.getConstant(1, MVT::i32)); MaskVec2.push_back(DAG.getConstant(0, MVT::i32)); - SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec2[0], - MaskVec2.size()); + SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, + &MaskVec2[0], MaskVec2.size()); - SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32, - DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, + SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, + DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op.getOperand(0), DAG.getIntPtrConstant(1))); - SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32, - DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, + SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, + DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op.getOperand(0), DAG.getIntPtrConstant(0))); - SDValue Unpck1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, + SDValue Unpck1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v4i32, XR1, XR2, UnpcklMask); - SDValue CLod0 = DAG.getLoad(MVT::v4i32, DAG.getEntryNode(), CPIdx0, + SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, PseudoSourceValue::getConstantPool(), 0, false, 16); - SDValue Unpck2 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, + SDValue Unpck2 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v4i32, Unpck1, CLod0, UnpcklMask); - SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Unpck2); - SDValue CLod1 = DAG.getLoad(MVT::v2f64, CLod0.getValue(1), CPIdx1, + SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2); + SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, PseudoSourceValue::getConstantPool(), 0, false, 16); - SDValue Sub = DAG.getNode(ISD::FSUB, MVT::v2f64, XR2F, CLod1); + SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); // Add the halves; easiest way is to swap them into another reg first. - SDValue Shuf = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2f64, + SDValue Shuf = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2f64, Sub, Sub, ShufMask); - SDValue Add = DAG.getNode(ISD::FADD, MVT::v2f64, Shuf, Sub); - return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64, Add, + SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, DAG.getIntPtrConstant(0)); } // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); // FP constant to bias correct the final result. SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), MVT::f64); // Load the 32-bit value into an XMM register. - SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32, - DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, + SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, + DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op.getOperand(0), DAG.getIntPtrConstant(0))); - Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64, - DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Load), + Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load), DAG.getIntPtrConstant(0)); // Or the load with the bias. - SDValue Or = DAG.getNode(ISD::OR, MVT::v2i64, - DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, - DAG.getNode(ISD::SCALAR_TO_VECTOR, + SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, + DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)), - DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, - DAG.getNode(ISD::SCALAR_TO_VECTOR, + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, + DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias))); - Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64, - DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Or), + Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or), DAG.getIntPtrConstant(0)); // Subtract the bias. - SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Or, Bias); + SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); // Handle final rounding. MVT DestVT = Op.getValueType(); if (DestVT.bitsLT(MVT::f64)) { - return DAG.getNode(ISD::FP_ROUND, DestVT, Sub, + return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, DAG.getIntPtrConstant(0)); } else if (DestVT.bitsGT(MVT::f64)) { - return DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); + return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); } // Handle final rounding. @@ -4911,12 +4965,13 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) { SDValue N0 = Op.getOperand(0); + DebugLoc dl = Op.getNode()->getDebugLoc(); // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform // the optimization here. if (DAG.SignBitIsZero(N0)) - return DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), N0); + return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); MVT SrcVT = N0.getValueType(); if (SrcVT == MVT::i64) { @@ -4935,6 +4990,7 @@ std::pair X86TargetLowering:: FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); assert(Op.getValueType().getSimpleVT() <= MVT::i64 && Op.getValueType().getSimpleVT() >= MVT::i16 && "Unknown FP_TO_SINT to lower!"); @@ -4966,13 +5022,13 @@ SDValue Value = Op.getOperand(0); if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); - Chain = DAG.getStore(Chain, Value, StackSlot, + Chain = DAG.getStore(Chain, dl, Value, StackSlot, PseudoSourceValue::getFixedStack(SSFI), 0); SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) }; - Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3); + Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3); Chain = Value.getValue(1); SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); @@ -4980,7 +5036,7 @@ // Build the FP_TO_INT*_IN_MEM SDValue Ops[] = { Chain, Value, StackSlot }; - SDValue FIST = DAG.getNode(Opc, MVT::Other, Ops, 3); + SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3); return std::make_pair(FIST, StackSlot); } @@ -4991,10 +5047,12 @@ if (FIST.getNode() == 0) return SDValue(); // Load the result. - return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0); + return DAG.getLoad(Op.getValueType(), Op.getNode()->getDebugLoc(), + FIST, StackSlot, NULL, 0); } SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); MVT VT = Op.getValueType(); MVT EltVT = VT; if (VT.isVector()) @@ -5013,13 +5071,14 @@ } Constant *C = ConstantVector::get(CV); SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); - SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, + SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, false, 16); - return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask); + return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); } SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); MVT VT = Op.getValueType(); MVT EltVT = VT; unsigned EltNum = 1; @@ -5041,33 +5100,35 @@ } Constant *C = ConstantVector::get(CV); SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); - SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, + SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, false, 16); if (VT.isVector()) { - return DAG.getNode(ISD::BIT_CONVERT, VT, - DAG.getNode(ISD::XOR, MVT::v2i64, - DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)), - DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask))); + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, + DAG.getNode(ISD::XOR, dl, MVT::v2i64, + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, + Op.getOperand(0)), + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask))); } else { - return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask); + return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); } } SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { SDValue Op0 = Op.getOperand(0); SDValue Op1 = Op.getOperand(1); + DebugLoc dl = Op.getNode()->getDebugLoc(); MVT VT = Op.getValueType(); MVT SrcVT = Op1.getValueType(); // If second operand is smaller, extend it first. if (SrcVT.bitsLT(VT)) { - Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1); + Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); SrcVT = VT; } // And if it is bigger, shrink it first. if (SrcVT.bitsGT(VT)) { - Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1)); + Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); SrcVT = VT; } @@ -5087,19 +5148,19 @@ } Constant *C = ConstantVector::get(CV); SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); - SDValue Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, + SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, false, 16); - SDValue SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1); + SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); // Shift sign bit right or left if the two operands have different types. if (SrcVT.bitsGT(VT)) { // Op0 is MVT::f32, Op1 is MVT::f64. - SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit); - SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit, + SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); + SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, DAG.getConstant(32, MVT::i32)); - SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit); - SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit, + SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit); + SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, DAG.getIntPtrConstant(0)); } @@ -5116,19 +5177,20 @@ } C = ConstantVector::get(CV); CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); - SDValue Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, + SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, false, 16); - SDValue Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2); + SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); // Or the value with the sign bit. - return DAG.getNode(X86ISD::FOR, VT, Val, SignBit); + return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); } SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); SDValue Op0 = Op.getOperand(0); SDValue Op1 = Op.getOperand(1); + DebugLoc dl = Op.getNode()->getDebugLoc(); ISD::CondCode CC = cast(Op.getOperand(2))->get(); // Lower (X & (1 << N)) == 0 to BT(X, N). @@ -5169,16 +5231,16 @@ // that doing a bittest on the i16 value is ok. We extend to i32 because // the encoding for the i16 version is larger than the i32 version. if (LHS.getValueType() == MVT::i8) - LHS = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, LHS); + LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); // If the operand types disagree, extend the shift amount to match. Since // BT ignores high bits (like shifts) we can use anyextend. if (LHS.getValueType() != RHS.getValueType()) - RHS = DAG.getNode(ISD::ANY_EXTEND, LHS.getValueType(), RHS); + RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); - SDValue BT = DAG.getNode(X86ISD::BT, MVT::i32, LHS, RHS); + SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; - return DAG.getNode(X86ISD::SETCC, MVT::i8, + return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, DAG.getConstant(Cond, MVT::i8), BT); } } @@ -5186,8 +5248,8 @@ bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); - SDValue Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1); - return DAG.getNode(X86ISD::SETCC, MVT::i8, + SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); + return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, DAG.getConstant(X86CC, MVT::i8), Cond); } @@ -5199,6 +5261,7 @@ MVT VT = Op.getValueType(); ISD::CondCode SetCCOpcode = cast(CC)->get(); bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); + DebugLoc dl = Op.getNode()->getDebugLoc(); if (isFP) { unsigned SSECC = 8; @@ -5235,20 +5298,20 @@ if (SSECC == 8) { if (SetCCOpcode == ISD::SETUEQ) { SDValue UNORD, EQ; - UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); - EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); - return DAG.getNode(ISD::OR, VT, UNORD, EQ); + UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); + EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); + return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); } else if (SetCCOpcode == ISD::SETONE) { SDValue ORD, NEQ; - ORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); - NEQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); - return DAG.getNode(ISD::AND, VT, ORD, NEQ); + ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); + NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); + return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); } assert(0 && "Illegal FP comparison"); } // Handle all other FP comparisons here. - return DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); + return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); } // We are handling one of the integer comparisons here. Since SSE only has @@ -5288,17 +5351,17 @@ SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), EltVT); std::vector SignBits(VT.getVectorNumElements(), SignBit); - SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0], + SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], SignBits.size()); - Op0 = DAG.getNode(ISD::XOR, VT, Op0, SignVec); - Op1 = DAG.getNode(ISD::XOR, VT, Op1, SignVec); + Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); + Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); } - SDValue Result = DAG.getNode(Opc, VT, Op0, Op1); + SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); // If the logical-not of the result is required, perform that now. if (Invert) - Result = DAG.getNOT(Op.getDebugLoc(), Result, VT); + Result = DAG.getNOT(dl, Result, VT); return Result; } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=63650&r1=63649&r2=63650&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Feb 3 13:33:06 2009 @@ -549,7 +549,7 @@ bool CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall); SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, SDValue Chain, bool IsTailCall, bool Is64Bit, - int FPDiff); + int FPDiff, DebugLoc dl); CCAssignFn *CCAssignFnForNode(unsigned CallingConv) const; NameDecorationStyle NameDecorationForFORMAL_ARGUMENTS(SDValue Op); From sabre at nondot.org Tue Feb 3 13:41:50 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Feb 2009 19:41:50 -0000 Subject: [llvm-commits] [llvm] r63651 - /llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Message-ID: <200902031941.n13JfoCD013084@zion.cs.uiuc.edu> Author: lattner Date: Tue Feb 3 13:41:50 2009 New Revision: 63651 URL: http://llvm.org/viewvc/llvm-project?rev=63651&view=rev Log: switch ConvertScalar_InsertValue to use an IRBuilder, no functionality change. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=63651&r1=63650&r2=63651&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Tue Feb 3 13:41:50 2009 @@ -33,6 +33,7 @@ #include "llvm/Transforms/Utils/PromoteMemToReg.h" #include "llvm/Support/Debug.h" #include "llvm/Support/GetElementPtrTypeIterator.h" +#include "llvm/Support/IRBuilder.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/Compiler.h" #include "llvm/ADT/SmallVector.h" @@ -131,7 +132,7 @@ Value *ConvertUsesOfLoadToScalar(LoadInst *LI, AllocaInst *NewAI, uint64_t Offset); Value *ConvertScalar_InsertValue(Value *StoredVal, Value *ExistingVal, - uint64_t Offset, Instruction *InsertPt); + uint64_t Offset, IRBuilder<> &Builder); static Instruction *isOnlyCopiedFromConstantGlobal(AllocationInst *AI); }; } @@ -1326,9 +1327,12 @@ if (StoreInst *SI = dyn_cast(User)) { assert(SI->getOperand(0) != Ptr && "Consistency error!"); - Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", SI); - Value *New = ConvertScalar_InsertValue(SI->getOperand(0), Old, Offset,SI); - new StoreInst(New, NewAI, SI); + + IRBuilder<> Builder(SI->getParent(), SI); + Value *Old = Builder.CreateLoad(NewAI, (NewAI->getName()+".in").c_str()); + Value *New = ConvertScalar_InsertValue(SI->getOperand(0), Old, Offset, + Builder); + Builder.CreateStore(New, NewAI); SI->eraseFromParent(); continue; } @@ -1364,10 +1368,12 @@ for (unsigned i = 1; i != NumBytes; ++i) APVal |= APVal << 8; - Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", MSI); + IRBuilder<> Builder(MSI->getParent(), MSI); + + Value *Old = Builder.CreateLoad(NewAI, (NewAI->getName()+".in").c_str()); Value *New = ConvertScalar_InsertValue(ConstantInt::get(APVal), Old, - Offset, MSI); - new StoreInst(New, NewAI, MSI); + Offset, Builder); + Builder.CreateStore(New, NewAI); MSI->eraseFromParent(); continue; } @@ -1477,7 +1483,7 @@ /// Offset is an offset from the original alloca, in bits that need to be /// shifted to the right. Value *SROA::ConvertScalar_InsertValue(Value *SV, Value *Old, - uint64_t Offset, Instruction *IP) { + uint64_t Offset, IRBuilder<> &Builder) { // Convert the stored type to the actual type, shift it left to insert // then 'or' into place. @@ -1487,17 +1493,17 @@ // If the result alloca is a vector type, this is either an element // access or a bitcast to another vector type. if (isa(SV->getType())) { - SV = new BitCastInst(SV, AllocaType, SV->getName(), IP); + SV = Builder.CreateBitCast(SV, AllocaType, "tmp"); } else { // Must be an element insertion. unsigned Elt = Offset/TD->getTypePaddedSizeInBits(VTy->getElementType()); if (SV->getType() != VTy->getElementType()) - SV = new BitCastInst(SV, VTy->getElementType(), "tmp", IP); + SV = Builder.CreateBitCast(SV, VTy->getElementType(), "tmp"); - SV = InsertElementInst::Create(Old, SV, - ConstantInt::get(Type::Int32Ty, Elt), - "tmp", IP); + SV = Builder.CreateInsertElement(Old, SV, + ConstantInt::get(Type::Int32Ty, Elt), + "tmp"); } return SV; } @@ -1506,9 +1512,10 @@ if (const StructType *ST = dyn_cast(SV->getType())) { const StructLayout &Layout = *TD->getStructLayout(ST); for (unsigned i = 0, e = ST->getNumElements(); i != e; ++i) { - Value *Elt = ExtractValueInst::Create(SV, i, "tmp", IP); + Value *Elt = Builder.CreateExtractValue(SV, i, "tmp"); Old = ConvertScalar_InsertValue(Elt, Old, - Offset+Layout.getElementOffset(i), IP); + Offset+Layout.getElementOffset(i), + Builder); } return Old; } @@ -1516,8 +1523,8 @@ if (const ArrayType *AT = dyn_cast(SV->getType())) { uint64_t EltSize = TD->getTypePaddedSizeInBits(AT->getElementType()); for (unsigned i = 0, e = AT->getNumElements(); i != e; ++i) { - Value *Elt = ExtractValueInst::Create(SV, i, "tmp", IP); - Old = ConvertScalar_InsertValue(Elt, Old, Offset+i*EltSize, IP); + Value *Elt = Builder.CreateExtractValue(SV, i, "tmp"); + Old = ConvertScalar_InsertValue(Elt, Old, Offset+i*EltSize, Builder); } return Old; } @@ -1529,19 +1536,19 @@ unsigned SrcStoreWidth = TD->getTypeStoreSizeInBits(SV->getType()); unsigned DestStoreWidth = TD->getTypeStoreSizeInBits(AllocaType); if (SV->getType()->isFloatingPoint() || isa(SV->getType())) - SV = new BitCastInst(SV, IntegerType::get(SrcWidth), SV->getName(), IP); + SV = Builder.CreateBitCast(SV, IntegerType::get(SrcWidth), "tmp"); else if (isa(SV->getType())) - SV = new PtrToIntInst(SV, TD->getIntPtrType(), SV->getName(), IP); + SV = Builder.CreatePtrToInt(SV, TD->getIntPtrType(), "tmp"); // Zero extend or truncate the value if needed. if (SV->getType() != AllocaType) { if (SV->getType()->getPrimitiveSizeInBits() < AllocaType->getPrimitiveSizeInBits()) - SV = new ZExtInst(SV, AllocaType, SV->getName(), IP); + SV = Builder.CreateZExt(SV, AllocaType, "tmp"); else { // Truncation may be needed if storing more than the alloca can hold // (undefined behavior). - SV = new TruncInst(SV, AllocaType, SV->getName(), IP); + SV = Builder.CreateTrunc(SV, AllocaType, "tmp"); SrcWidth = DestWidth; SrcStoreWidth = DestStoreWidth; } @@ -1564,14 +1571,10 @@ // only some bits in the structure are set. APInt Mask(APInt::getLowBitsSet(DestWidth, SrcWidth)); if (ShAmt > 0 && (unsigned)ShAmt < DestWidth) { - SV = BinaryOperator::CreateShl(SV, - ConstantInt::get(SV->getType(), ShAmt), - SV->getName(), IP); + SV = Builder.CreateShl(SV, ConstantInt::get(SV->getType(), ShAmt), "tmp"); Mask <<= ShAmt; } else if (ShAmt < 0 && (unsigned)-ShAmt < DestWidth) { - SV = BinaryOperator::CreateLShr(SV, - ConstantInt::get(SV->getType(), -ShAmt), - SV->getName(), IP); + SV = Builder.CreateLShr(SV, ConstantInt::get(SV->getType(), -ShAmt), "tmp"); Mask = Mask.lshr(-ShAmt); } @@ -1579,9 +1582,8 @@ // in the new bits. if (SrcWidth != DestWidth) { assert(DestWidth > SrcWidth); - Old = BinaryOperator::CreateAnd(Old, ConstantInt::get(~Mask), - Old->getName()+".mask", IP); - SV = BinaryOperator::CreateOr(Old, SV, SV->getName()+".ins", IP); + Old = Builder.CreateAnd(Old, ConstantInt::get(~Mask), "mask"); + SV = Builder.CreateOr(Old, SV, "ins"); } return SV; } From sabre at nondot.org Tue Feb 3 13:45:44 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Feb 2009 19:45:44 -0000 Subject: [llvm-commits] [llvm] r63652 - /llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Message-ID: <200902031945.n13JjiPL013318@zion.cs.uiuc.edu> Author: lattner Date: Tue Feb 3 13:45:44 2009 New Revision: 63652 URL: http://llvm.org/viewvc/llvm-project?rev=63652&view=rev Log: convert ConvertUsesOfLoadToScalar to use IRBuilder, no functionality change. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=63652&r1=63651&r2=63652&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Tue Feb 3 13:45:44 2009 @@ -130,7 +130,7 @@ bool &SawVec, uint64_t Offset, unsigned AllocaSize); void ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, uint64_t Offset); Value *ConvertUsesOfLoadToScalar(LoadInst *LI, AllocaInst *NewAI, - uint64_t Offset); + uint64_t Offset, IRBuilder<> &Builder); Value *ConvertScalar_InsertValue(Value *StoredVal, Value *ExistingVal, uint64_t Offset, IRBuilder<> &Builder); static Instruction *isOnlyCopiedFromConstantGlobal(AllocationInst *AI); @@ -1319,24 +1319,6 @@ while (!Ptr->use_empty()) { Instruction *User = cast(Ptr->use_back()); - if (LoadInst *LI = dyn_cast(User)) { - LI->replaceAllUsesWith(ConvertUsesOfLoadToScalar(LI, NewAI, Offset)); - LI->eraseFromParent(); - continue; - } - - if (StoreInst *SI = dyn_cast(User)) { - assert(SI->getOperand(0) != Ptr && "Consistency error!"); - - IRBuilder<> Builder(SI->getParent(), SI); - Value *Old = Builder.CreateLoad(NewAI, (NewAI->getName()+".in").c_str()); - Value *New = ConvertScalar_InsertValue(SI->getOperand(0), Old, Offset, - Builder); - Builder.CreateStore(New, NewAI); - SI->eraseFromParent(); - continue; - } - if (BitCastInst *CI = dyn_cast(User)) { ConvertUsesToScalar(CI, NewAI, Offset); CI->eraseFromParent(); @@ -1353,6 +1335,25 @@ continue; } + IRBuilder<> Builder(User->getParent(), User); + + if (LoadInst *LI = dyn_cast(User)) { + Value *LoadVal = ConvertUsesOfLoadToScalar(LI, NewAI, Offset, Builder); + LI->replaceAllUsesWith(LoadVal); + LI->eraseFromParent(); + continue; + } + + if (StoreInst *SI = dyn_cast(User)) { + assert(SI->getOperand(0) != Ptr && "Consistency error!"); + Value *Old = Builder.CreateLoad(NewAI, (NewAI->getName()+".in").c_str()); + Value *New = ConvertScalar_InsertValue(SI->getOperand(0), Old, Offset, + Builder); + Builder.CreateStore(New, NewAI); + SI->eraseFromParent(); + continue; + } + // If this is a constant sized memset of a constant value (e.g. 0) we can // transform it into a store of the expanded constant value. if (MemSetInst *MSI = dyn_cast(User)) { @@ -1368,8 +1369,6 @@ for (unsigned i = 1; i != NumBytes; ++i) APVal |= APVal << 8; - IRBuilder<> Builder(MSI->getParent(), MSI); - Value *Old = Builder.CreateLoad(NewAI, (NewAI->getName()+".in").c_str()); Value *New = ConvertScalar_InsertValue(ConstantInt::get(APVal), Old, Offset, Builder); @@ -1393,9 +1392,9 @@ /// Offset is an offset from the original alloca, in bits that need to be /// shifted to the right. By the end of this, there should be no uses of Ptr. Value *SROA::ConvertUsesOfLoadToScalar(LoadInst *LI, AllocaInst *NewAI, - uint64_t Offset) { + uint64_t Offset, IRBuilder<> &Builder) { // The load is a bit extract from NewAI shifted right by Offset bits. - Value *NV = new LoadInst(NewAI, LI->getName(), LI); + Value *NV = Builder.CreateLoad(NewAI, "tmp"); // If the load is of the whole new alloca, no conversion is needed. if (NV->getType() == LI->getType() && Offset == 0) @@ -1405,7 +1404,7 @@ // access or a bitcast to another vector type of the same size. if (const VectorType *VTy = dyn_cast(NV->getType())) { if (isa(LI->getType())) - return new BitCastInst(NV, LI->getType(), LI->getName(), LI); + return Builder.CreateBitCast(NV, LI->getType(), "tmp"); // Otherwise it must be an element access. unsigned Elt = 0; @@ -1415,10 +1414,11 @@ assert(EltSize*Elt == Offset && "Invalid modulus in validity checking"); } // Return the element extracted out of it. - Value *V = new ExtractElementInst(NV, ConstantInt::get(Type::Int32Ty, Elt), - "tmp", LI); + Value *V = Builder.CreateExtractElement(NV, + ConstantInt::get(Type::Int32Ty,Elt), + "tmp"); if (V->getType() != LI->getType()) - V = new BitCastInst(V, LI->getType(), "tmp", LI); + V = Builder.CreateBitCast(V, LI->getType(), "tmp"); return V; } @@ -1442,20 +1442,16 @@ // We do this to support (f.e.) loads off the end of a structure where // only some bits are used. if (ShAmt > 0 && (unsigned)ShAmt < NTy->getBitWidth()) - NV = BinaryOperator::CreateLShr(NV, - ConstantInt::get(NV->getType(), ShAmt), - LI->getName(), LI); + NV = Builder.CreateLShr(NV, ConstantInt::get(NV->getType(), ShAmt), "tmp"); else if (ShAmt < 0 && (unsigned)-ShAmt < NTy->getBitWidth()) - NV = BinaryOperator::CreateShl(NV, - ConstantInt::get(NV->getType(), -ShAmt), - LI->getName(), LI); + NV = Builder.CreateShl(NV, ConstantInt::get(NV->getType(), -ShAmt), "tmp"); // Finally, unconditionally truncate the integer to the right width. unsigned LIBitWidth = TD->getTypeSizeInBits(LI->getType()); if (LIBitWidth < NTy->getBitWidth()) - NV = new TruncInst(NV, IntegerType::get(LIBitWidth), LI->getName(), LI); + NV = Builder.CreateTrunc(NV, IntegerType::get(LIBitWidth), "tmp"); else if (LIBitWidth > NTy->getBitWidth()) - NV = new ZExtInst(NV, IntegerType::get(LIBitWidth), LI->getName(), LI); + NV = Builder.CreateZExt(NV, IntegerType::get(LIBitWidth), "tmp"); // If the result is an integer, this is a trunc or bitcast. if (isa(LI->getType())) { @@ -1463,10 +1459,10 @@ } else if (LI->getType()->isFloatingPoint() || isa(LI->getType())) { // Just do a bitcast, we know the sizes match up. - NV = new BitCastInst(NV, LI->getType(), LI->getName(), LI); + NV = Builder.CreateBitCast(NV, LI->getType(), "tmp"); } else { // Otherwise must be a pointer. - NV = new IntToPtrInst(NV, LI->getType(), LI->getName(), LI); + NV = Builder.CreateIntToPtr(NV, LI->getType(), "tmp"); } assert(NV->getType() == LI->getType() && "Didn't convert right?"); return NV; From dpatel at apple.com Tue Feb 3 13:46:28 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 03 Feb 2009 19:46:28 -0000 Subject: [llvm-commits] [llvm] r63653 - in /llvm/trunk: include/llvm/CodeGen/MachineModuleInfo.h lib/CodeGen/MachineModuleInfo.cpp Message-ID: <200902031946.n13JkSDW013362@zion.cs.uiuc.edu> Author: dpatel Date: Tue Feb 3 13:46:28 2009 New Revision: 63653 URL: http://llvm.org/viewvc/llvm-project?rev=63653&view=rev Log: Remove dead code. Modified: llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h?rev=63653&r1=63652&r2=63653&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h Tue Feb 3 13:46:28 2009 @@ -55,25 +55,6 @@ class StructType; //===----------------------------------------------------------------------===// -/// SourceLineInfo - This class is used to record source line correspondence. -/// -class SourceLineInfo { - unsigned Line; // Source line number. - unsigned Column; // Source column. - unsigned SourceID; // Source ID number. - unsigned LabelID; // Label in code ID number. -public: - SourceLineInfo(unsigned L, unsigned C, unsigned S, unsigned I) - : Line(L), Column(C), SourceID(S), LabelID(I) {} - - // Accessors - unsigned getLine() const { return Line; } - unsigned getColumn() const { return Column; } - unsigned getSourceID() const { return SourceID; } - unsigned getLabelID() const { return LabelID; } -}; - -//===----------------------------------------------------------------------===// /// LandingPadInfo - This structure is used to retain landing pad info for /// the current function. /// @@ -99,9 +80,6 @@ /// class MachineModuleInfo : public ImmutablePass { private: - // Lines - List of of source line correspondence. - std::vector Lines; - // LabelIDList - One entry per assigned label. Normally the entry is equal to // the list index(+1). If the entry is zero then the label has been deleted. // Any other value indicates the label has been deleted by is mapped to @@ -217,12 +195,6 @@ return LabelID ? LabelIDList[LabelID - 1] : 0; } - /// getSourceLines - Return a vector of source lines. - /// - const std::vector &getSourceLines() const { - return Lines; - } - /// getFrameMoves - Returns a reference to a list of moves done in the current /// function's prologue. Used to construct frame maps for debug and exception /// handling comsumers. Modified: llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp?rev=63653&r1=63652&r2=63653&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp Tue Feb 3 13:46:28 2009 @@ -36,7 +36,6 @@ MachineModuleInfo::MachineModuleInfo() : ImmutablePass(&ID) -, Lines() , LabelIDList() , FrameMoves() , LandingPads() From dalej at apple.com Tue Feb 3 14:21:25 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 03 Feb 2009 20:21:25 -0000 Subject: [llvm-commits] [llvm] r63656 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200902032021.n13KLPEQ014546@zion.cs.uiuc.edu> Author: johannes Date: Tue Feb 3 14:21:25 2009 New Revision: 63656 URL: http://llvm.org/viewvc/llvm-project?rev=63656&view=rev Log: DebugLoc propagation. done with file. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=63656&r1=63655&r2=63656&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Feb 3 14:21:25 2009 @@ -5374,6 +5374,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { bool addTest = true; SDValue Cond = Op.getOperand(0); + DebugLoc dl = Op.getNode()->getDebugLoc(); SDValue CC; if (Cond.getOpcode() == ISD::SETCC) @@ -5401,7 +5402,8 @@ if (addTest) { CC = DAG.getConstant(X86::COND_NE, MVT::i8); - Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8)); + Cond= DAG.getNode(X86ISD::CMP, dl, MVT::i32, Cond, + DAG.getConstant(0, MVT::i8)); } const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(), @@ -5413,7 +5415,7 @@ Ops.push_back(Op.getOperand(1)); Ops.push_back(CC); Ops.push_back(Cond); - return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); + return DAG.getNode(X86ISD::CMOV, dl, VTs, 2, &Ops[0], Ops.size()); } // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or @@ -5447,6 +5449,7 @@ SDValue Chain = Op.getOperand(0); SDValue Cond = Op.getOperand(1); SDValue Dest = Op.getOperand(2); + DebugLoc dl = Op.getNode()->getDebugLoc(); SDValue CC; if (Cond.getOpcode() == ISD::SETCC) @@ -5495,7 +5498,7 @@ if (Cmp == Cond.getOperand(1).getOperand(1) && isX86LogicalCmp(Opc)) { CC = Cond.getOperand(0).getOperand(0); - Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(), + Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), Chain, Dest, CC, Cmp); CC = Cond.getOperand(1).getOperand(0); Cond = Cmp; @@ -5525,7 +5528,7 @@ assert(NewBR == User); Dest = FalseBB; - Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(), + Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), Chain, Dest, CC, Cmp); X86::CondCode CCode = (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); @@ -5551,9 +5554,10 @@ if (addTest) { CC = DAG.getConstant(X86::COND_NE, MVT::i8); - Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8)); + Cond= DAG.getNode(X86ISD::CMP, dl, MVT::i32, Cond, + DAG.getConstant(0, MVT::i8)); } - return DAG.getNode(X86ISD::BRCOND, Op.getValueType(), + return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), Chain, Dest, CC, Cond); } @@ -5568,6 +5572,7 @@ SelectionDAG &DAG) { assert(Subtarget->isTargetCygMing() && "This should be used only on Cygwin/Mingw targets"); + DebugLoc dl = Op.getNode()->getDebugLoc(); // Get the inputs. SDValue Chain = Op.getOperand(0); @@ -5590,7 +5595,7 @@ DAG.getRegister(X86::EAX, IntPtr), DAG.getRegister(X86StackPtr, SPTy), Flag }; - Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 5); + Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5); Flag = Chain.getValue(1); Chain = DAG.getCALLSEQ_END(Chain, @@ -5601,7 +5606,7 @@ Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1); SDValue Ops1[2] = { Chain.getValue(0), Chain }; - return DAG.getMergeValues(Ops1, 2); + return DAG.getMergeValues(Ops1, 2, dl); } SDValue @@ -5820,12 +5825,13 @@ SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { const Value *SV = cast(Op.getOperand(2))->getValue(); + DebugLoc dl = Op.getNode()->getDebugLoc(); if (!Subtarget->is64Bit()) { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); - return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0); + return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); } // __va_list_tag: @@ -5836,30 +5842,34 @@ SmallVector MemOps; SDValue FIN = Op.getOperand(1); // Store gp_offset - SDValue Store = DAG.getStore(Op.getOperand(0), + SDValue Store = DAG.getStore(Op.getOperand(0), dl, DAG.getConstant(VarArgsGPOffset, MVT::i32), FIN, SV, 0); MemOps.push_back(Store); // Store fp_offset - FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4)); - Store = DAG.getStore(Op.getOperand(0), + FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), + FIN, DAG.getIntPtrConstant(4)); + Store = DAG.getStore(Op.getOperand(0), dl, DAG.getConstant(VarArgsFPOffset, MVT::i32), FIN, SV, 0); MemOps.push_back(Store); // Store ptr to overflow_arg_area - FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4)); + FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), + FIN, DAG.getIntPtrConstant(4)); SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); - Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0); + Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0); MemOps.push_back(Store); // Store ptr to reg_save_area. - FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8)); + FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), + FIN, DAG.getIntPtrConstant(8)); SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); - Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0); + Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0); MemOps.push_back(Store); - return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size()); + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + &MemOps[0], MemOps.size()); } SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) { @@ -5890,6 +5900,7 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); unsigned IntNo = cast(Op.getOperand(0))->getZExtValue(); switch (IntNo) { default: return SDValue(); // Don't custom lower most intrinsics. @@ -5987,10 +5998,10 @@ SDValue LHS = Op.getOperand(1); SDValue RHS = Op.getOperand(2); unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); - SDValue Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS); - SDValue SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8, + SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); + SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, DAG.getConstant(X86CC, MVT::i8), Cond); - return DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, SetCC); + return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); } // Fix vector shift instructions where the last operand is a non-immediate @@ -6075,9 +6086,9 @@ } } MVT VT = Op.getValueType(); - ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT, - DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt)); - return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, + ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, + DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt)); + return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(NewIntNo, MVT::i32), Op.getOperand(1), ShAmt); } @@ -6086,20 +6097,23 @@ SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { unsigned Depth = cast(Op.getOperand(0))->getZExtValue(); + DebugLoc dl = Op.getNode()->getDebugLoc(); if (Depth > 0) { SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); SDValue Offset = DAG.getConstant(TD->getPointerSize(), Subtarget->is64Bit() ? MVT::i64 : MVT::i32); - return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), - DAG.getNode(ISD::ADD, getPointerTy(), FrameAddr, Offset), + return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), + DAG.getNode(ISD::ADD, dl, getPointerTy(), + FrameAddr, Offset), NULL, 0); } // Just load the return address. SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); - return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); + return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), + RetAddrFI, NULL, 0); } SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { @@ -6125,19 +6139,20 @@ SDValue Chain = Op.getOperand(0); SDValue Offset = Op.getOperand(1); SDValue Handler = Op.getOperand(2); + DebugLoc dl = Op.getNode()->getDebugLoc(); SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP, getPointerTy()); unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); - SDValue StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame, + SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame, DAG.getIntPtrConstant(-TD->getPointerSize())); - StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset); - Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0); + StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); + Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0); Chain = DAG.getCopyToReg(Chain, StoreAddrReg, StoreAddr); MF.getRegInfo().addLiveOut(StoreAddrReg); - return DAG.getNode(X86ISD::EH_RETURN, + return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); } @@ -6148,6 +6163,7 @@ SDValue Trmp = Op.getOperand(1); // trampoline SDValue FPtr = Op.getOperand(2); // nested function SDValue Nest = Op.getOperand(3); // 'nest' parameter value + DebugLoc dl = Op.getNode()->getDebugLoc(); const Value *TrmpAddr = cast(Op.getOperand(4))->getValue(); @@ -6170,36 +6186,41 @@ // Load the pointer to the nested function into R11. unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 SDValue Addr = Trmp; - OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, - TrmpAddr, 0); + OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), + Addr, TrmpAddr, 0); - Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64)); - OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2); + Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, + DAG.getConstant(2, MVT::i64)); + OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2); // Load the 'nest' parameter value into R10. // R10 is specified in X86CallingConv.td OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 - Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64)); - OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, - TrmpAddr, 10); - - Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64)); - OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2); + Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, + DAG.getConstant(10, MVT::i64)); + OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), + Addr, TrmpAddr, 10); + + Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, + DAG.getConstant(12, MVT::i64)); + OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2); // Jump to the nested function. OpCode = (JMP64r << 8) | REX_WB; // jmpq *... - Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64)); - OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, - TrmpAddr, 20); + Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, + DAG.getConstant(20, MVT::i64)); + OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), + Addr, TrmpAddr, 20); unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 - Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64)); - OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr, + Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, + DAG.getConstant(22, MVT::i64)); + OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, TrmpAddr, 22); SDValue Ops[] = - { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) }; - return DAG.getMergeValues(Ops, 2); + { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) }; + return DAG.getMergeValues(Ops, 2, dl); } else { const Function *Func = cast(cast(Op.getOperand(5))->getValue()); @@ -6247,28 +6268,33 @@ SDValue OutChains[4]; SDValue Addr, Disp; - Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32)); - Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr); + Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, + DAG.getConstant(10, MVT::i32)); + Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri); const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); - OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8), + OutChains[0] = DAG.getStore(Root, dl, + DAG.getConstant(MOV32ri|N86Reg, MVT::i8), Trmp, TrmpAddr, 0); - Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32)); - OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1); + Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, + DAG.getConstant(1, MVT::i32)); + OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1); const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP); - Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32)); - OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr, + Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, + DAG.getConstant(5, MVT::i32)); + OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, TrmpAddr, 5, false, 1); - Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32)); - OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1); + Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, + DAG.getConstant(6, MVT::i32)); + OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1); SDValue Ops[] = - { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) }; - return DAG.getMergeValues(Ops, 2); + { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) }; + return DAG.getMergeValues(Ops, 2, dl); } } @@ -6297,33 +6323,34 @@ const TargetFrameInfo &TFI = *TM.getFrameInfo(); unsigned StackAlignment = TFI.getStackAlignment(); MVT VT = Op.getValueType(); + DebugLoc dl = Op.getNode()->getDebugLoc(); // Save FP Control Word to stack slot int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment); SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); - SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other, + SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other, DAG.getEntryNode(), StackSlot); // Load FP Control Word from stack slot - SDValue CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0); + SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0); // Transform as necessary SDValue CWD1 = - DAG.getNode(ISD::SRL, MVT::i16, - DAG.getNode(ISD::AND, MVT::i16, + DAG.getNode(ISD::SRL, dl, MVT::i16, + DAG.getNode(ISD::AND, dl, MVT::i16, CWD, DAG.getConstant(0x800, MVT::i16)), DAG.getConstant(11, MVT::i8)); SDValue CWD2 = - DAG.getNode(ISD::SRL, MVT::i16, - DAG.getNode(ISD::AND, MVT::i16, + DAG.getNode(ISD::SRL, dl, MVT::i16, + DAG.getNode(ISD::AND, dl, MVT::i16, CWD, DAG.getConstant(0x400, MVT::i16)), DAG.getConstant(9, MVT::i8)); SDValue RetVal = - DAG.getNode(ISD::AND, MVT::i16, - DAG.getNode(ISD::ADD, MVT::i16, - DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2), + DAG.getNode(ISD::AND, dl, MVT::i16, + DAG.getNode(ISD::ADD, dl, MVT::i16, + DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2), DAG.getConstant(1, MVT::i16)), DAG.getConstant(3, MVT::i16)); @@ -6336,17 +6363,18 @@ MVT VT = Op.getValueType(); MVT OpVT = VT; unsigned NumBits = VT.getSizeInBits(); + DebugLoc dl = Op.getNode()->getDebugLoc(); Op = Op.getOperand(0); if (VT == MVT::i8) { // Zero extend to i32 since there is not an i8 bsr. OpVT = MVT::i32; - Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op); + Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); } // Issue a bsr (scan bits in reverse) which also sets EFLAGS. SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); - Op = DAG.getNode(X86ISD::BSR, VTs, Op); + Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); // If src is zero (i.e. bsr sets ZF), returns NumBits. SmallVector Ops; @@ -6354,13 +6382,13 @@ Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT)); Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); Ops.push_back(Op.getValue(1)); - Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4); + Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4); // Finally xor with NumBits-1. - Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); + Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); if (VT == MVT::i8) - Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op); + Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); return Op; } @@ -6368,16 +6396,17 @@ MVT VT = Op.getValueType(); MVT OpVT = VT; unsigned NumBits = VT.getSizeInBits(); + DebugLoc dl = Op.getNode()->getDebugLoc(); Op = Op.getOperand(0); if (VT == MVT::i8) { OpVT = MVT::i32; - Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op); + Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); } // Issue a bsf (scan bits forward) which also sets EFLAGS. SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); - Op = DAG.getNode(X86ISD::BSF, VTs, Op); + Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); // If src is zero (i.e. bsf sets ZF), returns NumBits. SmallVector Ops; @@ -6385,16 +6414,17 @@ Ops.push_back(DAG.getConstant(NumBits, OpVT)); Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); Ops.push_back(Op.getValue(1)); - Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4); + Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4); if (VT == MVT::i8) - Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op); + Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); return Op; } SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); + DebugLoc dl = Op.getNode()->getDebugLoc(); // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); @@ -6409,29 +6439,29 @@ SDValue A = Op.getOperand(0); SDValue B = Op.getOperand(1); - SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, + SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), A, DAG.getConstant(32, MVT::i32)); - SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, + SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), B, DAG.getConstant(32, MVT::i32)); - SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, + SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), A, B); - SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, + SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), A, Bhi); - SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, + SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), Ahi, B); - AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, + AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), AloBhi, DAG.getConstant(32, MVT::i32)); - AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, + AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), AhiBlo, DAG.getConstant(32, MVT::i32)); - SDValue Res = DAG.getNode(ISD::ADD, VT, AloBlo, AloBhi); - Res = DAG.getNode(ISD::ADD, VT, Res, AhiBlo); + SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); + Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); return Res; } @@ -6446,6 +6476,7 @@ SDValue RHS = N->getOperand(1); unsigned BaseOp = 0; unsigned Cond = 0; + DebugLoc dl = Op.getNode()->getDebugLoc(); switch (Op.getOpcode()) { default: assert(0 && "Unknown ovf instruction!"); @@ -6477,10 +6508,10 @@ // Also sets EFLAGS. SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); - SDValue Sum = DAG.getNode(BaseOp, VTs, LHS, RHS); + SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS); SDValue SetCC = - DAG.getNode(X86ISD::SETCC, N->getValueType(1), + DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1), DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1)); DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); @@ -6489,6 +6520,7 @@ SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { MVT T = Op.getValueType(); + DebugLoc dl = Op.getNode()->getDebugLoc(); unsigned Reg = 0; unsigned size = 0; switch(T.getSimpleVT()) { @@ -6510,7 +6542,7 @@ DAG.getTargetConstant(size, MVT::i8), cpIn.getValue(1) }; SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); - SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5); + SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5); SDValue cpOut = DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1)); return cpOut; @@ -6521,25 +6553,27 @@ assert(Subtarget->is64Bit() && "Result not type legalized?"); SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); SDValue TheChain = Op.getOperand(0); - SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1); + DebugLoc dl = Op.getNode()->getDebugLoc(); + SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1)); SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX, MVT::i64, rax.getValue(2)); - SDValue Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx, + SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, DAG.getConstant(32, MVT::i8)); SDValue Ops[] = { - DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), + DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), rdx.getValue(1) }; - return DAG.getMergeValues(Ops, 2); + return DAG.getMergeValues(Ops, 2, dl); } SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { SDNode *Node = Op.getNode(); + DebugLoc dl = Node->getDebugLoc(); MVT T = Node->getValueType(0); - SDValue negOp = DAG.getNode(ISD::SUB, T, + SDValue negOp = DAG.getNode(ISD::SUB, dl, T, DAG.getConstant(0, T), Node->getOperand(2)); - return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, + return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, cast(Node)->getMemoryVT(), Node->getOperand(0), Node->getOperand(1), negOp, @@ -6609,22 +6643,23 @@ ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl&Results, SelectionDAG &DAG, unsigned NewOp) { MVT T = Node->getValueType(0); + DebugLoc dl = Node->getDebugLoc(); assert (T == MVT::i64 && "Only know how to expand i64 atomics"); SDValue Chain = Node->getOperand(0); SDValue In1 = Node->getOperand(1); - SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, + SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Node->getOperand(2), DAG.getIntPtrConstant(0)); - SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, + SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Node->getOperand(2), DAG.getIntPtrConstant(1)); // This is a generalized SDNode, not an AtomicSDNode, so it doesn't // have a MemOperand. Pass the info through as a normal operand. SDValue LSI = DAG.getMemOperand(cast(Node)->getMemOperand()); SDValue Ops[] = { Chain, In1, In2L, In2H, LSI }; SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); - SDValue Result = DAG.getNode(NewOp, Tys, Ops, 5); + SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5); SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; - Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2)); + Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); Results.push_back(Result.getValue(2)); } @@ -6633,6 +6668,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl&Results, SelectionDAG &DAG) { + DebugLoc dl = N->getDebugLoc(); switch (N->getOpcode()) { default: assert(false && "Do not know how to custom type legalize this operation!"); @@ -6643,20 +6679,20 @@ if (FIST.getNode() != 0) { MVT VT = N->getValueType(0); // Return a load from the stack slot. - Results.push_back(DAG.getLoad(VT, FIST, StackSlot, NULL, 0)); + Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0)); } return; } case ISD::READCYCLECOUNTER: { SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); SDValue TheChain = N->getOperand(0); - SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1); + SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)); SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX, MVT::i32, eax.getValue(2)); // Use a buildpair to merge the two 32-bit values into a 64-bit one. SDValue Ops[] = { eax, edx }; - Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2)); + Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); Results.push_back(edx.getValue(1)); return; } @@ -6664,17 +6700,17 @@ MVT T = N->getValueType(0); assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); SDValue cpInL, cpInH; - cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(2), + cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), DAG.getConstant(0, MVT::i32)); - cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(2), + cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), DAG.getConstant(1, MVT::i32)); cpInL = DAG.getCopyToReg(N->getOperand(0), X86::EAX, cpInL, SDValue()); cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX, cpInH, cpInL.getValue(1)); SDValue swapInL, swapInH; - swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(3), + swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), DAG.getConstant(0, MVT::i32)); - swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(3), + swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), DAG.getConstant(1, MVT::i32)); swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX, swapInL, cpInH.getValue(1)); @@ -6684,13 +6720,13 @@ N->getOperand(1), swapInH.getValue(1) }; SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); - SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3); + SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3); SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32, Result.getValue(1)); SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32, cpOutL.getValue(2)); SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; - Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2)); + Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); Results.push_back(cpOutH.getValue(1)); return; } @@ -6953,6 +6989,7 @@ // Insert instructions into newMBB based on incoming instruction assert(bInstr->getNumOperands() < 8 && "unexpected number of operands"); + DebugLoc dl = bInstr->getDebugLoc(); MachineOperand& destOper = bInstr->getOperand(0); MachineOperand* argOpers[6]; int numArgs = bInstr->getNumOperands() - 1; @@ -6964,13 +7001,13 @@ int valArgIndx = 4; unsigned t1 = F->getRegInfo().createVirtualRegister(RC); - MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(LoadOpc), t1); + MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); for (int i=0; i <= lastAddrIndx; ++i) (*MIB).addOperand(*argOpers[i]); unsigned tt = F->getRegInfo().createVirtualRegister(RC); if (invSrc) { - MIB = BuildMI(newMBB, TII->get(notOpc), tt).addReg(t1); + MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); } else tt = t1; @@ -6980,27 +7017,27 @@ argOpers[valArgIndx]->isImm()) && "invalid operand"); if (argOpers[valArgIndx]->isReg()) - MIB = BuildMI(newMBB, TII->get(regOpc), t2); + MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); else - MIB = BuildMI(newMBB, TII->get(immOpc), t2); + MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); MIB.addReg(tt); (*MIB).addOperand(*argOpers[valArgIndx]); - MIB = BuildMI(newMBB, TII->get(copyOpc), EAXreg); + MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg); MIB.addReg(t1); - MIB = BuildMI(newMBB, TII->get(CXchgOpc)); + MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); for (int i=0; i <= lastAddrIndx; ++i) (*MIB).addOperand(*argOpers[i]); MIB.addReg(t2); assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); (*MIB).addMemOperand(*F, *bInstr->memoperands_begin()); - MIB = BuildMI(newMBB, TII->get(copyOpc), destOper.getReg()); + MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg()); MIB.addReg(EAXreg); // insert branch - BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB); + BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB); F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. return nextMBB; @@ -7057,6 +7094,7 @@ newMBB->addSuccessor(nextMBB); newMBB->addSuccessor(newMBB); + DebugLoc dl = bInstr->getDebugLoc(); // Insert instructions into newMBB based on incoming instruction // There are 8 "real" operands plus 9 implicit def/uses, ignored here. assert(bInstr->getNumOperands() < 18 && "unexpected number of operands"); @@ -7070,11 +7108,11 @@ int lastAddrIndx = 3; // [0,3] unsigned t1 = F->getRegInfo().createVirtualRegister(RC); - MachineInstrBuilder MIB = BuildMI(thisMBB, TII->get(LoadOpc), t1); + MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); for (int i=0; i <= lastAddrIndx; ++i) (*MIB).addOperand(*argOpers[i]); unsigned t2 = F->getRegInfo().createVirtualRegister(RC); - MIB = BuildMI(thisMBB, TII->get(LoadOpc), t2); + MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); // add 4 to displacement. for (int i=0; i <= lastAddrIndx-1; ++i) (*MIB).addOperand(*argOpers[i]); @@ -7088,16 +7126,16 @@ // t3/4 are defined later, at the bottom of the loop unsigned t3 = F->getRegInfo().createVirtualRegister(RC); unsigned t4 = F->getRegInfo().createVirtualRegister(RC); - BuildMI(newMBB, TII->get(X86::PHI), dest1Oper.getReg()) + BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); - BuildMI(newMBB, TII->get(X86::PHI), dest2Oper.getReg()) + BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); unsigned tt1 = F->getRegInfo().createVirtualRegister(RC); unsigned tt2 = F->getRegInfo().createVirtualRegister(RC); if (invSrc) { - MIB = BuildMI(newMBB, TII->get(NotOpc), tt1).addReg(t1); - MIB = BuildMI(newMBB, TII->get(NotOpc), tt2).addReg(t2); + MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1); + MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2); } else { tt1 = t1; tt2 = t2; @@ -7108,46 +7146,46 @@ unsigned t5 = F->getRegInfo().createVirtualRegister(RC); unsigned t6 = F->getRegInfo().createVirtualRegister(RC); if (argOpers[4]->isReg()) - MIB = BuildMI(newMBB, TII->get(regOpcL), t5); + MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); else - MIB = BuildMI(newMBB, TII->get(immOpcL), t5); + MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); if (regOpcL != X86::MOV32rr) MIB.addReg(tt1); (*MIB).addOperand(*argOpers[4]); assert(argOpers[5]->isReg() == argOpers[4]->isReg()); assert(argOpers[5]->isImm() == argOpers[4]->isImm()); if (argOpers[5]->isReg()) - MIB = BuildMI(newMBB, TII->get(regOpcH), t6); + MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); else - MIB = BuildMI(newMBB, TII->get(immOpcH), t6); + MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); if (regOpcH != X86::MOV32rr) MIB.addReg(tt2); (*MIB).addOperand(*argOpers[5]); - MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EAX); + MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX); MIB.addReg(t1); - MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EDX); + MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX); MIB.addReg(t2); - MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EBX); + MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX); MIB.addReg(t5); - MIB = BuildMI(newMBB, TII->get(copyOpc), X86::ECX); + MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX); MIB.addReg(t6); - MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG8B)); + MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); for (int i=0; i <= lastAddrIndx; ++i) (*MIB).addOperand(*argOpers[i]); assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); (*MIB).addMemOperand(*F, *bInstr->memoperands_begin()); - MIB = BuildMI(newMBB, TII->get(copyOpc), t3); + MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3); MIB.addReg(X86::EAX); - MIB = BuildMI(newMBB, TII->get(copyOpc), t4); + MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4); MIB.addReg(X86::EDX); // insert branch - BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB); + BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB); F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. return nextMBB; @@ -7193,6 +7231,7 @@ newMBB->addSuccessor(nextMBB); newMBB->addSuccessor(newMBB); + DebugLoc dl = mInstr->getDebugLoc(); // Insert instructions into newMBB based on incoming instruction assert(mInstr->getNumOperands() < 8 && "unexpected number of operands"); MachineOperand& destOper = mInstr->getOperand(0); @@ -7206,7 +7245,7 @@ int valArgIndx = 4; unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); - MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1); + MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); for (int i=0; i <= lastAddrIndx; ++i) (*MIB).addOperand(*argOpers[i]); @@ -7217,37 +7256,37 @@ unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); if (argOpers[valArgIndx]->isReg()) - MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2); + MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); else - MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2); + MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); (*MIB).addOperand(*argOpers[valArgIndx]); - MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX); + MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX); MIB.addReg(t1); - MIB = BuildMI(newMBB, TII->get(X86::CMP32rr)); + MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); MIB.addReg(t1); MIB.addReg(t2); // Generate movc unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); - MIB = BuildMI(newMBB, TII->get(cmovOpc),t3); + MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); MIB.addReg(t2); MIB.addReg(t1); // Cmp and exchange if none has modified the memory location - MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32)); + MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); for (int i=0; i <= lastAddrIndx; ++i) (*MIB).addOperand(*argOpers[i]); MIB.addReg(t3); assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); (*MIB).addMemOperand(*F, *mInstr->memoperands_begin()); - MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg()); + MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg()); MIB.addReg(X86::EAX); // insert branch - BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB); + BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB); F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now. return nextMBB; @@ -7257,6 +7296,7 @@ MachineBasicBlock * X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) { + DebugLoc dl = MI->getDebugLoc(); const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); switch (MI->getOpcode()) { default: assert(false && "Unexpected instr type to insert"); @@ -7286,7 +7326,7 @@ MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); unsigned Opc = X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); - BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB); + BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); F->insert(It, copy0MBB); F->insert(It, sinkMBB); // Update machine-CFG edges by transferring all successors of the current @@ -7309,7 +7349,7 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg()) + BuildMI(BB, dl, TII->get(X86::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); @@ -7330,22 +7370,23 @@ // mode when truncating to an integer value. MachineFunction *F = BB->getParent(); int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); - addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx); + addFrameReference(BuildMI(BB, dl, TII->get(X86::FNSTCW16m)), CWFrameIdx); // Load the old value of the high byte of the control word... unsigned OldCW = F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); - addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx); + addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW), + CWFrameIdx); // Set the high part to be round to zero... - addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx) + addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mi)), CWFrameIdx) .addImm(0xC7F); // Reload the modified control word now... - addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); + addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx); // Restore the memory image of control word to original value - addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx) + addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mr)), CWFrameIdx) .addReg(OldCW); // Get the X86 opcode to use. @@ -7384,11 +7425,11 @@ } else { AM.Disp = Op.getImm(); } - addFullAddress(BuildMI(BB, TII->get(Opc)), AM) + addFullAddress(BuildMI(BB, dl, TII->get(Opc)), AM) .addReg(MI->getOperand(4).getReg()); // Reload the original control word now. - addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); + addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx); F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; @@ -7658,6 +7699,7 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI) { MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); + DebugLoc dl = N->getDebugLoc(); MVT VT = N->getValueType(0); MVT EVT = VT.getVectorElementType(); SDValue PermMask = N->getOperand(2); @@ -7669,11 +7711,12 @@ LoadSDNode *LD = cast(Base); if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI)) - return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), - LD->getSrcValueOffset(), LD->isVolatile()); - return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), - LD->getSrcValueOffset(), LD->isVolatile(), - LD->getAlignment()); + return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), + LD->getSrcValue(), LD->getSrcValueOffset(), + LD->isVolatile()); + return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), + LD->getSrcValue(), LD->getSrcValueOffset(), + LD->isVolatile(), LD->getAlignment()); } /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd. @@ -7682,6 +7725,7 @@ const X86Subtarget *Subtarget, const TargetLowering &TLI) { unsigned NumOps = N->getNumOperands(); + DebugLoc dl = N->getDebugLoc(); // Ignore single operand BUILD_VECTOR. if (NumOps == 1) @@ -7722,7 +7766,7 @@ SDVTList Tys = DAG.getVTList(VT, MVT::Other); SDValue Ops[] = { LD->getChain(), LD->getBasePtr() }; - SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, Tys, Ops, 2); + SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2); TargetLowering::TargetLoweringOpt TLO(DAG); TLO.CombineTo(SDValue(Base, 1), ResNode.getValue(1)); DCI.CommitTargetLoweringOpt(TLO); @@ -7732,6 +7776,7 @@ /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget) { + DebugLoc dl = N->getDebugLoc(); SDValue Cond = N->getOperand(0); // If we have SSE[12] support, try to form min/max nodes. @@ -7793,7 +7838,7 @@ } if (Opcode) - return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS); + return DAG.getNode(Opcode, dl, N->getValueType(0), LHS, RHS); } } @@ -7818,6 +7863,7 @@ SDValue ShAmtOp = N->getOperand(1); MVT EltVT = VT.getVectorElementType(); + DebugLoc dl = N->getDebugLoc(); SDValue BaseShAmt; if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { unsigned NumElts = VT.getVectorNumElements(); @@ -7837,15 +7883,15 @@ } } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && isSplatMask(ShAmtOp.getOperand(2).getNode())) { - BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, ShAmtOp, + BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, ShAmtOp, DAG.getIntPtrConstant(0)); } else return SDValue(); if (EltVT.bitsGT(MVT::i32)) - BaseShAmt = DAG.getNode(ISD::TRUNCATE, MVT::i32, BaseShAmt); + BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt); else if (EltVT.bitsLT(MVT::i32)) - BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BaseShAmt); + BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BaseShAmt); // The shift amount is identical so we can do a vector shift. SDValue ValOp = N->getOperand(0); @@ -7855,39 +7901,39 @@ break; case ISD::SHL: if (VT == MVT::v2i64) - return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, + return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), ValOp, BaseShAmt); if (VT == MVT::v4i32) - return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, + return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), ValOp, BaseShAmt); if (VT == MVT::v8i16) - return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, + return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), ValOp, BaseShAmt); break; case ISD::SRA: if (VT == MVT::v4i32) - return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, + return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), ValOp, BaseShAmt); if (VT == MVT::v8i16) - return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, + return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), ValOp, BaseShAmt); break; case ISD::SRL: if (VT == MVT::v2i64) - return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, + return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), ValOp, BaseShAmt); if (VT == MVT::v4i32) - return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, + return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), ValOp, BaseShAmt); if (VT == MVT::v8i16) - return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, + return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), ValOp, BaseShAmt); break; @@ -7929,32 +7975,33 @@ } } if (Ld) { + DebugLoc dl = N->getDebugLoc(); // If we are a 64-bit capable x86, lower to a single movq load/store pair. if (Subtarget->is64Bit()) { - SDValue NewLd = DAG.getLoad(MVT::i64, Ld->getChain(), + SDValue NewLd = DAG.getLoad(MVT::i64, dl, Ld->getChain(), Ld->getBasePtr(), Ld->getSrcValue(), Ld->getSrcValueOffset(), Ld->isVolatile(), Ld->getAlignment()); SDValue NewChain = NewLd.getValue(1); if (TokenFactorIndex != -1) { Ops.push_back(NewChain); - NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], + NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Ops[0], Ops.size()); } - return DAG.getStore(NewChain, NewLd, St->getBasePtr(), + return DAG.getStore(NewChain, dl, NewLd, St->getBasePtr(), St->getSrcValue(), St->getSrcValueOffset(), St->isVolatile(), St->getAlignment()); } // Otherwise, lower to two 32-bit copies. SDValue LoAddr = Ld->getBasePtr(); - SDValue HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr, + SDValue HiAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, LoAddr, DAG.getConstant(4, MVT::i32)); - SDValue LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr, + SDValue LoLd = DAG.getLoad(MVT::i32, dl, Ld->getChain(), LoAddr, Ld->getSrcValue(), Ld->getSrcValueOffset(), Ld->isVolatile(), Ld->getAlignment()); - SDValue HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr, + SDValue HiLd = DAG.getLoad(MVT::i32, dl, Ld->getChain(), HiAddr, Ld->getSrcValue(), Ld->getSrcValueOffset()+4, Ld->isVolatile(), MinAlign(Ld->getAlignment(), 4)); @@ -7963,23 +8010,23 @@ if (TokenFactorIndex != -1) { Ops.push_back(LoLd); Ops.push_back(HiLd); - NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], + NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Ops[0], Ops.size()); } LoAddr = St->getBasePtr(); - HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr, + HiAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, LoAddr, DAG.getConstant(4, MVT::i32)); - SDValue LoSt = DAG.getStore(NewChain, LoLd, LoAddr, + SDValue LoSt = DAG.getStore(NewChain, dl, LoLd, LoAddr, St->getSrcValue(), St->getSrcValueOffset(), St->isVolatile(), St->getAlignment()); - SDValue HiSt = DAG.getStore(NewChain, HiLd, HiAddr, + SDValue HiSt = DAG.getStore(NewChain, dl, HiLd, HiAddr, St->getSrcValue(), St->getSrcValueOffset() + 4, St->isVolatile(), MinAlign(St->getAlignment(), 4)); - return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt); + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoSt, HiSt); } } return SDValue(); From sabre at nondot.org Tue Feb 3 15:01:04 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Feb 2009 21:01:04 -0000 Subject: [llvm-commits] [llvm] r63658 - /llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Message-ID: <200902032101.n13L14a6015975@zion.cs.uiuc.edu> Author: lattner Date: Tue Feb 3 15:01:03 2009 New Revision: 63658 URL: http://llvm.org/viewvc/llvm-project?rev=63658&view=rev Log: refactor the interface to ConvertUsesOfLoadToScalar, renaming it to ConvertScalar_ExtractValue Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=63658&r1=63657&r2=63658&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Tue Feb 3 15:01:03 2009 @@ -129,7 +129,7 @@ bool CanConvertToScalar(Value *V, bool &IsNotTrivial, const Type *&VecTy, bool &SawVec, uint64_t Offset, unsigned AllocaSize); void ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, uint64_t Offset); - Value *ConvertUsesOfLoadToScalar(LoadInst *LI, AllocaInst *NewAI, + Value *ConvertScalar_ExtractValue(Value *NV, const Type *ToType, uint64_t Offset, IRBuilder<> &Builder); Value *ConvertScalar_InsertValue(Value *StoredVal, Value *ExistingVal, uint64_t Offset, IRBuilder<> &Builder); @@ -1338,8 +1338,11 @@ IRBuilder<> Builder(User->getParent(), User); if (LoadInst *LI = dyn_cast(User)) { - Value *LoadVal = ConvertUsesOfLoadToScalar(LI, NewAI, Offset, Builder); - LI->replaceAllUsesWith(LoadVal); + // The load is a bit extract from NewAI shifted right by Offset bits. + Value *LoadedVal = Builder.CreateLoad(NewAI, "tmp"); + Value *NewLoadVal + = ConvertScalar_ExtractValue(LoadedVal, LI->getType(), Offset, Builder); + LI->replaceAllUsesWith(NewLoadVal); LI->eraseFromParent(); continue; } @@ -1383,28 +1386,27 @@ } } -/// ConvertUsesOfLoadToScalar - Convert all of the users of the specified load -/// to use the new alloca directly, returning the value that should replace the -/// load. This happens when we are converting an "integer union" to a single +/// ConvertScalar_ExtractValue - Extract a value of type ToType from an integer +/// or vector value FromVal, extracting the bits from the offset specified by +/// Offset. This returns the value, which is of type ToType. +/// +/// This happens when we are converting an "integer union" to a single /// integer scalar, or when we are converting a "vector union" to a vector with /// insert/extractelement instructions. /// /// Offset is an offset from the original alloca, in bits that need to be -/// shifted to the right. By the end of this, there should be no uses of Ptr. -Value *SROA::ConvertUsesOfLoadToScalar(LoadInst *LI, AllocaInst *NewAI, - uint64_t Offset, IRBuilder<> &Builder) { - // The load is a bit extract from NewAI shifted right by Offset bits. - Value *NV = Builder.CreateLoad(NewAI, "tmp"); - +/// shifted to the right. +Value *SROA::ConvertScalar_ExtractValue(Value *FromVal, const Type *ToType, + uint64_t Offset, IRBuilder<> &Builder) { // If the load is of the whole new alloca, no conversion is needed. - if (NV->getType() == LI->getType() && Offset == 0) - return NV; + if (FromVal->getType() == ToType && Offset == 0) + return FromVal; // If the result alloca is a vector type, this is either an element // access or a bitcast to another vector type of the same size. - if (const VectorType *VTy = dyn_cast(NV->getType())) { - if (isa(LI->getType())) - return Builder.CreateBitCast(NV, LI->getType(), "tmp"); + if (const VectorType *VTy = dyn_cast(FromVal->getType())) { + if (isa(ToType)) + return Builder.CreateBitCast(FromVal, ToType, "tmp"); // Otherwise it must be an element access. unsigned Elt = 0; @@ -1414,16 +1416,16 @@ assert(EltSize*Elt == Offset && "Invalid modulus in validity checking"); } // Return the element extracted out of it. - Value *V = Builder.CreateExtractElement(NV, + Value *V = Builder.CreateExtractElement(FromVal, ConstantInt::get(Type::Int32Ty,Elt), "tmp"); - if (V->getType() != LI->getType()) - V = Builder.CreateBitCast(V, LI->getType(), "tmp"); + if (V->getType() != ToType) + V = Builder.CreateBitCast(V, ToType, "tmp"); return V; } // Otherwise, this must be a union that was converted to an integer value. - const IntegerType *NTy = cast(NV->getType()); + const IntegerType *NTy = cast(FromVal->getType()); // If this is a big-endian system and the load is narrower than the // full alloca type, we need to do a shift to get the right bits. @@ -1433,7 +1435,7 @@ // from the pointer given by getTypeStoreSizeInBits. This matters for // integers with a bitwidth that is not a multiple of 8. ShAmt = TD->getTypeStoreSizeInBits(NTy) - - TD->getTypeStoreSizeInBits(LI->getType()) - Offset; + TD->getTypeStoreSizeInBits(ToType) - Offset; } else { ShAmt = Offset; } @@ -1442,30 +1444,29 @@ // We do this to support (f.e.) loads off the end of a structure where // only some bits are used. if (ShAmt > 0 && (unsigned)ShAmt < NTy->getBitWidth()) - NV = Builder.CreateLShr(NV, ConstantInt::get(NV->getType(), ShAmt), "tmp"); + FromVal = Builder.CreateLShr(FromVal, ConstantInt::get(FromVal->getType(), ShAmt), "tmp"); else if (ShAmt < 0 && (unsigned)-ShAmt < NTy->getBitWidth()) - NV = Builder.CreateShl(NV, ConstantInt::get(NV->getType(), -ShAmt), "tmp"); + FromVal = Builder.CreateShl(FromVal, ConstantInt::get(FromVal->getType(), -ShAmt), "tmp"); // Finally, unconditionally truncate the integer to the right width. - unsigned LIBitWidth = TD->getTypeSizeInBits(LI->getType()); + unsigned LIBitWidth = TD->getTypeSizeInBits(ToType); if (LIBitWidth < NTy->getBitWidth()) - NV = Builder.CreateTrunc(NV, IntegerType::get(LIBitWidth), "tmp"); + FromVal = Builder.CreateTrunc(FromVal, IntegerType::get(LIBitWidth), "tmp"); else if (LIBitWidth > NTy->getBitWidth()) - NV = Builder.CreateZExt(NV, IntegerType::get(LIBitWidth), "tmp"); + FromVal = Builder.CreateZExt(FromVal, IntegerType::get(LIBitWidth), "tmp"); // If the result is an integer, this is a trunc or bitcast. - if (isa(LI->getType())) { + if (isa(ToType)) { // Should be done. - } else if (LI->getType()->isFloatingPoint() || - isa(LI->getType())) { + } else if (ToType->isFloatingPoint() || isa(ToType)) { // Just do a bitcast, we know the sizes match up. - NV = Builder.CreateBitCast(NV, LI->getType(), "tmp"); + FromVal = Builder.CreateBitCast(FromVal, ToType, "tmp"); } else { // Otherwise must be a pointer. - NV = Builder.CreateIntToPtr(NV, LI->getType(), "tmp"); + FromVal = Builder.CreateIntToPtr(FromVal, ToType, "tmp"); } - assert(NV->getType() == LI->getType() && "Didn't convert right?"); - return NV; + assert(FromVal->getType() == ToType && "Didn't convert right?"); + return FromVal; } From clattner at apple.com Tue Feb 3 15:03:52 2009 From: clattner at apple.com (Chris Lattner) Date: Tue, 3 Feb 2009 13:03:52 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63633 - /llvm-gcc-4.2/trunk/gcc/gcc.c In-Reply-To: <200902031620.n13GKM9K005714@zion.cs.uiuc.edu> References: <200902031620.n13GKM9K005714@zion.cs.uiuc.edu> Message-ID: On Feb 3, 2009, at 8:20 AM, Rafael Espindola wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=63633&view=rev > Log: > One difference of the way the Apple ld and gold implement plugins is > that gold > doesn't search for the plugin. It must be passed with the -plugin > option. > > This patch makes gcc search for the plugin in the same way it > searches for cc1. > The search only happens if the -use-gold-plugin option is used. If > the plugin > is found, it is passed to gold. Very nice Rafael, Please use the LTDL_SUFFIX (or whatever) macro which indicates whether a dynamic library suffix is ".so" or ".dylib" or .somethingelse. I know that gold currently only supports elf, but it would be nice to keep the code general. Also, please make sure to wrap your llvm-gcc changes with "LLVM LOCAL" markers so that the changes don't get lost in merges. Thanks! -Chris > > > > Modified: > llvm-gcc-4.2/trunk/gcc/gcc.c > > Modified: llvm-gcc-4.2/trunk/gcc/gcc.c > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gcc.c?rev=63633&r1=63632&r2=63633&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm-gcc-4.2/trunk/gcc/gcc.c (original) > +++ llvm-gcc-4.2/trunk/gcc/gcc.c Tue Feb 3 10:20:19 2009 > @@ -713,10 +713,12 @@ > scripts which exist in user specified directories, or in standard > directories. */ > /* APPLE LOCAL begin add fcreate-profile */ > +/* LLVM LOCAL begin add use-gold-plugin */ > #ifndef LINK_COMMAND_SPEC > #define LINK_COMMAND_SPEC "\ > %{!fsyntax-only:%{!c:%{!M:%{!MM:%{!E:%{!S:\ > - %(linker) %l " LINK_PIE_SPEC "%X %{o*} %{A} %{d} %{e*} %{m} % > {N} %{n} %{r}\ > + %(linker) %{use-gold-plugin: -plugin %(gold_plugin_file)} \ > + %l " LINK_PIE_SPEC "%X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r}\ > %{s} %{t} %{u*} %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles: > %S}}}\ > %{static:} %{L*} %(mfwrap) %(link_libgcc) %o\ > %{fopenmp:%:include(libgomp.spec)%(link_gomp)} %(mflib)\ > @@ -765,6 +767,7 @@ > static const char *startfile_spec = STARTFILE_SPEC; > static const char *switches_need_spaces = SWITCHES_NEED_SPACES; > static const char *linker_name_spec = LINKER_NAME; > +static const char *gold_plugin_file_spec = ""; > static const char *link_command_spec = LINK_COMMAND_SPEC; > static const char *link_libgcc_spec = LINK_LIBGCC_SPEC; > static const char *startfile_prefix_spec = STARTFILE_PREFIX_SPEC; > @@ -1637,6 +1640,7 @@ > INIT_STATIC_SPEC ("linker", &linker_name_spec), > INIT_STATIC_SPEC ("link_libgcc", &link_libgcc_spec), > /* LLVM LOCAL */ > + INIT_STATIC_SPEC ("gold_plugin_file", &gold_plugin_file_spec), > INIT_STATIC_SPEC ("llvm_options", &llvm_options), > INIT_STATIC_SPEC ("md_exec_prefix", &md_exec_prefix), > INIT_STATIC_SPEC ("md_startfile_prefix", &md_startfile_prefix), > @@ -7138,6 +7142,7 @@ > if (num_linker_inputs > 0 && error_count == 0) > { > int tmp = execution_count; > + const char *use_gold_plugin = "use-gold-plugin"; > > /* We'll use ld if we can't find collect2. */ > if (! strcmp (linker_name_spec, "collect2")) > @@ -7146,6 +7151,17 @@ > if (s == NULL) > linker_name_spec = "ld"; > } > + > + if (switch_matches (use_gold_plugin, > + use_gold_plugin + strlen (use_gold_plugin), 0)) > + { > + gold_plugin_file_spec = find_a_file (&exec_prefixes, > + "libLLVMgold.so", X_OK, > + false); > + if (!gold_plugin_file_spec) > + fatal ("-use-gold-plugin, but libLLVMgold.so not found."); > + } > + > /* Rebuild the COMPILER_PATH and LIBRARY_PATH environment > variables > for collect. */ > putenv_from_prefixes (&exec_prefixes, "COMPILER_PATH", false); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From sabre at nondot.org Tue Feb 3 15:08:45 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Feb 2009 21:08:45 -0000 Subject: [llvm-commits] [llvm] r63659 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/sroa-fca.ll Message-ID: <200902032108.n13L8jNE016300@zion.cs.uiuc.edu> Author: lattner Date: Tue Feb 3 15:08:45 2009 New Revision: 63659 URL: http://llvm.org/viewvc/llvm-project?rev=63659&view=rev Log: teach "convert from scalar" to handle loads of fca's. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/trunk/test/Transforms/ScalarRepl/sroa-fca.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=63659&r1=63658&r2=63659&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Tue Feb 3 15:08:45 2009 @@ -1423,6 +1423,31 @@ V = Builder.CreateBitCast(V, ToType, "tmp"); return V; } + + // If ToType is a first class aggregate, extract out each of the pieces and + // use insertvalue's to form the FCA. + if (const StructType *ST = dyn_cast(ToType)) { + const StructLayout &Layout = *TD->getStructLayout(ST); + Value *Res = UndefValue::get(ST); + for (unsigned i = 0, e = ST->getNumElements(); i != e; ++i) { + Value *Elt = ConvertScalar_ExtractValue(FromVal, ST->getElementType(i), + Offset+Layout.getElementOffset(i), + Builder); + Res = Builder.CreateInsertValue(Res, Elt, i, "tmp"); + } + return Res; + } + + if (const ArrayType *AT = dyn_cast(ToType)) { + uint64_t EltSize = TD->getTypePaddedSizeInBits(AT->getElementType()); + Value *Res = UndefValue::get(AT); + for (unsigned i = 0, e = AT->getNumElements(); i != e; ++i) { + Value *Elt = ConvertScalar_ExtractValue(FromVal, AT->getElementType(), + Offset+i*EltSize, Builder); + Res = Builder.CreateInsertValue(Res, Elt, i, "tmp"); + } + return Res; + } // Otherwise, this must be a union that was converted to an integer value. const IntegerType *NTy = cast(FromVal->getType()); @@ -1444,9 +1469,11 @@ // We do this to support (f.e.) loads off the end of a structure where // only some bits are used. if (ShAmt > 0 && (unsigned)ShAmt < NTy->getBitWidth()) - FromVal = Builder.CreateLShr(FromVal, ConstantInt::get(FromVal->getType(), ShAmt), "tmp"); + FromVal = Builder.CreateLShr(FromVal, ConstantInt::get(FromVal->getType(), + ShAmt), "tmp"); else if (ShAmt < 0 && (unsigned)-ShAmt < NTy->getBitWidth()) - FromVal = Builder.CreateShl(FromVal, ConstantInt::get(FromVal->getType(), -ShAmt), "tmp"); + FromVal = Builder.CreateShl(FromVal, ConstantInt::get(FromVal->getType(), + -ShAmt), "tmp"); // Finally, unconditionally truncate the integer to the right width. unsigned LIBitWidth = TD->getTypeSizeInBits(ToType); Modified: llvm/trunk/test/Transforms/ScalarRepl/sroa-fca.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/sroa-fca.ll?rev=63659&r1=63658&r2=63659&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/sroa-fca.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/sroa-fca.ll Tue Feb 3 15:08:45 2009 @@ -10,3 +10,12 @@ ret i64 %Q } +define {i32,i32} @test2(i64 %A) { + %X = alloca i64 + %Y = bitcast i64* %X to {i32,i32}* + store i64 %A, i64* %X + + %Q = load {i32,i32}* %Y + ret {i32,i32} %Q +} + From isanbard at gmail.com Tue Feb 3 15:17:20 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 03 Feb 2009 21:17:20 -0000 Subject: [llvm-commits] [llvm] r63660 - in /llvm/trunk/lib/CodeGen: AsmPrinter/DwarfWriter.cpp GCStrategy.cpp Message-ID: <200902032117.n13LHKdE016666@zion.cs.uiuc.edu> Author: void Date: Tue Feb 3 15:17:20 2009 New Revision: 63660 URL: http://llvm.org/viewvc/llvm-project?rev=63660&view=rev Log: Whitespace and comment changes. No functionality change. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp llvm/trunk/lib/CodeGen/GCStrategy.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=63660&r1=63659&r2=63660&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Tue Feb 3 15:17:20 2009 @@ -54,9 +54,9 @@ /// Configuration values for initial hash set sizes (log2). /// -static const unsigned InitDiesSetSize = 9; // 512 -static const unsigned InitAbbreviationsSetSize = 9; // 512 -static const unsigned InitValuesSetSize = 9; // 512 +static const unsigned InitDiesSetSize = 9; // log2(512) +static const unsigned InitAbbreviationsSetSize = 9; // log2(512) +static const unsigned InitValuesSetSize = 9; // log2(512) //===----------------------------------------------------------------------===// /// Forward declarations. @@ -855,9 +855,7 @@ /// Dwarf - Emits general Dwarf directives. /// class Dwarf { - protected: - //===--------------------------------------------------------------------===// // Core attributes used by the Dwarf writer. // @@ -918,7 +916,6 @@ } public: - //===--------------------------------------------------------------------===// // Accessors. // @@ -1166,7 +1163,7 @@ unsigned LabelID; // Label in code ID number. public: SrcLineInfo(unsigned L, unsigned C, unsigned S, unsigned I) - : Line(L), Column(C), SourceID(S), LabelID(I) {} + : Line(L), Column(C), SourceID(S), LabelID(I) {} // Accessors unsigned getLine() const { return Line; } @@ -1175,7 +1172,6 @@ unsigned getLabelID() const { return LabelID; } }; - //===----------------------------------------------------------------------===// /// SrcFileInfo - This class is used to track source information. /// @@ -1207,10 +1203,8 @@ /// DbgVariable - This class is used to track local variable information. /// class DbgVariable { -private: DIVariable Var; // Variable Descriptor. unsigned FrameIndex; // Variable frame index. - public: DbgVariable(DIVariable V, unsigned I) : Var(V), FrameIndex(I) {} @@ -1223,7 +1217,6 @@ /// DbgScope - This class is used to track scope information. /// class DbgScope { -private: DbgScope *Parent; // Parent to this scope. DIDescriptor Desc; // Debug info descriptor for scope. // Either subprogram or block. @@ -1231,7 +1224,6 @@ unsigned EndLabelID; // Label ID of the end of scope. SmallVector Scopes; // Scopes defined in scope. SmallVector Variables;// Variables declared in scope. - public: DbgScope(DbgScope *P, DIDescriptor D) : Parent(P), Desc(D), StartLabelID(0), EndLabelID(0), Scopes(), Variables() @@ -1264,8 +1256,6 @@ /// DwarfDebug - Emits Dwarf debug directives. /// class DwarfDebug : public Dwarf { - -private: //===--------------------------------------------------------------------===// // Attributes used to construct specific Dwarf sections. // @@ -1641,7 +1631,7 @@ else if (Ty.isDerivedType(Ty.getTag())) ConstructTypeDIE(DW_Unit, Buffer, DIDerivedType(Ty.getGV())); else { - assert (Ty.isCompositeType(Ty.getTag()) && "Unknown kind of DIType"); + assert(Ty.isCompositeType(Ty.getTag()) && "Unknown kind of DIType"); ConstructTypeDIE(DW_Unit, Buffer, DICompositeType(Ty.getGV())); } @@ -1656,8 +1646,7 @@ Die->AddChild(Child); Buffer.Detach(); SetDIEntry(Slot, Child); - } - else { + } else { Die = DW_Unit->AddDie(Buffer); SetDIEntry(Slot, Die); } @@ -1806,8 +1795,8 @@ } } - // ConstructSubrangeDIE - Construct subrange DIE from DISubrange. - void ConstructSubrangeDIE (DIE &Buffer, DISubrange SR, DIE *IndexTy) { + /// ConstructSubrangeDIE - Construct subrange DIE from DISubrange. + void ConstructSubrangeDIE(DIE &Buffer, DISubrange SR, DIE *IndexTy) { int64_t L = SR.getLo(); int64_t H = SR.getHi(); DIE *DW_Subrange = new DIE(DW_TAG_subrange_type); @@ -1845,8 +1834,7 @@ } } - /// ConstructEnumTypeDIE - Construct enum type DIE from - /// DIEnumerator. + /// ConstructEnumTypeDIE - Construct enum type DIE from DIEnumerator. DIE *ConstructEnumTypeDIE(CompileUnit *DW_Unit, DIEnumerator *ETy) { DIE *Enumerator = new DIE(DW_TAG_enumerator); @@ -1857,7 +1845,7 @@ } /// CreateGlobalVariableDIE - Create new DIE using GV. - DIE *CreateGlobalVariableDIE(CompileUnit *DW_Unit, const DIGlobalVariable &GV) + DIE *CreateGlobalVariableDIE(CompileUnit *DW_Unit, const DIGlobalVariable &GV) { DIE *GVDie = new DIE(DW_TAG_variable); AddString(GVDie, DW_AT_name, DW_FORM_string, GV.getName()); @@ -2101,9 +2089,9 @@ std::string SPName = "llvm.dbg.subprograms"; std::vector Result; getGlobalVariablesUsing(*M, SPName, Result); + for (std::vector::iterator I = Result.begin(), E = Result.end(); I != E; ++I) { - DISubprogram SPD(*I); if (SPD.getName() == MF->getFunction()->getName()) { @@ -3183,8 +3171,6 @@ /// DwarfException - Emits Dwarf exception handling directives. /// class DwarfException : public Dwarf { - -private: struct FunctionEHFrameInfo { std::string FnName; unsigned Number; Modified: llvm/trunk/lib/CodeGen/GCStrategy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GCStrategy.cpp?rev=63660&r1=63659&r2=63660&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/GCStrategy.cpp (original) +++ llvm/trunk/lib/CodeGen/GCStrategy.cpp Tue Feb 3 15:17:20 2009 @@ -329,6 +329,7 @@ unsigned MachineCodeAnalysis::InsertLabel(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { unsigned Label = MMI->NextLabelID(); + // N.B. we assume that MI is *not* equal to the "end()" iterator. BuildMI(MBB, MI, MI->getDebugLoc(), TII->get(TargetInstrInfo::GC_LABEL)).addImm(Label); return Label; From isanbard at gmail.com Tue Feb 3 15:38:21 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 03 Feb 2009 21:38:21 -0000 Subject: [llvm-commits] [llvm] r63663 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Message-ID: <200902032138.n13LcLIo017450@zion.cs.uiuc.edu> Author: void Date: Tue Feb 3 15:38:21 2009 New Revision: 63663 URL: http://llvm.org/viewvc/llvm-project?rev=63663&view=rev Log: More whitespace fixin'. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=63663&r1=63662&r2=63663&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Tue Feb 3 15:38:21 2009 @@ -2783,7 +2783,7 @@ CompileUnit *Unit = new CompileUnit(ID, Die); if (DIUnit.isMain()) { - assert (!MainCU && "Multiple main compile units are found!"); + assert(!MainCU && "Multiple main compile units are found!"); MainCU = Unit; } DW_CUs[DIUnit.getGV()] = Unit; @@ -2889,41 +2889,40 @@ /// SetDebugInfo - Create global DIEs and emit initial debug info sections. /// This is inovked by the target AsmPrinter. void SetDebugInfo(MachineModuleInfo *mmi) { - - // Create all the compile unit DIEs. - ConstructCompileUnits(); + // Create all the compile unit DIEs. + ConstructCompileUnits(); - if (DW_CUs.empty()) - return; + if (DW_CUs.empty()) + return; - MMI = mmi; - shouldEmit = true; - MMI->setDebugInfoAvailability(true); - - // Create DIEs for each of the externally visible global variables. - ConstructGlobalVariableDIEs(); - - // Create DIEs for each of the externally visible subprograms. - ConstructSubprograms(); - - // Prime section data. - SectionMap.insert(TAI->getTextSection()); - - // Print out .file directives to specify files for .loc directives. These - // are printed out early so that they precede any .loc directives. - if (TAI->hasDotLocAndDotFile()) { - for (unsigned i = 1, e = SrcFiles.size(); i <= e; ++i) { - sys::Path FullPath(Directories[SrcFiles[i].getDirectoryID()]); - bool AppendOk = FullPath.appendComponent(SrcFiles[i].getName()); - assert(AppendOk && "Could not append filename to directory!"); - AppendOk = false; - Asm->EmitFile(i, FullPath.toString()); - Asm->EOL(); - } + MMI = mmi; + shouldEmit = true; + MMI->setDebugInfoAvailability(true); + + // Create DIEs for each of the externally visible global variables. + ConstructGlobalVariableDIEs(); + + // Create DIEs for each of the externally visible subprograms. + ConstructSubprograms(); + + // Prime section data. + SectionMap.insert(TAI->getTextSection()); + + // Print out .file directives to specify files for .loc directives. These + // are printed out early so that they precede any .loc directives. + if (TAI->hasDotLocAndDotFile()) { + for (unsigned i = 1, e = SrcFiles.size(); i <= e; ++i) { + sys::Path FullPath(Directories[SrcFiles[i].getDirectoryID()]); + bool AppendOk = FullPath.appendComponent(SrcFiles[i].getName()); + assert(AppendOk && "Could not append filename to directory!"); + AppendOk = false; + Asm->EmitFile(i, FullPath.toString()); + Asm->EOL(); } + } - // Emit initial sections - EmitInitial(); + // Emit initial sections + EmitInitial(); } /// BeginModule - Emit all Dwarf sections that should come prior to the @@ -3082,13 +3081,13 @@ unsigned Tag = DI.getTag(); switch (Tag) { case DW_TAG_variable: - assert (DIVariable(GV).Verify() && "Invalid DebugInfo value"); + assert(DIVariable(GV).Verify() && "Invalid DebugInfo value"); break; case DW_TAG_compile_unit: - assert (DICompileUnit(GV).Verify() && "Invalid DebugInfo value"); + assert(DICompileUnit(GV).Verify() && "Invalid DebugInfo value"); break; case DW_TAG_subprogram: - assert (DISubprogram(GV).Verify() && "Invalid DebugInfo value"); + assert(DISubprogram(GV).Verify() && "Invalid DebugInfo value"); break; default: break; @@ -3102,7 +3101,7 @@ /// correspondence to the source line list. unsigned RecordSourceLine(Value *V, unsigned Line, unsigned Col) { CompileUnit *Unit = DW_CUs[V]; - assert (Unit && "Unable to find CompileUnit"); + assert(Unit && "Unable to find CompileUnit"); unsigned ID = MMI->NextLabelID(); Lines.push_back(SrcLineInfo(Line, Col, Unit->getID(), ID)); return ID; @@ -3161,7 +3160,7 @@ DIVariable DV(GV); Scope = getOrCreateScope(DV.getContext().getGV()); } - assert (Scope && "Unable to find variable' scope"); + assert(Scope && "Unable to find variable' scope"); DbgVariable *DV = new DbgVariable(DIVariable(GV), FrameIndex); Scope->AddVariable(DV); } From ggreif at gmail.com Tue Feb 3 15:41:51 2009 From: ggreif at gmail.com (Gabor Greif) Date: Tue, 3 Feb 2009 13:41:51 -0800 (PST) Subject: [llvm-commits] [llvm] r63539 - /llvm/trunk/win32/config.h In-Reply-To: <16e5fdf90902021641h7dfd7779v736716e6e5f119b@mail.gmail.com> References: <200902021922.n12JM3W7015508@zion.cs.uiuc.edu> <49ea1292-789b-48bf-9c6c-95fb73d71511@w1g2000prm.googlegroups.com> <16e5fdf90902021641h7dfd7779v736716e6e5f119b@mail.gmail.com> Message-ID: <65dd6f7d-19a1-4852-8ef1-e780bf322a26@n33g2000pri.googlegroups.com> On 3 fev, 01:41, Bill Wendling wrote: > On Mon, Feb 2, 2009 at 12:39 PM, Gabor Greif wrote: > > On 2 Feb., 20:22, Steve Naroff wrote: > >> Author: snaroff > >> Date: Mon Feb ?2 13:22:02 2009 > >> New Revision: 63539 > > >> URL:http://llvm.org/viewvc/llvm-project?rev=63539&view=rev > >> Log: > >> Update hand-crafted VC++ build. > >> - Add PACKAGE_STRING definition to Windows config.h. > > >> Modified: > >> ? ? llvm/trunk/win32/config.h > > >> Modified: llvm/trunk/win32/config.h > >> URL:http://llvm.org/viewvc/llvm-project/llvm/trunk/win32/config.h?rev=635... > > >> =========================================================================== === > >> --- llvm/trunk/win32/config.h (original) > >> +++ llvm/trunk/win32/config.h Mon Feb ?2 13:22:02 2009 > >> @@ -3,6 +3,7 @@ > > >> ?#define PACKAGE_NAME "LLVM (win32 vc8.0)" > >> ?#define PACKAGE_VERSION 2.4 > > > Bill, this ^^^^^^ does not seem right. > > Bill? :-) Ehrm, sorry Bill, that should be Steve... :-) Cheers, Gabor > > -bw > _______________________________________________ > llvm-commits mailing list > llvm-comm... at cs.uiuc.eduhttp://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dalej at apple.com Tue Feb 3 15:48:12 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 03 Feb 2009 21:48:12 -0000 Subject: [llvm-commits] [llvm] r63664 - /llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Message-ID: <200902032148.n13LmCou017828@zion.cs.uiuc.edu> Author: johannes Date: Tue Feb 3 15:48:12 2009 New Revision: 63664 URL: http://llvm.org/viewvc/llvm-project?rev=63664&view=rev Log: DebugLoc propgation Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=63664&r1=63663&r2=63664&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Feb 3 15:48:12 2009 @@ -658,12 +658,13 @@ MemVT = SrcIsSSE ? SrcVT : DstVT; SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT); + DebugLoc dl = N->getDebugLoc(); // FIXME: optimize the case where the src/dest is a load or store? - SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), + SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl, N->getOperand(0), MemTmp, NULL, 0, MemVT); - SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, DstVT, Store, MemTmp, + SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp, NULL, 0, MemVT); // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the @@ -729,6 +730,7 @@ bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM, bool isRoot, unsigned Depth) { bool is64Bit = Subtarget->is64Bit(); + DebugLoc dl = N.getNode()->getDebugLoc(); DOUT << "MatchAddress: "; DEBUG(AM.dump()); // Limit recursion. if (Depth > 5) @@ -950,10 +952,11 @@ // Get the new AND mask, this folds to a constant. SDValue X = Shift.getOperand(0); - SDValue NewANDMask = CurDAG->getNode(ISD::SRL, N.getValueType(), + SDValue NewANDMask = CurDAG->getNode(ISD::SRL, dl, N.getValueType(), SDValue(C2, 0), SDValue(C1, 0)); - SDValue NewAND = CurDAG->getNode(ISD::AND, N.getValueType(), X, NewANDMask); - SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, N.getValueType(), + SDValue NewAND = CurDAG->getNode(ISD::AND, dl, N.getValueType(), X, + NewANDMask); + SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, dl, N.getValueType(), NewAND, SDValue(C1, 0)); // Insert the new nodes into the topological ordering. @@ -1164,6 +1167,7 @@ assert(!Subtarget->is64Bit() && "getTruncateTo8Bit is only needed on x86-32!"); SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1 + DebugLoc dl = N0.getNode()->getDebugLoc(); // Ensure that the source register has an 8-bit subreg on 32-bit targets unsigned Opc; @@ -1180,8 +1184,8 @@ // The use of MVT::Flag here is not strictly accurate, but it helps // scheduling in some cases. - N0 = SDValue(CurDAG->getTargetNode(Opc, N0VT, MVT::Flag, N0), 0); - return CurDAG->getTargetNode(X86::EXTRACT_SUBREG, + N0 = SDValue(CurDAG->getTargetNode(Opc, dl, N0VT, MVT::Flag, N0), 0); + return CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl, MVT::i8, N0, SRIdx, N0.getValue(1)); } @@ -1195,7 +1199,8 @@ return NULL; SDValue LSI = Node->getOperand(4); // MemOperand const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, In2L, In2H, LSI, Chain }; - return CurDAG->getTargetNode(Opc, MVT::i32, MVT::i32, MVT::Other, Ops, 8); + return CurDAG->getTargetNode(Opc, Node->getDebugLoc(), + MVT::i32, MVT::i32, MVT::Other, Ops, 8); } SDNode *X86DAGToDAGISel::Select(SDValue N) { @@ -1203,7 +1208,8 @@ MVT NVT = Node->getValueType(0); unsigned Opc, MOpc; unsigned Opcode = Node->getOpcode(); - + DebugLoc dl = Node->getDebugLoc(); + #ifndef NDEBUG DOUT << std::string(Indent, ' ') << "Selecting: "; DEBUG(Node->dump(CurDAG)); @@ -1288,13 +1294,13 @@ if (foldedLoad) { SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag }; SDNode *CNode = - CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6); + CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops, 6); InFlag = SDValue(CNode, 1); // Update the chain. ReplaceUses(N1.getValue(1), SDValue(CNode, 0)); } else { InFlag = - SDValue(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0); + SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0); } // Copy the low half of the result, if it is needed. @@ -1318,11 +1324,12 @@ Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), X86::AX, MVT::i16, InFlag); InFlag = Result.getValue(2); - Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result, + Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16, + Result, CurDAG->getTargetConstant(8, MVT::i8)), 0); // Then truncate it down to i8. SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1 - Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, + Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl, MVT::i8, Result, SRIdx), 0); } else { Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), @@ -1405,13 +1412,13 @@ if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) { SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) }; Move = - SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, MVT::i16, MVT::Other, - Ops, 5), 0); + SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, MVT::i16, + MVT::Other, Ops, 5), 0); Chain = Move.getValue(1); ReplaceUses(N0.getValue(1), Chain); } else { Move = - SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, MVT::i16, N0), 0); + SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0); Chain = CurDAG->getEntryNode(); } Chain = CurDAG->getCopyToReg(Chain, X86::AX, Move, SDValue()); @@ -1423,10 +1430,11 @@ if (isSigned && !signBitIsZero) { // Sign extend the low part into the high part. InFlag = - SDValue(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0); + SDValue(CurDAG->getTargetNode(SExtOpcode, dl, MVT::Flag, InFlag),0); } else { // Zero out the high part, effectively zero extending the input. - SDValue ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, NVT), 0); + SDValue ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, dl, NVT), + 0); InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), HiReg, ClrNode, InFlag).getValue(1); } @@ -1435,13 +1443,13 @@ if (foldedLoad) { SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag }; SDNode *CNode = - CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6); + CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops, 6); InFlag = SDValue(CNode, 1); // Update the chain. ReplaceUses(N1.getValue(1), SDValue(CNode, 0)); } else { InFlag = - SDValue(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0); + SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0); } // Copy the division (low) result, if it is needed. @@ -1465,11 +1473,13 @@ Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), X86::AX, MVT::i16, InFlag); InFlag = Result.getValue(2); - Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result, - CurDAG->getTargetConstant(8, MVT::i8)), 0); + Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16, + Result, + CurDAG->getTargetConstant(8, MVT::i8)), + 0); // Then truncate it down to i8. SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1 - Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, + Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl, MVT::i8, Result, SRIdx), 0); } else { Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), @@ -1508,7 +1518,7 @@ break; } - SDNode *ResNode = CurDAG->getTargetNode(Opc, NVT, TruncOp); + SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, NVT, TruncOp); #ifndef NDEBUG DOUT << std::string(Indent-2, ' ') << "=> "; @@ -1563,7 +1573,7 @@ SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GVNode->getGlobal(), TLI.getPointerTy()); SDValue Ops[] = { Tmp1, Tmp2, Chain }; - return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, + return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl, MVT::Other, Ops, 3); break; } From snaroff at apple.com Tue Feb 3 15:48:37 2009 From: snaroff at apple.com (steve naroff) Date: Tue, 3 Feb 2009 16:48:37 -0500 Subject: [llvm-commits] [llvm] r63539 - /llvm/trunk/win32/config.h In-Reply-To: <65dd6f7d-19a1-4852-8ef1-e780bf322a26@n33g2000pri.googlegroups.com> References: <200902021922.n12JM3W7015508@zion.cs.uiuc.edu> <49ea1292-789b-48bf-9c6c-95fb73d71511@w1g2000prm.googlegroups.com> <16e5fdf90902021641h7dfd7779v736716e6e5f119b@mail.gmail.com> <65dd6f7d-19a1-4852-8ef1-e780bf322a26@n33g2000pri.googlegroups.com> Message-ID: On Feb 3, 2009, at 4:41 PM, Gabor Greif wrote: > On 3 fev, 01:41, Bill Wendling wrote: >> On Mon, Feb 2, 2009 at 12:39 PM, Gabor Greif >> wrote: >>> On 2 Feb., 20:22, Steve Naroff wrote: >>>> Author: snaroff >>>> Date: Mon Feb 2 13:22:02 2009 >>>> New Revision: 63539 >> >>>> URL:http://llvm.org/viewvc/llvm-project?rev=63539&view=rev >>>> Log: >>>> Update hand-crafted VC++ build. >>>> - Add PACKAGE_STRING definition to Windows config.h. >> >>>> Modified: >>>> llvm/trunk/win32/config.h >> >>>> Modified: llvm/trunk/win32/config.h >>>> URL:http://llvm.org/viewvc/llvm-project/llvm/trunk/win32/config.h?rev=635 >>>> ... >> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> ================================================================= >>>> === >>>> --- llvm/trunk/win32/config.h (original) >>>> +++ llvm/trunk/win32/config.h Mon Feb 2 13:22:02 2009 >>>> @@ -3,6 +3,7 @@ >> >>>> #define PACKAGE_NAME "LLVM (win32 vc8.0)" >>>> #define PACKAGE_VERSION 2.4 >> >>> Bill, this ^^^^^^ does not seem right. >> >> Bill? :-) > > Ehrm, sorry Bill, that should be Steve... :-) > Gabor, I assume you are talking about the #define for PACKAGE_STRING? I added it just to make the Windows work. If the #define is incorrect, please let me know why (and I will be happy to fix it). Thanks, snaroff > Cheers, > > Gabor > >> >> -bw >> _______________________________________________ >> llvm-commits mailing list >> llvm-comm... at cs.uiuc.eduhttp://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From ggreif at gmail.com Tue Feb 3 15:59:17 2009 From: ggreif at gmail.com (Gabor Greif) Date: Tue, 3 Feb 2009 13:59:17 -0800 (PST) Subject: [llvm-commits] [llvm] r63539 - /llvm/trunk/win32/config.h In-Reply-To: References: <200902021922.n12JM3W7015508@zion.cs.uiuc.edu> <49ea1292-789b-48bf-9c6c-95fb73d71511@w1g2000prm.googlegroups.com> <16e5fdf90902021641h7dfd7779v736716e6e5f119b@mail.gmail.com> <65dd6f7d-19a1-4852-8ef1-e780bf322a26@n33g2000pri.googlegroups.com> Message-ID: No, PACKAGE_STRING looks awesome, but I have my doubts about PACKAGE_VERSION (the line above your change). Cheers, Gabor On 3 fev, 22:48, steve naroff wrote: > On Feb 3, 2009, at 4:41 PM, Gabor Greif wrote: > > > > > On 3 fev, 01:41, Bill Wendling wrote: > >> On Mon, Feb 2, 2009 at 12:39 PM, Gabor Greif ? > >> wrote: > >>> On 2 Feb., 20:22, Steve Naroff wrote: > >>>> Author: snaroff > >>>> Date: Mon Feb ?2 13:22:02 2009 > >>>> New Revision: 63539 > > >>>> URL:http://llvm.org/viewvc/llvm-project?rev=63539&view=rev > >>>> Log: > >>>> Update hand-crafted VC++ build. > >>>> - Add PACKAGE_STRING definition to Windows config.h. > > >>>> Modified: > >>>> ? ? llvm/trunk/win32/config.h > > >>>> Modified: llvm/trunk/win32/config.h > >>>> URL:http://llvm.org/viewvc/llvm-project/llvm/trunk/win32/config.h?rev=635 > >>>> ... > > >>>> = > >>>> = > >>>> = > >>>> = > >>>> = > >>>> = > >>>> = > >>>> = > >>>> = > >>>> = > >>>> ================================================================= ? > >>>> === > >>>> --- llvm/trunk/win32/config.h (original) > >>>> +++ llvm/trunk/win32/config.h Mon Feb ?2 13:22:02 2009 > >>>> @@ -3,6 +3,7 @@ > > >>>> ?#define PACKAGE_NAME "LLVM (win32 vc8.0)" > >>>> ?#define PACKAGE_VERSION 2.4 > > >>> Bill, this ^^^^^^ does not seem right. > > >> Bill? :-) > > > Ehrm, sorry Bill, that should be Steve... :-) > > Gabor, > > I assume you are talking about ?the #define for PACKAGE_STRING? > > I added it just to make the Windows work. If the #define is incorrect, ? > please let me know why (and I will be happy to fix it). > > Thanks, > > snaroff > > > Cheers, > > > ? ?Gabor > > >> -bw > >> _______________________________________________ > >> llvm-commits mailing list > >> llvm-comm... at cs.uiuc.eduhttp://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-comm... at cs.uiuc.eduhttp://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Tue Feb 3 16:04:27 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 03 Feb 2009 22:04:27 -0000 Subject: [llvm-commits] [llvm] r63670 - /llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Message-ID: <200902032204.n13M4R0U018443@zion.cs.uiuc.edu> Author: dpatel Date: Tue Feb 3 16:04:27 2009 New Revision: 63670 URL: http://llvm.org/viewvc/llvm-project?rev=63670&view=rev Log: If "optimize for size" attribute is set then block non-trivial loop unswitches but allow trivial loop unswitches. Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=63670&r1=63669&r2=63670&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Tue Feb 3 16:04:27 2009 @@ -430,9 +430,6 @@ initLoopData(); Function *F = loopHeader->getParent(); - // Do not unswitch if the function is optimized for size. - if (!F->isDeclaration() && F->hasFnAttr(Attribute::OptimizeForSize)) - return false; // Check to see if it would be profitable to unswitch current loop. unsigned Cost = getLoopUnswitchCost(LoopCond); @@ -440,6 +437,8 @@ // Do not do non-trivial unswitch while optimizing for size. if (Cost && OptimizeForSize) return false; + if (Cost && !F->isDeclaration() && F->hasFnAttr(Attribute::OptimizeForSize)) + return false; if (Cost > Threshold) { // FIXME: this should estimate growth by the amount of code shared by the From dpatel at apple.com Tue Feb 3 16:12:03 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 03 Feb 2009 22:12:03 -0000 Subject: [llvm-commits] [llvm] r63671 - in /llvm/trunk: lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/two-entry-phi-return.dbg.ll Message-ID: <200902032212.n13MC3u1018698@zion.cs.uiuc.edu> Author: dpatel Date: Tue Feb 3 16:12:02 2009 New Revision: 63671 URL: http://llvm.org/viewvc/llvm-project?rev=63671&view=rev Log: Do not let dbg intrinsic block folding of two entry phi node. Added: llvm/trunk/test/Transforms/SimplifyCFG/two-entry-phi-return.dbg.ll Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=63671&r1=63670&r2=63671&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Feb 3 16:12:02 2009 @@ -15,6 +15,7 @@ #include "llvm/Transforms/Utils/Local.h" #include "llvm/Constants.h" #include "llvm/Instructions.h" +#include "llvm/IntrinsicInst.h" #include "llvm/Type.h" #include "llvm/DerivedTypes.h" #include "llvm/Support/CFG.h" @@ -1262,7 +1263,7 @@ DomBlock = *pred_begin(Pred); for (BasicBlock::iterator I = Pred->begin(); !isa(I); ++I) - if (!AggressiveInsts.count(I)) { + if (!AggressiveInsts.count(I) && !isa(I)) { // This is not an aggressive instruction that we can promote. // Because of this, we won't be able to get rid of the control // flow, so the xform is not worth it. @@ -1276,7 +1277,7 @@ DomBlock = *pred_begin(Pred); for (BasicBlock::iterator I = Pred->begin(); !isa(I); ++I) - if (!AggressiveInsts.count(I)) { + if (!AggressiveInsts.count(I) && !isa(I)) { // This is not an aggressive instruction that we can promote. // Because of this, we won't be able to get rid of the control // flow, so the xform is not worth it. Added: llvm/trunk/test/Transforms/SimplifyCFG/two-entry-phi-return.dbg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/two-entry-phi-return.dbg.ll?rev=63671&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/two-entry-phi-return.dbg.ll (added) +++ llvm/trunk/test/Transforms/SimplifyCFG/two-entry-phi-return.dbg.ll Tue Feb 3 16:12:02 2009 @@ -0,0 +1,28 @@ +; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | not grep br + + %llvm.dbg.anchor.type = type { i32, i32 } + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } + + at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata" ; + + at .str = internal constant [4 x i8] c"a.c\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at .str1 = internal constant [6 x i8] c"/tmp/\00", section "llvm.metadata" ; <[6 x i8]*> [#uses=1] + at .str2 = internal constant [55 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build 00)\00", section "llvm.metadata" ; <[55 x i8]*> [#uses=1] + at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([6 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([55 x i8]* @.str2, i32 0, i32 0), i1 true, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] + +declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind + +define i1 @qux(i8* %m, i8* %n, i8* %o, i8* %p) nounwind { +entry: + %tmp7 = icmp eq i8* %m, %n + br i1 %tmp7, label %bb, label %UnifiedReturnBlock + +bb: +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %tmp15 = icmp eq i8* %o, %p + br label %UnifiedReturnBlock + +UnifiedReturnBlock: + %result = phi i1 [ 0, %entry ], [ %tmp15, %bb ] + ret i1 %result +} From dalej at apple.com Tue Feb 3 16:26:10 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 03 Feb 2009 22:26:10 -0000 Subject: [llvm-commits] [llvm] r63673 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/X86/X86ISelLowering.cpp Message-ID: <200902032226.n13MQA6S019291@zion.cs.uiuc.edu> Author: johannes Date: Tue Feb 3 16:26:09 2009 New Revision: 63673 URL: http://llvm.org/viewvc/llvm-project?rev=63673&view=rev Log: Add some DL propagation to places that didn't have it yet. More coming. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63673&r1=63672&r2=63673&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Feb 3 16:26:09 2009 @@ -325,6 +325,10 @@ return getNode(ISD::CopyToReg, MVT::Other, Chain, getRegister(Reg, N.getValueType()), N); } + SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) { + return getNode(ISD::CopyToReg, dl, MVT::Other, Chain, + getRegister(Reg, N.getValueType()), N); + } // This version of the getCopyToReg method takes an extra operand, which // indicates that there is potentially an incoming flag value (if Flag is not @@ -335,6 +339,12 @@ SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag }; return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.getNode() ? 4 : 3); } + SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N, + SDValue Flag) { + const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag); + SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag }; + return getNode(ISD::CopyToReg, dl, VTs, 2, Ops, Flag.getNode() ? 4 : 3); + } // Similar to last getCopyToReg() except parameter Reg is a SDValue SDValue getCopyToReg(SDValue Chain, SDValue Reg, SDValue N, @@ -343,12 +353,23 @@ SDValue Ops[] = { Chain, Reg, N, Flag }; return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.getNode() ? 4 : 3); } + SDValue getCopyToReg(SDValue Chain, DebugLoc dl, SDValue Reg, SDValue N, + SDValue Flag) { + const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag); + SDValue Ops[] = { Chain, Reg, N, Flag }; + return getNode(ISD::CopyToReg, dl, VTs, 2, Ops, Flag.getNode() ? 4 : 3); + } SDValue getCopyFromReg(SDValue Chain, unsigned Reg, MVT VT) { const MVT *VTs = getNodeValueTypes(VT, MVT::Other); SDValue Ops[] = { Chain, getRegister(Reg, VT) }; return getNode(ISD::CopyFromReg, VTs, 2, Ops, 2); } + SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, MVT VT) { + const MVT *VTs = getNodeValueTypes(VT, MVT::Other); + SDValue Ops[] = { Chain, getRegister(Reg, VT) }; + return getNode(ISD::CopyFromReg, dl, VTs, 2, Ops, 2); + } // This version of the getCopyFromReg method takes an extra operand, which // indicates that there is potentially an incoming flag value (if Flag is not @@ -359,6 +380,12 @@ SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag }; return getNode(ISD::CopyFromReg, VTs, 3, Ops, Flag.getNode() ? 3 : 2); } + SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, MVT VT, + SDValue Flag) { + const MVT *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag); + SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag }; + return getNode(ISD::CopyFromReg, dl, VTs, 3, Ops, Flag.getNode() ? 3 : 2); + } SDValue getCondCode(ISD::CondCode Cond); @@ -366,6 +393,9 @@ /// disappear in the future and most targets don't support it. SDValue getConvertRndSat(MVT VT, SDValue Val, SDValue DTy, SDValue STy, SDValue Rnd, SDValue Sat, ISD::CvtCode Code); + SDValue getConvertRndSat(MVT VT, DebugLoc dl, SDValue Val, SDValue DTy, + SDValue STy, + SDValue Rnd, SDValue Sat, ISD::CvtCode Code); /// getZeroExtendInReg - Return the expression required to zero extend the Op /// value assuming it was the smaller SrcTy value. @@ -466,15 +496,35 @@ SDValue getMemcpy(SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool AlwaysInline, const Value *DstSV, uint64_t DstSVOff, + const Value *SrcSV, uint64_t SrcSVOff) { + return getMemcpy(Chain, DebugLoc::getUnknownLoc(), Dst, Src, Size, Align, + AlwaysInline, DstSV, DstSVOff, SrcSV, SrcSVOff); + } + SDValue getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src, + SDValue Size, unsigned Align, bool AlwaysInline, + const Value *DstSV, uint64_t DstSVOff, const Value *SrcSV, uint64_t SrcSVOff); SDValue getMemmove(SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, const Value *DstSV, uint64_t DstOSVff, + const Value *SrcSV, uint64_t SrcSVOff) { + return getMemmove(Chain, DebugLoc::getUnknownLoc(), Dst, Src, Size, Align, + DstSV, DstOSVff, SrcSV, SrcSVOff); + } + SDValue getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src, + SDValue Size, unsigned Align, + const Value *DstSV, uint64_t DstOSVff, const Value *SrcSV, uint64_t SrcSVOff); SDValue getMemset(SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, + const Value *DstSV, uint64_t DstSVOff) { + return getMemset(Chain, DebugLoc::getUnknownLoc(), Dst, Src, Size, Align, + DstSV, DstSVOff); + } + SDValue getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src, + SDValue Size, unsigned Align, const Value *DstSV, uint64_t DstSVOff); /// getSetCC - Helper function to make it easier to build SetCC's if you just @@ -521,6 +571,8 @@ /// and a source value as input. SDValue getVAArg(MVT VT, SDValue Chain, SDValue Ptr, SDValue SV); + SDValue getVAArg(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, + SDValue SV); /// getAtomic - Gets a node for an atomic op, produces result and chain and /// takes 3 operands Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=63673&r1=63672&r2=63673&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Tue Feb 3 16:26:09 2009 @@ -1101,7 +1101,7 @@ /// for another call). If the target chooses to decline an AlwaysInline /// request here, legalize will resort to using simple loads and stores. virtual SDValue - EmitTargetCodeForMemcpy(SelectionDAG &DAG, + EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, @@ -1118,7 +1118,7 @@ /// SDValue if the target declines to use custom code and a different /// lowering strategy should be used. virtual SDValue - EmitTargetCodeForMemmove(SelectionDAG &DAG, + EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, @@ -1134,7 +1134,7 @@ /// SDValue if the target declines to use custom code and a different /// lowering strategy should be used. virtual SDValue - EmitTargetCodeForMemset(SelectionDAG &DAG, + EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63673&r1=63672&r2=63673&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Feb 3 16:26:09 2009 @@ -2927,7 +2927,8 @@ /// getMemsetValue - Vectorized representation of the memset value /// operand. -static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG) { +static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG, + DebugLoc dl) { unsigned NumBits = VT.isVector() ? VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); if (ConstantSDNode *C = dyn_cast(Value)) { @@ -2943,11 +2944,11 @@ } const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); + Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value); unsigned Shift = 8; for (unsigned i = NumBits; i > 8; i >>= 1) { - Value = DAG.getNode(ISD::OR, VT, - DAG.getNode(ISD::SHL, VT, Value, + Value = DAG.getNode(ISD::OR, dl, VT, + DAG.getNode(ISD::SHL, dl, VT, Value, DAG.getConstant(Shift, TLI.getShiftAmountTy())), Value); @@ -2960,7 +2961,7 @@ /// getMemsetStringVal - Similar to getMemsetValue. Except this is only /// used when a memcpy is turned into a memset when the source is a constant /// string ptr. -static SDValue getMemsetStringVal(MVT VT, SelectionDAG &DAG, +static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG, const TargetLowering &TLI, std::string &Str, unsigned Offset) { // Handle vector with all elements zero. @@ -2969,7 +2970,7 @@ return DAG.getConstant(0, VT); unsigned NumElts = VT.getVectorNumElements(); MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; - return DAG.getNode(ISD::BIT_CONVERT, VT, + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); } @@ -3104,7 +3105,7 @@ return true; } -static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, +static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, unsigned Align, bool AlwaysInline, @@ -3141,15 +3142,15 @@ // We also handle store a vector with all zero's. // FIXME: Handle other cases where store of vector immediate is done in // a single instruction. - Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); - Store = DAG.getStore(Chain, Value, + Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff); + Store = DAG.getStore(Chain, dl, Value, getMemBasePlusOffset(Dst, DstOff, DAG), DstSV, DstSVOff + DstOff, false, DstAlign); } else { - Value = DAG.getLoad(VT, Chain, + Value = DAG.getLoad(VT, dl, Chain, getMemBasePlusOffset(Src, SrcOff, DAG), SrcSV, SrcSVOff + SrcOff, false, Align); - Store = DAG.getStore(Chain, Value, + Store = DAG.getStore(Chain, dl, Value, getMemBasePlusOffset(Dst, DstOff, DAG), DstSV, DstSVOff + DstOff, false, DstAlign); } @@ -3158,11 +3159,11 @@ DstOff += VTSize; } - return DAG.getNode(ISD::TokenFactor, MVT::Other, + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &OutChains[0], OutChains.size()); } -static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, +static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, unsigned Align, bool AlwaysInline, @@ -3194,14 +3195,14 @@ unsigned VTSize = VT.getSizeInBits() / 8; SDValue Value, Store; - Value = DAG.getLoad(VT, Chain, + Value = DAG.getLoad(VT, dl, Chain, getMemBasePlusOffset(Src, SrcOff, DAG), SrcSV, SrcSVOff + SrcOff, false, Align); LoadValues.push_back(Value); LoadChains.push_back(Value.getValue(1)); SrcOff += VTSize; } - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LoadChains[0], LoadChains.size()); OutChains.clear(); for (unsigned i = 0; i < NumMemOps; i++) { @@ -3209,18 +3210,18 @@ unsigned VTSize = VT.getSizeInBits() / 8; SDValue Value, Store; - Store = DAG.getStore(Chain, LoadValues[i], + Store = DAG.getStore(Chain, dl, LoadValues[i], getMemBasePlusOffset(Dst, DstOff, DAG), DstSV, DstSVOff + DstOff, false, DstAlign); OutChains.push_back(Store); DstOff += VTSize; } - return DAG.getNode(ISD::TokenFactor, MVT::Other, + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &OutChains[0], OutChains.size()); } -static SDValue getMemsetStores(SelectionDAG &DAG, +static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, unsigned Align, @@ -3243,19 +3244,19 @@ for (unsigned i = 0; i < NumMemOps; i++) { MVT VT = MemOps[i]; unsigned VTSize = VT.getSizeInBits() / 8; - SDValue Value = getMemsetValue(Src, VT, DAG); - SDValue Store = DAG.getStore(Chain, Value, + SDValue Value = getMemsetValue(Src, VT, DAG, dl); + SDValue Store = DAG.getStore(Chain, dl, Value, getMemBasePlusOffset(Dst, DstOff, DAG), DstSV, DstSVOff + DstOff); OutChains.push_back(Store); DstOff += VTSize; } - return DAG.getNode(ISD::TokenFactor, MVT::Other, + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &OutChains[0], OutChains.size()); } -SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst, +SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool AlwaysInline, const Value *DstSV, uint64_t DstSVOff, @@ -3270,7 +3271,7 @@ return Chain; SDValue Result = - getMemcpyLoadsAndStores(*this, Chain, Dst, Src, + getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); if (Result.getNode()) @@ -3280,7 +3281,7 @@ // Then check to see if we should lower the memcpy with target-specific // code. If the target chooses to do this, this is the next best. SDValue Result = - TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align, + TLI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align, AlwaysInline, DstSV, DstSVOff, SrcSV, SrcSVOff); if (Result.getNode()) @@ -3290,7 +3291,7 @@ // use a (potentially long) sequence of loads and stores. if (AlwaysInline) { assert(ConstantSize && "AlwaysInline requires a constant size!"); - return getMemcpyLoadsAndStores(*this, Chain, Dst, Src, + return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), Align, true, DstSV, DstSVOff, SrcSV, SrcSVOff); } @@ -3307,11 +3308,11 @@ TLI.LowerCallTo(Chain, Type::VoidTy, false, false, false, false, CallingConv::C, false, getExternalSymbol("memcpy", TLI.getPointerTy()), - Args, *this, DebugLoc::getUnknownLoc()); + Args, *this, dl); return CallResult.second; } -SDValue SelectionDAG::getMemmove(SDValue Chain, SDValue Dst, +SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, const Value *DstSV, uint64_t DstSVOff, @@ -3326,7 +3327,7 @@ return Chain; SDValue Result = - getMemmoveLoadsAndStores(*this, Chain, Dst, Src, + getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); if (Result.getNode()) @@ -3336,7 +3337,7 @@ // Then check to see if we should lower the memmove with target-specific // code. If the target chooses to do this, this is the next best. SDValue Result = - TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align, + TLI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align, DstSV, DstSVOff, SrcSV, SrcSVOff); if (Result.getNode()) return Result; @@ -3353,11 +3354,11 @@ TLI.LowerCallTo(Chain, Type::VoidTy, false, false, false, false, CallingConv::C, false, getExternalSymbol("memmove", TLI.getPointerTy()), - Args, *this, DebugLoc::getUnknownLoc()); + Args, *this, dl); return CallResult.second; } -SDValue SelectionDAG::getMemset(SDValue Chain, SDValue Dst, +SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, const Value *DstSV, uint64_t DstSVOff) { @@ -3371,7 +3372,7 @@ return Chain; SDValue Result = - getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getZExtValue(), + getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), Align, DstSV, DstSVOff); if (Result.getNode()) return Result; @@ -3380,7 +3381,7 @@ // Then check to see if we should lower the memset with target-specific // code. If the target chooses to do this, this is the next best. SDValue Result = - TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align, + TLI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align, DstSV, DstSVOff); if (Result.getNode()) return Result; @@ -3393,9 +3394,9 @@ Args.push_back(Entry); // Extend or truncate the argument to be an i32 value for the call. if (Src.getValueType().bitsGT(MVT::i32)) - Src = getNode(ISD::TRUNCATE, MVT::i32, Src); + Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src); else - Src = getNode(ISD::ZERO_EXTEND, MVT::i32, Src); + Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; Args.push_back(Entry); Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; @@ -3405,7 +3406,7 @@ TLI.LowerCallTo(Chain, Type::VoidTy, false, false, false, false, CallingConv::C, false, getExternalSymbol("memset", TLI.getPointerTy()), - Args, *this, DebugLoc::getUnknownLoc()); + Args, *this, dl); return CallResult.second; } @@ -4043,6 +4044,13 @@ return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3); } +SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl, + SDValue Chain, SDValue Ptr, + SDValue SV) { + SDValue Ops[] = { Chain, Ptr, SV }; + return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3); +} + SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, const SDUse *Ops, unsigned NumOps) { return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, Ops, NumOps); Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=63673&r1=63672&r2=63673&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Feb 3 16:26:09 2009 @@ -1242,7 +1242,7 @@ } SDValue -ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, +ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, @@ -1279,24 +1279,24 @@ while (EmittedNumMemOps < NumMemOps) { for (i = 0; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { - Loads[i] = DAG.getLoad(VT, Chain, - DAG.getNode(ISD::ADD, MVT::i32, Src, + Loads[i] = DAG.getLoad(VT, dl, Chain, + DAG.getNode(ISD::ADD, dl, MVT::i32, Src, DAG.getConstant(SrcOff, MVT::i32)), SrcSV, SrcSVOff + SrcOff); TFOps[i] = Loads[i].getValue(1); SrcOff += VTSize; } - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); for (i = 0; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { - TFOps[i] = DAG.getStore(Chain, Loads[i], - DAG.getNode(ISD::ADD, MVT::i32, Dst, + TFOps[i] = DAG.getStore(Chain, dl, Loads[i], + DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, DAG.getConstant(DstOff, MVT::i32)), DstSV, DstSVOff + DstOff); DstOff += VTSize; } - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); EmittedNumMemOps += i; } @@ -1316,8 +1316,8 @@ VTSize = 1; } - Loads[i] = DAG.getLoad(VT, Chain, - DAG.getNode(ISD::ADD, MVT::i32, Src, + Loads[i] = DAG.getLoad(VT, dl, Chain, + DAG.getNode(ISD::ADD, dl, MVT::i32, Src, DAG.getConstant(SrcOff, MVT::i32)), SrcSV, SrcSVOff + SrcOff); TFOps[i] = Loads[i].getValue(1); @@ -1325,7 +1325,7 @@ SrcOff += VTSize; BytesLeft -= VTSize; } - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); i = 0; BytesLeft = BytesLeftSave; @@ -1338,15 +1338,15 @@ VTSize = 1; } - TFOps[i] = DAG.getStore(Chain, Loads[i], - DAG.getNode(ISD::ADD, MVT::i32, Dst, + TFOps[i] = DAG.getStore(Chain, dl, Loads[i], + DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, DAG.getConstant(DstOff, MVT::i32)), DstSV, DstSVOff + DstOff); ++i; DstOff += VTSize; BytesLeft -= VTSize; } - return DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); } static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) { Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=63673&r1=63672&r2=63673&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Tue Feb 3 16:26:09 2009 @@ -149,7 +149,7 @@ SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG); SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG); - SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, + SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=63673&r1=63672&r2=63673&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Feb 3 16:26:09 2009 @@ -5610,7 +5610,7 @@ } SDValue -X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, +X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, @@ -5641,12 +5641,10 @@ Args.push_back(Entry); Entry.Node = Size; Args.push_back(Entry); - // FIXME provide DebugLoc info std::pair CallResult = LowerCallTo(Chain, Type::VoidTy, false, false, false, false, CallingConv::C, false, - DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, - DebugLoc::getUnknownLoc()); + DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl); return CallResult.second; } @@ -5696,20 +5694,22 @@ BytesLeft = SizeVal % UBytes; } - Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT), + Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT), InFlag); InFlag = Chain.getValue(1); } else { AVT = MVT::i8; Count = DAG.getIntPtrConstant(SizeVal); - Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag); + Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); InFlag = Chain.getValue(1); } - Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, + Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : + X86::ECX, Count, InFlag); InFlag = Chain.getValue(1); - Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI, + Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : + X86::EDI, Dst, InFlag); InFlag = Chain.getValue(1); @@ -5718,15 +5718,16 @@ Ops.push_back(Chain); Ops.push_back(DAG.getValueType(AVT)); Ops.push_back(InFlag); - Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size()); + Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size()); if (TwoRepStos) { InFlag = Chain.getValue(1); Count = Size; MVT CVT = Count.getValueType(); - SDValue Left = DAG.getNode(ISD::AND, CVT, Count, + SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count, DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); - Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX, + Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : + X86::ECX, Left, InFlag); InFlag = Chain.getValue(1); Tys = DAG.getVTList(MVT::Other, MVT::Flag); @@ -5734,15 +5735,15 @@ Ops.push_back(Chain); Ops.push_back(DAG.getValueType(MVT::i8)); Ops.push_back(InFlag); - Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size()); + Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size()); } else if (BytesLeft) { // Handle the last 1 - 7 bytes. unsigned Offset = SizeVal - BytesLeft; MVT AddrVT = Dst.getValueType(); MVT SizeVT = Size.getValueType(); - Chain = DAG.getMemset(Chain, - DAG.getNode(ISD::ADD, AddrVT, Dst, + Chain = DAG.getMemset(Chain, dl, + DAG.getNode(ISD::ADD, dl, AddrVT, Dst, DAG.getConstant(Offset, AddrVT)), Src, DAG.getConstant(BytesLeft, SizeVT), @@ -5754,7 +5755,7 @@ } SDValue -X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, +X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool AlwaysInline, @@ -5784,13 +5785,16 @@ unsigned BytesLeft = SizeVal % UBytes; SDValue InFlag(0, 0); - Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, + Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : + X86::ECX, Count, InFlag); InFlag = Chain.getValue(1); - Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI, + Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : + X86::EDI, Dst, InFlag); InFlag = Chain.getValue(1); - Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI, + Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI : + X86::ESI, Src, InFlag); InFlag = Chain.getValue(1); @@ -5799,7 +5803,7 @@ Ops.push_back(Chain); Ops.push_back(DAG.getValueType(AVT)); Ops.push_back(InFlag); - SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size()); + SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size()); SmallVector Results; Results.push_back(RepMovs); @@ -5809,10 +5813,10 @@ MVT DstVT = Dst.getValueType(); MVT SrcVT = Src.getValueType(); MVT SizeVT = Size.getValueType(); - Results.push_back(DAG.getMemcpy(Chain, - DAG.getNode(ISD::ADD, DstVT, Dst, + Results.push_back(DAG.getMemcpy(Chain, dl, + DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, DstVT)), - DAG.getNode(ISD::ADD, SrcVT, Src, + DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, SrcVT)), DAG.getConstant(BytesLeft, SizeVT), Align, AlwaysInline, @@ -5820,7 +5824,8 @@ SrcSV, SrcSVOff + Offset)); } - return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size()); + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + &Results[0], Results.size()); } SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { From dalej at apple.com Tue Feb 3 16:26:34 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 03 Feb 2009 22:26:34 -0000 Subject: [llvm-commits] [llvm] r63674 - /llvm/trunk/lib/Target/X86/X86ISelLowering.h Message-ID: <200902032226.n13MQYKS019313@zion.cs.uiuc.edu> Author: johannes Date: Tue Feb 3 16:26:34 2009 New Revision: 63674 URL: http://llvm.org/viewvc/llvm-project?rev=63674&view=rev Log: Need this file too. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=63674&r1=63673&r2=63674&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Feb 3 16:26:34 2009 @@ -612,12 +612,12 @@ void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl &Results, SelectionDAG &DAG, unsigned NewOp); - SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, + SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, const Value *DstSV, uint64_t DstSVOff); - SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, + SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, From isanbard at gmail.com Tue Feb 3 16:49:16 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 03 Feb 2009 22:49:16 -0000 Subject: [llvm-commits] [llvm] r63675 - /llvm/trunk/include/llvm/CodeGen/DebugLoc.h Message-ID: <200902032249.n13MnGK3019987@zion.cs.uiuc.edu> Author: void Date: Tue Feb 3 16:49:14 2009 New Revision: 63675 URL: http://llvm.org/viewvc/llvm-project?rev=63675&view=rev Log: Add getter for the index. Modified: llvm/trunk/include/llvm/CodeGen/DebugLoc.h Modified: llvm/trunk/include/llvm/CodeGen/DebugLoc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DebugLoc.h?rev=63675&r1=63674&r2=63675&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/DebugLoc.h (original) +++ llvm/trunk/include/llvm/CodeGen/DebugLoc.h Tue Feb 3 16:49:14 2009 @@ -40,6 +40,8 @@ static DebugLoc getUnknownLoc() { DebugLoc L; L.Idx = 0; return L; } static DebugLoc get(unsigned idx) { DebugLoc L; L.Idx = idx; return L; } + unsigned getIndex() const { return Idx; } + /// isInvalid - Return true if the DebugLoc is invalid. bool isInvalid() const { return Idx == ~0U; } From isanbard at gmail.com Tue Feb 3 16:49:58 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 03 Feb 2009 22:49:58 -0000 Subject: [llvm-commits] [llvm] r63676 - in /llvm/trunk: include/llvm/CodeGen/MachineFunction.h lib/CodeGen/MachineFunction.cpp Message-ID: <200902032249.n13Mnwq4020026@zion.cs.uiuc.edu> Author: void Date: Tue Feb 3 16:49:58 2009 New Revision: 63676 URL: http://llvm.org/viewvc/llvm-project?rev=63676&view=rev Log: Add getDebugLocTuple to retrieve the DebugLocTuple for a given DebugLoc object. Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h llvm/trunk/lib/CodeGen/MachineFunction.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=63676&r1=63675&r2=63676&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Tue Feb 3 16:49:58 2009 @@ -313,9 +313,12 @@ // /// getOrCreateDebugLocID - Look up the DebugLocTuple index with the given - /// source file, line, and column. If none currently exists, create add a new - /// new DebugLocTuple and insert it into the DebugIdMap. + /// source file, line, and column. If none currently exists, create a new + /// DebugLocTuple, and insert it into the DebugIdMap. unsigned getOrCreateDebugLocID(unsigned Src, unsigned Line, unsigned Col); + + /// getDebugLocTuple - Get the DebugLocTuple for a given DebugLoc object. + const DebugLocTuple &getDebugLocTuple(DebugLoc DL); }; //===--------------------------------------------------------------------===// Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=63676&r1=63675&r2=63676&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Feb 3 16:49:58 2009 @@ -380,11 +380,11 @@ } /// getOrCreateDebugLocID - Look up the DebugLocTuple index with the given -/// source file, line, and column. If none currently exists, create add a new -/// new DebugLocTuple and insert it into the DebugIdMap. +/// source file, line, and column. If none currently exists, create a new +/// DebugLocTuple, and insert it into the DebugIdMap. unsigned MachineFunction::getOrCreateDebugLocID(unsigned Src, unsigned Line, unsigned Col) { - struct DebugLocTuple Tuple(Src, Line, Col); + DebugLocTuple Tuple(Src, Line, Col); DenseMap::iterator II = DebugLocInfo.DebugIdMap.find(Tuple); if (II != DebugLocInfo.DebugIdMap.end()) @@ -396,6 +396,14 @@ return Id; } +/// getDebugLocTuple - Get the DebugLocTuple for a given DebugLoc object. +const DebugLocTuple &MachineFunction::getDebugLocTuple(DebugLoc DL) { + unsigned Idx; + assert(Idx < DebugLocInfo.DebugLocations.size() && + "Invalid index into debug locations!"); + return DebugLocInfo.DebugLocations[Idx]; +} + //===----------------------------------------------------------------------===// // MachineFrameInfo implementation //===----------------------------------------------------------------------===// From isanbard at gmail.com Tue Feb 3 16:55:54 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 03 Feb 2009 22:55:54 -0000 Subject: [llvm-commits] [llvm] r63677 - /llvm/trunk/lib/CodeGen/MachineFunction.cpp Message-ID: <200902032255.n13Mtsdt020225@zion.cs.uiuc.edu> Author: void Date: Tue Feb 3 16:55:54 2009 New Revision: 63677 URL: http://llvm.org/viewvc/llvm-project?rev=63677&view=rev Log: Erm. Would be nice to initialize this variable. . . Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=63677&r1=63676&r2=63677&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Feb 3 16:55:54 2009 @@ -398,7 +398,7 @@ /// getDebugLocTuple - Get the DebugLocTuple for a given DebugLoc object. const DebugLocTuple &MachineFunction::getDebugLocTuple(DebugLoc DL) { - unsigned Idx; + unsigned Idx = DL.getIndex(); assert(Idx < DebugLocInfo.DebugLocations.size() && "Invalid index into debug locations!"); return DebugLocInfo.DebugLocations[Idx]; From dalej at apple.com Tue Feb 3 17:04:43 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 03 Feb 2009 23:04:43 -0000 Subject: [llvm-commits] [llvm] r63680 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Message-ID: <200902032304.n13N4iuI020510@zion.cs.uiuc.edu> Author: johannes Date: Tue Feb 3 17:04:43 2009 New Revision: 63680 URL: http://llvm.org/viewvc/llvm-project?rev=63680&view=rev Log: DebugLoc propagation; adjustment to things omitted from SelectionDagBuild. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=63680&r1=63679&r2=63680&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Tue Feb 3 17:04:43 2009 @@ -2153,6 +2153,12 @@ : SDNode(ISD::CONVERT_RNDSAT, getSDVTList(VT), Ops, NumOps), CvtCode(Code) { assert(NumOps == 5 && "wrong number of operations"); } + explicit CvtRndSatSDNode(MVT VT, DebugLoc dl, const SDValue *Ops, + unsigned NumOps, ISD::CvtCode Code) + : SDNode(ISD::CONVERT_RNDSAT, dl, getSDVTList(VT), Ops, NumOps), + CvtCode(Code) { + assert(NumOps == 5 && "wrong number of operations"); + } public: ISD::CvtCode getCvtCode() const { return CvtCode; } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63680&r1=63679&r2=63680&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Feb 3 17:04:43 2009 @@ -1175,7 +1175,8 @@ return SDValue(CondCodeNodes[Cond], 0); } -SDValue SelectionDAG::getConvertRndSat(MVT VT, SDValue Val, SDValue DTy, +SDValue SelectionDAG::getConvertRndSat(MVT VT, + SDValue Val, SDValue DTy, SDValue STy, SDValue Rnd, SDValue Sat, ISD::CvtCode Code) { // If the src and dest types are the same, no conversion is necessary. @@ -1194,6 +1195,26 @@ return SDValue(N, 0); } +SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl, + SDValue Val, SDValue DTy, + SDValue STy, SDValue Rnd, SDValue Sat, + ISD::CvtCode Code) { + // If the src and dest types are the same, no conversion is necessary. + if (DTy == STy) + return Val; + + FoldingSetNodeID ID; + void* IP = 0; + if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) + return SDValue(E, 0); + CvtRndSatSDNode *N = NodeAllocator.Allocate(); + SDValue Ops[] = { Val, DTy, STy, Rnd, Sat }; + new (N) CvtRndSatSDNode(VT, dl, Ops, 5, Code); + CSEMap.InsertNode(N, IP); + AllNodes.push_back(N); + return SDValue(N, 0); +} + SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63680&r1=63679&r2=63680&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Tue Feb 3 17:04:43 2009 @@ -1395,7 +1395,8 @@ // Emit the code for the jump table assert(JT.Reg != -1U && "Should lower JT Header first!"); MVT PTy = TLI.getPointerTy(); - SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy); + SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), + JT.Reg, PTy); SDValue Table = DAG.getJumpTable(JT.JTI, PTy); DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(), MVT::Other, Index.getValue(1), @@ -1427,7 +1428,8 @@ TLI.getPointerTy(), SUB); unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); - SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp); + SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), + JumpTableReg, SwitchOp); JT.Reg = JumpTableReg; // Emit the range check for the jump table, and branch to the default block @@ -1478,7 +1480,8 @@ TLI.getPointerTy(), SUB); B.Reg = FuncInfo.MakeReg(TLI.getPointerTy()); - SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), B.Reg, ShiftOp); + SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), + B.Reg, ShiftOp); // Set NextBlock to be the MBB immediately after the current one, if any. // This is used to avoid emitting unnecessary branches to the next block. @@ -1508,7 +1511,7 @@ unsigned Reg, BitTestCase &B) { // Make desired shift - SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), Reg, + SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg, TLI.getPointerTy()); SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), TLI.getPointerTy(), @@ -3843,7 +3846,7 @@ SDValue Op2 = getValue(I.getOperand(2)); SDValue Op3 = getValue(I.getOperand(3)); unsigned Align = cast(I.getOperand(4))->getZExtValue(); - DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false, + DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false, I.getOperand(1), 0, I.getOperand(2), 0)); return 0; } @@ -3852,7 +3855,7 @@ SDValue Op2 = getValue(I.getOperand(2)); SDValue Op3 = getValue(I.getOperand(3)); unsigned Align = cast(I.getOperand(4))->getZExtValue(); - DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align, + DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, I.getOperand(1), 0)); return 0; } @@ -3869,12 +3872,12 @@ Size = C->getZExtValue(); if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) == AliasAnalysis::NoAlias) { - DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false, + DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false, I.getOperand(1), 0, I.getOperand(2), 0)); return 0; } - DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align, + DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, I.getOperand(1), 0, I.getOperand(2), 0)); return 0; } @@ -4094,7 +4097,7 @@ } MVT DestVT = TLI.getValueType(I.getType()); Value* Op1 = I.getOperand(1); - setValue(&I, DAG.getConvertRndSat(DestVT, getValue(Op1), + setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), DAG.getValueType(DestVT), DAG.getValueType(getValue(Op1).getValueType()), getValue(I.getOperand(2)), @@ -4512,9 +4515,9 @@ for (unsigned i = 0; i != NumRegs; ++i) { SDValue P; if (Flag == 0) - P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT); + P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); else { - P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag); + P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); *Flag = P.getValue(2); } Chain = P.getValue(1); @@ -4599,9 +4602,9 @@ for (unsigned i = 0; i != NumRegs; ++i) { SDValue Part; if (Flag == 0) - Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]); + Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); else { - Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag); + Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); *Flag = Part.getValue(1); } Chains[i] = Part.getValue(0); @@ -5436,9 +5439,9 @@ } void SelectionDAGLowering::visitVAArg(VAArgInst &I) { - SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), - getValue(I.getOperand(0)), - DAG.getSrcValue(I.getOperand(0))); + SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), + getRoot(), getValue(I.getOperand(0)), + DAG.getSrcValue(I.getOperand(0))); setValue(&I, V); DAG.setRoot(V.getValue(1)); } From evan.cheng at apple.com Tue Feb 3 17:21:41 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 3 Feb 2009 15:21:41 -0800 Subject: [llvm-commits] [llvm] r63677 - /llvm/trunk/lib/CodeGen/MachineFunction.cpp In-Reply-To: <200902032255.n13Mtsdt020225@zion.cs.uiuc.edu> References: <200902032255.n13Mtsdt020225@zion.cs.uiuc.edu> Message-ID: <11B9ED1C-88C7-4E57-9E24-40C338520516@apple.com> On Feb 3, 2009, at 2:55 PM, Bill Wendling wrote: > Author: void > Date: Tue Feb 3 16:55:54 2009 > New Revision: 63677 > > URL: http://llvm.org/viewvc/llvm-project?rev=63677&view=rev > Log: > Erm. Would be nice to initialize this variable. . . > > Modified: > llvm/trunk/lib/CodeGen/MachineFunction.cpp > > Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=63677&r1=63676&r2=63677&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original) > +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Feb 3 16:55:54 > 2009 > @@ -398,7 +398,7 @@ > > /// getDebugLocTuple - Get the DebugLocTuple for a given DebugLoc > object. > const DebugLocTuple &MachineFunction::getDebugLocTuple(DebugLoc DL) { It doesn't have to return a reference since DebugLocTuple is light weight. Also, this method should be const. Evan > > - unsigned Idx; > + unsigned Idx = DL.getIndex(); > assert(Idx < DebugLocInfo.DebugLocations.size() && > "Invalid index into debug locations!"); > return DebugLocInfo.DebugLocations[Idx]; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From rafael.espindola at gmail.com Tue Feb 3 17:28:07 2009 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 03 Feb 2009 23:28:07 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63682 - /llvm-gcc-4.2/trunk/gcc/gcc.c Message-ID: <200902032328.n13NS7C7021246@zion.cs.uiuc.edu> Author: rafael Date: Tue Feb 3 17:28:07 2009 New Revision: 63682 URL: http://llvm.org/viewvc/llvm-project?rev=63682&view=rev Log: add LLVM LOCAL Modified: llvm-gcc-4.2/trunk/gcc/gcc.c Modified: llvm-gcc-4.2/trunk/gcc/gcc.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gcc.c?rev=63682&r1=63681&r2=63682&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/gcc.c (original) +++ llvm-gcc-4.2/trunk/gcc/gcc.c Tue Feb 3 17:28:07 2009 @@ -767,7 +767,9 @@ static const char *startfile_spec = STARTFILE_SPEC; static const char *switches_need_spaces = SWITCHES_NEED_SPACES; static const char *linker_name_spec = LINKER_NAME; +/* LLVM LOCAL begin */ static const char *gold_plugin_file_spec = ""; +/* LLVM LOCAL end */ static const char *link_command_spec = LINK_COMMAND_SPEC; static const char *link_libgcc_spec = LINK_LIBGCC_SPEC; static const char *startfile_prefix_spec = STARTFILE_PREFIX_SPEC; @@ -7142,7 +7144,9 @@ if (num_linker_inputs > 0 && error_count == 0) { int tmp = execution_count; + /* LLVM LOCAL begin */ const char *use_gold_plugin = "use-gold-plugin"; + /* LLVM LOCAL end */ /* We'll use ld if we can't find collect2. */ if (! strcmp (linker_name_spec, "collect2")) @@ -7152,6 +7156,7 @@ linker_name_spec = "ld"; } + /* LLVM LOCAL begin */ if (switch_matches (use_gold_plugin, use_gold_plugin + strlen (use_gold_plugin), 0)) { @@ -7161,6 +7166,7 @@ if (!gold_plugin_file_spec) fatal ("-use-gold-plugin, but libLLVMgold.so not found."); } + /* LLVM LOCAL end */ /* Rebuild the COMPILER_PATH and LIBRARY_PATH environment variables for collect. */ From espindola at google.com Tue Feb 3 17:28:46 2009 From: espindola at google.com (Rafael Espindola) Date: Tue, 3 Feb 2009 23:28:46 +0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63633 - /llvm-gcc-4.2/trunk/gcc/gcc.c In-Reply-To: References: <200902031620.n13GKM9K005714@zion.cs.uiuc.edu> Message-ID: <38a0d8450902031528oe5a14d8xb81b2d648d517351@mail.gmail.com> > Please use the LTDL_SUFFIX (or whatever) macro which indicates whether > a dynamic library suffix is ".so" or ".dylib" or .somethingelse. There is LTDL_SHLIB_EXT, but it is not available in gcc.c. Could not find any constant with the suffix... > I > know that gold currently only supports elf, but it would be nice to > keep the code general. Also, please make sure to wrap your llvm-gcc > changes with "LLVM LOCAL" markers so that the changes don't get lost > in merges. Done. > Thanks! > > -Chris Cheers, -- Rafael Avila de Espindola Google | Gordon House | Barrow Street | Dublin 4 | Ireland Registered in Dublin, Ireland | Registration Number: 368047 From dpatel at apple.com Tue Feb 3 18:03:08 2009 From: dpatel at apple.com (Devang Patel) Date: Wed, 04 Feb 2009 00:03:08 -0000 Subject: [llvm-commits] [llvm] r63687 - in /llvm/trunk: lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/hoist-common-code.dbg.ll Message-ID: <200902040003.n14038gJ022327@zion.cs.uiuc.edu> Author: dpatel Date: Tue Feb 3 18:03:08 2009 New Revision: 63687 URL: http://llvm.org/viewvc/llvm-project?rev=63687&view=rev Log: Ignore dbg intrinsics while hoisting common code in the two blocks up into the branch block. Added: llvm/trunk/test/Transforms/SimplifyCFG/hoist-common-code.dbg.ll Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=63687&r1=63686&r2=63687&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Feb 3 18:03:08 2009 @@ -853,7 +853,14 @@ BasicBlock *BB1 = BI->getSuccessor(0); // The true destination. BasicBlock *BB2 = BI->getSuccessor(1); // The false destination - Instruction *I1 = BB1->begin(), *I2 = BB2->begin(); + BasicBlock::iterator BB1_Itr = BB1->begin(); + BasicBlock::iterator BB2_Itr = BB2->begin(); + + Instruction *I1 = BB1_Itr++, *I2 = BB2_Itr++; + while (isa(I1)) + I1 = BB1_Itr++; + while (isa(I2)) + I2 = BB2_Itr++; if (I1->getOpcode() != I2->getOpcode() || isa(I1) || isa(I1) || !I1->isIdenticalTo(I2)) return false; @@ -875,8 +882,12 @@ I2->replaceAllUsesWith(I1); BB2->getInstList().erase(I2); - I1 = BB1->begin(); - I2 = BB2->begin(); + I1 = BB1_Itr++; + while (isa(I1)) + I1 = BB1_Itr++; + I2 = BB2_Itr++; + while (isa(I2)) + I2 = BB2_Itr++; } while (I1->getOpcode() == I2->getOpcode() && I1->isIdenticalTo(I2)); return true; Added: llvm/trunk/test/Transforms/SimplifyCFG/hoist-common-code.dbg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/hoist-common-code.dbg.ll?rev=63687&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/hoist-common-code.dbg.ll (added) +++ llvm/trunk/test/Transforms/SimplifyCFG/hoist-common-code.dbg.ll Tue Feb 3 18:03:08 2009 @@ -0,0 +1,33 @@ +; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | not grep br + + + %llvm.dbg.anchor.type = type { i32, i32 } + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } + + at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata" ; + + at .str = internal constant [4 x i8] c"a.c\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at .str1 = internal constant [6 x i8] c"/tmp/\00", section "llvm.metadata" ; <[6 x i8]*> [#uses=1] + at .str2 = internal constant [55 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build 00)\00", section "llvm.metadata" ; <[55 x i8]*> [#uses=1] + at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([6 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([55 x i8]* @.str2, i32 0, i32 0), i1 true, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] + +declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind + +declare void @bar(i32) + +define void @test(i1 %P, i32* %Q) { + br i1 %P, label %T, label %F +T: ; preds = %0 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + store i32 1, i32* %Q + %A = load i32* %Q ; [#uses=1] + call void @bar( i32 %A ) + ret void +F: ; preds = %0 + store i32 1, i32* %Q +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %B = load i32* %Q ; [#uses=1] + call void @bar( i32 %B ) + ret void +} + From isanbard at gmail.com Tue Feb 3 18:05:34 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 04 Feb 2009 00:05:34 -0000 Subject: [llvm-commits] [llvm] r63689 - in /llvm/trunk: include/llvm/CodeGen/MachineFunction.h lib/CodeGen/MachineFunction.cpp Message-ID: <200902040005.n1405YVl022411@zion.cs.uiuc.edu> Author: void Date: Tue Feb 3 18:05:34 2009 New Revision: 63689 URL: http://llvm.org/viewvc/llvm-project?rev=63689&view=rev Log: Constify and don't return a reference. Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h llvm/trunk/lib/CodeGen/MachineFunction.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=63689&r1=63688&r2=63689&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Tue Feb 3 18:05:34 2009 @@ -318,7 +318,7 @@ unsigned getOrCreateDebugLocID(unsigned Src, unsigned Line, unsigned Col); /// getDebugLocTuple - Get the DebugLocTuple for a given DebugLoc object. - const DebugLocTuple &getDebugLocTuple(DebugLoc DL); + DebugLocTuple getDebugLocTuple(DebugLoc DL) const; }; //===--------------------------------------------------------------------===// Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=63689&r1=63688&r2=63689&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Feb 3 18:05:34 2009 @@ -397,7 +397,7 @@ } /// getDebugLocTuple - Get the DebugLocTuple for a given DebugLoc object. -const DebugLocTuple &MachineFunction::getDebugLocTuple(DebugLoc DL) { +DebugLocTuple MachineFunction::getDebugLocTuple(DebugLoc DL) const { unsigned Idx = DL.getIndex(); assert(Idx < DebugLocInfo.DebugLocations.size() && "Invalid index into debug locations!"); From isanbard at gmail.com Tue Feb 3 18:06:15 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 3 Feb 2009 16:06:15 -0800 Subject: [llvm-commits] [llvm] r63677 - /llvm/trunk/lib/CodeGen/MachineFunction.cpp In-Reply-To: <11B9ED1C-88C7-4E57-9E24-40C338520516@apple.com> References: <200902032255.n13Mtsdt020225@zion.cs.uiuc.edu> <11B9ED1C-88C7-4E57-9E24-40C338520516@apple.com> Message-ID: <16e5fdf90902031606v452a5d63ma45bd19ae74896aa@mail.gmail.com> On Tue, Feb 3, 2009 at 3:21 PM, Evan Cheng wrote: > On Feb 3, 2009, at 2:55 PM, Bill Wendling wrote: > >> const DebugLocTuple &MachineFunction::getDebugLocTuple(DebugLoc DL) { > > It doesn't have to return a reference since DebugLocTuple is light > weight. Also, this method should be const. > It's 3 unsigned ints, so it's not that small, but I don't really care that much. Fixed. -bw From dalej at apple.com Tue Feb 3 18:13:36 2009 From: dalej at apple.com (Dale Johannesen) Date: Wed, 04 Feb 2009 00:13:36 -0000 Subject: [llvm-commits] [llvm] r63690 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp LegalizeIntegerTypes.cpp LegalizeTypesGeneric.cpp LegalizeVectorTypes.cpp SelectionDAGISel.cpp Message-ID: <200902040013.n140Db6x022677@zion.cs.uiuc.edu> Author: johannes Date: Tue Feb 3 18:13:36 2009 New Revision: 63690 URL: http://llvm.org/viewvc/llvm-project?rev=63690&view=rev Log: Fill in more omissions in DebugLog propagation. I think that's it for this directory. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63690&r1=63689&r2=63690&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Feb 3 18:13:36 2009 @@ -1108,7 +1108,7 @@ default: assert(0 && "This action is not supported yet!"); case TargetLowering::Expand: { unsigned Reg = TLI.getExceptionAddressRegister(); - Result = DAG.getCopyFromReg(Tmp1, Reg, VT); + Result = DAG.getCopyFromReg(Tmp1, dl, Reg, VT); } break; case TargetLowering::Custom: @@ -1142,7 +1142,7 @@ default: assert(0 && "This action is not supported yet!"); case TargetLowering::Expand: { unsigned Reg = TLI.getExceptionSelectorRegister(); - Result = DAG.getCopyFromReg(Tmp2, Reg, VT); + Result = DAG.getCopyFromReg(Tmp2, dl, Reg, VT); } break; case TargetLowering::Custom: @@ -1911,7 +1911,7 @@ Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); SDValue Size = Tmp2.getOperand(1); - SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT); + SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); Chain = SP.getValue(1); unsigned Align = cast(Tmp3)->getZExtValue(); unsigned StackAlign = @@ -1920,7 +1920,7 @@ SP = DAG.getNode(ISD::AND, dl, VT, SP, DAG.getConstant(-(uint64_t)Align, VT)); Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value - Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain + Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), DAG.getIntPtrConstant(0, true), SDValue()); @@ -2882,7 +2882,7 @@ // Expand to CopyFromReg if the target set // StackPointerRegisterToSaveRestore. if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { - Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, + Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), dl, SP, Node->getValueType(0)); Tmp2 = Tmp1.getValue(1); } else { @@ -2914,7 +2914,7 @@ // Expand to CopyToReg if the target set // StackPointerRegisterToSaveRestore. if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { - Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); + Result = DAG.getCopyToReg(Tmp1, dl, SP, Tmp2); } else { Result = Tmp1; } @@ -4029,7 +4029,7 @@ Result = PromoteOp(Node->getOperand(0)); // For FP, make Op1 a i32 - Result = DAG.getConvertRndSat(Op.getValueType(), Result, + Result = DAG.getConvertRndSat(Op.getValueType(), dl, Result, DTyOp, STyOp, RndOp, SatOp, CvtCode); break; } @@ -4593,7 +4593,7 @@ CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && "can only promote integers"); - Result = DAG.getConvertRndSat(NVT, Node->getOperand(0), + Result = DAG.getConvertRndSat(NVT, dl, Node->getOperand(0), Node->getOperand(1), Node->getOperand(2), Node->getOperand(3), Node->getOperand(4), CvtCode); @@ -4877,11 +4877,11 @@ Tmp1 = Node->getOperand(0); // Get the chain. Tmp2 = Node->getOperand(1); // Get the pointer. if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { - Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); + Tmp3 = DAG.getVAArg(VT, dl, Tmp1, Tmp2, Node->getOperand(2)); Result = TLI.LowerOperation(Tmp3, DAG); } else { const Value *V = cast(Node->getOperand(2))->getValue(); - SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); + SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0); // Increment the pointer, VAList, to the next vaarg Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, DAG.getConstant(VT.getSizeInBits()/8, @@ -6578,8 +6578,8 @@ case ISD::VAARG: { SDValue Ch = Node->getOperand(0); // Legalize the chain. SDValue Ptr = Node->getOperand(1); // Legalize the pointer. - Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); - Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); + Lo = DAG.getVAArg(NVT, dl, Ch, Ptr, Node->getOperand(2)); + Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, Node->getOperand(2)); // Remember that we legalized the chain. Hi = LegalizeOp(Hi); @@ -7744,9 +7744,9 @@ SDValue RndOp = Node->getOperand(3); SDValue SatOp = Node->getOperand(4); - Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL, + Lo = DAG.getConvertRndSat(NewVT_Lo, dl, L, DTyOpL, STyOpL, RndOp, SatOp, CvtCode); - Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH, + Hi = DAG.getConvertRndSat(NewVT_Hi, dl, H, DTyOpH, STyOpH, RndOp, SatOp, CvtCode); break; } @@ -7892,7 +7892,7 @@ break; case ISD::CONVERT_RNDSAT: { SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0)); - Result = DAG.getConvertRndSat(NewVT, Op0, + Result = DAG.getConvertRndSat(NewVT, dl, Op0, DAG.getValueType(NewVT), DAG.getValueType(Op0.getValueType()), Node->getOperand(3), @@ -8199,7 +8199,7 @@ SDValue STyOp = DAG.getValueType(SrcOp.getValueType()); ISD::CvtCode CvtCode = cast(Node)->getCvtCode(); - Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp, + Result = DAG.getConvertRndSat(WidenVT, dl, SrcOp, DTyOp, STyOp, RndOp, SatOp, CvtCode); break; } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=63690&r1=63689&r2=63690&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Feb 3 18:13:36 2009 @@ -262,7 +262,7 @@ CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && "can only promote integers"); MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); - return DAG.getConvertRndSat(OutVT, N->getOperand(0), + return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3), N->getOperand(4), CvtCode); } @@ -608,7 +608,7 @@ SmallVector Parts(NumRegs); for (unsigned i = 0; i < NumRegs; ++i) { - Parts[i] = DAG.getVAArg(RegVT, Chain, Ptr, N->getOperand(2)); + Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2)); Chain = Parts[i].getValue(1); } @@ -823,7 +823,7 @@ CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) && "can only promote integer arguments"); SDValue InOp = GetPromotedInteger(N->getOperand(0)); - return DAG.getConvertRndSat(N->getValueType(0), InOp, + return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp, N->getOperand(1), N->getOperand(2), N->getOperand(3), N->getOperand(4), CvtCode); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=63690&r1=63689&r2=63690&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Tue Feb 3 18:13:36 2009 @@ -209,9 +209,10 @@ MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Chain = N->getOperand(0); SDValue Ptr = N->getOperand(1); + DebugLoc dl = N->getDebugLoc(); - Lo = DAG.getVAArg(NVT, Chain, Ptr, N->getOperand(2)); - Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, N->getOperand(2)); + Lo = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2)); + Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, N->getOperand(2)); // Handle endianness of the load. if (TLI.isBigEndian()) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=63690&r1=63689&r2=63690&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Feb 3 18:13:36 2009 @@ -126,7 +126,8 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) { MVT NewVT = N->getValueType(0).getVectorElementType(); SDValue Op0 = GetScalarizedVector(N->getOperand(0)); - return DAG.getConvertRndSat(NewVT, Op0, DAG.getValueType(NewVT), + return DAG.getConvertRndSat(NewVT, N->getDebugLoc(), + Op0, DAG.getValueType(NewVT), DAG.getValueType(Op0.getValueType()), N->getOperand(3), N->getOperand(4), @@ -533,6 +534,7 @@ void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo, SDValue &Hi) { MVT LoVT, HiVT; + DebugLoc dl = N->getDebugLoc(); GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); SDValue VLo, VHi; GetSplitVector(N->getOperand(0), VLo, VHi); @@ -545,8 +547,10 @@ SDValue SatOp = N->getOperand(4); ISD::CvtCode CvtCode = cast(N)->getCvtCode(); - Lo = DAG.getConvertRndSat(LoVT, VLo, DTyOpLo, STyOpLo, RndOp, SatOp, CvtCode); - Hi = DAG.getConvertRndSat(HiVT, VHi, DTyOpHi, STyOpHi, RndOp, SatOp, CvtCode); + Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp, + CvtCode); + Hi = DAG.getConvertRndSat(HiVT, dl, VHi, DTyOpHi, STyOpHi, RndOp, SatOp, + CvtCode); } void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, @@ -1454,6 +1458,7 @@ } SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) { + DebugLoc dl = N->getDebugLoc(); SDValue InOp = N->getOperand(0); SDValue RndOp = N->getOperand(3); SDValue SatOp = N->getOperand(4); @@ -1475,7 +1480,7 @@ InVT = InOp.getValueType(); InVTNumElts = InVT.getVectorNumElements(); if (InVTNumElts == WidenNumElts) - return DAG.getConvertRndSat(WidenVT, InOp, DTyOp, STyOp, RndOp, + return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, SatOp, CvtCode); } @@ -1490,20 +1495,20 @@ unsigned NumConcat = WidenNumElts/InVTNumElts; SmallVector Ops(NumConcat); Ops[0] = InOp; - SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT); + SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT); for (unsigned i = 1; i != NumConcat; ++i) { Ops[i] = UndefVal; } - InOp = DAG.getNode(ISD::CONCAT_VECTORS, InWidenVT, &Ops[0], NumConcat); - return DAG.getConvertRndSat(WidenVT, InOp, DTyOp, STyOp, RndOp, + InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat); + return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, SatOp, CvtCode); } if (InVTNumElts % WidenNumElts == 0) { // Extract the input and convert the shorten input vector. - InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InWidenVT, InOp, + InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp, DAG.getIntPtrConstant(0)); - return DAG.getConvertRndSat(WidenVT, InOp, DTyOp, STyOp, RndOp, + return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, SatOp, CvtCode); } } @@ -1517,17 +1522,17 @@ unsigned MinElts = std::min(InVTNumElts, WidenNumElts); unsigned i; for (i=0; i < MinElts; ++i) { - SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, InEltVT, InOp, + SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, DAG.getIntPtrConstant(i)); - Ops[i] = DAG.getConvertRndSat(WidenVT, ExtVal, DTyOp, STyOp, RndOp, + Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp, SatOp, CvtCode); } - SDValue UndefVal = DAG.getNode(ISD::UNDEF, EltVT); + SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT); for (; i < WidenNumElts; ++i) Ops[i] = UndefVal; - return DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &Ops[0], WidenNumElts); + return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); } SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=63690&r1=63689&r2=63690&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Feb 3 18:13:36 2009 @@ -440,9 +440,11 @@ MVT VT = Arg.getValueType(); unsigned VReg = MF.getRegInfo(). createVirtualRegister(TLI.getRegClassFor(VT)); - Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag); + Chain = DAG.getCopyToReg(Chain, Arg.getNode()->getDebugLoc(), + VReg, Arg, InFlag); InFlag = Chain.getValue(1); - Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag); + Arg = DAG.getCopyFromReg(Chain, Arg.getNode()->getDebugLoc(), + VReg, VT, InFlag); Chain = Arg.getValue(1); InFlag = Arg.getValue(2); } From clattner at apple.com Tue Feb 3 18:27:25 2009 From: clattner at apple.com (Chris Lattner) Date: Tue, 3 Feb 2009 16:27:25 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r63633 - /llvm-gcc-4.2/trunk/gcc/gcc.c In-Reply-To: <38a0d8450902031528oe5a14d8xb81b2d648d517351@mail.gmail.com> References: <200902031620.n13GKM9K005714@zion.cs.uiuc.edu> <38a0d8450902031528oe5a14d8xb81b2d648d517351@mail.gmail.com> Message-ID: <78987006-1A92-4132-8353-315EEFF3D2FB@apple.com> On Feb 3, 2009, at 3:28 PM, Rafael Espindola wrote: >> Please use the LTDL_SUFFIX (or whatever) macro which indicates >> whether >> a dynamic library suffix is ".so" or ".dylib" or .somethingelse. > > There is LTDL_SHLIB_EXT, but it is not available in gcc.c. Could not > find any constant with the suffix... ok, no worries. >> know that gold currently only supports elf, but it would be nice to >> keep the code general. Also, please make sure to wrap your llvm-gcc >> changes with "LLVM LOCAL" markers so that the changes don't get lost >> in merges. > > Done. Thanks! From clattner at apple.com Tue Feb 3 18:28:08 2009 From: clattner at apple.com (Chris Lattner) Date: Tue, 3 Feb 2009 16:28:08 -0800 Subject: [llvm-commits] [llvm] r63690 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp LegalizeIntegerTypes.cpp LegalizeTypesGeneric.cpp LegalizeVectorTypes.cpp SelectionDAGISel.cpp In-Reply-To: <200902040013.n140Db6x022677@zion.cs.uiuc.edu> References: <200902040013.n140Db6x022677@zion.cs.uiuc.edu> Message-ID: <15A3D289-C010-423F-AB76-410C007E1E17@apple.com> On Feb 3, 2009, at 4:13 PM, Dale Johannesen wrote: > Author: johannes > Date: Tue Feb 3 18:13:36 2009 > New Revision: 63690 > > URL: http://llvm.org/viewvc/llvm-project?rev=63690&view=rev > Log: > Fill in more omissions in DebugLog propagation. > I think that's it for this directory. Nice! Can the non-debugloc "get" methods go away now? -Chris From evan.cheng at apple.com Tue Feb 3 18:29:54 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 3 Feb 2009 16:29:54 -0800 Subject: [llvm-commits] [llvm] r63677 - /llvm/trunk/lib/CodeGen/MachineFunction.cpp In-Reply-To: <16e5fdf90902031606v452a5d63ma45bd19ae74896aa@mail.gmail.com> References: <200902032255.n13Mtsdt020225@zion.cs.uiuc.edu> <11B9ED1C-88C7-4E57-9E24-40C338520516@apple.com> <16e5fdf90902031606v452a5d63ma45bd19ae74896aa@mail.gmail.com> Message-ID: <9C7C9381-AC52-436C-A27E-3500B0506F08@apple.com> On Feb 3, 2009, at 4:06 PM, Bill Wendling wrote: > On Tue, Feb 3, 2009 at 3:21 PM, Evan Cheng > wrote: >> On Feb 3, 2009, at 2:55 PM, Bill Wendling wrote: >> >>> const DebugLocTuple &MachineFunction::getDebugLocTuple(DebugLoc >>> DL) { >> >> It doesn't have to return a reference since DebugLocTuple is light >> weight. Also, this method should be const. >> > It's 3 unsigned ints, so it's not that small, but I don't really care > that much. Fixed. Thanks. MachineFunction owns the tuples, nothing else should modify them. Returning ref's means something else can mess with them (const can always be casted away). Evan > > > -bw > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dalej at apple.com Tue Feb 3 18:33:21 2009 From: dalej at apple.com (Dale Johannesen) Date: Wed, 04 Feb 2009 00:33:21 -0000 Subject: [llvm-commits] [llvm] r63693 - in /llvm/trunk/lib/Target/X86: X86ISelDAGToDAG.cpp X86ISelLowering.cpp Message-ID: <200902040033.n140XLSA023404@zion.cs.uiuc.edu> Author: johannes Date: Tue Feb 3 18:33:20 2009 New Revision: 63693 URL: http://llvm.org/viewvc/llvm-project?rev=63693&view=rev Log: Patch up omissions in DebugLoc propagation. Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=63693&r1=63692&r2=63693&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Feb 3 18:33:20 2009 @@ -1288,7 +1288,7 @@ std::swap(N0, N1); } - SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), LoReg, + SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, N0, SDValue()).getValue(1); if (foldedLoad) { @@ -1305,7 +1305,7 @@ // Copy the low half of the result, if it is needed. if (!N.getValue(0).use_empty()) { - SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), + SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT, InFlag); InFlag = Result.getValue(2); ReplaceUses(N.getValue(0), Result); @@ -1321,7 +1321,7 @@ if (HiReg == X86::AH && Subtarget->is64Bit()) { // Prevent use of AH in a REX instruction by referencing AX instead. // Shift it down 8 bits. - Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), + Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, X86::AX, MVT::i16, InFlag); InFlag = Result.getValue(2); Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16, @@ -1332,7 +1332,7 @@ Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl, MVT::i8, Result, SRIdx), 0); } else { - Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), + Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT, InFlag); InFlag = Result.getValue(2); } @@ -1421,11 +1421,11 @@ SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0); Chain = CurDAG->getEntryNode(); } - Chain = CurDAG->getCopyToReg(Chain, X86::AX, Move, SDValue()); + Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue()); InFlag = Chain.getValue(1); } else { InFlag = - CurDAG->getCopyToReg(CurDAG->getEntryNode(), + CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, N0, SDValue()).getValue(1); if (isSigned && !signBitIsZero) { // Sign extend the low part into the high part. @@ -1435,7 +1435,7 @@ // Zero out the high part, effectively zero extending the input. SDValue ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, dl, NVT), 0); - InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), HiReg, + InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, HiReg, ClrNode, InFlag).getValue(1); } } @@ -1454,7 +1454,7 @@ // Copy the division (low) result, if it is needed. if (!N.getValue(0).use_empty()) { - SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), + SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT, InFlag); InFlag = Result.getValue(2); ReplaceUses(N.getValue(0), Result); @@ -1470,7 +1470,7 @@ if (HiReg == X86::AH && Subtarget->is64Bit()) { // Prevent use of AH in a REX instruction by referencing AX instead. // Shift it down 8 bits. - Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), + Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, X86::AX, MVT::i16, InFlag); InFlag = Result.getValue(2); Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16, @@ -1482,7 +1482,7 @@ Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl, MVT::i8, Result, SRIdx), 0); } else { - Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), + Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT, InFlag); InFlag = Result.getValue(2); } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=63693&r1=63692&r2=63693&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Feb 3 18:33:20 2009 @@ -987,7 +987,7 @@ continue; } - Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag); + Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); Flag = Chain.getValue(1); } @@ -1004,9 +1004,9 @@ Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); FuncInfo->setSRetReturnReg(Reg); } - SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy()); + SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); - Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag); + Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); Flag = Chain.getValue(1); } @@ -1060,7 +1060,7 @@ CopyVT = MVT::f80; } - Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(), + Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), CopyVT, InFlag).getValue(1); SDValue Val = Chain.getValue(0); InFlag = Chain.getValue(2); @@ -1199,9 +1199,10 @@ /// function parameter. static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, - ISD::ArgFlagsTy Flags, SelectionDAG &DAG) { + ISD::ArgFlagsTy Flags, SelectionDAG &DAG, + DebugLoc dl) { SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); - return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), + return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), /*AlwaysInline=*/true, NULL, 0, NULL, 0); } @@ -1302,7 +1303,7 @@ } unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); - SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); + SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT); // If this is an 8 or 16-bit value, it is really passed promoted to 32 // bits. Insert an assert[sz]ext to capture this, then truncate to the @@ -1346,7 +1347,7 @@ Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); FuncInfo->setSRetReturnReg(Reg); } - SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]); + SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]); Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root); } @@ -1417,7 +1418,7 @@ for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs], X86::GR64RegisterClass); - SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64); + SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64); SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0); @@ -1432,7 +1433,7 @@ for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass); - SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32); + SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::v4f32); SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0); @@ -1484,7 +1485,7 @@ SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); if (Flags.isByVal()) { - return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG); + return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); } return DAG.getStore(Chain, dl, Arg, PtrOff, PseudoSourceValue::getStack(), LocMemOffset); @@ -1633,7 +1634,7 @@ if (!IsTailCall || (IsTailCall && isByVal)) { assert(VA.isMemLoc()); if (StackPtr.getNode() == 0) - StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy()); + StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA, Chain, Arg, Flags)); @@ -1652,15 +1653,15 @@ // tail call optimization the copies to registers are lowered later. if (!IsTailCall) for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, - InFlag); + Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, + RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } // ELF / PIC requires GOT in the EBX register before function calls via PLT // GOT pointer. if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) { - Chain = DAG.getCopyToReg(Chain, X86::EBX, + Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), InFlag); InFlag = Chain.getValue(1); @@ -1700,7 +1701,7 @@ assert((Subtarget->hasSSE1() || !NumXMMRegs) && "SSE registers cannot be used when SSE is disabled"); - Chain = DAG.getCopyToReg(Chain, X86::AL, + Chain = DAG.getCopyToReg(Chain, dl, X86::AL, DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); InFlag = Chain.getValue(1); } @@ -1729,11 +1730,12 @@ // Copy relative to framepointer. SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); if (StackPtr.getNode() == 0) - StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy()); + StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, + getPointerTy()); Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain, - Flags, DAG)); + Flags, DAG, dl)); } else { // Store relative to framepointer. MemOpChains2.push_back( @@ -1749,8 +1751,8 @@ // Copy arguments to their registers. for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, - InFlag); + Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, + RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } InFlag =SDValue(); @@ -1774,7 +1776,7 @@ } else if (IsTailCall) { unsigned Opc = Is64Bit ? X86::R9 : X86::EAX; - Chain = DAG.getCopyToReg(Chain, + Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Opc, getPointerTy()), Callee,InFlag); Callee = DAG.getRegister(Opc, getPointerTy()); @@ -4577,7 +4579,8 @@ LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, const MVT PtrVT) { SDValue InFlag; - SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX, + DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better + SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, DAG.getNode(X86ISD::GlobalBaseReg, PtrVT), InFlag); InFlag = Chain.getValue(1); @@ -4594,7 +4597,7 @@ // call ___tls_get_addr. This function receives its argument in // the register EAX. - Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag); + Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Result, InFlag); InFlag = Chain.getValue(1); NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); @@ -4607,7 +4610,7 @@ Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5); InFlag = Chain.getValue(1); - return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag); + return DAG.getCopyFromReg(Chain, dl, X86::EAX, PtrVT, InFlag); } // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit @@ -4615,6 +4618,7 @@ LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, const MVT PtrVT) { SDValue InFlag, Chain; + DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better // emit leaq symbol at TLSGD(%rip), %rdi SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag); @@ -4628,7 +4632,7 @@ // call __tls_get_addr. This function receives its argument in // the register RDI. - Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag); + Chain = DAG.getCopyToReg(Chain, dl, X86::RDI, Result, InFlag); InFlag = Chain.getValue(1); NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); @@ -4640,7 +4644,7 @@ Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4); InFlag = Chain.getValue(1); - return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag); + return DAG.getCopyFromReg(Chain, dl, X86::RAX, PtrVT, InFlag); } // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or @@ -5586,7 +5590,7 @@ Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); - Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag); + Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag); Flag = Chain.getValue(1); SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); @@ -5603,7 +5607,7 @@ DAG.getIntPtrConstant(0, true), Flag); - Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); SDValue Ops1[2] = { Chain.getValue(0), Chain }; return DAG.getMergeValues(Ops1, 2, dl); @@ -5897,8 +5901,9 @@ SDValue SrcPtr = Op.getOperand(2); const Value *DstSV = cast(Op.getOperand(3))->getValue(); const Value *SrcSV = cast(Op.getOperand(4))->getValue(); + DebugLoc dl = Op.getNode()->getDebugLoc(); - return DAG.getMemcpy(Chain, DstPtr, SrcPtr, + return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr, DAG.getIntPtrConstant(24), 8, false, DstSV, 0, SrcSV, 0); } @@ -6125,11 +6130,12 @@ MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); MFI->setFrameAddressIsTaken(true); MVT VT = Op.getValueType(); + DebugLoc dl = Op.getNode()->getDebugLoc(); // FIXME probably not meaningful unsigned Depth = cast(Op.getOperand(0))->getZExtValue(); unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; - SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), FrameReg, VT); + SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); while (Depth--) - FrameAddr = DAG.getLoad(VT, DAG.getEntryNode(), FrameAddr, NULL, 0); + FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0); return FrameAddr; } @@ -6154,7 +6160,7 @@ DAG.getIntPtrConstant(-TD->getPointerSize())); StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0); - Chain = DAG.getCopyToReg(Chain, StoreAddrReg, StoreAddr); + Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); MF.getRegInfo().addLiveOut(StoreAddrReg); return DAG.getNode(X86ISD::EH_RETURN, dl, @@ -6539,7 +6545,7 @@ Reg = X86::RAX; size = 8; break; } - SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg, + SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg, Op.getOperand(2), SDValue()); SDValue Ops[] = { cpIn.getValue(0), Op.getOperand(1), @@ -6549,7 +6555,7 @@ SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5); SDValue cpOut = - DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1)); + DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1)); return cpOut; } @@ -6560,8 +6566,8 @@ SDValue TheChain = Op.getOperand(0); DebugLoc dl = Op.getNode()->getDebugLoc(); SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); - SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1)); - SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX, MVT::i64, + SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); + SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, rax.getValue(2)); SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, DAG.getConstant(32, MVT::i8)); @@ -6692,8 +6698,9 @@ SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); SDValue TheChain = N->getOperand(0); SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); - SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)); - SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX, MVT::i32, + SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, + rd.getValue(1)); + SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, eax.getValue(2)); // Use a buildpair to merge the two 32-bit values into a 64-bit one. SDValue Ops[] = { eax, edx }; @@ -6709,27 +6716,27 @@ DAG.getConstant(0, MVT::i32)); cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), DAG.getConstant(1, MVT::i32)); - cpInL = DAG.getCopyToReg(N->getOperand(0), X86::EAX, cpInL, SDValue()); - cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX, cpInH, + cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue()); + cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH, cpInL.getValue(1)); SDValue swapInL, swapInH; swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), DAG.getConstant(0, MVT::i32)); swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), DAG.getConstant(1, MVT::i32)); - swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX, swapInL, + swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL, cpInH.getValue(1)); - swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX, swapInH, + swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH, swapInL.getValue(1)); SDValue Ops[] = { swapInH.getValue(0), N->getOperand(1), swapInH.getValue(1) }; SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3); - SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32, - Result.getValue(1)); - SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32, - cpOutL.getValue(2)); + SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, + MVT::i32, Result.getValue(1)); + SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, + MVT::i32, cpOutL.getValue(2)); SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); Results.push_back(cpOutH.getValue(1)); From dalej at apple.com Tue Feb 3 18:35:24 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 3 Feb 2009 16:35:24 -0800 Subject: [llvm-commits] [llvm] r63690 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp LegalizeIntegerTypes.cpp LegalizeTypesGeneric.cpp LegalizeVectorTypes.cpp SelectionDAGISel.cpp In-Reply-To: <15A3D289-C010-423F-AB76-410C007E1E17@apple.com> References: <200902040013.n140Db6x022677@zion.cs.uiuc.edu> <15A3D289-C010-423F-AB76-410C007E1E17@apple.com> Message-ID: <29A8DABD-D69B-4BA6-B8ED-5D0F24CEC1D3@apple.com> On Feb 3, 2009, at 4:28 PMPST, Chris Lattner wrote: > > On Feb 3, 2009, at 4:13 PM, Dale Johannesen wrote: > >> Author: johannes >> Date: Tue Feb 3 18:13:36 2009 >> New Revision: 63690 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=63690&view=rev >> Log: >> Fill in more omissions in DebugLog propagation. >> I think that's it for this directory. > > Nice! Can the non-debugloc "get" methods go away now? > > -Chris Some of them maybe, I'm about to try. There's lot of target-specific code nobody's touched, and it may not be the right idea to touch it at this point (I've done X86). From clattner at apple.com Tue Feb 3 18:44:07 2009 From: clattner at apple.com (Chris Lattner) Date: Tue, 3 Feb 2009 16:44:07 -0800 Subject: [llvm-commits] [llvm] r63690 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp LegalizeIntegerTypes.cpp LegalizeTypesGeneric.cpp LegalizeVectorTypes.cpp SelectionDAGISel.cpp In-Reply-To: <29A8DABD-D69B-4BA6-B8ED-5D0F24CEC1D3@apple.com> References: <200902040013.n140Db6x022677@zion.cs.uiuc.edu> <15A3D289-C010-423F-AB76-410C007E1E17@apple.com> <29A8DABD-D69B-4BA6-B8ED-5D0F24CEC1D3@apple.com> Message-ID: On Feb 3, 2009, at 4:35 PM, Dale Johannesen wrote: > > On Feb 3, 2009, at 4:28 PMPST, Chris Lattner wrote: > >> >> On Feb 3, 2009, at 4:13 PM, Dale Johannesen wrote: >> >>> Author: johannes >>> Date: Tue Feb 3 18:13:36 2009 >>> New Revision: 63690 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=63690&view=rev >>> Log: >>> Fill in more omissions in DebugLog propagation. >>> I think that's it for this directory. >> >> Nice! Can the non-debugloc "get" methods go away now? >> >> -Chris > > Some of them maybe, I'm about to try. There's lot of target-specific > code nobody's touched, and it may not be the right idea to touch it at > this point (I've done X86). Thanks. Even if a bit painful, it would be really nice to do this. Eliminating these old accessors means that it is much more difficult to write code that forgets about the debug info. -Chris From isanbard at gmail.com Tue Feb 3 18:48:52 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 3 Feb 2009 16:48:52 -0800 Subject: [llvm-commits] [llvm] r63677 - /llvm/trunk/lib/CodeGen/MachineFunction.cpp In-Reply-To: <9C7C9381-AC52-436C-A27E-3500B0506F08@apple.com> References: <200902032255.n13Mtsdt020225@zion.cs.uiuc.edu> <11B9ED1C-88C7-4E57-9E24-40C338520516@apple.com> <16e5fdf90902031606v452a5d63ma45bd19ae74896aa@mail.gmail.com> <9C7C9381-AC52-436C-A27E-3500B0506F08@apple.com> Message-ID: <16e5fdf90902031648g26b67f96u14cdf40d6dde91f3@mail.gmail.com> On Tue, Feb 3, 2009 at 4:29 PM, Evan Cheng wrote: > > On Feb 3, 2009, at 4:06 PM, Bill Wendling wrote: > >> On Tue, Feb 3, 2009 at 3:21 PM, Evan Cheng >> wrote: >>> On Feb 3, 2009, at 2:55 PM, Bill Wendling wrote: >>> >>>> const DebugLocTuple &MachineFunction::getDebugLocTuple(DebugLoc >>>> DL) { >>> >>> It doesn't have to return a reference since DebugLocTuple is light >>> weight. Also, this method should be const. >>> >> It's 3 unsigned ints, so it's not that small, but I don't really care >> that much. Fixed. > > Thanks. MachineFunction owns the tuples, nothing else should modify > them. Returning ref's means something else can mess with them (const > can always be casted away). > const_cast is evil! :-) -bw From stuart at apple.com Tue Feb 3 18:53:40 2009 From: stuart at apple.com (Stuart Hastings) Date: Wed, 04 Feb 2009 00:53:40 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63696 - /llvm-gcc-4.2/trunk/gcc/cp/parser.c Message-ID: <200902040053.n140reOt024041@zion.cs.uiuc.edu> Author: stuart Date: Tue Feb 3 18:53:40 2009 New Revision: 63696 URL: http://llvm.org/viewvc/llvm-project?rev=63696&view=rev Log: Call cp_finish_decl() before marking the block_holder_tmp_decl readonly. Fixes these DejaGNU regressions: g++.apple/block-call-with-sideeffect.c g++.apple/block-global-block.c g++.apple/block-id-global-block.c g++.apple/block-localisglobal.c g++.apple/block-nested-global-copied-var-2.c g++.apple/block-nested-global.c Modified: llvm-gcc-4.2/trunk/gcc/cp/parser.c Modified: llvm-gcc-4.2/trunk/gcc/cp/parser.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/cp/parser.c?rev=63696&r1=63695&r2=63696&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/cp/parser.c (original) +++ llvm-gcc-4.2/trunk/gcc/cp/parser.c Tue Feb 3 18:53:40 2009 @@ -21065,13 +21065,13 @@ TREE_PUBLIC (block_holder_tmp_decl) = 0; TREE_STATIC (block_holder_tmp_decl) = 1; } + cp_finish_decl (block_holder_tmp_decl, constructor, 0, 0, LOOKUP_ONLYCONVERTING); /* LLVM LOCAL begin radar 5865221 */ #ifdef ENABLE_LLVM TREE_CONSTANT (block_holder_tmp_decl) = 1; TREE_READONLY (block_holder_tmp_decl) = 1; #endif /* LLVM LOCAL end radar 5865221 */ - cp_finish_decl (block_holder_tmp_decl, constructor, 0, 0, LOOKUP_ONLYCONVERTING); return block_holder_tmp_decl; } /* APPLE LOCAL end radar 6169527 */ From dpatel at apple.com Tue Feb 3 19:06:11 2009 From: dpatel at apple.com (Devang Patel) Date: Wed, 04 Feb 2009 01:06:11 -0000 Subject: [llvm-commits] [llvm] r63700 - in /llvm/trunk: lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/switch_formation.dbg.ll Message-ID: <200902040106.n1416BkY024520@zion.cs.uiuc.edu> Author: dpatel Date: Tue Feb 3 19:06:11 2009 New Revision: 63700 URL: http://llvm.org/viewvc/llvm-project?rev=63700&view=rev Log: While folding vallue comparison terminators ignore dbg intrinsics. Added: llvm/trunk/test/Transforms/SimplifyCFG/switch_formation.dbg.ll Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=63700&r1=63699&r2=63700&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Feb 3 19:06:11 2009 @@ -1882,7 +1882,10 @@ return SimplifyCFG(BB) || 1; // This block must be empty, except for the setcond inst, if it exists. + // Ignore dbg intrinsics. BasicBlock::iterator I = BB->begin(); + while (isa(I)) + I++; if (&*I == BI || (&*I == cast(BI->getCondition()) && &*++I == BI)) Added: llvm/trunk/test/Transforms/SimplifyCFG/switch_formation.dbg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/switch_formation.dbg.ll?rev=63700&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/switch_formation.dbg.ll (added) +++ llvm/trunk/test/Transforms/SimplifyCFG/switch_formation.dbg.ll Tue Feb 3 19:06:11 2009 @@ -0,0 +1,49 @@ +; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | not grep br +; END. + + + %llvm.dbg.anchor.type = type { i32, i32 } + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } + + at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata" ; + + at .str = internal constant [4 x i8] c"a.c\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at .str1 = internal constant [6 x i8] c"/tmp/\00", section "llvm.metadata" ; <[6 x i8]*> [#uses=1] + at .str2 = internal constant [55 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build 00)\00", section "llvm.metadata" ; <[55 x i8]*> [#uses=1] + at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([6 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([55 x i8]* @.str2, i32 0, i32 0), i1 true, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] + +declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind + +define i1 @_ZN4llvm11SetCondInst7classofEPKNS_11InstructionE({ i32, i32 }* %I) { +entry: + %tmp.1.i = getelementptr { i32, i32 }* %I, i64 0, i32 1 ; [#uses=1] + %tmp.2.i = load i32* %tmp.1.i ; [#uses=6] + %tmp.2 = icmp eq i32 %tmp.2.i, 14 ; [#uses=1] + br i1 %tmp.2, label %shortcirc_done.4, label %shortcirc_next.0 +shortcirc_next.0: ; preds = %entry +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %tmp.6 = icmp eq i32 %tmp.2.i, 15 ; [#uses=1] + br i1 %tmp.6, label %shortcirc_done.4, label %shortcirc_next.1 +shortcirc_next.1: ; preds = %shortcirc_next.0 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %tmp.11 = icmp eq i32 %tmp.2.i, 16 ; [#uses=1] + br i1 %tmp.11, label %shortcirc_done.4, label %shortcirc_next.2 +shortcirc_next.2: ; preds = %shortcirc_next.1 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %tmp.16 = icmp eq i32 %tmp.2.i, 17 ; [#uses=1] + br i1 %tmp.16, label %shortcirc_done.4, label %shortcirc_next.3 +shortcirc_next.3: ; preds = %shortcirc_next.2 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %tmp.21 = icmp eq i32 %tmp.2.i, 18 ; [#uses=1] + br i1 %tmp.21, label %shortcirc_done.4, label %shortcirc_next.4 +shortcirc_next.4: ; preds = %shortcirc_next.3 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %tmp.26 = icmp eq i32 %tmp.2.i, 19 ; [#uses=1] + br label %UnifiedReturnBlock +shortcirc_done.4: ; preds = %shortcirc_next.3, %shortcirc_next.2, %shortcirc_next.1, %shortcirc_next.0, %entry + br label %UnifiedReturnBlock +UnifiedReturnBlock: ; preds = %shortcirc_done.4, %shortcirc_next.4 + %UnifiedRetVal = phi i1 [ %tmp.26, %shortcirc_next.4 ], [ true, %shortcirc_done.4 ] ; [#uses=1] + ret i1 %UnifiedRetVal +} + From wangmp at apple.com Tue Feb 3 19:16:59 2009 From: wangmp at apple.com (Mon P Wang) Date: Wed, 04 Feb 2009 01:16:59 -0000 Subject: [llvm-commits] [llvm] r63702 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/vec_shuffle-30.ll Message-ID: <200902040116.n141GxBo024855@zion.cs.uiuc.edu> Author: wangmp Date: Tue Feb 3 19:16:59 2009 New Revision: 63702 URL: http://llvm.org/viewvc/llvm-project?rev=63702&view=rev Log: Fixes a case where we generate an incorrect mask for pshfhw in the presence of undefs and incorrectly determining if we have punpckldq. Added: llvm/trunk/test/CodeGen/X86/vec_shuffle-30.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=63702&r1=63701&r2=63702&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Feb 3 19:16:59 2009 @@ -2317,7 +2317,7 @@ if (!isUndefOrEqual(BitI, j)) return false; if (V2IsSplat) { - if (isUndefOrEqual(BitI1, NumElts)) + if (!isUndefOrEqual(BitI1, NumElts)) return false; } else { if (!isUndefOrEqual(BitI1, j + NumElts)) @@ -2652,9 +2652,10 @@ for (unsigned i = 7; i >= 4; --i) { unsigned Val = 0; SDValue Arg = N->getOperand(i); - if (Arg.getOpcode() != ISD::UNDEF) + if (Arg.getOpcode() != ISD::UNDEF) { Val = cast(Arg)->getZExtValue(); - Mask |= (Val - 4); + Mask |= (Val - 4); + } if (i != 4) Mask <<= 2; } @@ -4200,10 +4201,10 @@ // new vector_shuffle with the corrected mask. SDValue NewMask = NormalizeMask(PermMask, DAG); if (NewMask.getNode() != PermMask.getNode()) { - if (X86::isUNPCKLMask(PermMask.getNode(), true)) { + if (X86::isUNPCKLMask(NewMask.getNode(), true)) { SDValue NewMask = getUnpacklMask(NumElems, DAG, dl); return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask); - } else if (X86::isUNPCKHMask(PermMask.getNode(), true)) { + } else if (X86::isUNPCKHMask(NewMask.getNode(), true)) { SDValue NewMask = getUnpackhMask(NumElems, DAG, dl); return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask); } Added: llvm/trunk/test/CodeGen/X86/vec_shuffle-30.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-30.ll?rev=63702&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_shuffle-30.ll (added) +++ llvm/trunk/test/CodeGen/X86/vec_shuffle-30.ll Tue Feb 3 19:16:59 2009 @@ -0,0 +1,23 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 -disable-mmx -o %t -f +; RUN: grep pshufhw %t | grep 161 | count 1 +; RUN: grep pslldq %t | count 1 + + + +; Test case when creating pshufhw, we incorrectly set the higher order bit +; for an undef, +define void @test(<8 x i16>* %dest, <8 x i16> %in) { +entry: + %0 = load <8 x i16>* %dest + %1 = shufflevector <8 x i16> %0, <8 x i16> %in, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 13, i32 undef, i32 14, i32 14> + store <8 x i16> %1, <8 x i16>* %dest + ret void +} + +; A test case where we shouldn't generate a punpckldq but a pshufd and a pslldq +define void @test2(<4 x i32>* %dest, <4 x i32> %in) { +entry: + %0 = shufflevector <4 x i32> %in, <4 x i32> , <4 x i32> < i32 undef, i32 5, i32 undef, i32 2> + store <4 x i32> %0, <4 x i32>* %dest + ret void +} \ No newline at end of file From dalej at apple.com Tue Feb 3 19:17:06 2009 From: dalej at apple.com (Dale Johannesen) Date: Wed, 04 Feb 2009 01:17:06 -0000 Subject: [llvm-commits] [llvm] r63703 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp lib/Target/PIC16/PIC16ISelLowering.cpp lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200902040117.n141H68U024877@zion.cs.uiuc.edu> Author: johannes Date: Tue Feb 3 19:17:06 2009 New Revision: 63703 URL: http://llvm.org/viewvc/llvm-project?rev=63703&view=rev Log: Remove a few non-DebugLoc versions of node creation functions. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63703&r1=63702&r2=63703&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Feb 3 19:17:06 2009 @@ -306,6 +306,8 @@ int Offset = 0) { return getConstantPool(C, VT, Align, Offset, true); } + // When generating a branch to a BB, we don't in general know enough + // to provide debug info for the BB at that time, so keep this one around. SDValue getBasicBlock(MachineBasicBlock *MBB); SDValue getBasicBlock(MachineBasicBlock *MBB, DebugLoc dl); SDValue getExternalSymbol(const char *Sym, MVT VT); @@ -317,7 +319,7 @@ SDValue getRegister(unsigned Reg, MVT VT); SDValue getDbgStopPoint(SDValue Root, unsigned Line, unsigned Col, Value *CU); - SDValue getLabel(unsigned Opcode, SDValue Root, unsigned LabelID); +// SDValue getLabel(unsigned Opcode, SDValue Root, unsigned LabelID); SDValue getLabel(unsigned Opcode, DebugLoc dl, SDValue Root, unsigned LabelID); @@ -391,8 +393,8 @@ /// Returns the ConvertRndSat Note: Avoid using this node because it may /// disappear in the future and most targets don't support it. - SDValue getConvertRndSat(MVT VT, SDValue Val, SDValue DTy, SDValue STy, - SDValue Rnd, SDValue Sat, ISD::CvtCode Code); +// SDValue getConvertRndSat(MVT VT, SDValue Val, SDValue DTy, SDValue STy, +// SDValue Rnd, SDValue Sat, ISD::CvtCode Code); SDValue getConvertRndSat(MVT VT, DebugLoc dl, SDValue Val, SDValue DTy, SDValue STy, SDValue Rnd, SDValue Sat, ISD::CvtCode Code); @@ -493,36 +495,16 @@ SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5); - SDValue getMemcpy(SDValue Chain, SDValue Dst, SDValue Src, - SDValue Size, unsigned Align, bool AlwaysInline, - const Value *DstSV, uint64_t DstSVOff, - const Value *SrcSV, uint64_t SrcSVOff) { - return getMemcpy(Chain, DebugLoc::getUnknownLoc(), Dst, Src, Size, Align, - AlwaysInline, DstSV, DstSVOff, SrcSV, SrcSVOff); - } SDValue getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool AlwaysInline, const Value *DstSV, uint64_t DstSVOff, const Value *SrcSV, uint64_t SrcSVOff); - SDValue getMemmove(SDValue Chain, SDValue Dst, SDValue Src, - SDValue Size, unsigned Align, - const Value *DstSV, uint64_t DstOSVff, - const Value *SrcSV, uint64_t SrcSVOff) { - return getMemmove(Chain, DebugLoc::getUnknownLoc(), Dst, Src, Size, Align, - DstSV, DstOSVff, SrcSV, SrcSVOff); - } SDValue getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, const Value *DstSV, uint64_t DstOSVff, const Value *SrcSV, uint64_t SrcSVOff); - SDValue getMemset(SDValue Chain, SDValue Dst, SDValue Src, - SDValue Size, unsigned Align, - const Value *DstSV, uint64_t DstSVOff) { - return getMemset(Chain, DebugLoc::getUnknownLoc(), Dst, Src, Size, Align, - DstSV, DstSVOff); - } SDValue getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, const Value *DstSV, uint64_t DstSVOff); @@ -569,25 +551,17 @@ /// getVAArg - VAArg produces a result and token chain, and takes a pointer /// and a source value as input. - SDValue getVAArg(MVT VT, SDValue Chain, SDValue Ptr, - SDValue SV); SDValue getVAArg(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, SDValue SV); /// getAtomic - Gets a node for an atomic op, produces result and chain and /// takes 3 operands - SDValue getAtomic(unsigned Opcode, MVT MemVT, SDValue Chain, SDValue Ptr, - SDValue Cmp, SDValue Swp, const Value* PtrVal, - unsigned Alignment=0); SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, const Value* PtrVal, unsigned Alignment=0); /// getAtomic - Gets a node for an atomic op, produces result and chain and /// takes 2 operands. - SDValue getAtomic(unsigned Opcode, MVT MemVT, SDValue Chain, SDValue Ptr, - SDValue Val, const Value* PtrVal, - unsigned Alignment = 0); SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, const Value* PtrVal, unsigned Alignment = 0); @@ -624,9 +598,6 @@ /// getCall - Create a CALL node from the given information. /// - SDValue getCall(unsigned CallingConv, bool IsVarArgs, bool IsTailCall, - bool isInreg, SDVTList VTs, const SDValue *Operands, - unsigned NumOperands); SDValue getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, bool IsTailCall, bool isInreg, SDVTList VTs, const SDValue *Operands, unsigned NumOperands); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63703&r1=63702&r2=63703&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Feb 3 19:17:06 2009 @@ -1068,7 +1068,6 @@ return SDValue(N, 0); } - SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); @@ -1175,26 +1174,6 @@ return SDValue(CondCodeNodes[Cond], 0); } -SDValue SelectionDAG::getConvertRndSat(MVT VT, - SDValue Val, SDValue DTy, - SDValue STy, SDValue Rnd, SDValue Sat, - ISD::CvtCode Code) { - // If the src and dest types are the same, no conversion is necessary. - if (DTy == STy) - return Val; - - FoldingSetNodeID ID; - void* IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - CvtRndSatSDNode *N = NodeAllocator.Allocate(); - SDValue Ops[] = { Val, DTy, STy, Rnd, Sat }; - new (N) CvtRndSatSDNode(VT, Ops, 5, Code); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl, SDValue Val, SDValue DTy, SDValue STy, SDValue Rnd, SDValue Sat, @@ -1238,23 +1217,6 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getLabel(unsigned Opcode, - SDValue Root, - unsigned LabelID) { - FoldingSetNodeID ID; - SDValue Ops[] = { Root }; - AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); - ID.AddInteger(LabelID); - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - SDNode *N = NodeAllocator.Allocate(); - new (N) LabelSDNode(Opcode, Root, LabelID); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl, SDValue Root, unsigned LabelID) { @@ -3431,35 +3393,6 @@ return CallResult.second; } -SDValue SelectionDAG::getAtomic(unsigned Opcode, MVT MemVT, - SDValue Chain, - SDValue Ptr, SDValue Cmp, - SDValue Swp, const Value* PtrVal, - unsigned Alignment) { - assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op"); - assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); - - MVT VT = Cmp.getValueType(); - - if (Alignment == 0) // Ensure that codegen never sees alignment 0 - Alignment = getMVTAlignment(MemVT); - - SDVTList VTs = getVTList(VT, MVT::Other); - FoldingSetNodeID ID; - ID.AddInteger(MemVT.getRawBits()); - SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; - AddNodeIDNode(ID, Opcode, VTs, Ops, 4); - void* IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - SDNode* N = NodeAllocator.Allocate(); - new (N) AtomicSDNode(Opcode, VTs, MemVT, - Chain, Ptr, Cmp, Swp, PtrVal, Alignment); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain, SDValue Ptr, SDValue Cmp, @@ -3489,45 +3422,6 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getAtomic(unsigned Opcode, MVT MemVT, - SDValue Chain, - SDValue Ptr, SDValue Val, - const Value* PtrVal, - unsigned Alignment) { - assert((Opcode == ISD::ATOMIC_LOAD_ADD || - Opcode == ISD::ATOMIC_LOAD_SUB || - Opcode == ISD::ATOMIC_LOAD_AND || - Opcode == ISD::ATOMIC_LOAD_OR || - Opcode == ISD::ATOMIC_LOAD_XOR || - Opcode == ISD::ATOMIC_LOAD_NAND || - Opcode == ISD::ATOMIC_LOAD_MIN || - Opcode == ISD::ATOMIC_LOAD_MAX || - Opcode == ISD::ATOMIC_LOAD_UMIN || - Opcode == ISD::ATOMIC_LOAD_UMAX || - Opcode == ISD::ATOMIC_SWAP) && - "Invalid Atomic Op"); - - MVT VT = Val.getValueType(); - - if (Alignment == 0) // Ensure that codegen never sees alignment 0 - Alignment = getMVTAlignment(MemVT); - - SDVTList VTs = getVTList(VT, MVT::Other); - FoldingSetNodeID ID; - ID.AddInteger(MemVT.getRawBits()); - SDValue Ops[] = {Chain, Ptr, Val}; - AddNodeIDNode(ID, Opcode, VTs, Ops, 3); - void* IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - SDNode* N = NodeAllocator.Allocate(); - new (N) AtomicSDNode(Opcode, VTs, MemVT, - Chain, Ptr, Val, PtrVal, Alignment); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, @@ -3675,31 +3569,6 @@ } SDValue -SelectionDAG::getCall(unsigned CallingConv, bool IsVarArgs, bool IsTailCall, - bool IsInreg, SDVTList VTs, - const SDValue *Operands, unsigned NumOperands) { - // Do not include isTailCall in the folding set profile. - FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); - ID.AddInteger(CallingConv); - ID.AddInteger(IsVarArgs); - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { - // Instead of including isTailCall in the folding set, we just - // set the flag of the existing node. - if (!IsTailCall) - cast(E)->setNotTailCall(); - return SDValue(E, 0); - } - SDNode *N = NodeAllocator.Allocate(); - new (N) CallSDNode(CallingConv, IsVarArgs, IsTailCall, IsInreg, - VTs, Operands, NumOperands); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - -SDValue SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, bool IsTailCall, bool IsInreg, SDVTList VTs, const SDValue *Operands, unsigned NumOperands) { @@ -4058,13 +3927,6 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getVAArg(MVT VT, - SDValue Chain, SDValue Ptr, - SDValue SV) { - SDValue Ops[] = { Chain, Ptr, SV }; - return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3); -} - SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, SDValue SV) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63703&r1=63702&r2=63703&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Tue Feb 3 19:17:06 2009 @@ -3905,7 +3905,8 @@ if (DW && DW->ValidDebugInfo(RSI.getContext())) { unsigned LabelID = DW->RecordRegionStart(cast(RSI.getContext())); - DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), + getRoot(), LabelID)); } return 0; @@ -3916,7 +3917,8 @@ if (DW && DW->ValidDebugInfo(REI.getContext())) { unsigned LabelID = DW->RecordRegionEnd(cast(REI.getContext())); - DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), + getRoot(), LabelID)); } return 0; @@ -3941,7 +3943,8 @@ unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile); if (DW->getRecordSourceLineCount() != 1) - DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), + getRoot(), LabelID)); setCurDebugLoc(DebugLoc::get(DAG.getMachineFunction(). getOrCreateDebugLocID(SrcFile, Line, 0))); @@ -4386,7 +4389,8 @@ // Both PendingLoads and PendingExports must be flushed here; // this call might not return. (void)getRoot(); - DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel)); + DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(), + getControlRoot(), BeginLabel)); } std::pair Result = @@ -4405,7 +4409,8 @@ // Insert a label at the end of the invoke call to mark the try range. This // can be used to detect deletion of the invoke via the MachineModuleInfo. EndLabel = MMI->NextLabelID(); - DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel)); + DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(), + getRoot(), EndLabel)); // Inform MachineModuleInfo of range. MMI->addInvoke(LandingPad, BeginLabel, EndLabel); Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=63703&r1=63702&r2=63703&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Tue Feb 3 19:17:06 2009 @@ -1005,9 +1005,9 @@ SDVTList VTs = DAG.getVTList(&NodeTys[0], NodeTys.size()); SDValue NewCall = - DAG.getCall(TheCall->getCallingConv(), TheCall->isVarArg(), - TheCall->isTailCall(), TheCall->isInreg(), VTs, - &Ops[0], Ops.size()); + DAG.getCall(TheCall->getCallingConv(), TheCall->getDebugLoc(), + TheCall->isVarArg(), TheCall->isTailCall(), + TheCall->isInreg(), VTs, &Ops[0], Ops.size()); return NewCall; } Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=63703&r1=63702&r2=63703&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Feb 3 19:17:06 2009 @@ -2076,10 +2076,10 @@ static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, - unsigned Size) { + unsigned Size, DebugLoc dl) { SDValue SizeNode = DAG.getConstant(Size, MVT::i32); - return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), false, - NULL, 0, NULL, 0); + return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), + false, NULL, 0, NULL, 0); } /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of @@ -2118,6 +2118,7 @@ && CC == CallingConv::Fast && PerformTailCallOpt; SDValue Callee = TheCall->getCallee(); unsigned NumOps = TheCall->getNumArgs(); + DebugLoc dl = TheCall->getDebugLoc(); bool isMachoABI = Subtarget.isMachoABI(); bool isELF32_ABI = Subtarget.isELF32_ABI(); @@ -2251,7 +2252,7 @@ SDValue AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const); SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, CallSeqStart.getNode()->getOperand(0), - Flags, DAG, Size); + Flags, DAG, Size, dl); // This must go outside the CALLSEQ_START..END. SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, CallSeqStart.getNode()->getOperand(1)); @@ -2267,7 +2268,7 @@ // registers. (This is not what the doc says.) SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, CallSeqStart.getNode()->getOperand(0), - Flags, DAG, Size); + Flags, DAG, Size, dl); // This must go outside the CALLSEQ_START..END. SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, CallSeqStart.getNode()->getOperand(1)); From dalej at apple.com Tue Feb 3 19:33:21 2009 From: dalej at apple.com (Dale Johannesen) Date: Wed, 04 Feb 2009 01:33:21 -0000 Subject: [llvm-commits] [llvm] r63704 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Message-ID: <200902040133.n141XL3J025326@zion.cs.uiuc.edu> Author: johannes Date: Tue Feb 3 19:33:20 2009 New Revision: 63704 URL: http://llvm.org/viewvc/llvm-project?rev=63704&view=rev Log: Check in file I forgot. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=63704&r1=63703&r2=63704&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Feb 3 19:33:20 2009 @@ -150,8 +150,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { SDValue Op2 = GetPromotedInteger(N->getOperand(2)); SDValue Op3 = GetPromotedInteger(N->getOperand(3)); - SDValue Res = DAG.getAtomic(N->getOpcode(), N->getMemoryVT(), - N->getChain(), N->getBasePtr(), + SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), + N->getMemoryVT(), N->getChain(), N->getBasePtr(), Op2, Op3, N->getSrcValue(), N->getAlignment()); // Legalized the chain result - switch anything that used the old chain to // use the new one. @@ -1248,7 +1248,7 @@ Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2); SDValue Cmp = - DAG.getSetCC(TLI.getSetCCResultType(LoOps[0].getValueType()), + DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()), LoOps[0], LoOps[1], ISD::SETULT); SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, DAG.getConstant(1, NVT), From dalej at apple.com Tue Feb 3 19:48:28 2009 From: dalej at apple.com (Dale Johannesen) Date: Wed, 04 Feb 2009 01:48:28 -0000 Subject: [llvm-commits] [llvm] r63705 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp lib/Target/Alpha/AlphaISelLowering.cpp lib/Target/CellSPU/SPUISelLowering.cpp lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200902040148.n141mT1F025860@zion.cs.uiuc.edu> Author: johannes Date: Tue Feb 3 19:48:28 2009 New Revision: 63705 URL: http://llvm.org/viewvc/llvm-project?rev=63705&view=rev Log: Remove some more non-DebugLoc versions of construction functions, with callers adjusted to fit. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63705&r1=63704&r2=63705&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Feb 3 19:48:28 2009 @@ -319,7 +319,6 @@ SDValue getRegister(unsigned Reg, MVT VT); SDValue getDbgStopPoint(SDValue Root, unsigned Line, unsigned Col, Value *CU); -// SDValue getLabel(unsigned Opcode, SDValue Root, unsigned LabelID); SDValue getLabel(unsigned Opcode, DebugLoc dl, SDValue Root, unsigned LabelID); @@ -393,8 +392,6 @@ /// Returns the ConvertRndSat Note: Avoid using this node because it may /// disappear in the future and most targets don't support it. -// SDValue getConvertRndSat(MVT VT, SDValue Val, SDValue DTy, SDValue STy, -// SDValue Rnd, SDValue Sat, ISD::CvtCode Code); SDValue getConvertRndSat(MVT VT, DebugLoc dl, SDValue Val, SDValue DTy, SDValue STy, SDValue Rnd, SDValue Sat, ISD::CvtCode Code); @@ -512,11 +509,6 @@ /// getSetCC - Helper function to make it easier to build SetCC's if you just /// have an ISD::CondCode instead of an SDValue. /// - SDValue getSetCC(MVT VT, SDValue LHS, SDValue RHS, - ISD::CondCode Cond) { - return getNode(ISD::SETCC, DebugLoc::getUnknownLoc(), VT, - LHS, RHS, getCondCode(Cond)); - } SDValue getSetCC(DebugLoc DL, MVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond) { return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond)); @@ -525,11 +517,6 @@ /// getVSetCC - Helper function to make it easier to build VSetCC's nodes /// if you just have an ISD::CondCode instead of an SDValue. /// - SDValue getVSetCC(MVT VT, SDValue LHS, SDValue RHS, - ISD::CondCode Cond) { - return getNode(ISD::VSETCC, DebugLoc::getUnknownLoc(), VT, - LHS, RHS, getCondCode(Cond)); - } SDValue getVSetCC(DebugLoc DL, MVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond) { return getNode(ISD::VSETCC, DL, VT, LHS, RHS, getCondCode(Cond)); @@ -538,11 +525,6 @@ /// getSelectCC - Helper function to make it easier to build SelectCC's if you /// just have an ISD::CondCode instead of an SDValue. /// - SDValue getSelectCC(SDValue LHS, SDValue RHS, - SDValue True, SDValue False, ISD::CondCode Cond) { - return getNode(ISD::SELECT_CC, DebugLoc::getUnknownLoc(), True.getValueType(), - LHS, RHS, True, False, getCondCode(Cond)); - } SDValue getSelectCC(DebugLoc DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond) { return getNode(ISD::SELECT_CC, DL, True.getValueType(), @@ -568,12 +550,6 @@ /// getMemIntrinsicNode - Creates a MemIntrinsicNode that may produce a /// result and takes a list of operands. - SDValue getMemIntrinsicNode(unsigned Opcode, - const MVT *VTs, unsigned NumVTs, - const SDValue *Ops, unsigned NumOps, - MVT MemVT, const Value *srcValue, int SVOff, - unsigned Align = 0, bool Vol = false, - bool ReadMem = true, bool WriteMem = true); SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, const MVT *VTs, unsigned NumVTs, const SDValue *Ops, unsigned NumOps, @@ -581,11 +557,6 @@ unsigned Align = 0, bool Vol = false, bool ReadMem = true, bool WriteMem = true); - SDValue getMemIntrinsicNode(unsigned Opcode, SDVTList VTList, - const SDValue *Ops, unsigned NumOps, - MVT MemVT, const Value *srcValue, int SVOff, - unsigned Align = 0, bool Vol = false, - bool ReadMem = true, bool WriteMem = true); SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, const SDValue *Ops, unsigned NumOps, MVT MemVT, const Value *srcValue, int SVOff, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63705&r1=63704&r2=63705&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Feb 3 19:48:28 2009 @@ -3489,18 +3489,6 @@ } SDValue -SelectionDAG::getMemIntrinsicNode(unsigned Opcode, - const MVT *VTs, unsigned NumVTs, - const SDValue *Ops, unsigned NumOps, - MVT MemVT, const Value *srcValue, int SVOff, - unsigned Align, bool Vol, - bool ReadMem, bool WriteMem) { - return getMemIntrinsicNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps, - MemVT, srcValue, SVOff, Align, Vol, - ReadMem, WriteMem); -} - -SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, const MVT *VTs, unsigned NumVTs, const SDValue *Ops, unsigned NumOps, @@ -3513,34 +3501,6 @@ } SDValue -SelectionDAG::getMemIntrinsicNode(unsigned Opcode, SDVTList VTList, - const SDValue *Ops, unsigned NumOps, - MVT MemVT, const Value *srcValue, int SVOff, - unsigned Align, bool Vol, - bool ReadMem, bool WriteMem) { - // Memoize the node unless it returns a flag. - MemIntrinsicSDNode *N; - if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { - FoldingSetNodeID ID; - AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - - N = NodeAllocator.Allocate(); - new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, - srcValue, SVOff, Align, Vol, ReadMem, WriteMem); - CSEMap.InsertNode(N, IP); - } else { - N = NodeAllocator.Allocate(); - new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, - srcValue, SVOff, Align, Vol, ReadMem, WriteMem); - } - AllNodes.push_back(N); - return SDValue(N, 0); -} - -SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, const SDValue *Ops, unsigned NumOps, MVT MemVT, const Value *srcValue, int SVOff, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63705&r1=63704&r2=63705&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Tue Feb 3 19:48:28 2009 @@ -1318,6 +1318,7 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { SDValue Cond; SDValue CondLHS = getValue(CB.CmpLHS); + DebugLoc dl = getCurDebugLoc(); // Build the setcc now. if (CB.CmpMHS == NULL) { @@ -1327,10 +1328,9 @@ Cond = CondLHS; else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { SDValue True = DAG.getConstant(1, CondLHS.getValueType()); - Cond = DAG.getNode(ISD::XOR, getCurDebugLoc(), - CondLHS.getValueType(), CondLHS, True); + Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); } else - Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); + Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); } else { assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); @@ -1341,11 +1341,12 @@ MVT VT = CmpOp.getValueType(); if (cast(CB.CmpLHS)->isMinValue(true)) { - Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); + Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), + ISD::SETLE); } else { - SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), + SDValue SUB = DAG.getNode(ISD::SUB, dl, VT, CmpOp, DAG.getConstant(Low, VT)); - Cond = DAG.getSetCC(MVT::i1, SUB, + Cond = DAG.getSetCC(dl, MVT::i1, SUB, DAG.getConstant(High-Low, VT), ISD::SETULE); } } @@ -1366,10 +1367,9 @@ if (CB.TrueBB == NextBlock) { std::swap(CB.TrueBB, CB.FalseBB); SDValue True = DAG.getConstant(1, Cond.getValueType()); - Cond = DAG.getNode(ISD::XOR, getCurDebugLoc(), - Cond.getValueType(), Cond, True); + Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); } - SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), + SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, MVT::Other, getControlRoot(), Cond, DAG.getBasicBlock(CB.TrueBB)); @@ -1385,7 +1385,7 @@ if (CB.FalseBB == NextBlock) DAG.setRoot(BrCond); else - DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, + DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, DAG.getBasicBlock(CB.FalseBB))); } } @@ -1435,7 +1435,8 @@ // Emit the range check for the jump table, and branch to the default block // for the switch statement if the value being switched on exceeds the largest // case in the switch. - SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB.getValueType()), SUB, + SDValue CMP = DAG.getSetCC(getCurDebugLoc(), + TLI.getSetCCResultType(SUB.getValueType()), SUB, DAG.getConstant(JTH.Last-JTH.First,VT), ISD::SETUGT); @@ -1467,8 +1468,9 @@ DAG.getConstant(B.First, VT)); // Check range - SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB.getValueType()), SUB, - DAG.getConstant(B.Range, VT), + SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), + TLI.getSetCCResultType(SUB.getValueType()), + SUB, DAG.getConstant(B.Range, VT), ISD::SETUGT); SDValue ShiftOp; @@ -1522,7 +1524,8 @@ SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), TLI.getPointerTy(), SwitchVal, DAG.getConstant(B.Mask, TLI.getPointerTy())); - SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp.getValueType()), + SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(), + TLI.getSetCCResultType(AndOp.getValueType()), AndOp, DAG.getConstant(0, TLI.getPointerTy()), ISD::SETNE); @@ -2191,7 +2194,7 @@ SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); ISD::CondCode Opcode = getICmpCondCode(predicate); - setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); + setValue(&I, DAG.getSetCC(getCurDebugLoc(),MVT::i1, Op1, Op2, Opcode)); } void SelectionDAGLowering::visitFCmp(User &I) { @@ -2203,7 +2206,7 @@ SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); ISD::CondCode Condition = getFCmpCondCode(predicate); - setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); + setValue(&I, DAG.getSetCC(getCurDebugLoc(), MVT::i1, Op1, Op2, Condition)); } void SelectionDAGLowering::visitVICmp(User &I) { @@ -2215,7 +2218,8 @@ SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); ISD::CondCode Opcode = getICmpCondCode(predicate); - setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode)); + setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(), + Op1, Op2, Opcode)); } void SelectionDAGLowering::visitVFCmp(User &I) { @@ -2229,7 +2233,7 @@ ISD::CondCode Condition = getFCmpCondCode(predicate); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition)); + setValue(&I, DAG.getVSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); } void SelectionDAGLowering::visitSelect(User &I) { Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=63705&r1=63704&r2=63705&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Tue Feb 3 19:48:28 2009 @@ -434,26 +434,27 @@ Chain = N->getOperand(0); SDValue VAListP = N->getOperand(1); const Value *VAListS = cast(N->getOperand(2))->getValue(); + DebugLoc dl = N->getDebugLoc(); - SDValue Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0); - SDValue Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP, + SDValue Base = DAG.getLoad(MVT::i64, dl, Chain, VAListP, VAListS, 0); + SDValue Tmp = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP, DAG.getConstant(8, MVT::i64)); - SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1), + SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Base.getValue(1), Tmp, NULL, 0, MVT::i32); - DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset); + DataPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Base, Offset); if (N->getValueType(0).isFloatingPoint()) { //if fp && Offset < 6*8, then subtract 6*8 from DataPtr - SDValue FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr, + SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, MVT::i64, DataPtr, DAG.getConstant(8*6, MVT::i64)); - SDValue CC = DAG.getSetCC(MVT::i64, Offset, + SDValue CC = DAG.getSetCC(dl, MVT::i64, Offset, DAG.getConstant(8*6, MVT::i64), ISD::SETLT); - DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr); + DataPtr = DAG.getNode(ISD::SELECT, dl, MVT::i64, CC, FPDataPtr, DataPtr); } - SDValue NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset, + SDValue NewOffset = DAG.getNode(ISD::ADD, dl, MVT::i64, Offset, DAG.getConstant(8, MVT::i64)); - Chain = DAG.getTruncStore(Offset.getValue(1), NewOffset, Tmp, NULL, 0, + Chain = DAG.getTruncStore(Offset.getValue(1), dl, NewOffset, Tmp, NULL, 0, MVT::i32); } Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=63705&r1=63704&r2=63705&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Tue Feb 3 19:48:28 2009 @@ -2455,6 +2455,7 @@ static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) { CondCodeSDNode *CC = dyn_cast(Op.getOperand(2)); + DebugLoc dl = Op.getNode()->getDebugLoc(); assert(CC != 0 && "LowerSETCC: CondCodeSDNode should not be null here!\n"); SDValue lhs = Op.getOperand(0); @@ -2468,35 +2469,35 @@ // Take advantage of the fact that (truncate (sra arg, 32)) is efficiently // selected to a NOP: - SDValue i64lhs = DAG.getNode(ISD::BIT_CONVERT, IntVT, lhs); + SDValue i64lhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, lhs); SDValue lhsHi32 = - DAG.getNode(ISD::TRUNCATE, MVT::i32, - DAG.getNode(ISD::SRL, IntVT, + DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, + DAG.getNode(ISD::SRL, dl, IntVT, i64lhs, DAG.getConstant(32, MVT::i32))); SDValue lhsHi32abs = - DAG.getNode(ISD::AND, MVT::i32, + DAG.getNode(ISD::AND, dl, MVT::i32, lhsHi32, DAG.getConstant(0x7fffffff, MVT::i32)); SDValue lhsLo32 = - DAG.getNode(ISD::TRUNCATE, MVT::i32, i64lhs); + DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, i64lhs); // SETO and SETUO only use the lhs operand: if (CC->get() == ISD::SETO) { // Evaluates to true if Op0 is not [SQ]NaN - lowers to the inverse of // SETUO APInt ccResultAllOnes = APInt::getAllOnesValue(ccResultVT.getSizeInBits()); - return DAG.getNode(ISD::XOR, ccResultVT, - DAG.getSetCC(ccResultVT, + return DAG.getNode(ISD::XOR, dl, ccResultVT, + DAG.getSetCC(dl, ccResultVT, lhs, DAG.getConstantFP(0.0, lhsVT), ISD::SETUO), DAG.getConstant(ccResultAllOnes, ccResultVT)); } else if (CC->get() == ISD::SETUO) { // Evaluates to true if Op0 is [SQ]NaN - return DAG.getNode(ISD::AND, ccResultVT, - DAG.getSetCC(ccResultVT, + return DAG.getNode(ISD::AND, dl, ccResultVT, + DAG.getSetCC(dl, ccResultVT, lhsHi32abs, DAG.getConstant(0x7ff00000, MVT::i32), ISD::SETGE), - DAG.getSetCC(ccResultVT, + DAG.getSetCC(dl, ccResultVT, lhsLo32, DAG.getConstant(0, MVT::i32), ISD::SETGT)); @@ -2504,26 +2505,26 @@ SDValue i64rhs = DAG.getNode(ISD::BIT_CONVERT, IntVT, rhs); SDValue rhsHi32 = - DAG.getNode(ISD::TRUNCATE, MVT::i32, - DAG.getNode(ISD::SRL, IntVT, + DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, + DAG.getNode(ISD::SRL, dl, IntVT, i64rhs, DAG.getConstant(32, MVT::i32))); // If a value is negative, subtract from the sign magnitude constant: SDValue signMag2TC = DAG.getConstant(0x8000000000000000ULL, IntVT); // Convert the sign-magnitude representation into 2's complement: - SDValue lhsSelectMask = DAG.getNode(ISD::SRA, ccResultVT, + SDValue lhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT, lhsHi32, DAG.getConstant(31, MVT::i32)); - SDValue lhsSignMag2TC = DAG.getNode(ISD::SUB, IntVT, signMag2TC, i64lhs); + SDValue lhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64lhs); SDValue lhsSelect = - DAG.getNode(ISD::SELECT, IntVT, + DAG.getNode(ISD::SELECT, dl, IntVT, lhsSelectMask, lhsSignMag2TC, i64lhs); - SDValue rhsSelectMask = DAG.getNode(ISD::SRA, ccResultVT, + SDValue rhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT, rhsHi32, DAG.getConstant(31, MVT::i32)); - SDValue rhsSignMag2TC = DAG.getNode(ISD::SUB, IntVT, signMag2TC, i64rhs); + SDValue rhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64rhs); SDValue rhsSelect = - DAG.getNode(ISD::SELECT, IntVT, + DAG.getNode(ISD::SELECT, dl, IntVT, rhsSelectMask, rhsSignMag2TC, i64rhs); unsigned compareOp; @@ -2554,19 +2555,20 @@ } SDValue result = - DAG.getSetCC(ccResultVT, lhsSelect, rhsSelect, (ISD::CondCode) compareOp); + DAG.getSetCC(dl, ccResultVT, lhsSelect, rhsSelect, + (ISD::CondCode) compareOp); if ((CC->get() & 0x8) == 0) { // Ordered comparison: - SDValue lhsNaN = DAG.getSetCC(ccResultVT, + SDValue lhsNaN = DAG.getSetCC(dl, ccResultVT, lhs, DAG.getConstantFP(0.0, MVT::f64), ISD::SETO); - SDValue rhsNaN = DAG.getSetCC(ccResultVT, + SDValue rhsNaN = DAG.getSetCC(dl, ccResultVT, rhs, DAG.getConstantFP(0.0, MVT::f64), ISD::SETO); - SDValue ordered = DAG.getNode(ISD::AND, ccResultVT, lhsNaN, rhsNaN); + SDValue ordered = DAG.getNode(ISD::AND, dl, ccResultVT, lhsNaN, rhsNaN); - result = DAG.getNode(ISD::AND, ccResultVT, ordered, result); + result = DAG.getNode(ISD::AND, dl, ccResultVT, ordered, result); } return result; Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=63705&r1=63704&r2=63705&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Feb 3 19:48:28 2009 @@ -1173,6 +1173,7 @@ SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { ISD::CondCode CC = cast(Op.getOperand(2))->get(); + DebugLoc dl = Op.getNode()->getDebugLoc(); // If we're comparing for equality to zero, expose the fact that this is // implented as a ctlz/srl pair on ppc, so that the dag combiner can @@ -1183,13 +1184,13 @@ SDValue Zext = Op.getOperand(0); if (VT.bitsLT(MVT::i32)) { VT = MVT::i32; - Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); + Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); } unsigned Log2b = Log2_32(VT.getSizeInBits()); - SDValue Clz = DAG.getNode(ISD::CTLZ, VT, Zext); - SDValue Scc = DAG.getNode(ISD::SRL, VT, Clz, + SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); + SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, DAG.getConstant(Log2b, MVT::i32)); - return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); + return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); } // Leave comparisons against 0 and -1 alone for now, since they're usually // optimized. FIXME: revisit this when we can custom lower all setcc @@ -1206,9 +1207,9 @@ MVT LHSVT = Op.getOperand(0).getValueType(); if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { MVT VT = Op.getValueType(); - SDValue Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), + SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), Op.getOperand(1)); - return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); + return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); } return SDValue(); } @@ -3035,6 +3036,7 @@ } SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); MVT VT = Op.getValueType(); unsigned BitWidth = VT.getSizeInBits(); assert(Op.getNumOperands() == 3 && @@ -3047,16 +3049,16 @@ SDValue Amt = Op.getOperand(2); MVT AmtVT = Amt.getValueType(); - SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT, + SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, DAG.getConstant(BitWidth, AmtVT), Amt); - SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt); - SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1); - SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); - SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, + SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); + SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); + SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); + SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, DAG.getConstant(-BitWidth, AmtVT)); - SDValue Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5); - SDValue OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt); - SDValue OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT), + SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); + SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); + SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), Tmp4, Tmp6, ISD::SETLE); SDValue OutOps[] = { OutLo, OutHi }; return DAG.getMergeValues(OutOps, 2); From sabre at nondot.org Tue Feb 3 19:51:53 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 04 Feb 2009 01:51:53 -0000 Subject: [llvm-commits] [llvm] r63706 - /llvm/trunk/include/llvm/Target/TargetAsmInfo.h Message-ID: <200902040151.n141prmi025973@zion.cs.uiuc.edu> Author: lattner Date: Tue Feb 3 19:51:53 2009 New Revision: 63706 URL: http://llvm.org/viewvc/llvm-project?rev=63706&view=rev Log: add a friend needed by a stringmap change. Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=63706&r1=63705&r2=63706&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Tue Feb 3 19:51:53 2009 @@ -105,12 +105,14 @@ class Section { friend class TargetAsmInfo; friend class StringMapEntry
    ; + friend class StringMap
    ; std::string Name; unsigned Flags; - explicit Section(unsigned F = SectionFlags::Invalid):Flags(F) { } + public: + bool isNamed() const { return Flags & SectionFlags::Named; } unsigned getEntitySize() const { return (Flags >> 24) & 0xFF; } From sabre at nondot.org Tue Feb 3 19:54:10 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 04 Feb 2009 01:54:10 -0000 Subject: [llvm-commits] [llvm] r63707 - /llvm/trunk/include/llvm/ADT/StringMap.h Message-ID: <200902040154.n141sA36026048@zion.cs.uiuc.edu> Author: lattner Date: Tue Feb 3 19:54:10 2009 New Revision: 63707 URL: http://llvm.org/viewvc/llvm-project?rev=63707&view=rev Log: fix a pretty serious bug in StringMap where GetOrCreate(strstart,strend, z) would not set new values to Z. Modified: llvm/trunk/include/llvm/ADT/StringMap.h Modified: llvm/trunk/include/llvm/ADT/StringMap.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/StringMap.h?rev=63707&r1=63706&r2=63707&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/StringMap.h (original) +++ llvm/trunk/include/llvm/ADT/StringMap.h Tue Feb 3 19:54:10 2009 @@ -34,6 +34,7 @@ public: template static void Initialize(StringMapEntry &T, InitTy InitVal) { + T.second = InitVal; } }; @@ -195,7 +196,7 @@ } static StringMapEntry *Create(const char *KeyStart, const char *KeyEnd) { - return Create(KeyStart, KeyEnd, 0); + return Create(KeyStart, KeyEnd, ValueTy()); } /// GetStringMapEntryFromValue - Given a value that is known to be embedded @@ -240,6 +241,17 @@ StringMap() : StringMapImpl(static_cast(sizeof(MapEntryTy))) {} explicit StringMap(unsigned InitialSize) : StringMapImpl(InitialSize, static_cast(sizeof(MapEntryTy))) {} + explicit StringMap(const StringMap &RHS) + : StringMapImpl(static_cast(sizeof(MapEntryTy))) { + assert(RHS.empty() && + "Copy ctor from non-empty stringmap not implemented yet!"); + } + void operator=(const StringMap &RHS) { + assert(RHS.empty() && + "assignment from non-empty stringmap not implemented yet!"); + clear(); + } + AllocatorTy &getAllocator() { return Allocator; } const AllocatorTy &getAllocator() const { return Allocator; } @@ -292,13 +304,11 @@ } ValueTy& operator[](const char *Key) { - value_type& entry = GetOrCreateValue(Key, Key + strlen(Key)); - return entry.getValue(); + return GetOrCreateValue(Key, Key + strlen(Key)).getValue(); } ValueTy& operator[](const std::string &Key) { const char* key_start = (Key.empty() ? NULL : &Key[0]); - value_type& entry = GetOrCreateValue(key_start, key_start + Key.size()); - return entry.getValue(); + return GetOrCreateValue(key_start, key_start + Key.size()).getValue(); } size_type count(const char *KeyStart, const char *KeyEnd) const { @@ -378,7 +388,7 @@ StringMapEntry &GetOrCreateValue(const char *KeyStart, const char *KeyEnd) { - return GetOrCreateValue(KeyStart, KeyEnd, 0); + return GetOrCreateValue(KeyStart, KeyEnd, ValueTy()); } /// remove - Remove the specified key/value pair from the map, but do not @@ -411,9 +421,6 @@ clear(); free(TheTable); } -private: - StringMap(const StringMap &); // FIXME: Implement. - void operator=(const StringMap &); // FIXME: Implement. }; From dalej at apple.com Tue Feb 3 20:34:38 2009 From: dalej at apple.com (Dale Johannesen) Date: Wed, 04 Feb 2009 02:34:38 -0000 Subject: [llvm-commits] [llvm] r63716 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/Target/Alpha/AlphaISelLowering.cpp lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/Sparc/SparcISelLowering.cpp Message-ID: <200902040234.n142Ydrj027298@zion.cs.uiuc.edu> Author: johannes Date: Tue Feb 3 20:34:38 2009 New Revision: 63716 URL: http://llvm.org/viewvc/llvm-project?rev=63716&view=rev Log: Remove non-DebugLoc forms of the exotic forms of Lod and Sto; patch uses. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63716&r1=63715&r2=63716&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Feb 3 20:34:38 2009 @@ -582,16 +582,10 @@ SDValue getLoad(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, const Value *SV, int SVOffset, bool isVolatile=false, unsigned Alignment=0); - SDValue getExtLoad(ISD::LoadExtType ExtType, MVT VT, - SDValue Chain, SDValue Ptr, const Value *SV, - int SVOffset, MVT EVT, bool isVolatile=false, - unsigned Alignment=0); SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT, SDValue Chain, SDValue Ptr, const Value *SV, int SVOffset, MVT EVT, bool isVolatile=false, unsigned Alignment=0); - SDValue getIndexedLoad(SDValue OrigLoad, SDValue Base, - SDValue Offset, ISD::MemIndexedMode AM); SDValue getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM); SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, @@ -613,14 +607,9 @@ SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr, const Value *SV, int SVOffset, bool isVolatile=false, unsigned Alignment=0); - SDValue getTruncStore(SDValue Chain, SDValue Val, SDValue Ptr, - const Value *SV, int SVOffset, MVT TVT, - bool isVolatile=false, unsigned Alignment=0); SDValue getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr, const Value *SV, int SVOffset, MVT TVT, bool isVolatile=false, unsigned Alignment=0); - SDValue getIndexedStore(SDValue OrigStoe, SDValue Base, - SDValue Offset, ISD::MemIndexedMode AM); SDValue getIndexedStore(SDValue OrigStoe, DebugLoc dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63716&r1=63715&r2=63716&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Feb 3 20:34:38 2009 @@ -585,7 +585,8 @@ SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); unsigned Alignment = 1 << cast(CPIdx)->getAlignment(); if (Extend) - return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(), + return DAG.getExtLoad(ISD::EXTLOAD, CFP->getDebugLoc(), + OrigVT, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, VT, false, Alignment); return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63716&r1=63715&r2=63716&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Feb 3 20:34:38 2009 @@ -3669,16 +3669,6 @@ SV, SVOffset, VT, isVolatile, Alignment); } -SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT, - SDValue Chain, SDValue Ptr, - const Value *SV, - int SVOffset, MVT EVT, - bool isVolatile, unsigned Alignment) { - SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); - return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef, - SV, SVOffset, EVT, isVolatile, Alignment); -} - SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT, SDValue Chain, SDValue Ptr, const Value *SV, @@ -3690,18 +3680,6 @@ } SDValue -SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base, - SDValue Offset, ISD::MemIndexedMode AM) { - LoadSDNode *LD = cast(OrigLoad); - assert(LD->getOffset().getOpcode() == ISD::UNDEF && - "Load is already a indexed load!"); - return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), - LD->getChain(), Base, Offset, LD->getSrcValue(), - LD->getSrcValueOffset(), LD->getMemoryVT(), - LD->isVolatile(), LD->getAlignment()); -} - -SDValue SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) { LoadSDNode *LD = cast(OrigLoad); @@ -3767,41 +3745,6 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val, - SDValue Ptr, const Value *SV, - int SVOffset, MVT SVT, - bool isVolatile, unsigned Alignment) { - MVT VT = Val.getValueType(); - - if (VT == SVT) - return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment); - - assert(VT.bitsGT(SVT) && "Not a truncation?"); - assert(VT.isInteger() == SVT.isInteger() && - "Can't do FP-INT conversion!"); - - if (Alignment == 0) // Ensure that codegen never sees alignment 0 - Alignment = getMVTAlignment(VT); - - SDVTList VTs = getVTList(MVT::Other); - SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); - SDValue Ops[] = { Chain, Val, Ptr, Undef }; - FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); - ID.AddInteger(SVT.getRawBits()); - ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, - isVolatile, Alignment)); - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - SDNode *N = NodeAllocator.Allocate(); - new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, true, - SVT, SV, SVOffset, Alignment, isVolatile); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr, const Value *SV, int SVOffset, MVT SVT, @@ -3838,31 +3781,6 @@ } SDValue -SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base, - SDValue Offset, ISD::MemIndexedMode AM) { - StoreSDNode *ST = cast(OrigStore); - assert(ST->getOffset().getOpcode() == ISD::UNDEF && - "Store is already a indexed store!"); - SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); - SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; - FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); - ID.AddInteger(ST->getMemoryVT().getRawBits()); - ID.AddInteger(ST->getRawSubclassData()); - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - SDNode *N = NodeAllocator.Allocate(); - new (N) StoreSDNode(Ops, VTs, AM, - ST->isTruncatingStore(), ST->getMemoryVT(), - ST->getSrcValue(), ST->getSrcValueOffset(), - ST->getAlignment(), ST->isVolatile()); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - -SDValue SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) { StoreSDNode *ST = cast(OrigStore); Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=63716&r1=63715&r2=63716&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Tue Feb 3 20:34:38 2009 @@ -461,6 +461,7 @@ /// LowerOperation - Provide custom lowering hooks for some operations. /// SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); switch (Op.getOpcode()) { default: assert(0 && "Wasn't expecting to be able to lower this!"); case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG, @@ -573,10 +574,10 @@ SDValue Result; if (Op.getValueType() == MVT::i32) - Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Chain, DataPtr, + Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Chain, DataPtr, NULL, 0, MVT::i32); else - Result = DAG.getLoad(Op.getValueType(), Chain, DataPtr, NULL, 0); + Result = DAG.getLoad(Op.getValueType(), dl, Chain, DataPtr, NULL, 0); return Result; } case ISD::VACOPY: { @@ -586,14 +587,15 @@ const Value *DestS = cast(Op.getOperand(3))->getValue(); const Value *SrcS = cast(Op.getOperand(4))->getValue(); - SDValue Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0); - SDValue Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0); - SDValue NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP, + SDValue Val = DAG.getLoad(getPointerTy(), dl, Chain, SrcP, SrcS, 0); + SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP, DestS, 0); + SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP, DAG.getConstant(8, MVT::i64)); - Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32); - SDValue NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP, + Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Result, + NP, NULL,0, MVT::i32); + SDValue NPD = DAG.getNode(ISD::ADD, dl, MVT::i64, DestP, DAG.getConstant(8, MVT::i64)); - return DAG.getTruncStore(Val.getValue(1), Val, NPD, NULL, 0, MVT::i32); + return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD, NULL, 0, MVT::i32); } case ISD::VASTART: { SDValue Chain = Op.getOperand(0); @@ -602,10 +604,10 @@ // vastart stores the address of the VarArgsBase and VarArgsOffset SDValue FR = DAG.getFrameIndex(VarArgsBase, MVT::i64); - SDValue S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0); - SDValue SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP, + SDValue S1 = DAG.getStore(Chain, dl, FR, VAListP, VAListS, 0); + SDValue SA2 = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP, DAG.getConstant(8, MVT::i64)); - return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64), + return DAG.getTruncStore(S1, dl, DAG.getConstant(VarArgsOffset, MVT::i64), SA2, NULL, 0, MVT::i32); } case ISD::RETURNADDR: Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=63716&r1=63715&r2=63716&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Feb 3 20:34:38 2009 @@ -1399,6 +1399,7 @@ SmallVector ArgValues; SDValue Root = Op.getOperand(0); bool isVarArg = cast(Op.getOperand(2))->getZExtValue() != 0; + DebugLoc dl = Op.getNode()->getDebugLoc(); MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); bool isPPC64 = PtrVT == MVT::i64; @@ -1551,8 +1552,8 @@ if (GPR_idx != Num_GPR_Regs) { unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); RegInfo.addLiveIn(GPR[GPR_idx], VReg); - SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT); - SDValue Store = DAG.getTruncStore(Val.getValue(1), Val, FIN, + SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT); + SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 ); MemOps.push_back(Store); ++GPR_idx; @@ -1571,8 +1572,8 @@ RegInfo.addLiveIn(GPR[GPR_idx], VReg); int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset); SDValue FIN = DAG.getFrameIndex(FI, PtrVT); - SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT); - SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); + SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT); + SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); MemOps.push_back(Store); ++GPR_idx; if (isMachoABI) ArgOffset += PtrByteSize; @@ -1594,7 +1595,7 @@ if (GPR_idx != Num_GPR_Regs) { unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); RegInfo.addLiveIn(GPR[GPR_idx], VReg); - ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); + ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); ++GPR_idx; } else { needsLoad = true; @@ -1612,19 +1613,19 @@ if (GPR_idx != Num_GPR_Regs) { unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); RegInfo.addLiveIn(GPR[GPR_idx], VReg); - ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); + ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64); if (ObjectVT == MVT::i32) { // PPC64 passes i8, i16, and i32 values in i64 registers. Promote // value to MVT::i64 and then truncate to the correct register size. if (Flags.isSExt()) - ArgVal = DAG.getNode(ISD::AssertSext, MVT::i64, ArgVal, + ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, DAG.getValueType(ObjectVT)); else if (Flags.isZExt()) - ArgVal = DAG.getNode(ISD::AssertZext, MVT::i64, ArgVal, + ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, DAG.getValueType(ObjectVT)); - ArgVal = DAG.getNode(ISD::TRUNCATE, MVT::i32, ArgVal); + ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); } ++GPR_idx; @@ -1652,7 +1653,7 @@ else VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); RegInfo.addLiveIn(FPR[FPR_idx], VReg); - ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); + ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT); ++FPR_idx; } else { needsLoad = true; @@ -1673,7 +1674,7 @@ if (VR_idx != Num_VR_Regs) { unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass); RegInfo.addLiveIn(VR[VR_idx], VReg); - ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); + ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT); if (isVarArg) { while ((ArgOffset % 16) != 0) { ArgOffset += PtrByteSize; @@ -1707,7 +1708,7 @@ CurArgOffset + (ArgSize - ObjSize), isImmutable); SDValue FIN = DAG.getFrameIndex(FI, PtrVT); - ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); + ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0); } ArgValues.push_back(ArgVal); @@ -1763,11 +1764,11 @@ if (isELF32_ABI) { for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) { SDValue Val = DAG.getRegister(GPR[GPR_idx], PtrVT); - SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0); + SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by four for the next argument to store SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); - FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); + FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); } } @@ -1782,12 +1783,12 @@ VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); RegInfo.addLiveIn(GPR[GPR_idx], VReg); - SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT); - SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); + SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT); + SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by four for the next argument to store SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); - FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); + FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); } // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex @@ -1795,12 +1796,12 @@ if (isELF32_ABI) { for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) { SDValue Val = DAG.getRegister(FPR[FPR_idx], MVT::f64); - SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0); + SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by eight for the next argument to store SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, PtrVT); - FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); + FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); } for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) { @@ -1808,24 +1809,25 @@ VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); RegInfo.addLiveIn(FPR[FPR_idx], VReg); - SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::f64); - SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); + SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::f64); + SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by eight for the next argument to store SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, PtrVT); - FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); + FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); } } } if (!MemOps.empty()) - Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); + Root = DAG.getNode(ISD::TokenFactor, dl, + MVT::Other, &MemOps[0], MemOps.size()); ArgValues.push_back(Root); // Return the new list of results. - return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), &ArgValues[0], ArgValues.size()); } @@ -2223,13 +2225,13 @@ else PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); - PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); + PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); // On PPC64, promote integers to 64-bit values. if (isPPC64 && Arg.getValueType() == MVT::i32) { // FIXME: Should this use ANY_EXTEND if neither sext nor zext? unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; - Arg = DAG.getNode(ExtOp, MVT::i64, Arg); + Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); } // FIXME Elf untested, what are alignment rules? @@ -2242,7 +2244,7 @@ // Everything else is passed left-justified. MVT VT = (Size==1) ? MVT::i8 : MVT::i16; if (GPR_idx != NumGPRs) { - SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg, + SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, NULL, 0, VT); MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); @@ -2250,7 +2252,7 @@ ArgOffset += PtrByteSize; } else { SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType()); - SDValue AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const); + SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, CallSeqStart.getNode()->getOperand(0), Flags, DAG, Size, dl); @@ -2278,9 +2280,9 @@ // And copy the pieces of it that fit into registers. for (unsigned j=0; jgetVTList(), &Ops[0], Ops.size()); return SDValue(Chain.getNode(), Op.getResNo()); } - Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); + Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); InFlag = Chain.getValue(1); Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), @@ -2595,7 +2597,8 @@ CCValAssign &VA = RVLocs[i]; MVT VT = VA.getValVT(); assert(VA.isRegLoc() && "Can only return in registers!"); - Chain = DAG.getCopyFromReg(Chain, VA.getLocReg(), VT, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, + VA.getLocReg(), VT, InFlag).getValue(1); ResultVals.push_back(Chain.getValue(0)); InFlag = Chain.getValue(2); } @@ -2606,7 +2609,7 @@ // Otherwise, merge everything together with a MERGE_VALUES node. ResultVals.push_back(Chain); - SDValue Res = DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), + SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(), &ResultVals[0], ResultVals.size()); return Res.getValue(Op.getResNo()); } Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=63716&r1=63715&r2=63716&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Tue Feb 3 20:34:38 2009 @@ -103,16 +103,16 @@ case MVT::i32: if (I->use_empty()) { // Argument is dead. if (CurArgReg < ArgRegEnd) ++CurArgReg; - ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); + ArgValues.push_back(DAG.getNode(ISD::UNDEF, dl, ObjectVT)); } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); - SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); + SDValue Arg = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); if (ObjectVT != MVT::i32) { unsigned AssertOp = ISD::AssertSext; - Arg = DAG.getNode(AssertOp, MVT::i32, Arg, + Arg = DAG.getNode(AssertOp, dl, MVT::i32, Arg, DAG.getValueType(ObjectVT)); - Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); + Arg = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Arg); } ArgValues.push_back(Arg); } else { @@ -120,17 +120,17 @@ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); SDValue Load; if (ObjectVT == MVT::i32) { - Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); + Load = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0); } else { ISD::LoadExtType LoadOp = ISD::SEXTLOAD; // Sparc is big endian, so add an offset based on the ObjectVT. unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8); - FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, + FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, DAG.getConstant(Offset, MVT::i32)); - Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, + Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Root, FIPtr, NULL, 0, ObjectVT); - Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); + Load = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Load); } ArgValues.push_back(Load); } @@ -140,19 +140,19 @@ case MVT::f32: if (I->use_empty()) { // Argument is dead. if (CurArgReg < ArgRegEnd) ++CurArgReg; - ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); + ArgValues.push_back(DAG.getNode(ISD::UNDEF, dl, ObjectVT)); } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR // FP value is passed in an integer register. unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); - SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); + SDValue Arg = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); - Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); + Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Arg); ArgValues.push_back(Arg); } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - SDValue Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0); + SDValue Load = DAG.getLoad(MVT::f32, dl, Root, FIPtr, NULL, 0); ArgValues.push_back(Load); } ArgOffset += 4; @@ -163,37 +163,37 @@ if (I->use_empty()) { // Argument is dead. if (CurArgReg < ArgRegEnd) ++CurArgReg; if (CurArgReg < ArgRegEnd) ++CurArgReg; - ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); + ArgValues.push_back(DAG.getNode(ISD::UNDEF, dl, ObjectVT)); } else { SDValue HiVal; if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi); - HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); + HiVal = DAG.getCopyFromReg(Root, dl, VRegHi, MVT::i32); } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); + HiVal = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0); } SDValue LoVal; if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo); - LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); + LoVal = DAG.getCopyFromReg(Root, dl, VRegLo, MVT::i32); } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); + LoVal = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0); } // Compose the two halves together into an i64 unit. SDValue WholeValue = - DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); + DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); // If we want a double, do a bit convert. if (ObjectVT == MVT::f64) - WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); + WholeValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, WholeValue); ArgValues.push_back(WholeValue); } @@ -210,18 +210,18 @@ for (; CurArgReg != ArgRegEnd; ++CurArgReg) { unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg, VReg); - SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); + SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0)); + OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, NULL, 0)); ArgOffset += 4; } } if (!OutChains.empty()) - DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, + DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &OutChains[0], OutChains.size())); } From nicholas at mxc.ca Tue Feb 3 22:36:58 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 03 Feb 2009 20:36:58 -0800 Subject: [llvm-commits] [llvm] r63623 - in /llvm/trunk/tools: Makefile gold/ gold/Makefile gold/README.txt gold/gold-plugin.cpp In-Reply-To: <200902031042.11251.baldrick@free.fr> References: <200902030713.n137DP9o009780@zion.cs.uiuc.edu> <200902031042.11251.baldrick@free.fr> Message-ID: <49891B6A.1010106@mxc.ca> Duncan Sands wrote: > Hey Nick, > >> Add LLVM plugin for gold. > > this is great! It's like Christmas a second time :) You're welcome! With Rafael's patch to llvm-gcc in r63633, we now get transparent LTO with the gold plugin and CFLAGS=-O4 -use-gold-plugin. Nick PS. for values of transparent equal to installing gold out of binutils CVS, but anyways :) From resistor at mac.com Tue Feb 3 23:16:47 2009 From: resistor at mac.com (Owen Anderson) Date: Wed, 04 Feb 2009 05:16:47 -0000 Subject: [llvm-commits] [llvm] r63718 - in /llvm/trunk: lib/Analysis/AliasAnalysis.cpp lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/cas.ll Message-ID: <200902040516.n145Gmh1032364@zion.cs.uiuc.edu> Author: resistor Date: Tue Feb 3 23:16:46 2009 New Revision: 63718 URL: http://llvm.org/viewvc/llvm-project?rev=63718&view=rev Log: Finish making AliasAnalysis aware of the fact that most atomic intrinsics only dereference their arguments, and enhance BasicAA to make use of this fact when computing ModRef info. Added: llvm/trunk/test/Analysis/BasicAA/cas.ll Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=63718&r1=63717&r2=63718&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Tue Feb 3 23:16:46 2009 @@ -150,6 +150,27 @@ AliasAnalysis::ModRefBehavior AliasAnalysis::getModRefBehavior(Function *F, std::vector *Info) { + if (F->isIntrinsic()) { + switch (F->getIntrinsicID()) { + case Intrinsic::atomic_cmp_swap: + case Intrinsic::atomic_load_add: + case Intrinsic::atomic_load_and: + case Intrinsic::atomic_load_max: + case Intrinsic::atomic_load_min: + case Intrinsic::atomic_load_nand: + case Intrinsic::atomic_load_or: + case Intrinsic::atomic_load_sub: + case Intrinsic::atomic_load_umax: + case Intrinsic::atomic_load_umin: + case Intrinsic::atomic_load_xor: + case Intrinsic::atomic_swap: + // CAS and related intrinsics only access their arguments. + return AliasAnalysis::AccessesArguments; + default: + break; + } + } + if (F->doesNotAccessMemory()) // Can't do better than this. return DoesNotAccessMemory; Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=63718&r1=63717&r2=63718&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Tue Feb 3 23:16:46 2009 @@ -256,6 +256,22 @@ // AliasAnalysis::ModRefResult BasicAliasAnalysis::getModRefInfo(CallSite CS, Value *P, unsigned Size) { + // If the function only accesses its arguments, it suffices to check that + // P does not alias any of those arguments. + if (AliasAnalysis::getModRefBehavior(CS, 0) == + AliasAnalysis::AccessesArguments) { + bool doesAlias = false; + for (CallSite::arg_iterator AI = CS.arg_begin(), AE = CS.arg_end(); + AI != AE; ++AI) + if (alias(*AI, ~0U, P, Size) != NoAlias) { + doesAlias = true; + break; + } + + if (!doesAlias) + return NoModRef; + } + if (!isa(P)) { const Value *Object = P->getUnderlyingObject(); Added: llvm/trunk/test/Analysis/BasicAA/cas.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/cas.ll?rev=63718&view=auto ============================================================================== --- llvm/trunk/test/Analysis/BasicAA/cas.ll (added) +++ llvm/trunk/test/Analysis/BasicAA/cas.ll Tue Feb 3 23:16:46 2009 @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | opt -basicaa -gvn | llvm-dis | grep load | count 1 + + at flag0 = internal global i32 zeroinitializer + at turn = internal global i32 zeroinitializer + + +define i32 @main() { + %a = load i32* @flag0 + %b = tail call i32 @llvm.atomic.swap.i32.p0i32(i32* @turn, i32 1) + %c = load i32* @flag0 + ret i32 %c +} + +declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind \ No newline at end of file From baldrick at free.fr Wed Feb 4 00:14:10 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 4 Feb 2009 07:14:10 +0100 Subject: [llvm-commits] [llvm] r63718 - in /llvm/trunk: lib/Analysis/AliasAnalysis.cpp lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/cas.ll In-Reply-To: <200902040516.n145Gmh1032364@zion.cs.uiuc.edu> References: <200902040516.n145Gmh1032364@zion.cs.uiuc.edu> Message-ID: <200902040714.10407.baldrick@free.fr> Hi Owen, > Finish making AliasAnalysis aware of the fact that most atomic intrinsics > only dereference their arguments shouldn't they get the "noescape" attribute then? > and enhance > BasicAA to make use of this fact when computing ModRef info. Can this be reworked to use noescape attributes instead? Ciao, Duncan. From nicholas at mxc.ca Wed Feb 4 00:26:47 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 04 Feb 2009 06:26:47 -0000 Subject: [llvm-commits] [llvm] r63723 - in /llvm/trunk: Makefile.config.in autoconf/configure.ac lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp Message-ID: <200902040626.n146QlxH002153@zion.cs.uiuc.edu> Author: nicholas Date: Wed Feb 4 00:26:47 2009 New Revision: 63723 URL: http://llvm.org/viewvc/llvm-project?rev=63723&view=rev Log: Reapply patch from r62553, with a fix to avoid looking for an ffi.h that isn't there. This changes the interpreter to use libffi. After this patch, the interpreter will barely be able to call any external functions if built on a system without libffi installed (just enough to pass 'make check' really). But with libffi, we can now call any function that isn't variadic or taking a struct or vector parameter (but pointer to struct is fine). Patch by Alexei Svitkine! Modified: llvm/trunk/Makefile.config.in llvm/trunk/autoconf/configure.ac llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp Modified: llvm/trunk/Makefile.config.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.config.in?rev=63723&r1=63722&r2=63723&view=diff ============================================================================== --- llvm/trunk/Makefile.config.in (original) +++ llvm/trunk/Makefile.config.in Wed Feb 4 00:26:47 2009 @@ -286,3 +286,6 @@ # Location of the plugin header file for gold. BINUTILS_INCDIR := @BINUTILS_INCDIR@ + +# Can we use libFFI for the interpreter? +HAVE_FFI := @HAVE_FFI@ Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=63723&r1=63722&r2=63723&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Wed Feb 4 00:26:47 2009 @@ -735,6 +735,10 @@ [Define if dlopen() is available on this platform.]), AC_MSG_WARN([dlopen() not found - disabling plugin support])) +dnl libffi is optional; used to call external functions from the interpreter +AC_CHECK_LIB(ffi,ffi_call,[have_libffi=1], + AC_MSG_WARN([libffi not found - disabling external calls from interpreter])) + dnl mallinfo is optional; the code can compile (minus features) without it AC_SEARCH_LIBS(mallinfo,malloc,AC_DEFINE([HAVE_MALLINFO],[1], [Define if mallinfo() is available on this platform.])) @@ -791,12 +795,17 @@ AC_CHECK_HEADERS([sys/types.h malloc/malloc.h mach/mach.h]) if test "$ENABLE_THREADS" -eq 1 ; then AC_CHECK_HEADERS(pthread.h, - AC_SUBST(HAVE_PTHREAD, 1), - AC_SUBST(HAVE_PTHREAD, 0)) + AC_SUBST(HAVE_PTHREAD, 1), + AC_SUBST(HAVE_PTHREAD, 0)) else AC_SUBST(HAVE_PTHREAD, 0) fi +dnl Once we know we have libffi, try to find ffi.h. +if test -n "$have_libffi" ; then + AC_CHECK_HEADERS([ffi.h ffi/ffi.h], [AC_SUBST(HAVE_FFI, 1)]) +fi + dnl===-----------------------------------------------------------------------=== dnl=== dnl=== SECTION 7: Check for types and structures @@ -954,7 +963,7 @@ AC_DEFINE_UNQUOTED(LLVM_CONFIGTIME, "$LLVM_CONFIGTIME", [Time at which LLVM was configured]) AC_DEFINE_UNQUOTED(LLVM_HOSTTRIPLE, "$host", - [Host triple we were built on]) + [Host triple we were built on]) # Determine which bindings to build. if test "$BINDINGS_TO_BUILD" = auto ; then Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp?rev=63723&r1=63722&r2=63723&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp Wed Feb 4 00:26:47 2009 @@ -10,18 +10,19 @@ // This file contains both code to deal with invoking "external" functions, but // also contains code that implements "exported" external functions. // -// External functions in the interpreter are implemented by -// using the system's dynamic loader to look up the address of the function -// we want to invoke. If a function is found, then one of the -// many lle_* wrapper functions in this file will translate its arguments from -// GenericValues to the types the function is actually expecting, before the -// function is called. +// There are currently two mechanisms for handling external functions in the +// Interpreter. The first is to implement lle_* wrapper functions that are +// specific to well-known library functions which manually translate the +// arguments from GenericValues and make the call. If such a wrapper does +// not exist, and libffi is available, then the Interpreter will attempt to +// invoke the function using libffi, after finding its address. // //===----------------------------------------------------------------------===// #include "Interpreter.h" #include "llvm/DerivedTypes.h" #include "llvm/Module.h" +#include "llvm/Config/config.h" // Detect libffi #include "llvm/Support/Streams.h" #include "llvm/System/DynamicLibrary.h" #include "llvm/Target/TargetData.h" @@ -32,18 +33,28 @@ #include #include -#ifdef __linux__ -#include +#ifdef HAVE_FFI +#ifdef HAVE_FFI_H +#include +#elif HAVE_FFI_FFI_H +#include +#else +#error "Not sure where configure found ffi.h!" +#endif #endif - -using std::vector; using namespace llvm; -typedef GenericValue (*ExFunc)(FunctionType *, const vector &); -static ManagedStatic > Functions; +typedef GenericValue (*ExFunc)(const FunctionType *, + const std::vector &); +static ManagedStatic > ExportedFunctions; static std::map FuncNames; +#ifdef HAVE_FFI +typedef void (*RawFunc)(void); +static ManagedStatic > RawFunctions; +#endif + static Interpreter *TheInterpreter; static char getTypeID(const Type *Ty) { @@ -89,34 +100,181 @@ if (FnPtr == 0) // Try calling a generic function... if it exists... FnPtr = (ExFunc)(intptr_t)sys::DynamicLibrary::SearchForAddressOfSymbol( ("lle_X_"+F->getName()).c_str()); - if (FnPtr == 0) - FnPtr = (ExFunc)(intptr_t) - sys::DynamicLibrary::SearchForAddressOfSymbol(F->getName()); if (FnPtr != 0) - Functions->insert(std::make_pair(F, FnPtr)); // Cache for later + ExportedFunctions->insert(std::make_pair(F, FnPtr)); // Cache for later return FnPtr; } +#ifdef HAVE_FFI +static ffi_type *ffiTypeFor(const Type *Ty) { + switch (Ty->getTypeID()) { + case Type::VoidTyID: return &ffi_type_void; + case Type::IntegerTyID: + switch (cast(Ty)->getBitWidth()) { + case 8: return &ffi_type_sint8; + case 16: return &ffi_type_sint16; + case 32: return &ffi_type_sint32; + case 64: return &ffi_type_sint64; + } + case Type::FloatTyID: return &ffi_type_float; + case Type::DoubleTyID: return &ffi_type_double; + case Type::PointerTyID: return &ffi_type_pointer; + default: break; + } + // TODO: Support other types such as StructTyID, ArrayTyID, OpaqueTyID, etc. + cerr << "Type could not be mapped for use with libffi.\n"; + abort(); + return NULL; +} + +static void *ffiValueFor(const Type *Ty, const GenericValue &AV, + void *ArgDataPtr) { + switch (Ty->getTypeID()) { + case Type::IntegerTyID: + switch (cast(Ty)->getBitWidth()) { + case 8: { + int8_t *I8Ptr = (int8_t *) ArgDataPtr; + *I8Ptr = (int8_t) AV.IntVal.getZExtValue(); + return ArgDataPtr; + } + case 16: { + int16_t *I16Ptr = (int16_t *) ArgDataPtr; + *I16Ptr = (int16_t) AV.IntVal.getZExtValue(); + return ArgDataPtr; + } + case 32: { + int32_t *I32Ptr = (int32_t *) ArgDataPtr; + *I32Ptr = (int32_t) AV.IntVal.getZExtValue(); + return ArgDataPtr; + } + case 64: { + int64_t *I64Ptr = (int64_t *) ArgDataPtr; + *I64Ptr = (int64_t) AV.IntVal.getZExtValue(); + return ArgDataPtr; + } + } + case Type::FloatTyID: { + float *FloatPtr = (float *) ArgDataPtr; + *FloatPtr = AV.DoubleVal; + return ArgDataPtr; + } + case Type::DoubleTyID: { + double *DoublePtr = (double *) ArgDataPtr; + *DoublePtr = AV.DoubleVal; + return ArgDataPtr; + } + case Type::PointerTyID: { + void **PtrPtr = (void **) ArgDataPtr; + *PtrPtr = GVTOP(AV); + return ArgDataPtr; + } + default: break; + } + // TODO: Support other types such as StructTyID, ArrayTyID, OpaqueTyID, etc. + cerr << "Type value could not be mapped for use with libffi.\n"; + abort(); + return NULL; +} + +static bool ffiInvoke(RawFunc Fn, Function *F, + const std::vector &ArgVals, + const TargetData *TD, GenericValue &Result) { + ffi_cif cif; + const FunctionType *FTy = F->getFunctionType(); + const unsigned NumArgs = F->arg_size(); + + // TODO: We don't have type information about the remaining arguments, because + // this information is never passed into ExecutionEngine::runFunction(). + if (ArgVals.size() > NumArgs && F->isVarArg()) { + cerr << "Calling external var arg function '" << F->getName() + << "' is not supported by the Interpreter.\n"; + abort(); + } + + unsigned ArgBytes = 0; + + std::vector args(NumArgs); + for (Function::const_arg_iterator A = F->arg_begin(), E = F->arg_end(); + A != E; ++A) { + const unsigned ArgNo = A->getArgNo(); + const Type *ArgTy = FTy->getParamType(ArgNo); + args[ArgNo] = ffiTypeFor(ArgTy); + ArgBytes += TD->getTypeStoreSize(ArgTy); + } + + uint8_t *ArgData = (uint8_t*) alloca(ArgBytes); + uint8_t *ArgDataPtr = ArgData; + std::vector values(NumArgs); + for (Function::const_arg_iterator A = F->arg_begin(), E = F->arg_end(); + A != E; ++A) { + const unsigned ArgNo = A->getArgNo(); + const Type *ArgTy = FTy->getParamType(ArgNo); + values[ArgNo] = ffiValueFor(ArgTy, ArgVals[ArgNo], ArgDataPtr); + ArgDataPtr += TD->getTypeStoreSize(ArgTy); + } + + const Type *RetTy = FTy->getReturnType(); + ffi_type *rtype = ffiTypeFor(RetTy); + + if (ffi_prep_cif(&cif, FFI_DEFAULT_ABI, NumArgs, rtype, &args[0]) == FFI_OK) { + void *ret = NULL; + if (RetTy->getTypeID() != Type::VoidTyID) + ret = alloca(TD->getTypeStoreSize(RetTy)); + ffi_call(&cif, Fn, ret, &values[0]); + switch (RetTy->getTypeID()) { + case Type::IntegerTyID: + switch (cast(RetTy)->getBitWidth()) { + case 8: Result.IntVal = APInt(8 , *(int8_t *) ret); break; + case 16: Result.IntVal = APInt(16, *(int16_t*) ret); break; + case 32: Result.IntVal = APInt(32, *(int32_t*) ret); break; + case 64: Result.IntVal = APInt(64, *(int64_t*) ret); break; + } + break; + case Type::FloatTyID: Result.FloatVal = *(float *) ret; break; + case Type::DoubleTyID: Result.DoubleVal = *(double*) ret; break; + case Type::PointerTyID: Result.PointerVal = *(void **) ret; break; + default: break; + } + return true; + } + + return false; +} +#endif // HAVE_FFI + GenericValue Interpreter::callExternalFunction(Function *F, const std::vector &ArgVals) { TheInterpreter = this; // Do a lookup to see if the function is in our cache... this should just be a // deferred annotation! - std::map::iterator FI = Functions->find(F); - ExFunc Fn = (FI == Functions->end()) ? lookupFunction(F) : FI->second; - if (Fn == 0) { - cerr << "Tried to execute an unknown external function: " - << F->getType()->getDescription() << " " << F->getName() << "\n"; - if (F->getName() == "__main") - return GenericValue(); - abort(); + std::map::iterator FI = ExportedFunctions->find(F); + if (ExFunc Fn = (FI == ExportedFunctions->end()) ? lookupFunction(F) + : FI->second) + return Fn(F->getFunctionType(), ArgVals); + +#ifdef HAVE_FFI + std::map::iterator RF = RawFunctions->find(F); + RawFunc RawFn; + if (RF == RawFunctions->end()) { + RawFn = (RawFunc)(intptr_t) + sys::DynamicLibrary::SearchForAddressOfSymbol(F->getName()); + if (RawFn != 0) + RawFunctions->insert(std::make_pair(F, RawFn)); // Cache for later + } else { + RawFn = RF->second; } - // TODO: FIXME when types are not const! - GenericValue Result = Fn(const_cast(F->getFunctionType()), - ArgVals); - return Result; + GenericValue Result; + if (RawFn != 0 && ffiInvoke(RawFn, F, ArgVals, getTargetData(), Result)) + return Result; +#endif // HAVE_FFI + + cerr << "Tried to execute an unknown external function: " + << F->getType()->getDescription() << " " << F->getName() << "\n"; + if (F->getName() != "__main") + abort(); + return GenericValue(); } @@ -125,24 +283,9 @@ // extern "C" { // Don't add C++ manglings to llvm mangling :) -// void putchar(ubyte) -GenericValue lle_X_putchar(FunctionType *FT, const vector &Args){ - cout << ((char)Args[0].IntVal.getZExtValue()) << std::flush; - return Args[0]; -} - -// void _IO_putc(int c, FILE* fp) -GenericValue lle_X__IO_putc(FunctionType *FT, const vector &Args){ -#ifdef __linux__ - _IO_putc((char)Args[0].IntVal.getZExtValue(), (FILE*) Args[1].PointerVal); -#else - assert(0 && "Can't call _IO_putc on this platform"); -#endif - return Args[0]; -} - // void atexit(Function*) -GenericValue lle_X_atexit(FunctionType *FT, const vector &Args) { +GenericValue lle_X_atexit(const FunctionType *FT, + const std::vector &Args) { assert(Args.size() == 1); TheInterpreter->addAtExitHandler((Function*)GVTOP(Args[0])); GenericValue GV; @@ -151,163 +294,23 @@ } // void exit(int) -GenericValue lle_X_exit(FunctionType *FT, const vector &Args) { +GenericValue lle_X_exit(const FunctionType *FT, + const std::vector &Args) { TheInterpreter->exitCalled(Args[0]); return GenericValue(); } // void abort(void) -GenericValue lle_X_abort(FunctionType *FT, const vector &Args) { +GenericValue lle_X_abort(const FunctionType *FT, + const std::vector &Args) { raise (SIGABRT); return GenericValue(); } -// void *malloc(uint) -GenericValue lle_X_malloc(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1 && "Malloc expects one argument!"); - assert(isa(FT->getReturnType()) && "malloc must return pointer"); - return PTOGV(malloc(Args[0].IntVal.getZExtValue())); -} - -// void *calloc(uint, uint) -GenericValue lle_X_calloc(FunctionType *FT, const vector &Args) { - assert(Args.size() == 2 && "calloc expects two arguments!"); - assert(isa(FT->getReturnType()) && "calloc must return pointer"); - return PTOGV(calloc(Args[0].IntVal.getZExtValue(), - Args[1].IntVal.getZExtValue())); -} - -// void *calloc(uint, uint) -GenericValue lle_X_realloc(FunctionType *FT, const vector &Args) { - assert(Args.size() == 2 && "calloc expects two arguments!"); - assert(isa(FT->getReturnType()) &&"realloc must return pointer"); - return PTOGV(realloc(GVTOP(Args[0]), Args[1].IntVal.getZExtValue())); -} - -// void free(void *) -GenericValue lle_X_free(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - free(GVTOP(Args[0])); - return GenericValue(); -} - -// int atoi(char *) -GenericValue lle_X_atoi(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - GenericValue GV; - GV.IntVal = APInt(32, atoi((char*)GVTOP(Args[0]))); - return GV; -} - -// double pow(double, double) -GenericValue lle_X_pow(FunctionType *FT, const vector &Args) { - assert(Args.size() == 2); - GenericValue GV; - GV.DoubleVal = pow(Args[0].DoubleVal, Args[1].DoubleVal); - return GV; -} - -// double sin(double) -GenericValue lle_X_sin(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - GenericValue GV; - GV.DoubleVal = sin(Args[0].DoubleVal); - return GV; -} - -// double cos(double) -GenericValue lle_X_cos(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - GenericValue GV; - GV.DoubleVal = cos(Args[0].DoubleVal); - return GV; -} - -// double exp(double) -GenericValue lle_X_exp(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - GenericValue GV; - GV.DoubleVal = exp(Args[0].DoubleVal); - return GV; -} - -// double sqrt(double) -GenericValue lle_X_sqrt(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - GenericValue GV; - GV.DoubleVal = sqrt(Args[0].DoubleVal); - return GV; -} - -// double log(double) -GenericValue lle_X_log(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - GenericValue GV; - GV.DoubleVal = log(Args[0].DoubleVal); - return GV; -} - -// double floor(double) -GenericValue lle_X_floor(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - GenericValue GV; - GV.DoubleVal = floor(Args[0].DoubleVal); - return GV; -} - -#ifdef HAVE_RAND48 - -// double drand48() -GenericValue lle_X_drand48(FunctionType *FT, const vector &Args) { - assert(Args.empty()); - GenericValue GV; - GV.DoubleVal = drand48(); - return GV; -} - -// long lrand48() -GenericValue lle_X_lrand48(FunctionType *FT, const vector &Args) { - assert(Args.empty()); - GenericValue GV; - GV.IntVal = APInt(32, lrand48()); - return GV; -} - -// void srand48(long) -GenericValue lle_X_srand48(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - srand48(Args[0].IntVal.getZExtValue()); - return GenericValue(); -} - -#endif - -// int rand() -GenericValue lle_X_rand(FunctionType *FT, const vector &Args) { - assert(Args.empty()); - GenericValue GV; - GV.IntVal = APInt(32, rand()); - return GV; -} - -// void srand(uint) -GenericValue lle_X_srand(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - srand(Args[0].IntVal.getZExtValue()); - return GenericValue(); -} - -// int puts(const char*) -GenericValue lle_X_puts(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - GenericValue GV; - GV.IntVal = APInt(32, puts((char*)GVTOP(Args[0]))); - return GV; -} - -// int sprintf(sbyte *, sbyte *, ...) - a very rough implementation to make +// int sprintf(char *, const char *, ...) - a very rough implementation to make // output useful. -GenericValue lle_X_sprintf(FunctionType *FT, const vector &Args) { +GenericValue lle_X_sprintf(const FunctionType *FT, + const std::vector &Args) { char *OutputBuffer = (char *)GVTOP(Args[0]); const char *FmtStr = (const char *)GVTOP(Args[1]); unsigned ArgNo = 2; @@ -384,10 +387,12 @@ return GV; } -// int printf(sbyte *, ...) - a very rough implementation to make output useful. -GenericValue lle_X_printf(FunctionType *FT, const vector &Args) { +// int printf(const char *, ...) - a very rough implementation to make output +// useful. +GenericValue lle_X_printf(const FunctionType *FT, + const std::vector &Args) { char Buffer[10000]; - vector NewArgs; + std::vector NewArgs; NewArgs.push_back(PTOGV((void*)&Buffer[0])); NewArgs.insert(NewArgs.end(), Args.begin(), Args.end()); GenericValue GV = lle_X_sprintf(FT, NewArgs); @@ -472,7 +477,8 @@ } // int sscanf(const char *format, ...); -GenericValue lle_X_sscanf(FunctionType *FT, const vector &args) { +GenericValue lle_X_sscanf(const FunctionType *FT, + const std::vector &args) { assert(args.size() < 10 && "Only handle up to 10 args to sscanf right now!"); char *Args[10]; @@ -488,7 +494,8 @@ } // int scanf(const char *format, ...); -GenericValue lle_X_scanf(FunctionType *FT, const vector &args) { +GenericValue lle_X_scanf(const FunctionType *FT, + const std::vector &args) { assert(args.size() < 10 && "Only handle up to 10 args to scanf right now!"); char *Args[10]; @@ -503,324 +510,33 @@ return GV; } - -// int clock(void) - Profiling implementation -GenericValue lle_i_clock(FunctionType *FT, const vector &Args) { - extern unsigned int clock(void); - GenericValue GV; - GV.IntVal = APInt(32, clock()); - return GV; -} - - -//===----------------------------------------------------------------------===// -// String Functions... -//===----------------------------------------------------------------------===// - -// int strcmp(const char *S1, const char *S2); -GenericValue lle_X_strcmp(FunctionType *FT, const vector &Args) { - assert(Args.size() == 2); - GenericValue Ret; - Ret.IntVal = APInt(32, strcmp((char*)GVTOP(Args[0]), (char*)GVTOP(Args[1]))); - return Ret; -} - -// char *strcat(char *Dest, const char *src); -GenericValue lle_X_strcat(FunctionType *FT, const vector &Args) { - assert(Args.size() == 2); - assert(isa(FT->getReturnType()) &&"strcat must return pointer"); - return PTOGV(strcat((char*)GVTOP(Args[0]), (char*)GVTOP(Args[1]))); -} - -// char *strcpy(char *Dest, const char *src); -GenericValue lle_X_strcpy(FunctionType *FT, const vector &Args) { - assert(Args.size() == 2); - assert(isa(FT->getReturnType()) &&"strcpy must return pointer"); - return PTOGV(strcpy((char*)GVTOP(Args[0]), (char*)GVTOP(Args[1]))); -} - -static GenericValue size_t_to_GV (size_t n) { - GenericValue Ret; - if (sizeof (size_t) == sizeof (uint64_t)) { - Ret.IntVal = APInt(64, n); - } else { - assert (sizeof (size_t) == sizeof (unsigned int)); - Ret.IntVal = APInt(32, n); - } - return Ret; -} - -static size_t GV_to_size_t (GenericValue GV) { - size_t count; - if (sizeof (size_t) == sizeof (uint64_t)) { - count = (size_t)GV.IntVal.getZExtValue(); - } else { - assert (sizeof (size_t) == sizeof (unsigned int)); - count = (size_t)GV.IntVal.getZExtValue(); - } - return count; -} - -// size_t strlen(const char *src); -GenericValue lle_X_strlen(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - size_t strlenResult = strlen ((char *) GVTOP (Args[0])); - return size_t_to_GV (strlenResult); -} - -// char *strdup(const char *src); -GenericValue lle_X_strdup(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - assert(isa(FT->getReturnType()) && "strdup must return pointer"); - return PTOGV(strdup((char*)GVTOP(Args[0]))); -} - -// char *__strdup(const char *src); -GenericValue lle_X___strdup(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - assert(isa(FT->getReturnType()) &&"_strdup must return pointer"); - return PTOGV(strdup((char*)GVTOP(Args[0]))); -} - -// void *memset(void *S, int C, size_t N) -GenericValue lle_X_memset(FunctionType *FT, const vector &Args) { - assert(Args.size() == 3); - size_t count = GV_to_size_t (Args[2]); - assert(isa(FT->getReturnType()) && "memset must return pointer"); - return PTOGV(memset(GVTOP(Args[0]), uint32_t(Args[1].IntVal.getZExtValue()), - count)); -} - -// void *memcpy(void *Dest, void *src, size_t Size); -GenericValue lle_X_memcpy(FunctionType *FT, const vector &Args) { - assert(Args.size() == 3); - assert(isa(FT->getReturnType()) && "memcpy must return pointer"); - size_t count = GV_to_size_t (Args[2]); - return PTOGV(memcpy((char*)GVTOP(Args[0]), (char*)GVTOP(Args[1]), count)); -} - -// void *memcpy(void *Dest, void *src, size_t Size); -GenericValue lle_X_memmove(FunctionType *FT, const vector &Args) { - assert(Args.size() == 3); - assert(isa(FT->getReturnType()) && "memmove must return pointer"); - size_t count = GV_to_size_t (Args[2]); - return PTOGV(memmove((char*)GVTOP(Args[0]), (char*)GVTOP(Args[1]), count)); -} - -//===----------------------------------------------------------------------===// -// IO Functions... -//===----------------------------------------------------------------------===// - -// getFILE - Turn a pointer in the host address space into a legit pointer in -// the interpreter address space. This is an identity transformation. -#define getFILE(ptr) ((FILE*)ptr) - -// FILE *fopen(const char *filename, const char *mode); -GenericValue lle_X_fopen(FunctionType *FT, const vector &Args) { - assert(Args.size() == 2); - assert(isa(FT->getReturnType()) && "fopen must return pointer"); - return PTOGV(fopen((const char *)GVTOP(Args[0]), - (const char *)GVTOP(Args[1]))); -} - -// int fclose(FILE *F); -GenericValue lle_X_fclose(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - GenericValue GV; - GV.IntVal = APInt(32, fclose(getFILE(GVTOP(Args[0])))); - return GV; -} - -// int feof(FILE *stream); -GenericValue lle_X_feof(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - GenericValue GV; - - GV.IntVal = APInt(32, feof(getFILE(GVTOP(Args[0])))); - return GV; -} - -// size_t fread(void *ptr, size_t size, size_t nitems, FILE *stream); -GenericValue lle_X_fread(FunctionType *FT, const vector &Args) { - assert(Args.size() == 4); - size_t result; - - result = fread((void*)GVTOP(Args[0]), GV_to_size_t (Args[1]), - GV_to_size_t (Args[2]), getFILE(GVTOP(Args[3]))); - return size_t_to_GV (result); -} - -// size_t fwrite(const void *ptr, size_t size, size_t nitems, FILE *stream); -GenericValue lle_X_fwrite(FunctionType *FT, const vector &Args) { - assert(Args.size() == 4); - size_t result; - - result = fwrite((void*)GVTOP(Args[0]), GV_to_size_t (Args[1]), - GV_to_size_t (Args[2]), getFILE(GVTOP(Args[3]))); - return size_t_to_GV (result); -} - -// char *fgets(char *s, int n, FILE *stream); -GenericValue lle_X_fgets(FunctionType *FT, const vector &Args) { - assert(Args.size() == 3); - return PTOGV(fgets((char*)GVTOP(Args[0]), Args[1].IntVal.getZExtValue(), - getFILE(GVTOP(Args[2])))); -} - -// FILE *freopen(const char *path, const char *mode, FILE *stream); -GenericValue lle_X_freopen(FunctionType *FT, const vector &Args) { - assert(Args.size() == 3); - assert(isa(FT->getReturnType()) &&"freopen must return pointer"); - return PTOGV(freopen((char*)GVTOP(Args[0]), (char*)GVTOP(Args[1]), - getFILE(GVTOP(Args[2])))); -} - -// int fflush(FILE *stream); -GenericValue lle_X_fflush(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - GenericValue GV; - GV.IntVal = APInt(32, fflush(getFILE(GVTOP(Args[0])))); - return GV; -} - -// int getc(FILE *stream); -GenericValue lle_X_getc(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - GenericValue GV; - GV.IntVal = APInt(32, getc(getFILE(GVTOP(Args[0])))); - return GV; -} - -// int _IO_getc(FILE *stream); -GenericValue lle_X__IO_getc(FunctionType *F, const vector &Args) { - return lle_X_getc(F, Args); -} - -// int fputc(int C, FILE *stream); -GenericValue lle_X_fputc(FunctionType *FT, const vector &Args) { - assert(Args.size() == 2); - GenericValue GV; - GV.IntVal = APInt(32, fputc(Args[0].IntVal.getZExtValue(), - getFILE(GVTOP(Args[1])))); - return GV; -} - -// int ungetc(int C, FILE *stream); -GenericValue lle_X_ungetc(FunctionType *FT, const vector &Args) { - assert(Args.size() == 2); - GenericValue GV; - GV.IntVal = APInt(32, ungetc(Args[0].IntVal.getZExtValue(), - getFILE(GVTOP(Args[1])))); - return GV; -} - -// int ferror (FILE *stream); -GenericValue lle_X_ferror(FunctionType *FT, const vector &Args) { - assert(Args.size() == 1); - GenericValue GV; - GV.IntVal = APInt(32, ferror (getFILE(GVTOP(Args[0])))); - return GV; -} - -// int fprintf(FILE *,sbyte *, ...) - a very rough implementation to make output -// useful. -GenericValue lle_X_fprintf(FunctionType *FT, const vector &Args) { +// int fprintf(FILE *, const char *, ...) - a very rough implementation to make +// output useful. +GenericValue lle_X_fprintf(const FunctionType *FT, + const std::vector &Args) { assert(Args.size() >= 2); char Buffer[10000]; - vector NewArgs; + std::vector NewArgs; NewArgs.push_back(PTOGV(Buffer)); NewArgs.insert(NewArgs.end(), Args.begin()+1, Args.end()); GenericValue GV = lle_X_sprintf(FT, NewArgs); - fputs(Buffer, getFILE(GVTOP(Args[0]))); + fputs(Buffer, (FILE *) GVTOP(Args[0])); return GV; } -// int __cxa_guard_acquire (__guard *g); -GenericValue lle_X___cxa_guard_acquire(FunctionType *FT, - const vector &Args) { - assert(Args.size() == 1); - GenericValue GV; -#ifdef __linux__ - GV.IntVal = APInt(32, __cxxabiv1::__cxa_guard_acquire ( - (__cxxabiv1::__guard*)GVTOP(Args[0]))); -#else - assert(0 && "Can't call __cxa_guard_acquire on this platform"); -#endif - return GV; -} - -// void __cxa_guard_release (__guard *g); -GenericValue lle_X___cxa_guard_release(FunctionType *FT, - const vector &Args) { - assert(Args.size() == 1); -#ifdef __linux__ - __cxxabiv1::__cxa_guard_release ((__cxxabiv1::__guard*)GVTOP(Args[0])); -#else - assert(0 && "Can't call __cxa_guard_release on this platform"); -#endif - return GenericValue(); -} - } // End extern "C" void Interpreter::initializeExternalFunctions() { - FuncNames["lle_X_putchar"] = lle_X_putchar; - FuncNames["lle_X__IO_putc"] = lle_X__IO_putc; + FuncNames["lle_X_atexit"] = lle_X_atexit; FuncNames["lle_X_exit"] = lle_X_exit; FuncNames["lle_X_abort"] = lle_X_abort; - FuncNames["lle_X_malloc"] = lle_X_malloc; - FuncNames["lle_X_calloc"] = lle_X_calloc; - FuncNames["lle_X_realloc"] = lle_X_realloc; - FuncNames["lle_X_free"] = lle_X_free; - FuncNames["lle_X_atoi"] = lle_X_atoi; - FuncNames["lle_X_pow"] = lle_X_pow; - FuncNames["lle_X_sin"] = lle_X_sin; - FuncNames["lle_X_cos"] = lle_X_cos; - FuncNames["lle_X_exp"] = lle_X_exp; - FuncNames["lle_X_log"] = lle_X_log; - FuncNames["lle_X_floor"] = lle_X_floor; - FuncNames["lle_X_srand"] = lle_X_srand; - FuncNames["lle_X_rand"] = lle_X_rand; -#ifdef HAVE_RAND48 - FuncNames["lle_X_drand48"] = lle_X_drand48; - FuncNames["lle_X_srand48"] = lle_X_srand48; - FuncNames["lle_X_lrand48"] = lle_X_lrand48; -#endif - FuncNames["lle_X_sqrt"] = lle_X_sqrt; - FuncNames["lle_X_puts"] = lle_X_puts; + FuncNames["lle_X_printf"] = lle_X_printf; FuncNames["lle_X_sprintf"] = lle_X_sprintf; FuncNames["lle_X_sscanf"] = lle_X_sscanf; FuncNames["lle_X_scanf"] = lle_X_scanf; - FuncNames["lle_i_clock"] = lle_i_clock; - - FuncNames["lle_X_strcmp"] = lle_X_strcmp; - FuncNames["lle_X_strcat"] = lle_X_strcat; - FuncNames["lle_X_strcpy"] = lle_X_strcpy; - FuncNames["lle_X_strlen"] = lle_X_strlen; - FuncNames["lle_X___strdup"] = lle_X___strdup; - FuncNames["lle_X_memset"] = lle_X_memset; - FuncNames["lle_X_memcpy"] = lle_X_memcpy; - FuncNames["lle_X_memmove"] = lle_X_memmove; - - FuncNames["lle_X_fopen"] = lle_X_fopen; - FuncNames["lle_X_fclose"] = lle_X_fclose; - FuncNames["lle_X_feof"] = lle_X_feof; - FuncNames["lle_X_fread"] = lle_X_fread; - FuncNames["lle_X_fwrite"] = lle_X_fwrite; - FuncNames["lle_X_fgets"] = lle_X_fgets; - FuncNames["lle_X_fflush"] = lle_X_fflush; - FuncNames["lle_X_fgetc"] = lle_X_getc; - FuncNames["lle_X_getc"] = lle_X_getc; - FuncNames["lle_X__IO_getc"] = lle_X__IO_getc; - FuncNames["lle_X_fputc"] = lle_X_fputc; - FuncNames["lle_X_ungetc"] = lle_X_ungetc; FuncNames["lle_X_fprintf"] = lle_X_fprintf; - FuncNames["lle_X_freopen"] = lle_X_freopen; - - FuncNames["lle_X___cxa_guard_acquire"] = lle_X___cxa_guard_acquire; - FuncNames["lle_X____cxa_guard_release"] = lle_X___cxa_guard_release; } From nicholas at mxc.ca Wed Feb 4 00:27:45 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 04 Feb 2009 06:27:45 -0000 Subject: [llvm-commits] [llvm] r63724 - in /llvm/trunk: configure include/llvm/Config/config.h.in Message-ID: <200902040627.n146Rjp6002192@zion.cs.uiuc.edu> Author: nicholas Date: Wed Feb 4 00:27:44 2009 New Revision: 63724 URL: http://llvm.org/viewvc/llvm-project?rev=63724&view=rev Log: Regenerate. Modified: llvm/trunk/configure llvm/trunk/include/llvm/Config/config.h.in Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=63724&r1=63723&r2=63724&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Wed Feb 4 00:27:44 2009 @@ -907,6 +907,7 @@ LLVMGXX USE_UDIS86 HAVE_PTHREAD +HAVE_FFI HUGE_VAL_SANITY ALLOCA MMAP_FILE @@ -10861,7 +10862,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext + echo '#line 13009 "configure"' > conftest.$ac_ext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 (eval $ac_compile) 2>&5 ac_status=$? @@ -14723,11 +14724,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:14726: $lt_compile\"" >&5) + (eval echo "\"\$as_me:14727: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:14730: \$? = $ac_status" >&5 + echo "$as_me:14731: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -14991,11 +14992,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:14994: $lt_compile\"" >&5) + (eval echo "\"\$as_me:14995: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:14998: \$? = $ac_status" >&5 + echo "$as_me:14999: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -15095,11 +15096,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:15098: $lt_compile\"" >&5) + (eval echo "\"\$as_me:15099: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:15102: \$? = $ac_status" >&5 + echo "$as_me:15103: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -17547,7 +17548,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext <&5) + (eval echo "\"\$as_me:20019: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:20022: \$? = $ac_status" >&5 + echo "$as_me:20023: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -20119,11 +20120,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:20122: $lt_compile\"" >&5) + (eval echo "\"\$as_me:20123: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:20126: \$? = $ac_status" >&5 + echo "$as_me:20127: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -21689,11 +21690,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21692: $lt_compile\"" >&5) + (eval echo "\"\$as_me:21693: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:21696: \$? = $ac_status" >&5 + echo "$as_me:21697: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -21793,11 +21794,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21796: $lt_compile\"" >&5) + (eval echo "\"\$as_me:21797: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:21800: \$? = $ac_status" >&5 + echo "$as_me:21801: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -24028,11 +24029,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:24031: $lt_compile\"" >&5) + (eval echo "\"\$as_me:24032: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:24035: \$? = $ac_status" >&5 + echo "$as_me:24036: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -24296,11 +24297,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:24299: $lt_compile\"" >&5) + (eval echo "\"\$as_me:24300: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:24303: \$? = $ac_status" >&5 + echo "$as_me:24304: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -24400,11 +24401,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:24403: $lt_compile\"" >&5) + (eval echo "\"\$as_me:24404: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:24407: \$? = $ac_status" >&5 + echo "$as_me:24408: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -27744,6 +27745,91 @@ fi +{ echo "$as_me:$LINENO: checking for ffi_call in -lffi" >&5 +echo $ECHO_N "checking for ffi_call in -lffi... $ECHO_C" >&6; } +if test "${ac_cv_lib_ffi_ffi_call+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lffi $LIBS" +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char ffi_call (); +int +main () +{ +return ffi_call (); + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && + { ac_try='test -z "$ac_c_werror_flag" || test ! -s conftest.err' + { (case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest$ac_exeext' + { (case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; }; then + ac_cv_lib_ffi_ffi_call=yes +else + echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_lib_ffi_ffi_call=no +fi + +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ echo "$as_me:$LINENO: result: $ac_cv_lib_ffi_ffi_call" >&5 +echo "${ECHO_T}$ac_cv_lib_ffi_ffi_call" >&6; } +if test $ac_cv_lib_ffi_ffi_call = yes; then + have_libffi=1 +else + { echo "$as_me:$LINENO: WARNING: libffi not found - disabling external calls from interpreter" >&5 +echo "$as_me: WARNING: libffi not found - disabling external calls from interpreter" >&2;} +fi + + { echo "$as_me:$LINENO: checking for library containing mallinfo" >&5 echo $ECHO_N "checking for library containing mallinfo... $ECHO_C" >&6; } if test "${ac_cv_search_mallinfo+set}" = set; then @@ -29986,6 +30072,180 @@ fi +if test -n "$have_libffi" ; then + + +for ac_header in ffi.h ffi/ffi.h +do +as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + { echo "$as_me:$LINENO: checking for $ac_header" >&5 +echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +fi +ac_res=`eval echo '${'$as_ac_Header'}'` + { echo "$as_me:$LINENO: result: $ac_res" >&5 +echo "${ECHO_T}$ac_res" >&6; } +else + # Is the header compilable? +{ echo "$as_me:$LINENO: checking $ac_header usability" >&5 +echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +$ac_includes_default +#include <$ac_header> +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && + { ac_try='test -z "$ac_c_werror_flag" || test ! -s conftest.err' + { (case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' + { (case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; }; then + ac_header_compiler=yes +else + echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_header_compiler=no +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +{ echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 +echo "${ECHO_T}$ac_header_compiler" >&6; } + +# Is the header present? +{ echo "$as_me:$LINENO: checking $ac_header presence" >&5 +echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include <$ac_header> +_ACEOF +if { (ac_try="$ac_cpp conftest.$ac_ext" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 + (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } >/dev/null; then + if test -s conftest.err; then + ac_cpp_err=$ac_c_preproc_warn_flag + ac_cpp_err=$ac_cpp_err$ac_c_werror_flag + else + ac_cpp_err= + fi +else + ac_cpp_err=yes +fi +if test -z "$ac_cpp_err"; then + ac_header_preproc=yes +else + echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_header_preproc=no +fi + +rm -f conftest.err conftest.$ac_ext +{ echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 +echo "${ECHO_T}$ac_header_preproc" >&6; } + +# So? What about this header? +case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in + yes:no: ) + { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 +echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} + { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 +echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} + ac_header_preproc=yes + ;; + no:yes:* ) + { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 +echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} + { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 +echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} + { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 +echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} + { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 +echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} + { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 +echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} + { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 +echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} + ( cat <<\_ASBOX +## ----------------------------------- ## +## Report this to llvmbugs at cs.uiuc.edu ## +## ----------------------------------- ## +_ASBOX + ) | sed "s/^/$as_me: WARNING: /" >&2 + ;; +esac +{ echo "$as_me:$LINENO: checking for $ac_header" >&5 +echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + eval "$as_ac_Header=\$ac_header_preproc" +fi +ac_res=`eval echo '${'$as_ac_Header'}'` + { echo "$as_me:$LINENO: result: $ac_res" >&5 +echo "${ECHO_T}$ac_res" >&6; } + +fi +if test `eval echo '${'$as_ac_Header'}'` = yes; then + cat >>confdefs.h <<_ACEOF +#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + HAVE_FFI=1 + +fi + +done + +fi + { echo "$as_me:$LINENO: checking for HUGE_VAL sanity" >&5 @@ -35477,6 +35737,7 @@ LLVMGXX!$LLVMGXX$ac_delim USE_UDIS86!$USE_UDIS86$ac_delim HAVE_PTHREAD!$HAVE_PTHREAD$ac_delim +HAVE_FFI!$HAVE_FFI$ac_delim HUGE_VAL_SANITY!$HUGE_VAL_SANITY$ac_delim ALLOCA!$ALLOCA$ac_delim MMAP_FILE!$MMAP_FILE$ac_delim @@ -35506,7 +35767,7 @@ LTLIBOBJS!$LTLIBOBJS$ac_delim _ACEOF - if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 81; then + if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 82; then break elif $ac_last_try; then { { echo "$as_me:$LINENO: error: could not make $CONFIG_STATUS" >&5 Modified: llvm/trunk/include/llvm/Config/config.h.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.in?rev=63724&r1=63723&r2=63724&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/config.h.in (original) +++ llvm/trunk/include/llvm/Config/config.h.in Wed Feb 4 00:27:44 2009 @@ -109,6 +109,12 @@ /* Define to 1 if you have the header file. */ #undef HAVE_FCNTL_H +/* Define to 1 if you have the header file. */ +#undef HAVE_FFI_FFI_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_FFI_H + /* Set to 1 if the finite function is found in */ #undef HAVE_FINITE_IN_IEEEFP_H From baldrick at free.fr Wed Feb 4 01:11:17 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 4 Feb 2009 08:11:17 +0100 Subject: [llvm-commits] [llvm] r63641 - in /llvm/trunk/lib/CodeGen/SelectionDAG: SelectionDAG.cpp SelectionDAGISel.cpp In-Reply-To: <200902031846.n13IkXcH010986@zion.cs.uiuc.edu> References: <200902031846.n13IkXcH010986@zion.cs.uiuc.edu> Message-ID: <200902040811.17747.baldrick@free.fr> Hi Devang, > First initialize DAG otherwise dwarf writer is used uninitialized. > Duncan spotted this. Thanks! is this fix correct? Someplace was trying to output debug info, and was using an uninitialized DW. Now that DW is zero, it won't crash but it also won't output the debug info. But maybe it should be outputting debug info? If so, then DW needs to be initialized to a non-null value earlier... Ciao, Duncan. > > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63641&r1=63640&r2=63641&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Feb 3 12:46:32 2009 > @@ -787,7 +787,7 @@ > } > > SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) > - : TLI(tli), FLI(fli), > + : TLI(tli), FLI(fli), DW(0), > EntryNode(ISD::EntryToken, getVTList(MVT::Other)), > Root(getEntryNode()) { > AllNodes.push_back(&EntryNode); > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=63641&r1=63640&r2=63641&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Feb 3 12:46:32 2009 > @@ -313,10 +313,10 @@ > RegInfo = &MF->getRegInfo(); > DOUT << "\n\n\n=== " << Fn.getName() << "\n"; > > - FuncInfo->set(Fn, *MF, *CurDAG, EnableFastISel); > MachineModuleInfo *MMI = getAnalysisIfAvailable(); > DwarfWriter *DW = getAnalysisIfAvailable(); > CurDAG->init(*MF, MMI, DW); > + FuncInfo->set(Fn, *MF, *CurDAG, EnableFastISel); > SDL->init(GFI, *AA); > > for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From evan.cheng at apple.com Wed Feb 4 01:17:49 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Feb 2009 07:17:49 -0000 Subject: [llvm-commits] [llvm] r63725 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp Message-ID: <200902040717.n147HnF2003824@zion.cs.uiuc.edu> Author: evancheng Date: Wed Feb 4 01:17:49 2009 New Revision: 63725 URL: http://llvm.org/viewvc/llvm-project?rev=63725&view=rev Log: For now, only hoist re-materilizable instructions. LICM will increase register pressure. We want to avoid spilling more instructions if it's possible. Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=63725&r1=63724&r2=63725&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Wed Feb 4 01:17:49 2009 @@ -186,18 +186,27 @@ if (TID.mayStore() || TID.isCall() || TID.isTerminator() || TID.hasUnmodeledSideEffects()) return false; - + + bool isInvLoad = false; if (TID.mayLoad()) { // Okay, this instruction does a load. As a refinement, we allow the target // to decide whether the loaded value is actually a constant. If so, we can // actually use it as a load. - if (!TII->isInvariantLoad(&I)) + isInvLoad = TII->isInvariantLoad(&I); + if (!isInvLoad) // FIXME: we should be able to sink loads with no other side effects if // there is nothing that can change memory from here until the end of // block. This is a trivial form of alias analysis. return false; } + // FIXME: For now, only hoist re-materilizable instructions. LICM will + // increase register pressure. We want to make sure it doesn't increase + // spilling. + if (!isInvLoad && (!TID.isRematerializable() || + !TII->isTriviallyReMaterializable(&I))) + return false; + DEBUG({ DOUT << "--- Checking if we can hoist " << I; if (I.getDesc().getImplicitUses()) { From evan.cheng at apple.com Wed Feb 4 03:19:56 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Feb 2009 09:19:56 -0000 Subject: [llvm-commits] [llvm] r63728 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp Message-ID: <200902040919.n149JuiI017932@zion.cs.uiuc.edu> Author: evancheng Date: Wed Feb 4 03:19:56 2009 New Revision: 63728 URL: http://llvm.org/viewvc/llvm-project?rev=63728&view=rev Log: Don't bother hoisting out a "cheap" instruction if all of its uses are PHIs. LICM "cheap" instructions are not particularly beneficial to start with. This will just end up making the copies harder to coalesce. Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=63728&r1=63727&r2=63728&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Wed Feb 4 03:19:56 2009 @@ -76,6 +76,10 @@ /// bool IsLoopInvariantInst(MachineInstr &I); + /// IsProfitableToHoist - Return true if it is potentially profitable to + /// hoist the given loop invariant. + bool IsProfitableToHoist(MachineInstr &MI); + /// HoistRegion - Walk the specified region of the CFG (defined by all /// blocks dominated by the specified block, and that are in the current /// loop) in depth first order w.r.t the DominatorTree. This allows us to @@ -187,26 +191,17 @@ TID.hasUnmodeledSideEffects()) return false; - bool isInvLoad = false; if (TID.mayLoad()) { // Okay, this instruction does a load. As a refinement, we allow the target // to decide whether the loaded value is actually a constant. If so, we can // actually use it as a load. - isInvLoad = TII->isInvariantLoad(&I); - if (!isInvLoad) + if (!TII->isInvariantLoad(&I)) // FIXME: we should be able to sink loads with no other side effects if // there is nothing that can change memory from here until the end of // block. This is a trivial form of alias analysis. return false; } - // FIXME: For now, only hoist re-materilizable instructions. LICM will - // increase register pressure. We want to make sure it doesn't increase - // spilling. - if (!isInvLoad && (!TID.isRematerializable() || - !TII->isTriviallyReMaterializable(&I))) - return false; - DEBUG({ DOUT << "--- Checking if we can hoist " << I; if (I.getDesc().getImplicitUses()) { @@ -263,11 +258,61 @@ return true; } +/// HasOnlyPHIUses - Return true if the only uses of Reg are PHIs. +static bool HasOnlyPHIUses(unsigned Reg, MachineRegisterInfo *RegInfo) { + bool OnlyPHIUse = false; + for (MachineRegisterInfo::use_iterator UI = RegInfo->use_begin(Reg), + UE = RegInfo->use_end(); UI != UE; ++UI) { + MachineInstr *UseMI = &*UI; + if (UseMI->getOpcode() != TargetInstrInfo::PHI) + return false; + OnlyPHIUse = true; + } + return OnlyPHIUse; +} + +/// IsProfitableToHoist - Return true if it is potentially profitable to hoist +/// the given loop invariant. +bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) { + const TargetInstrDesc &TID = MI.getDesc(); + + bool isInvLoad = false; + if (TID.mayLoad()) { + isInvLoad = TII->isInvariantLoad(&MI); + if (!isInvLoad) + return false; + } + + // FIXME: For now, only hoist re-materilizable instructions. LICM will + // increase register pressure. We want to make sure it doesn't increase + // spilling. + if (!isInvLoad && (!TID.isRematerializable() || + !TII->isTriviallyReMaterializable(&MI))) + return false; + + if (!TID.isAsCheapAsAMove()) + return true; + + // If the instruction is "cheap" and the only uses of the register(s) defined + // by this MI are PHIs, then don't hoist it. Otherwise we just end up with a + // cheap instruction (e.g. constant) with long live interval feeeding into + // copies that are not always coalesced away. + bool OnlyPHIUses = false; + for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI.getOperand(i); + if (!MO.isReg() || !MO.isDef()) + continue; + OnlyPHIUses |= HasOnlyPHIUses(MO.getReg(), RegInfo); + } + return !OnlyPHIUses; +} + /// Hoist - When an instruction is found to use only loop invariant operands /// that are safe to hoist, this instruction is called to do the dirty work. /// void MachineLICM::Hoist(MachineInstr &MI) { if (!IsLoopInvariantInst(MI)) return; + if (!IsProfitableToHoist(MI)) return; // Now move the instructions to the predecessor, inserting it before any // terminator instructions. From evan.cheng at apple.com Wed Feb 4 03:21:58 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Feb 2009 09:21:58 -0000 Subject: [llvm-commits] [llvm] r63729 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp Message-ID: <200902040921.n149Lxxl018068@zion.cs.uiuc.edu> Author: evancheng Date: Wed Feb 4 03:21:58 2009 New Revision: 63729 URL: http://llvm.org/viewvc/llvm-project?rev=63729&view=rev Log: Don't call isInvariantLoad twice. Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=63729&r1=63728&r2=63729&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Wed Feb 4 03:21:58 2009 @@ -276,18 +276,11 @@ bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); - bool isInvLoad = false; - if (TID.mayLoad()) { - isInvLoad = TII->isInvariantLoad(&MI); - if (!isInvLoad) - return false; - } - // FIXME: For now, only hoist re-materilizable instructions. LICM will // increase register pressure. We want to make sure it doesn't increase // spilling. - if (!isInvLoad && (!TID.isRematerializable() || - !TII->isTriviallyReMaterializable(&MI))) + if (!TID.mayLoad() && (!TID.isRematerializable() || + !TII->isTriviallyReMaterializable(&MI))) return false; if (!TID.isAsCheapAsAMove()) From baldrick at free.fr Wed Feb 4 04:17:20 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 04 Feb 2009 10:17:20 -0000 Subject: [llvm-commits] [llvm] r63730 - in /llvm/trunk: lib/VMCore/ConstantFold.cpp test/Transforms/InstCombine/2009-02-04-FPBitcast.ll Message-ID: <200902041017.n14AHL3F020546@zion.cs.uiuc.edu> Author: baldrick Date: Wed Feb 4 04:17:14 2009 New Revision: 63730 URL: http://llvm.org/viewvc/llvm-project?rev=63730&view=rev Log: Fix PR3468: a crash when constant folding a bitcast of i80 to x86 long double (this was presumably generated by sroa). Added: llvm/trunk/test/Transforms/InstCombine/2009-02-04-FPBitcast.ll Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantFold.cpp?rev=63730&r1=63729&r2=63730&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/ConstantFold.cpp (original) +++ llvm/trunk/lib/VMCore/ConstantFold.cpp Wed Feb 4 04:17:14 2009 @@ -153,12 +153,11 @@ // Integral -> Integral. This is a no-op because the bit widths must // be the same. Consequently, we just fold to V. return V; - - if (DestTy->isFloatingPoint()) { - assert((DestTy == Type::DoubleTy || DestTy == Type::FloatTy) && - "Unknown FP type!"); - return ConstantFP::get(APFloat(CI->getValue())); - } + + if (DestTy->isFloatingPoint()) + return ConstantFP::get(APFloat(CI->getValue(), + DestTy != Type::PPC_FP128Ty)); + // Otherwise, can't fold this (vector?) return 0; } Added: llvm/trunk/test/Transforms/InstCombine/2009-02-04-FPBitcast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2009-02-04-FPBitcast.ll?rev=63730&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/2009-02-04-FPBitcast.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/2009-02-04-FPBitcast.ll Wed Feb 4 04:17:14 2009 @@ -0,0 +1,7 @@ +; RUN: llvm-as < %s | opt -instcombine +; PR3468 + +define x86_fp80 @cast() { + %tmp = bitcast i80 0 to x86_fp80 ; [#uses=1] + ret x86_fp80 %tmp +} From baldrick at free.fr Wed Feb 4 05:17:15 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 04 Feb 2009 11:17:15 -0000 Subject: [llvm-commits] [llvm] r63731 - in /llvm/trunk: lib/VMCore/ConstantFold.cpp test/Transforms/InstCombine/2009-02-04-FPBitcast.ll Message-ID: <200902041117.n14BHGbo026314@zion.cs.uiuc.edu> Author: baldrick Date: Wed Feb 4 05:17:06 2009 New Revision: 63731 URL: http://llvm.org/viewvc/llvm-project?rev=63731&view=rev Log: Allow the inverse transform x86_fp80 -> i80 (also fires during the Ada build). Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp llvm/trunk/test/Transforms/InstCombine/2009-02-04-FPBitcast.ll Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantFold.cpp?rev=63731&r1=63730&r2=63731&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/ConstantFold.cpp (original) +++ llvm/trunk/lib/VMCore/ConstantFold.cpp Wed Feb 4 05:17:06 2009 @@ -161,17 +161,12 @@ // Otherwise, can't fold this (vector?) return 0; } - + // Handle ConstantFP input. - if (const ConstantFP *FP = dyn_cast(V)) { + if (const ConstantFP *FP = dyn_cast(V)) // FP -> Integral. - if (DestTy == Type::Int32Ty) { - return ConstantInt::get(FP->getValueAPF().bitcastToAPInt()); - } else { - assert(DestTy == Type::Int64Ty && "only support f32/f64 for now!"); - return ConstantInt::get(FP->getValueAPF().bitcastToAPInt()); - } - } + return ConstantInt::get(FP->getValueAPF().bitcastToAPInt()); + return 0; } Modified: llvm/trunk/test/Transforms/InstCombine/2009-02-04-FPBitcast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2009-02-04-FPBitcast.ll?rev=63731&r1=63730&r2=63731&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/2009-02-04-FPBitcast.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/2009-02-04-FPBitcast.ll Wed Feb 4 05:17:06 2009 @@ -5,3 +5,8 @@ %tmp = bitcast i80 0 to x86_fp80 ; [#uses=1] ret x86_fp80 %tmp } + +define i80 @invcast() { + %tmp = bitcast x86_fp80 0xK00000000000000000000 to i80 ; [#uses=1] + ret i80 %tmp +} From mrs at apple.com Wed Feb 4 10:43:37 2009 From: mrs at apple.com (Mike Stump) Date: Wed, 4 Feb 2009 08:43:37 -0800 Subject: [llvm-commits] [llvm] r63623 - in /llvm/trunk/tools: Makefile gold/ gold/Makefile gold/README.txt gold/gold-plugin.cpp In-Reply-To: <49891B6A.1010106@mxc.ca> References: <200902030713.n137DP9o009780@zion.cs.uiuc.edu> <200902031042.11251.baldrick@free.fr> <49891B6A.1010106@mxc.ca> Message-ID: <1A3250C2-449A-466A-B616-49AC4D036D9C@apple.com> On Feb 3, 2009, at 8:36 PM, Nick Lewycky wrote: > With Rafael's patch to llvm-gcc in r63633, we now get transparent LTO > with the gold plugin and CFLAGS=-O4 -use-gold-plugin. Hum, can we configure in -use-gold-plugin so that we get goldness with just -O4 when the environment can support it? From stuart at apple.com Wed Feb 4 10:46:20 2009 From: stuart at apple.com (Stuart Hastings) Date: Wed, 04 Feb 2009 16:46:20 -0000 Subject: [llvm-commits] [llvm] r63736 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200902041646.n14GkKve004174@zion.cs.uiuc.edu> Author: stuart Date: Wed Feb 4 10:46:19 2009 New Revision: 63736 URL: http://llvm.org/viewvc/llvm-project?rev=63736&view=rev Log: Since I'm obliged to work with a development OS that currently doesn't support GraphViz, I've been using the foo->dump() facility. This patch is a minor rewrite to the SelectionDAG dump() stuff to make it a little more helpful. The existing foo->dump() functionality does not change; this patch adds foo->dumpr(). All of this is only useful when running LLVM under a debugger. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=63736&r1=63735&r2=63736&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Feb 4 10:46:19 2009 @@ -1329,8 +1329,12 @@ /// std::string getOperationName(const SelectionDAG *G = 0) const; static const char* getIndexedModeName(ISD::MemIndexedMode AM); + void print_types(raw_ostream &OS, const SelectionDAG *G) const; + void print_details(raw_ostream &OS, const SelectionDAG *G) const; void print(raw_ostream &OS, const SelectionDAG *G = 0) const; + void printr(raw_ostream &OS, const SelectionDAG *G = 0) const; void dump() const; + void dumpr() const; void dump(const SelectionDAG *G) const; static bool classof(const SDNode *) { return true; } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63736&r1=63735&r2=63736&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Feb 4 10:46:19 2009 @@ -5638,7 +5638,7 @@ errs().flush(); } -void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { +void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const { OS << (void*)this << ": "; for (unsigned i = 0, e = getNumValues(); i != e; ++i) { @@ -5649,15 +5649,9 @@ OS << getValueType(i).getMVTString(); } OS << " = " << getOperationName(G); +} - OS << " "; - for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { - if (i) OS << ", "; - OS << (void*)getOperand(i).getNode(); - if (unsigned RN = getOperand(i).getResNo()) - OS << ":" << RN; - } - +void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { SDNode *Mask = getOperand(2).getNode(); OS << "<"; @@ -5798,6 +5792,18 @@ } } +void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { + print_types(OS, G); + OS << " "; + for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { + if (i) OS << ", "; + OS << (void*)getOperand(i).getNode(); + if (unsigned RN = getOperand(i).getResNo()) + OS << ":" << RN; + } + print_details(OS, G); +} + static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) if (N->getOperand(i).getNode()->hasOneUse()) @@ -5826,6 +5832,47 @@ cerr << "\n\n"; } +void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const { + print_types(OS, G); + print_details(OS, G); +} + +typedef SmallPtrSet VisitedSDNodeSet; +static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent, const SelectionDAG *G, VisitedSDNodeSet &once) { + if (!once.insert(N)) // If we've been here before, return now. + return; + // Dump the current SDNode, but don't end the line yet. + OS << std::string(indent, ' '); + N->printr(OS, G); + // Having printed this SDNode, walk the children: + for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { + const SDNode *child = N->getOperand(i).getNode(); + if (i) OS << ","; + OS << " "; + if (child->getNumOperands() == 0) { + // This child has no grandchildren; print it inline right here. + child->printr(OS, G); + once.insert(child); + } else { // Just the address. FIXME: also print the child's opcode + OS << (void*)child; + if (unsigned RN = N->getOperand(i).getResNo()) + OS << ":" << RN; + } + } + OS << "\n"; + // Dump children that have grandchildren on their own line(s). + for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { + const SDNode *child = N->getOperand(i).getNode(); + DumpNodesr(OS, child, indent+2, G, once); + } +} + +void SDNode::dumpr() const { + VisitedSDNodeSet once; + DumpNodesr(errs(), this, 0, 0, once); + errs().flush(); +} + const Type *ConstantPoolSDNode::getType() const { if (isMachineConstantPoolEntry()) return Val.MachineCPVal->getType(); From baldrick at free.fr Wed Feb 4 10:51:03 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 4 Feb 2009 17:51:03 +0100 Subject: [llvm-commits] [llvm] r63736 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp In-Reply-To: <200902041646.n14GkKve004174@zion.cs.uiuc.edu> References: <200902041646.n14GkKve004174@zion.cs.uiuc.edu> Message-ID: <200902041751.04153.baldrick@free.fr> Hi Stuart, can you please document what the difference is between dump and dumpr; likewise print and printr. Thanks! Ciao, Duncan. From espindola at google.com Wed Feb 4 11:04:31 2009 From: espindola at google.com (Rafael Espindola) Date: Wed, 4 Feb 2009 17:04:31 +0000 Subject: [llvm-commits] [llvm] r63623 - in /llvm/trunk/tools: Makefile gold/ gold/Makefile gold/README.txt gold/gold-plugin.cpp In-Reply-To: <1A3250C2-449A-466A-B616-49AC4D036D9C@apple.com> References: <200902030713.n137DP9o009780@zion.cs.uiuc.edu> <200902031042.11251.baldrick@free.fr> <49891B6A.1010106@mxc.ca> <1A3250C2-449A-466A-B616-49AC4D036D9C@apple.com> Message-ID: <38a0d8450902040904s1280c627y148a4df97efd0d7e@mail.gmail.com> > Hum, can we configure in -use-gold-plugin so that we get goldness with > just -O4 when the environment can support it? Maybe. We would need a check the linker is gold. Not sure if it is ok do do it at configure time. What happens if the user changes the linker? We could try to check the linker version at run time, do you think it is worth it? Cheers, -- Rafael Avila de Espindola Google | Gordon House | Barrow Street | Dublin 4 | Ireland Registered in Dublin, Ireland | Registration Number: 368047 From gohman at apple.com Wed Feb 4 11:28:58 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 04 Feb 2009 17:28:58 -0000 Subject: [llvm-commits] [llvm] r63740 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200902041728.n14HSwpe006366@zion.cs.uiuc.edu> Author: djg Date: Wed Feb 4 11:28:58 2009 New Revision: 63740 URL: http://llvm.org/viewvc/llvm-project?rev=63740&view=rev Log: Minor code cleanups; no functionality change. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=63740&r1=63739&r2=63740&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Feb 4 11:28:58 2009 @@ -976,11 +976,11 @@ // Returns in ST0/ST1 are handled specially: these are pushed as operands to // the RET instruction and handled by the FP Stackifier. - if (RVLocs[i].getLocReg() == X86::ST0 || - RVLocs[i].getLocReg() == X86::ST1) { + if (VA.getLocReg() == X86::ST0 || + VA.getLocReg() == X86::ST1) { // If this is a copy from an xmm register to ST(0), use an FPExtend to // change the value to the FP stack register class. - if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) + if (isScalarFPTypeInSSEReg(VA.getValVT())) ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); RetOps.push_back(ValToCopy); // Don't emit a copytoreg. @@ -1042,7 +1042,8 @@ // Copy all of the result registers out of their specified physreg. for (unsigned i = 0; i != RVLocs.size(); ++i) { - MVT CopyVT = RVLocs[i].getValVT(); + CCValAssign &VA = RVLocs[i]; + MVT CopyVT = VA.getValVT(); // If this is x86-64, and we disabled SSE, we can't return FP values if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && @@ -1054,21 +1055,21 @@ // If this is a call to a function that returns an fp value on the floating // point stack, but where we prefer to use the value in xmm registers, copy // it out as F80 and use a truncate to move it from fp stack reg to xmm reg. - if ((RVLocs[i].getLocReg() == X86::ST0 || - RVLocs[i].getLocReg() == X86::ST1) && - isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) { + if ((VA.getLocReg() == X86::ST0 || + VA.getLocReg() == X86::ST1) && + isScalarFPTypeInSSEReg(VA.getValVT())) { CopyVT = MVT::f80; } - Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), + Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), CopyVT, InFlag).getValue(1); SDValue Val = Chain.getValue(0); InFlag = Chain.getValue(2); - if (CopyVT != RVLocs[i].getValVT()) { + if (CopyVT != VA.getValVT()) { // Round the F80 the right size, which also moves to the appropriate xmm // register. - Val = DAG.getNode(ISD::FP_ROUND, dl, RVLocs[i].getValVT(), Val, + Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, // This truncation won't change the value. DAG.getIntPtrConstant(1)); } From edwintorok at gmail.com Wed Feb 4 11:39:30 2009 From: edwintorok at gmail.com (Torok Edwin) Date: Wed, 04 Feb 2009 17:39:30 -0000 Subject: [llvm-commits] [llvm] r63741 - /llvm/trunk/tools/gold/gold-plugin.cpp Message-ID: <200902041739.n14HdUeg007139@zion.cs.uiuc.edu> Author: edwin Date: Wed Feb 4 11:39:30 2009 New Revision: 63741 URL: http://llvm.org/viewvc/llvm-project?rev=63741&view=rev Log: add support for .a files containing LLVM IR to the gold plugin Modified: llvm/trunk/tools/gold/gold-plugin.cpp Modified: llvm/trunk/tools/gold/gold-plugin.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/gold-plugin.cpp?rev=63741&r1=63740&r2=63741&view=diff ============================================================================== --- llvm/trunk/tools/gold/gold-plugin.cpp (original) +++ llvm/trunk/tools/gold/gold-plugin.cpp Wed Feb 4 11:39:30 2009 @@ -23,6 +23,7 @@ #include #include #include +#include using namespace llvm; @@ -44,6 +45,7 @@ struct claimed_file { lto_module_t M; void *handle; + void *buf; std::vector syms; }; @@ -155,19 +157,49 @@ /// with add_symbol if possible. ld_plugin_status claim_file_hook(const ld_plugin_input_file *file, int *claimed) { + void *buf = NULL; + printf("%s,%d,%d\n",file->name, file->offset, file->filesize); // If set, this means gold found IR in an ELF section. LLVM doesn't wrap its - // IR in ELF, so we know it's not us. - if (file->offset) - return LDPS_OK; - - if (!lto_module_is_object_file(file->name)) + // IR in ELF, so we know it's not us. But it can also be an .a file containing + // LLVM IR. + if (file->offset) { + if (lseek(file->fd, file->offset, SEEK_SET) == -1) { + (*message)(LDPL_ERROR, + "Failed to seek to archive member of %s at offset %d: %s\n", + file->name, + file->offset, strerror(errno)); + return LDPS_ERR; + } + buf = malloc(file->filesize); + if (!buf) { + (*message)(LDPL_ERROR, + "Failed to allocate buffer for archive member of size: %d\n", + file->filesize); + return LDPS_ERR; + } + if (read(file->fd, buf, file->filesize) != file->filesize) { + (*message)(LDPL_ERROR, + "Failed to read archive member of %s at offset %d: %s\n", + file->name, + file->offset, + strerror(errno)); + free(buf); + return LDPS_ERR; + } + if (!lto_module_is_object_file_in_memory(buf, file->filesize)) { + free(buf); + return LDPS_OK; + } + } else if (!lto_module_is_object_file(file->name)) return LDPS_OK; *claimed = 1; Modules.resize(Modules.size() + 1); claimed_file &cf = Modules.back(); - cf.M = lto_module_create(file->name); + cf.M = buf ? lto_module_create_from_memory(buf, file->filesize) : + lto_module_create(file->name); + cf.buf = buf; if (!cf.M) { (*message)(LDPL_ERROR, "Failed to create LLVM module: %s", lto_get_error_message()); @@ -201,6 +233,7 @@ break; default: (*message)(LDPL_ERROR, "Unknown scope attribute: %d", scope); + free(buf); return LDPS_ERR; } @@ -220,6 +253,7 @@ break; default: (*message)(LDPL_ERROR, "Unknown definition attribute: %d", definition); + free(buf); return LDPS_ERR; } @@ -235,6 +269,7 @@ if (!cf.syms.empty()) { if ((*add_symbols)(cf.handle, cf.syms.size(), &cf.syms[0]) != LDPS_OK) { (*message)(LDPL_ERROR, "Unable to add symbols!"); + free(buf); return LDPS_ERR; } } @@ -303,6 +338,10 @@ objFile->close(); lto_codegen_dispose(cg); + for (std::list::iterator I = Modules.begin(), + E = Modules.end(); I != E; ++I) { + free(I->buf); + } if ((*add_input_file)(const_cast(uniqueObjPath.c_str())) != LDPS_OK) { (*message)(LDPL_ERROR, "Unable to add .o file to the link."); From edwintorok at gmail.com Wed Feb 4 11:40:28 2009 From: edwintorok at gmail.com (Torok Edwin) Date: Wed, 04 Feb 2009 17:40:28 -0000 Subject: [llvm-commits] [llvm] r63742 - /llvm/trunk/tools/gold/gold-plugin.cpp Message-ID: <200902041740.n14HeS6c007226@zion.cs.uiuc.edu> Author: edwin Date: Wed Feb 4 11:40:28 2009 New Revision: 63742 URL: http://llvm.org/viewvc/llvm-project?rev=63742&view=rev Log: remove printf - it was there only for debugging! Modified: llvm/trunk/tools/gold/gold-plugin.cpp Modified: llvm/trunk/tools/gold/gold-plugin.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/gold-plugin.cpp?rev=63742&r1=63741&r2=63742&view=diff ============================================================================== --- llvm/trunk/tools/gold/gold-plugin.cpp (original) +++ llvm/trunk/tools/gold/gold-plugin.cpp Wed Feb 4 11:40:28 2009 @@ -158,7 +158,6 @@ ld_plugin_status claim_file_hook(const ld_plugin_input_file *file, int *claimed) { void *buf = NULL; - printf("%s,%d,%d\n",file->name, file->offset, file->filesize); // If set, this means gold found IR in an ELF section. LLVM doesn't wrap its // IR in ELF, so we know it's not us. But it can also be an .a file containing // LLVM IR. From stuart at apple.com Wed Feb 4 11:45:53 2009 From: stuart at apple.com (Stuart Hastings) Date: Wed, 4 Feb 2009 09:45:53 -0800 Subject: [llvm-commits] [llvm] r63736 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp In-Reply-To: <200902041751.04153.baldrick@free.fr> References: <200902041646.n14GkKve004174@zion.cs.uiuc.edu> <200902041751.04153.baldrick@free.fr> Message-ID: On Feb 4, 2009, at 8:51 AM, Duncan Sands wrote: > Hi Stuart, can you please document what the difference > is between dump and dumpr; likewise print and printr. Sorry to be clueless, but I don't know where the SelectionDAG dump and print functions are documented. :-( Please direct me. I presumed that very few LLVM developers were using the SelectionDAG dump(), as it only prints one instruction, and that doesn't seem very "friendly" when you're working on a DAG. dumpr() prints all all the children of a given node, as if you picked up that node and walked the DAG underneath. Trivial nodes that have no children are printed inline, on the same line as their parent, and may appear multiple times in one dump. Non-trivial nodes that have children go on a unique line, and are printed exactly once. The resulting dump seems "denser" IMHO, making more effective use of the screen area. I made the dump go top-down because of a comment from Dale; personally, I don't care if the root node is at the top or the bottom. printr() is just print(), but it omits the usual list of children so they may be dumped by other means (e.g. simple children printed inline). I prefer to run GDB under Emacs. With dumpr(), I can see the entire DAG as viewed from a particular node, and I can use the Emacs search feature to find and highlight multiple references to a given node. (Emacs highlights all the matching strings visible in a buffer window. The color choices are garish, but the matches are immediately obvious. :-) If nobody objects, I would propose to delete the existing SelectionDAG dump() and rename dumpr() to replace it. I guess the existing print() should stay, as it seems to be an LLVM requirement (?). Mike Stump has informed me that he has a tweaked version of GraphViz that should work on the OS I'm obliged to use. IMHO GraphViz would be a vastly superior debugging aid when it's available. IMHO dumpr() is friendlier than dump(), but both are useless when you're dealing with a really large DAG. stuart From sabre at nondot.org Wed Feb 4 11:48:18 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 04 Feb 2009 17:48:18 -0000 Subject: [llvm-commits] [llvm] r63743 - /llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp Message-ID: <200902041748.n14HmIs5007800@zion.cs.uiuc.edu> Author: lattner Date: Wed Feb 4 11:48:18 2009 New Revision: 63743 URL: http://llvm.org/viewvc/llvm-project?rev=63743&view=rev Log: allow main to have any integer type. Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp?rev=63743&r1=63742&r2=63743&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp Wed Feb 4 11:48:18 2009 @@ -347,7 +347,7 @@ } // FALLS THROUGH case 0: - if (FTy->getReturnType() != Type::Int32Ty && + if (!isa(FTy->getReturnType()) && FTy->getReturnType() != Type::VoidTy) { cerr << "Invalid return type of main() supplied\n"; abort(); From dpatel at apple.com Wed Feb 4 11:49:12 2009 From: dpatel at apple.com (Devang Patel) Date: Wed, 4 Feb 2009 09:49:12 -0800 Subject: [llvm-commits] [llvm] r63641 - in /llvm/trunk/lib/CodeGen/SelectionDAG: SelectionDAG.cpp SelectionDAGISel.cpp In-Reply-To: <200902040811.17747.baldrick@free.fr> References: <200902031846.n13IkXcH010986@zion.cs.uiuc.edu> <200902040811.17747.baldrick@free.fr> Message-ID: <89F7310F-F2B6-409B-B02D-50959AAE7887@apple.com> On Feb 3, 2009, at 11:11 PM, Duncan Sands wrote: > Hi Devang, > >> First initialize DAG otherwise dwarf writer is used uninitialized. >> Duncan spotted this. Thanks! > > is this fix correct? Someplace was trying to output debug info, > and was using an uninitialized DW. Now that DW is zero, it won't > crash but it also won't output the debug info. > But maybe it should > be outputting debug info? If so, then DW needs to be initialized > to a non-null value earlier... ... it is. Now, CurDAG->init() happens before FuncInfo->set(..., *CurDAG, ..). init() sets DW and set(...) wants to output debug info. - Devang > > > Ciao, > > Duncan. > >> >> >> Modified: >> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp >> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp >> >> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63641&r1=63640&r2=63641&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Feb 3 >> 12:46:32 2009 >> @@ -787,7 +787,7 @@ >> } >> >> SelectionDAG::SelectionDAG(TargetLowering &tli, >> FunctionLoweringInfo &fli) >> - : TLI(tli), FLI(fli), >> + : TLI(tli), FLI(fli), DW(0), >> EntryNode(ISD::EntryToken, getVTList(MVT::Other)), >> Root(getEntryNode()) { >> AllNodes.push_back(&EntryNode); >> >> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=63641&r1=63640&r2=63641&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp >> (original) >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue >> Feb 3 12:46:32 2009 >> @@ -313,10 +313,10 @@ >> RegInfo = &MF->getRegInfo(); >> DOUT << "\n\n\n=== " << Fn.getName() << "\n"; >> >> - FuncInfo->set(Fn, *MF, *CurDAG, EnableFastISel); >> MachineModuleInfo *MMI = >> getAnalysisIfAvailable(); >> DwarfWriter *DW = getAnalysisIfAvailable(); >> CurDAG->init(*MF, MMI, DW); >> + FuncInfo->set(Fn, *MF, *CurDAG, EnableFastISel); >> SDL->init(GFI, *AA); >> >> for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > - Devang From kremenek at apple.com Wed Feb 4 12:01:42 2009 From: kremenek at apple.com (Ted Kremenek) Date: Wed, 04 Feb 2009 18:01:42 -0000 Subject: [llvm-commits] [llvm] r63746 - /llvm/tags/checker/checker-0.148/ Message-ID: <200902041801.n14I1gq4008851@zion.cs.uiuc.edu> Author: kremenek Date: Wed Feb 4 12:01:42 2009 New Revision: 63746 URL: http://llvm.org/viewvc/llvm-project?rev=63746&view=rev Log: Tagging checker-0.148. Added: llvm/tags/checker/checker-0.148/ - copied from r63745, llvm/trunk/ From evan.cheng at apple.com Wed Feb 4 12:18:58 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Feb 2009 18:18:58 -0000 Subject: [llvm-commits] [llvm] r63748 - /llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Message-ID: <200902041818.n14IIxk4010090@zion.cs.uiuc.edu> Author: evancheng Date: Wed Feb 4 12:18:58 2009 New Revision: 63748 URL: http://llvm.org/viewvc/llvm-project?rev=63748&view=rev Log: Skip over zero registers. Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=63748&r1=63747&r2=63748&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Wed Feb 4 12:18:58 2009 @@ -2449,6 +2449,8 @@ if (!MO.isReg()) continue; unsigned Reg = MO.getReg(); + if (!Reg) + continue; if (TargetRegisterInfo::isVirtualRegister(Reg)) DeadDefs.push_back(Reg); if (MO.isDead()) From mrs at apple.com Wed Feb 4 12:38:17 2009 From: mrs at apple.com (Mike Stump) Date: Wed, 4 Feb 2009 10:38:17 -0800 Subject: [llvm-commits] [llvm] r63623 - in /llvm/trunk/tools: Makefile gold/ gold/Makefile gold/README.txt gold/gold-plugin.cpp In-Reply-To: <38a0d8450902040904s1280c627y148a4df97efd0d7e@mail.gmail.com> References: <200902030713.n137DP9o009780@zion.cs.uiuc.edu> <200902031042.11251.baldrick@free.fr> <49891B6A.1010106@mxc.ca> <1A3250C2-449A-466A-B616-49AC4D036D9C@apple.com> <38a0d8450902040904s1280c627y148a4df97efd0d7e@mail.gmail.com> Message-ID: <7E0DC045-651D-4998-9666-F006061BE830@apple.com> On Feb 4, 2009, at 9:04 AM, Rafael Espindola wrote: > We would need a check the linker is gold. Not sure if it is ok do do > it at configure time. What happens if the user changes the linker? Assuming backwards compatibility is reasonably safe (gcc does it for as and ld all the time), never been much a problem. > We could try to check the linker version at run time, do you think > it is worth it? I think it is best to avoid the time hit at runtime. As for the general idea being worth it, if it works well, if the plugin is stable and improves codegen... If the user experience is horrible, better to default it to off. From edwintorok at gmail.com Wed Feb 4 12:46:26 2009 From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=) Date: Wed, 04 Feb 2009 20:46:26 +0200 Subject: [llvm-commits] [llvm] r63741 - /llvm/trunk/tools/gold/gold-plugin.cpp In-Reply-To: <200902041739.n14HdUeg007139@zion.cs.uiuc.edu> References: <200902041739.n14HdUeg007139@zion.cs.uiuc.edu> Message-ID: <4989E282.20805@gmail.com> On 2009-02-04 19:39, Torok Edwin wrote: > Author: edwin > Date: Wed Feb 4 11:39:30 2009 > New Revision: 63741 > > URL: http://llvm.org/viewvc/llvm-project?rev=63741&view=rev > Log: > add support for .a files containing LLVM IR to the gold plugin This currently doesn't work with .a files containing LLVM IR that are not linked with -Wl,--whole-archive. But it works for -Wl,--whole-archive, followed by .a file containing LLVM IR, and even .a file containing regular ELF objects (like libc_nonshared.a). I haven't figured how to make it work with .a files w/o --whole-archive because that requires an .a symbol table, but ranlib is unable to emit it (it runs successfully, it justs doesn't create the symbols). llvm-ranlib uses an incompatible format. Perhaps it could be taught to output ar compatible output? Best regards, --Edwin From espindola at google.com Wed Feb 4 12:55:01 2009 From: espindola at google.com (Rafael Espindola) Date: Wed, 4 Feb 2009 18:55:01 +0000 Subject: [llvm-commits] [llvm] r63623 - in /llvm/trunk/tools: Makefile gold/ gold/Makefile gold/README.txt gold/gold-plugin.cpp In-Reply-To: <7E0DC045-651D-4998-9666-F006061BE830@apple.com> References: <200902030713.n137DP9o009780@zion.cs.uiuc.edu> <200902031042.11251.baldrick@free.fr> <49891B6A.1010106@mxc.ca> <1A3250C2-449A-466A-B616-49AC4D036D9C@apple.com> <38a0d8450902040904s1280c627y148a4df97efd0d7e@mail.gmail.com> <7E0DC045-651D-4998-9666-F006061BE830@apple.com> Message-ID: <38a0d8450902041055k7de1b590gd809cda4d2eb0533@mail.gmail.com> > I think it is best to avoid the time hit at runtime. As for the > general idea being worth it, if it works well, if the plugin is stable > and improves codegen... If the user experience is horrible, better to > default it to off. Will keep that in mind :-) We will be testing and improving it. Depending on the progress we will try to enable it at -O4. Cheers, -- Rafael Avila de Espindola Google | Gordon House | Barrow Street | Dublin 4 | Ireland Registered in Dublin, Ireland | Registration Number: 368047 From sabre at nondot.org Wed Feb 4 13:08:02 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 04 Feb 2009 19:08:02 -0000 Subject: [llvm-commits] [llvm] r63751 - /llvm/trunk/lib/Target/X86/README-SSE.txt Message-ID: <200902041908.n14J82kD013698@zion.cs.uiuc.edu> Author: lattner Date: Wed Feb 4 13:08:01 2009 New Revision: 63751 URL: http://llvm.org/viewvc/llvm-project?rev=63751&view=rev Log: add a note, this is why we're faster at SciMark-MonteCarlo with SSE disabled. Modified: llvm/trunk/lib/Target/X86/README-SSE.txt Modified: llvm/trunk/lib/Target/X86/README-SSE.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-SSE.txt?rev=63751&r1=63750&r2=63751&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/README-SSE.txt (original) +++ llvm/trunk/lib/Target/X86/README-SSE.txt Wed Feb 4 13:08:01 2009 @@ -912,3 +912,43 @@ Consider using movlps instead of movsd to implement (scalar_to_vector (loadf64)) when code size is critical. movlps is slower than movsd on core2 but it's one byte shorter. + +//===---------------------------------------------------------------------===// + +We should use a dynamic programming based approach to tell when using FPStack +operations is cheaper than SSE. SciMark montecarlo contains code like this +for example: + +double MonteCarlo_num_flops(int Num_samples) { + return ((double) Num_samples)* 4.0; +} + +In fpstack mode, this compiles into: + +LCPI1_0: + .long 1082130432 ## float 4.000000e+00 +_MonteCarlo_num_flops: + subl $4, %esp + movl 8(%esp), %eax + movl %eax, (%esp) + fildl (%esp) + fmuls LCPI1_0 + addl $4, %esp + ret + +in SSE mode, it compiles into significantly slower code: + +_MonteCarlo_num_flops: + subl $12, %esp + cvtsi2sd 16(%esp), %xmm0 + mulsd LCPI1_0, %xmm0 + movsd %xmm0, (%esp) + fldl (%esp) + addl $12, %esp + ret + +There are also other cases in scimark where using fpstack is better, it is +cheaper to do fld1 than load from a constant pool for example, so +"load, add 1.0, store" is better done in the fp stack, etc. + +//===---------------------------------------------------------------------===// From sabre at nondot.org Wed Feb 4 13:09:08 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 04 Feb 2009 19:09:08 -0000 Subject: [llvm-commits] [llvm] r63752 - /llvm/trunk/lib/Target/X86/README-SSE.txt Message-ID: <200902041909.n14J98el013805@zion.cs.uiuc.edu> Author: lattner Date: Wed Feb 4 13:09:07 2009 New Revision: 63752 URL: http://llvm.org/viewvc/llvm-project?rev=63752&view=rev Log: Bill implemented this. Modified: llvm/trunk/lib/Target/X86/README-SSE.txt Modified: llvm/trunk/lib/Target/X86/README-SSE.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-SSE.txt?rev=63752&r1=63751&r2=63752&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/README-SSE.txt (original) +++ llvm/trunk/lib/Target/X86/README-SSE.txt Wed Feb 4 13:09:07 2009 @@ -841,42 +841,6 @@ movaps %xmm0, 0 //===---------------------------------------------------------------------===// -rdar://6037315 - -llvm-gcc-4.2 does the following for uint32_t -> float conversions on i386: - - uint32_t x; - float y = (float)x; - -becomes: - -movl %eax, -8(%ebp) // write x to the stack -movl $0x3ff00000, -4(%ebp) // 2^52 + x as a double at -4(%ebp) -movsd -8(%ebp), %xmm0 -subsd [2^52 double], %xmm0 // subtract 2^52 -- this is exact -cvtsd2ss %xmm0, %xmm0 // convert to single -- rounding happens here - -On merom/yonah, this takes a substantial stall. The following is a much -better option: - -movd %eax, %xmm0 // load x into low word of xmm0 -movsd [2^52 double], %xmm1 // load 2^52 into xmm1 -orpd %xmm1, %xmm0 // 2^52 + x in double precision -subsd %xmm1, %xmm0 // x in double precision -cvtsd2ss %xmm0, %xmm0 // x rounded to single precision - -IF we don't already need PIC, then the following is even faster still, at a -small cost to code size: - -movl $0x3ff00000, %ecx // conjure high word of 2^52 -movd %ecx, %xmm1 -movss %eax, %xmm0 // load x into low word of xmm0 -psllq $32, %xmm1 // 2^52 -orpd %xmm1, %xmm0 // 2^52 + x in double precision -subsd %xmm1, %xmm0 // x in double precision -cvtsd2ss %xmm0, %xmm0 // x in single precision - -//===---------------------------------------------------------------------===// rdar://5907648 This function: From edwintorok at gmail.com Wed Feb 4 13:12:26 2009 From: edwintorok at gmail.com (Torok Edwin) Date: Wed, 04 Feb 2009 19:12:26 -0000 Subject: [llvm-commits] [llvm] r63755 - /llvm/trunk/tools/gold/README.txt Message-ID: <200902041912.n14JCQsI014071@zion.cs.uiuc.edu> Author: edwin Date: Wed Feb 4 13:12:25 2009 New Revision: 63755 URL: http://llvm.org/viewvc/llvm-project?rev=63755&view=rev Log: mention that PIC is needed for libLTO and libLLVMgold Modified: llvm/trunk/tools/gold/README.txt Modified: llvm/trunk/tools/gold/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/README.txt?rev=63755&r1=63754&r2=63755&view=diff ============================================================================== --- llvm/trunk/tools/gold/README.txt (original) +++ llvm/trunk/tools/gold/README.txt Wed Feb 4 13:12:25 2009 @@ -13,5 +13,9 @@ Then build binutils with "make all-gold". To build the LLVMgold plugin, configure LLVM with the option ---with-binutils-include=/path/to/binutils/src/include/ . To use the +--with-binutils-include=/path/to/binutils/src/include/ --enable-pic. To use the plugin, run "ld-new --plugin /path/to/libLLVMgold.so". +Without PIC libLTO and libLLVMgold are not being built (because they would fail +link on x86-64 with a relocation error: PIC and non-PIC can't be combined). +As an alternative to passing --enable-pic, you can use 'make ENABLE_PIC=1' in +your entire LLVM build. From evan.cheng at apple.com Wed Feb 4 13:17:09 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 4 Feb 2009 11:17:09 -0800 Subject: [llvm-commits] [llvm] r63736 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp In-Reply-To: <200902041646.n14GkKve004174@zion.cs.uiuc.edu> References: <200902041646.n14GkKve004174@zion.cs.uiuc.edu> Message-ID: <61EFEB5F-5A8D-4B7A-8F02-2BF618A9541F@apple.com> This looks like it's longer than 80 col. :-) +static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent, const SelectionDAG *G, VisitedSDNodeSet &once) { Evan On Feb 4, 2009, at 8:46 AM, Stuart Hastings wrote: > Author: stuart > Date: Wed Feb 4 10:46:19 2009 > New Revision: 63736 > > URL: http://llvm.org/viewvc/llvm-project?rev=63736&view=rev > Log: > Since I'm obliged to work with a development OS that currently doesn't > support GraphViz, I've been using the foo->dump() facility. This > patch is a minor rewrite to the SelectionDAG dump() stuff to make it a > little more helpful. The existing foo->dump() functionality does not > change; this patch adds foo->dumpr(). All of this is only useful when > running LLVM under a debugger. > > Modified: > llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp > > Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=63736&r1=63735&r2=63736&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) > +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Feb 4 > 10:46:19 2009 > @@ -1329,8 +1329,12 @@ > /// > std::string getOperationName(const SelectionDAG *G = 0) const; > static const char* getIndexedModeName(ISD::MemIndexedMode AM); > + void print_types(raw_ostream &OS, const SelectionDAG *G) const; > + void print_details(raw_ostream &OS, const SelectionDAG *G) const; > void print(raw_ostream &OS, const SelectionDAG *G = 0) const; > + void printr(raw_ostream &OS, const SelectionDAG *G = 0) const; > void dump() const; > + void dumpr() const; > void dump(const SelectionDAG *G) const; > > static bool classof(const SDNode *) { return true; } > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63736&r1=63735&r2=63736&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Feb 4 > 10:46:19 2009 > @@ -5638,7 +5638,7 @@ > errs().flush(); > } > > -void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { > +void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) > const { > OS << (void*)this << ": "; > > for (unsigned i = 0, e = getNumValues(); i != e; ++i) { > @@ -5649,15 +5649,9 @@ > OS << getValueType(i).getMVTString(); > } > OS << " = " << getOperationName(G); > +} > > - OS << " "; > - for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { > - if (i) OS << ", "; > - OS << (void*)getOperand(i).getNode(); > - if (unsigned RN = getOperand(i).getResNo()) > - OS << ":" << RN; > - } > - > +void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) > const { > if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { > SDNode *Mask = getOperand(2).getNode(); > OS << "<"; > @@ -5798,6 +5792,18 @@ > } > } > > +void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { > + print_types(OS, G); > + OS << " "; > + for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { > + if (i) OS << ", "; > + OS << (void*)getOperand(i).getNode(); > + if (unsigned RN = getOperand(i).getResNo()) > + OS << ":" << RN; > + } > + print_details(OS, G); > +} > + > static void DumpNodes(const SDNode *N, unsigned indent, const > SelectionDAG *G) { > for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) > if (N->getOperand(i).getNode()->hasOneUse()) > @@ -5826,6 +5832,47 @@ > cerr << "\n\n"; > } > > +void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const { > + print_types(OS, G); > + print_details(OS, G); > +} > + > +typedef SmallPtrSet VisitedSDNodeSet; > +static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned > indent, const SelectionDAG *G, VisitedSDNodeSet &once) { > + if (!once.insert(N)) // If we've been here before, return now. > + return; > + // Dump the current SDNode, but don't end the line yet. > + OS << std::string(indent, ' '); > + N->printr(OS, G); > + // Having printed this SDNode, walk the children: > + for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { > + const SDNode *child = N->getOperand(i).getNode(); > + if (i) OS << ","; > + OS << " "; > + if (child->getNumOperands() == 0) { > + // This child has no grandchildren; print it inline right here. > + child->printr(OS, G); > + once.insert(child); > + } else { // Just the address. FIXME: also print the child's > opcode > + OS << (void*)child; > + if (unsigned RN = N->getOperand(i).getResNo()) > + OS << ":" << RN; > + } > + } > + OS << "\n"; > + // Dump children that have grandchildren on their own line(s). > + for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { > + const SDNode *child = N->getOperand(i).getNode(); > + DumpNodesr(OS, child, indent+2, G, once); > + } > +} > + > +void SDNode::dumpr() const { > + VisitedSDNodeSet once; > + DumpNodesr(errs(), this, 0, 0, once); > + errs().flush(); > +} > + > const Type *ConstantPoolSDNode::getType() const { > if (isMachineConstantPoolEntry()) > return Val.MachineCPVal->getType(); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090204/83fb6121/attachment.html From wangmp at apple.com Wed Feb 4 13:38:14 2009 From: wangmp at apple.com (Mon P Wang) Date: Wed, 04 Feb 2009 19:38:14 -0000 Subject: [llvm-commits] [llvm] r63760 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200902041938.n14JcFGo015187@zion.cs.uiuc.edu> Author: wangmp Date: Wed Feb 4 13:38:14 2009 New Revision: 63760 URL: http://llvm.org/viewvc/llvm-project?rev=63760&view=rev Log: Avoids generating a legalization assert for the case where a vector type is legal but when legalizing the operation, we split the vector type and generate a library call whose type needs to be promoted. For example, X86 with SSE on but MMX off, a divide v2i64 will be scalarized to 2 calls to a library using i64. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63760&r1=63759&r2=63760&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Feb 4 13:38:14 2009 @@ -68,6 +68,11 @@ /// being legalized (which could lead to non-serialized call sequences). bool IsLegalizingCall; + /// IsLegalizingCallArguments - This member is used only for the purpose + /// of providing assert to check for LegalizeTypes because legalizing an + /// operation might introduce call nodes that might need type legalization. + bool IsLegalizingCallArgs; + enum LegalizeAction { Legal, // The target natively supports this operation. Promote, // This operation should be executed in a larger type. @@ -368,7 +373,8 @@ void SelectionDAGLegalize::LegalizeDAG() { LastCALLSEQ_END = DAG.getEntryNode(); IsLegalizingCall = false; - + IsLegalizingCallArgs = false; + // The legalize process is inherently a bottom-up recursive process (users // legalize their uses before themselves). Given infinite stack space, we // could just start legalizing on the root and traverse the whole graph. In @@ -503,7 +509,7 @@ // those) or for build vector used as a mask for a vector shuffle. // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957. assert((TypesNeedLegalizing || getTypeAction(VT) == Legal || - Op.getOpcode() == ISD::TargetConstant || + IsLegalizingCallArgs || Op.getOpcode() == ISD::TargetConstant || Op.getOpcode() == ISD::BUILD_VECTOR) && "Illegal type introduced after type legalization?"); switch (getTypeAction(VT)) { @@ -1805,11 +1811,13 @@ // Recursively Legalize all of the inputs of the call end that do not lead // to this call start. This ensures that any libcalls that need be inserted // are inserted *before* the CALLSEQ_START. + IsLegalizingCallArgs = true; {SmallPtrSet NodesLeadingTo; for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, NodesLeadingTo); } + IsLegalizingCallArgs = false; // Now that we legalized all of the inputs (which may have inserted // libcalls) create the new CALLSEQ_START node. From gohman at apple.com Wed Feb 4 13:43:48 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 4 Feb 2009 11:43:48 -0800 Subject: [llvm-commits] [llvm] r63751 - /llvm/trunk/lib/Target/X86/README-SSE.txt In-Reply-To: <200902041908.n14J82kD013698@zion.cs.uiuc.edu> References: <200902041908.n14J82kD013698@zion.cs.uiuc.edu> Message-ID: On Feb 4, 2009, at 11:08 AM, Chris Lattner wrote: > Author: lattner > Date: Wed Feb 4 13:08:01 2009 > New Revision: 63751 > > URL: http://llvm.org/viewvc/llvm-project?rev=63751&view=rev > Log: > add a note, this is why we're faster at SciMark-MonteCarlo with > SSE disabled. > > Modified: > llvm/trunk/lib/Target/X86/README-SSE.txt > > Modified: llvm/trunk/lib/Target/X86/README-SSE.txt > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-SSE.txt?rev=63751&r1=63750&r2=63751&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/README-SSE.txt (original) > +++ llvm/trunk/lib/Target/X86/README-SSE.txt Wed Feb 4 13:08:01 2009 > @@ -912,3 +912,43 @@ > Consider using movlps instead of movsd to implement > (scalar_to_vector (loadf64)) > when code size is critical. movlps is slower than movsd on core2 but > it's one > byte shorter. > + > +// > = > = > = > --------------------------------------------------------------------- > ===// > + > +We should use a dynamic programming based approach to tell when > using FPStack > +operations is cheaper than SSE. SciMark montecarlo contains code > like this > +for example: > + > +double MonteCarlo_num_flops(int Num_samples) { > + return ((double) Num_samples)* 4.0; > +} This looks like a capital opportunity for inlining. It seems that this kind of thing only really matters in small functions when the compiler is hemmed in by the ABI. If code like this is hot, inlining it would probably yield a much better result than the best x87 boondoggle could achieve. Dan From clattner at apple.com Wed Feb 4 13:46:53 2009 From: clattner at apple.com (Chris Lattner) Date: Wed, 4 Feb 2009 11:46:53 -0800 Subject: [llvm-commits] [llvm] r63751 - /llvm/trunk/lib/Target/X86/README-SSE.txt In-Reply-To: References: <200902041908.n14J82kD013698@zion.cs.uiuc.edu> Message-ID: <01C62574-83D8-4698-9421-6D9B2276ADC9@apple.com> On Feb 4, 2009, at 11:43 AM, Dan Gohman wrote: >> +We should use a dynamic programming based approach to tell when >> using FPStack >> +operations is cheaper than SSE. SciMark montecarlo contains code >> like this >> +for example: >> + >> +double MonteCarlo_num_flops(int Num_samples) { >> + return ((double) Num_samples)* 4.0; >> +} > > This looks like a capital opportunity for inlining. It seems that > this kind of thing > only really matters in small functions when the compiler is hemmed in > by the > ABI. If code like this is hot, inlining it would probably yield a much > better result > than the best x87 boondoggle could achieve. The caller and callee are defined in separate files and the LTO wasn't being used. -Chris From natebegeman at mac.com Wed Feb 4 13:47:21 2009 From: natebegeman at mac.com (Nate Begeman) Date: Wed, 04 Feb 2009 19:47:21 -0000 Subject: [llvm-commits] [llvm] r63765 - in /llvm/trunk: ./ include/llvm/ include/llvm/Target/ lib/AsmParser/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/VMCore/ utils/TableGen/ Message-ID: <200902041947.n14JlMdj015607@zion.cs.uiuc.edu> Author: sampo Date: Wed Feb 4 13:47:21 2009 New Revision: 63765 URL: http://llvm.org/viewvc/llvm-project?rev=63765&view=rev Log: New feature: add support for target intrinsics being defined in the target directories themselves. This also means that VMCore no longer needs to know about every target's list of intrinsics. Future work will include converting the PowerPC target to this interface as an example implementation. Added: llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp Modified: llvm/trunk/Makefile.rules llvm/trunk/include/llvm/Function.h llvm/trunk/include/llvm/Intrinsics.h llvm/trunk/include/llvm/Intrinsics.td llvm/trunk/include/llvm/Module.h llvm/trunk/include/llvm/Target/TargetMachine.h llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp llvm/trunk/lib/VMCore/AutoUpgrade.cpp llvm/trunk/lib/VMCore/Function.cpp llvm/trunk/lib/VMCore/Module.cpp llvm/trunk/lib/VMCore/Verifier.cpp llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h llvm/trunk/utils/TableGen/CodeGenIntrinsics.h llvm/trunk/utils/TableGen/CodeGenTarget.cpp llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp llvm/trunk/utils/TableGen/IntrinsicEmitter.h llvm/trunk/utils/TableGen/TableGen.cpp Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=63765&r1=63764&r2=63765&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Wed Feb 4 13:47:21 2009 @@ -1346,6 +1346,11 @@ $(Echo) "Building $( RetTypes = ret_types; list ParamTypes = param_types; list Properties = properties; + + bit isTarget = 0; } /// GCCBuiltin - If this intrinsic exactly corresponds to a GCC builtin, this Modified: llvm/trunk/include/llvm/Module.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Module.h?rev=63765&r1=63764&r2=63765&view=diff ============================================================================== --- llvm/trunk/include/llvm/Module.h (original) +++ llvm/trunk/include/llvm/Module.h Wed Feb 4 13:47:21 2009 @@ -213,6 +213,10 @@ Constant *getOrInsertFunction(const std::string &Name, const Type *RetTy, ...) END_WITH_NULL; + Constant *getOrInsertTargetIntrinsic(const std::string &Name, + const FunctionType *Ty, + AttrListPtr AttributeList); + /// getFunction - Look up the specified function in the module symbol table. /// If it does not exist, return null. Function *getFunction(const std::string &Name) const; Added: llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h?rev=63765&view=auto ============================================================================== --- llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h (added) +++ llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h Wed Feb 4 13:47:21 2009 @@ -0,0 +1,48 @@ +//===-- llvm/Target/TargetIntrinsicInfo.h - Instruction Info ----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the target intrinsic instructions to the code generator. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_TARGET_TARGETINTRINSICINFO_H +#define LLVM_TARGET_TARGETINTRINSICINFO_H + +namespace llvm { + +class Function; +class Module; + +//--------------------------------------------------------------------------- +/// +/// TargetIntrinsicInfo - Interface to description of machine instruction set +/// +class TargetIntrinsicInfo { + + const char **Intrinsics; // Raw array to allow static init'n + unsigned NumIntrinsics; // Number of entries in the desc array + + TargetIntrinsicInfo(const TargetIntrinsicInfo &); // DO NOT IMPLEMENT + void operator=(const TargetIntrinsicInfo &); // DO NOT IMPLEMENT +public: + TargetIntrinsicInfo(const char **desc, unsigned num); + virtual ~TargetIntrinsicInfo(); + + unsigned getNumIntrinsics() const { return NumIntrinsics; } + + virtual Function *getDeclaration(Module *M, const char *BuiltinName) const { + return 0; + } + + virtual unsigned getIntrinsicID(Function *F) const { return 0; } +}; + +} // End llvm namespace + +#endif Modified: llvm/trunk/include/llvm/Target/TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=63765&r1=63764&r2=63765&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetMachine.h (original) +++ llvm/trunk/include/llvm/Target/TargetMachine.h Wed Feb 4 13:47:21 2009 @@ -23,6 +23,7 @@ class TargetData; class TargetSubtarget; class TargetInstrInfo; +class TargetIntrinsicInfo; class TargetJITInfo; class TargetLowering; class TargetFrameInfo; @@ -118,7 +119,6 @@ virtual TargetLowering *getTargetLowering() const { return 0; } virtual const TargetData *getTargetData() const { return 0; } - /// getTargetAsmInfo - Return target specific asm information. /// const TargetAsmInfo *getTargetAsmInfo() const { @@ -141,6 +141,11 @@ /// details of graph coloring register allocation removed from it. /// virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; } + + /// getIntrinsicInfo - If intrinsic information is available, return it. If + /// not, return null. + /// + virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; } /// getJITInfo - If this target supports a JIT, return information for it, /// otherwise return null. Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=63765&r1=63764&r2=63765&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Wed Feb 4 13:47:21 2009 @@ -2949,15 +2949,6 @@ Value *Callee; if (ConvertValIDToValue(PFTy, CalleeID, Callee, PFS)) return true; - // Check for call to invalid intrinsic to avoid crashing later. - if (Function *F = dyn_cast(Callee)) { - if (F->hasName() && F->getNameLen() >= 5 && - !strncmp(F->getValueName()->getKeyData(), "llvm.", 5) && - !F->getIntrinsicID(true)) - return Error(CallLoc, "Call to invalid LLVM intrinsic function '" + - F->getNameStr() + "'"); - } - // FIXME: In LLVM 3.0, stop accepting zext, sext and inreg as optional // function attributes. unsigned ObsoleteFuncAttrs = Attribute::ZExt|Attribute::SExt|Attribute::InReg; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63765&r1=63764&r2=63765&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Wed Feb 4 13:47:21 2009 @@ -43,6 +43,7 @@ #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetIntrinsicInfo.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" @@ -4426,6 +4427,14 @@ const char *RenameFn = 0; if (Function *F = I.getCalledFunction()) { if (F->isDeclaration()) { + const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo(); + if (II) { + if (unsigned IID = II->getIntrinsicID(F)) { + RenameFn = visitIntrinsicCall(I, IID); + if (!RenameFn) + return; + } + } if (unsigned IID = F->getIntrinsicID()) { RenameFn = visitIntrinsicCall(I, IID); if (!RenameFn) Added: llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp?rev=63765&view=auto ============================================================================== --- llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp (added) +++ llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp Wed Feb 4 13:47:21 2009 @@ -0,0 +1,22 @@ +//===-- TargetIntrinsicInfo.cpp - Target Instruction Information ----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the TargetIntrinsicInfo class. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Target/TargetIntrinsicInfo.h" +using namespace llvm; + +TargetIntrinsicInfo::TargetIntrinsicInfo(const char **desc, unsigned count) + : Intrinsics(desc), NumIntrinsics(count) { +} + +TargetIntrinsicInfo::~TargetIntrinsicInfo() { +} Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=63765&r1=63764&r2=63765&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original) +++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Wed Feb 4 13:47:21 2009 @@ -217,7 +217,7 @@ // Upgrade intrinsic attributes. This does not change the function. if (NewFn) F = NewFn; - if (unsigned id = F->getIntrinsicID(true)) + if (unsigned id = F->getIntrinsicID()) F->setAttributes(Intrinsic::getAttributes((Intrinsic::ID)id)); return Upgraded; } Modified: llvm/trunk/lib/VMCore/Function.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Function.cpp?rev=63765&r1=63764&r2=63765&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Function.cpp (original) +++ llvm/trunk/lib/VMCore/Function.cpp Wed Feb 4 13:47:21 2009 @@ -175,7 +175,7 @@ ParentModule->getFunctionList().push_back(this); // Ensure intrinsics have the right parameter attributes. - if (unsigned IID = getIntrinsicID(true)) + if (unsigned IID = getIntrinsicID()) setAttributes(Intrinsic::getAttributes(Intrinsic::ID(IID))); } @@ -304,7 +304,7 @@ /// particular intrinsic functions which correspond to this value are defined in /// llvm/Intrinsics.h. /// -unsigned Function::getIntrinsicID(bool noAssert) const { +unsigned Function::getIntrinsicID() const { const ValueName *ValName = this->getValueName(); if (!ValName) return 0; @@ -315,12 +315,9 @@ || Name[2] != 'v' || Name[3] != 'm') return 0; // All intrinsics start with 'llvm.' - assert((Len != 5 || noAssert) && "'llvm.' is an invalid intrinsic name!"); - #define GET_FUNCTION_RECOGNIZER #include "llvm/Intrinsics.gen" #undef GET_FUNCTION_RECOGNIZER - assert(noAssert && "Invalid LLVM intrinsic name"); return 0; } @@ -373,4 +370,9 @@ getType(id, Tys, numTys))); } +// This defines the "Intrinsic::getIntrinsicForGCCBuiltin()" method. +#define GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN +#include "llvm/Intrinsics.gen" +#undef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN + // vim: sw=2 ai Modified: llvm/trunk/lib/VMCore/Module.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Module.cpp?rev=63765&r1=63764&r2=63765&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Module.cpp (original) +++ llvm/trunk/lib/VMCore/Module.cpp Wed Feb 4 13:47:21 2009 @@ -171,6 +171,25 @@ return F; } +Constant *Module::getOrInsertTargetIntrinsic(const std::string &Name, + const FunctionType *Ty, + AttrListPtr AttributeList) { + ValueSymbolTable &SymTab = getValueSymbolTable(); + + // See if we have a definition for the specified function already. + GlobalValue *F = dyn_cast_or_null(SymTab.lookup(Name)); + if (F == 0) { + // Nope, add it + Function *New = Function::Create(Ty, GlobalVariable::ExternalLinkage, Name); + New->setAttributes(AttributeList); + FunctionList.push_back(New); + return New; // Return the new prototype. + } + + // Otherwise, we just found the existing function or a prototype. + return F; +} + Constant *Module::getOrInsertFunction(const std::string &Name, const FunctionType *Ty) { AttrListPtr AttributeList = AttrListPtr::get((AttributeWithIndex *)0, 0); Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=63765&r1=63764&r2=63765&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Wed Feb 4 13:47:21 2009 @@ -1004,10 +1004,9 @@ void Verifier::visitCallInst(CallInst &CI) { VerifyCallSite(&CI); - if (Function *F = CI.getCalledFunction()) { + if (Function *F = CI.getCalledFunction()) if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) visitIntrinsicFunctionCall(ID, CI); - } } void Verifier::visitInvokeInst(InvokeInst &II) { Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=63765&r1=63764&r2=63765&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Wed Feb 4 13:47:21 2009 @@ -1303,7 +1303,8 @@ // FIXME: REMOVE OSTREAM ARGUMENT CodeGenDAGPatterns::CodeGenDAGPatterns(RecordKeeper &R) : Records(R) { - Intrinsics = LoadIntrinsics(Records); + Intrinsics = LoadIntrinsics(Records, false); + TgtIntrinsics = LoadIntrinsics(Records, true); ParseNodeInfo(); ParseNodeTransforms(); ParseComplexPatterns(); Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h?rev=63765&r1=63764&r2=63765&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h Wed Feb 4 13:47:21 2009 @@ -465,6 +465,7 @@ RecordKeeper &Records; CodeGenTarget Target; std::vector Intrinsics; + std::vector TgtIntrinsics; std::map SDNodes; std::map > SDNodeXForms; @@ -515,18 +516,25 @@ const CodeGenIntrinsic &getIntrinsic(Record *R) const { for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i) if (Intrinsics[i].TheDef == R) return Intrinsics[i]; + for (unsigned i = 0, e = TgtIntrinsics.size(); i != e; ++i) + if (TgtIntrinsics[i].TheDef == R) return TgtIntrinsics[i]; assert(0 && "Unknown intrinsic!"); abort(); } const CodeGenIntrinsic &getIntrinsicInfo(unsigned IID) const { - assert(IID-1 < Intrinsics.size() && "Bad intrinsic ID!"); - return Intrinsics[IID-1]; + if (IID-1 < Intrinsics.size()) + return Intrinsics[IID-1]; + if (IID-Intrinsics.size()-1 < TgtIntrinsics.size()) + return TgtIntrinsics[IID-Intrinsics.size()-1]; + assert(0 && "Bad intrinsic ID!"); } unsigned getIntrinsicID(Record *R) const { for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i) if (Intrinsics[i].TheDef == R) return i; + for (unsigned i = 0, e = TgtIntrinsics.size(); i != e; ++i) + if (TgtIntrinsics[i].TheDef == R) return i + Intrinsics.size(); assert(0 && "Unknown intrinsic!"); abort(); } Modified: llvm/trunk/utils/TableGen/CodeGenIntrinsics.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenIntrinsics.h?rev=63765&r1=63764&r2=63765&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenIntrinsics.h (original) +++ llvm/trunk/utils/TableGen/CodeGenIntrinsics.h Wed Feb 4 13:47:21 2009 @@ -80,7 +80,8 @@ /// LoadIntrinsics - Read all of the intrinsics defined in the specified /// .td file. - std::vector LoadIntrinsics(const RecordKeeper &RC); + std::vector LoadIntrinsics(const RecordKeeper &RC, + bool TargetOnly); } #endif Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=63765&r1=63764&r2=63765&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Wed Feb 4 13:47:21 2009 @@ -426,13 +426,17 @@ // CodeGenIntrinsic Implementation //===----------------------------------------------------------------------===// -std::vector llvm::LoadIntrinsics(const RecordKeeper &RC) { +std::vector llvm::LoadIntrinsics(const RecordKeeper &RC, + bool TargetOnly) { std::vector I = RC.getAllDerivedDefinitions("Intrinsic"); std::vector Result; - for (unsigned i = 0, e = I.size(); i != e; ++i) - Result.push_back(CodeGenIntrinsic(I[i])); + for (unsigned i = 0, e = I.size(); i != e; ++i) { + bool isTarget = I[i]->getValueAsBit("isTarget"); + if (isTarget == TargetOnly) + Result.push_back(CodeGenIntrinsic(I[i])); + } return Result; } Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=63765&r1=63764&r2=63765&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Wed Feb 4 13:47:21 2009 @@ -25,7 +25,10 @@ void IntrinsicEmitter::run(std::ostream &OS) { EmitSourceFileHeader("Intrinsic Function Source Fragment", OS); - std::vector Ints = LoadIntrinsics(Records); + std::vector Ints = LoadIntrinsics(Records, TargetOnly); + + if (TargetOnly && !Ints.empty()) + TargetPrefix = Ints[0].TargetPrefix; // Emit the enum information. EmitEnumInfo(Ints, OS); @@ -91,12 +94,12 @@ if (Ints[I->second].isOverloaded) OS << " if (Len > " << I->first.size() << " && !memcmp(Name, \"" << I->first << ".\", " - << (I->first.size() + 1) << ")) return Intrinsic::" + << (I->first.size() + 1) << ")) return " << TargetPrefix << "Intrinsic::" << Ints[I->second].EnumName << ";\n"; else OS << " if (Len == " << I->first.size() << " && !memcmp(Name, \"" << I->first << "\", " - << I->first.size() << ")) return Intrinsic::" + << I->first.size() << ")) return " << TargetPrefix << "Intrinsic::" << Ints[I->second].EnumName << ";\n"; } OS << " }\n"; @@ -351,11 +354,13 @@ Ints[i].IS.ParamTypeDefs)].push_back(i); // Loop through the array, emitting one generator for each batch. + std::string IntrinsicStr = TargetPrefix + "Intrinsic::"; + for (MapTy::iterator I = UniqueArgInfos.begin(), E = UniqueArgInfos.end(); I != E; ++I) { for (unsigned i = 0, e = I->second.size(); i != e; ++i) - OS << " case Intrinsic::" << Ints[I->second[i]].EnumName << ":\t\t// " - << Ints[I->second[i]].Name << "\n"; + OS << " case " << IntrinsicStr << Ints[I->second[i]].EnumName + << ":\t\t// " << Ints[I->second[i]].Name << "\n"; const RecPair &ArgTypes = I->first; const std::vector &RetTys = ArgTypes.first; @@ -392,7 +397,11 @@ EmitAttributes(const std::vector &Ints, std::ostream &OS) { OS << "// Add parameter attributes that are not common to all intrinsics.\n"; OS << "#ifdef GET_INTRINSIC_ATTRIBUTES\n"; - OS << "AttrListPtr Intrinsic::getAttributes(ID id) {"; + if (TargetOnly) + OS << "static AttrListPtr getAttributes(" << TargetPrefix + << "Intrinsic::ID id) {"; + else + OS << "AttrListPtr Intrinsic::getAttributes(ID id) {"; OS << " // No intrinsic can throw exceptions.\n"; OS << " Attributes Attr = Attribute::NoUnwind;\n"; OS << " switch (id) {\n"; @@ -404,7 +413,8 @@ switch (Ints[i].ModRef) { default: break; case CodeGenIntrinsic::NoMem: - OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; + OS << " case " << TargetPrefix << "Intrinsic::" << Ints[i].EnumName + << ":\n"; break; } } @@ -415,7 +425,8 @@ default: break; case CodeGenIntrinsic::ReadArgMem: case CodeGenIntrinsic::ReadMem: - OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; + OS << " case " << TargetPrefix << "Intrinsic::" << Ints[i].EnumName + << ":\n"; break; } } @@ -431,7 +442,8 @@ for (unsigned i = 0, e = Ints.size(); i != e; ++i) { if (Ints[i].ArgumentAttributes.empty()) continue; - OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; + OS << " case " << TargetPrefix << "Intrinsic::" << Ints[i].EnumName + << ":\n"; std::vector > ArgAttrs = Ints[i].ArgumentAttributes; @@ -495,7 +507,7 @@ typedef std::map::const_iterator StrMapIterator; static void EmitBuiltinComparisons(StrMapIterator Start, StrMapIterator End, unsigned CharStart, unsigned Indent, - std::ostream &OS) { + std::string TargetPrefix, std::ostream &OS) { if (Start == End) return; // empty range. // Determine what, if anything, is the same about all these strings. @@ -522,7 +534,8 @@ OS << CommonString.size() - CharStart << "))\n"; ++Indent; } - OS << std::string(Indent*2, ' ') << "IntrinsicID = Intrinsic::"; + OS << std::string(Indent*2, ' ') << "IntrinsicID = " << TargetPrefix + << "Intrinsic::"; OS << Start->second << ";\n"; return; } @@ -535,7 +548,8 @@ OS << ", \"" << (CommonString.c_str()+CharStart) << "\", "; OS << CommonString.size()-CharStart << ")) {\n"; - EmitBuiltinComparisons(Start, End, CommonString.size(), Indent+1, OS); + EmitBuiltinComparisons(Start, End, CommonString.size(), Indent+1, + TargetPrefix, OS); OS << std::string(Indent*2, ' ') << "}\n"; return; } @@ -556,7 +570,7 @@ for (++NextChar; NextChar != End && NextChar->first[CharStart] == ThisChar; ++NextChar) /*empty*/; - EmitBuiltinComparisons(I, NextChar, CharStart+1, Indent+1, OS); + EmitBuiltinComparisons(I, NextChar, CharStart+1, Indent+1, TargetPrefix,OS); OS << std::string(Indent*2, ' ') << " break;\n"; I = NextChar; } @@ -566,6 +580,7 @@ /// EmitTargetBuiltins - All of the builtins in the specified map are for the /// same target, and we already checked it. static void EmitTargetBuiltins(const std::map &BIM, + const std::string &TargetPrefix, std::ostream &OS) { // Rearrange the builtins by length. std::vector > BuiltinsByLen; @@ -584,7 +599,7 @@ if (BuiltinsByLen[i].empty()) continue; OS << " case " << i << ":\n"; EmitBuiltinComparisons(BuiltinsByLen[i].begin(), BuiltinsByLen[i].end(), - 0, 3, OS); + 0, 3, TargetPrefix, OS); OS << " break;\n"; } OS << " }\n"; @@ -613,7 +628,22 @@ OS << "// in as BuiltinName, and a target prefix (e.g. 'ppc') is passed\n"; OS << "// in as TargetPrefix. The result is assigned to 'IntrinsicID'.\n"; OS << "#ifdef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN\n"; - OS << " IntrinsicID = Intrinsic::not_intrinsic;\n"; + + if (TargetOnly) { + OS << "static " << TargetPrefix << "Intrinsic::ID " + << "getIntrinsicForGCCBuiltin(const char " + << "*TargetPrefix, const char *BuiltinName) {\n"; + OS << " " << TargetPrefix << "Intrinsic::ID IntrinsicID = "; + } else { + OS << "Intrinsic::ID Intrinsic::getIntrinsicForGCCBuiltin(const char " + << "*TargetPrefix, const char *BuiltinName) {\n"; + OS << " Intrinsic::ID IntrinsicID = "; + } + + if (TargetOnly) + OS << "(" << TargetPrefix<< "Intrinsic::ID)"; + + OS << "Intrinsic::not_intrinsic;\n"; // Note: this could emit significantly better code if we cared. for (BIMTy::iterator I = BuiltinMap.begin(), E = BuiltinMap.end();I != E;++I){ @@ -625,8 +655,10 @@ OS << "{\n"; // Emit the comparisons for this target prefix. - EmitTargetBuiltins(I->second, OS); + EmitTargetBuiltins(I->second, TargetPrefix, OS); OS << " }\n"; } + OS << " return IntrinsicID;\n"; + OS << "}\n"; OS << "#endif\n\n"; } Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.h?rev=63765&r1=63764&r2=63765&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/IntrinsicEmitter.h (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.h Wed Feb 4 13:47:21 2009 @@ -20,9 +20,12 @@ namespace llvm { class IntrinsicEmitter : public TableGenBackend { RecordKeeper &Records; + bool TargetOnly; + std::string TargetPrefix; public: - IntrinsicEmitter(RecordKeeper &R) : Records(R) {} + IntrinsicEmitter(RecordKeeper &R, bool T = false) + : Records(R), TargetOnly(T) {} void run(std::ostream &OS); Modified: llvm/trunk/utils/TableGen/TableGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=63765&r1=63764&r2=63765&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TableGen.cpp (original) +++ llvm/trunk/utils/TableGen/TableGen.cpp Wed Feb 4 13:47:21 2009 @@ -49,6 +49,7 @@ GenFastISel, GenSubtarget, GenIntrinsic, + GenTgtIntrinsic, GenLLVMCConf, PrintEnums }; @@ -82,6 +83,8 @@ "Generate subtarget enumerations"), clEnumValN(GenIntrinsic, "gen-intrinsic", "Generate intrinsic information"), + clEnumValN(GenTgtIntrinsic, "gen-tgt-intrinsic", + "Generate target intrinsic information"), clEnumValN(GenLLVMCConf, "gen-llvmc", "Generate LLVMC configuration library"), clEnumValN(PrintEnums, "print-enums", @@ -190,6 +193,9 @@ case GenIntrinsic: IntrinsicEmitter(Records).run(*Out); break; + case GenTgtIntrinsic: + IntrinsicEmitter(Records, true).run(*Out); + break; case GenLLVMCConf: LLVMCConfigurationEmitter(Records).run(*Out); break; From baldrick at free.fr Wed Feb 4 13:57:20 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 4 Feb 2009 20:57:20 +0100 Subject: [llvm-commits] [llvm] r63760 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp In-Reply-To: <200902041938.n14JcFGo015187@zion.cs.uiuc.edu> References: <200902041938.n14JcFGo015187@zion.cs.uiuc.edu> Message-ID: <200902042057.21140.baldrick@free.fr> Testcase? Ciao, Duncan. From dalej at apple.com Wed Feb 4 14:06:27 2009 From: dalej at apple.com (Dale Johannesen) Date: Wed, 04 Feb 2009 20:06:27 -0000 Subject: [llvm-commits] [llvm] r63767 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ lib/Target/XCore/ Message-ID: <200902042006.n14K6S2x016138@zion.cs.uiuc.edu> Author: johannes Date: Wed Feb 4 14:06:27 2009 New Revision: 63767 URL: http://llvm.org/viewvc/llvm-project?rev=63767&view=rev Log: Remove non-DebugLoc versions of getLoad and getStore. Adjust the many callers of those versions. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63767&r1=63766&r2=63767&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Feb 4 14:06:27 2009 @@ -576,9 +576,6 @@ /// getLoad - Loads are not normal binary operators: their result type is not /// determined by their operands, and they produce a value AND a token chain. /// - SDValue getLoad(MVT VT, SDValue Chain, SDValue Ptr, - const Value *SV, int SVOffset, bool isVolatile=false, - unsigned Alignment=0); SDValue getLoad(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, const Value *SV, int SVOffset, bool isVolatile=false, unsigned Alignment=0); @@ -588,11 +585,6 @@ unsigned Alignment=0); SDValue getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM); - SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, - MVT VT, SDValue Chain, - SDValue Ptr, SDValue Offset, - const Value *SV, int SVOffset, MVT EVT, - bool isVolatile=false, unsigned Alignment=0); SDValue getLoad(ISD::MemIndexedMode AM, DebugLoc dl, ISD::LoadExtType ExtType, MVT VT, SDValue Chain, SDValue Ptr, SDValue Offset, @@ -601,9 +593,6 @@ /// getStore - Helper function to build ISD::STORE nodes. /// - SDValue getStore(SDValue Chain, SDValue Val, SDValue Ptr, - const Value *SV, int SVOffset, bool isVolatile=false, - unsigned Alignment=0); SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr, const Value *SV, int SVOffset, bool isVolatile=false, unsigned Alignment=0); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63767&r1=63766&r2=63767&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Feb 4 14:06:27 2009 @@ -556,6 +556,7 @@ static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, SelectionDAG &DAG, const TargetLowering &TLI) { bool Extend = false; + DebugLoc dl = CFP->getDebugLoc(); // If a FP immediate is precise when represented as a float and if the // target can do an extending load from float to double, we put it into @@ -591,11 +592,11 @@ SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); unsigned Alignment = 1 << cast(CPIdx)->getAlignment(); if (Extend) - return DAG.getExtLoad(ISD::EXTLOAD, CFP->getDebugLoc(), + return DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, VT, false, Alignment); - return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, + return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, false, Alignment); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63767&r1=63766&r2=63767&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Feb 4 14:06:27 2009 @@ -3554,55 +3554,6 @@ } SDValue -SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, - MVT VT, SDValue Chain, - SDValue Ptr, SDValue Offset, - const Value *SV, int SVOffset, MVT EVT, - bool isVolatile, unsigned Alignment) { - if (Alignment == 0) // Ensure that codegen never sees alignment 0 - Alignment = getMVTAlignment(VT); - - if (VT == EVT) { - ExtType = ISD::NON_EXTLOAD; - } else if (ExtType == ISD::NON_EXTLOAD) { - assert(VT == EVT && "Non-extending load from different memory type!"); - } else { - // Extending load. - if (VT.isVector()) - assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && - "Invalid vector extload!"); - else - assert(EVT.bitsLT(VT) && - "Should only be an extending load, not truncating!"); - assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && - "Cannot sign/zero extend a FP/Vector load!"); - assert(VT.isInteger() == EVT.isInteger() && - "Cannot convert from FP to Int or Int -> FP!"); - } - - bool Indexed = AM != ISD::UNINDEXED; - assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && - "Unindexed load with an offset!"); - - SDVTList VTs = Indexed ? - getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); - SDValue Ops[] = { Chain, Ptr, Offset }; - FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); - ID.AddInteger(EVT.getRawBits()); - ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment)); - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - SDNode *N = NodeAllocator.Allocate(); - new (N) LoadSDNode(Ops, VTs, AM, ExtType, EVT, SV, SVOffset, - Alignment, isVolatile); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - -SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, ISD::LoadExtType ExtType, MVT VT, SDValue Chain, SDValue Ptr, SDValue Offset, @@ -3651,15 +3602,6 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getLoad(MVT VT, - SDValue Chain, SDValue Ptr, - const Value *SV, int SVOffset, - bool isVolatile, unsigned Alignment) { - SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); - return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, - SV, SVOffset, VT, isVolatile, Alignment); -} - SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, const Value *SV, int SVOffset, @@ -3691,33 +3633,6 @@ LD->isVolatile(), LD->getAlignment()); } -SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val, - SDValue Ptr, const Value *SV, int SVOffset, - bool isVolatile, unsigned Alignment) { - MVT VT = Val.getValueType(); - - if (Alignment == 0) // Ensure that codegen never sees alignment 0 - Alignment = getMVTAlignment(VT); - - SDVTList VTs = getVTList(MVT::Other); - SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); - SDValue Ops[] = { Chain, Val, Ptr, Undef }; - FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); - ID.AddInteger(VT.getRawBits()); - ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, - isVolatile, Alignment)); - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - SDNode *N = NodeAllocator.Allocate(); - new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, false, - VT, SV, SVOffset, Alignment, isVolatile); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr, const Value *SV, int SVOffset, bool isVolatile, unsigned Alignment) { Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=63767&r1=63766&r2=63767&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Feb 4 14:06:27 2009 @@ -403,7 +403,8 @@ TheCall->getCallingConv() == CallingConv::Fast) && "unknown calling convention"); SDValue Callee = TheCall->getCallee(); - unsigned NumOps = TheCall->getNumArgs(); + unsigned NumOps = TheCall->getNumArgs(); + DebugLoc dl = TheCall->getDebugLoc(); unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot unsigned NumGPRs = 0; // GPRs used for parameter passing. @@ -458,25 +459,25 @@ break; case MVT::f32: RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], - DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg))); + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg))); break; case MVT::i64: { - SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg, DAG.getConstant(0, getPointerTy())); - SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg, DAG.getConstant(1, getPointerTy())); RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo)); if (ObjGPRs == 2) RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi)); else { SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); - PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); - MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0)); + PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); + MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, NULL, 0)); } break; } case MVT::f64: { - SDValue Cvt = DAG.getNode(ARMISD::FMRRD, + SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt)); @@ -485,8 +486,8 @@ Cvt.getValue(1))); else { SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); - PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); - MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff, + PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); + MemOpChains.push_back(DAG.getStore(Chain, dl, Cvt.getValue(1), PtrOff, NULL, 0)); } break; @@ -495,8 +496,8 @@ } else { assert(ObjSize != 0); SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); - PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); } NumGPRs += ObjGPRs; @@ -504,15 +505,15 @@ } if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token chain // and flag operands which copy the outgoing args into the appropriate regs. SDValue InFlag; for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, - InFlag); + Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, + RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } @@ -538,9 +539,11 @@ ARMCP::CPStub, 4); SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); + Callee = DAG.getLoad(getPointerTy(), dl, + DAG.getEntryNode(), CPAddr, NULL, 0); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); - Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); + Callee = DAG.getNode(ARMISD::PIC_ADD, dl, + getPointerTy(), Callee, PICLabel); } else Callee = DAG.getTargetGlobalAddress(GV, getPointerTy()); } else if (ExternalSymbolSDNode *S = dyn_cast(Callee)) { @@ -555,9 +558,11 @@ ARMCP::CPStub, 4); SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); + Callee = DAG.getLoad(getPointerTy(), dl, + DAG.getEntryNode(), CPAddr, NULL, 0); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); - Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); + Callee = DAG.getNode(ARMISD::PIC_ADD, dl, + getPointerTy(), Callee, PICLabel); } else Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); } @@ -576,7 +581,7 @@ } if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) { // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK - Chain = DAG.getCopyToReg(Chain, ARM::LR, + Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getNode(ISD::UNDEF, MVT::i32), InFlag); InFlag = Chain.getValue(1); } @@ -594,7 +599,7 @@ if (InFlag.getNode()) Ops.push_back(InFlag); // Returns a chain and a flag for retval copy to use. - Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag), + Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag), &Ops[0], Ops.size()); InFlag = Chain.getValue(1); @@ -611,25 +616,27 @@ case MVT::Other: break; case MVT::i32: - Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, ARM::R0, + MVT::i32, InFlag).getValue(1); ResultVals.push_back(Chain.getValue(0)); if (TheCall->getNumRetVals() > 1 && TheCall->getRetValType(1) == MVT::i32) { // Returns a i64 value. - Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, + Chain = DAG.getCopyFromReg(Chain, dl, ARM::R1, MVT::i32, Chain.getValue(2)).getValue(1); ResultVals.push_back(Chain.getValue(0)); } break; case MVT::f32: - Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); - ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32, + Chain = DAG.getCopyFromReg(Chain, dl, ARM::R0, + MVT::i32, InFlag).getValue(1); + ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Chain.getValue(0))); break; case MVT::f64: { - SDValue Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag); - SDValue Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2)); - ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi)); + SDValue Lo = DAG.getCopyFromReg(Chain, dl, ARM::R0, MVT::i32, InFlag); + SDValue Hi = DAG.getCopyFromReg(Lo, dl, ARM::R1, MVT::i32, Lo.getValue(2)); + ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi)); break; } } @@ -638,7 +645,7 @@ return Chain; ResultVals.push_back(Chain); - SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size()); + SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl); return Res.getValue(Op.getResNo()); } @@ -721,6 +728,7 @@ SDValue ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) { + DebugLoc dl = GA->getDebugLoc(); MVT PtrVT = getPointerTy(); unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; ARMConstantPoolValue *CPV = @@ -728,11 +736,11 @@ PCAdj, "tlsgd", true); SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2); Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument); - Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0); + Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0); SDValue Chain = Argument.getValue(1); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); - Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel); + Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); // call __tls_get_addr. ArgListTy Args; @@ -744,8 +752,7 @@ std::pair CallResult = LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false, CallingConv::C, false, - DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, - DebugLoc::getUnknownLoc()); + DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); return CallResult.first; } @@ -755,11 +762,12 @@ ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, SelectionDAG &DAG) { GlobalValue *GV = GA->getGlobal(); + DebugLoc dl = GA->getDebugLoc(); SDValue Offset; SDValue Chain = DAG.getEntryNode(); MVT PtrVT = getPointerTy(); // Get the Thread Pointer - SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); + SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); if (GV->isDeclaration()){ // initial exec model @@ -769,25 +777,25 @@ PCAdj, "gottpoff", true); Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); - Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); + Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0); Chain = Offset.getValue(1); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); - Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel); + Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); - Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); + Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0); } else { // local exec model ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff"); Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); - Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); + Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0); } // The address of the thread local variable is the add of the thread // pointer with the offset of the variable. - return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); + return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); } SDValue @@ -807,6 +815,7 @@ SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) { MVT PtrVT = getPointerTy(); + DebugLoc dl = Op.getDebugLoc(); GlobalValue *GV = cast(Op)->getGlobal(); Reloc::Model RelocM = getTargetMachine().getRelocationModel(); if (RelocM == Reloc::PIC_) { @@ -815,17 +824,18 @@ new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT"); SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); + SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), + CPAddr, NULL, 0); SDValue Chain = Result.getValue(1); SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT); - Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT); + Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); if (!UseGOTOFF) - Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); + Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0); return Result; } else { SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); + return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); } } @@ -843,6 +853,7 @@ SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) { MVT PtrVT = getPointerTy(); + DebugLoc dl = Op.getDebugLoc(); GlobalValue *GV = cast(Op)->getGlobal(); Reloc::Model RelocM = getTargetMachine().getRelocationModel(); bool IsIndirect = GVIsIndirectSymbol(GV, RelocM); @@ -860,15 +871,15 @@ } CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); + SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); SDValue Chain = Result.getValue(1); if (RelocM == Reloc::PIC_) { SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); - Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); + Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); } if (IsIndirect) - Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); + Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0); return Result; } @@ -878,15 +889,16 @@ assert(Subtarget->isTargetELF() && "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); MVT PtrVT = getPointerTy(); + DebugLoc dl = Op.getDebugLoc(); unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_", ARMPCLabelIndex, ARMCP::CPValue, PCAdj); SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); + SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); - return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); + return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); } static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { @@ -903,15 +915,16 @@ unsigned VarArgsFrameIndex) { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. + DebugLoc dl = Op.getDebugLoc(); MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); const Value *SV = cast(Op.getOperand(2))->getValue(); - return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); + return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); } static SDValue LowerFORMAL_ARGUMENT(SDValue Op, SelectionDAG &DAG, unsigned ArgNo, unsigned &NumGPRs, - unsigned &ArgOffset) { + unsigned &ArgOffset, DebugLoc dl) { MachineFunction &MF = DAG.getMachineFunction(); MVT ObjectVT = Op.getValue(ArgNo).getValueType(); SDValue Root = Op.getOperand(0); @@ -936,20 +949,20 @@ if (ObjGPRs == 1) { unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); - ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); + ArgValue = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); if (ObjectVT == MVT::f32) - ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue); + ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue); } else if (ObjGPRs == 2) { unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); - ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); + ArgValue = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg); - SDValue ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32); + SDValue ArgValue2 = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); assert(ObjectVT != MVT::i64 && "i64 should already be lowered"); - ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); + ArgValue = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2); } NumGPRs += ObjGPRs; @@ -958,11 +971,11 @@ int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); if (ObjGPRs == 0) - ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); + ArgValue = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0); else { - SDValue ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0); + SDValue ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0); assert(ObjectVT != MVT::i64 && "i64 should already be lowered"); - ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); + ArgValue = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2); } ArgOffset += ObjSize; // Move on to the next argument. @@ -975,13 +988,14 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { std::vector ArgValues; SDValue Root = Op.getOperand(0); + DebugLoc dl = Op.getDebugLoc(); unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot unsigned NumGPRs = 0; // GPRs used for parameter passing. unsigned NumArgs = Op.getNode()->getNumValues()-1; for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo, - NumGPRs, ArgOffset)); + NumGPRs, ArgOffset, dl)); bool isVarArg = cast(Op.getOperand(2))->getZExtValue() != 0; if (isVarArg) { @@ -1009,14 +1023,14 @@ for (; NumGPRs < 4; ++NumGPRs) { unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); - SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); - SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); + SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); + SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); MemOps.push_back(Store); - FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, + FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, DAG.getConstant(4, getPointerTy())); } if (!MemOps.empty()) - Root = DAG.getNode(ISD::TokenFactor, MVT::Other, + Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0], MemOps.size()); } else // This will point to the next argument passed via stack. @@ -1026,7 +1040,7 @@ ArgValues.push_back(Root); // Return the new list of results. - return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), &ArgValues[0], ArgValues.size()); } @@ -1194,6 +1208,7 @@ SDValue Chain = Op.getOperand(0); SDValue Table = Op.getOperand(1); SDValue Index = Op.getOperand(2); + DebugLoc dl = Op.getDebugLoc(); MVT PTy = getPointerTy(); JumpTableSDNode *JT = cast(Table); @@ -1201,15 +1216,15 @@ SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId); - Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy)); - SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); + Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); + SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; - Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, + Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, dl, Chain, Addr, NULL, 0); Chain = Addr.getValue(1); if (isPIC) - Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table); - return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId); + Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); + return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); } static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=63767&r1=63766&r2=63767&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Wed Feb 4 14:06:27 2009 @@ -219,6 +219,7 @@ MachineFrameInfo *MFI = MF.getFrameInfo(); std::vector ArgValues; SDValue Root = Op.getOperand(0); + DebugLoc dl = Op.getDebugLoc(); AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA @@ -240,17 +241,17 @@ case MVT::f64: args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo], &Alpha::F8RCRegClass); - ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT); + ArgVal = DAG.getCopyFromReg(Root, dl, args_float[ArgNo], ObjectVT); break; case MVT::f32: args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo], &Alpha::F4RCRegClass); - ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT); + ArgVal = DAG.getCopyFromReg(Root, dl, args_float[ArgNo], ObjectVT); break; case MVT::i64: args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo], &Alpha::GPRCRegClass); - ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64); + ArgVal = DAG.getCopyFromReg(Root, dl, args_int[ArgNo], MVT::i64); break; } } else { //more args @@ -260,7 +261,7 @@ // Create the SelectionDAG nodes corresponding to a load //from this parameter SDValue FIN = DAG.getFrameIndex(FI, MVT::i64); - ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); + ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0); } ArgValues.push_back(ArgVal); } @@ -273,28 +274,28 @@ for (int i = 0; i < 6; ++i) { if (TargetRegisterInfo::isPhysicalRegister(args_int[i])) args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass); - SDValue argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64); + SDValue argt = DAG.getCopyFromReg(Root, dl, args_int[i], MVT::i64); int FI = MFI->CreateFixedObject(8, -8 * (6 - i)); if (i == 0) VarArgsBase = FI; SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64); - LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0)); + LS.push_back(DAG.getStore(Root, dl, argt, SDFI, NULL, 0)); if (TargetRegisterInfo::isPhysicalRegister(args_float[i])) args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass); - argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64); + argt = DAG.getCopyFromReg(Root, dl, args_float[i], MVT::f64); FI = MFI->CreateFixedObject(8, - 8 * (12 - i)); SDFI = DAG.getFrameIndex(FI, MVT::i64); - LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0)); + LS.push_back(DAG.getStore(Root, dl, argt, SDFI, NULL, 0)); } //Set up a token factor with all the stack traffic - Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size()); + Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LS[0], LS.size()); } ArgValues.push_back(Root); // Return the new list of results. - return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), &ArgValues[0], ArgValues.size()); } @@ -622,13 +623,14 @@ void AlphaTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl&Results, SelectionDAG &DAG) { + DebugLoc dl = N->getDebugLoc(); assert(N->getValueType(0) == MVT::i32 && N->getOpcode() == ISD::VAARG && "Unknown node to custom promote!"); SDValue Chain, DataPtr; LowerVAARG(N, Chain, DataPtr, DAG); - SDValue Res = DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL, 0); + SDValue Res = DAG.getLoad(N->getValueType(0), dl, Chain, DataPtr, NULL, 0); Results.push_back(Res); Results.push_back(SDValue(Res.getNode(), 1)); } Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=63767&r1=63766&r2=63767&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Wed Feb 4 14:06:27 2009 @@ -249,6 +249,7 @@ SDNode *emitBuildVector(SDValue build_vec) { MVT vecVT = build_vec.getValueType(); SDNode *bvNode = build_vec.getNode(); + DebugLoc dl = bvNode->getDebugLoc(); // Check to see if this vector can be represented as a CellSPU immediate // constant by invoking all of the instruction selection predicates: @@ -279,7 +280,7 @@ SDValue CGPoolOffset = SPU::LowerConstantPool(CPIdx, *CurDAG, SPUtli.getSPUTargetMachine()); - return SelectCode(CurDAG->getLoad(build_vec.getValueType(), + return SelectCode(CurDAG->getLoad(build_vec.getValueType(), dl, CurDAG->getEntryNode(), CGPoolOffset, PseudoSourceValue::getConstantPool(), 0, false, Alignment)); Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=63767&r1=63766&r2=63767&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Wed Feb 4 14:06:27 2009 @@ -507,6 +507,7 @@ ISD::LoadExtType ExtType = LN->getExtensionType(); unsigned alignment = LN->getAlignment(); const valtype_map_s *vtm = getValueTypeMapEntry(InVT); + DebugLoc dl = Op.getDebugLoc(); switch (LN->getAddressingMode()) { case ISD::UNINDEXED: { @@ -553,7 +554,7 @@ int64_t rotamt = -vtm->prefslot_byte; if (rotamt < 0) rotamt += 16; - rotate = DAG.getNode(ISD::ADD, PtrVT, + rotate = DAG.getNode(ISD::ADD, dl, PtrVT, basePtr, DAG.getConstant(rotamt, PtrVT)); } @@ -573,8 +574,8 @@ // in a register. Note that this is done because we need to avoid // creating a 0(reg) d-form address due to the SPU's block loads. basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, Op0, Op1); - the_chain = DAG.getCopyToReg(the_chain, VReg, basePtr, Flag); - basePtr = DAG.getCopyFromReg(the_chain, VReg, PtrVT); + the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag); + basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT); } else { // Convert the (add , ) to an indirect address, which // will likely be lowered as a reg(reg) x-form address. @@ -588,13 +589,13 @@ // Offset the rotate amount by the basePtr and the preferred slot // byte offset - rotate = DAG.getNode(ISD::ADD, PtrVT, + rotate = DAG.getNode(ISD::ADD, dl, PtrVT, basePtr, DAG.getConstant(-vtm->prefslot_byte, PtrVT)); } // Re-emit as a v16i8 vector load - result = DAG.getLoad(MVT::v16i8, the_chain, basePtr, + result = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr, LN->getSrcValue(), LN->getSrcValueOffset(), LN->isVolatile(), 16); @@ -602,27 +603,27 @@ the_chain = result.getValue(1); // Rotate into the preferred slot: - result = DAG.getNode(SPUISD::ROTBYTES_LEFT, MVT::v16i8, + result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, MVT::v16i8, result.getValue(0), rotate); // Convert the loaded v16i8 vector to the appropriate vector type // specified by the operand: MVT vecVT = MVT::getVectorVT(InVT, (128 / InVT.getSizeInBits())); - result = DAG.getNode(SPUISD::VEC2PREFSLOT, InVT, - DAG.getNode(ISD::BIT_CONVERT, vecVT, result)); + result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT, + DAG.getNode(ISD::BIT_CONVERT, dl, vecVT, result)); // Handle extending loads by extending the scalar result: if (ExtType == ISD::SEXTLOAD) { - result = DAG.getNode(ISD::SIGN_EXTEND, OutVT, result); + result = DAG.getNode(ISD::SIGN_EXTEND, dl, OutVT, result); } else if (ExtType == ISD::ZEXTLOAD) { - result = DAG.getNode(ISD::ZERO_EXTEND, OutVT, result); + result = DAG.getNode(ISD::ZERO_EXTEND, dl, OutVT, result); } else if (ExtType == ISD::EXTLOAD) { unsigned NewOpc = ISD::ANY_EXTEND; if (OutVT.isFloatingPoint()) NewOpc = ISD::FP_EXTEND; - result = DAG.getNode(NewOpc, OutVT, result); + result = DAG.getNode(NewOpc, dl, OutVT, result); } SDVTList retvts = DAG.getVTList(OutVT, MVT::Other); @@ -631,7 +632,7 @@ the_chain }; - result = DAG.getNode(SPUISD::LDRESULT, retvts, + result = DAG.getNode(SPUISD::LDRESULT, dl, retvts, retops, sizeof(retops) / sizeof(retops[0])); return result; } @@ -663,6 +664,7 @@ MVT VT = Value.getValueType(); MVT StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT()); MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + DebugLoc dl = Op.getDebugLoc(); unsigned alignment = SN->getAlignment(); switch (SN->getAddressingMode()) { @@ -719,8 +721,8 @@ // in a register. Note that this is done because we need to avoid // creating a 0(reg) d-form address due to the SPU's block loads. basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, Op0, Op1); - the_chain = DAG.getCopyToReg(the_chain, VReg, basePtr, Flag); - basePtr = DAG.getCopyFromReg(the_chain, VReg, PtrVT); + the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag); + basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT); } else { // Convert the (add , ) to an indirect address, which // will likely be lowered as a reg(reg) x-form address. @@ -733,13 +735,13 @@ } // Insertion point is solely determined by basePtr's contents - insertEltOffs = DAG.getNode(ISD::ADD, PtrVT, + insertEltOffs = DAG.getNode(ISD::ADD, dl, PtrVT, basePtr, DAG.getConstant(0, PtrVT)); } // Re-emit as a v16i8 vector load - alignLoadVec = DAG.getLoad(MVT::v16i8, the_chain, basePtr, + alignLoadVec = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr, SN->getSrcValue(), SN->getSrcValueOffset(), SN->isVolatile(), 16); @@ -771,15 +773,16 @@ #endif SDValue insertEltOp = - DAG.getNode(SPUISD::SHUFFLE_MASK, vecVT, insertEltOffs); + DAG.getNode(SPUISD::SHUFFLE_MASK, dl, vecVT, insertEltOffs); SDValue vectorizeOp = - DAG.getNode(ISD::SCALAR_TO_VECTOR, vecVT, theValue); + DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, vecVT, theValue); - result = DAG.getNode(SPUISD::SHUFB, vecVT, + result = DAG.getNode(SPUISD::SHUFB, dl, vecVT, vectorizeOp, alignLoadVec, - DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, insertEltOp)); + DAG.getNode(ISD::BIT_CONVERT, dl, + MVT::v4i32, insertEltOp)); - result = DAG.getStore(the_chain, result, basePtr, + result = DAG.getStore(the_chain, dl, result, basePtr, LN->getSrcValue(), LN->getSrcValueOffset(), LN->isVolatile(), LN->getAlignment()); @@ -926,6 +929,7 @@ SmallVector ArgValues; SDValue Root = Op.getOperand(0); bool isVarArg = cast(Op.getOperand(2))->getZExtValue() != 0; + DebugLoc dl = Op.getDebugLoc(); const unsigned *ArgRegs = SPURegisterInfo::getArgRegs(); const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs(); @@ -986,7 +990,7 @@ unsigned VReg = RegInfo.createVirtualRegister(ArgRegClass); RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); - ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); + ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT); ++ArgRegIdx; } else { // We need to load the argument to a virtual register if we determined @@ -994,7 +998,7 @@ // or we're forced to do vararg int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); SDValue FIN = DAG.getFrameIndex(FI, PtrVT); - ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); + ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0); ArgOffset += StackSlotSize; } @@ -1015,7 +1019,7 @@ VarArgsFrameIndex = MFI->CreateFixedObject(StackSlotSize, ArgOffset); SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); SDValue ArgVal = DAG.getRegister(ArgRegs[ArgRegIdx], MVT::v16i8); - SDValue Store = DAG.getStore(Root, ArgVal, FIN, NULL, 0); + SDValue Store = DAG.getStore(Root, dl, ArgVal, FIN, NULL, 0); Root = Store.getOperand(0); MemOps.push_back(Store); @@ -1023,13 +1027,14 @@ ArgOffset += StackSlotSize; } if (!MemOps.empty()) - Root = DAG.getNode(ISD::TokenFactor,MVT::Other,&MemOps[0],MemOps.size()); + Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + &MemOps[0], MemOps.size()); } ArgValues.push_back(Root); // Return the new list of results. - return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), &ArgValues[0], ArgValues.size()); } @@ -1056,6 +1061,7 @@ unsigned StackSlotSize = SPUFrameInfo::stackSlotSize(); const unsigned *ArgRegs = SPURegisterInfo::getArgRegs(); const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs(); + DebugLoc dl = TheCall->getDebugLoc(); // Handy pointer type MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); @@ -1086,7 +1092,7 @@ // PtrOff will be used to store the current argument to the stack if a // register cannot be found for it. SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); - PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); + PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); switch (Arg.getValueType().getSimpleVT()) { default: assert(0 && "Unexpected ValueType for argument!"); @@ -1098,7 +1104,7 @@ if (ArgRegIdx != NumArgRegs) { RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg)); } else { - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); ArgOffset += StackSlotSize; } break; @@ -1107,7 +1113,7 @@ if (ArgRegIdx != NumArgRegs) { RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg)); } else { - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); ArgOffset += StackSlotSize; } break; @@ -1120,7 +1126,7 @@ if (ArgRegIdx != NumArgRegs) { RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg)); } else { - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); ArgOffset += StackSlotSize; } break; @@ -1134,7 +1140,7 @@ if (!MemOpChains.empty()) { // Adjust the stack pointer for the stack arguments. - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); } @@ -1142,8 +1148,8 @@ // and flag operands which copy the outgoing args into the appropriate regs. SDValue InFlag; for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, - InFlag); + Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, + RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } @@ -1207,7 +1213,7 @@ if (InFlag.getNode()) Ops.push_back(InFlag); // Returns a chain and a flag for retval copy to use. - Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag), + Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag), &Ops[0], Ops.size()); InFlag = Chain.getValue(1); @@ -1225,31 +1231,35 @@ case MVT::Other: break; case MVT::i32: if (TheCall->getValueType(1) == MVT::i32) { - Chain = DAG.getCopyFromReg(Chain, SPU::R4, MVT::i32, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R4, + MVT::i32, InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); - Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i32, + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32, Chain.getValue(2)).getValue(1); ResultVals[1] = Chain.getValue(0); NumResults = 2; } else { - Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i32, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32, + InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; } break; case MVT::i64: - Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i64, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i64, + InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; break; case MVT::i128: - Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i128, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i128, + InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; break; case MVT::f32: case MVT::f64: - Chain = DAG.getCopyFromReg(Chain, SPU::R3, TheCall->getValueType(0), + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, TheCall->getValueType(0), InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; @@ -1260,7 +1270,7 @@ case MVT::v4i32: case MVT::v8i16: case MVT::v16i8: - Chain = DAG.getCopyFromReg(Chain, SPU::R3, TheCall->getValueType(0), + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, TheCall->getValueType(0), InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; @@ -1273,7 +1283,7 @@ // Otherwise, merge everything together with a MERGE_VALUES node. ResultVals[NumResults++] = Chain; - SDValue Res = DAG.getMergeValues(ResultVals, NumResults); + SDValue Res = DAG.getMergeValues(ResultVals, NumResults, dl); return Res.getValue(Op.getResNo()); } Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp?rev=63767&r1=63766&r2=63767&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp Wed Feb 4 14:06:27 2009 @@ -554,6 +554,7 @@ SDValue IA64TargetLowering:: LowerOperation(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); switch (Op.getOpcode()) { default: assert(0 && "Should not custom lower this!"); case ISD::GlobalTLSAddress: @@ -566,21 +567,21 @@ assert(0 && "Do not know how to return this many arguments!"); abort(); case 1: - AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64); - AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), IA64::AR_PFS, + AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64); + AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, IA64::AR_PFS, AR_PFSVal); - return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal); + return DAG.getNode(IA64ISD::RET_FLAG, dl, MVT::Other, AR_PFSVal); case 3: { // Copy the result into the output register & restore ar.pfs MVT ArgVT = Op.getOperand(1).getValueType(); unsigned ArgReg = ArgVT.isInteger() ? IA64::r8 : IA64::F8; - AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64); - Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), ArgReg, Op.getOperand(1), - SDValue()); - AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), IA64::AR_PFS, AR_PFSVal, - Copy.getValue(1)); - return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, + AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64); + Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, ArgReg, + Op.getOperand(1), SDValue()); + AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), dl, + IA64::AR_PFS, AR_PFSVal, Copy.getValue(1)); + return DAG.getNode(IA64ISD::RET_FLAG, dl, MVT::Other, AR_PFSVal, AR_PFSVal.getValue(1)); } } @@ -589,24 +590,24 @@ case ISD::VAARG: { MVT VT = getPointerTy(); const Value *SV = cast(Op.getOperand(2))->getValue(); - SDValue VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1), + SDValue VAList = DAG.getLoad(VT, dl, Op.getOperand(0), Op.getOperand(1), SV, 0); // Increment the pointer, VAList, to the next vaarg - SDValue VAIncr = DAG.getNode(ISD::ADD, VT, VAList, + SDValue VAIncr = DAG.getNode(ISD::ADD, dl, VT, VAList, DAG.getConstant(VT.getSizeInBits()/8, VT)); // Store the incremented VAList to the legalized pointer - VAIncr = DAG.getStore(VAList.getValue(1), VAIncr, + VAIncr = DAG.getStore(VAList.getValue(1), dl, VAIncr, Op.getOperand(1), SV, 0); // Load the actual argument out of the pointer VAList - return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0); + return DAG.getLoad(Op.getValueType(), dl, VAIncr, VAList, NULL, 0); } case ISD::VASTART: { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64); const Value *SV = cast(Op.getOperand(2))->getValue(); - return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); + return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); } // Frame & Return address. Currently unimplemented case ISD::RETURNADDR: break; Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=63767&r1=63766&r2=63767&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Feb 4 14:06:27 2009 @@ -468,6 +468,7 @@ SDValue MipsTargetLowering:: LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); GlobalValue *GV = cast(Op)->getGlobal(); SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); @@ -478,21 +479,22 @@ if (!isa(GV) && IsGlobalInSmallSection(GV)) { SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1); SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32); - return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); + return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); } // %hi/%lo relocation - SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1); - SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA); - return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo); + SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, 1, Ops, 1); + SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA); + return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); } else { // Abicall relocations, TODO: make this cleaner. - SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0); + SDValue ResNode = DAG.getLoad(MVT::i32, dl, + DAG.getEntryNode(), GA, NULL, 0); // On functions and global targets not internal linked only // a load from got/GP is necessary for PIC to work. if (!GV->hasLocalLinkage() || isa(GV)) return ResNode; - SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA); - return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo); + SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA); + return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo); } assert(0 && "Dont know how to handle GlobalAddress"); @@ -511,6 +513,7 @@ { SDValue ResNode; SDValue HiPart; + DebugLoc dl = Op.getDebugLoc(); MVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast(Op); @@ -519,12 +522,12 @@ if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { const MVT *VTs = DAG.getNodeValueTypes(MVT::i32); SDValue Ops[] = { JTI }; - HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1); + HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, 1, Ops, 1); } else // Emit Load from Global Pointer - HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0); + HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0); - SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI); - ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo); + SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI); + ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); return ResNode; } @@ -586,6 +589,7 @@ SDValue Callee = TheCall->getCallee(); bool isVarArg = TheCall->isVarArg(); unsigned CC = TheCall->getCallingConv(); + DebugLoc dl = TheCall->getDebugLoc(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -627,13 +631,13 @@ default: assert(0 && "Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: - Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); + Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); break; case CCValAssign::ZExt: - Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); + Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); break; case CCValAssign::AExt: - Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); + Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); break; } @@ -659,13 +663,13 @@ // emit ISD::STORE whichs stores the // parameter value to a stack Location - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); } // Transform all store nodes into one single node because all store // nodes are independent of each other. if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token @@ -674,7 +678,7 @@ // stuck together. SDValue InFlag; for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, + Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } @@ -706,7 +710,7 @@ if (InFlag.getNode()) Ops.push_back(InFlag); - Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size()); + Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); InFlag = Chain.getValue(1); // Create the CALLSEQ_END node. @@ -736,9 +740,9 @@ // Reload GP value. FI = MipsFI->getGPFI(); SDValue FIN = DAG.getFrameIndex(FI,getPointerTy()); - SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0); + SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0); Chain = GPLoad.getValue(1); - Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32), + Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32), GPLoad, SDValue(0,0)); InFlag = Chain.getValue(1); } @@ -758,6 +762,7 @@ unsigned CallingConv, SelectionDAG &DAG) { bool isVarArg = TheCall->isVarArg(); + DebugLoc dl = TheCall->getDebugLoc(); // Assign locations to each value returned by this call. SmallVector RVLocs; @@ -768,7 +773,7 @@ // Copy all of the result registers out of their specified physreg. for (unsigned i = 0; i != RVLocs.size(); ++i) { - Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(), + Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), RVLocs[i].getValVT(), InFlag).getValue(1); InFlag = Chain.getValue(2); ResultVals.push_back(Chain.getValue(0)); @@ -777,7 +782,7 @@ ResultVals.push_back(Chain); // Merge everything together with a MERGE_VALUES node. - return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(), &ResultVals[0], ResultVals.size()).getNode(); } @@ -796,6 +801,7 @@ MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo(); + DebugLoc dl = Op.getDebugLoc(); bool isVarArg = cast(Op.getOperand(2))->getZExtValue() != 0; unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); @@ -840,20 +846,20 @@ // Transform the arguments stored on // physical registers into virtual ones unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); - SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); + SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT); // If this is an 8 or 16-bit value, it is really passed promoted // to 32 bits. Insert an assert[sz]ext to capture this, then // truncate to the right size. if (VA.getLocInfo() == CCValAssign::SExt) - ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue, + ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, DAG.getValueType(VA.getValVT())); else if (VA.getLocInfo() == CCValAssign::ZExt) - ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue, + ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, DAG.getValueType(VA.getValVT())); if (VA.getLocInfo() != CCValAssign::Full) - ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue); + ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); ArgValues.push_back(ArgValue); @@ -877,7 +883,7 @@ // emit ISD::STORE whichs stores the // parameter value to a stack Location - ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0)); + ArgValues.push_back(DAG.getStore(Root, dl, ArgValue, PtrOff, NULL, 0)); } } else { // VA.isRegLoc() @@ -900,7 +906,7 @@ // Create load nodes to retrieve arguments from the stack SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); - ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0)); + ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0)); } } @@ -913,14 +919,14 @@ Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); MipsFI->setSRetReturnReg(Reg); } - SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]); - Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root); + SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]); + Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root); } ArgValues.push_back(Root); // Return the new list of results. - return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), &ArgValues[0], ArgValues.size()).getValue(Op.getResNo()); } Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=63767&r1=63766&r2=63767&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Feb 4 14:06:27 2009 @@ -1140,11 +1140,12 @@ GlobalValue *GV = GSDN->getGlobal(); SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); SDValue Zero = DAG.getConstant(0, PtrVT); + DebugLoc dl = GSDN->getDebugLoc(); const TargetMachine &TM = DAG.getTarget(); - SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); - SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); + SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero); + SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero); // If this is a non-darwin platform, we don't support non-static relo models // yet. @@ -1152,23 +1153,23 @@ !TM.getSubtarget().isDarwin()) { // Generate non-pic code that has direct accesses to globals. // The address of the global is just (hi(&g)+lo(&g)). - return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); + return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); } if (TM.getRelocationModel() == Reloc::PIC_) { // With PIC, the first instruction is actually "GR+hi(&G)". - Hi = DAG.getNode(ISD::ADD, PtrVT, + Hi = DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); } - Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); + Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); if (!TM.getSubtarget().hasLazyResolverStub(GV)) return Lo; // If the global is weak or external, we have to go through the lazy // resolution stub. - return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); + return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0); } SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { @@ -1270,6 +1271,7 @@ unsigned VarArgsNumGPR, unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget) { + DebugLoc dl = Op.getNode()->getDebugLoc(); if (Subtarget.isMachoABI()) { // vastart just stores the address of the VarArgsFrameIndex slot into the @@ -1277,7 +1279,7 @@ MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); const Value *SV = cast(Op.getOperand(2))->getValue(); - return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); + return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); } // For ELF 32 ABI we follow the layout of the va_list struct. @@ -1326,26 +1328,26 @@ const Value *SV = cast(Op.getOperand(2))->getValue(); // Store first byte : number of int regs - SDValue firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, + SDValue firstStore = DAG.getStore(Op.getOperand(0), dl, ArgGPR, Op.getOperand(1), SV, 0); uint64_t nextOffset = FPROffset; - SDValue nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), + SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), ConstFPROffset); // Store second byte : number of float regs SDValue secondStore = - DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset); + DAG.getStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset); nextOffset += StackOffset; - nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset); + nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); // Store second word : arguments given on stack SDValue thirdStore = - DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset); + DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset); nextOffset += FrameOffset; - nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset); + nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset); // Store third word : arguments given in registers - return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset); + return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset); } @@ -1987,13 +1989,14 @@ StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, SDValue Chain, const SmallVector &TailCallArgs, - SmallVector &MemOpChains) { + SmallVector &MemOpChains, + DebugLoc dl) { for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { SDValue Arg = TailCallArgs[i].Arg; SDValue FIN = TailCallArgs[i].FrameIdxOp; int FI = TailCallArgs[i].FrameIdx; // Store relative to framepointer. - MemOpChains.push_back(DAG.getStore(Chain, Arg, FIN, + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN, PseudoSourceValue::getFixedStack(FI), 0)); } @@ -2008,7 +2011,8 @@ SDValue OldFP, int SPDiff, bool isPPC64, - bool isMachoABI) { + bool isMachoABI, + DebugLoc dl) { if (SPDiff) { // Calculate the new stack slot for the return address. int SlotSize = isPPC64 ? 8 : 4; @@ -2022,10 +2026,10 @@ MVT VT = isPPC64 ? MVT::i64 : MVT::i32; SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); - Chain = DAG.getStore(Chain, OldRetAddr, NewRetAddrFrIdx, + Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, PseudoSourceValue::getFixedStack(NewRetAddr), 0); SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); - Chain = DAG.getStore(Chain, OldFP, NewFramePtrIdx, + Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, PseudoSourceValue::getFixedStack(NewFPIdx), 0); } return Chain; @@ -2053,18 +2057,19 @@ /// stack slot. Returns the chain as result and the loaded frame pointers in /// LROpOut/FPOpout. Used when tail calling. SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, - int SPDiff, - SDValue Chain, - SDValue &LROpOut, - SDValue &FPOpOut) { + int SPDiff, + SDValue Chain, + SDValue &LROpOut, + SDValue &FPOpOut, + DebugLoc dl) { if (SPDiff) { // Load the LR and FP stack slot for later adjusting. MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; LROpOut = getReturnAddrFrameIndex(DAG); - LROpOut = DAG.getLoad(VT, Chain, LROpOut, NULL, 0); + LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0); Chain = SDValue(LROpOut.getNode(), 1); FPOpOut = getFramePointerFrameIndex(DAG); - FPOpOut = DAG.getLoad(VT, Chain, FPOpOut, NULL, 0); + FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0); Chain = SDValue(FPOpOut.getNode(), 1); } return Chain; @@ -2092,7 +2097,8 @@ SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVector &MemOpChains, - SmallVector& TailCallArguments) { + SmallVector& TailCallArguments, + DebugLoc dl) { MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); if (!isTailCall) { if (isVector) { @@ -2101,10 +2107,10 @@ StackPtr = DAG.getRegister(PPC::X1, MVT::i64); else StackPtr = DAG.getRegister(PPC::R1, MVT::i32); - PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, + PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, DAG.getConstant(ArgOffset, PtrVT)); } - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); // Calculate and remember argument location. } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, TailCallArguments); @@ -2165,7 +2171,7 @@ // Load the return address and frame pointer so it can be move somewhere else // later. SDValue LROp, FPOp; - Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp); + Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl); // Set up a copy of the stack pointer for use loading and storing any // arguments that may not fit in the registers available for argument @@ -2306,7 +2312,7 @@ } else { LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, isPPC64, isTailCall, false, MemOpChains, - TailCallArguments); + TailCallArguments, dl); inMem = true; } if (inMem || isMachoABI) { @@ -2356,7 +2362,7 @@ } else { LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, isPPC64, isTailCall, false, MemOpChains, - TailCallArguments); + TailCallArguments, dl); inMem = true; } if (inMem || isMachoABI) { @@ -2417,7 +2423,7 @@ // We are emitting Altivec params in order. LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, isPPC64, isTailCall, true, MemOpChains, - TailCallArguments); + TailCallArguments, dl); ArgOffset += 16; } break; @@ -2443,7 +2449,7 @@ // We are emitting Altivec params in order. LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, isPPC64, isTailCall, true, MemOpChains, - TailCallArguments); + TailCallArguments, dl); ArgOffset += 16; } } @@ -2477,14 +2483,14 @@ // Do not flag preceeding copytoreg stuff together with the following stuff. InFlag = SDValue(); StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, - MemOpChains2); + MemOpChains2, dl); if (!MemOpChains2.empty()) Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains2[0], MemOpChains2.size()); // Store the return address to the appropriate stack slot. Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, - isPPC64, isMachoABI); + isPPC64, isMachoABI, dl); } // Emit callseq_end just before tailcall node. @@ -2679,6 +2685,7 @@ SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) { // When we pop the dynamic allocation we need to restore the SP link. + DebugLoc dl = Op.getNode()->getDebugLoc(); // Get the corect type for pointers. MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); @@ -2693,13 +2700,13 @@ SDValue SaveSP = Op.getOperand(1); // Load the old link SP. - SDValue LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0); + SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0); // Restore the stack pointer. - Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP); + Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); // Store the old link SP. - return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0); + return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0); } @@ -2850,17 +2857,18 @@ SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { assert(Op.getOperand(0).getValueType().isFloatingPoint()); SDValue Src = Op.getOperand(0); + DebugLoc dl = Op.getNode()->getDebugLoc(); if (Src.getValueType() == MVT::f32) - Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); + Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); SDValue Tmp; switch (Op.getValueType().getSimpleVT()) { default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); case MVT::i32: - Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); + Tmp = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Src); break; case MVT::i64: - Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); + Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src); break; } @@ -2868,26 +2876,29 @@ SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); // Emit a store to the stack slot. - SDValue Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0); + SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0); // Result is a load from the stack slot. If loading 4 bytes, make sure to // add in a bias. if (Op.getValueType() == MVT::i32) - FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, + FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, DAG.getConstant(4, FIPtr.getValueType())); - return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0); + return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0); } SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); // Don't handle ppc_fp128 here; let it be lowered to a libcall. if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) return SDValue(); if (Op.getOperand(0).getValueType() == MVT::i64) { - SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); - SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); + SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl, + MVT::f64, Op.getOperand(0)); + SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); if (Op.getValueType() == MVT::f32) - FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); + FP = DAG.getNode(ISD::FP_ROUND, dl, + MVT::f32, FP, DAG.getIntPtrConstant(0)); return FP; } @@ -2902,26 +2913,27 @@ MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); - SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, + SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32, Op.getOperand(0)); // STD the extended value into the stack slot. MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx), MachineMemOperand::MOStore, 0, 8, 8); - SDValue Store = DAG.getNode(PPCISD::STD_32, MVT::Other, + SDValue Store = DAG.getNode(PPCISD::STD_32, dl, MVT::Other, DAG.getEntryNode(), Ext64, FIdx, DAG.getMemOperand(MO)); // Load the value as a double. - SDValue Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); + SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0); // FCFID it and return it. - SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); + SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); if (Op.getValueType() == MVT::f32) - FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); + FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); return FP; } SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); /* The rounding mode is in bits 30:31 of FPSR, and has the following settings: @@ -2950,36 +2962,36 @@ // Save FP Control Word to register NodeTys.push_back(MVT::f64); // return register NodeTys.push_back(MVT::Flag); // unused in this context - SDValue Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); + SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); // Save FP register to stack slot int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); - SDValue Store = DAG.getStore(DAG.getEntryNode(), Chain, + SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, StackSlot, NULL, 0); // Load FP Control Word from low 32 bits of stack slot. SDValue Four = DAG.getConstant(4, PtrVT); - SDValue Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four); - SDValue CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0); + SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); + SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0); // Transform as necessary SDValue CWD1 = - DAG.getNode(ISD::AND, MVT::i32, + DAG.getNode(ISD::AND, dl, MVT::i32, CWD, DAG.getConstant(3, MVT::i32)); SDValue CWD2 = - DAG.getNode(ISD::SRL, MVT::i32, - DAG.getNode(ISD::AND, MVT::i32, - DAG.getNode(ISD::XOR, MVT::i32, + DAG.getNode(ISD::SRL, dl, MVT::i32, + DAG.getNode(ISD::AND, dl, MVT::i32, + DAG.getNode(ISD::XOR, dl, MVT::i32, CWD, DAG.getConstant(3, MVT::i32)), DAG.getConstant(3, MVT::i32)), DAG.getConstant(1, MVT::i32)); SDValue RetVal = - DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2); + DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); return DAG.getNode((VT.getSizeInBits() < 16 ? - ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); + ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); } SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) { @@ -3713,6 +3725,7 @@ SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); // Create a stack slot that is 16-byte aligned. MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); int FrameIdx = FrameInfo->CreateStackObject(16, 16); @@ -3720,10 +3733,10 @@ SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); // Store the input value into Value#0 of the stack slot. - SDValue Store = DAG.getStore(DAG.getEntryNode(), + SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx, NULL, 0); // Load it out. - return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); + return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0); } SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { @@ -4893,6 +4906,7 @@ } SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); // Depths > 0 not supported yet! if (cast(Op.getOperand(0))->getZExtValue() > 0) return SDValue(); @@ -4906,7 +4920,8 @@ // Make sure the function really does not optimize away the store of the RA // to the stack. FuncInfo->setLRStoreRequired(); - return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); + return DAG.getLoad(getPointerTy(), dl, + DAG.getEntryNode(), RetAddrFI, NULL, 0); } SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=63767&r1=63766&r2=63767&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Wed Feb 4 14:06:27 2009 @@ -340,10 +340,11 @@ SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, - int SPDiff, - SDValue Chain, - SDValue &LROpOut, - SDValue &FPOpOut); + int SPDiff, + SDValue Chain, + SDValue &LROpOut, + SDValue &FPOpOut, + DebugLoc dl); SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG); SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=63767&r1=63766&r2=63767&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Wed Feb 4 14:06:27 2009 @@ -231,6 +231,7 @@ SDValue Chain = TheCall->getChain(); SDValue Callee = TheCall->getCallee(); bool isVarArg = TheCall->isVarArg(); + DebugLoc dl = TheCall->getDebugLoc(); #if 0 // Analyze operands of the call, assigning locations to each operand. @@ -344,7 +345,7 @@ ValToStore = Val; } else { // Convert this to a FP value in an int reg. - Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); + Val = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Val); RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val)); } break; @@ -358,14 +359,15 @@ // Break into top and bottom parts by storing to the stack and loading // out the parts as integers. Top part goes in a reg. SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32); - SDValue Store = DAG.getStore(DAG.getEntryNode(), Val, StackPtr, NULL, 0); + SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, + Val, StackPtr, NULL, 0); // Sparc is big-endian, so the high part comes first. - SDValue Hi = DAG.getLoad(MVT::i32, Store, StackPtr, NULL, 0, 0); + SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0); // Increment the pointer to the other half. - StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr, + StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, DAG.getIntPtrConstant(4)); // Load the low part. - SDValue Lo = DAG.getLoad(MVT::i32, Store, StackPtr, NULL, 0, 0); + SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0); RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi)); @@ -386,9 +388,9 @@ } // Split the value into top and bottom part. Top part goes in a reg. - SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val, DAG.getConstant(1, MVT::i32)); - SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val, DAG.getConstant(0, MVT::i32)); RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi)); @@ -406,8 +408,9 @@ if (ValToStore.getNode()) { SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32); - PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); - MemOpChains.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); + PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); + MemOpChains.push_back(DAG.getStore(Chain, dl, ValToStore, + PtrOff, NULL, 0)); } ArgOffset += ObjSize; } @@ -415,7 +418,7 @@ // Emit all stores, make sure the occur before any copies into physregs. if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token @@ -429,7 +432,7 @@ if (Reg >= SP::I0 && Reg <= SP::I7) Reg = Reg-SP::I0+SP::O0; - Chain = DAG.getCopyToReg(Chain, Reg, RegsToPass[i].second, InFlag); + Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } @@ -445,7 +448,7 @@ NodeTys.push_back(MVT::Other); // Returns a chain NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. SDValue Ops[] = { Chain, Callee, InFlag }; - Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.getNode() ? 3 : 2); + Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops, InFlag.getNode() ? 3 : 2); InFlag = Chain.getValue(1); Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), @@ -467,7 +470,7 @@ if (Reg >= SP::I0 && Reg <= SP::I7) Reg = Reg-SP::I0+SP::O0; - Chain = DAG.getCopyFromReg(Chain, Reg, + Chain = DAG.getCopyFromReg(Chain, dl, Reg, RVLocs[i].getValVT(), InFlag).getValue(1); InFlag = Chain.getValue(2); ResultVals.push_back(Chain.getValue(0)); @@ -476,7 +479,8 @@ ResultVals.push_back(Chain); // Merge everything together with a MERGE_VALUES node. - return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), &ResultVals[0], + return DAG.getNode(ISD::MERGE_VALUES, dl, + TheCall->getVTList(), &ResultVals[0], ResultVals.size()); } @@ -824,12 +828,13 @@ SparcTargetLowering &TLI) { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. - SDValue Offset = DAG.getNode(ISD::ADD, MVT::i32, + DebugLoc dl = Op.getNode()->getDebugLoc(); + SDValue Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, DAG.getRegister(SP::I6, MVT::i32), DAG.getConstant(TLI.getVarArgsFrameOffset(), MVT::i32)); const Value *SV = cast(Op.getOperand(2))->getValue(); - return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0); + return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), SV, 0); } static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { @@ -838,28 +843,29 @@ SDValue InChain = Node->getOperand(0); SDValue VAListPtr = Node->getOperand(1); const Value *SV = cast(Node->getOperand(2))->getValue(); - SDValue VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0); + DebugLoc dl = Node->getDebugLoc(); + SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, SV, 0); // Increment the pointer, VAList, to the next vaarg - SDValue NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList, + SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList, DAG.getConstant(VT.getSizeInBits()/8, MVT::i32)); // Store the incremented VAList to the legalized pointer - InChain = DAG.getStore(VAList.getValue(1), NextPtr, + InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr, VAListPtr, SV, 0); // Load the actual argument out of the pointer VAList, unless this is an // f64 load. if (VT != MVT::f64) - return DAG.getLoad(VT, InChain, VAList, NULL, 0); + return DAG.getLoad(VT, dl, InChain, VAList, NULL, 0); // Otherwise, load it as i64, then do a bitconvert. - SDValue V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0); + SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, NULL, 0); // Bit-Convert the value to f64. SDValue Ops[2] = { - DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V), + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, V), V.getValue(1) }; - return DAG.getMergeValues(Ops, 2); + return DAG.getMergeValues(Ops, 2, dl); } static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=63767&r1=63766&r2=63767&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Feb 4 14:06:27 2009 @@ -4527,7 +4527,7 @@ } SDValue -X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, +X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, int64_t Offset, SelectionDAG &DAG) const { bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_; @@ -4546,8 +4546,8 @@ // With PIC, the address is actually $g + Offset. if (IsPic && !Subtarget->isPICStyleRIPRel()) { - Result = DAG.getNode(ISD::ADD, getPointerTy(), - DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), + Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), + DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), Result); } @@ -4557,13 +4557,13 @@ // the GV offset field. Platform check is inside GVRequiresExtraLoad() call // The same applies for external symbols during PIC codegen if (ExtraLoadRequired) - Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, + Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, PseudoSourceValue::getGOT(), 0); // If there was a non-zero offset that we didn't fold, create an explicit // addition for it. if (Offset != 0) - Result = DAG.getNode(ISD::ADD, getPointerTy(), Result, + Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, DAG.getConstant(Offset, getPointerTy())); return Result; @@ -4573,7 +4573,7 @@ X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { const GlobalValue *GV = cast(Op)->getGlobal(); int64_t Offset = cast(Op)->getOffset(); - return LowerGlobalAddress(GV, Offset, DAG); + return LowerGlobalAddress(GV, Op.getNode()->getDebugLoc(), Offset, DAG); } // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit @@ -4653,6 +4653,7 @@ // "local exec" model. static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, const MVT PtrVT) { + DebugLoc dl = GA->getDebugLoc(); // Get the Thread Pointer SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT); // emit "addl x at ntpoff,%eax" (local exec) or "addl x at indntpoff,%eax" (initial @@ -4663,12 +4664,12 @@ SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA); if (GA->getGlobal()->isDeclaration()) // initial exec TLS model - Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, + Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, PseudoSourceValue::getGOT(), 0); // The address of the thread local variable is the add of the thread // pointer with the offset of the variable. - return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); + return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); } SDValue @@ -8227,7 +8228,8 @@ if (GA) { if (hasMemory) - Op = LowerGlobalAddress(GA->getGlobal(), Offset, DAG); + Op = LowerGlobalAddress(GA->getGlobal(), Op.getNode()->getDebugLoc(), + Offset, DAG); else Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), Offset); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=63767&r1=63766&r2=63767&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Feb 4 14:06:27 2009 @@ -566,8 +566,8 @@ SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG); SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG); SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); - SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset, - SelectionDAG &DAG) const; + SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, + int64_t Offset, SelectionDAG &DAG) const; SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG); Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=63767&r1=63766&r2=63767&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Wed Feb 4 14:06:27 2009 @@ -340,30 +340,32 @@ assert(0 && "unimplemented"); // FIX Arguments passed by reference need a extra dereference. SDNode *Node = Op.getNode(); + DebugLoc dl = Node->getDebugLoc(); const Value *V = cast(Node->getOperand(2))->getValue(); MVT VT = Node->getValueType(0); - SDValue VAList = DAG.getLoad(getPointerTy(), Node->getOperand(0), + SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0), Node->getOperand(1), V, 0); // Increment the pointer, VAList, to the next vararg - SDValue Tmp3 = DAG.getNode(ISD::ADD, getPointerTy(), VAList, + SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList, DAG.getConstant(VT.getSizeInBits(), getPointerTy())); // Store the incremented VAList to the legalized pointer - Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Node->getOperand(1), V, 0); + Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1), V, 0); // Load the actual argument out of the pointer VAList - return DAG.getLoad(VT, Tmp3, VAList, NULL, 0); + return DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0); } SDValue XCoreTargetLowering:: LowerVASTART(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); // vastart stores the address of the VarArgsFrameIndex slot into the // memory location argument MachineFunction &MF = DAG.getMachineFunction(); XCoreFunctionInfo *XFI = MF.getInfo(); SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32); const Value *SV = cast(Op.getOperand(2))->getValue(); - return DAG.getStore(Op.getOperand(0), Addr, Op.getOperand(1), SV, 0); + return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1), SV, 0); } SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { @@ -601,6 +603,7 @@ SDValue Root = Op.getOperand(0); bool isVarArg = cast(Op.getOperand(2))->getZExtValue() != 0; unsigned CC = MF.getFunction()->getCallingConv(); + DebugLoc dl = Op.getDebugLoc(); // Assign locations to all of the incoming arguments. SmallVector ArgLocs; @@ -631,7 +634,7 @@ unsigned VReg = RegInfo.createVirtualRegister( XCore::GRRegsRegisterClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); - ArgValues.push_back(DAG.getCopyFromReg(Root, VReg, RegVT)); + ArgValues.push_back(DAG.getCopyFromReg(Root, dl, VReg, RegVT)); } } else { // sanity check @@ -650,7 +653,7 @@ // Create the SelectionDAG nodes corresponding to a load //from this parameter SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); - ArgValues.push_back(DAG.getLoad(VA.getLocVT(), Root, FIN, NULL, 0)); + ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN, NULL, 0)); } } @@ -679,13 +682,13 @@ unsigned VReg = RegInfo.createVirtualRegister( XCore::GRRegsRegisterClass); RegInfo.addLiveIn(ArgRegs[i], VReg); - SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); + SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); // Move argument from virt reg -> stack - SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); + SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); MemOps.push_back(Store); } if (!MemOps.empty()) - Root = DAG.getNode(ISD::TokenFactor, MVT::Other, + Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0], MemOps.size()); } else { // This will point to the next argument passed via stack. @@ -699,7 +702,8 @@ // Return the new list of results. std::vector RetVT(Op.getNode()->value_begin(), Op.getNode()->value_end()); - return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); + return DAG.getNode(ISD::MERGE_VALUES, dl, RetVT, + &ArgValues[0], ArgValues.size()); } //===----------------------------------------------------------------------===// From stuart at apple.com Wed Feb 4 14:30:10 2009 From: stuart at apple.com (Stuart Hastings) Date: Wed, 04 Feb 2009 20:30:10 -0000 Subject: [llvm-commits] [llvm] r63768 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200902042030.n14KUBV8016955@zion.cs.uiuc.edu> Author: stuart Date: Wed Feb 4 14:30:10 2009 New Revision: 63768 URL: http://llvm.org/viewvc/llvm-project?rev=63768&view=rev Log: 80 column rule. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63768&r1=63767&r2=63768&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Feb 4 14:30:10 2009 @@ -5753,7 +5753,8 @@ } typedef SmallPtrSet VisitedSDNodeSet; -static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent, const SelectionDAG *G, VisitedSDNodeSet &once) { +static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent, + const SelectionDAG *G, VisitedSDNodeSet &once) { if (!once.insert(N)) // If we've been here before, return now. return; // Dump the current SDNode, but don't end the line yet. From edwintorok at gmail.com Wed Feb 4 15:00:02 2009 From: edwintorok at gmail.com (Torok Edwin) Date: Wed, 04 Feb 2009 21:00:02 -0000 Subject: [llvm-commits] [llvm] r63771 - /llvm/trunk/tools/gold/gold-plugin.cpp Message-ID: <200902042100.n14L0273017851@zion.cs.uiuc.edu> Author: edwin Date: Wed Feb 4 15:00:02 2009 New Revision: 63771 URL: http://llvm.org/viewvc/llvm-project?rev=63771&view=rev Log: Alphabetize includes. Update comment. Modified: llvm/trunk/tools/gold/gold-plugin.cpp Modified: llvm/trunk/tools/gold/gold-plugin.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/gold-plugin.cpp?rev=63771&r1=63770&r2=63771&view=diff ============================================================================== --- llvm/trunk/tools/gold/gold-plugin.cpp (original) +++ llvm/trunk/tools/gold/gold-plugin.cpp Wed Feb 4 15:00:02 2009 @@ -19,11 +19,11 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/System/Path.h" +#include #include #include #include #include -#include using namespace llvm; @@ -158,10 +158,9 @@ ld_plugin_status claim_file_hook(const ld_plugin_input_file *file, int *claimed) { void *buf = NULL; - // If set, this means gold found IR in an ELF section. LLVM doesn't wrap its - // IR in ELF, so we know it's not us. But it can also be an .a file containing - // LLVM IR. if (file->offset) { + /* This is probably an archive member containing either an ELF object, or + * LLVM IR. Find out which one it is */ if (lseek(file->fd, file->offset, SEEK_SET) == -1) { (*message)(LDPL_ERROR, "Failed to seek to archive member of %s at offset %d: %s\n", From natebegeman at mac.com Wed Feb 4 15:07:38 2009 From: natebegeman at mac.com (Nate Begeman) Date: Wed, 04 Feb 2009 21:07:38 -0000 Subject: [llvm-commits] [llvm] r63772 - /llvm/trunk/test/Assembler/2007-04-15-BadIntrinsic.ll Message-ID: <200902042107.n14L7cV6018098@zion.cs.uiuc.edu> Author: sampo Date: Wed Feb 4 15:07:37 2009 New Revision: 63772 URL: http://llvm.org/viewvc/llvm-project?rev=63772&view=rev Log: Remove now-incorrect test. Removed: llvm/trunk/test/Assembler/2007-04-15-BadIntrinsic.ll Removed: llvm/trunk/test/Assembler/2007-04-15-BadIntrinsic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/2007-04-15-BadIntrinsic.ll?rev=63771&view=auto ============================================================================== --- llvm/trunk/test/Assembler/2007-04-15-BadIntrinsic.ll (original) +++ llvm/trunk/test/Assembler/2007-04-15-BadIntrinsic.ll (removed) @@ -1,9 +0,0 @@ -; RUN: not llvm-as %s -o /dev/null -f |& grep {Call to invalid LLVM intrinsic} - -declare i32 @llvm.foobar(i32 %foo) - -define i32 @test() { - %nada = call i32 @llvm.foobar(i32 0) - ret i32 %nada -} - From wangmp at apple.com Wed Feb 4 15:10:56 2009 From: wangmp at apple.com (Mon P Wang) Date: Wed, 04 Feb 2009 21:10:56 -0000 Subject: [llvm-commits] [llvm] r63774 - /llvm/trunk/test/CodeGen/X86/legalizedag_vec.ll Message-ID: <200902042110.n14LAuLD018215@zion.cs.uiuc.edu> Author: wangmp Date: Wed Feb 4 15:10:56 2009 New Revision: 63774 URL: http://llvm.org/viewvc/llvm-project?rev=63774&view=rev Log: Add test case for r63760. Added: llvm/trunk/test/CodeGen/X86/legalizedag_vec.ll Added: llvm/trunk/test/CodeGen/X86/legalizedag_vec.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/legalizedag_vec.ll?rev=63774&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/legalizedag_vec.ll (added) +++ llvm/trunk/test/CodeGen/X86/legalizedag_vec.ll Wed Feb 4 15:10:56 2009 @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -disable-mmx -o %t -f +; RUN: grep divdi3 %t | count 2 + + +; Test case for r63760 where we generate a legalization assert that an illegal +; type has been inserted by LegalizeDAG after LegalizeType has run. With sse2, +; v2i64 is a legal type but with mmx disabled, i64 is an illegal type. When +; legalizing the divide in LegalizeDAG, we scalarize the vector divide and make +; two 64 bit divide library calls which introduces i64 nodes that needs to be +; promoted. + +define <2 x i64> @test_long_div(<2 x i64> %num, <2 x i64> %div) { + %div.r = sdiv <2 x i64> %num, %div + ret <2 x i64> %div.r +} \ No newline at end of file From wangmp at apple.com Wed Feb 4 15:12:06 2009 From: wangmp at apple.com (Mon Ping Wang) Date: Wed, 4 Feb 2009 13:12:06 -0800 Subject: [llvm-commits] [llvm] r63760 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp In-Reply-To: <200902042057.21140.baldrick@free.fr> References: <200902041938.n14JcFGo015187@zion.cs.uiuc.edu> <200902042057.21140.baldrick@free.fr> Message-ID: <0CF40453-0BDD-4482-8A1B-1A289D689173@apple.com> Fixed. Grazie, -- Mon Ping On Feb 4, 2009, at 11:57 AM, Duncan Sands wrote: > Testcase? > > Ciao, > > Duncan. From dpatel at apple.com Wed Feb 4 15:39:48 2009 From: dpatel at apple.com (Devang Patel) Date: Wed, 04 Feb 2009 21:39:48 -0000 Subject: [llvm-commits] [llvm] r63781 - in /llvm/trunk: lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/branch_fold_dbg.ll Message-ID: <200902042139.n14LdmXK019149@zion.cs.uiuc.edu> Author: dpatel Date: Wed Feb 4 15:39:48 2009 New Revision: 63781 URL: http://llvm.org/viewvc/llvm-project?rev=63781&view=rev Log: Ignore dbg intrinsics. Added: llvm/trunk/test/Transforms/SimplifyCFG/branch_fold_dbg.ll Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=63781&r1=63780&r2=63781&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed Feb 4 15:39:48 2009 @@ -1430,14 +1430,24 @@ // Only allow this if the condition is a simple instruction that can be // executed unconditionally. It must be in the same block as the branch, and // must be at the front of the block. + BasicBlock::iterator FrontIt = BB->front(); + // Ignore dbg intrinsics. + while(isa(FrontIt)) + ++FrontIt; if ((!isa(Cond) && !isa(Cond)) || - Cond->getParent() != BB || &BB->front() != Cond || !Cond->hasOneUse()) + Cond->getParent() != BB || &*FrontIt != Cond || !Cond->hasOneUse()) { return false; + } // Make sure the instruction after the condition is the cond branch. BasicBlock::iterator CondIt = Cond; ++CondIt; - if (&*CondIt != BI) + // Ingore dbg intrinsics. + while(isa(CondIt)) + ++CondIt; + if (&*CondIt != BI) { + assert (!isa(CondIt) && "Hey do not forget debug info!"); return false; + } // Cond is known to be a compare or binary operator. Check to make sure that // neither operand is a potentially-trapping constant expression. @@ -1867,6 +1877,9 @@ BasicBlock::iterator BBI = BB->getFirstNonPHI(); BasicBlock *Succ = BI->getSuccessor(0); + // Ignore dbg intrinsics. + while (isa(BBI)) + ++BBI; if (BBI->isTerminator() && // Terminator is the only non-phi instruction! Succ != BB) // Don't hurt infinite loops! if (TryToSimplifyUncondBranchFromEmptyBlock(BB, Succ)) @@ -1884,15 +1897,24 @@ // This block must be empty, except for the setcond inst, if it exists. // Ignore dbg intrinsics. BasicBlock::iterator I = BB->begin(); + // Ignore dbg intrinsics. while (isa(I)) - I++; - if (&*I == BI || - (&*I == cast(BI->getCondition()) && - &*++I == BI)) + ++I; + if (&*I == BI) { if (FoldValueComparisonIntoPredecessors(BI)) return SimplifyCFG(BB) | true; + } else if (&*I == cast(BI->getCondition())){ + ++I; + // Ignore dbg intrinsics. + while (isa(I)) + ++I; + if(&*I == BI) { + if (FoldValueComparisonIntoPredecessors(BI)) + return SimplifyCFG(BB) | true; + } + } } - + // If this is a branch on a phi node in the current block, thread control // through this block if any PHI node entries are constants. if (PHINode *PN = dyn_cast(BI->getCondition())) Added: llvm/trunk/test/Transforms/SimplifyCFG/branch_fold_dbg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/branch_fold_dbg.ll?rev=63781&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/branch_fold_dbg.ll (added) +++ llvm/trunk/test/Transforms/SimplifyCFG/branch_fold_dbg.ll Wed Feb 4 15:39:48 2009 @@ -0,0 +1,122 @@ +; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | not grep br +; END. + + %llvm.dbg.anchor.type = type { i32, i32 } + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } + + at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata" ; + + at .str = internal constant [4 x i8] c"a.c\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at .str1 = internal constant [6 x i8] c"/tmp/\00", section "llvm.metadata" ; <[6 x i8]*> [#uses=1] + at .str2 = internal constant [55 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build 00)\00", section "llvm.metadata" ; <[55 x i8]*> [#uses=1] + at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([6 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([55 x i8]* @.str2, i32 0, i32 0), i1 true, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] + +declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind + + +define void @main() { +entry: +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %tmp.14.i19 = icmp eq i32 0, 2 ; [#uses=1] +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 %tmp.14.i19, label %endif.1.i20, label %read_min.exit +endif.1.i20: ; preds = %entry +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %tmp.9.i.i = icmp eq i8* null, null ; [#uses=1] +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 %tmp.9.i.i, label %then.i12.i, label %then.i.i +then.i.i: ; preds = %endif.1.i20 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + ret void +then.i12.i: ; preds = %endif.1.i20 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %tmp.9.i4.i = icmp eq i8* null, null ; [#uses=1] +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 %tmp.9.i4.i, label %endif.2.i33, label %then.i5.i +then.i5.i: ; preds = %then.i12.i +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + ret void +endif.2.i33: ; preds = %then.i12.i +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 false, label %loopexit.0.i40, label %no_exit.0.i35 +no_exit.0.i35: ; preds = %no_exit.0.i35, %endif.2.i33 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %tmp.130.i = icmp slt i32 0, 0 ; [#uses=1] +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 %tmp.130.i, label %loopexit.0.i40.loopexit, label %no_exit.0.i35 +loopexit.0.i40.loopexit: ; preds = %no_exit.0.i35 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br label %loopexit.0.i40 +loopexit.0.i40: ; preds = %loopexit.0.i40.loopexit, %endif.2.i33 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %tmp.341.i = icmp eq i32 0, 0 ; [#uses=1] +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 %tmp.341.i, label %loopentry.1.i, label %read_min.exit +loopentry.1.i: ; preds = %loopexit.0.i40 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %tmp.347.i = icmp sgt i32 0, 0 ; [#uses=1] +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 %tmp.347.i, label %no_exit.1.i41, label %loopexit.2.i44 +no_exit.1.i41: ; preds = %endif.5.i, %loopentry.1.i + %indvar.i42 = phi i32 [ %indvar.next.i, %endif.5.i ], [ 0, %loopentry.1.i ] ; [#uses=1] +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %tmp.355.i = icmp eq i32 0, 3 ; [#uses=1] +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 %tmp.355.i, label %endif.5.i, label %read_min.exit +endif.5.i: ; preds = %no_exit.1.i41 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %tmp.34773.i = icmp sgt i32 0, 0 ; [#uses=1] +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %indvar.next.i = add i32 %indvar.i42, 1 ; [#uses=1] +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 %tmp.34773.i, label %no_exit.1.i41, label %loopexit.1.i.loopexit +loopexit.1.i.loopexit: ; preds = %endif.5.i +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + ret void +loopexit.2.i44: ; preds = %loopentry.1.i +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + ret void +read_min.exit: ; preds = %no_exit.1.i41, %loopexit.0.i40, %entry +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %tmp.23 = icmp eq i32 0, 0 ; [#uses=1] +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 %tmp.23, label %endif.1, label %then.1 +then.1: ; preds = %read_min.exit +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 false, label %endif.0.i, label %then.0.i +then.0.i: ; preds = %then.1 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 false, label %endif.1.i, label %then.1.i +endif.0.i: ; preds = %then.1 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 false, label %endif.1.i, label %then.1.i +then.1.i: ; preds = %endif.0.i, %then.0.i +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 false, label %getfree.exit, label %then.2.i +endif.1.i: ; preds = %endif.0.i, %then.0.i +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 false, label %getfree.exit, label %then.2.i +then.2.i: ; preds = %endif.1.i, %then.1.i +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + ret void +getfree.exit: ; preds = %endif.1.i, %then.1.i +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + ret void +endif.1: ; preds = %read_min.exit +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %tmp.27.i = getelementptr i32* null, i32 0 ; [#uses=0] +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 false, label %loopexit.0.i15, label %no_exit.0.i14 +no_exit.0.i14: ; preds = %endif.1 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + ret void +loopexit.0.i15: ; preds = %endif.1 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 false, label %primal_start_artificial.exit, label %no_exit.1.i16 +no_exit.1.i16: ; preds = %no_exit.1.i16, %loopexit.0.i15 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 false, label %primal_start_artificial.exit, label %no_exit.1.i16 +primal_start_artificial.exit: ; preds = %no_exit.1.i16, %loopexit.0.i15 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + ret void +} From clattner at apple.com Wed Feb 4 15:45:04 2009 From: clattner at apple.com (Chris Lattner) Date: Wed, 4 Feb 2009 13:45:04 -0800 Subject: [llvm-commits] [llvm] r63718 - in /llvm/trunk: lib/Analysis/AliasAnalysis.cpp lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/cas.ll In-Reply-To: <200902040516.n145Gmh1032364@zion.cs.uiuc.edu> References: <200902040516.n145Gmh1032364@zion.cs.uiuc.edu> Message-ID: On Feb 3, 2009, at 9:16 PM, Owen Anderson wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=63718&view=rev > Log: > Finish making AliasAnalysis aware of the fact that most atomic > intrinsics only dereference their arguments, and enhance > BasicAA to make use of this fact when computing ModRef info. Hi Owen, thanks for working on this. > @@ -150,6 +150,27 @@ > AliasAnalysis::ModRefBehavior > AliasAnalysis::getModRefBehavior(Function *F, > std::vector > *Info) { > > + if (F->isIntrinsic()) { > + switch (F->getIntrinsicID()) { Handling of specific intrinsics like this should go into basicaa, not AliasAnalysis. You also duplicate the same code into two methods, please don't do this. Intead, add a static isCASBuiltin(ID) function or something. > +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Tue Feb 3 > 23:16:46 2009 > @@ -256,6 +256,22 @@ > // > AliasAnalysis::ModRefResult > BasicAliasAnalysis::getModRefInfo(CallSite CS, Value *P, unsigned > Size) { > + // If the function only accesses its arguments, it suffices to > check that > + // P does not alias any of those arguments. > + if (AliasAnalysis::getModRefBehavior(CS, 0) == > + AliasAnalysis::AccessesArguments) { > + bool doesAlias = false; > + for (CallSite::arg_iterator AI = CS.arg_begin(), AE = > CS.arg_end(); > + AI != AE; ++AI) > + if (alias(*AI, ~0U, P, Size) != NoAlias) { > + doesAlias = true; > + break; > + } > + > + if (!doesAlias) > + return NoModRef; > + } This code is general and independent of the AA impl, it should go into AliasAnalysis, not basicaa. -Chris From dalej at apple.com Wed Feb 4 15:48:36 2009 From: dalej at apple.com (Dale Johannesen) Date: Wed, 4 Feb 2009 13:48:36 -0800 Subject: [llvm-commits] [llvm] r63765 - in /llvm/trunk: ./ include/llvm/ include/llvm/Target/ lib/AsmParser/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/VMCore/ utils/TableGen/ In-Reply-To: <200902041947.n14JlMdj015607@zion.cs.uiuc.edu> References: <200902041947.n14JlMdj015607@zion.cs.uiuc.edu> Message-ID: <7E9D07B2-3D42-43AE-9B0E-AF4DFB602AC7@apple.com> This seems to have broken both llvm-gcc and clang. Could you look? On Feb 4, 2009, at 11:47 AMPST, Nate Begeman wrote: > Author: sampo > Date: Wed Feb 4 13:47:21 2009 > New Revision: 63765 > > URL: http://llvm.org/viewvc/llvm-project?rev=63765&view=rev > Log: > New feature: add support for target intrinsics being defined in the > target directories themselves. This also means that VMCore no longer > needs to know about every target's list of intrinsics. Future work > will include converting the PowerPC target to this interface as an > example implementation. > > Added: > llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h > llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp > Modified: > llvm/trunk/Makefile.rules > llvm/trunk/include/llvm/Function.h > llvm/trunk/include/llvm/Intrinsics.h > llvm/trunk/include/llvm/Intrinsics.td > llvm/trunk/include/llvm/Module.h > llvm/trunk/include/llvm/Target/TargetMachine.h > llvm/trunk/lib/AsmParser/LLParser.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp > llvm/trunk/lib/VMCore/AutoUpgrade.cpp > llvm/trunk/lib/VMCore/Function.cpp > llvm/trunk/lib/VMCore/Module.cpp > llvm/trunk/lib/VMCore/Verifier.cpp > llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp > llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h > llvm/trunk/utils/TableGen/CodeGenIntrinsics.h > llvm/trunk/utils/TableGen/CodeGenTarget.cpp > llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp > llvm/trunk/utils/TableGen/IntrinsicEmitter.h > llvm/trunk/utils/TableGen/TableGen.cpp > > Modified: llvm/trunk/Makefile.rules > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/Makefile.rules (original) > +++ llvm/trunk/Makefile.rules Wed Feb 4 13:47:21 2009 > @@ -1346,6 +1346,11 @@ > $(Echo) "Building $( $(Verb) $(TableGen) -gen-callingconv -o $(call SYSPATH, $@) $< > > +$(TARGET:%=$(ObjDir)/%GenIntrinsics.inc.tmp): \ > +$(ObjDir)/%GenIntrinsics.inc.tmp : Intrinsics%.td $(ObjDir)/.dir > + $(Echo) "Building $( + $(Verb) $(TableGen) -gen-tgt-intrinsic -o $(call SYSPATH, $@) $< > + > clean-local:: > -$(Verb) $(RM) -f $(INCFiles) > > > Modified: llvm/trunk/include/llvm/Function.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Function.h?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Function.h (original) > +++ llvm/trunk/include/llvm/Function.h Wed Feb 4 13:47:21 2009 > @@ -129,7 +129,7 @@ > /// The particular intrinsic functions which correspond to this > value are > /// defined in llvm/Intrinsics.h. > /// > - unsigned getIntrinsicID(bool noAssert = false) const; > + unsigned getIntrinsicID() const; > bool isIntrinsic() const { return getIntrinsicID() != 0; } > > /// getCallingConv()/setCallingConv(uint) - These method get and > set the > > Modified: llvm/trunk/include/llvm/Intrinsics.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.h?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Intrinsics.h (original) > +++ llvm/trunk/include/llvm/Intrinsics.h Wed Feb 4 13:47:21 2009 > @@ -63,6 +63,9 @@ > /// intrinsic. > Function *getDeclaration(Module *M, ID id, const Type **Tys = 0, > unsigned numTys = 0); > + > + /// Map a GCC builtin name to an intrinsic ID. > + ID getIntrinsicForGCCBuiltin(const char *Prefix, const char > *BuiltinName); > > } // End Intrinsic namespace > > > Modified: llvm/trunk/include/llvm/Intrinsics.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Intrinsics.td (original) > +++ llvm/trunk/include/llvm/Intrinsics.td Wed Feb 4 13:47:21 2009 > @@ -144,6 +144,8 @@ > list RetTypes = ret_types; > list ParamTypes = param_types; > list Properties = properties; > + > + bit isTarget = 0; > } > > /// GCCBuiltin - If this intrinsic exactly corresponds to a GCC > builtin, this > > Modified: llvm/trunk/include/llvm/Module.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Module.h?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Module.h (original) > +++ llvm/trunk/include/llvm/Module.h Wed Feb 4 13:47:21 2009 > @@ -213,6 +213,10 @@ > Constant *getOrInsertFunction(const std::string &Name, const Type > *RetTy, ...) > END_WITH_NULL; > > + Constant *getOrInsertTargetIntrinsic(const std::string &Name, > + const FunctionType *Ty, > + AttrListPtr AttributeList); > + > /// getFunction - Look up the specified function in the module > symbol table. > /// If it does not exist, return null. > Function *getFunction(const std::string &Name) const; > > Added: llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h?rev=63765&view=auto > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h (added) > +++ llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h Wed Feb 4 > 13:47:21 2009 > @@ -0,0 +1,48 @@ > +//===-- llvm/Target/TargetIntrinsicInfo.h - Instruction Info ----*- > C++ -*-===// > +// > +// The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open > Source > +// License. See LICENSE.TXT for details. > +// > +// > = > = > = > ----------------------------------------------------------------------= > ==// > +// > +// This file describes the target intrinsic instructions to the > code generator. > +// > +// > = > = > = > ----------------------------------------------------------------------= > ==// > + > +#ifndef LLVM_TARGET_TARGETINTRINSICINFO_H > +#define LLVM_TARGET_TARGETINTRINSICINFO_H > + > +namespace llvm { > + > +class Function; > +class Module; > + > + > //--------------------------------------------------------------------------- > +/// > +/// TargetIntrinsicInfo - Interface to description of machine > instruction set > +/// > +class TargetIntrinsicInfo { > + > + const char **Intrinsics; // Raw array to allow > static init'n > + unsigned NumIntrinsics; // Number of entries in > the desc array > + > + TargetIntrinsicInfo(const TargetIntrinsicInfo &); // DO NOT > IMPLEMENT > + void operator=(const TargetIntrinsicInfo &); // DO NOT IMPLEMENT > +public: > + TargetIntrinsicInfo(const char **desc, unsigned num); > + virtual ~TargetIntrinsicInfo(); > + > + unsigned getNumIntrinsics() const { return NumIntrinsics; } > + > + virtual Function *getDeclaration(Module *M, const char > *BuiltinName) const { > + return 0; > + } > + > + virtual unsigned getIntrinsicID(Function *F) const { return 0; } > +}; > + > +} // End llvm namespace > + > +#endif > > Modified: llvm/trunk/include/llvm/Target/TargetMachine.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Target/TargetMachine.h (original) > +++ llvm/trunk/include/llvm/Target/TargetMachine.h Wed Feb 4 > 13:47:21 2009 > @@ -23,6 +23,7 @@ > class TargetData; > class TargetSubtarget; > class TargetInstrInfo; > +class TargetIntrinsicInfo; > class TargetJITInfo; > class TargetLowering; > class TargetFrameInfo; > @@ -118,7 +119,6 @@ > virtual TargetLowering *getTargetLowering() const > { return 0; } > virtual const TargetData *getTargetData() const > { return 0; } > > - > /// getTargetAsmInfo - Return target specific asm information. > /// > const TargetAsmInfo *getTargetAsmInfo() const { > @@ -141,6 +141,11 @@ > /// details of graph coloring register allocation removed from it. > /// > virtual const TargetRegisterInfo *getRegisterInfo() const { return > 0; } > + > + /// getIntrinsicInfo - If intrinsic information is available, > return it. If > + /// not, return null. > + /// > + virtual const TargetIntrinsicInfo *getIntrinsicInfo() const > { return 0; } > > /// getJITInfo - If this target supports a JIT, return information > for it, > /// otherwise return null. > > Modified: llvm/trunk/lib/AsmParser/LLParser.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) > +++ llvm/trunk/lib/AsmParser/LLParser.cpp Wed Feb 4 13:47:21 2009 > @@ -2949,15 +2949,6 @@ > Value *Callee; > if (ConvertValIDToValue(PFTy, CalleeID, Callee, PFS)) return true; > > - // Check for call to invalid intrinsic to avoid crashing later. > - if (Function *F = dyn_cast(Callee)) { > - if (F->hasName() && F->getNameLen() >= 5 && > - !strncmp(F->getValueName()->getKeyData(), "llvm.", 5) && > - !F->getIntrinsicID(true)) > - return Error(CallLoc, "Call to invalid LLVM intrinsic > function '" + > - F->getNameStr() + "'"); > - } > - > // FIXME: In LLVM 3.0, stop accepting zext, sext and inreg as > optional > // function attributes. > unsigned ObsoleteFuncAttrs = Attribute::ZExt|Attribute::SExt| > Attribute::InReg; > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp > (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Wed > Feb 4 13:47:21 2009 > @@ -43,6 +43,7 @@ > #include "llvm/Target/TargetData.h" > #include "llvm/Target/TargetFrameInfo.h" > #include "llvm/Target/TargetInstrInfo.h" > +#include "llvm/Target/TargetIntrinsicInfo.h" > #include "llvm/Target/TargetLowering.h" > #include "llvm/Target/TargetMachine.h" > #include "llvm/Target/TargetOptions.h" > @@ -4426,6 +4427,14 @@ > const char *RenameFn = 0; > if (Function *F = I.getCalledFunction()) { > if (F->isDeclaration()) { > + const TargetIntrinsicInfo *II = > TLI.getTargetMachine().getIntrinsicInfo(); > + if (II) { > + if (unsigned IID = II->getIntrinsicID(F)) { > + RenameFn = visitIntrinsicCall(I, IID); > + if (!RenameFn) > + return; > + } > + } > if (unsigned IID = F->getIntrinsicID()) { > RenameFn = visitIntrinsicCall(I, IID); > if (!RenameFn) > > Added: llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp?rev=63765&view=auto > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp (added) > +++ llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp Wed Feb 4 > 13:47:21 2009 > @@ -0,0 +1,22 @@ > +//===-- TargetIntrinsicInfo.cpp - Target Instruction Information > ----------===// > +// > +// The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open > Source > +// License. See LICENSE.TXT for details. > +// > +// > = > = > = > ----------------------------------------------------------------------= > ==// > +// > +// This file implements the TargetIntrinsicInfo class. > +// > +// > = > = > = > ----------------------------------------------------------------------= > ==// > + > +#include "llvm/Target/TargetIntrinsicInfo.h" > +using namespace llvm; > + > +TargetIntrinsicInfo::TargetIntrinsicInfo(const char **desc, > unsigned count) > + : Intrinsics(desc), NumIntrinsics(count) { > +} > + > +TargetIntrinsicInfo::~TargetIntrinsicInfo() { > +} > > Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original) > +++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Wed Feb 4 13:47:21 2009 > @@ -217,7 +217,7 @@ > // Upgrade intrinsic attributes. This does not change the function. > if (NewFn) > F = NewFn; > - if (unsigned id = F->getIntrinsicID(true)) > + if (unsigned id = F->getIntrinsicID()) > F->setAttributes(Intrinsic::getAttributes((Intrinsic::ID)id)); > return Upgraded; > } > > Modified: llvm/trunk/lib/VMCore/Function.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Function.cpp?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/VMCore/Function.cpp (original) > +++ llvm/trunk/lib/VMCore/Function.cpp Wed Feb 4 13:47:21 2009 > @@ -175,7 +175,7 @@ > ParentModule->getFunctionList().push_back(this); > > // Ensure intrinsics have the right parameter attributes. > - if (unsigned IID = getIntrinsicID(true)) > + if (unsigned IID = getIntrinsicID()) > setAttributes(Intrinsic::getAttributes(Intrinsic::ID(IID))); > > } > @@ -304,7 +304,7 @@ > /// particular intrinsic functions which correspond to this value > are defined in > /// llvm/Intrinsics.h. > /// > -unsigned Function::getIntrinsicID(bool noAssert) const { > +unsigned Function::getIntrinsicID() const { > const ValueName *ValName = this->getValueName(); > if (!ValName) > return 0; > @@ -315,12 +315,9 @@ > || Name[2] != 'v' || Name[3] != 'm') > return 0; // All intrinsics start with 'llvm.' > > - assert((Len != 5 || noAssert) && "'llvm.' is an invalid intrinsic > name!"); > - > #define GET_FUNCTION_RECOGNIZER > #include "llvm/Intrinsics.gen" > #undef GET_FUNCTION_RECOGNIZER > - assert(noAssert && "Invalid LLVM intrinsic name"); > return 0; > } > > @@ -373,4 +370,9 @@ > getType(id, Tys, numTys))); > } > > +// This defines the "Intrinsic::getIntrinsicForGCCBuiltin()" method. > +#define GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN > +#include "llvm/Intrinsics.gen" > +#undef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN > + > // vim: sw=2 ai > > Modified: llvm/trunk/lib/VMCore/Module.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Module.cpp?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/VMCore/Module.cpp (original) > +++ llvm/trunk/lib/VMCore/Module.cpp Wed Feb 4 13:47:21 2009 > @@ -171,6 +171,25 @@ > return F; > } > > +Constant *Module::getOrInsertTargetIntrinsic(const std::string &Name, > + const FunctionType *Ty, > + AttrListPtr > AttributeList) { > + ValueSymbolTable &SymTab = getValueSymbolTable(); > + > + // See if we have a definition for the specified function already. > + GlobalValue *F = > dyn_cast_or_null(SymTab.lookup(Name)); > + if (F == 0) { > + // Nope, add it > + Function *New = Function::Create(Ty, > GlobalVariable::ExternalLinkage, Name); > + New->setAttributes(AttributeList); > + FunctionList.push_back(New); > + return New; // Return the new prototype. > + } > + > + // Otherwise, we just found the existing function or a prototype. > + return F; > +} > + > Constant *Module::getOrInsertFunction(const std::string &Name, > const FunctionType *Ty) { > AttrListPtr AttributeList = AttrListPtr::get((AttributeWithIndex > *)0, 0); > > Modified: llvm/trunk/lib/VMCore/Verifier.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/VMCore/Verifier.cpp (original) > +++ llvm/trunk/lib/VMCore/Verifier.cpp Wed Feb 4 13:47:21 2009 > @@ -1004,10 +1004,9 @@ > void Verifier::visitCallInst(CallInst &CI) { > VerifyCallSite(&CI); > > - if (Function *F = CI.getCalledFunction()) { > + if (Function *F = CI.getCalledFunction()) > if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) > visitIntrinsicFunctionCall(ID, CI); > - } > } > > void Verifier::visitInvokeInst(InvokeInst &II) { > > Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) > +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Wed Feb 4 > 13:47:21 2009 > @@ -1303,7 +1303,8 @@ > > // FIXME: REMOVE OSTREAM ARGUMENT > CodeGenDAGPatterns::CodeGenDAGPatterns(RecordKeeper &R) : Records(R) { > - Intrinsics = LoadIntrinsics(Records); > + Intrinsics = LoadIntrinsics(Records, false); > + TgtIntrinsics = LoadIntrinsics(Records, true); > ParseNodeInfo(); > ParseNodeTransforms(); > ParseComplexPatterns(); > > Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h (original) > +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h Wed Feb 4 > 13:47:21 2009 > @@ -465,6 +465,7 @@ > RecordKeeper &Records; > CodeGenTarget Target; > std::vector Intrinsics; > + std::vector TgtIntrinsics; > > std::map SDNodes; > std::map > SDNodeXForms; > @@ -515,18 +516,25 @@ > const CodeGenIntrinsic &getIntrinsic(Record *R) const { > for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i) > if (Intrinsics[i].TheDef == R) return Intrinsics[i]; > + for (unsigned i = 0, e = TgtIntrinsics.size(); i != e; ++i) > + if (TgtIntrinsics[i].TheDef == R) return TgtIntrinsics[i]; > assert(0 && "Unknown intrinsic!"); > abort(); > } > > const CodeGenIntrinsic &getIntrinsicInfo(unsigned IID) const { > - assert(IID-1 < Intrinsics.size() && "Bad intrinsic ID!"); > - return Intrinsics[IID-1]; > + if (IID-1 < Intrinsics.size()) > + return Intrinsics[IID-1]; > + if (IID-Intrinsics.size()-1 < TgtIntrinsics.size()) > + return TgtIntrinsics[IID-Intrinsics.size()-1]; > + assert(0 && "Bad intrinsic ID!"); > } > > unsigned getIntrinsicID(Record *R) const { > for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i) > if (Intrinsics[i].TheDef == R) return i; > + for (unsigned i = 0, e = TgtIntrinsics.size(); i != e; ++i) > + if (TgtIntrinsics[i].TheDef == R) return i + Intrinsics.size(); > assert(0 && "Unknown intrinsic!"); > abort(); > } > > Modified: llvm/trunk/utils/TableGen/CodeGenIntrinsics.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenIntrinsics.h?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/CodeGenIntrinsics.h (original) > +++ llvm/trunk/utils/TableGen/CodeGenIntrinsics.h Wed Feb 4 > 13:47:21 2009 > @@ -80,7 +80,8 @@ > > /// LoadIntrinsics - Read all of the intrinsics defined in the > specified > /// .td file. > - std::vector LoadIntrinsics(const RecordKeeper > &RC); > + std::vector LoadIntrinsics(const RecordKeeper > &RC, > + bool TargetOnly); > } > > #endif > > Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) > +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Wed Feb 4 13:47:21 > 2009 > @@ -426,13 +426,17 @@ > // CodeGenIntrinsic Implementation > // > = > = > = > ----------------------------------------------------------------------= > ==// > > -std::vector llvm::LoadIntrinsics(const > RecordKeeper &RC) { > +std::vector llvm::LoadIntrinsics(const > RecordKeeper &RC, > + bool TargetOnly) { > std::vector I = RC.getAllDerivedDefinitions("Intrinsic"); > > std::vector Result; > > - for (unsigned i = 0, e = I.size(); i != e; ++i) > - Result.push_back(CodeGenIntrinsic(I[i])); > + for (unsigned i = 0, e = I.size(); i != e; ++i) { > + bool isTarget = I[i]->getValueAsBit("isTarget"); > + if (isTarget == TargetOnly) > + Result.push_back(CodeGenIntrinsic(I[i])); > + } > return Result; > } > > > Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Wed Feb 4 > 13:47:21 2009 > @@ -25,7 +25,10 @@ > void IntrinsicEmitter::run(std::ostream &OS) { > EmitSourceFileHeader("Intrinsic Function Source Fragment", OS); > > - std::vector Ints = LoadIntrinsics(Records); > + std::vector Ints = LoadIntrinsics(Records, > TargetOnly); > + > + if (TargetOnly && !Ints.empty()) > + TargetPrefix = Ints[0].TargetPrefix; > > // Emit the enum information. > EmitEnumInfo(Ints, OS); > @@ -91,12 +94,12 @@ > if (Ints[I->second].isOverloaded) > OS << " if (Len > " << I->first.size() > << " && !memcmp(Name, \"" << I->first << ".\", " > - << (I->first.size() + 1) << ")) return Intrinsic::" > + << (I->first.size() + 1) << ")) return " << TargetPrefix << > "Intrinsic::" > << Ints[I->second].EnumName << ";\n"; > else > OS << " if (Len == " << I->first.size() > << " && !memcmp(Name, \"" << I->first << "\", " > - << I->first.size() << ")) return Intrinsic::" > + << I->first.size() << ")) return " << TargetPrefix << > "Intrinsic::" > << Ints[I->second].EnumName << ";\n"; > } > OS << " }\n"; > @@ -351,11 +354,13 @@ > Ints[i].IS.ParamTypeDefs)].push_back(i); > > // Loop through the array, emitting one generator for each batch. > + std::string IntrinsicStr = TargetPrefix + "Intrinsic::"; > + > for (MapTy::iterator I = UniqueArgInfos.begin(), > E = UniqueArgInfos.end(); I != E; ++I) { > for (unsigned i = 0, e = I->second.size(); i != e; ++i) > - OS << " case Intrinsic::" << Ints[I->second[i]].EnumName << > ":\t\t// " > - << Ints[I->second[i]].Name << "\n"; > + OS << " case " << IntrinsicStr << Ints[I->second[i]].EnumName > + << ":\t\t// " << Ints[I->second[i]].Name << "\n"; > > const RecPair &ArgTypes = I->first; > const std::vector &RetTys = ArgTypes.first; > @@ -392,7 +397,11 @@ > EmitAttributes(const std::vector &Ints, > std::ostream &OS) { > OS << "// Add parameter attributes that are not common to all > intrinsics.\n"; > OS << "#ifdef GET_INTRINSIC_ATTRIBUTES\n"; > - OS << "AttrListPtr Intrinsic::getAttributes(ID id) {"; > + if (TargetOnly) > + OS << "static AttrListPtr getAttributes(" << TargetPrefix > + << "Intrinsic::ID id) {"; > + else > + OS << "AttrListPtr Intrinsic::getAttributes(ID id) {"; > OS << " // No intrinsic can throw exceptions.\n"; > OS << " Attributes Attr = Attribute::NoUnwind;\n"; > OS << " switch (id) {\n"; > @@ -404,7 +413,8 @@ > switch (Ints[i].ModRef) { > default: break; > case CodeGenIntrinsic::NoMem: > - OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; > + OS << " case " << TargetPrefix << "Intrinsic::" << > Ints[i].EnumName > + << ":\n"; > break; > } > } > @@ -415,7 +425,8 @@ > default: break; > case CodeGenIntrinsic::ReadArgMem: > case CodeGenIntrinsic::ReadMem: > - OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; > + OS << " case " << TargetPrefix << "Intrinsic::" << > Ints[i].EnumName > + << ":\n"; > break; > } > } > @@ -431,7 +442,8 @@ > for (unsigned i = 0, e = Ints.size(); i != e; ++i) { > if (Ints[i].ArgumentAttributes.empty()) continue; > > - OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; > + OS << " case " << TargetPrefix << "Intrinsic::" << > Ints[i].EnumName > + << ":\n"; > > std::vector > > ArgAttrs = > Ints[i].ArgumentAttributes; > @@ -495,7 +507,7 @@ > typedef std::map::const_iterator > StrMapIterator; > static void EmitBuiltinComparisons(StrMapIterator Start, > StrMapIterator End, > unsigned CharStart, unsigned > Indent, > - std::ostream &OS) { > + std::string TargetPrefix, > std::ostream &OS) { > if (Start == End) return; // empty range. > > // Determine what, if anything, is the same about all these strings. > @@ -522,7 +534,8 @@ > OS << CommonString.size() - CharStart << "))\n"; > ++Indent; > } > - OS << std::string(Indent*2, ' ') << "IntrinsicID = Intrinsic::"; > + OS << std::string(Indent*2, ' ') << "IntrinsicID = " << > TargetPrefix > + << "Intrinsic::"; > OS << Start->second << ";\n"; > return; > } > @@ -535,7 +548,8 @@ > OS << ", \"" << (CommonString.c_str()+CharStart) << "\", "; > OS << CommonString.size()-CharStart << ")) {\n"; > > - EmitBuiltinComparisons(Start, End, CommonString.size(), Indent > +1, OS); > + EmitBuiltinComparisons(Start, End, CommonString.size(), Indent+1, > + TargetPrefix, OS); > OS << std::string(Indent*2, ' ') << "}\n"; > return; > } > @@ -556,7 +570,7 @@ > for (++NextChar; NextChar != End && NextChar->first[CharStart] > == ThisChar; > ++NextChar) > /*empty*/; > - EmitBuiltinComparisons(I, NextChar, CharStart+1, Indent+1, OS); > + EmitBuiltinComparisons(I, NextChar, CharStart+1, Indent+1, > TargetPrefix,OS); > OS << std::string(Indent*2, ' ') << " break;\n"; > I = NextChar; > } > @@ -566,6 +580,7 @@ > /// EmitTargetBuiltins - All of the builtins in the specified map > are for the > /// same target, and we already checked it. > static void EmitTargetBuiltins(const std::map std::string> &BIM, > + const std::string &TargetPrefix, > std::ostream &OS) { > // Rearrange the builtins by length. > std::vector > BuiltinsByLen; > @@ -584,7 +599,7 @@ > if (BuiltinsByLen[i].empty()) continue; > OS << " case " << i << ":\n"; > EmitBuiltinComparisons(BuiltinsByLen[i].begin(), > BuiltinsByLen[i].end(), > - 0, 3, OS); > + 0, 3, TargetPrefix, OS); > OS << " break;\n"; > } > OS << " }\n"; > @@ -613,7 +628,22 @@ > OS << "// in as BuiltinName, and a target prefix (e.g. 'ppc') is > passed\n"; > OS << "// in as TargetPrefix. The result is assigned to > 'IntrinsicID'.\n"; > OS << "#ifdef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN\n"; > - OS << " IntrinsicID = Intrinsic::not_intrinsic;\n"; > + > + if (TargetOnly) { > + OS << "static " << TargetPrefix << "Intrinsic::ID " > + << "getIntrinsicForGCCBuiltin(const char " > + << "*TargetPrefix, const char *BuiltinName) {\n"; > + OS << " " << TargetPrefix << "Intrinsic::ID IntrinsicID = "; > + } else { > + OS << "Intrinsic::ID Intrinsic::getIntrinsicForGCCBuiltin(const > char " > + << "*TargetPrefix, const char *BuiltinName) {\n"; > + OS << " Intrinsic::ID IntrinsicID = "; > + } > + > + if (TargetOnly) > + OS << "(" << TargetPrefix<< "Intrinsic::ID)"; > + > + OS << "Intrinsic::not_intrinsic;\n"; > > // Note: this could emit significantly better code if we cared. > for (BIMTy::iterator I = BuiltinMap.begin(), E = > BuiltinMap.end();I != E;++I){ > @@ -625,8 +655,10 @@ > OS << "{\n"; > > // Emit the comparisons for this target prefix. > - EmitTargetBuiltins(I->second, OS); > + EmitTargetBuiltins(I->second, TargetPrefix, OS); > OS << " }\n"; > } > + OS << " return IntrinsicID;\n"; > + OS << "}\n"; > OS << "#endif\n\n"; > } > > Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.h?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/IntrinsicEmitter.h (original) > +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.h Wed Feb 4 13:47:21 > 2009 > @@ -20,9 +20,12 @@ > namespace llvm { > class IntrinsicEmitter : public TableGenBackend { > RecordKeeper &Records; > + bool TargetOnly; > + std::string TargetPrefix; > > public: > - IntrinsicEmitter(RecordKeeper &R) : Records(R) {} > + IntrinsicEmitter(RecordKeeper &R, bool T = false) > + : Records(R), TargetOnly(T) {} > > void run(std::ostream &OS); > > > Modified: llvm/trunk/utils/TableGen/TableGen.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=63765&r1=63764&r2=63765&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/TableGen.cpp (original) > +++ llvm/trunk/utils/TableGen/TableGen.cpp Wed Feb 4 13:47:21 2009 > @@ -49,6 +49,7 @@ > GenFastISel, > GenSubtarget, > GenIntrinsic, > + GenTgtIntrinsic, > GenLLVMCConf, > PrintEnums > }; > @@ -82,6 +83,8 @@ > "Generate subtarget enumerations"), > clEnumValN(GenIntrinsic, "gen-intrinsic", > "Generate intrinsic information"), > + clEnumValN(GenTgtIntrinsic, "gen-tgt-intrinsic", > + "Generate target intrinsic > information"), > clEnumValN(GenLLVMCConf, "gen-llvmc", > "Generate LLVMC configuration > library"), > clEnumValN(PrintEnums, "print-enums", > @@ -190,6 +193,9 @@ > case GenIntrinsic: > IntrinsicEmitter(Records).run(*Out); > break; > + case GenTgtIntrinsic: > + IntrinsicEmitter(Records, true).run(*Out); > + break; > case GenLLVMCConf: > LLVMCConfigurationEmitter(Records).run(*Out); > break; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gohman at apple.com Wed Feb 4 16:14:20 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 04 Feb 2009 22:14:20 -0000 Subject: [llvm-commits] [test-suite] r63783 - /test-suite/trunk/External/SPEC/CINT2006/473.astar/Makefile Message-ID: <200902042214.n14MEKCM020223@zion.cs.uiuc.edu> Author: djg Date: Wed Feb 4 16:14:20 2009 New Revision: 63783 URL: http://llvm.org/viewvc/llvm-project?rev=63783&view=rev Log: Fix 473.astar's Makefile to include Makefile.spec2006 before using RUN_TYPE. This unbreaks 473.astar. Modified: test-suite/trunk/External/SPEC/CINT2006/473.astar/Makefile Modified: test-suite/trunk/External/SPEC/CINT2006/473.astar/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2006/473.astar/Makefile?rev=63783&r1=63782&r2=63783&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT2006/473.astar/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT2006/473.astar/Makefile Wed Feb 4 16:14:20 2009 @@ -8,6 +8,8 @@ FP_TOLERANCE = 0.001 +include ../../Makefile.spec2006 + ifeq ($(ENDIAN),big) CPPFLAGS += -DSPEC_CPU_BIG_ENDIAN else @@ -24,6 +26,3 @@ LDFLAGS = -lstdc++ -lm LIBS = -lm - -include ../../Makefile.spec2006 - From isanbard at gmail.com Wed Feb 4 16:16:36 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 4 Feb 2009 14:16:36 -0800 Subject: [llvm-commits] [llvm] r63765 - in /llvm/trunk: ./ include/llvm/ include/llvm/Target/ lib/AsmParser/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/VMCore/ utils/TableGen/ In-Reply-To: <7E9D07B2-3D42-43AE-9B0E-AF4DFB602AC7@apple.com> References: <200902041947.n14JlMdj015607@zion.cs.uiuc.edu> <7E9D07B2-3D42-43AE-9B0E-AF4DFB602AC7@apple.com> Message-ID: <16e5fdf90902041416p3949190agfae8510008a17ba3@mail.gmail.com> Here's the error message: g++ -m32 -c -g -DIN_GCC -W -Wall -Wwrite-strings -Wmissing-format-attribute -mdynamic-no-pic -DHAVE_CONFIG_H -Wno-unused -DTARGET_NAME=\"i686-apple-darwin9\" -DNDEBUG -I. -I. -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/. -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/../include -I./../intl -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/../libcpp/include -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore.roots/llvmCore~dst/Developer/usr/local/include -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore.roots/llvmCore~obj/src/include -DENABLE_LLVM -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore.roots/llvmCore~dst/Developer/usr/local/include -D_DEBUG -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -DLLVM_VERSION_INFO='"9999"' -I. -I. -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/. -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/../include -I./../intl -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/../libcpp/include -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore.roots/llvmCore~dst/Developer/usr/local/include -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore.roots/llvmCore~obj/src/include /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/llvm-debug.cpp -o llvm-debug.o /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore.roots/llvmCore~dst/Developer/usr/local/include/llvm/Intrinsics.gen: In member function 'bool TreeToLLVM::EmitBuiltinCall(tree_node*, tree_node*, const MemRef*, llvm::Value*&)': /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore.roots/llvmCore~dst/Developer/usr/local/include/llvm/Intrinsics.gen:5360: error: a function-definition is not allowed here before '{' token gcc -m32 -c -g -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -Wmissing-format-attribute -mdynamic-no-pic -DHAVE_CONFIG_H -I. -I. -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/. -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/../include -I./../intl -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/../libcpp/include -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore.roots/llvmCore~dst/Developer/usr/local/include -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore.roots/llvmCore~obj/src/include -DENABLE_LLVM -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore.roots/llvmCore~dst/Developer/usr/local/include -D_DEBUG -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -DLLVM_VERSION_INFO='"9999"' \ /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/config/i386/i386.c -o i386.o make[4]: *** [llvm-convert.o] Error 1 make[4]: *** Waiting for unfinished jobs.... -bw On Wed, Feb 4, 2009 at 1:48 PM, Dale Johannesen wrote: > This seems to have broken both llvm-gcc and clang. Could you look? > > On Feb 4, 2009, at 11:47 AMPST, Nate Begeman wrote: > >> Author: sampo >> Date: Wed Feb 4 13:47:21 2009 >> New Revision: 63765 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=63765&view=rev >> Log: >> New feature: add support for target intrinsics being defined in the >> target directories themselves. This also means that VMCore no longer >> needs to know about every target's list of intrinsics. Future work >> will include converting the PowerPC target to this interface as an >> example implementation. >> >> Added: >> llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h >> llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp >> Modified: >> llvm/trunk/Makefile.rules >> llvm/trunk/include/llvm/Function.h >> llvm/trunk/include/llvm/Intrinsics.h >> llvm/trunk/include/llvm/Intrinsics.td >> llvm/trunk/include/llvm/Module.h >> llvm/trunk/include/llvm/Target/TargetMachine.h >> llvm/trunk/lib/AsmParser/LLParser.cpp >> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp >> llvm/trunk/lib/VMCore/AutoUpgrade.cpp >> llvm/trunk/lib/VMCore/Function.cpp >> llvm/trunk/lib/VMCore/Module.cpp >> llvm/trunk/lib/VMCore/Verifier.cpp >> llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp >> llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h >> llvm/trunk/utils/TableGen/CodeGenIntrinsics.h >> llvm/trunk/utils/TableGen/CodeGenTarget.cpp >> llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp >> llvm/trunk/utils/TableGen/IntrinsicEmitter.h >> llvm/trunk/utils/TableGen/TableGen.cpp >> >> Modified: llvm/trunk/Makefile.rules >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/Makefile.rules (original) >> +++ llvm/trunk/Makefile.rules Wed Feb 4 13:47:21 2009 >> @@ -1346,6 +1346,11 @@ >> $(Echo) "Building $(> $(Verb) $(TableGen) -gen-callingconv -o $(call SYSPATH, $@) $< >> >> +$(TARGET:%=$(ObjDir)/%GenIntrinsics.inc.tmp): \ >> +$(ObjDir)/%GenIntrinsics.inc.tmp : Intrinsics%.td $(ObjDir)/.dir >> + $(Echo) "Building $(> + $(Verb) $(TableGen) -gen-tgt-intrinsic -o $(call SYSPATH, $@) $< >> + >> clean-local:: >> -$(Verb) $(RM) -f $(INCFiles) >> >> >> Modified: llvm/trunk/include/llvm/Function.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Function.h?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/include/llvm/Function.h (original) >> +++ llvm/trunk/include/llvm/Function.h Wed Feb 4 13:47:21 2009 >> @@ -129,7 +129,7 @@ >> /// The particular intrinsic functions which correspond to this >> value are >> /// defined in llvm/Intrinsics.h. >> /// >> - unsigned getIntrinsicID(bool noAssert = false) const; >> + unsigned getIntrinsicID() const; >> bool isIntrinsic() const { return getIntrinsicID() != 0; } >> >> /// getCallingConv()/setCallingConv(uint) - These method get and >> set the >> >> Modified: llvm/trunk/include/llvm/Intrinsics.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.h?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/include/llvm/Intrinsics.h (original) >> +++ llvm/trunk/include/llvm/Intrinsics.h Wed Feb 4 13:47:21 2009 >> @@ -63,6 +63,9 @@ >> /// intrinsic. >> Function *getDeclaration(Module *M, ID id, const Type **Tys = 0, >> unsigned numTys = 0); >> + >> + /// Map a GCC builtin name to an intrinsic ID. >> + ID getIntrinsicForGCCBuiltin(const char *Prefix, const char >> *BuiltinName); >> >> } // End Intrinsic namespace >> >> >> Modified: llvm/trunk/include/llvm/Intrinsics.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/include/llvm/Intrinsics.td (original) >> +++ llvm/trunk/include/llvm/Intrinsics.td Wed Feb 4 13:47:21 2009 >> @@ -144,6 +144,8 @@ >> list RetTypes = ret_types; >> list ParamTypes = param_types; >> list Properties = properties; >> + >> + bit isTarget = 0; >> } >> >> /// GCCBuiltin - If this intrinsic exactly corresponds to a GCC >> builtin, this >> >> Modified: llvm/trunk/include/llvm/Module.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Module.h?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/include/llvm/Module.h (original) >> +++ llvm/trunk/include/llvm/Module.h Wed Feb 4 13:47:21 2009 >> @@ -213,6 +213,10 @@ >> Constant *getOrInsertFunction(const std::string &Name, const Type >> *RetTy, ...) >> END_WITH_NULL; >> >> + Constant *getOrInsertTargetIntrinsic(const std::string &Name, >> + const FunctionType *Ty, >> + AttrListPtr AttributeList); >> + >> /// getFunction - Look up the specified function in the module >> symbol table. >> /// If it does not exist, return null. >> Function *getFunction(const std::string &Name) const; >> >> Added: llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h?rev=63765&view=auto >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h (added) >> +++ llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h Wed Feb 4 >> 13:47:21 2009 >> @@ -0,0 +1,48 @@ >> +//===-- llvm/Target/TargetIntrinsicInfo.h - Instruction Info ----*- >> C++ -*-===// >> +// >> +// The LLVM Compiler Infrastructure >> +// >> +// This file is distributed under the University of Illinois Open >> Source >> +// License. See LICENSE.TXT for details. >> +// >> +// >> = >> = >> = >> ----------------------------------------------------------------------= >> ==// >> +// >> +// This file describes the target intrinsic instructions to the >> code generator. >> +// >> +// >> = >> = >> = >> ----------------------------------------------------------------------= >> ==// >> + >> +#ifndef LLVM_TARGET_TARGETINTRINSICINFO_H >> +#define LLVM_TARGET_TARGETINTRINSICINFO_H >> + >> +namespace llvm { >> + >> +class Function; >> +class Module; >> + >> + >> //--------------------------------------------------------------------------- >> +/// >> +/// TargetIntrinsicInfo - Interface to description of machine >> instruction set >> +/// >> +class TargetIntrinsicInfo { >> + >> + const char **Intrinsics; // Raw array to allow >> static init'n >> + unsigned NumIntrinsics; // Number of entries in >> the desc array >> + >> + TargetIntrinsicInfo(const TargetIntrinsicInfo &); // DO NOT >> IMPLEMENT >> + void operator=(const TargetIntrinsicInfo &); // DO NOT IMPLEMENT >> +public: >> + TargetIntrinsicInfo(const char **desc, unsigned num); >> + virtual ~TargetIntrinsicInfo(); >> + >> + unsigned getNumIntrinsics() const { return NumIntrinsics; } >> + >> + virtual Function *getDeclaration(Module *M, const char >> *BuiltinName) const { >> + return 0; >> + } >> + >> + virtual unsigned getIntrinsicID(Function *F) const { return 0; } >> +}; >> + >> +} // End llvm namespace >> + >> +#endif >> >> Modified: llvm/trunk/include/llvm/Target/TargetMachine.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/include/llvm/Target/TargetMachine.h (original) >> +++ llvm/trunk/include/llvm/Target/TargetMachine.h Wed Feb 4 >> 13:47:21 2009 >> @@ -23,6 +23,7 @@ >> class TargetData; >> class TargetSubtarget; >> class TargetInstrInfo; >> +class TargetIntrinsicInfo; >> class TargetJITInfo; >> class TargetLowering; >> class TargetFrameInfo; >> @@ -118,7 +119,6 @@ >> virtual TargetLowering *getTargetLowering() const >> { return 0; } >> virtual const TargetData *getTargetData() const >> { return 0; } >> >> - >> /// getTargetAsmInfo - Return target specific asm information. >> /// >> const TargetAsmInfo *getTargetAsmInfo() const { >> @@ -141,6 +141,11 @@ >> /// details of graph coloring register allocation removed from it. >> /// >> virtual const TargetRegisterInfo *getRegisterInfo() const { return >> 0; } >> + >> + /// getIntrinsicInfo - If intrinsic information is available, >> return it. If >> + /// not, return null. >> + /// >> + virtual const TargetIntrinsicInfo *getIntrinsicInfo() const >> { return 0; } >> >> /// getJITInfo - If this target supports a JIT, return information >> for it, >> /// otherwise return null. >> >> Modified: llvm/trunk/lib/AsmParser/LLParser.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) >> +++ llvm/trunk/lib/AsmParser/LLParser.cpp Wed Feb 4 13:47:21 2009 >> @@ -2949,15 +2949,6 @@ >> Value *Callee; >> if (ConvertValIDToValue(PFTy, CalleeID, Callee, PFS)) return true; >> >> - // Check for call to invalid intrinsic to avoid crashing later. >> - if (Function *F = dyn_cast(Callee)) { >> - if (F->hasName() && F->getNameLen() >= 5 && >> - !strncmp(F->getValueName()->getKeyData(), "llvm.", 5) && >> - !F->getIntrinsicID(true)) >> - return Error(CallLoc, "Call to invalid LLVM intrinsic >> function '" + >> - F->getNameStr() + "'"); >> - } >> - >> // FIXME: In LLVM 3.0, stop accepting zext, sext and inreg as >> optional >> // function attributes. >> unsigned ObsoleteFuncAttrs = Attribute::ZExt|Attribute::SExt| >> Attribute::InReg; >> >> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp >> (original) >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Wed >> Feb 4 13:47:21 2009 >> @@ -43,6 +43,7 @@ >> #include "llvm/Target/TargetData.h" >> #include "llvm/Target/TargetFrameInfo.h" >> #include "llvm/Target/TargetInstrInfo.h" >> +#include "llvm/Target/TargetIntrinsicInfo.h" >> #include "llvm/Target/TargetLowering.h" >> #include "llvm/Target/TargetMachine.h" >> #include "llvm/Target/TargetOptions.h" >> @@ -4426,6 +4427,14 @@ >> const char *RenameFn = 0; >> if (Function *F = I.getCalledFunction()) { >> if (F->isDeclaration()) { >> + const TargetIntrinsicInfo *II = >> TLI.getTargetMachine().getIntrinsicInfo(); >> + if (II) { >> + if (unsigned IID = II->getIntrinsicID(F)) { >> + RenameFn = visitIntrinsicCall(I, IID); >> + if (!RenameFn) >> + return; >> + } >> + } >> if (unsigned IID = F->getIntrinsicID()) { >> RenameFn = visitIntrinsicCall(I, IID); >> if (!RenameFn) >> >> Added: llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp?rev=63765&view=auto >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp (added) >> +++ llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp Wed Feb 4 >> 13:47:21 2009 >> @@ -0,0 +1,22 @@ >> +//===-- TargetIntrinsicInfo.cpp - Target Instruction Information >> ----------===// >> +// >> +// The LLVM Compiler Infrastructure >> +// >> +// This file is distributed under the University of Illinois Open >> Source >> +// License. See LICENSE.TXT for details. >> +// >> +// >> = >> = >> = >> ----------------------------------------------------------------------= >> ==// >> +// >> +// This file implements the TargetIntrinsicInfo class. >> +// >> +// >> = >> = >> = >> ----------------------------------------------------------------------= >> ==// >> + >> +#include "llvm/Target/TargetIntrinsicInfo.h" >> +using namespace llvm; >> + >> +TargetIntrinsicInfo::TargetIntrinsicInfo(const char **desc, >> unsigned count) >> + : Intrinsics(desc), NumIntrinsics(count) { >> +} >> + >> +TargetIntrinsicInfo::~TargetIntrinsicInfo() { >> +} >> >> Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original) >> +++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Wed Feb 4 13:47:21 2009 >> @@ -217,7 +217,7 @@ >> // Upgrade intrinsic attributes. This does not change the function. >> if (NewFn) >> F = NewFn; >> - if (unsigned id = F->getIntrinsicID(true)) >> + if (unsigned id = F->getIntrinsicID()) >> F->setAttributes(Intrinsic::getAttributes((Intrinsic::ID)id)); >> return Upgraded; >> } >> >> Modified: llvm/trunk/lib/VMCore/Function.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Function.cpp?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/lib/VMCore/Function.cpp (original) >> +++ llvm/trunk/lib/VMCore/Function.cpp Wed Feb 4 13:47:21 2009 >> @@ -175,7 +175,7 @@ >> ParentModule->getFunctionList().push_back(this); >> >> // Ensure intrinsics have the right parameter attributes. >> - if (unsigned IID = getIntrinsicID(true)) >> + if (unsigned IID = getIntrinsicID()) >> setAttributes(Intrinsic::getAttributes(Intrinsic::ID(IID))); >> >> } >> @@ -304,7 +304,7 @@ >> /// particular intrinsic functions which correspond to this value >> are defined in >> /// llvm/Intrinsics.h. >> /// >> -unsigned Function::getIntrinsicID(bool noAssert) const { >> +unsigned Function::getIntrinsicID() const { >> const ValueName *ValName = this->getValueName(); >> if (!ValName) >> return 0; >> @@ -315,12 +315,9 @@ >> || Name[2] != 'v' || Name[3] != 'm') >> return 0; // All intrinsics start with 'llvm.' >> >> - assert((Len != 5 || noAssert) && "'llvm.' is an invalid intrinsic >> name!"); >> - >> #define GET_FUNCTION_RECOGNIZER >> #include "llvm/Intrinsics.gen" >> #undef GET_FUNCTION_RECOGNIZER >> - assert(noAssert && "Invalid LLVM intrinsic name"); >> return 0; >> } >> >> @@ -373,4 +370,9 @@ >> getType(id, Tys, numTys))); >> } >> >> +// This defines the "Intrinsic::getIntrinsicForGCCBuiltin()" method. >> +#define GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN >> +#include "llvm/Intrinsics.gen" >> +#undef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN >> + >> // vim: sw=2 ai >> >> Modified: llvm/trunk/lib/VMCore/Module.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Module.cpp?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/lib/VMCore/Module.cpp (original) >> +++ llvm/trunk/lib/VMCore/Module.cpp Wed Feb 4 13:47:21 2009 >> @@ -171,6 +171,25 @@ >> return F; >> } >> >> +Constant *Module::getOrInsertTargetIntrinsic(const std::string &Name, >> + const FunctionType *Ty, >> + AttrListPtr >> AttributeList) { >> + ValueSymbolTable &SymTab = getValueSymbolTable(); >> + >> + // See if we have a definition for the specified function already. >> + GlobalValue *F = >> dyn_cast_or_null(SymTab.lookup(Name)); >> + if (F == 0) { >> + // Nope, add it >> + Function *New = Function::Create(Ty, >> GlobalVariable::ExternalLinkage, Name); >> + New->setAttributes(AttributeList); >> + FunctionList.push_back(New); >> + return New; // Return the new prototype. >> + } >> + >> + // Otherwise, we just found the existing function or a prototype. >> + return F; >> +} >> + >> Constant *Module::getOrInsertFunction(const std::string &Name, >> const FunctionType *Ty) { >> AttrListPtr AttributeList = AttrListPtr::get((AttributeWithIndex >> *)0, 0); >> >> Modified: llvm/trunk/lib/VMCore/Verifier.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/lib/VMCore/Verifier.cpp (original) >> +++ llvm/trunk/lib/VMCore/Verifier.cpp Wed Feb 4 13:47:21 2009 >> @@ -1004,10 +1004,9 @@ >> void Verifier::visitCallInst(CallInst &CI) { >> VerifyCallSite(&CI); >> >> - if (Function *F = CI.getCalledFunction()) { >> + if (Function *F = CI.getCalledFunction()) >> if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) >> visitIntrinsicFunctionCall(ID, CI); >> - } >> } >> >> void Verifier::visitInvokeInst(InvokeInst &II) { >> >> Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) >> +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Wed Feb 4 >> 13:47:21 2009 >> @@ -1303,7 +1303,8 @@ >> >> // FIXME: REMOVE OSTREAM ARGUMENT >> CodeGenDAGPatterns::CodeGenDAGPatterns(RecordKeeper &R) : Records(R) { >> - Intrinsics = LoadIntrinsics(Records); >> + Intrinsics = LoadIntrinsics(Records, false); >> + TgtIntrinsics = LoadIntrinsics(Records, true); >> ParseNodeInfo(); >> ParseNodeTransforms(); >> ParseComplexPatterns(); >> >> Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h (original) >> +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h Wed Feb 4 >> 13:47:21 2009 >> @@ -465,6 +465,7 @@ >> RecordKeeper &Records; >> CodeGenTarget Target; >> std::vector Intrinsics; >> + std::vector TgtIntrinsics; >> >> std::map SDNodes; >> std::map > SDNodeXForms; >> @@ -515,18 +516,25 @@ >> const CodeGenIntrinsic &getIntrinsic(Record *R) const { >> for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i) >> if (Intrinsics[i].TheDef == R) return Intrinsics[i]; >> + for (unsigned i = 0, e = TgtIntrinsics.size(); i != e; ++i) >> + if (TgtIntrinsics[i].TheDef == R) return TgtIntrinsics[i]; >> assert(0 && "Unknown intrinsic!"); >> abort(); >> } >> >> const CodeGenIntrinsic &getIntrinsicInfo(unsigned IID) const { >> - assert(IID-1 < Intrinsics.size() && "Bad intrinsic ID!"); >> - return Intrinsics[IID-1]; >> + if (IID-1 < Intrinsics.size()) >> + return Intrinsics[IID-1]; >> + if (IID-Intrinsics.size()-1 < TgtIntrinsics.size()) >> + return TgtIntrinsics[IID-Intrinsics.size()-1]; >> + assert(0 && "Bad intrinsic ID!"); >> } >> >> unsigned getIntrinsicID(Record *R) const { >> for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i) >> if (Intrinsics[i].TheDef == R) return i; >> + for (unsigned i = 0, e = TgtIntrinsics.size(); i != e; ++i) >> + if (TgtIntrinsics[i].TheDef == R) return i + Intrinsics.size(); >> assert(0 && "Unknown intrinsic!"); >> abort(); >> } >> >> Modified: llvm/trunk/utils/TableGen/CodeGenIntrinsics.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenIntrinsics.h?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/utils/TableGen/CodeGenIntrinsics.h (original) >> +++ llvm/trunk/utils/TableGen/CodeGenIntrinsics.h Wed Feb 4 >> 13:47:21 2009 >> @@ -80,7 +80,8 @@ >> >> /// LoadIntrinsics - Read all of the intrinsics defined in the >> specified >> /// .td file. >> - std::vector LoadIntrinsics(const RecordKeeper >> &RC); >> + std::vector LoadIntrinsics(const RecordKeeper >> &RC, >> + bool TargetOnly); >> } >> >> #endif >> >> Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) >> +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Wed Feb 4 13:47:21 >> 2009 >> @@ -426,13 +426,17 @@ >> // CodeGenIntrinsic Implementation >> // >> = >> = >> = >> ----------------------------------------------------------------------= >> ==// >> >> -std::vector llvm::LoadIntrinsics(const >> RecordKeeper &RC) { >> +std::vector llvm::LoadIntrinsics(const >> RecordKeeper &RC, >> + bool TargetOnly) { >> std::vector I = RC.getAllDerivedDefinitions("Intrinsic"); >> >> std::vector Result; >> >> - for (unsigned i = 0, e = I.size(); i != e; ++i) >> - Result.push_back(CodeGenIntrinsic(I[i])); >> + for (unsigned i = 0, e = I.size(); i != e; ++i) { >> + bool isTarget = I[i]->getValueAsBit("isTarget"); >> + if (isTarget == TargetOnly) >> + Result.push_back(CodeGenIntrinsic(I[i])); >> + } >> return Result; >> } >> >> >> Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) >> +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Wed Feb 4 >> 13:47:21 2009 >> @@ -25,7 +25,10 @@ >> void IntrinsicEmitter::run(std::ostream &OS) { >> EmitSourceFileHeader("Intrinsic Function Source Fragment", OS); >> >> - std::vector Ints = LoadIntrinsics(Records); >> + std::vector Ints = LoadIntrinsics(Records, >> TargetOnly); >> + >> + if (TargetOnly && !Ints.empty()) >> + TargetPrefix = Ints[0].TargetPrefix; >> >> // Emit the enum information. >> EmitEnumInfo(Ints, OS); >> @@ -91,12 +94,12 @@ >> if (Ints[I->second].isOverloaded) >> OS << " if (Len > " << I->first.size() >> << " && !memcmp(Name, \"" << I->first << ".\", " >> - << (I->first.size() + 1) << ")) return Intrinsic::" >> + << (I->first.size() + 1) << ")) return " << TargetPrefix << >> "Intrinsic::" >> << Ints[I->second].EnumName << ";\n"; >> else >> OS << " if (Len == " << I->first.size() >> << " && !memcmp(Name, \"" << I->first << "\", " >> - << I->first.size() << ")) return Intrinsic::" >> + << I->first.size() << ")) return " << TargetPrefix << >> "Intrinsic::" >> << Ints[I->second].EnumName << ";\n"; >> } >> OS << " }\n"; >> @@ -351,11 +354,13 @@ >> Ints[i].IS.ParamTypeDefs)].push_back(i); >> >> // Loop through the array, emitting one generator for each batch. >> + std::string IntrinsicStr = TargetPrefix + "Intrinsic::"; >> + >> for (MapTy::iterator I = UniqueArgInfos.begin(), >> E = UniqueArgInfos.end(); I != E; ++I) { >> for (unsigned i = 0, e = I->second.size(); i != e; ++i) >> - OS << " case Intrinsic::" << Ints[I->second[i]].EnumName << >> ":\t\t// " >> - << Ints[I->second[i]].Name << "\n"; >> + OS << " case " << IntrinsicStr << Ints[I->second[i]].EnumName >> + << ":\t\t// " << Ints[I->second[i]].Name << "\n"; >> >> const RecPair &ArgTypes = I->first; >> const std::vector &RetTys = ArgTypes.first; >> @@ -392,7 +397,11 @@ >> EmitAttributes(const std::vector &Ints, >> std::ostream &OS) { >> OS << "// Add parameter attributes that are not common to all >> intrinsics.\n"; >> OS << "#ifdef GET_INTRINSIC_ATTRIBUTES\n"; >> - OS << "AttrListPtr Intrinsic::getAttributes(ID id) {"; >> + if (TargetOnly) >> + OS << "static AttrListPtr getAttributes(" << TargetPrefix >> + << "Intrinsic::ID id) {"; >> + else >> + OS << "AttrListPtr Intrinsic::getAttributes(ID id) {"; >> OS << " // No intrinsic can throw exceptions.\n"; >> OS << " Attributes Attr = Attribute::NoUnwind;\n"; >> OS << " switch (id) {\n"; >> @@ -404,7 +413,8 @@ >> switch (Ints[i].ModRef) { >> default: break; >> case CodeGenIntrinsic::NoMem: >> - OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; >> + OS << " case " << TargetPrefix << "Intrinsic::" << >> Ints[i].EnumName >> + << ":\n"; >> break; >> } >> } >> @@ -415,7 +425,8 @@ >> default: break; >> case CodeGenIntrinsic::ReadArgMem: >> case CodeGenIntrinsic::ReadMem: >> - OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; >> + OS << " case " << TargetPrefix << "Intrinsic::" << >> Ints[i].EnumName >> + << ":\n"; >> break; >> } >> } >> @@ -431,7 +442,8 @@ >> for (unsigned i = 0, e = Ints.size(); i != e; ++i) { >> if (Ints[i].ArgumentAttributes.empty()) continue; >> >> - OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; >> + OS << " case " << TargetPrefix << "Intrinsic::" << >> Ints[i].EnumName >> + << ":\n"; >> >> std::vector >> > ArgAttrs = >> Ints[i].ArgumentAttributes; >> @@ -495,7 +507,7 @@ >> typedef std::map::const_iterator >> StrMapIterator; >> static void EmitBuiltinComparisons(StrMapIterator Start, >> StrMapIterator End, >> unsigned CharStart, unsigned >> Indent, >> - std::ostream &OS) { >> + std::string TargetPrefix, >> std::ostream &OS) { >> if (Start == End) return; // empty range. >> >> // Determine what, if anything, is the same about all these strings. >> @@ -522,7 +534,8 @@ >> OS << CommonString.size() - CharStart << "))\n"; >> ++Indent; >> } >> - OS << std::string(Indent*2, ' ') << "IntrinsicID = Intrinsic::"; >> + OS << std::string(Indent*2, ' ') << "IntrinsicID = " << >> TargetPrefix >> + << "Intrinsic::"; >> OS << Start->second << ";\n"; >> return; >> } >> @@ -535,7 +548,8 @@ >> OS << ", \"" << (CommonString.c_str()+CharStart) << "\", "; >> OS << CommonString.size()-CharStart << ")) {\n"; >> >> - EmitBuiltinComparisons(Start, End, CommonString.size(), Indent >> +1, OS); >> + EmitBuiltinComparisons(Start, End, CommonString.size(), Indent+1, >> + TargetPrefix, OS); >> OS << std::string(Indent*2, ' ') << "}\n"; >> return; >> } >> @@ -556,7 +570,7 @@ >> for (++NextChar; NextChar != End && NextChar->first[CharStart] >> == ThisChar; >> ++NextChar) >> /*empty*/; >> - EmitBuiltinComparisons(I, NextChar, CharStart+1, Indent+1, OS); >> + EmitBuiltinComparisons(I, NextChar, CharStart+1, Indent+1, >> TargetPrefix,OS); >> OS << std::string(Indent*2, ' ') << " break;\n"; >> I = NextChar; >> } >> @@ -566,6 +580,7 @@ >> /// EmitTargetBuiltins - All of the builtins in the specified map >> are for the >> /// same target, and we already checked it. >> static void EmitTargetBuiltins(const std::map> std::string> &BIM, >> + const std::string &TargetPrefix, >> std::ostream &OS) { >> // Rearrange the builtins by length. >> std::vector > BuiltinsByLen; >> @@ -584,7 +599,7 @@ >> if (BuiltinsByLen[i].empty()) continue; >> OS << " case " << i << ":\n"; >> EmitBuiltinComparisons(BuiltinsByLen[i].begin(), >> BuiltinsByLen[i].end(), >> - 0, 3, OS); >> + 0, 3, TargetPrefix, OS); >> OS << " break;\n"; >> } >> OS << " }\n"; >> @@ -613,7 +628,22 @@ >> OS << "// in as BuiltinName, and a target prefix (e.g. 'ppc') is >> passed\n"; >> OS << "// in as TargetPrefix. The result is assigned to >> 'IntrinsicID'.\n"; >> OS << "#ifdef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN\n"; >> - OS << " IntrinsicID = Intrinsic::not_intrinsic;\n"; >> + >> + if (TargetOnly) { >> + OS << "static " << TargetPrefix << "Intrinsic::ID " >> + << "getIntrinsicForGCCBuiltin(const char " >> + << "*TargetPrefix, const char *BuiltinName) {\n"; >> + OS << " " << TargetPrefix << "Intrinsic::ID IntrinsicID = "; >> + } else { >> + OS << "Intrinsic::ID Intrinsic::getIntrinsicForGCCBuiltin(const >> char " >> + << "*TargetPrefix, const char *BuiltinName) {\n"; >> + OS << " Intrinsic::ID IntrinsicID = "; >> + } >> + >> + if (TargetOnly) >> + OS << "(" << TargetPrefix<< "Intrinsic::ID)"; >> + >> + OS << "Intrinsic::not_intrinsic;\n"; >> >> // Note: this could emit significantly better code if we cared. >> for (BIMTy::iterator I = BuiltinMap.begin(), E = >> BuiltinMap.end();I != E;++I){ >> @@ -625,8 +655,10 @@ >> OS << "{\n"; >> >> // Emit the comparisons for this target prefix. >> - EmitTargetBuiltins(I->second, OS); >> + EmitTargetBuiltins(I->second, TargetPrefix, OS); >> OS << " }\n"; >> } >> + OS << " return IntrinsicID;\n"; >> + OS << "}\n"; >> OS << "#endif\n\n"; >> } >> >> Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.h?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/utils/TableGen/IntrinsicEmitter.h (original) >> +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.h Wed Feb 4 13:47:21 >> 2009 >> @@ -20,9 +20,12 @@ >> namespace llvm { >> class IntrinsicEmitter : public TableGenBackend { >> RecordKeeper &Records; >> + bool TargetOnly; >> + std::string TargetPrefix; >> >> public: >> - IntrinsicEmitter(RecordKeeper &R) : Records(R) {} >> + IntrinsicEmitter(RecordKeeper &R, bool T = false) >> + : Records(R), TargetOnly(T) {} >> >> void run(std::ostream &OS); >> >> >> Modified: llvm/trunk/utils/TableGen/TableGen.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=63765&r1=63764&r2=63765&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/utils/TableGen/TableGen.cpp (original) >> +++ llvm/trunk/utils/TableGen/TableGen.cpp Wed Feb 4 13:47:21 2009 >> @@ -49,6 +49,7 @@ >> GenFastISel, >> GenSubtarget, >> GenIntrinsic, >> + GenTgtIntrinsic, >> GenLLVMCConf, >> PrintEnums >> }; >> @@ -82,6 +83,8 @@ >> "Generate subtarget enumerations"), >> clEnumValN(GenIntrinsic, "gen-intrinsic", >> "Generate intrinsic information"), >> + clEnumValN(GenTgtIntrinsic, "gen-tgt-intrinsic", >> + "Generate target intrinsic >> information"), >> clEnumValN(GenLLVMCConf, "gen-llvmc", >> "Generate LLVMC configuration >> library"), >> clEnumValN(PrintEnums, "print-enums", >> @@ -190,6 +193,9 @@ >> case GenIntrinsic: >> IntrinsicEmitter(Records).run(*Out); >> break; >> + case GenTgtIntrinsic: >> + IntrinsicEmitter(Records, true).run(*Out); >> + break; >> case GenLLVMCConf: >> LLVMCConfigurationEmitter(Records).run(*Out); >> break; >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From dalej at apple.com Wed Feb 4 16:47:25 2009 From: dalej at apple.com (Dale Johannesen) Date: Wed, 04 Feb 2009 22:47:25 -0000 Subject: [llvm-commits] [llvm] r63786 - in /llvm/trunk: ./ include/llvm/ include/llvm/Target/ lib/AsmParser/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/VMCore/ utils/TableGen/ Message-ID: <200902042247.n14MlQ8A021275@zion.cs.uiuc.edu> Author: johannes Date: Wed Feb 4 16:47:25 2009 New Revision: 63786 URL: http://llvm.org/viewvc/llvm-project?rev=63786&view=rev Log: Reverting 63765. This broke the build of both clang and llvm-gcc. Modified: llvm/trunk/Makefile.rules llvm/trunk/include/llvm/Function.h llvm/trunk/include/llvm/Intrinsics.h llvm/trunk/include/llvm/Intrinsics.td llvm/trunk/include/llvm/Module.h llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h llvm/trunk/include/llvm/Target/TargetMachine.h llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp llvm/trunk/lib/VMCore/AutoUpgrade.cpp llvm/trunk/lib/VMCore/Function.cpp llvm/trunk/lib/VMCore/Module.cpp llvm/trunk/lib/VMCore/Verifier.cpp llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h llvm/trunk/utils/TableGen/CodeGenIntrinsics.h llvm/trunk/utils/TableGen/CodeGenTarget.cpp llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp llvm/trunk/utils/TableGen/IntrinsicEmitter.h llvm/trunk/utils/TableGen/TableGen.cpp Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=63786&r1=63785&r2=63786&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Wed Feb 4 16:47:25 2009 @@ -1346,11 +1346,6 @@ $(Echo) "Building $( RetTypes = ret_types; list ParamTypes = param_types; list Properties = properties; - - bit isTarget = 0; } /// GCCBuiltin - If this intrinsic exactly corresponds to a GCC builtin, this Modified: llvm/trunk/include/llvm/Module.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Module.h?rev=63786&r1=63785&r2=63786&view=diff ============================================================================== --- llvm/trunk/include/llvm/Module.h (original) +++ llvm/trunk/include/llvm/Module.h Wed Feb 4 16:47:25 2009 @@ -213,10 +213,6 @@ Constant *getOrInsertFunction(const std::string &Name, const Type *RetTy, ...) END_WITH_NULL; - Constant *getOrInsertTargetIntrinsic(const std::string &Name, - const FunctionType *Ty, - AttrListPtr AttributeList); - /// getFunction - Look up the specified function in the module symbol table. /// If it does not exist, return null. Function *getFunction(const std::string &Name) const; Modified: llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h?rev=63786&r1=63785&r2=63786&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h Wed Feb 4 16:47:25 2009 @@ -1,48 +0,0 @@ -//===-- llvm/Target/TargetIntrinsicInfo.h - Instruction Info ----*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the target intrinsic instructions to the code generator. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_TARGET_TARGETINTRINSICINFO_H -#define LLVM_TARGET_TARGETINTRINSICINFO_H - -namespace llvm { - -class Function; -class Module; - -//--------------------------------------------------------------------------- -/// -/// TargetIntrinsicInfo - Interface to description of machine instruction set -/// -class TargetIntrinsicInfo { - - const char **Intrinsics; // Raw array to allow static init'n - unsigned NumIntrinsics; // Number of entries in the desc array - - TargetIntrinsicInfo(const TargetIntrinsicInfo &); // DO NOT IMPLEMENT - void operator=(const TargetIntrinsicInfo &); // DO NOT IMPLEMENT -public: - TargetIntrinsicInfo(const char **desc, unsigned num); - virtual ~TargetIntrinsicInfo(); - - unsigned getNumIntrinsics() const { return NumIntrinsics; } - - virtual Function *getDeclaration(Module *M, const char *BuiltinName) const { - return 0; - } - - virtual unsigned getIntrinsicID(Function *F) const { return 0; } -}; - -} // End llvm namespace - -#endif Modified: llvm/trunk/include/llvm/Target/TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=63786&r1=63785&r2=63786&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetMachine.h (original) +++ llvm/trunk/include/llvm/Target/TargetMachine.h Wed Feb 4 16:47:25 2009 @@ -23,7 +23,6 @@ class TargetData; class TargetSubtarget; class TargetInstrInfo; -class TargetIntrinsicInfo; class TargetJITInfo; class TargetLowering; class TargetFrameInfo; @@ -119,6 +118,7 @@ virtual TargetLowering *getTargetLowering() const { return 0; } virtual const TargetData *getTargetData() const { return 0; } + /// getTargetAsmInfo - Return target specific asm information. /// const TargetAsmInfo *getTargetAsmInfo() const { @@ -141,11 +141,6 @@ /// details of graph coloring register allocation removed from it. /// virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; } - - /// getIntrinsicInfo - If intrinsic information is available, return it. If - /// not, return null. - /// - virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; } /// getJITInfo - If this target supports a JIT, return information for it, /// otherwise return null. Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=63786&r1=63785&r2=63786&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Wed Feb 4 16:47:25 2009 @@ -2949,6 +2949,15 @@ Value *Callee; if (ConvertValIDToValue(PFTy, CalleeID, Callee, PFS)) return true; + // Check for call to invalid intrinsic to avoid crashing later. + if (Function *F = dyn_cast(Callee)) { + if (F->hasName() && F->getNameLen() >= 5 && + !strncmp(F->getValueName()->getKeyData(), "llvm.", 5) && + !F->getIntrinsicID(true)) + return Error(CallLoc, "Call to invalid LLVM intrinsic function '" + + F->getNameStr() + "'"); + } + // FIXME: In LLVM 3.0, stop accepting zext, sext and inreg as optional // function attributes. unsigned ObsoleteFuncAttrs = Attribute::ZExt|Attribute::SExt|Attribute::InReg; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63786&r1=63785&r2=63786&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Wed Feb 4 16:47:25 2009 @@ -43,7 +43,6 @@ #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetIntrinsicInfo.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" @@ -4427,14 +4426,6 @@ const char *RenameFn = 0; if (Function *F = I.getCalledFunction()) { if (F->isDeclaration()) { - const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo(); - if (II) { - if (unsigned IID = II->getIntrinsicID(F)) { - RenameFn = visitIntrinsicCall(I, IID); - if (!RenameFn) - return; - } - } if (unsigned IID = F->getIntrinsicID()) { RenameFn = visitIntrinsicCall(I, IID); if (!RenameFn) Modified: llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp?rev=63786&r1=63785&r2=63786&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp Wed Feb 4 16:47:25 2009 @@ -1,22 +0,0 @@ -//===-- TargetIntrinsicInfo.cpp - Target Instruction Information ----------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements the TargetIntrinsicInfo class. -// -//===----------------------------------------------------------------------===// - -#include "llvm/Target/TargetIntrinsicInfo.h" -using namespace llvm; - -TargetIntrinsicInfo::TargetIntrinsicInfo(const char **desc, unsigned count) - : Intrinsics(desc), NumIntrinsics(count) { -} - -TargetIntrinsicInfo::~TargetIntrinsicInfo() { -} Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=63786&r1=63785&r2=63786&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original) +++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Wed Feb 4 16:47:25 2009 @@ -217,7 +217,7 @@ // Upgrade intrinsic attributes. This does not change the function. if (NewFn) F = NewFn; - if (unsigned id = F->getIntrinsicID()) + if (unsigned id = F->getIntrinsicID(true)) F->setAttributes(Intrinsic::getAttributes((Intrinsic::ID)id)); return Upgraded; } Modified: llvm/trunk/lib/VMCore/Function.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Function.cpp?rev=63786&r1=63785&r2=63786&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Function.cpp (original) +++ llvm/trunk/lib/VMCore/Function.cpp Wed Feb 4 16:47:25 2009 @@ -175,7 +175,7 @@ ParentModule->getFunctionList().push_back(this); // Ensure intrinsics have the right parameter attributes. - if (unsigned IID = getIntrinsicID()) + if (unsigned IID = getIntrinsicID(true)) setAttributes(Intrinsic::getAttributes(Intrinsic::ID(IID))); } @@ -304,7 +304,7 @@ /// particular intrinsic functions which correspond to this value are defined in /// llvm/Intrinsics.h. /// -unsigned Function::getIntrinsicID() const { +unsigned Function::getIntrinsicID(bool noAssert) const { const ValueName *ValName = this->getValueName(); if (!ValName) return 0; @@ -315,9 +315,12 @@ || Name[2] != 'v' || Name[3] != 'm') return 0; // All intrinsics start with 'llvm.' + assert((Len != 5 || noAssert) && "'llvm.' is an invalid intrinsic name!"); + #define GET_FUNCTION_RECOGNIZER #include "llvm/Intrinsics.gen" #undef GET_FUNCTION_RECOGNIZER + assert(noAssert && "Invalid LLVM intrinsic name"); return 0; } @@ -370,9 +373,4 @@ getType(id, Tys, numTys))); } -// This defines the "Intrinsic::getIntrinsicForGCCBuiltin()" method. -#define GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN -#include "llvm/Intrinsics.gen" -#undef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN - // vim: sw=2 ai Modified: llvm/trunk/lib/VMCore/Module.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Module.cpp?rev=63786&r1=63785&r2=63786&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Module.cpp (original) +++ llvm/trunk/lib/VMCore/Module.cpp Wed Feb 4 16:47:25 2009 @@ -171,25 +171,6 @@ return F; } -Constant *Module::getOrInsertTargetIntrinsic(const std::string &Name, - const FunctionType *Ty, - AttrListPtr AttributeList) { - ValueSymbolTable &SymTab = getValueSymbolTable(); - - // See if we have a definition for the specified function already. - GlobalValue *F = dyn_cast_or_null(SymTab.lookup(Name)); - if (F == 0) { - // Nope, add it - Function *New = Function::Create(Ty, GlobalVariable::ExternalLinkage, Name); - New->setAttributes(AttributeList); - FunctionList.push_back(New); - return New; // Return the new prototype. - } - - // Otherwise, we just found the existing function or a prototype. - return F; -} - Constant *Module::getOrInsertFunction(const std::string &Name, const FunctionType *Ty) { AttrListPtr AttributeList = AttrListPtr::get((AttributeWithIndex *)0, 0); Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=63786&r1=63785&r2=63786&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Wed Feb 4 16:47:25 2009 @@ -1004,9 +1004,10 @@ void Verifier::visitCallInst(CallInst &CI) { VerifyCallSite(&CI); - if (Function *F = CI.getCalledFunction()) + if (Function *F = CI.getCalledFunction()) { if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) visitIntrinsicFunctionCall(ID, CI); + } } void Verifier::visitInvokeInst(InvokeInst &II) { Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=63786&r1=63785&r2=63786&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Wed Feb 4 16:47:25 2009 @@ -1303,8 +1303,7 @@ // FIXME: REMOVE OSTREAM ARGUMENT CodeGenDAGPatterns::CodeGenDAGPatterns(RecordKeeper &R) : Records(R) { - Intrinsics = LoadIntrinsics(Records, false); - TgtIntrinsics = LoadIntrinsics(Records, true); + Intrinsics = LoadIntrinsics(Records); ParseNodeInfo(); ParseNodeTransforms(); ParseComplexPatterns(); Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h?rev=63786&r1=63785&r2=63786&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h Wed Feb 4 16:47:25 2009 @@ -465,7 +465,6 @@ RecordKeeper &Records; CodeGenTarget Target; std::vector Intrinsics; - std::vector TgtIntrinsics; std::map SDNodes; std::map > SDNodeXForms; @@ -516,25 +515,18 @@ const CodeGenIntrinsic &getIntrinsic(Record *R) const { for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i) if (Intrinsics[i].TheDef == R) return Intrinsics[i]; - for (unsigned i = 0, e = TgtIntrinsics.size(); i != e; ++i) - if (TgtIntrinsics[i].TheDef == R) return TgtIntrinsics[i]; assert(0 && "Unknown intrinsic!"); abort(); } const CodeGenIntrinsic &getIntrinsicInfo(unsigned IID) const { - if (IID-1 < Intrinsics.size()) - return Intrinsics[IID-1]; - if (IID-Intrinsics.size()-1 < TgtIntrinsics.size()) - return TgtIntrinsics[IID-Intrinsics.size()-1]; - assert(0 && "Bad intrinsic ID!"); + assert(IID-1 < Intrinsics.size() && "Bad intrinsic ID!"); + return Intrinsics[IID-1]; } unsigned getIntrinsicID(Record *R) const { for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i) if (Intrinsics[i].TheDef == R) return i; - for (unsigned i = 0, e = TgtIntrinsics.size(); i != e; ++i) - if (TgtIntrinsics[i].TheDef == R) return i + Intrinsics.size(); assert(0 && "Unknown intrinsic!"); abort(); } Modified: llvm/trunk/utils/TableGen/CodeGenIntrinsics.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenIntrinsics.h?rev=63786&r1=63785&r2=63786&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenIntrinsics.h (original) +++ llvm/trunk/utils/TableGen/CodeGenIntrinsics.h Wed Feb 4 16:47:25 2009 @@ -80,8 +80,7 @@ /// LoadIntrinsics - Read all of the intrinsics defined in the specified /// .td file. - std::vector LoadIntrinsics(const RecordKeeper &RC, - bool TargetOnly); + std::vector LoadIntrinsics(const RecordKeeper &RC); } #endif Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=63786&r1=63785&r2=63786&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Wed Feb 4 16:47:25 2009 @@ -426,17 +426,13 @@ // CodeGenIntrinsic Implementation //===----------------------------------------------------------------------===// -std::vector llvm::LoadIntrinsics(const RecordKeeper &RC, - bool TargetOnly) { +std::vector llvm::LoadIntrinsics(const RecordKeeper &RC) { std::vector I = RC.getAllDerivedDefinitions("Intrinsic"); std::vector Result; - for (unsigned i = 0, e = I.size(); i != e; ++i) { - bool isTarget = I[i]->getValueAsBit("isTarget"); - if (isTarget == TargetOnly) - Result.push_back(CodeGenIntrinsic(I[i])); - } + for (unsigned i = 0, e = I.size(); i != e; ++i) + Result.push_back(CodeGenIntrinsic(I[i])); return Result; } Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=63786&r1=63785&r2=63786&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Wed Feb 4 16:47:25 2009 @@ -25,10 +25,7 @@ void IntrinsicEmitter::run(std::ostream &OS) { EmitSourceFileHeader("Intrinsic Function Source Fragment", OS); - std::vector Ints = LoadIntrinsics(Records, TargetOnly); - - if (TargetOnly && !Ints.empty()) - TargetPrefix = Ints[0].TargetPrefix; + std::vector Ints = LoadIntrinsics(Records); // Emit the enum information. EmitEnumInfo(Ints, OS); @@ -94,12 +91,12 @@ if (Ints[I->second].isOverloaded) OS << " if (Len > " << I->first.size() << " && !memcmp(Name, \"" << I->first << ".\", " - << (I->first.size() + 1) << ")) return " << TargetPrefix << "Intrinsic::" + << (I->first.size() + 1) << ")) return Intrinsic::" << Ints[I->second].EnumName << ";\n"; else OS << " if (Len == " << I->first.size() << " && !memcmp(Name, \"" << I->first << "\", " - << I->first.size() << ")) return " << TargetPrefix << "Intrinsic::" + << I->first.size() << ")) return Intrinsic::" << Ints[I->second].EnumName << ";\n"; } OS << " }\n"; @@ -354,13 +351,11 @@ Ints[i].IS.ParamTypeDefs)].push_back(i); // Loop through the array, emitting one generator for each batch. - std::string IntrinsicStr = TargetPrefix + "Intrinsic::"; - for (MapTy::iterator I = UniqueArgInfos.begin(), E = UniqueArgInfos.end(); I != E; ++I) { for (unsigned i = 0, e = I->second.size(); i != e; ++i) - OS << " case " << IntrinsicStr << Ints[I->second[i]].EnumName - << ":\t\t// " << Ints[I->second[i]].Name << "\n"; + OS << " case Intrinsic::" << Ints[I->second[i]].EnumName << ":\t\t// " + << Ints[I->second[i]].Name << "\n"; const RecPair &ArgTypes = I->first; const std::vector &RetTys = ArgTypes.first; @@ -397,11 +392,7 @@ EmitAttributes(const std::vector &Ints, std::ostream &OS) { OS << "// Add parameter attributes that are not common to all intrinsics.\n"; OS << "#ifdef GET_INTRINSIC_ATTRIBUTES\n"; - if (TargetOnly) - OS << "static AttrListPtr getAttributes(" << TargetPrefix - << "Intrinsic::ID id) {"; - else - OS << "AttrListPtr Intrinsic::getAttributes(ID id) {"; + OS << "AttrListPtr Intrinsic::getAttributes(ID id) {"; OS << " // No intrinsic can throw exceptions.\n"; OS << " Attributes Attr = Attribute::NoUnwind;\n"; OS << " switch (id) {\n"; @@ -413,8 +404,7 @@ switch (Ints[i].ModRef) { default: break; case CodeGenIntrinsic::NoMem: - OS << " case " << TargetPrefix << "Intrinsic::" << Ints[i].EnumName - << ":\n"; + OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; break; } } @@ -425,8 +415,7 @@ default: break; case CodeGenIntrinsic::ReadArgMem: case CodeGenIntrinsic::ReadMem: - OS << " case " << TargetPrefix << "Intrinsic::" << Ints[i].EnumName - << ":\n"; + OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; break; } } @@ -442,8 +431,7 @@ for (unsigned i = 0, e = Ints.size(); i != e; ++i) { if (Ints[i].ArgumentAttributes.empty()) continue; - OS << " case " << TargetPrefix << "Intrinsic::" << Ints[i].EnumName - << ":\n"; + OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; std::vector > ArgAttrs = Ints[i].ArgumentAttributes; @@ -507,7 +495,7 @@ typedef std::map::const_iterator StrMapIterator; static void EmitBuiltinComparisons(StrMapIterator Start, StrMapIterator End, unsigned CharStart, unsigned Indent, - std::string TargetPrefix, std::ostream &OS) { + std::ostream &OS) { if (Start == End) return; // empty range. // Determine what, if anything, is the same about all these strings. @@ -534,8 +522,7 @@ OS << CommonString.size() - CharStart << "))\n"; ++Indent; } - OS << std::string(Indent*2, ' ') << "IntrinsicID = " << TargetPrefix - << "Intrinsic::"; + OS << std::string(Indent*2, ' ') << "IntrinsicID = Intrinsic::"; OS << Start->second << ";\n"; return; } @@ -548,8 +535,7 @@ OS << ", \"" << (CommonString.c_str()+CharStart) << "\", "; OS << CommonString.size()-CharStart << ")) {\n"; - EmitBuiltinComparisons(Start, End, CommonString.size(), Indent+1, - TargetPrefix, OS); + EmitBuiltinComparisons(Start, End, CommonString.size(), Indent+1, OS); OS << std::string(Indent*2, ' ') << "}\n"; return; } @@ -570,7 +556,7 @@ for (++NextChar; NextChar != End && NextChar->first[CharStart] == ThisChar; ++NextChar) /*empty*/; - EmitBuiltinComparisons(I, NextChar, CharStart+1, Indent+1, TargetPrefix,OS); + EmitBuiltinComparisons(I, NextChar, CharStart+1, Indent+1, OS); OS << std::string(Indent*2, ' ') << " break;\n"; I = NextChar; } @@ -580,7 +566,6 @@ /// EmitTargetBuiltins - All of the builtins in the specified map are for the /// same target, and we already checked it. static void EmitTargetBuiltins(const std::map &BIM, - const std::string &TargetPrefix, std::ostream &OS) { // Rearrange the builtins by length. std::vector > BuiltinsByLen; @@ -599,7 +584,7 @@ if (BuiltinsByLen[i].empty()) continue; OS << " case " << i << ":\n"; EmitBuiltinComparisons(BuiltinsByLen[i].begin(), BuiltinsByLen[i].end(), - 0, 3, TargetPrefix, OS); + 0, 3, OS); OS << " break;\n"; } OS << " }\n"; @@ -628,22 +613,7 @@ OS << "// in as BuiltinName, and a target prefix (e.g. 'ppc') is passed\n"; OS << "// in as TargetPrefix. The result is assigned to 'IntrinsicID'.\n"; OS << "#ifdef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN\n"; - - if (TargetOnly) { - OS << "static " << TargetPrefix << "Intrinsic::ID " - << "getIntrinsicForGCCBuiltin(const char " - << "*TargetPrefix, const char *BuiltinName) {\n"; - OS << " " << TargetPrefix << "Intrinsic::ID IntrinsicID = "; - } else { - OS << "Intrinsic::ID Intrinsic::getIntrinsicForGCCBuiltin(const char " - << "*TargetPrefix, const char *BuiltinName) {\n"; - OS << " Intrinsic::ID IntrinsicID = "; - } - - if (TargetOnly) - OS << "(" << TargetPrefix<< "Intrinsic::ID)"; - - OS << "Intrinsic::not_intrinsic;\n"; + OS << " IntrinsicID = Intrinsic::not_intrinsic;\n"; // Note: this could emit significantly better code if we cared. for (BIMTy::iterator I = BuiltinMap.begin(), E = BuiltinMap.end();I != E;++I){ @@ -655,10 +625,8 @@ OS << "{\n"; // Emit the comparisons for this target prefix. - EmitTargetBuiltins(I->second, TargetPrefix, OS); + EmitTargetBuiltins(I->second, OS); OS << " }\n"; } - OS << " return IntrinsicID;\n"; - OS << "}\n"; OS << "#endif\n\n"; } Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.h?rev=63786&r1=63785&r2=63786&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/IntrinsicEmitter.h (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.h Wed Feb 4 16:47:25 2009 @@ -20,12 +20,9 @@ namespace llvm { class IntrinsicEmitter : public TableGenBackend { RecordKeeper &Records; - bool TargetOnly; - std::string TargetPrefix; public: - IntrinsicEmitter(RecordKeeper &R, bool T = false) - : Records(R), TargetOnly(T) {} + IntrinsicEmitter(RecordKeeper &R) : Records(R) {} void run(std::ostream &OS); Modified: llvm/trunk/utils/TableGen/TableGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=63786&r1=63785&r2=63786&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TableGen.cpp (original) +++ llvm/trunk/utils/TableGen/TableGen.cpp Wed Feb 4 16:47:25 2009 @@ -49,7 +49,6 @@ GenFastISel, GenSubtarget, GenIntrinsic, - GenTgtIntrinsic, GenLLVMCConf, PrintEnums }; @@ -83,8 +82,6 @@ "Generate subtarget enumerations"), clEnumValN(GenIntrinsic, "gen-intrinsic", "Generate intrinsic information"), - clEnumValN(GenTgtIntrinsic, "gen-tgt-intrinsic", - "Generate target intrinsic information"), clEnumValN(GenLLVMCConf, "gen-llvmc", "Generate LLVMC configuration library"), clEnumValN(PrintEnums, "print-enums", @@ -193,9 +190,6 @@ case GenIntrinsic: IntrinsicEmitter(Records).run(*Out); break; - case GenTgtIntrinsic: - IntrinsicEmitter(Records, true).run(*Out); - break; case GenLLVMCConf: LLVMCConfigurationEmitter(Records).run(*Out); break; From tonic at nondot.org Wed Feb 4 16:54:57 2009 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 04 Feb 2009 22:54:57 -0000 Subject: [llvm-commits] [llvm] r63787 - in /llvm/branches/release_25: lib/Transforms/Utils/InlineFunction.cpp test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll Message-ID: <200902042254.n14Msv3J021647@zion.cs.uiuc.edu> Author: tbrethou Date: Wed Feb 4 16:54:57 2009 New Revision: 63787 URL: http://llvm.org/viewvc/llvm-project?rev=63787&view=rev Log: Merge from mainline. Revert r63600. Removed: llvm/branches/release_25/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll Modified: llvm/branches/release_25/lib/Transforms/Utils/InlineFunction.cpp Modified: llvm/branches/release_25/lib/Transforms/Utils/InlineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Transforms/Utils/InlineFunction.cpp?rev=63787&r1=63786&r2=63787&view=diff ============================================================================== --- llvm/branches/release_25/lib/Transforms/Utils/InlineFunction.cpp (original) +++ llvm/branches/release_25/lib/Transforms/Utils/InlineFunction.cpp Wed Feb 4 16:54:57 2009 @@ -41,8 +41,7 @@ /// block of the inlined code (the last block is the end of the function), /// and InlineCodeInfo is information about the code that got inlined. static void HandleInlinedInvoke(InvokeInst *II, BasicBlock *FirstNewBlock, - ClonedCodeInfo &InlinedCodeInfo, - CallGraph *CG) { + ClonedCodeInfo &InlinedCodeInfo) { BasicBlock *InvokeDest = II->getUnwindDest(); std::vector InvokeDestPHIValues; @@ -94,10 +93,6 @@ // Make sure that anything using the call now uses the invoke! CI->replaceAllUsesWith(II); - // Update the callgraph. - if (CG) - (*CG)[Caller]->replaceCallSite(CI, II); - // Delete the unconditional branch inserted by splitBasicBlock BB->getInstList().pop_back(); Split->getInstList().pop_front(); // Delete the original call @@ -438,7 +433,7 @@ // any inlined 'unwind' instructions into branches to the invoke exception // destination, and call instructions into invoke instructions. if (InvokeInst *II = dyn_cast(TheCall)) - HandleInlinedInvoke(II, FirstNewBlock, InlinedFunctionInfo, CG); + HandleInlinedInvoke(II, FirstNewBlock, InlinedFunctionInfo); // If we cloned in _exactly one_ basic block, and if that block ends in a // return instruction, we splice the body of the inlined callee directly into Removed: llvm/branches/release_25/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll?rev=63786&view=auto ============================================================================== --- llvm/branches/release_25/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll (original) +++ llvm/branches/release_25/test/Transforms/Inline/2009-02-02-InvokeUpdateCG.ll (removed) @@ -1,32 +0,0 @@ -; RUN: llvm-as < %s | opt -inline -prune-eh -; PR3367 - -define void @f2() { - invoke void @f6() - to label %ok1 unwind label %lpad1 - -ok1: - ret void - -lpad1: - invoke void @f4() - to label %ok2 unwind label %lpad2 - -ok2: - call void @f8() - unreachable - -lpad2: - unreachable -} - -declare void @f3() - -define void @f4() { - call void @f3() - ret void -} - -declare void @f6() nounwind - -declare void @f8() From tonic at nondot.org Wed Feb 4 17:00:52 2009 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 04 Feb 2009 23:00:52 -0000 Subject: [llvm-commits] [llvm] r63788 - in /llvm/branches/release_25: docs/LangRef.html lib/AsmParser/LLLexer.cpp test/Assembler/vector-cmp.ll test/CodeGen/X86/2008-07-23-VSetCC.ll test/CodeGen/X86/vfcmp.ll test/Transforms/ConstProp/2008-07-07-VectorCompare.ll Message-ID: <200902042300.n14N0qFM021840@zion.cs.uiuc.edu> Author: tbrethou Date: Wed Feb 4 17:00:52 2009 New Revision: 63788 URL: http://llvm.org/viewvc/llvm-project?rev=63788&view=rev Log: Disable support for vicmp/vfcmp from the LLVM 2.5 release branch, like we did for LLVM 2.4. These are slated to be removed (PR3370) and we don't want to have to be backwards compatible with them in the future. Modified: llvm/branches/release_25/docs/LangRef.html llvm/branches/release_25/lib/AsmParser/LLLexer.cpp llvm/branches/release_25/test/Assembler/vector-cmp.ll llvm/branches/release_25/test/CodeGen/X86/2008-07-23-VSetCC.ll llvm/branches/release_25/test/CodeGen/X86/vfcmp.ll llvm/branches/release_25/test/Transforms/ConstProp/2008-07-07-VectorCompare.ll Modified: llvm/branches/release_25/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/docs/LangRef.html?rev=63788&r1=63787&r2=63788&view=diff ============================================================================== --- llvm/branches/release_25/docs/LangRef.html (original) +++ llvm/branches/release_25/docs/LangRef.html Wed Feb 4 17:00:52 2009 @@ -150,8 +150,6 @@
    1. 'icmp' Instruction
    2. 'fcmp' Instruction
      3. -
    3. 'vicmp' Instruction
      4. -
    4. 'vfcmp' Instruction
    5. 'phi' Instruction
    6. 'select' Instruction
    7. 'call' Instruction
      8. @@ -1942,12 +1940,6 @@
      fcmp COND ( VAL1, VAL2 )
      Performs the fcmp operation on constants.
      -
      vicmp COND ( VAL1, VAL2 )
      -
      Performs the vicmp operation on constants.
      - -
      vfcmp COND ( VAL1, VAL2 )
      -
      Performs the vfcmp operation on constants.
      -
      extractelement ( VAL, IDX )
      Perform the extractelement @@ -4254,109 +4246,6 @@
      - 'vicmp' Instruction -
      -
      -
      Syntax:
      -
        <result> = vicmp <cond> <ty> <op1>, <op2>   ; yields {ty}:result
-
      -
      Overview:
      -

      The 'vicmp' instruction returns an integer vector value based on -element-wise comparison of its two integer vector operands.

      -
      Arguments:
      -

      The 'vicmp' instruction takes three operands. The first operand is -the condition code indicating the kind of comparison to perform. It is not -a value, just a keyword. The possible condition code are:

      -
        -
      1. eq: equal
        2. -
      2. ne: not equal
        3. -
      3. ugt: unsigned greater than
        4. -
      4. uge: unsigned greater or equal
        5. -
      5. ult: unsigned less than
        6. -
      6. ule: unsigned less or equal
        7. -
      7. sgt: signed greater than
        8. -
      8. sge: signed greater or equal
        9. -
      9. slt: signed less than
        10. -
      10. sle: signed less or equal
        11. -
      -

      The remaining two arguments must be vector or -integer typed. They must also be identical types.

      -
      Semantics:
      -

      The 'vicmp' instruction compares op1 and op2 -according to the condition code given as cond. The comparison yields a -vector of integer result, of -identical type as the values being compared. The most significant bit in each -element is 1 if the element-wise comparison evaluates to true, and is 0 -otherwise. All other bits of the result are undefined. The condition codes -are evaluated identically to the 'icmp' -instruction.

      - -
      Example:
      -
      -  <result> = vicmp eq <2 x i32> < i32 4, i32 0>, < i32 5, i32 0>   ; yields: result=<2 x i32> < i32 0, i32 -1 >
-  <result> = vicmp ult <2 x i8 > < i8 1, i8 2>, < i8 2, i8 2 >        ; yields: result=<2 x i8> < i8 -1, i8 0 >
-
      -
      - - -
      - 'vfcmp' Instruction -
      -
      -
      Syntax:
      -
        <result> = vfcmp <cond> <ty> <op1>, <op2>
      -
      Overview:
      -

      The 'vfcmp' instruction returns an integer vector value based on -element-wise comparison of its two floating point vector operands. The output -elements have the same width as the input elements.

      -
      Arguments:
      -

      The 'vfcmp' instruction takes three operands. The first operand is -the condition code indicating the kind of comparison to perform. It is not -a value, just a keyword. The possible condition code are:

      -
        -
      1. false: no comparison, always returns false
        2. -
      2. oeq: ordered and equal
        3. -
      3. ogt: ordered and greater than
        4. -
      4. oge: ordered and greater than or equal
        5. -
      5. olt: ordered and less than
        6. -
      6. ole: ordered and less than or equal
        7. -
      7. one: ordered and not equal
        8. -
      8. ord: ordered (no nans)
        9. -
      9. ueq: unordered or equal
        10. -
      10. ugt: unordered or greater than
        11. -
      11. uge: unordered or greater than or equal
        12. -
      12. ult: unordered or less than
        13. -
      13. ule: unordered or less than or equal
        14. -
      14. une: unordered or not equal
        15. -
      15. uno: unordered (either nans)
        16. -
      16. true: no comparison, always returns true
        17. -
      -

      The remaining two arguments must be vector of -floating point typed. They must also be identical -types.

      -
      Semantics:
      -

      The 'vfcmp' instruction compares op1 and op2 -according to the condition code given as cond. The comparison yields a -vector of integer result, with -an identical number of elements as the values being compared, and each element -having identical with to the width of the floating point elements. The most -significant bit in each element is 1 if the element-wise comparison evaluates to -true, and is 0 otherwise. All other bits of the result are undefined. The -condition codes are evaluated identically to the -'fcmp' instruction.

      - -
      Example:
      -
      -  ; yields: result=<2 x i32> < i32 0, i32 -1 >
-  <result> = vfcmp oeq <2 x float> < float 4, float 0 >, < float 5, float 0 >
-  
-  ; yields: result=<2 x i64> < i64 -1, i64 0 >
-  <result> = vfcmp ult <2 x double> < double 1, double 2 >, < double 2, double 2>
-
      -
      - - -
      'phi' Instruction
      Modified: llvm/branches/release_25/lib/AsmParser/LLLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/AsmParser/LLLexer.cpp?rev=63788&r1=63787&r2=63788&view=diff ============================================================================== --- llvm/branches/release_25/lib/AsmParser/LLLexer.cpp (original) +++ llvm/branches/release_25/lib/AsmParser/LLLexer.cpp Wed Feb 4 17:00:52 2009 @@ -560,7 +560,6 @@ INSTKEYWORD(shl, Shl); INSTKEYWORD(lshr, LShr); INSTKEYWORD(ashr, AShr); INSTKEYWORD(and, And); INSTKEYWORD(or, Or); INSTKEYWORD(xor, Xor); INSTKEYWORD(icmp, ICmp); INSTKEYWORD(fcmp, FCmp); - INSTKEYWORD(vicmp, VICmp); INSTKEYWORD(vfcmp, VFCmp); INSTKEYWORD(phi, PHI); INSTKEYWORD(call, Call); Modified: llvm/branches/release_25/test/Assembler/vector-cmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/test/Assembler/vector-cmp.ll?rev=63788&r1=63787&r2=63788&view=diff ============================================================================== --- llvm/branches/release_25/test/Assembler/vector-cmp.ll (original) +++ llvm/branches/release_25/test/Assembler/vector-cmp.ll Wed Feb 4 17:00:52 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | grep {global.*vicmp slt} +; RUN: echo disabled ; PR2317 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i686-apple-darwin9.2.2" Modified: llvm/branches/release_25/test/CodeGen/X86/2008-07-23-VSetCC.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/test/CodeGen/X86/2008-07-23-VSetCC.ll?rev=63788&r1=63787&r2=63788&view=diff ============================================================================== --- llvm/branches/release_25/test/CodeGen/X86/2008-07-23-VSetCC.ll (original) +++ llvm/branches/release_25/test/CodeGen/X86/2008-07-23-VSetCC.ll Wed Feb 4 17:00:52 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86 -mcpu=pentium +; RUN: echo disabled ; PR2575 define void @entry(i32 %m_task_id, i32 %start_x, i32 %end_x) nounwind { Modified: llvm/branches/release_25/test/CodeGen/X86/vfcmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/test/CodeGen/X86/vfcmp.ll?rev=63788&r1=63787&r2=63788&view=diff ============================================================================== --- llvm/branches/release_25/test/CodeGen/X86/vfcmp.ll (original) +++ llvm/branches/release_25/test/CodeGen/X86/vfcmp.ll Wed Feb 4 17:00:52 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 +; RUN: echo disabled ; PR2620 define void @t(i32 %m_task_id, i32 %start_x, i32 %end_x) nounwind { Modified: llvm/branches/release_25/test/Transforms/ConstProp/2008-07-07-VectorCompare.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/test/Transforms/ConstProp/2008-07-07-VectorCompare.ll?rev=63788&r1=63787&r2=63788&view=diff ============================================================================== --- llvm/branches/release_25/test/Transforms/ConstProp/2008-07-07-VectorCompare.ll (original) +++ llvm/branches/release_25/test/Transforms/ConstProp/2008-07-07-VectorCompare.ll Wed Feb 4 17:00:52 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | opt -constprop -disable-output +; RUN: echo disabled ; PR2529 define <4 x i32> @test1(i32 %argc, i8** %argv) { entry: From dalej at apple.com Wed Feb 4 17:02:31 2009 From: dalej at apple.com (Dale Johannesen) Date: Wed, 04 Feb 2009 23:02:31 -0000 Subject: [llvm-commits] [llvm] r63789 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/XCore/ utils/TableGen/ Message-ID: <200902042302.n14N2WvW021922@zion.cs.uiuc.edu> Author: johannes Date: Wed Feb 4 17:02:30 2009 New Revision: 63789 URL: http://llvm.org/viewvc/llvm-project?rev=63789&view=rev Log: Remove non-DebugLoc forms of CopyToReg and CopyFromReg. Adjust callers. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63789&r1=63788&r2=63789&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Feb 4 17:02:30 2009 @@ -322,10 +322,6 @@ SDValue getLabel(unsigned Opcode, DebugLoc dl, SDValue Root, unsigned LabelID); - SDValue getCopyToReg(SDValue Chain, unsigned Reg, SDValue N) { - return getNode(ISD::CopyToReg, MVT::Other, Chain, - getRegister(Reg, N.getValueType()), N); - } SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) { return getNode(ISD::CopyToReg, dl, MVT::Other, Chain, getRegister(Reg, N.getValueType()), N); @@ -334,12 +330,6 @@ // This version of the getCopyToReg method takes an extra operand, which // indicates that there is potentially an incoming flag value (if Flag is not // null) and that there should be a flag result. - SDValue getCopyToReg(SDValue Chain, unsigned Reg, SDValue N, - SDValue Flag) { - const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag); - SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag }; - return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.getNode() ? 4 : 3); - } SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N, SDValue Flag) { const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag); @@ -348,12 +338,6 @@ } // Similar to last getCopyToReg() except parameter Reg is a SDValue - SDValue getCopyToReg(SDValue Chain, SDValue Reg, SDValue N, - SDValue Flag) { - const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag); - SDValue Ops[] = { Chain, Reg, N, Flag }; - return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.getNode() ? 4 : 3); - } SDValue getCopyToReg(SDValue Chain, DebugLoc dl, SDValue Reg, SDValue N, SDValue Flag) { const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag); @@ -361,11 +345,6 @@ return getNode(ISD::CopyToReg, dl, VTs, 2, Ops, Flag.getNode() ? 4 : 3); } - SDValue getCopyFromReg(SDValue Chain, unsigned Reg, MVT VT) { - const MVT *VTs = getNodeValueTypes(VT, MVT::Other); - SDValue Ops[] = { Chain, getRegister(Reg, VT) }; - return getNode(ISD::CopyFromReg, VTs, 2, Ops, 2); - } SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, MVT VT) { const MVT *VTs = getNodeValueTypes(VT, MVT::Other); SDValue Ops[] = { Chain, getRegister(Reg, VT) }; @@ -375,12 +354,6 @@ // This version of the getCopyFromReg method takes an extra operand, which // indicates that there is potentially an incoming flag value (if Flag is not // null) and that there should be a flag result. - SDValue getCopyFromReg(SDValue Chain, unsigned Reg, MVT VT, - SDValue Flag) { - const MVT *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag); - SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag }; - return getNode(ISD::CopyFromReg, VTs, 3, Ops, Flag.getNode() ? 3 : 2); - } SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, MVT VT, SDValue Flag) { const MVT *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63789&r1=63788&r2=63789&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Feb 4 17:02:30 2009 @@ -4386,7 +4386,7 @@ /// /// Note that MorphNodeTo returns the resultant node. If there is already a /// node of the specified opcode and operands, it returns that node instead of -/// the current one. +/// the current one. Note that the DebugLoc need not be the same. /// /// Using MorphNodeTo is faster than creating a new node and swapping it in /// with ReplaceAllUsesWith both because it often avoids allocating a new Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=63789&r1=63788&r2=63789&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Feb 4 17:02:30 2009 @@ -652,6 +652,7 @@ static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { SDValue Copy; SDValue Chain = Op.getOperand(0); + DebugLoc dl = Op.getDebugLoc(); switch(Op.getNumOperands()) { default: assert(0 && "Do not know how to return this many arguments!"); @@ -672,13 +673,14 @@ return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign, Op.getValue(1), Sign); } - Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDValue()); + Copy = DAG.getCopyToReg(Chain, dl, ARM::R0, Op, SDValue()); if (DAG.getMachineFunction().getRegInfo().liveout_empty()) DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); break; case 5: - Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDValue()); - Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1)); + Copy = DAG.getCopyToReg(Chain, dl, ARM::R1, Op.getOperand(3), SDValue()); + Copy = DAG.getCopyToReg(Copy, dl, ARM::R0, Op.getOperand(1), + Copy.getValue(1)); // If we haven't noted the R0+R1 are live out, do so now. if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); @@ -686,10 +688,13 @@ } break; case 9: // i128 -> 4 regs - Copy = DAG.getCopyToReg(Chain, ARM::R3, Op.getOperand(7), SDValue()); - Copy = DAG.getCopyToReg(Copy , ARM::R2, Op.getOperand(5), Copy.getValue(1)); - Copy = DAG.getCopyToReg(Copy , ARM::R1, Op.getOperand(3), Copy.getValue(1)); - Copy = DAG.getCopyToReg(Copy , ARM::R0, Op.getOperand(1), Copy.getValue(1)); + Copy = DAG.getCopyToReg(Chain, dl, ARM::R3, Op.getOperand(7), SDValue()); + Copy = DAG.getCopyToReg(Copy , dl, ARM::R2, Op.getOperand(5), + Copy.getValue(1)); + Copy = DAG.getCopyToReg(Copy , dl, ARM::R1, Op.getOperand(3), + Copy.getValue(1)); + Copy = DAG.getCopyToReg(Copy , dl, ARM::R0, Op.getOperand(1), + Copy.getValue(1)); // If we haven't noted the R0+R1 are live out, do so now. if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); Modified: llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp?rev=63789&r1=63788&r2=63789&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Wed Feb 4 17:02:30 2009 @@ -204,8 +204,9 @@ break; } assert(GP && "GOT PTR not in liveins"); + // FIXME is there anywhere sensible to get a DebugLoc here? return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), - GP, MVT::i64); + DebugLoc::getUnknownLoc(), GP, MVT::i64); } /// getRASaveReg - Grab the return address @@ -219,8 +220,9 @@ break; } assert(RA && "RA PTR not in liveins"); + // FIXME is there anywhere sensible to get a DebugLoc here? return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), - RA, MVT::i64); + DebugLoc::getUnknownLoc(), RA, MVT::i64); } /// InstructionSelect - This callback is invoked by @@ -240,6 +242,7 @@ if (N->isMachineOpcode()) { return NULL; // Already selected. } + DebugLoc dl = N->getDebugLoc(); switch (N->getOpcode()) { default: break; @@ -269,23 +272,23 @@ SDValue N0 = Op.getOperand(0); SDValue N1 = Op.getOperand(1); SDValue N2 = Op.getOperand(2); - Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1, + Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R24, N1, SDValue(0,0)); - Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2, + Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R25, N2, Chain.getValue(1)); - Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0, + Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, N0, Chain.getValue(1)); SDNode *CNode = - CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag, + CurDAG->getTargetNode(Alpha::JSRs, dl, MVT::Other, MVT::Flag, Chain, Chain.getValue(1)); - Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64, + Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, MVT::i64, SDValue(CNode, 1)); return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain); } case ISD::READCYCLECOUNTER: { SDValue Chain = N->getOperand(0); - return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other, + return CurDAG->getTargetNode(Alpha::RPCC, dl, MVT::i64, MVT::Other, Chain); } @@ -293,7 +296,7 @@ uint64_t uval = cast(N)->getZExtValue(); if (uval == 0) { - SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), + SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, Alpha::R31, MVT::i64); ReplaceUses(Op, Result); return NULL; @@ -311,7 +314,7 @@ //Else use the constant pool ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval); SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64); - SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, + SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, dl, MVT::i64, CPI, getGlobalBaseReg()); return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, CPI, SDValue(Tmp, 0), CurDAG->getEntryNode()); @@ -363,25 +366,27 @@ }; SDValue tmp1 = N->getOperand(rev?1:0); SDValue tmp2 = N->getOperand(rev?0:1); - SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64, tmp1, tmp2); + SDNode *cmp = CurDAG->getTargetNode(Opc, dl, MVT::f64, tmp1, tmp2); if (inv) - cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDValue(cmp, 0), + cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, dl, + MVT::f64, SDValue(cmp, 0), CurDAG->getRegister(Alpha::F31, MVT::f64)); switch(CC) { case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE: case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE: { - SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64, + SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, dl, MVT::f64, tmp1, tmp2); - cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64, + cmp = CurDAG->getTargetNode(Alpha::ADDT, dl, MVT::f64, SDValue(cmp2, 0), SDValue(cmp, 0)); break; } default: break; } - SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, SDValue(cmp, 0)); - return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64, + SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, dl, + MVT::i64, SDValue(cmp, 0)); + return CurDAG->getTargetNode(Alpha::CMPULT, dl, MVT::i64, CurDAG->getRegister(Alpha::R31, MVT::i64), SDValue(LD,0)); } @@ -400,9 +405,9 @@ SDValue TV = N->getOperand(1); SDValue FV = N->getOperand(2); - SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, MVT::f64, cond); + SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, dl, MVT::f64, cond); return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES, - MVT::f64, FV, TV, SDValue(LD,0)); + dl, MVT::f64, FV, TV, SDValue(LD,0)); } break; @@ -427,10 +432,10 @@ if (get_zapImm(mask)) { SDValue Z = - SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64, + SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, dl, MVT::i64, N->getOperand(0).getOperand(0), getI64Imm(get_zapImm(mask))), 0); - return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z, + return CurDAG->getTargetNode(Alpha::SRLr, dl, MVT::i64, Z, getI64Imm(sval)); } } @@ -449,6 +454,7 @@ SDValue Chain = N->getOperand(0); SDValue Addr = N->getOperand(1); SDValue InFlag(0,0); // Null incoming flag value. + DebugLoc dl = N->getDebugLoc(); std::vector CallOperands; std::vector TypeOperands; @@ -477,16 +483,18 @@ assert(0 && "Unknown operand"); SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8), - CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64), - Chain }; - Chain = SDValue(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0); + CurDAG->getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64), + Chain }; + Chain = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 4), 0); } for (int i = 0; i < std::min(6, count); ++i) { if (TypeOperands[i].isInteger()) { - Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag); + Chain = CurDAG->getCopyToReg(Chain, dl, args_int[i], + CallOperands[i], InFlag); InFlag = Chain.getValue(1); } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) { - Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag); + Chain = CurDAG->getCopyToReg(Chain, dl, args_float[i], + CallOperands[i], InFlag); InFlag = Chain.getValue(1); } else assert(0 && "Unknown operand"); @@ -496,15 +504,16 @@ // call itself. if (Addr.getOpcode() == AlphaISD::GPRelLo) { SDValue GOT = getGlobalBaseReg(); - Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag); + Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R29, GOT, InFlag); InFlag = Chain.getValue(1); - Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag, - Addr.getOperand(0), Chain, InFlag), 0); + Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, dl, MVT::Other, + MVT::Flag, Addr.getOperand(0), + Chain, InFlag), 0); } else { - Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag); + Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, Addr, InFlag); InFlag = Chain.getValue(1); - Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag, - Chain, InFlag), 0); + Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, dl, MVT::Other, + MVT::Flag, Chain, InFlag), 0); } InFlag = Chain.getValue(1); @@ -514,15 +523,18 @@ default: assert(0 && "Unexpected ret value!"); case MVT::Other: break; case MVT::i64: - Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1); + Chain = CurDAG->getCopyFromReg(Chain, dl, + Alpha::R0, MVT::i64, InFlag).getValue(1); CallResults.push_back(Chain.getValue(0)); break; case MVT::f32: - Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1); + Chain = CurDAG->getCopyFromReg(Chain, dl, + Alpha::F0, MVT::f32, InFlag).getValue(1); CallResults.push_back(Chain.getValue(0)); break; case MVT::f64: - Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1); + Chain = CurDAG->getCopyFromReg(Chain, dl, + Alpha::F0, MVT::f64, InFlag).getValue(1); CallResults.push_back(Chain.getValue(0)); break; } Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=63789&r1=63788&r2=63789&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Wed Feb 4 17:02:30 2009 @@ -300,7 +300,8 @@ } static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { - SDValue Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26, + DebugLoc dl = Op.getDebugLoc(); + SDValue Copy = DAG.getCopyToReg(Op.getOperand(0), dl, Alpha::R26, DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64), SDValue()); @@ -320,7 +321,8 @@ assert(ArgVT.isFloatingPoint()); ArgReg = Alpha::F0; } - Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1)); + Copy = DAG.getCopyToReg(Copy, dl, ArgReg, + Op.getOperand(1), Copy.getValue(1)); if (DAG.getMachineFunction().getRegInfo().liveout_empty()) DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg); break; @@ -336,12 +338,14 @@ ArgReg1 = Alpha::F0; ArgReg2 = Alpha::F1; } - Copy = DAG.getCopyToReg(Copy, ArgReg1, Op.getOperand(1), Copy.getValue(1)); + Copy = DAG.getCopyToReg(Copy, dl, ArgReg1, + Op.getOperand(1), Copy.getValue(1)); if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(), DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1) == DAG.getMachineFunction().getRegInfo().liveout_end()) DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1); - Copy = DAG.getCopyToReg(Copy, ArgReg2, Op.getOperand(3), Copy.getValue(1)); + Copy = DAG.getCopyToReg(Copy, dl, ArgReg2, + Op.getOperand(3), Copy.getValue(1)); if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(), DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2) == DAG.getMachineFunction().getRegInfo().liveout_end()) @@ -349,7 +353,8 @@ break; } } - return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); + return DAG.getNode(AlphaISD::RET_FLAG, dl, + MVT::Other, Copy, Copy.getValue(1)); } std::pair Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=63789&r1=63788&r2=63789&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Wed Feb 4 17:02:30 2009 @@ -1292,6 +1292,7 @@ SmallVector RVLocs; unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); + DebugLoc dl = Op.getDebugLoc(); CCState CCInfo(CC, isVarArg, TM, RVLocs); CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SPU); @@ -1309,14 +1310,15 @@ for (unsigned i = 0; i != RVLocs.size(); ++i) { CCValAssign &VA = RVLocs[i]; assert(VA.isRegLoc() && "Can only return in registers!"); - Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); + Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), + Op.getOperand(i*2+1), Flag); Flag = Chain.getValue(1); } if (Flag.getNode()) - return DAG.getNode(SPUISD::RET_FLAG, MVT::Other, Chain, Flag); + return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain, Flag); else - return DAG.getNode(SPUISD::RET_FLAG, MVT::Other, Chain); + return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain); } @@ -1765,6 +1767,7 @@ SDValue V1 = Op.getOperand(0); SDValue V2 = Op.getOperand(1); SDValue PermMask = Op.getOperand(2); + DebugLoc dl = Op.getDebugLoc(); if (V2.getOpcode() == ISD::UNDEF) V2 = V1; @@ -1839,18 +1842,19 @@ MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Initialize temporary register to 0 SDValue InitTempReg = - DAG.getCopyToReg(DAG.getEntryNode(), VReg, DAG.getConstant(0, PtrVT)); + DAG.getCopyToReg(DAG.getEntryNode(), dl, VReg, DAG.getConstant(0, PtrVT)); // Copy register's contents as index in SHUFFLE_MASK: SDValue ShufMaskOp = - DAG.getNode(SPUISD::SHUFFLE_MASK, MVT::v4i32, + DAG.getNode(SPUISD::SHUFFLE_MASK, dl, MVT::v4i32, DAG.getTargetConstant(V2Elt, MVT::i32), - DAG.getCopyFromReg(InitTempReg, VReg, PtrVT)); + DAG.getCopyFromReg(InitTempReg, dl, VReg, PtrVT)); // Use shuffle mask in SHUFB synthetic instruction: - return DAG.getNode(SPUISD::SHUFB, V1.getValueType(), V2, V1, ShufMaskOp); + return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V2, V1, + ShufMaskOp); } else if (rotate) { int rotamt = (MaxElts - V0Elt) * EltVT.getSizeInBits()/8; - return DAG.getNode(SPUISD::ROTBYTES_LEFT, V1.getValueType(), + return DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, V1.getValueType(), V1, DAG.getConstant(rotamt, MVT::i16)); } else { // Convert the SHUFFLE_VECTOR mask's input element units to the @@ -1871,9 +1875,9 @@ } } - SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, + SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, &ResultMask[0], ResultMask.size()); - return DAG.getNode(SPUISD::SHUFB, V1.getValueType(), V1, V2, VPermMask); + return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V1, V2, VPermMask); } } @@ -2307,6 +2311,7 @@ static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); MVT vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits())); + DebugLoc dl = Op.getDebugLoc(); switch (VT.getSimpleVT()) { default: @@ -2315,10 +2320,10 @@ SDValue N = Op.getOperand(0); SDValue Elt0 = DAG.getConstant(0, MVT::i32); - SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, vecVT, N, N); - SDValue CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote); + SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N); + SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote); - return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i8, CNTB, Elt0); + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i8, CNTB, Elt0); } case MVT::i16: { @@ -2332,22 +2337,22 @@ SDValue Mask0 = DAG.getConstant(0x0f, MVT::i16); SDValue Shift1 = DAG.getConstant(8, MVT::i32); - SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, vecVT, N, N); - SDValue CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote); + SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N); + SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote); // CNTB_result becomes the chain to which all of the virtual registers // CNTB_reg, SUM1_reg become associated: SDValue CNTB_result = - DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, CNTB, Elt0); + DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, CNTB, Elt0); SDValue CNTB_rescopy = - DAG.getCopyToReg(CNTB_result, CNTB_reg, CNTB_result); + DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result); - SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i16); + SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i16); - return DAG.getNode(ISD::AND, MVT::i16, - DAG.getNode(ISD::ADD, MVT::i16, - DAG.getNode(ISD::SRL, MVT::i16, + return DAG.getNode(ISD::AND, dl, MVT::i16, + DAG.getNode(ISD::ADD, dl, MVT::i16, + DAG.getNode(ISD::SRL, dl, MVT::i16, Tmp1, Shift1), Tmp1), Mask0); @@ -2366,37 +2371,38 @@ SDValue Shift1 = DAG.getConstant(16, MVT::i32); SDValue Shift2 = DAG.getConstant(8, MVT::i32); - SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, vecVT, N, N); - SDValue CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote); + SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N); + SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote); // CNTB_result becomes the chain to which all of the virtual registers // CNTB_reg, SUM1_reg become associated: SDValue CNTB_result = - DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, CNTB, Elt0); + DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, CNTB, Elt0); SDValue CNTB_rescopy = - DAG.getCopyToReg(CNTB_result, CNTB_reg, CNTB_result); + DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result); SDValue Comp1 = - DAG.getNode(ISD::SRL, MVT::i32, - DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i32), Shift1); + DAG.getNode(ISD::SRL, dl, MVT::i32, + DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32), + Shift1); SDValue Sum1 = - DAG.getNode(ISD::ADD, MVT::i32, - Comp1, DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i32)); + DAG.getNode(ISD::ADD, dl, MVT::i32, Comp1, + DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32)); SDValue Sum1_rescopy = - DAG.getCopyToReg(CNTB_result, SUM1_reg, Sum1); + DAG.getCopyToReg(CNTB_result, dl, SUM1_reg, Sum1); SDValue Comp2 = - DAG.getNode(ISD::SRL, MVT::i32, - DAG.getCopyFromReg(Sum1_rescopy, SUM1_reg, MVT::i32), + DAG.getNode(ISD::SRL, dl, MVT::i32, + DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32), Shift2); SDValue Sum2 = - DAG.getNode(ISD::ADD, MVT::i32, Comp2, - DAG.getCopyFromReg(Sum1_rescopy, SUM1_reg, MVT::i32)); + DAG.getNode(ISD::ADD, dl, MVT::i32, Comp2, + DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32)); - return DAG.getNode(ISD::AND, MVT::i32, Sum2, Mask0); + return DAG.getNode(ISD::AND, dl, MVT::i32, Sum2, Mask0); } case MVT::i64: Modified: llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp?rev=63789&r1=63788&r2=63789&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp Wed Feb 4 17:02:30 2009 @@ -300,6 +300,7 @@ SDNode *N = Op.getNode(); if (N->isMachineOpcode()) return NULL; // Already selected. + DebugLoc dl = Op.getDebugLoc(); switch (N->getOpcode()) { default: break; @@ -334,22 +335,22 @@ // load the branch target's entry point [mem] and // GP value [mem+8] SDValue targetEntryPoint= - SDValue(CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other, + SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other, FnDescriptor, CurDAG->getEntryNode()), 0); Chain = targetEntryPoint.getValue(1); SDValue targetGPAddr= - SDValue(CurDAG->getTargetNode(IA64::ADDS, MVT::i64, + SDValue(CurDAG->getTargetNode(IA64::ADDS, dl, MVT::i64, FnDescriptor, CurDAG->getConstant(8, MVT::i64)), 0); Chain = targetGPAddr.getValue(1); SDValue targetGP = - SDValue(CurDAG->getTargetNode(IA64::LD8, MVT::i64,MVT::Other, + SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64,MVT::Other, targetGPAddr, CurDAG->getEntryNode()), 0); Chain = targetGP.getValue(1); - Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag); + Chain = CurDAG->getCopyToReg(Chain, dl, IA64::r1, targetGP, InFlag); InFlag = Chain.getValue(1); - Chain = CurDAG->getCopyToReg(Chain, IA64::B6, + Chain = CurDAG->getCopyToReg(Chain, dl, IA64::B6, targetEntryPoint, InFlag); // FLAG these? InFlag = Chain.getValue(1); @@ -359,11 +360,11 @@ // Finally, once everything is setup, emit the call itself if (InFlag.getNode()) - Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, - CallOperand, InFlag), 0); + Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other, + MVT::Flag, CallOperand, InFlag), 0); else // there might be no arguments - Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, - CallOperand, Chain), 0); + Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other, + MVT::Flag, CallOperand, Chain), 0); InFlag = Chain.getValue(1); std::vector CallResults; @@ -378,7 +379,7 @@ case IA64ISD::GETFD: { SDValue Input = N->getOperand(0); - return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input); + return CurDAG->getTargetNode(IA64::GETFD, dl, MVT::i64, Input); } case ISD::FDIV: @@ -394,10 +395,10 @@ SDValue V; ConstantFPSDNode* N2 = cast(N); if (N2->getValueAPF().isPosZero()) { - V = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64); + V = CurDAG->getCopyFromReg(Chain, dl, IA64::F0, MVT::f64); } else if (N2->isExactlyValue(N2->getValueType(0) == MVT::f32 ? APFloat(+1.0f) : APFloat(+1.0))) { - V = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64); + V = CurDAG->getCopyFromReg(Chain, dl, IA64::F1, MVT::f64); } else assert(0 && "Unexpected FP constant!"); @@ -411,7 +412,7 @@ return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64, CurDAG->getTargetFrameIndex(FI, MVT::i64)); else - return CurDAG->getTargetNode(IA64::MOV, MVT::i64, + return CurDAG->getTargetNode(IA64::MOV, dl, MVT::i64, CurDAG->getTargetFrameIndex(FI, MVT::i64)); } @@ -421,7 +422,7 @@ Constant *C = CP->getConstVal(); SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64, CP->getAlignment()); - return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ? + return CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64, // ? CurDAG->getRegister(IA64::r1, MVT::i64), CPI); } @@ -429,10 +430,10 @@ GlobalValue *GV = cast(N)->getGlobal(); SDValue GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64); SDValue Tmp = - SDValue(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, + SDValue(CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64, CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0); - return CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other, Tmp, + return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other, Tmp, CurDAG->getEntryNode()); } @@ -441,11 +442,11 @@ SDValue EA = CurDAG->getTargetExternalSymbol( cast(N)->getSymbol(), MVT::i64); - SDValue Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64, + SDValue Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, dl, MVT::i64, CurDAG->getRegister(IA64::r1, MVT::i64), EA); - return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp); + return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, Tmp); } */ @@ -465,9 +466,11 @@ case MVT::i1: { // this is a bool Opc = IA64::LD1; // first we load a byte, then compare for != 0 if(N->getValueType(0) == MVT::i1) { // XXX: early exit! - return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other, - SDValue(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0), - CurDAG->getRegister(IA64::r0, MVT::i64), + return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other, + SDValue(CurDAG->getTargetNode(Opc, dl, + MVT::i64, + Address), 0), + CurDAG->getRegister(IA64::r0, MVT::i64), Chain); } /* otherwise, we want to load a bool into something bigger: LD1 @@ -499,12 +502,12 @@ case MVT::i1: { // this is a bool Opc = IA64::ST1; // we store either 0 or 1 as a byte // first load zero! - SDValue Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64); + SDValue Initial = CurDAG->getCopyFromReg(Chain, dl, IA64::r0, MVT::i64); Chain = Initial.getValue(1); // then load 1 into the same reg iff the predicate to store is 1 SDValue Tmp = ST->getValue(); Tmp = - SDValue(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial, + SDValue(CurDAG->getTargetNode(IA64::TPCADDS, dl, MVT::i64, Initial, CurDAG->getTargetConstant(1, MVT::i64), Tmp), 0); Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp?rev=63789&r1=63788&r2=63789&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp Wed Feb 4 17:02:30 2009 @@ -197,8 +197,8 @@ // FP args go into f8..f15 as needed: (hence the ++) argPreg[count] = args_FP[used_FPArgs++]; argOpc[count] = IA64::FMOV; - argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], - MVT::f64); + argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), dl, + argVreg[count], MVT::f64); if (I->getType() == Type::FloatTy) argt = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, argt, DAG.getIntPtrConstant(0)); @@ -217,7 +217,7 @@ argPreg[count] = args_int[count]; argOpc[count] = IA64::MOV; argt = newroot = - DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64); + DAG.getCopyFromReg(DAG.getRoot(), dl, argVreg[count], MVT::i64); if ( getValueType(I->getType()) != MVT::i64) argt = DAG.getNode(ISD::TRUNCATE, dl, getValueType(I->getType()), newroot); @@ -423,13 +423,16 @@ SDValue InFlag; // save the current GP, SP and RP : FIXME: do we need to do all 3 always? - SDValue GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag); + SDValue GPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::r1, + MVT::i64, InFlag); Chain = GPBeforeCall.getValue(1); InFlag = Chain.getValue(2); - SDValue SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag); + SDValue SPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::r12, + MVT::i64, InFlag); Chain = SPBeforeCall.getValue(1); InFlag = Chain.getValue(2); - SDValue RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag); + SDValue RPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::rp, + MVT::i64, InFlag); Chain = RPBeforeCall.getValue(1); InFlag = Chain.getValue(2); @@ -444,8 +447,8 @@ unsigned seenConverts = 0; for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { if(RegValuesToPass[i].getValueType().isFloatingPoint()) { - Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++], - InFlag); + Chain = DAG.getCopyToReg(Chain, dl, IntArgRegs[i], + Converts[seenConverts++], InFlag); InFlag = Chain.getValue(1); } } @@ -453,7 +456,7 @@ // next copy args into the usual places, these are flagged unsigned usedFPArgs = 0; for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, + Chain = DAG.getCopyToReg(Chain, dl, RegValuesToPass[i].getValueType().isInteger() ? IntArgRegs[i] : FPArgRegs[usedFPArgs++], RegValuesToPass[i], InFlag); InFlag = Chain.getValue(1); @@ -486,11 +489,11 @@ InFlag = Chain.getValue(1); // restore the GP, SP and RP after the call - Chain = DAG.getCopyToReg(Chain, IA64::r1, GPBeforeCall, InFlag); + Chain = DAG.getCopyToReg(Chain, dl, IA64::r1, GPBeforeCall, InFlag); InFlag = Chain.getValue(1); - Chain = DAG.getCopyToReg(Chain, IA64::r12, SPBeforeCall, InFlag); + Chain = DAG.getCopyToReg(Chain, dl, IA64::r12, SPBeforeCall, InFlag); InFlag = Chain.getValue(1); - Chain = DAG.getCopyToReg(Chain, IA64::rp, RPBeforeCall, InFlag); + Chain = DAG.getCopyToReg(Chain, dl, IA64::rp, RPBeforeCall, InFlag); InFlag = Chain.getValue(1); std::vector RetVals; @@ -505,10 +508,12 @@ case MVT::i1: { // bools are just like other integers (returned in r8) // we *could* fall through to the truncate below, but this saves a // few redundant predicate ops - SDValue boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,InFlag); + SDValue boolInR8 = DAG.getCopyFromReg(Chain, dl, IA64::r8, + MVT::i64,InFlag); InFlag = boolInR8.getValue(2); Chain = boolInR8.getValue(1); - SDValue zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag); + SDValue zeroReg = DAG.getCopyFromReg(Chain, dl, IA64::r0, + MVT::i64, InFlag); InFlag = zeroReg.getValue(2); Chain = zeroReg.getValue(1); @@ -518,7 +523,7 @@ case MVT::i8: case MVT::i16: case MVT::i32: - RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag); + RetVal = DAG.getCopyFromReg(Chain, dl, IA64::r8, MVT::i64, InFlag); Chain = RetVal.getValue(1); // keep track of whether it is sign or zero extended (todo: bools?) @@ -529,18 +534,18 @@ RetVal = DAG.getNode(ISD::TRUNCATE, dl, RetTyVT, RetVal); break; case MVT::i64: - RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag); + RetVal = DAG.getCopyFromReg(Chain, dl, IA64::r8, MVT::i64, InFlag); Chain = RetVal.getValue(1); InFlag = RetVal.getValue(2); // XXX dead break; case MVT::f32: - RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag); + RetVal = DAG.getCopyFromReg(Chain, dl, IA64::F8, MVT::f64, InFlag); Chain = RetVal.getValue(1); RetVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, RetVal, DAG.getIntPtrConstant(0)); break; case MVT::f64: - RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag); + RetVal = DAG.getCopyFromReg(Chain, dl, IA64::F8, MVT::f64, InFlag); Chain = RetVal.getValue(1); InFlag = RetVal.getValue(2); // XXX dead break; Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=63789&r1=63788&r2=63789&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Wed Feb 4 17:02:30 2009 @@ -126,8 +126,9 @@ break; } assert(GP && "GOT PTR not in liveins"); + // FIXME is there a sensible place to get debug info for this? return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), - GP, MVT::i32); + DebugLoc::getUnknownLoc(), GP, MVT::i32); } /// ComplexPattern used on MipsInstrInfo @@ -187,6 +188,7 @@ { SDNode *Node = N.getNode(); unsigned Opcode = Node->getOpcode(); + DebugLoc dl = Node->getDebugLoc(); // Dump information about the Node being selected #ifndef NDEBUG @@ -238,8 +240,8 @@ SDValue RHS = Node->getOperand(1); MVT VT = LHS.getValueType(); - SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, VT, Ops, 2); - SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT, + SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, dl, VT, Ops, 2); + SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, dl, VT, SDValue(Carry,0), RHS); return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, MVT::Flag, @@ -260,13 +262,13 @@ else Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV); - SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2); + SDNode *Node = CurDAG->getTargetNode(Op, dl, MVT::Flag, Op1, Op2); SDValue InFlag = SDValue(Node, 0); - SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, MVT::i32, + SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, dl, MVT::i32, MVT::Flag, InFlag); InFlag = SDValue(Lo,1); - SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, MVT::i32, InFlag); + SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, dl, MVT::i32, InFlag); if (!N.getValue(0).use_empty()) ReplaceUses(N.getValue(0), SDValue(Lo,0)); @@ -285,14 +287,15 @@ SDValue MulOp2 = Node->getOperand(1); unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT); - SDNode *MulNode = CurDAG->getTargetNode(MulOp, MVT::Flag, MulOp1, MulOp2); + SDNode *MulNode = CurDAG->getTargetNode(MulOp, dl, + MVT::Flag, MulOp1, MulOp2); SDValue InFlag = SDValue(MulNode, 0); if (MulOp == ISD::MUL) - return CurDAG->getTargetNode(Mips::MFLO, MVT::i32, InFlag); + return CurDAG->getTargetNode(Mips::MFLO, dl, MVT::i32, InFlag); else - return CurDAG->getTargetNode(Mips::MFHI, MVT::i32, InFlag); + return CurDAG->getTargetNode(Mips::MFHI, dl, MVT::i32, InFlag); } /// Div/Rem operations @@ -311,10 +314,10 @@ Op = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu); MOp = Mips::MFHI; } - SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2); + SDNode *Node = CurDAG->getTargetNode(Op, dl, MVT::Flag, Op1, Op2); SDValue InFlag = SDValue(Node, 0); - return CurDAG->getTargetNode(MOp, MVT::i32, InFlag); + return CurDAG->getTargetNode(MOp, dl, MVT::i32, InFlag); } // Get target GOT address. @@ -344,18 +347,18 @@ // Use load to get GOT target SDValue Ops[] = { Callee, GPReg, Chain }; - SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, MVT::i32, + SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, dl, MVT::i32, MVT::Other, Ops, 3), 0); Chain = Load.getValue(1); // Call target must be on T9 - Chain = CurDAG->getCopyToReg(Chain, T9Reg, Load, InFlag); + Chain = CurDAG->getCopyToReg(Chain, dl, T9Reg, Load, InFlag); } else /// Indirect call - Chain = CurDAG->getCopyToReg(Chain, T9Reg, Callee, InFlag); + Chain = CurDAG->getCopyToReg(Chain, dl, T9Reg, Callee, InFlag); // Emit Jump and Link Register - SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, MVT::Other, + SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, dl, MVT::Other, MVT::Flag, T9Reg, Chain); Chain = SDValue(ResNode, 0); InFlag = SDValue(ResNode, 1); Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=63789&r1=63788&r2=63789&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Feb 4 17:02:30 2009 @@ -367,22 +367,23 @@ { SDValue Chain = Op.getOperand(0); SDValue Size = Op.getOperand(1); + DebugLoc dl = Op.getDebugLoc(); // Get a reference from Mips stack pointer - SDValue StackPointer = DAG.getCopyFromReg(Chain, Mips::SP, MVT::i32); + SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32); // Subtract the dynamic size from the actual stack size to // obtain the new stack size. - SDValue Sub = DAG.getNode(ISD::SUB, MVT::i32, StackPointer, Size); + SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size); // The Sub result contains the new stack start address, so it // must be placed in the stack pointer register. - Chain = DAG.getCopyToReg(StackPointer.getValue(1), Mips::SP, Sub); + Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub); // This node always has two return values: a new stack pointer // value and a chain SDValue Ops[2] = { Sub, Chain }; - return DAG.getMergeValues(Ops, 2); + return DAG.getMergeValues(Ops, 2, dl); } SDValue MipsTargetLowering:: @@ -942,6 +943,7 @@ SmallVector RVLocs; unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); + DebugLoc dl = Op.getDebugLoc(); // CCState - Info about the registers and stack slot. CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs); @@ -968,7 +970,8 @@ // ISD::RET => ret chain, (regnum1,val1), ... // So i*2+1 index only the regnums - Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); + Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), + Op.getOperand(i*2+1), Flag); // guarantee that all emitted copies are // stuck together, avoiding something bad @@ -986,18 +989,18 @@ if (!Reg) assert(0 && "sret virtual register not created in the entry block"); - SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy()); + SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); - Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag); + Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); Flag = Chain.getValue(1); } // Return on Mips is always a "jr $ra" if (Flag.getNode()) - return DAG.getNode(MipsISD::Ret, MVT::Other, + return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); else // Return Void - return DAG.getNode(MipsISD::Ret, MVT::Other, + return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(Mips::RA, MVT::i32)); } Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=63789&r1=63788&r2=63789&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Wed Feb 4 17:02:30 2009 @@ -652,6 +652,7 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) { SDNode *N = Op.getNode(); + DebugLoc dl = N->getDebugLoc(); unsigned Imm; ISD::CondCode CC = cast(N->getOperand(2))->get(); if (isInt32Immediate(N->getOperand(1), Imm)) { @@ -663,13 +664,13 @@ switch (CC) { default: break; case ISD::SETEQ: { - Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0); + Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, dl, MVT::i32, Op), 0); SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } case ISD::SETNE: { SDValue AD = - SDValue(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, + SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, Op, getI32Imm(~0U)), 0); return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1)); @@ -680,8 +681,8 @@ } case ISD::SETGT: { SDValue T = - SDValue(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0); - T = SDValue(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0); + SDValue(CurDAG->getTargetNode(PPC::NEG, dl, MVT::i32, Op), 0); + T = SDValue(CurDAG->getTargetNode(PPC::ANDC, dl, MVT::i32, T, Op), 0); SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } @@ -691,30 +692,32 @@ switch (CC) { default: break; case ISD::SETEQ: - Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, + Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, Op, getI32Imm(1)), 0); return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, - SDValue(CurDAG->getTargetNode(PPC::LI, MVT::i32, - getI32Imm(0)), 0), - Op.getValue(1)); + SDValue(CurDAG->getTargetNode(PPC::LI, dl, + MVT::i32, + getI32Imm(0)), 0), + Op.getValue(1)); case ISD::SETNE: { - Op = SDValue(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0); - SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, + Op = SDValue(CurDAG->getTargetNode(PPC::NOR, dl, MVT::i32, Op, Op), 0); + SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, Op, getI32Imm(~0U)); return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), Op, SDValue(AD, 1)); } case ISD::SETLT: { - SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op, + SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, dl, MVT::i32, Op, getI32Imm(1)), 0); - SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, + SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, dl, MVT::i32, AD, Op), 0); SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } case ISD::SETGT: { SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; - Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0); + Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), + 0); return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1)); } @@ -732,14 +735,14 @@ SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32); SDValue InFlag(0, 0); // Null incoming flag value. - CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg, + CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg, InFlag).getValue(1); if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1) - IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, + IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg, CCReg), 0); else - IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0); + IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, CCReg), 0); SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31), getI32Imm(31), getI32Imm(31) }; @@ -748,7 +751,7 @@ // Get the specified bit. SDValue Tmp = - SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0); + SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); if (Inv) { assert(OtherCondIdx == -1 && "Can't have split plus negation"); return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); @@ -760,7 +763,7 @@ // Get the other bit of the comparison. Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31); SDValue OtherCond = - SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0); + SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond); } Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=63789&r1=63788&r2=63789&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Feb 4 17:02:30 2009 @@ -2625,6 +2625,7 @@ SmallVector RVLocs; unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); + DebugLoc dl = Op.getDebugLoc(); CCState CCInfo(CC, isVarArg, TM, RVLocs); CCInfo.AnalyzeReturn(Op.getNode(), RetCC_PPC); @@ -2662,7 +2663,7 @@ for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) { Operands.push_back(Chain.getOperand(i)); } - return DAG.getNode(PPCISD::TC_RETURN, MVT::Other, &Operands[0], + return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Operands[0], Operands.size()); } @@ -2672,14 +2673,15 @@ for (unsigned i = 0; i != RVLocs.size(); ++i) { CCValAssign &VA = RVLocs[i]; assert(VA.isRegLoc() && "Can only return in registers!"); - Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); + Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), + Op.getOperand(i*2+1), Flag); Flag = Chain.getValue(1); } if (Flag.getNode()) - return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag); + return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag); else - return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain); + return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain); } SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, @@ -4925,6 +4927,7 @@ } SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); // Depths > 0 not supported yet! if (cast(Op.getOperand(0))->getZExtValue() > 0) return SDValue(); @@ -4938,10 +4941,10 @@ && MFI->getStackSize(); if (isPPC64) - return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1, + return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1, MVT::i64); else - return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1, + return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1, MVT::i32); } Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=63789&r1=63788&r2=63789&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Wed Feb 4 17:02:30 2009 @@ -36,6 +36,7 @@ SmallVector RVLocs; unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); + DebugLoc dl = Op.getDebugLoc(); // CCState - Info about the registers and stack slot. CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs); @@ -61,15 +62,16 @@ // ISD::RET => ret chain, (regnum1,val1), ... // So i*2+1 index only the regnums. - Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); + Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), + Op.getOperand(i*2+1), Flag); // Guarantee that all emitted copies are stuck together with flags. Flag = Chain.getValue(1); } if (Flag.getNode()) - return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain, Flag); - return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain); + return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, Flag); + return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain); } /// LowerArguments - V8 uses a very simple ABI, where all values are passed in @@ -871,18 +873,19 @@ static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { SDValue Chain = Op.getOperand(0); // Legalize the chain. SDValue Size = Op.getOperand(1); // Legalize the size. + DebugLoc dl = Op.getDebugLoc(); unsigned SPReg = SP::O6; - SDValue SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32); - SDValue NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value - Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain + SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32); + SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value + Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain // The resultant pointer is actually 16 words from the bottom of the stack, // to provide a register spill area. - SDValue NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, + SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP, DAG.getConstant(96, MVT::i32)); SDValue Ops[2] = { NewVal, Chain }; - return DAG.getMergeValues(Ops, 2); + return DAG.getMergeValues(Ops, 2, dl); } Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=63789&r1=63788&r2=63789&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Wed Feb 4 17:02:30 2009 @@ -369,14 +369,15 @@ } SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); // Depths > 0 not supported yet! if (cast(Op.getOperand(0))->getZExtValue() > 0) return SDValue(); MachineFunction &MF = DAG.getMachineFunction(); const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo(); - return DAG.getCopyFromReg(DAG.getEntryNode(), RegInfo->getFrameRegister(MF), - MVT::i32); + return DAG.getCopyFromReg(DAG.getEntryNode(), dl, + RegInfo->getFrameRegister(MF), MVT::i32); } //===----------------------------------------------------------------------===// @@ -424,6 +425,7 @@ SDValue Chain = TheCall->getChain(); SDValue Callee = TheCall->getCallee(); bool isVarArg = TheCall->isVarArg(); + DebugLoc dl = Op.getDebugLoc(); // Analyze operands of the call, assigning locations to each operand. SmallVector ArgLocs; @@ -456,13 +458,13 @@ default: assert(0 && "Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: - Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); + Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); break; case CCValAssign::ZExt: - Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); + Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); break; case CCValAssign::AExt: - Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); + Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); break; } @@ -475,7 +477,8 @@ int Offset = VA.getLocMemOffset(); - MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, MVT::Other, Chain, Arg, + MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other, + Chain, Arg, DAG.getConstant(Offset/4, MVT::i32))); } } @@ -483,7 +486,7 @@ // Transform all store nodes into one single node because // all store nodes are independent of each other. if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token @@ -492,7 +495,7 @@ // stuck together. SDValue InFlag; for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, + Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } @@ -523,7 +526,7 @@ if (InFlag.getNode()) Ops.push_back(InFlag); - Chain = DAG.getNode(XCoreISD::BL, NodeTys, &Ops[0], Ops.size()); + Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, &Ops[0], Ops.size()); InFlag = Chain.getValue(1); // Create the CALLSEQ_END node. @@ -548,6 +551,7 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall, unsigned CallingConv, SelectionDAG &DAG) { bool isVarArg = TheCall->isVarArg(); + DebugLoc dl = TheCall->getDebugLoc(); // Assign locations to each value returned by this call. SmallVector RVLocs; @@ -558,7 +562,7 @@ // Copy all of the result registers out of their specified physreg. for (unsigned i = 0; i != RVLocs.size(); ++i) { - Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(), + Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), RVLocs[i].getValVT(), InFlag).getValue(1); InFlag = Chain.getValue(2); ResultVals.push_back(Chain.getValue(0)); @@ -567,7 +571,7 @@ ResultVals.push_back(Chain); // Merge everything together with a MERGE_VALUES node. - return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(), &ResultVals[0], ResultVals.size()).getNode(); } @@ -718,6 +722,7 @@ SmallVector RVLocs; unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); + DebugLoc dl = Op.getDebugLoc(); // CCState - Info about the registers and stack slot. CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs); @@ -744,7 +749,8 @@ // ISD::RET => ret chain, (regnum1,val1), ... // So i*2+1 index only the regnums - Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); + Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), + Op.getOperand(i*2+1), Flag); // guarantee that all emitted copies are // stuck together, avoiding something bad @@ -753,10 +759,10 @@ // Return on XCore is always a "retsp 0" if (Flag.getNode()) - return DAG.getNode(XCoreISD::RETSP, MVT::Other, + return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, Chain, DAG.getConstant(0, MVT::i32), Flag); else // Return Void - return DAG.getNode(XCoreISD::RETSP, MVT::Other, + return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, Chain, DAG.getConstant(0, MVT::i32)); } Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=63789&r1=63788&r2=63789&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Wed Feb 4 17:02:30 2009 @@ -1395,6 +1395,7 @@ } std::string Decl = (!ResNodeDecled) ? "SDNode *" : ""; emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" + ChainName + + ", " + RootName + ".getDebugLoc()" + ", " + getQualifiedName(RR) + ", " + RootName + utostr(OpNo) + ", InFlag).getNode();"); ResNodeDecled = true; From tonic at nondot.org Wed Feb 4 17:12:25 2009 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 04 Feb 2009 23:12:25 -0000 Subject: [llvm-commits] [llvm] r63790 - in /llvm/branches/release_25: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll test/Transforms/ScalarRepl/2006-11-07-InvalidArrayPromote.ll test/Transforms/ScalarRepl/bitfield-sroa.ll test/Transforms/ScalarRepl/memset-aggregate.ll test/Transforms/ScalarRepl/vector_promote.ll Message-ID: <200902042312.n14NCPDc022257@zion.cs.uiuc.edu> Author: tbrethou Date: Wed Feb 4 17:12:25 2009 New Revision: 63790 URL: http://llvm.org/viewvc/llvm-project?rev=63790&view=rev Log: SROA CBE Fix. Modified: llvm/branches/release_25/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/branches/release_25/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll llvm/branches/release_25/test/Transforms/ScalarRepl/2006-11-07-InvalidArrayPromote.ll llvm/branches/release_25/test/Transforms/ScalarRepl/bitfield-sroa.ll llvm/branches/release_25/test/Transforms/ScalarRepl/memset-aggregate.ll llvm/branches/release_25/test/Transforms/ScalarRepl/vector_promote.ll Modified: llvm/branches/release_25/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=63790&r1=63789&r2=63790&view=diff ============================================================================== --- llvm/branches/release_25/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/branches/release_25/lib/Transforms/Scalar/ScalarReplAggregates.cpp Wed Feb 4 17:12:25 2009 @@ -125,13 +125,13 @@ void RewriteLoadUserOfWholeAlloca(LoadInst *LI, AllocationInst *AI, SmallVector &NewElts); - bool CanConvertToScalar(Value *V, bool &IsNotTrivial, const Type *&VecTy, - uint64_t Offset, unsigned AllocaSize); - void ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, uint64_t Offset); + const Type *CanConvertToScalar(Value *V, bool &IsNotTrivial); + void ConvertToScalar(AllocationInst *AI, const Type *Ty); + void ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, unsigned Offset); Value *ConvertUsesOfLoadToScalar(LoadInst *LI, AllocaInst *NewAI, - uint64_t Offset); - Value *ConvertUsesOfStoreToScalar(Value *StoredVal, AllocaInst *NewAI, - uint64_t Offset, Instruction *InsertPt); + unsigned Offset); + Value *ConvertUsesOfStoreToScalar(StoreInst *SI, AllocaInst *NewAI, + unsigned Offset); static Instruction *isOnlyCopiedFromConstantGlobal(AllocationInst *AI); }; } @@ -223,38 +223,17 @@ AI->eraseFromParent(); continue; } - - // If this alloca is impossible for us to promote, reject it early. - if (AI->isArrayAllocation() || !AI->getAllocatedType()->isSized()) - continue; - - // Check to see if this allocation is only modified by a memcpy/memmove from - // a constant global. If this is the case, we can change all users to use - // the constant global instead. This is commonly produced by the CFE by - // constructs like "void foo() { int A[] = {1,2,3,4,5,6,7,8,9...}; }" if 'A' - // is only subsequently read. - if (Instruction *TheCopy = isOnlyCopiedFromConstantGlobal(AI)) { - DOUT << "Found alloca equal to global: " << *AI; - DOUT << " memcpy = " << *TheCopy; - Constant *TheSrc = cast(TheCopy->getOperand(2)); - AI->replaceAllUsesWith(ConstantExpr::getBitCast(TheSrc, AI->getType())); - TheCopy->eraseFromParent(); // Don't mutate the global. - AI->eraseFromParent(); - ++NumGlobals; - Changed = true; - continue; - } // Check to see if we can perform the core SROA transformation. We cannot // transform the allocation instruction if it is an array allocation // (allocations OF arrays are ok though), and an allocation of a scalar // value cannot be decomposed at all. - uint64_t AllocaSize = TD->getTypePaddedSize(AI->getAllocatedType()); - - if ((isa(AI->getAllocatedType()) || + if (!AI->isArrayAllocation() && + (isa(AI->getAllocatedType()) || isa(AI->getAllocatedType())) && - // Do not promote any struct whose size is too big. - AllocaSize < SRThreshold && + AI->getAllocatedType()->isSized() && + // Do not promote any struct whose size is larger than "128" bytes. + TD->getTypePaddedSize(AI->getAllocatedType()) < SRThreshold && // Do not promote any struct into more than "32" separate vars. getNumSAElements(AI->getAllocatedType()) < SRThreshold/4) { // Check that all of the users of the allocation are capable of being @@ -272,40 +251,35 @@ continue; } } + + // Check to see if this allocation is only modified by a memcpy/memmove from + // a constant global. If this is the case, we can change all users to use + // the constant global instead. This is commonly produced by the CFE by + // constructs like "void foo() { int A[] = {1,2,3,4,5,6,7,8,9...}; }" if 'A' + // is only subsequently read. + if (Instruction *TheCopy = isOnlyCopiedFromConstantGlobal(AI)) { + DOUT << "Found alloca equal to global: " << *AI; + DOUT << " memcpy = " << *TheCopy; + Constant *TheSrc = cast(TheCopy->getOperand(2)); + AI->replaceAllUsesWith(ConstantExpr::getBitCast(TheSrc, AI->getType())); + TheCopy->eraseFromParent(); // Don't mutate the global. + AI->eraseFromParent(); + ++NumGlobals; + Changed = true; + continue; + } // If we can turn this aggregate value (potentially with casts) into a // simple scalar value that can be mem2reg'd into a register value. - // IsNotTrivial tracks whether this is something that mem2reg could have - // promoted itself. If so, we don't want to transform it needlessly. Note - // that we can't just check based on the type: the alloca may be of an i32 - // but that has pointer arithmetic to set byte 3 of it or something. bool IsNotTrivial = false; - const Type *VectorTy = 0; - if (CanConvertToScalar(AI, IsNotTrivial, VectorTy, - 0, unsigned(AllocaSize)) && IsNotTrivial) { - AllocaInst *NewAI; - if (VectorTy && isa(VectorTy)) { - DOUT << "CONVERT TO VECTOR: " << *AI << " TYPE = " << *VectorTy <<"\n"; - - // Create and insert the vector alloca. - NewAI = new AllocaInst(VectorTy, 0, "", AI->getParent()->begin()); - ConvertUsesToScalar(AI, NewAI, 0); - } else { - DOUT << "CONVERT TO SCALAR INTEGER: " << *AI << "\n"; - - // Create and insert the integer alloca. - const Type *NewTy = IntegerType::get(AllocaSize*8); - NewAI = new AllocaInst(NewTy, 0, "", AI->getParent()->begin()); - ConvertUsesToScalar(AI, NewAI, 0); + if (const Type *ActualType = CanConvertToScalar(AI, IsNotTrivial)) + if (IsNotTrivial && ActualType != Type::VoidTy) { + ConvertToScalar(AI, ActualType); + Changed = true; + continue; } - NewAI->takeName(AI); - AI->eraseFromParent(); - ++NumConverted; - Changed = true; - continue; - } - // Otherwise, couldn't process this alloca. + // Otherwise, couldn't process this. } return Changed; @@ -1171,126 +1145,229 @@ } } -/// MergeInType - Add the 'In' type to the accumulated type (Accum) so far at -/// the offset specified by Offset (which is specified in bytes). +/// MergeInType - Add the 'In' type to the accumulated type so far. If the +/// types are incompatible, return true, otherwise update Accum and return +/// false. /// -/// There are two cases we handle here: -/// 1) A union of vector types of the same size and potentially its elements. +/// There are three cases we handle here: +/// 1) An effectively-integer union, where the pieces are stored into as +/// smaller integers (common with byte swap and other idioms). +/// 2) A union of vector types of the same size and potentially its elements. /// Here we turn element accesses into insert/extract element operations. -/// This promotes a <4 x float> with a store of float to the third element -/// into a <4 x float> that uses insert element. -/// 2) A fully general blob of memory, which we turn into some (potentially -/// large) integer type with extract and insert operations where the loads -/// and stores would mutate the memory. -static void MergeInType(const Type *In, uint64_t Offset, const Type *&VecTy, - unsigned AllocaSize, const TargetData &TD) { - // If this could be contributing to a vector, analyze it. - if (VecTy != Type::VoidTy) { // either null or a vector type. - - // If the In type is a vector that is the same size as the alloca, see if it - // matches the existing VecTy. - if (const VectorType *VInTy = dyn_cast(In)) { - if (VInTy->getBitWidth()/8 == AllocaSize && Offset == 0) { - // If we're storing/loading a vector of the right size, allow it as a - // vector. If this the first vector we see, remember the type so that - // we know the element size. - if (VecTy == 0) - VecTy = VInTy; - return; - } - } else if (In == Type::FloatTy || In == Type::DoubleTy || - (isa(In) && In->getPrimitiveSizeInBits() >= 8 && - isPowerOf2_32(In->getPrimitiveSizeInBits()))) { - // If we're accessing something that could be an element of a vector, see - // if the implied vector agrees with what we already have and if Offset is - // compatible with it. - unsigned EltSize = In->getPrimitiveSizeInBits()/8; - if (Offset % EltSize == 0 && - AllocaSize % EltSize == 0 && - (VecTy == 0 || - cast(VecTy)->getElementType() - ->getPrimitiveSizeInBits()/8 == EltSize)) { - if (VecTy == 0) - VecTy = VectorType::get(In, AllocaSize/EltSize); - return; - } +/// 3) A union of scalar types, such as int/float or int/pointer. Here we +/// merge together into integers, allowing the xform to work with #1 as +/// well. +static bool MergeInType(const Type *In, const Type *&Accum, + const TargetData &TD) { + // If this is our first type, just use it. + const VectorType *PTy; + if (Accum == Type::VoidTy || In == Accum) { + Accum = In; + } else if (In == Type::VoidTy) { + // Noop. + } else if (In->isInteger() && Accum->isInteger()) { // integer union. + // Otherwise pick whichever type is larger. + if (cast(In)->getBitWidth() > + cast(Accum)->getBitWidth()) + Accum = In; + } else if (isa(In) && isa(Accum)) { + // Pointer unions just stay as one of the pointers. + } else if (isa(In) || isa(Accum)) { + if ((PTy = dyn_cast(Accum)) && + PTy->getElementType() == In) { + // Accum is a vector, and we are accessing an element: ok. + } else if ((PTy = dyn_cast(In)) && + PTy->getElementType() == Accum) { + // In is a vector, and accum is an element: ok, remember In. + Accum = In; + } else if ((PTy = dyn_cast(In)) && isa(Accum) && + PTy->getBitWidth() == cast(Accum)->getBitWidth()) { + // Two vectors of the same size: keep Accum. + } else { + // Cannot insert an short into a <4 x int> or handle + // <2 x int> -> <4 x int> + return true; } + } else { + // Pointer/FP/Integer unions merge together as integers. + switch (Accum->getTypeID()) { + case Type::PointerTyID: Accum = TD.getIntPtrType(); break; + case Type::FloatTyID: Accum = Type::Int32Ty; break; + case Type::DoubleTyID: Accum = Type::Int64Ty; break; + case Type::X86_FP80TyID: return true; + case Type::FP128TyID: return true; + case Type::PPC_FP128TyID: return true; + default: + assert(Accum->isInteger() && "Unknown FP type!"); + break; + } + + switch (In->getTypeID()) { + case Type::PointerTyID: In = TD.getIntPtrType(); break; + case Type::FloatTyID: In = Type::Int32Ty; break; + case Type::DoubleTyID: In = Type::Int64Ty; break; + case Type::X86_FP80TyID: return true; + case Type::FP128TyID: return true; + case Type::PPC_FP128TyID: return true; + default: + assert(In->isInteger() && "Unknown FP type!"); + break; + } + return MergeInType(In, Accum, TD); } - - // Otherwise, we have a case that we can't handle with an optimized vector - // form. We can still turn this into a large integer. - VecTy = Type::VoidTy; -} - -/// CanConvertToScalar - V is a pointer. If we can convert the pointee and all -/// its accesses to use a to single vector type, return true, and set VecTy to -/// the new type. If we could convert the alloca into a single promotable -/// integer, return true but set VecTy to VoidTy. Further, if the use is not a -/// completely trivial use that mem2reg could promote, set IsNotTrivial. Offset -/// is the current offset from the base of the alloca being analyzed. + return false; +} + +/// getIntAtLeastAsBigAs - Return an integer type that is at least as big as the +/// specified type. If there is no suitable type, this returns null. +const Type *getIntAtLeastAsBigAs(unsigned NumBits) { + if (NumBits > 64) return 0; + if (NumBits > 32) return Type::Int64Ty; + if (NumBits > 16) return Type::Int32Ty; + if (NumBits > 8) return Type::Int16Ty; + return Type::Int8Ty; +} + +/// CanConvertToScalar - V is a pointer. If we can convert the pointee to a +/// single scalar integer type, return that type. Further, if the use is not +/// a completely trivial use that mem2reg could promote, set IsNotTrivial. If +/// there are no uses of this pointer, return Type::VoidTy to differentiate from +/// failure. /// -bool SROA::CanConvertToScalar(Value *V, bool &IsNotTrivial, - const Type *&VecTy, uint64_t Offset, - unsigned AllocaSize) { +const Type *SROA::CanConvertToScalar(Value *V, bool &IsNotTrivial) { + const Type *UsedType = Type::VoidTy; // No uses, no forced type. + const PointerType *PTy = cast(V->getType()); + for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI!=E; ++UI) { Instruction *User = cast(*UI); if (LoadInst *LI = dyn_cast(User)) { - // Don't break volatile loads. if (LI->isVolatile()) - return false; - MergeInType(LI->getType(), Offset, VecTy, AllocaSize, *TD); + return 0; + + // FIXME: Loads of a first class aggregrate value could be converted to a + // series of loads and insertvalues + if (!LI->getType()->isSingleValueType()) + return 0; + + if (MergeInType(LI->getType(), UsedType, *TD)) + return 0; continue; } if (StoreInst *SI = dyn_cast(User)) { // Storing the pointer, not into the value? if (SI->getOperand(0) == V || SI->isVolatile()) return 0; - MergeInType(SI->getOperand(0)->getType(), Offset, VecTy, AllocaSize, *TD); + + // FIXME: Stores of a first class aggregrate value could be converted to a + // series of extractvalues and stores + if (!SI->getOperand(0)->getType()->isSingleValueType()) + return 0; + + // NOTE: We could handle storing of FP imms into integers here! + + if (MergeInType(SI->getOperand(0)->getType(), UsedType, *TD)) + return 0; continue; } - - if (BitCastInst *BCI = dyn_cast(User)) { - if (!CanConvertToScalar(BCI, IsNotTrivial, VecTy, Offset, AllocaSize)) - return false; + if (BitCastInst *CI = dyn_cast(User)) { IsNotTrivial = true; + const Type *SubTy = CanConvertToScalar(CI, IsNotTrivial); + if (!SubTy || MergeInType(SubTy, UsedType, *TD)) return 0; continue; } if (GetElementPtrInst *GEP = dyn_cast(User)) { - // If this is a GEP with a variable indices, we can't handle it. - if (!GEP->hasAllConstantIndices()) - return false; + // Check to see if this is stepping over an element: GEP Ptr, int C + if (GEP->getNumOperands() == 2 && isa(GEP->getOperand(1))) { + unsigned Idx = cast(GEP->getOperand(1))->getZExtValue(); + unsigned ElSize = TD->getTypePaddedSize(PTy->getElementType()); + unsigned BitOffset = Idx*ElSize*8; + if (BitOffset > 64 || !isPowerOf2_32(ElSize)) return 0; + + IsNotTrivial = true; + const Type *SubElt = CanConvertToScalar(GEP, IsNotTrivial); + if (SubElt == 0) return 0; + if (SubElt != Type::VoidTy && SubElt->isInteger()) { + const Type *NewTy = + getIntAtLeastAsBigAs(TD->getTypePaddedSizeInBits(SubElt)+BitOffset); + if (NewTy == 0 || MergeInType(NewTy, UsedType, *TD)) return 0; + continue; + } + // Cannot handle this! + return 0; + } - // Compute the offset that this GEP adds to the pointer. - SmallVector Indices(GEP->op_begin()+1, GEP->op_end()); - uint64_t GEPOffset = TD->getIndexedOffset(GEP->getOperand(0)->getType(), - &Indices[0], Indices.size()); - // See if all uses can be converted. - if (!CanConvertToScalar(GEP, IsNotTrivial, VecTy, Offset+GEPOffset, - AllocaSize)) - return false; - IsNotTrivial = true; - continue; - } - - // If this is a constant sized memset of a constant value (e.g. 0) we can - // handle it. - if (isa(User) && - // Store of constant value. - isa(User->getOperand(2)) && - // Store with constant size. - isa(User->getOperand(3))) { - VecTy = Type::VoidTy; - IsNotTrivial = true; - continue; + if (GEP->getNumOperands() == 3 && + isa(GEP->getOperand(1)) && + isa(GEP->getOperand(2)) && + cast(GEP->getOperand(1))->isZero()) { + // We are stepping into an element, e.g. a structure or an array: + // GEP Ptr, i32 0, i32 Cst + const Type *AggTy = PTy->getElementType(); + unsigned Idx = cast(GEP->getOperand(2))->getZExtValue(); + + if (const ArrayType *ATy = dyn_cast(AggTy)) { + if (Idx >= ATy->getNumElements()) return 0; // Out of range. + } else if (const VectorType *VectorTy = dyn_cast(AggTy)) { + // Getting an element of the vector. + if (Idx >= VectorTy->getNumElements()) return 0; // Out of range. + + // Merge in the vector type. + if (MergeInType(VectorTy, UsedType, *TD)) return 0; + + const Type *SubTy = CanConvertToScalar(GEP, IsNotTrivial); + if (SubTy == 0) return 0; + + if (SubTy != Type::VoidTy && MergeInType(SubTy, UsedType, *TD)) + return 0; + + // We'll need to change this to an insert/extract element operation. + IsNotTrivial = true; + continue; // Everything looks ok + + } else if (isa(AggTy)) { + // Structs are always ok. + } else { + return 0; + } + const Type *NTy = + getIntAtLeastAsBigAs(TD->getTypePaddedSizeInBits(AggTy)); + if (NTy == 0 || MergeInType(NTy, UsedType, *TD)) return 0; + const Type *SubTy = CanConvertToScalar(GEP, IsNotTrivial); + if (SubTy == 0) return 0; + if (SubTy != Type::VoidTy && MergeInType(SubTy, UsedType, *TD)) + return 0; + continue; // Everything looks ok + } + return 0; } - // Otherwise, we cannot handle this! - return false; + // Cannot handle this! + return 0; } - return true; + return UsedType; +} + +/// ConvertToScalar - The specified alloca passes the CanConvertToScalar +/// predicate and is non-trivial. Convert it to something that can be trivially +/// promoted into a register by mem2reg. +void SROA::ConvertToScalar(AllocationInst *AI, const Type *ActualTy) { + DOUT << "CONVERT TO SCALAR: " << *AI << " TYPE = " + << *ActualTy << "\n"; + ++NumConverted; + + BasicBlock *EntryBlock = AI->getParent(); + assert(EntryBlock == &EntryBlock->getParent()->getEntryBlock() && + "Not in the entry block!"); + EntryBlock->getInstList().remove(AI); // Take the alloca out of the program. + + // Create and insert the alloca. + AllocaInst *NewAI = new AllocaInst(ActualTy, 0, AI->getName(), + EntryBlock->begin()); + ConvertUsesToScalar(AI, NewAI, 0); + delete AI; } @@ -1301,87 +1378,105 @@ /// /// Offset is an offset from the original alloca, in bits that need to be /// shifted to the right. By the end of this, there should be no uses of Ptr. -void SROA::ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, uint64_t Offset) { +void SROA::ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, unsigned Offset) { while (!Ptr->use_empty()) { Instruction *User = cast(Ptr->use_back()); - + if (LoadInst *LI = dyn_cast(User)) { - LI->replaceAllUsesWith(ConvertUsesOfLoadToScalar(LI, NewAI, Offset)); + Value *NV = ConvertUsesOfLoadToScalar(LI, NewAI, Offset); + LI->replaceAllUsesWith(NV); LI->eraseFromParent(); continue; } - + if (StoreInst *SI = dyn_cast(User)) { assert(SI->getOperand(0) != Ptr && "Consistency error!"); - new StoreInst(ConvertUsesOfStoreToScalar(SI->getOperand(0), NewAI, - Offset, SI), NewAI, SI); + + Value *SV = ConvertUsesOfStoreToScalar(SI, NewAI, Offset); + new StoreInst(SV, NewAI, SI); SI->eraseFromParent(); continue; } - + if (BitCastInst *CI = dyn_cast(User)) { ConvertUsesToScalar(CI, NewAI, Offset); CI->eraseFromParent(); continue; } - - if (GetElementPtrInst *GEP = dyn_cast(User)) { - // Compute the offset that this GEP adds to the pointer. - SmallVector Indices(GEP->op_begin()+1, GEP->op_end()); - uint64_t GEPOffset = TD->getIndexedOffset(GEP->getOperand(0)->getType(), - &Indices[0], Indices.size()); - ConvertUsesToScalar(GEP, NewAI, Offset+GEPOffset*8); - GEP->eraseFromParent(); - continue; - } - // If this is a constant sized memset of a constant value (e.g. 0) we can - // transform it into a store of the expanded constant value. - if (MemSetInst *MSI = dyn_cast(User)) { - assert(MSI->getRawDest() == Ptr && "Consistency error!"); - unsigned NumBytes = cast(MSI->getLength())->getZExtValue(); - unsigned Val = cast(MSI->getValue())->getZExtValue(); + if (GetElementPtrInst *GEP = dyn_cast(User)) { + const PointerType *AggPtrTy = + cast(GEP->getOperand(0)->getType()); + unsigned AggSizeInBits = + TD->getTypePaddedSizeInBits(AggPtrTy->getElementType()); + + // Check to see if this is stepping over an element: GEP Ptr, int C + unsigned NewOffset = Offset; + if (GEP->getNumOperands() == 2) { + unsigned Idx = cast(GEP->getOperand(1))->getZExtValue(); + unsigned BitOffset = Idx*AggSizeInBits; + + NewOffset += BitOffset; + ConvertUsesToScalar(GEP, NewAI, NewOffset); + GEP->eraseFromParent(); + continue; + } - // Compute the value replicated the right number of times. - APInt APVal(NumBytes*8, Val); - - // Splat the value if non-zero. - if (Val) - for (unsigned i = 1; i != NumBytes; ++i) - APVal |= APVal << 8; + assert(GEP->getNumOperands() == 3 && "Unsupported operation"); - new StoreInst(ConvertUsesOfStoreToScalar(ConstantInt::get(APVal), NewAI, - Offset, MSI), NewAI, MSI); - MSI->eraseFromParent(); + // We know that operand #2 is zero. + unsigned Idx = cast(GEP->getOperand(2))->getZExtValue(); + const Type *AggTy = AggPtrTy->getElementType(); + if (const SequentialType *SeqTy = dyn_cast(AggTy)) { + unsigned ElSizeBits = + TD->getTypePaddedSizeInBits(SeqTy->getElementType()); + + NewOffset += ElSizeBits*Idx; + } else { + const StructType *STy = cast(AggTy); + unsigned EltBitOffset = + TD->getStructLayout(STy)->getElementOffsetInBits(Idx); + + NewOffset += EltBitOffset; + } + ConvertUsesToScalar(GEP, NewAI, NewOffset); + GEP->eraseFromParent(); continue; } - assert(0 && "Unsupported operation!"); abort(); } } -/// ConvertUsesOfLoadToScalar - Convert all of the users of the specified load -/// to use the new alloca directly, returning the value that should replace the -/// load. This happens when we are converting an "integer union" to a single -/// integer scalar, or when we are converting a "vector union" to a vector with -/// insert/extractelement instructions. +/// ConvertUsesOfLoadToScalar - Convert all of the users the specified load to +/// use the new alloca directly, returning the value that should replace the +/// load. This happens when we are converting an "integer union" to a +/// single integer scalar, or when we are converting a "vector union" to a +/// vector with insert/extractelement instructions. /// /// Offset is an offset from the original alloca, in bits that need to be /// shifted to the right. By the end of this, there should be no uses of Ptr. -Value *SROA::ConvertUsesOfLoadToScalar(LoadInst *LI, AllocaInst *NewAI, - uint64_t Offset) { +Value *SROA::ConvertUsesOfLoadToScalar(LoadInst *LI, AllocaInst *NewAI, + unsigned Offset) { // The load is a bit extract from NewAI shifted right by Offset bits. Value *NV = new LoadInst(NewAI, LI->getName(), LI); - - // If the load is of the whole new alloca, no conversion is needed. - if (NV->getType() == LI->getType() && Offset == 0) + + if (NV->getType() == LI->getType() && Offset == 0) { + // We win, no conversion needed. return NV; + } - // If the result alloca is a vector type, this is either an element - // access or a bitcast to another vector type of the same size. + // If the result type of the 'union' is a pointer, then this must be ptr->ptr + // cast. Anything else would result in NV being an integer. + if (isa(NV->getType())) { + assert(isa(LI->getType())); + return new BitCastInst(NV, LI->getType(), LI->getName(), LI); + } + if (const VectorType *VTy = dyn_cast(NV->getType())) { + // If the result alloca is a vector type, this is either an element + // access or a bitcast to another vector type. if (isa(LI->getType())) return new BitCastInst(NV, LI->getType(), LI->getName(), LI); @@ -1390,19 +1485,18 @@ if (Offset) { unsigned EltSize = TD->getTypePaddedSizeInBits(VTy->getElementType()); Elt = Offset/EltSize; - assert(EltSize*Elt == Offset && "Invalid modulus in validity checking"); + Offset -= EltSize*Elt; } - // Return the element extracted out of it. - Value *V = new ExtractElementInst(NV, ConstantInt::get(Type::Int32Ty, Elt), - "tmp", LI); - if (V->getType() != LI->getType()) - V = new BitCastInst(V, LI->getType(), "tmp", LI); - return V; + NV = new ExtractElementInst(NV, ConstantInt::get(Type::Int32Ty, Elt), + "tmp", LI); + + // If we're done, return this element. + if (NV->getType() == LI->getType() && Offset == 0) + return NV; } - - // Otherwise, this must be a union that was converted to an integer value. + const IntegerType *NTy = cast(NV->getType()); - + // If this is a big-endian system and the load is narrower than the // full alloca type, we need to do a shift to get the right bits. int ShAmt = 0; @@ -1415,30 +1509,29 @@ } else { ShAmt = Offset; } - + // Note: we support negative bitwidths (with shl) which are not defined. // We do this to support (f.e.) loads off the end of a structure where // only some bits are used. if (ShAmt > 0 && (unsigned)ShAmt < NTy->getBitWidth()) - NV = BinaryOperator::CreateLShr(NV, - ConstantInt::get(NV->getType(), ShAmt), + NV = BinaryOperator::CreateLShr(NV, + ConstantInt::get(NV->getType(),ShAmt), LI->getName(), LI); else if (ShAmt < 0 && (unsigned)-ShAmt < NTy->getBitWidth()) - NV = BinaryOperator::CreateShl(NV, - ConstantInt::get(NV->getType(), -ShAmt), + NV = BinaryOperator::CreateShl(NV, + ConstantInt::get(NV->getType(),-ShAmt), LI->getName(), LI); - + // Finally, unconditionally truncate the integer to the right width. unsigned LIBitWidth = TD->getTypeSizeInBits(LI->getType()); if (LIBitWidth < NTy->getBitWidth()) NV = new TruncInst(NV, IntegerType::get(LIBitWidth), LI->getName(), LI); - + // If the result is an integer, this is a trunc or bitcast. if (isa(LI->getType())) { // Should be done. - } else if (LI->getType()->isFloatingPoint() || - isa(LI->getType())) { + } else if (LI->getType()->isFloatingPoint()) { // Just do a bitcast, we know the sizes match up. NV = new BitCastInst(NV, LI->getType(), LI->getName(), LI); } else { @@ -1458,100 +1551,90 @@ /// /// Offset is an offset from the original alloca, in bits that need to be /// shifted to the right. By the end of this, there should be no uses of Ptr. -Value *SROA::ConvertUsesOfStoreToScalar(Value *SV, AllocaInst *NewAI, - uint64_t Offset, Instruction *IP) { - +Value *SROA::ConvertUsesOfStoreToScalar(StoreInst *SI, AllocaInst *NewAI, + unsigned Offset) { + // Convert the stored type to the actual type, shift it left to insert // then 'or' into place. + Value *SV = SI->getOperand(0); const Type *AllocaType = NewAI->getType()->getElementType(); - if (SV->getType() == AllocaType && Offset == 0) - return SV; - - if (const VectorType *VTy = dyn_cast(AllocaType)) { - Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", IP); - + if (SV->getType() == AllocaType && Offset == 0) { + // All is well. + } else if (const VectorType *PTy = dyn_cast(AllocaType)) { + Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", SI); + // If the result alloca is a vector type, this is either an element // access or a bitcast to another vector type. if (isa(SV->getType())) { - SV = new BitCastInst(SV, AllocaType, SV->getName(), IP); + SV = new BitCastInst(SV, AllocaType, SV->getName(), SI); } else { // Must be an element insertion. - unsigned Elt = Offset/TD->getTypePaddedSizeInBits(VTy->getElementType()); - - if (SV->getType() != VTy->getElementType()) - SV = new BitCastInst(SV, VTy->getElementType(), "tmp", IP); - + unsigned Elt = Offset/TD->getTypePaddedSizeInBits(PTy->getElementType()); SV = InsertElementInst::Create(Old, SV, ConstantInt::get(Type::Int32Ty, Elt), - "tmp", IP); - } - return SV; - } - - - Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", IP); - - // If SV is a float, convert it to the appropriate integer type. - // If it is a pointer, do the same, and also handle ptr->ptr casts - // here. - unsigned SrcWidth = TD->getTypeSizeInBits(SV->getType()); - unsigned DestWidth = TD->getTypeSizeInBits(AllocaType); - unsigned SrcStoreWidth = TD->getTypeStoreSizeInBits(SV->getType()); - unsigned DestStoreWidth = TD->getTypeStoreSizeInBits(AllocaType); - if (SV->getType()->isFloatingPoint() || isa(SV->getType())) - SV = new BitCastInst(SV, IntegerType::get(SrcWidth), SV->getName(), IP); - else if (isa(SV->getType())) - SV = new PtrToIntInst(SV, TD->getIntPtrType(), SV->getName(), IP); - - // Zero extend or truncate the value if needed. - if (SV->getType() != AllocaType) { - if (SV->getType()->getPrimitiveSizeInBits() < - AllocaType->getPrimitiveSizeInBits()) - SV = new ZExtInst(SV, AllocaType, SV->getName(), IP); - else { - // Truncation may be needed if storing more than the alloca can hold - // (undefined behavior). - SV = new TruncInst(SV, AllocaType, SV->getName(), IP); - SrcWidth = DestWidth; - SrcStoreWidth = DestStoreWidth; + "tmp", SI); } - } - - // If this is a big-endian system and the store is narrower than the - // full alloca type, we need to do a shift to get the right bits. - int ShAmt = 0; - if (TD->isBigEndian()) { - // On big-endian machines, the lowest bit is stored at the bit offset - // from the pointer given by getTypeStoreSizeInBits. This matters for - // integers with a bitwidth that is not a multiple of 8. - ShAmt = DestStoreWidth - SrcStoreWidth - Offset; + } else if (isa(AllocaType)) { + // If the alloca type is a pointer, then all the elements must be + // pointers. + if (SV->getType() != AllocaType) + SV = new BitCastInst(SV, AllocaType, SV->getName(), SI); } else { - ShAmt = Offset; - } - - // Note: we support negative bitwidths (with shr) which are not defined. - // We do this to support (f.e.) stores off the end of a structure where - // only some bits in the structure are set. - APInt Mask(APInt::getLowBitsSet(DestWidth, SrcWidth)); - if (ShAmt > 0 && (unsigned)ShAmt < DestWidth) { - SV = BinaryOperator::CreateShl(SV, - ConstantInt::get(SV->getType(), ShAmt), - SV->getName(), IP); - Mask <<= ShAmt; - } else if (ShAmt < 0 && (unsigned)-ShAmt < DestWidth) { - SV = BinaryOperator::CreateLShr(SV, - ConstantInt::get(SV->getType(), -ShAmt), - SV->getName(), IP); - Mask = Mask.lshr(-ShAmt); - } - - // Mask out the bits we are about to insert from the old value, and or - // in the new bits. - if (SrcWidth != DestWidth) { - assert(DestWidth > SrcWidth); - Old = BinaryOperator::CreateAnd(Old, ConstantInt::get(~Mask), - Old->getName()+".mask", IP); - SV = BinaryOperator::CreateOr(Old, SV, SV->getName()+".ins", IP); + Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", SI); + + // If SV is a float, convert it to the appropriate integer type. + // If it is a pointer, do the same, and also handle ptr->ptr casts + // here. + unsigned SrcWidth = TD->getTypeSizeInBits(SV->getType()); + unsigned DestWidth = TD->getTypeSizeInBits(AllocaType); + unsigned SrcStoreWidth = TD->getTypeStoreSizeInBits(SV->getType()); + unsigned DestStoreWidth = TD->getTypeStoreSizeInBits(AllocaType); + if (SV->getType()->isFloatingPoint()) + SV = new BitCastInst(SV, IntegerType::get(SrcWidth), + SV->getName(), SI); + else if (isa(SV->getType())) + SV = new PtrToIntInst(SV, TD->getIntPtrType(), SV->getName(), SI); + + // Always zero extend the value if needed. + if (SV->getType() != AllocaType) + SV = new ZExtInst(SV, AllocaType, SV->getName(), SI); + + // If this is a big-endian system and the store is narrower than the + // full alloca type, we need to do a shift to get the right bits. + int ShAmt = 0; + if (TD->isBigEndian()) { + // On big-endian machines, the lowest bit is stored at the bit offset + // from the pointer given by getTypeStoreSizeInBits. This matters for + // integers with a bitwidth that is not a multiple of 8. + ShAmt = DestStoreWidth - SrcStoreWidth - Offset; + } else { + ShAmt = Offset; + } + + // Note: we support negative bitwidths (with shr) which are not defined. + // We do this to support (f.e.) stores off the end of a structure where + // only some bits in the structure are set. + APInt Mask(APInt::getLowBitsSet(DestWidth, SrcWidth)); + if (ShAmt > 0 && (unsigned)ShAmt < DestWidth) { + SV = BinaryOperator::CreateShl(SV, + ConstantInt::get(SV->getType(), ShAmt), + SV->getName(), SI); + Mask <<= ShAmt; + } else if (ShAmt < 0 && (unsigned)-ShAmt < DestWidth) { + SV = BinaryOperator::CreateLShr(SV, + ConstantInt::get(SV->getType(),-ShAmt), + SV->getName(), SI); + Mask = Mask.lshr(ShAmt); + } + + // Mask out the bits we are about to insert from the old value, and or + // in the new bits. + if (SrcWidth != DestWidth) { + assert(DestWidth > SrcWidth); + Old = BinaryOperator::CreateAnd(Old, ConstantInt::get(~Mask), + Old->getName()+".mask", SI); + SV = BinaryOperator::CreateOr(Old, SV, SV->getName()+".ins", SI); + } } return SV; } Modified: llvm/branches/release_25/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll?rev=63790&r1=63789&r2=63790&view=diff ============================================================================== --- llvm/branches/release_25/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll (original) +++ llvm/branches/release_25/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll Wed Feb 4 17:12:25 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | opt -scalarrepl -instcombine | llvm-dis | grep {ret i32 undef} +; RUN: echo disabled ; Test that an array is not incorrectly deconstructed. Modified: llvm/branches/release_25/test/Transforms/ScalarRepl/2006-11-07-InvalidArrayPromote.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/test/Transforms/ScalarRepl/2006-11-07-InvalidArrayPromote.ll?rev=63790&r1=63789&r2=63790&view=diff ============================================================================== --- llvm/branches/release_25/test/Transforms/ScalarRepl/2006-11-07-InvalidArrayPromote.ll (original) +++ llvm/branches/release_25/test/Transforms/ScalarRepl/2006-11-07-InvalidArrayPromote.ll Wed Feb 4 17:12:25 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | not grep alloca +; RUN: echo disabled define i32 @func(<4 x float> %v0, <4 x float> %v1) nounwind { %vsiidx = alloca [2 x <4 x i32>], align 16 ; <[2 x <4 x i32>]*> [#uses=3] Modified: llvm/branches/release_25/test/Transforms/ScalarRepl/bitfield-sroa.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/test/Transforms/ScalarRepl/bitfield-sroa.ll?rev=63790&r1=63789&r2=63790&view=diff ============================================================================== --- llvm/branches/release_25/test/Transforms/ScalarRepl/bitfield-sroa.ll (original) +++ llvm/branches/release_25/test/Transforms/ScalarRepl/bitfield-sroa.ll Wed Feb 4 17:12:25 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | not grep alloca +; RUN: echo disabled ; rdar://6532315 %t = type { { i32, i16, i8, i8 } } Modified: llvm/branches/release_25/test/Transforms/ScalarRepl/memset-aggregate.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/test/Transforms/ScalarRepl/memset-aggregate.ll?rev=63790&r1=63789&r2=63790&view=diff ============================================================================== --- llvm/branches/release_25/test/Transforms/ScalarRepl/memset-aggregate.ll (original) +++ llvm/branches/release_25/test/Transforms/ScalarRepl/memset-aggregate.ll Wed Feb 4 17:12:25 2009 @@ -1,7 +1,6 @@ ; PR1226 ; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | grep {ret i32 16843009} ; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | not grep alloca -; RUN: llvm-as < %s | opt -scalarrepl -instcombine | llvm-dis | grep {ret i16 514} target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" target triple = "i686-apple-darwin8" @@ -49,18 +48,3 @@ } - %struct.f = type { i32, i32, i32, i32, i32, i32 } - -define i16 @test4() nounwind { -entry: - %A = alloca %struct.f, align 8 ; <%struct.f*> [#uses=3] - %0 = getelementptr %struct.f* %A, i32 0, i32 0 ; [#uses=1] - store i32 1, i32* %0, align 8 - %1 = getelementptr %struct.f* %A, i32 0, i32 1 ; [#uses=1] - %2 = bitcast i32* %1 to i8* ; [#uses=1] - call void @llvm.memset.i32(i8* %2, i8 2, i32 12, i32 4) - %3 = getelementptr %struct.f* %A, i32 0, i32 2 ; [#uses=1] - %4 = load i32* %3, align 8 ; [#uses=1] - %retval12 = trunc i32 %4 to i16 ; [#uses=1] - ret i16 %retval12 -} Modified: llvm/branches/release_25/test/Transforms/ScalarRepl/vector_promote.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/test/Transforms/ScalarRepl/vector_promote.ll?rev=63790&r1=63789&r2=63790&view=diff ============================================================================== --- llvm/branches/release_25/test/Transforms/ScalarRepl/vector_promote.ll (original) +++ llvm/branches/release_25/test/Transforms/ScalarRepl/vector_promote.ll Wed Feb 4 17:12:25 2009 @@ -53,12 +53,3 @@ ret void } -define i32 @test5(float %X) { ;; should turn into bitcast. - %X_addr = alloca [4 x float] - %X1 = getelementptr [4 x float]* %X_addr, i32 0, i32 2 - store float %X, float* %X1 - %a = bitcast float* %X1 to i32* - %tmp = load i32* %a - ret i32 %tmp -} - From tonic at nondot.org Wed Feb 4 17:14:59 2009 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 04 Feb 2009 23:14:59 -0000 Subject: [llvm-commits] [llvm] r63791 - /llvm/branches/release_25/lib/Analysis/ScalarEvolution.cpp Message-ID: <200902042314.n14NEx4R022390@zion.cs.uiuc.edu> Author: tbrethou Date: Wed Feb 4 17:14:59 2009 New Revision: 63791 URL: http://llvm.org/viewvc/llvm-project?rev=63791&view=rev Log: Back out r62958 from the release branch. Modified: llvm/branches/release_25/lib/Analysis/ScalarEvolution.cpp Modified: llvm/branches/release_25/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Analysis/ScalarEvolution.cpp?rev=63791&r1=63790&r2=63791&view=diff ============================================================================== --- llvm/branches/release_25/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/branches/release_25/lib/Analysis/ScalarEvolution.cpp Wed Feb 4 17:14:59 2009 @@ -585,7 +585,17 @@ } // We need at least W + T bits for the multiplication step - unsigned CalculationBits = W + T; + // FIXME: A temporary hack; we round up the bitwidths + // to the nearest power of 2 to be nice to the code generator. + unsigned CalculationBits = 1U << Log2_32_Ceil(W + T); + // FIXME: Temporary hack to avoid generating integers that are too wide. + // Although, it's not completely clear how to determine how much + // widening is safe; for example, on X86, we can't really widen + // beyond 64 because we need to be able to do multiplication + // that's CalculationBits wide, but on X86-64, we can safely widen up to + // 128 bits. + if (CalculationBits > 64) + return new SCEVCouldNotCompute(); // Calcuate 2^T, at width T+W. APInt DivFactor = APInt(CalculationBits, 1).shl(T); From tonic at nondot.org Wed Feb 4 17:16:46 2009 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 04 Feb 2009 23:16:46 -0000 Subject: [llvm-commits] [llvm] r63792 - /llvm/branches/release_25/lib/Target/X86/X86Subtarget.cpp Message-ID: <200902042316.n14NGktQ022465@zion.cs.uiuc.edu> Author: tbrethou Date: Wed Feb 4 17:16:46 2009 New Revision: 63792 URL: http://llvm.org/viewvc/llvm-project?rev=63792&view=rev Log: Merge from mainline. Tevert part of the x86 subtarget logic changes: when -march=x86-64 is given, override the subtarget settings and enable 64-bit support. This restores the earlier behavior, and fixes regressions on Non-64-bit-capable x86-32 hosts. This isn't necessarily the best approach, but the most obvious alternative is to require -mcpu=x86-64 or -mattr=+64bit to be used with -march=x86-64 when the host doesn't have 64-bit support. This makes things little more consistent, but it's less convenient, and it has the practical drawback of requiring lots of test changes, so I opted for the above approach for now. Modified: llvm/branches/release_25/lib/Target/X86/X86Subtarget.cpp Modified: llvm/branches/release_25/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Target/X86/X86Subtarget.cpp?rev=63792&r1=63791&r2=63792&view=diff ============================================================================== --- llvm/branches/release_25/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/branches/release_25/lib/Target/X86/X86Subtarget.cpp Wed Feb 4 17:16:46 2009 @@ -327,15 +327,16 @@ } else { // Otherwise, use CPUID to auto-detect feature set. AutoDetectSubtargetFeatures(); - // If requesting codegen for X86-64, make sure that 64-bit features - // are enabled. - if (Is64Bit) - HasX86_64 = true; // Make sure SSE2 is enabled; it is available on all X86-64 CPUs. if (Is64Bit && X86SSELevel < SSE2) X86SSELevel = SSE2; } + // If requesting codegen for X86-64, make sure that 64-bit features + // are enabled. + if (Is64Bit) + HasX86_64 = true; + DOUT << "Subtarget features: SSELevel " << X86SSELevel << ", 3DNowLevel " << X863DNowLevel << ", 64bit " << HasX86_64 << "\n"; From tonic at nondot.org Wed Feb 4 17:20:50 2009 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 04 Feb 2009 23:20:50 -0000 Subject: [llvm-commits] [llvm] r63793 - in /llvm/branches/release_25/lib/CodeGen/SelectionDAG: SelectionDAG.cpp SelectionDAGISel.cpp Message-ID: <200902042320.n14NKoZ4022631@zion.cs.uiuc.edu> Author: tbrethou Date: Wed Feb 4 17:20:50 2009 New Revision: 63793 URL: http://llvm.org/viewvc/llvm-project?rev=63793&view=rev Log: Merge from mainline. First initialize DAG otherwise dwarf writer is used uninitialized. Duncan spotted this. Thanks! Modified: llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63793&r1=63792&r2=63793&view=diff ============================================================================== --- llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Feb 4 17:20:50 2009 @@ -787,7 +787,7 @@ } SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) - : TLI(tli), FLI(fli), + : TLI(tli), FLI(fli), DW(0), EntryNode(ISD::EntryToken, getVTList(MVT::Other)), Root(getEntryNode()) { AllNodes.push_back(&EntryNode); Modified: llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=63793&r1=63792&r2=63793&view=diff ============================================================================== --- llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/branches/release_25/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Feb 4 17:20:50 2009 @@ -313,10 +313,10 @@ RegInfo = &MF->getRegInfo(); DOUT << "\n\n\n=== " << Fn.getName() << "\n"; - FuncInfo->set(Fn, *MF, *CurDAG, EnableFastISel); MachineModuleInfo *MMI = getAnalysisIfAvailable(); DwarfWriter *DW = getAnalysisIfAvailable(); CurDAG->init(*MF, MMI, DW); + FuncInfo->set(Fn, *MF, *CurDAG, EnableFastISel); SDL->init(GFI, *AA); for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) From kremenek at apple.com Wed Feb 4 17:50:59 2009 From: kremenek at apple.com (Ted Kremenek) Date: Wed, 04 Feb 2009 23:50:59 -0000 Subject: [llvm-commits] [llvm] r63797 - /llvm/tags/checker/checker-0.149/ Message-ID: <200902042350.n14NoxQu023619@zion.cs.uiuc.edu> Author: kremenek Date: Wed Feb 4 17:50:58 2009 New Revision: 63797 URL: http://llvm.org/viewvc/llvm-project?rev=63797&view=rev Log: Tagging checker-0.149. Added: llvm/tags/checker/checker-0.149/ - copied from r63796, llvm/trunk/ From dalej at apple.com Wed Feb 4 18:20:10 2009 From: dalej at apple.com (Dale Johannesen) Date: Thu, 05 Feb 2009 00:20:10 -0000 Subject: [llvm-commits] [llvm] r63800 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp lib/Target/PIC16/PIC16ISelLowering.cpp lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200902050020.n150KB7c024577@zion.cs.uiuc.edu> Author: johannes Date: Wed Feb 4 18:20:09 2009 New Revision: 63800 URL: http://llvm.org/viewvc/llvm-project?rev=63800&view=rev Log: Remove non-DebugLoc versions of getMergeValues, ZeroExtendInReg. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63800&r1=63799&r2=63800&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Feb 4 18:20:09 2009 @@ -371,7 +371,6 @@ /// getZeroExtendInReg - Return the expression required to zero extend the Op /// value assuming it was the smaller SrcTy value. - SDValue getZeroExtendInReg(SDValue Op, MVT SrcTy); SDValue getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT SrcTy); /// getNOT - Create a bitwise NOT operation as (XOR Val, -1). @@ -537,7 +536,6 @@ bool ReadMem = true, bool WriteMem = true); /// getMergeValues - Create a MERGE_VALUES node from the given operands. - SDValue getMergeValues(const SDValue *Ops, unsigned NumOps); SDValue getMergeValues(const SDValue *Ops, unsigned NumOps, DebugLoc dl); /// getCall - Create a CALL node from the given information. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=63800&r1=63799&r2=63800&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Wed Feb 4 18:20:09 2009 @@ -389,7 +389,7 @@ return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, DAG.getValueType(N->getOperand(0).getValueType())); if (N->getOpcode() == ISD::ZERO_EXTEND) - return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType()); + return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType()); assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); return Res; } @@ -573,7 +573,7 @@ // Calculate the overflow flag: zero extend the arithmetic result from // the original type. - SDValue Ofl = DAG.getZeroExtendInReg(Res, OVT); + SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT); // Overflowed if and only if this is not equal to Res. Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); @@ -853,10 +853,11 @@ SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { SDValue NewOps[6]; + DebugLoc dl = N->getDebugLoc(); NewOps[0] = N->getOperand(0); for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { SDValue Flag = GetPromotedInteger(N->getOperand(i)); - NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1); + NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1); } return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps, array_lengthof(NewOps)); @@ -941,9 +942,10 @@ } SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { + DebugLoc dl = N->getDebugLoc(); SDValue Op = GetPromotedInteger(N->getOperand(0)); - Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); - return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType()); + Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); + return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType()); } @@ -1905,7 +1907,7 @@ SplitInteger(Res, Lo, Hi); unsigned ExcessBits = Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); - Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits)); + Hi = DAG.getZeroExtendInReg(Hi, dl, MVT::getIntegerVT(ExcessBits)); } } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=63800&r1=63799&r2=63800&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Wed Feb 4 18:20:09 2009 @@ -231,8 +231,9 @@ /// final size. SDValue SExtPromotedInteger(SDValue Op) { MVT OldVT = Op.getValueType(); + DebugLoc dl = Op.getDebugLoc(); Op = GetPromotedInteger(Op); - return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, + return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op, DAG.getValueType(OldVT)); } @@ -240,8 +241,9 @@ /// final size. SDValue ZExtPromotedInteger(SDValue Op) { MVT OldVT = Op.getValueType(); + DebugLoc dl = Op.getDebugLoc(); Op = GetPromotedInteger(Op); - return DAG.getZeroExtendInReg(Op, OldVT); + return DAG.getZeroExtendInReg(Op, dl, OldVT); } // Integer Result Promotion. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63800&r1=63799&r2=63800&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Feb 4 18:20:09 2009 @@ -829,14 +829,6 @@ Root = getEntryNode(); } -SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) { - if (Op.getValueType() == VT) return Op; - APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), - VT.getSizeInBits()); - return getNode(ISD::AND, Op.getValueType(), Op, - getConstant(Imm, Op.getValueType())); -} - SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) { if (Op.getValueType() == VT) return Op; APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), @@ -3463,18 +3455,6 @@ /// getMergeValues - Create a MERGE_VALUES node from the given operands. /// Allowed to return something different (and simpler) if Simplify is true. -SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps) { - if (NumOps == 1) - return Ops[0]; - - SmallVector VTs; - VTs.reserve(NumOps); - for (unsigned i = 0; i < NumOps; ++i) - VTs.push_back(Ops[i].getValueType()); - return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps); -} - -/// DebugLoc-aware version. SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, DebugLoc dl) { if (NumOps == 1) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63800&r1=63799&r2=63800&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Wed Feb 4 18:20:09 2009 @@ -882,7 +882,8 @@ for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) Constants.push_back(SDValue(Val, i)); } - return DAG.getMergeValues(&Constants[0], Constants.size()); + return DAG.getMergeValues(&Constants[0], Constants.size(), + getCurDebugLoc()); } if (isa(C->getType()) || isa(C->getType())) { @@ -904,7 +905,7 @@ else Constants[i] = DAG.getConstant(0, EltVT); } - return DAG.getMergeValues(&Constants[0], NumElts); + return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc()); } const VectorType *VecTy = cast(V->getType()); @@ -5786,7 +5787,8 @@ ComputeValueVTs(TLI, AI->getType(), ValueVTs); unsigned NumValues = ValueVTs.size(); if (!AI->use_empty()) { - SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues)); + SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues, + SDL->getCurDebugLoc())); // If this argument is live outside of the entry block, insert a copy from // whereever we got it to the vreg that other BB's will reference it as. DenseMap::iterator VMI=FuncInfo->ValueMap.find(AI); Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=63800&r1=63799&r2=63800&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Wed Feb 4 18:20:09 2009 @@ -926,6 +926,7 @@ SDValue InFlag, SelectionDAG &DAG) { CallSDNode *TheCall = dyn_cast(Op); + DebugLoc dl = TheCall->getDebugLoc(); // Currently handling primitive types only. They will come in // i8 parts unsigned RetVals = TheCall->getNumRetVals(); @@ -948,7 +949,7 @@ for(unsigned i=0, Offset=0;i Author: djg Date: Wed Feb 4 18:24:30 2009 New Revision: 63801 URL: http://llvm.org/viewvc/llvm-project?rev=63801&view=rev Log: Use "-mllvm -disable-llvm-optzns" instead of -O0 to disable preliminary optimizations when LTO is being used. The front-end behaves differently at -O0. Modified: test-suite/trunk/Makefile.rules Modified: test-suite/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.rules?rev=63801&r1=63800&r2=63801&view=diff ============================================================================== --- test-suite/trunk/Makefile.rules (original) +++ test-suite/trunk/Makefile.rules Wed Feb 4 18:24:30 2009 @@ -321,12 +321,14 @@ # Default optimization level: OPTFLAGS := -O3 -# If LTO is on, compile each .c .cpp file with -O0 and optimize with -# opt and llvm-ld. +# If LTO is on, compile each .c .cpp file with -mllvm -disable-llvm-optzns. +# This is similar to -O0, except it just disables optimizations and doesn't +# change the behavior of the front-end. Optimization will be done separately +# with opt and llvm-ld. ifdef DISABLE_LTO LOPTFLAGS := $(OPTFLAGS) else -LOPTFLAGS := -O0 +LOPTFLAGS := $(OPTFLAGS) -mllvm -disable-llvm-optzns endif From dpatel at apple.com Wed Feb 4 18:30:44 2009 From: dpatel at apple.com (Devang Patel) Date: Thu, 05 Feb 2009 00:30:44 -0000 Subject: [llvm-commits] [llvm] r63802 - in /llvm/trunk: lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch-dbg.ll Message-ID: <200902050030.n150UiI9024936@zion.cs.uiuc.edu> Author: dpatel Date: Wed Feb 4 18:30:42 2009 New Revision: 63802 URL: http://llvm.org/viewvc/llvm-project?rev=63802&view=rev Log: Ignore dbg intrinsics while folding switch instruction. Added: llvm/trunk/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch-dbg.ll Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=63802&r1=63801&r2=63802&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed Feb 4 18:30:42 2009 @@ -1330,6 +1330,20 @@ return true; } +/// isTerminatorFirstRelevantInsn - Return true if Term is very first +/// instruction ignoring Phi nodes and dbg intrinsics. +static bool isTerminatorFirstRelevantInsn(BasicBlock *BB, Instruction *Term) { + BasicBlock::iterator BBI = Term; + while (BBI != BB->begin()) { + --BBI; + if (!isa(BBI)) + break; + } + if (isa(BBI) || &*BBI == Term) + return true; + return false; +} + /// SimplifyCondBranchToTwoReturns - If we found a conditional branch that goes /// to two returning blocks, try to merge them together into one return, /// introducing a select if the return values disagree. @@ -1343,12 +1357,10 @@ // Check to ensure both blocks are empty (just a return) or optionally empty // with PHI nodes. If there are other instructions, merging would cause extra // computation on one path or the other. - BasicBlock::iterator BBI = TrueRet; - if (BBI != TrueSucc->begin() && !isa(--BBI)) - return false; // Not empty with optional phi nodes. - BBI = FalseRet; - if (BBI != FalseSucc->begin() && !isa(--BBI)) - return false; // Not empty with optional phi nodes. + if (!isTerminatorFirstRelevantInsn(TrueSucc, TrueRet)) + return false; + if (!isTerminatorFirstRelevantInsn(FalseSucc, FalseRet)) + return false; // Okay, we found a branch that is going to two return nodes. If // there is no return value for this function, just change the @@ -1750,8 +1762,7 @@ // different return values, fold the replace the branch/return with a select // and return. if (ReturnInst *RI = dyn_cast(BB->getTerminator())) { - BasicBlock::iterator BBI = BB->getTerminator(); - if (BBI == BB->begin() || isa(--BBI)) { + if (isTerminatorFirstRelevantInsn(BB, BB->getTerminator())) { // Find predecessors that end with branches. SmallVector UncondBranchPreds; SmallVector CondBranchPreds; Added: llvm/trunk/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch-dbg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch-dbg.ll?rev=63802&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch-dbg.ll (added) +++ llvm/trunk/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch-dbg.ll Wed Feb 4 18:30:42 2009 @@ -0,0 +1,58 @@ +; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | \ +; RUN: not grep switch + + + %llvm.dbg.anchor.type = type { i32, i32 } + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } + + at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata" ; + + at .str = internal constant [4 x i8] c"a.c\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at .str1 = internal constant [6 x i8] c"/tmp/\00", section "llvm.metadata" ; <[6 x i8]*> [#uses=1] + at .str2 = internal constant [55 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build 00)\00", section "llvm.metadata" ; <[55 x i8]*> [#uses=1] + at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([6 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([55 x i8]* @.str2, i32 0, i32 0), i1 true, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] + +declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind + +; Test folding all to same dest +define i32 @test3(i1 %C) { + br i1 %C, label %Start, label %TheDest +Start: ; preds = %0 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + switch i32 3, label %TheDest [ + i32 0, label %TheDest + i32 1, label %TheDest + i32 2, label %TheDest + i32 5, label %TheDest + ] +TheDest: ; preds = %Start, %Start, %Start, %Start, %Start, %0 + ret i32 1234 +} + +; Test folding switch -> branch +define i32 @test4(i32 %C) { + switch i32 %C, label %L1 [ + i32 0, label %L2 + ] +L1: ; preds = %0 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + ret i32 0 +L2: ; preds = %0 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + ret i32 1 +} + +; Can fold into a cond branch! +define i32 @test5(i32 %C) { + switch i32 %C, label %L1 [ + i32 0, label %L2 + i32 123, label %L1 + ] +L1: ; preds = %0, %0 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + ret i32 0 +L2: ; preds = %0 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + ret i32 1 +} + From kremenek at apple.com Wed Feb 4 18:38:11 2009 From: kremenek at apple.com (Ted Kremenek) Date: Thu, 05 Feb 2009 00:38:11 -0000 Subject: [llvm-commits] [llvm] r63804 - /llvm/tags/checker/checker-0.149/ Message-ID: <200902050038.n150cBaX025202@zion.cs.uiuc.edu> Author: kremenek Date: Wed Feb 4 18:38:11 2009 New Revision: 63804 URL: http://llvm.org/viewvc/llvm-project?rev=63804&view=rev Log: Removing checker-0.149. Removed: llvm/tags/checker/checker-0.149/ From kremenek at apple.com Wed Feb 4 18:38:45 2009 From: kremenek at apple.com (Ted Kremenek) Date: Thu, 05 Feb 2009 00:38:45 -0000 Subject: [llvm-commits] [llvm] r63806 - /llvm/tags/checker/checker-0.149/ Message-ID: <200902050038.n150cjfa025252@zion.cs.uiuc.edu> Author: kremenek Date: Wed Feb 4 18:38:44 2009 New Revision: 63806 URL: http://llvm.org/viewvc/llvm-project?rev=63806&view=rev Log: Tagging checker-0.149. Added: llvm/tags/checker/checker-0.149/ - copied from r63805, llvm/trunk/ From dalej at apple.com Wed Feb 4 19:01:16 2009 From: dalej at apple.com (Dale Johannesen) Date: Thu, 05 Feb 2009 01:01:16 -0000 Subject: [llvm-commits] [llvm] r63808 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/Target/PIC16/PIC16ISelLowering.cpp lib/Target/PIC16/PIC16ISelLowering.h lib/Target/XCore/XCoreISelLowering.cpp Message-ID: <200902050101.n1511HsW026071@zion.cs.uiuc.edu> Author: johannes Date: Wed Feb 4 19:01:16 2009 New Revision: 63808 URL: http://llvm.org/viewvc/llvm-project?rev=63808&view=rev Log: Get rid of 3 non-DebugLoc getNode variants. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63808&r1=63807&r2=63808&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Feb 4 19:01:16 2009 @@ -449,17 +449,10 @@ SDValue getNode(unsigned Opcode, SDVTList VTs, SDValue N1, SDValue N2); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N1, SDValue N2); - SDValue getNode(unsigned Opcode, SDVTList VTs, - SDValue N1, SDValue N2, SDValue N3); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N1, SDValue N2, SDValue N3); - SDValue getNode(unsigned Opcode, SDVTList VTs, - SDValue N1, SDValue N2, SDValue N3, SDValue N4); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N1, SDValue N2, SDValue N3, SDValue N4); - SDValue getNode(unsigned Opcode, SDVTList VTs, - SDValue N1, SDValue N2, SDValue N3, SDValue N4, - SDValue N5); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63808&r1=63807&r2=63808&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Feb 4 19:01:16 2009 @@ -3924,23 +3924,12 @@ return getNode(Opcode, DL, VTList, Ops, 2); } -SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, - SDValue N1, SDValue N2, SDValue N3) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2, N3); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3) { SDValue Ops[] = { N1, N2, N3 }; return getNode(Opcode, DL, VTList, Ops, 3); } -SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, - SDValue N1, SDValue N2, SDValue N3, - SDValue N4) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2, N3, N4); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4) { @@ -3948,12 +3937,6 @@ return getNode(Opcode, DL, VTList, Ops, 4); } -SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, - SDValue N1, SDValue N2, SDValue N3, - SDValue N4, SDValue N5) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2, N3, N4, N5); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) { Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=63808&r1=63807&r2=63808&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Wed Feb 4 19:01:16 2009 @@ -631,6 +631,7 @@ LoadSDNode *LD = dyn_cast(SDValue(N, 0)); SDValue Chain = LD->getChain(); SDValue Ptr = LD->getBasePtr(); + DebugLoc dl = LD->getDebugLoc(); SDValue Load, Offset; SDVTList Tys; @@ -653,7 +654,7 @@ // Add the pointer offset if any Offset = DAG.getConstant(iter + LoadOffset, MVT::i8); Tys = DAG.getVTList(MVT::i8, MVT::Other); - Load = DAG.getNode(PIC16ISD::PIC16Load, Tys, Chain, PtrLo, PtrHi, + Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi, Offset); PICLoads.push_back(Load); } @@ -675,7 +676,7 @@ for (iter=0; iter(Op); SDValue Chain = TheCall->getChain(); SDValue Callee = TheCall->getCallee(); + DebugLoc dl = TheCall->getDebugLoc(); unsigned i =0; if (Callee.getValueType() == MVT::i16 && Callee.getOpcode() == ISD::BUILD_PAIR) { @@ -1006,7 +1011,7 @@ SDVTList VTs = DAG.getVTList(&NodeTys[0], NodeTys.size()); SDValue NewCall = - DAG.getCall(TheCall->getCallingConv(), TheCall->getDebugLoc(), + DAG.getCall(TheCall->getCallingConv(), dl, TheCall->isVarArg(), TheCall->isTailCall(), TheCall->isInreg(), VTs, &Ops[0], Ops.size()); @@ -1061,7 +1066,7 @@ OperFlag = getOutFlag(CallArgs); SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); - SDValue PICCall = DAG.getNode(PIC16ISD::CALL, Tys, Chain, Callee, + SDValue PICCall = DAG.getNode(PIC16ISD::CALL, dl, Tys, Chain, Callee, OperFlag); Chain = getChain(PICCall); OperFlag = getOutFlag(PICCall); @@ -1108,14 +1113,15 @@ } SDValue PIC16TargetLowering:: LowerBinOp(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); // We should have handled larger operands in type legalizer itself. assert (Op.getValueType() == MVT::i8 && "illegal Op to lower"); unsigned MemOp = 1; if (NeedToConvertToMemOp(Op, MemOp)) { // Put one value on stack. - SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG); + SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl); - return DAG.getNode(Op.getOpcode(), MVT::i8, Op.getOperand(MemOp ^ 1), + return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1), NewVal); } else { @@ -1126,18 +1132,20 @@ SDValue PIC16TargetLowering:: LowerADD(SDValue Op, SelectionDAG &DAG) { // We should have handled larger operands in type legalizer itself. assert (Op.getValueType() == MVT::i8 && "illegal add to lower"); + DebugLoc dl = Op.getDebugLoc(); unsigned MemOp = 1; if (NeedToConvertToMemOp(Op, MemOp)) { // Put one value on stack. - SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG); + SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl); SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag); if (Op.getOpcode() == ISD::ADDE) - return DAG.getNode(Op.getOpcode(), Tys, Op.getOperand(MemOp ^ 1), NewVal, - Op.getOperand(2)); + return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1), + NewVal, Op.getOperand(2)); else - return DAG.getNode(Op.getOpcode(), Tys, Op.getOperand(MemOp ^ 1), NewVal); + return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1), + NewVal); } else if (Op.getOpcode() == ISD::ADD) { return Op; @@ -1148,6 +1156,7 @@ } SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); // We should have handled larger operands in type legalizer itself. assert (Op.getValueType() == MVT::i8 && "illegal sub to lower"); @@ -1157,14 +1166,14 @@ return SDValue(); // Put first operand on stack. - SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG); + SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG, dl); SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag); if (Op.getOpcode() == ISD::SUBE) - return DAG.getNode(Op.getOpcode(), Tys, NewVal, Op.getOperand(1), + return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1), Op.getOperand(2)); else - return DAG.getNode(Op.getOpcode(), Tys, NewVal, Op.getOperand(1)); + return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1)); } // LowerFORMAL_ARGUMENTS - In Lowering FORMAL ARGUMENTS - MERGE_VALUES nodes @@ -1249,7 +1258,7 @@ // Returns appropriate CMP insn and corresponding condition code in PIC16CC SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS, unsigned CC, SDValue &PIC16CC, - SelectionDAG &DAG) { + SelectionDAG &DAG, DebugLoc dl) { PIC16CC::CondCodes CondCode = (PIC16CC::CondCodes) CC; // PIC16 sub is literal - W. So Swap the operands and condition if needed. @@ -1294,8 +1303,8 @@ // These are signed comparisons. SDValue Mask = DAG.getConstant(128, MVT::i8); if (isSignedComparison(CondCode)) { - LHS = DAG.getNode (ISD::XOR, MVT::i8, LHS, Mask); - RHS = DAG.getNode (ISD::XOR, MVT::i8, RHS, Mask); + LHS = DAG.getNode (ISD::XOR, dl, MVT::i8, LHS, Mask); + RHS = DAG.getNode (ISD::XOR, dl, MVT::i8, RHS, Mask); } SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag); @@ -1305,11 +1314,11 @@ // for subwf and literal for sublw) and it is used by this operation only. if ((LHS.getOpcode() == ISD::Constant || isDirectLoad(LHS)) && LHS.hasOneUse()) - return DAG.getNode(PIC16ISD::SUBCC, VTs, LHS, RHS); + return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS); // else convert the first operand to mem. - LHS = ConvertToMemOperand (LHS, DAG); - return DAG.getNode(PIC16ISD::SUBCC, VTs, LHS, RHS); + LHS = ConvertToMemOperand (LHS, DAG, dl); + return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS); } @@ -1320,6 +1329,7 @@ SDValue TrueVal = Op.getOperand(2); SDValue FalseVal = Op.getOperand(3); unsigned ORIGCC = ~0; + DebugLoc dl = Op.getDebugLoc(); // If this is a select_cc of a "setcc", and if the setcc got lowered into // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. @@ -1332,9 +1342,9 @@ if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC); SDValue PIC16CC; - SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG); + SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl); - return DAG.getNode (PIC16ISD::SELECT_ICC, TrueVal.getValueType(), TrueVal, + return DAG.getNode (PIC16ISD::SELECT_ICC, dl, TrueVal.getValueType(), TrueVal, FalseVal, PIC16CC, Cmp.getValue(1)); } @@ -1400,6 +1410,7 @@ SDValue RHS = Op.getOperand(3); // RHS of the condition. SDValue Dest = Op.getOperand(4); // BB to jump to unsigned ORIGCC = ~0; + DebugLoc dl = Op.getDebugLoc(); // If this is a br_cc of a "setcc", and if the setcc got lowered into // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. @@ -1408,9 +1419,9 @@ // Get the Compare insn and condition code. SDValue PIC16CC; - SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG); + SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl); - return DAG.getNode(PIC16ISD::BRCOND, MVT::Other, Chain, Dest, PIC16CC, + return DAG.getNode(PIC16ISD::BRCOND, dl, MVT::Other, Chain, Dest, PIC16CC, Cmp.getValue(1)); } Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h?rev=63808&r1=63807&r2=63808&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h (original) +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h Wed Feb 4 19:01:16 2009 @@ -88,7 +88,7 @@ SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG); SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); SDValue getPIC16Cmp(SDValue LHS, SDValue RHS, unsigned OrigCC, SDValue &CC, - SelectionDAG &DAG); + SelectionDAG &DAG, DebugLoc dl); virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB); @@ -146,7 +146,7 @@ // We can not have both operands of a binary operation in W. // This function is used to put one operand on stack and generate a load. - SDValue ConvertToMemOperand(SDValue Op, SelectionDAG &DAG); + SDValue ConvertToMemOperand(SDValue Op, SelectionDAG &DAG, DebugLoc dl); // This function checks if we need to put an operand of an operation on // stack and generate a load or not. Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=63808&r1=63807&r2=63808&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Wed Feb 4 19:01:16 2009 @@ -308,30 +308,31 @@ (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && "Unknown operand to lower!"); assert(!Subtarget.isXS1A() && "Cannot custom lower ADD/SUB on xs1a"); + DebugLoc dl = N->getDebugLoc(); // Extract components - SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), - DAG.getConstant(0, MVT::i32)); - SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), - DAG.getConstant(1, MVT::i32)); - SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(1), - DAG.getConstant(0, MVT::i32)); - SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(1), - DAG.getConstant(1, MVT::i32)); + SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + N->getOperand(0), DAG.getConstant(0, MVT::i32)); + SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + N->getOperand(0), DAG.getConstant(1, MVT::i32)); + SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + N->getOperand(1), DAG.getConstant(0, MVT::i32)); + SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + N->getOperand(1), DAG.getConstant(1, MVT::i32)); // Expand unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD : XCoreISD::LSUB; SDValue Zero = DAG.getConstant(0, MVT::i32); - SDValue Carry = DAG.getNode(Opcode, DAG.getVTList(MVT::i32, MVT::i32), + SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), LHSL, RHSL, Zero); SDValue Lo(Carry.getNode(), 1); - SDValue Ignored = DAG.getNode(Opcode, DAG.getVTList(MVT::i32, MVT::i32), + SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), LHSH, RHSH, Carry); SDValue Hi(Ignored.getNode(), 1); // Merge the pieces - return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); + return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); } SDValue XCoreTargetLowering:: From dalej at apple.com Wed Feb 4 19:49:46 2009 From: dalej at apple.com (Dale Johannesen) Date: Thu, 05 Feb 2009 01:49:46 -0000 Subject: [llvm-commits] [llvm] r63812 - in /llvm/trunk: ./ include/llvm/ include/llvm/Target/ lib/AsmParser/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/VMCore/ utils/TableGen/ Message-ID: <200902050149.n151nlDG027857@zion.cs.uiuc.edu> Author: johannes Date: Wed Feb 4 19:49:45 2009 New Revision: 63812 URL: http://llvm.org/viewvc/llvm-project?rev=63812&view=rev Log: Reapply 63765. Patches for clang and llvm-gcc to follow. Modified: llvm/trunk/Makefile.rules llvm/trunk/include/llvm/Function.h llvm/trunk/include/llvm/Intrinsics.h llvm/trunk/include/llvm/Intrinsics.td llvm/trunk/include/llvm/Module.h llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h llvm/trunk/include/llvm/Target/TargetMachine.h llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp llvm/trunk/lib/VMCore/AutoUpgrade.cpp llvm/trunk/lib/VMCore/Function.cpp llvm/trunk/lib/VMCore/Module.cpp llvm/trunk/lib/VMCore/Verifier.cpp llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h llvm/trunk/utils/TableGen/CodeGenIntrinsics.h llvm/trunk/utils/TableGen/CodeGenTarget.cpp llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp llvm/trunk/utils/TableGen/IntrinsicEmitter.h llvm/trunk/utils/TableGen/TableGen.cpp Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=63812&r1=63811&r2=63812&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Wed Feb 4 19:49:45 2009 @@ -1346,6 +1346,11 @@ $(Echo) "Building $( RetTypes = ret_types; list ParamTypes = param_types; list Properties = properties; + + bit isTarget = 0; } /// GCCBuiltin - If this intrinsic exactly corresponds to a GCC builtin, this Modified: llvm/trunk/include/llvm/Module.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Module.h?rev=63812&r1=63811&r2=63812&view=diff ============================================================================== --- llvm/trunk/include/llvm/Module.h (original) +++ llvm/trunk/include/llvm/Module.h Wed Feb 4 19:49:45 2009 @@ -213,6 +213,10 @@ Constant *getOrInsertFunction(const std::string &Name, const Type *RetTy, ...) END_WITH_NULL; + Constant *getOrInsertTargetIntrinsic(const std::string &Name, + const FunctionType *Ty, + AttrListPtr AttributeList); + /// getFunction - Look up the specified function in the module symbol table. /// If it does not exist, return null. Function *getFunction(const std::string &Name) const; Modified: llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h?rev=63812&r1=63811&r2=63812&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetIntrinsicInfo.h Wed Feb 4 19:49:45 2009 @@ -0,0 +1,48 @@ +//===-- llvm/Target/TargetIntrinsicInfo.h - Instruction Info ----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the target intrinsic instructions to the code generator. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_TARGET_TARGETINTRINSICINFO_H +#define LLVM_TARGET_TARGETINTRINSICINFO_H + +namespace llvm { + +class Function; +class Module; + +//--------------------------------------------------------------------------- +/// +/// TargetIntrinsicInfo - Interface to description of machine instruction set +/// +class TargetIntrinsicInfo { + + const char **Intrinsics; // Raw array to allow static init'n + unsigned NumIntrinsics; // Number of entries in the desc array + + TargetIntrinsicInfo(const TargetIntrinsicInfo &); // DO NOT IMPLEMENT + void operator=(const TargetIntrinsicInfo &); // DO NOT IMPLEMENT +public: + TargetIntrinsicInfo(const char **desc, unsigned num); + virtual ~TargetIntrinsicInfo(); + + unsigned getNumIntrinsics() const { return NumIntrinsics; } + + virtual Function *getDeclaration(Module *M, const char *BuiltinName) const { + return 0; + } + + virtual unsigned getIntrinsicID(Function *F) const { return 0; } +}; + +} // End llvm namespace + +#endif Modified: llvm/trunk/include/llvm/Target/TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=63812&r1=63811&r2=63812&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetMachine.h (original) +++ llvm/trunk/include/llvm/Target/TargetMachine.h Wed Feb 4 19:49:45 2009 @@ -23,6 +23,7 @@ class TargetData; class TargetSubtarget; class TargetInstrInfo; +class TargetIntrinsicInfo; class TargetJITInfo; class TargetLowering; class TargetFrameInfo; @@ -118,7 +119,6 @@ virtual TargetLowering *getTargetLowering() const { return 0; } virtual const TargetData *getTargetData() const { return 0; } - /// getTargetAsmInfo - Return target specific asm information. /// const TargetAsmInfo *getTargetAsmInfo() const { @@ -141,6 +141,11 @@ /// details of graph coloring register allocation removed from it. /// virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; } + + /// getIntrinsicInfo - If intrinsic information is available, return it. If + /// not, return null. + /// + virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; } /// getJITInfo - If this target supports a JIT, return information for it, /// otherwise return null. Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=63812&r1=63811&r2=63812&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Wed Feb 4 19:49:45 2009 @@ -2949,15 +2949,6 @@ Value *Callee; if (ConvertValIDToValue(PFTy, CalleeID, Callee, PFS)) return true; - // Check for call to invalid intrinsic to avoid crashing later. - if (Function *F = dyn_cast(Callee)) { - if (F->hasName() && F->getNameLen() >= 5 && - !strncmp(F->getValueName()->getKeyData(), "llvm.", 5) && - !F->getIntrinsicID(true)) - return Error(CallLoc, "Call to invalid LLVM intrinsic function '" + - F->getNameStr() + "'"); - } - // FIXME: In LLVM 3.0, stop accepting zext, sext and inreg as optional // function attributes. unsigned ObsoleteFuncAttrs = Attribute::ZExt|Attribute::SExt|Attribute::InReg; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63812&r1=63811&r2=63812&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Wed Feb 4 19:49:45 2009 @@ -43,6 +43,7 @@ #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetIntrinsicInfo.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" @@ -4427,6 +4428,14 @@ const char *RenameFn = 0; if (Function *F = I.getCalledFunction()) { if (F->isDeclaration()) { + const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo(); + if (II) { + if (unsigned IID = II->getIntrinsicID(F)) { + RenameFn = visitIntrinsicCall(I, IID); + if (!RenameFn) + return; + } + } if (unsigned IID = F->getIntrinsicID()) { RenameFn = visitIntrinsicCall(I, IID); if (!RenameFn) Modified: llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp?rev=63812&r1=63811&r2=63812&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetIntrinsicInfo.cpp Wed Feb 4 19:49:45 2009 @@ -0,0 +1,22 @@ +//===-- TargetIntrinsicInfo.cpp - Target Instruction Information ----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the TargetIntrinsicInfo class. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Target/TargetIntrinsicInfo.h" +using namespace llvm; + +TargetIntrinsicInfo::TargetIntrinsicInfo(const char **desc, unsigned count) + : Intrinsics(desc), NumIntrinsics(count) { +} + +TargetIntrinsicInfo::~TargetIntrinsicInfo() { +} Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=63812&r1=63811&r2=63812&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original) +++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Wed Feb 4 19:49:45 2009 @@ -217,7 +217,7 @@ // Upgrade intrinsic attributes. This does not change the function. if (NewFn) F = NewFn; - if (unsigned id = F->getIntrinsicID(true)) + if (unsigned id = F->getIntrinsicID()) F->setAttributes(Intrinsic::getAttributes((Intrinsic::ID)id)); return Upgraded; } Modified: llvm/trunk/lib/VMCore/Function.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Function.cpp?rev=63812&r1=63811&r2=63812&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Function.cpp (original) +++ llvm/trunk/lib/VMCore/Function.cpp Wed Feb 4 19:49:45 2009 @@ -175,7 +175,7 @@ ParentModule->getFunctionList().push_back(this); // Ensure intrinsics have the right parameter attributes. - if (unsigned IID = getIntrinsicID(true)) + if (unsigned IID = getIntrinsicID()) setAttributes(Intrinsic::getAttributes(Intrinsic::ID(IID))); } @@ -304,7 +304,7 @@ /// particular intrinsic functions which correspond to this value are defined in /// llvm/Intrinsics.h. /// -unsigned Function::getIntrinsicID(bool noAssert) const { +unsigned Function::getIntrinsicID() const { const ValueName *ValName = this->getValueName(); if (!ValName) return 0; @@ -315,12 +315,9 @@ || Name[2] != 'v' || Name[3] != 'm') return 0; // All intrinsics start with 'llvm.' - assert((Len != 5 || noAssert) && "'llvm.' is an invalid intrinsic name!"); - #define GET_FUNCTION_RECOGNIZER #include "llvm/Intrinsics.gen" #undef GET_FUNCTION_RECOGNIZER - assert(noAssert && "Invalid LLVM intrinsic name"); return 0; } @@ -373,4 +370,9 @@ getType(id, Tys, numTys))); } +// This defines the "Intrinsic::getIntrinsicForGCCBuiltin()" method. +#define GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN +#include "llvm/Intrinsics.gen" +#undef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN + // vim: sw=2 ai Modified: llvm/trunk/lib/VMCore/Module.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Module.cpp?rev=63812&r1=63811&r2=63812&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Module.cpp (original) +++ llvm/trunk/lib/VMCore/Module.cpp Wed Feb 4 19:49:45 2009 @@ -171,6 +171,25 @@ return F; } +Constant *Module::getOrInsertTargetIntrinsic(const std::string &Name, + const FunctionType *Ty, + AttrListPtr AttributeList) { + ValueSymbolTable &SymTab = getValueSymbolTable(); + + // See if we have a definition for the specified function already. + GlobalValue *F = dyn_cast_or_null(SymTab.lookup(Name)); + if (F == 0) { + // Nope, add it + Function *New = Function::Create(Ty, GlobalVariable::ExternalLinkage, Name); + New->setAttributes(AttributeList); + FunctionList.push_back(New); + return New; // Return the new prototype. + } + + // Otherwise, we just found the existing function or a prototype. + return F; +} + Constant *Module::getOrInsertFunction(const std::string &Name, const FunctionType *Ty) { AttrListPtr AttributeList = AttrListPtr::get((AttributeWithIndex *)0, 0); Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=63812&r1=63811&r2=63812&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Wed Feb 4 19:49:45 2009 @@ -1004,10 +1004,9 @@ void Verifier::visitCallInst(CallInst &CI) { VerifyCallSite(&CI); - if (Function *F = CI.getCalledFunction()) { + if (Function *F = CI.getCalledFunction()) if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) visitIntrinsicFunctionCall(ID, CI); - } } void Verifier::visitInvokeInst(InvokeInst &II) { Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=63812&r1=63811&r2=63812&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Wed Feb 4 19:49:45 2009 @@ -1303,7 +1303,8 @@ // FIXME: REMOVE OSTREAM ARGUMENT CodeGenDAGPatterns::CodeGenDAGPatterns(RecordKeeper &R) : Records(R) { - Intrinsics = LoadIntrinsics(Records); + Intrinsics = LoadIntrinsics(Records, false); + TgtIntrinsics = LoadIntrinsics(Records, true); ParseNodeInfo(); ParseNodeTransforms(); ParseComplexPatterns(); Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h?rev=63812&r1=63811&r2=63812&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h Wed Feb 4 19:49:45 2009 @@ -465,6 +465,7 @@ RecordKeeper &Records; CodeGenTarget Target; std::vector Intrinsics; + std::vector TgtIntrinsics; std::map SDNodes; std::map > SDNodeXForms; @@ -515,18 +516,25 @@ const CodeGenIntrinsic &getIntrinsic(Record *R) const { for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i) if (Intrinsics[i].TheDef == R) return Intrinsics[i]; + for (unsigned i = 0, e = TgtIntrinsics.size(); i != e; ++i) + if (TgtIntrinsics[i].TheDef == R) return TgtIntrinsics[i]; assert(0 && "Unknown intrinsic!"); abort(); } const CodeGenIntrinsic &getIntrinsicInfo(unsigned IID) const { - assert(IID-1 < Intrinsics.size() && "Bad intrinsic ID!"); - return Intrinsics[IID-1]; + if (IID-1 < Intrinsics.size()) + return Intrinsics[IID-1]; + if (IID-Intrinsics.size()-1 < TgtIntrinsics.size()) + return TgtIntrinsics[IID-Intrinsics.size()-1]; + assert(0 && "Bad intrinsic ID!"); } unsigned getIntrinsicID(Record *R) const { for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i) if (Intrinsics[i].TheDef == R) return i; + for (unsigned i = 0, e = TgtIntrinsics.size(); i != e; ++i) + if (TgtIntrinsics[i].TheDef == R) return i + Intrinsics.size(); assert(0 && "Unknown intrinsic!"); abort(); } Modified: llvm/trunk/utils/TableGen/CodeGenIntrinsics.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenIntrinsics.h?rev=63812&r1=63811&r2=63812&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenIntrinsics.h (original) +++ llvm/trunk/utils/TableGen/CodeGenIntrinsics.h Wed Feb 4 19:49:45 2009 @@ -80,7 +80,8 @@ /// LoadIntrinsics - Read all of the intrinsics defined in the specified /// .td file. - std::vector LoadIntrinsics(const RecordKeeper &RC); + std::vector LoadIntrinsics(const RecordKeeper &RC, + bool TargetOnly); } #endif Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=63812&r1=63811&r2=63812&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Wed Feb 4 19:49:45 2009 @@ -426,13 +426,17 @@ // CodeGenIntrinsic Implementation //===----------------------------------------------------------------------===// -std::vector llvm::LoadIntrinsics(const RecordKeeper &RC) { +std::vector llvm::LoadIntrinsics(const RecordKeeper &RC, + bool TargetOnly) { std::vector I = RC.getAllDerivedDefinitions("Intrinsic"); std::vector Result; - for (unsigned i = 0, e = I.size(); i != e; ++i) - Result.push_back(CodeGenIntrinsic(I[i])); + for (unsigned i = 0, e = I.size(); i != e; ++i) { + bool isTarget = I[i]->getValueAsBit("isTarget"); + if (isTarget == TargetOnly) + Result.push_back(CodeGenIntrinsic(I[i])); + } return Result; } Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=63812&r1=63811&r2=63812&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Wed Feb 4 19:49:45 2009 @@ -25,7 +25,10 @@ void IntrinsicEmitter::run(std::ostream &OS) { EmitSourceFileHeader("Intrinsic Function Source Fragment", OS); - std::vector Ints = LoadIntrinsics(Records); + std::vector Ints = LoadIntrinsics(Records, TargetOnly); + + if (TargetOnly && !Ints.empty()) + TargetPrefix = Ints[0].TargetPrefix; // Emit the enum information. EmitEnumInfo(Ints, OS); @@ -91,12 +94,12 @@ if (Ints[I->second].isOverloaded) OS << " if (Len > " << I->first.size() << " && !memcmp(Name, \"" << I->first << ".\", " - << (I->first.size() + 1) << ")) return Intrinsic::" + << (I->first.size() + 1) << ")) return " << TargetPrefix << "Intrinsic::" << Ints[I->second].EnumName << ";\n"; else OS << " if (Len == " << I->first.size() << " && !memcmp(Name, \"" << I->first << "\", " - << I->first.size() << ")) return Intrinsic::" + << I->first.size() << ")) return " << TargetPrefix << "Intrinsic::" << Ints[I->second].EnumName << ";\n"; } OS << " }\n"; @@ -351,11 +354,13 @@ Ints[i].IS.ParamTypeDefs)].push_back(i); // Loop through the array, emitting one generator for each batch. + std::string IntrinsicStr = TargetPrefix + "Intrinsic::"; + for (MapTy::iterator I = UniqueArgInfos.begin(), E = UniqueArgInfos.end(); I != E; ++I) { for (unsigned i = 0, e = I->second.size(); i != e; ++i) - OS << " case Intrinsic::" << Ints[I->second[i]].EnumName << ":\t\t// " - << Ints[I->second[i]].Name << "\n"; + OS << " case " << IntrinsicStr << Ints[I->second[i]].EnumName + << ":\t\t// " << Ints[I->second[i]].Name << "\n"; const RecPair &ArgTypes = I->first; const std::vector &RetTys = ArgTypes.first; @@ -392,7 +397,11 @@ EmitAttributes(const std::vector &Ints, std::ostream &OS) { OS << "// Add parameter attributes that are not common to all intrinsics.\n"; OS << "#ifdef GET_INTRINSIC_ATTRIBUTES\n"; - OS << "AttrListPtr Intrinsic::getAttributes(ID id) {"; + if (TargetOnly) + OS << "static AttrListPtr getAttributes(" << TargetPrefix + << "Intrinsic::ID id) {"; + else + OS << "AttrListPtr Intrinsic::getAttributes(ID id) {"; OS << " // No intrinsic can throw exceptions.\n"; OS << " Attributes Attr = Attribute::NoUnwind;\n"; OS << " switch (id) {\n"; @@ -404,7 +413,8 @@ switch (Ints[i].ModRef) { default: break; case CodeGenIntrinsic::NoMem: - OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; + OS << " case " << TargetPrefix << "Intrinsic::" << Ints[i].EnumName + << ":\n"; break; } } @@ -415,7 +425,8 @@ default: break; case CodeGenIntrinsic::ReadArgMem: case CodeGenIntrinsic::ReadMem: - OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; + OS << " case " << TargetPrefix << "Intrinsic::" << Ints[i].EnumName + << ":\n"; break; } } @@ -431,7 +442,8 @@ for (unsigned i = 0, e = Ints.size(); i != e; ++i) { if (Ints[i].ArgumentAttributes.empty()) continue; - OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; + OS << " case " << TargetPrefix << "Intrinsic::" << Ints[i].EnumName + << ":\n"; std::vector > ArgAttrs = Ints[i].ArgumentAttributes; @@ -495,7 +507,7 @@ typedef std::map::const_iterator StrMapIterator; static void EmitBuiltinComparisons(StrMapIterator Start, StrMapIterator End, unsigned CharStart, unsigned Indent, - std::ostream &OS) { + std::string TargetPrefix, std::ostream &OS) { if (Start == End) return; // empty range. // Determine what, if anything, is the same about all these strings. @@ -522,7 +534,8 @@ OS << CommonString.size() - CharStart << "))\n"; ++Indent; } - OS << std::string(Indent*2, ' ') << "IntrinsicID = Intrinsic::"; + OS << std::string(Indent*2, ' ') << "IntrinsicID = " << TargetPrefix + << "Intrinsic::"; OS << Start->second << ";\n"; return; } @@ -535,7 +548,8 @@ OS << ", \"" << (CommonString.c_str()+CharStart) << "\", "; OS << CommonString.size()-CharStart << ")) {\n"; - EmitBuiltinComparisons(Start, End, CommonString.size(), Indent+1, OS); + EmitBuiltinComparisons(Start, End, CommonString.size(), Indent+1, + TargetPrefix, OS); OS << std::string(Indent*2, ' ') << "}\n"; return; } @@ -556,7 +570,7 @@ for (++NextChar; NextChar != End && NextChar->first[CharStart] == ThisChar; ++NextChar) /*empty*/; - EmitBuiltinComparisons(I, NextChar, CharStart+1, Indent+1, OS); + EmitBuiltinComparisons(I, NextChar, CharStart+1, Indent+1, TargetPrefix,OS); OS << std::string(Indent*2, ' ') << " break;\n"; I = NextChar; } @@ -566,6 +580,7 @@ /// EmitTargetBuiltins - All of the builtins in the specified map are for the /// same target, and we already checked it. static void EmitTargetBuiltins(const std::map &BIM, + const std::string &TargetPrefix, std::ostream &OS) { // Rearrange the builtins by length. std::vector > BuiltinsByLen; @@ -584,7 +599,7 @@ if (BuiltinsByLen[i].empty()) continue; OS << " case " << i << ":\n"; EmitBuiltinComparisons(BuiltinsByLen[i].begin(), BuiltinsByLen[i].end(), - 0, 3, OS); + 0, 3, TargetPrefix, OS); OS << " break;\n"; } OS << " }\n"; @@ -613,7 +628,22 @@ OS << "// in as BuiltinName, and a target prefix (e.g. 'ppc') is passed\n"; OS << "// in as TargetPrefix. The result is assigned to 'IntrinsicID'.\n"; OS << "#ifdef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN\n"; - OS << " IntrinsicID = Intrinsic::not_intrinsic;\n"; + + if (TargetOnly) { + OS << "static " << TargetPrefix << "Intrinsic::ID " + << "getIntrinsicForGCCBuiltin(const char " + << "*TargetPrefix, const char *BuiltinName) {\n"; + OS << " " << TargetPrefix << "Intrinsic::ID IntrinsicID = "; + } else { + OS << "Intrinsic::ID Intrinsic::getIntrinsicForGCCBuiltin(const char " + << "*TargetPrefix, const char *BuiltinName) {\n"; + OS << " Intrinsic::ID IntrinsicID = "; + } + + if (TargetOnly) + OS << "(" << TargetPrefix<< "Intrinsic::ID)"; + + OS << "Intrinsic::not_intrinsic;\n"; // Note: this could emit significantly better code if we cared. for (BIMTy::iterator I = BuiltinMap.begin(), E = BuiltinMap.end();I != E;++I){ @@ -625,8 +655,10 @@ OS << "{\n"; // Emit the comparisons for this target prefix. - EmitTargetBuiltins(I->second, OS); + EmitTargetBuiltins(I->second, TargetPrefix, OS); OS << " }\n"; } + OS << " return IntrinsicID;\n"; + OS << "}\n"; OS << "#endif\n\n"; } Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.h?rev=63812&r1=63811&r2=63812&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/IntrinsicEmitter.h (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.h Wed Feb 4 19:49:45 2009 @@ -20,9 +20,12 @@ namespace llvm { class IntrinsicEmitter : public TableGenBackend { RecordKeeper &Records; + bool TargetOnly; + std::string TargetPrefix; public: - IntrinsicEmitter(RecordKeeper &R) : Records(R) {} + IntrinsicEmitter(RecordKeeper &R, bool T = false) + : Records(R), TargetOnly(T) {} void run(std::ostream &OS); Modified: llvm/trunk/utils/TableGen/TableGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=63812&r1=63811&r2=63812&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TableGen.cpp (original) +++ llvm/trunk/utils/TableGen/TableGen.cpp Wed Feb 4 19:49:45 2009 @@ -49,6 +49,7 @@ GenFastISel, GenSubtarget, GenIntrinsic, + GenTgtIntrinsic, GenLLVMCConf, PrintEnums }; @@ -82,6 +83,8 @@ "Generate subtarget enumerations"), clEnumValN(GenIntrinsic, "gen-intrinsic", "Generate intrinsic information"), + clEnumValN(GenTgtIntrinsic, "gen-tgt-intrinsic", + "Generate target intrinsic information"), clEnumValN(GenLLVMCConf, "gen-llvmc", "Generate LLVMC configuration library"), clEnumValN(PrintEnums, "print-enums", @@ -190,6 +193,9 @@ case GenIntrinsic: IntrinsicEmitter(Records).run(*Out); break; + case GenTgtIntrinsic: + IntrinsicEmitter(Records, true).run(*Out); + break; case GenLLVMCConf: LLVMCConfigurationEmitter(Records).run(*Out); break; From dalej at apple.com Wed Feb 4 19:51:34 2009 From: dalej at apple.com (Dale Johannesen) Date: Thu, 05 Feb 2009 01:51:34 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63815 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <200902050151.n151pY7p027954@zion.cs.uiuc.edu> Author: johannes Date: Wed Feb 4 19:51:34 2009 New Revision: 63815 URL: http://llvm.org/viewvc/llvm-project?rev=63815&view=rev Log: Adjust to match new API introduced in llvm 63765. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=63815&r1=63814&r2=63815&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Feb 4 19:51:34 2009 @@ -4548,11 +4548,8 @@ // If this builtin directly corresponds to an LLVM intrinsic, get the // IntrinsicID now. const char *BuiltinName = IDENTIFIER_POINTER(DECL_NAME(fndecl)); - Intrinsic::ID IntrinsicID = Intrinsic::not_intrinsic; -#define GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN -#include "llvm/Intrinsics.gen" -#undef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN - + Intrinsic::ID IntrinsicID = + Intrinsic::getIntrinsicForGCCBuiltin(TargetPrefix, BuiltinName); if (IntrinsicID == Intrinsic::not_intrinsic) { if (EmitFrontendExpandedBuiltinCall(exp, fndecl, DestLoc, Result)) return true; From gohman at apple.com Wed Feb 4 20:44:33 2009 From: gohman at apple.com (Dan Gohman) Date: Thu, 05 Feb 2009 02:44:33 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63817 - in /llvm-gcc-4.2/trunk/gcc: gcc.c gcc.h Message-ID: <200902050244.n152iYHo029644@zion.cs.uiuc.edu> Author: djg Date: Wed Feb 4 20:44:33 2009 New Revision: 63817 URL: http://llvm.org/viewvc/llvm-project?rev=63817&view=rev Log: Fix the "-mllvm" option for non-Darwin hosts. On Darwin command-line options are curiously munged by TARGET_OPTION_TRANSLATE_TABLE. Modified: llvm-gcc-4.2/trunk/gcc/gcc.c llvm-gcc-4.2/trunk/gcc/gcc.h Modified: llvm-gcc-4.2/trunk/gcc/gcc.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gcc.c?rev=63817&r1=63816&r2=63817&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/gcc.c (original) +++ llvm-gcc-4.2/trunk/gcc/gcc.c Wed Feb 4 20:44:33 2009 @@ -1171,6 +1171,9 @@ {"--include-with-prefix-after", "-iwithprefix", "a"}, {"--language", "-x", "a"}, {"--library-directory", "-L", "a"}, + /* LLVM LOCAL begin */ + {"--llvm-options", "-mllvm", "a"}, + /* LLVM LOCAL end */ {"--machine", "-m", "aj"}, {"--machine-", "-m", "*j"}, {"--no-integrated-cpp", "-no-integrated-cpp", 0}, Modified: llvm-gcc-4.2/trunk/gcc/gcc.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gcc.h?rev=63817&r1=63816&r2=63817&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/gcc.h (original) +++ llvm-gcc-4.2/trunk/gcc/gcc.h Wed Feb 4 20:44:33 2009 @@ -55,6 +55,9 @@ /* APPLE LOCAL ARM iwithsysroot 4917039 */ \ || !strcmp (STR, "iwithsysroot") \ || !strcmp (STR, "-param") || !strcmp (STR, "specs") \ + /* LLVM LOCAL begin */ \ + || !strcmp (STR, "mllvm") \ + /* LLVM LOCAL end */ \ || !strcmp (STR, "MF") || !strcmp (STR, "MT") || !strcmp (STR, "MQ")) From daniel at zuster.org Wed Feb 4 21:12:36 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 05 Feb 2009 03:12:36 -0000 Subject: [llvm-commits] [test-suite] r63818 - /test-suite/trunk/RunSafely.sh Message-ID: <200902050312.n153CbPA030500@zion.cs.uiuc.edu> Author: ddunbar Date: Wed Feb 4 21:12:33 2009 New Revision: 63818 URL: http://llvm.org/viewvc/llvm-project?rev=63818&view=rev Log: 250 MB wasn't enough for me (or rather, it wasn't enough for MultiSource/Benchmarks/NPB-serial/is). Modified: test-suite/trunk/RunSafely.sh Modified: test-suite/trunk/RunSafely.sh URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/RunSafely.sh?rev=63818&r1=63817&r2=63818&view=diff ============================================================================== --- test-suite/trunk/RunSafely.sh (original) +++ test-suite/trunk/RunSafely.sh Wed Feb 4 21:12:33 2009 @@ -104,8 +104,8 @@ # of files being output by the tests. 10 MB should be enough for anybody. ;) ULIMITCMD="$ULIMITCMD ulimit -f 10485760;" - # virtual memory: 250 MB should be enough for anybody. ;) - ULIMITCMD="$ULIMITCMD ulimit -v 250000;" + # virtual memory: 300 MB should be enough for anybody. ;) + ULIMITCMD="$ULIMITCMD ulimit -v 300000;" esac rm -f core core.* From isanbard at gmail.com Wed Feb 4 21:55:37 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Feb 2009 03:55:37 -0000 Subject: [llvm-commits] [llvm] r63819 - /llvm/branches/Apple/Dib/ Message-ID: <200902050355.n153tbo9031992@zion.cs.uiuc.edu> Author: void Date: Wed Feb 4 21:55:37 2009 New Revision: 63819 URL: http://llvm.org/viewvc/llvm-project?rev=63819&view=rev Log: Remove branch in preparation for re-branching from 2.5 release. Removed: llvm/branches/Apple/Dib/ From isanbard at gmail.com Wed Feb 4 21:55:48 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Feb 2009 03:55:48 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63820 - /llvm-gcc-4.2/branches/Apple/Dib/ Message-ID: <200902050355.n153tmwr032011@zion.cs.uiuc.edu> Author: void Date: Wed Feb 4 21:55:48 2009 New Revision: 63820 URL: http://llvm.org/viewvc/llvm-project?rev=63820&view=rev Log: Remove branch in preparation for re-branching from 2.5 release. Removed: llvm-gcc-4.2/branches/Apple/Dib/ From isanbard at gmail.com Wed Feb 4 21:56:53 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Feb 2009 03:56:53 -0000 Subject: [llvm-commits] [llvm] r63821 - /llvm/branches/Apple/Dib/ Message-ID: <200902050356.n153ur0c032057@zion.cs.uiuc.edu> Author: void Date: Wed Feb 4 21:56:53 2009 New Revision: 63821 URL: http://llvm.org/viewvc/llvm-project?rev=63821&view=rev Log: Branch Dib from 2.5 release branch. Added: llvm/branches/Apple/Dib/ - copied from r63820, llvm/branches/release_25/ From isanbard at gmail.com Wed Feb 4 21:57:14 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Feb 2009 03:57:14 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63822 - /llvm-gcc-4.2/branches/Apple/Dib/ Message-ID: <200902050357.n153vEc5032079@zion.cs.uiuc.edu> Author: void Date: Wed Feb 4 21:57:14 2009 New Revision: 63822 URL: http://llvm.org/viewvc/llvm-project?rev=63822&view=rev Log: Branch Dib from 2.5 release branch. Added: llvm-gcc-4.2/branches/Apple/Dib/ - copied from r63821, llvm-gcc-4.2/branches/release_25/ From nicholas at mxc.ca Wed Feb 4 22:00:22 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 04 Feb 2009 20:00:22 -0800 Subject: [llvm-commits] [llvm] r63623 - in /llvm/trunk/tools: Makefile gold/ gold/Makefile gold/README.txt gold/gold-plugin.cpp In-Reply-To: <1A3250C2-449A-466A-B616-49AC4D036D9C@apple.com> References: <200902030713.n137DP9o009780@zion.cs.uiuc.edu> <200902031042.11251.baldrick@free.fr> <49891B6A.1010106@mxc.ca> <1A3250C2-449A-466A-B616-49AC4D036D9C@apple.com> Message-ID: <498A6456.6070305@mxc.ca> Mike Stump wrote: > On Feb 3, 2009, at 8:36 PM, Nick Lewycky wrote: >> With Rafael's patch to llvm-gcc in r63633, we now get transparent LTO >> with the gold plugin and CFLAGS=-O4 -use-gold-plugin. > > Hum, can we configure in -use-gold-plugin so that we get goldness with > just -O4 when the environment can support it? I don't see why not. llvm-gcc -O4 is broken on linux for non-Gold users, and probably always will be. Nick > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From nicholas at mxc.ca Wed Feb 4 22:14:27 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 05 Feb 2009 04:14:27 -0000 Subject: [llvm-commits] [llvm] r63823 - /llvm/trunk/tools/gold/gold-plugin.cpp Message-ID: <200902050414.n154ER4X032570@zion.cs.uiuc.edu> Author: nicholas Date: Wed Feb 4 22:14:23 2009 New Revision: 63823 URL: http://llvm.org/viewvc/llvm-project?rev=63823&view=rev Log: Remove accidentally included debug message! Reword a comment for clarity. Remove some extra whitespace. Modified: llvm/trunk/tools/gold/gold-plugin.cpp Modified: llvm/trunk/tools/gold/gold-plugin.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/gold-plugin.cpp?rev=63823&r1=63822&r2=63823&view=diff ============================================================================== --- llvm/trunk/tools/gold/gold-plugin.cpp (original) +++ llvm/trunk/tools/gold/gold-plugin.cpp Wed Feb 4 22:14:23 2009 @@ -159,8 +159,8 @@ int *claimed) { void *buf = NULL; if (file->offset) { - /* This is probably an archive member containing either an ELF object, or - * LLVM IR. Find out which one it is */ + // Gold has found what might be IR part-way inside of a file, such as + // an .a archive. if (lseek(file->fd, file->offset, SEEK_SET) == -1) { (*message)(LDPL_ERROR, "Failed to seek to archive member of %s at offset %d: %s\n", @@ -195,8 +195,8 @@ Modules.resize(Modules.size() + 1); claimed_file &cf = Modules.back(); - cf.M = buf ? lto_module_create_from_memory(buf, file->filesize) : - lto_module_create(file->name); + cf.M = buf ? lto_module_create_from_memory(buf, file->filesize) : + lto_module_create(file->name); cf.buf = buf; if (!cf.M) { (*message)(LDPL_ERROR, "Failed to create LLVM module: %s", @@ -294,8 +294,6 @@ E = Modules.end(); I != E; ++I) { (*get_symbols)(I->handle, I->syms.size(), &I->syms[0]); for (unsigned i = 0, e = I->syms.size(); i != e; i++) { - (*message)(LDPL_WARNING, "def: %d visibility: %d resolution %d", - I->syms[i].def, I->syms[i].visibility, I->syms[i].resolution); if (I->syms[i].resolution == LDPR_PREVAILING_DEF) { lto_codegen_add_must_preserve_symbol(cg, I->syms[i].name); anySymbolsPreserved = true; From isanbard at gmail.com Wed Feb 4 22:22:14 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Feb 2009 04:22:14 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63824 - /llvm-gcc-4.2/branches/Apple/Dib/gcc/cp/parser.c Message-ID: <200902050422.n154MHM7000435@zion.cs.uiuc.edu> Author: void Date: Wed Feb 4 22:22:09 2009 New Revision: 63824 URL: http://llvm.org/viewvc/llvm-project?rev=63824&view=rev Log: Pull r63696 into Dib: Call cp_finish_decl() before marking the block_holder_tmp_decl readonly. Fixes these DejaGNU regressions: g++.apple/block-call-with-sideeffect.c g++.apple/block-global-block.c g++.apple/block-id-global-block.c g++.apple/block-localisglobal.c g++.apple/block-nested-global-copied-var-2.c g++.apple/block-nested-global.c Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/cp/parser.c Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/cp/parser.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/cp/parser.c?rev=63824&r1=63823&r2=63824&view=diff ============================================================================== --- llvm-gcc-4.2/branches/Apple/Dib/gcc/cp/parser.c (original) +++ llvm-gcc-4.2/branches/Apple/Dib/gcc/cp/parser.c Wed Feb 4 22:22:09 2009 @@ -21065,13 +21065,13 @@ TREE_PUBLIC (block_holder_tmp_decl) = 0; TREE_STATIC (block_holder_tmp_decl) = 1; } + cp_finish_decl (block_holder_tmp_decl, constructor, 0, 0, LOOKUP_ONLYCONVERTING); /* LLVM LOCAL begin radar 5865221 */ #ifdef ENABLE_LLVM TREE_CONSTANT (block_holder_tmp_decl) = 1; TREE_READONLY (block_holder_tmp_decl) = 1; #endif /* LLVM LOCAL end radar 5865221 */ - cp_finish_decl (block_holder_tmp_decl, constructor, 0, 0, LOOKUP_ONLYCONVERTING); return block_holder_tmp_decl; } /* APPLE LOCAL end radar 6169527 */ From isanbard at gmail.com Wed Feb 4 22:33:06 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Feb 2009 04:33:06 -0000 Subject: [llvm-commits] [llvm] r63825 - in /llvm/branches/Apple/Dib: ./ include/llvm/ include/llvm/Target/ lib/AsmParser/ lib/CodeGen/SelectionDAG/ lib/VMCore/ test/Assembler/ utils/TableGen/ Message-ID: <200902050433.n154X8c5010574@zion.cs.uiuc.edu> Author: void Date: Wed Feb 4 22:33:04 2009 New Revision: 63825 URL: http://llvm.org/viewvc/llvm-project?rev=63825&view=rev Log: New feature: add support for target intrinsics being defined in the target directories themselves. This also means that VMCore no longer needs to know about every target's list of intrinsics. Future work will include converting the PowerPC target to this interface as an example implementation. With patch by Dale. Also remove now invalid test. Removed: llvm/branches/Apple/Dib/test/Assembler/2007-04-15-BadIntrinsic.ll Modified: llvm/branches/Apple/Dib/Makefile.rules llvm/branches/Apple/Dib/include/llvm/Function.h llvm/branches/Apple/Dib/include/llvm/Intrinsics.h llvm/branches/Apple/Dib/include/llvm/Intrinsics.td llvm/branches/Apple/Dib/include/llvm/Module.h llvm/branches/Apple/Dib/include/llvm/Target/TargetMachine.h llvm/branches/Apple/Dib/lib/AsmParser/LLParser.cpp llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp llvm/branches/Apple/Dib/lib/VMCore/AutoUpgrade.cpp llvm/branches/Apple/Dib/lib/VMCore/Function.cpp llvm/branches/Apple/Dib/lib/VMCore/Module.cpp llvm/branches/Apple/Dib/lib/VMCore/Verifier.cpp llvm/branches/Apple/Dib/utils/TableGen/CodeGenDAGPatterns.cpp llvm/branches/Apple/Dib/utils/TableGen/CodeGenDAGPatterns.h llvm/branches/Apple/Dib/utils/TableGen/CodeGenIntrinsics.h llvm/branches/Apple/Dib/utils/TableGen/CodeGenTarget.cpp llvm/branches/Apple/Dib/utils/TableGen/IntrinsicEmitter.cpp llvm/branches/Apple/Dib/utils/TableGen/IntrinsicEmitter.h llvm/branches/Apple/Dib/utils/TableGen/TableGen.cpp Modified: llvm/branches/Apple/Dib/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/Makefile.rules?rev=63825&r1=63824&r2=63825&view=diff ============================================================================== --- llvm/branches/Apple/Dib/Makefile.rules (original) +++ llvm/branches/Apple/Dib/Makefile.rules Wed Feb 4 22:33:04 2009 @@ -1346,6 +1346,11 @@ $(Echo) "Building $( RetTypes = ret_types; list ParamTypes = param_types; list Properties = properties; + + bit isTarget = 0; } /// GCCBuiltin - If this intrinsic exactly corresponds to a GCC builtin, this Modified: llvm/branches/Apple/Dib/include/llvm/Module.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/Module.h?rev=63825&r1=63824&r2=63825&view=diff ============================================================================== --- llvm/branches/Apple/Dib/include/llvm/Module.h (original) +++ llvm/branches/Apple/Dib/include/llvm/Module.h Wed Feb 4 22:33:04 2009 @@ -213,6 +213,10 @@ Constant *getOrInsertFunction(const std::string &Name, const Type *RetTy, ...) END_WITH_NULL; + Constant *getOrInsertTargetIntrinsic(const std::string &Name, + const FunctionType *Ty, + AttrListPtr AttributeList); + /// getFunction - Look up the specified function in the module symbol table. /// If it does not exist, return null. Function *getFunction(const std::string &Name) const; Modified: llvm/branches/Apple/Dib/include/llvm/Target/TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/Target/TargetMachine.h?rev=63825&r1=63824&r2=63825&view=diff ============================================================================== --- llvm/branches/Apple/Dib/include/llvm/Target/TargetMachine.h (original) +++ llvm/branches/Apple/Dib/include/llvm/Target/TargetMachine.h Wed Feb 4 22:33:04 2009 @@ -23,6 +23,7 @@ class TargetData; class TargetSubtarget; class TargetInstrInfo; +class TargetIntrinsicInfo; class TargetJITInfo; class TargetLowering; class TargetFrameInfo; @@ -118,7 +119,6 @@ virtual TargetLowering *getTargetLowering() const { return 0; } virtual const TargetData *getTargetData() const { return 0; } - /// getTargetAsmInfo - Return target specific asm information. /// const TargetAsmInfo *getTargetAsmInfo() const { @@ -141,6 +141,11 @@ /// details of graph coloring register allocation removed from it. /// virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; } + + /// getIntrinsicInfo - If intrinsic information is available, return it. If + /// not, return null. + /// + virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; } /// getJITInfo - If this target supports a JIT, return information for it, /// otherwise return null. Modified: llvm/branches/Apple/Dib/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/AsmParser/LLParser.cpp?rev=63825&r1=63824&r2=63825&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/AsmParser/LLParser.cpp (original) +++ llvm/branches/Apple/Dib/lib/AsmParser/LLParser.cpp Wed Feb 4 22:33:04 2009 @@ -2949,15 +2949,6 @@ Value *Callee; if (ConvertValIDToValue(PFTy, CalleeID, Callee, PFS)) return true; - // Check for call to invalid intrinsic to avoid crashing later. - if (Function *F = dyn_cast(Callee)) { - if (F->hasName() && F->getNameLen() >= 5 && - !strncmp(F->getValueName()->getKeyData(), "llvm.", 5) && - !F->getIntrinsicID(true)) - return Error(CallLoc, "Call to invalid LLVM intrinsic function '" + - F->getNameStr() + "'"); - } - // FIXME: In LLVM 3.0, stop accepting zext, sext and inreg as optional // function attributes. unsigned ObsoleteFuncAttrs = Attribute::ZExt|Attribute::SExt|Attribute::InReg; Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63825&r1=63824&r2=63825&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Wed Feb 4 22:33:04 2009 @@ -43,6 +43,7 @@ #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetIntrinsicInfo.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" @@ -4414,6 +4415,14 @@ const char *RenameFn = 0; if (Function *F = I.getCalledFunction()) { if (F->isDeclaration()) { + const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo(); + if (II) { + if (unsigned IID = II->getIntrinsicID(F)) { + RenameFn = visitIntrinsicCall(I, IID); + if (!RenameFn) + return; + } + } if (unsigned IID = F->getIntrinsicID()) { RenameFn = visitIntrinsicCall(I, IID); if (!RenameFn) Modified: llvm/branches/Apple/Dib/lib/VMCore/AutoUpgrade.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/VMCore/AutoUpgrade.cpp?rev=63825&r1=63824&r2=63825&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/VMCore/AutoUpgrade.cpp (original) +++ llvm/branches/Apple/Dib/lib/VMCore/AutoUpgrade.cpp Wed Feb 4 22:33:04 2009 @@ -217,7 +217,7 @@ // Upgrade intrinsic attributes. This does not change the function. if (NewFn) F = NewFn; - if (unsigned id = F->getIntrinsicID(true)) + if (unsigned id = F->getIntrinsicID()) F->setAttributes(Intrinsic::getAttributes((Intrinsic::ID)id)); return Upgraded; } Modified: llvm/branches/Apple/Dib/lib/VMCore/Function.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/VMCore/Function.cpp?rev=63825&r1=63824&r2=63825&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/VMCore/Function.cpp (original) +++ llvm/branches/Apple/Dib/lib/VMCore/Function.cpp Wed Feb 4 22:33:04 2009 @@ -175,7 +175,7 @@ ParentModule->getFunctionList().push_back(this); // Ensure intrinsics have the right parameter attributes. - if (unsigned IID = getIntrinsicID(true)) + if (unsigned IID = getIntrinsicID()) setAttributes(Intrinsic::getAttributes(Intrinsic::ID(IID))); } @@ -304,7 +304,7 @@ /// particular intrinsic functions which correspond to this value are defined in /// llvm/Intrinsics.h. /// -unsigned Function::getIntrinsicID(bool noAssert) const { +unsigned Function::getIntrinsicID() const { const ValueName *ValName = this->getValueName(); if (!ValName) return 0; @@ -315,12 +315,9 @@ || Name[2] != 'v' || Name[3] != 'm') return 0; // All intrinsics start with 'llvm.' - assert((Len != 5 || noAssert) && "'llvm.' is an invalid intrinsic name!"); - #define GET_FUNCTION_RECOGNIZER #include "llvm/Intrinsics.gen" #undef GET_FUNCTION_RECOGNIZER - assert(noAssert && "Invalid LLVM intrinsic name"); return 0; } @@ -373,4 +370,9 @@ getType(id, Tys, numTys))); } +// This defines the "Intrinsic::getIntrinsicForGCCBuiltin()" method. +#define GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN +#include "llvm/Intrinsics.gen" +#undef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN + // vim: sw=2 ai Modified: llvm/branches/Apple/Dib/lib/VMCore/Module.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/VMCore/Module.cpp?rev=63825&r1=63824&r2=63825&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/VMCore/Module.cpp (original) +++ llvm/branches/Apple/Dib/lib/VMCore/Module.cpp Wed Feb 4 22:33:04 2009 @@ -171,6 +171,25 @@ return F; } +Constant *Module::getOrInsertTargetIntrinsic(const std::string &Name, + const FunctionType *Ty, + AttrListPtr AttributeList) { + ValueSymbolTable &SymTab = getValueSymbolTable(); + + // See if we have a definition for the specified function already. + GlobalValue *F = dyn_cast_or_null(SymTab.lookup(Name)); + if (F == 0) { + // Nope, add it + Function *New = Function::Create(Ty, GlobalVariable::ExternalLinkage, Name); + New->setAttributes(AttributeList); + FunctionList.push_back(New); + return New; // Return the new prototype. + } + + // Otherwise, we just found the existing function or a prototype. + return F; +} + Constant *Module::getOrInsertFunction(const std::string &Name, const FunctionType *Ty) { AttrListPtr AttributeList = AttrListPtr::get((AttributeWithIndex *)0, 0); Modified: llvm/branches/Apple/Dib/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/VMCore/Verifier.cpp?rev=63825&r1=63824&r2=63825&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/VMCore/Verifier.cpp (original) +++ llvm/branches/Apple/Dib/lib/VMCore/Verifier.cpp Wed Feb 4 22:33:04 2009 @@ -1004,10 +1004,9 @@ void Verifier::visitCallInst(CallInst &CI) { VerifyCallSite(&CI); - if (Function *F = CI.getCalledFunction()) { + if (Function *F = CI.getCalledFunction()) if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) visitIntrinsicFunctionCall(ID, CI); - } } void Verifier::visitInvokeInst(InvokeInst &II) { Removed: llvm/branches/Apple/Dib/test/Assembler/2007-04-15-BadIntrinsic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/Assembler/2007-04-15-BadIntrinsic.ll?rev=63824&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/Assembler/2007-04-15-BadIntrinsic.ll (original) +++ llvm/branches/Apple/Dib/test/Assembler/2007-04-15-BadIntrinsic.ll (removed) @@ -1,9 +0,0 @@ -; RUN: not llvm-as %s -o /dev/null -f |& grep {Call to invalid LLVM intrinsic} - -declare i32 @llvm.foobar(i32 %foo) - -define i32 @test() { - %nada = call i32 @llvm.foobar(i32 0) - ret i32 %nada -} - Modified: llvm/branches/Apple/Dib/utils/TableGen/CodeGenDAGPatterns.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/utils/TableGen/CodeGenDAGPatterns.cpp?rev=63825&r1=63824&r2=63825&view=diff ============================================================================== --- llvm/branches/Apple/Dib/utils/TableGen/CodeGenDAGPatterns.cpp (original) +++ llvm/branches/Apple/Dib/utils/TableGen/CodeGenDAGPatterns.cpp Wed Feb 4 22:33:04 2009 @@ -1303,7 +1303,8 @@ // FIXME: REMOVE OSTREAM ARGUMENT CodeGenDAGPatterns::CodeGenDAGPatterns(RecordKeeper &R) : Records(R) { - Intrinsics = LoadIntrinsics(Records); + Intrinsics = LoadIntrinsics(Records, false); + TgtIntrinsics = LoadIntrinsics(Records, true); ParseNodeInfo(); ParseNodeTransforms(); ParseComplexPatterns(); Modified: llvm/branches/Apple/Dib/utils/TableGen/CodeGenDAGPatterns.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/utils/TableGen/CodeGenDAGPatterns.h?rev=63825&r1=63824&r2=63825&view=diff ============================================================================== --- llvm/branches/Apple/Dib/utils/TableGen/CodeGenDAGPatterns.h (original) +++ llvm/branches/Apple/Dib/utils/TableGen/CodeGenDAGPatterns.h Wed Feb 4 22:33:04 2009 @@ -465,6 +465,7 @@ RecordKeeper &Records; CodeGenTarget Target; std::vector Intrinsics; + std::vector TgtIntrinsics; std::map SDNodes; std::map > SDNodeXForms; @@ -515,18 +516,25 @@ const CodeGenIntrinsic &getIntrinsic(Record *R) const { for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i) if (Intrinsics[i].TheDef == R) return Intrinsics[i]; + for (unsigned i = 0, e = TgtIntrinsics.size(); i != e; ++i) + if (TgtIntrinsics[i].TheDef == R) return TgtIntrinsics[i]; assert(0 && "Unknown intrinsic!"); abort(); } const CodeGenIntrinsic &getIntrinsicInfo(unsigned IID) const { - assert(IID-1 < Intrinsics.size() && "Bad intrinsic ID!"); - return Intrinsics[IID-1]; + if (IID-1 < Intrinsics.size()) + return Intrinsics[IID-1]; + if (IID-Intrinsics.size()-1 < TgtIntrinsics.size()) + return TgtIntrinsics[IID-Intrinsics.size()-1]; + assert(0 && "Bad intrinsic ID!"); } unsigned getIntrinsicID(Record *R) const { for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i) if (Intrinsics[i].TheDef == R) return i; + for (unsigned i = 0, e = TgtIntrinsics.size(); i != e; ++i) + if (TgtIntrinsics[i].TheDef == R) return i + Intrinsics.size(); assert(0 && "Unknown intrinsic!"); abort(); } Modified: llvm/branches/Apple/Dib/utils/TableGen/CodeGenIntrinsics.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/utils/TableGen/CodeGenIntrinsics.h?rev=63825&r1=63824&r2=63825&view=diff ============================================================================== --- llvm/branches/Apple/Dib/utils/TableGen/CodeGenIntrinsics.h (original) +++ llvm/branches/Apple/Dib/utils/TableGen/CodeGenIntrinsics.h Wed Feb 4 22:33:04 2009 @@ -80,7 +80,8 @@ /// LoadIntrinsics - Read all of the intrinsics defined in the specified /// .td file. - std::vector LoadIntrinsics(const RecordKeeper &RC); + std::vector LoadIntrinsics(const RecordKeeper &RC, + bool TargetOnly); } #endif Modified: llvm/branches/Apple/Dib/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/utils/TableGen/CodeGenTarget.cpp?rev=63825&r1=63824&r2=63825&view=diff ============================================================================== --- llvm/branches/Apple/Dib/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/branches/Apple/Dib/utils/TableGen/CodeGenTarget.cpp Wed Feb 4 22:33:04 2009 @@ -426,13 +426,17 @@ // CodeGenIntrinsic Implementation //===----------------------------------------------------------------------===// -std::vector llvm::LoadIntrinsics(const RecordKeeper &RC) { +std::vector llvm::LoadIntrinsics(const RecordKeeper &RC, + bool TargetOnly) { std::vector I = RC.getAllDerivedDefinitions("Intrinsic"); std::vector Result; - for (unsigned i = 0, e = I.size(); i != e; ++i) - Result.push_back(CodeGenIntrinsic(I[i])); + for (unsigned i = 0, e = I.size(); i != e; ++i) { + bool isTarget = I[i]->getValueAsBit("isTarget"); + if (isTarget == TargetOnly) + Result.push_back(CodeGenIntrinsic(I[i])); + } return Result; } Modified: llvm/branches/Apple/Dib/utils/TableGen/IntrinsicEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/utils/TableGen/IntrinsicEmitter.cpp?rev=63825&r1=63824&r2=63825&view=diff ============================================================================== --- llvm/branches/Apple/Dib/utils/TableGen/IntrinsicEmitter.cpp (original) +++ llvm/branches/Apple/Dib/utils/TableGen/IntrinsicEmitter.cpp Wed Feb 4 22:33:04 2009 @@ -25,7 +25,10 @@ void IntrinsicEmitter::run(std::ostream &OS) { EmitSourceFileHeader("Intrinsic Function Source Fragment", OS); - std::vector Ints = LoadIntrinsics(Records); + std::vector Ints = LoadIntrinsics(Records, TargetOnly); + + if (TargetOnly && !Ints.empty()) + TargetPrefix = Ints[0].TargetPrefix; // Emit the enum information. EmitEnumInfo(Ints, OS); @@ -91,12 +94,12 @@ if (Ints[I->second].isOverloaded) OS << " if (Len > " << I->first.size() << " && !memcmp(Name, \"" << I->first << ".\", " - << (I->first.size() + 1) << ")) return Intrinsic::" + << (I->first.size() + 1) << ")) return " << TargetPrefix << "Intrinsic::" << Ints[I->second].EnumName << ";\n"; else OS << " if (Len == " << I->first.size() << " && !memcmp(Name, \"" << I->first << "\", " - << I->first.size() << ")) return Intrinsic::" + << I->first.size() << ")) return " << TargetPrefix << "Intrinsic::" << Ints[I->second].EnumName << ";\n"; } OS << " }\n"; @@ -351,11 +354,13 @@ Ints[i].IS.ParamTypeDefs)].push_back(i); // Loop through the array, emitting one generator for each batch. + std::string IntrinsicStr = TargetPrefix + "Intrinsic::"; + for (MapTy::iterator I = UniqueArgInfos.begin(), E = UniqueArgInfos.end(); I != E; ++I) { for (unsigned i = 0, e = I->second.size(); i != e; ++i) - OS << " case Intrinsic::" << Ints[I->second[i]].EnumName << ":\t\t// " - << Ints[I->second[i]].Name << "\n"; + OS << " case " << IntrinsicStr << Ints[I->second[i]].EnumName + << ":\t\t// " << Ints[I->second[i]].Name << "\n"; const RecPair &ArgTypes = I->first; const std::vector &RetTys = ArgTypes.first; @@ -392,7 +397,11 @@ EmitAttributes(const std::vector &Ints, std::ostream &OS) { OS << "// Add parameter attributes that are not common to all intrinsics.\n"; OS << "#ifdef GET_INTRINSIC_ATTRIBUTES\n"; - OS << "AttrListPtr Intrinsic::getAttributes(ID id) {"; + if (TargetOnly) + OS << "static AttrListPtr getAttributes(" << TargetPrefix + << "Intrinsic::ID id) {"; + else + OS << "AttrListPtr Intrinsic::getAttributes(ID id) {"; OS << " // No intrinsic can throw exceptions.\n"; OS << " Attributes Attr = Attribute::NoUnwind;\n"; OS << " switch (id) {\n"; @@ -404,7 +413,8 @@ switch (Ints[i].ModRef) { default: break; case CodeGenIntrinsic::NoMem: - OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; + OS << " case " << TargetPrefix << "Intrinsic::" << Ints[i].EnumName + << ":\n"; break; } } @@ -415,7 +425,8 @@ default: break; case CodeGenIntrinsic::ReadArgMem: case CodeGenIntrinsic::ReadMem: - OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; + OS << " case " << TargetPrefix << "Intrinsic::" << Ints[i].EnumName + << ":\n"; break; } } @@ -431,7 +442,8 @@ for (unsigned i = 0, e = Ints.size(); i != e; ++i) { if (Ints[i].ArgumentAttributes.empty()) continue; - OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; + OS << " case " << TargetPrefix << "Intrinsic::" << Ints[i].EnumName + << ":\n"; std::vector > ArgAttrs = Ints[i].ArgumentAttributes; @@ -495,7 +507,7 @@ typedef std::map::const_iterator StrMapIterator; static void EmitBuiltinComparisons(StrMapIterator Start, StrMapIterator End, unsigned CharStart, unsigned Indent, - std::ostream &OS) { + std::string TargetPrefix, std::ostream &OS) { if (Start == End) return; // empty range. // Determine what, if anything, is the same about all these strings. @@ -522,7 +534,8 @@ OS << CommonString.size() - CharStart << "))\n"; ++Indent; } - OS << std::string(Indent*2, ' ') << "IntrinsicID = Intrinsic::"; + OS << std::string(Indent*2, ' ') << "IntrinsicID = " << TargetPrefix + << "Intrinsic::"; OS << Start->second << ";\n"; return; } @@ -535,7 +548,8 @@ OS << ", \"" << (CommonString.c_str()+CharStart) << "\", "; OS << CommonString.size()-CharStart << ")) {\n"; - EmitBuiltinComparisons(Start, End, CommonString.size(), Indent+1, OS); + EmitBuiltinComparisons(Start, End, CommonString.size(), Indent+1, + TargetPrefix, OS); OS << std::string(Indent*2, ' ') << "}\n"; return; } @@ -556,7 +570,7 @@ for (++NextChar; NextChar != End && NextChar->first[CharStart] == ThisChar; ++NextChar) /*empty*/; - EmitBuiltinComparisons(I, NextChar, CharStart+1, Indent+1, OS); + EmitBuiltinComparisons(I, NextChar, CharStart+1, Indent+1, TargetPrefix,OS); OS << std::string(Indent*2, ' ') << " break;\n"; I = NextChar; } @@ -566,6 +580,7 @@ /// EmitTargetBuiltins - All of the builtins in the specified map are for the /// same target, and we already checked it. static void EmitTargetBuiltins(const std::map &BIM, + const std::string &TargetPrefix, std::ostream &OS) { // Rearrange the builtins by length. std::vector > BuiltinsByLen; @@ -584,7 +599,7 @@ if (BuiltinsByLen[i].empty()) continue; OS << " case " << i << ":\n"; EmitBuiltinComparisons(BuiltinsByLen[i].begin(), BuiltinsByLen[i].end(), - 0, 3, OS); + 0, 3, TargetPrefix, OS); OS << " break;\n"; } OS << " }\n"; @@ -613,7 +628,22 @@ OS << "// in as BuiltinName, and a target prefix (e.g. 'ppc') is passed\n"; OS << "// in as TargetPrefix. The result is assigned to 'IntrinsicID'.\n"; OS << "#ifdef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN\n"; - OS << " IntrinsicID = Intrinsic::not_intrinsic;\n"; + + if (TargetOnly) { + OS << "static " << TargetPrefix << "Intrinsic::ID " + << "getIntrinsicForGCCBuiltin(const char " + << "*TargetPrefix, const char *BuiltinName) {\n"; + OS << " " << TargetPrefix << "Intrinsic::ID IntrinsicID = "; + } else { + OS << "Intrinsic::ID Intrinsic::getIntrinsicForGCCBuiltin(const char " + << "*TargetPrefix, const char *BuiltinName) {\n"; + OS << " Intrinsic::ID IntrinsicID = "; + } + + if (TargetOnly) + OS << "(" << TargetPrefix<< "Intrinsic::ID)"; + + OS << "Intrinsic::not_intrinsic;\n"; // Note: this could emit significantly better code if we cared. for (BIMTy::iterator I = BuiltinMap.begin(), E = BuiltinMap.end();I != E;++I){ @@ -625,8 +655,10 @@ OS << "{\n"; // Emit the comparisons for this target prefix. - EmitTargetBuiltins(I->second, OS); + EmitTargetBuiltins(I->second, TargetPrefix, OS); OS << " }\n"; } + OS << " return IntrinsicID;\n"; + OS << "}\n"; OS << "#endif\n\n"; } Modified: llvm/branches/Apple/Dib/utils/TableGen/IntrinsicEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/utils/TableGen/IntrinsicEmitter.h?rev=63825&r1=63824&r2=63825&view=diff ============================================================================== --- llvm/branches/Apple/Dib/utils/TableGen/IntrinsicEmitter.h (original) +++ llvm/branches/Apple/Dib/utils/TableGen/IntrinsicEmitter.h Wed Feb 4 22:33:04 2009 @@ -20,9 +20,12 @@ namespace llvm { class IntrinsicEmitter : public TableGenBackend { RecordKeeper &Records; + bool TargetOnly; + std::string TargetPrefix; public: - IntrinsicEmitter(RecordKeeper &R) : Records(R) {} + IntrinsicEmitter(RecordKeeper &R, bool T = false) + : Records(R), TargetOnly(T) {} void run(std::ostream &OS); Modified: llvm/branches/Apple/Dib/utils/TableGen/TableGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/utils/TableGen/TableGen.cpp?rev=63825&r1=63824&r2=63825&view=diff ============================================================================== --- llvm/branches/Apple/Dib/utils/TableGen/TableGen.cpp (original) +++ llvm/branches/Apple/Dib/utils/TableGen/TableGen.cpp Wed Feb 4 22:33:04 2009 @@ -49,6 +49,7 @@ GenFastISel, GenSubtarget, GenIntrinsic, + GenTgtIntrinsic, GenLLVMCConf, PrintEnums }; @@ -82,6 +83,8 @@ "Generate subtarget enumerations"), clEnumValN(GenIntrinsic, "gen-intrinsic", "Generate intrinsic information"), + clEnumValN(GenTgtIntrinsic, "gen-tgt-intrinsic", + "Generate target intrinsic information"), clEnumValN(GenLLVMCConf, "gen-llvmc", "Generate LLVMC configuration library"), clEnumValN(PrintEnums, "print-enums", @@ -190,6 +193,9 @@ case GenIntrinsic: IntrinsicEmitter(Records).run(*Out); break; + case GenTgtIntrinsic: + IntrinsicEmitter(Records, true).run(*Out); + break; case GenLLVMCConf: LLVMCConfigurationEmitter(Records).run(*Out); break; From isanbard at gmail.com Wed Feb 4 22:33:58 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Feb 2009 04:33:58 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63826 - /llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-convert.cpp Message-ID: <200902050433.n154Xw8k010637@zion.cs.uiuc.edu> Author: void Date: Wed Feb 4 22:33:57 2009 New Revision: 63826 URL: http://llvm.org/viewvc/llvm-project?rev=63826&view=rev Log: Fix in llvm-gcc FE for r63765. Patch by Dale! Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-convert.cpp?rev=63826&r1=63825&r2=63826&view=diff ============================================================================== --- llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/branches/Apple/Dib/gcc/llvm-convert.cpp Wed Feb 4 22:33:57 2009 @@ -4548,11 +4548,8 @@ // If this builtin directly corresponds to an LLVM intrinsic, get the // IntrinsicID now. const char *BuiltinName = IDENTIFIER_POINTER(DECL_NAME(fndecl)); - Intrinsic::ID IntrinsicID = Intrinsic::not_intrinsic; -#define GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN -#include "llvm/Intrinsics.gen" -#undef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN - + Intrinsic::ID IntrinsicID = + Intrinsic::getIntrinsicForGCCBuiltin(TargetPrefix, BuiltinName); if (IntrinsicID == Intrinsic::not_intrinsic) { if (EmitFrontendExpandedBuiltinCall(exp, fndecl, DestLoc, Result)) return true; From isanbard at gmail.com Wed Feb 4 22:37:03 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Feb 2009 04:37:03 -0000 Subject: [llvm-commits] [llvm] r63827 - /llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200902050437.n154b4vS010786@zion.cs.uiuc.edu> Author: void Date: Wed Feb 4 22:37:03 2009 New Revision: 63827 URL: http://llvm.org/viewvc/llvm-project?rev=63827&view=rev Log: Pull r63760 into Dib: Avoids generating a legalization assert for the case where a vector type is legal but when legalizing the operation, we split the vector type and generate a library call whose type needs to be promoted. For example, X86 with SSE on but MMX off, a divide v2i64 will be scalarized to 2 calls to a library using i64. Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63827&r1=63826&r2=63827&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Feb 4 22:37:03 2009 @@ -68,6 +68,11 @@ /// being legalized (which could lead to non-serialized call sequences). bool IsLegalizingCall; + /// IsLegalizingCallArguments - This member is used only for the purpose + /// of providing assert to check for LegalizeTypes because legalizing an + /// operation might introduce call nodes that might need type legalization. + bool IsLegalizingCallArgs; + enum LegalizeAction { Legal, // The target natively supports this operation. Promote, // This operation should be executed in a larger type. @@ -368,7 +373,8 @@ void SelectionDAGLegalize::LegalizeDAG() { LastCALLSEQ_END = DAG.getEntryNode(); IsLegalizingCall = false; - + IsLegalizingCallArgs = false; + // The legalize process is inherently a bottom-up recursive process (users // legalize their uses before themselves). Given infinite stack space, we // could just start legalizing on the root and traverse the whole graph. In @@ -503,7 +509,7 @@ // those) or for build vector used as a mask for a vector shuffle. // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957. assert((TypesNeedLegalizing || getTypeAction(VT) == Legal || - Op.getOpcode() == ISD::TargetConstant || + IsLegalizingCallArgs || Op.getOpcode() == ISD::TargetConstant || Op.getOpcode() == ISD::BUILD_VECTOR) && "Illegal type introduced after type legalization?"); switch (getTypeAction(VT)) { @@ -1804,11 +1810,13 @@ // Recursively Legalize all of the inputs of the call end that do not lead // to this call start. This ensures that any libcalls that need be inserted // are inserted *before* the CALLSEQ_START. + IsLegalizingCallArgs = true; {SmallPtrSet NodesLeadingTo; for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, NodesLeadingTo); } + IsLegalizingCallArgs = false; // Now that we legalized all of the inputs (which may have inserted // libcalls) create the new CALLSEQ_START node. From isanbard at gmail.com Wed Feb 4 22:41:01 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Feb 2009 04:41:01 -0000 Subject: [llvm-commits] [llvm] r63828 - in /llvm/branches/Apple/Dib: include/llvm/Target/TargetIntrinsicInfo.h lib/Target/TargetIntrinsicInfo.cpp Message-ID: <200902050441.n154f1Zr010954@zion.cs.uiuc.edu> Author: void Date: Wed Feb 4 22:41:00 2009 New Revision: 63828 URL: http://llvm.org/viewvc/llvm-project?rev=63828&view=rev Log: Add missing files from r63765. Added: llvm/branches/Apple/Dib/include/llvm/Target/TargetIntrinsicInfo.h llvm/branches/Apple/Dib/lib/Target/TargetIntrinsicInfo.cpp Added: llvm/branches/Apple/Dib/include/llvm/Target/TargetIntrinsicInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/Target/TargetIntrinsicInfo.h?rev=63828&view=auto ============================================================================== --- llvm/branches/Apple/Dib/include/llvm/Target/TargetIntrinsicInfo.h (added) +++ llvm/branches/Apple/Dib/include/llvm/Target/TargetIntrinsicInfo.h Wed Feb 4 22:41:00 2009 @@ -0,0 +1,48 @@ +//===-- llvm/Target/TargetIntrinsicInfo.h - Instruction Info ----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the target intrinsic instructions to the code generator. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_TARGET_TARGETINTRINSICINFO_H +#define LLVM_TARGET_TARGETINTRINSICINFO_H + +namespace llvm { + +class Function; +class Module; + +//--------------------------------------------------------------------------- +/// +/// TargetIntrinsicInfo - Interface to description of machine instruction set +/// +class TargetIntrinsicInfo { + + const char **Intrinsics; // Raw array to allow static init'n + unsigned NumIntrinsics; // Number of entries in the desc array + + TargetIntrinsicInfo(const TargetIntrinsicInfo &); // DO NOT IMPLEMENT + void operator=(const TargetIntrinsicInfo &); // DO NOT IMPLEMENT +public: + TargetIntrinsicInfo(const char **desc, unsigned num); + virtual ~TargetIntrinsicInfo(); + + unsigned getNumIntrinsics() const { return NumIntrinsics; } + + virtual Function *getDeclaration(Module *M, const char *BuiltinName) const { + return 0; + } + + virtual unsigned getIntrinsicID(Function *F) const { return 0; } +}; + +} // End llvm namespace + +#endif Added: llvm/branches/Apple/Dib/lib/Target/TargetIntrinsicInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/TargetIntrinsicInfo.cpp?rev=63828&view=auto ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/TargetIntrinsicInfo.cpp (added) +++ llvm/branches/Apple/Dib/lib/Target/TargetIntrinsicInfo.cpp Wed Feb 4 22:41:00 2009 @@ -0,0 +1,22 @@ +//===-- TargetIntrinsicInfo.cpp - Target Instruction Information ----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the TargetIntrinsicInfo class. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Target/TargetIntrinsicInfo.h" +using namespace llvm; + +TargetIntrinsicInfo::TargetIntrinsicInfo(const char **desc, unsigned count) + : Intrinsics(desc), NumIntrinsics(count) { +} + +TargetIntrinsicInfo::~TargetIntrinsicInfo() { +} From isanbard at gmail.com Wed Feb 4 22:41:18 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Feb 2009 04:41:18 -0000 Subject: [llvm-commits] [llvm] r63829 - /llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle-30.ll Message-ID: <200902050441.n154fI4d010974@zion.cs.uiuc.edu> Author: void Date: Wed Feb 4 22:41:18 2009 New Revision: 63829 URL: http://llvm.org/viewvc/llvm-project?rev=63829&view=rev Log: Add testcase. Added: llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle-30.ll Added: llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle-30.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle-30.ll?rev=63829&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle-30.ll (added) +++ llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle-30.ll Wed Feb 4 22:41:18 2009 @@ -0,0 +1,23 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 -disable-mmx -o %t -f +; RUN: grep pshufhw %t | grep 161 | count 1 +; RUN: grep pslldq %t | count 1 + + + +; Test case when creating pshufhw, we incorrectly set the higher order bit +; for an undef, +define void @test(<8 x i16>* %dest, <8 x i16> %in) { +entry: + %0 = load <8 x i16>* %dest + %1 = shufflevector <8 x i16> %0, <8 x i16> %in, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 13, i32 undef, i32 14, i32 14> + store <8 x i16> %1, <8 x i16>* %dest + ret void +} + +; A test case where we shouldn't generate a punpckldq but a pshufd and a pslldq +define void @test2(<4 x i32>* %dest, <4 x i32> %in) { +entry: + %0 = shufflevector <4 x i32> %in, <4 x i32> , <4 x i32> < i32 undef, i32 5, i32 undef, i32 2> + store <4 x i32> %0, <4 x i32>* %dest + ret void +} \ No newline at end of file From isanbard at gmail.com Wed Feb 4 22:41:57 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Feb 2009 04:41:57 -0000 Subject: [llvm-commits] [llvm] r63830 - /llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200902050441.n154fwuq011011@zion.cs.uiuc.edu> Author: void Date: Wed Feb 4 22:41:57 2009 New Revision: 63830 URL: http://llvm.org/viewvc/llvm-project?rev=63830&view=rev Log: Pull r63702 into Dib: Fixes a case where we generate an incorrect mask for pshfhw in the presence of undefs and incorrectly determining if we have punpckldq. Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp?rev=63830&r1=63829&r2=63830&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp Wed Feb 4 22:41:57 2009 @@ -2308,7 +2308,7 @@ if (!isUndefOrEqual(BitI, j)) return false; if (V2IsSplat) { - if (isUndefOrEqual(BitI1, NumElts)) + if (!isUndefOrEqual(BitI1, NumElts)) return false; } else { if (!isUndefOrEqual(BitI1, j + NumElts)) @@ -2643,9 +2643,10 @@ for (unsigned i = 7; i >= 4; --i) { unsigned Val = 0; SDValue Arg = N->getOperand(i); - if (Arg.getOpcode() != ISD::UNDEF) + if (Arg.getOpcode() != ISD::UNDEF) { Val = cast(Arg)->getZExtValue(); - Mask |= (Val - 4); + Mask |= (Val - 4); + } if (i != 4) Mask <<= 2; } @@ -4160,10 +4161,10 @@ // new vector_shuffle with the corrected mask. SDValue NewMask = NormalizeMask(PermMask, DAG); if (NewMask.getNode() != PermMask.getNode()) { - if (X86::isUNPCKLMask(PermMask.getNode(), true)) { + if (X86::isUNPCKLMask(NewMask.getNode(), true)) { SDValue NewMask = getUnpacklMask(NumElems, DAG); return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); - } else if (X86::isUNPCKHMask(PermMask.getNode(), true)) { + } else if (X86::isUNPCKHMask(NewMask.getNode(), true)) { SDValue NewMask = getUnpackhMask(NumElems, DAG); return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); } From wangmp at apple.com Wed Feb 4 22:47:43 2009 From: wangmp at apple.com (Mon P Wang) Date: Thu, 05 Feb 2009 04:47:43 -0000 Subject: [llvm-commits] [llvm] r63831 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200902050447.n154lijM012427@zion.cs.uiuc.edu> Author: wangmp Date: Wed Feb 4 22:47:42 2009 New Revision: 63831 URL: http://llvm.org/viewvc/llvm-project?rev=63831&view=rev Log: Fix a bug where we were not emitting a cvt rnd sat node for converting between a unsigned integer and signed integer. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63831&r1=63830&r2=63831&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Feb 4 22:47:42 2009 @@ -1170,8 +1170,10 @@ SDValue Val, SDValue DTy, SDValue STy, SDValue Rnd, SDValue Sat, ISD::CvtCode Code) { - // If the src and dest types are the same, no conversion is necessary. - if (DTy == STy) + // If the src and dest types are the same and the conversion is between + // integer types of the same sign or two floats, no conversion is necessary. + if (DTy == STy && + (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF)) return Val; FoldingSetNodeID ID; From isanbard at gmail.com Wed Feb 4 22:52:14 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Feb 2009 04:52:14 -0000 Subject: [llvm-commits] [llvm] r63832 - /llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200902050452.n154qEUD013688@zion.cs.uiuc.edu> Author: void Date: Wed Feb 4 22:52:13 2009 New Revision: 63832 URL: http://llvm.org/viewvc/llvm-project?rev=63832&view=rev Log: Pull r63831 into Dib: Fix a bug where we were not emitting a cvt rnd sat node for converting between a unsigned integer and signed integer. Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63832&r1=63831&r2=63832&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Feb 4 22:52:13 2009 @@ -1178,8 +1178,10 @@ SDValue SelectionDAG::getConvertRndSat(MVT VT, SDValue Val, SDValue DTy, SDValue STy, SDValue Rnd, SDValue Sat, ISD::CvtCode Code) { - // If the src and dest types are the same, no conversion is necessary. - if (DTy == STy) + // If the src and dest types are the same and the conversion is between + // integer types of the same sign or two floats, no conversion is necessary. + if (DTy == STy && + (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF)) return Val; FoldingSetNodeID ID; From tonic at nondot.org Wed Feb 4 23:00:51 2009 From: tonic at nondot.org (Tanya Lattner) Date: Thu, 05 Feb 2009 05:00:51 -0000 Subject: [llvm-commits] [llvm] r63833 - /llvm/branches/release_25/utils/Makefile Message-ID: <200902050500.n1550qac024514@zion.cs.uiuc.edu> Author: tbrethou Date: Wed Feb 4 23:00:51 2009 New Revision: 63833 URL: http://llvm.org/viewvc/llvm-project?rev=63833&view=rev Log: Disable building unittests unless PR3487 can be fixed. Modified: llvm/branches/release_25/utils/Makefile Modified: llvm/branches/release_25/utils/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/utils/Makefile?rev=63833&r1=63832&r2=63833&view=diff ============================================================================== --- llvm/branches/release_25/utils/Makefile (original) +++ llvm/branches/release_25/utils/Makefile Wed Feb 4 23:00:51 2009 @@ -8,7 +8,7 @@ ##===----------------------------------------------------------------------===## LEVEL = .. -PARALLEL_DIRS := TableGen fpcmp PerfectShuffle unittest +PARALLEL_DIRS := TableGen fpcmp PerfectShuffle EXTRA_DIST := cgiplotNLT.pl check-each-file codegen-diff countloc.sh cvsupdate \ DSAclean.py DSAextract.py emacs findsym.pl GenLibDeps.pl \ From nicholas at mxc.ca Wed Feb 4 23:36:02 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 05 Feb 2009 05:36:02 -0000 Subject: [llvm-commits] [llvm] r63834 - /llvm/trunk/tools/gold/gold-plugin.cpp Message-ID: <200902050536.n155a2Wf002890@zion.cs.uiuc.edu> Author: nicholas Date: Wed Feb 4 23:36:01 2009 New Revision: 63834 URL: http://llvm.org/viewvc/llvm-project?rev=63834&view=rev Log: It's not obvious, but lto_module_create_from_memory doesn't need to use the buffer after it creates the Module. Thus, we don't need to store this pointer in claimed_file. Modified: llvm/trunk/tools/gold/gold-plugin.cpp Modified: llvm/trunk/tools/gold/gold-plugin.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/gold-plugin.cpp?rev=63834&r1=63833&r2=63834&view=diff ============================================================================== --- llvm/trunk/tools/gold/gold-plugin.cpp (original) +++ llvm/trunk/tools/gold/gold-plugin.cpp Wed Feb 4 23:36:01 2009 @@ -45,7 +45,6 @@ struct claimed_file { lto_module_t M; void *handle; - void *buf; std::vector syms; }; @@ -197,7 +196,6 @@ cf.M = buf ? lto_module_create_from_memory(buf, file->filesize) : lto_module_create(file->name); - cf.buf = buf; if (!cf.M) { (*message)(LDPL_ERROR, "Failed to create LLVM module: %s", lto_get_error_message()); @@ -334,10 +332,6 @@ objFile->close(); lto_codegen_dispose(cg); - for (std::list::iterator I = Modules.begin(), - E = Modules.end(); I != E; ++I) { - free(I->buf); - } if ((*add_input_file)(const_cast(uniqueObjPath.c_str())) != LDPS_OK) { (*message)(LDPL_ERROR, "Unable to add .o file to the link."); From sabre at nondot.org Wed Feb 4 23:37:35 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Feb 2009 05:37:35 -0000 Subject: [llvm-commits] [test-suite] r63835 - /test-suite/trunk/MultiSource/Applications/sqlite3/sqlite3.h Message-ID: <200902050537.n155bZqk002953@zion.cs.uiuc.edu> Author: lattner Date: Wed Feb 4 23:37:35 2009 New Revision: 63835 URL: http://llvm.org/viewvc/llvm-project?rev=63835&view=rev Log: add header file needed by this test, PR3479 Added: test-suite/trunk/MultiSource/Applications/sqlite3/sqlite3.h Added: test-suite/trunk/MultiSource/Applications/sqlite3/sqlite3.h URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Applications/sqlite3/sqlite3.h?rev=63835&view=auto ============================================================================== --- test-suite/trunk/MultiSource/Applications/sqlite3/sqlite3.h (added) +++ test-suite/trunk/MultiSource/Applications/sqlite3/sqlite3.h Wed Feb 4 23:37:35 2009 @@ -0,0 +1,2679 @@ +/* +** 2001 September 15 +** +** The author disclaims copyright to this source code. In place of +** a legal notice, here is a blessing: +** +** May you do good and not evil. +** May you find forgiveness for yourself and forgive others. +** May you share freely, never taking more than you give. +** +************************************************************************* +** This header file defines the interface that the SQLite library +** presents to client programs. If a C-function, structure, datatype, +** or constant definition does not appear in this file, then it is +** not a published API of SQLite, is subject to change without +** notice, and should not be referenced by programs that use SQLite. +** +** Some of the definitions that are in this file are marked as +** "experimental". Experimental interfaces are normally new +** features recently added to SQLite. We do not anticipate changes +** to experimental interfaces but reserve to make minor changes if +** experience from use "in the wild" suggest such changes are prudent. +** +** The official C-language API documentation for SQLite is derived +** from comments in this file. This file is the authoritative source +** on how SQLite interfaces are suppose to operate. +** +** The name of this file under configuration management is "sqlite.h.in". +** The makefile makes some minor changes to this file (such as inserting +** the version number) and changes its name to "sqlite3.h" as +** part of the build process. +** +** @(#) $Id: sqlite.h.in,v 1.212 2007/06/14 20:57:19 drh Exp $ +*/ +#ifndef _SQLITE3_H_ +#define _SQLITE3_H_ +#include /* Needed for the definition of va_list */ + +/* +** Make sure we can call this stuff from C++. +*/ +#ifdef __cplusplus +extern "C" { +#endif + +/* +** Make sure these symbols where not defined by some previous header +** file. +*/ +#ifdef SQLITE_VERSION +# undef SQLITE_VERSION +#endif +#ifdef SQLITE_VERSION_NUMBER +# undef SQLITE_VERSION_NUMBER +#endif + +/* +** CAPI3REF: Compile-Time Library Version Numbers +** +** The version of the SQLite library is contained in the sqlite3.h +** header file in a #define named SQLITE_VERSION. The SQLITE_VERSION +** macro resolves to a string constant. +** +** The format of the version string is "X.Y.Z", where +** X is the major version number, Y is the minor version number and Z +** is the release number. The X.Y.Z might be followed by "alpha" or "beta". +** For example "3.1.1beta". +** +** The X value is always 3 in SQLite. The X value only changes when +** backwards compatibility is broken and we intend to never break +** backwards compatibility. The Y value only changes when +** there are major feature enhancements that are forwards compatible +** but not backwards compatible. The Z value is incremented with +** each release but resets back to 0 when Y is incremented. +** +** The SQLITE_VERSION_NUMBER is an integer with the value +** (X*1000000 + Y*1000 + Z). For example, for version "3.1.1beta", +** SQLITE_VERSION_NUMBER is set to 3001001. To detect if they are using +** version 3.1.1 or greater at compile time, programs may use the test +** (SQLITE_VERSION_NUMBER>=3001001). +** +** See also: [sqlite3_libversion()] and [sqlite3_libversion_number()]. +*/ +#define SQLITE_VERSION "3.4.0" +#define SQLITE_VERSION_NUMBER 3004000 + +/* +** CAPI3REF: Run-Time Library Version Numbers +** +** These routines return values equivalent to the header constants +** [SQLITE_VERSION] and [SQLITE_VERSION_NUMBER]. The values returned +** by this routines should only be different from the header values +** if you compile your program using an sqlite3.h header from a +** different version of SQLite that the version of the library you +** link against. +** +** The sqlite3_version[] string constant contains the text of the +** [SQLITE_VERSION] string. The sqlite3_libversion() function returns +** a poiner to the sqlite3_version[] string constant. The function +** is provided for DLL users who can only access functions and not +** constants within the DLL. +*/ +extern const char sqlite3_version[]; +const char *sqlite3_libversion(void); +int sqlite3_libversion_number(void); + +/* +** CAPI3REF: Database Connection Handle +** +** Each open SQLite database is represented by pointer to an instance of the +** opaque structure named "sqlite3". It is useful to think of an sqlite3 +** pointer as an object. The [sqlite3_open] interface is its constructor +** and [sqlite3_close] is its destructor. There are many other interfaces +** (such as [sqlite3_prepare_v2], [sqlite3_create_function], and +** [sqlite3_busy_timeout] to name but three) that are methods on this +** object. +*/ +typedef struct sqlite3 sqlite3; + + +/* +** CAPI3REF: 64-Bit Integer Types +** +** Some compilers do not support the "long long" datatype. So we have +** to do compiler-specific typedefs for 64-bit signed and unsigned integers. +** +** Many SQLite interface functions require a 64-bit integer arguments. +** Those interfaces are declared using this typedef. +*/ +#ifdef SQLITE_INT64_TYPE + typedef SQLITE_INT64_TYPE sqlite_int64; + typedef unsigned SQLITE_INT64_TYPE sqlite_uint64; +#elif defined(_MSC_VER) || defined(__BORLANDC__) + typedef __int64 sqlite_int64; + typedef unsigned __int64 sqlite_uint64; +#else + typedef long long int sqlite_int64; + typedef unsigned long long int sqlite_uint64; +#endif + +/* +** If compiling for a processor that lacks floating point support, +** substitute integer for floating-point +*/ +#ifdef SQLITE_OMIT_FLOATING_POINT +# define double sqlite_int64 +#endif + +/* +** CAPI3REF: Closing A Database Connection +** +** Call this function with a pointer to a structure that was previously +** returned from [sqlite3_open()] and the corresponding database will by +** closed. +** +** All SQL statements prepared using [sqlite3_prepare_v2()] or +** [sqlite3_prepare16_v2()] must be destroyed using [sqlite3_finalize()] +** before this routine is called. Otherwise, SQLITE_BUSY is returned and the +** database connection remains open. +*/ +int sqlite3_close(sqlite3 *); + +/* +** The type for a callback function. +** This is legacy and deprecated. It is included for historical +** compatibility and is not documented. +*/ +typedef int (*sqlite3_callback)(void*,int,char**, char**); + +/* +** CAPI3REF: One-Step Query Execution Interface +** +** This interface is used to do a one-time evaluatation of zero +** or more SQL statements. UTF-8 text of the SQL statements to +** be evaluted is passed in as the second parameter. The statements +** are prepared one by one using [sqlite3_prepare()], evaluated +** using [sqlite3_step()], then destroyed using [sqlite3_finalize()]. +** +** If one or more of the SQL statements are queries, then +** the callback function specified by the 3rd parameter is +** invoked once for each row of the query result. This callback +** should normally return 0. If the callback returns a non-zero +** value then the query is aborted, all subsequent SQL statements +** are skipped and the sqlite3_exec() function returns the SQLITE_ABORT. +** +** The 4th parameter to this interface is an arbitrary pointer that is +** passed through to the callback function as its first parameter. +** +** The 2nd parameter to the callback function is the number of +** columns in the query result. The 3rd parameter to the callback +** is an array of strings holding the values for each column +** as extracted using [sqlite3_column_text()]. +** The 4th parameter to the callback is an array of strings +** obtained using [sqlite3_column_name()] and holding +** the names of each column. +** +** The callback function may be NULL, even for queries. A NULL +** callback is not an error. It just means that no callback +** will be invoked. +** +** If an error occurs while parsing or evaluating the SQL (but +** not while executing the callback) then an appropriate error +** message is written into memory obtained from [sqlite3_malloc()] and +** *errmsg is made to point to that message. The calling function +** is responsible for freeing the memory that holds the error +** message. Use [sqlite3_free()] for this. If errmsg==NULL, +** then no error message is ever written. +** +** The return value is is SQLITE_OK if there are no errors and +** some other [SQLITE_OK | return code] if there is an error. +** The particular return value depends on the type of error. +** +*/ +int sqlite3_exec( + sqlite3*, /* An open database */ + const char *sql, /* SQL to be evaluted */ + int (*callback)(void*,int,char**,char**), /* Callback function */ + void *, /* 1st argument to callback */ + char **errmsg /* Error msg written here */ +); + +/* +** CAPI3REF: Result Codes +** KEYWORDS: SQLITE_OK +** +** Many SQLite functions return an integer result code from the set shown +** above in order to indicates success or failure. +** +** The result codes above are the only ones returned by SQLite in its +** default configuration. However, the [sqlite3_extended_result_codes()] +** API can be used to set a database connectoin to return more detailed +** result codes. +** +** See also: [SQLITE_IOERR_READ | extended result codes] +** +*/ +#define SQLITE_OK 0 /* Successful result */ +/* beginning-of-error-codes */ +#define SQLITE_ERROR 1 /* SQL error or missing database */ +#define SQLITE_INTERNAL 2 /* NOT USED. Internal logic error in SQLite */ +#define SQLITE_PERM 3 /* Access permission denied */ +#define SQLITE_ABORT 4 /* Callback routine requested an abort */ +#define SQLITE_BUSY 5 /* The database file is locked */ +#define SQLITE_LOCKED 6 /* A table in the database is locked */ +#define SQLITE_NOMEM 7 /* A malloc() failed */ +#define SQLITE_READONLY 8 /* Attempt to write a readonly database */ +#define SQLITE_INTERRUPT 9 /* Operation terminated by sqlite3_interrupt()*/ +#define SQLITE_IOERR 10 /* Some kind of disk I/O error occurred */ +#define SQLITE_CORRUPT 11 /* The database disk image is malformed */ +#define SQLITE_NOTFOUND 12 /* NOT USED. Table or record not found */ +#define SQLITE_FULL 13 /* Insertion failed because database is full */ +#define SQLITE_CANTOPEN 14 /* Unable to open the database file */ +#define SQLITE_PROTOCOL 15 /* NOT USED. Database lock protocol error */ +#define SQLITE_EMPTY 16 /* Database is empty */ +#define SQLITE_SCHEMA 17 /* The database schema changed */ +#define SQLITE_TOOBIG 18 /* String or BLOB exceeds size limit */ +#define SQLITE_CONSTRAINT 19 /* Abort due to contraint violation */ +#define SQLITE_MISMATCH 20 /* Data type mismatch */ +#define SQLITE_MISUSE 21 /* Library used incorrectly */ +#define SQLITE_NOLFS 22 /* Uses OS features not supported on host */ +#define SQLITE_AUTH 23 /* Authorization denied */ +#define SQLITE_FORMAT 24 /* Auxiliary database format error */ +#define SQLITE_RANGE 25 /* 2nd parameter to sqlite3_bind out of range */ +#define SQLITE_NOTADB 26 /* File opened that is not a database file */ +#define SQLITE_ROW 100 /* sqlite3_step() has another row ready */ +#define SQLITE_DONE 101 /* sqlite3_step() has finished executing */ +/* end-of-error-codes */ + +/* +** CAPI3REF: Extended Result Codes +** +** In its default configuration, SQLite API routines return one of 26 integer +** result codes described at result-codes. However, experience has shown that +** many of these result codes are too course-grained. They do not provide as +** much information about problems as users might like. In an effort to +** address this, newer versions of SQLite (version 3.3.8 and later) include +** support for additional result codes that provide more detailed information +** about errors. The extended result codes are enabled (or disabled) for +** each database +** connection using the [sqlite3_extended_result_codes()] API. +** +** Some of the available extended result codes are listed above. +** We expect the number of extended result codes will be expand +** over time. Software that uses extended result codes should expect +** to see new result codes in future releases of SQLite. +** +** The symbolic name for an extended result code always contains a related +** primary result code as a prefix. Primary result codes contain a single +** "_" character. Extended result codes contain two or more "_" characters. +** The numeric value of an extended result code can be converted to its +** corresponding primary result code by masking off the lower 8 bytes. +** +** The SQLITE_OK result code will never be extended. It will always +** be exactly zero. +*/ +#define SQLITE_IOERR_READ (SQLITE_IOERR | (1<<8)) +#define SQLITE_IOERR_SHORT_READ (SQLITE_IOERR | (2<<8)) +#define SQLITE_IOERR_WRITE (SQLITE_IOERR | (3<<8)) +#define SQLITE_IOERR_FSYNC (SQLITE_IOERR | (4<<8)) +#define SQLITE_IOERR_DIR_FSYNC (SQLITE_IOERR | (5<<8)) +#define SQLITE_IOERR_TRUNCATE (SQLITE_IOERR | (6<<8)) +#define SQLITE_IOERR_FSTAT (SQLITE_IOERR | (7<<8)) +#define SQLITE_IOERR_UNLOCK (SQLITE_IOERR | (8<<8)) +#define SQLITE_IOERR_RDLOCK (SQLITE_IOERR | (9<<8)) +#define SQLITE_IOERR_DELETE (SQLITE_IOERR | (10<<8)) +#define SQLITE_IOERR_BLOCKED (SQLITE_IOERR | (11<<8)) + +/* +** CAPI3REF: Enable Or Disable Extended Result Codes +** +** This routine enables or disables the +** [SQLITE_IOERR_READ | extended result codes] feature. +** By default, SQLite API routines return one of only 26 integer +** [SQLITE_OK | result codes]. When extended result codes +** are enabled by this routine, the repetoire of result codes can be +** much larger and can (hopefully) provide more detailed information +** about the cause of an error. +** +** The second argument is a boolean value that turns extended result +** codes on and off. Extended result codes are off by default for +** backwards compatibility with older versions of SQLite. +*/ +int sqlite3_extended_result_codes(sqlite3*, int onoff); + +/* +** CAPI3REF: Last Insert Rowid +** +** Each entry in an SQLite table has a unique 64-bit signed integer key +** called the "rowid". The rowid is always available as an undeclared +** column named ROWID, OID, or _ROWID_. If the table has a column of +** type INTEGER PRIMARY KEY then that column is another an alias for the +** rowid. +** +** This routine returns the rowid of the most recent INSERT into +** the database from the database connection given in the first +** argument. If no inserts have ever occurred on this database +** connection, zero is returned. +** +** If an INSERT occurs within a trigger, then the rowid of the +** inserted row is returned by this routine as long as the trigger +** is running. But once the trigger terminates, the value returned +** by this routine reverts to the last value inserted before the +** trigger fired. +*/ +sqlite_int64 sqlite3_last_insert_rowid(sqlite3*); + +/* +** CAPI3REF: Count The Number Of Rows Modified +** +** This function returns the number of database rows that were changed +** (or inserted or deleted) by the most recent SQL statement. Only +** changes that are directly specified by the INSERT, UPDATE, or +** DELETE statement are counted. Auxiliary changes caused by +** triggers are not counted. Use the [sqlite3_total_changes()] function +** to find the total number of changes including changes caused by triggers. +** +** Within the body of a trigger, the sqlite3_changes() interface can be +** called to find the number of +** changes in the most recently completed INSERT, UPDATE, or DELETE +** statement within the body of the trigger. +** +** All changes are counted, even if they were later undone by a +** ROLLBACK or ABORT. Except, changes associated with creating and +** dropping tables are not counted. +** +** If a callback invokes [sqlite3_exec()] or [sqlite3_step()] recursively, +** then the changes in the inner, recursive call are counted together +** with the changes in the outer call. +** +** SQLite implements the command "DELETE FROM table" without a WHERE clause +** by dropping and recreating the table. (This is much faster than going +** through and deleting individual elements form the table.) Because of +** this optimization, the change count for "DELETE FROM table" will be +** zero regardless of the number of elements that were originally in the +** table. To get an accurate count of the number of rows deleted, use +** "DELETE FROM table WHERE 1" instead. +*/ +int sqlite3_changes(sqlite3*); + +/* +** CAPI3REF: Total Number Of Rows Modified +*** +** This function returns the number of database rows that have been +** modified by INSERT, UPDATE or DELETE statements since the database handle +** was opened. This includes UPDATE, INSERT and DELETE statements executed +** as part of trigger programs. All changes are counted as soon as the +** statement that makes them is completed (when the statement handle is +** passed to [sqlite3_reset()] or [sqlite_finalise()]). +** +** See also the [sqlite3_change()] interface. +** +** SQLite implements the command "DELETE FROM table" without a WHERE clause +** by dropping and recreating the table. (This is much faster than going +** through and deleting individual elements form the table.) Because of +** this optimization, the change count for "DELETE FROM table" will be +** zero regardless of the number of elements that were originally in the +** table. To get an accurate count of the number of rows deleted, use +** "DELETE FROM table WHERE 1" instead. +*/ +int sqlite3_total_changes(sqlite3*); + +/* +** CAPI3REF: Interrupt A Long-Running Query +** +** This function causes any pending database operation to abort and +** return at its earliest opportunity. This routine is typically +** called in response to a user action such as pressing "Cancel" +** or Ctrl-C where the user wants a long query operation to halt +** immediately. +** +** It is safe to call this routine from a thread different from the +** thread that is currently running the database operation. +** +** The SQL operation that is interrupted will return [SQLITE_INTERRUPT]. +** If an interrupted operation was an update that is inside an +** explicit transaction, then the entire transaction will be rolled +** back automatically. +*/ +void sqlite3_interrupt(sqlite3*); + +/* +** CAPI3REF: Determine If An SQL Statement Is Complete +** +** These functions return true if the given input string comprises +** one or more complete SQL statements. For the sqlite3_complete() call, +** the parameter must be a nul-terminated UTF-8 string. For +** sqlite3_complete16(), a nul-terminated machine byte order UTF-16 string +** is required. +** +** These routines are useful for command-line input to determine if the +** currently entered text forms one or more complete SQL statements or +** if additional input is needed before sending the statements into +** SQLite for parsing. The algorithm is simple. If the +** last token other than spaces and comments is a semicolon, then return +** true. Actually, the algorithm is a little more complicated than that +** in order to deal with triggers, but the basic idea is the same: the +** statement is not complete unless it ends in a semicolon. +*/ +int sqlite3_complete(const char *sql); +int sqlite3_complete16(const void *sql); + +/* +** CAPI3REF: Register A Callback To Handle SQLITE_BUSY Errors +** +** This routine identifies a callback function that might be invoked +** whenever an attempt is made to open a database table +** that another thread or process has locked. +** If the busy callback is NULL, then [SQLITE_BUSY] +** (or sometimes [SQLITE_IOERR_BLOCKED]) +** is returned immediately upon encountering the lock. +** If the busy callback is not NULL, then the +** callback will be invoked with two arguments. The +** first argument to the handler is a copy of the void* pointer which +** is the third argument to this routine. The second argument to +** the handler is the number of times that the busy handler has +** been invoked for this locking event. If the +** busy callback returns 0, then no additional attempts are made to +** access the database and [SQLITE_BUSY] or [SQLITE_IOERR_BLOCKED] is returned. +** If the callback returns non-zero, then another attempt is made to open the +** database for reading and the cycle repeats. +** +** The presence of a busy handler does not guarantee that +** it will be invoked when there is lock contention. +** If SQLite determines that invoking the busy handler could result in +** a deadlock, it will return [SQLITE_BUSY] instead. +** Consider a scenario where one process is holding a read lock that +** it is trying to promote to a reserved lock and +** a second process is holding a reserved lock that it is trying +** to promote to an exclusive lock. The first process cannot proceed +** because it is blocked by the second and the second process cannot +** proceed because it is blocked by the first. If both processes +** invoke the busy handlers, neither will make any progress. Therefore, +** SQLite returns [SQLITE_BUSY] for the first process, hoping that this +** will induce the first process to release its read lock and allow +** the second process to proceed. +** +** The default busy callback is NULL. +** +** The [SQLITE_BUSY] error is converted to [SQLITE_IOERR_BLOCKED] when +** SQLite is in the middle of a large transaction where all the +** changes will not fit into the in-memory cache. SQLite will +** already hold a RESERVED lock on the database file, but it needs +** to promote this lock to EXCLUSIVE so that it can spill cache +** pages into the database file without harm to concurrent +** readers. If it is unable to promote the lock, then the in-memory +** cache will be left in an inconsistent state and so the error +** code is promoted from the relatively benign [SQLITE_BUSY] to +** the more severe [SQLITE_IOERR_BLOCKED]. This error code promotion +** forces an automatic rollback of the changes. See the +** +** CorruptionFollowingBusyError wiki page for a discussion of why +** this is important. +** +** Sqlite is re-entrant, so the busy handler may start a new query. +** (It is not clear why anyone would every want to do this, but it +** is allowed, in theory.) But the busy handler may not close the +** database. Closing the database from a busy handler will delete +** data structures out from under the executing query and will +** probably result in a segmentation fault or other runtime error. +** +** There can only be a single busy handler defined for each database +** connection. Setting a new busy handler clears any previous one. +** Note that calling [sqlite3_busy_timeout()] will also set or clear +** the busy handler. +*/ +int sqlite3_busy_handler(sqlite3*, int(*)(void*,int), void*); + +/* +** CAPI3REF: Set A Busy Timeout +** +** This routine sets a busy handler that sleeps for a while when a +** table is locked. The handler will sleep multiple times until +** at least "ms" milliseconds of sleeping have been done. After +** "ms" milliseconds of sleeping, the handler returns 0 which +** causes [sqlite3_step()] to return [SQLITE_BUSY] or [SQLITE_IOERR_BLOCKED]. +** +** Calling this routine with an argument less than or equal to zero +** turns off all busy handlers. +** +** There can only be a single busy handler for a particular database +** connection. If another busy handler was defined +** (using [sqlite3_busy_handler()]) prior to calling +** this routine, that other busy handler is cleared. +*/ +int sqlite3_busy_timeout(sqlite3*, int ms); + +/* +** CAPI3REF: Convenience Routines For Running Queries +** +** This next routine is a convenience wrapper around [sqlite3_exec()]. +** Instead of invoking a user-supplied callback for each row of the +** result, this routine remembers each row of the result in memory +** obtained from [sqlite3_malloc()], then returns all of the result after the +** query has finished. +** +** As an example, suppose the query result where this table: +** +** 
      +**        Name        | Age
+**        -----------------------
+**        Alice       | 43
+**        Bob         | 28
+**        Cindy       | 21
+**
      +** +** If the 3rd argument were &azResult then after the function returns +** azResult will contain the following data: +** +** 
      +**        azResult[0] = "Name";
+**        azResult[1] = "Age";
+**        azResult[2] = "Alice";
+**        azResult[3] = "43";
+**        azResult[4] = "Bob";
+**        azResult[5] = "28";
+**        azResult[6] = "Cindy";
+**        azResult[7] = "21";
+**
      +** +** Notice that there is an extra row of data containing the column +** headers. But the *nrow return value is still 3. *ncolumn is +** set to 2. In general, the number of values inserted into azResult +** will be ((*nrow) + 1)*(*ncolumn). +** +** After the calling function has finished using the result, it should +** pass the result data pointer to sqlite3_free_table() in order to +** release the memory that was malloc-ed. Because of the way the +** [sqlite3_malloc()] happens, the calling function must not try to call +** [sqlite3_free()] directly. Only [sqlite3_free_table()] is able to release +** the memory properly and safely. +** +** The return value of this routine is the same as from [sqlite3_exec()]. +*/ +int sqlite3_get_table( + sqlite3*, /* An open database */ + const char *sql, /* SQL to be executed */ + char ***resultp, /* Result written to a char *[] that this points to */ + int *nrow, /* Number of result rows written here */ + int *ncolumn, /* Number of result columns written here */ + char **errmsg /* Error msg written here */ +); +void sqlite3_free_table(char **result); + +/* +** CAPI3REF: Formatted String Printing Functions +** +** These routines are workalikes of the "printf()" family of functions +** from the standard C library. +** +** The sqlite3_mprintf() and sqlite3_vmprintf() routines write their +** results into memory obtained from [sqlite_malloc()]. +** The strings returned by these two routines should be +** released by [sqlite3_free()]. Both routines return a +** NULL pointer if [sqlite3_malloc()] is unable to allocate enough +** memory to hold the resulting string. +** +** In sqlite3_snprintf() routine is similar to "snprintf()" from +** the standard C library. The result is written into the +** buffer supplied as the second parameter whose size is given by +** the first parameter. Note that the order of the +** first two parameters is reversed from snprintf(). This is an +** historical accident that cannot be fixed without breaking +** backwards compatibility. Note also that sqlite3_snprintf() +** returns a pointer to its buffer instead of the number of +** characters actually written into the buffer. We admit that +** the number of characters written would be a more useful return +** value but we cannot change the implementation of sqlite3_snprintf() +** now without breaking compatibility. +** +** As long as the buffer size is greater than zero, sqlite3_snprintf() +** guarantees that the buffer is always zero-terminated. The first +** parameter "n" is the total size of the buffer, including space for +** the zero terminator. So the longest string that can be completely +** written will be n-1 characters. +** +** These routines all implement some additional formatting +** options that are useful for constructing SQL statements. +** All of the usual printf formatting options apply. In addition, there +** is are "%q" and "%Q" options. +** +** The %q option works like %s in that it substitutes a null-terminated +** string from the argument list. But %q also doubles every '\'' character. +** %q is designed for use inside a string literal. By doubling each '\'' +** character it escapes that character and allows it to be inserted into +** the string. +** +** For example, so some string variable contains text as follows: +** +** 
      +**  char *zText = "It's a happy day!";
+**
      +** +** One can use this text in an SQL statement as follows: +** +** 
      +**  char *zSQL = sqlite3_mprintf("INSERT INTO table VALUES('%q')", zText);
+**  sqlite3_exec(db, zSQL, 0, 0, 0);
+**  sqlite3_free(zSQL);
+**
      +** +** Because the %q format string is used, the '\'' character in zText +** is escaped and the SQL generated is as follows: +** +** 
      +**  INSERT INTO table1 VALUES('It''s a happy day!')
+**
      +** +** This is correct. Had we used %s instead of %q, the generated SQL +** would have looked like this: +** +** 
      +**  INSERT INTO table1 VALUES('It's a happy day!');
+**
      +** +** This second example is an SQL syntax error. As a general rule you +** should always use %q instead of %s when inserting text into a string +** literal. +** +** The %Q option works like %q except it also adds single quotes around +** the outside of the total string. Or if the parameter in the argument +** list is a NULL pointer, %Q substitutes the text "NULL" (without single +** quotes) in place of the %Q option. So, for example, one could say: +** +** 
      +**  char *zSQL = sqlite3_mprintf("INSERT INTO table VALUES(%Q)", zText);
+**  sqlite3_exec(db, zSQL, 0, 0, 0);
+**  sqlite3_free(zSQL);
+**
      +** +** The code above will render a correct SQL statement in the zSQL +** variable even if the zText variable is a NULL pointer. +*/ +char *sqlite3_mprintf(const char*,...); +char *sqlite3_vmprintf(const char*, va_list); +char *sqlite3_snprintf(int,char*,const char*, ...); + +/* +** CAPI3REF: Memory Allocation Functions +** +** SQLite uses its own memory allocator. On some installations, this +** memory allocator is identical to the standard malloc()/realloc()/free() +** and can be used interchangable. On others, the implementations are +** different. For maximum portability, it is best not to mix calls +** to the standard malloc/realloc/free with the sqlite versions. +*/ +void *sqlite3_malloc(int); +void *sqlite3_realloc(void*, int); +void sqlite3_free(void*); + +/* +** CAPI3REF: Compile-Time Authorization Callbacks +*** +** This routine registers a authorizer callback with the SQLite library. +** The authorizer callback is invoked as SQL statements are being compiled +** by [sqlite3_prepare()] or its variants [sqlite3_prepare_v2()], +** [sqlite3_prepare16()] and [sqlite3_prepare16_v2()]. At various +** points during the compilation process, as logic is being created +** to perform various actions, the authorizer callback is invoked to +** see if those actions are allowed. The authorizer callback should +** return SQLITE_OK to allow the action, [SQLITE_IGNORE] to disallow the +** specific action but allow the SQL statement to continue to be +** compiled, or [SQLITE_DENY] to cause the entire SQL statement to be +** rejected with an error. +** +** Depending on the action, the [SQLITE_IGNORE] and [SQLITE_DENY] return +** codes might mean something different or they might mean the same +** thing. If the action is, for example, to perform a delete opertion, +** then [SQLITE_IGNORE] and [SQLITE_DENY] both cause the statement compilation +** to fail with an error. But if the action is to read a specific column +** from a specific table, then [SQLITE_DENY] will cause the entire +** statement to fail but [SQLITE_IGNORE] will cause a NULL value to be +** read instead of the actual column value. +** +** The first parameter to the authorizer callback is a copy of +** the third parameter to the sqlite3_set_authorizer() interface. +** The second parameter to the callback is an integer +** [SQLITE_COPY | action code] that specifies the particular action +** to be authorized. The available action codes are +** [SQLITE_COPY | documented separately]. The third through sixth +** parameters to the callback are strings that contain additional +** details about the action to be authorized. +** +** An authorizer is used when preparing SQL statements from an untrusted +** source, to ensure that the SQL statements do not try to access data +** that they are not allowed to see, or that they do not try to +** execute malicious statements that damage the database. For +** example, an application may allow a user to enter arbitrary +** SQL queries for evaluation by a database. But the application does +** not want the user to be able to make arbitrary changes to the +** database. An authorizer could then be put in place while the +** user-entered SQL is being prepared that disallows everything +** except SELECT statements. +** +** Only a single authorizer can be in place on a database connection +** at a time. Each call to sqlite3_set_authorizer overrides the +** previous call. A NULL authorizer means that no authorization +** callback is invoked. The default authorizer is NULL. +** +** Note that the authorizer callback is invoked only during +** [sqlite3_prepare()] or its variants. Authorization is not +** performed during statement evaluation in [sqlite3_step()]. +*/ +int sqlite3_set_authorizer( + sqlite3*, + int (*xAuth)(void*,int,const char*,const char*,const char*,const char*), + void *pUserData +); + +/* +** CAPI3REF: Authorizer Return Codes +** +** The [sqlite3_set_authorizer | authorizer callback function] must +** return either [SQLITE_OK] or one of these two constants in order +** to signal SQLite whether or not the action is permitted. See the +** [sqlite3_set_authorizer | authorizer documentation] for additional +** information. +*/ +#define SQLITE_DENY 1 /* Abort the SQL statement with an error */ +#define SQLITE_IGNORE 2 /* Don't allow access, but don't generate an error */ + +/* +** CAPI3REF: Authorizer Action Codes +** +** The [sqlite3_set_authorizer()] interface registers a callback function +** that is invoked to authorizer certain SQL statement actions. The +** second parameter to the callback is an integer code that specifies +** what action is being authorized. These are the integer action codes that +** the authorizer callback may be passed. +** +** These action code values signify what kind of operation is to be +** authorized. The 3rd and 4th parameters to the authorization callback +** function will be parameters or NULL depending on which of these +** codes is used as the second parameter. The 5th parameter to the +** authorizer callback is the name of the database ("main", "temp", +** etc.) if applicable. The 6th parameter to the authorizer callback +** is the name of the inner-most trigger or view that is responsible for +** the access attempt or NULL if this access attempt is directly from +** top-level SQL code. +*/ +/******************************************* 3rd ************ 4th ***********/ +#define SQLITE_CREATE_INDEX 1 /* Index Name Table Name */ +#define SQLITE_CREATE_TABLE 2 /* Table Name NULL */ +#define SQLITE_CREATE_TEMP_INDEX 3 /* Index Name Table Name */ +#define SQLITE_CREATE_TEMP_TABLE 4 /* Table Name NULL */ +#define SQLITE_CREATE_TEMP_TRIGGER 5 /* Trigger Name Table Name */ +#define SQLITE_CREATE_TEMP_VIEW 6 /* View Name NULL */ +#define SQLITE_CREATE_TRIGGER 7 /* Trigger Name Table Name */ +#define SQLITE_CREATE_VIEW 8 /* View Name NULL */ +#define SQLITE_DELETE 9 /* Table Name NULL */ +#define SQLITE_DROP_INDEX 10 /* Index Name Table Name */ +#define SQLITE_DROP_TABLE 11 /* Table Name NULL */ +#define SQLITE_DROP_TEMP_INDEX 12 /* Index Name Table Name */ +#define SQLITE_DROP_TEMP_TABLE 13 /* Table Name NULL */ +#define SQLITE_DROP_TEMP_TRIGGER 14 /* Trigger Name Table Name */ +#define SQLITE_DROP_TEMP_VIEW 15 /* View Name NULL */ +#define SQLITE_DROP_TRIGGER 16 /* Trigger Name Table Name */ +#define SQLITE_DROP_VIEW 17 /* View Name NULL */ +#define SQLITE_INSERT 18 /* Table Name NULL */ +#define SQLITE_PRAGMA 19 /* Pragma Name 1st arg or NULL */ +#define SQLITE_READ 20 /* Table Name Column Name */ +#define SQLITE_SELECT 21 /* NULL NULL */ +#define SQLITE_TRANSACTION 22 /* NULL NULL */ +#define SQLITE_UPDATE 23 /* Table Name Column Name */ +#define SQLITE_ATTACH 24 /* Filename NULL */ +#define SQLITE_DETACH 25 /* Database Name NULL */ +#define SQLITE_ALTER_TABLE 26 /* Database Name Table Name */ +#define SQLITE_REINDEX 27 /* Index Name NULL */ +#define SQLITE_ANALYZE 28 /* Table Name NULL */ +#define SQLITE_CREATE_VTABLE 29 /* Table Name Module Name */ +#define SQLITE_DROP_VTABLE 30 /* Table Name Module Name */ +#define SQLITE_FUNCTION 31 /* Function Name NULL */ +#define SQLITE_COPY 0 /* No longer used */ + +/* +** CAPI3REF: Tracing And Profiling Functions +** +** These routines register callback functions that can be used for +** tracing and profiling the execution of SQL statements. +** The callback function registered by sqlite3_trace() is invoked +** at the first [sqlite3_step()] for the evaluation of an SQL statement. +** The callback function registered by sqlite3_profile() is invoked +** as each SQL statement finishes and includes +** information on how long that statement ran. +** +** The sqlite3_profile() API is currently considered experimental and +** is subject to change. +*/ +void *sqlite3_trace(sqlite3*, void(*xTrace)(void*,const char*), void*); +void *sqlite3_profile(sqlite3*, + void(*xProfile)(void*,const char*,sqlite_uint64), void*); + +/* +** CAPI3REF: Query Progress Callbacks +** +** This routine configures a callback function - the progress callback - that +** is invoked periodically during long running calls to [sqlite3_exec()], +** [sqlite3_step()] and [sqlite3_get_table()]. An example use for this +** interface is to keep a GUI updated during a large query. +** +** The progress callback is invoked once for every N virtual machine opcodes, +** where N is the second argument to this function. The progress callback +** itself is identified by the third argument to this function. The fourth +** argument to this function is a void pointer passed to the progress callback +** function each time it is invoked. +** +** If a call to [sqlite3_exec()], [sqlite3_step()], or [sqlite3_get_table()] +** results in fewer than N opcodes being executed, then the progress +** callback is never invoked. +** +** Only a single progress callback function may be registered for each +** open database connection. Every call to sqlite3_progress_handler() +** overwrites the results of the previous call. +** To remove the progress callback altogether, pass NULL as the third +** argument to this function. +** +** If the progress callback returns a result other than 0, then the current +** query is immediately terminated and any database changes rolled back. +** The containing [sqlite3_exec()], [sqlite3_step()], or +** [sqlite3_get_table()] call returns SQLITE_INTERRUPT. This feature +** can be used, for example, to implement the "Cancel" button on a +** progress dialog box in a GUI. +*/ +void sqlite3_progress_handler(sqlite3*, int, int(*)(void*), void*); + +/* +** CAPI3REF: Opening A New Database Connection +** +** Open the sqlite database file "filename". The "filename" is UTF-8 +** encoded for sqlite3_open() and UTF-16 encoded in the native byte order +** for sqlite3_open16(). An [sqlite3*] handle is returned in *ppDb, even +** if an error occurs. If the database is opened (or created) successfully, +** then SQLITE_OK is returned. Otherwise an error code is returned. The +** sqlite3_errmsg() or sqlite3_errmsg16() routines can be used to obtain +** an English language description of the error. +** +** If the database file does not exist, then a new database will be created +** as needed. The default encoding for the database will be UTF-8 if +** sqlite3_open() is called and UTF-16 if sqlite3_open16 is used. +** +** Whether or not an error occurs when it is opened, resources associated +** with the [sqlite3*] handle should be released by passing it to +** sqlite3_close() when it is no longer required. +** +** Note to windows users: The encoding used for the filename argument +** of sqlite3_open() must be UTF-8, not whatever codepage is currently +** defined. Filenames containing international characters must be converted +** to UTF-8 prior to passing them into sqlite3_open(). +*/ +int sqlite3_open( + const char *filename, /* Database filename (UTF-8) */ + sqlite3 **ppDb /* OUT: SQLite db handle */ +); +int sqlite3_open16( + const void *filename, /* Database filename (UTF-16) */ + sqlite3 **ppDb /* OUT: SQLite db handle */ +); + +/* +** CAPI3REF: Error Codes And Messages +** +** The sqlite3_errcode() interface returns the numeric +** [SQLITE_OK | result code] or [SQLITE_IOERR_READ | extended result code] +** for the most recent failed sqlite3_* API call associated +** with [sqlite3] handle 'db'. If a prior API call failed but the +** most recent API call succeeded, the return value from sqlite3_errcode() +** is undefined. +** +** The sqlite3_errmsg() and sqlite3_errmsg16() return English-langauge +** text that describes the error, as either UTF8 or UTF16 respectively. +** Memory to hold the error message string is managed internally. The +** string may be overwritten or deallocated by subsequent calls to SQLite +** interface functions. +** +** Calls to many sqlite3_* functions set the error code and string returned +** by [sqlite3_errcode()], [sqlite3_errmsg()], and [sqlite3_errmsg16()] +** (overwriting the previous values). Note that calls to [sqlite3_errcode()], +** [sqlite3_errmsg()], and [sqlite3_errmsg16()] themselves do not affect the +** results of future invocations. Calls to API routines that do not return +** an error code (examples: [sqlite3_data_count()] or [sqlite3_mprintf()]) do +** not change the error code returned by this routine. +** +** Assuming no other intervening sqlite3_* API calls are made, the error +** code returned by this function is associated with the same error as +** the strings returned by [sqlite3_errmsg()] and [sqlite3_errmsg16()]. +*/ +int sqlite3_errcode(sqlite3 *db); +const char *sqlite3_errmsg(sqlite3*); +const void *sqlite3_errmsg16(sqlite3*); + +/* +** CAPI3REF: SQL Statement Object +** +** Instance of this object represent single SQL statements. This +** is variously known as a "prepared statement" or a +** "compiled SQL statement" or simply as a "statement". +** +** The life of a statement object goes something like this: +** +**
        +**
      1. Create the object using [sqlite3_prepare_v2()] or a related +** function. +**
      2. Bind values to host parameters using +** [sqlite3_bind_blob | sqlite3_bind_* interfaces]. +**
      3. Run the SQL by calling [sqlite3_step()] one or more times. +**
      4. Reset the statement using [sqlite3_reset()] then go back +** to step 2. Do this zero or more times. +**
      5. Destroy the object using [sqlite3_finalize()]. +**
      +** +** Refer to documentation on individual methods above for additional +** information. +*/ +typedef struct sqlite3_stmt sqlite3_stmt; + +/* +** CAPI3REF: Compiling An SQL Statement +** +** To execute an SQL query, it must first be compiled into a byte-code +** program using one of these routines. +** +** The first argument "db" is an [sqlite3 | SQLite database handle] +** obtained from a prior call to [sqlite3_open()] or [sqlite3_open16()]. +** The second argument "zSql" is the statement to be compiled, encoded +** as either UTF-8 or UTF-16. The sqlite3_prepare() and sqlite3_prepare_v2() +** interfaces uses UTF-8 and sqlite3_prepare16() and sqlite3_prepare16_v2() +** use UTF-16. If the next argument, "nBytes", is less +** than zero, then zSql is read up to the first zero terminator. If +** "nBytes" is not less than zero, then it is the length of the string zSql +** in bytes (not characters). +** +** *pzTail is made to point to the first byte past the end of the first +** SQL statement in zSql. This routine only compiles the first statement +** in zSql, so *pzTail is left pointing to what remains uncompiled. +** +** *ppStmt is left pointing to a compiled +** [sqlite3_stmt | SQL statement structure] that can be +** executed using [sqlite3_step()]. Or if there is an error, *ppStmt may be +** set to NULL. If the input text contained no SQL (if the input is and +** empty string or a comment) then *ppStmt is set to NULL. The calling +** procedure is responsible for deleting the compiled SQL statement +** using [sqlite3_finalize()] after it has finished with it. +** +** On success, [SQLITE_OK] is returned. Otherwise an +** [SQLITE_ERROR | error code] is returned. +** +** The sqlite3_prepare_v2() and sqlite3_prepare16_v2() interfaces are +** recommended for all new programs. The two older interfaces are retained +** for backwards compatibility, but their use is discouraged. +** In the "v2" interfaces, the prepared statement +** that is returned (the [sqlite3_stmt] object) contains a copy of the +** original SQL text. This causes the [sqlite3_step()] interface to +** behave a differently in two ways: +** +**
        +**
      1. +** If the database schema changes, instead of returning [SQLITE_SCHEMA] as it +** always used to do, [sqlite3_step()] will automatically recompile the SQL +** statement and try to run it again. If the schema has changed in a way +** that makes the statement no longer valid, [sqlite3_step()] will still +** return [SQLITE_SCHEMA]. But unlike the legacy behavior, [SQLITE_SCHEMA] is +** now a fatal error. Calling [sqlite3_prepare_v2()] again will not make the +** error go away. Note: use [sqlite3_errmsg()] to find the text of the parsing +** error that results in an [SQLITE_SCHEMA] return. +**
        2. +** +**
      2. +** When an error occurs, +** [sqlite3_step()] will return one of the detailed +** [SQLITE_ERROR | result codes] or +** [SQLITE_IOERR_READ | extended result codes] such as directly. +** The legacy behavior was that [sqlite3_step()] would only return a generic +** [SQLITE_ERROR] result code and you would have to make a second call to +** [sqlite3_reset()] in order to find the underlying cause of the problem. +** With the "v2" prepare interfaces, the underlying reason for the error is +** returned immediately. +**
        3. +**
      +*/ +int sqlite3_prepare( + sqlite3 *db, /* Database handle */ + const char *zSql, /* SQL statement, UTF-8 encoded */ + int nBytes, /* Length of zSql in bytes. */ + sqlite3_stmt **ppStmt, /* OUT: Statement handle */ + const char **pzTail /* OUT: Pointer to unused portion of zSql */ +); +int sqlite3_prepare_v2( + sqlite3 *db, /* Database handle */ + const char *zSql, /* SQL statement, UTF-8 encoded */ + int nBytes, /* Length of zSql in bytes. */ + sqlite3_stmt **ppStmt, /* OUT: Statement handle */ + const char **pzTail /* OUT: Pointer to unused portion of zSql */ +); +int sqlite3_prepare16( + sqlite3 *db, /* Database handle */ + const void *zSql, /* SQL statement, UTF-16 encoded */ + int nBytes, /* Length of zSql in bytes. */ + sqlite3_stmt **ppStmt, /* OUT: Statement handle */ + const void **pzTail /* OUT: Pointer to unused portion of zSql */ +); +int sqlite3_prepare16_v2( + sqlite3 *db, /* Database handle */ + const void *zSql, /* SQL statement, UTF-16 encoded */ + int nBytes, /* Length of zSql in bytes. */ + sqlite3_stmt **ppStmt, /* OUT: Statement handle */ + const void **pzTail /* OUT: Pointer to unused portion of zSql */ +); + +/* +** CAPI3REF: Dynamically Typed Value Object +** +** SQLite uses dynamic typing for the values it stores. Values can +** be integers, floating point values, strings, BLOBs, or NULL. When +** passing around values internally, each value is represented as +** an instance of the sqlite3_value object. +*/ +typedef struct Mem sqlite3_value; + +/* +** CAPI3REF: SQL Function Context Object +** +** The context in which an SQL function executes is stored in an +** sqlite3_context object. A pointer to such an object is the +** first parameter to user-defined SQL functions. +*/ +typedef struct sqlite3_context sqlite3_context; + +/* +** CAPI3REF: Binding Values To Prepared Statements +** +** In the SQL strings input to [sqlite3_prepare_v2()] and its variants, +** one or more literals can be replace by a parameter in one of these +** forms: +** +**
        +**
      • ? +**
      • ?NNN +**
      • :AAA +**
      • @AAA +**
      • $VVV +**
      +** +** In the parameter forms shown above NNN is an integer literal, +** AAA is an alphanumeric identifier and VVV is a variable name according +** to the syntax rules of the TCL programming language. +** The values of these parameters (also called "host parameter names") +** can be set using the sqlite3_bind_*() routines defined here. +** +** The first argument to the sqlite3_bind_*() routines always is a pointer +** to the [sqlite3_stmt] object returned from [sqlite3_prepare_v2()] or +** its variants. The second +** argument is the index of the parameter to be set. The first parameter has +** an index of 1. When the same named parameter is used more than once, second +** and subsequent +** occurrences have the same index as the first occurrence. The index for +** named parameters can be looked up using the +** [sqlite3_bind_parameter_name()] API if desired. The index for "?NNN" +** parametes is the value of NNN. +** The NNN value must be between 1 and the compile-time +** parameter SQLITE_MAX_VARIABLE_NUMBER (default value: 999). +** See limits.html for additional information. +** +** The third argument is the value to bind to the parameter. +** +** In those +** routines that have a fourth argument, its value is the number of bytes +** in the parameter. To be clear: the value is the number of bytes in the +** string, not the number of characters. The number +** of bytes does not include the zero-terminator at the end of strings. +** If the fourth parameter is negative, the length of the string is +** number of bytes up to the first zero terminator. +** +** The fifth argument to sqlite3_bind_blob(), sqlite3_bind_text(), and +** sqlite3_bind_text16() is a destructor used to dispose of the BLOB or +** text after SQLite has finished with it. If the fifth argument is the +** special value [SQLITE_STATIC], then the library assumes that the information +** is in static, unmanaged space and does not need to be freed. If the +** fifth argument has the value [SQLITE_TRANSIENT], then SQLite makes its +** own private copy of the data immediately, before the sqlite3_bind_*() +** routine returns. +** +** The sqlite3_bind_zeroblob() routine binds a BLOB of length n that +** is filled with zeros. A zeroblob uses a fixed amount of memory +** (just an integer to hold it size) while it is being processed. +** Zeroblobs are intended to serve as place-holders for BLOBs whose +** content is later written using +** [sqlite3_blob_open | increment BLOB I/O] routines. +** +** The sqlite3_bind_*() routines must be called after +** [sqlite3_prepare_v2()] (and its variants) or [sqlite3_reset()] and +** before [sqlite3_step()]. +** Bindings are not cleared by the [sqlite3_reset()] routine. +** Unbound parameters are interpreted as NULL. +** +** These routines return [SQLITE_OK] on success or an error code if +** anything goes wrong. [SQLITE_RANGE] is returned if the parameter +** index is out of range. [SQLITE_NOMEM] is returned if malloc fails. +** [SQLITE_MISUSE] is returned if these routines are called on a virtual +** machine that is the wrong state or which has already been finalized. +*/ +int sqlite3_bind_blob(sqlite3_stmt*, int, const void*, int n, void(*)(void*)); +int sqlite3_bind_double(sqlite3_stmt*, int, double); +int sqlite3_bind_int(sqlite3_stmt*, int, int); +int sqlite3_bind_int64(sqlite3_stmt*, int, sqlite_int64); +int sqlite3_bind_null(sqlite3_stmt*, int); +int sqlite3_bind_text(sqlite3_stmt*, int, const char*, int n, void(*)(void*)); +int sqlite3_bind_text16(sqlite3_stmt*, int, const void*, int, void(*)(void*)); +int sqlite3_bind_value(sqlite3_stmt*, int, const sqlite3_value*); +int sqlite3_bind_zeroblob(sqlite3_stmt*, int, int n); + +/* +** CAPI3REF: Number Of Host Parameters +** +** Return the largest host parameter index in the precompiled statement given +** as the argument. When the host parameters are of the forms like ":AAA" +** or "?", then they are assigned sequential increasing numbers beginning +** with one, so the value returned is the number of parameters. However +** if the same host parameter name is used multiple times, each occurrance +** is given the same number, so the value returned in that case is the number +** of unique host parameter names. If host parameters of the form "?NNN" +** are used (where NNN is an integer) then there might be gaps in the +** numbering and the value returned by this interface is the index of the +** host parameter with the largest index value. +*/ +int sqlite3_bind_parameter_count(sqlite3_stmt*); + +/* +** CAPI3REF: Name Of A Host Parameter +** +** This routine returns a pointer to the name of the n-th parameter in a +** [sqlite3_stmt | prepared statement]. +** Host parameters of the form ":AAA" or "@AAA" or "$VVV" have a name +** which is the string ":AAA" or "@AAA" or "$VVV". +** In other words, the initial ":" or "$" or "@" +** is included as part of the name. +** Parameters of the form "?" or "?NNN" have no name. +** +** The first bound parameter has an index of 1, not 0. +** +** If the value n is out of range or if the n-th parameter is nameless, +** then NULL is returned. The returned string is always in the +** UTF-8 encoding even if the named parameter was originally specified +** as UTF-16 in [sqlite3_prepare16()] or [sqlite3_prepare16_v2()]. +*/ +const char *sqlite3_bind_parameter_name(sqlite3_stmt*, int); + +/* +** CAPI3REF: Index Of A Parameter With A Given Name +** +** This routine returns the index of a host parameter with the given name. +** The name must match exactly. If no parameter with the given name is +** found, return 0. Parameter names must be UTF8. +*/ +int sqlite3_bind_parameter_index(sqlite3_stmt*, const char *zName); + +/* +** CAPI3REF: Reset All Bindings On A Prepared Statement +** +** Contrary to the intuition of many, [sqlite3_reset()] does not +** reset the [sqlite3_bind_blob | bindings] on a +** [sqlite3_stmt | prepared statement]. Use this routine to +** reset all host parameters to NULL. +*/ +int sqlite3_clear_bindings(sqlite3_stmt*); + +/* +** CAPI3REF: Number Of Columns In A Result Set +** +** Return the number of columns in the result set returned by the +** [sqlite3_stmt | compiled SQL statement]. This routine returns 0 +** if pStmt is an SQL statement that does not return data (for +** example an UPDATE). +*/ +int sqlite3_column_count(sqlite3_stmt *pStmt); + +/* +** CAPI3REF: Column Names In A Result Set +** +** These routines return the name assigned to a particular column +** in the result set of a SELECT statement. The sqlite3_column_name() +** interface returns a pointer to a UTF8 string and sqlite3_column_name16() +** returns a pointer to a UTF16 string. The first parameter is the +** [sqlite_stmt | prepared statement] that implements the SELECT statement. +** The second parameter is the column number. The left-most column is +** number 0. +** +** The returned string pointer is valid until either the +** [sqlite_stmt | prepared statement] is destroyed by [sqlite3_finalize()] +** or until the next call sqlite3_column_name() or sqlite3_column_name16() +** on the same column. +*/ +const char *sqlite3_column_name(sqlite3_stmt*, int N); +const void *sqlite3_column_name16(sqlite3_stmt*, int N); + +/* +** CAPI3REF: Source Of Data In A Query Result +** +** These routines provide a means to determine what column of what +** table in which database a result of a SELECT statement comes from. +** The name of the database or table or column can be returned as +** either a UTF8 or UTF16 string. The returned string is valid until +** the [sqlite3_stmt | prepared statement] is destroyed using +** [sqlite3_finalize()] or until the same information is requested +** again about the same column. +** +** The first argument to the following calls is a +** [sqlite3_stmt | compiled SQL statement]. +** These functions return information about the Nth column returned by +** the statement, where N is the second function argument. +** +** If the Nth column returned by the statement is an expression +** or subquery and is not a column value, then all of these functions +** return NULL. Otherwise, they return the +** name of the attached database, table and column that query result +** column was extracted from. +** +** As with all other SQLite APIs, those postfixed with "16" return UTF-16 +** encoded strings, the other functions return UTF-8. +** +** These APIs are only available if the library was compiled with the +** SQLITE_ENABLE_COLUMN_METADATA preprocessor symbol defined. +*/ +const char *sqlite3_column_database_name(sqlite3_stmt*,int); +const void *sqlite3_column_database_name16(sqlite3_stmt*,int); +const char *sqlite3_column_table_name(sqlite3_stmt*,int); +const void *sqlite3_column_table_name16(sqlite3_stmt*,int); +const char *sqlite3_column_origin_name(sqlite3_stmt*,int); +const void *sqlite3_column_origin_name16(sqlite3_stmt*,int); + +/* +** CAPI3REF: Declared Datatype Of A Query Result +** +** The first parameter is a [sqlite3_stmt | compiled SQL statement]. +** If this statement is a SELECT statement and the Nth column of the +** returned result set of that SELECT is a table column (not an +** expression or subquery) then the declared type of the table +** column is returned. If the Nth column of the result set is an +** expression or subquery, then a NULL pointer is returned. +** The returned string is always UTF-8 encoded. For example, in +** the database schema: +** +** CREATE TABLE t1(c1 VARIANT); +** +** And the following statement compiled: +** +** SELECT c1 + 1, c1 FROM t1; +** +** Then this routine would return the string "VARIANT" for the second +** result column (i==1), and a NULL pointer for the first result column +** (i==0). +** +** SQLite uses dynamic run-time typing. So just because a column +** is declared to contain a particular type does not mean that the +** data stored in that column is of the declared type. SQLite is +** strongly typed, but the typing is dynamic not static. Type +** is associated with individual values, not with the containers +** used to hold those values. +*/ +const char *sqlite3_column_decltype(sqlite3_stmt *, int i); +const void *sqlite3_column_decltype16(sqlite3_stmt*,int); + +/* +** CAPI3REF: Evaluate An SQL Statement +** +** After an [sqlite3_stmt | SQL statement] has been prepared with a call +** to either [sqlite3_prepare_v2()] or [sqlite3_prepare16_v2()] or to one of +** the legacy interfaces [sqlite3_prepare()] or [sqlite3_prepare16()], +** then this function must be called one or more times to evaluate the +** statement. +** +** The details of the behavior of this sqlite3_step() interface depend +** on whether the statement was prepared using the newer "v2" interface +** [sqlite3_prepare_v2()] and [sqlite3_prepare16_v2()] or the older legacy +** interface [sqlite3_prepare()] and [sqlite3_prepare16()]. The use of the +** new "v2" interface is recommended for new applications but the legacy +** interface will continue to be supported. +** +** In the lagacy interface, the return value will be either [SQLITE_BUSY], +** [SQLITE_DONE], [SQLITE_ROW], [SQLITE_ERROR], or [SQLITE_MISUSE]. +** With the "v2" interface, any of the other [SQLITE_OK | result code] +** or [SQLITE_IOERR_READ | extended result code] might be returned as +** well. +** +** [SQLITE_BUSY] means that the database engine was unable to acquire the +** database locks it needs to do its job. If the statement is a COMMIT +** or occurs outside of an explicit transaction, then you can retry the +** statement. If the statement is not a COMMIT and occurs within a +** explicit transaction then you should rollback the transaction before +** continuing. +** +** [SQLITE_DONE] means that the statement has finished executing +** successfully. sqlite3_step() should not be called again on this virtual +** machine without first calling [sqlite3_reset()] to reset the virtual +** machine back to its initial state. +** +** If the SQL statement being executed returns any data, then +** [SQLITE_ROW] is returned each time a new row of data is ready +** for processing by the caller. The values may be accessed using +** the [sqlite3_column_int | column access functions]. +** sqlite3_step() is called again to retrieve the next row of data. +** +** [SQLITE_ERROR] means that a run-time error (such as a constraint +** violation) has occurred. sqlite3_step() should not be called again on +** the VM. More information may be found by calling [sqlite3_errmsg()]. +** With the legacy interface, a more specific error code (example: +** [SQLITE_INTERRUPT], [SQLITE_SCHEMA], [SQLITE_CORRUPT], and so forth) +** can be obtained by calling [sqlite3_reset()] on the +** [sqlite_stmt | prepared statement]. In the "v2" interface, +** the more specific error code is returned directly by sqlite3_step(). +** +** [SQLITE_MISUSE] means that the this routine was called inappropriately. +** Perhaps it was called on a [sqlite_stmt | prepared statement] that has +** already been [sqlite3_finalize | finalized] or on one that had +** previously returned [SQLITE_ERROR] or [SQLITE_DONE]. Or it could +** be the case that the same database connection is being used by two or +** more threads at the same moment in time. +** +** Goofy Interface Alert: +** In the legacy interface, +** the sqlite3_step() API always returns a generic error code, +** [SQLITE_ERROR], following any error other than [SQLITE_BUSY] +** and [SQLITE_MISUSE]. You must call [sqlite3_reset()] or +** [sqlite3_finalize()] in order to find one of the specific +** [SQLITE_ERROR | result codes] that better describes the error. +** We admit that this is a goofy design. The problem has been fixed +** with the "v2" interface. If you prepare all of your SQL statements +** using either [sqlite3_prepare_v2()] or [sqlite3_prepare16_v2()] instead +** of the legacy [sqlite3_prepare()] and [sqlite3_prepare16()], then the +** more specific [SQLITE_ERROR | result codes] are returned directly +** by sqlite3_step(). The use of the "v2" interface is recommended. +*/ +int sqlite3_step(sqlite3_stmt*); + +/* +** CAPI3REF: +** +** Return the number of values in the current row of the result set. +** +** After a call to [sqlite3_step()] that returns [SQLITE_ROW], this routine +** will return the same value as the [sqlite3_column_count()] function. +** After [sqlite3_step()] has returned an [SQLITE_DONE], [SQLITE_BUSY], or +** a [SQLITE_ERROR | error code], or before [sqlite3_step()] has been +** called on the [sqlite_stmt | prepared statement] for the first time, +** this routine returns zero. +*/ +int sqlite3_data_count(sqlite3_stmt *pStmt); + +/* +** CAPI3REF: Fundamental Datatypes +** +** Every value in SQLite has one of five fundamental datatypes: +** +**
        +**
      • 64-bit signed integer +**
      • 64-bit IEEE floating point number +**
      • string +**
      • BLOB +**
      • NULL +**
      +** +** These constants are codes for each of those types. +** +** Note that the SQLITE_TEXT constant was also used in SQLite version 2 +** for a completely different meaning. Software that links against both +** SQLite version 2 and SQLite version 3 should use SQLITE3_TEXT not +** SQLITE_TEXT. +*/ +#define SQLITE_INTEGER 1 +#define SQLITE_FLOAT 2 +#define SQLITE_BLOB 4 +#define SQLITE_NULL 5 +#ifdef SQLITE_TEXT +# undef SQLITE_TEXT +#else +# define SQLITE_TEXT 3 +#endif +#define SQLITE3_TEXT 3 + +/* +** CAPI3REF: Results Values From A Query +** +** These routines return information about the information +** in a single column of the current result row of a query. In every +** case the first argument is a pointer to the +** [sqlite3_stmt | SQL statement] that is being +** evaluate (the [sqlite_stmt*] that was returned from +** [sqlite3_prepare_v2()] or one of its variants) and +** the second argument is the index of the column for which information +** should be returned. The left-most column has an index of 0. +** +** If the SQL statement is not currently point to a valid row, or if the +** the column index is out of range, the result is undefined. +** +** The sqlite3_column_type() routine returns +** [SQLITE_INTEGER | datatype code] for the initial data type +** of the result column. The returned value is one of [SQLITE_INTEGER], +** [SQLITE_FLOAT], [SQLITE_TEXT], [SQLITE_BLOB], or [SQLITE_NULL]. The value +** returned by sqlite3_column_type() is only meaningful if no type +** conversions have occurred as described below. After a type conversion, +** the value returned by sqlite3_column_type() is undefined. Future +** versions of SQLite may change the behavior of sqlite3_column_type() +** following a type conversion. +** +*** The sqlite3_column_nm +** +** If the result is a BLOB or UTF-8 string then the sqlite3_column_bytes() +** routine returns the number of bytes in that BLOB or string. +** If the result is a UTF-16 string, then sqlite3_column_bytes() converts +** the string to UTF-8 and then returns the number of bytes. +** If the result is a numeric value then sqlite3_column_bytes() uses +** [sqlite3_snprintf()] to convert that value to a UTF-8 string and returns +** the number of bytes in that string. +** The value returned does not include the zero terminator at the end +** of the string. For clarity: the value returned is the number of +** bytes in the string, not the number of characters. +** +** The sqlite3_column_bytes16() routine is similar to sqlite3_column_bytes() +** but leaves the result in UTF-16 instead of UTF-8. +** The zero terminator is not included in this count. +** +** These routines attempt to convert the value where appropriate. For +** example, if the internal representation is FLOAT and a text result +** is requested, [sqlite3_snprintf()] is used internally to do the conversion +** automatically. The following table details the conversions that +** are applied: +** +**
      +** +**
      Internal Requested +**
      Type Type Conversion +** +**
      NULL INTEGER Result is 0 +**
      NULL FLOAT Result is 0.0 +**
      NULL TEXT Result is NULL pointer +**
      NULL BLOB Result is NULL pointer +**
      INTEGER FLOAT Convert from integer to float +**
      INTEGER TEXT ASCII rendering of the integer +**
      INTEGER BLOB Same as for INTEGER->TEXT +**
      FLOAT INTEGER Convert from float to integer +**
      FLOAT TEXT ASCII rendering of the float +**
      FLOAT BLOB Same as FLOAT->TEXT +**
      TEXT INTEGER Use atoi() +**
      TEXT FLOAT Use atof() +**
      TEXT BLOB No change +**
      BLOB INTEGER Convert to TEXT then use atoi() +**
      BLOB FLOAT Convert to TEXT then use atof() +**
      BLOB TEXT Add a zero terminator if needed +**
      +**
      +** +** The table above makes reference to standard C library functions atoi() +** and atof(). SQLite does not really use these functions. It has its +** on equavalent internal routines. The atoi() and atof() names are +** used in the table for brevity and because they are familiar to most +** C programmers. +** +** Note that when type conversions occur, pointers returned by prior +** calls to sqlite3_column_blob(), sqlite3_column_text(), and/or +** sqlite3_column_text16() may be invalidated. +** Type conversions and pointer invalidations might occur +** in the following cases: +** +**
        +**

      • The initial content is a BLOB and sqlite3_column_text() +** or sqlite3_column_text16() is called. A zero-terminator might +** need to be added to the string.

        • +** +**

      • The initial content is UTF-8 text and sqlite3_column_bytes16() or +** sqlite3_column_text16() is called. The content must be converted +** to UTF-16.

        • +** +**

      • The initial content is UTF-16 text and sqlite3_column_bytes() or +** sqlite3_column_text() is called. The content must be converted +** to UTF-8.

        • +**
      +** +** Conversions between UTF-16be and UTF-16le are always done in place and do +** not invalidate a prior pointer, though of course the content of the buffer +** that the prior pointer points to will have been modified. Other kinds +** of conversion are done in place when it is possible, but sometime it is +** not possible and in those cases prior pointers are invalidated. +** +** The safest and easiest to remember policy is to invoke these routines +** in one of the following ways: +** +**
        +**
      • sqlite3_column_text() followed by sqlite3_column_bytes()
        • +**
      • sqlite3_column_blob() followed by sqlite3_column_bytes()
        • +**
      • sqlite3_column_text16() followed by sqlite3_column_bytes16()
        • +**
      +** +** In other words, you should call sqlite3_column_text(), sqlite3_column_blob(), +** or sqlite3_column_text16() first to force the result into the desired +** format, then invoke sqlite3_column_bytes() or sqlite3_column_bytes16() to +** find the size of the result. Do not mix call to sqlite3_column_text() or +** sqlite3_column_blob() with calls to sqlite3_column_bytes16(). And do not +** mix calls to sqlite3_column_text16() with calls to sqlite3_column_bytes(). +*/ +const void *sqlite3_column_blob(sqlite3_stmt*, int iCol); +int sqlite3_column_bytes(sqlite3_stmt*, int iCol); +int sqlite3_column_bytes16(sqlite3_stmt*, int iCol); +double sqlite3_column_double(sqlite3_stmt*, int iCol); +int sqlite3_column_int(sqlite3_stmt*, int iCol); +sqlite_int64 sqlite3_column_int64(sqlite3_stmt*, int iCol); +const unsigned char *sqlite3_column_text(sqlite3_stmt*, int iCol); +const void *sqlite3_column_text16(sqlite3_stmt*, int iCol); +int sqlite3_column_type(sqlite3_stmt*, int iCol); +sqlite3_value *sqlite3_column_value(sqlite3_stmt*, int iCol); + +/* +** CAPI3REF: Destroy A Prepared Statement Object +** +** The sqlite3_finalize() function is called to delete a +** [sqlite3_stmt | compiled SQL statement]. If the statement was +** executed successfully, or not executed at all, then SQLITE_OK is returned. +** If execution of the statement failed then an +** [SQLITE_ERROR | error code] or [SQLITE_IOERR_READ | extended error code] +** is returned. +** +** This routine can be called at any point during the execution of the +** [sqlite3_stmt | virtual machine]. If the virtual machine has not +** completed execution when this routine is called, that is like +** encountering an error or an interrupt. (See [sqlite3_interrupt()].) +** Incomplete updates may be rolled back and transactions cancelled, +** depending on the circumstances, and the +** [SQLITE_ERROR | result code] returned will be [SQLITE_ABORT]. +*/ +int sqlite3_finalize(sqlite3_stmt *pStmt); + +/* +** CAPI3REF: Reset A Prepared Statement Object +** +** The sqlite3_reset() function is called to reset a +** [sqlite_stmt | compiled SQL statement] object. +** back to it's initial state, ready to be re-executed. +** Any SQL statement variables that had values bound to them using +** the [sqlite3_bind_blob | sqlite3_bind_*() API] retain their values. +** Use [sqlite3_clear_bindings()] to reset the bindings. +*/ +int sqlite3_reset(sqlite3_stmt *pStmt); + +/* +** CAPI3REF: Create Or Redefine SQL Functions +** +** The following two functions are used to add SQL functions or aggregates +** or to redefine the behavior of existing SQL functions or aggregates. The +** difference only between the two is that the second parameter, the +** name of the (scalar) function or aggregate, is encoded in UTF-8 for +** sqlite3_create_function() and UTF-16 for sqlite3_create_function16(). +** +** The first argument is the [sqlite3 | database handle] that holds the +** SQL function or aggregate is to be added or redefined. If a single +** program uses more than one database handle internally, then SQL +** functions or aggregates must be added individually to each database +** handle with which they will be used. +** +** The second parameter is the name of the SQL function to be created +** or redefined. +** The length of the name is limited to 255 bytes, exclusive of the +** zero-terminator. Note that the name length limit is in bytes, not +** characters. Any attempt to create a function with a longer name +** will result in an SQLITE_ERROR error. +** +** The third parameter is the number of arguments that the SQL function or +** aggregate takes. If this parameter is negative, then the SQL function or +** aggregate may take any number of arguments. +** +** The fourth parameter, eTextRep, specifies what +** [SQLITE_UTF8 | text encoding] this SQL function prefers for +** its parameters. Any SQL function implementation should be able to work +** work with UTF-8, UTF-16le, or UTF-16be. But some implementations may be +** more efficient with one encoding than another. It is allowed to +** invoke sqlite_create_function() or sqlite3_create_function16() multiple +** times with the same function but with different values of eTextRep. +** When multiple implementations of the same function are available, SQLite +** will pick the one that involves the least amount of data conversion. +** If there is only a single implementation which does not care what +** text encoding is used, then the fourth argument should be +** [SQLITE_ANY]. +** +** The fifth parameter is an arbitrary pointer. The implementation +** of the function can gain access to this pointer using +** [sqlite_user_data()]. +** +** The seventh, eighth and ninth parameters, xFunc, xStep and xFinal, are +** pointers to C-language functions that implement the SQL +** function or aggregate. A scalar SQL function requires an implementation of +** the xFunc callback only, NULL pointers should be passed as the xStep +** and xFinal parameters. An aggregate SQL function requires an implementation +** of xStep and xFinal and NULL should be passed for xFunc. To delete an +** existing SQL function or aggregate, pass NULL for all three function +** callback. +** +** It is permitted to register multiple implementations of the same +** functions with the same name but with either differing numbers of +** arguments or differing perferred text encodings. SQLite will use +** the implementation most closely matches the way in which the +** SQL function is used. +*/ +int sqlite3_create_function( + sqlite3 *, + const char *zFunctionName, + int nArg, + int eTextRep, + void*, + void (*xFunc)(sqlite3_context*,int,sqlite3_value**), + void (*xStep)(sqlite3_context*,int,sqlite3_value**), + void (*xFinal)(sqlite3_context*) +); +int sqlite3_create_function16( + sqlite3*, + const void *zFunctionName, + int nArg, + int eTextRep, + void*, + void (*xFunc)(sqlite3_context*,int,sqlite3_value**), + void (*xStep)(sqlite3_context*,int,sqlite3_value**), + void (*xFinal)(sqlite3_context*) +); + +/* +** CAPI3REF: Text Encodings +** +** These constant define integer codes that represent the various +** text encodings supported by SQLite. +*/ +#define SQLITE_UTF8 1 +#define SQLITE_UTF16LE 2 +#define SQLITE_UTF16BE 3 +#define SQLITE_UTF16 4 /* Use native byte order */ +#define SQLITE_ANY 5 /* sqlite3_create_function only */ +#define SQLITE_UTF16_ALIGNED 8 /* sqlite3_create_collation only */ + +/* +** CAPI3REF: Obsolete Functions +** +** These functions are all now obsolete. In order to maintain +** backwards compatibility with older code, we continue to support +** these functions. However, new development projects should avoid +** the use of these functions. To help encourage people to avoid +** using these functions, we are not going to tell you want they do. +*/ +int sqlite3_aggregate_count(sqlite3_context*); +int sqlite3_expired(sqlite3_stmt*); +int sqlite3_transfer_bindings(sqlite3_stmt*, sqlite3_stmt*); +int sqlite3_global_recover(void); + + +/* +** CAPI3REF: Obtaining SQL Function Parameter Values +** +** The C-language implementation of SQL functions and aggregates uses +** this set of interface routines to access the parameter values on +** the function or aggregate. +** +** The xFunc (for scalar functions) or xStep (for aggregates) parameters +** to [sqlite3_create_function()] and [sqlite3_create_function16()] +** define callbacks that implement the SQL functions and aggregates. +** The 4th parameter to these callbacks is an array of pointers to +** [sqlite3_value] objects. There is one [sqlite3_value] object for +** each parameter to the SQL function. These routines are used to +** extract values from the [sqlite3_value] objects. +** +** These routines work just like the corresponding +** [sqlite3_column_blob | sqlite3_column_* routines] except that +** these routines take a single [sqlite3_value*] pointer instead +** of an [sqlite3_stmt*] pointer and an integer column number. +** +** The sqlite3_value_text16() interface extracts a UTF16 string +** in the native byte-order of the host machine. The +** sqlite3_value_text16be() and sqlite3_value_text16le() interfaces +** extract UTF16 strings as big-endian and little-endian respectively. +** +** The sqlite3_value_numeric_type() interface attempts to apply +** numeric affinity to the value. This means that an attempt is +** made to convert the value to an integer or floating point. If +** such a conversion is possible without loss of information (in order +** words if the value is original a string that looks like a number) +** then it is done. Otherwise no conversion occurs. The +** [SQLITE_INTEGER | datatype] after conversion is returned. +** +** Please pay particular attention to the fact that the pointer that +** is returned from [sqlite3_value_blob()], [sqlite3_value_text()], or +** [sqlite3_value_text16()] can be invalidated by a subsequent call to +** [sqlite3_value_bytes()], [sqlite3_value_bytes16()], [sqlite_value_text()], +** or [sqlite3_value_text16()]. +*/ +const void *sqlite3_value_blob(sqlite3_value*); +int sqlite3_value_bytes(sqlite3_value*); +int sqlite3_value_bytes16(sqlite3_value*); +double sqlite3_value_double(sqlite3_value*); +int sqlite3_value_int(sqlite3_value*); +sqlite_int64 sqlite3_value_int64(sqlite3_value*); +const unsigned char *sqlite3_value_text(sqlite3_value*); +const void *sqlite3_value_text16(sqlite3_value*); +const void *sqlite3_value_text16le(sqlite3_value*); +const void *sqlite3_value_text16be(sqlite3_value*); +int sqlite3_value_type(sqlite3_value*); +int sqlite3_value_numeric_type(sqlite3_value*); + +/* +** CAPI3REF: Obtain Aggregate Function Context +** +** The implementation of aggregate SQL functions use this routine to allocate +** a structure for storing their state. The first time this routine +** is called for a particular aggregate, a new structure of size nBytes +** is allocated, zeroed, and returned. On subsequent calls (for the +** same aggregate instance) the same buffer is returned. The implementation +** of the aggregate can use the returned buffer to accumulate data. +** +** The buffer allocated is freed automatically by SQLite whan the aggregate +** query concludes. +** +** The first parameter should be a copy of the +** [sqlite3_context | SQL function context] that is the first +** parameter to the callback routine that implements the aggregate +** function. +*/ +void *sqlite3_aggregate_context(sqlite3_context*, int nBytes); + +/* +** CAPI3REF: User Data For Functions +** +** The pUserData parameter to the [sqlite3_create_function()] +** and [sqlite3_create_function16()] routines +** used to register user functions is available to +** the implementation of the function using this call. +*/ +void *sqlite3_user_data(sqlite3_context*); + +/* +** CAPI3REF: Function Auxiliary Data +** +** The following two functions may be used by scalar SQL functions to +** associate meta-data with argument values. If the same value is passed to +** multiple invocations of the same SQL function during query execution, under +** some circumstances the associated meta-data may be preserved. This may +** be used, for example, to add a regular-expression matching scalar +** function. The compiled version of the regular expression is stored as +** meta-data associated with the SQL value passed as the regular expression +** pattern. The compiled regular expression can be reused on multiple +** invocations of the same function so that the original pattern string +** does not need to be recompiled on each invocation. +** +** The sqlite3_get_auxdata() interface returns a pointer to the meta-data +** associated with the Nth argument value to the current SQL function +** call, where N is the second parameter. If no meta-data has been set for +** that value, then a NULL pointer is returned. +** +** The sqlite3_set_auxdata() is used to associate meta-data with an SQL +** function argument. The third parameter is a pointer to the meta-data +** to be associated with the Nth user function argument value. The fourth +** parameter specifies a destructor that will be called on the meta- +** data pointer to release it when it is no longer required. If the +** destructor is NULL, it is not invoked. +** +** In practice, meta-data is preserved between function calls for +** expressions that are constant at compile time. This includes literal +** values and SQL variables. +*/ +void *sqlite3_get_auxdata(sqlite3_context*, int); +void sqlite3_set_auxdata(sqlite3_context*, int, void*, void (*)(void*)); + + +/* +** CAPI3REF: Constants Defining Special Destructor Behavior +** +** These are special value for the destructor that is passed in as the +** final argument to routines like [sqlite3_result_blob()]. If the destructor +** argument is SQLITE_STATIC, it means that the content pointer is constant +** and will never change. It does not need to be destroyed. The +** SQLITE_TRANSIENT value means that the content will likely change in +** the near future and that SQLite should make its own private copy of +** the content before returning. +** +** The typedef is necessary to work around problems in certain +** C++ compilers. See ticket #2191. +*/ +typedef void (*sqlite3_destructor_type)(void*); +#define SQLITE_STATIC ((sqlite3_destructor_type)0) +#define SQLITE_TRANSIENT ((sqlite3_destructor_type)-1) + +/* +** CAPI3REF: Setting The Result Of An SQL Function +** +** These routines are used by the xFunc or xFinal callbacks that +** implement SQL functions and aggregates. See +** [sqlite3_create_function()] and [sqlite3_create_function16()] +** for additional information. +** +** These functions work very much like the +** [sqlite3_bind_blob | sqlite3_bind_*] family of functions used +** to bind values to host parameters in prepared statements. +** Refer to the +** [sqlite3_bind_blob | sqlite3_bind_* documentation] for +** additional information. +** +** The sqlite3_result_error() and sqlite3_result_error16() functions +** cause the implemented SQL function to throw an exception. The +** parameter to sqlite3_result_error() or sqlite3_result_error16() +** is the text of an error message. +** +** The sqlite3_result_toobig() cause the function implementation +** to throw and error indicating that a string or BLOB is to long +** to represent. +*/ +void sqlite3_result_blob(sqlite3_context*, const void*, int, void(*)(void*)); +void sqlite3_result_double(sqlite3_context*, double); +void sqlite3_result_error(sqlite3_context*, const char*, int); +void sqlite3_result_error16(sqlite3_context*, const void*, int); +void sqlite3_result_error_toobig(sqlite3_context*); +void sqlite3_result_int(sqlite3_context*, int); +void sqlite3_result_int64(sqlite3_context*, sqlite_int64); +void sqlite3_result_null(sqlite3_context*); +void sqlite3_result_text(sqlite3_context*, const char*, int, void(*)(void*)); +void sqlite3_result_text16(sqlite3_context*, const void*, int, void(*)(void*)); +void sqlite3_result_text16le(sqlite3_context*, const void*, int,void(*)(void*)); +void sqlite3_result_text16be(sqlite3_context*, const void*, int,void(*)(void*)); +void sqlite3_result_value(sqlite3_context*, sqlite3_value*); +void sqlite3_result_zeroblob(sqlite3_context*, int n); + +/* +** CAPI3REF: Define New Collating Sequences +** +** These functions are used to add new collation sequences to the +** [sqlite3*] handle specified as the first argument. +** +** The name of the new collation sequence is specified as a UTF-8 string +** for sqlite3_create_collation() and sqlite3_create_collation_v2() +** and a UTF-16 string for sqlite3_create_collation16(). In all cases +** the name is passed as the second function argument. +** +** The third argument must be one of the constants [SQLITE_UTF8], +** [SQLITE_UTF16LE] or [SQLITE_UTF16BE], indicating that the user-supplied +** routine expects to be passed pointers to strings encoded using UTF-8, +** UTF-16 little-endian or UTF-16 big-endian respectively. +** +** A pointer to the user supplied routine must be passed as the fifth +** argument. If it is NULL, this is the same as deleting the collation +** sequence (so that SQLite cannot call it anymore). Each time the user +** supplied function is invoked, it is passed a copy of the void* passed as +** the fourth argument to sqlite3_create_collation() or +** sqlite3_create_collation16() as its first parameter. +** +** The remaining arguments to the user-supplied routine are two strings, +** each represented by a [length, data] pair and encoded in the encoding +** that was passed as the third argument when the collation sequence was +** registered. The user routine should return negative, zero or positive if +** the first string is less than, equal to, or greater than the second +** string. i.e. (STRING1 - STRING2). +** +** The sqlite3_create_collation_v2() works like sqlite3_create_collation() +** excapt that it takes an extra argument which is a destructor for +** the collation. The destructor is called when the collation is +** destroyed and is passed a copy of the fourth parameter void* pointer +** of the sqlite3_create_collation_v2(). Collations are destroyed when +** they are overridden by later calls to the collation creation functions +** or when the [sqlite3*] database handle is closed using [sqlite3_close()]. +** +** The sqlite3_create_collation_v2() interface is experimental and +** subject to change in future releases. The other collation creation +** functions are stable. +*/ +int sqlite3_create_collation( + sqlite3*, + const char *zName, + int eTextRep, + void*, + int(*xCompare)(void*,int,const void*,int,const void*) +); +int sqlite3_create_collation_v2( + sqlite3*, + const char *zName, + int eTextRep, + void*, + int(*xCompare)(void*,int,const void*,int,const void*), + void(*xDestroy)(void*) +); +int sqlite3_create_collation16( + sqlite3*, + const char *zName, + int eTextRep, + void*, + int(*xCompare)(void*,int,const void*,int,const void*) +); + +/* +** CAPI3REF: Collation Needed Callbacks +** +** To avoid having to register all collation sequences before a database +** can be used, a single callback function may be registered with the +** database handle to be called whenever an undefined collation sequence is +** required. +** +** If the function is registered using the sqlite3_collation_needed() API, +** then it is passed the names of undefined collation sequences as strings +** encoded in UTF-8. If sqlite3_collation_needed16() is used, the names +** are passed as UTF-16 in machine native byte order. A call to either +** function replaces any existing callback. +** +** When the callback is invoked, the first argument passed is a copy +** of the second argument to sqlite3_collation_needed() or +** sqlite3_collation_needed16(). The second argument is the database +** handle. The third argument is one of [SQLITE_UTF8], [SQLITE_UTF16BE], or +** [SQLITE_UTF16LE], indicating the most desirable form of the collation +** sequence function required. The fourth parameter is the name of the +** required collation sequence. +** +** The callback function should register the desired collation using +** [sqlite3_create_collation()], [sqlite3_create_collation16()], or +** [sqlite3_create_collation_v2()]. +*/ +int sqlite3_collation_needed( + sqlite3*, + void*, + void(*)(void*,sqlite3*,int eTextRep,const char*) +); +int sqlite3_collation_needed16( + sqlite3*, + void*, + void(*)(void*,sqlite3*,int eTextRep,const void*) +); + +/* +** Specify the key for an encrypted database. This routine should be +** called right after sqlite3_open(). +** +** The code to implement this API is not available in the public release +** of SQLite. +*/ +int sqlite3_key( + sqlite3 *db, /* Database to be rekeyed */ + const void *pKey, int nKey /* The key */ +); + +/* +** Change the key on an open database. If the current database is not +** encrypted, this routine will encrypt it. If pNew==0 or nNew==0, the +** database is decrypted. +** +** The code to implement this API is not available in the public release +** of SQLite. +*/ +int sqlite3_rekey( + sqlite3 *db, /* Database to be rekeyed */ + const void *pKey, int nKey /* The new key */ +); + +/* +** CAPI3REF: Suspend Execution For A Short Time +** +** This function causes the current thread to suspect execution +** a number of milliseconds specified in its parameter. +** +** If the operating system does not support sleep requests with +** millisecond time resolution, then the time will be rounded up to +** the nearest second. The number of milliseconds of sleep actually +** requested from the operating system is returned. +*/ +int sqlite3_sleep(int); + +/* +** CAPI3REF: Name Of The Folder Holding Temporary Files +** +** If this global variable is made to point to a string which is +** the name of a folder (a.ka. directory), then all temporary files +** created by SQLite will be placed in that directory. If this variable +** is NULL pointer, then SQLite does a search for an appropriate temporary +** file directory. +** +** Once [sqlite3_open()] has been called, changing this variable will +** invalidate the current temporary database, if any. Generally speaking, +** it is not safe to invoke this routine after [sqlite3_open()] has +** been called. +*/ +extern char *sqlite3_temp_directory; + +/* +** CAPI3REF: Test To See If The Databse Is In Auto-Commit Mode +** +** Test to see whether or not the database connection is in autocommit +** mode. Return TRUE if it is and FALSE if not. Autocommit mode is on +** by default. Autocommit is disabled by a BEGIN statement and reenabled +** by the next COMMIT or ROLLBACK. +*/ +int sqlite3_get_autocommit(sqlite3*); + +/* +** CAPI3REF: Find The Database Handle Associated With A Prepared Statement +** +** Return the [sqlite3*] database handle to which a +** [sqlite3_stmt | prepared statement] belongs. +** This is the same database handle that was +** the first argument to the [sqlite3_prepare_v2()] or its variants +** that was used to create the statement in the first place. +*/ +sqlite3 *sqlite3_db_handle(sqlite3_stmt*); + + +/* +** CAPI3REF: Commit And Rollback Notification Callbacks +** +** These routines +** register callback functions to be invoked whenever a transaction +** is committed or rolled back. The pArg argument is passed through +** to the callback. If the callback on a commit hook function +** returns non-zero, then the commit is converted into a rollback. +** +** If another function was previously registered, its pArg value is returned. +** Otherwise NULL is returned. +** +** Registering a NULL function disables the callback. +** +** For the purposes of this API, a transaction is said to have been +** rolled back if an explicit "ROLLBACK" statement is executed, or +** an error or constraint causes an implicit rollback to occur. The +** callback is not invoked if a transaction is automatically rolled +** back because the database connection is closed. +** +** These are experimental interfaces and are subject to change. +*/ +void *sqlite3_commit_hook(sqlite3*, int(*)(void*), void*); +void *sqlite3_rollback_hook(sqlite3*, void(*)(void *), void*); + +/* +** CAPI3REF: Data Change Notification Callbacks +** +** Register a callback function with the database connection identified by the +** first argument to be invoked whenever a row is updated, inserted or deleted. +** Any callback set by a previous call to this function for the same +** database connection is overridden. +** +** The second argument is a pointer to the function to invoke when a +** row is updated, inserted or deleted. The first argument to the callback is +** a copy of the third argument to sqlite3_update_hook(). The second callback +** argument is one of SQLITE_INSERT, SQLITE_DELETE or SQLITE_UPDATE, depending +** on the operation that caused the callback to be invoked. The third and +** fourth arguments to the callback contain pointers to the database and +** table name containing the affected row. The final callback parameter is +** the rowid of the row. In the case of an update, this is the rowid after +** the update takes place. +** +** The update hook is not invoked when internal system tables are +** modified (i.e. sqlite_master and sqlite_sequence). +** +** If another function was previously registered, its pArg value is returned. +** Otherwise NULL is returned. +*/ +void *sqlite3_update_hook( + sqlite3*, + void(*)(void *,int ,char const *,char const *,sqlite_int64), + void* +); + +/* +** CAPI3REF: Enable Or Disable Shared Pager Cache +** +** This routine enables or disables the sharing of the database cache +** and schema data structures between connections to the same database. +** Sharing is enabled if the argument is true and disabled if the argument +** is false. +** +** Cache sharing is enabled and disabled on a thread-by-thread basis. +** Each call to this routine enables or disables cache sharing only for +** connections created in the same thread in which this routine is called. +** There is no mechanism for sharing cache between database connections +** running in different threads. +** +** Sharing must be disabled prior to shutting down a thread or else +** the thread will leak memory. Call this routine with an argument of +** 0 to turn off sharing. Or use the sqlite3_thread_cleanup() API. +** +** This routine must not be called when any database connections +** are active in the current thread. Enabling or disabling shared +** cache while there are active database connections will result +** in memory corruption. +** +** When the shared cache is enabled, the +** following routines must always be called from the same thread: +** [sqlite3_open()], [sqlite3_prepare_v2()], [sqlite3_step()], +** [sqlite3_reset()], [sqlite3_finalize()], and [sqlite3_close()]. +** This is due to the fact that the shared cache makes use of +** thread-specific storage so that it will be available for sharing +** with other connections. +** +** Virtual tables cannot be used with a shared cache. When shared +** cache is enabled, the sqlite3_create_module() API used to register +** virtual tables will always return an error. +** +** This routine returns [SQLITE_OK] if shared cache was +** enabled or disabled successfully. An [SQLITE_ERROR | error code] +** is returned otherwise. +** +** Shared cache is disabled by default for backward compatibility. +*/ +int sqlite3_enable_shared_cache(int); + +/* +** CAPI3REF: Attempt To Free Heap Memory +** +** Attempt to free N bytes of heap memory by deallocating non-essential +** memory allocations held by the database library (example: memory +** used to cache database pages to improve performance). +** +** This function is not a part of standard builds. It is only created +** if SQLite is compiled with the SQLITE_ENABLE_MEMORY_MANAGEMENT macro. +*/ +int sqlite3_release_memory(int); + +/* +** CAPI3REF: Impose A Limit On Heap Size +** +** Place a "soft" limit on the amount of heap memory that may be allocated by +** SQLite within the current thread. If an internal allocation is requested +** that would exceed the specified limit, [sqlite3_release_memory()] is invoked +** one or more times to free up some space before the allocation is made. +** +** The limit is called "soft", because if [sqlite3_release_memory()] cannot free +** sufficient memory to prevent the limit from being exceeded, the memory is +** allocated anyway and the current operation proceeds. +** +** Prior to shutting down a thread sqlite3_soft_heap_limit() must be set to +** zero (the default) or else the thread will leak memory. Alternatively, use +** the [sqlite3_thread_cleanup()] API. +** +** A negative or zero value for N means that there is no soft heap limit and +** [sqlite3_release_memory()] will only be called when memory is exhaused. +** The default value for the soft heap limit is zero. +** +** SQLite makes a best effort to honor the soft heap limit. But if it +** is unable to reduce memory usage below the soft limit, execution will +** continue without error or notification. This is why the limit is +** called a "soft" limit. It is advisory only. +** +** This function is only available if the library was compiled with the +** SQLITE_ENABLE_MEMORY_MANAGEMENT option set. +** memory-management has been enabled. +*/ +void sqlite3_soft_heap_limit(int); + +/* +** CAPI3REF: Clean Up Thread Local Storage +** +** This routine makes sure that all thread-local storage has been +** deallocated for the current thread. +** +** This routine is not technically necessary. All thread-local storage +** will be automatically deallocated once memory-management and +** shared-cache are disabled and the soft heap limit has been set +** to zero. This routine is provided as a convenience for users who +** want to make absolutely sure they have not forgotten something +** prior to killing off a thread. +*/ +void sqlite3_thread_cleanup(void); + +/* +** CAPI3REF: Extract Metadata About A Column Of A Table +** +** This routine +** returns meta-data about a specific column of a specific database +** table accessible using the connection handle passed as the first function +** argument. +** +** The column is identified by the second, third and fourth parameters to +** this function. The second parameter is either the name of the database +** (i.e. "main", "temp" or an attached database) containing the specified +** table or NULL. If it is NULL, then all attached databases are searched +** for the table using the same algorithm as the database engine uses to +** resolve unqualified table references. +** +** The third and fourth parameters to this function are the table and column +** name of the desired column, respectively. Neither of these parameters +** may be NULL. +** +** Meta information is returned by writing to the memory locations passed as +** the 5th and subsequent parameters to this function. Any of these +** arguments may be NULL, in which case the corresponding element of meta +** information is ommitted. +** +** 
      +** Parameter     Output Type      Description
+** -----------------------------------
+**
+**   5th         const char*      Data type
+**   6th         const char*      Name of the default collation sequence 
+**   7th         int              True if the column has a NOT NULL constraint
+**   8th         int              True if the column is part of the PRIMARY KEY
+**   9th         int              True if the column is AUTOINCREMENT
+**
      +** +** +** The memory pointed to by the character pointers returned for the +** declaration type and collation sequence is valid only until the next +** call to any sqlite API function. +** +** If the specified table is actually a view, then an error is returned. +** +** If the specified column is "rowid", "oid" or "_rowid_" and an +** INTEGER PRIMARY KEY column has been explicitly declared, then the output +** parameters are set for the explicitly declared column. If there is no +** explicitly declared IPK column, then the output parameters are set as +** follows: +** +** 
      +**     data type: "INTEGER"
+**     collation sequence: "BINARY"
+**     not null: 0
+**     primary key: 1
+**     auto increment: 0
+**
      +** +** This function may load one or more schemas from database files. If an +** error occurs during this process, or if the requested table or column +** cannot be found, an SQLITE error code is returned and an error message +** left in the database handle (to be retrieved using sqlite3_errmsg()). +** +** This API is only available if the library was compiled with the +** SQLITE_ENABLE_COLUMN_METADATA preprocessor symbol defined. +*/ +int sqlite3_table_column_metadata( + sqlite3 *db, /* Connection handle */ + const char *zDbName, /* Database name or NULL */ + const char *zTableName, /* Table name */ + const char *zColumnName, /* Column name */ + char const **pzDataType, /* OUTPUT: Declared data type */ + char const **pzCollSeq, /* OUTPUT: Collation sequence name */ + int *pNotNull, /* OUTPUT: True if NOT NULL constraint exists */ + int *pPrimaryKey, /* OUTPUT: True if column part of PK */ + int *pAutoinc /* OUTPUT: True if colums is auto-increment */ +); + +/* +** CAPI3REF: Load An Extension +** +** Attempt to load an SQLite extension library contained in the file +** zFile. The entry point is zProc. zProc may be 0 in which case the +** name of the entry point defaults to "sqlite3_extension_init". +** +** Return [SQLITE_OK] on success and [SQLITE_ERROR] if something goes wrong. +** +** If an error occurs and pzErrMsg is not 0, then fill *pzErrMsg with +** error message text. The calling function should free this memory +** by calling [sqlite3_free()]. +** +** Extension loading must be enabled using [sqlite3_enable_load_extension()] +** prior to calling this API or an error will be returned. +*/ +int sqlite3_load_extension( + sqlite3 *db, /* Load the extension into this database connection */ + const char *zFile, /* Name of the shared library containing extension */ + const char *zProc, /* Entry point. Derived from zFile if 0 */ + char **pzErrMsg /* Put error message here if not 0 */ +); + +/* +** CAPI3REF: Enable Or Disable Extension Loading +** +** So as not to open security holes in older applications that are +** unprepared to deal with extension loading, and as a means of disabling +** extension loading while evaluating user-entered SQL, the following +** API is provided to turn the [sqlite3_load_extension()] mechanism on and +** off. It is off by default. See ticket #1863. +** +** Call this routine with onoff==1 to turn extension loading on +** and call it with onoff==0 to turn it back off again. +*/ +int sqlite3_enable_load_extension(sqlite3 *db, int onoff); + +/* +** CAPI3REF: Make Arrangements To Automatically Load An Extension +** +** Register an extension entry point that is automatically invoked +** whenever a new database connection is opened using +** [sqlite3_open()] or [sqlite3_open16()]. +** +** This API can be invoked at program startup in order to register +** one or more statically linked extensions that will be available +** to all new database connections. +** +** Duplicate extensions are detected so calling this routine multiple +** times with the same extension is harmless. +** +** This routine stores a pointer to the extension in an array +** that is obtained from malloc(). If you run a memory leak +** checker on your program and it reports a leak because of this +** array, then invoke [sqlite3_automatic_extension_reset()] prior +** to shutdown to free the memory. +** +** Automatic extensions apply across all threads. +** +** This interface is experimental and is subject to change or +** removal in future releases of SQLite. +*/ +int sqlite3_auto_extension(void *xEntryPoint); + + +/* +** CAPI3REF: Reset Automatic Extension Loading +** +** Disable all previously registered automatic extensions. This +** routine undoes the effect of all prior [sqlite3_automatic_extension()] +** calls. +** +** This call disabled automatic extensions in all threads. +** +** This interface is experimental and is subject to change or +** removal in future releases of SQLite. +*/ +void sqlite3_reset_auto_extension(void); + + +/* +****** EXPERIMENTAL - subject to change without notice ************** +** +** The interface to the virtual-table mechanism is currently considered +** to be experimental. The interface might change in incompatible ways. +** If this is a problem for you, do not use the interface at this time. +** +** When the virtual-table mechanism stablizes, we will declare the +** interface fixed, support it indefinitely, and remove this comment. +*/ + +/* +** Structures used by the virtual table interface +*/ +typedef struct sqlite3_vtab sqlite3_vtab; +typedef struct sqlite3_index_info sqlite3_index_info; +typedef struct sqlite3_vtab_cursor sqlite3_vtab_cursor; +typedef struct sqlite3_module sqlite3_module; + +/* +** A module is a class of virtual tables. Each module is defined +** by an instance of the following structure. This structure consists +** mostly of methods for the module. +*/ +struct sqlite3_module { + int iVersion; + int (*xCreate)(sqlite3*, void *pAux, + int argc, const char *const*argv, + sqlite3_vtab **ppVTab, char**); + int (*xConnect)(sqlite3*, void *pAux, + int argc, const char *const*argv, + sqlite3_vtab **ppVTab, char**); + int (*xBestIndex)(sqlite3_vtab *pVTab, sqlite3_index_info*); + int (*xDisconnect)(sqlite3_vtab *pVTab); + int (*xDestroy)(sqlite3_vtab *pVTab); + int (*xOpen)(sqlite3_vtab *pVTab, sqlite3_vtab_cursor **ppCursor); + int (*xClose)(sqlite3_vtab_cursor*); + int (*xFilter)(sqlite3_vtab_cursor*, int idxNum, const char *idxStr, + int argc, sqlite3_value **argv); + int (*xNext)(sqlite3_vtab_cursor*); + int (*xEof)(sqlite3_vtab_cursor*); + int (*xColumn)(sqlite3_vtab_cursor*, sqlite3_context*, int); + int (*xRowid)(sqlite3_vtab_cursor*, sqlite_int64 *pRowid); + int (*xUpdate)(sqlite3_vtab *, int, sqlite3_value **, sqlite_int64 *); + int (*xBegin)(sqlite3_vtab *pVTab); + int (*xSync)(sqlite3_vtab *pVTab); + int (*xCommit)(sqlite3_vtab *pVTab); + int (*xRollback)(sqlite3_vtab *pVTab); + int (*xFindFunction)(sqlite3_vtab *pVtab, int nArg, const char *zName, + void (**pxFunc)(sqlite3_context*,int,sqlite3_value**), + void **ppArg); +}; + +/* +** The sqlite3_index_info structure and its substructures is used to +** pass information into and receive the reply from the xBestIndex +** method of an sqlite3_module. The fields under **Inputs** are the +** inputs to xBestIndex and are read-only. xBestIndex inserts its +** results into the **Outputs** fields. +** +** The aConstraint[] array records WHERE clause constraints of the +** form: +** +** column OP expr +** +** Where OP is =, <, <=, >, or >=. The particular operator is stored +** in aConstraint[].op. The index of the column is stored in +** aConstraint[].iColumn. aConstraint[].usable is TRUE if the +** expr on the right-hand side can be evaluated (and thus the constraint +** is usable) and false if it cannot. +** +** The optimizer automatically inverts terms of the form "expr OP column" +** and makes other simplificatinos to the WHERE clause in an attempt to +** get as many WHERE clause terms into the form shown above as possible. +** The aConstraint[] array only reports WHERE clause terms in the correct +** form that refer to the particular virtual table being queried. +** +** Information about the ORDER BY clause is stored in aOrderBy[]. +** Each term of aOrderBy records a column of the ORDER BY clause. +** +** The xBestIndex method must fill aConstraintUsage[] with information +** about what parameters to pass to xFilter. If argvIndex>0 then +** the right-hand side of the corresponding aConstraint[] is evaluated +** and becomes the argvIndex-th entry in argv. If aConstraintUsage[].omit +** is true, then the constraint is assumed to be fully handled by the +** virtual table and is not checked again by SQLite. +** +** The idxNum and idxPtr values are recorded and passed into xFilter. +** sqlite3_free() is used to free idxPtr if needToFreeIdxPtr is true. +** +** The orderByConsumed means that output from xFilter will occur in +** the correct order to satisfy the ORDER BY clause so that no separate +** sorting step is required. +** +** The estimatedCost value is an estimate of the cost of doing the +** particular lookup. A full scan of a table with N entries should have +** a cost of N. A binary search of a table of N entries should have a +** cost of approximately log(N). +*/ +struct sqlite3_index_info { + /* Inputs */ + const int nConstraint; /* Number of entries in aConstraint */ + const struct sqlite3_index_constraint { + int iColumn; /* Column on left-hand side of constraint */ + unsigned char op; /* Constraint operator */ + unsigned char usable; /* True if this constraint is usable */ + int iTermOffset; /* Used internally - xBestIndex should ignore */ + } *const aConstraint; /* Table of WHERE clause constraints */ + const int nOrderBy; /* Number of terms in the ORDER BY clause */ + const struct sqlite3_index_orderby { + int iColumn; /* Column number */ + unsigned char desc; /* True for DESC. False for ASC. */ + } *const aOrderBy; /* The ORDER BY clause */ + + /* Outputs */ + struct sqlite3_index_constraint_usage { + int argvIndex; /* if >0, constraint is part of argv to xFilter */ + unsigned char omit; /* Do not code a test for this constraint */ + } *const aConstraintUsage; + int idxNum; /* Number used to identify the index */ + char *idxStr; /* String, possibly obtained from sqlite3_malloc */ + int needToFreeIdxStr; /* Free idxStr using sqlite3_free() if true */ + int orderByConsumed; /* True if output is already ordered */ + double estimatedCost; /* Estimated cost of using this index */ +}; +#define SQLITE_INDEX_CONSTRAINT_EQ 2 +#define SQLITE_INDEX_CONSTRAINT_GT 4 +#define SQLITE_INDEX_CONSTRAINT_LE 8 +#define SQLITE_INDEX_CONSTRAINT_LT 16 +#define SQLITE_INDEX_CONSTRAINT_GE 32 +#define SQLITE_INDEX_CONSTRAINT_MATCH 64 + +/* +** This routine is used to register a new module name with an SQLite +** connection. Module names must be registered before creating new +** virtual tables on the module, or before using preexisting virtual +** tables of the module. +*/ +int sqlite3_create_module( + sqlite3 *db, /* SQLite connection to register module with */ + const char *zName, /* Name of the module */ + const sqlite3_module *, /* Methods for the module */ + void * /* Client data for xCreate/xConnect */ +); + +/* +** Every module implementation uses a subclass of the following structure +** to describe a particular instance of the module. Each subclass will +** be taylored to the specific needs of the module implementation. The +** purpose of this superclass is to define certain fields that are common +** to all module implementations. +** +** Virtual tables methods can set an error message by assigning a +** string obtained from sqlite3_mprintf() to zErrMsg. The method should +** take care that any prior string is freed by a call to sqlite3_free() +** prior to assigning a new string to zErrMsg. After the error message +** is delivered up to the client application, the string will be automatically +** freed by sqlite3_free() and the zErrMsg field will be zeroed. Note +** that sqlite3_mprintf() and sqlite3_free() are used on the zErrMsg field +** since virtual tables are commonly implemented in loadable extensions which +** do not have access to sqlite3MPrintf() or sqlite3Free(). +*/ +struct sqlite3_vtab { + const sqlite3_module *pModule; /* The module for this virtual table */ + int nRef; /* Used internally */ + char *zErrMsg; /* Error message from sqlite3_mprintf() */ + /* Virtual table implementations will typically add additional fields */ +}; + +/* Every module implementation uses a subclass of the following structure +** to describe cursors that point into the virtual table and are used +** to loop through the virtual table. Cursors are created using the +** xOpen method of the module. Each module implementation will define +** the content of a cursor structure to suit its own needs. +** +** This superclass exists in order to define fields of the cursor that +** are common to all implementations. +*/ +struct sqlite3_vtab_cursor { + sqlite3_vtab *pVtab; /* Virtual table of this cursor */ + /* Virtual table implementations will typically add additional fields */ +}; + +/* +** The xCreate and xConnect methods of a module use the following API +** to declare the format (the names and datatypes of the columns) of +** the virtual tables they implement. +*/ +int sqlite3_declare_vtab(sqlite3*, const char *zCreateTable); + +/* +** Virtual tables can provide alternative implementations of functions +** using the xFindFunction method. But global versions of those functions +** must exist in order to be overloaded. +** +** This API makes sure a global version of a function with a particular +** name and number of parameters exists. If no such function exists +** before this API is called, a new function is created. The implementation +** of the new function always causes an exception to be thrown. So +** the new function is not good for anything by itself. Its only +** purpose is to be a place-holder function that can be overloaded +** by virtual tables. +** +** This API should be considered part of the virtual table interface, +** which is experimental and subject to change. +*/ +int sqlite3_overload_function(sqlite3*, const char *zFuncName, int nArg); + +/* +** The interface to the virtual-table mechanism defined above (back up +** to a comment remarkably similar to this one) is currently considered +** to be experimental. The interface might change in incompatible ways. +** If this is a problem for you, do not use the interface at this time. +** +** When the virtual-table mechanism stablizes, we will declare the +** interface fixed, support it indefinitely, and remove this comment. +** +****** EXPERIMENTAL - subject to change without notice ************** +*/ + +/* +** CAPI3REF: A Handle To An Open BLOB +** +** An instance of the following opaque structure is used to +** represent an blob-handle. A blob-handle is created by +** [sqlite3_blob_open()] and destroyed by [sqlite3_blob_close()]. +** The [sqlite3_blob_read()] and [sqlite3_blob_write()] interfaces +** can be used to read or write small subsections of the blob. +** The [sqltie3_blob_size()] interface returns the size of the +** blob in bytes. +*/ +typedef struct sqlite3_blob sqlite3_blob; + +/* +** CAPI3REF: Open A BLOB For Incremental I/O +** +** Open a handle to the blob located in row iRow,, column zColumn, +** table zTable in database zDb. i.e. the same blob that would +** be selected by: +** +** 
      +**     SELECT zColumn FROM zDb.zTable WHERE rowid = iRow;
+**
      +** +** If the flags parameter is non-zero, the blob is opened for +** read and write access. If it is zero, the blob is opened for read +** access. +** +** On success, [SQLITE_OK] is returned and the new +** [sqlite3_blob | blob handle] is written to *ppBlob. +** Otherwise an error code is returned and +** any value written to *ppBlob should not be used by the caller. +** This function sets the database-handle error code and message +** accessible via [sqlite3_errcode()] and [sqlite3_errmsg()]. +*/ +int sqlite3_blob_open( + sqlite3*, + const char *zDb, + const char *zTable, + const char *zColumn, + sqlite_int64 iRow, + int flags, + sqlite3_blob **ppBlob +); + +/* +** CAPI3REF: Close A BLOB Handle +** +** Close an open [sqlite3_blob | blob handle]. +*/ +int sqlite3_blob_close(sqlite3_blob *); + +/* +** CAPI3REF: Return The Size Of An Open BLOB +** +** Return the size in bytes of the blob accessible via the open +** [sqlite3_blob | blob-handle] passed as an argument. +*/ +int sqlite3_blob_bytes(sqlite3_blob *); + +/* +** CAPI3REF: Read Data From A BLOB Incrementally +** +** This function is used to read data from an open +** [sqlite3_blob | blob-handle] into a caller supplied buffer. +** n bytes of data are copied into buffer +** z from the open blob, starting at offset iOffset. +** +** On success, SQLITE_OK is returned. Otherwise, an +** [SQLITE_ERROR | SQLite error code] or an +** [SQLITE_IOERR_READ | extended error code] is returned. +*/ +int sqlite3_blob_read(sqlite3_blob *, void *z, int n, int iOffset); + +/* +** CAPI3REF: Write Data Into A BLOB Incrementally +** +** This function is used to write data into an open +** [sqlite3_blob | blob-handle] from a user supplied buffer. +** n bytes of data are copied from the buffer +** pointed to by z into the open blob, starting at offset iOffset. +** +** If the [sqlite3_blob | blob-handle] passed as the first argument +** was not opened for writing (the flags parameter to [sqlite3_blob_open()] +*** was zero), this function returns [SQLITE_READONLY]. +** +** This function may only modify the contents of the blob, it is +** not possible to increase the size of a blob using this API. If +** offset iOffset is less than n bytes from the end of the blob, +** [SQLITE_ERROR] is returned and no data is written. +** +** On success, SQLITE_OK is returned. Otherwise, an +** [SQLITE_ERROR | SQLite error code] or an +** [SQLITE_IOERR_READ | extended error code] is returned. +*/ +int sqlite3_blob_write(sqlite3_blob *, const void *z, int n, int iOffset); + +/* +** Undo the hack that converts floating point types to integer for +** builds on processors without floating point support. +*/ +#ifdef SQLITE_OMIT_FLOATING_POINT +# undef double +#endif + +#ifdef __cplusplus +} /* End of the 'extern "C"' block */ +#endif +#endif From sabre at nondot.org Wed Feb 4 23:42:30 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Feb 2009 05:42:30 -0000 Subject: [llvm-commits] [llvm] r63836 - /llvm/trunk/docs/LangRef.html Message-ID: <200902050542.n155gUro006415@zion.cs.uiuc.edu> Author: lattner Date: Wed Feb 4 23:42:28 2009 New Revision: 63836 URL: http://llvm.org/viewvc/llvm-project?rev=63836&view=rev Log: PR3485, document alignment on byref. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=63836&r1=63835&r2=63836&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Wed Feb 4 23:42:28 2009 @@ -922,7 +922,10 @@ belong to the caller not the callee (for example, readonly functions should not write to byval parameters). This is not a valid attribute for return - values.
      + values. The byval attribute also supports specifying an alignment with the + align attribute. This has a target-specific effect on the code generator + that usually indicates a desired alignment for the synthesized stack + slot.
      sret
      This indicates that the pointer parameter specifies the address of a From resistor at mac.com Wed Feb 4 23:58:41 2009 From: resistor at mac.com (Owen Anderson) Date: Thu, 05 Feb 2009 05:58:41 -0000 Subject: [llvm-commits] [llvm] r63837 - /llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Message-ID: <200902050558.n155wf7n007857@zion.cs.uiuc.edu> Author: resistor Date: Wed Feb 4 23:58:41 2009 New Revision: 63837 URL: http://llvm.org/viewvc/llvm-project?rev=63837&view=rev Log: Pre-alloc splitting needs to be more careful to avoid inserting spills/restores between call frame setup/restore points. Unfortunately, this regresses code size a bit, but at least it's correct now! Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=63837&r1=63836&r2=63837&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original) +++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Wed Feb 4 23:58:41 2009 @@ -228,28 +228,52 @@ ++MII; unsigned Index = LIs->getInstructionIndex(MII); unsigned Gap = LIs->findGapBeforeInstr(Index); - if (Gap) { - Pt = MII; - SpillIndex = Gap; - break; // We can't insert the spill between the barrier (a call), and its - // corresponding call frame setup. - } else if (prior(MII)->getOpcode() == TRI->getCallFrameSetupOpcode() && - MII == MachineBasicBlock::iterator(MI)) + // corresponding call frame setup/teardown. + if (prior(MII)->getOpcode() == TRI->getCallFrameSetupOpcode()) { + bool reachedBarrier = false; + do { + if (MII == EndPt) { + reachedBarrier = true; + break; + } + ++MII; + } while (MII->getOpcode() != TRI->getCallFrameDestroyOpcode()); + + if (reachedBarrier) break; + } else if (Gap) { + Pt = MII; + SpillIndex = Gap; break; + } } while (MII != EndPt); } else { MachineBasicBlock::iterator MII = MI; MachineBasicBlock::iterator EndPt = DefMI ? MachineBasicBlock::iterator(DefMI) : MBB->begin(); - // We can't insert the spill between the barrier (a call), and its - // corresponding call frame setup. - if (prior(MII)->getOpcode() == TRI->getCallFrameSetupOpcode()) --MII; while (MII != EndPt && !RefsInMBB.count(MII)) { unsigned Index = LIs->getInstructionIndex(MII); - if (LIs->hasGapBeforeInstr(Index)) { + + // We can't insert the spill between the barrier (a call), and its + // corresponding call frame setup. + if (prior(MII)->getOpcode() == TRI->getCallFrameSetupOpcode()) { + --MII; + continue; + } if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode()) { + bool reachedBarrier = false; + while (MII->getOpcode() != TRI->getCallFrameSetupOpcode()) { + --MII; + if (MII == EndPt) { + reachedBarrier = true; + break; + } + } + + if (reachedBarrier) break; + else continue; + } else if (LIs->hasGapBeforeInstr(Index)) { Pt = MII; SpillIndex = LIs->findGapBeforeInstr(Index, true); } @@ -283,25 +307,32 @@ do { unsigned Index = LIs->getInstructionIndex(MII); unsigned Gap = LIs->findGapBeforeInstr(Index); - if (Gap) { - Pt = MII; - RestoreIndex = Gap; - break; // We can't insert a restore between the barrier (a call) and its // corresponding call frame teardown. - } else if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode() && - prior(MII) == MachineBasicBlock::iterator(MI)) + if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode()) { + bool reachedBarrier = false; + while (MII->getOpcode() != TRI->getCallFrameSetupOpcode()) { + --MII; + if (MII == EndPt) { + reachedBarrier = true; + break; + } + } + + if (reachedBarrier) break; + else continue; + } else if (Gap) { + Pt = MII; + RestoreIndex = Gap; break; + } + --MII; } while (MII != EndPt); } else { MachineBasicBlock::iterator MII = MI; MII = ++MII; - // We can't insert a restore between the barrier (a call) and its - // corresponding call frame teardown. - if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode()) - ++MII; // FIXME: Limit the number of instructions to examine to reduce // compile time? @@ -310,10 +341,29 @@ if (Index > LastIdx) break; unsigned Gap = LIs->findGapBeforeInstr(Index); - if (Gap) { + + // We can't insert a restore between the barrier (a call) and its + // corresponding call frame teardown. + if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode()) { + ++MII; + continue; + } else if (prior(MII)->getOpcode() == TRI->getCallFrameSetupOpcode()) { + bool reachedBarrier = false; + do { + if (MII == MBB->getFirstTerminator() || RefsInMBB.count(MII)) { + reachedBarrier = true; + break; + } + + ++MII; + } while (MII->getOpcode() != TRI->getCallFrameDestroyOpcode()); + + if (reachedBarrier) break; + } else if (Gap) { Pt = MII; RestoreIndex = Gap; } + if (RefsInMBB.count(MII)) break; ++MII; From kremenek at apple.com Thu Feb 5 00:37:35 2009 From: kremenek at apple.com (Ted Kremenek) Date: Thu, 05 Feb 2009 06:37:35 -0000 Subject: [llvm-commits] [llvm] r63838 - /llvm/tags/checker/checker-0.149/ Message-ID: <200902050637.n156bZUq022101@zion.cs.uiuc.edu> Author: kremenek Date: Thu Feb 5 00:37:35 2009 New Revision: 63838 URL: http://llvm.org/viewvc/llvm-project?rev=63838&view=rev Log: Removing checker-0.149. Removed: llvm/tags/checker/checker-0.149/ From kremenek at apple.com Thu Feb 5 00:50:47 2009 From: kremenek at apple.com (Ted Kremenek) Date: Thu, 05 Feb 2009 06:50:47 -0000 Subject: [llvm-commits] [llvm] r63841 - /llvm/tags/checker/checker-0.149/ Message-ID: <200902050650.n156ol4a024990@zion.cs.uiuc.edu> Author: kremenek Date: Thu Feb 5 00:50:47 2009 New Revision: 63841 URL: http://llvm.org/viewvc/llvm-project?rev=63841&view=rev Log: Tagging checker-0.149. Added: llvm/tags/checker/checker-0.149/ - copied from r63840, llvm/trunk/ From sabre at nondot.org Thu Feb 5 00:55:21 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Feb 2009 06:55:21 -0000 Subject: [llvm-commits] [llvm] r63843 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/X86/2009-02-04-sext-i64-gep.ll Message-ID: <200902050655.n156tL6v026261@zion.cs.uiuc.edu> Author: lattner Date: Thu Feb 5 00:55:21 2009 New Revision: 63843 URL: http://llvm.org/viewvc/llvm-project?rev=63843&view=rev Log: if we have a large GEP offset on a 32-bit or other target, make sure to print the value properly sext'd to the right pointer size. This fixes PR3481. Added: llvm/trunk/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=63843&r1=63842&r2=63843&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Feb 5 00:55:21 2009 @@ -815,6 +815,12 @@ SmallVector idxVec(CE->op_begin()+1, CE->op_end()); if (int64_t Offset = TD->getIndexedOffset(ptrVal->getType(), &idxVec[0], idxVec.size())) { + // Truncate/sext the offset to the pointer size. + if (TD->getPointerSizeInBits() != 64) { + int SExtAmount = 64-TD->getPointerSizeInBits(); + Offset = (Offset << SExtAmount) >> SExtAmount; + } + if (Offset) O << '('; EmitConstantValueOnly(ptrVal); Added: llvm/trunk/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll?rev=63843&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll (added) +++ llvm/trunk/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll Thu Feb 5 00:55:21 2009 @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc | grep { - 92} +; PR3481 +; The offset should print as -92, not +17179869092 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" +target triple = "i386-pc-linux-gnu" + at p = common global [10 x i32] zeroinitializer, align 4 ; <[10 x i32]*> + at g = global [1 x i32*] [ i32* bitcast (i8* getelementptr (i8* bitcast +([10 x i32]* @p to i8*), i64 17179869092) to i32*) ], align 4 From espindola at google.com Thu Feb 5 02:14:14 2009 From: espindola at google.com (Rafael Espindola) Date: Thu, 5 Feb 2009 08:14:14 +0000 Subject: [llvm-commits] [llvm] r63834 - /llvm/trunk/tools/gold/gold-plugin.cpp In-Reply-To: <200902050536.n155a2Wf002890@zion.cs.uiuc.edu> References: <200902050536.n155a2Wf002890@zion.cs.uiuc.edu> Message-ID: <38a0d8450902050014x2bf643f4pe7c4900163d0ac27@mail.gmail.com> 2009/2/5 Nick Lewycky : > Author: nicholas > Date: Wed Feb 4 23:36:01 2009 > New Revision: 63834 > > URL: http://llvm.org/viewvc/llvm-project?rev=63834&view=rev > Log: > It's not obvious, but lto_module_create_from_memory doesn't need to use the > buffer after it creates the Module. Thus, we don't need to store this pointer > in claimed_file. Don't you need to free it? > lto_codegen_dispose(cg); > - for (std::list::iterator I = Modules.begin(), > - E = Modules.end(); I != E; ++I) { > - free(I->buf); > - } Cheers, -- Rafael Avila de Espindola Google | Gordon House | Barrow Street | Dublin 4 | Ireland Registered in Dublin, Ireland | Registration Number: 368047 From baldrick at free.fr Thu Feb 5 02:19:00 2009 From: baldrick at free.fr (Duncan Sands) Date: Thu, 5 Feb 2009 09:19:00 +0100 Subject: [llvm-commits] [llvm] r63772 - /llvm/trunk/test/Assembler/2007-04-15-BadIntrinsic.ll In-Reply-To: <200902042107.n14L7cV6018098@zion.cs.uiuc.edu> References: <200902042107.n14L7cV6018098@zion.cs.uiuc.edu> Message-ID: <200902050919.00634.baldrick@free.fr> Hi Nate, > Remove now-incorrect test. why is it incorrect? Ciao, Duncan. > > Removed: > llvm/trunk/test/Assembler/2007-04-15-BadIntrinsic.ll > > Removed: llvm/trunk/test/Assembler/2007-04-15-BadIntrinsic.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/2007-04-15-BadIntrinsic.ll?rev=63771&view=auto > > ============================================================================== > --- llvm/trunk/test/Assembler/2007-04-15-BadIntrinsic.ll (original) > +++ llvm/trunk/test/Assembler/2007-04-15-BadIntrinsic.ll (removed) > @@ -1,9 +0,0 @@ > -; RUN: not llvm-as %s -o /dev/null -f |& grep {Call to invalid LLVM intrinsic} > - > -declare i32 @llvm.foobar(i32 %foo) > - > -define i32 @test() { > - %nada = call i32 @llvm.foobar(i32 0) > - ret i32 %nada > -} > - > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From baldrick at free.fr Thu Feb 5 02:20:01 2009 From: baldrick at free.fr (Duncan Sands) Date: Thu, 5 Feb 2009 09:20:01 +0100 Subject: [llvm-commits] [llvm] r63774 - /llvm/trunk/test/CodeGen/X86/legalizedag_vec.ll In-Reply-To: <200902042110.n14LAuLD018215@zion.cs.uiuc.edu> References: <200902042110.n14LAuLD018215@zion.cs.uiuc.edu> Message-ID: <200902050920.01868.baldrick@free.fr> > Add test case for r63760. Thanks! This will help ensure that the issue gets solved before I delete all the type legalization stuff in LegalizeDAG :) Ciao, Duncan. From baldrick at free.fr Thu Feb 5 02:24:38 2009 From: baldrick at free.fr (Duncan Sands) Date: Thu, 5 Feb 2009 09:24:38 +0100 Subject: [llvm-commits] [llvm] r63623 - in /llvm/trunk/tools: Makefile gold/ gold/Makefile gold/README.txt gold/gold-plugin.cpp In-Reply-To: <498A6456.6070305@mxc.ca> References: <200902030713.n137DP9o009780@zion.cs.uiuc.edu> <1A3250C2-449A-466A-B616-49AC4D036D9C@apple.com> <498A6456.6070305@mxc.ca> Message-ID: <200902050924.38914.baldrick@free.fr> > > Hum, can we configure in -use-gold-plugin so that we get goldness with > > just -O4 when the environment can support it? > > I don't see why not. llvm-gcc -O4 is broken on linux for non-Gold users, > and probably always will be. I would like llvm-gcc to do the right thing when passed bitcode files, regardless of the optimization level. Ciao, Duncan. From espindola at google.com Thu Feb 5 02:35:03 2009 From: espindola at google.com (Rafael Espindola) Date: Thu, 5 Feb 2009 08:35:03 +0000 Subject: [llvm-commits] [llvm] r63623 - in /llvm/trunk/tools: Makefile gold/ gold/Makefile gold/README.txt gold/gold-plugin.cpp In-Reply-To: <200902050924.38914.baldrick@free.fr> References: <200902030713.n137DP9o009780@zion.cs.uiuc.edu> <1A3250C2-449A-466A-B616-49AC4D036D9C@apple.com> <498A6456.6070305@mxc.ca> <200902050924.38914.baldrick@free.fr> Message-ID: <38a0d8450902050035k3ecdd83btccd94fed99f73b79@mail.gmail.com> > I would like llvm-gcc to do the right thing when passed bitcode files, > regardless of the optimization level. You need a linker plugin in the general case for that to work. Right now it should work if you pass -use-gold-plugin. I am wondering what is the best way to add a configure option to always look for the plugin at run time. > Ciao, > > Duncan. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > Cheers, -- Rafael Avila de Espindola Google | Gordon House | Barrow Street | Dublin 4 | Ireland Registered in Dublin, Ireland | Registration Number: 368047 From evan.cheng at apple.com Thu Feb 5 02:41:57 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 05 Feb 2009 08:41:57 -0000 Subject: [llvm-commits] [llvm] r63851 - /llvm/trunk/include/llvm/Target/TargetInstrDesc.h Message-ID: <200902050841.n158fwdA003635@zion.cs.uiuc.edu> Author: evancheng Date: Thu Feb 5 02:41:53 2009 New Revision: 63851 URL: http://llvm.org/viewvc/llvm-project?rev=63851&view=rev Log: Clarify comments. Modified: llvm/trunk/include/llvm/Target/TargetInstrDesc.h Modified: llvm/trunk/include/llvm/Target/TargetInstrDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrDesc.h?rev=63851&r1=63850&r2=63851&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrDesc.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrDesc.h Thu Feb 5 02:41:53 2009 @@ -407,9 +407,10 @@ /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or /// less) than a move instruction. This is useful during certain types of - /// rematerializations (e.g., during two-address conversion) where we would - /// like to remat the instruction, but not if it costs more than moving the - /// instruction into the appropriate register. + /// optimizations (e.g., remat during two-address conversion or machine licm) + /// where we would like to remat or hoist the instruction, but not if it costs + /// more than moving the instruction into the appropriate register. Note, we + /// are not marking copies from and to the same register class with this flag. bool isAsCheapAsAMove() const { return Flags & (1 << TID::CheapAsAMove); } From evan.cheng at apple.com Thu Feb 5 02:42:55 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 05 Feb 2009 08:42:55 -0000 Subject: [llvm-commits] [llvm] r63852 - in /llvm/trunk/lib/Target: ARM/ARMInstrInfo.td X86/X86Instr64bit.td X86/X86InstrInfo.td X86/X86InstrSSE.td Message-ID: <200902050842.n158guTB003907@zion.cs.uiuc.edu> Author: evancheng Date: Thu Feb 5 02:42:55 2009 New Revision: 63852 URL: http://llvm.org/viewvc/llvm-project?rev=63852&view=rev Log: A few more isAsCheapAsAMove. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/X86/X86Instr64bit.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=63852&r1=63851&r2=63852&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Feb 5 02:42:55 2009 @@ -773,7 +773,7 @@ def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm, "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP; -let isReMaterializable = 1 in +let isReMaterializable = 1, isAsCheapAsAMove = 1 in def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP; @@ -922,7 +922,7 @@ def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm, "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP; -let isReMaterializable = 1 in +let isReMaterializable = 1, isAsCheapAsAMove = 1 in def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm, "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP; Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=63852&r1=63851&r2=63852&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Thu Feb 5 02:42:55 2009 @@ -1229,7 +1229,7 @@ [(set GR64:$dst, 0)]>; // Materialize i64 constant where top 32-bits are zero. -let AddedComplexity = 1, isReMaterializable = 1 in +let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src), "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}", [(set GR64:$dst, i64immZExt32:$src)]>; Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=63852&r1=63851&r2=63852&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Feb 5 02:42:55 2009 @@ -2812,7 +2812,7 @@ // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX). -let neverHasSideEffects = 1 in { +let neverHasSideEffects = 1, isAsCheapAsAMove = 1 in { def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src), "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src), Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=63852&r1=63851&r2=63852&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Feb 5 02:42:55 2009 @@ -1004,6 +1004,7 @@ } // FR32 to 128-bit vector conversion. +let isAsCheapAsAMove = 1 in def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src), "movss\t{$src, $dst|$dst, $src}", [(set VR128:$dst, @@ -1018,6 +1019,7 @@ // like this: // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), // (f32 FR32:$src)>; +let isAsCheapAsAMove = 1 in def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src), "movss\t{$src, $dst|$dst, $src}", [(set FR32:$dst, (vector_extract (v4f32 VR128:$src), @@ -2269,6 +2271,7 @@ [(set VR128:$dst, (v4i32 immAllOnesV))]>; // FR64 to 128-bit vector conversion. +let isAsCheapAsAMove = 1 in def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src), "movsd\t{$src, $dst|$dst, $src}", [(set VR128:$dst, @@ -2311,6 +2314,7 @@ // like this: // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), // (f32 FR32:$src)>; +let isAsCheapAsAMove = 1 in def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src), "movsd\t{$src, $dst|$dst, $src}", [(set FR64:$dst, (vector_extract (v2f64 VR128:$src), From evan.cheng at apple.com Thu Feb 5 02:45:04 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 05 Feb 2009 08:45:04 -0000 Subject: [llvm-commits] [llvm] r63853 - in /llvm/trunk/lib/CodeGen: SimpleRegisterCoalescing.cpp SimpleRegisterCoalescing.h Message-ID: <200902050845.n158j4Bq004541@zion.cs.uiuc.edu> Author: evancheng Date: Thu Feb 5 02:45:04 2009 New Revision: 63853 URL: http://llvm.org/viewvc/llvm-project?rev=63853&view=rev Log: ReMaterializeTrivialDef need to trim the live interval to the last kill if the copy kills the source register. This fixes uint64tof64.ll after ARM::MOVi is marked as isAsCheapAsAMove. Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=63853&r1=63852&r2=63853&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Thu Feb 5 02:45:04 2009 @@ -450,6 +450,97 @@ return true; } +/// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply +/// fallthoughs to SuccMBB. +static bool isSameOrFallThroughBB(MachineBasicBlock *MBB, + MachineBasicBlock *SuccMBB, + const TargetInstrInfo *tii_) { + if (MBB == SuccMBB) + return true; + MachineBasicBlock *TBB = 0, *FBB = 0; + SmallVector Cond; + return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB && + MBB->isSuccessor(SuccMBB); +} + +/// removeRange - Wrapper for LiveInterval::removeRange. This removes a range +/// from a physical register live interval as well as from the live intervals +/// of its sub-registers. +static void removeRange(LiveInterval &li, unsigned Start, unsigned End, + LiveIntervals *li_, const TargetRegisterInfo *tri_) { + li.removeRange(Start, End, true); + if (TargetRegisterInfo::isPhysicalRegister(li.reg)) { + for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) { + if (!li_->hasInterval(*SR)) + continue; + LiveInterval &sli = li_->getInterval(*SR); + unsigned RemoveEnd = Start; + while (RemoveEnd != End) { + LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start); + if (LR == sli.end()) + break; + RemoveEnd = (LR->end < End) ? LR->end : End; + sli.removeRange(Start, RemoveEnd, true); + Start = RemoveEnd; + } + } + } +} + +/// TrimLiveIntervalToLastUse - If there is a last use in the same basic block +/// as the copy instruction, trim the ive interval to the last use and return +/// true. +bool +SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(unsigned CopyIdx, + MachineBasicBlock *CopyMBB, + LiveInterval &li, + const LiveRange *LR) { + unsigned MBBStart = li_->getMBBStartIdx(CopyMBB); + unsigned LastUseIdx; + MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg, + LastUseIdx); + if (LastUse) { + MachineInstr *LastUseMI = LastUse->getParent(); + if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) { + // r1024 = op + // ... + // BB1: + // = r1024 + // + // BB2: + // r1025 = r1024 + if (MBBStart < LR->end) + removeRange(li, MBBStart, LR->end, li_, tri_); + return true; + } + + // There are uses before the copy, just shorten the live range to the end + // of last use. + LastUse->setIsKill(); + removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_); + unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; + if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && + DstReg == li.reg) { + // Last use is itself an identity code. + int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_); + LastUseMI->getOperand(DeadIdx).setIsDead(); + } + return true; + } + + // Is it livein? + if (LR->start <= MBBStart && LR->end > MBBStart) { + if (LR->start == 0) { + assert(TargetRegisterInfo::isPhysicalRegister(li.reg)); + // Live-in to the function but dead. Remove it from entry live-in set. + mf_->begin()->removeLiveIn(li.reg); + } + // FIXME: Shorten intervals in BBs that reaches this BB. + } + + return false; +} + /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial /// computation, replace the copy by rematerialize the definition. bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt, @@ -485,7 +576,12 @@ } } + // If copy kills the source register, find the last use and propagate + // kill. MachineBasicBlock *MBB = CopyMI->getParent(); + if (CopyMI->killsRegister(SrcInt.reg)) + TrimLiveIntervalToLastUse(CopyIdx, MBB, SrcInt, SrcLR); + MachineBasicBlock::iterator MII = next(MachineBasicBlock::iterator(CopyMI)); CopyMI->removeFromParent(); tii_->reMaterialize(*MBB, MII, DstReg, DefMI); @@ -660,30 +756,6 @@ } } -/// removeRange - Wrapper for LiveInterval::removeRange. This removes a range -/// from a physical register live interval as well as from the live intervals -/// of its sub-registers. -static void removeRange(LiveInterval &li, unsigned Start, unsigned End, - LiveIntervals *li_, const TargetRegisterInfo *tri_) { - li.removeRange(Start, End, true); - if (TargetRegisterInfo::isPhysicalRegister(li.reg)) { - for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) { - if (!li_->hasInterval(*SR)) - continue; - LiveInterval &sli = li_->getInterval(*SR); - unsigned RemoveEnd = Start; - while (RemoveEnd != End) { - LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start); - if (LR == sli.end()) - break; - RemoveEnd = (LR->end < End) ? LR->end : End; - sli.removeRange(Start, RemoveEnd, true); - Start = RemoveEnd; - } - } - } -} - /// removeIntervalIfEmpty - Check if the live interval of a physical register /// is empty, if so remove it and also remove the empty intervals of its /// sub-registers. Return true if live interval is removed. @@ -752,19 +824,6 @@ } } -/// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply -/// fallthoughs to SuccMBB. -static bool isSameOrFallThroughBB(MachineBasicBlock *MBB, - MachineBasicBlock *SuccMBB, - const TargetInstrInfo *tii_) { - if (MBB == SuccMBB) - return true; - MachineBasicBlock *TBB = 0, *FBB = 0; - SmallVector Cond; - return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB && - MBB->isSuccessor(SuccMBB); -} - /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially /// extended by a dead copy. Mark the last use (if any) of the val# as kill as /// ends the live range there. If there isn't another use, then this live range @@ -796,49 +855,10 @@ // More uses past this copy? Nothing to do. return false; - MachineBasicBlock *CopyMBB = CopyMI->getParent(); - unsigned MBBStart = li_->getMBBStartIdx(CopyMBB); - unsigned LastUseIdx; - MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg, - LastUseIdx); - if (LastUse) { - MachineInstr *LastUseMI = LastUse->getParent(); - if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) { - // r1024 = op - // ... - // BB1: - // = r1024 - // - // BB2: - // r1025 = r1024 - if (MBBStart < LR->end) - removeRange(li, MBBStart, LR->end, li_, tri_); - return false; - } - - // There are uses before the copy, just shorten the live range to the end - // of last use. - LastUse->setIsKill(); - removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_); - unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; - if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && - DstReg == li.reg) { - // Last use is itself an identity code. - int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_); - LastUseMI->getOperand(DeadIdx).setIsDead(); - } + // If there is a last use in the same bb, we can't remove the live range. + // Shorten the live interval and return. + if (TrimLiveIntervalToLastUse(CopyIdx, CopyMI->getParent(), li, LR)) return false; - } - - // Is it livein? - if (LR->start <= MBBStart && LR->end > MBBStart) { - if (LR->start == 0) { - assert(TargetRegisterInfo::isPhysicalRegister(li.reg)); - // Live-in to the function but dead. Remove it from entry live-in set. - mf_->begin()->removeLiveIn(li.reg); - } - // FIXME: Shorten intervals in BBs that reaches this BB. - } if (LR->valno->def == RemoveStart) // If the def MI defines the val#, propagate the dead marker. Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h?rev=63853&r1=63852&r2=63853&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Thu Feb 5 02:45:04 2009 @@ -196,6 +196,15 @@ bool RemoveCopyByCommutingDef(LiveInterval &IntA, LiveInterval &IntB, MachineInstr *CopyMI); + /// TrimLiveIntervalToLastUse - If there is a last use in the same basic + /// block as the copy instruction, trim the ive interval to the last use + /// and return true. + bool TrimLiveIntervalToLastUse(unsigned CopyIdx, + MachineBasicBlock *CopyMBB, + LiveInterval &li, const LiveRange *LR); + + /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial + /// computation, replace the copy by rematerialize the definition. bool ReMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg, MachineInstr *CopyMI); From evan.cheng at apple.com Thu Feb 5 02:45:46 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 05 Feb 2009 08:45:46 -0000 Subject: [llvm-commits] [llvm] r63854 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp Message-ID: <200902050845.n158jkuJ004776@zion.cs.uiuc.edu> Author: evancheng Date: Thu Feb 5 02:45:46 2009 New Revision: 63854 URL: http://llvm.org/viewvc/llvm-project?rev=63854&view=rev Log: Teach machine licm to CSE hoisted instructions. Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=63854&r1=63853&r2=63854&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Thu Feb 5 02:45:46 2009 @@ -28,6 +28,7 @@ #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/Statistic.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Compiler.h" @@ -36,6 +37,7 @@ using namespace llvm; STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops"); +STATISTIC(NumCSEed, "Number of hoisted machine instructions CSEed"); namespace { class VISIBILITY_HIDDEN MachineLICM : public MachineFunctionPass { @@ -51,6 +53,10 @@ bool Changed; // True if a loop is changed. MachineLoop *CurLoop; // The current loop we are working on. MachineBasicBlock *CurPreheader; // The preheader for CurLoop. + + // For each BB and opcode pair, keep a list of hoisted instructions. + DenseMap, + std::vector > CSEMap; public: static char ID; // Pass identification, replacement for typeid MachineLICM() : MachineFunctionPass(&ID) {} @@ -68,6 +74,11 @@ AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } + + virtual void releaseMemory() { + CSEMap.clear(); + } + private: /// IsLoopInvariantInst - Returns true if the instruction is loop /// invariant. I.e., all virtual register operands are defined outside of @@ -163,13 +174,13 @@ if (!CurLoop->contains(BB)) return; for (MachineBasicBlock::iterator - I = BB->begin(), E = BB->end(); I != E; ) { - MachineInstr &MI = *I++; + MII = BB->begin(), E = BB->end(); MII != E; ) { + MachineBasicBlock::iterator NextMII = MII; ++NextMII; + MachineInstr &MI = *MII; - // Try hoisting the instruction out of the loop. We can only do this if - // all of the operands of the instruction are loop invariant and if it is - // safe to hoist the instruction. Hoist(MI); + + MII = NextMII; } const std::vector &Children = N->getChildren(); @@ -258,17 +269,16 @@ return true; } -/// HasOnlyPHIUses - Return true if the only uses of Reg are PHIs. -static bool HasOnlyPHIUses(unsigned Reg, MachineRegisterInfo *RegInfo) { - bool OnlyPHIUse = false; + +/// HasPHIUses - Return true if the specified register has any PHI use. +static bool HasPHIUses(unsigned Reg, MachineRegisterInfo *RegInfo) { for (MachineRegisterInfo::use_iterator UI = RegInfo->use_begin(Reg), UE = RegInfo->use_end(); UI != UE; ++UI) { MachineInstr *UseMI = &*UI; - if (UseMI->getOpcode() != TargetInstrInfo::PHI) - return false; - OnlyPHIUse = true; + if (UseMI->getOpcode() == TargetInstrInfo::PHI) + return true; } - return OnlyPHIUse; + return false; } /// IsProfitableToHoist - Return true if it is potentially profitable to hoist @@ -283,21 +293,42 @@ !TII->isTriviallyReMaterializable(&MI))) return false; - if (!TID.isAsCheapAsAMove()) - return true; - - // If the instruction is "cheap" and the only uses of the register(s) defined - // by this MI are PHIs, then don't hoist it. Otherwise we just end up with a - // cheap instruction (e.g. constant) with long live interval feeeding into - // copies that are not always coalesced away. - bool OnlyPHIUses = false; + // If result(s) of this instruction is used by PHIs, then don't hoist it. + // The presence of joins makes it difficult for current register allocator + // implementation to perform remat. for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI.getOperand(i); if (!MO.isReg() || !MO.isDef()) continue; - OnlyPHIUses |= HasOnlyPHIUses(MO.getReg(), RegInfo); + if (HasPHIUses(MO.getReg(), RegInfo)) + return false; } - return !OnlyPHIUses; + + return true; +} + +static const MachineInstr *LookForDuplicate(const MachineInstr *MI, + std::vector &PrevMIs) { + unsigned NumOps = MI->getNumOperands(); + for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) { + const MachineInstr *PrevMI = PrevMIs[i]; + unsigned NumOps2 = PrevMI->getNumOperands(); + if (NumOps != NumOps2) + continue; + bool IsSame = true; + for (unsigned j = 0; j != NumOps; ++j) { + const MachineOperand &MO = MI->getOperand(j); + if (MO.isReg() && MO.isDef()) + continue; + if (!MO.isIdenticalTo(PrevMI->getOperand(j))) { + IsSame = false; + break; + } + } + if (IsSame) + return PrevMI; + } + return 0; } /// Hoist - When an instruction is found to use only loop invariant operands @@ -320,7 +351,41 @@ DOUT << "\n"; }); - CurPreheader->splice(CurPreheader->getFirstTerminator(), MI.getParent(), &MI); + // Look for opportunity to CSE the hoisted instruction. + std::pair BBOpcPair = + std::make_pair(CurPreheader->getNumber(), MI.getOpcode()); + DenseMap, + std::vector >::iterator CI = CSEMap.find(BBOpcPair); + bool DoneCSE = false; + if (CI != CSEMap.end()) { + const MachineInstr *Dup = LookForDuplicate(&MI, CI->second); + if (Dup) { + DOUT << "CSEing " << MI; + DOUT << " with " << *Dup; + for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI.getOperand(i); + if (MO.isReg() && MO.isDef()) + RegInfo->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg()); + } + MI.eraseFromParent(); + DoneCSE = true; + ++NumCSEed; + } + } + + // Otherwise, splice the instruction to the preheader. + if (!DoneCSE) { + CurPreheader->splice(CurPreheader->getFirstTerminator(), + MI.getParent(), &MI); + // Add to the CSE map. + if (CI != CSEMap.end()) + CI->second.push_back(&MI); + else { + std::vector CSEMIs; + CSEMIs.push_back(&MI); + CSEMap.insert(std::make_pair(BBOpcPair, CSEMIs)); + } + } ++NumHoisted; Changed = true; From evan.cheng at apple.com Thu Feb 5 02:46:34 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 05 Feb 2009 08:46:34 -0000 Subject: [llvm-commits] [llvm] r63855 - in /llvm/trunk: lib/CodeGen/LLVMTargetMachine.cpp test/CodeGen/ARM/remat.ll test/CodeGen/X86/pre-split2.ll Message-ID: <200902050846.n158kYUp005014@zion.cs.uiuc.edu> Author: evancheng Date: Thu Feb 5 02:46:33 2009 New Revision: 63855 URL: http://llvm.org/viewvc/llvm-project?rev=63855&view=rev Log: Turn on machine LICM in non-fast mode. Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp llvm/trunk/test/CodeGen/ARM/remat.ll llvm/trunk/test/CodeGen/X86/pre-split2.ll Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=63855&r1=63854&r2=63855&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Thu Feb 5 02:46:33 2009 @@ -42,10 +42,6 @@ static cl::opt EnableSinking("enable-sinking", cl::init(false), cl::Hidden, cl::desc("Perform sinking on machine code")); -static cl::opt -EnableLICM("machine-licm", - cl::init(false), cl::Hidden, - cl::desc("Perform loop-invariant code motion on machine code")); // When this works it will be on by default. static cl::opt @@ -187,7 +183,7 @@ if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (EnableLICM) + if (!Fast) PM.add(createMachineLICMPass()); if (EnableSinking) Modified: llvm/trunk/test/CodeGen/ARM/remat.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/remat.ll?rev=63855&r1=63854&r2=63855&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/remat.ll (original) +++ llvm/trunk/test/CodeGen/ARM/remat.ll Thu Feb 5 02:46:33 2009 @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -stats -info-output-file - | grep "Number of re-materialization" | grep 3 +; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -stats -info-output-file - | grep "Number of re-materialization" | grep 2 %struct.CONTENTBOX = type { i32, i32, i32, i32, i32 } %struct.LOCBOX = type { i32, i32, i32, i32 } Modified: llvm/trunk/test/CodeGen/X86/pre-split2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split2.ll?rev=63855&r1=63854&r2=63855&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/pre-split2.ll (original) +++ llvm/trunk/test/CodeGen/X86/pre-split2.ll Thu Feb 5 02:46:33 2009 @@ -1,7 +1,7 @@ ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \ -; RUN: grep {pre-alloc-split} | count 3 +; RUN: grep {pre-alloc-split} | count 2 -define i32 @t() { +define i32 @t(i32 %arg) { entry: br label %bb6 @@ -12,7 +12,7 @@ br label %bb6 bb6: ; preds = %.noexc6, %entry - %1 = uitofp i32 0 to double ; [#uses=1] + %1 = uitofp i32 %arg to double ; [#uses=1] %2 = sub i32 0, 0 ; [#uses=1] %3 = invoke i8* @_Znwm(i32 0) to label %.noexc6 unwind label %lpad32 ; [#uses=1] From evan.cheng at apple.com Thu Feb 5 02:51:13 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 05 Feb 2009 08:51:13 -0000 Subject: [llvm-commits] [llvm] r63856 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp Message-ID: <200902050851.n158pDMB007232@zion.cs.uiuc.edu> Author: evancheng Date: Thu Feb 5 02:51:13 2009 New Revision: 63856 URL: http://llvm.org/viewvc/llvm-project?rev=63856&view=rev Log: Machine LICM increases register pressure and it almost always increase code size. For now, disable it for optimizing for size. Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=63856&r1=63855&r2=63856&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Thu Feb 5 02:51:13 2009 @@ -126,6 +126,10 @@ /// loop. /// bool MachineLICM::runOnMachineFunction(MachineFunction &MF) { + const Function *F = MF.getFunction(); + if (F->hasFnAttr(Attribute::OptimizeForSize)) + return false; + DOUT << "******** Machine LICM ********\n"; Changed = false; From evan.cheng at apple.com Thu Feb 5 03:04:16 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 05 Feb 2009 09:04:16 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63857 - in /llvm-gcc-4.2/branches/Apple/Dib/gcc: cgraphunit.c ipa-inline.c passes.c tree-pass.h Message-ID: <200902050904.n1594GsA010132@zion.cs.uiuc.edu> Author: evancheng Date: Thu Feb 5 03:04:15 2009 New Revision: 63857 URL: http://llvm.org/viewvc/llvm-project?rev=63857&view=rev Log: Restore gcc inliner in teh Dib branch for now. It's exposing some performance issues. Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/cgraphunit.c llvm-gcc-4.2/branches/Apple/Dib/gcc/ipa-inline.c llvm-gcc-4.2/branches/Apple/Dib/gcc/passes.c llvm-gcc-4.2/branches/Apple/Dib/gcc/tree-pass.h Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/cgraphunit.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/cgraphunit.c?rev=63857&r1=63856&r2=63857&view=diff ============================================================================== --- llvm-gcc-4.2/branches/Apple/Dib/gcc/cgraphunit.c (original) +++ llvm-gcc-4.2/branches/Apple/Dib/gcc/cgraphunit.c Thu Feb 5 03:04:15 2009 @@ -1600,8 +1600,6 @@ return false; } -/* LLVM LOCAL begin */ -#ifndef ENABLE_LLVM static void ipa_passes (void) { @@ -1611,8 +1609,6 @@ execute_ipa_pass_list (all_ipa_passes); bitmap_obstack_release (NULL); } -#endif -/* LLVM LOCAL end */ /* Perform simple optimizations based on callgraph. */ @@ -1650,13 +1646,9 @@ dump_cgraph (cgraph_dump_file); } - /* LLVM LOCAL begin */ -#ifndef ENABLE_LLVM /* Don't run the IPA passes if there was any error or sorry messages. */ if (errorcount == 0 && sorrycount == 0) ipa_passes (); -#endif - /* LLVM LOCAL end */ /* This pass remove bodies of extern inline functions we never inlined. Do this later so other IPA passes see what is really going on. */ Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/ipa-inline.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/ipa-inline.c?rev=63857&r1=63856&r2=63857&view=diff ============================================================================== --- llvm-gcc-4.2/branches/Apple/Dib/gcc/ipa-inline.c (original) +++ llvm-gcc-4.2/branches/Apple/Dib/gcc/ipa-inline.c Thu Feb 5 03:04:15 2009 @@ -942,7 +942,11 @@ /* At the moment, no IPA passes change function bodies before inlining. Save some time by not recomputing function body sizes if early inlining already did so. */ + /* LLVM local begin - Don't rely on pass_early_ipa_inline being run. */ +#ifndef ENABLE_LLVM if (!flag_early_inlining) +#endif + /* LLVM local end */ node->local.self_insns = node->global.insns = estimate_num_insns (node->decl); @@ -1029,9 +1033,19 @@ overall_insns - old_insns); } + /* LLVM local begin */ +#ifdef ENABLE_LLVM + if (1) /* FIXME: 1 should be 0 some day, see PR2353. */ +#endif + /* LLVM local end*/ if (!flag_really_no_inline) cgraph_decide_inlining_of_small_functions (); + /* LLVM local begin */ +#ifdef ENABLE_LLVM + if (1) /* FIXME: 1 should be 0 some day, see PR2353. */ +#endif + /* LLVM local end*/ if (!flag_really_no_inline && flag_inline_functions_called_once) { @@ -1150,6 +1164,11 @@ } /* Now do the automatic inlining. */ + /* LLVM local begin */ +#ifdef ENABLE_LLVM + if (1) /* FIXME: 1 should be 0 some day, see PR2353. */ +#endif + /* LLVM local end */ if (!flag_really_no_inline) for (e = node->callees; e; e = e->next_callee) if (e->callee->local.inlinable Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/passes.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/passes.c?rev=63857&r1=63856&r2=63857&view=diff ============================================================================== --- llvm-gcc-4.2/branches/Apple/Dib/gcc/passes.c (original) +++ llvm-gcc-4.2/branches/Apple/Dib/gcc/passes.c Thu Feb 5 03:04:15 2009 @@ -333,11 +333,10 @@ /* The root of the compilation pass tree, once constructed. */ +struct tree_opt_pass *all_passes, *all_ipa_passes, *all_lowering_passes; /* LLVM LOCAL begin */ #ifdef ENABLE_LLVM -struct tree_opt_pass *all_lowering_passes, *all_extra_lowering_passes; -#else -struct tree_opt_pass *all_passes, *all_ipa_passes, *all_lowering_passes; +struct tree_opt_pass *all_extra_lowering_passes; #endif /* LLVM LOCAL end */ @@ -480,21 +479,23 @@ struct tree_opt_pass **p; #define NEXT_PASS(PASS) (p = next_pass_1 (p, &PASS)) - /* LLVM LOCAL begin */ -#ifndef ENABLE_LLVM /* Interprocedural optimization passes. */ p = &all_ipa_passes; + /* LLVM local begin */ +#ifndef ENABLE_LLVM NEXT_PASS (pass_early_ipa_inline); NEXT_PASS (pass_early_local_passes); NEXT_PASS (pass_ipa_cp); - NEXT_PASS (pass_ipa_inline); +#endif + NEXT_PASS (pass_ipa_inline); /* LLVM: inline functions marked always_inline */ +#ifndef ENABLE_LLVM NEXT_PASS (pass_ipa_reference); NEXT_PASS (pass_ipa_pure_const); NEXT_PASS (pass_ipa_type_escape); NEXT_PASS (pass_ipa_pta); - *p = NULL; #endif - /* LLVM LOCAL end */ + /* LLVM local end */ + *p = NULL; /* All passes needed to lower the function into shape optimizers can operate on. */ @@ -764,18 +765,14 @@ NEXT_PASS (pass_final); *p = NULL; #endif - /* LLVM LOCAL end */ + /* LLVM local end */ #undef NEXT_PASS /* Register the passes with the tree dump code. */ - /* LLVM LOCAL begin */ -#ifndef ENABLE_LLVM register_dump_files (all_ipa_passes, true, PROP_gimple_any | PROP_gimple_lcf | PROP_gimple_leh | PROP_cfg); -#endif - /* LLVM LOCAL end */ register_dump_files (all_lowering_passes, false, PROP_gimple_any); /* LLVM LOCAL begin */ #ifdef ENABLE_LLVM @@ -853,7 +850,6 @@ dump_file, dump_flags); else { -/* LLVM LOCAL begin */ #ifndef ENABLE_LLVM if (dump_flags & TDF_SLIM) print_rtl_slim_with_bb (dump_file, get_insns (), dump_flags); @@ -862,7 +858,6 @@ else print_rtl (dump_file, get_insns ()); #endif -/* LLVM LOCAL end */ if (curr_properties & PROP_cfg && graph_dump_format != no_graph && (dump_flags & TDF_GRAPH)) Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/tree-pass.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/tree-pass.h?rev=63857&r1=63856&r2=63857&view=diff ============================================================================== --- llvm-gcc-4.2/branches/Apple/Dib/gcc/tree-pass.h (original) +++ llvm-gcc-4.2/branches/Apple/Dib/gcc/tree-pass.h Thu Feb 5 03:04:15 2009 @@ -399,11 +399,10 @@ extern struct tree_opt_pass pass_rtl_seqabstr; /* The root of the compilation pass tree, once constructed. */ +extern struct tree_opt_pass *all_passes, *all_ipa_passes, *all_lowering_passes; /* LLVM LOCAL begin */ #ifdef ENABLE_LLVM -extern struct tree_opt_pass *all_lowering_passes, *all_extra_lowering_passes; -#else -extern struct tree_opt_pass *all_passes, *all_ipa_passes, *all_lowering_passes; +extern struct tree_opt_pass *all_extra_lowering_passes; #endif /* LLVM LOCAL end */ From baldrick at free.fr Thu Feb 5 03:54:03 2009 From: baldrick at free.fr (Duncan Sands) Date: Thu, 05 Feb 2009 09:54:03 -0000 Subject: [llvm-commits] [llvm] r63860 - /llvm/trunk/tools/gold/Makefile Message-ID: <200902050954.n159s3Xh014672@zion.cs.uiuc.edu> Author: baldrick Date: Thu Feb 5 03:54:02 2009 New Revision: 63860 URL: http://llvm.org/viewvc/llvm-project?rev=63860&view=rev Log: Stop llvm-config thinking that there are circular dependencies between libraries due to __dso_handle when doing "make install". I don't know what the LINK_COMPONENTS stuff is about, so I left it alone. Modified: llvm/trunk/tools/gold/Makefile Modified: llvm/trunk/tools/gold/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/Makefile?rev=63860&r1=63859&r2=63860&view=diff ============================================================================== --- llvm/trunk/tools/gold/Makefile (original) +++ llvm/trunk/tools/gold/Makefile Thu Feb 5 03:54:02 2009 @@ -15,11 +15,7 @@ # early so we can set up LINK_COMPONENTS before including Makefile.rules include $(LEVEL)/Makefile.config -LINK_LIBS_IN_SHARED=1 -SHARED_LIBRARY = 1 -BUILD_ARCHIVE = 0 -DONT_BUILD_RELINKED = 1 - +LOADABLE_MODULE = 1 LINK_COMPONENTS := include $(LEVEL)/Makefile.common From baldrick at free.fr Thu Feb 5 04:21:43 2009 From: baldrick at free.fr (Duncan Sands) Date: Thu, 05 Feb 2009 10:21:43 -0000 Subject: [llvm-commits] [llvm] r63861 - /llvm/trunk/tools/gold/Makefile Message-ID: <200902051021.n15ALhTq016092@zion.cs.uiuc.edu> Author: baldrick Date: Thu Feb 5 04:21:34 2009 New Revision: 63861 URL: http://llvm.org/viewvc/llvm-project?rev=63861&view=rev Log: Revert the previous commit. It seems it didn't really solve the problem. Also it changed the name from libLLVMgold to LLVMgold (correcting the name resulted in the original problem suddenly reappearing). Modified: llvm/trunk/tools/gold/Makefile Modified: llvm/trunk/tools/gold/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/Makefile?rev=63861&r1=63860&r2=63861&view=diff ============================================================================== --- llvm/trunk/tools/gold/Makefile (original) +++ llvm/trunk/tools/gold/Makefile Thu Feb 5 04:21:34 2009 @@ -15,7 +15,11 @@ # early so we can set up LINK_COMPONENTS before including Makefile.rules include $(LEVEL)/Makefile.config -LOADABLE_MODULE = 1 +LINK_LIBS_IN_SHARED=1 +SHARED_LIBRARY = 1 +BUILD_ARCHIVE = 0 +DONT_BUILD_RELINKED = 1 + LINK_COMPONENTS := include $(LEVEL)/Makefile.common From rafael.espindola at gmail.com Thu Feb 5 05:42:33 2009 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 05 Feb 2009 11:42:33 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63865 - /llvm-gcc-4.2/trunk/gcc/gcc.c Message-ID: <200902051142.n15BgYhA018748@zion.cs.uiuc.edu> Author: rafael Date: Thu Feb 5 05:42:24 2009 New Revision: 63865 URL: http://llvm.org/viewvc/llvm-project?rev=63865&view=rev Log: Don't pass -emit-llvm to the plugin. Gold confuses it with -e mit-llvm. This fixes gcc -emit-llvm -use-gold-plugin t.c -o t Modified: llvm-gcc-4.2/trunk/gcc/gcc.c Modified: llvm-gcc-4.2/trunk/gcc/gcc.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gcc.c?rev=63865&r1=63864&r2=63865&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/gcc.c (original) +++ llvm-gcc-4.2/trunk/gcc/gcc.c Thu Feb 5 05:42:24 2009 @@ -713,12 +713,13 @@ scripts which exist in user specified directories, or in standard directories. */ /* APPLE LOCAL begin add fcreate-profile */ -/* LLVM LOCAL begin add use-gold-plugin */ +/* LLVM LOCAL begin add use-gold-plugin, remove emit-llvm */ #ifndef LINK_COMMAND_SPEC #define LINK_COMMAND_SPEC "\ %{!fsyntax-only:%{!c:%{!M:%{!MM:%{!E:%{!S:\ %(linker) %{use-gold-plugin: -plugin %(gold_plugin_file)} \ - %l " LINK_PIE_SPEC "%X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r}\ + %l " LINK_PIE_SPEC "%X %{o*} %{A} %{d} % Author: lattner Date: Thu Feb 5 11:58:39 2009 New Revision: 63870 URL: http://llvm.org/viewvc/llvm-project?rev=63870&view=rev Log: fix PR3488: llvm-ar r doesn't replace existing files Patch by Daniel Shelton! Modified: llvm/trunk/tools/llvm-ar/llvm-ar.cpp Modified: llvm/trunk/tools/llvm-ar/llvm-ar.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-ar/llvm-ar.cpp?rev=63870&r1=63869&r2=63870&view=diff ============================================================================== --- llvm/trunk/tools/llvm-ar/llvm-ar.cpp (original) +++ llvm/trunk/tools/llvm-ar/llvm-ar.cpp Thu Feb 5 11:58:39 2009 @@ -638,7 +638,7 @@ const sys::FileStatus *si = PwS.getFileStatus(false, &Err); if (!si) return true; - if (si->isDir) { + if (!si->isDir) { if (OnlyUpdate) { // Replace the item only if it is newer. if (si->modTime > I->getModTime()) From sabre at nondot.org Thu Feb 5 12:14:58 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Feb 2009 18:14:58 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63873 - in /llvm-gcc-4.2/trunk/gcc: c-common.h c-typeck.c objc/objc-act.c stub-objc.c Message-ID: <200902051814.n15IExue032023@zion.cs.uiuc.edu> Author: lattner Date: Thu Feb 5 12:14:58 2009 New Revision: 63873 URL: http://llvm.org/viewvc/llvm-project?rev=63873&view=rev Log: Fix rdar://6551276, a bogus warning being emitted because volatile is being propagated without the matching 'objc_volatilized' attribute, used by the objc front-end with @try. Testcase here: llvm/test/FrontendObjC/2009-02-05-VolatileProp.m Modified: llvm-gcc-4.2/trunk/gcc/c-common.h llvm-gcc-4.2/trunk/gcc/c-typeck.c llvm-gcc-4.2/trunk/gcc/objc/objc-act.c llvm-gcc-4.2/trunk/gcc/stub-objc.c Modified: llvm-gcc-4.2/trunk/gcc/c-common.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/c-common.h?rev=63873&r1=63872&r2=63873&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/c-common.h (original) +++ llvm-gcc-4.2/trunk/gcc/c-common.h Thu Feb 5 12:14:58 2009 @@ -993,6 +993,8 @@ /* APPLE LOCAL radar 4507230 */ bool objc_type_valid_for_messaging (tree); extern void objc_volatilize_decl (tree); +/* LLVM LOCAL rdar 6551276 */ +extern tree objc_build_volatilized_type (tree); extern bool objc_type_quals_match (tree, tree); extern tree objc_rewrite_function_call (tree, tree); extern tree objc_message_selector (void); Modified: llvm-gcc-4.2/trunk/gcc/c-typeck.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/c-typeck.c?rev=63873&r1=63872&r2=63873&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/c-typeck.c (original) +++ llvm-gcc-4.2/trunk/gcc/c-typeck.c Thu Feb 5 12:14:58 2009 @@ -2081,6 +2081,13 @@ if (TREE_CODE (type) != ARRAY_TYPE && !objc_is_object_ptr (type)) /* APPLE LOCAL end radar 6164211 */ type = TYPE_MAIN_VARIANT (type); + + /* LLVM LOCAL begin propagate objc_volatilized: rdar://6551276 */ + if (lookup_attribute ("objc_volatilized", + TYPE_ATTRIBUTES (TREE_TYPE (TREE_TYPE (array))))) + type = objc_build_volatilized_type(type); + /* LLVM LOCAL end propagate objc_volatilized: rdar://6551276 */ + rval = build4 (ARRAY_REF, type, array, index, NULL_TREE, NULL_TREE); /* Array ref is const/volatile if the array elements are or if the array is. */ @@ -2097,6 +2104,7 @@ in an inline function. Hope it doesn't break something else. */ | TREE_THIS_VOLATILE (array)); + return require_complete_type (fold (rval)); } else Modified: llvm-gcc-4.2/trunk/gcc/objc/objc-act.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/objc/objc-act.c?rev=63873&r1=63872&r2=63873&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/objc/objc-act.c (original) +++ llvm-gcc-4.2/trunk/gcc/objc/objc-act.c Thu Feb 5 12:14:58 2009 @@ -3452,7 +3452,8 @@ /* Build a type differing from TYPE only in that TYPE_VOLATILE is set. Unlike tree.c:build_qualified_type(), preserve TYPE_LANG_SPECIFIC in the process. */ -static tree +/* LLVM LOCAL rdar 6551276 */ +tree objc_build_volatilized_type (tree type) { tree t; Modified: llvm-gcc-4.2/trunk/gcc/stub-objc.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/stub-objc.c?rev=63873&r1=63872&r2=63873&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/stub-objc.c (original) +++ llvm-gcc-4.2/trunk/gcc/stub-objc.c Thu Feb 5 12:14:58 2009 @@ -79,6 +79,14 @@ } /* APPLE LOCAL end radar 4330422 */ +/* LLVM LOCAL begin radar 6551276 */ +tree +objc_build_volatilized_type (tree type) +{ + return type; +} +/* LLVM LOCAL end radar 6551276 */ + /* APPLE LOCAL begin radar 4697411 */ void objc_volatilize_component_ref (tree ARG_UNUSED (cref), tree ARG_UNUSED (type)) From sabre at nondot.org Thu Feb 5 12:15:17 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Feb 2009 18:15:17 -0000 Subject: [llvm-commits] [llvm] r63874 - /llvm/trunk/test/FrontendObjC/2009-02-05-VolatileProp.m Message-ID: <200902051815.n15IFHtZ032040@zion.cs.uiuc.edu> Author: lattner Date: Thu Feb 5 12:15:17 2009 New Revision: 63874 URL: http://llvm.org/viewvc/llvm-project?rev=63874&view=rev Log: testcase for rdar://6551276 and llvm-gcc r63873 Added: llvm/trunk/test/FrontendObjC/2009-02-05-VolatileProp.m Added: llvm/trunk/test/FrontendObjC/2009-02-05-VolatileProp.m URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendObjC/2009-02-05-VolatileProp.m?rev=63874&view=auto ============================================================================== --- llvm/trunk/test/FrontendObjC/2009-02-05-VolatileProp.m (added) +++ llvm/trunk/test/FrontendObjC/2009-02-05-VolatileProp.m Thu Feb 5 12:15:17 2009 @@ -0,0 +1,11 @@ +/* RUN: %llvmgcc -w -x objective-c -c %s -o /dev/null -pedantic-errors + rdar://6551276 */ + +void foo(const unsigned short *); +void bar() { + unsigned short *s[3]; + int i; + @try { } @catch (id anException) { } + foo(2+s[i]); +} + From mrs at apple.com Thu Feb 5 12:59:33 2009 From: mrs at apple.com (Mike Stump) Date: Thu, 5 Feb 2009 10:59:33 -0800 Subject: [llvm-commits] [llvm] r63623 - in /llvm/trunk/tools: Makefile gold/ gold/Makefile gold/README.txt gold/gold-plugin.cpp In-Reply-To: <38a0d8450902050035k3ecdd83btccd94fed99f73b79@mail.gmail.com> References: <200902030713.n137DP9o009780@zion.cs.uiuc.edu> <1A3250C2-449A-466A-B616-49AC4D036D9C@apple.com> <498A6456.6070305@mxc.ca> <200902050924.38914.baldrick@free.fr> <38a0d8450902050035k3ecdd83btccd94fed99f73b79@mail.gmail.com> Message-ID: <04843970-84F5-43D2-B1E7-0AEA7A60B475@apple.com> On Feb 5, 2009, at 12:35 AM, Rafael Espindola wrote: >> I would like llvm-gcc to do the right thing when passed bitcode >> files, >> regardless of the optimization level. > > You need a linker plugin in the general case for that to work. Right > now it should work if you pass -use-gold-plugin. I am wondering what > is the best way to add a configure option to always look for the > plugin at run time. In gcc, --enable-gold. Then, that turns on code that passes -use-gold- plugin on down (or sets the variable). From dpatel at apple.com Thu Feb 5 13:15:39 2009 From: dpatel at apple.com (Devang Patel) Date: Thu, 05 Feb 2009 19:15:39 -0000 Subject: [llvm-commits] [llvm] r63876 - in /llvm/trunk: include/llvm/Transforms/Utils/Local.h lib/Transforms/Scalar/CondPropagate.cpp lib/Transforms/Utils/Local.cpp lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/CondProp/basictest-dbg.ll Message-ID: <200902051915.n15JFdfw001763@zion.cs.uiuc.edu> Author: dpatel Date: Thu Feb 5 13:15:39 2009 New Revision: 63876 URL: http://llvm.org/viewvc/llvm-project?rev=63876&view=rev Log: Ignore dbg intrinsics while propagating conditional expression info. Added: llvm/trunk/test/Transforms/CondProp/basictest-dbg.ll Modified: llvm/trunk/include/llvm/Transforms/Utils/Local.h llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp llvm/trunk/lib/Transforms/Utils/Local.cpp llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/include/llvm/Transforms/Utils/Local.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/Local.h?rev=63876&r1=63875&r2=63876&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/Utils/Local.h (original) +++ llvm/trunk/include/llvm/Transforms/Utils/Local.h Thu Feb 5 13:15:39 2009 @@ -40,6 +40,14 @@ bool ConstantFoldTerminator(BasicBlock *BB); //===----------------------------------------------------------------------===// +// CFG Simplification +// + +/// isTerminatorFirstRelevantInsn - Return true if Term is very first +/// instruction ignoring Phi nodes and dbg intrinsics. +bool isTerminatorFirstRelevantInsn(BasicBlock *BB, Instruction *Term); + +//===----------------------------------------------------------------------===// // Local dead code elimination. // Modified: llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp?rev=63876&r1=63875&r2=63876&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp Thu Feb 5 13:15:39 2009 @@ -137,7 +137,7 @@ if (!PN->hasOneUse()) return; BasicBlock *BB = BI->getParent(); - if (&*BB->begin() != PN || &*next(BB->begin()) != BI) + if (!isTerminatorFirstRelevantInsn (BB, BI)) return; // Ok, we have this really simple case, walk the PHI operands, looking for @@ -171,7 +171,7 @@ if (!PN->hasOneUse()) return; BasicBlock *BB = SI->getParent(); - if (&*BB->begin() != PN || &*next(BB->begin()) != SI) + if (!isTerminatorFirstRelevantInsn (BB, SI)) return; bool RemovedPreds = false; Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=63876&r1=63875&r2=63876&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Thu Feb 5 13:15:39 2009 @@ -148,6 +148,23 @@ return false; } +//===----------------------------------------------------------------------===// +// CFG Simplification +// + +/// isTerminatorFirstRelevantInsn - Return true if Term is very first +/// instruction ignoring Phi nodes and dbg intrinsics. +bool llvm::isTerminatorFirstRelevantInsn(BasicBlock *BB, Instruction *Term) { + BasicBlock::iterator BBI = Term; + while (BBI != BB->begin()) { + --BBI; + if (!isa(BBI)) + break; + } + if (isa(BBI) || &*BBI == Term) + return true; + return false; +} //===----------------------------------------------------------------------===// // Local dead code elimination... Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=63876&r1=63875&r2=63876&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Thu Feb 5 13:15:39 2009 @@ -1330,20 +1330,6 @@ return true; } -/// isTerminatorFirstRelevantInsn - Return true if Term is very first -/// instruction ignoring Phi nodes and dbg intrinsics. -static bool isTerminatorFirstRelevantInsn(BasicBlock *BB, Instruction *Term) { - BasicBlock::iterator BBI = Term; - while (BBI != BB->begin()) { - --BBI; - if (!isa(BBI)) - break; - } - if (isa(BBI) || &*BBI == Term) - return true; - return false; -} - /// SimplifyCondBranchToTwoReturns - If we found a conditional branch that goes /// to two returning blocks, try to merge them together into one return, /// introducing a select if the return values disagree. Added: llvm/trunk/test/Transforms/CondProp/basictest-dbg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/CondProp/basictest-dbg.ll?rev=63876&view=auto ============================================================================== --- llvm/trunk/test/Transforms/CondProp/basictest-dbg.ll (added) +++ llvm/trunk/test/Transforms/CondProp/basictest-dbg.ll Thu Feb 5 13:15:39 2009 @@ -0,0 +1,45 @@ +; RUN: llvm-as < %s | opt -condprop | llvm-dis | \ +; RUN: not grep {br label} + + %llvm.dbg.anchor.type = type { i32, i32 } + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } + + at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata" ; + + at .str = internal constant [4 x i8] c"a.c\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at .str1 = internal constant [6 x i8] c"/tmp/\00", section "llvm.metadata" ; <[6 x i8]*> [#uses=1] + at .str2 = internal constant [55 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build 00)\00", section "llvm.metadata" ; <[55 x i8]*> [#uses=1] + at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([6 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([55 x i8]* @.str2, i32 0, i32 0), i1 true, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] + +declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind + + +define i32 @test(i1 %C) { + br i1 %C, label %T1, label %F1 + +T1: ; preds = %0 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br label %Cont + +F1: ; preds = %0 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br label %Cont + +Cont: ; preds = %F1, %T1 + %C2 = phi i1 [ false, %F1 ], [ true, %T1 ] ; [#uses=1] +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 %C2, label %T2, label %F2 + +T2: ; preds = %Cont +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + call void @bar( ) +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + ret i32 17 + +F2: ; preds = %Cont +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + ret i32 1 +} + +declare void @bar() + From dpatel at apple.com Thu Feb 5 13:59:42 2009 From: dpatel at apple.com (Devang Patel) Date: Thu, 05 Feb 2009 19:59:42 -0000 Subject: [llvm-commits] [llvm] r63880 - in /llvm/trunk: lib/Transforms/Scalar/CondPropagate.cpp test/Transforms/CondProp/basictest.ll Message-ID: <200902051959.n15JxguB003253@zion.cs.uiuc.edu> Author: dpatel Date: Thu Feb 5 13:59:42 2009 New Revision: 63880 URL: http://llvm.org/viewvc/llvm-project?rev=63880&view=rev Log: Remove dead blocks in the end. Modified: llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp llvm/trunk/test/Transforms/CondProp/basictest.ll Modified: llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp?rev=63880&r1=63879&r2=63880&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp Thu Feb 5 13:59:42 2009 @@ -23,6 +23,7 @@ #include "llvm/Transforms/Utils/Local.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/Statistic.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Streams.h" using namespace llvm; @@ -44,6 +45,7 @@ private: bool MadeChange; + SmallVector DeadBlocks; void SimplifyBlock(BasicBlock *BB); void SimplifyPredecessors(BranchInst *BI); void SimplifyPredecessors(SwitchInst *SI); @@ -60,14 +62,22 @@ bool CondProp::runOnFunction(Function &F) { bool EverMadeChange = false; + DeadBlocks.clear(); // While we are simplifying blocks, keep iterating. do { MadeChange = false; - for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) - SimplifyBlock(BB); + for (Function::iterator BB = F.begin(), E = F.end(); BB != E;) + SimplifyBlock(BB++); EverMadeChange = EverMadeChange || MadeChange; } while (MadeChange); + + if (EverMadeChange) { + while (!DeadBlocks.empty()) { + BasicBlock *BB = DeadBlocks.back(); DeadBlocks.pop_back(); + DeleteDeadBlock(BB); + } + } return EverMadeChange; } @@ -111,8 +121,9 @@ // Succ is now dead, but we cannot delete it without potentially // invalidating iterators elsewhere. Just insert an unreachable - // instruction in it. + // instruction in it and delete this block later on. new UnreachableInst(Succ); + DeadBlocks.push_back(Succ); MadeChange = true; } } Modified: llvm/trunk/test/Transforms/CondProp/basictest.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/CondProp/basictest.ll?rev=63880&r1=63879&r2=63880&view=diff ============================================================================== --- llvm/trunk/test/Transforms/CondProp/basictest.ll (original) +++ llvm/trunk/test/Transforms/CondProp/basictest.ll Thu Feb 5 13:59:42 2009 @@ -1,5 +1,6 @@ ; RUN: llvm-as < %s | opt -condprop | llvm-dis | \ ; RUN: not grep {br label} +; RUN: llvm-as < %s | opt -condprop | llvm-dis | not grep T2 define i32 @test(i1 %C) { From natebegeman at mac.com Thu Feb 5 14:41:09 2009 From: natebegeman at mac.com (Nate Begeman) Date: Thu, 05 Feb 2009 12:41:09 -0800 Subject: [llvm-commits] [llvm] r63772 - /llvm/trunk/test/Assembler/2007-04-15-BadIntrinsic.ll In-Reply-To: <200902050919.00634.baldrick@free.fr> References: <200902042107.n14L7cV6018098@zion.cs.uiuc.edu> <200902050919.00634.baldrick@free.fr> Message-ID: <0F7B44B8-87BF-4C03-B6CC-A6DFF9B73935@mac.com> On Feb 5, 2009, at 12:19 AM, Duncan Sands wrote: > Hi Nate, > >> Remove now-incorrect test. > > why is it incorrect? Because functions unknown to VMCore may begin with the llvm. prefix. Nate From mrs at apple.com Thu Feb 5 14:45:27 2009 From: mrs at apple.com (Mike Stump) Date: Thu, 05 Feb 2009 20:45:27 -0000 Subject: [llvm-commits] [llvm] r63882 - /llvm/trunk/utils/unittest/googletest/Makefile Message-ID: <200902052045.n15KjRfM004837@zion.cs.uiuc.edu> Author: mrs Date: Thu Feb 5 14:45:27 2009 New Revision: 63882 URL: http://llvm.org/viewvc/llvm-project?rev=63882&view=rev Log: Probe for flags before using them to try to help compiling with compilers that don't support those flags. This hopefully will help gcc 3.X compile this code. http://llvm.org/PR3487 Modified: llvm/trunk/utils/unittest/googletest/Makefile Modified: llvm/trunk/utils/unittest/googletest/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/Makefile?rev=63882&r1=63881&r2=63882&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/Makefile (original) +++ llvm/trunk/utils/unittest/googletest/Makefile Thu Feb 5 14:45:27 2009 @@ -9,10 +9,13 @@ LEVEL := ../../.. include $(LEVEL)/Makefile.config +NO_MISSING_FIELD_INITIALIZERS := $(shell $(CXX) -Wno-missing-field-initializers -fsyntax-only -xc /dev/null 2>/dev/null && echo -Wno-missing-field-initializers) +NO_VAROADIC_MACROS := $(shell $(CXX) -Wno-variadic-macros -fsyntax-only -xc /dev/null 2>/dev/null && echo -Wno-variadic-macros) + LIBRARYNAME = GoogleTest BUILD_ARCHIVE = 1 CPP.Flags += -I$(LLVM_SRC_ROOT)/utils/unittest/googletest/include/ -CPP.Flags += -Wno-missing-field-initializers -Wno-variadic-macros +CPP.Flags += $(NO_MISSING_FIELD_INITIALIZERS) $(NO_VAROADIC_MACROS) include $(LEVEL)/Makefile.common From baldrick at free.fr Thu Feb 5 14:47:40 2009 From: baldrick at free.fr (Duncan Sands) Date: Thu, 5 Feb 2009 21:47:40 +0100 Subject: [llvm-commits] [llvm] r63772 - /llvm/trunk/test/Assembler/2007-04-15-BadIntrinsic.ll In-Reply-To: <0F7B44B8-87BF-4C03-B6CC-A6DFF9B73935@mac.com> References: <200902042107.n14L7cV6018098@zion.cs.uiuc.edu> <200902050919.00634.baldrick@free.fr> <0F7B44B8-87BF-4C03-B6CC-A6DFF9B73935@mac.com> Message-ID: <200902052147.40723.baldrick@free.fr> > > why is it incorrect? > > Because functions unknown to VMCore may begin with the llvm. prefix. Will it be caught later then? Ciao, Duncan. From mrs at apple.com Thu Feb 5 14:49:49 2009 From: mrs at apple.com (Mike Stump) Date: Thu, 05 Feb 2009 20:49:49 -0000 Subject: [llvm-commits] [llvm] r63883 - /llvm/trunk/utils/unittest/googletest/Makefile Message-ID: <200902052049.n15Knnqc004989@zion.cs.uiuc.edu> Author: mrs Date: Thu Feb 5 14:49:49 2009 New Revision: 63883 URL: http://llvm.org/viewvc/llvm-project?rev=63883&view=rev Log: FIx spelling. Modified: llvm/trunk/utils/unittest/googletest/Makefile Modified: llvm/trunk/utils/unittest/googletest/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/Makefile?rev=63883&r1=63882&r2=63883&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/Makefile (original) +++ llvm/trunk/utils/unittest/googletest/Makefile Thu Feb 5 14:49:49 2009 @@ -10,12 +10,12 @@ LEVEL := ../../.. include $(LEVEL)/Makefile.config NO_MISSING_FIELD_INITIALIZERS := $(shell $(CXX) -Wno-missing-field-initializers -fsyntax-only -xc /dev/null 2>/dev/null && echo -Wno-missing-field-initializers) -NO_VAROADIC_MACROS := $(shell $(CXX) -Wno-variadic-macros -fsyntax-only -xc /dev/null 2>/dev/null && echo -Wno-variadic-macros) +NO_VARIADIC_MACROS := $(shell $(CXX) -Wno-variadic-macros -fsyntax-only -xc /dev/null 2>/dev/null && echo -Wno-variadic-macros) LIBRARYNAME = GoogleTest BUILD_ARCHIVE = 1 CPP.Flags += -I$(LLVM_SRC_ROOT)/utils/unittest/googletest/include/ -CPP.Flags += $(NO_MISSING_FIELD_INITIALIZERS) $(NO_VAROADIC_MACROS) +CPP.Flags += $(NO_MISSING_FIELD_INITIALIZERS) $(NO_VARIADIC_MACROS) include $(LEVEL)/Makefile.common From clattner at apple.com Thu Feb 5 14:50:56 2009 From: clattner at apple.com (Chris Lattner) Date: Thu, 5 Feb 2009 12:50:56 -0800 Subject: [llvm-commits] [llvm] r63883 - /llvm/trunk/utils/unittest/googletest/Makefile In-Reply-To: <200902052049.n15Knnqc004989@zion.cs.uiuc.edu> References: <200902052049.n15Knnqc004989@zion.cs.uiuc.edu> Message-ID: thanks Mike! On Feb 5, 2009, at 12:49 PM, Mike Stump wrote: > Author: mrs > Date: Thu Feb 5 14:49:49 2009 > New Revision: 63883 > > URL: http://llvm.org/viewvc/llvm-project?rev=63883&view=rev > Log: > FIx spelling. > > Modified: > llvm/trunk/utils/unittest/googletest/Makefile > > Modified: llvm/trunk/utils/unittest/googletest/Makefile > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/Makefile?rev=63883&r1=63882&r2=63883&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/unittest/googletest/Makefile (original) > +++ llvm/trunk/utils/unittest/googletest/Makefile Thu Feb 5 > 14:49:49 2009 > @@ -10,12 +10,12 @@ > LEVEL := ../../.. > include $(LEVEL)/Makefile.config > NO_MISSING_FIELD_INITIALIZERS := $(shell $(CXX) -Wno-missing-field- > initializers -fsyntax-only -xc /dev/null 2>/dev/null && echo -Wno- > missing-field-initializers) > -NO_VAROADIC_MACROS := $(shell $(CXX) -Wno-variadic-macros -fsyntax- > only -xc /dev/null 2>/dev/null && echo -Wno-variadic-macros) > +NO_VARIADIC_MACROS := $(shell $(CXX) -Wno-variadic-macros -fsyntax- > only -xc /dev/null 2>/dev/null && echo -Wno-variadic-macros) > > > LIBRARYNAME = GoogleTest > BUILD_ARCHIVE = 1 > CPP.Flags += -I$(LLVM_SRC_ROOT)/utils/unittest/googletest/include/ > -CPP.Flags += $(NO_MISSING_FIELD_INITIALIZERS) $(NO_VAROADIC_MACROS) > +CPP.Flags += $(NO_MISSING_FIELD_INITIALIZERS) $(NO_VARIADIC_MACROS) > > include $(LEVEL)/Makefile.common > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Thu Feb 5 14:52:28 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Feb 2009 20:52:28 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r63884 - in /llvm-gcc-4.2/branches/Apple/Dib/gcc: c-common.h c-typeck.c objc/objc-act.c stub-objc.c Message-ID: <200902052052.n15KqS3T005126@zion.cs.uiuc.edu> Author: void Date: Thu Feb 5 14:52:28 2009 New Revision: 63884 URL: http://llvm.org/viewvc/llvm-project?rev=63884&view=rev Log: Pull r63873 into Dib: Fix rdar://6551276, a bogus warning being emitted because volatile is being propagated without the matching 'objc_volatilized' attribute, used by the objc front-end with @try. Testcase here: llvm/test/FrontendObjC/2009-02-05-VolatileProp.m Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/c-common.h llvm-gcc-4.2/branches/Apple/Dib/gcc/c-typeck.c llvm-gcc-4.2/branches/Apple/Dib/gcc/objc/objc-act.c llvm-gcc-4.2/branches/Apple/Dib/gcc/stub-objc.c Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/c-common.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/c-common.h?rev=63884&r1=63883&r2=63884&view=diff ============================================================================== --- llvm-gcc-4.2/branches/Apple/Dib/gcc/c-common.h (original) +++ llvm-gcc-4.2/branches/Apple/Dib/gcc/c-common.h Thu Feb 5 14:52:28 2009 @@ -993,6 +993,8 @@ /* APPLE LOCAL radar 4507230 */ bool objc_type_valid_for_messaging (tree); extern void objc_volatilize_decl (tree); +/* LLVM LOCAL rdar 6551276 */ +extern tree objc_build_volatilized_type (tree); extern bool objc_type_quals_match (tree, tree); extern tree objc_rewrite_function_call (tree, tree); extern tree objc_message_selector (void); Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/c-typeck.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/c-typeck.c?rev=63884&r1=63883&r2=63884&view=diff ============================================================================== --- llvm-gcc-4.2/branches/Apple/Dib/gcc/c-typeck.c (original) +++ llvm-gcc-4.2/branches/Apple/Dib/gcc/c-typeck.c Thu Feb 5 14:52:28 2009 @@ -2081,6 +2081,13 @@ if (TREE_CODE (type) != ARRAY_TYPE && !objc_is_object_ptr (type)) /* APPLE LOCAL end radar 6164211 */ type = TYPE_MAIN_VARIANT (type); + + /* LLVM LOCAL begin propagate objc_volatilized: rdar://6551276 */ + if (lookup_attribute ("objc_volatilized", + TYPE_ATTRIBUTES (TREE_TYPE (TREE_TYPE (array))))) + type = objc_build_volatilized_type(type); + /* LLVM LOCAL end propagate objc_volatilized: rdar://6551276 */ + rval = build4 (ARRAY_REF, type, array, index, NULL_TREE, NULL_TREE); /* Array ref is const/volatile if the array elements are or if the array is. */ @@ -2097,6 +2104,7 @@ in an inline function. Hope it doesn't break something else. */ | TREE_THIS_VOLATILE (array)); + return require_complete_type (fold (rval)); } else Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/objc/objc-act.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/objc/objc-act.c?rev=63884&r1=63883&r2=63884&view=diff ============================================================================== --- llvm-gcc-4.2/branches/Apple/Dib/gcc/objc/objc-act.c (original) +++ llvm-gcc-4.2/branches/Apple/Dib/gcc/objc/objc-act.c Thu Feb 5 14:52:28 2009 @@ -3452,7 +3452,8 @@ /* Build a type differing from TYPE only in that TYPE_VOLATILE is set. Unlike tree.c:build_qualified_type(), preserve TYPE_LANG_SPECIFIC in the process. */ -static tree +/* LLVM LOCAL rdar 6551276 */ +tree objc_build_volatilized_type (tree type) { tree t; Modified: llvm-gcc-4.2/branches/Apple/Dib/gcc/stub-objc.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/gcc/stub-objc.c?rev=63884&r1=63883&r2=63884&view=diff ============================================================================== --- llvm-gcc-4.2/branches/Apple/Dib/gcc/stub-objc.c (original) +++ llvm-gcc-4.2/branches/Apple/Dib/gcc/stub-objc.c Thu Feb 5 14:52:28 2009 @@ -79,6 +79,14 @@ } /* APPLE LOCAL end radar 4330422 */ +/* LLVM LOCAL begin radar 6551276 */ +tree +objc_build_volatilized_type (tree type) +{ + return type; +} +/* LLVM LOCAL end radar 6551276 */ + /* APPLE LOCAL begin radar 4697411 */ void objc_volatilize_component_ref (tree ARG_UNUSED (cref), tree ARG_UNUSED (type)) From isanbard at gmail.com Thu Feb 5 14:53:54 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Feb 2009 20:53:54 -0000 Subject: [llvm-commits] [llvm] r63885 - /llvm/branches/Apple/Dib/test/FrontendObjC/2009-02-05-VolatileProp.m Message-ID: <200902052053.n15KrshX005192@zion.cs.uiuc.edu> Author: void Date: Thu Feb 5 14:53:54 2009 New Revision: 63885 URL: http://llvm.org/viewvc/llvm-project?rev=63885&view=rev Log: Add testcase for r63884. Added: llvm/branches/Apple/Dib/test/FrontendObjC/2009-02-05-VolatileProp.m Added: llvm/branches/Apple/Dib/test/FrontendObjC/2009-02-05-VolatileProp.m URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/FrontendObjC/2009-02-05-VolatileProp.m?rev=63885&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/FrontendObjC/2009-02-05-VolatileProp.m (added) +++ llvm/branches/Apple/Dib/test/FrontendObjC/2009-02-05-VolatileProp.m Thu Feb 5 14:53:54 2009 @@ -0,0 +1,11 @@ +/* RUN: %llvmgcc -w -x objective-c -c %s -o /dev/null -pedantic-errors + rdar://6551276 */ + +void foo(const unsigned short *); +void bar() { + unsigned short *s[3]; + int i; + @try { } @catch (id anException) { } + foo(2+s[i]); +} + From dalej at apple.com Thu Feb 5 15:20:45 2009 From: dalej at apple.com (Dale Johannesen) Date: Thu, 05 Feb 2009 21:20:45 -0000 Subject: [llvm-commits] [llvm] r63886 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200902052120.n15LKji7006382@zion.cs.uiuc.edu> Author: johannes Date: Thu Feb 5 15:20:44 2009 New Revision: 63886 URL: http://llvm.org/viewvc/llvm-project?rev=63886&view=rev Log: Remove 3 non-DebugLoc variants of getNode. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63886&r1=63885&r2=63886&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Thu Feb 5 15:20:44 2009 @@ -442,11 +442,8 @@ SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, const SDValue *Ops, unsigned NumOps); - SDValue getNode(unsigned Opcode, SDVTList VTs); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs); - SDValue getNode(unsigned Opcode, SDVTList VTs, SDValue N); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N); - SDValue getNode(unsigned Opcode, SDVTList VTs, SDValue N1, SDValue N2); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N1, SDValue N2); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63886&r1=63885&r2=63886&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Feb 5 15:20:44 2009 @@ -3896,30 +3896,16 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) { return getNode(Opcode, DL, VTList, 0, 0); } -SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, - SDValue N1) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1) { SDValue Ops[] = { N1 }; return getNode(Opcode, DL, VTList, Ops, 1); } -SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, - SDValue N1, SDValue N2) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2) { SDValue Ops[] = { N1, N2 }; From natebegeman at mac.com Thu Feb 5 15:22:30 2009 From: natebegeman at mac.com (Nate Begeman) Date: Thu, 05 Feb 2009 13:22:30 -0800 Subject: [llvm-commits] [llvm] r63772 - /llvm/trunk/test/Assembler/2007-04-15-BadIntrinsic.ll In-Reply-To: <200902052147.40723.baldrick@free.fr> References: <200902042107.n14L7cV6018098@zion.cs.uiuc.edu> <200902050919.00634.baldrick@free.fr> <0F7B44B8-87BF-4C03-B6CC-A6DFF9B73935@mac.com> <200902052147.40723.baldrick@free.fr> Message-ID: <19025F08-F0B5-41A9-B0CC-6A34A6B7542F@mac.com> On Feb 5, 2009, at 12:47 PM, Duncan Sands wrote: >>> why is it incorrect? >> >> Because functions unknown to VMCore may begin with the llvm. prefix. > > Will it be caught later then? It will not match as an intrinsic in CodeGen and turn into a libcall. An assert could presumably be added at that point. Nate From gohman at apple.com Thu Feb 5 15:34:56 2009 From: gohman at apple.com (Dan Gohman) Date: Thu, 05 Feb 2009 21:34:56 -0000 Subject: [llvm-commits] [llvm] r63887 - /llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Message-ID: <200902052134.n15LYuTr006876@zion.cs.uiuc.edu> Author: djg Date: Thu Feb 5 15:34:56 2009 New Revision: 63887 URL: http://llvm.org/viewvc/llvm-project?rev=63887&view=rev Log: Delete some trailing whiespaces. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=63887&r1=63886&r2=63887&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Feb 5 15:34:56 2009 @@ -1613,14 +1613,14 @@ const Value *srcValue, int SVOff, unsigned alignment, bool isvolatile); - MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, const SDValue *Ops, + MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, const SDValue *Ops, unsigned NumOps, MVT MemoryVT, const Value *srcValue, int SVOff, unsigned alignment, bool isvolatile); /// Returns alignment and volatility of the memory access unsigned getAlignment() const { return (1u << (SubclassData >> 6)) >> 1; } bool isVolatile() const { return (SubclassData >> 5) & 1; } - + /// getRawSubclassData - Return the SubclassData value, which contains an /// encoding of the alignment and volatile information, as well as bits /// used by subclasses. This function should only be used to compute a @@ -1632,10 +1632,10 @@ /// Returns the SrcValue and offset that describes the location of the access const Value *getSrcValue() const { return SrcValue; } int getSrcValueOffset() const { return SVOffset; } - + /// getMemoryVT - Return the type of the in-memory value. MVT getMemoryVT() const { return MemoryVT; } - + /// getMemOperand - Return a MachineMemOperand object describing the memory /// reference performed by operation. MachineMemOperand getMemOperand() const; @@ -1667,14 +1667,14 @@ N->getOpcode() == ISD::INTRINSIC_W_CHAIN || N->getOpcode() == ISD::INTRINSIC_VOID || N->isTargetOpcode(); - } + } }; /// AtomicSDNode - A SDNode reprenting atomic operations. /// class AtomicSDNode : public MemSDNode { SDUse Ops[4]; - + public: // Opc: opcode for atomic // VTL: value type list @@ -1693,7 +1693,7 @@ InitOperands(Ops, Chain, Ptr, Cmp, Swp); } AtomicSDNode(unsigned Opc, SDVTList VTL, MVT MemVT, - SDValue Chain, SDValue Ptr, + SDValue Chain, SDValue Ptr, SDValue Val, const Value* SrcVal, unsigned Align=0) : MemSDNode(Opc, VTL, MemVT, SrcVal, /*SVOffset=*/0, Align, /*isVolatile=*/true) { @@ -1708,18 +1708,18 @@ InitOperands(Ops, Chain, Ptr, Cmp, Swp); } AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, MVT MemVT, - SDValue Chain, SDValue Ptr, + SDValue Chain, SDValue Ptr, SDValue Val, const Value* SrcVal, unsigned Align=0) : MemSDNode(Opc, dl, VTL, MemVT, SrcVal, /*SVOffset=*/0, Align, /*isVolatile=*/true) { InitOperands(Ops, Chain, Ptr, Val); } - + const SDValue &getBasePtr() const { return getOperand(1); } const SDValue &getVal() const { return getOperand(2); } - bool isCompareAndSwap() const { - unsigned Op = getOpcode(); + bool isCompareAndSwap() const { + unsigned Op = getOpcode(); return Op == ISD::ATOMIC_CMP_SWAP; } @@ -2371,8 +2371,8 @@ assert((getOffset().getOpcode() == ISD::UNDEF || isIndexed()) && "Only indexed loads and stores have a non-undef offset operand"); } - LSBaseSDNode(ISD::NodeType NodeTy, DebugLoc dl, SDValue *Operands, - unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM, + LSBaseSDNode(ISD::NodeType NodeTy, DebugLoc dl, SDValue *Operands, + unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM, MVT VT, const Value *SV, int SVO, unsigned Align, bool Vol) : MemSDNode(NodeTy, dl, VTs, VT, SV, SVO, Align, Vol) { assert(Align != 0 && "Loads and stores should have non-zero aligment"); @@ -2437,7 +2437,7 @@ const SDValue &getBasePtr() const { return getOperand(1); } const SDValue &getOffset() const { return getOperand(2); } - + static bool classof(const LoadSDNode *) { return true; } static bool classof(const SDNode *N) { return N->getOpcode() == ISD::LOAD; @@ -2475,7 +2475,7 @@ const SDValue &getValue() const { return getOperand(1); } const SDValue &getBasePtr() const { return getOperand(2); } const SDValue &getOffset() const { return getOperand(3); } - + static bool classof(const StoreSDNode *) { return true; } static bool classof(const SDNode *N) { return N->getOpcode() == ISD::STORE; From dpatel at apple.com Thu Feb 5 15:46:42 2009 From: dpatel at apple.com (Devang Patel) Date: Thu, 05 Feb 2009 21:46:42 -0000 Subject: [llvm-commits] [llvm] r63888 - in /llvm/trunk: include/llvm/Transforms/Utils/Local.h lib/Transforms/Scalar/CondPropagate.cpp lib/Transforms/Utils/Local.cpp lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/CondProp/basictest-dbg.ll Message-ID: <200902052146.n15LkgqV007278@zion.cs.uiuc.edu> Author: dpatel Date: Thu Feb 5 15:46:41 2009 New Revision: 63888 URL: http://llvm.org/viewvc/llvm-project?rev=63888&view=rev Log: Revert rev. 63876. It is causing llvm-gcc bootstrap failure. Removed: llvm/trunk/test/Transforms/CondProp/basictest-dbg.ll Modified: llvm/trunk/include/llvm/Transforms/Utils/Local.h llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp llvm/trunk/lib/Transforms/Utils/Local.cpp llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/include/llvm/Transforms/Utils/Local.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/Local.h?rev=63888&r1=63887&r2=63888&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/Utils/Local.h (original) +++ llvm/trunk/include/llvm/Transforms/Utils/Local.h Thu Feb 5 15:46:41 2009 @@ -40,14 +40,6 @@ bool ConstantFoldTerminator(BasicBlock *BB); //===----------------------------------------------------------------------===// -// CFG Simplification -// - -/// isTerminatorFirstRelevantInsn - Return true if Term is very first -/// instruction ignoring Phi nodes and dbg intrinsics. -bool isTerminatorFirstRelevantInsn(BasicBlock *BB, Instruction *Term); - -//===----------------------------------------------------------------------===// // Local dead code elimination. // Modified: llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp?rev=63888&r1=63887&r2=63888&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp Thu Feb 5 15:46:41 2009 @@ -148,7 +148,7 @@ if (!PN->hasOneUse()) return; BasicBlock *BB = BI->getParent(); - if (!isTerminatorFirstRelevantInsn (BB, BI)) + if (&*BB->begin() != PN || &*next(BB->begin()) != BI) return; // Ok, we have this really simple case, walk the PHI operands, looking for @@ -182,7 +182,7 @@ if (!PN->hasOneUse()) return; BasicBlock *BB = SI->getParent(); - if (!isTerminatorFirstRelevantInsn (BB, SI)) + if (&*BB->begin() != PN || &*next(BB->begin()) != SI) return; bool RemovedPreds = false; Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=63888&r1=63887&r2=63888&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Thu Feb 5 15:46:41 2009 @@ -148,23 +148,6 @@ return false; } -//===----------------------------------------------------------------------===// -// CFG Simplification -// - -/// isTerminatorFirstRelevantInsn - Return true if Term is very first -/// instruction ignoring Phi nodes and dbg intrinsics. -bool llvm::isTerminatorFirstRelevantInsn(BasicBlock *BB, Instruction *Term) { - BasicBlock::iterator BBI = Term; - while (BBI != BB->begin()) { - --BBI; - if (!isa(BBI)) - break; - } - if (isa(BBI) || &*BBI == Term) - return true; - return false; -} //===----------------------------------------------------------------------===// // Local dead code elimination... Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=63888&r1=63887&r2=63888&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Thu Feb 5 15:46:41 2009 @@ -1330,6 +1330,20 @@ return true; } +/// isTerminatorFirstRelevantInsn - Return true if Term is very first +/// instruction ignoring Phi nodes and dbg intrinsics. +static bool isTerminatorFirstRelevantInsn(BasicBlock *BB, Instruction *Term) { + BasicBlock::iterator BBI = Term; + while (BBI != BB->begin()) { + --BBI; + if (!isa(BBI)) + break; + } + if (isa(BBI) || &*BBI == Term) + return true; + return false; +} + /// SimplifyCondBranchToTwoReturns - If we found a conditional branch that goes /// to two returning blocks, try to merge them together into one return, /// introducing a select if the return values disagree. Removed: llvm/trunk/test/Transforms/CondProp/basictest-dbg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/CondProp/basictest-dbg.ll?rev=63887&view=auto ============================================================================== --- llvm/trunk/test/Transforms/CondProp/basictest-dbg.ll (original) +++ llvm/trunk/test/Transforms/CondProp/basictest-dbg.ll (removed) @@ -1,45 +0,0 @@ -; RUN: llvm-as < %s | opt -condprop | llvm-dis | \ -; RUN: not grep {br label} - - %llvm.dbg.anchor.type = type { i32, i32 } - %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } - - at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata" ; - - at .str = internal constant [4 x i8] c"a.c\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] - at .str1 = internal constant [6 x i8] c"/tmp/\00", section "llvm.metadata" ; <[6 x i8]*> [#uses=1] - at .str2 = internal constant [55 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build 00)\00", section "llvm.metadata" ; <[55 x i8]*> [#uses=1] - at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([6 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([55 x i8]* @.str2, i32 0, i32 0), i1 true, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] - -declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind - - -define i32 @test(i1 %C) { - br i1 %C, label %T1, label %F1 - -T1: ; preds = %0 -call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) - br label %Cont - -F1: ; preds = %0 -call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) - br label %Cont - -Cont: ; preds = %F1, %T1 - %C2 = phi i1 [ false, %F1 ], [ true, %T1 ] ; [#uses=1] -call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) - br i1 %C2, label %T2, label %F2 - -T2: ; preds = %Cont -call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) - call void @bar( ) -call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) - ret i32 17 - -F2: ; preds = %Cont -call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) - ret i32 1 -} - -declare void @bar() - From dalej at apple.com Thu Feb 5 16:07:54 2009 From: dalej at apple.com (Dale Johannesen) Date: Thu, 05 Feb 2009 22:07:54 -0000 Subject: [llvm-commits] [llvm] r63889 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/PowerPC/PPCISelLowering.h lib/Target/Sparc/SparcISelLowering.cpp utils/TableGen/DAGISelEmitter.cpp Message-ID: <200902052207.n15M7s8G008085@zion.cs.uiuc.edu> Author: johannes Date: Thu Feb 5 16:07:54 2009 New Revision: 63889 URL: http://llvm.org/viewvc/llvm-project?rev=63889&view=rev Log: Remove a non-DebugLoc version of getNode. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63889&r1=63888&r2=63889&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Thu Feb 5 16:07:54 2009 @@ -428,8 +428,6 @@ const SDValue *Ops, unsigned NumOps); SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, const SDValue *Ops, unsigned NumOps); - SDValue getNode(unsigned Opcode, const std::vector &ResultTys, - const SDValue *Ops, unsigned NumOps); SDValue getNode(unsigned Opcode, DebugLoc DL, const std::vector &ResultTys, const SDValue *Ops, unsigned NumOps); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63889&r1=63888&r2=63889&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Feb 5 16:07:54 2009 @@ -3792,12 +3792,6 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getNode(unsigned Opcode, - const std::vector &ResultTys, - const SDValue *Ops, unsigned NumOps) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), ResultTys, Ops, NumOps); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, const std::vector &ResultTys, const SDValue *Ops, unsigned NumOps) { Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=63889&r1=63888&r2=63889&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Feb 5 16:07:54 2009 @@ -2856,10 +2856,10 @@ } // FIXME: Split this code up when LegalizeDAGTypes lands. -SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { +SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, + DebugLoc dl) { assert(Op.getOperand(0).getValueType().isFloatingPoint()); SDValue Src = Op.getOperand(0); - DebugLoc dl = Op.getNode()->getDebugLoc(); if (Src.getValueType() == MVT::f32) Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); @@ -3664,6 +3664,7 @@ SelectionDAG &DAG) { // If this is a lowered altivec predicate compare, CompareOpc is set to the // opcode number of the comparison. + DebugLoc dl = Op.getDebugLoc(); int CompareOpc; bool isDot; if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) @@ -3671,10 +3672,10 @@ // If this is a non-dot comparison, make the VCMP node and we are done. if (!isDot) { - SDValue Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), + SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), Op.getOperand(1), Op.getOperand(2), DAG.getConstant(CompareOpc, MVT::i32)); - return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); + return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp); } // Create the PPCISD altivec 'dot' comparison node. @@ -3686,11 +3687,11 @@ std::vector VTs; VTs.push_back(Op.getOperand(2).getValueType()); VTs.push_back(MVT::Flag); - SDValue CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); + SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); // Now that we have the comparison, emit a copy from the CR to a GPR. // This is flagged to the above dot comparison. - SDValue Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, + SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32, DAG.getRegister(PPC::CR6, MVT::i32), CompNode.getValue(1)); @@ -3714,15 +3715,15 @@ } // Shift the bit into the low position. - Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, + Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, DAG.getConstant(8-(3-BitNo), MVT::i32)); // Isolate the bit. - Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, + Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, DAG.getConstant(1, MVT::i32)); // If we are supposed to, toggle the bit. if (InvertBit) - Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, + Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, DAG.getConstant(1, MVT::i32)); return Flags; } @@ -3834,7 +3835,8 @@ return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); - case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); + case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, + Op.getDebugLoc()); case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); @@ -3860,6 +3862,7 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl&Results, SelectionDAG &DAG) { + DebugLoc dl = N->getDebugLoc(); switch (N->getOpcode()) { default: assert(false && "Do not know how to custom type legalize this operation!"); @@ -3867,9 +3870,11 @@ case ISD::FP_ROUND_INREG: { assert(N->getValueType(0) == MVT::ppcf128); assert(N->getOperand(0).getValueType() == MVT::ppcf128); - SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::f64, N->getOperand(0), + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, + MVT::f64, N->getOperand(0), DAG.getIntPtrConstant(0)); - SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::f64, N->getOperand(0), + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, + MVT::f64, N->getOperand(0), DAG.getIntPtrConstant(1)); // This sequence changes FPSCR to do round-to-zero, adds the two halves @@ -3880,7 +3885,7 @@ NodeTys.push_back(MVT::f64); // Return register NodeTys.push_back(MVT::Flag); // Returns a flag for later insns - Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); + Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); MFFSreg = Result.getValue(0); InFlag = Result.getValue(1); @@ -3888,14 +3893,14 @@ NodeTys.push_back(MVT::Flag); // Returns a flag Ops[0] = DAG.getConstant(31, MVT::i32); Ops[1] = InFlag; - Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2); + Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2); InFlag = Result.getValue(0); NodeTys.clear(); NodeTys.push_back(MVT::Flag); // Returns a flag Ops[0] = DAG.getConstant(30, MVT::i32); Ops[1] = InFlag; - Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2); + Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2); InFlag = Result.getValue(0); NodeTys.clear(); @@ -3904,7 +3909,7 @@ Ops[0] = Lo; Ops[1] = Hi; Ops[2] = InFlag; - Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3); + Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3); FPreg = Result.getValue(0); InFlag = Result.getValue(1); @@ -3914,16 +3919,17 @@ Ops[1] = MFFSreg; Ops[2] = FPreg; Ops[3] = InFlag; - Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4); + Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4); FPreg = Result.getValue(0); // We know the low half is about to be thrown away, so just use something // convenient. - Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::ppcf128, FPreg, FPreg)); + Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, + FPreg, FPreg)); return; } case ISD::FP_TO_SINT: - Results.push_back(LowerFP_TO_SINT(SDValue(N, 0), DAG)); + Results.push_back(LowerFP_TO_SINT(SDValue(N, 0), DAG, dl)); return; } } @@ -4458,6 +4464,7 @@ DAGCombinerInfo &DCI) const { TargetMachine &TM = getTargetMachine(); SelectionDAG &DAG = DCI.DAG; + DebugLoc dl = N->getDebugLoc(); switch (N->getOpcode()) { default: break; case PPCISD::SHL: @@ -4490,16 +4497,16 @@ N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { SDValue Val = N->getOperand(0).getOperand(0); if (Val.getValueType() == MVT::f32) { - Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); + Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); DCI.AddToWorklist(Val.getNode()); } - Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); + Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val); DCI.AddToWorklist(Val.getNode()); - Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); + Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val); DCI.AddToWorklist(Val.getNode()); if (N->getValueType(0) == MVT::f32) { - Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val, + Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val, DAG.getIntPtrConstant(0)); DCI.AddToWorklist(Val.getNode()); } @@ -4520,13 +4527,13 @@ N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { SDValue Val = N->getOperand(1).getOperand(0); if (Val.getValueType() == MVT::f32) { - Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); + Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); DCI.AddToWorklist(Val.getNode()); } - Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); + Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); DCI.AddToWorklist(Val.getNode()); - Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, + Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val, N->getOperand(2), N->getOperand(3)); DCI.AddToWorklist(Val.getNode()); return Val; @@ -4540,10 +4547,10 @@ SDValue BSwapOp = N->getOperand(1).getOperand(0); // Do an any-extend to 32-bits if this is a half-word input. if (BSwapOp.getValueType() == MVT::i16) - BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp); + BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); - return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp, - N->getOperand(2), N->getOperand(3), + return DAG.getNode(PPCISD::STBRX, dl, MVT::Other, N->getOperand(0), + BSwapOp, N->getOperand(2), N->getOperand(3), DAG.getValueType(N->getOperand(1).getValueType())); } break; @@ -4565,12 +4572,12 @@ MO, // MemOperand DAG.getValueType(N->getValueType(0)) // VT }; - SDValue BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); + SDValue BSLoad = DAG.getNode(PPCISD::LBRX, dl, VTs, Ops, 4); // If this is an i16 load, insert the truncate. SDValue ResVal = BSLoad; if (N->getValueType(0) == MVT::i16) - ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad); + ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); // First, combine the bswap away. This makes the value produced by the // load dead. @@ -4658,7 +4665,7 @@ if (CC == ISD::SETEQ) // Cond never true, remove branch. return N->getOperand(0); // Always !=, turn it into an unconditional branch. - return DAG.getNode(ISD::BR, MVT::Other, + return DAG.getNode(ISD::BR, dl, MVT::Other, N->getOperand(0), N->getOperand(4)); } @@ -4673,7 +4680,7 @@ }; VTs.push_back(LHS.getOperand(2).getValueType()); VTs.push_back(MVT::Flag); - SDValue CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); + SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); // Unpack the result based on how the target uses it. PPC::Predicate CompOpc; @@ -4693,7 +4700,7 @@ break; } - return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), + return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), DAG.getConstant(CompOpc, MVT::i32), DAG.getRegister(PPC::CR6, MVT::i32), N->getOperand(4), CompNode.getValue(1)); Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=63889&r1=63888&r2=63889&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Thu Feb 5 16:07:54 2009 @@ -375,7 +375,7 @@ SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget); SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); - SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG); + SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, DebugLoc dl); SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG); SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG); SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG); Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=63889&r1=63888&r2=63889&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Thu Feb 5 16:07:54 2009 @@ -771,6 +771,7 @@ SDValue LHS = Op.getOperand(2); SDValue RHS = Op.getOperand(3); SDValue Dest = Op.getOperand(4); + DebugLoc dl = Op.getDebugLoc(); unsigned Opc, SPCC = ~0U; // If this is a br_cc of a "setcc", and if the setcc got lowered into @@ -784,15 +785,15 @@ VTs.push_back(MVT::i32); VTs.push_back(MVT::Flag); SDValue Ops[2] = { LHS, RHS }; - CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); + CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); Opc = SPISD::BRICC; } else { - CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); + CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS); if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); Opc = SPISD::BRFCC; } - return DAG.getNode(Opc, MVT::Other, Chain, Dest, + return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, DAG.getConstant(SPCC, MVT::i32), CompareFlag); } @@ -802,6 +803,7 @@ ISD::CondCode CC = cast(Op.getOperand(4))->get(); SDValue TrueVal = Op.getOperand(2); SDValue FalseVal = Op.getOperand(3); + DebugLoc dl = Op.getDebugLoc(); unsigned Opc, SPCC = ~0U; // If this is a select_cc of a "setcc", and if the setcc got lowered into @@ -814,15 +816,15 @@ VTs.push_back(LHS.getValueType()); // subcc returns a value VTs.push_back(MVT::Flag); SDValue Ops[2] = { LHS, RHS }; - CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); + CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); Opc = SPISD::SELECT_ICC; if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); } else { - CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); + CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS); Opc = SPISD::SELECT_FCC; if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); } - return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, + return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, DAG.getConstant(SPCC, MVT::i32), CompareFlag); } Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=63889&r1=63888&r2=63889&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Thu Feb 5 16:07:54 2009 @@ -1902,8 +1902,8 @@ << " std::vector VTs;\n" << " VTs.push_back(MVT::Other);\n" << " VTs.push_back(MVT::Flag);\n" - << " SDValue New = CurDAG->getNode(ISD::INLINEASM, VTs, &Ops[0], " - "Ops.size());\n" + << " SDValue New = CurDAG->getNode(ISD::INLINEASM, N.getDebugLoc(), " + "VTs, &Ops[0], Ops.size());\n" << " return New.getNode();\n" << "}\n\n"; From evan.cheng at apple.com Thu Feb 5 16:24:17 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 05 Feb 2009 22:24:17 -0000 Subject: [llvm-commits] [llvm] r63890 - in /llvm/trunk: lib/CodeGen/SimpleRegisterCoalescing.cpp test/CodeGen/X86/2009-02-05-CoalescerBug.ll Message-ID: <200902052224.n15MOHPc008779@zion.cs.uiuc.edu> Author: evancheng Date: Thu Feb 5 16:24:17 2009 New Revision: 63890 URL: http://llvm.org/viewvc/llvm-project?rev=63890&view=rev Log: isAsCheapAsMove instructions can have register src operands. Check if they are really re-materializable. This fixes sse.expandfft and sse.stepfft. Added: llvm/trunk/test/CodeGen/X86/2009-02-05-CoalescerBug.ll Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=63890&r1=63889&r2=63890&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Thu Feb 5 16:24:17 2009 @@ -558,6 +558,9 @@ const TargetInstrDesc &TID = DefMI->getDesc(); if (!TID.isAsCheapAsAMove()) return false; + if (!DefMI->getDesc().isRematerializable() || + !tii_->isTriviallyReMaterializable(DefMI)) + return false; bool SawStore = false; if (!DefMI->isSafeToMove(tii_, SawStore)) return false; Added: llvm/trunk/test/CodeGen/X86/2009-02-05-CoalescerBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-02-05-CoalescerBug.ll?rev=63890&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-02-05-CoalescerBug.ll (added) +++ llvm/trunk/test/CodeGen/X86/2009-02-05-CoalescerBug.ll Thu Feb 5 16:24:17 2009 @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movss | count 2 +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movaps | count 4 + +define i1 @cfft2_bb12_bb12_2E_ce([2 x float]* %y, [2 x float]* %w, i32, [2 x float]* %x.pn59, i32 %smax190, i32 %j.1180, <4 x float> %wu.2179, <4 x float> %wr.2178, <4 x float>* %tmp89.out, <4 x float>* %tmp107.out, i32* %indvar.next218.out) nounwind { +newFuncRoot: + %tmp82 = insertelement <4 x float> %wr.2178, float 0.000000e+00, i32 0 ; <<4 x float>> [#uses=1] + %tmp85 = insertelement <4 x float> %tmp82, float 0.000000e+00, i32 1 ; <<4 x float>> [#uses=1] + %tmp87 = insertelement <4 x float> %tmp85, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1] + %tmp89 = insertelement <4 x float> %tmp87, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=1] + store <4 x float> %tmp89, <4 x float>* %tmp89.out + ret i1 false +} From kremenek at apple.com Thu Feb 5 16:35:15 2009 From: kremenek at apple.com (Ted Kremenek) Date: Thu, 05 Feb 2009 22:35:15 -0000 Subject: [llvm-commits] [llvm] r63892 - /llvm/tags/checker/checker-0.150/ Message-ID: <200902052235.n15MZFiO009297@zion.cs.uiuc.edu> Author: kremenek Date: Thu Feb 5 16:35:15 2009 New Revision: 63892 URL: http://llvm.org/viewvc/llvm-project?rev=63892&view=rev Log: Tagging checker-0.150. Added: llvm/tags/checker/checker-0.150/ - copied from r63891, llvm/trunk/ From dpatel at apple.com Thu Feb 5 17:32:53 2009 From: dpatel at apple.com (Devang Patel) Date: Thu, 05 Feb 2009 23:32:53 -0000 Subject: [llvm-commits] [llvm] r63898 - in /llvm/trunk: lib/Transforms/Scalar/CondPropagate.cpp test/Transforms/CondProp/basictest-dbg.ll Message-ID: <200902052332.n15NWr2N011865@zion.cs.uiuc.edu> Author: dpatel Date: Thu Feb 5 17:32:52 2009 New Revision: 63898 URL: http://llvm.org/viewvc/llvm-project?rev=63898&view=rev Log: Ignore dbg intrinsics while propagating conditional expression info. Take 2. Added: llvm/trunk/test/Transforms/CondProp/basictest-dbg.ll Modified: llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp Modified: llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp?rev=63898&r1=63897&r2=63898&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp Thu Feb 5 17:32:52 2009 @@ -17,6 +17,7 @@ #include "llvm/Constants.h" #include "llvm/Function.h" #include "llvm/Instructions.h" +#include "llvm/IntrinsicInst.h" #include "llvm/Pass.h" #include "llvm/Type.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" @@ -134,8 +135,8 @@ // jump directly to the destination instead of going through this block. void CondProp::SimplifyPredecessors(BranchInst *BI) { // TODO: We currently only handle the most trival case, where the PHI node has - // one use (the branch), and is the only instruction besides the branch in the - // block. + // one use (the branch), and is the only instruction besides the branch and dbg + // intrinsics in the block. PHINode *PN = cast(BI->getCondition()); if (PN->getNumIncomingValues() == 1) { @@ -148,7 +149,12 @@ if (!PN->hasOneUse()) return; BasicBlock *BB = BI->getParent(); - if (&*BB->begin() != PN || &*next(BB->begin()) != BI) + if (&*BB->begin() != PN) + return; + BasicBlock::iterator BBI = BB->begin(); + BasicBlock::iterator BBE = BB->end(); + while (BBI != BBE && isa(++BBI)); + if (&*BBI != BI) return; // Ok, we have this really simple case, walk the PHI operands, looking for @@ -176,13 +182,18 @@ // the destination instead of going through this block. void CondProp::SimplifyPredecessors(SwitchInst *SI) { // TODO: We currently only handle the most trival case, where the PHI node has - // one use (the branch), and is the only instruction besides the branch in the - // block. + // one use (the branch), and is the only instruction besides the branch and + // dbg intrinsics in the block. PHINode *PN = cast(SI->getCondition()); if (!PN->hasOneUse()) return; BasicBlock *BB = SI->getParent(); - if (&*BB->begin() != PN || &*next(BB->begin()) != SI) + if (&*BB->begin() != PN) + return; + BasicBlock::iterator BBI = BB->begin(); + BasicBlock::iterator BBE = BB->end(); + while (BBI != BBE && isa(++BBI)); + if (&*BBI != SI) return; bool RemovedPreds = false; Added: llvm/trunk/test/Transforms/CondProp/basictest-dbg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/CondProp/basictest-dbg.ll?rev=63898&view=auto ============================================================================== --- llvm/trunk/test/Transforms/CondProp/basictest-dbg.ll (added) +++ llvm/trunk/test/Transforms/CondProp/basictest-dbg.ll Thu Feb 5 17:32:52 2009 @@ -0,0 +1,45 @@ +; RUN: llvm-as < %s | opt -condprop | llvm-dis | \ +; RUN: not grep {br label} + + %llvm.dbg.anchor.type = type { i32, i32 } + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } + + at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata" ; + + at .str = internal constant [4 x i8] c"a.c\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at .str1 = internal constant [6 x i8] c"/tmp/\00", section "llvm.metadata" ; <[6 x i8]*> [#uses=1] + at .str2 = internal constant [55 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build 00)\00", section "llvm.metadata" ; <[55 x i8]*> [#uses=1] + at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([6 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([55 x i8]* @.str2, i32 0, i32 0), i1 true, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] + +declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind + + +define i32 @test(i1 %C) { + br i1 %C, label %T1, label %F1 + +T1: ; preds = %0 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br label %Cont + +F1: ; preds = %0 +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br label %Cont + +Cont: ; preds = %F1, %T1 + %C2 = phi i1 [ false, %F1 ], [ true, %T1 ] ; [#uses=1] +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + br i1 %C2, label %T2, label %F2 + +T2: ; preds = %Cont +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + call void @bar( ) +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + ret i32 17 + +F2: ; preds = %Cont +call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + ret i32 1 +} + +declare void @bar() + From resistor at mac.com Thu Feb 5 17:36:27 2009 From: resistor at mac.com (Owen Anderson) Date: Thu, 05 Feb 2009 23:36:27 -0000 Subject: [llvm-commits] [llvm] r63900 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/AliasDebugger.cpp lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/IPA/GlobalsModRef.cpp Message-ID: <200902052336.n15NaRcp012007@zion.cs.uiuc.edu> Author: resistor Date: Thu Feb 5 17:36:27 2009 New Revision: 63900 URL: http://llvm.org/viewvc/llvm-project?rev=63900&view=rev Log: Refactor my previous change to maintain the distinction between AliasAnalysis and BasicAliasAnalysis. This involves some wider changes because it folds away some never-used methods. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h llvm/trunk/lib/Analysis/AliasAnalysis.cpp llvm/trunk/lib/Analysis/AliasDebugger.cpp llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=63900&r1=63899&r2=63900&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Thu Feb 5 17:36:27 2009 @@ -187,12 +187,12 @@ }; /// getModRefBehavior - Return the behavior when calling the given call site. - ModRefBehavior getModRefBehavior(CallSite CS, + virtual ModRefBehavior getModRefBehavior(CallSite CS, std::vector *Info = 0); /// getModRefBehavior - Return the behavior when calling the given function. /// For use when the call site is not known. - ModRefBehavior getModRefBehavior(Function *F, + virtual ModRefBehavior getModRefBehavior(Function *F, std::vector *Info = 0); /// doesNotAccessMemory - If the specified call is known to never read or @@ -267,13 +267,6 @@ /// virtual bool hasNoModRefInfoForCalls() const; -protected: - /// getModRefBehavior - Return the behavior of the specified function if - /// called from the specified call site. The call site may be null in which - /// case the most generic behavior of this function should be returned. - virtual ModRefBehavior getModRefBehavior(Function *F, CallSite CS, - std::vector *Info = 0); - public: /// Convenience functions... ModRefResult getModRefInfo(LoadInst *L, Value *P, unsigned Size); Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=63900&r1=63899&r2=63900&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Thu Feb 5 17:36:27 2009 @@ -59,13 +59,6 @@ return AA->pointsToConstantMemory(P); } -AliasAnalysis::ModRefBehavior -AliasAnalysis::getModRefBehavior(Function *F, CallSite CS, - std::vector *Info) { - assert(AA && "AA didn't call InitializeAliasAnalysis in its run method!"); - return AA->getModRefBehavior(F, CS, Info); -} - bool AliasAnalysis::hasNoModRefInfoForCalls() const { assert(AA && "AA didn't call InitializeAliasAnalysis in its run method!"); return AA->hasNoModRefInfoForCalls(); @@ -115,33 +108,10 @@ AliasAnalysis::ModRefBehavior AliasAnalysis::getModRefBehavior(CallSite CS, std::vector *Info) { - if (IntrinsicInst* II = dyn_cast(CS.getInstruction())) { - switch (II->getIntrinsicID()) { - case Intrinsic::atomic_cmp_swap: - case Intrinsic::atomic_load_add: - case Intrinsic::atomic_load_and: - case Intrinsic::atomic_load_max: - case Intrinsic::atomic_load_min: - case Intrinsic::atomic_load_nand: - case Intrinsic::atomic_load_or: - case Intrinsic::atomic_load_sub: - case Intrinsic::atomic_load_umax: - case Intrinsic::atomic_load_umin: - case Intrinsic::atomic_load_xor: - case Intrinsic::atomic_swap: - // CAS and related intrinsics only access their arguments. - return AliasAnalysis::AccessesArguments; - default: - break; - } - } - if (CS.doesNotAccessMemory()) // Can't do better than this. return DoesNotAccessMemory; - ModRefBehavior MRB = UnknownModRefBehavior; - if (Function *F = CS.getCalledFunction()) - MRB = getModRefBehavior(F, CS, Info); + ModRefBehavior MRB = getModRefBehavior(CS.getCalledFunction(), Info); if (MRB != DoesNotAccessMemory && CS.onlyReadsMemory()) return OnlyReadsMemory; return MRB; @@ -150,34 +120,10 @@ AliasAnalysis::ModRefBehavior AliasAnalysis::getModRefBehavior(Function *F, std::vector *Info) { - if (F->isIntrinsic()) { - switch (F->getIntrinsicID()) { - case Intrinsic::atomic_cmp_swap: - case Intrinsic::atomic_load_add: - case Intrinsic::atomic_load_and: - case Intrinsic::atomic_load_max: - case Intrinsic::atomic_load_min: - case Intrinsic::atomic_load_nand: - case Intrinsic::atomic_load_or: - case Intrinsic::atomic_load_sub: - case Intrinsic::atomic_load_umax: - case Intrinsic::atomic_load_umin: - case Intrinsic::atomic_load_xor: - case Intrinsic::atomic_swap: - // CAS and related intrinsics only access their arguments. - return AliasAnalysis::AccessesArguments; - default: - break; - } - } - if (F->doesNotAccessMemory()) // Can't do better than this. return DoesNotAccessMemory; - ModRefBehavior MRB = getModRefBehavior(F, CallSite(), Info); - if (MRB != DoesNotAccessMemory && F->onlyReadsMemory()) - return OnlyReadsMemory; - return MRB; + return UnknownModRefBehavior; } AliasAnalysis::ModRefResult @@ -188,6 +134,18 @@ Mask = Ref; else if (MRB == DoesNotAccessMemory) return NoModRef; + else if (MRB == AliasAnalysis::AccessesArguments) { + bool doesAlias = false; + for (CallSite::arg_iterator AI = CS.arg_begin(), AE = CS.arg_end(); + AI != AE; ++AI) + if (alias(*AI, ~0U, P, Size) != NoAlias) { + doesAlias = true; + break; + } + + if (!doesAlias) + return NoModRef; + } if (!AA) return Mask; Modified: llvm/trunk/lib/Analysis/AliasDebugger.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasDebugger.cpp?rev=63900&r1=63899&r2=63900&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasDebugger.cpp (original) +++ llvm/trunk/lib/Analysis/AliasDebugger.cpp Thu Feb 5 17:36:27 2009 @@ -102,15 +102,6 @@ return AliasAnalysis::pointsToConstantMemory(P); } - /// getModRefBehavior - Return the behavior of the specified function if - /// called from the specified call site. The call site may be null in which - /// case the most generic behavior of this function should be returned. - virtual ModRefBehavior getModRefBehavior(Function *F, CallSite CS, - std::vector *Info) { - assert(Vals.find(F) != Vals.end() && "Never seen value in AA before"); - return AliasAnalysis::getModRefBehavior(F, CS, Info); - } - virtual void deleteValue(Value *V) { assert(Vals.find(V) != Vals.end() && "Never seen value in AA before"); AliasAnalysis::deleteValue(V); Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=63900&r1=63899&r2=63900&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Thu Feb 5 17:36:27 2009 @@ -155,11 +155,6 @@ return MayAlias; } - virtual ModRefBehavior getModRefBehavior(Function *F, CallSite CS, - std::vector *Info) { - return UnknownModRefBehavior; - } - virtual void getArgumentAccesses(Function *F, CallSite CS, std::vector &Info) { assert(0 && "This method may not be called on this function!"); @@ -207,6 +202,12 @@ ModRefResult getModRefInfo(CallSite CS, Value *P, unsigned Size); ModRefResult getModRefInfo(CallSite CS1, CallSite CS2); + virtual ModRefBehavior getModRefBehavior(CallSite CS, + std::vector *Info = 0); + + virtual ModRefBehavior getModRefBehavior(Function *F, + std::vector *Info = 0); + /// hasNoModRefInfoForCalls - We can provide mod/ref information against /// non-escaping allocations. virtual bool hasNoModRefInfoForCalls() const { return false; } @@ -249,6 +250,52 @@ return false; } + +static bool isAtomicRMW(Function* F) { + if (!F) return false; + if (F->isIntrinsic()) { + switch (F->getIntrinsicID()) { + case Intrinsic::atomic_cmp_swap: + case Intrinsic::atomic_load_add: + case Intrinsic::atomic_load_and: + case Intrinsic::atomic_load_max: + case Intrinsic::atomic_load_min: + case Intrinsic::atomic_load_nand: + case Intrinsic::atomic_load_or: + case Intrinsic::atomic_load_sub: + case Intrinsic::atomic_load_umax: + case Intrinsic::atomic_load_umin: + case Intrinsic::atomic_load_xor: + case Intrinsic::atomic_swap: + return true; + default: + return false; + } + } + + return false; +} + +AliasAnalysis::ModRefBehavior +BasicAliasAnalysis::getModRefBehavior(CallSite CS, + std::vector *Info) { + if (isAtomicRMW(CS.getCalledFunction())) + // CAS and related intrinsics only access their arguments. + return AliasAnalysis::AccessesArguments; + + return AliasAnalysis::getModRefBehavior(CS, Info); +} + +AliasAnalysis::ModRefBehavior +BasicAliasAnalysis::getModRefBehavior(Function *F, + std::vector *Info) { + if (isAtomicRMW(F)) + // CAS and related intrinsics only access their arguments. + return AliasAnalysis::AccessesArguments; + + return AliasAnalysis::getModRefBehavior(F, Info); +} + // getModRefInfo - Check to see if the specified callsite can clobber the // specified memory object. Since we only look at local properties of this // function, we really can't say much about this query. We do, however, use @@ -256,22 +303,6 @@ // AliasAnalysis::ModRefResult BasicAliasAnalysis::getModRefInfo(CallSite CS, Value *P, unsigned Size) { - // If the function only accesses its arguments, it suffices to check that - // P does not alias any of those arguments. - if (AliasAnalysis::getModRefBehavior(CS, 0) == - AliasAnalysis::AccessesArguments) { - bool doesAlias = false; - for (CallSite::arg_iterator AI = CS.arg_begin(), AE = CS.arg_end(); - AI != AE; ++AI) - if (alias(*AI, ~0U, P, Size) != NoAlias) { - doesAlias = true; - break; - } - - if (!doesAlias) - return NoModRef; - } - if (!isa(P)) { const Value *Object = P->getUnderlyingObject(); Modified: llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp?rev=63900&r1=63899&r2=63900&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp (original) +++ llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp Thu Feb 5 17:36:27 2009 @@ -117,7 +117,7 @@ /// getModRefBehavior - Return the behavior of the specified function if /// called from the specified call site. The call site may be null in which /// case the most generic behavior of this function should be returned. - virtual ModRefBehavior getModRefBehavior(Function *F, CallSite CS, + ModRefBehavior getModRefBehavior(Function *F, std::vector *Info) { if (FunctionRecord *FR = getFunctionInfo(F)) { if (FR->FunctionEffect == 0) @@ -125,7 +125,23 @@ else if ((FR->FunctionEffect & Mod) == 0) return OnlyReadsMemory; } - return AliasAnalysis::getModRefBehavior(F, CS, Info); + return AliasAnalysis::getModRefBehavior(F, Info); + } + + /// getModRefBehavior - Return the behavior of the specified function if + /// called from the specified call site. The call site may be null in which + /// case the most generic behavior of this function should be returned. + ModRefBehavior getModRefBehavior(CallSite CS, + std::vector *Info) { + Function* F = CS.getCalledFunction(); + if (!F) return AliasAnalysis::getModRefBehavior(CS, Info); + if (FunctionRecord *FR = getFunctionInfo(F)) { + if (FR->FunctionEffect == 0) + return DoesNotAccessMemory; + else if ((FR->FunctionEffect & Mod) == 0) + return OnlyReadsMemory; + } + return AliasAnalysis::getModRefBehavior(CS, Info); } virtual void deleteValue(Value *V); From resistor at mac.com Thu Feb 5 18:13:43 2009 From: resistor at mac.com (Owen Anderson) Date: Fri, 06 Feb 2009 00:13:43 -0000 Subject: [llvm-commits] [llvm] r63902 - /llvm/trunk/lib/Analysis/AliasAnalysis.cpp Message-ID: <200902060013.n160DhZp013731@zion.cs.uiuc.edu> Author: resistor Date: Thu Feb 5 18:13:43 2009 New Revision: 63902 URL: http://llvm.org/viewvc/llvm-project?rev=63902&view=rev Log: Fix a crasher: we need to check that the function is non-null before using it! Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=63902&r1=63901&r2=63902&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Thu Feb 5 18:13:43 2009 @@ -120,7 +120,7 @@ AliasAnalysis::ModRefBehavior AliasAnalysis::getModRefBehavior(Function *F, std::vector *Info) { - if (F->doesNotAccessMemory()) + if (F && F->doesNotAccessMemory()) // Can't do better than this. return DoesNotAccessMemory; return UnknownModRefBehavior; From dalej at apple.com Thu Feb 5 19:31:28 2009 From: dalej at apple.com (Dale Johannesen) Date: Fri, 06 Feb 2009 01:31:28 -0000 Subject: [llvm-commits] [llvm] r63904 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/X86/ utils/TableGen/ Message-ID: <200902060131.n161VTCw016348@zion.cs.uiuc.edu> Author: johannes Date: Thu Feb 5 19:31:28 2009 New Revision: 63904 URL: http://llvm.org/viewvc/llvm-project?rev=63904&view=rev Log: Get rid of one more non-DebugLoc getNode and its corresponding getTargetNode. Lots of caller changes. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63904&r1=63903&r2=63904&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Thu Feb 5 19:31:28 2009 @@ -424,8 +424,6 @@ const SDUse *Ops, unsigned NumOps); SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, const SDUse *Ops, unsigned NumOps); - SDValue getNode(unsigned Opcode, MVT VT, - const SDValue *Ops, unsigned NumOps); SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, const SDValue *Ops, unsigned NumOps); SDValue getNode(unsigned Opcode, DebugLoc DL, @@ -665,8 +663,6 @@ SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1, SDValue Op2, SDValue Op3); - SDNode *getTargetNode(unsigned Opcode, MVT VT, - const SDValue *Ops, unsigned NumOps); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, const SDValue *Ops, unsigned NumOps); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63904&r1=63903&r2=63904&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Feb 5 19:31:28 2009 @@ -892,7 +892,8 @@ if (VT.isVector()) { SmallVector Ops; Ops.assign(VT.getVectorNumElements(), Result); - Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); + Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), + VT, &Ops[0], Ops.size()); } return Result; } @@ -935,7 +936,9 @@ if (VT.isVector()) { SmallVector Ops; Ops.assign(VT.getVectorNumElements(), Result); - Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); + // FIXME DebugLoc info might be appropriate here + Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), + VT, &Ops[0], Ops.size()); } return Result; } @@ -3730,11 +3733,6 @@ return getNode(Opcode, DL, VT, &NewOps[0], NumOps); } -SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, - const SDValue *Ops, unsigned NumOps) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, Ops, NumOps); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, const SDValue *Ops, unsigned NumOps) { switch (NumOps) { @@ -4450,10 +4448,6 @@ return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, - const SDValue *Ops, unsigned NumOps) { - return getNode(~Opcode, VT, Ops, NumOps).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, const SDValue *Ops, unsigned NumOps) { return getNode(~Opcode, dl, VT, Ops, NumOps).getNode(); Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=63904&r1=63903&r2=63904&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Feb 5 19:31:28 2009 @@ -532,6 +532,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { SDNode *N = Op.getNode(); + DebugLoc dl = N->getDebugLoc(); if (N->isMachineOpcode()) return NULL; // Already selected. @@ -556,7 +557,7 @@ SDNode *ResNode; if (Subtarget->isThumb()) - ResNode = CurDAG->getTargetNode(ARM::tLDRcp, MVT::i32, MVT::Other, + ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other, CPIdx, CurDAG->getEntryNode()); else { SDValue Ops[] = { @@ -567,7 +568,8 @@ CurDAG->getRegister(0, MVT::i32), CurDAG->getEntryNode() }; - ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 6); + ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other, + Ops, 6); } ReplaceUses(Op, SDValue(ResNode, 0)); return NULL; @@ -632,20 +634,20 @@ } break; case ARMISD::FMRRD: - return CurDAG->getTargetNode(ARM::FMRRD, MVT::i32, MVT::i32, + return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32, Op.getOperand(0), getAL(CurDAG), CurDAG->getRegister(0, MVT::i32)); case ISD::UMUL_LOHI: { SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), CurDAG->getRegister(0, MVT::i32) }; - return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32, Ops, 5); + return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5); } case ISD::SMUL_LOHI: { SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), CurDAG->getRegister(0, MVT::i32) }; - return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32, Ops, 5); + return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5); } case ISD::LOAD: { LoadSDNode *LD = cast(Op); @@ -685,7 +687,7 @@ SDValue Base = LD->getBasePtr(); SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), Chain }; - return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32, + return CurDAG->getTargetNode(Opcode, dl, MVT::i32, MVT::i32, MVT::Other, Ops, 6); } } @@ -855,7 +857,7 @@ TLI.getPointerTy()); SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy()); SDValue Ops[] = { Tmp1, Tmp2, Chain }; - return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, + return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl, MVT::Other, Ops, 3); } break; Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=63904&r1=63903&r2=63904&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Thu Feb 5 19:31:28 2009 @@ -662,6 +662,7 @@ unsigned NewOpc; MVT OpVT = Op.getValueType(); SDValue Ops[8]; + DebugLoc dl = N->getDebugLoc(); if (N->isMachineOpcode()) { return NULL; // Already selected. @@ -680,7 +681,7 @@ } else { NewOpc = SPU::Ar32; Ops[0] = CurDAG->getRegister(SPU::R1, Op.getValueType()); - Ops[1] = SDValue(CurDAG->getTargetNode(SPU::ILAr32, Op.getValueType(), + Ops[1] = SDValue(CurDAG->getTargetNode(SPU::ILAr32, dl, Op.getValueType(), TFI, Imm0), 0); n_ops = 2; } @@ -704,7 +705,7 @@ /*NOTREACHED*/ break; case MVT::i32: - shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32, + shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, CurDAG->getConstant(0x80808080, MVT::i32), CurDAG->getConstant(0x00010203, MVT::i32), CurDAG->getConstant(0x80808080, MVT::i32), @@ -712,7 +713,7 @@ break; case MVT::i16: - shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32, + shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, CurDAG->getConstant(0x80808080, MVT::i32), CurDAG->getConstant(0x80800203, MVT::i32), CurDAG->getConstant(0x80808080, MVT::i32), @@ -720,7 +721,7 @@ break; case MVT::i8: - shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32, + shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, CurDAG->getConstant(0x80808080, MVT::i32), CurDAG->getConstant(0x80808003, MVT::i32), CurDAG->getConstant(0x80808080, MVT::i32), @@ -730,10 +731,10 @@ SDNode *shufMaskLoad = emitBuildVector(shufMask); SDNode *PromoteScalar = - SelectCode(CurDAG->getNode(SPUISD::PREFSLOT2VEC, Op0VecVT, Op0)); + SelectCode(CurDAG->getNode(SPUISD::PREFSLOT2VEC, dl, Op0VecVT, Op0)); SDValue zextShuffle = - CurDAG->getNode(SPUISD::SHUFB, OpVecVT, + CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT, SDValue(PromoteScalar, 0), SDValue(PromoteScalar, 0), SDValue(shufMaskLoad, 0)); @@ -742,27 +743,27 @@ // re-use it in the VEC2PREFSLOT selection without needing to explicitly // call SelectCode (it's already done for us.) SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, OpVecVT, zextShuffle)); - return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, OpVT, + return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT, zextShuffle)); } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) { SDNode *CGLoad = - emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG)); + emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG, dl)); - return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, OpVT, + return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT, Op.getOperand(0), Op.getOperand(1), SDValue(CGLoad, 0))); } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) { SDNode *CGLoad = - emitBuildVector(SPU::getBorrowGenerateShufMask(*CurDAG)); + emitBuildVector(SPU::getBorrowGenerateShufMask(*CurDAG, dl)); - return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, OpVT, + return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT, Op.getOperand(0), Op.getOperand(1), SDValue(CGLoad, 0))); } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) { SDNode *CGLoad = - emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG)); + emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG, dl)); - return SelectCode(CurDAG->getNode(SPUISD::MUL64_MARKER, OpVT, + return SelectCode(CurDAG->getNode(SPUISD::MUL64_MARKER, dl, OpVT, Op.getOperand(0), Op.getOperand(1), SDValue(CGLoad, 0))); } else if (Opc == ISD::TRUNCATE) { @@ -780,7 +781,8 @@ if (shift_amt >= 32) { SDNode *hi32 = - CurDAG->getTargetNode(SPU::ORr32_r64, OpVT, Op0.getOperand(0)); + CurDAG->getTargetNode(SPU::ORr32_r64, dl, OpVT, + Op0.getOperand(0)); shift_amt -= 32; if (shift_amt > 0) { @@ -791,7 +793,8 @@ if (Op0.getOpcode() == ISD::SRL) Opc = SPU::ROTMr32; - hi32 = CurDAG->getTargetNode(Opc, OpVT, SDValue(hi32, 0), shift); + hi32 = CurDAG->getTargetNode(Opc, dl, OpVT, SDValue(hi32, 0), + shift); } return hi32; @@ -829,9 +832,9 @@ if (vtm->ldresult_imm) { SDValue Zero = CurDAG->getTargetConstant(0, VT); - Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain); + Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Zero, Chain); } else { - Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Arg, Chain); + Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Arg, Chain); } return Result; @@ -867,7 +870,7 @@ if (N->hasOneUse()) return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops); else - return CurDAG->getTargetNode(NewOpc, OpVT, Ops, n_ops); + return CurDAG->getTargetNode(NewOpc, dl, OpVT, Ops, n_ops); } else return SelectCode(Op); } @@ -892,13 +895,14 @@ MVT ShiftAmtVT = ShiftAmt.getValueType(); SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0; SDValue SelMaskVal; + DebugLoc dl = Op.getDebugLoc(); - VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op0); + VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op0); SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16); - SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, VecVT, SelMaskVal); - ZeroFill = CurDAG->getTargetNode(SPU::ILv2i64, VecVT, + SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal); + ZeroFill = CurDAG->getTargetNode(SPU::ILv2