From isanbard at gmail.com Mon Feb 9 00:42:41 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 09 Feb 2009 06:42:41 -0000 Subject: [llvm-commits] [llvm] r64119 - /llvm/trunk/utils/buildit/build_llvm Message-ID: <200902090642.n196gfuq003849@zion.cs.uiuc.edu> Author: void Date: Mon Feb 9 00:42:40 2009 New Revision: 64119 URL: http://llvm.org/viewvc/llvm-project?rev=64119&view=rev Log: Strip the LTO dylib. Modified: llvm/trunk/utils/buildit/build_llvm Modified: llvm/trunk/utils/buildit/build_llvm URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=64119&r1=64118&r2=64119&view=diff ============================================================================== --- llvm/trunk/utils/buildit/build_llvm (original) +++ llvm/trunk/utils/buildit/build_llvm Mon Feb 9 00:42:40 2009 @@ -204,6 +204,7 @@ cd $DEST_DIR$DEST_ROOT mkdir -p $DT_HOME/lib mv lib/libLTO.dylib $DT_HOME/lib/libLTO.dylib +strip -S lib/libLTO.dylib $DT_HOME/lib/libLTO.dylib rm -f lib/libLTO.a lib/libLTO.la # Compress manpages From isanbard at gmail.com Mon Feb 9 00:43:10 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 09 Feb 2009 06:43:10 -0000 Subject: [llvm-commits] [llvm] r64120 - /llvm/branches/Apple/Dib/utils/buildit/build_llvm Message-ID: <200902090643.n196hAjH003872@zion.cs.uiuc.edu> Author: void Date: Mon Feb 9 00:43:10 2009 New Revision: 64120 URL: http://llvm.org/viewvc/llvm-project?rev=64120&view=rev Log: Strip the LTO dylib. Modified: llvm/branches/Apple/Dib/utils/buildit/build_llvm Modified: llvm/branches/Apple/Dib/utils/buildit/build_llvm URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/utils/buildit/build_llvm?rev=64120&r1=64119&r2=64120&view=diff ============================================================================== --- llvm/branches/Apple/Dib/utils/buildit/build_llvm (original) +++ llvm/branches/Apple/Dib/utils/buildit/build_llvm Mon Feb 9 00:43:10 2009 @@ -204,6 +204,7 @@ cd $DEST_DIR$DEST_ROOT mkdir -p $DT_HOME/lib mv lib/libLTO.dylib $DT_HOME/lib/libLTO.dylib +strip -S lib/libLTO.dylib $DT_HOME/lib/libLTO.dylib rm -f lib/libLTO.a lib/libLTO.la # Compress manpages From isanbard at gmail.com Mon Feb 9 00:54:13 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 09 Feb 2009 06:54:13 -0000 Subject: [llvm-commits] [llvm] r64121 - /llvm/tags/Apple/llvmCore-2095.1/ Message-ID: <200902090654.n196sDga004229@zion.cs.uiuc.edu> Author: void Date: Mon Feb 9 00:54:13 2009 New Revision: 64121 URL: http://llvm.org/viewvc/llvm-project?rev=64121&view=rev Log: Creating llvmCore-2095.1 from llvmCore-2095. Added: llvm/tags/Apple/llvmCore-2095.1/ - copied from r64120, llvm/tags/Apple/llvmCore-2095/ From isanbard at gmail.com Mon Feb 9 00:54:57 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 09 Feb 2009 06:54:57 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r64122 - /llvm-gcc-4.2/tags/Apple/llvmgcc42-2095.1/ Message-ID: <200902090654.n196sv88004262@zion.cs.uiuc.edu> Author: void Date: Mon Feb 9 00:54:57 2009 New Revision: 64122 URL: http://llvm.org/viewvc/llvm-project?rev=64122&view=rev Log: Creating llvmgcc42-2095.1 from llvmgcc42-2095. Added: llvm-gcc-4.2/tags/Apple/llvmgcc42-2095.1/ - copied from r64121, llvm-gcc-4.2/tags/Apple/llvmgcc42-2095/ From isanbard at gmail.com Mon Feb 9 00:57:57 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 09 Feb 2009 06:57:57 -0000 Subject: [llvm-commits] [llvm] r64123 - /llvm/tags/Apple/llvmCore-2095.1/utils/buildit/build_llvm Message-ID: <200902090657.n196vviN004366@zion.cs.uiuc.edu> Author: void Date: Mon Feb 9 00:57:56 2009 New Revision: 64123 URL: http://llvm.org/viewvc/llvm-project?rev=64123&view=rev Log: - Make sure the 'strip' command has .so files to strip. - Don't run 'lipo' on scripts. - Strip the libLTO.dylib dylib. Modified: llvm/tags/Apple/llvmCore-2095.1/utils/buildit/build_llvm Modified: llvm/tags/Apple/llvmCore-2095.1/utils/buildit/build_llvm URL: http://llvm.org/viewvc/llvm-project/llvm/tags/Apple/llvmCore-2095.1/utils/buildit/build_llvm?rev=64123&r1=64122&r2=64123&view=diff ============================================================================== --- llvm/tags/Apple/llvmCore-2095.1/utils/buildit/build_llvm (original) +++ llvm/tags/Apple/llvmCore-2095.1/utils/buildit/build_llvm Mon Feb 9 00:57:56 2009 @@ -176,7 +176,9 @@ if [ "x$LLVM_DEBUG" != "x1" ]; then # Strip local symbols from llvm libraries. strip -S $DEST_DIR$DEST_ROOT/lib/*.[oa] - strip -Sx $DEST_DIR$DEST_ROOT/lib/*.so + for f in `ls $DEST_DIR$DEST_ROOT/lib/*.so`; do + strip -Sx $f + done fi # Copy over the tblgen utility. @@ -184,21 +186,25 @@ # Remove .dir files cd $DEST_DIR$DEST_ROOT -rm bin/.dir etc/llvm/.dir lib/.dir +rm -f bin/.dir etc/llvm/.dir lib/.dir # Remove PPC64 fat slices. cd $DEST_DIR$DEST_ROOT/bin if [ $MACOSX_DEPLOYMENT_TARGET = "10.4" ]; then - find . -perm 755 -type f -exec lipo -extract ppc -extract i386 {} -output {} \; + find . -perm 755 -type f \! \( -name '*gccas' -o -name '*gccld' -o -name llvm-config \) \ + -exec lipo -extract ppc -extract i386 {} -output {} \; elif [ $MACOSX_DEPLOYMENT_TARGET = "10.5" ]; then - find . -perm 755 -type f -exec lipo -extract ppc7400 -extract i386 {} -output {} \; + find . -perm 755 -type f \! \( -name '*gccas' -o -name '*gccld' -o -name llvm-config \) \ + -exec lipo -extract ppc7400 -extract i386 {} -output {} \; else - find . -perm 755 -type f -exec lipo -extract ppc7400 -extract i386 -extract x86_64 {} -output {} \; + find . -perm 755 -type f \! \( -name '*gccas' -o -name '*gccld' -o -name llvm-config \) \ + -exec lipo -extract ppc7400 -extract i386 -extract x86_64 {} -output {} \; fi cd $DEST_DIR$DEST_ROOT mkdir -p $DT_HOME/lib mv lib/libLTO.dylib $DT_HOME/lib/libLTO.dylib +strip -S lib/libLTO.dylib $DT_HOME/lib/libLTO.dylib rm -f lib/libLTO.a lib/libLTO.la # Compress manpages From evan.cheng at apple.com Mon Feb 9 01:14:22 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 09 Feb 2009 07:14:22 -0000 Subject: [llvm-commits] [llvm] r64124 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/X86/ lib/Target/XCore/ Message-ID: <200902090714.n197EMxc004979@zion.cs.uiuc.edu> Author: evancheng Date: Mon Feb 9 01:14:22 2009 New Revision: 64124 URL: http://llvm.org/viewvc/llvm-project?rev=64124&view=rev Log: Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/CodeGen/BranchFolding.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.h llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.h llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.h llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=64124&r1=64123&r2=64124&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Mon Feb 9 01:14:22 2009 @@ -195,9 +195,13 @@ /// Note that RemoveBranch and InsertBranch must be implemented to support /// cases where this method returns success. /// + /// If AllowModify is true, then this routine is allowed to modify the basic + /// block (e.g. delete instructions after the unconditional branch). + /// virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + SmallVectorImpl &Cond, + bool AllowModify = false) const { return true; } Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=64124&r1=64123&r2=64124&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Mon Feb 9 01:14:22 2009 @@ -191,7 +191,7 @@ for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; I++) { MachineBasicBlock *MBB = I, *TBB = 0, *FBB = 0; SmallVector Cond; - if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond)) + if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, true)) EverMadeChange |= MBB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty()); EverMadeChange |= OptimizeImpDefsBlock(MBB); } @@ -434,7 +434,7 @@ MachineBasicBlock *TBB = 0, *FBB = 0; SmallVector Cond; if (I != MF->end() && - !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond)) { + !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond, true)) { MachineBasicBlock *NextBB = I; if (TBB == NextBB && !Cond.empty() && !FBB) { if (!TII->ReverseBranchCondition(Cond)) { @@ -711,7 +711,7 @@ continue; MachineBasicBlock *TBB = 0, *FBB = 0; SmallVector Cond; - if (!TII->AnalyzeBranch(*PBB, TBB, FBB, Cond)) { + if (!TII->AnalyzeBranch(*PBB, TBB, FBB, Cond, true)) { // Failing case: IBB is the target of a cbr, and // we cannot reverse the branch. SmallVector NewCond(Cond); @@ -845,7 +845,7 @@ bool BranchFolder::CanFallThrough(MachineBasicBlock *CurBB) { MachineBasicBlock *TBB = 0, *FBB = 0; SmallVector Cond; - bool CurUnAnalyzable = TII->AnalyzeBranch(*CurBB, TBB, FBB, Cond); + bool CurUnAnalyzable = TII->AnalyzeBranch(*CurBB, TBB, FBB, Cond, true); return CanFallThrough(CurBB, CurUnAnalyzable, TBB, FBB, Cond); } @@ -910,7 +910,7 @@ MachineBasicBlock *PriorTBB = 0, *PriorFBB = 0; SmallVector PriorCond; bool PriorUnAnalyzable = - TII->AnalyzeBranch(PrevBB, PriorTBB, PriorFBB, PriorCond); + TII->AnalyzeBranch(PrevBB, PriorTBB, PriorFBB, PriorCond, true); if (!PriorUnAnalyzable) { // If the CFG for the prior block has extra edges, remove them. MadeChange |= PrevBB.CorrectExtraCFGEdges(PriorTBB, PriorFBB, @@ -1023,7 +1023,7 @@ // Analyze the branch in the current block. MachineBasicBlock *CurTBB = 0, *CurFBB = 0; SmallVector CurCond; - bool CurUnAnalyzable = TII->AnalyzeBranch(*MBB, CurTBB, CurFBB, CurCond); + bool CurUnAnalyzable= TII->AnalyzeBranch(*MBB, CurTBB, CurFBB, CurCond, true); if (!CurUnAnalyzable) { // If the CFG for the prior block has extra edges, remove them. MadeChange |= MBB->CorrectExtraCFGEdges(CurTBB, CurFBB, !CurCond.empty()); Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=64124&r1=64123&r2=64124&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Mon Feb 9 01:14:22 2009 @@ -335,7 +335,8 @@ // Branch analysis. bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) @@ -385,7 +386,8 @@ (LastOpc == ARM::B || LastOpc == ARM::tB)) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return false; } @@ -396,7 +398,8 @@ SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr) && (LastOpc == ARM::B || LastOpc == ARM::tB)) { I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return true; } Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=64124&r1=64123&r2=64124&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Mon Feb 9 01:14:22 2009 @@ -172,7 +172,8 @@ // Branch analysis. virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=64124&r1=64123&r2=64124&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Mon Feb 9 01:14:22 2009 @@ -321,8 +321,9 @@ // Branch analysis. bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, - MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) @@ -373,7 +374,8 @@ LastInst->getOpcode() == Alpha::BR) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return false; } Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h?rev=64124&r1=64123&r2=64124&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h Mon Feb 9 01:14:22 2009 @@ -83,7 +83,8 @@ bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; unsigned RemoveBranch(MachineBasicBlock &MBB) const; void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const; Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=64124&r1=64123&r2=64124&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Mon Feb 9 01:14:22 2009 @@ -524,7 +524,8 @@ bool SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) @@ -575,7 +576,8 @@ if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return false; } Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h?rev=64124&r1=64123&r2=64124&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h Mon Feb 9 01:14:22 2009 @@ -100,7 +100,8 @@ virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=64124&r1=64123&r2=64124&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Mon Feb 9 01:14:22 2009 @@ -453,7 +453,8 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); @@ -525,7 +526,8 @@ if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return false; } Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=64124&r1=64123&r2=64124&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Mon Feb 9 01:14:22 2009 @@ -166,7 +166,8 @@ /// Branch Analysis virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=64124&r1=64123&r2=64124&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Mon Feb 9 01:14:22 2009 @@ -204,7 +204,8 @@ // Branch analysis. bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) @@ -253,7 +254,8 @@ LastInst->getOpcode() == PPC::B) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return false; } Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=64124&r1=64123&r2=64124&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Mon Feb 9 01:14:22 2009 @@ -104,7 +104,8 @@ // Branch analysis. virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=64124&r1=64123&r2=64124&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Feb 9 01:14:22 2009 @@ -1488,7 +1488,8 @@ bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + SmallVectorImpl &Cond, + bool AllowModify) const { // Start from the bottom of the block and work up, examining the // terminator instructions. MachineBasicBlock::iterator I = MBB.end(); @@ -1504,6 +1505,11 @@ return true; // Handle unconditional branches. if (I->getOpcode() == X86::JMP) { + if (!AllowModify) { + TBB = I->getOperand(0).getMBB(); + return false; + } + // If the block has any instructions after a JMP, delete them. while (next(I) != MBB.end()) next(I)->eraseFromParent(); Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=64124&r1=64123&r2=64124&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Mon Feb 9 01:14:22 2009 @@ -323,7 +323,8 @@ virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp?rev=64124&r1=64123&r2=64124&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp Mon Feb 9 01:14:22 2009 @@ -228,8 +228,9 @@ /// bool XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, - MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) @@ -288,7 +289,8 @@ IsBRU(LastInst->getOpcode())) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return false; } Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h?rev=64124&r1=64123&r2=64124&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h Mon Feb 9 01:14:22 2009 @@ -56,7 +56,8 @@ virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, From clattner at apple.com Mon Feb 9 01:20:57 2009 From: clattner at apple.com (Chris Lattner) Date: Sun, 8 Feb 2009 23:20:57 -0800 Subject: [llvm-commits] [llvm] r64124 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/X86/ lib/Target/XCore/ In-Reply-To: <200902090714.n197EMxc004979@zion.cs.uiuc.edu> References: <200902090714.n197EMxc004979@zion.cs.uiuc.edu> Message-ID: <1067F87A-9600-411A-810D-9D450ADC7C46@apple.com> On Feb 8, 2009, at 11:14 PM, Evan Cheng wrote: > Author: evancheng > Date: Mon Feb 9 01:14:22 2009 > New Revision: 64124 > > URL: http://llvm.org/viewvc/llvm-project?rev=64124&view=rev > Log: > Turns out AnalyzeBranch can modify the mbb being analyzed. This is a > nasty > suprise to some callers, e.g. register coalescer. For now, add an > parameter > that tells AnalyzeBranch whether it's safe to modify the mbb. A better > solution is out there, but I don't have time to deal with it right > now. Whoa, that's really not cool. *why* does analyze branch modify a mbb? What breaks if that is disabled from all targets? -chris From evan.cheng at apple.com Mon Feb 9 02:37:45 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 09 Feb 2009 08:37:45 -0000 Subject: [llvm-commits] [llvm] r64125 - /llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Message-ID: <200902090837.n198bjBE008601@zion.cs.uiuc.edu> Author: evancheng Date: Mon Feb 9 02:37:45 2009 New Revision: 64125 URL: http://llvm.org/viewvc/llvm-project?rev=64125&view=rev Log: Fix another case ShortenDeadCopySrcLiveRange is shortening too much. No test case possible since I don't know what to grep for. :-( Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=64125&r1=64124&r2=64125&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Mon Feb 9 02:37:45 2009 @@ -861,22 +861,29 @@ // If there is a last use in the same bb, we can't remove the live range. // Shorten the live interval and return. - if (TrimLiveIntervalToLastUse(CopyIdx, CopyMI->getParent(), li, LR)) + MachineBasicBlock *CopyMBB = CopyMI->getParent(); + if (TrimLiveIntervalToLastUse(CopyIdx, CopyMBB, li, LR)) return false; + MachineBasicBlock *StartMBB = li_->getMBBFromIndex(RemoveStart); + if (!isSameOrFallThroughBB(StartMBB, CopyMBB, tii_)) + // If the live range starts in another mbb and the copy mbb is not a fall + // through mbb, then we can only cut the range from the beginning of the + // copy mbb. + RemoveStart = li_->getMBBStartIdx(CopyMBB) + 1; + if (LR->valno->def == RemoveStart) { // If the def MI defines the val# and this copy is the only kill of the // val#, then propagate the dead marker. - if (!li.isOnlyLROfValNo(LR)) { - if (li.isKill(LR->valno, RemoveEnd)) - li.removeKill(LR->valno, RemoveEnd); - } else { + if (li.isOnlyLROfValNo(LR)) { PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_); ++numDeadValNo; } + if (li.isKill(LR->valno, RemoveEnd)) + li.removeKill(LR->valno, RemoveEnd); } - removeRange(li, RemoveStart, LR->end, li_, tri_); + removeRange(li, RemoveStart, RemoveEnd, li_, tri_); return removeIntervalIfEmpty(li, li_, tri_); } From evan.cheng at apple.com Mon Feb 9 02:41:58 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 9 Feb 2009 00:41:58 -0800 Subject: [llvm-commits] [llvm] r64124 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/X86/ lib/Target/XCore/ In-Reply-To: <1067F87A-9600-411A-810D-9D450ADC7C46@apple.com> References: <200902090714.n197EMxc004979@zion.cs.uiuc.edu> <1067F87A-9600-411A-810D-9D450ADC7C46@apple.com> Message-ID: <6EE4E128-338A-4737-AE0A-1359A9DE6318@apple.com> On Feb 8, 2009, at 11:20 PM, Chris Lattner wrote: > > On Feb 8, 2009, at 11:14 PM, Evan Cheng wrote: > >> Author: evancheng >> Date: Mon Feb 9 01:14:22 2009 >> New Revision: 64124 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=64124&view=rev >> Log: >> Turns out AnalyzeBranch can modify the mbb being analyzed. This is a >> nasty >> suprise to some callers, e.g. register coalescer. For now, add an >> parameter >> that tells AnalyzeBranch whether it's safe to modify the mbb. A >> better >> solution is out there, but I don't have time to deal with it right >> now. > > Whoa, that's really not cool. *why* does analyze branch modify a > mbb? What breaks if that is disabled from all targets? It's trimming instructions in a mbb after an unconditional branch. I don't know why that would happen but it does. I think it's branching folding's job to trim those instructions. But I don't have the energy to deal with that right now. Evan > > > -chris > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon Feb 9 02:45:40 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 09 Feb 2009 08:45:40 -0000 Subject: [llvm-commits] [llvm] r64126 - in /llvm/trunk: lib/CodeGen/LLVMTargetMachine.cpp test/CodeGen/ARM/lsr-code-insertion.ll test/CodeGen/X86/2006-05-11-InstrSched.ll test/CodeGen/X86/2009-02-07-CoalescerBug.ll Message-ID: <200902090845.n198jefX011242@zion.cs.uiuc.edu> Author: evancheng Date: Mon Feb 9 02:45:39 2009 New Revision: 64126 URL: http://llvm.org/viewvc/llvm-project?rev=64126&view=rev Log: Re-enable machine sinking pass now that the coalescer bugs and the AnalyzeBrnach bug are fixed. Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp llvm/trunk/test/CodeGen/ARM/lsr-code-insertion.ll llvm/trunk/test/CodeGen/X86/2006-05-11-InstrSched.ll llvm/trunk/test/CodeGen/X86/2009-02-07-CoalescerBug.ll Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=64126&r1=64125&r2=64126&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Mon Feb 9 02:45:39 2009 @@ -38,11 +38,6 @@ static cl::opt PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data")); -// Hidden options to help debugging -static cl::opt -EnableSinking("enable-sinking", cl::init(false), cl::Hidden, - cl::desc("Perform sinking on machine code")); - // When this works it will be on by default. static cl::opt DisablePostRAScheduler("disable-post-RA-scheduler", @@ -183,11 +178,10 @@ if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (!Fast) + if (!Fast) { PM.add(createMachineLICMPass()); - - if (EnableSinking) PM.add(createMachineSinkingPass()); + } // Run pre-ra passes. if (addPreRegAlloc(PM, Fast) && PrintMachineCode) Modified: llvm/trunk/test/CodeGen/ARM/lsr-code-insertion.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/lsr-code-insertion.ll?rev=64126&r1=64125&r2=64126&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/lsr-code-insertion.ll (original) +++ llvm/trunk/test/CodeGen/ARM/lsr-code-insertion.ll Mon Feb 9 02:45:39 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -stats |& grep {39.*Number of machine instrs printed} +; RUN: llvm-as < %s | llc -stats |& grep {40.*Number of machine instrs printed} ; RUN: llvm-as < %s | llc -stats |& grep {.*Number of re-materialization} ; This test really wants to check that the resultant "cond_true" block only ; has a single store in it, and that cond_true55 only has code to materialize Modified: llvm/trunk/test/CodeGen/X86/2006-05-11-InstrSched.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2006-05-11-InstrSched.ll?rev=64126&r1=64125&r2=64126&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2006-05-11-InstrSched.ll (original) +++ llvm/trunk/test/CodeGen/X86/2006-05-11-InstrSched.ll Mon Feb 9 02:45:39 2009 @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats -realign-stack=0 |&\ -; RUN: grep {asm-printer} | grep 32 +; RUN: grep {asm-printer} | grep 31 target datalayout = "e-p:32:32" define void @foo(i32* %mc, i32* %bp, i32* %ms, i32* %xmb, i32* %mpp, i32* %tpmm, i32* %ip, i32* %tpim, i32* %dpp, i32* %tpdm, i32* %bpi, i32 %M) nounwind { Modified: llvm/trunk/test/CodeGen/X86/2009-02-07-CoalescerBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-02-07-CoalescerBug.ll?rev=64126&r1=64125&r2=64126&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-02-07-CoalescerBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-02-07-CoalescerBug.ll Mon Feb 9 02:45:39 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86 -enable-sinking -relocation-model=pic -stats |& grep {Number of valno def marked dead} | grep 1 +; RUN: llvm-as < %s | llc -march=x86 -relocation-model=pic -stats |& grep {Number of valno def marked dead} | grep 1 ; rdar://6566708 target triple = "i386-apple-darwin9.6" From clattner at apple.com Mon Feb 9 02:56:06 2009 From: clattner at apple.com (Chris Lattner) Date: Mon, 9 Feb 2009 00:56:06 -0800 Subject: [llvm-commits] [llvm] r64124 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/X86/ lib/Target/XCore/ In-Reply-To: <6EE4E128-338A-4737-AE0A-1359A9DE6318@apple.com> References: <200902090714.n197EMxc004979@zion.cs.uiuc.edu> <1067F87A-9600-411A-810D-9D450ADC7C46@apple.com> <6EE4E128-338A-4737-AE0A-1359A9DE6318@apple.com> Message-ID: <512664C1-FD05-4271-A5B1-2B9A2A85B962@apple.com> On Feb 9, 2009, at 12:41 AM, Evan Cheng wrote: > On Feb 8, 2009, at 11:20 PM, Chris Lattner wrote: >> On Feb 8, 2009, at 11:14 PM, Evan Cheng wrote: >> >>> Author: evancheng >>> Date: Mon Feb 9 01:14:22 2009 >>> New Revision: 64124 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=64124&view=rev >>> Log: >>> Turns out AnalyzeBranch can modify the mbb being analyzed. This is a >>> nasty >>> suprise to some callers, e.g. register coalescer. For now, add an >>> parameter >>> that tells AnalyzeBranch whether it's safe to modify the mbb. A >>> better >>> solution is out there, but I don't have time to deal with it right >>> now. >> >> Whoa, that's really not cool. *why* does analyze branch modify a >> mbb? What breaks if that is disabled from all targets? > > It's trimming instructions in a mbb after an unconditional branch. I > don't know why that would happen but it does. I think it's branching > folding's job to trim those instructions. But I don't have the energy > to deal with that right now. Ok no problem, please file a bugzilla, thanks! -Chris From baldrick at free.fr Mon Feb 9 03:40:15 2009 From: baldrick at free.fr (Duncan Sands) Date: Mon, 09 Feb 2009 09:40:15 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r64130 - in /llvm-gcc-4.2/trunk/gcc: llvm-convert.cpp llvm-internal.h Message-ID: <200902090940.n199eHHF019770@zion.cs.uiuc.edu> Author: baldrick Date: Mon Feb 9 03:40:04 2009 New Revision: 64130 URL: http://llvm.org/viewvc/llvm-project?rev=64130&view=rev Log: Add support for FLOOR_DIV_EXPR. This is sometimes produced by the Fortran front-end, see PR2437. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp llvm-gcc-4.2/trunk/gcc/llvm-internal.h Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=64130&r1=64129&r2=64130&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Feb 9 03:40:04 2009 @@ -1050,6 +1050,7 @@ break; case RDIV_EXPR: Result = EmitBinOp(exp, DestLoc, Instruction::FDiv); break; case CEIL_DIV_EXPR: Result = EmitCEIL_DIV_EXPR(exp); break; + case FLOOR_DIV_EXPR: Result = EmitFLOOR_DIV_EXPR(exp); break; case ROUND_DIV_EXPR: Result = EmitROUND_DIV_EXPR(exp); break; case TRUNC_MOD_EXPR: if (TYPE_UNSIGNED(TREE_TYPE(exp))) @@ -3698,6 +3699,55 @@ return Builder.CreateAdd(CDiv, Offset, "cdiv"); } +Value *TreeToLLVM::EmitFLOOR_DIV_EXPR(tree exp) { + // Notation: FLOOR_DIV_EXPR <-> FDiv, TRUNC_DIV_EXPR <-> Div. + Value *LHS = Emit(TREE_OPERAND(exp, 0), 0); + Value *RHS = Emit(TREE_OPERAND(exp, 1), 0); + + // FDiv calculates LHS/RHS by rounding down to the nearest integer. In terms + // of Div this means if the values of LHS and RHS have the same sign or if LHS + // is zero, then FDiv necessarily equals Div; and + // LHS FDiv RHS = (LHS + Sign(RHS)) Div RHS - 1 + // otherwise. + + if (TYPE_UNSIGNED(TREE_TYPE(exp))) + // In the case of unsigned arithmetic, LHS and RHS necessarily have the + // same sign, so FDiv is the same as Div. + return Builder.CreateUDiv(LHS, RHS, "fdiv"); + + const Type *Ty = ConvertType(TREE_TYPE(exp)); + Constant *Zero = ConstantInt::get(Ty, 0); + Constant *One = ConstantInt::get(Ty, 1); + Constant *MinusOne = ConstantInt::getAllOnesValue(Ty); + + // In the case of signed arithmetic, we calculate FDiv as follows: + // LHS FDiv RHS = (LHS + Sign(RHS) * Offset) Div RHS - Offset, + // where Offset is 1 if LHS and RHS have opposite signs and LHS is + // not zero, and 0 otherwise. + + // Determine the signs of LHS and RHS, and whether they have the same sign. + Value *LHSIsPositive = Builder.CreateICmpSGE(LHS, Zero); + Value *RHSIsPositive = Builder.CreateICmpSGE(RHS, Zero); + Value *SignsDiffer = Builder.CreateICmpNE(LHSIsPositive, RHSIsPositive); + + // Offset equals 1 if LHS and RHS have opposite signs and LHS is not zero. + Value *LHSNotZero = Builder.CreateICmpNE(LHS, Zero); + Value *OffsetOne = Builder.CreateAnd(SignsDiffer, LHSNotZero); + // ... otherwise it is 0. + Value *Offset = Builder.CreateSelect(OffsetOne, One, Zero); + + // Calculate Sign(RHS) ... + Value *SignRHS = Builder.CreateSelect(RHSIsPositive, One, MinusOne); + // ... and Sign(RHS) * Offset + Value *SignedOffset = CastToType(Instruction::SExt, OffsetOne, Ty); + SignedOffset = Builder.CreateAnd(SignRHS, SignedOffset); + + // Return FDiv = (LHS + Sign(RHS) * Offset) Div RHS - Offset. + Value *FDiv = Builder.CreateAdd(LHS, SignedOffset); + FDiv = Builder.CreateSDiv(FDiv, RHS); + return Builder.CreateSub(FDiv, Offset, "fdiv"); +} + Value *TreeToLLVM::EmitROUND_DIV_EXPR(tree exp) { // Notation: ROUND_DIV_EXPR <-> RDiv, TRUNC_DIV_EXPR <-> Div. Modified: llvm-gcc-4.2/trunk/gcc/llvm-internal.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-internal.h?rev=64130&r1=64129&r2=64130&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-internal.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-internal.h Mon Feb 9 03:40:04 2009 @@ -515,6 +515,7 @@ unsigned Opc); Value *EmitFLOOR_MOD_EXPR(tree_node *exp, const MemRef *DestLoc); Value *EmitCEIL_DIV_EXPR(tree_node *exp); + Value *EmitFLOOR_DIV_EXPR(tree_node *exp); Value *EmitROUND_DIV_EXPR(tree_node *exp); // Exception Handling. From baldrick at free.fr Mon Feb 9 03:41:50 2009 From: baldrick at free.fr (Duncan Sands) Date: Mon, 09 Feb 2009 09:41:50 -0000 Subject: [llvm-commits] [llvm] r64131 - /llvm/trunk/test/FrontendFortran/2009-02-09-FloorDivExpr.f90 Message-ID: <200902090941.n199foxd019837@zion.cs.uiuc.edu> Author: baldrick Date: Mon Feb 9 03:41:49 2009 New Revision: 64131 URL: http://llvm.org/viewvc/llvm-project?rev=64131&view=rev Log: Testcase for PR2437. Added: llvm/trunk/test/FrontendFortran/2009-02-09-FloorDivExpr.f90 Added: llvm/trunk/test/FrontendFortran/2009-02-09-FloorDivExpr.f90 URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendFortran/2009-02-09-FloorDivExpr.f90?rev=64131&view=auto ============================================================================== --- llvm/trunk/test/FrontendFortran/2009-02-09-FloorDivExpr.f90 (added) +++ llvm/trunk/test/FrontendFortran/2009-02-09-FloorDivExpr.f90 Mon Feb 9 03:41:49 2009 @@ -0,0 +1,32 @@ +! RUN: %llvmgcc -c %s +! PR2437 +program main + implicit none + call build (77) +contains + subroutine build (order) + integer :: order, i, j + + + call test (1, order, 3, (/ (i, i = 1, order, 3) /)) + call test (order, 1, -3, (/ (i, i = order, 1, -3) /)) + + do j = -10, 10 + call test (order + j, order, 5, (/ (i, i = order + j, order, 5) /)) + call test (order + j, order, -5, (/ (i, i = order + j, order, -5) /)) + end do + + end subroutine build + + subroutine test (from, to, step, values) + integer, dimension (:) :: values + integer :: from, to, step, last, i + + last = 0 + do i = from, to, step + last = last + 1 + if (values (last) .ne. i) call abort + end do + if (size (values, dim = 1) .ne. last) call abort + end subroutine test +end program main From sabre at nondot.org Mon Feb 9 04:01:06 2009 From: sabre at nondot.org (Chris Lattner) Date: Mon, 09 Feb 2009 10:01:06 -0000 Subject: [llvm-commits] [llvm] r64132 - /llvm/trunk/docs/LangRef.html Message-ID: <200902091001.n19A1AQm020415@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 9 04:00:56 2009 New Revision: 64132 URL: http://llvm.org/viewvc/llvm-project?rev=64132&view=rev Log: fix typo, patch by Jonathan Brandmeyer! Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=64132&r1=64131&r2=64132&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Mon Feb 9 04:00:56 2009 @@ -1677,7 +1677,7 @@ references (with their equivalent as named type declarations) include:

-   { \2 * }                %x = type { %t* }
+   { \2 * }                %x = type { %x* }
    { \2 }*                 %y = type { %y }*
    \1*                     %z = type %z*
From clattner at apple.com Mon Feb 9 04:01:34 2009 From: clattner at apple.com (Chris Lattner) Date: Mon, 9 Feb 2009 02:01:34 -0800 Subject: [llvm-commits] Minor nitpick patch to LangRef In-Reply-To: <1234135800.31978.4.camel@localhost> References: <1234135800.31978.4.camel@localhost> Message-ID: <4B6059EC-2196-4CE1-AE79-EC856EC333B6@apple.com> On Feb 8, 2009, at 3:29 PM, Jonathan Brandmeyer wrote: > Correct a nit in the Type Up-references documentation. Thanks! http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090209/073509.html From isanbard at gmail.com Mon Feb 9 04:54:08 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 09 Feb 2009 10:54:08 -0000 Subject: [llvm-commits] [llvm] r64133 - in /llvm/branches/Apple/Dib: include/llvm/Target/ lib/CodeGen/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/X86/ lib/Target/XCore/ Message-ID: <200902091054.n19As93U022438@zion.cs.uiuc.edu> Author: void Date: Mon Feb 9 04:54:06 2009 New Revision: 64133 URL: http://llvm.org/viewvc/llvm-project?rev=64133&view=rev Log: Pull r64124 into Dib: Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. Modified: llvm/branches/Apple/Dib/include/llvm/Target/TargetInstrInfo.h llvm/branches/Apple/Dib/lib/CodeGen/BranchFolding.cpp llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.h llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.cpp llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.h llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.h llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.cpp llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.h llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.h llvm/branches/Apple/Dib/lib/Target/XCore/XCoreInstrInfo.cpp llvm/branches/Apple/Dib/lib/Target/XCore/XCoreInstrInfo.h Modified: llvm/branches/Apple/Dib/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/Target/TargetInstrInfo.h?rev=64133&r1=64132&r2=64133&view=diff ============================================================================== --- llvm/branches/Apple/Dib/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/branches/Apple/Dib/include/llvm/Target/TargetInstrInfo.h Mon Feb 9 04:54:06 2009 @@ -195,9 +195,13 @@ /// Note that RemoveBranch and InsertBranch must be implemented to support /// cases where this method returns success. /// + /// If AllowModify is true, then this routine is allowed to modify the basic + /// block (e.g. delete instructions after the unconditional branch). + /// virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + SmallVectorImpl &Cond, + bool AllowModify = false) const { return true; } Modified: llvm/branches/Apple/Dib/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/BranchFolding.cpp?rev=64133&r1=64132&r2=64133&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/BranchFolding.cpp Mon Feb 9 04:54:06 2009 @@ -191,7 +191,7 @@ for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; I++) { MachineBasicBlock *MBB = I, *TBB = 0, *FBB = 0; SmallVector Cond; - if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond)) + if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, true)) EverMadeChange |= MBB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty()); EverMadeChange |= OptimizeImpDefsBlock(MBB); } @@ -434,7 +434,7 @@ MachineBasicBlock *TBB = 0, *FBB = 0; SmallVector Cond; if (I != MF->end() && - !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond)) { + !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond, true)) { MachineBasicBlock *NextBB = I; if (TBB == NextBB && !Cond.empty() && !FBB) { if (!TII->ReverseBranchCondition(Cond)) { @@ -711,7 +711,7 @@ continue; MachineBasicBlock *TBB = 0, *FBB = 0; SmallVector Cond; - if (!TII->AnalyzeBranch(*PBB, TBB, FBB, Cond)) { + if (!TII->AnalyzeBranch(*PBB, TBB, FBB, Cond, true)) { // Failing case: IBB is the target of a cbr, and // we cannot reverse the branch. SmallVector NewCond(Cond); @@ -845,7 +845,7 @@ bool BranchFolder::CanFallThrough(MachineBasicBlock *CurBB) { MachineBasicBlock *TBB = 0, *FBB = 0; SmallVector Cond; - bool CurUnAnalyzable = TII->AnalyzeBranch(*CurBB, TBB, FBB, Cond); + bool CurUnAnalyzable = TII->AnalyzeBranch(*CurBB, TBB, FBB, Cond, true); return CanFallThrough(CurBB, CurUnAnalyzable, TBB, FBB, Cond); } @@ -910,7 +910,7 @@ MachineBasicBlock *PriorTBB = 0, *PriorFBB = 0; SmallVector PriorCond; bool PriorUnAnalyzable = - TII->AnalyzeBranch(PrevBB, PriorTBB, PriorFBB, PriorCond); + TII->AnalyzeBranch(PrevBB, PriorTBB, PriorFBB, PriorCond, true); if (!PriorUnAnalyzable) { // If the CFG for the prior block has extra edges, remove them. MadeChange |= PrevBB.CorrectExtraCFGEdges(PriorTBB, PriorFBB, @@ -1023,7 +1023,7 @@ // Analyze the branch in the current block. MachineBasicBlock *CurTBB = 0, *CurFBB = 0; SmallVector CurCond; - bool CurUnAnalyzable = TII->AnalyzeBranch(*MBB, CurTBB, CurFBB, CurCond); + bool CurUnAnalyzable= TII->AnalyzeBranch(*MBB, CurTBB, CurFBB, CurCond, true); if (!CurUnAnalyzable) { // If the CFG for the prior block has extra edges, remove them. MadeChange |= MBB->CorrectExtraCFGEdges(CurTBB, CurFBB, !CurCond.empty()); Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp?rev=64133&r1=64132&r2=64133&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp Mon Feb 9 04:54:06 2009 @@ -335,7 +335,8 @@ // Branch analysis. bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) @@ -385,7 +386,8 @@ (LastOpc == ARM::B || LastOpc == ARM::tB)) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return false; } @@ -396,7 +398,8 @@ SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr) && (LastOpc == ARM::B || LastOpc == ARM::tB)) { I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return true; } Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.h?rev=64133&r1=64132&r2=64133&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.h (original) +++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.h Mon Feb 9 04:54:06 2009 @@ -172,7 +172,8 @@ // Branch analysis. virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, Modified: llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=64133&r1=64132&r2=64133&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.cpp Mon Feb 9 04:54:06 2009 @@ -321,8 +321,9 @@ // Branch analysis. bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, - MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) @@ -373,7 +374,8 @@ LastInst->getOpcode() == Alpha::BR) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return false; } Modified: llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.h?rev=64133&r1=64132&r2=64133&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.h (original) +++ llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.h Mon Feb 9 04:54:06 2009 @@ -83,7 +83,8 @@ bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; unsigned RemoveBranch(MachineBasicBlock &MBB) const; void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const; Modified: llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=64133&r1=64132&r2=64133&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp Mon Feb 9 04:54:06 2009 @@ -524,7 +524,8 @@ bool SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) @@ -575,7 +576,8 @@ if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return false; } Modified: llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.h?rev=64133&r1=64132&r2=64133&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.h (original) +++ llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.h Mon Feb 9 04:54:06 2009 @@ -100,7 +100,8 @@ virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; Modified: llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.cpp?rev=64133&r1=64132&r2=64133&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.cpp Mon Feb 9 04:54:06 2009 @@ -453,7 +453,8 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); @@ -525,7 +526,8 @@ if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return false; } Modified: llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.h?rev=64133&r1=64132&r2=64133&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.h (original) +++ llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.h Mon Feb 9 04:54:06 2009 @@ -166,7 +166,8 @@ /// Branch Analysis virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=64133&r1=64132&r2=64133&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp Mon Feb 9 04:54:06 2009 @@ -204,7 +204,8 @@ // Branch analysis. bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) @@ -253,7 +254,8 @@ LastInst->getOpcode() == PPC::B) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return false; } Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h?rev=64133&r1=64132&r2=64133&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h (original) +++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h Mon Feb 9 04:54:06 2009 @@ -104,7 +104,8 @@ // Branch analysis. virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp?rev=64133&r1=64132&r2=64133&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp Mon Feb 9 04:54:06 2009 @@ -1488,7 +1488,8 @@ bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + SmallVectorImpl &Cond, + bool AllowModify) const { // Start from the bottom of the block and work up, examining the // terminator instructions. MachineBasicBlock::iterator I = MBB.end(); @@ -1504,6 +1505,11 @@ return true; // Handle unconditional branches. if (I->getOpcode() == X86::JMP) { + if (!AllowModify) { + TBB = I->getOperand(0).getMBB(); + return false; + } + // If the block has any instructions after a JMP, delete them. while (next(I) != MBB.end()) next(I)->eraseFromParent(); Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.h?rev=64133&r1=64132&r2=64133&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.h (original) +++ llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.h Mon Feb 9 04:54:06 2009 @@ -323,7 +323,8 @@ virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, Modified: llvm/branches/Apple/Dib/lib/Target/XCore/XCoreInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/XCore/XCoreInstrInfo.cpp?rev=64133&r1=64132&r2=64133&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/XCore/XCoreInstrInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/XCore/XCoreInstrInfo.cpp Mon Feb 9 04:54:06 2009 @@ -228,8 +228,9 @@ /// bool XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, - MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) @@ -288,7 +289,8 @@ IsBRU(LastInst->getOpcode())) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return false; } Modified: llvm/branches/Apple/Dib/lib/Target/XCore/XCoreInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/XCore/XCoreInstrInfo.h?rev=64133&r1=64132&r2=64133&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/XCore/XCoreInstrInfo.h (original) +++ llvm/branches/Apple/Dib/lib/Target/XCore/XCoreInstrInfo.h Mon Feb 9 04:54:06 2009 @@ -56,7 +56,8 @@ virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, From isanbard at gmail.com Mon Feb 9 04:54:59 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 09 Feb 2009 10:54:59 -0000 Subject: [llvm-commits] [llvm] r64134 - /llvm/branches/Apple/Dib/lib/CodeGen/SimpleRegisterCoalescing.cpp Message-ID: <200902091054.n19AsxbU022475@zion.cs.uiuc.edu> Author: void Date: Mon Feb 9 04:54:59 2009 New Revision: 64134 URL: http://llvm.org/viewvc/llvm-project?rev=64134&view=rev Log: Pull r64125 into Dib: Fix another case ShortenDeadCopySrcLiveRange is shortening too much. No test case possible since I don't know what to grep for. :-( Modified: llvm/branches/Apple/Dib/lib/CodeGen/SimpleRegisterCoalescing.cpp Modified: llvm/branches/Apple/Dib/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=64134&r1=64133&r2=64134&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SimpleRegisterCoalescing.cpp Mon Feb 9 04:54:59 2009 @@ -861,22 +861,29 @@ // If there is a last use in the same bb, we can't remove the live range. // Shorten the live interval and return. - if (TrimLiveIntervalToLastUse(CopyIdx, CopyMI->getParent(), li, LR)) + MachineBasicBlock *CopyMBB = CopyMI->getParent(); + if (TrimLiveIntervalToLastUse(CopyIdx, CopyMBB, li, LR)) return false; + MachineBasicBlock *StartMBB = li_->getMBBFromIndex(RemoveStart); + if (!isSameOrFallThroughBB(StartMBB, CopyMBB, tii_)) + // If the live range starts in another mbb and the copy mbb is not a fall + // through mbb, then we can only cut the range from the beginning of the + // copy mbb. + RemoveStart = li_->getMBBStartIdx(CopyMBB) + 1; + if (LR->valno->def == RemoveStart) { // If the def MI defines the val# and this copy is the only kill of the // val#, then propagate the dead marker. - if (!li.isOnlyLROfValNo(LR)) { - if (li.isKill(LR->valno, RemoveEnd)) - li.removeKill(LR->valno, RemoveEnd); - } else { + if (li.isOnlyLROfValNo(LR)) { PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_); ++numDeadValNo; } + if (li.isKill(LR->valno, RemoveEnd)) + li.removeKill(LR->valno, RemoveEnd); } - removeRange(li, RemoveStart, LR->end, li_, tri_); + removeRange(li, RemoveStart, RemoveEnd, li_, tri_); return removeIntervalIfEmpty(li, li_, tri_); } From isanbard at gmail.com Mon Feb 9 04:56:41 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 09 Feb 2009 10:56:41 -0000 Subject: [llvm-commits] [llvm] r64135 - in /llvm/branches/Apple/Dib: lib/CodeGen/LLVMTargetMachine.cpp test/CodeGen/ARM/lsr-code-insertion.ll test/CodeGen/X86/2006-05-11-InstrSched.ll test/CodeGen/X86/2009-02-07-CoalescerBug.ll Message-ID: <200902091056.n19Aufeb022534@zion.cs.uiuc.edu> Author: void Date: Mon Feb 9 04:56:40 2009 New Revision: 64135 URL: http://llvm.org/viewvc/llvm-project?rev=64135&view=rev Log: Pull r64126 into Dib: Re-enable machine sinking pass now that the coalescer bugs and the AnalyzeBrnach bug are fixed. Modified: llvm/branches/Apple/Dib/lib/CodeGen/LLVMTargetMachine.cpp llvm/branches/Apple/Dib/test/CodeGen/ARM/lsr-code-insertion.ll llvm/branches/Apple/Dib/test/CodeGen/X86/2006-05-11-InstrSched.ll llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-07-CoalescerBug.ll Modified: llvm/branches/Apple/Dib/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/LLVMTargetMachine.cpp?rev=64135&r1=64134&r2=64135&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/LLVMTargetMachine.cpp Mon Feb 9 04:56:40 2009 @@ -38,11 +38,6 @@ static cl::opt PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data")); -// Hidden options to help debugging -static cl::opt -EnableSinking("enable-sinking", cl::init(false), cl::Hidden, - cl::desc("Perform sinking on machine code")); - // When this works it will be on by default. static cl::opt DisablePostRAScheduler("disable-post-RA-scheduler", @@ -183,11 +178,10 @@ if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (!Fast) + if (!Fast) { PM.add(createMachineLICMPass()); - - if (EnableSinking) PM.add(createMachineSinkingPass()); + } // Run pre-ra passes. if (addPreRegAlloc(PM, Fast) && PrintMachineCode) Modified: llvm/branches/Apple/Dib/test/CodeGen/ARM/lsr-code-insertion.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/ARM/lsr-code-insertion.ll?rev=64135&r1=64134&r2=64135&view=diff ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/ARM/lsr-code-insertion.ll (original) +++ llvm/branches/Apple/Dib/test/CodeGen/ARM/lsr-code-insertion.ll Mon Feb 9 04:56:40 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -stats |& grep {39.*Number of machine instrs printed} +; RUN: llvm-as < %s | llc -stats |& grep {40.*Number of machine instrs printed} ; RUN: llvm-as < %s | llc -stats |& grep {.*Number of re-materialization} ; This test really wants to check that the resultant "cond_true" block only ; has a single store in it, and that cond_true55 only has code to materialize Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/2006-05-11-InstrSched.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/2006-05-11-InstrSched.ll?rev=64135&r1=64134&r2=64135&view=diff ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/X86/2006-05-11-InstrSched.ll (original) +++ llvm/branches/Apple/Dib/test/CodeGen/X86/2006-05-11-InstrSched.ll Mon Feb 9 04:56:40 2009 @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats -realign-stack=0 |&\ -; RUN: grep {asm-printer} | grep 32 +; RUN: grep {asm-printer} | grep 31 target datalayout = "e-p:32:32" define void @foo(i32* %mc, i32* %bp, i32* %ms, i32* %xmb, i32* %mpp, i32* %tpmm, i32* %ip, i32* %tpim, i32* %dpp, i32* %tpdm, i32* %bpi, i32 %M) nounwind { Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-07-CoalescerBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-07-CoalescerBug.ll?rev=64135&r1=64134&r2=64135&view=diff ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-07-CoalescerBug.ll (original) +++ llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-07-CoalescerBug.ll Mon Feb 9 04:56:40 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86 -enable-sinking -relocation-model=pic -stats |& grep {Number of valno def marked dead} | grep 1 +; RUN: llvm-as < %s | llc -march=x86 -relocation-model=pic -stats |& grep {Number of valno def marked dead} | grep 1 ; rdar://6566708 target triple = "i386-apple-darwin9.6" From isanbard at gmail.com Mon Feb 9 06:31:27 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 09 Feb 2009 12:31:27 -0000 Subject: [llvm-commits] [llvm] r64136 - in /llvm/trunk/include/llvm/ADT: APInt.h APSInt.h Message-ID: <200902091231.n19CVSwl025669@zion.cs.uiuc.edu> Author: void Date: Mon Feb 9 06:31:26 2009 New Revision: 64136 URL: http://llvm.org/viewvc/llvm-project?rev=64136&view=rev Log: These function return 'void'. Don't have 'return' return anything. Modified: llvm/trunk/include/llvm/ADT/APInt.h llvm/trunk/include/llvm/ADT/APSInt.h Modified: llvm/trunk/include/llvm/ADT/APInt.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/APInt.h?rev=64136&r1=64135&r2=64136&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/APInt.h (original) +++ llvm/trunk/include/llvm/ADT/APInt.h Mon Feb 9 06:31:26 2009 @@ -1125,13 +1125,13 @@ /// Considers the APInt to be unsigned and converts it into a string in the /// radix given. The radix can be 2, 8, 10 or 16. void toStringUnsigned(SmallVectorImpl &Str, unsigned Radix = 10) const { - return toString(Str, Radix, false); + toString(Str, Radix, false); } /// Considers the APInt to be signed and converts it into a string in the /// radix given. The radix can be 2, 8, 10 or 16. void toStringSigned(SmallVectorImpl &Str, unsigned Radix = 10) const { - return toString(Str, Radix, true); + toString(Str, Radix, true); } /// toString - This returns the APInt as a std::string. Note that this is an Modified: llvm/trunk/include/llvm/ADT/APSInt.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/APSInt.h?rev=64136&r1=64135&r2=64136&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/APSInt.h (original) +++ llvm/trunk/include/llvm/ADT/APSInt.h Mon Feb 9 06:31:26 2009 @@ -59,7 +59,7 @@ /// toString - Append this APSInt to the specified SmallString. void toString(SmallVectorImpl &Str, unsigned Radix = 10) const { - return APInt::toString(Str, Radix, isSigned()); + APInt::toString(Str, Radix, isSigned()); } /// toString - Converts an APInt to a std::string. This is an inefficient /// method, your should prefer passing in a SmallString instead. From isanbard at gmail.com Mon Feb 9 06:31:41 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 09 Feb 2009 12:31:41 -0000 Subject: [llvm-commits] [llvm] r64137 - /llvm/trunk/unittests/ADT/APInt.cpp Message-ID: <200902091231.n19CVfZt025686@zion.cs.uiuc.edu> Author: void Date: Mon Feb 9 06:31:40 2009 New Revision: 64137 URL: http://llvm.org/viewvc/llvm-project?rev=64137&view=rev Log: Fix comment. Modified: llvm/trunk/unittests/ADT/APInt.cpp Modified: llvm/trunk/unittests/ADT/APInt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/APInt.cpp?rev=64137&r1=64136&r2=64137&view=diff ============================================================================== --- llvm/trunk/unittests/ADT/APInt.cpp (original) +++ llvm/trunk/unittests/ADT/APInt.cpp Mon Feb 9 06:31:40 2009 @@ -1,4 +1,4 @@ -//===- llvm/unittest/ADT/APInt.cpp - APInt unit tests -----------*- C++ -*-===// +//===- llvm/unittest/ADT/APInt.cpp - APInt unit tests ---------------------===// // // The LLVM Compiler Infrastructure // From ggreif at gmail.com Mon Feb 9 09:45:07 2009 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 09 Feb 2009 15:45:07 -0000 Subject: [llvm-commits] [llvm] r64142 - in /llvm/trunk: include/llvm/Instructions.h lib/VMCore/AsmWriter.cpp Message-ID: <200902091545.n19Fj8E5032006@zion.cs.uiuc.edu> Author: ggreif Date: Mon Feb 9 09:45:06 2009 New Revision: 64142 URL: http://llvm.org/viewvc/llvm-project?rev=64142&view=rev Log: make sure that BranchInst::getSuccessor() does not assert in cast<> even if the underlying operand is NULL. This may happen in debugging context within opt with partial loop unrolling (see test/Transforms/LoopUnroll/partial.ll). After this fix I can resubmit the (backed out) r63459: * lib/VMCore/AsmWriter.cpp: use precise accessors. Modified: llvm/trunk/include/llvm/Instructions.h llvm/trunk/lib/VMCore/AsmWriter.cpp Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=64142&r1=64141&r2=64142&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Mon Feb 9 09:45:06 2009 @@ -2186,7 +2186,9 @@ BasicBlock *getSuccessor(unsigned i) const { assert(i < getNumSuccessors() && "Successor # out of range for Branch!"); - return cast(getOperand(i)); + if (Value *V = getOperand(i)) + return cast(V); + return 0; } void setSuccessor(unsigned idx, BasicBlock *NewSucc) { Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=64142&r1=64141&r2=64142&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Mon Feb 9 09:45:06 2009 @@ -1505,13 +1505,14 @@ const Value *Operand = I.getNumOperands() ? I.getOperand(0) : 0; // Special case conditional branches to swizzle the condition out to the front - if (isa(I) && I.getNumOperands() > 1) { + if (isa(I) && cast(I).isConditional()) { + BranchInst &BI(cast(I)); Out << ' '; - writeOperand(I.getOperand(2), true); + writeOperand(BI.getCondition(), true); Out << ", "; - writeOperand(Operand, true); + writeOperand(BI.getSuccessor(0), true); Out << ", "; - writeOperand(I.getOperand(1), true); + writeOperand(BI.getSuccessor(1), true); } else if (isa(I)) { // Special case switch statement to get formatting nice and correct... From nicholas at mxc.ca Mon Feb 9 11:06:49 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 09 Feb 2009 09:06:49 -0800 Subject: [llvm-commits] [llvm] r64142 - in /llvm/trunk: include/llvm/Instructions.h lib/VMCore/AsmWriter.cpp In-Reply-To: <200902091545.n19Fj8E5032006@zion.cs.uiuc.edu> References: <200902091545.n19Fj8E5032006@zion.cs.uiuc.edu> Message-ID: <499062A9.5000703@mxc.ca> Gabor Greif wrote: > Author: ggreif > Date: Mon Feb 9 09:45:06 2009 > New Revision: 64142 > > URL: http://llvm.org/viewvc/llvm-project?rev=64142&view=rev > Log: > make sure that BranchInst::getSuccessor() does not assert in cast<> > even if the underlying operand is NULL. This may happen in debugging context > within opt with partial loop unrolling (see test/Transforms/LoopUnroll/partial.ll). > After this fix I can resubmit the (backed out) r63459: > * lib/VMCore/AsmWriter.cpp: use precise accessors. > > Modified: > llvm/trunk/include/llvm/Instructions.h > llvm/trunk/lib/VMCore/AsmWriter.cpp > > Modified: llvm/trunk/include/llvm/Instructions.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=64142&r1=64141&r2=64142&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/Instructions.h (original) > +++ llvm/trunk/include/llvm/Instructions.h Mon Feb 9 09:45:06 2009 > @@ -2186,7 +2186,9 @@ > > BasicBlock *getSuccessor(unsigned i) const { > assert(i < getNumSuccessors() && "Successor # out of range for Branch!"); > - return cast(getOperand(i)); > + if (Value *V = getOperand(i)) > + return cast(V); > + return 0; return cast_or_null(getOperand(i)); Nick > } > > void setSuccessor(unsigned idx, BasicBlock *NewSucc) { > > Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=64142&r1=64141&r2=64142&view=diff > > ============================================================================== > --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) > +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Mon Feb 9 09:45:06 2009 > @@ -1505,13 +1505,14 @@ > const Value *Operand = I.getNumOperands() ? I.getOperand(0) : 0; > > // Special case conditional branches to swizzle the condition out to the front > - if (isa(I) && I.getNumOperands() > 1) { > + if (isa(I) && cast(I).isConditional()) { > + BranchInst &BI(cast(I)); > Out << ' '; > - writeOperand(I.getOperand(2), true); > + writeOperand(BI.getCondition(), true); > Out << ", "; > - writeOperand(Operand, true); > + writeOperand(BI.getSuccessor(0), true); > Out << ", "; > - writeOperand(I.getOperand(1), true); > + writeOperand(BI.getSuccessor(1), true); > > } else if (isa(I)) { > // Special case switch statement to get formatting nice and correct... > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From foldr at codedgers.com Mon Feb 9 11:11:05 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Mon, 09 Feb 2009 17:11:05 -0000 Subject: [llvm-commits] [llvm] r64147 - in /llvm/trunk/include/llvm: InstrTypes.h Instructions.h Message-ID: <200902091711.n19HB6Io002531@zion.cs.uiuc.edu> Author: foldr Date: Mon Feb 9 11:11:05 2009 New Revision: 64147 URL: http://llvm.org/viewvc/llvm-project?rev=64147&view=rev Log: 80-column violations. Modified: llvm/trunk/include/llvm/InstrTypes.h llvm/trunk/include/llvm/Instructions.h Modified: llvm/trunk/include/llvm/InstrTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InstrTypes.h?rev=64147&r1=64146&r2=64147&view=diff ============================================================================== --- llvm/trunk/include/llvm/InstrTypes.h (original) +++ llvm/trunk/include/llvm/InstrTypes.h Mon Feb 9 11:11:05 2009 @@ -90,7 +90,8 @@ UnaryInstruction(const UnaryInstruction&); // Do not implement protected: - UnaryInstruction(const Type *Ty, unsigned iType, Value *V, Instruction *IB = 0) + UnaryInstruction(const Type *Ty, unsigned iType, Value *V, + Instruction *IB = 0) : Instruction(Ty, iType, &Op<0>(), 1, IB) { Op<0>() = V; } @@ -109,7 +110,7 @@ /// Transparently provide more efficient getOperand methods. DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); - + // Methods for support type inquiry through isa, cast, and dyn_cast: static inline bool classof(const UnaryInstruction *) { return true; } static inline bool classof(const Instruction *I) { @@ -266,22 +267,22 @@ : UnaryInstruction(CI.getType(), CI.getOpcode(), CI.getOperand(0)) { } /// @brief Do not allow default construction - CastInst(); + CastInst(); protected: /// @brief Constructor with insert-before-instruction semantics for subclasses - CastInst(const Type *Ty, unsigned iType, Value *S, + CastInst(const Type *Ty, unsigned iType, Value *S, const std::string &NameStr = "", Instruction *InsertBefore = 0) : UnaryInstruction(Ty, iType, S, InsertBefore) { setName(NameStr); } /// @brief Constructor with insert-at-end-of-block semantics for subclasses - CastInst(const Type *Ty, unsigned iType, Value *S, + CastInst(const Type *Ty, unsigned iType, Value *S, const std::string &NameStr, BasicBlock *InsertAtEnd) : UnaryInstruction(Ty, iType, S, InsertAtEnd) { setName(NameStr); } public: - /// Provides a way to construct any of the CastInst subclasses using an + /// Provides a way to construct any of the CastInst subclasses using an /// opcode instead of the subclass's constructor. The opcode must be in the /// CastOps category (Instruction::isCast(opcode) returns true). This /// constructor has insert-before-instruction semantics to automatically @@ -376,7 +377,7 @@ /// @brief Create an FPExt, BitCast, or FPTrunc for fp -> fp casts static CastInst *CreateFPCast( - Value *S, ///< The floating point value to be casted + Value *S, ///< The floating point value to be casted const Type *Ty, ///< The floating point type to cast to const std::string &Name = "", ///< Name for the instruction Instruction *InsertBefore = 0 ///< Place to insert the instruction @@ -384,7 +385,7 @@ /// @brief Create an FPExt, BitCast, or FPTrunc for fp -> fp casts static CastInst *CreateFPCast( - Value *S, ///< The floating point value to be casted + Value *S, ///< The floating point value to be casted const Type *Ty, ///< The floating point type to cast to const std::string &Name, ///< The name for the instruction BasicBlock *InsertAtEnd ///< The block to insert the instruction into @@ -422,7 +423,7 @@ bool DstIsSigned ///< Whether to treate the dest. as signed ); - /// There are several places where we need to know if a cast instruction + /// There are several places where we need to know if a cast instruction /// only deals with integer source and destination types. To simplify that /// logic, this method is provided. /// @returns true iff the cast has only integral typed operand and dest type. @@ -431,20 +432,20 @@ /// A lossless cast is one that does not alter the basic value. It implies /// a no-op cast but is more stringent, preventing things like int->float, - /// long->double, int->ptr, or vector->anything. + /// long->double, int->ptr, or vector->anything. /// @returns true iff the cast is lossless. /// @brief Determine if this is a lossless cast. bool isLosslessCast() const; - /// A no-op cast is one that can be effected without changing any bits. + /// A no-op cast is one that can be effected without changing any bits. /// It implies that the source and destination types are the same size. The - /// IntPtrTy argument is used to make accurate determinations for casts + /// IntPtrTy argument is used to make accurate determinations for casts /// involving Integer and Pointer types. They are no-op casts if the integer - /// is the same size as the pointer. However, pointer size varies with + /// is the same size as the pointer. However, pointer size varies with /// platform. Generally, the result of TargetData::getIntPtrType() should be /// passed in. If that's not available, use Type::Int64Ty, which will make /// the isNoopCast call conservative. - /// @brief Determine if this cast is a no-op cast. + /// @brief Determine if this cast is a no-op cast. bool isNoopCast( const Type *IntPtrTy ///< Integer type corresponding to pointer ) const; @@ -452,7 +453,7 @@ /// Determine how a pair of casts can be eliminated, if they can be at all. /// This is a helper function for both CastInst and ConstantExpr. /// @returns 0 if the CastInst pair can't be eliminated - /// @returns Instruction::CastOps value for a cast that can replace + /// @returns Instruction::CastOps value for a cast that can replace /// the pair, casting SrcTy to DstTy. /// @brief Determine if a cast pair is eliminable static unsigned isEliminableCastPair( @@ -465,8 +466,8 @@ ); /// @brief Return the opcode of this CastInst - Instruction::CastOps getOpcode() const { - return Instruction::CastOps(Instruction::getOpcode()); + Instruction::CastOps getOpcode() const { + return Instruction::CastOps(Instruction::getOpcode()); } /// @brief Return the source type, as a convenience @@ -475,7 +476,7 @@ const Type* getDestTy() const { return getType(); } /// This method can be used to determine if a cast from S to DstTy using - /// Opcode op is valid or not. + /// Opcode op is valid or not. /// @returns true iff the proposed cast is valid. /// @brief Determine if a cast is valid without creating one. static bool castIsValid(Instruction::CastOps op, Value *S, const Type *DstTy); @@ -494,7 +495,7 @@ // CmpInst Class //===----------------------------------------------------------------------===// -/// This class is the base class for the comparison instructions. +/// This class is the base class for the comparison instructions. /// @brief Abstract base class of comparison instructions. // FIXME: why not derive from BinaryOperator? class CmpInst: public Instruction { @@ -504,7 +505,7 @@ CmpInst(const Type *ty, Instruction::OtherOps op, unsigned short pred, Value *LHS, Value *RHS, const std::string &Name = "", Instruction *InsertBefore = 0); - + CmpInst(const Type *ty, Instruction::OtherOps op, unsigned short pred, Value *LHS, Value *RHS, const std::string &Name, BasicBlock *InsertAtEnd); @@ -554,21 +555,21 @@ void *operator new(size_t s) { return User::operator new(s, 2); } - /// Construct a compare instruction, given the opcode, the predicate and - /// the two operands. Optionally (if InstBefore is specified) insert the - /// instruction into a BasicBlock right before the specified instruction. + /// Construct a compare instruction, given the opcode, the predicate and + /// the two operands. Optionally (if InstBefore is specified) insert the + /// instruction into a BasicBlock right before the specified instruction. /// The specified Instruction is allowed to be a dereferenced end iterator. /// @brief Create a CmpInst - static CmpInst *Create(OtherOps Op, unsigned short predicate, Value *S1, + static CmpInst *Create(OtherOps Op, unsigned short predicate, Value *S1, Value *S2, const std::string &Name = "", Instruction *InsertBefore = 0); - /// Construct a compare instruction, given the opcode, the predicate and the - /// two operands. Also automatically insert this instruction to the end of + /// Construct a compare instruction, given the opcode, the predicate and the + /// two operands. Also automatically insert this instruction to the end of /// the BasicBlock specified. /// @brief Create a CmpInst - static CmpInst *Create(OtherOps Op, unsigned short predicate, Value *S1, - Value *S2, const std::string &Name, + static CmpInst *Create(OtherOps Op, unsigned short predicate, Value *S1, + Value *S2, const std::string &Name, BasicBlock *InsertAtEnd); /// @brief Get the opcode casted to the right type @@ -581,10 +582,10 @@ /// @brief Set the predicate for this instruction to the specified value. void setPredicate(Predicate P) { SubclassData = P; } - + /// For example, EQ -> NE, UGT -> ULE, SLT -> SGE, /// OEQ -> UNE, UGT -> OLE, OLT -> UGE, etc. - /// @returns the inverse predicate for the instruction's current predicate. + /// @returns the inverse predicate for the instruction's current predicate. /// @brief Return the inverse of the instruction's predicate. Predicate getInversePredicate() const { return getInversePredicate(getPredicate()); @@ -592,21 +593,21 @@ /// For example, EQ -> NE, UGT -> ULE, SLT -> SGE, /// OEQ -> UNE, UGT -> OLE, OLT -> UGE, etc. - /// @returns the inverse predicate for predicate provided in \p pred. + /// @returns the inverse predicate for predicate provided in \p pred. /// @brief Return the inverse of a given predicate static Predicate getInversePredicate(Predicate pred); /// For example, EQ->EQ, SLE->SGE, ULT->UGT, /// OEQ->OEQ, ULE->UGE, OLT->OGT, etc. - /// @returns the predicate that would be the result of exchanging the two - /// operands of the CmpInst instruction without changing the result - /// produced. + /// @returns the predicate that would be the result of exchanging the two + /// operands of the CmpInst instruction without changing the result + /// produced. /// @brief Return the predicate as if the operands were swapped Predicate getSwappedPredicate() const { return getSwappedPredicate(getPredicate()); } - /// This is a static version that you can use without an instruction + /// This is a static version that you can use without an instruction /// available. /// @brief Return the predicate as if the operands were swapped. static Predicate getSwappedPredicate(Predicate pred); @@ -644,7 +645,7 @@ /// @brief Methods for support type inquiry through isa, cast, and dyn_cast: static inline bool classof(const CmpInst *) { return true; } static inline bool classof(const Instruction *I) { - return I->getOpcode() == Instruction::ICmp || + return I->getOpcode() == Instruction::ICmp || I->getOpcode() == Instruction::FCmp || I->getOpcode() == Instruction::VICmp || I->getOpcode() == Instruction::VFCmp; Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=64147&r1=64146&r2=64147&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Mon Feb 9 11:11:05 2009 @@ -164,7 +164,7 @@ : AllocationInst(Ty, ArraySize, Alloca, Align, NameStr, InsertAtEnd) {} virtual AllocaInst *clone() const; - + /// isStaticAlloca - Return true if this alloca is in the entry block of the /// function and is a constant size. If so, the code generator will fold it /// into the prolog/epilog code, so it is basically free. @@ -194,7 +194,7 @@ FreeInst(Value *Ptr, BasicBlock *InsertAfter); virtual FreeInst *clone() const; - + // Accessor methods for consistency with other memory operations Value *getPointerOperand() { return getOperand(0); } const Value *getPointerOperand() const { return getOperand(0); } @@ -232,7 +232,7 @@ public: LoadInst(Value *Ptr, const std::string &NameStr, Instruction *InsertBefore); LoadInst(Value *Ptr, const std::string &NameStr, BasicBlock *InsertAtEnd); - LoadInst(Value *Ptr, const std::string &NameStr, bool isVolatile = false, + LoadInst(Value *Ptr, const std::string &NameStr, bool isVolatile = false, Instruction *InsertBefore = 0); LoadInst(Value *Ptr, const std::string &NameStr, bool isVolatile, unsigned Align, Instruction *InsertBefore = 0); @@ -247,7 +247,7 @@ bool isVolatile = false, Instruction *InsertBefore = 0); LoadInst(Value *Ptr, const char *NameStr, bool isVolatile, BasicBlock *InsertAtEnd); - + /// isVolatile - Return true if this is a load from a volatile memory /// location. /// @@ -255,8 +255,8 @@ /// setVolatile - Specify whether this is a volatile load or not. /// - void setVolatile(bool V) { - SubclassData = (SubclassData & ~1) | (V ? 1 : 0); + void setVolatile(bool V) { + SubclassData = (SubclassData & ~1) | (V ? 1 : 0); } virtual LoadInst *clone() const; @@ -266,7 +266,7 @@ unsigned getAlignment() const { return (1 << (SubclassData>>1)) >> 1; } - + void setAlignment(unsigned Align); Value *getPointerOperand() { return getOperand(0); } @@ -292,14 +292,14 @@ /// class StoreInst : public Instruction { void *operator new(size_t, unsigned); // DO NOT IMPLEMENT - + StoreInst(const StoreInst &SI) : Instruction(SI.getType(), Store, &Op<0>(), 2) { Op<0>() = SI.Op<0>(); Op<1>() = SI.Op<1>(); setVolatile(SI.isVolatile()); setAlignment(SI.getAlignment()); - + #ifndef NDEBUG AssertOK(); #endif @@ -328,8 +328,8 @@ /// setVolatile - Specify whether this is a volatile load or not. /// - void setVolatile(bool V) { - SubclassData = (SubclassData & ~1) | (V ? 1 : 0); + void setVolatile(bool V) { + SubclassData = (SubclassData & ~1) | (V ? 1 : 0); } /// Transparently provide more efficient getOperand methods. @@ -340,9 +340,9 @@ unsigned getAlignment() const { return (1 << (SubclassData>>1)) >> 1; } - + void setAlignment(unsigned Align); - + virtual StoreInst *clone() const; Value *getPointerOperand() { return getOperand(1); } @@ -393,7 +393,7 @@ // do arithmetic on in constant time std::random_access_iterator_tag) { unsigned NumIdx = static_cast(std::distance(IdxBegin, IdxEnd)); - + if (NumIdx > 0) { // This requires that the iterator points to contiguous memory. init(Ptr, &*IdxBegin, NumIdx, NameStr); // FIXME: for the general case @@ -412,7 +412,7 @@ /// template static const Type *getIndexedType(const Type *Ptr, - InputIterator IdxBegin, + InputIterator IdxBegin, InputIterator IdxEnd, // This argument ensures that we // have an iterator we can do @@ -432,7 +432,7 @@ /// instruction, the second appends the new instruction to the specified /// BasicBlock. template - inline GetElementPtrInst(Value *Ptr, InputIterator IdxBegin, + inline GetElementPtrInst(Value *Ptr, InputIterator IdxBegin, InputIterator IdxEnd, unsigned Values, const std::string &NameStr, @@ -451,11 +451,11 @@ const std::string &NameStr, BasicBlock *InsertAtEnd); public: template - static GetElementPtrInst *Create(Value *Ptr, InputIterator IdxBegin, + static GetElementPtrInst *Create(Value *Ptr, InputIterator IdxBegin, InputIterator IdxEnd, const std::string &NameStr = "", Instruction *InsertBefore = 0) { - typename std::iterator_traits::difference_type Values = + typename std::iterator_traits::difference_type Values = 1 + std::distance(IdxBegin, IdxEnd); return new(Values) GetElementPtrInst(Ptr, IdxBegin, IdxEnd, Values, NameStr, InsertBefore); @@ -465,7 +465,7 @@ InputIterator IdxBegin, InputIterator IdxEnd, const std::string &NameStr, BasicBlock *InsertAtEnd) { - typename std::iterator_traits::difference_type Values = + typename std::iterator_traits::difference_type Values = 1 + std::distance(IdxBegin, IdxEnd); return new(Values) GetElementPtrInst(Ptr, IdxBegin, IdxEnd, Values, NameStr, InsertAtEnd); @@ -507,7 +507,7 @@ return getIndexedType(Ptr, IdxBegin, IdxEnd, typename std::iterator_traits:: iterator_category()); - } + } static const Type *getIndexedType(const Type *Ptr, Value* const *Idx, unsigned NumIdx); @@ -531,13 +531,13 @@ static unsigned getPointerOperandIndex() { return 0U; // get index for modifying correct operand } - + /// getPointerOperandType - Method to return the pointer operand as a /// PointerType. const PointerType *getPointerOperandType() const { return reinterpret_cast(getPointerOperand()->getType()); } - + unsigned getNumIndices() const { // Note: always non-negative return getNumOperands() - 1; @@ -546,17 +546,17 @@ bool hasIndices() const { return getNumOperands() > 1; } - + /// hasAllZeroIndices - Return true if all of the indices of this GEP are /// zeros. If so, the result pointer and the first operand have the same /// value, just potentially different types. bool hasAllZeroIndices() const; - + /// hasAllConstantIndices - Return true if all of the indices of this GEP are /// constant integers. If so, the result pointer and the first operand have /// a constant offset between them. bool hasAllConstantIndices() const; - + // Methods for support type inquiry through isa, cast, and dyn_cast: static inline bool classof(const GetElementPtrInst *) { return true; } @@ -574,7 +574,7 @@ template GetElementPtrInst::GetElementPtrInst(Value *Ptr, - InputIterator IdxBegin, + InputIterator IdxBegin, InputIterator IdxEnd, unsigned Values, const std::string &NameStr, @@ -639,7 +639,7 @@ assert(getOperand(0)->getType() == getOperand(1)->getType() && "Both operands to ICmp instruction are not of the same type!"); // Check that the operands are the right type - assert((getOperand(0)->getType()->isIntOrIntVector() || + assert((getOperand(0)->getType()->isIntOrIntVector() || isa(getOperand(0)->getType())) && "Invalid operand types for ICmp instruction"); } @@ -660,7 +660,7 @@ assert(getOperand(0)->getType() == getOperand(1)->getType() && "Both operands to ICmp instruction are not of the same type!"); // Check that the operands are the right type - assert((getOperand(0)->getType()->isIntOrIntVector() || + assert((getOperand(0)->getType()->isIntOrIntVector() || isa(getOperand(0)->getType())) && "Invalid operand types for ICmp instruction"); } @@ -694,7 +694,7 @@ static bool isEquality(Predicate P) { return P == ICMP_EQ || P == ICMP_NE; } - + /// isEquality - Return true if this predicate is either EQ or NE. This also /// tests for commutativity. bool isEquality() const { @@ -705,18 +705,18 @@ /// @brief Determine if this relation is commutative. bool isCommutative() const { return isEquality(); } - /// isRelational - Return true if the predicate is relational (not EQ or NE). + /// isRelational - Return true if the predicate is relational (not EQ or NE). /// bool isRelational() const { return !isEquality(); } - /// isRelational - Return true if the predicate is relational (not EQ or NE). + /// isRelational - Return true if the predicate is relational (not EQ or NE). /// static bool isRelational(Predicate P) { return !isEquality(P); } - + /// @returns true if the predicate of this ICmpInst is signed, false otherwise /// @brief Determine if this instruction's predicate is signed. bool isSignedPredicate() const { return isSignedPredicate(getPredicate()); } @@ -741,14 +741,14 @@ return isTrueWhenEqual(getPredicate()); } - /// Initialize a set of values that all satisfy the predicate with C. + /// Initialize a set of values that all satisfy the predicate with C. /// @brief Make a ConstantRange for a relation with a constant value. static ConstantRange makeConstantRange(Predicate pred, const APInt &C); /// Exchange the two operands to this instruction in such a way that it does /// not modify the semantics of the instruction. The predicate value may be /// changed to retain the same result if the predicate is order dependent - /// (e.g. ult). + /// (e.g. ult). /// @brief Swap operands and adjust predicate. void swapOperands() { SubclassData = getSwappedPredicate(); @@ -773,7 +773,7 @@ //===----------------------------------------------------------------------===// /// This instruction compares its operands according to the predicate given -/// to the constructor. It only operates on floating point values or packed +/// to the constructor. It only operates on floating point values or packed /// vectors of floating point values. The operands must be identical types. /// @brief Represents a floating point comparison operator. class FCmpInst: public CmpInst { @@ -833,14 +833,14 @@ SubclassData == FCMP_UNO; } - /// @returns true if the predicate is relational (not EQ or NE). + /// @returns true if the predicate is relational (not EQ or NE). /// @brief Determine if this a relational predicate. bool isRelational() const { return !isEquality(); } /// Exchange the two operands to this instruction in such a way that it does /// not modify the semantics of the instruction. The predicate value may be /// changed to retain the same result if the predicate is order dependent - /// (e.g. ult). + /// (e.g. ult). /// @brief Swap operands and adjust predicate. void swapOperands() { SubclassData = getSwappedPredicate(); @@ -857,7 +857,7 @@ static inline bool classof(const Value *V) { return isa(V) && classof(cast(V)); } - + }; //===----------------------------------------------------------------------===// @@ -901,7 +901,7 @@ assert(getOperand(0)->getType() == getOperand(1)->getType() && "Both operands to VICmp instruction are not of the same type!"); } - + /// @brief Return the predicate for this instruction. Predicate getPredicate() const { return Predicate(SubclassData); } @@ -996,7 +996,7 @@ // do arithmetic on in constant time std::random_access_iterator_tag) { unsigned NumArgs = (unsigned)std::distance(ArgBegin, ArgEnd); - + // This requires that the iterator points to contiguous memory. init(Func, NumArgs ? &*ArgBegin : 0, NumArgs); setName(NameStr); @@ -1074,7 +1074,7 @@ /// Provide fast operand accessors DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); - + /// getCallingConv/setCallingConv - Get or set the calling convention of this /// function call. unsigned getCallingConv() const { return SubclassData >> 1; } @@ -1089,7 +1089,7 @@ /// setAttributes - Set the parameter attributes for this call. /// void setAttributes(const AttrListPtr &Attrs) { AttributeList = Attrs; } - + /// addAttribute - adds the attribute to the list of attributes. void addAttribute(unsigned i, Attributes attr); @@ -1140,7 +1140,7 @@ else removeAttribute(~0, Attribute::NoUnwind); } - /// @brief Determine if the call returns a structure through first + /// @brief Determine if the call returns a structure through first /// pointer argument. bool hasStructRetAttr() const { // Be friendly and also check the callee. @@ -1159,7 +1159,7 @@ return dyn_cast(getOperand(0)); } - /// getCalledValue - Get a pointer to the function that is invoked by this + /// getCalledValue - Get a pointer to the function that is invoked by this /// instruction const Value *getCalledValue() const { return getOperand(0); } Value *getCalledValue() { return getOperand(0); } @@ -1198,7 +1198,7 @@ Instruction::Call, OperandTraits::op_end(this) - (ArgEnd - ArgBegin + 1), (unsigned)(ArgEnd - ArgBegin + 1), InsertBefore) { - init(Func, ArgBegin, ArgEnd, NameStr, + init(Func, ArgBegin, ArgEnd, NameStr, typename std::iterator_traits::iterator_category()); } @@ -1251,7 +1251,7 @@ Value *getCondition() const { return Op<0>(); } Value *getTrueValue() const { return Op<1>(); } Value *getFalseValue() const { return Op<2>(); } - + /// areInvalidOperands - Return a string if the specified operands are invalid /// for a select operation, otherwise return null. static const char *areInvalidOperands(Value *Cond, Value *True, Value *False); @@ -1378,9 +1378,11 @@ class InsertElementInst : public Instruction { InsertElementInst(const InsertElementInst &IE); InsertElementInst(Value *Vec, Value *NewElt, Value *Idx, - const std::string &NameStr = "",Instruction *InsertBefore = 0); + const std::string &NameStr = "", + Instruction *InsertBefore = 0); InsertElementInst(Value *Vec, Value *NewElt, unsigned Idx, - const std::string &NameStr = "",Instruction *InsertBefore = 0); + const std::string &NameStr = "", + Instruction *InsertBefore = 0); InsertElementInst(Value *Vec, Value *NewElt, Value *Idx, const std::string &NameStr, BasicBlock *InsertAtEnd); InsertElementInst(Value *Vec, Value *NewElt, unsigned Idx, @@ -1477,7 +1479,7 @@ /// Transparently provide more efficient getOperand methods. DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); - + /// getMaskValue - Return the index from the shuffle mask for the specified /// output result. This is either -1 if the element is undef or a number less /// than 2*numelements. @@ -1521,7 +1523,7 @@ // do arithmetic on in constant time std::random_access_iterator_tag) { unsigned NumIdx = static_cast(std::distance(IdxBegin, IdxEnd)); - + // There's no fundamental reason why we require at least one index // (other than weirdness with &*IdxBegin being invalid; see // getelementptr's init routine for example). But there's no @@ -1544,7 +1546,7 @@ template static const Type *getIndexedType(const Type *Ptr, - InputIterator IdxBegin, + InputIterator IdxBegin, InputIterator IdxEnd, // This argument ensures that we // have an iterator we can do @@ -1564,7 +1566,7 @@ /// an existing instruction, the second appends the new instruction to the /// specified BasicBlock. template - inline ExtractValueInst(Value *Agg, InputIterator IdxBegin, + inline ExtractValueInst(Value *Agg, InputIterator IdxBegin, InputIterator IdxEnd, const std::string &NameStr, Instruction *InsertBefore); @@ -1580,7 +1582,7 @@ public: template - static ExtractValueInst *Create(Value *Agg, InputIterator IdxBegin, + static ExtractValueInst *Create(Value *Agg, InputIterator IdxBegin, InputIterator IdxEnd, const std::string &NameStr = "", Instruction *InsertBefore = 0) { @@ -1631,7 +1633,7 @@ return getIndexedType(Ptr, IdxBegin, IdxEnd, typename std::iterator_traits:: iterator_category()); - } + } static const Type *getIndexedType(const Type *Ptr, unsigned Idx); typedef const unsigned* idx_iterator; @@ -1655,7 +1657,7 @@ bool hasIndices() const { return true; } - + // Methods for support type inquiry through isa, cast, and dyn_cast: static inline bool classof(const ExtractValueInst *) { return true; } static inline bool classof(const Instruction *I) { @@ -1668,7 +1670,7 @@ template ExtractValueInst::ExtractValueInst(Value *Agg, - InputIterator IdxBegin, + InputIterator IdxBegin, InputIterator IdxEnd, const std::string &NameStr, Instruction *InsertBefore) @@ -1716,7 +1718,7 @@ // do arithmetic on in constant time std::random_access_iterator_tag) { unsigned NumIdx = static_cast(std::distance(IdxBegin, IdxEnd)); - + // There's no fundamental reason why we require at least one index // (other than weirdness with &*IdxBegin being invalid; see // getelementptr's init routine for example). But there's no @@ -1733,7 +1735,7 @@ /// optionally insert before an existing instruction, the second appends /// the new instruction to the specified BasicBlock. template - inline InsertValueInst(Value *Agg, Value *Val, InputIterator IdxBegin, + inline InsertValueInst(Value *Agg, Value *Val, InputIterator IdxBegin, InputIterator IdxEnd, const std::string &NameStr, Instruction *InsertBefore); @@ -1827,7 +1829,7 @@ bool hasIndices() const { return true; } - + // Methods for support type inquiry through isa, cast, and dyn_cast: static inline bool classof(const InsertValueInst *) { return true; } static inline bool classof(const Instruction *I) { @@ -1845,7 +1847,7 @@ template InsertValueInst::InsertValueInst(Value *Agg, Value *Val, - InputIterator IdxBegin, + InputIterator IdxBegin, InputIterator IdxEnd, const std::string &NameStr, Instruction *InsertBefore) @@ -2030,7 +2032,7 @@ struct OperandTraits : HungoffOperandTraits<2> { }; -DEFINE_TRANSPARENT_OPERAND_ACCESSORS(PHINode, Value) +DEFINE_TRANSPARENT_OPERAND_ACCESSORS(PHINode, Value) //===----------------------------------------------------------------------===// @@ -2246,7 +2248,7 @@ /// constructor can also autoinsert before another instruction. SwitchInst(Value *Value, BasicBlock *Default, unsigned NumCases, Instruction *InsertBefore = 0); - + /// SwitchInst ctor - Create a new switch instruction, specifying a value to /// switch on and a default destination. The number of additional cases can /// be specified here to make memory allocation more efficient. This @@ -2367,7 +2369,7 @@ struct OperandTraits : HungoffOperandTraits<2> { }; -DEFINE_TRANSPARENT_OPERAND_ACCESSORS(SwitchInst, Value) +DEFINE_TRANSPARENT_OPERAND_ACCESSORS(SwitchInst, Value) //===----------------------------------------------------------------------===// @@ -2391,7 +2393,7 @@ // do arithmetic on in constant time std::random_access_iterator_tag) { unsigned NumArgs = (unsigned)std::distance(ArgBegin, ArgEnd); - + // This requires that the iterator points to contiguous memory. init(Func, IfNormal, IfException, NumArgs ? &*ArgBegin : 0, NumArgs); setName(NameStr); @@ -2448,7 +2450,7 @@ /// Provide fast operand accessors DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); - + /// getCallingConv/setCallingConv - Get or set the calling convention of this /// function call. unsigned getCallingConv() const { return SubclassData; } @@ -2472,7 +2474,7 @@ /// @brief Determine whether the call or the callee has the given attribute. bool paramHasAttr(unsigned i, Attributes attr) const; - + /// @brief Extract the alignment for a call or parameter (0=unknown). unsigned getParamAlignment(unsigned i) const { return AttributeList.getParamAlignment(i); @@ -2514,7 +2516,7 @@ else removeAttribute(~0, Attribute::NoUnwind); } - /// @brief Determine if the call returns a structure through first + /// @brief Determine if the call returns a structure through first /// pointer argument. bool hasStructRetAttr() const { // Be friendly and also check the callee. @@ -2533,7 +2535,7 @@ return dyn_cast(getOperand(0)); } - /// getCalledValue - Get a pointer to the function that is invoked by this + /// getCalledValue - Get a pointer to the function that is invoked by this /// instruction const Value *getCalledValue() const { return getOperand(0); } Value *getCalledValue() { return getOperand(0); } From gohman at apple.com Mon Feb 9 11:41:23 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 09 Feb 2009 17:41:23 -0000 Subject: [llvm-commits] [llvm] r64148 - /llvm/trunk/lib/AsmParser/LLParser.cpp Message-ID: <200902091741.n19HfNXD003385@zion.cs.uiuc.edu> Author: djg Date: Mon Feb 9 11:41:21 2009 New Revision: 64148 URL: http://llvm.org/viewvc/llvm-project?rev=64148&view=rev Log: Use slightly more correct grammar in error messages. Modified: llvm/trunk/lib/AsmParser/LLParser.cpp Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=64148&r1=64147&r2=64148&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Mon Feb 9 11:41:21 2009 @@ -1025,7 +1025,7 @@ if (Result.get() == Type::LabelTy) return TokError("basic block pointers are invalid"); if (Result.get() == Type::VoidTy) - return TokError("pointers to void are invalid, use i8* instead"); + return TokError("pointers to void are invalid; use i8* instead"); Result = HandleUpRefs(PointerType::getUnqual(Result.get())); Lex.Lex(); break; @@ -1035,7 +1035,7 @@ if (Result.get() == Type::LabelTy) return TokError("basic block pointers are invalid"); if (Result.get() == Type::VoidTy) - return TokError("pointers to void are invalid, use i8* instead"); + return TokError("pointers to void are invalid; use i8* instead"); unsigned AddrSpace; if (ParseOptionalAddrSpace(AddrSpace) || ParseToken(lltok::star, "expected '*' in address space")) From gohman at apple.com Mon Feb 9 12:12:09 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 09 Feb 2009 18:12:09 -0000 Subject: [llvm-commits] [llvm] r64150 - /llvm/trunk/lib/Target/X86/X86TargetMachine.h Message-ID: <200902091812.n19IC9Xr004325@zion.cs.uiuc.edu> Author: djg Date: Mon Feb 9 12:12:09 2009 New Revision: 64150 URL: http://llvm.org/viewvc/llvm-project?rev=64150&view=rev Log: Use doxygen comment syntax. Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=64150&r1=64149&r2=64150&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Mon Feb 9 12:12:09 2009 @@ -83,10 +83,10 @@ virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast, bool DumpAsm, MachineCodeEmitter &MCE); - // symbolicAddressesAreRIPRel - Return true if symbolic addresses are - // RIP-relative on this machine, taking into consideration the relocation - // model and subtarget. RIP-relative addresses cannot have a separate - // base or index register. + /// symbolicAddressesAreRIPRel - Return true if symbolic addresses are + /// RIP-relative on this machine, taking into consideration the relocation + /// model and subtarget. RIP-relative addresses cannot have a separate + /// base or index register. bool symbolicAddressesAreRIPRel() const; }; From ggreif at gmail.com Mon Feb 9 14:27:45 2009 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 09 Feb 2009 20:27:45 -0000 Subject: [llvm-commits] [llvm] r64158 - /llvm/trunk/include/llvm/Instructions.h Message-ID: <200902092027.n19KRjJj009540@zion.cs.uiuc.edu> Author: ggreif Date: Mon Feb 9 14:27:45 2009 New Revision: 64158 URL: http://llvm.org/viewvc/llvm-project?rev=64158&view=rev Log: incorporate review feedback Modified: llvm/trunk/include/llvm/Instructions.h Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=64158&r1=64157&r2=64158&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Mon Feb 9 14:27:45 2009 @@ -2188,9 +2188,7 @@ BasicBlock *getSuccessor(unsigned i) const { assert(i < getNumSuccessors() && "Successor # out of range for Branch!"); - if (Value *V = getOperand(i)) - return cast(V); - return 0; + return cast_or_null(getOperand(i)); } void setSuccessor(unsigned idx, BasicBlock *NewSucc) { From ggreif at gmail.com Mon Feb 9 14:32:31 2009 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 9 Feb 2009 12:32:31 -0800 (PST) Subject: [llvm-commits] [llvm] r64142 - in /llvm/trunk: include/llvm/Instructions.h lib/VMCore/AsmWriter.cpp In-Reply-To: <499062A9.5000703@mxc.ca> References: <200902091545.n19Fj8E5032006@zion.cs.uiuc.edu> <499062A9.5000703@mxc.ca> Message-ID: <84d1206a-b551-4b2a-aec8-48cdd4d6ccc7@l39g2000yqn.googlegroups.com> On 9 Feb., 18:06, Nick Lewycky wrote: > Gabor Greif wrote: > > Author: ggreif > > Date: Mon Feb ?9 09:45:06 2009 > > New Revision: 64142 > > > URL:http://llvm.org/viewvc/llvm-project?rev=64142&view=rev > > Log: > > make sure that BranchInst::getSuccessor() does not assert in cast<> > > even if the underlying operand is NULL. This may happen in debugging context > > within opt with partial loop unrolling (see test/Transforms/LoopUnroll/partial.ll). > > After this fix I can resubmit the (backed out) r63459: > > * lib/VMCore/AsmWriter.cpp: use precise accessors. > > > Modified: > > ? ? llvm/trunk/include/llvm/Instructions.h > > ? ? llvm/trunk/lib/VMCore/AsmWriter.cpp > > > Modified: llvm/trunk/include/llvm/Instructions.h > > URL:http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructi... > > > =========================================================================== === > > --- llvm/trunk/include/llvm/Instructions.h (original) > > +++ llvm/trunk/include/llvm/Instructions.h Mon Feb ?9 09:45:06 2009 > > @@ -2186,7 +2186,9 @@ > > > ? ?BasicBlock *getSuccessor(unsigned i) const { > > ? ? ?assert(i < getNumSuccessors() && "Successor # out of range for Branch!"); > > - ? ?return cast(getOperand(i)); > > + ? ?if (Value *V = getOperand(i)) > > + ? ? ?return cast(V); > > + ? ?return 0; > > return cast_or_null(getOperand(i)); Thanks, committed! Cheers, Gabor > > Nick > > > > > ? ?} > > > ? ?void setSuccessor(unsigned idx, BasicBlock *NewSucc) { > > > Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp > > URL:http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.c... > > > =========================================================================== === > > --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) > > +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Mon Feb ?9 09:45:06 2009 > > @@ -1505,13 +1505,14 @@ > > ? ?const Value *Operand = I.getNumOperands() ? I.getOperand(0) : 0; > > > ? ?// Special case conditional branches to swizzle the condition out to the front > > - ?if (isa(I) && I.getNumOperands() > 1) { > > + ?if (isa(I) && cast(I).isConditional()) { > > + ? ?BranchInst &BI(cast(I)); > > ? ? ?Out << ' '; > > - ? ?writeOperand(I.getOperand(2), true); > > + ? ?writeOperand(BI.getCondition(), true); > > ? ? ?Out << ", "; > > - ? ?writeOperand(Operand, true); > > + ? ?writeOperand(BI.getSuccessor(0), true); > > ? ? ?Out << ", "; > > - ? ?writeOperand(I.getOperand(1), true); > > + ? ?writeOperand(BI.getSuccessor(1), true); > > > ? ?} else if (isa(I)) { > > ? ? ?// Special case switch statement to get formatting nice and correct... > > > _______________________________________________ > > llvm-commits mailing list > > llvm-comm... at cs.uiuc.edu > >http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-comm... at cs.uiuc.eduhttp://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon Feb 9 14:54:38 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 09 Feb 2009 20:54:38 -0000 Subject: [llvm-commits] [llvm] r64163 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp test/CodeGen/X86/negative-subscript.ll Message-ID: <200902092054.n19Ksc5H010422@zion.cs.uiuc.edu> Author: evancheng Date: Mon Feb 9 14:54:38 2009 New Revision: 64163 URL: http://llvm.org/viewvc/llvm-project?rev=64163&view=rev Log: Make sure constant subscript is truncated to ptr size if it may not fit. Added: llvm/trunk/test/CodeGen/X86/negative-subscript.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=64163&r1=64162&r2=64163&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon Feb 9 14:54:38 2009 @@ -2699,8 +2699,15 @@ if (CI->getZExtValue() == 0) continue; uint64_t Offs = TD->getTypePaddedSize(Ty)*cast(CI)->getSExtValue(); + SDValue OffsVal = DAG.getConstant(Offs, MVT::i64); + unsigned PtrBits = TLI.getPointerTy().getSizeInBits(); + if (PtrBits < 64) + OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), + TLI.getPointerTy(), OffsVal); + else + OffsVal = DAG.getIntPtrConstant(Offs); N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, - DAG.getIntPtrConstant(Offs)); + OffsVal); continue; } Added: llvm/trunk/test/CodeGen/X86/negative-subscript.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/negative-subscript.ll?rev=64163&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/negative-subscript.ll (added) +++ llvm/trunk/test/CodeGen/X86/negative-subscript.ll Mon Feb 9 14:54:38 2009 @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=x86 +; rdar://6559995 + + at a = external global [255 x i8*], align 32 + +define i32 @main() nounwind { +entry: + store i8* bitcast (i8** getelementptr ([255 x i8*]* @a, i32 0, i32 -2147483624) to i8*), i8** getelementptr ([255 x i8*]* @a, i32 0, i32 16), align 32 + ret i32 0 +} From evan.cheng at apple.com Mon Feb 9 15:01:06 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 09 Feb 2009 21:01:06 -0000 Subject: [llvm-commits] [llvm] r64164 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Message-ID: <200902092101.n19L16kv010768@zion.cs.uiuc.edu> Author: evancheng Date: Mon Feb 9 15:01:06 2009 New Revision: 64164 URL: http://llvm.org/viewvc/llvm-project?rev=64164&view=rev Log: Simplify code. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=64164&r1=64163&r2=64164&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon Feb 9 15:01:06 2009 @@ -2699,12 +2699,13 @@ if (CI->getZExtValue() == 0) continue; uint64_t Offs = TD->getTypePaddedSize(Ty)*cast(CI)->getSExtValue(); - SDValue OffsVal = DAG.getConstant(Offs, MVT::i64); + SDValue OffsVal; unsigned PtrBits = TLI.getPointerTy().getSizeInBits(); - if (PtrBits < 64) - OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), - TLI.getPointerTy(), OffsVal); - else + if (PtrBits < 64) { + OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), + TLI.getPointerTy(), + DAG.getConstant(Offs, MVT::i64)); + } else OffsVal = DAG.getIntPtrConstant(Offs); N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, OffsVal); From isanbard at gmail.com Mon Feb 9 15:04:05 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 09 Feb 2009 21:04:05 -0000 Subject: [llvm-commits] [llvm] r64165 - in /llvm/branches/Apple/Dib: lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp test/CodeGen/X86/negative-subscript.ll Message-ID: <200902092104.n19L45qs010877@zion.cs.uiuc.edu> Author: void Date: Mon Feb 9 15:04:05 2009 New Revision: 64165 URL: http://llvm.org/viewvc/llvm-project?rev=64165&view=rev Log: Pull r64163 into Dib: Make sure constant subscript is truncated to ptr size if it may not fit. Added: llvm/branches/Apple/Dib/test/CodeGen/X86/negative-subscript.ll Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=64165&r1=64164&r2=64165&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon Feb 9 15:04:05 2009 @@ -2695,8 +2695,15 @@ if (CI->getZExtValue() == 0) continue; uint64_t Offs = TD->getTypePaddedSize(Ty)*cast(CI)->getSExtValue(); + SDValue OffsVal = DAG.getConstant(Offs, MVT::i64); + unsigned PtrBits = TLI.getPointerTy().getSizeInBits(); + if (PtrBits < 64) + OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), + TLI.getPointerTy(), OffsVal); + else + OffsVal = DAG.getIntPtrConstant(Offs); N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, - DAG.getIntPtrConstant(Offs)); + OffsVal); continue; } Added: llvm/branches/Apple/Dib/test/CodeGen/X86/negative-subscript.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/negative-subscript.ll?rev=64165&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/X86/negative-subscript.ll (added) +++ llvm/branches/Apple/Dib/test/CodeGen/X86/negative-subscript.ll Mon Feb 9 15:04:05 2009 @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=x86 +; rdar://6559995 + + at a = external global [255 x i8*], align 32 + +define i32 @main() nounwind { +entry: + store i8* bitcast (i8** getelementptr ([255 x i8*]* @a, i32 0, i32 -2147483624) to i8*), i8** getelementptr ([255 x i8*]* @a, i32 0, i32 16), align 32 + ret i32 0 +} From isanbard at gmail.com Mon Feb 9 15:05:45 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 09 Feb 2009 21:05:45 -0000 Subject: [llvm-commits] [llvm] r64167 - /llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Message-ID: <200902092105.n19L5jGd010956@zion.cs.uiuc.edu> Author: void Date: Mon Feb 9 15:05:45 2009 New Revision: 64167 URL: http://llvm.org/viewvc/llvm-project?rev=64167&view=rev Log: Pull r64164 into Dib: Simplify code. Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=64167&r1=64166&r2=64167&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon Feb 9 15:05:45 2009 @@ -2695,12 +2695,13 @@ if (CI->getZExtValue() == 0) continue; uint64_t Offs = TD->getTypePaddedSize(Ty)*cast(CI)->getSExtValue(); - SDValue OffsVal = DAG.getConstant(Offs, MVT::i64); + SDValue OffsVal; unsigned PtrBits = TLI.getPointerTy().getSizeInBits(); - if (PtrBits < 64) - OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), - TLI.getPointerTy(), OffsVal); - else + if (PtrBits < 64) { + OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), + TLI.getPointerTy(), + DAG.getConstant(Offs, MVT::i64)); + } else OffsVal = DAG.getIntPtrConstant(Offs); N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, OffsVal); From gohman at apple.com Mon Feb 9 15:25:34 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 09 Feb 2009 21:25:34 -0000 Subject: [llvm-commits] [test-suite] r64170 - in /test-suite/trunk/External: HMMER/ Nurbs/ SPEC/CINT95/099.go/ SPEC/CINT95/124.m88ksim/ SPEC/CINT95/126.gcc/ SPEC/CINT95/129.compress/ SPEC/CINT95/130.li/ SPEC/CINT95/132.ijpeg/ SPEC/CINT95/134.perl/ SPEC/CINT95/147.vortex/ Message-ID: <200902092125.n19LPZNh011720@zion.cs.uiuc.edu> Author: djg Date: Mon Feb 9 15:25:34 2009 New Revision: 64170 URL: http://llvm.org/viewvc/llvm-project?rev=64170&view=rev Log: Add svn:ignore properties for Output directories. Modified: test-suite/trunk/External/HMMER/ (props changed) test-suite/trunk/External/Nurbs/ (props changed) test-suite/trunk/External/SPEC/CINT95/099.go/ (props changed) test-suite/trunk/External/SPEC/CINT95/124.m88ksim/ (props changed) test-suite/trunk/External/SPEC/CINT95/126.gcc/ (props changed) test-suite/trunk/External/SPEC/CINT95/129.compress/ (props changed) test-suite/trunk/External/SPEC/CINT95/130.li/ (props changed) test-suite/trunk/External/SPEC/CINT95/132.ijpeg/ (props changed) test-suite/trunk/External/SPEC/CINT95/134.perl/ (props changed) test-suite/trunk/External/SPEC/CINT95/147.vortex/ (props changed) Propchange: test-suite/trunk/External/HMMER/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Feb 9 15:25:34 2009 @@ -0,0 +1 @@ +Output Propchange: test-suite/trunk/External/Nurbs/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Feb 9 15:25:34 2009 @@ -0,0 +1 @@ +Output Propchange: test-suite/trunk/External/SPEC/CINT95/099.go/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Feb 9 15:25:34 2009 @@ -0,0 +1 @@ +Output Propchange: test-suite/trunk/External/SPEC/CINT95/124.m88ksim/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Feb 9 15:25:34 2009 @@ -0,0 +1 @@ +Output Propchange: test-suite/trunk/External/SPEC/CINT95/126.gcc/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Feb 9 15:25:34 2009 @@ -0,0 +1 @@ +Output Propchange: test-suite/trunk/External/SPEC/CINT95/129.compress/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Feb 9 15:25:34 2009 @@ -0,0 +1 @@ +Output Propchange: test-suite/trunk/External/SPEC/CINT95/130.li/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Feb 9 15:25:34 2009 @@ -0,0 +1 @@ +Output Propchange: test-suite/trunk/External/SPEC/CINT95/132.ijpeg/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Feb 9 15:25:34 2009 @@ -0,0 +1 @@ +Output Propchange: test-suite/trunk/External/SPEC/CINT95/134.perl/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Feb 9 15:25:34 2009 @@ -0,0 +1 @@ +Output Propchange: test-suite/trunk/External/SPEC/CINT95/147.vortex/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Feb 9 15:25:34 2009 @@ -0,0 +1 @@ +Output From gohman at apple.com Mon Feb 9 15:27:50 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 09 Feb 2009 21:27:50 -0000 Subject: [llvm-commits] [test-suite] r64171 - /test-suite/trunk/SingleSource/UnitTests/Vector/Makefile Message-ID: <200902092127.n19LRo6D011814@zion.cs.uiuc.edu> Author: djg Date: Mon Feb 9 15:27:49 2009 New Revision: 64171 URL: http://llvm.org/viewvc/llvm-project?rev=64171&view=rev Log: Run the SSE tests when ARCH is x86_64. Modified: test-suite/trunk/SingleSource/UnitTests/Vector/Makefile Modified: test-suite/trunk/SingleSource/UnitTests/Vector/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Vector/Makefile?rev=64171&r1=64170&r2=64171&view=diff ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/Vector/Makefile (original) +++ test-suite/trunk/SingleSource/UnitTests/Vector/Makefile Mon Feb 9 15:27:49 2009 @@ -12,6 +12,9 @@ ifeq ($(ARCH),x86) DIRS += SSE endif +ifeq ($(ARCH),x86_64) +DIRS += SSE +endif include $(LEVEL)/SingleSource/Makefile.singlesrc From evan.cheng at apple.com Mon Feb 9 15:36:39 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 09 Feb 2009 21:36:39 -0000 Subject: [llvm-commits] [test-suite] r64172 - /test-suite/trunk/Makefile.programs Message-ID: <200902092136.n19LadFP012114@zion.cs.uiuc.edu> Author: evancheng Date: Mon Feb 9 15:36:38 2009 New Revision: 64172 URL: http://llvm.org/viewvc/llvm-project?rev=64172&view=rev Log: Machine sinking is now on by default. Modified: test-suite/trunk/Makefile.programs Modified: test-suite/trunk/Makefile.programs URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=64172&r1=64171&r2=64172&view=diff ============================================================================== --- test-suite/trunk/Makefile.programs (original) +++ test-suite/trunk/Makefile.programs Mon Feb 9 15:36:38 2009 @@ -211,10 +211,9 @@ endif#DISABLE_DIFFS ifeq ($(ARCH),PowerPC) -LLCBETAOPTION := -enable-sinking +LLCBETAOPTION := --enable-ppc-preinc #-aggressive-remat #--enable-tail-merge -#--enable-ppc-preinc #-regalloc=local -fast endif ifeq ($(ARCH),Alpha) From gohman at apple.com Mon Feb 9 15:51:02 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 09 Feb 2009 21:51:02 -0000 Subject: [llvm-commits] [test-suite] r64174 - /test-suite/trunk/Makefile.rules Message-ID: <200902092151.n19Lp2mt012518@zion.cs.uiuc.edu> Author: djg Date: Mon Feb 9 15:51:02 2009 New Revision: 64174 URL: http://llvm.org/viewvc/llvm-project?rev=64174&view=rev Log: Remove the predefine of __NO_MATH_INLINES. It is now predefined by llvm-gcc. See PR879 for details. Modified: test-suite/trunk/Makefile.rules Modified: test-suite/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.rules?rev=64174&r1=64173&r2=64174&view=diff ============================================================================== --- test-suite/trunk/Makefile.rules (original) +++ test-suite/trunk/Makefile.rules Mon Feb 9 15:51:02 2009 @@ -338,12 +338,6 @@ endif endif -ifeq ($(OS),Linux) -ifeq ($(ARCH),x86) -CPPFLAGS += -D__NO_MATH_INLINES -endif -endif - ifeq ($(ARCH),Alpha) CPPFLAGS += -mieee CFLAGS += -mieee From gohman at apple.com Mon Feb 9 16:00:18 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 09 Feb 2009 22:00:18 -0000 Subject: [llvm-commits] [test-suite] r64176 - /test-suite/trunk/Makefile.programs Message-ID: <200902092200.n19M0I3a012971@zion.cs.uiuc.edu> Author: djg Date: Mon Feb 9 16:00:17 2009 New Revision: 64176 URL: http://llvm.org/viewvc/llvm-project?rev=64176&view=rev Log: Handle ARCH=x86_64 the same as ARCH=x86 here. Modified: test-suite/trunk/Makefile.programs Modified: test-suite/trunk/Makefile.programs URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=64176&r1=64175&r2=64176&view=diff ============================================================================== --- test-suite/trunk/Makefile.programs (original) +++ test-suite/trunk/Makefile.programs Mon Feb 9 16:00:17 2009 @@ -223,6 +223,9 @@ ifeq ($(ARCH),IA64) LLCBETAOPTION := -sched=simple endif +ifeq ($(ARCH),x86_64) +LLCBETAOPTION := -disable-post-RA-scheduler=false +endif ifeq ($(ARCH),x86) LLCBETAOPTION := -disable-post-RA-scheduler=false #-pre-alloc-split @@ -347,11 +350,13 @@ # -enable-eh is no longer required to get DWARF exceptions. ifneq ($(ARCH),PowerPC) ifneq ($(ARCH),x86) +ifneq ($(ARCH),x86_64) LLCFLAGS += -enable-correct-eh-support LLVMLD_FLAGS += -disable-inlining endif endif endif +endif # Pass target specific llc flags ifdef TARGET_LLCFLAGS From dalej at apple.com Mon Feb 9 16:14:15 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 09 Feb 2009 22:14:15 -0000 Subject: [llvm-commits] [llvm] r64177 - in /llvm/trunk: lib/Transforms/Scalar/LoopStrengthReduce.cpp test/Transforms/LoopStrengthReduce/2009-02-09-ivs-different-sizes.ll Message-ID: <200902092214.n19MEFhH013451@zion.cs.uiuc.edu> Author: johannes Date: Mon Feb 9 16:14:15 2009 New Revision: 64177 URL: http://llvm.org/viewvc/llvm-project?rev=64177&view=rev Log: Fix PR 3471, and some cleanups. Added: llvm/trunk/test/Transforms/LoopStrengthReduce/2009-02-09-ivs-different-sizes.ll Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=64177&r1=64176&r2=64177&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Mon Feb 9 16:14:15 2009 @@ -430,8 +430,8 @@ if (!AddRec->isAffine()) return false; // If Start contains an SCEVAddRecExpr from a different loop, other than an - // outer loop of the current loop, reject it. SCEV has no concept of operating - // on one loop at a time so don't confuse it with such expressions. + // outer loop of the current loop, reject it. SCEV has no concept of + // operating on one loop at a time so don't confuse it with such expressions. if (containsAddRecFromDifferentLoop(Start, L)) return false; @@ -774,14 +774,14 @@ // which need not be an immediate predecessor of this PHI. This way we // need only one copy of it even if it is referenced multiple times in // the PHI. We don't do this when the original expression is inside the - // loop because multiple copies sometimes do useful sinking of code in that - // case(?). + // loop because multiple copies sometimes do useful sinking of code in + // that case(?). Instruction *OldLoc = dyn_cast(OperandValToReplace); if (L->contains(OldLoc->getParent())) { - // If this is a critical edge, split the edge so that we do not insert the - // code on all predecessor/successor paths. We do this unless this is the - // canonical backedge for this loop, as this can make some inserted code - // be in an illegal position. + // If this is a critical edge, split the edge so that we do not insert + // the code on all predecessor/successor paths. We do this unless this + // is the canonical backedge for this loop, as this can make some + // inserted code be in an illegal position. BasicBlock *PHIPred = PN->getIncomingBlock(i); if (e != 1 && PHIPred->getTerminator()->getNumSuccessors() > 1 && (PN->getParent() != L->getHeader() || !L->contains(PHIPred))) { @@ -1224,19 +1224,21 @@ return true; } -/// RequiresTypeConversion - Returns true if converting Ty to NewTy is not +/// RequiresTypeConversion - Returns true if converting Ty1 to Ty2 is not /// a nop. bool LoopStrengthReduce::RequiresTypeConversion(const Type *Ty1, const Type *Ty2) { if (Ty1 == Ty2) return false; + if (Ty1->canLosslesslyBitCastTo(Ty2)) + return false; if (TLI && TLI->isTruncateFree(Ty1, Ty2)) return false; - return (!Ty1->canLosslesslyBitCastTo(Ty2) && - !(isa(Ty2) && - Ty1->canLosslesslyBitCastTo(UIntPtrTy)) && - !(isa(Ty1) && - Ty2->canLosslesslyBitCastTo(UIntPtrTy))); + if (isa(Ty2) && Ty1->canLosslesslyBitCastTo(UIntPtrTy)) + return false; + if (isa(Ty1) && Ty2->canLosslesslyBitCastTo(UIntPtrTy)) + return false; + return true; } /// CheckForIVReuse - Returns the multiple if the stride is the multiple @@ -1661,15 +1663,28 @@ Rewriter.clear(); // If we are reusing the iv, then it must be multiplied by a constant - // factor take advantage of addressing mode scale component. + // factor to take advantage of the addressing mode scale component. if (!isa(RewriteFactor) || !cast(RewriteFactor)->isZero()) { // If we're reusing an IV with a nonzero base (currently this happens // only when all reuses are outside the loop) subtract that base here. // The base has been used to initialize the PHI node but we don't want // it here. - if (!ReuseIV.Base->isZero()) - RewriteExpr = SE->getMinusSCEV(RewriteExpr, ReuseIV.Base); + if (!ReuseIV.Base->isZero()) { + SCEVHandle typedBase = ReuseIV.Base; + if (RewriteExpr->getType()->getPrimitiveSizeInBits() != + ReuseIV.Base->getType()->getPrimitiveSizeInBits()) { + // It's possible the original IV is a larger type than the new IV, + // in which case we have to truncate the Base. We checked in + // RequiresTypeConversion that this is valid. + assert (RewriteExpr->getType()->getPrimitiveSizeInBits() < + ReuseIV.Base->getType()->getPrimitiveSizeInBits() && + "Unexpected lengthening conversion!"); + typedBase = SE->getTruncateExpr(ReuseIV.Base, + RewriteExpr->getType()); + } + RewriteExpr = SE->getMinusSCEV(RewriteExpr, typedBase); + } // Multiply old variable, with base removed, by new scale factor. RewriteExpr = SE->getMulExpr(RewriteFactor, Added: llvm/trunk/test/Transforms/LoopStrengthReduce/2009-02-09-ivs-different-sizes.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/2009-02-09-ivs-different-sizes.ll?rev=64177&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopStrengthReduce/2009-02-09-ivs-different-sizes.ll (added) +++ llvm/trunk/test/Transforms/LoopStrengthReduce/2009-02-09-ivs-different-sizes.ll Mon Feb 9 16:14:15 2009 @@ -0,0 +1,33 @@ +; RUN: llvm-as < %s | llc +; This used to crash. +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout ="e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-unknown-linux-gnu" + +define void @parse_number(i8* nocapture %p) nounwind { +entry: + %shift.0 = select i1 false, i32 4, i32 2 ; [#uses=1] + br label %bb47 + +bb47: ; preds = %bb47, %entry + br i1 false, label %bb54, label %bb47 + +bb54: ; preds = %bb47 + br i1 false, label %bb56, label %bb66 + +bb56: ; preds = %bb62, %bb54 + %p_addr.0.pn.rec = phi i64 [ %p_addr.6.rec, %bb62 ], [ 0, %bb54 ] ; [#uses=2] + %ch.6.in.in = phi i8* [ %p_addr.6, %bb62 ], [ null, %bb54 ] ; [#uses=0] + %indvar202 = trunc i64 %p_addr.0.pn.rec to i32 ; [#uses=1] + %frac_bits.0 = mul i32 %indvar202, %shift.0 ; [#uses=1] + %p_addr.6.rec = add i64 %p_addr.0.pn.rec, 1 ; [#uses=2] + %p_addr.6 = getelementptr i8* null, i64 %p_addr.6.rec ; [#uses=1] + br i1 false, label %bb66, label %bb62 + +bb62: ; preds = %bb56 + br label %bb56 + +bb66: ; preds = %bb56, %bb54 + %frac_bits.1 = phi i32 [ 0, %bb54 ], [ %frac_bits.0, %bb56 ] ; [#uses=0] + unreachable +} From kremenek at apple.com Mon Feb 9 16:23:44 2009 From: kremenek at apple.com (Ted Kremenek) Date: Mon, 09 Feb 2009 22:23:44 -0000 Subject: [llvm-commits] [llvm] r64178 - /llvm/tags/checker/checker-0.152/ Message-ID: <200902092223.n19MNisJ013798@zion.cs.uiuc.edu> Author: kremenek Date: Mon Feb 9 16:23:44 2009 New Revision: 64178 URL: http://llvm.org/viewvc/llvm-project?rev=64178&view=rev Log: Tagging checker-0.152. Added: llvm/tags/checker/checker-0.152/ - copied from r64177, llvm/trunk/ From isanbard at gmail.com Mon Feb 9 16:24:56 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 09 Feb 2009 22:24:56 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r64180 - /llvm-gcc-4.2/trunk/build_gcc Message-ID: <200902092224.n19MOuxb013861@zion.cs.uiuc.edu> Author: void Date: Mon Feb 9 16:24:56 2009 New Revision: 64180 URL: http://llvm.org/viewvc/llvm-project?rev=64180&view=rev Log: Don't strip dSYM objects. Modified: llvm-gcc-4.2/trunk/build_gcc Modified: llvm-gcc-4.2/trunk/build_gcc URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/build_gcc?rev=64180&r1=64179&r2=64180&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/build_gcc (original) +++ llvm-gcc-4.2/trunk/build_gcc Mon Feb 9 16:24:56 2009 @@ -582,17 +582,20 @@ # Remove debugging information from DEST_DIR. if [ "x$LLVM_DEBUG" != "x1" ]; then - find $DEST_DIR -perm -0111 \! -name \*.dylib \! -name fixinc.sh \ - \! -name mkheaders \! -name libstdc++.dylib -type f -print \ + # LLVM LOCAL begin - don't strip dSYM objects + find $DEST_DIR -perm -0111 \! -path '*DWARF*' \! -name \*.dylib \ + \! -name fixinc.sh \! -name mkheaders \! -name libstdc++.dylib \ + -type f -print \ | xargs strip || exit 1 - # APPLE LOCAL begin LLVM - Strip with -Sx instead of -SX - find $DEST_DIR \( -name \*.a -or -name \*.dylib \) \ + # LLVM LOCAL begin - Strip with -Sx instead of -SX + find $DEST_DIR \! -path '*DWARF*' \( -name \*.a -or -name \*.dylib \) \ \! -name libgcc_s.10.*.dylib \! -name libstdc++.dylib -type f \ -print \ | xargs strip -SX || exit 1 - # APPLE LOCAL end LLVM - Strip with -Sx instead of -SX - find $DEST_DIR -name \*.a -type f -print \ + # LLVM LOCAL end - Strip with -Sx instead of -SX + find $DEST_DIR \! -path '*DWARF*' -name \*.a -type f -print \ | xargs ranlib || exit 1 + # LLVM LOCAL end - don't strip dSYM objects fi # LLVM LOCAL begin From isanbard at gmail.com Mon Feb 9 16:25:24 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 09 Feb 2009 22:25:24 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r64181 - /llvm-gcc-4.2/branches/Apple/Dib/build_gcc Message-ID: <200902092225.n19MPOeL013888@zion.cs.uiuc.edu> Author: void Date: Mon Feb 9 16:25:23 2009 New Revision: 64181 URL: http://llvm.org/viewvc/llvm-project?rev=64181&view=rev Log: Don't strip dSYM objects. Modified: llvm-gcc-4.2/branches/Apple/Dib/build_gcc Modified: llvm-gcc-4.2/branches/Apple/Dib/build_gcc URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/Apple/Dib/build_gcc?rev=64181&r1=64180&r2=64181&view=diff ============================================================================== --- llvm-gcc-4.2/branches/Apple/Dib/build_gcc (original) +++ llvm-gcc-4.2/branches/Apple/Dib/build_gcc Mon Feb 9 16:25:23 2009 @@ -582,17 +582,20 @@ # Remove debugging information from DEST_DIR. if [ "x$LLVM_DEBUG" != "x1" ]; then - find $DEST_DIR -perm -0111 \! -name \*.dylib \! -name fixinc.sh \ - \! -name mkheaders \! -name libstdc++.dylib -type f -print \ + # LLVM LOCAL begin - don't strip dSYM objects + find $DEST_DIR -perm -0111 \! -path '*DWARF*' \! -name \*.dylib \ + \! -name fixinc.sh \! -name mkheaders \! -name libstdc++.dylib \ + -type f -print \ | xargs strip || exit 1 - # APPLE LOCAL begin LLVM - Strip with -Sx instead of -SX - find $DEST_DIR \( -name \*.a -or -name \*.dylib \) \ + # LLVM LOCAL begin - Strip with -Sx instead of -SX + find $DEST_DIR \! -path '*DWARF*' \( -name \*.a -or -name \*.dylib \) \ \! -name libgcc_s.10.*.dylib \! -name libstdc++.dylib -type f \ -print \ | xargs strip -SX || exit 1 - # APPLE LOCAL end LLVM - Strip with -Sx instead of -SX - find $DEST_DIR -name \*.a -type f -print \ + # LLVM LOCAL end - Strip with -Sx instead of -SX + find $DEST_DIR \! -path '*DWARF*' -name \*.a -type f -print \ | xargs ranlib || exit 1 + # LLVM LOCAL end - don't strip dSYM objects fi # LLVM LOCAL begin From isanbard at gmail.com Mon Feb 9 16:34:46 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 09 Feb 2009 22:34:46 -0000 Subject: [llvm-commits] [llvm] r64182 - in /llvm/branches/Apple/Dib: lib/Transforms/Scalar/LoopStrengthReduce.cpp test/Transforms/LoopStrengthReduce/2009-02-09-ivs-different-sizes.ll Message-ID: <200902092234.n19MYkpi014204@zion.cs.uiuc.edu> Author: void Date: Mon Feb 9 16:34:46 2009 New Revision: 64182 URL: http://llvm.org/viewvc/llvm-project?rev=64182&view=rev Log: Pull r64177 into Dib: Fix PR 3471, and some cleanups. Added: llvm/branches/Apple/Dib/test/Transforms/LoopStrengthReduce/2009-02-09-ivs-different-sizes.ll Modified: llvm/branches/Apple/Dib/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/branches/Apple/Dib/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=64182&r1=64181&r2=64182&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/branches/Apple/Dib/lib/Transforms/Scalar/LoopStrengthReduce.cpp Mon Feb 9 16:34:46 2009 @@ -430,8 +430,8 @@ if (!AddRec->isAffine()) return false; // If Start contains an SCEVAddRecExpr from a different loop, other than an - // outer loop of the current loop, reject it. SCEV has no concept of operating - // on one loop at a time so don't confuse it with such expressions. + // outer loop of the current loop, reject it. SCEV has no concept of + // operating on one loop at a time so don't confuse it with such expressions. if (containsAddRecFromDifferentLoop(Start, L)) return false; @@ -774,14 +774,14 @@ // which need not be an immediate predecessor of this PHI. This way we // need only one copy of it even if it is referenced multiple times in // the PHI. We don't do this when the original expression is inside the - // loop because multiple copies sometimes do useful sinking of code in that - // case(?). + // loop because multiple copies sometimes do useful sinking of code in + // that case(?). Instruction *OldLoc = dyn_cast(OperandValToReplace); if (L->contains(OldLoc->getParent())) { - // If this is a critical edge, split the edge so that we do not insert the - // code on all predecessor/successor paths. We do this unless this is the - // canonical backedge for this loop, as this can make some inserted code - // be in an illegal position. + // If this is a critical edge, split the edge so that we do not insert + // the code on all predecessor/successor paths. We do this unless this + // is the canonical backedge for this loop, as this can make some + // inserted code be in an illegal position. BasicBlock *PHIPred = PN->getIncomingBlock(i); if (e != 1 && PHIPred->getTerminator()->getNumSuccessors() > 1 && (PN->getParent() != L->getHeader() || !L->contains(PHIPred))) { @@ -1224,19 +1224,21 @@ return true; } -/// RequiresTypeConversion - Returns true if converting Ty to NewTy is not +/// RequiresTypeConversion - Returns true if converting Ty1 to Ty2 is not /// a nop. bool LoopStrengthReduce::RequiresTypeConversion(const Type *Ty1, const Type *Ty2) { if (Ty1 == Ty2) return false; + if (Ty1->canLosslesslyBitCastTo(Ty2)) + return false; if (TLI && TLI->isTruncateFree(Ty1, Ty2)) return false; - return (!Ty1->canLosslesslyBitCastTo(Ty2) && - !(isa(Ty2) && - Ty1->canLosslesslyBitCastTo(UIntPtrTy)) && - !(isa(Ty1) && - Ty2->canLosslesslyBitCastTo(UIntPtrTy))); + if (isa(Ty2) && Ty1->canLosslesslyBitCastTo(UIntPtrTy)) + return false; + if (isa(Ty1) && Ty2->canLosslesslyBitCastTo(UIntPtrTy)) + return false; + return true; } /// CheckForIVReuse - Returns the multiple if the stride is the multiple @@ -1661,15 +1663,28 @@ Rewriter.clear(); // If we are reusing the iv, then it must be multiplied by a constant - // factor take advantage of addressing mode scale component. + // factor to take advantage of the addressing mode scale component. if (!isa(RewriteFactor) || !cast(RewriteFactor)->isZero()) { // If we're reusing an IV with a nonzero base (currently this happens // only when all reuses are outside the loop) subtract that base here. // The base has been used to initialize the PHI node but we don't want // it here. - if (!ReuseIV.Base->isZero()) - RewriteExpr = SE->getMinusSCEV(RewriteExpr, ReuseIV.Base); + if (!ReuseIV.Base->isZero()) { + SCEVHandle typedBase = ReuseIV.Base; + if (RewriteExpr->getType()->getPrimitiveSizeInBits() != + ReuseIV.Base->getType()->getPrimitiveSizeInBits()) { + // It's possible the original IV is a larger type than the new IV, + // in which case we have to truncate the Base. We checked in + // RequiresTypeConversion that this is valid. + assert (RewriteExpr->getType()->getPrimitiveSizeInBits() < + ReuseIV.Base->getType()->getPrimitiveSizeInBits() && + "Unexpected lengthening conversion!"); + typedBase = SE->getTruncateExpr(ReuseIV.Base, + RewriteExpr->getType()); + } + RewriteExpr = SE->getMinusSCEV(RewriteExpr, typedBase); + } // Multiply old variable, with base removed, by new scale factor. RewriteExpr = SE->getMulExpr(RewriteFactor, Added: llvm/branches/Apple/Dib/test/Transforms/LoopStrengthReduce/2009-02-09-ivs-different-sizes.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/Transforms/LoopStrengthReduce/2009-02-09-ivs-different-sizes.ll?rev=64182&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/Transforms/LoopStrengthReduce/2009-02-09-ivs-different-sizes.ll (added) +++ llvm/branches/Apple/Dib/test/Transforms/LoopStrengthReduce/2009-02-09-ivs-different-sizes.ll Mon Feb 9 16:34:46 2009 @@ -0,0 +1,33 @@ +; RUN: llvm-as < %s | llc +; This used to crash. +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout ="e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-unknown-linux-gnu" + +define void @parse_number(i8* nocapture %p) nounwind { +entry: + %shift.0 = select i1 false, i32 4, i32 2 ; [#uses=1] + br label %bb47 + +bb47: ; preds = %bb47, %entry + br i1 false, label %bb54, label %bb47 + +bb54: ; preds = %bb47 + br i1 false, label %bb56, label %bb66 + +bb56: ; preds = %bb62, %bb54 + %p_addr.0.pn.rec = phi i64 [ %p_addr.6.rec, %bb62 ], [ 0, %bb54 ] ; [#uses=2] + %ch.6.in.in = phi i8* [ %p_addr.6, %bb62 ], [ null, %bb54 ] ; [#uses=0] + %indvar202 = trunc i64 %p_addr.0.pn.rec to i32 ; [#uses=1] + %frac_bits.0 = mul i32 %indvar202, %shift.0 ; [#uses=1] + %p_addr.6.rec = add i64 %p_addr.0.pn.rec, 1 ; [#uses=2] + %p_addr.6 = getelementptr i8* null, i64 %p_addr.6.rec ; [#uses=1] + br i1 false, label %bb66, label %bb62 + +bb62: ; preds = %bb56 + br label %bb56 + +bb66: ; preds = %bb56, %bb54 + %frac_bits.1 = phi i32 [ 0, %bb54 ], [ %frac_bits.0, %bb56 ] ; [#uses=0] + unreachable +} From isanbard at gmail.com Mon Feb 9 16:41:59 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 09 Feb 2009 22:41:59 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r64183 - /llvm-gcc-4.2/tags/Apple/llvmgcc42-2095.1/build_gcc Message-ID: <200902092242.n19Mg0Ou014461@zion.cs.uiuc.edu> Author: void Date: Mon Feb 9 16:41:59 2009 New Revision: 64183 URL: http://llvm.org/viewvc/llvm-project?rev=64183&view=rev Log: Don't strip dSYM objects. Modified: llvm-gcc-4.2/tags/Apple/llvmgcc42-2095.1/build_gcc Modified: llvm-gcc-4.2/tags/Apple/llvmgcc42-2095.1/build_gcc URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/tags/Apple/llvmgcc42-2095.1/build_gcc?rev=64183&r1=64182&r2=64183&view=diff ============================================================================== --- llvm-gcc-4.2/tags/Apple/llvmgcc42-2095.1/build_gcc (original) +++ llvm-gcc-4.2/tags/Apple/llvmgcc42-2095.1/build_gcc Mon Feb 9 16:41:59 2009 @@ -582,17 +582,20 @@ # Remove debugging information from DEST_DIR. if [ "x$LLVM_DEBUG" != "x1" ]; then - find $DEST_DIR -perm -0111 \! -name \*.dylib \! -name fixinc.sh \ - \! -name mkheaders \! -name libstdc++.dylib -type f -print \ + # LLVM LOCAL begin - don't strip dSYM objects + find $DEST_DIR -perm -0111 \! -path '*DWARF*' \! -name \*.dylib \ + \! -name fixinc.sh \! -name mkheaders \! -name libstdc++.dylib \ + -type f -print \ | xargs strip || exit 1 - # APPLE LOCAL begin LLVM - Strip with -Sx instead of -SX - find $DEST_DIR \( -name \*.a -or -name \*.dylib \) \ + # LLVM LOCAL begin - Strip with -Sx instead of -SX + find $DEST_DIR \! -path '*DWARF*' \( -name \*.a -or -name \*.dylib \) \ \! -name libgcc_s.10.*.dylib \! -name libstdc++.dylib -type f \ -print \ | xargs strip -SX || exit 1 - # APPLE LOCAL end LLVM - Strip with -Sx instead of -SX - find $DEST_DIR -name \*.a -type f -print \ + # LLVM LOCAL end - Strip with -Sx instead of -SX + find $DEST_DIR \! -path '*DWARF*' -name \*.a -type f -print \ | xargs ranlib || exit 1 + # LLVM LOCAL end - don't strip dSYM objects fi # LLVM LOCAL begin From evan.cheng at apple.com Mon Feb 9 16:47:36 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 09 Feb 2009 22:47:36 -0000 Subject: [llvm-commits] [llvm] r64184 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp Message-ID: <200902092247.n19MlaFN014685@zion.cs.uiuc.edu> Author: evancheng Date: Mon Feb 9 16:47:36 2009 New Revision: 64184 URL: http://llvm.org/viewvc/llvm-project?rev=64184&view=rev Log: If the target cannot issue a copy for the given source and dest registers, abort instead of silently continue. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp?rev=64184&r1=64183&r2=64184&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp Mon Feb 9 16:47:36 2009 @@ -125,10 +125,11 @@ } else { // Create the reg, emit the copy. VRBase = MRI.createVirtualRegister(DstRC); - bool Emitted = - TII->copyRegToReg(*BB, End, VRBase, SrcReg, DstRC, SrcRC); - Emitted = Emitted; // Silence compiler warning. - assert(Emitted && "Unable to issue a copy instruction!"); + bool Emitted = TII->copyRegToReg(*BB, End, VRBase, SrcReg, DstRC, SrcRC); + if (!Emitted) { + cerr << "Unable to issue a copy instruction!\n"; + abort(); + } } SDValue Op(Node, ResNo); @@ -529,7 +530,11 @@ else DstTRC = TRI->getPhysicalRegisterRegClass(DestReg, Node->getOperand(1).getValueType()); - TII->copyRegToReg(*BB, End, DestReg, SrcReg, DstTRC, SrcTRC); + bool Emitted = TII->copyRegToReg(*BB, End, DestReg, SrcReg, DstTRC, SrcTRC); + if (!Emitted) { + cerr << "Unable to issue a copy instruction!\n"; + abort(); + } break; } case ISD::CopyFromReg: { From dalej at apple.com Mon Feb 9 16:59:35 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 9 Feb 2009 14:59:35 -0800 Subject: [llvm-commits] [llvm] r64124 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/X86/ lib/Target/XCore/ In-Reply-To: <6EE4E128-338A-4737-AE0A-1359A9DE6318@apple.com> References: <200902090714.n197EMxc004979@zion.cs.uiuc.edu> <1067F87A-9600-411A-810D-9D450ADC7C46@apple.com> <6EE4E128-338A-4737-AE0A-1359A9DE6318@apple.com> Message-ID: On Feb 9, 2009, at 12:41 AMPST, Evan Cheng wrote: > > On Feb 8, 2009, at 11:20 PM, Chris Lattner wrote: > >> >> On Feb 8, 2009, at 11:14 PM, Evan Cheng wrote: >> >>> Author: evancheng >>> Date: Mon Feb 9 01:14:22 2009 >>> New Revision: 64124 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=64124&view=rev >>> Log: >>> Turns out AnalyzeBranch can modify the mbb being analyzed. This is a >>> nasty >>> suprise to some callers, e.g. register coalescer. For now, add an >>> parameter >>> that tells AnalyzeBranch whether it's safe to modify the mbb. A >>> better >>> solution is out there, but I don't have time to deal with it right >>> now. >> >> Whoa, that's really not cool. *why* does analyze branch modify a >> mbb? What breaks if that is disabled from all targets? > > It's trimming instructions in a mbb after an unconditional branch. I > don't know why that would happen but it does. I think it's branching > folding's job to trim those instructions. But I don't have the energy > to deal with that right now. I think it's every pass's job to be sure things like this don't get created, and the verification between passes should check it. This was not a popular view last time I expressed it:) From evan.cheng at apple.com Mon Feb 9 17:32:07 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 09 Feb 2009 23:32:07 -0000 Subject: [llvm-commits] [llvm] r64186 - in /llvm/trunk: lib/Target/X86/X86FloatingPoint.cpp lib/Target/X86/X86InstrFPStack.td lib/Target/X86/X86InstrInfo.cpp test/CodeGen/X86/fp-stack-set-st1.ll Message-ID: <200902092332.n19NW72X016523@zion.cs.uiuc.edu> Author: evancheng Date: Mon Feb 9 17:32:07 2009 New Revision: 64186 URL: http://llvm.org/viewvc/llvm-project?rev=64186&view=rev Log: Implement FpSET_ST1_*. Added: llvm/trunk/test/CodeGen/X86/fp-stack-set-st1.ll Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp llvm/trunk/lib/Target/X86/X86InstrFPStack.td llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=64186&r1=64185&r2=64186&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Mon Feb 9 17:32:07 2009 @@ -982,7 +982,21 @@ case X86::FpSET_ST0_32: case X86::FpSET_ST0_64: case X86::FpSET_ST0_80: - assert(StackTop == 1 && "Stack should have one element on it to return!"); + assert((StackTop == 1 || StackTop == 2) + && "Stack should have one or two element on it to return!"); + --StackTop; // "Forget" we have something on the top of stack! + break; + case X86::FpSET_ST1_32: + case X86::FpSET_ST1_64: + case X86::FpSET_ST1_80: + // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them. + if (StackTop == 1) { + BuildMI(*MBB, I, TII->get(X86::XCH_F)).addReg(X86::ST1); + NumFXCH++; + StackTop = 0; + break; + } + assert(StackTop == 2 && "Stack should have two element on it to return!"); --StackTop; // "Forget" we have something on the top of stack! break; case X86::MOV_Fp3232: Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=64186&r1=64185&r2=64186&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Mon Feb 9 17:32:07 2009 @@ -151,6 +151,12 @@ def FpSET_ST0_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(0) = FPR } +let Defs = [ST1] in { +def FpSET_ST1_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(1) = FPR +def FpSET_ST1_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(1) = FPR +def FpSET_ST1_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(1) = FPR +} + // FpIf32, FpIf64 - Floating Point Psuedo Instruction template. // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. // f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=64186&r1=64185&r2=64186&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Feb 9 17:32:07 2009 @@ -1753,19 +1753,20 @@ // Moving to ST(0) turns into FpSET_ST0_32 etc. if (DestRC == &X86::RSTRegClass) { - // Copying to ST(0). FIXME: handle ST(1) also - if (DestReg != X86::ST0) + // Copying to ST(0) / ST(1). + if (DestReg != X86::ST0 && DestReg != X86::ST1) // Can only copy to TOS right now return false; + bool isST0 = DestReg == X86::ST0; unsigned Opc; if (SrcRC == &X86::RFP32RegClass) - Opc = X86::FpSET_ST0_32; + Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32; else if (SrcRC == &X86::RFP64RegClass) - Opc = X86::FpSET_ST0_64; + Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64; else { if (SrcRC != &X86::RFP80RegClass) return false; - Opc = X86::FpSET_ST0_80; + Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80; } BuildMI(MBB, MI, get(Opc)).addReg(SrcReg); return true; Added: llvm/trunk/test/CodeGen/X86/fp-stack-set-st1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp-stack-set-st1.ll?rev=64186&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/fp-stack-set-st1.ll (added) +++ llvm/trunk/test/CodeGen/X86/fp-stack-set-st1.ll Mon Feb 9 17:32:07 2009 @@ -0,0 +1,7 @@ +; RUN: llvm-as < %s | llc -march=x86 | grep fxch | count 2 + +define i32 @main() nounwind { +entry: + %asmtmp = tail call { double, double } asm sideeffect "fmul\09%st(1),%st\0A\09fst\09%st(1)\0A\09frndint\0A\09fxch %st(1)\0A\09fsub\09%st(1),%st\0A\09f2xm1\0A\09", "={st},={st(1)},0,1,~{dirflag},~{fpsr},~{flags}"(double 0x4030FEFBD582097D, double 4.620000e+01) nounwind ; <{ double, double }> [#uses=0] + unreachable +} From sanjiv.gupta at microchip.com Mon Feb 9 22:20:27 2009 From: sanjiv.gupta at microchip.com (Sanjiv Gupta) Date: Tue, 10 Feb 2009 04:20:27 -0000 Subject: [llvm-commits] [llvm] r64199 - /llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Message-ID: <200902100420.n1A4KRXx010552@zion.cs.uiuc.edu> Author: sgupta Date: Mon Feb 9 22:20:26 2009 New Revision: 64199 URL: http://llvm.org/viewvc/llvm-project?rev=64199&view=rev Log: Function temporaries can not overlap with retval or args.See the comment in source code to know the reason. Anything having .auto. in its name is local to a function in nature irrespective of the linkage specified. print static local variables in module level IDATA section. Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=64199&r1=64198&r2=64199&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Mon Feb 9 22:20:26 2009 @@ -212,15 +212,19 @@ // Emit declarations for external globals. for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); I != E; I++) { + // Any variables reaching here with ".auto." in its name is a local scope + // variable and should not be printed in global data section. std::string Name = Mang->getValueName(I); + if (Name.find(".auto.") != std::string::npos) + continue; + if (I->isDeclaration()) O << "\textern "<< Name << "\n"; - else if (I->getLinkage() == GlobalValue::CommonLinkage) - O << "\tglobal "<< Name << "\n"; - else if (I->getLinkage() == GlobalValue::ExternalLinkage) + else if (I->hasCommonLinkage() || I->hasExternalLinkage()) O << "\tglobal "<< Name << "\n"; } } + void PIC16AsmPrinter::EmitInitData (Module &M) { SwitchToSection(TAI->getDataSection()); for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); @@ -240,7 +244,7 @@ // Any variables reaching here with "." in its name is a local scope // variable and should not be printed in global data section. std::string name = Mang->getValueName(I); - if (name.find(".") != std::string::npos) + if (name.find(".auto.") != std::string::npos) continue; O << name; @@ -352,9 +356,12 @@ // The variables of a function are of form FuncName.* . If this variable // does not belong to this function then continue. - if (!(VarName.find(FuncName + ".") == 0 ? true : false)) + // Static local varilabes of a function does not have .auto. in their + // name. They are not printed as part of function data but module + // level global data. + if (!(VarName.find(FuncName + ".auto.") == 0 ? true : false)) continue; - + Constant *C = I->getInitializer(); const Type *Ty = C->getType(); unsigned Size = TD->getTypePaddedSize(Ty); @@ -362,9 +369,14 @@ // Emit memory reserve directive. O << VarName << " RES " << Size << "\n"; } - emitFunctionTempData(MF, FrameSize); + + // Return value can not overlap with temp data, becasue a temp slot + // may be read/written after a return value is calculated and saved + // within the function. if (RetSize > FrameSize) - O << CurrentFnName << ".dummy" << "RES" << (RetSize - FrameSize); + O << CurrentFnName << ".dummy" << " RES " << (RetSize - FrameSize) << "\n"; + + emitFunctionTempData(MF, FrameSize); } void PIC16AsmPrinter::emitFunctionTempData(MachineFunction &MF, From kremenek at apple.com Mon Feb 9 23:44:31 2009 From: kremenek at apple.com (Ted Kremenek) Date: Tue, 10 Feb 2009 05:44:31 -0000 Subject: [llvm-commits] [llvm] r64201 - /llvm/tags/checker/checker-0.153/ Message-ID: <200902100544.n1A5iVXe013502@zion.cs.uiuc.edu> Author: kremenek Date: Mon Feb 9 23:44:31 2009 New Revision: 64201 URL: http://llvm.org/viewvc/llvm-project?rev=64201&view=rev Log: Tagging checker-0.153. Added: llvm/tags/checker/checker-0.153/ - copied from r64200, llvm/trunk/ From dpatel at apple.com Tue Feb 10 00:04:08 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 10 Feb 2009 06:04:08 -0000 Subject: [llvm-commits] [llvm] r64204 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Message-ID: <200902100604.n1A6481f014098@zion.cs.uiuc.edu> Author: dpatel Date: Tue Feb 10 00:04:08 2009 New Revision: 64204 URL: http://llvm.org/viewvc/llvm-project?rev=64204&view=rev Log: Validate file id. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=64204&r1=64203&r2=64204&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Tue Feb 10 00:04:08 2009 @@ -1554,6 +1554,7 @@ unsigned Line = V->getLineNumber(); CompileUnit *Unit = FindCompileUnit(V->getCompileUnit()); FileID = Unit->getID(); + assert (FileID && "Invalid file id"); AddUInt(Die, DW_AT_decl_file, 0, FileID); AddUInt(Die, DW_AT_decl_line, 0, Line); } @@ -1565,6 +1566,7 @@ unsigned Line = G->getLineNumber(); CompileUnit *Unit = FindCompileUnit(G->getCompileUnit()); FileID = Unit->getID(); + assert (FileID && "Invalid file id"); AddUInt(Die, DW_AT_decl_file, 0, FileID); AddUInt(Die, DW_AT_decl_line, 0, Line); } @@ -1577,6 +1579,7 @@ return; CompileUnit *Unit = FindCompileUnit(CU); FileID = Unit->getID(); + assert (FileID && "Invalid file id"); AddUInt(Die, DW_AT_decl_file, 0, FileID); AddUInt(Die, DW_AT_decl_line, 0, Line); } From anton at korobeynikov.info Tue Feb 10 00:06:29 2009 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Tue, 10 Feb 2009 09:06:29 +0300 Subject: [llvm-commits] [llvm] r64186 - in /llvm/trunk: lib/Target/X86/X86FloatingPoint.cpp lib/Target/X86/X86InstrFPStack.td lib/Target/X86/X86InstrInfo.cpp test/CodeGen/X86/fp-stack-set-st1.ll In-Reply-To: <200902092332.n19NW72X016523@zion.cs.uiuc.edu> References: <200902092332.n19NW72X016523@zion.cs.uiuc.edu> Message-ID: Hello, Evan > Log: > Implement FpSET_ST1_*. Did this fix PR2257? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From dpatel at apple.com Tue Feb 10 01:00:59 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 10 Feb 2009 07:00:59 -0000 Subject: [llvm-commits] [llvm] r64207 - in /llvm/trunk: include/llvm/Transforms/Utils/Local.h lib/Transforms/Scalar/ScalarReplAggregates.cpp lib/Transforms/Utils/Local.cpp test/Transforms/ScalarRepl/debuginfo.ll Message-ID: <200902100700.n1A70xfb016017@zion.cs.uiuc.edu> Author: dpatel Date: Tue Feb 10 01:00:59 2009 New Revision: 64207 URL: http://llvm.org/viewvc/llvm-project?rev=64207&view=rev Log: Enable scalar replacement of AllocaInst whose one of the user is dbg info. Added: llvm/trunk/test/Transforms/ScalarRepl/debuginfo.ll Modified: llvm/trunk/include/llvm/Transforms/Utils/Local.h llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/trunk/lib/Transforms/Utils/Local.cpp Modified: llvm/trunk/include/llvm/Transforms/Utils/Local.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/Local.h?rev=64207&r1=64206&r2=64207&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/Utils/Local.h (original) +++ llvm/trunk/include/llvm/Transforms/Utils/Local.h Tue Feb 10 01:00:59 2009 @@ -25,6 +25,7 @@ class AllocaInst; class ConstantExpr; class TargetData; +class DbgInfoIntrinsic; template class SmallVectorImpl; @@ -94,6 +95,11 @@ /// The phi node is deleted and it returns the pointer to the alloca inserted. AllocaInst *DemotePHIToStack(PHINode *P, Instruction *AllocaPoint = 0); +/// OnlyUsedByDbgIntrinsics - Return true if the instruction I is only used +/// by DbgIntrinsics. If DbgInUses is specified then the vector is filled +/// with DbgInfoIntrinsic that use the instruction I. +bool OnlyUsedByDbgInfoIntrinsics(Instruction *I, + SmallVectorImpl *DbgInUses = 0); } // End llvm namespace #endif Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=64207&r1=64206&r2=64207&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Tue Feb 10 01:00:59 2009 @@ -31,6 +31,7 @@ #include "llvm/Analysis/Dominators.h" #include "llvm/Target/TargetData.h" #include "llvm/Transforms/Utils/PromoteMemToReg.h" +#include "llvm/Transforms/Utils/Local.h" #include "llvm/Support/Debug.h" #include "llvm/Support/GetElementPtrTypeIterator.h" #include "llvm/Support/IRBuilder.h" @@ -80,9 +81,9 @@ /// isUnsafe - This is set to true if the alloca cannot be SROA'd. bool isUnsafe : 1; - /// needsCanon - This is set to true if there is some use of the alloca - /// that requires canonicalization. - bool needsCanon : 1; + /// needsCleanup - This is set to true if there is some use of the alloca + /// that requires cleanup. + bool needsCleanup : 1; /// isMemCpySrc - This is true if this aggregate is memcpy'd from. bool isMemCpySrc : 1; @@ -91,7 +92,7 @@ bool isMemCpyDst : 1; AllocaInfo() - : isUnsafe(false), needsCanon(false), + : isUnsafe(false), needsCleanup(false), isMemCpySrc(false), isMemCpyDst(false) {} }; @@ -112,7 +113,8 @@ void DoScalarReplacement(AllocationInst *AI, std::vector &WorkList); - void CanonicalizeAllocaUsers(AllocationInst *AI); + void CleanupGEP(GetElementPtrInst *GEP); + void CleanupAllocaUsers(AllocationInst *AI); AllocaInst *AddNewAlloca(Function &F, const Type *Ty, AllocationInst *Base); void RewriteBitCastUserOfAlloca(Instruction *BCInst, AllocationInst *AI, @@ -265,7 +267,7 @@ case 0: // Not safe to scalar replace. break; case 1: // Safe, but requires cleanup/canonicalizations first - CanonicalizeAllocaUsers(AI); + CleanupAllocaUsers(AI); // FALL THROUGH. case 3: // Safe to scalar replace. DoScalarReplacement(AI, WorkList); @@ -548,7 +550,7 @@ // out if this is the only problem. if ((NumElements == 1 || NumElements == 2) && AllUsersAreLoads(GEPI)) { - Info.needsCanon = true; + Info.needsCleanup = true; return; // Canonicalization required! } return MarkUnsafe(Info); @@ -655,7 +657,17 @@ continue; } return MarkUnsafe(Info); - } else { + } else if (isa(UI)) { + // If one user is DbgInfoIntrinsic then check if all users are + // DbgInfoIntrinsics. + if (OnlyUsedByDbgInfoIntrinsics(BC)) { + Info.needsCleanup = true; + return; + } + else + MarkUnsafe(Info); + } + else { return MarkUnsafe(Info); } if (Info.isUnsafe) return; @@ -1121,59 +1133,76 @@ return 0; // If we require cleanup, return 1, otherwise return 3. - return Info.needsCanon ? 1 : 3; + return Info.needsCleanup ? 1 : 3; +} + +/// CleanupGEP - GEP is used by an Alloca, which can be prompted after the GEP +/// is canonicalized here. +void SROA::CleanupGEP(GetElementPtrInst *GEPI) { + gep_type_iterator I = gep_type_begin(GEPI); + ++I; + + if (const ArrayType *AT = dyn_cast(*I)) { + uint64_t NumElements = AT->getNumElements(); + + if (!isa(I.getOperand())) { + if (NumElements == 1) { + GEPI->setOperand(2, Constant::getNullValue(Type::Int32Ty)); + } else { + assert(NumElements == 2 && "Unhandled case!"); + // All users of the GEP must be loads. At each use of the GEP, insert + // two loads of the appropriate indexed GEP and select between them. + Value *IsOne = new ICmpInst(ICmpInst::ICMP_NE, I.getOperand(), + Constant::getNullValue(I.getOperand()->getType()), + "isone", GEPI); + // Insert the new GEP instructions, which are properly indexed. + SmallVector Indices(GEPI->op_begin()+1, GEPI->op_end()); + Indices[1] = Constant::getNullValue(Type::Int32Ty); + Value *ZeroIdx = GetElementPtrInst::Create(GEPI->getOperand(0), + Indices.begin(), + Indices.end(), + GEPI->getName()+".0", GEPI); + Indices[1] = ConstantInt::get(Type::Int32Ty, 1); + Value *OneIdx = GetElementPtrInst::Create(GEPI->getOperand(0), + Indices.begin(), + Indices.end(), + GEPI->getName()+".1", GEPI); + // Replace all loads of the variable index GEP with loads from both + // indexes and a select. + while (!GEPI->use_empty()) { + LoadInst *LI = cast(GEPI->use_back()); + Value *Zero = new LoadInst(ZeroIdx, LI->getName()+".0", LI); + Value *One = new LoadInst(OneIdx , LI->getName()+".1", LI); + Value *R = SelectInst::Create(IsOne, One, Zero, LI->getName(), LI); + LI->replaceAllUsesWith(R); + LI->eraseFromParent(); + } + GEPI->eraseFromParent(); + } + } + } } -/// CanonicalizeAllocaUsers - If SROA reported that it can promote the specified +/// CleanupAllocaUsers - If SROA reported that it can promote the specified /// allocation, but only if cleaned up, perform the cleanups required. -void SROA::CanonicalizeAllocaUsers(AllocationInst *AI) { +void SROA::CleanupAllocaUsers(AllocationInst *AI) { // At this point, we know that the end result will be SROA'd and promoted, so // we can insert ugly code if required so long as sroa+mem2reg will clean it // up. for (Value::use_iterator UI = AI->use_begin(), E = AI->use_end(); UI != E; ) { - GetElementPtrInst *GEPI = dyn_cast(*UI++); - if (!GEPI) continue; - gep_type_iterator I = gep_type_begin(GEPI); - ++I; - - if (const ArrayType *AT = dyn_cast(*I)) { - uint64_t NumElements = AT->getNumElements(); - - if (!isa(I.getOperand())) { - if (NumElements == 1) { - GEPI->setOperand(2, Constant::getNullValue(Type::Int32Ty)); - } else { - assert(NumElements == 2 && "Unhandled case!"); - // All users of the GEP must be loads. At each use of the GEP, insert - // two loads of the appropriate indexed GEP and select between them. - Value *IsOne = new ICmpInst(ICmpInst::ICMP_NE, I.getOperand(), - Constant::getNullValue(I.getOperand()->getType()), - "isone", GEPI); - // Insert the new GEP instructions, which are properly indexed. - SmallVector Indices(GEPI->op_begin()+1, GEPI->op_end()); - Indices[1] = Constant::getNullValue(Type::Int32Ty); - Value *ZeroIdx = GetElementPtrInst::Create(GEPI->getOperand(0), - Indices.begin(), - Indices.end(), - GEPI->getName()+".0", GEPI); - Indices[1] = ConstantInt::get(Type::Int32Ty, 1); - Value *OneIdx = GetElementPtrInst::Create(GEPI->getOperand(0), - Indices.begin(), - Indices.end(), - GEPI->getName()+".1", GEPI); - // Replace all loads of the variable index GEP with loads from both - // indexes and a select. - while (!GEPI->use_empty()) { - LoadInst *LI = cast(GEPI->use_back()); - Value *Zero = new LoadInst(ZeroIdx, LI->getName()+".0", LI); - Value *One = new LoadInst(OneIdx , LI->getName()+".1", LI); - Value *R = SelectInst::Create(IsOne, One, Zero, LI->getName(), LI); - LI->replaceAllUsesWith(R); - LI->eraseFromParent(); - } - GEPI->eraseFromParent(); + User *U = *UI++; + if (GetElementPtrInst *GEPI = dyn_cast(U)) + CleanupGEP(GEPI); + else if (Instruction *I = dyn_cast(U)) { + SmallVector DbgInUses; + if (OnlyUsedByDbgInfoIntrinsics(I, &DbgInUses)) { + // Safe to remove debug info uses. + while (!DbgInUses.empty()) { + DbgInfoIntrinsic *DI = DbgInUses.back(); DbgInUses.pop_back(); + DI->eraseFromParent(); } + I->eraseFromParent(); } } } Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=64207&r1=64206&r2=64207&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Tue Feb 10 01:00:59 2009 @@ -248,3 +248,25 @@ // Nuke BB. PredBB->eraseFromParent(); } + +/// OnlyUsedByDbgIntrinsics - Return true if the instruction I is only used +/// by DbgIntrinsics. If DbgInUses is specified then the vector is filled +/// with the DbgInfoIntrinsic that use the instruction I. +bool llvm::OnlyUsedByDbgInfoIntrinsics(Instruction *I, + SmallVectorImpl *DbgInUses) { + if (DbgInUses) + DbgInUses->clear(); + + for (Value::use_iterator UI = I->use_begin(), UE = I->use_end(); UI != UE; + ++UI) { + if (DbgInfoIntrinsic *DI = dyn_cast(*UI)) { + if (DbgInUses) + DbgInUses->push_back(DI); + } else { + if (DbgInUses) + DbgInUses->clear(); + return false; + } + } + return true; +} Added: llvm/trunk/test/Transforms/ScalarRepl/debuginfo.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/debuginfo.ll?rev=64207&view=auto ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/debuginfo.ll (added) +++ llvm/trunk/test/Transforms/ScalarRepl/debuginfo.ll Tue Feb 10 01:00:59 2009 @@ -0,0 +1,105 @@ +; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | not grep alloca + %llvm.dbg.anchor.type = type { i32, i32 } + %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 } + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } + %llvm.dbg.composite.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, { }* } + %llvm.dbg.derivedtype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }* } + %llvm.dbg.subprogram.type = type { i32, { }*, { }*, i8*, i8*, i8*, { }*, i32, { }*, i1, i1 } + %llvm.dbg.variable.type = type { i32, { }*, i8*, { }*, i32, { }* } + %struct.Sphere = type { %struct.Vec } + %struct.Vec = type { i32, i32, i32 } + at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] + at .str = internal constant [6 x i8] c"r.cpp\00", section "llvm.metadata" ; <[6 x i8]*> [#uses=1] + at .str1 = internal constant [5 x i8] c"/tmp\00", section "llvm.metadata" ; <[5 x i8]*> [#uses=1] + at .str2 = internal constant [55 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build 00)\00", section "llvm.metadata" ; <[55 x i8]*> [#uses=1] + at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 4, i8* getelementptr ([6 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([5 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([55 x i8]* @.str2, i32 0, i32 0), i1 true, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] + at .str3 = internal constant [4 x i8] c"Vec\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at .str4 = internal constant [4 x i8] c"int\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str4, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, i32 5 }, section "llvm.metadata" ; <%llvm.dbg.basictype.type*> [#uses=1] + at .str5 = internal constant [2 x i8] c"x\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1] + at llvm.dbg.derivedtype = internal constant %llvm.dbg.derivedtype.type { i32 458765, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([2 x i8]* @.str5, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 4, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at .str6 = internal constant [2 x i8] c"y\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1] + at llvm.dbg.derivedtype7 = internal constant %llvm.dbg.derivedtype.type { i32 458765, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([2 x i8]* @.str6, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 4, i64 32, i64 32, i64 32, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at .str8 = internal constant [2 x i8] c"z\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1] + at llvm.dbg.derivedtype9 = internal constant %llvm.dbg.derivedtype.type { i32 458765, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([2 x i8]* @.str8, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 4, i64 32, i64 32, i64 64, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.derivedtype10 = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite18 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.derivedtype11 = internal constant %llvm.dbg.derivedtype.type { i32 458790, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 96, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite18 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.derivedtype12 = internal constant %llvm.dbg.derivedtype.type { i32 458768, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype11 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.array = internal constant [3 x { }*] [ { }* null, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype10 to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype12 to { }*) ], section "llvm.metadata" ; <[3 x { }*]*> [#uses=1] + at llvm.dbg.composite13 = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at llvm.dbg.subprograms = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 46 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] + at llvm.dbg.subprogram = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 2, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite13 to { }*), i1 false, i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at llvm.dbg.array14 = internal constant [5 x { }*] [ { }* null, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype10 to { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) ], section "llvm.metadata" ; <[5 x { }*]*> [#uses=1] + at llvm.dbg.composite15 = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([5 x { }*]* @llvm.dbg.array14 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at llvm.dbg.subprogram16 = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 5, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite15 to { }*), i1 false, i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at llvm.dbg.array17 = internal constant [5 x { }*] [ { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype7 to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype9 to { }*), { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram16 to { }*) ], section "llvm.metadata" ; <[5 x { }*]*> [#uses=1] + at llvm.dbg.composite18 = internal constant %llvm.dbg.composite.type { i32 458771, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 2, i64 96, i64 32, i64 0, i32 0, { }* null, { }* bitcast ([5 x { }*]* @llvm.dbg.array17 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at llvm.dbg.derivedtype19 = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite18 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.array20 = internal constant [5 x { }*] [ { }* null, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype19 to { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) ], section "llvm.metadata" ; <[5 x { }*]*> [#uses=1] + at llvm.dbg.composite = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([5 x { }*]* @llvm.dbg.array20 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at .str21 = internal constant [13 x i8] c"__comp_ctor \00", section "llvm.metadata" ; <[13 x i8]*> [#uses=1] + at .str22 = internal constant [14 x i8] c"_ZN3VecC1Eiii\00", section "llvm.metadata" ; <[14 x i8]*> [#uses=1] + at llvm.dbg.array32 = internal constant [3 x { }*] [ { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite18 to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype12 to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype12 to { }*) ], section "llvm.metadata" ; <[3 x { }*]*> [#uses=1] + at llvm.dbg.composite33 = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array32 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at .str34 = internal constant [10 x i8] c"operator-\00", section "llvm.metadata" ; <[10 x i8]*> [#uses=1] + at .str35 = internal constant [14 x i8] c"_ZmiRK3VecS1_\00", section "llvm.metadata" ; <[14 x i8]*> [#uses=1] + at .str41 = internal constant [7 x i8] c"Sphere\00", section "llvm.metadata" ; <[7 x i8]*> [#uses=1] + at .str43 = internal constant [7 x i8] c"center\00", section "llvm.metadata" ; <[7 x i8]*> [#uses=1] + at llvm.dbg.derivedtype44 = internal constant %llvm.dbg.derivedtype.type { i32 458765, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([7 x i8]* @.str43, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 14, i64 96, i64 32, i64 0, i32 1, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite18 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.derivedtype45 = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite52 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.array46 = internal constant [3 x { }*] [ { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype45 to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype12 to { }*) ], section "llvm.metadata" ; <[3 x { }*]*> [#uses=1] + at llvm.dbg.composite47 = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array46 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at .str48 = internal constant [11 x i8] c"ray_sphere\00", section "llvm.metadata" ; <[11 x i8]*> [#uses=1] + at .str49 = internal constant [30 x i8] c"_ZN6Sphere10ray_sphereERK3Vec\00", section "llvm.metadata" ; <[30 x i8]*> [#uses=1] + at llvm.dbg.subprogram50 = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([11 x i8]* @.str48, i32 0, i32 0), i8* getelementptr ([11 x i8]* @.str48, i32 0, i32 0), i8* getelementptr ([30 x i8]* @.str49, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 16, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite47 to { }*), i1 false, i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at llvm.dbg.array51 = internal constant [2 x { }*] [ { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype44 to { }*), { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram50 to { }*) ], section "llvm.metadata" ; <[2 x { }*]*> [#uses=1] + at llvm.dbg.composite52 = internal constant %llvm.dbg.composite.type { i32 458771, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([7 x i8]* @.str41, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 12, i64 96, i64 32, i64 0, i32 0, { }* null, { }* bitcast ([2 x { }*]* @llvm.dbg.array51 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at llvm.dbg.derivedtype53 = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite52 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.array54 = internal constant [3 x { }*] [ { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype53 to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype12 to { }*) ], section "llvm.metadata" ; <[3 x { }*]*> [#uses=1] + at llvm.dbg.composite55 = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array54 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at llvm.dbg.subprogram56 = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([11 x i8]* @.str48, i32 0, i32 0), i8* getelementptr ([11 x i8]* @.str48, i32 0, i32 0), i8* getelementptr ([30 x i8]* @.str49, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 16, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite55 to { }*), i1 false, i1 true }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at .str61 = internal constant [2 x i8] c"v\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1] + at llvm.dbg.variable62 = internal constant %llvm.dbg.variable.type { i32 459008, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram56 to { }*), i8* getelementptr ([2 x i8]* @.str61, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 17, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite18 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=1] + +declare void @llvm.dbg.func.start({ }*) nounwind + +declare void @llvm.dbg.declare({ }*, { }*) nounwind + +declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind + +declare void @llvm.dbg.region.end({ }*) nounwind + +define i32 @_ZN6Sphere10ray_sphereERK3Vec(%struct.Sphere* %this, %struct.Vec* %Orig) nounwind { +entry: + %v = alloca %struct.Vec, align 8 ; <%struct.Vec*> [#uses=4] + call void @llvm.dbg.func.start({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram56 to { }*)) + %0 = bitcast %struct.Vec* %v to { }* ; <{ }*> [#uses=1] + call void @llvm.dbg.declare({ }* %0, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable62 to { }*)) + %1 = getelementptr %struct.Sphere* %this, i32 0, i32 0, i32 2 ; [#uses=1] + %2 = load i32* %1, align 4 ; [#uses=1] + %3 = getelementptr %struct.Vec* %Orig, i32 0, i32 2 ; [#uses=1] + %4 = load i32* %3, align 4 ; [#uses=1] + %5 = sub i32 %2, %4 ; [#uses=1] + %6 = getelementptr %struct.Sphere* %this, i32 0, i32 0, i32 1 ; [#uses=1] + %7 = load i32* %6, align 4 ; [#uses=1] + %8 = getelementptr %struct.Vec* %Orig, i32 0, i32 1 ; [#uses=1] + %9 = load i32* %8, align 4 ; [#uses=1] + %10 = sub i32 %7, %9 ; [#uses=1] + %11 = getelementptr %struct.Sphere* %this, i32 0, i32 0, i32 0 ; [#uses=1] + %12 = load i32* %11, align 4 ; [#uses=1] + %13 = getelementptr %struct.Vec* %Orig, i32 0, i32 0 ; [#uses=1] + %14 = load i32* %13, align 4 ; [#uses=1] + %15 = sub i32 %12, %14 ; [#uses=1] + %16 = getelementptr %struct.Vec* %v, i32 0, i32 0 ; [#uses=2] + store i32 %15, i32* %16, align 8 + %17 = getelementptr %struct.Vec* %v, i32 0, i32 1 ; [#uses=1] + store i32 %10, i32* %17, align 4 + %18 = getelementptr %struct.Vec* %v, i32 0, i32 2 ; [#uses=1] + store i32 %5, i32* %18, align 8 + call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) nounwind + call void @llvm.dbg.stoppoint(i32 9, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) nounwind + %19 = load i32* %16, align 8 ; [#uses=1] + call void @llvm.dbg.stoppoint(i32 18, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + call void @llvm.dbg.region.end({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram56 to { }*)) + ret i32 %19 +} From dpatel at apple.com Tue Feb 10 01:48:18 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 10 Feb 2009 07:48:18 -0000 Subject: [llvm-commits] [llvm] r64209 - in /llvm/trunk: lib/Transforms/Utils/CloneFunction.cpp test/Transforms/Inline/llvm.dbg.func.start.ll Message-ID: <200902100748.n1A7mIgb017528@zion.cs.uiuc.edu> Author: dpatel Date: Tue Feb 10 01:48:18 2009 New Revision: 64209 URL: http://llvm.org/viewvc/llvm-project?rev=64209&view=rev Log: Do not clone llvm.dbg.func.start and corresponding llvm.dbg.region.end during inlining. Added: llvm/trunk/test/Transforms/Inline/llvm.dbg.func.start.ll Modified: llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp Modified: llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp?rev=64209&r1=64208&r2=64209&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp Tue Feb 10 01:48:18 2009 @@ -17,6 +17,7 @@ #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Instructions.h" +#include "llvm/IntrinsicInst.h" #include "llvm/GlobalVariable.h" #include "llvm/Function.h" #include "llvm/Support/CFG.h" @@ -181,7 +182,7 @@ const char *NameSuffix; ClonedCodeInfo *CodeInfo; const TargetData *TD; - + Value *DbgFnStart; public: PruningFunctionCloner(Function *newFunc, const Function *oldFunc, DenseMap &valueMap, @@ -190,7 +191,7 @@ ClonedCodeInfo *codeInfo, const TargetData *td) : NewFunc(newFunc), OldFunc(oldFunc), ValueMap(valueMap), Returns(returns), - NameSuffix(nameSuffix), CodeInfo(codeInfo), TD(td) { + NameSuffix(nameSuffix), CodeInfo(codeInfo), TD(td), DbgFnStart(NULL) { } /// CloneBlock - The specified block is found to be reachable, clone it and @@ -231,7 +232,17 @@ ValueMap[II] = C; continue; } - + + // Do not clone llvm.dbg.func.start and corresponding llvm.dbg.region.end. + if (const DbgFuncStartInst *DFSI = dyn_cast(II)) { + DbgFnStart = DFSI->getSubprogram(); + continue; + } + if (const DbgRegionEndInst *DREIS = dyn_cast(II)) { + if (DREIS->getContext() == DbgFnStart) + continue; + } + Instruction *NewInst = II->clone(); if (II->hasName()) NewInst->setName(II->getName()+NameSuffix); Added: llvm/trunk/test/Transforms/Inline/llvm.dbg.func.start.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Inline/llvm.dbg.func.start.ll?rev=64209&view=auto ============================================================================== --- llvm/trunk/test/Transforms/Inline/llvm.dbg.func.start.ll (added) +++ llvm/trunk/test/Transforms/Inline/llvm.dbg.func.start.ll Tue Feb 10 01:48:18 2009 @@ -0,0 +1,86 @@ +; RUN: llvm-as < %s | opt -inline | llvm-dis | grep func.start | count 3 +; RUN: llvm-as < %s | opt -inline | llvm-dis | grep region.end | count 3 + %llvm.dbg.anchor.type = type { i32, i32 } + %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 } + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } + %llvm.dbg.composite.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, { }* } + %llvm.dbg.derivedtype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }* } + %llvm.dbg.subprogram.type = type { i32, { }*, { }*, i8*, i8*, i8*, { }*, i32, { }*, i1, i1 } + %llvm.dbg.variable.type = type { i32, { }*, i8*, { }*, i32, { }* } + at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] + at .str = internal constant [4 x i8] c"a.c\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at .str1 = internal constant [6 x i8] c"/tmp/\00", section "llvm.metadata" ; <[6 x i8]*> [#uses=1] + at .str2 = internal constant [55 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build 00)\00", section "llvm.metadata" ; <[55 x i8]*> [#uses=1] + at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([6 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([55 x i8]* @.str2, i32 0, i32 0), i1 true, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] + at .str3 = internal constant [4 x i8] c"int\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, i32 5 }, section "llvm.metadata" ; <%llvm.dbg.basictype.type*> [#uses=1] + at .str4 = internal constant [5 x i8] c"char\00", section "llvm.metadata" ; <[5 x i8]*> [#uses=1] + at llvm.dbg.basictype5 = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([5 x i8]* @.str4, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 8, i64 8, i64 0, i32 0, i32 6 }, section "llvm.metadata" ; <%llvm.dbg.basictype.type*> [#uses=1] + at llvm.dbg.derivedtype = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype5 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.array = internal constant [2 x { }*] [ { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*) ], section "llvm.metadata" ; <[2 x { }*]*> [#uses=1] + at llvm.dbg.composite = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([2 x { }*]* @llvm.dbg.array to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at llvm.dbg.subprograms = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 46 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] + at .str6 = internal constant [4 x i8] c"bar\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at llvm.dbg.subprogram = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str6, i32 0, i32 0), i8* getelementptr ([4 x i8]* @.str6, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 1, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite to { }*), i1 false, i1 true }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at .str7 = internal constant [2 x i8] c"c\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1] + at llvm.dbg.variable = internal constant %llvm.dbg.variable.type { i32 459009, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([2 x i8]* @.str7, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 1, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=1] + at llvm.dbg.array8 = internal constant [1 x { }*] [ { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) ], section "llvm.metadata" ; <[1 x { }*]*> [#uses=1] + at llvm.dbg.composite9 = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([1 x { }*]* @llvm.dbg.array8 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at .str10 = internal constant [5 x i8] c"main\00", section "llvm.metadata" ; <[5 x i8]*> [#uses=1] + at llvm.dbg.subprogram11 = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([5 x i8]* @.str10, i32 0, i32 0), i8* getelementptr ([5 x i8]* @.str10, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 2, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite9 to { }*), i1 false, i1 true }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] +@"\01LC" = internal constant [3 x i8] c"hi\00" ; <[3 x i8]*> [#uses=1] + +define i32 @bar(i8* %c) nounwind { +entry: + %c_addr = alloca i8* ; [#uses=3] + %retval = alloca i32 ; [#uses=2] + %0 = alloca i32 ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + call void @llvm.dbg.func.start({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*)) + %1 = bitcast i8** %c_addr to { }* ; <{ }*> [#uses=1] + call void @llvm.dbg.declare({ }* %1, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable to { }*)) + store i8* %c, i8** %c_addr + call void @llvm.dbg.stoppoint(i32 1, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %2 = load i8** %c_addr, align 4 ; [#uses=1] + %3 = load i8* %2, align 1 ; [#uses=1] + %4 = sext i8 %3 to i32 ; [#uses=1] + %5 = add i32 %4, 42 ; [#uses=1] + store i32 %5, i32* %0, align 4 + %6 = load i32* %0, align 4 ; [#uses=1] + store i32 %6, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval1 = load i32* %retval ; [#uses=1] + call void @llvm.dbg.stoppoint(i32 1, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + call void @llvm.dbg.region.end({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*)) + ret i32 %retval1 +} + +declare void @llvm.dbg.func.start({ }*) nounwind + +declare void @llvm.dbg.declare({ }*, { }*) nounwind + +declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind + +declare void @llvm.dbg.region.end({ }*) nounwind + +define i32 @main() nounwind { +entry: + %retval = alloca i32 ; [#uses=2] + %0 = alloca i32 ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + call void @llvm.dbg.func.start({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram11 to { }*)) + call void @llvm.dbg.stoppoint(i32 2, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %1 = call i32 @bar(i8* getelementptr ([3 x i8]* @"\01LC", i32 0, i32 0)) nounwind ; [#uses=1] + store i32 %1, i32* %0, align 4 + %2 = load i32* %0, align 4 ; [#uses=1] + store i32 %2, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval1 = load i32* %retval ; [#uses=1] + call void @llvm.dbg.stoppoint(i32 2, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + call void @llvm.dbg.region.end({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram11 to { }*)) + ret i32 %retval1 +} From evan.cheng at apple.com Tue Feb 10 02:30:11 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 10 Feb 2009 08:30:11 -0000 Subject: [llvm-commits] [llvm] r64210 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/ARM/memcpy-inline.ll test/CodeGen/X86/fold-pcmpeqd-0.ll test/CodeGen/X86/pr3457.ll Message-ID: <200902100830.n1A8UBhk018796@zion.cs.uiuc.edu> Author: evancheng Date: Tue Feb 10 02:30:11 2009 New Revision: 64210 URL: http://llvm.org/viewvc/llvm-project?rev=64210&view=rev Log: Fix PR3457: Ignore control successors when looking for closest scheduled successor. A control successor doesn't read result(s) produced by the scheduling unit being evaluated. Added: llvm/trunk/test/CodeGen/X86/pr3457.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=64210&r1=64209&r2=64210&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Feb 10 02:30:11 2009 @@ -30,7 +30,6 @@ #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" #include -#include "llvm/Support/CommandLine.h" using namespace llvm; STATISTIC(NumBacktracks, "Number of times scheduler backtracked"); @@ -1047,6 +1046,7 @@ unsigned MaxHeight = 0; for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); I != E; ++I) { + if (I->isCtrl()) continue; // ignore chain succs unsigned Height = I->getSUnit()->getHeight(); // If there are bunch of CopyToRegs stacked up, they should be considered // to be at the same position. Modified: llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll?rev=64210&r1=64209&r2=64210&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll (original) +++ llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll Tue Feb 10 02:30:11 2009 @@ -1,6 +1,9 @@ -; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep ldmia ; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep ldrb ; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep ldrh +; This used to look for ldmia. But it's no longer lucky enough to +; have the load / store instructions lined up just right after +; scheduler change for pr3457. We'll look for a robust solution +; later. %struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } @src = external global %struct.x Modified: llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll?rev=64210&r1=64209&r2=64210&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll (original) +++ llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll Tue Feb 10 02:30:11 2009 @@ -1,8 +1,10 @@ -; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | grep pcmpeqd | count 1 +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | not grep pcmpeqd +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | grep orps | grep CPI1_2 | count 2 ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep pcmpeqd | count 1 ; This testcase shouldn't need to spill the -1 value, ; so it should just use pcmpeqd to materialize an all-ones vector. +; For i386, cp load of -1 are folded. %struct.__ImageExecInfo = type <{ <4 x i32>, <4 x float>, <2 x i64>, i8*, i8*, i8*, i32, i32, i32, i32, i32 }> %struct._cl_image_format_t = type <{ i32, i32, i32 }> Added: llvm/trunk/test/CodeGen/X86/pr3457.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr3457.ll?rev=64210&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pr3457.ll (added) +++ llvm/trunk/test/CodeGen/X86/pr3457.ll Tue Feb 10 02:30:11 2009 @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | not grep fstpt +; PR3457 +; rdar://6548010 + +define void @foo(double* nocapture %P) nounwind { +entry: + %0 = tail call double (...)* @test() nounwind ; [#uses=2] + %1 = tail call double (...)* @test() nounwind ; [#uses=2] + %2 = mul double %0, %0 ; [#uses=1] + %3 = mul double %1, %1 ; [#uses=1] + %4 = add double %2, %3 ; [#uses=1] + store double %4, double* %P, align 8 + ret void +} + +declare double @test(...) From isanbard at gmail.com Tue Feb 10 05:10:33 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 10 Feb 2009 11:10:33 -0000 Subject: [llvm-commits] [llvm] r64214 - in /llvm/branches/Apple/Dib: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/ARM/memcpy-inline.ll test/CodeGen/X86/fold-pcmpeqd-0.ll Message-ID: <200902101110.n1ABAZqE001868@zion.cs.uiuc.edu> Author: void Date: Tue Feb 10 05:10:12 2009 New Revision: 64214 URL: http://llvm.org/viewvc/llvm-project?rev=64214&view=rev Log: Pull r64210 into Dib: Fix PR3457: Ignore control successors when looking for closest scheduled successor. A control successor doesn't read result(s) produced by the scheduling unit being evaluated. Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp llvm/branches/Apple/Dib/test/CodeGen/ARM/memcpy-inline.ll llvm/branches/Apple/Dib/test/CodeGen/X86/fold-pcmpeqd-0.ll Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=64214&r1=64213&r2=64214&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Feb 10 05:10:12 2009 @@ -30,7 +30,6 @@ #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" #include -#include "llvm/Support/CommandLine.h" using namespace llvm; STATISTIC(NumBacktracks, "Number of times scheduler backtracked"); @@ -1047,6 +1046,7 @@ unsigned MaxHeight = 0; for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); I != E; ++I) { + if (I->isCtrl()) continue; // ignore chain succs unsigned Height = I->getSUnit()->getHeight(); // If there are bunch of CopyToRegs stacked up, they should be considered // to be at the same position. Modified: llvm/branches/Apple/Dib/test/CodeGen/ARM/memcpy-inline.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/ARM/memcpy-inline.ll?rev=64214&r1=64213&r2=64214&view=diff ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/ARM/memcpy-inline.ll (original) +++ llvm/branches/Apple/Dib/test/CodeGen/ARM/memcpy-inline.ll Tue Feb 10 05:10:12 2009 @@ -1,6 +1,9 @@ -; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep ldmia ; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep ldrb ; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep ldrh +; This used to look for ldmia. But it's no longer lucky enough to +; have the load / store instructions lined up just right after +; scheduler change for pr3457. We'll look for a robust solution +; later. %struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } @src = external global %struct.x Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/fold-pcmpeqd-0.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/fold-pcmpeqd-0.ll?rev=64214&r1=64213&r2=64214&view=diff ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/X86/fold-pcmpeqd-0.ll (original) +++ llvm/branches/Apple/Dib/test/CodeGen/X86/fold-pcmpeqd-0.ll Tue Feb 10 05:10:12 2009 @@ -1,8 +1,10 @@ -; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | grep pcmpeqd | count 1 +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | not grep pcmpeqd +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | grep orps | grep CPI1_2 | count 2 ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep pcmpeqd | count 1 ; This testcase shouldn't need to spill the -1 value, ; so it should just use pcmpeqd to materialize an all-ones vector. +; For i386, cp load of -1 are folded. %struct.__ImageExecInfo = type <{ <4 x i32>, <4 x float>, <2 x i64>, i8*, i8*, i8*, i32, i32, i32, i32, i32 }> %struct._cl_image_format_t = type <{ i32, i32, i32 }> From isanbard at gmail.com Tue Feb 10 05:11:31 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 10 Feb 2009 11:11:31 -0000 Subject: [llvm-commits] [llvm] r64215 - in /llvm/branches/Apple/Dib/test/CodeGen/X86: 2009-02-08-CoalescerBug.ll pr3457.ll Message-ID: <200902101111.n1ABBVYT001916@zion.cs.uiuc.edu> Author: void Date: Tue Feb 10 05:11:30 2009 New Revision: 64215 URL: http://llvm.org/viewvc/llvm-project?rev=64215&view=rev Log: New tests. Added: llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-08-CoalescerBug.ll llvm/branches/Apple/Dib/test/CodeGen/X86/pr3457.ll Added: llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-08-CoalescerBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-08-CoalescerBug.ll?rev=64215&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-08-CoalescerBug.ll (added) +++ llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-08-CoalescerBug.ll Tue Feb 10 05:11:30 2009 @@ -0,0 +1,22 @@ +; RUN: llvm-as < %s | llc -march=x86 +; PR3486 + +define i32 @foo(i8 signext %p_26) nounwind { +entry: + %0 = icmp eq i8 %p_26, 0 ; [#uses=2] + %or.cond = or i1 false, %0 ; [#uses=2] + %iftmp.1.0 = zext i1 %or.cond to i16 ; [#uses=1] + br i1 %0, label %bb.i, label %bar.exit + +bb.i: ; preds = %entry + %1 = zext i1 %or.cond to i32 ; [#uses=1] + %2 = sdiv i32 %1, 0 ; [#uses=1] + %3 = trunc i32 %2 to i16 ; [#uses=1] + br label %bar.exit + +bar.exit: ; preds = %bb.i, %entry + %4 = phi i16 [ %3, %bb.i ], [ %iftmp.1.0, %entry ] ; [#uses=1] + %5 = trunc i16 %4 to i8 ; [#uses=1] + %6 = sext i8 %5 to i32 ; [#uses=1] + ret i32 %6 +} Added: llvm/branches/Apple/Dib/test/CodeGen/X86/pr3457.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/pr3457.ll?rev=64215&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/X86/pr3457.ll (added) +++ llvm/branches/Apple/Dib/test/CodeGen/X86/pr3457.ll Tue Feb 10 05:11:30 2009 @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | not grep fstpt +; PR3457 +; rdar://6548010 + +define void @foo(double* nocapture %P) nounwind { +entry: + %0 = tail call double (...)* @test() nounwind ; [#uses=2] + %1 = tail call double (...)* @test() nounwind ; [#uses=2] + %2 = mul double %0, %0 ; [#uses=1] + %3 = mul double %1, %1 ; [#uses=1] + %4 = add double %2, %3 ; [#uses=1] + store double %4, double* %P, align 8 + ret void +} + +declare double @test(...) From isanbard at gmail.com Tue Feb 10 05:13:49 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 10 Feb 2009 11:13:49 -0000 Subject: [llvm-commits] [llvm] r64216 - in /llvm/branches/Apple/Dib: include/llvm/Transforms/Utils/Local.h lib/Transforms/Scalar/ScalarReplAggregates.cpp lib/Transforms/Utils/Local.cpp test/Transforms/ScalarRepl/debuginfo.ll Message-ID: <200902101113.n1ABDnCK002024@zion.cs.uiuc.edu> Author: void Date: Tue Feb 10 05:13:48 2009 New Revision: 64216 URL: http://llvm.org/viewvc/llvm-project?rev=64216&view=rev Log: Pull r64207 into Dib: Enable scalar replacement of AllocaInst whose one of the user is dbg info. Added: llvm/branches/Apple/Dib/test/Transforms/ScalarRepl/debuginfo.ll Modified: llvm/branches/Apple/Dib/include/llvm/Transforms/Utils/Local.h llvm/branches/Apple/Dib/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/branches/Apple/Dib/lib/Transforms/Utils/Local.cpp Modified: llvm/branches/Apple/Dib/include/llvm/Transforms/Utils/Local.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/Transforms/Utils/Local.h?rev=64216&r1=64215&r2=64216&view=diff ============================================================================== --- llvm/branches/Apple/Dib/include/llvm/Transforms/Utils/Local.h (original) +++ llvm/branches/Apple/Dib/include/llvm/Transforms/Utils/Local.h Tue Feb 10 05:13:48 2009 @@ -25,6 +25,7 @@ class AllocaInst; class ConstantExpr; class TargetData; +class DbgInfoIntrinsic; template class SmallVectorImpl; @@ -94,6 +95,11 @@ /// The phi node is deleted and it returns the pointer to the alloca inserted. AllocaInst *DemotePHIToStack(PHINode *P, Instruction *AllocaPoint = 0); +/// OnlyUsedByDbgIntrinsics - Return true if the instruction I is only used +/// by DbgIntrinsics. If DbgInUses is specified then the vector is filled +/// with DbgInfoIntrinsic that use the instruction I. +bool OnlyUsedByDbgInfoIntrinsics(Instruction *I, + SmallVectorImpl *DbgInUses = 0); } // End llvm namespace #endif Modified: llvm/branches/Apple/Dib/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=64216&r1=64215&r2=64216&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/branches/Apple/Dib/lib/Transforms/Scalar/ScalarReplAggregates.cpp Tue Feb 10 05:13:48 2009 @@ -31,6 +31,7 @@ #include "llvm/Analysis/Dominators.h" #include "llvm/Target/TargetData.h" #include "llvm/Transforms/Utils/PromoteMemToReg.h" +#include "llvm/Transforms/Utils/Local.h" #include "llvm/Support/Debug.h" #include "llvm/Support/GetElementPtrTypeIterator.h" #include "llvm/Support/MathExtras.h" @@ -79,9 +80,9 @@ /// isUnsafe - This is set to true if the alloca cannot be SROA'd. bool isUnsafe : 1; - /// needsCanon - This is set to true if there is some use of the alloca - /// that requires canonicalization. - bool needsCanon : 1; + /// needsCleanup - This is set to true if there is some use of the alloca + /// that requires cleanup. + bool needsCleanup : 1; /// isMemCpySrc - This is true if this aggregate is memcpy'd from. bool isMemCpySrc : 1; @@ -90,7 +91,7 @@ bool isMemCpyDst : 1; AllocaInfo() - : isUnsafe(false), needsCanon(false), + : isUnsafe(false), needsCleanup(false), isMemCpySrc(false), isMemCpyDst(false) {} }; @@ -111,7 +112,8 @@ void DoScalarReplacement(AllocationInst *AI, std::vector &WorkList); - void CanonicalizeAllocaUsers(AllocationInst *AI); + void CleanupGEP(GetElementPtrInst *GEP); + void CleanupAllocaUsers(AllocationInst *AI); AllocaInst *AddNewAlloca(Function &F, const Type *Ty, AllocationInst *Base); void RewriteBitCastUserOfAlloca(Instruction *BCInst, AllocationInst *AI, @@ -243,7 +245,7 @@ case 0: // Not safe to scalar replace. break; case 1: // Safe, but requires cleanup/canonicalizations first - CanonicalizeAllocaUsers(AI); + CleanupAllocaUsers(AI); // FALL THROUGH. case 3: // Safe to scalar replace. DoScalarReplacement(AI, WorkList); @@ -514,7 +516,7 @@ // out if this is the only problem. if ((NumElements == 1 || NumElements == 2) && AllUsersAreLoads(GEPI)) { - Info.needsCanon = true; + Info.needsCleanup = true; return; // Canonicalization required! } return MarkUnsafe(Info); @@ -621,7 +623,17 @@ continue; } return MarkUnsafe(Info); - } else { + } else if (isa(UI)) { + // If one user is DbgInfoIntrinsic then check if all users are + // DbgInfoIntrinsics. + if (OnlyUsedByDbgInfoIntrinsics(BC)) { + Info.needsCleanup = true; + return; + } + else + MarkUnsafe(Info); + } + else { return MarkUnsafe(Info); } if (Info.isUnsafe) return; @@ -1087,59 +1099,76 @@ return 0; // If we require cleanup, return 1, otherwise return 3. - return Info.needsCanon ? 1 : 3; + return Info.needsCleanup ? 1 : 3; } -/// CanonicalizeAllocaUsers - If SROA reported that it can promote the specified +/// CleanupGEP - GEP is used by an Alloca, which can be prompted after the GEP +/// is canonicalized here. +void SROA::CleanupGEP(GetElementPtrInst *GEPI) { + gep_type_iterator I = gep_type_begin(GEPI); + ++I; + + if (const ArrayType *AT = dyn_cast(*I)) { + uint64_t NumElements = AT->getNumElements(); + + if (!isa(I.getOperand())) { + if (NumElements == 1) { + GEPI->setOperand(2, Constant::getNullValue(Type::Int32Ty)); + } else { + assert(NumElements == 2 && "Unhandled case!"); + // All users of the GEP must be loads. At each use of the GEP, insert + // two loads of the appropriate indexed GEP and select between them. + Value *IsOne = new ICmpInst(ICmpInst::ICMP_NE, I.getOperand(), + Constant::getNullValue(I.getOperand()->getType()), + "isone", GEPI); + // Insert the new GEP instructions, which are properly indexed. + SmallVector Indices(GEPI->op_begin()+1, GEPI->op_end()); + Indices[1] = Constant::getNullValue(Type::Int32Ty); + Value *ZeroIdx = GetElementPtrInst::Create(GEPI->getOperand(0), + Indices.begin(), + Indices.end(), + GEPI->getName()+".0", GEPI); + Indices[1] = ConstantInt::get(Type::Int32Ty, 1); + Value *OneIdx = GetElementPtrInst::Create(GEPI->getOperand(0), + Indices.begin(), + Indices.end(), + GEPI->getName()+".1", GEPI); + // Replace all loads of the variable index GEP with loads from both + // indexes and a select. + while (!GEPI->use_empty()) { + LoadInst *LI = cast(GEPI->use_back()); + Value *Zero = new LoadInst(ZeroIdx, LI->getName()+".0", LI); + Value *One = new LoadInst(OneIdx , LI->getName()+".1", LI); + Value *R = SelectInst::Create(IsOne, One, Zero, LI->getName(), LI); + LI->replaceAllUsesWith(R); + LI->eraseFromParent(); + } + GEPI->eraseFromParent(); + } + } + } +} + +/// CleanupAllocaUsers - If SROA reported that it can promote the specified /// allocation, but only if cleaned up, perform the cleanups required. -void SROA::CanonicalizeAllocaUsers(AllocationInst *AI) { +void SROA::CleanupAllocaUsers(AllocationInst *AI) { // At this point, we know that the end result will be SROA'd and promoted, so // we can insert ugly code if required so long as sroa+mem2reg will clean it // up. for (Value::use_iterator UI = AI->use_begin(), E = AI->use_end(); UI != E; ) { - GetElementPtrInst *GEPI = dyn_cast(*UI++); - if (!GEPI) continue; - gep_type_iterator I = gep_type_begin(GEPI); - ++I; - - if (const ArrayType *AT = dyn_cast(*I)) { - uint64_t NumElements = AT->getNumElements(); - - if (!isa(I.getOperand())) { - if (NumElements == 1) { - GEPI->setOperand(2, Constant::getNullValue(Type::Int32Ty)); - } else { - assert(NumElements == 2 && "Unhandled case!"); - // All users of the GEP must be loads. At each use of the GEP, insert - // two loads of the appropriate indexed GEP and select between them. - Value *IsOne = new ICmpInst(ICmpInst::ICMP_NE, I.getOperand(), - Constant::getNullValue(I.getOperand()->getType()), - "isone", GEPI); - // Insert the new GEP instructions, which are properly indexed. - SmallVector Indices(GEPI->op_begin()+1, GEPI->op_end()); - Indices[1] = Constant::getNullValue(Type::Int32Ty); - Value *ZeroIdx = GetElementPtrInst::Create(GEPI->getOperand(0), - Indices.begin(), - Indices.end(), - GEPI->getName()+".0", GEPI); - Indices[1] = ConstantInt::get(Type::Int32Ty, 1); - Value *OneIdx = GetElementPtrInst::Create(GEPI->getOperand(0), - Indices.begin(), - Indices.end(), - GEPI->getName()+".1", GEPI); - // Replace all loads of the variable index GEP with loads from both - // indexes and a select. - while (!GEPI->use_empty()) { - LoadInst *LI = cast(GEPI->use_back()); - Value *Zero = new LoadInst(ZeroIdx, LI->getName()+".0", LI); - Value *One = new LoadInst(OneIdx , LI->getName()+".1", LI); - Value *R = SelectInst::Create(IsOne, One, Zero, LI->getName(), LI); - LI->replaceAllUsesWith(R); - LI->eraseFromParent(); - } - GEPI->eraseFromParent(); + User *U = *UI++; + if (GetElementPtrInst *GEPI = dyn_cast(U)) + CleanupGEP(GEPI); + else if (Instruction *I = dyn_cast(U)) { + SmallVector DbgInUses; + if (OnlyUsedByDbgInfoIntrinsics(I, &DbgInUses)) { + // Safe to remove debug info uses. + while (!DbgInUses.empty()) { + DbgInfoIntrinsic *DI = DbgInUses.back(); DbgInUses.pop_back(); + DI->eraseFromParent(); } + I->eraseFromParent(); } } } Modified: llvm/branches/Apple/Dib/lib/Transforms/Utils/Local.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Transforms/Utils/Local.cpp?rev=64216&r1=64215&r2=64216&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Transforms/Utils/Local.cpp (original) +++ llvm/branches/Apple/Dib/lib/Transforms/Utils/Local.cpp Tue Feb 10 05:13:48 2009 @@ -248,3 +248,25 @@ // Nuke BB. PredBB->eraseFromParent(); } + +/// OnlyUsedByDbgIntrinsics - Return true if the instruction I is only used +/// by DbgIntrinsics. If DbgInUses is specified then the vector is filled +/// with the DbgInfoIntrinsic that use the instruction I. +bool llvm::OnlyUsedByDbgInfoIntrinsics(Instruction *I, + SmallVectorImpl *DbgInUses) { + if (DbgInUses) + DbgInUses->clear(); + + for (Value::use_iterator UI = I->use_begin(), UE = I->use_end(); UI != UE; + ++UI) { + if (DbgInfoIntrinsic *DI = dyn_cast(*UI)) { + if (DbgInUses) + DbgInUses->push_back(DI); + } else { + if (DbgInUses) + DbgInUses->clear(); + return false; + } + } + return true; +} Added: llvm/branches/Apple/Dib/test/Transforms/ScalarRepl/debuginfo.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/Transforms/ScalarRepl/debuginfo.ll?rev=64216&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/Transforms/ScalarRepl/debuginfo.ll (added) +++ llvm/branches/Apple/Dib/test/Transforms/ScalarRepl/debuginfo.ll Tue Feb 10 05:13:48 2009 @@ -0,0 +1,105 @@ +; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | not grep alloca + %llvm.dbg.anchor.type = type { i32, i32 } + %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 } + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } + %llvm.dbg.composite.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, { }* } + %llvm.dbg.derivedtype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }* } + %llvm.dbg.subprogram.type = type { i32, { }*, { }*, i8*, i8*, i8*, { }*, i32, { }*, i1, i1 } + %llvm.dbg.variable.type = type { i32, { }*, i8*, { }*, i32, { }* } + %struct.Sphere = type { %struct.Vec } + %struct.Vec = type { i32, i32, i32 } + at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] + at .str = internal constant [6 x i8] c"r.cpp\00", section "llvm.metadata" ; <[6 x i8]*> [#uses=1] + at .str1 = internal constant [5 x i8] c"/tmp\00", section "llvm.metadata" ; <[5 x i8]*> [#uses=1] + at .str2 = internal constant [55 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build 00)\00", section "llvm.metadata" ; <[55 x i8]*> [#uses=1] + at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 4, i8* getelementptr ([6 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([5 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([55 x i8]* @.str2, i32 0, i32 0), i1 true, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] + at .str3 = internal constant [4 x i8] c"Vec\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at .str4 = internal constant [4 x i8] c"int\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str4, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, i32 5 }, section "llvm.metadata" ; <%llvm.dbg.basictype.type*> [#uses=1] + at .str5 = internal constant [2 x i8] c"x\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1] + at llvm.dbg.derivedtype = internal constant %llvm.dbg.derivedtype.type { i32 458765, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([2 x i8]* @.str5, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 4, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at .str6 = internal constant [2 x i8] c"y\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1] + at llvm.dbg.derivedtype7 = internal constant %llvm.dbg.derivedtype.type { i32 458765, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([2 x i8]* @.str6, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 4, i64 32, i64 32, i64 32, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at .str8 = internal constant [2 x i8] c"z\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1] + at llvm.dbg.derivedtype9 = internal constant %llvm.dbg.derivedtype.type { i32 458765, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([2 x i8]* @.str8, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 4, i64 32, i64 32, i64 64, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.derivedtype10 = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite18 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.derivedtype11 = internal constant %llvm.dbg.derivedtype.type { i32 458790, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 96, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite18 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.derivedtype12 = internal constant %llvm.dbg.derivedtype.type { i32 458768, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype11 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.array = internal constant [3 x { }*] [ { }* null, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype10 to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype12 to { }*) ], section "llvm.metadata" ; <[3 x { }*]*> [#uses=1] + at llvm.dbg.composite13 = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at llvm.dbg.subprograms = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 46 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] + at llvm.dbg.subprogram = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 2, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite13 to { }*), i1 false, i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at llvm.dbg.array14 = internal constant [5 x { }*] [ { }* null, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype10 to { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) ], section "llvm.metadata" ; <[5 x { }*]*> [#uses=1] + at llvm.dbg.composite15 = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([5 x { }*]* @llvm.dbg.array14 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at llvm.dbg.subprogram16 = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 5, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite15 to { }*), i1 false, i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at llvm.dbg.array17 = internal constant [5 x { }*] [ { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype7 to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype9 to { }*), { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram16 to { }*) ], section "llvm.metadata" ; <[5 x { }*]*> [#uses=1] + at llvm.dbg.composite18 = internal constant %llvm.dbg.composite.type { i32 458771, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 2, i64 96, i64 32, i64 0, i32 0, { }* null, { }* bitcast ([5 x { }*]* @llvm.dbg.array17 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at llvm.dbg.derivedtype19 = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite18 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.array20 = internal constant [5 x { }*] [ { }* null, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype19 to { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) ], section "llvm.metadata" ; <[5 x { }*]*> [#uses=1] + at llvm.dbg.composite = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([5 x { }*]* @llvm.dbg.array20 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at .str21 = internal constant [13 x i8] c"__comp_ctor \00", section "llvm.metadata" ; <[13 x i8]*> [#uses=1] + at .str22 = internal constant [14 x i8] c"_ZN3VecC1Eiii\00", section "llvm.metadata" ; <[14 x i8]*> [#uses=1] + at llvm.dbg.array32 = internal constant [3 x { }*] [ { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite18 to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype12 to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype12 to { }*) ], section "llvm.metadata" ; <[3 x { }*]*> [#uses=1] + at llvm.dbg.composite33 = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array32 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at .str34 = internal constant [10 x i8] c"operator-\00", section "llvm.metadata" ; <[10 x i8]*> [#uses=1] + at .str35 = internal constant [14 x i8] c"_ZmiRK3VecS1_\00", section "llvm.metadata" ; <[14 x i8]*> [#uses=1] + at .str41 = internal constant [7 x i8] c"Sphere\00", section "llvm.metadata" ; <[7 x i8]*> [#uses=1] + at .str43 = internal constant [7 x i8] c"center\00", section "llvm.metadata" ; <[7 x i8]*> [#uses=1] + at llvm.dbg.derivedtype44 = internal constant %llvm.dbg.derivedtype.type { i32 458765, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([7 x i8]* @.str43, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 14, i64 96, i64 32, i64 0, i32 1, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite18 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.derivedtype45 = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite52 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.array46 = internal constant [3 x { }*] [ { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype45 to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype12 to { }*) ], section "llvm.metadata" ; <[3 x { }*]*> [#uses=1] + at llvm.dbg.composite47 = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array46 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at .str48 = internal constant [11 x i8] c"ray_sphere\00", section "llvm.metadata" ; <[11 x i8]*> [#uses=1] + at .str49 = internal constant [30 x i8] c"_ZN6Sphere10ray_sphereERK3Vec\00", section "llvm.metadata" ; <[30 x i8]*> [#uses=1] + at llvm.dbg.subprogram50 = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([11 x i8]* @.str48, i32 0, i32 0), i8* getelementptr ([11 x i8]* @.str48, i32 0, i32 0), i8* getelementptr ([30 x i8]* @.str49, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 16, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite47 to { }*), i1 false, i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at llvm.dbg.array51 = internal constant [2 x { }*] [ { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype44 to { }*), { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram50 to { }*) ], section "llvm.metadata" ; <[2 x { }*]*> [#uses=1] + at llvm.dbg.composite52 = internal constant %llvm.dbg.composite.type { i32 458771, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([7 x i8]* @.str41, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 12, i64 96, i64 32, i64 0, i32 0, { }* null, { }* bitcast ([2 x { }*]* @llvm.dbg.array51 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at llvm.dbg.derivedtype53 = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite52 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.array54 = internal constant [3 x { }*] [ { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype53 to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype12 to { }*) ], section "llvm.metadata" ; <[3 x { }*]*> [#uses=1] + at llvm.dbg.composite55 = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array54 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at llvm.dbg.subprogram56 = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([11 x i8]* @.str48, i32 0, i32 0), i8* getelementptr ([11 x i8]* @.str48, i32 0, i32 0), i8* getelementptr ([30 x i8]* @.str49, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 16, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite55 to { }*), i1 false, i1 true }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at .str61 = internal constant [2 x i8] c"v\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1] + at llvm.dbg.variable62 = internal constant %llvm.dbg.variable.type { i32 459008, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram56 to { }*), i8* getelementptr ([2 x i8]* @.str61, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 17, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite18 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=1] + +declare void @llvm.dbg.func.start({ }*) nounwind + +declare void @llvm.dbg.declare({ }*, { }*) nounwind + +declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind + +declare void @llvm.dbg.region.end({ }*) nounwind + +define i32 @_ZN6Sphere10ray_sphereERK3Vec(%struct.Sphere* %this, %struct.Vec* %Orig) nounwind { +entry: + %v = alloca %struct.Vec, align 8 ; <%struct.Vec*> [#uses=4] + call void @llvm.dbg.func.start({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram56 to { }*)) + %0 = bitcast %struct.Vec* %v to { }* ; <{ }*> [#uses=1] + call void @llvm.dbg.declare({ }* %0, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable62 to { }*)) + %1 = getelementptr %struct.Sphere* %this, i32 0, i32 0, i32 2 ; [#uses=1] + %2 = load i32* %1, align 4 ; [#uses=1] + %3 = getelementptr %struct.Vec* %Orig, i32 0, i32 2 ; [#uses=1] + %4 = load i32* %3, align 4 ; [#uses=1] + %5 = sub i32 %2, %4 ; [#uses=1] + %6 = getelementptr %struct.Sphere* %this, i32 0, i32 0, i32 1 ; [#uses=1] + %7 = load i32* %6, align 4 ; [#uses=1] + %8 = getelementptr %struct.Vec* %Orig, i32 0, i32 1 ; [#uses=1] + %9 = load i32* %8, align 4 ; [#uses=1] + %10 = sub i32 %7, %9 ; [#uses=1] + %11 = getelementptr %struct.Sphere* %this, i32 0, i32 0, i32 0 ; [#uses=1] + %12 = load i32* %11, align 4 ; [#uses=1] + %13 = getelementptr %struct.Vec* %Orig, i32 0, i32 0 ; [#uses=1] + %14 = load i32* %13, align 4 ; [#uses=1] + %15 = sub i32 %12, %14 ; [#uses=1] + %16 = getelementptr %struct.Vec* %v, i32 0, i32 0 ; [#uses=2] + store i32 %15, i32* %16, align 8 + %17 = getelementptr %struct.Vec* %v, i32 0, i32 1 ; [#uses=1] + store i32 %10, i32* %17, align 4 + %18 = getelementptr %struct.Vec* %v, i32 0, i32 2 ; [#uses=1] + store i32 %5, i32* %18, align 8 + call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) nounwind + call void @llvm.dbg.stoppoint(i32 9, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) nounwind + %19 = load i32* %16, align 8 ; [#uses=1] + call void @llvm.dbg.stoppoint(i32 18, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + call void @llvm.dbg.region.end({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram56 to { }*)) + ret i32 %19 +} From isanbard at gmail.com Tue Feb 10 05:14:56 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 10 Feb 2009 11:14:56 -0000 Subject: [llvm-commits] [llvm] r64217 - in /llvm/branches/Apple/Dib: lib/Transforms/Utils/CloneFunction.cpp test/Transforms/Inline/llvm.dbg.func.start.ll Message-ID: <200902101114.n1ABEuIB002077@zion.cs.uiuc.edu> Author: void Date: Tue Feb 10 05:14:56 2009 New Revision: 64217 URL: http://llvm.org/viewvc/llvm-project?rev=64217&view=rev Log: Pull r64209 into Dib: Do not clone llvm.dbg.func.start and corresponding llvm.dbg.region.end during inlining. Added: llvm/branches/Apple/Dib/test/Transforms/Inline/llvm.dbg.func.start.ll Modified: llvm/branches/Apple/Dib/lib/Transforms/Utils/CloneFunction.cpp Modified: llvm/branches/Apple/Dib/lib/Transforms/Utils/CloneFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Transforms/Utils/CloneFunction.cpp?rev=64217&r1=64216&r2=64217&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Transforms/Utils/CloneFunction.cpp (original) +++ llvm/branches/Apple/Dib/lib/Transforms/Utils/CloneFunction.cpp Tue Feb 10 05:14:56 2009 @@ -17,6 +17,7 @@ #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Instructions.h" +#include "llvm/IntrinsicInst.h" #include "llvm/GlobalVariable.h" #include "llvm/Function.h" #include "llvm/Support/CFG.h" @@ -181,7 +182,7 @@ const char *NameSuffix; ClonedCodeInfo *CodeInfo; const TargetData *TD; - + Value *DbgFnStart; public: PruningFunctionCloner(Function *newFunc, const Function *oldFunc, DenseMap &valueMap, @@ -190,7 +191,7 @@ ClonedCodeInfo *codeInfo, const TargetData *td) : NewFunc(newFunc), OldFunc(oldFunc), ValueMap(valueMap), Returns(returns), - NameSuffix(nameSuffix), CodeInfo(codeInfo), TD(td) { + NameSuffix(nameSuffix), CodeInfo(codeInfo), TD(td), DbgFnStart(NULL) { } /// CloneBlock - The specified block is found to be reachable, clone it and @@ -231,7 +232,17 @@ ValueMap[II] = C; continue; } - + + // Do not clone llvm.dbg.func.start and corresponding llvm.dbg.region.end. + if (const DbgFuncStartInst *DFSI = dyn_cast(II)) { + DbgFnStart = DFSI->getSubprogram(); + continue; + } + if (const DbgRegionEndInst *DREIS = dyn_cast(II)) { + if (DREIS->getContext() == DbgFnStart) + continue; + } + Instruction *NewInst = II->clone(); if (II->hasName()) NewInst->setName(II->getName()+NameSuffix); Added: llvm/branches/Apple/Dib/test/Transforms/Inline/llvm.dbg.func.start.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/Transforms/Inline/llvm.dbg.func.start.ll?rev=64217&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/Transforms/Inline/llvm.dbg.func.start.ll (added) +++ llvm/branches/Apple/Dib/test/Transforms/Inline/llvm.dbg.func.start.ll Tue Feb 10 05:14:56 2009 @@ -0,0 +1,86 @@ +; RUN: llvm-as < %s | opt -inline | llvm-dis | grep func.start | count 3 +; RUN: llvm-as < %s | opt -inline | llvm-dis | grep region.end | count 3 + %llvm.dbg.anchor.type = type { i32, i32 } + %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 } + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } + %llvm.dbg.composite.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, { }* } + %llvm.dbg.derivedtype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }* } + %llvm.dbg.subprogram.type = type { i32, { }*, { }*, i8*, i8*, i8*, { }*, i32, { }*, i1, i1 } + %llvm.dbg.variable.type = type { i32, { }*, i8*, { }*, i32, { }* } + at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] + at .str = internal constant [4 x i8] c"a.c\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at .str1 = internal constant [6 x i8] c"/tmp/\00", section "llvm.metadata" ; <[6 x i8]*> [#uses=1] + at .str2 = internal constant [55 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build 00)\00", section "llvm.metadata" ; <[55 x i8]*> [#uses=1] + at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([6 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([55 x i8]* @.str2, i32 0, i32 0), i1 true, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] + at .str3 = internal constant [4 x i8] c"int\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, i32 5 }, section "llvm.metadata" ; <%llvm.dbg.basictype.type*> [#uses=1] + at .str4 = internal constant [5 x i8] c"char\00", section "llvm.metadata" ; <[5 x i8]*> [#uses=1] + at llvm.dbg.basictype5 = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([5 x i8]* @.str4, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 8, i64 8, i64 0, i32 0, i32 6 }, section "llvm.metadata" ; <%llvm.dbg.basictype.type*> [#uses=1] + at llvm.dbg.derivedtype = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype5 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.array = internal constant [2 x { }*] [ { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*) ], section "llvm.metadata" ; <[2 x { }*]*> [#uses=1] + at llvm.dbg.composite = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([2 x { }*]* @llvm.dbg.array to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at llvm.dbg.subprograms = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 46 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] + at .str6 = internal constant [4 x i8] c"bar\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at llvm.dbg.subprogram = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str6, i32 0, i32 0), i8* getelementptr ([4 x i8]* @.str6, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 1, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite to { }*), i1 false, i1 true }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at .str7 = internal constant [2 x i8] c"c\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1] + at llvm.dbg.variable = internal constant %llvm.dbg.variable.type { i32 459009, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([2 x i8]* @.str7, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 1, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=1] + at llvm.dbg.array8 = internal constant [1 x { }*] [ { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) ], section "llvm.metadata" ; <[1 x { }*]*> [#uses=1] + at llvm.dbg.composite9 = internal constant %llvm.dbg.composite.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([1 x { }*]* @llvm.dbg.array8 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at .str10 = internal constant [5 x i8] c"main\00", section "llvm.metadata" ; <[5 x i8]*> [#uses=1] + at llvm.dbg.subprogram11 = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([5 x i8]* @.str10, i32 0, i32 0), i8* getelementptr ([5 x i8]* @.str10, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 2, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite9 to { }*), i1 false, i1 true }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] +@"\01LC" = internal constant [3 x i8] c"hi\00" ; <[3 x i8]*> [#uses=1] + +define i32 @bar(i8* %c) nounwind { +entry: + %c_addr = alloca i8* ; [#uses=3] + %retval = alloca i32 ; [#uses=2] + %0 = alloca i32 ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + call void @llvm.dbg.func.start({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*)) + %1 = bitcast i8** %c_addr to { }* ; <{ }*> [#uses=1] + call void @llvm.dbg.declare({ }* %1, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable to { }*)) + store i8* %c, i8** %c_addr + call void @llvm.dbg.stoppoint(i32 1, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %2 = load i8** %c_addr, align 4 ; [#uses=1] + %3 = load i8* %2, align 1 ; [#uses=1] + %4 = sext i8 %3 to i32 ; [#uses=1] + %5 = add i32 %4, 42 ; [#uses=1] + store i32 %5, i32* %0, align 4 + %6 = load i32* %0, align 4 ; [#uses=1] + store i32 %6, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval1 = load i32* %retval ; [#uses=1] + call void @llvm.dbg.stoppoint(i32 1, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + call void @llvm.dbg.region.end({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*)) + ret i32 %retval1 +} + +declare void @llvm.dbg.func.start({ }*) nounwind + +declare void @llvm.dbg.declare({ }*, { }*) nounwind + +declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind + +declare void @llvm.dbg.region.end({ }*) nounwind + +define i32 @main() nounwind { +entry: + %retval = alloca i32 ; [#uses=2] + %0 = alloca i32 ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + call void @llvm.dbg.func.start({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram11 to { }*)) + call void @llvm.dbg.stoppoint(i32 2, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %1 = call i32 @bar(i8* getelementptr ([3 x i8]* @"\01LC", i32 0, i32 0)) nounwind ; [#uses=1] + store i32 %1, i32* %0, align 4 + %2 = load i32* %0, align 4 ; [#uses=1] + store i32 %2, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval1 = load i32* %retval ; [#uses=1] + call void @llvm.dbg.stoppoint(i32 2, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + call void @llvm.dbg.region.end({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram11 to { }*)) + ret i32 %retval1 +} From gohman at apple.com Tue Feb 10 09:04:39 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 10 Feb 2009 15:04:39 -0000 Subject: [llvm-commits] [test-suite] r64218 - in /test-suite/trunk: TEST.beta-compare.Makefile TEST.beta-compare.report TEST.jit.Makefile TEST.libcalls.Makefile Message-ID: <200902101504.n1AF4deJ009533@zion.cs.uiuc.edu> Author: djg Date: Tue Feb 10 09:04:37 2009 New Revision: 64218 URL: http://llvm.org/viewvc/llvm-project?rev=64218&view=rev Log: Fix 80-col violations in comments. Modified: test-suite/trunk/TEST.beta-compare.Makefile test-suite/trunk/TEST.beta-compare.report test-suite/trunk/TEST.jit.Makefile test-suite/trunk/TEST.libcalls.Makefile Modified: test-suite/trunk/TEST.beta-compare.Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/TEST.beta-compare.Makefile?rev=64218&r1=64217&r2=64218&view=diff ============================================================================== --- test-suite/trunk/TEST.beta-compare.Makefile (original) +++ test-suite/trunk/TEST.beta-compare.Makefile Tue Feb 10 09:04:37 2009 @@ -1,4 +1,4 @@ -##===- TEST.beta-compare.Makefile -----------------------------------*- Makefile -*-===## +##===- TEST.beta-compare.Makefile --------------------------*- Makefile -*-===## # # This test runs llc and llc-beta and generates numbers to compare their static # values produced by -stats. Modified: test-suite/trunk/TEST.beta-compare.report URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/TEST.beta-compare.report?rev=64218&r1=64217&r2=64218&view=diff ============================================================================== --- test-suite/trunk/TEST.beta-compare.report (original) +++ test-suite/trunk/TEST.beta-compare.report Tue Feb 10 09:04:37 2009 @@ -1,4 +1,4 @@ -##=== TEST.beta-compare.report - Compare llc vs llcbeta -*- perl -*-===## +##=== TEST.beta-compare.report - Compare llc vs llcbeta --------*- perl -*-===## # # This file defines a report to be generated for the beta-compare test. # Modified: test-suite/trunk/TEST.jit.Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/TEST.jit.Makefile?rev=64218&r1=64217&r2=64218&view=diff ============================================================================== --- test-suite/trunk/TEST.jit.Makefile (original) +++ test-suite/trunk/TEST.jit.Makefile Tue Feb 10 09:04:37 2009 @@ -1,4 +1,4 @@ -##===- TEST.jit.Makefile ----------------------------------*- Makefile -*-===## +##===- TEST.jit.Makefile -----------------------------------*- Makefile -*-===## # # This test tries running the Just-In-Time compiler on all of the programs to # see which ones work and which ones don't. It provides a report to tabulate Modified: test-suite/trunk/TEST.libcalls.Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/TEST.libcalls.Makefile?rev=64218&r1=64217&r2=64218&view=diff ============================================================================== --- test-suite/trunk/TEST.libcalls.Makefile (original) +++ test-suite/trunk/TEST.libcalls.Makefile Tue Feb 10 09:04:37 2009 @@ -1,4 +1,4 @@ -##===- TEST.libcalls.Makefile -------------------------------*- Makefile -*-===## +##===- TEST.libcalls.Makefile ------------------------------*- Makefile -*-===## # # This recursively traverses the programs, and runs the -simplify-libcalls pass # on each *.linked.rbc bytecode file with -stats set so that it is possible to From gohman at apple.com Tue Feb 10 09:07:08 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 10 Feb 2009 15:07:08 -0000 Subject: [llvm-commits] [test-suite] r64219 - in /test-suite/trunk/External/SPEC: CFP2006/482.sphinx3/Makefile CINT2000/176.gcc/Makefile CINT2000/252.eon/Makefile CINT2000/254.gap/Makefile CINT2000/255.vortex/Makefile Makefile.spec2000 Makefile.spec2006 Message-ID: <200902101507.n1AF78Tn009627@zion.cs.uiuc.edu> Author: djg Date: Tue Feb 10 09:07:08 2009 New Revision: 64219 URL: http://llvm.org/viewvc/llvm-project?rev=64219&view=rev Log: Add -DSPEC_CPU2000_LP64 and -DSPEC_CPU_LP64 to CPPFLAGS in the top-level SPEC Makefiles, instead of in individual benchmark Makefiles. Also, set them when ARCH is x86_64. Modified: test-suite/trunk/External/SPEC/CFP2006/482.sphinx3/Makefile test-suite/trunk/External/SPEC/CINT2000/176.gcc/Makefile test-suite/trunk/External/SPEC/CINT2000/252.eon/Makefile test-suite/trunk/External/SPEC/CINT2000/254.gap/Makefile test-suite/trunk/External/SPEC/CINT2000/255.vortex/Makefile test-suite/trunk/External/SPEC/Makefile.spec2000 test-suite/trunk/External/SPEC/Makefile.spec2006 Modified: test-suite/trunk/External/SPEC/CFP2006/482.sphinx3/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CFP2006/482.sphinx3/Makefile?rev=64219&r1=64218&r2=64219&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CFP2006/482.sphinx3/Makefile (original) +++ test-suite/trunk/External/SPEC/CFP2006/482.sphinx3/Makefile Tue Feb 10 09:07:08 2009 @@ -10,7 +10,7 @@ include ../../Makefile.spec2006 -CPPFLAGS += -I$(SPEC_BENCH_DIR)/src/libutil -DHAVE_CONFIG_H -DSPEC_CPU +CPPFLAGS += -I$(SPEC_BENCH_DIR)/src/libutil -DHAVE_CONFIG_H ifeq ($(RUN_TYPE),test) RUN_OPTIONS = `cp an406-fcaw-b.be.raw an406-fcaw-b.raw` \ Modified: test-suite/trunk/External/SPEC/CINT2000/176.gcc/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2000/176.gcc/Makefile?rev=64219&r1=64218&r2=64219&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT2000/176.gcc/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT2000/176.gcc/Makefile Tue Feb 10 09:07:08 2009 @@ -23,13 +23,3 @@ ## SPEC portability note for GCC says to use these flags and cross fingers: CPPFLAGS += -DSPEC_CPU2000_LP64 endif -ifeq ($(ARCH),Alpha) - ## SPEC portability note for GCC says to use these flags and cross fingers: - CPPFLAGS += -DSPEC_CPU2000_LP64 -endif -ifeq ($(ARCH),IA64) - ## SPEC portability note for GCC says to use these flags and cross fingers: - CPPFLAGS += -DSPEC_CPU2000_LP64 -endif - - Modified: test-suite/trunk/External/SPEC/CINT2000/252.eon/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2000/252.eon/Makefile?rev=64219&r1=64218&r2=64219&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT2000/252.eon/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT2000/252.eon/Makefile Tue Feb 10 09:07:08 2009 @@ -13,10 +13,6 @@ CPPFLAGS += -DFMAX_IS_DOUBLE endif -ifeq ($(ARCH),Alpha) - CPPFLAGS += -DSPEC_CPU2000_LP64 -endif - Source = $(addprefix $(SPEC_BENCH_DIR)/src/, \ ggCoverageSolidTexture.cc ggPathDielectricMaterial.cc ggBox2.cc \ ggBox3.cc ggRasterSurfaceTexture.cc ggJitterSample1.cc \ Modified: test-suite/trunk/External/SPEC/CINT2000/254.gap/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2000/254.gap/Makefile?rev=64219&r1=64218&r2=64219&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT2000/254.gap/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT2000/254.gap/Makefile Tue Feb 10 09:07:08 2009 @@ -10,12 +10,6 @@ ifeq ($(ARCH),Sparc) CPPFLAGS+= -DSPEC_CPU2000_LP64 endif -ifeq ($(ARCH),Alpha) -CPPFLAGS+= -DSPEC_CPU2000_LP64 -endif -ifeq ($(ARCH),IA64) -CPPFLAGS+= -DSPEC_CPU2000_LP64 -endif ifeq ($(OS),Darwin) CPPFLAGS += -DSYS_IS_BSD Modified: test-suite/trunk/External/SPEC/CINT2000/255.vortex/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2000/255.vortex/Makefile?rev=64219&r1=64218&r2=64219&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT2000/255.vortex/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT2000/255.vortex/Makefile Tue Feb 10 09:07:08 2009 @@ -14,15 +14,3 @@ ## SPEC portability note for vortex says to use this flag on 64-bit machines CPPFLAGS += -DSPEC_CPU2000_LP64 endif - -ifeq ($(ARCH),Alpha) - ## SPEC portability note for vortex says to use this flag on 64-bit machines - CPPFLAGS += -DSPEC_CPU2000_LP64 -endif - -ifeq ($(ARCH),IA64) - ## SPEC portability note for vortex says to use this flag on 64-bit machines - CPPFLAGS += -DSPEC_CPU2000_LP64 -endif - - Modified: test-suite/trunk/External/SPEC/Makefile.spec2000 URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/Makefile.spec2000?rev=64219&r1=64218&r2=64219&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/Makefile.spec2000 (original) +++ test-suite/trunk/External/SPEC/Makefile.spec2000 Tue Feb 10 09:07:08 2009 @@ -9,6 +9,16 @@ SPEC_ROOT := $(SPEC2000_ROOT) CPPFLAGS += -DSPEC_CPU2000 +ifeq ($(ARCH),x86_64) + CPPFLAGS += -DSPEC_CPU2000_LP64 +endif +ifeq ($(ARCH),Alpha) + CPPFLAGS += -DSPEC_CPU2000_LP64 +endif +ifeq ($(ARCH),IA64) + CPPFLAGS += -DSPEC_CPU2000_LP64 +endif + # RUN_TYPE - Either ref, test, or train. May be specified on the command line. # individual tests may override this to provide better input sizes ifndef RUN_TYPE Modified: test-suite/trunk/External/SPEC/Makefile.spec2006 URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/Makefile.spec2006?rev=64219&r1=64218&r2=64219&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/Makefile.spec2006 (original) +++ test-suite/trunk/External/SPEC/Makefile.spec2006 Tue Feb 10 09:07:08 2009 @@ -9,6 +9,16 @@ SPEC_ROOT := $(SPEC2006_ROOT) CPPFLAGS += -DSPEC_CPU2006 +ifeq ($(ARCH),x86_64) + CPPFLAGS += -DSPEC_CPU_LP64 +endif +ifeq ($(ARCH),Alpha) + CPPFLAGS += -DSPEC_CPU_LP64 +endif +ifeq ($(ARCH),IA64) + CPPFLAGS += -DSPEC_CPU_LP64 +endif + # RUN_TYPE - Either ref, test, or train. May be specified on the command line. # Individual tests may override this to provide better input sizes. ifndef RUN_TYPE From baldrick at free.fr Tue Feb 10 10:24:56 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 10 Feb 2009 16:24:56 -0000 Subject: [llvm-commits] [llvm] r64220 - /llvm/trunk/lib/AsmParser/LLParser.cpp Message-ID: <200902101624.n1AGOubi012115@zion.cs.uiuc.edu> Author: baldrick Date: Tue Feb 10 10:24:55 2009 New Revision: 64220 URL: http://llvm.org/viewvc/llvm-project?rev=64220&view=rev Log: Pacify gcc-4.3 (thinks IsConstant may be used uninitialized). Modified: llvm/trunk/lib/AsmParser/LLParser.cpp Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=64220&r1=64219&r2=64220&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Tue Feb 10 10:24:55 2009 @@ -331,8 +331,10 @@ IsConstant = true; else if (Lex.getKind() == lltok::kw_global) IsConstant = false; - else + else { + IsConstant = false; return TokError("expected 'global' or 'constant'"); + } Lex.Lex(); return false; } From gohman at apple.com Tue Feb 10 11:26:53 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 10 Feb 2009 17:26:53 -0000 Subject: [llvm-commits] [llvm] r64222 - /llvm/trunk/docs/FAQ.html Message-ID: <200902101726.n1AHQrB8014059@zion.cs.uiuc.edu> Author: djg Date: Tue Feb 10 11:26:53 2009 New Revision: 64222 URL: http://llvm.org/viewvc/llvm-project?rev=64222&view=rev Log: Answer a common FAQ: "Can I compile C or C++ code to platform-independent LLVM bitcode?" Modified: llvm/trunk/docs/FAQ.html Modified: llvm/trunk/docs/FAQ.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/FAQ.html?rev=64222&r1=64221&r2=64222&view=diff ============================================================================== --- llvm/trunk/docs/FAQ.html (original) +++ llvm/trunk/docs/FAQ.html Tue Feb 10 11:26:53 2009 @@ -87,6 +87,8 @@
  • Can I use LLVM to convert C++ code to C code?
    • +
  • Can I compile C or C++ code to platform-independent LLVM bitcode?
    • + @@ -629,6 +631,31 @@ +
    +

    +Can I compile C or C++ code to platform-independent LLVM bitcode? +

    +
    + +
    + +

    No. C and C++ are inherently platform-dependent languages. The most +obvious example of this is the preprocessor. A very common way that C code +is made portable is by using the preprocessor to include platform-specific +code. In practice, information about other platforms is lost after +preprocessing, so the result is inherently dependent on the platform that +the preprocessing was targetting.

    + +

    Another example is sizeof. It's common for sizeof(long) +to vary between platforms. In most C front-ends, sizeof is expanded +to a constant immediately, thus hardwaring a platform-specific detail.

    + +

    Also, since many platforms define their ABIs in terms of C, and since +LLVM is lower-level than C, front-ends currently must emit platform-specific +IR in order to have the result conform to the platform ABI.

    + +
    +
    Questions about code generated by the GCC front-end From gohman at apple.com Tue Feb 10 11:56:28 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 10 Feb 2009 17:56:28 -0000 Subject: [llvm-commits] [llvm] r64224 - /llvm/trunk/lib/System/Unix/Signals.inc Message-ID: <200902101756.n1AHuTi8015063@zion.cs.uiuc.edu> Author: djg Date: Tue Feb 10 11:56:28 2009 New Revision: 64224 URL: http://llvm.org/viewvc/llvm-project?rev=64224&view=rev Log: Use const, to support platforms where strrchr returns a const char *. This fixes PR3535. Modified: llvm/trunk/lib/System/Unix/Signals.inc Modified: llvm/trunk/lib/System/Unix/Signals.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Signals.inc?rev=64224&r1=64223&r2=64224&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Signals.inc (original) +++ llvm/trunk/lib/System/Unix/Signals.inc Tue Feb 10 11:56:28 2009 @@ -78,7 +78,7 @@ for (int i = 0; i < depth; ++i) { Dl_info dlinfo; dladdr(StackTrace[i], &dlinfo); - char* name = strrchr(dlinfo.dli_fname, '/'); + const char* name = strrchr(dlinfo.dli_fname, '/'); int nwidth; if (name == NULL) nwidth = strlen(dlinfo.dli_fname); @@ -93,7 +93,7 @@ fprintf(stderr, "%-3d", i); - char* name = strrchr(dlinfo.dli_fname, '/'); + const char* name = strrchr(dlinfo.dli_fname, '/'); if (name == NULL) fprintf(stderr, " %-*s", width, dlinfo.dli_fname); else fprintf(stderr, " %-*s", width, name+1); From evan.cheng at apple.com Tue Feb 10 13:00:49 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 10 Feb 2009 11:00:49 -0800 Subject: [llvm-commits] [llvm] r64186 - in /llvm/trunk: lib/Target/X86/X86FloatingPoint.cpp lib/Target/X86/X86InstrFPStack.td lib/Target/X86/X86InstrInfo.cpp test/CodeGen/X86/fp-stack-set-st1.ll In-Reply-To: References: <200902092332.n19NW72X016523@zion.cs.uiuc.edu> Message-ID: <639FDFBC-521A-4735-9F6F-1FA91C3B1442@apple.com> No. We still have troubles with inline asm with x87 math. Evan On Feb 9, 2009, at 10:06 PM, Anton Korobeynikov wrote: > Hello, Evan > >> Log: >> Implement FpSET_ST1_*. > Did this fix PR2257? > > -- > With best regards, Anton Korobeynikov > Faculty of Mathematics and Mechanics, Saint Petersburg State > University > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From sanjiv.gupta at microchip.com Tue Feb 10 13:00:44 2009 From: sanjiv.gupta at microchip.com (sanjiv gupta) Date: Wed, 11 Feb 2009 00:30:44 +0530 Subject: [llvm-commits] r64000 breaks PIC16 Message-ID: <1234292444.7110.7.camel@idc-lt-i00171.microchip.com> Try with a simple test int foo (int i) { if (i < 0) return -1; else return 1; } The correct assembly is: (as per r63998) code.foo.# CODE foo: movlw 128 banksel foo.arg.i xorwf foo.arg.i + 1, W movwf foo.tmp + 2 movlw 127 movwf foo.tmp + 1 movf foo.tmp + 2, W subwf foo.tmp + 1, W blt .BB1_2 ; if.else (correct - br after test) .BB1_1 ; if.then movlw 255 movwf foo.args + 0 movwf foo.args + 1 goto .BB1_3 ; return .BB1_2 ; if.else movlw 1 movwf foo.args + 0 ... The incorrect assembly is : (as per r64000) code.foo.# CODE foo: movlw 127 movwf foo.tmp + 1 blt .BB1_2 ; if.else (??? - br w/o test) .BB1_1 ; if.then movlw 128 banksel foo.arg.i xorwf foo.arg.i + 1, W subwf foo.tmp + 1, W movlw 255 movwf foo.args + 0 movwf foo.args + 1 goto .BB1_3 ; return .BB1_2 ; if.else movlw 1 movwf foo.args + 0 movlw 0 movwf foo.args + 1 Thanks, -Sanjiv From evan.cheng at apple.com Tue Feb 10 13:03:27 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 10 Feb 2009 11:03:27 -0800 Subject: [llvm-commits] [llvm] r64207 - in /llvm/trunk: include/llvm/Transforms/Utils/Local.h lib/Transforms/Scalar/ScalarReplAggregates.cpp lib/Transforms/Utils/Local.cpp test/Transforms/ScalarRepl/debuginfo.ll In-Reply-To: <200902100700.n1A70xfb016017@zion.cs.uiuc.edu> References: <200902100700.n1A70xfb016017@zion.cs.uiuc.edu> Message-ID: <148B0CB9-508A-47CD-A1A9-B043E7E344D7@apple.com> On Feb 9, 2009, at 11:00 PM, Devang Patel wrote: > > +/// CleanupGEP - GEP is used by an Alloca, which can be prompted > after the GEP > +/// is canonicalized here. > +void SROA::CleanupGEP(GetElementPtrInst *GEPI) { > + gep_type_iterator I = gep_type_begin(GEPI); > + ++I; > + > + if (const ArrayType *AT = dyn_cast(*I)) { > + uint64_t NumElements = AT->getNumElements(); > + > + if (!isa(I.getOperand())) { Just a nitpick. You should use early exit to eliminate nesting here. Evan > > + if (NumElements == 1) { > + GEPI->setOperand(2, Constant::getNullValue(Type::Int32Ty)); > + } else { > + assert(NumElements == 2 && "Unhandled case!"); > + // All users of the GEP must be loads. At each use of the > GEP, insert > + // two loads of the appropriate indexed GEP and select > between them. > + Value *IsOne = new ICmpInst(ICmpInst::ICMP_NE, > I.getOperand(), > + > Constant::getNullValue(I.getOperand()->getType()), > + "isone", GEPI); > + // Insert the new GEP instructions, which are properly > indexed. > + SmallVector Indices(GEPI->op_begin()+1, GEPI- > >op_end()); > + Indices[1] = Constant::getNullValue(Type::Int32Ty); > + Value *ZeroIdx = GetElementPtrInst::Create(GEPI- > >getOperand(0), > + Indices.begin(), > + Indices.end(), > + GEPI->getName() > +".0", GEPI); > + Indices[1] = ConstantInt::get(Type::Int32Ty, 1); > + Value *OneIdx = GetElementPtrInst::Create(GEPI- > >getOperand(0), > + Indices.begin(), > + Indices.end(), > + GEPI->getName()+". > 1", GEPI); > + // Replace all loads of the variable index GEP with loads > from both > + // indexes and a select. > + while (!GEPI->use_empty()) { > + LoadInst *LI = cast(GEPI->use_back()); > + Value *Zero = new LoadInst(ZeroIdx, LI->getName()+".0", > LI); > + Value *One = new LoadInst(OneIdx , LI->getName()+".1", > LI); > + Value *R = SelectInst::Create(IsOne, One, Zero, LI- > >getName(), LI); > + LI->replaceAllUsesWith(R); > + LI->eraseFromParent(); > + } > + GEPI->eraseFromParent(); > + } > + } > + } > } > > -/// CanonicalizeAllocaUsers - If SROA reported that it can promote > the specified > +/// CleanupAllocaUsers - If SROA reported that it can promote the > specified > /// allocation, but only if cleaned up, perform the cleanups required. > -void SROA::CanonicalizeAllocaUsers(AllocationInst *AI) { > +void SROA::CleanupAllocaUsers(AllocationInst *AI) { > // At this point, we know that the end result will be SROA'd and > promoted, so > // we can insert ugly code if required so long as sroa+mem2reg > will clean it > // up. > for (Value::use_iterator UI = AI->use_begin(), E = AI->use_end(); > UI != E; ) { > - GetElementPtrInst *GEPI = dyn_cast(*UI++); > - if (!GEPI) continue; > - gep_type_iterator I = gep_type_begin(GEPI); > - ++I; > - > - if (const ArrayType *AT = dyn_cast(*I)) { > - uint64_t NumElements = AT->getNumElements(); > - > - if (!isa(I.getOperand())) { > - if (NumElements == 1) { > - GEPI->setOperand(2, Constant::getNullValue(Type::Int32Ty)); > - } else { > - assert(NumElements == 2 && "Unhandled case!"); > - // All users of the GEP must be loads. At each use of > the GEP, insert > - // two loads of the appropriate indexed GEP and select > between them. > - Value *IsOne = new ICmpInst(ICmpInst::ICMP_NE, > I.getOperand(), > - Constant::getNullValue(I.getOperand()- > >getType()), > - "isone", GEPI); > - // Insert the new GEP instructions, which are properly > indexed. > - SmallVector Indices(GEPI->op_begin()+1, GEPI- > >op_end()); > - Indices[1] = Constant::getNullValue(Type::Int32Ty); > - Value *ZeroIdx = GetElementPtrInst::Create(GEPI- > >getOperand(0), > - Indices.begin(), > - Indices.end(), > - GEPI->getName() > +".0", GEPI); > - Indices[1] = ConstantInt::get(Type::Int32Ty, 1); > - Value *OneIdx = GetElementPtrInst::Create(GEPI- > >getOperand(0), > - Indices.begin(), > - Indices.end(), > - GEPI->getName() > +".1", GEPI); > - // Replace all loads of the variable index GEP with loads > from both > - // indexes and a select. > - while (!GEPI->use_empty()) { > - LoadInst *LI = cast(GEPI->use_back()); > - Value *Zero = new LoadInst(ZeroIdx, LI->getName()+".0", > LI); > - Value *One = new LoadInst(OneIdx , LI->getName()+".1", > LI); > - Value *R = SelectInst::Create(IsOne, One, Zero, LI- > >getName(), LI); > - LI->replaceAllUsesWith(R); > - LI->eraseFromParent(); > - } > - GEPI->eraseFromParent(); > + User *U = *UI++; > + if (GetElementPtrInst *GEPI = dyn_cast(U)) > + CleanupGEP(GEPI); > + else if (Instruction *I = dyn_cast(U)) { > + SmallVector DbgInUses; > + if (OnlyUsedByDbgInfoIntrinsics(I, &DbgInUses)) { > + // Safe to remove debug info uses. > + while (!DbgInUses.empty()) { > + DbgInfoIntrinsic *DI = DbgInUses.back(); > DbgInUses.pop_back(); > + DI->eraseFromParent(); > } > + I->eraseFromParent(); > } > } > } > > Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=64207&r1=64206&r2=64207&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original) > +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Tue Feb 10 01:00:59 2009 > @@ -248,3 +248,25 @@ > // Nuke BB. > PredBB->eraseFromParent(); > } > + > +/// OnlyUsedByDbgIntrinsics - Return true if the instruction I is > only used > +/// by DbgIntrinsics. If DbgInUses is specified then the vector is > filled > +/// with the DbgInfoIntrinsic that use the instruction I. > +bool llvm::OnlyUsedByDbgInfoIntrinsics(Instruction *I, > + SmallVectorImpl > *DbgInUses) { > + if (DbgInUses) > + DbgInUses->clear(); > + > + for (Value::use_iterator UI = I->use_begin(), UE = I->use_end(); > UI != UE; > + ++UI) { > + if (DbgInfoIntrinsic *DI = dyn_cast(*UI)) { > + if (DbgInUses) > + DbgInUses->push_back(DI); > + } else { > + if (DbgInUses) > + DbgInUses->clear(); > + return false; > + } > + } > + return true; > +} > > Added: llvm/trunk/test/Transforms/ScalarRepl/debuginfo.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/debuginfo.ll?rev=64207&view=auto > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/test/Transforms/ScalarRepl/debuginfo.ll (added) > +++ llvm/trunk/test/Transforms/ScalarRepl/debuginfo.ll Tue Feb 10 > 01:00:59 2009 > @@ -0,0 +1,105 @@ > +; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | not grep alloca > + %llvm.dbg.anchor.type = type { i32, i32 } > + %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, > i64, i64, i32, i32 } > + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, > i8*, i1, i1, i8* } > + %llvm.dbg.composite.type = type { i32, { }*, i8*, { }*, i32, i64, > i64, i64, i32, { }*, { }* } > + %llvm.dbg.derivedtype.type = type { i32, { }*, i8*, { }*, i32, > i64, i64, i64, i32, { }* } > + %llvm.dbg.subprogram.type = type { i32, { }*, { }*, i8*, i8*, i8*, > { }*, i32, { }*, i1, i1 } > + %llvm.dbg.variable.type = type { i32, { }*, i8*, { }*, i32, { }* } > + %struct.Sphere = type { %struct.Vec } > + %struct.Vec = type { i32, i32, i32 } > + at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type > { i32 458752, i32 17 }, section "llvm.metadata" ; < > %llvm.dbg.anchor.type*> [#uses=1] > + at .str = internal constant [6 x i8] c"r.cpp\00", section > "llvm.metadata" ; <[6 x i8]*> [#uses=1] > + at .str1 = internal constant [5 x i8] c"/tmp\00", section > "llvm.metadata" ; <[5 x i8]*> [#uses=1] > + at .str2 = internal constant [55 x i8] c"4.2.1 (Based on Apple Inc. > build 5636) (LLVM build 00)\00", section "llvm.metadata" ; <[55 x > i8]*> [#uses=1] > + at llvm.dbg.compile_unit = internal constant > %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast > (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 4, i8* > getelementptr ([6 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([5 > x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([55 x i8]* @.str2, > i32 0, i32 0), i1 true, i1 false, i8* null }, section > "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] > + at .str3 = internal constant [4 x i8] c"Vec\00", section > "llvm.metadata" ; <[4 x i8]*> [#uses=1] > + at .str4 = internal constant [4 x i8] c"int\00", section > "llvm.metadata" ; <[4 x i8]*> [#uses=1] > + at llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type > { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* > @.str4, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 > 0, i32 5 }, section "llvm.metadata" ; <%llvm.dbg.basictype.type*> > [#uses=1] > + at .str5 = internal constant [2 x i8] c"x\00", section > "llvm.metadata" ; <[2 x i8]*> [#uses=1] > + at llvm.dbg.derivedtype = internal constant > %llvm.dbg.derivedtype.type { i32 458765, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* > getelementptr ([2 x i8]* @.str5, i32 0, i32 0), { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 > 4, i64 32, i64 32, i64 0, i32 0, { }* bitcast > (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section > "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] > + at .str6 = internal constant [2 x i8] c"y\00", section > "llvm.metadata" ; <[2 x i8]*> [#uses=1] > + at llvm.dbg.derivedtype7 = internal constant > %llvm.dbg.derivedtype.type { i32 458765, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* > getelementptr ([2 x i8]* @.str6, i32 0, i32 0), { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 > 4, i64 32, i64 32, i64 32, i32 0, { }* bitcast > (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section > "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] > + at .str8 = internal constant [2 x i8] c"z\00", section > "llvm.metadata" ; <[2 x i8]*> [#uses=1] > + at llvm.dbg.derivedtype9 = internal constant > %llvm.dbg.derivedtype.type { i32 458765, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* > getelementptr ([2 x i8]* @.str8, i32 0, i32 0), { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 > 4, i64 32, i64 32, i64 64, i32 0, { }* bitcast > (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section > "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] > + at llvm.dbg.derivedtype10 = internal constant > %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* > null, { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 > 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite18 to > { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> > [#uses=1] > + at llvm.dbg.derivedtype11 = internal constant > %llvm.dbg.derivedtype.type { i32 458790, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* > null, { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i32 0, i64 96, i64 32, i64 0, i32 > 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite18 to > { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> > [#uses=1] > + at llvm.dbg.derivedtype12 = internal constant > %llvm.dbg.derivedtype.type { i32 458768, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* > null, { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 > 0, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype11 > to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> > [#uses=1] > + at llvm.dbg.array = internal constant [3 x { }*] [ { }* null, { }* > bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype10 to > { }*), { }* bitcast (%llvm.dbg.derivedtype.type* > @llvm.dbg.derivedtype12 to { }*) ], section "llvm.metadata" ; <[3 x > { }*]*> [#uses=1] > + at llvm.dbg.composite13 = internal constant %llvm.dbg.composite.type > { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 > 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* > @llvm.dbg.array to { }*) }, section "llvm.metadata" ; < > %llvm.dbg.composite.type*> [#uses=1] > + at llvm.dbg.subprograms = linkonce constant %llvm.dbg.anchor.type > { i32 458752, i32 46 }, section "llvm.metadata" ; < > %llvm.dbg.anchor.type*> [#uses=1] > + at llvm.dbg.subprogram = internal constant %llvm.dbg.subprogram.type > { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* > @llvm.dbg.subprograms to { }*), { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* > getelementptr ([4 x i8]* @.str3, i32 0, i32 0), i8* getelementptr > ([4 x i8]* @.str3, i32 0, i32 0), i8* null, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 > 2, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite13 to > { }*), i1 false, i1 false }, section "llvm.metadata" ; < > %llvm.dbg.subprogram.type*> [#uses=1] > + at llvm.dbg.array14 = internal constant [5 x { }*] [ { }* null, { }* > bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype10 to > { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype > to { }*), { }* bitcast (%llvm.dbg.basictype.type* > @llvm.dbg.basictype to { }*), { }* bitcast > (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) ], section > "llvm.metadata" ; <[5 x { }*]*> [#uses=1] > + at llvm.dbg.composite15 = internal constant %llvm.dbg.composite.type > { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 > 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([5 x { }*]* > @llvm.dbg.array14 to { }*) }, section "llvm.metadata" ; < > %llvm.dbg.composite.type*> [#uses=1] > + at llvm.dbg.subprogram16 = internal constant > %llvm.dbg.subprogram.type { i32 458798, { }* bitcast > (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* > getelementptr ([4 x i8]* @.str3, i32 0, i32 0), i8* getelementptr > ([4 x i8]* @.str3, i32 0, i32 0), i8* null, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 > 5, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite15 to > { }*), i1 false, i1 false }, section "llvm.metadata" ; < > %llvm.dbg.subprogram.type*> [#uses=1] > + at llvm.dbg.array17 = internal constant [5 x { }*] [ { }* bitcast > (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*), { }* > bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype7 to > { }*), { }* bitcast (%llvm.dbg.derivedtype.type* > @llvm.dbg.derivedtype9 to { }*), { }* bitcast > (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), { }* > bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram16 to > { }*) ], section "llvm.metadata" ; <[5 x { }*]*> [#uses=1] > + at llvm.dbg.composite18 = internal constant %llvm.dbg.composite.type > { i32 458771, { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* > @.str3, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i32 2, i64 96, i64 32, i64 0, i32 > 0, { }* null, { }* bitcast ([5 x { }*]* @llvm.dbg.array17 to > { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> > [#uses=1] > + at llvm.dbg.derivedtype19 = internal constant > %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* > null, { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 > 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite18 to > { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> > [#uses=1] > + at llvm.dbg.array20 = internal constant [5 x { }*] [ { }* null, { }* > bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype19 to > { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype > to { }*), { }* bitcast (%llvm.dbg.basictype.type* > @llvm.dbg.basictype to { }*), { }* bitcast > (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) ], section > "llvm.metadata" ; <[5 x { }*]*> [#uses=1] > + at llvm.dbg.composite = internal constant %llvm.dbg.composite.type > { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 > 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([5 x { }*]* > @llvm.dbg.array20 to { }*) }, section "llvm.metadata" ; < > %llvm.dbg.composite.type*> [#uses=1] > + at .str21 = internal constant [13 x i8] c"__comp_ctor \00", section > "llvm.metadata" ; <[13 x i8]*> [#uses=1] > + at .str22 = internal constant [14 x i8] c"_ZN3VecC1Eiii\00", section > "llvm.metadata" ; <[14 x i8]*> [#uses=1] > + at llvm.dbg.array32 = internal constant [3 x { }*] [ { }* bitcast > (%llvm.dbg.composite.type* @llvm.dbg.composite18 to { }*), { }* > bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype12 to > { }*), { }* bitcast (%llvm.dbg.derivedtype.type* > @llvm.dbg.derivedtype12 to { }*) ], section "llvm.metadata" ; <[3 x > { }*]*> [#uses=1] > + at llvm.dbg.composite33 = internal constant %llvm.dbg.composite.type > { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 > 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* > @llvm.dbg.array32 to { }*) }, section "llvm.metadata" ; < > %llvm.dbg.composite.type*> [#uses=1] > + at .str34 = internal constant [10 x i8] c"operator-\00", section > "llvm.metadata" ; <[10 x i8]*> [#uses=1] > + at .str35 = internal constant [14 x i8] c"_ZmiRK3VecS1_\00", section > "llvm.metadata" ; <[14 x i8]*> [#uses=1] > + at .str41 = internal constant [7 x i8] c"Sphere\00", section > "llvm.metadata" ; <[7 x i8]*> [#uses=1] > + at .str43 = internal constant [7 x i8] c"center\00", section > "llvm.metadata" ; <[7 x i8]*> [#uses=1] > + at llvm.dbg.derivedtype44 = internal constant > %llvm.dbg.derivedtype.type { i32 458765, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* > getelementptr ([7 x i8]* @.str43, i32 0, i32 0), { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 > 14, i64 96, i64 32, i64 0, i32 1, { }* bitcast > (%llvm.dbg.composite.type* @llvm.dbg.composite18 to { }*) }, section > "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] > + at llvm.dbg.derivedtype45 = internal constant > %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* > null, { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 > 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite52 to > { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> > [#uses=1] > + at llvm.dbg.array46 = internal constant [3 x { }*] [ { }* bitcast > (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* > bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype45 to > { }*), { }* bitcast (%llvm.dbg.derivedtype.type* > @llvm.dbg.derivedtype12 to { }*) ], section "llvm.metadata" ; <[3 x > { }*]*> [#uses=1] > + at llvm.dbg.composite47 = internal constant %llvm.dbg.composite.type > { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 > 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* > @llvm.dbg.array46 to { }*) }, section "llvm.metadata" ; < > %llvm.dbg.composite.type*> [#uses=1] > + at .str48 = internal constant [11 x i8] c"ray_sphere\00", section > "llvm.metadata" ; <[11 x i8]*> [#uses=1] > + at .str49 = internal constant [30 x i8] > c"_ZN6Sphere10ray_sphereERK3Vec\00", section "llvm.metadata" ; <[30 > x i8]*> [#uses=1] > + at llvm.dbg.subprogram50 = internal constant > %llvm.dbg.subprogram.type { i32 458798, { }* bitcast > (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* > getelementptr ([11 x i8]* @.str48, i32 0, i32 0), i8* getelementptr > ([11 x i8]* @.str48, i32 0, i32 0), i8* getelementptr ([30 x i8]* > @.str49, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i32 16, { }* bitcast > (%llvm.dbg.composite.type* @llvm.dbg.composite47 to { }*), i1 false, > i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> > [#uses=1] > + at llvm.dbg.array51 = internal constant [2 x { }*] [ { }* bitcast > (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype44 to { }*), { }* > bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram50 to > { }*) ], section "llvm.metadata" ; <[2 x { }*]*> [#uses=1] > + at llvm.dbg.composite52 = internal constant %llvm.dbg.composite.type > { i32 458771, { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i8* getelementptr ([7 x i8]* > @.str41, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i32 12, i64 96, i64 32, i64 0, i32 > 0, { }* null, { }* bitcast ([2 x { }*]* @llvm.dbg.array51 to > { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> > [#uses=1] > + at llvm.dbg.derivedtype53 = internal constant > %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* > null, { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 > 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite52 to > { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> > [#uses=1] > + at llvm.dbg.array54 = internal constant [3 x { }*] [ { }* bitcast > (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* > bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype53 to > { }*), { }* bitcast (%llvm.dbg.derivedtype.type* > @llvm.dbg.derivedtype12 to { }*) ], section "llvm.metadata" ; <[3 x > { }*]*> [#uses=1] > + at llvm.dbg.composite55 = internal constant %llvm.dbg.composite.type > { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 > 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* > @llvm.dbg.array54 to { }*) }, section "llvm.metadata" ; < > %llvm.dbg.composite.type*> [#uses=1] > + at llvm.dbg.subprogram56 = internal constant > %llvm.dbg.subprogram.type { i32 458798, { }* bitcast > (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* > getelementptr ([11 x i8]* @.str48, i32 0, i32 0), i8* getelementptr > ([11 x i8]* @.str48, i32 0, i32 0), i8* getelementptr ([30 x i8]* > @.str49, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i32 16, { }* bitcast > (%llvm.dbg.composite.type* @llvm.dbg.composite55 to { }*), i1 false, > i1 true }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> > [#uses=1] > + at .str61 = internal constant [2 x i8] c"v\00", section > "llvm.metadata" ; <[2 x i8]*> [#uses=1] > + at llvm.dbg.variable62 = internal constant %llvm.dbg.variable.type > { i32 459008, { }* bitcast (%llvm.dbg.subprogram.type* > @llvm.dbg.subprogram56 to { }*), i8* getelementptr ([2 x i8]* > @.str61, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* > @llvm.dbg.compile_unit to { }*), i32 17, { }* bitcast > (%llvm.dbg.composite.type* @llvm.dbg.composite18 to { }*) }, section > "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=1] > + > +declare void @llvm.dbg.func.start({ }*) nounwind > + > +declare void @llvm.dbg.declare({ }*, { }*) nounwind > + > +declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind > + > +declare void @llvm.dbg.region.end({ }*) nounwind > + > +define i32 @_ZN6Sphere10ray_sphereERK3Vec(%struct.Sphere* %this, > %struct.Vec* %Orig) nounwind { > +entry: > + %v = alloca %struct.Vec, align 8 ; <%struct.Vec*> [#uses=4] > + call void @llvm.dbg.func.start({ }* bitcast > (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram56 to { }*)) > + %0 = bitcast %struct.Vec* %v to { }* ; <{ }*> [#uses=1] > + call void @llvm.dbg.declare({ }* %0, { }* bitcast > (%llvm.dbg.variable.type* @llvm.dbg.variable62 to { }*)) > + %1 = getelementptr %struct.Sphere* %this, i32 0, i32 0, i32 2 ; > [#uses=1] > + %2 = load i32* %1, align 4 ; [#uses=1] > + %3 = getelementptr %struct.Vec* %Orig, i32 0, i32 2 ; > [#uses=1] > + %4 = load i32* %3, align 4 ; [#uses=1] > + %5 = sub i32 %2, %4 ; [#uses=1] > + %6 = getelementptr %struct.Sphere* %this, i32 0, i32 0, i32 1 ; > [#uses=1] > + %7 = load i32* %6, align 4 ; [#uses=1] > + %8 = getelementptr %struct.Vec* %Orig, i32 0, i32 1 ; > [#uses=1] > + %9 = load i32* %8, align 4 ; [#uses=1] > + %10 = sub i32 %7, %9 ; [#uses=1] > + %11 = getelementptr %struct.Sphere* %this, i32 0, i32 0, i32 0 ; > [#uses=1] > + %12 = load i32* %11, align 4 ; [#uses=1] > + %13 = getelementptr %struct.Vec* %Orig, i32 0, i32 0 ; > [#uses=1] > + %14 = load i32* %13, align 4 ; [#uses=1] > + %15 = sub i32 %12, %14 ; [#uses=1] > + %16 = getelementptr %struct.Vec* %v, i32 0, i32 0 ; > [#uses=2] > + store i32 %15, i32* %16, align 8 > + %17 = getelementptr %struct.Vec* %v, i32 0, i32 1 ; > [#uses=1] > + store i32 %10, i32* %17, align 4 > + %18 = getelementptr %struct.Vec* %v, i32 0, i32 2 ; > [#uses=1] > + store i32 %5, i32* %18, align 8 > + call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) > nounwind > + call void @llvm.dbg.stoppoint(i32 9, i32 0, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) > nounwind > + %19 = load i32* %16, align 8 ; [#uses=1] > + call void @llvm.dbg.stoppoint(i32 18, i32 0, { }* bitcast > (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) > + call void @llvm.dbg.region.end({ }* bitcast > (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram56 to { }*)) > + ret i32 %19 > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Tue Feb 10 13:09:35 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 10 Feb 2009 11:09:35 -0800 Subject: [llvm-commits] [llvm] r64207 - in /llvm/trunk: include/llvm/Transforms/Utils/Local.h lib/Transforms/Scalar/ScalarReplAggregates.cpp lib/Transforms/Utils/Local.cpp test/Transforms/ScalarRepl/debuginfo.ll In-Reply-To: <148B0CB9-508A-47CD-A1A9-B043E7E344D7@apple.com> References: <200902100700.n1A70xfb016017@zion.cs.uiuc.edu> <148B0CB9-508A-47CD-A1A9-B043E7E344D7@apple.com> Message-ID: <59E57475-4C66-4C4A-840B-38D088AD3180@apple.com> On Feb 10, 2009, at 11:03 AM, Evan Cheng wrote: > > On Feb 9, 2009, at 11:00 PM, Devang Patel wrote: > >> >> +/// CleanupGEP - GEP is used by an Alloca, which can be prompted >> after the GEP >> +/// is canonicalized here. >> +void SROA::CleanupGEP(GetElementPtrInst *GEPI) { >> + gep_type_iterator I = gep_type_begin(GEPI); >> + ++I; >> + >> + if (const ArrayType *AT = dyn_cast(*I)) { >> + uint64_t NumElements = AT->getNumElements(); >> + >> + if (!isa(I.getOperand())) { > > Just a nitpick. You should use early exit to eliminate nesting here. yup. I just moved this code in a separate function without doing any cosmetic surgeries :) - Devang > > > Evan > >> >> + if (NumElements == 1) { >> + GEPI->setOperand(2, Constant::getNullValue(Type::Int32Ty)); >> + } else { >> + assert(NumElements == 2 && "Unhandled case!"); >> + // All users of the GEP must be loads. At each use of the >> GEP, insert >> + // two loads of the appropriate indexed GEP and select >> between them. >> + Value *IsOne = new ICmpInst(ICmpInst::ICMP_NE, >> I.getOperand(), >> + >> Constant::getNullValue(I.getOperand()->getType()), >> + "isone", GEPI); >> + // Insert the new GEP instructions, which are properly >> indexed. >> + SmallVector Indices(GEPI->op_begin()+1, GEPI- >>> op_end()); >> + Indices[1] = Constant::getNullValue(Type::Int32Ty); >> + Value *ZeroIdx = GetElementPtrInst::Create(GEPI- >>> getOperand(0), >> + Indices.begin(), >> + Indices.end(), >> + GEPI->getName() >> +".0", GEPI); >> + Indices[1] = ConstantInt::get(Type::Int32Ty, 1); >> + Value *OneIdx = GetElementPtrInst::Create(GEPI- >>> getOperand(0), >> + Indices.begin(), >> + Indices.end(), >> + GEPI->getName()+". >> 1", GEPI); >> + // Replace all loads of the variable index GEP with loads >> from both >> + // indexes and a select. >> + while (!GEPI->use_empty()) { >> + LoadInst *LI = cast(GEPI->use_back()); >> + Value *Zero = new LoadInst(ZeroIdx, LI->getName()+".0", >> LI); >> + Value *One = new LoadInst(OneIdx , LI->getName()+".1", >> LI); >> + Value *R = SelectInst::Create(IsOne, One, Zero, LI- >>> getName(), LI); >> + LI->replaceAllUsesWith(R); >> + LI->eraseFromParent(); >> + } >> + GEPI->eraseFromParent(); >> + } >> + } >> + } >> } >> >> -/// CanonicalizeAllocaUsers - If SROA reported that it can promote >> the specified >> +/// CleanupAllocaUsers - If SROA reported that it can promote the >> specified >> /// allocation, but only if cleaned up, perform the cleanups >> required. >> -void SROA::CanonicalizeAllocaUsers(AllocationInst *AI) { >> +void SROA::CleanupAllocaUsers(AllocationInst *AI) { >> // At this point, we know that the end result will be SROA'd and >> promoted, so >> // we can insert ugly code if required so long as sroa+mem2reg >> will clean it >> // up. >> for (Value::use_iterator UI = AI->use_begin(), E = AI->use_end(); >> UI != E; ) { >> - GetElementPtrInst *GEPI = dyn_cast(*UI++); >> - if (!GEPI) continue; >> - gep_type_iterator I = gep_type_begin(GEPI); >> - ++I; >> - >> - if (const ArrayType *AT = dyn_cast(*I)) { >> - uint64_t NumElements = AT->getNumElements(); >> - >> - if (!isa(I.getOperand())) { >> - if (NumElements == 1) { >> - GEPI->setOperand(2, >> Constant::getNullValue(Type::Int32Ty)); >> - } else { >> - assert(NumElements == 2 && "Unhandled case!"); >> - // All users of the GEP must be loads. At each use of >> the GEP, insert >> - // two loads of the appropriate indexed GEP and select >> between them. >> - Value *IsOne = new ICmpInst(ICmpInst::ICMP_NE, >> I.getOperand(), >> - Constant::getNullValue(I.getOperand()- >>> getType()), >> - "isone", GEPI); >> - // Insert the new GEP instructions, which are properly >> indexed. >> - SmallVector Indices(GEPI->op_begin()+1, GEPI- >>> op_end()); >> - Indices[1] = Constant::getNullValue(Type::Int32Ty); >> - Value *ZeroIdx = GetElementPtrInst::Create(GEPI- >>> getOperand(0), >> - >> Indices.begin(), >> - Indices.end(), >> - GEPI->getName() >> +".0", GEPI); >> - Indices[1] = ConstantInt::get(Type::Int32Ty, 1); >> - Value *OneIdx = GetElementPtrInst::Create(GEPI- >>> getOperand(0), >> - Indices.begin(), >> - Indices.end(), >> - GEPI->getName() >> +".1", GEPI); >> - // Replace all loads of the variable index GEP with loads >> from both >> - // indexes and a select. >> - while (!GEPI->use_empty()) { >> - LoadInst *LI = cast(GEPI->use_back()); >> - Value *Zero = new LoadInst(ZeroIdx, LI->getName()+".0", >> LI); >> - Value *One = new LoadInst(OneIdx , LI->getName()+".1", >> LI); >> - Value *R = SelectInst::Create(IsOne, One, Zero, LI- >>> getName(), LI); >> - LI->replaceAllUsesWith(R); >> - LI->eraseFromParent(); >> - } >> - GEPI->eraseFromParent(); >> + User *U = *UI++; >> + if (GetElementPtrInst *GEPI = dyn_cast(U)) >> + CleanupGEP(GEPI); >> + else if (Instruction *I = dyn_cast(U)) { >> + SmallVector DbgInUses; >> + if (OnlyUsedByDbgInfoIntrinsics(I, &DbgInUses)) { >> + // Safe to remove debug info uses. >> + while (!DbgInUses.empty()) { >> + DbgInfoIntrinsic *DI = DbgInUses.back(); >> DbgInUses.pop_back(); >> + DI->eraseFromParent(); >> } >> + I->eraseFromParent(); >> } >> } >> } >> >> Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=64207&r1=64206&r2=64207&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original) >> +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Tue Feb 10 01:00:59 >> 2009 >> @@ -248,3 +248,25 @@ >> // Nuke BB. >> PredBB->eraseFromParent(); >> } >> + >> +/// OnlyUsedByDbgIntrinsics - Return true if the instruction I is >> only used >> +/// by DbgIntrinsics. If DbgInUses is specified then the vector is >> filled >> +/// with the DbgInfoIntrinsic that use the instruction I. >> +bool llvm::OnlyUsedByDbgInfoIntrinsics(Instruction *I, >> + SmallVectorImpl >> *DbgInUses) { >> + if (DbgInUses) >> + DbgInUses->clear(); >> + >> + for (Value::use_iterator UI = I->use_begin(), UE = I->use_end(); >> UI != UE; >> + ++UI) { >> + if (DbgInfoIntrinsic *DI = dyn_cast(*UI)) { >> + if (DbgInUses) >> + DbgInUses->push_back(DI); >> + } else { >> + if (DbgInUses) >> + DbgInUses->clear(); >> + return false; >> + } >> + } >> + return true; >> +} >> >> Added: llvm/trunk/test/Transforms/ScalarRepl/debuginfo.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/debuginfo.ll?rev=64207&view=auto >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/test/Transforms/ScalarRepl/debuginfo.ll (added) >> +++ llvm/trunk/test/Transforms/ScalarRepl/debuginfo.ll Tue Feb 10 >> 01:00:59 2009 >> @@ -0,0 +1,105 @@ >> +; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | not grep alloca >> + %llvm.dbg.anchor.type = type { i32, i32 } >> + %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, >> i64, i64, i32, i32 } >> + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, >> i8*, i1, i1, i8* } >> + %llvm.dbg.composite.type = type { i32, { }*, i8*, { }*, i32, i64, >> i64, i64, i32, { }*, { }* } >> + %llvm.dbg.derivedtype.type = type { i32, { }*, i8*, { }*, i32, >> i64, i64, i64, i32, { }* } >> + %llvm.dbg.subprogram.type = type { i32, { }*, { }*, i8*, i8*, i8*, >> { }*, i32, { }*, i1, i1 } >> + %llvm.dbg.variable.type = type { i32, { }*, i8*, { }*, i32, { }* } >> + %struct.Sphere = type { %struct.Vec } >> + %struct.Vec = type { i32, i32, i32 } >> + at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type >> { i32 458752, i32 17 }, section "llvm.metadata" ; < >> %llvm.dbg.anchor.type*> [#uses=1] >> + at .str = internal constant [6 x i8] c"r.cpp\00", section >> "llvm.metadata" ; <[6 x i8]*> [#uses=1] >> + at .str1 = internal constant [5 x i8] c"/tmp\00", section >> "llvm.metadata" ; <[5 x i8]*> [#uses=1] >> + at .str2 = internal constant [55 x i8] c"4.2.1 (Based on Apple Inc. >> build 5636) (LLVM build 00)\00", section "llvm.metadata" ; <[55 x >> i8]*> [#uses=1] >> + at llvm.dbg.compile_unit = internal constant >> %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast >> (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 4, i8* >> getelementptr ([6 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([5 >> x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([55 x i8]* @.str2, >> i32 0, i32 0), i1 true, i1 false, i8* null }, section >> "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] >> + at .str3 = internal constant [4 x i8] c"Vec\00", section >> "llvm.metadata" ; <[4 x i8]*> [#uses=1] >> + at .str4 = internal constant [4 x i8] c"int\00", section >> "llvm.metadata" ; <[4 x i8]*> [#uses=1] >> + at llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type >> { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* >> @.str4, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 >> 0, i32 5 }, section "llvm.metadata" ; <%llvm.dbg.basictype.type*> >> [#uses=1] >> + at .str5 = internal constant [2 x i8] c"x\00", section >> "llvm.metadata" ; <[2 x i8]*> [#uses=1] >> + at llvm.dbg.derivedtype = internal constant >> %llvm.dbg.derivedtype.type { i32 458765, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* >> getelementptr ([2 x i8]* @.str5, i32 0, i32 0), { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 >> 4, i64 32, i64 32, i64 0, i32 0, { }* bitcast >> (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section >> "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] >> + at .str6 = internal constant [2 x i8] c"y\00", section >> "llvm.metadata" ; <[2 x i8]*> [#uses=1] >> + at llvm.dbg.derivedtype7 = internal constant >> %llvm.dbg.derivedtype.type { i32 458765, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* >> getelementptr ([2 x i8]* @.str6, i32 0, i32 0), { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 >> 4, i64 32, i64 32, i64 32, i32 0, { }* bitcast >> (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section >> "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] >> + at .str8 = internal constant [2 x i8] c"z\00", section >> "llvm.metadata" ; <[2 x i8]*> [#uses=1] >> + at llvm.dbg.derivedtype9 = internal constant >> %llvm.dbg.derivedtype.type { i32 458765, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* >> getelementptr ([2 x i8]* @.str8, i32 0, i32 0), { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 >> 4, i64 32, i64 32, i64 64, i32 0, { }* bitcast >> (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section >> "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] >> + at llvm.dbg.derivedtype10 = internal constant >> %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* >> null, { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 >> 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite18 to >> { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> >> [#uses=1] >> + at llvm.dbg.derivedtype11 = internal constant >> %llvm.dbg.derivedtype.type { i32 458790, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* >> null, { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i32 0, i64 96, i64 32, i64 0, i32 >> 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite18 to >> { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> >> [#uses=1] >> + at llvm.dbg.derivedtype12 = internal constant >> %llvm.dbg.derivedtype.type { i32 458768, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* >> null, { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 >> 0, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype11 >> to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> >> [#uses=1] >> + at llvm.dbg.array = internal constant [3 x { }*] [ { }* null, { }* >> bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype10 to >> { }*), { }* bitcast (%llvm.dbg.derivedtype.type* >> @llvm.dbg.derivedtype12 to { }*) ], section "llvm.metadata" ; <[3 x >> { }*]*> [#uses=1] >> + at llvm.dbg.composite13 = internal constant %llvm.dbg.composite.type >> { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 >> 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* >> @llvm.dbg.array to { }*) }, section "llvm.metadata" ; < >> %llvm.dbg.composite.type*> [#uses=1] >> + at llvm.dbg.subprograms = linkonce constant %llvm.dbg.anchor.type >> { i32 458752, i32 46 }, section "llvm.metadata" ; < >> %llvm.dbg.anchor.type*> [#uses=1] >> + at llvm.dbg.subprogram = internal constant %llvm.dbg.subprogram.type >> { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* >> @llvm.dbg.subprograms to { }*), { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* >> getelementptr ([4 x i8]* @.str3, i32 0, i32 0), i8* getelementptr >> ([4 x i8]* @.str3, i32 0, i32 0), i8* null, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 >> 2, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite13 to >> { }*), i1 false, i1 false }, section "llvm.metadata" ; < >> %llvm.dbg.subprogram.type*> [#uses=1] >> + at llvm.dbg.array14 = internal constant [5 x { }*] [ { }* null, { }* >> bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype10 to >> { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype >> to { }*), { }* bitcast (%llvm.dbg.basictype.type* >> @llvm.dbg.basictype to { }*), { }* bitcast >> (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) ], section >> "llvm.metadata" ; <[5 x { }*]*> [#uses=1] >> + at llvm.dbg.composite15 = internal constant %llvm.dbg.composite.type >> { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 >> 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([5 x { }*]* >> @llvm.dbg.array14 to { }*) }, section "llvm.metadata" ; < >> %llvm.dbg.composite.type*> [#uses=1] >> + at llvm.dbg.subprogram16 = internal constant >> %llvm.dbg.subprogram.type { i32 458798, { }* bitcast >> (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* >> getelementptr ([4 x i8]* @.str3, i32 0, i32 0), i8* getelementptr >> ([4 x i8]* @.str3, i32 0, i32 0), i8* null, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 >> 5, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite15 to >> { }*), i1 false, i1 false }, section "llvm.metadata" ; < >> %llvm.dbg.subprogram.type*> [#uses=1] >> + at llvm.dbg.array17 = internal constant [5 x { }*] [ { }* bitcast >> (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*), { }* >> bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype7 to >> { }*), { }* bitcast (%llvm.dbg.derivedtype.type* >> @llvm.dbg.derivedtype9 to { }*), { }* bitcast >> (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), { }* >> bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram16 to >> { }*) ], section "llvm.metadata" ; <[5 x { }*]*> [#uses=1] >> + at llvm.dbg.composite18 = internal constant %llvm.dbg.composite.type >> { i32 458771, { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* >> @.str3, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i32 2, i64 96, i64 32, i64 0, i32 >> 0, { }* null, { }* bitcast ([5 x { }*]* @llvm.dbg.array17 to >> { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> >> [#uses=1] >> + at llvm.dbg.derivedtype19 = internal constant >> %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* >> null, { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 >> 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite18 to >> { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> >> [#uses=1] >> + at llvm.dbg.array20 = internal constant [5 x { }*] [ { }* null, { }* >> bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype19 to >> { }*), { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype >> to { }*), { }* bitcast (%llvm.dbg.basictype.type* >> @llvm.dbg.basictype to { }*), { }* bitcast >> (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) ], section >> "llvm.metadata" ; <[5 x { }*]*> [#uses=1] >> + at llvm.dbg.composite = internal constant %llvm.dbg.composite.type >> { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 >> 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([5 x { }*]* >> @llvm.dbg.array20 to { }*) }, section "llvm.metadata" ; < >> %llvm.dbg.composite.type*> [#uses=1] >> + at .str21 = internal constant [13 x i8] c"__comp_ctor \00", section >> "llvm.metadata" ; <[13 x i8]*> [#uses=1] >> + at .str22 = internal constant [14 x i8] c"_ZN3VecC1Eiii\00", section >> "llvm.metadata" ; <[14 x i8]*> [#uses=1] >> + at llvm.dbg.array32 = internal constant [3 x { }*] [ { }* bitcast >> (%llvm.dbg.composite.type* @llvm.dbg.composite18 to { }*), { }* >> bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype12 to >> { }*), { }* bitcast (%llvm.dbg.derivedtype.type* >> @llvm.dbg.derivedtype12 to { }*) ], section "llvm.metadata" ; <[3 x >> { }*]*> [#uses=1] >> + at llvm.dbg.composite33 = internal constant %llvm.dbg.composite.type >> { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 >> 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* >> @llvm.dbg.array32 to { }*) }, section "llvm.metadata" ; < >> %llvm.dbg.composite.type*> [#uses=1] >> + at .str34 = internal constant [10 x i8] c"operator-\00", section >> "llvm.metadata" ; <[10 x i8]*> [#uses=1] >> + at .str35 = internal constant [14 x i8] c"_ZmiRK3VecS1_\00", section >> "llvm.metadata" ; <[14 x i8]*> [#uses=1] >> + at .str41 = internal constant [7 x i8] c"Sphere\00", section >> "llvm.metadata" ; <[7 x i8]*> [#uses=1] >> + at .str43 = internal constant [7 x i8] c"center\00", section >> "llvm.metadata" ; <[7 x i8]*> [#uses=1] >> + at llvm.dbg.derivedtype44 = internal constant >> %llvm.dbg.derivedtype.type { i32 458765, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* >> getelementptr ([7 x i8]* @.str43, i32 0, i32 0), { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 >> 14, i64 96, i64 32, i64 0, i32 1, { }* bitcast >> (%llvm.dbg.composite.type* @llvm.dbg.composite18 to { }*) }, section >> "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] >> + at llvm.dbg.derivedtype45 = internal constant >> %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* >> null, { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 >> 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite52 to >> { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> >> [#uses=1] >> + at llvm.dbg.array46 = internal constant [3 x { }*] [ { }* bitcast >> (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* >> bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype45 to >> { }*), { }* bitcast (%llvm.dbg.derivedtype.type* >> @llvm.dbg.derivedtype12 to { }*) ], section "llvm.metadata" ; <[3 x >> { }*]*> [#uses=1] >> + at llvm.dbg.composite47 = internal constant %llvm.dbg.composite.type >> { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 >> 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* >> @llvm.dbg.array46 to { }*) }, section "llvm.metadata" ; < >> %llvm.dbg.composite.type*> [#uses=1] >> + at .str48 = internal constant [11 x i8] c"ray_sphere\00", section >> "llvm.metadata" ; <[11 x i8]*> [#uses=1] >> + at .str49 = internal constant [30 x i8] >> c"_ZN6Sphere10ray_sphereERK3Vec\00", section "llvm.metadata" ; <[30 >> x i8]*> [#uses=1] >> + at llvm.dbg.subprogram50 = internal constant >> %llvm.dbg.subprogram.type { i32 458798, { }* bitcast >> (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* >> getelementptr ([11 x i8]* @.str48, i32 0, i32 0), i8* getelementptr >> ([11 x i8]* @.str48, i32 0, i32 0), i8* getelementptr ([30 x i8]* >> @.str49, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i32 16, { }* bitcast >> (%llvm.dbg.composite.type* @llvm.dbg.composite47 to { }*), i1 false, >> i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> >> [#uses=1] >> + at llvm.dbg.array51 = internal constant [2 x { }*] [ { }* bitcast >> (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype44 to { }*), { }* >> bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram50 to >> { }*) ], section "llvm.metadata" ; <[2 x { }*]*> [#uses=1] >> + at llvm.dbg.composite52 = internal constant %llvm.dbg.composite.type >> { i32 458771, { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i8* getelementptr ([7 x i8]* >> @.str41, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i32 12, i64 96, i64 32, i64 0, i32 >> 0, { }* null, { }* bitcast ([2 x { }*]* @llvm.dbg.array51 to >> { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> >> [#uses=1] >> + at llvm.dbg.derivedtype53 = internal constant >> %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* >> null, { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 >> 0, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite52 to >> { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> >> [#uses=1] >> + at llvm.dbg.array54 = internal constant [3 x { }*] [ { }* bitcast >> (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* >> bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype53 to >> { }*), { }* bitcast (%llvm.dbg.derivedtype.type* >> @llvm.dbg.derivedtype12 to { }*) ], section "llvm.metadata" ; <[3 x >> { }*]*> [#uses=1] >> + at llvm.dbg.composite55 = internal constant %llvm.dbg.composite.type >> { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i8* null, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 >> 0, i64 0, i64 0, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* >> @llvm.dbg.array54 to { }*) }, section "llvm.metadata" ; < >> %llvm.dbg.composite.type*> [#uses=1] >> + at llvm.dbg.subprogram56 = internal constant >> %llvm.dbg.subprogram.type { i32 458798, { }* bitcast >> (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* >> getelementptr ([11 x i8]* @.str48, i32 0, i32 0), i8* getelementptr >> ([11 x i8]* @.str48, i32 0, i32 0), i8* getelementptr ([30 x i8]* >> @.str49, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i32 16, { }* bitcast >> (%llvm.dbg.composite.type* @llvm.dbg.composite55 to { }*), i1 false, >> i1 true }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> >> [#uses=1] >> + at .str61 = internal constant [2 x i8] c"v\00", section >> "llvm.metadata" ; <[2 x i8]*> [#uses=1] >> + at llvm.dbg.variable62 = internal constant %llvm.dbg.variable.type >> { i32 459008, { }* bitcast (%llvm.dbg.subprogram.type* >> @llvm.dbg.subprogram56 to { }*), i8* getelementptr ([2 x i8]* >> @.str61, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* >> @llvm.dbg.compile_unit to { }*), i32 17, { }* bitcast >> (%llvm.dbg.composite.type* @llvm.dbg.composite18 to { }*) }, section >> "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=1] >> + >> +declare void @llvm.dbg.func.start({ }*) nounwind >> + >> +declare void @llvm.dbg.declare({ }*, { }*) nounwind >> + >> +declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind >> + >> +declare void @llvm.dbg.region.end({ }*) nounwind >> + >> +define i32 @_ZN6Sphere10ray_sphereERK3Vec(%struct.Sphere* %this, >> %struct.Vec* %Orig) nounwind { >> +entry: >> + %v = alloca %struct.Vec, align 8 ; <%struct.Vec*> [#uses=4] >> + call void @llvm.dbg.func.start({ }* bitcast >> (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram56 to { }*)) >> + %0 = bitcast %struct.Vec* %v to { }* ; <{ }*> [#uses=1] >> + call void @llvm.dbg.declare({ }* %0, { }* bitcast >> (%llvm.dbg.variable.type* @llvm.dbg.variable62 to { }*)) >> + %1 = getelementptr %struct.Sphere* %this, i32 0, i32 0, i32 2 ; >> [#uses=1] >> + %2 = load i32* %1, align 4 ; [#uses=1] >> + %3 = getelementptr %struct.Vec* %Orig, i32 0, i32 2 ; >> [#uses=1] >> + %4 = load i32* %3, align 4 ; [#uses=1] >> + %5 = sub i32 %2, %4 ; [#uses=1] >> + %6 = getelementptr %struct.Sphere* %this, i32 0, i32 0, i32 1 ; >> [#uses=1] >> + %7 = load i32* %6, align 4 ; [#uses=1] >> + %8 = getelementptr %struct.Vec* %Orig, i32 0, i32 1 ; >> [#uses=1] >> + %9 = load i32* %8, align 4 ; [#uses=1] >> + %10 = sub i32 %7, %9 ; [#uses=1] >> + %11 = getelementptr %struct.Sphere* %this, i32 0, i32 0, i32 0 ; >> [#uses=1] >> + %12 = load i32* %11, align 4 ; [#uses=1] >> + %13 = getelementptr %struct.Vec* %Orig, i32 0, i32 0 ; >> [#uses=1] >> + %14 = load i32* %13, align 4 ; [#uses=1] >> + %15 = sub i32 %12, %14 ; [#uses=1] >> + %16 = getelementptr %struct.Vec* %v, i32 0, i32 0 ; >> [#uses=2] >> + store i32 %15, i32* %16, align 8 >> + %17 = getelementptr %struct.Vec* %v, i32 0, i32 1 ; >> [#uses=1] >> + store i32 %10, i32* %17, align 4 >> + %18 = getelementptr %struct.Vec* %v, i32 0, i32 2 ; >> [#uses=1] >> + store i32 %5, i32* %18, align 8 >> + call void @llvm.dbg.stoppoint(i32 5, i32 0, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) >> nounwind >> + call void @llvm.dbg.stoppoint(i32 9, i32 0, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) >> nounwind >> + %19 = load i32* %16, align 8 ; [#uses=1] >> + call void @llvm.dbg.stoppoint(i32 18, i32 0, { }* bitcast >> (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) >> + call void @llvm.dbg.region.end({ }* bitcast >> (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram56 to { }*)) >> + ret i32 %19 >> +} >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits - Devang From dalej at apple.com Tue Feb 10 13:13:11 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 10 Feb 2009 11:13:11 -0800 Subject: [llvm-commits] r64000 breaks PIC16 In-Reply-To: <1234292444.7110.7.camel@idc-lt-i00171.microchip.com> References: <1234292444.7110.7.camel@idc-lt-i00171.microchip.com> Message-ID: I'll look. I don't know enough about PIC16 to see what's wrong with the assembly, could you send a .bc file? On Feb 10, 2009, at 11:00 AMPST, sanjiv gupta wrote: > Try with a simple test > int foo (int i) > { > if (i < 0) > return -1; > else > return 1; > } > > The correct assembly is: (as per r63998) > code.foo.# CODE > foo: > movlw 128 > banksel foo.arg.i > xorwf foo.arg.i + 1, W > movwf foo.tmp + 2 > movlw 127 > movwf foo.tmp + 1 > movf foo.tmp + 2, W > subwf foo.tmp + 1, W > blt .BB1_2 ; if.else (correct - br after test) > .BB1_1 ; if.then > movlw 255 > movwf foo.args + 0 > movwf foo.args + 1 > goto .BB1_3 ; return > .BB1_2 ; if.else > movlw 1 > movwf foo.args + 0 > ... > > > > The incorrect assembly is : (as per r64000) > code.foo.# CODE > foo: > movlw 127 > movwf foo.tmp + 1 > blt .BB1_2 ; if.else (??? - br w/o test) > .BB1_1 ; if.then > movlw 128 > banksel foo.arg.i > xorwf foo.arg.i + 1, W > subwf foo.tmp + 1, W > movlw 255 > movwf foo.args + 0 > movwf foo.args + 1 > goto .BB1_3 ; return > .BB1_2 ; if.else > movlw 1 > movwf foo.args + 0 > movlw 0 > movwf foo.args + 1 > > > Thanks, > -Sanjiv From dpatel at apple.com Tue Feb 10 13:28:07 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 10 Feb 2009 19:28:07 -0000 Subject: [llvm-commits] [llvm] r64226 - /llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Message-ID: <200902101928.n1AJS7lE018139@zion.cs.uiuc.edu> Author: dpatel Date: Tue Feb 10 13:28:07 2009 New Revision: 64226 URL: http://llvm.org/viewvc/llvm-project?rev=64226&view=rev Log: Use early exits. Reduce indentation. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=64226&r1=64225&r2=64226&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Tue Feb 10 13:28:07 2009 @@ -1142,47 +1142,52 @@ gep_type_iterator I = gep_type_begin(GEPI); ++I; - if (const ArrayType *AT = dyn_cast(*I)) { - uint64_t NumElements = AT->getNumElements(); - - if (!isa(I.getOperand())) { - if (NumElements == 1) { - GEPI->setOperand(2, Constant::getNullValue(Type::Int32Ty)); - } else { - assert(NumElements == 2 && "Unhandled case!"); - // All users of the GEP must be loads. At each use of the GEP, insert - // two loads of the appropriate indexed GEP and select between them. - Value *IsOne = new ICmpInst(ICmpInst::ICMP_NE, I.getOperand(), - Constant::getNullValue(I.getOperand()->getType()), - "isone", GEPI); - // Insert the new GEP instructions, which are properly indexed. - SmallVector Indices(GEPI->op_begin()+1, GEPI->op_end()); - Indices[1] = Constant::getNullValue(Type::Int32Ty); - Value *ZeroIdx = GetElementPtrInst::Create(GEPI->getOperand(0), - Indices.begin(), - Indices.end(), - GEPI->getName()+".0", GEPI); - Indices[1] = ConstantInt::get(Type::Int32Ty, 1); - Value *OneIdx = GetElementPtrInst::Create(GEPI->getOperand(0), - Indices.begin(), - Indices.end(), - GEPI->getName()+".1", GEPI); - // Replace all loads of the variable index GEP with loads from both - // indexes and a select. - while (!GEPI->use_empty()) { - LoadInst *LI = cast(GEPI->use_back()); - Value *Zero = new LoadInst(ZeroIdx, LI->getName()+".0", LI); - Value *One = new LoadInst(OneIdx , LI->getName()+".1", LI); - Value *R = SelectInst::Create(IsOne, One, Zero, LI->getName(), LI); - LI->replaceAllUsesWith(R); - LI->eraseFromParent(); - } - GEPI->eraseFromParent(); - } - } + const ArrayType *AT = dyn_cast(*I); + if (!AT) + return; + + uint64_t NumElements = AT->getNumElements(); + + if (isa(I.getOperand())) + return; + + if (NumElements == 1) { + GEPI->setOperand(2, Constant::getNullValue(Type::Int32Ty)); + return; + } + + assert(NumElements == 2 && "Unhandled case!"); + // All users of the GEP must be loads. At each use of the GEP, insert + // two loads of the appropriate indexed GEP and select between them. + Value *IsOne = new ICmpInst(ICmpInst::ICMP_NE, I.getOperand(), + Constant::getNullValue(I.getOperand()->getType()), + "isone", GEPI); + // Insert the new GEP instructions, which are properly indexed. + SmallVector Indices(GEPI->op_begin()+1, GEPI->op_end()); + Indices[1] = Constant::getNullValue(Type::Int32Ty); + Value *ZeroIdx = GetElementPtrInst::Create(GEPI->getOperand(0), + Indices.begin(), + Indices.end(), + GEPI->getName()+".0", GEPI); + Indices[1] = ConstantInt::get(Type::Int32Ty, 1); + Value *OneIdx = GetElementPtrInst::Create(GEPI->getOperand(0), + Indices.begin(), + Indices.end(), + GEPI->getName()+".1", GEPI); + // Replace all loads of the variable index GEP with loads from both + // indexes and a select. + while (!GEPI->use_empty()) { + LoadInst *LI = cast(GEPI->use_back()); + Value *Zero = new LoadInst(ZeroIdx, LI->getName()+".0", LI); + Value *One = new LoadInst(OneIdx , LI->getName()+".1", LI); + Value *R = SelectInst::Create(IsOne, One, Zero, LI->getName(), LI); + LI->replaceAllUsesWith(R); + LI->eraseFromParent(); } + GEPI->eraseFromParent(); } + /// CleanupAllocaUsers - If SROA reported that it can promote the specified /// allocation, but only if cleaned up, perform the cleanups required. void SROA::CleanupAllocaUsers(AllocationInst *AI) { From sabre at nondot.org Tue Feb 10 13:32:36 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 10 Feb 2009 19:32:36 -0000 Subject: [llvm-commits] [test-suite] r64227 - /test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/scimark2.c Message-ID: <200902101932.n1AJWa0g018314@zion.cs.uiuc.edu> Author: lattner Date: Tue Feb 10 13:32:34 2009 New Revision: 64227 URL: http://llvm.org/viewvc/llvm-project?rev=64227&view=rev Log: factor out constant. Modified: test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/scimark2.c Modified: test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/scimark2.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/scimark2.c?rev=64227&r1=64226&r2=64227&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/scimark2.c (original) +++ test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/scimark2.c Tue Feb 10 13:32:34 2009 @@ -19,6 +19,7 @@ int Sparse_size_M = SPARSE_SIZE_M; int Sparse_size_nz = SPARSE_SIZE_nz; int LU_size = LU_SIZE; + int SCALE; /* run the benchmark */ @@ -67,20 +68,22 @@ Sparse_size_nz, min_time, R); res[5] = kernel_measureLU( LU_size, min_time, R); - - + /* make output determinstic by scaling results to 0. change this to 1 + * to see the actual output. */ + SCALE = 10000000; + res[0] = (res[1] + res[2] + res[3] + res[4] + res[5]) / 5; /* print out results */ printf("NOTE!!! All Mflops disabled to prevent diffs from failing!\n"); - printf("Composite Score: %8.2f\n" ,res[0]/10000000); - printf("FFT Mflops: %8.2f (N=%d)\n", res[1]/10000000, FFT_size); + printf("Composite Score: %8.2f\n" ,res[0]/SCALE); + printf("FFT Mflops: %8.2f (N=%d)\n", res[1]/SCALE, FFT_size); printf("SOR Mflops: %8.2f (%d x %d)\n", - res[2]/10000000, SOR_size, SOR_size); - printf("MonteCarlo: Mflops: %8.2f\n", res[3]/10000000); - printf("Sparse matmult Mflops: %8.2f (N=%d, nz=%d)\n", res[4]/10000000, + res[2]/SCALE, SOR_size, SOR_size); + printf("MonteCarlo: Mflops: %8.2f\n", res[3]/SCALE); + printf("Sparse matmult Mflops: %8.2f (N=%d, nz=%d)\n", res[4]/SCALE, Sparse_size_M, Sparse_size_nz); - printf("LU Mflops: %8.2f (M=%d, N=%d)\n", res[5]/10000000, + printf("LU Mflops: %8.2f (M=%d, N=%d)\n", res[5]/SCALE, LU_size, LU_size); From sabre at nondot.org Tue Feb 10 13:43:42 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 10 Feb 2009 19:43:42 -0000 Subject: [llvm-commits] [test-suite] r64228 - in /test-suite/trunk/MultiSource/Benchmarks/SciMark2-C: Random.c Stopwatch.c array.c kernel.c Message-ID: <200902101943.n1AJhgLb018688@zion.cs.uiuc.edu> Author: lattner Date: Tue Feb 10 13:43:42 2009 New Revision: 64228 URL: http://llvm.org/viewvc/llvm-project?rev=64228&view=rev Log: include the right header to get a malloc prototype. Modified: test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/Random.c test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/Stopwatch.c test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/array.c test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/kernel.c Modified: test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/Random.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/Random.c?rev=64228&r1=64227&r2=64228&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/Random.c (original) +++ test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/Random.c Tue Feb 10 13:43:42 2009 @@ -1,7 +1,6 @@ -/* #include (brg) */ - +#include #include "Random.h" #ifndef NULL Modified: test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/Stopwatch.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/Stopwatch.c?rev=64228&r1=64227&r2=64228&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/Stopwatch.c (original) +++ test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/Stopwatch.c Tue Feb 10 13:43:42 2009 @@ -1,4 +1,4 @@ -/* #include (brg) */ +#include #include "Stopwatch.h" double seconds() Modified: test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/array.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/array.c?rev=64228&r1=64227&r2=64228&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/array.c (original) +++ test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/array.c Tue Feb 10 13:43:42 2009 @@ -1,5 +1,5 @@ -/* #include (brg) */ #include +#include #include "array.h" #ifndef NULL Modified: test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/kernel.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/kernel.c?rev=64228&r1=64227&r2=64228&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/kernel.c (original) +++ test-suite/trunk/MultiSource/Benchmarks/SciMark2-C/kernel.c Tue Feb 10 13:43:42 2009 @@ -1,5 +1,4 @@ #include -/* #include (brg) */ #include #include "LU.h" #include "FFT.h" From gohman at apple.com Tue Feb 10 14:24:19 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 10 Feb 2009 12:24:19 -0800 Subject: [llvm-commits] r64000 breaks PIC16 In-Reply-To: <1234292444.7110.7.camel@idc-lt-i00171.microchip.com> References: <1234292444.7110.7.camel@idc-lt-i00171.microchip.com> Message-ID: <3BEE949D-7D28-4B3F-A69C-3E972C8716A9@apple.com> On Feb 10, 2009, at 11:00 AM, sanjiv gupta wrote: > The correct assembly is: (as per r63998) [snip] > > The incorrect assembly is : (as per r64000) [snip] It looks like 63999, enabling sinking, is more likely to be the revision that introduces the change. If it is, can you check to see if the problem is fixed in the latest trunk? Dan From baldrick at free.fr Tue Feb 10 14:43:26 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 10 Feb 2009 20:43:26 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r64234 - in /llvm-gcc-4.2/trunk/gcc: llvm-convert.cpp llvm-types.cpp Message-ID: <200902102043.n1AKhRlT020798@zion.cs.uiuc.edu> Author: baldrick Date: Tue Feb 10 14:43:26 2009 New Revision: 64234 URL: http://llvm.org/viewvc/llvm-project?rev=64234&view=rev Log: Handle odd-sized integers coming from bitfields using apint codegen rather than the current hack. See FrontendC/2008-01-07-UnusualIntSize.c. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=64234&r1=64233&r2=64234&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Feb 10 14:43:26 2009 @@ -1101,31 +1101,7 @@ Result = TreeConstantToLLVM::ConvertVECTOR_CST(exp); break; } - - // If this is an operation on an integer value in a precision smaller than - // the LLVM value we are computing it in, reduce the excess precision here. - // This happens with odd-sized bitfields (e.g. i33) that are evaluated in the - // next size power-of-two register (e.g. i64). This should be reevaluated - // when we have good support for unusual sized integers in the code generator. - if (Result && TREE_CODE(TREE_TYPE(exp)) == INTEGER_TYPE) { - unsigned LLVMWidth = Result->getType()->getPrimitiveSizeInBits(); - unsigned TreeWidth = TYPE_PRECISION(TREE_TYPE(exp)); - if (LLVMWidth > TreeWidth && lang_hooks.reduce_bit_field_operations) { - if (TYPE_UNSIGNED(TREE_TYPE(exp))) { - // Use an 'and' to clear excess top bits. - Constant *Mask = - ConstantInt::get(APInt::getLowBitsSet(LLVMWidth, TreeWidth)); - Result = Builder.CreateAnd(Result, Mask, "mask"); - } else { - // Shift Left then shift right. - Constant *ShAmt = ConstantInt::get(Result->getType(), - LLVMWidth-TreeWidth); - Result = Builder.CreateShl(Result, ShAmt, "sextl"); - Result = Builder.CreateAShr(Result, ShAmt, "sextr"); - } - } - } - + if (TheDebugInfo && EXPR_HAS_LOCATION(exp)) { // Restore location back down the tree. TheDebugInfo->setLocationFile(EXPR_FILENAME(exp)); Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=64234&r1=64233&r2=64234&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Tue Feb 10 14:43:26 2009 @@ -746,8 +746,7 @@ type = orig_type; case INTEGER_TYPE: if (const Type *Ty = GET_TYPE_LLVM(type)) return Ty; - return SET_TYPE_LLVM(type, - IntegerType::get(TREE_INT_CST_LOW(TYPE_SIZE(type)))); + return SET_TYPE_LLVM(type, IntegerType::get(TYPE_PRECISION(type))); case REAL_TYPE: if (const Type *Ty = GET_TYPE_LLVM(type)) return Ty; switch (TYPE_PRECISION(type)) { From baldrick at free.fr Tue Feb 10 14:44:16 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 10 Feb 2009 20:44:16 -0000 Subject: [llvm-commits] [llvm] r64236 - /llvm/trunk/test/FrontendC/2008-01-07-UnusualIntSize.c Message-ID: <200902102044.n1AKiGJg020840@zion.cs.uiuc.edu> Author: baldrick Date: Tue Feb 10 14:44:15 2009 New Revision: 64236 URL: http://llvm.org/viewvc/llvm-project?rev=64236&view=rev Log: This is now done using a real i33, rather than an emulated one. Adjust the check. Modified: llvm/trunk/test/FrontendC/2008-01-07-UnusualIntSize.c Modified: llvm/trunk/test/FrontendC/2008-01-07-UnusualIntSize.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2008-01-07-UnusualIntSize.c?rev=64236&r1=64235&r2=64236&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/2008-01-07-UnusualIntSize.c (original) +++ llvm/trunk/test/FrontendC/2008-01-07-UnusualIntSize.c Tue Feb 10 14:44:15 2009 @@ -1,4 +1,4 @@ -// RUN: %llvmgcc %s -S -o - -O | grep {and.*8589934591} +// RUN: %llvmgcc %s -S -o - -O | grep i33 // PR1721 struct s { From anton at korobeynikov.info Tue Feb 10 15:21:55 2009 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Wed, 11 Feb 2009 00:21:55 +0300 Subject: [llvm-commits] [llvm] r64186 - in /llvm/trunk: lib/Target/X86/X86FloatingPoint.cpp lib/Target/X86/X86InstrFPStack.td lib/Target/X86/X86InstrInfo.cpp test/CodeGen/X86/fp-stack-set-st1.ll In-Reply-To: <639FDFBC-521A-4735-9F6F-1FA91C3B1442@apple.com> References: <200902092332.n19NW72X016523@zion.cs.uiuc.edu> <639FDFBC-521A-4735-9F6F-1FA91C3B1442@apple.com> Message-ID: > No. We still have troubles with inline asm with x87 math. :( This seems to be the main problem preventing mingw64 port of LLVM -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From clattner at apple.com Tue Feb 10 15:38:02 2009 From: clattner at apple.com (Chris Lattner) Date: Tue, 10 Feb 2009 13:38:02 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r64234 - in /llvm-gcc-4.2/trunk/gcc: llvm-convert.cpp llvm-types.cpp In-Reply-To: <200902102043.n1AKhRlT020798@zion.cs.uiuc.edu> References: <200902102043.n1AKhRlT020798@zion.cs.uiuc.edu> Message-ID: <142507D2-BE3E-4428-B4F7-D39618E136BD@apple.com> On Feb 10, 2009, at 12:43 PM, Duncan Sands wrote: > Author: baldrick > Date: Tue Feb 10 14:43:26 2009 > New Revision: 64234 > > URL: http://llvm.org/viewvc/llvm-project?rev=64234&view=rev > Log: > Handle odd-sized integers coming from bitfields > using apint codegen rather than the current hack. > See FrontendC/2008-01-07-UnusualIntSize.c. nice! From evan.cheng at apple.com Tue Feb 10 15:39:44 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 10 Feb 2009 21:39:44 -0000 Subject: [llvm-commits] [llvm] r64237 - /llvm/trunk/lib/Target/X86/X86Instr64bit.td Message-ID: <200902102139.n1ALdj4R022875@zion.cs.uiuc.edu> Author: evancheng Date: Tue Feb 10 15:39:44 2009 New Revision: 64237 URL: http://llvm.org/viewvc/llvm-project?rev=64237&view=rev Log: 80 col violations. Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=64237&r1=64236&r2=64237&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Tue Feb 10 15:39:44 2009 @@ -120,19 +120,22 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in -def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset, variable_ops), +def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset, + variable_ops), "#TC_RETURN $dst $offset", []>; let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in -def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset, variable_ops), +def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset, + variable_ops), "#TC_RETURN $dst $offset", []>; let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in - def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst # TAILCALL", - []>; + def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst), + "jmp{q}\t{*}$dst # TAILCALL", + []>; // Branches let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { From evan.cheng at apple.com Tue Feb 10 16:06:28 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 10 Feb 2009 22:06:28 -0000 Subject: [llvm-commits] [llvm] r64240 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/maskmovdqu.ll Message-ID: <200902102206.n1AM6SrC024028@zion.cs.uiuc.edu> Author: evancheng Date: Tue Feb 10 16:06:28 2009 New Revision: 64240 URL: http://llvm.org/viewvc/llvm-project?rev=64240&view=rev Log: Handle llvm.x86.sse2.maskmov.dqu in 64-bit. Added: llvm/trunk/test/CodeGen/X86/maskmovdqu.ll Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=64240&r1=64239&r2=64240&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Feb 10 16:06:28 2009 @@ -2231,6 +2231,11 @@ "maskmovdqu\t{$mask, $src|$src, $mask}", [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>; +let Uses = [RDI] in +def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask), + "maskmovdqu\t{$mask, $src|$src, $mask}", + [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>; + // Non-temporal stores def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), "movntpd\t{$src, $dst|$dst, $src}", Added: llvm/trunk/test/CodeGen/X86/maskmovdqu.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/maskmovdqu.ll?rev=64240&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/maskmovdqu.ll (added) +++ llvm/trunk/test/CodeGen/X86/maskmovdqu.ll Tue Feb 10 16:06:28 2009 @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep -i EDI +; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse2 | grep -i RDI +; rdar://6573467 + +define void @test(<16 x i8> %a, <16 x i8> %b, i32 %dummy, i8* %c) nounwind { +entry: + tail call void @llvm.x86.sse2.maskmov.dqu( <16 x i8> %a, <16 x i8> %b, i8* %c ) + ret void +} + +declare void @llvm.x86.sse2.maskmov.dqu(<16 x i8>, <16 x i8>, i8*) nounwind From daniel at zuster.org Tue Feb 10 16:09:00 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 10 Feb 2009 22:09:00 -0000 Subject: [llvm-commits] [test-suite] r64241 - in /test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor: ch.c pointlis.c vor.c Message-ID: <200902102209.n1AM904c024141@zion.cs.uiuc.edu> Author: ddunbar Date: Tue Feb 10 16:09:00 2009 New Revision: 64241 URL: http://llvm.org/viewvc/llvm-project?rev=64241&view=rev Log: Include as needed. Modified: test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/ch.c test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/pointlis.c test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/vor.c Modified: test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/ch.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/ch.c?rev=64241&r1=64240&r2=64241&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/ch.c (original) +++ test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/ch.c Tue Feb 10 16:09:00 2009 @@ -14,6 +14,7 @@ ****/ #include +#include #include "struktur.h" #include "headers.h" Modified: test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/pointlis.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/pointlis.c?rev=64241&r1=64240&r2=64241&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/pointlis.c (original) +++ test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/pointlis.c Tue Feb 10 16:09:00 2009 @@ -14,6 +14,7 @@ ****/ #include +#include #include "struktur.h" #include "headers.h" extern int default_radius; Modified: test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/vor.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/vor.c?rev=64241&r1=64240&r2=64241&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/vor.c (original) +++ test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/vor.c Tue Feb 10 16:09:00 2009 @@ -15,6 +15,7 @@ #include #include +#include #include "struktur.h" #include "headers.h" From zaimoni at zaimoni.com Tue Feb 10 16:11:18 2009 From: zaimoni at zaimoni.com (Kenneth Boyd) Date: Tue, 10 Feb 2009 16:11:18 -0600 Subject: [llvm-commits] Win32/Alarm.inc rev. 64231 : MingW32 error Message-ID: <4991FB86.2020605@zaimoni.com> This patch gets the build past this point, leaving only one error to speak of. llvm[1]: Compiling Alarm.cpp for Release-Asserts build In file included from c:/CPP_App.SVN/llvm.svn/lib/System/Alarm.cpp:32: c:/CPP_App.SVN/llvm.svn/lib/System/Win32/Alarm.inc: In function 'void Sleep(unsigned int)': c:/CPP_App.SVN/llvm.svn/lib/System/Win32/Alarm.inc:39: error: call of overloaded 'Sleep(unsigned int)' is ambiguous c:/CPP_App.SVN/llvm.svn/lib/System/Win32/Alarm.inc:38: note: candidates are: void Sleep(unsigned int) c:/CPP_App.SVN/llvm.svn/include/llvm/System/Alarm.h:44: note: void llvm::sys::Sleep(unsigned int) make[1]: *** [/CPP_App.SVN/llvm.svn.optimized-noassert/lib/System/Release-Asserts/Alarm.o] Error 1 make[1]: Target `all' not remade because of errors. Please confirm that this patch enables building at least one MSVC build or one MingW32 build before committing. Kenneth P.S.: The extern "C" qualification is because I need that to link under MingW32 in another project. It also allows llvm-config to exist rather than be vainly regenerated each time. P.P.S.: the remaining error in a tools-only build, make[2]: Entering directory `C:/CPP_App.SVN/llvm.svn.optimized-noassert/utils/unittest' if [ ! -f googletest/Makefile ]; then \ /CPP_App.SVN/llvm.svn/autoconf/mkinstalldirs googletest; \ /bin/cp /CPP_App.SVN/llvm.svn/utils/unittest/googletest/Makefile googletest/Makefile; \ fi; \ c:/dev.tools/bin/make -C googletest all make[3]: Entering directory `C:/CPP_App.SVN/llvm.svn.optimized-noassert/utils/unittest/googletest' llvm[3]: Compiling gtest-filepath.cc for Release-Asserts build if g++ -I/CPP_App.SVN/llvm.svn/utils/unittest/googletest/include/ -Wno-missing-field-initializers -Wno-variadic-macros -I/CPP_App.SVN/llvm.svn.optimized-noassert/include -I/CPP_App.SVN/llvm.svn.optimized-noassert/utils/unittest/googletest -I/CPP_App.SVN/llvm.svn/include -I/CPP_App.SVN/llvm.svn/utils/unittest/googletest -DNDEBUG -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -O2 -fomit-frame-pointer -fno-exceptions -Woverloaded-virtual -pedantic -Wall -W -Wwrite-strings -Wno-long-long -Wunused -Wno-unused-parameter -c -MMD -MP -MF "/CPP_App.SVN/llvm.svn.optimized-noassert/utils/unittest/googletest/Release-Asserts/gtest-filepath.d.tmp" -MT "/CPP_App.SVN/llvm.svn.optimized-noassert/utils/unittest/googletest/Release-Asserts/gtest-filepath.lo" -MT "/CPP_App.SVN/llvm.svn.optimized-noassert/utils/unittest/googletest/Release-Asserts/gtest-filepath.o" -MT "/CPP_App.SVN/llvm.svn.optimized-noassert/utils/unittest/googletest/Release-Asserts/gtest-filepath.d" /CPP_App.SVN/llvm.svn/utils/unittest/googletest/gtest-filepath.cc -o /CPP_App.SVN/llvm.svn.optimized-noassert/utils/unittest/googletest/Release-Asserts/gtest-filepath.o ; \ then /bin/mv -f "/CPP_App.SVN/llvm.svn.optimized-noassert/utils/unittest/googletest/Release-Asserts/gtest-filepath.d.tmp" "/CPP_App.SVN/llvm.svn.optimized-noassert/utils/unittest/googletest/Release-Asserts/gtest-filepath.d"; else /bin/rm "/CPP_App.SVN/llvm.svn.optimized-noassert/utils/unittest/googletest/Release-Asserts/gtest-filepath.d.tmp"; exit 1; fi c:\mingw32\bin\../lib/gcc/mingw32/4.2.1-dw2/../../../../include/io.h: In member function 'bool testing::internal::FilePath::CreateFolder() const': c:\mingw32\bin\../lib/gcc/mingw32/4.2.1-dw2/../../../../include/io.h:176: error: too many arguments to function 'int mkdir(const char*)' c:/CPP_App.SVN/llvm.svn/utils/unittest/googletest/gtest-filepath.cc:277: error: at this point in file make[3]: *** [/CPP_App.SVN/llvm.svn.optimized-noassert/utils/unittest/googletest/Release-Asserts/gtest-filepath.o] Error 1 appears to be because GTEST_OS_WINDOWS is not defined. Fixing appears to be difficult (there is a todo note in gtest/internals/gtest-port.h that GTEST_OS_WINDOWS should be split into more macros, as it currently means both "OS is Windows" and "compiler is MSVC".) -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: Alarm.inc.patch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090210/d4d29fc1/attachment.pl From dpatel at apple.com Tue Feb 10 16:14:17 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 10 Feb 2009 22:14:17 -0000 Subject: [llvm-commits] [llvm] r64242 - in /llvm/trunk: lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/dbginfo.ll Message-ID: <200902102214.n1AMEH60024347@zion.cs.uiuc.edu> Author: dpatel Date: Tue Feb 10 16:14:17 2009 New Revision: 64242 URL: http://llvm.org/viewvc/llvm-project?rev=64242&view=rev Log: Ignore dbg intrinsic while folding unconditional branch. Added: llvm/trunk/test/Transforms/SimplifyCFG/dbginfo.ll Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=64242&r1=64241&r2=64242&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Feb 10 16:14:17 2009 @@ -1339,7 +1339,8 @@ if (!isa(BBI)) break; } - if (isa(BBI) || &*BBI == Term) + + if (isa(BBI) || &*BBI == Term || isa(BBI)) return true; return false; } Added: llvm/trunk/test/Transforms/SimplifyCFG/dbginfo.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/dbginfo.ll?rev=64242&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/dbginfo.ll (added) +++ llvm/trunk/test/Transforms/SimplifyCFG/dbginfo.ll Tue Feb 10 16:14:17 2009 @@ -0,0 +1,70 @@ +; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | grep region | count 1 + %llvm.dbg.anchor.type = type { i32, i32 } + %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 } + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } + %llvm.dbg.composite.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, { }* } + %llvm.dbg.derivedtype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }* } + %llvm.dbg.global_variable.type = type { i32, { }*, { }*, i8*, i8*, i8*, { }*, i32, { }*, i1, i1, { }* } + %llvm.dbg.subprogram.type = type { i32, { }*, { }*, i8*, i8*, i8*, { }*, i32, { }*, i1, i1 } + %llvm.dbg.subrange.type = type { i32, i64, i64 } + %struct.Group = type { %struct.Scene, %struct.Sphere, %"struct.std::list >" } + %struct.Ray = type { %struct.Vec, %struct.Vec } + %struct.Scene = type { i32 (...)** } + %struct.Sphere = type { %struct.Scene, %struct.Vec, double } + %struct.Vec = type { double, double, double } + %struct.__class_type_info_pseudo = type { %struct.__type_info_pseudo } + %struct.__false_type = type <{ i8 }> + %"struct.__gnu_cxx::new_allocator" = type <{ i8 }> + %"struct.__gnu_cxx::new_allocator >" = type <{ i8 }> + %struct.__si_class_type_info_pseudo = type { %struct.__type_info_pseudo, %"struct.std::type_info"* } + %struct.__type_info_pseudo = type { i8*, i8* } + %"struct.std::Hit" = type { double, %struct.Vec } + %"struct.std::_List_base >" = type { %"struct.std::_List_base >::_List_impl" } + %"struct.std::_List_base >::_List_impl" = type { %"struct.std::_List_node_base" } + %"struct.std::_List_const_iterator" = type { %"struct.std::_List_node_base"* } + %"struct.std::_List_iterator" = type { %"struct.std::_List_node_base"* } + %"struct.std::_List_node" = type { %"struct.std::_List_node_base", %struct.Scene* } + %"struct.std::_List_node_base" = type { %"struct.std::_List_node_base"*, %"struct.std::_List_node_base"* } + %"struct.std::allocator" = type <{ i8 }> + %"struct.std::allocator >" = type <{ i8 }> + %"struct.std::basic_ios >" = type { %"struct.std::ios_base", %"struct.std::basic_ostream >"*, i8, i8, %"struct.std::basic_streambuf >"*, %"struct.std::ctype"*, %"struct.std::num_get > >"*, %"struct.std::num_get > >"* } + %"struct.std::basic_ostream >" = type { i32 (...)**, %"struct.std::basic_ios >" } + %"struct.std::basic_streambuf >" = type { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, %"struct.std::locale" } + %"struct.std::ctype" = type { %"struct.std::locale::facet", i32*, i8, i32*, i32*, i32*, i8, [256 x i8], [256 x i8], i8 } + %"struct.std::ios_base" = type { i32 (...)**, i32, i32, i32, i32, i32, %"struct.std::ios_base::_Callback_list"*, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, %"struct.std::ios_base::_Words"*, %"struct.std::locale" } + %"struct.std::ios_base::Init" = type <{ i8 }> + %"struct.std::ios_base::_Callback_list" = type { %"struct.std::ios_base::_Callback_list"*, void (i32, %"struct.std::ios_base"*, i32)*, i32, i32 } + %"struct.std::ios_base::_Words" = type { i8*, i32 } + %"struct.std::list >" = type { %"struct.std::_List_base >" } + %"struct.std::locale" = type { %"struct.std::locale::_Impl"* } + %"struct.std::locale::_Impl" = type { i32, %"struct.std::locale::facet"**, i32, %"struct.std::locale::facet"**, i8** } + %"struct.std::locale::facet" = type { i32 (...)**, i32 } + %"struct.std::num_get > >" = type { %"struct.std::locale::facet" } + %"struct.std::num_put > >" = type { %"struct.std::locale::facet" } + %"struct.std::numeric_limits" = type <{ i8 }> + %"struct.std::type_info" = type { i32 (...)**, i8* } + at llvm.dbg.subprogram947 = external constant %llvm.dbg.subprogram.type ; <%llvm.dbg.subprogram.type*> [#uses=1] + +declare void @llvm.dbg.func.start({ }*) nounwind + +declare void @llvm.dbg.region.end({ }*) nounwind + +declare void @_ZN9__gnu_cxx13new_allocatorIP5SceneED2Ev(%struct.__false_type*) nounwind + +define void @_ZNSaIP5SceneED1Ev(%struct.__false_type* %this) nounwind { +entry: + %this_addr = alloca %struct.__false_type* ; <%struct.__false_type**> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + call void @llvm.dbg.func.start({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram947 to { }*)) + store %struct.__false_type* %this, %struct.__false_type** %this_addr + %0 = load %struct.__false_type** %this_addr, align 4 ; <%struct.__false_type*> [#uses=1] + call void @_ZN9__gnu_cxx13new_allocatorIP5SceneED2Ev(%struct.__false_type* %0) nounwind + br label %bb + +bb: ; preds = %entry + br label %return + +return: ; preds = %bb + call void @llvm.dbg.region.end({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram947 to { }*)) + ret void +} From isanbard at gmail.com Tue Feb 10 16:15:25 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 10 Feb 2009 22:15:25 -0000 Subject: [llvm-commits] [llvm] r64243 - in /llvm/branches/Apple/Dib: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/maskmovdqu.ll Message-ID: <200902102215.n1AMFPvO024438@zion.cs.uiuc.edu> Author: void Date: Tue Feb 10 16:15:25 2009 New Revision: 64243 URL: http://llvm.org/viewvc/llvm-project?rev=64243&view=rev Log: Pull r64240 into Dib: Handle llvm.x86.sse2.maskmov.dqu in 64-bit. Added: llvm/branches/Apple/Dib/test/CodeGen/X86/maskmovdqu.ll Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86InstrSSE.td Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86InstrSSE.td?rev=64243&r1=64242&r2=64243&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/branches/Apple/Dib/lib/Target/X86/X86InstrSSE.td Tue Feb 10 16:15:25 2009 @@ -2231,6 +2231,11 @@ "maskmovdqu\t{$mask, $src|$src, $mask}", [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>; +let Uses = [RDI] in +def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask), + "maskmovdqu\t{$mask, $src|$src, $mask}", + [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>; + // Non-temporal stores def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), "movntpd\t{$src, $dst|$dst, $src}", Added: llvm/branches/Apple/Dib/test/CodeGen/X86/maskmovdqu.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/maskmovdqu.ll?rev=64243&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/X86/maskmovdqu.ll (added) +++ llvm/branches/Apple/Dib/test/CodeGen/X86/maskmovdqu.ll Tue Feb 10 16:15:25 2009 @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep -i EDI +; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse2 | grep -i RDI +; rdar://6573467 + +define void @test(<16 x i8> %a, <16 x i8> %b, i32 %dummy, i8* %c) nounwind { +entry: + tail call void @llvm.x86.sse2.maskmov.dqu( <16 x i8> %a, <16 x i8> %b, i8* %c ) + ret void +} + +declare void @llvm.x86.sse2.maskmov.dqu(<16 x i8>, <16 x i8>, i8*) nounwind From isanbard at gmail.com Tue Feb 10 16:24:31 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 10 Feb 2009 22:24:31 -0000 Subject: [llvm-commits] [llvm] r64246 - in /llvm/branches/Apple/Dib: lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/dbginfo.ll Message-ID: <200902102224.n1AMOVlT024771@zion.cs.uiuc.edu> Author: void Date: Tue Feb 10 16:24:31 2009 New Revision: 64246 URL: http://llvm.org/viewvc/llvm-project?rev=64246&view=rev Log: Pulled r64242 into Dib: Ignore dbg intrinsic while folding unconditional branch. Added: llvm/branches/Apple/Dib/test/Transforms/SimplifyCFG/dbginfo.ll Modified: llvm/branches/Apple/Dib/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/branches/Apple/Dib/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Transforms/Utils/SimplifyCFG.cpp?rev=64246&r1=64245&r2=64246&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/branches/Apple/Dib/lib/Transforms/Utils/SimplifyCFG.cpp Tue Feb 10 16:24:31 2009 @@ -1339,7 +1339,8 @@ if (!isa(BBI)) break; } - if (isa(BBI) || &*BBI == Term) + + if (isa(BBI) || &*BBI == Term || isa(BBI)) return true; return false; } Added: llvm/branches/Apple/Dib/test/Transforms/SimplifyCFG/dbginfo.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/Transforms/SimplifyCFG/dbginfo.ll?rev=64246&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/Transforms/SimplifyCFG/dbginfo.ll (added) +++ llvm/branches/Apple/Dib/test/Transforms/SimplifyCFG/dbginfo.ll Tue Feb 10 16:24:31 2009 @@ -0,0 +1,70 @@ +; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | grep region | count 1 + %llvm.dbg.anchor.type = type { i32, i32 } + %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 } + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } + %llvm.dbg.composite.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, { }* } + %llvm.dbg.derivedtype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }* } + %llvm.dbg.global_variable.type = type { i32, { }*, { }*, i8*, i8*, i8*, { }*, i32, { }*, i1, i1, { }* } + %llvm.dbg.subprogram.type = type { i32, { }*, { }*, i8*, i8*, i8*, { }*, i32, { }*, i1, i1 } + %llvm.dbg.subrange.type = type { i32, i64, i64 } + %struct.Group = type { %struct.Scene, %struct.Sphere, %"struct.std::list >" } + %struct.Ray = type { %struct.Vec, %struct.Vec } + %struct.Scene = type { i32 (...)** } + %struct.Sphere = type { %struct.Scene, %struct.Vec, double } + %struct.Vec = type { double, double, double } + %struct.__class_type_info_pseudo = type { %struct.__type_info_pseudo } + %struct.__false_type = type <{ i8 }> + %"struct.__gnu_cxx::new_allocator" = type <{ i8 }> + %"struct.__gnu_cxx::new_allocator >" = type <{ i8 }> + %struct.__si_class_type_info_pseudo = type { %struct.__type_info_pseudo, %"struct.std::type_info"* } + %struct.__type_info_pseudo = type { i8*, i8* } + %"struct.std::Hit" = type { double, %struct.Vec } + %"struct.std::_List_base >" = type { %"struct.std::_List_base >::_List_impl" } + %"struct.std::_List_base >::_List_impl" = type { %"struct.std::_List_node_base" } + %"struct.std::_List_const_iterator" = type { %"struct.std::_List_node_base"* } + %"struct.std::_List_iterator" = type { %"struct.std::_List_node_base"* } + %"struct.std::_List_node" = type { %"struct.std::_List_node_base", %struct.Scene* } + %"struct.std::_List_node_base" = type { %"struct.std::_List_node_base"*, %"struct.std::_List_node_base"* } + %"struct.std::allocator" = type <{ i8 }> + %"struct.std::allocator >" = type <{ i8 }> + %"struct.std::basic_ios >" = type { %"struct.std::ios_base", %"struct.std::basic_ostream >"*, i8, i8, %"struct.std::basic_streambuf >"*, %"struct.std::ctype"*, %"struct.std::num_get > >"*, %"struct.std::num_get > >"* } + %"struct.std::basic_ostream >" = type { i32 (...)**, %"struct.std::basic_ios >" } + %"struct.std::basic_streambuf >" = type { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, %"struct.std::locale" } + %"struct.std::ctype" = type { %"struct.std::locale::facet", i32*, i8, i32*, i32*, i32*, i8, [256 x i8], [256 x i8], i8 } + %"struct.std::ios_base" = type { i32 (...)**, i32, i32, i32, i32, i32, %"struct.std::ios_base::_Callback_list"*, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, %"struct.std::ios_base::_Words"*, %"struct.std::locale" } + %"struct.std::ios_base::Init" = type <{ i8 }> + %"struct.std::ios_base::_Callback_list" = type { %"struct.std::ios_base::_Callback_list"*, void (i32, %"struct.std::ios_base"*, i32)*, i32, i32 } + %"struct.std::ios_base::_Words" = type { i8*, i32 } + %"struct.std::list >" = type { %"struct.std::_List_base >" } + %"struct.std::locale" = type { %"struct.std::locale::_Impl"* } + %"struct.std::locale::_Impl" = type { i32, %"struct.std::locale::facet"**, i32, %"struct.std::locale::facet"**, i8** } + %"struct.std::locale::facet" = type { i32 (...)**, i32 } + %"struct.std::num_get > >" = type { %"struct.std::locale::facet" } + %"struct.std::num_put > >" = type { %"struct.std::locale::facet" } + %"struct.std::numeric_limits" = type <{ i8 }> + %"struct.std::type_info" = type { i32 (...)**, i8* } + at llvm.dbg.subprogram947 = external constant %llvm.dbg.subprogram.type ; <%llvm.dbg.subprogram.type*> [#uses=1] + +declare void @llvm.dbg.func.start({ }*) nounwind + +declare void @llvm.dbg.region.end({ }*) nounwind + +declare void @_ZN9__gnu_cxx13new_allocatorIP5SceneED2Ev(%struct.__false_type*) nounwind + +define void @_ZNSaIP5SceneED1Ev(%struct.__false_type* %this) nounwind { +entry: + %this_addr = alloca %struct.__false_type* ; <%struct.__false_type**> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + call void @llvm.dbg.func.start({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram947 to { }*)) + store %struct.__false_type* %this, %struct.__false_type** %this_addr + %0 = load %struct.__false_type** %this_addr, align 4 ; <%struct.__false_type*> [#uses=1] + call void @_ZN9__gnu_cxx13new_allocatorIP5SceneED2Ev(%struct.__false_type* %0) nounwind + br label %bb + +bb: ; preds = %entry + br label %return + +return: ; preds = %bb + call void @llvm.dbg.region.end({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram947 to { }*)) + ret void +} From daniel at zuster.org Tue Feb 10 16:51:30 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 10 Feb 2009 22:51:30 -0000 Subject: [llvm-commits] [test-suite] r64253 - in /test-suite/trunk: MultiSource/Benchmarks/MiBench/network-dijkstra/dijkstra.c SingleSource/Benchmarks/Misc/himenobmtxpa.c Message-ID: <200902102251.n1AMpUQo025751@zion.cs.uiuc.edu> Author: ddunbar Date: Tue Feb 10 16:51:30 2009 New Revision: 64253 URL: http://llvm.org/viewvc/llvm-project?rev=64253&view=rev Log: Include as needed. Modified: test-suite/trunk/MultiSource/Benchmarks/MiBench/network-dijkstra/dijkstra.c test-suite/trunk/SingleSource/Benchmarks/Misc/himenobmtxpa.c Modified: test-suite/trunk/MultiSource/Benchmarks/MiBench/network-dijkstra/dijkstra.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/MiBench/network-dijkstra/dijkstra.c?rev=64253&r1=64252&r2=64253&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Benchmarks/MiBench/network-dijkstra/dijkstra.c (original) +++ test-suite/trunk/MultiSource/Benchmarks/MiBench/network-dijkstra/dijkstra.c Tue Feb 10 16:51:30 2009 @@ -1,4 +1,5 @@ #include +#include #define NUM_NODES 100 #define NONE 9999 Modified: test-suite/trunk/SingleSource/Benchmarks/Misc/himenobmtxpa.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Misc/himenobmtxpa.c?rev=64253&r1=64252&r2=64253&view=diff ============================================================================== --- test-suite/trunk/SingleSource/Benchmarks/Misc/himenobmtxpa.c (original) +++ test-suite/trunk/SingleSource/Benchmarks/Misc/himenobmtxpa.c Tue Feb 10 16:51:30 2009 @@ -37,6 +37,7 @@ ********************************************************************/ #include +#include #include #define MR(mt,n,r,c,d) mt->m[(n) * mt->mrows * mt->mcols * mt->mdeps + (r) * mt->mcols* mt->mdeps + (c) * mt->mdeps + (d)] From gohman at apple.com Tue Feb 10 17:27:53 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 10 Feb 2009 23:27:53 -0000 Subject: [llvm-commits] [llvm] r64254 - in /llvm/trunk: include/llvm/CodeGen/ScheduleDAG.h lib/CodeGen/PostRASchedulerList.cpp lib/CodeGen/ScheduleDAG.cpp lib/CodeGen/ScheduleDAGInstrs.cpp lib/CodeGen/ScheduleDAGInstrs.h lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Message-ID: <200902102327.n1ANRsHQ027057@zion.cs.uiuc.edu> Author: djg Date: Tue Feb 10 17:27:53 2009 New Revision: 64254 URL: http://llvm.org/viewvc/llvm-project?rev=64254&view=rev Log: Factor out more code for computing register live-range informationfor scheduling, and generalize is so that preserves state across scheduling regions. This fixes incorrect live-range information around terminators and labels, which are effective region boundaries. In place of looking for terminators to anchor inter-block dependencies, introduce special entry and exit scheduling units for this purpose. Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp llvm/trunk/lib/CodeGen/ScheduleDAG.cpp llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=64254&r1=64253&r2=64254&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Tue Feb 10 17:27:53 2009 @@ -282,6 +282,16 @@ isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), CopyDstRC(NULL), CopySrcRC(NULL) {} + /// SUnit - Construct a placeholder SUnit. + SUnit() + : Node(0), Instr(0), OrigNode(0), NodeNum(~0u), NodeQueueId(0), + Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), + isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), + isPending(false), isAvailable(false), isScheduled(false), + isScheduleHigh(false), isCloned(false), + isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), + CopyDstRC(NULL), CopySrcRC(NULL) {} + /// setNode - Assign the representative SDNode for this SUnit. /// This may be used during pre-regalloc scheduling. void setNode(SDNode *N) { @@ -430,6 +440,8 @@ std::vector Sequence; // The schedule. Null SUnit*'s // represent noop instructions. std::vector SUnits; // The scheduling units. + SUnit EntrySU; // Special node for the region entry. + SUnit ExitSU; // Special node for the region exit. explicit ScheduleDAG(MachineFunction &mf); @@ -446,6 +458,9 @@ MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End); + /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock + /// according to the order specified in Sequence. + /// virtual MachineBasicBlock *EmitSchedule() = 0; void dumpSchedule() const; Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=64254&r1=64253&r2=64254&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original) +++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Tue Feb 10 17:27:53 2009 @@ -94,6 +94,25 @@ /// HazardRec - The hazard recognizer to use. ScheduleHazardRecognizer *HazardRec; + /// Classes - For live regs that are only used in one register class in a + /// live range, the register class. If the register is not live, the + /// corresponding value is null. If the register is live but used in + /// multiple register classes, the corresponding value is -1 casted to a + /// pointer. + const TargetRegisterClass * + Classes[TargetRegisterInfo::FirstVirtualRegister]; + + /// RegRegs - Map registers to all their references within a live range. + std::multimap RegRefs; + + /// The index of the most recent kill (proceding bottom-up), or ~0u if + /// the register is not live. + unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister]; + + /// The index of the most recent complete def (proceding bottom up), or ~0u + /// if the register is live. + unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister]; + public: SchedulePostRATDList(MachineFunction &MF, const MachineLoopInfo &MLI, @@ -107,10 +126,29 @@ delete HazardRec; } + /// StartBlock - Initialize register live-range state for scheduling in + /// this block. + /// + void StartBlock(MachineBasicBlock *BB); + + /// Schedule - Schedule the instruction range using list scheduling. + /// void Schedule(); + /// Observe - Update liveness information to account for the current + /// instruction, which will not be scheduled. + /// + void Observe(MachineInstr *MI); + + /// FinishBlock - Clean up register live-range state. + /// + void FinishBlock(); + private: + void PrescanInstruction(MachineInstr *MI); + void ScanInstruction(MachineInstr *MI, unsigned Count); void ReleaseSucc(SUnit *SU, SDep *SuccEdge); + void ReleaseSuccessors(SUnit *SU); void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle); void ListScheduleTopDown(); bool BreakAntiDependencies(); @@ -173,6 +211,19 @@ }; } +/// isSchedulingBoundary - Test if the given instruction should be +/// considered a scheduling boundary. This primarily includes labels +/// and terminators. +/// +static bool isSchedulingBoundary(const MachineInstr *MI, + const MachineFunction &MF) { + // Terminators and labels can't be scheduled around. + if (MI->getDesc().isTerminator() || MI->isLabel()) + return true; + + return false; +} + bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { DOUT << "PostRAScheduler\n"; @@ -187,26 +238,111 @@ // Loop over all of the basic blocks for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); MBB != MBBe; ++MBB) { + // Initialize register live-range state for scheduling in this block. + Scheduler.StartBlock(MBB); + // Schedule each sequence of instructions not interrupted by a label // or anything else that effectively needs to shut down scheduling. - MachineBasicBlock::iterator Current = MBB->end(), Top = MBB->begin(); - for (MachineBasicBlock::iterator I = Current; I != Top; ) { - MachineInstr *MI = --I; - if (MI->getDesc().isTerminator() || MI->isLabel()) { - Scheduler.Run(0, MBB, next(I), Current); - Scheduler.EmitSchedule(); - Current = I; + MachineBasicBlock::iterator Current = MBB->end(); + for (MachineBasicBlock::iterator I = Current; I != MBB->begin(); ) { + MachineInstr *MI = prior(I); + if (isSchedulingBoundary(MI, Fn)) { + if (I != Current) { + Scheduler.Run(0, MBB, I, Current); + Scheduler.EmitSchedule(); + } + Scheduler.Observe(MI); + Current = MI; } + I = MI; } - - Scheduler.Run(0, MBB, Top, Current); + Scheduler.Run(0, MBB, MBB->begin(), Current); Scheduler.EmitSchedule(); + + // Clean up register live-range state. + Scheduler.FinishBlock(); } return true; } -/// Schedule - Schedule the DAG using list scheduling. +/// StartBlock - Initialize register live-range state for scheduling in +/// this block. +/// +void SchedulePostRATDList::StartBlock(MachineBasicBlock *BB) { + // Call the superclass. + ScheduleDAGInstrs::StartBlock(BB); + + // Clear out the register class data. + std::fill(Classes, array_endof(Classes), + static_cast(0)); + + // Initialize the indices to indicate that no registers are live. + std::fill(KillIndices, array_endof(KillIndices), ~0u); + std::fill(DefIndices, array_endof(DefIndices), BB->size()); + + // Determine the live-out physregs for this block. + if (!BB->empty() && BB->back().getDesc().isReturn()) + // In a return block, examine the function live-out regs. + for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(), + E = MRI.liveout_end(); I != E; ++I) { + unsigned Reg = *I; + Classes[Reg] = reinterpret_cast(-1); + KillIndices[Reg] = BB->size(); + DefIndices[Reg] = ~0u; + // Repeat, for all aliases. + for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { + unsigned AliasReg = *Alias; + Classes[AliasReg] = reinterpret_cast(-1); + KillIndices[AliasReg] = BB->size(); + DefIndices[AliasReg] = ~0u; + } + } + else + // In a non-return block, examine the live-in regs of all successors. + for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), + SE = BB->succ_end(); SI != SE; ++SI) + for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(), + E = (*SI)->livein_end(); I != E; ++I) { + unsigned Reg = *I; + Classes[Reg] = reinterpret_cast(-1); + KillIndices[Reg] = BB->size(); + DefIndices[Reg] = ~0u; + // Repeat, for all aliases. + for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { + unsigned AliasReg = *Alias; + Classes[AliasReg] = reinterpret_cast(-1); + KillIndices[AliasReg] = BB->size(); + DefIndices[AliasReg] = ~0u; + } + } + + // Consider callee-saved registers as live-out, since we're running after + // prologue/epilogue insertion so there's no way to add additional + // saved registers. + // + // TODO: If the callee saves and restores these, then we can potentially + // use them between the save and the restore. To do that, we could scan + // the exit blocks to see which of these registers are defined. + // Alternatively, callee-saved registers that aren't saved and restored + // could be marked live-in in every block. + for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) { + unsigned Reg = *I; + Classes[Reg] = reinterpret_cast(-1); + KillIndices[Reg] = BB->size(); + DefIndices[Reg] = ~0u; + // Repeat, for all aliases. + for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { + unsigned AliasReg = *Alias; + Classes[AliasReg] = reinterpret_cast(-1); + KillIndices[AliasReg] = BB->size(); + DefIndices[AliasReg] = ~0u; + } + } +} + +/// Schedule - Schedule the instruction range using list scheduling. +/// void SchedulePostRATDList::Schedule() { DOUT << "********** List Scheduling **********\n"; @@ -222,6 +358,8 @@ // that register, and add new anti-dependence and output-dependence // edges based on the next live range of the register. SUnits.clear(); + EntrySU = SUnit(); + ExitSU = SUnit(); BuildSchedGraph(); } } @@ -233,6 +371,23 @@ AvailableQueue.releaseState(); } +/// Observe - Update liveness information to account for the current +/// instruction, which will not be scheduled. +/// +void SchedulePostRATDList::Observe(MachineInstr *MI) { + PrescanInstruction(MI); + ScanInstruction(MI, 0); +} + +/// FinishBlock - Clean up register live-range state. +/// +void SchedulePostRATDList::FinishBlock() { + RegRefs.clear(); + + // Call the superclass. + ScheduleDAGInstrs::FinishBlock(); +} + /// getInstrOperandRegClass - Return register class of the operand of an /// instruction of the specified TargetInstrDesc. static const TargetRegisterClass* @@ -267,6 +422,111 @@ return Next; } +void SchedulePostRATDList::PrescanInstruction(MachineInstr *MI) { + // Scan the register operands for this instruction and update + // Classes and RegRefs. + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI->getOperand(i); + if (!MO.isReg()) continue; + unsigned Reg = MO.getReg(); + if (Reg == 0) continue; + const TargetRegisterClass *NewRC = + getInstrOperandRegClass(TRI, MI->getDesc(), i); + + // For now, only allow the register to be changed if its register + // class is consistent across all uses. + if (!Classes[Reg] && NewRC) + Classes[Reg] = NewRC; + else if (!NewRC || Classes[Reg] != NewRC) + Classes[Reg] = reinterpret_cast(-1); + + // Now check for aliases. + for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { + // If an alias of the reg is used during the live range, give up. + // Note that this allows us to skip checking if AntiDepReg + // overlaps with any of the aliases, among other things. + unsigned AliasReg = *Alias; + if (Classes[AliasReg]) { + Classes[AliasReg] = reinterpret_cast(-1); + Classes[Reg] = reinterpret_cast(-1); + } + } + + // If we're still willing to consider this register, note the reference. + if (Classes[Reg] != reinterpret_cast(-1)) + RegRefs.insert(std::make_pair(Reg, &MO)); + } +} + +void SchedulePostRATDList::ScanInstruction(MachineInstr *MI, + unsigned Count) { + // Update liveness. + // Proceding upwards, registers that are defed but not used in this + // instruction are now dead. + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI->getOperand(i); + if (!MO.isReg()) continue; + unsigned Reg = MO.getReg(); + if (Reg == 0) continue; + if (!MO.isDef()) continue; + // Ignore two-addr defs. + if (MI->isRegReDefinedByTwoAddr(i)) continue; + + DefIndices[Reg] = Count; + KillIndices[Reg] = ~0u; + Classes[Reg] = 0; + RegRefs.erase(Reg); + // Repeat, for all subregs. + for (const unsigned *Subreg = TRI->getSubRegisters(Reg); + *Subreg; ++Subreg) { + unsigned SubregReg = *Subreg; + DefIndices[SubregReg] = Count; + KillIndices[SubregReg] = ~0u; + Classes[SubregReg] = 0; + RegRefs.erase(SubregReg); + } + // Conservatively mark super-registers as unusable. + for (const unsigned *Super = TRI->getSuperRegisters(Reg); + *Super; ++Super) { + unsigned SuperReg = *Super; + Classes[SuperReg] = reinterpret_cast(-1); + } + } + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI->getOperand(i); + if (!MO.isReg()) continue; + unsigned Reg = MO.getReg(); + if (Reg == 0) continue; + if (!MO.isUse()) continue; + + const TargetRegisterClass *NewRC = + getInstrOperandRegClass(TRI, MI->getDesc(), i); + + // For now, only allow the register to be changed if its register + // class is consistent across all uses. + if (!Classes[Reg] && NewRC) + Classes[Reg] = NewRC; + else if (!NewRC || Classes[Reg] != NewRC) + Classes[Reg] = reinterpret_cast(-1); + + RegRefs.insert(std::make_pair(Reg, &MO)); + + // It wasn't previously live but now it is, this is a kill. + if (KillIndices[Reg] == ~0u) { + KillIndices[Reg] = Count; + DefIndices[Reg] = ~0u; + } + // Repeat, for all aliases. + for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { + unsigned AliasReg = *Alias; + if (KillIndices[AliasReg] == ~0u) { + KillIndices[AliasReg] = Count; + DefIndices[AliasReg] = ~0u; + } + } + } +} + /// BreakAntiDependencies - Identifiy anti-dependencies along the critical path /// of the ScheduleDAG and break them by renaming registers. /// @@ -291,84 +551,6 @@ SUnit *CriticalPathSU = Max; MachineInstr *CriticalPathMI = CriticalPathSU->getInstr(); - // For live regs that are only used in one register class in a live range, - // the register class. If the register is not live, the corresponding value - // is null. If the register is live but used in multiple register classes, - // the corresponding value is -1 casted to a pointer. - const TargetRegisterClass * - Classes[TargetRegisterInfo::FirstVirtualRegister] = {}; - - // Map registers to all their references within a live range. - std::multimap RegRefs; - - // The index of the most recent kill (proceding bottom-up), or ~0u if - // the register is not live. - unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister]; - std::fill(KillIndices, array_endof(KillIndices), ~0u); - // The index of the most recent complete def (proceding bottom up), or ~0u if - // the register is live. - unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister]; - std::fill(DefIndices, array_endof(DefIndices), BB->size()); - - // Determine the live-out physregs for this block. - if (BB->back().getDesc().isReturn()) - // In a return block, examine the function live-out regs. - for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(), - E = MRI.liveout_end(); I != E; ++I) { - unsigned Reg = *I; - Classes[Reg] = reinterpret_cast(-1); - KillIndices[Reg] = BB->size(); - DefIndices[Reg] = ~0u; - // Repeat, for all aliases. - for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { - unsigned AliasReg = *Alias; - Classes[AliasReg] = reinterpret_cast(-1); - KillIndices[AliasReg] = BB->size(); - DefIndices[AliasReg] = ~0u; - } - } - else - // In a non-return block, examine the live-in regs of all successors. - for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), - SE = BB->succ_end(); SI != SE; ++SI) - for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(), - E = (*SI)->livein_end(); I != E; ++I) { - unsigned Reg = *I; - Classes[Reg] = reinterpret_cast(-1); - KillIndices[Reg] = BB->size(); - DefIndices[Reg] = ~0u; - // Repeat, for all aliases. - for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { - unsigned AliasReg = *Alias; - Classes[AliasReg] = reinterpret_cast(-1); - KillIndices[AliasReg] = BB->size(); - DefIndices[AliasReg] = ~0u; - } - } - - // Consider callee-saved registers as live-out, since we're running after - // prologue/epilogue insertion so there's no way to add additional - // saved registers. - // - // TODO: If the callee saves and restores these, then we can potentially - // use them between the save and the restore. To do that, we could scan - // the exit blocks to see which of these registers are defined. - // Alternatively, callee-saved registers that aren't saved and restored - // could be marked live-in in every block. - for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) { - unsigned Reg = *I; - Classes[Reg] = reinterpret_cast(-1); - KillIndices[Reg] = BB->size(); - DefIndices[Reg] = ~0u; - // Repeat, for all aliases. - for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { - unsigned AliasReg = *Alias; - Classes[AliasReg] = reinterpret_cast(-1); - KillIndices[AliasReg] = BB->size(); - DefIndices[AliasReg] = ~0u; - } - } - // Consider this pattern: // A = ... // ... = A @@ -481,43 +663,19 @@ } } - // Scan the register operands for this instruction and update - // Classes and RegRefs. + PrescanInstruction(MI); + + // If this instruction has a use of AntiDepReg, breaking it + // is invalid. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); if (!MO.isReg()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) continue; - const TargetRegisterClass *NewRC = - getInstrOperandRegClass(TRI, MI->getDesc(), i); - - // If this instruction has a use of AntiDepReg, breaking it - // is invalid. - if (MO.isUse() && AntiDepReg == Reg) + if (MO.isUse() && AntiDepReg == Reg) { AntiDepReg = 0; - - // For now, only allow the register to be changed if its register - // class is consistent across all uses. - if (!Classes[Reg] && NewRC) - Classes[Reg] = NewRC; - else if (!NewRC || Classes[Reg] != NewRC) - Classes[Reg] = reinterpret_cast(-1); - - // Now check for aliases. - for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { - // If an alias of the reg is used during the live range, give up. - // Note that this allows us to skip checking if AntiDepReg - // overlaps with any of the aliases, among other things. - unsigned AliasReg = *Alias; - if (Classes[AliasReg]) { - Classes[AliasReg] = reinterpret_cast(-1); - Classes[Reg] = reinterpret_cast(-1); - } + break; } - - // If we're still willing to consider this register, note the reference. - if (Classes[Reg] != reinterpret_cast(-1)) - RegRefs.insert(std::make_pair(Reg, &MO)); } // Determine AntiDepReg's register class, if it is live and is @@ -584,71 +742,7 @@ } } - // Update liveness. - // Proceding upwards, registers that are defed but not used in this - // instruction are now dead. - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); - if (!MO.isReg()) continue; - unsigned Reg = MO.getReg(); - if (Reg == 0) continue; - if (!MO.isDef()) continue; - // Ignore two-addr defs. - if (MI->isRegReDefinedByTwoAddr(i)) continue; - - DefIndices[Reg] = Count; - KillIndices[Reg] = ~0u; - Classes[Reg] = 0; - RegRefs.erase(Reg); - // Repeat, for all subregs. - for (const unsigned *Subreg = TRI->getSubRegisters(Reg); - *Subreg; ++Subreg) { - unsigned SubregReg = *Subreg; - DefIndices[SubregReg] = Count; - KillIndices[SubregReg] = ~0u; - Classes[SubregReg] = 0; - RegRefs.erase(SubregReg); - } - // Conservatively mark super-registers as unusable. - for (const unsigned *Super = TRI->getSuperRegisters(Reg); - *Super; ++Super) { - unsigned SuperReg = *Super; - Classes[SuperReg] = reinterpret_cast(-1); - } - } - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); - if (!MO.isReg()) continue; - unsigned Reg = MO.getReg(); - if (Reg == 0) continue; - if (!MO.isUse()) continue; - - const TargetRegisterClass *NewRC = - getInstrOperandRegClass(TRI, MI->getDesc(), i); - - // For now, only allow the register to be changed if its register - // class is consistent across all uses. - if (!Classes[Reg] && NewRC) - Classes[Reg] = NewRC; - else if (!NewRC || Classes[Reg] != NewRC) - Classes[Reg] = reinterpret_cast(-1); - - RegRefs.insert(std::make_pair(Reg, &MO)); - - // It wasn't previously live but now it is, this is a kill. - if (KillIndices[Reg] == ~0u) { - KillIndices[Reg] = Count; - DefIndices[Reg] = ~0u; - } - // Repeat, for all aliases. - for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { - unsigned AliasReg = *Alias; - if (KillIndices[AliasReg] == ~0u) { - KillIndices[AliasReg] = Count; - DefIndices[AliasReg] = ~0u; - } - } - } + ScanInstruction(MI, Count); } assert(Count == ~0u && "Count mismatch!"); @@ -679,9 +773,17 @@ // their latencies. SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency()); - if (SuccSU->NumPredsLeft == 0) { + // If all the node's predecessors are scheduled, this node is ready + // to be scheduled. Ignore the special ExitSU node. + if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) PendingQueue.push_back(SuccSU); - } +} + +/// ReleaseSuccessors - Call ReleaseSucc on each of SU's successors. +void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) { + for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); + I != E; ++I) + ReleaseSucc(SU, &*I); } /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending @@ -695,11 +797,7 @@ assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!"); SU->setDepthToAtLeast(CurCycle); - // Top down: release successors. - for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); - I != E; ++I) - ReleaseSucc(SU, &*I); - + ReleaseSuccessors(SU); SU->isScheduled = true; AvailableQueue.ScheduledNode(SU); } @@ -709,6 +807,9 @@ void SchedulePostRATDList::ListScheduleTopDown() { unsigned CurCycle = 0; + // Release any successors of the special Entry node. + ReleaseSuccessors(&EntrySU); + // All leaves to Available queue. for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { // It is available if it has no predecessors. @@ -717,7 +818,7 @@ SUnits[i].isAvailable = true; } } - + // While Available queue is not empty, grab the node with the highest // priority. If it is not ready put it back. Schedule the node. std::vector NotReady; Modified: llvm/trunk/lib/CodeGen/ScheduleDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAG.cpp?rev=64254&r1=64253&r2=64254&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAG.cpp Tue Feb 10 17:27:53 2009 @@ -28,7 +28,8 @@ TRI(TM.getRegisterInfo()), TLI(TM.getTargetLowering()), MF(mf), MRI(mf.getRegInfo()), - ConstPool(MF.getConstantPool()) { + ConstPool(MF.getConstantPool()), + EntrySU(), ExitSU() { } ScheduleDAG::~ScheduleDAG() {} @@ -58,6 +59,8 @@ BB = bb; Begin = begin; End = end; + EntrySU = SUnit(); + ExitSU = SUnit(); Schedule(); Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=64254&r1=64253&r2=64254&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Tue Feb 10 17:27:53 2009 @@ -15,86 +15,22 @@ #define DEBUG_TYPE "sched-instrs" #include "ScheduleDAGInstrs.h" #include "llvm/Analysis/AliasAnalysis.h" -#include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetSubtarget.h" -#include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/SmallSet.h" -#include using namespace llvm; -namespace { - class VISIBILITY_HIDDEN LoopDependencies { - const MachineLoopInfo &MLI; - const MachineDominatorTree &MDT; - - public: - typedef std::map > - LoopDeps; - LoopDeps Deps; - - LoopDependencies(const MachineLoopInfo &mli, - const MachineDominatorTree &mdt) : - MLI(mli), MDT(mdt) {} - - void VisitLoop(const MachineLoop *Loop) { - Deps.clear(); - MachineBasicBlock *Header = Loop->getHeader(); - SmallSet LoopLiveIns; - for (MachineBasicBlock::livein_iterator LI = Header->livein_begin(), - LE = Header->livein_end(); LI != LE; ++LI) - LoopLiveIns.insert(*LI); - - const MachineDomTreeNode *Node = MDT.getNode(Header); - const MachineBasicBlock *MBB = Node->getBlock(); - assert(Loop->contains(MBB) && - "Loop does not contain header!"); - VisitRegion(Node, MBB, Loop, LoopLiveIns); - } - - private: - void VisitRegion(const MachineDomTreeNode *Node, - const MachineBasicBlock *MBB, - const MachineLoop *Loop, - const SmallSet &LoopLiveIns) { - unsigned Count = 0; - for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); - I != E; ++I, ++Count) { - const MachineInstr *MI = I; - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - const MachineOperand &MO = MI->getOperand(i); - if (!MO.isReg() || !MO.isUse()) - continue; - unsigned MOReg = MO.getReg(); - if (LoopLiveIns.count(MOReg)) - Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count))); - } - } - - const std::vector &Children = Node->getChildren(); - for (std::vector::const_iterator I = - Children.begin(), E = Children.end(); I != E; ++I) { - const MachineDomTreeNode *ChildNode = *I; - MachineBasicBlock *ChildBlock = ChildNode->getBlock(); - if (Loop->contains(ChildBlock)) - VisitRegion(ChildNode, ChildBlock, Loop, LoopLiveIns); - } - } - }; -} - ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo &mli, const MachineDominatorTree &mdt) - : ScheduleDAG(mf), MLI(mli), MDT(mdt) {} + : ScheduleDAG(mf), MLI(mli), MDT(mdt), LoopRegs(MLI, MDT) {} /// getOpcode - If this is an Instruction or a ConstantExpr, return the /// opcode value. Otherwise return UserOp1. @@ -172,7 +108,20 @@ return V; } +void ScheduleDAGInstrs::StartBlock(MachineBasicBlock *BB) { + if (MachineLoop *ML = MLI.getLoopFor(BB)) + if (BB == ML->getLoopLatch()) { + MachineBasicBlock *Header = ML->getHeader(); + for (MachineBasicBlock::livein_iterator I = Header->livein_begin(), + E = Header->livein_end(); I != E; ++I) + LoopLiveInRegs.insert(*I); + LoopRegs.VisitLoop(ML); + } +} + void ScheduleDAGInstrs::BuildSchedGraph() { + // We'll be allocating one SUnit for each instruction, plus one for + // the region exit node. SUnits.reserve(BB->size()); // We build scheduling units by walking a block's instruction list from bottom @@ -189,30 +138,6 @@ std::map MemDefs; std::map > MemUses; - // If we have an SUnit which is representing a terminator instruction, we - // can use it as a place-holder successor for inter-block dependencies. - SUnit *Terminator = 0; - - // Terminators can perform control transfers, we we need to make sure that - // all the work of the block is done before the terminator. Labels can - // mark points of interest for various types of meta-data (eg. EH data), - // and we need to make sure nothing is scheduled around them. - SUnit *SchedulingBarrier = 0; - - LoopDependencies LoopRegs(MLI, MDT); - - // Track which regs are live into a loop, to help guide back-edge-aware - // scheduling. - SmallSet LoopLiveInRegs; - if (MachineLoop *ML = MLI.getLoopFor(BB)) - if (BB == ML->getLoopLatch()) { - MachineBasicBlock *Header = ML->getHeader(); - for (MachineBasicBlock::livein_iterator I = Header->livein_begin(), - E = Header->livein_end(); I != E; ++I) - LoopLiveInRegs.insert(*I); - LoopRegs.VisitLoop(ML); - } - // Check to see if the scheduler cares about latencies. bool UnitLatencies = ForceUnitLatencies(); @@ -220,10 +145,14 @@ unsigned SpecialAddressLatency = TM.getSubtarget().getSpecialAddressLatency(); + // Walk the list of instructions, from bottom moving up. for (MachineBasicBlock::iterator MII = End, MIE = Begin; MII != MIE; --MII) { MachineInstr *MI = prior(MII); const TargetInstrDesc &TID = MI->getDesc(); + assert(!TID.isTerminator() && !MI->isLabel() && + "Cannot schedule terminators or labels!"); + // Create the SUnit for this MI. SUnit *SU = NewSUnit(MI); // Assign the Latency field of SU using target-provided information. @@ -298,8 +227,7 @@ // If a def is going to wrap back around to the top of the loop, // backschedule it. - // TODO: Blocks in loops without terminators can benefit too. - if (!UnitLatencies && Terminator && DefList.empty()) { + if (!UnitLatencies && DefList.empty()) { LoopDependencies::LoopDeps::iterator I = LoopRegs.Deps.find(Reg); if (I != LoopRegs.Deps.end()) { const MachineOperand *UseMO = I->second.first; @@ -323,10 +251,10 @@ // scheduling region. Latency -= std::min(Latency, Count); // Add the artifical edge. - Terminator->addPred(SDep(SU, SDep::Order, Latency, - /*Reg=*/0, /*isNormalMemory=*/false, - /*isMustAlias=*/false, - /*isArtificial=*/true)); + ExitSU.addPred(SDep(SU, SDep::Order, Latency, + /*Reg=*/0, /*isNormalMemory=*/false, + /*isMustAlias=*/false, + /*isArtificial=*/true)); } else if (SpecialAddressLatency > 0 && UseTID.OpInfo[UseMOIdx].isLookupPtrRegClass()) { // The entire loop body is within the current scheduling region @@ -355,7 +283,7 @@ // after stack slots are lowered to actual addresses. // TODO: Use an AliasAnalysis and do real alias-analysis queries, and // produce more precise dependence information. - if (TID.isCall() || TID.isTerminator() || TID.hasUnmodeledSideEffects()) { + if (TID.isCall() || TID.hasUnmodeledSideEffects()) { new_chain: // This is the conservative case. Add dependencies on all memory // references. @@ -379,7 +307,7 @@ // See if it is known to just have a single memory reference. MachineInstr *ChainMI = Chain->getInstr(); const TargetInstrDesc &ChainTID = ChainMI->getDesc(); - if (!ChainTID.isCall() && !ChainTID.isTerminator() && + if (!ChainTID.isCall() && !ChainTID.hasUnmodeledSideEffects() && ChainMI->hasOneMemOperand() && !ChainMI->memoperands_begin()->isVolatile() && @@ -452,28 +380,6 @@ PendingLoads.push_back(SU); } } - - // Add chain edges from terminators and labels to ensure that no - // instructions are scheduled past them. - if (SchedulingBarrier && SU->Succs.empty()) - SchedulingBarrier->addPred(SDep(SU, SDep::Order, SU->Latency)); - // If we encounter a mid-block label, we need to go back and add - // dependencies on SUnits we've already processed to prevent the - // label from moving downward. - if (MI->isLabel()) - for (SUnit *I = SU; I != &SUnits[0]; --I) { - SUnit *SuccSU = SU-1; - SuccSU->addPred(SDep(SU, SDep::Order, SU->Latency)); - MachineInstr *SuccMI = SuccSU->getInstr(); - if (SuccMI->getDesc().isTerminator() || SuccMI->isLabel()) - break; - } - // If this instruction obstructs all scheduling, remember it. - if (TID.isTerminator() || MI->isLabel()) - SchedulingBarrier = SU; - // If this instruction is a terminator, remember it. - if (TID.isTerminator()) - Terminator = SU; } for (int i = 0, e = TRI->getNumRegs(); i != e; ++i) { @@ -483,6 +389,10 @@ PendingLoads.clear(); } +void ScheduleDAGInstrs::FinishBlock() { + // Nothing to do. +} + void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) { const InstrItineraryData &InstrItins = TM.getInstrItineraryData(); @@ -505,7 +415,12 @@ std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const { std::string s; raw_string_ostream oss(s); - SU->getInstr()->print(oss); + if (SU == &EntrySU) + oss << ""; + else if (SU == &ExitSU) + oss << ""; + else + SU->getInstr()->print(oss); return oss.str(); } @@ -531,5 +446,10 @@ BB->insert(End, SU->getInstr()); } + // Update the Begin iterator, as the first instruction in the block + // may have been scheduled later. + if (!Sequence.empty()) + Begin = Sequence[0]->getInstr(); + return BB; } Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h?rev=64254&r1=64253&r2=64254&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h Tue Feb 10 17:27:53 2009 @@ -15,14 +15,86 @@ #ifndef SCHEDULEDAGINSTRS_H #define SCHEDULEDAGINSTRS_H +#include "llvm/ADT/SmallSet.h" +#include "llvm/CodeGen/MachineDominators.h" +#include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/ScheduleDAG.h" +#include "llvm/Support/Compiler.h" #include "llvm/Target/TargetRegisterInfo.h" +#include namespace llvm { class MachineLoopInfo; class MachineDominatorTree; - class ScheduleDAGInstrs : public ScheduleDAG { + /// LoopDependencies - This class analyzes loop-oriented register + /// dependencies, which are used to guide scheduling decisions. + /// For example, loop induction variable increments should be + /// scheduled as soon as possible after the variable's last use. + /// + class VISIBILITY_HIDDEN LoopDependencies { + const MachineLoopInfo &MLI; + const MachineDominatorTree &MDT; + + public: + typedef std::map > + LoopDeps; + LoopDeps Deps; + + LoopDependencies(const MachineLoopInfo &mli, + const MachineDominatorTree &mdt) : + MLI(mli), MDT(mdt) {} + + /// VisitLoop - Clear out any previous state and analyze the given loop. + /// + void VisitLoop(const MachineLoop *Loop) { + Deps.clear(); + MachineBasicBlock *Header = Loop->getHeader(); + SmallSet LoopLiveIns; + for (MachineBasicBlock::livein_iterator LI = Header->livein_begin(), + LE = Header->livein_end(); LI != LE; ++LI) + LoopLiveIns.insert(*LI); + + const MachineDomTreeNode *Node = MDT.getNode(Header); + const MachineBasicBlock *MBB = Node->getBlock(); + assert(Loop->contains(MBB) && + "Loop does not contain header!"); + VisitRegion(Node, MBB, Loop, LoopLiveIns); + } + + private: + void VisitRegion(const MachineDomTreeNode *Node, + const MachineBasicBlock *MBB, + const MachineLoop *Loop, + const SmallSet &LoopLiveIns) { + unsigned Count = 0; + for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); + I != E; ++I, ++Count) { + const MachineInstr *MI = I; + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + if (!MO.isReg() || !MO.isUse()) + continue; + unsigned MOReg = MO.getReg(); + if (LoopLiveIns.count(MOReg)) + Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count))); + } + } + + const std::vector &Children = Node->getChildren(); + for (std::vector::const_iterator I = + Children.begin(), E = Children.end(); I != E; ++I) { + const MachineDomTreeNode *ChildNode = *I; + MachineBasicBlock *ChildBlock = ChildNode->getBlock(); + if (Loop->contains(ChildBlock)) + VisitRegion(ChildNode, ChildBlock, Loop, LoopLiveIns); + } + } + }; + + /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of + /// MachineInstrs. + class VISIBILITY_HIDDEN ScheduleDAGInstrs : public ScheduleDAG { const MachineLoopInfo &MLI; const MachineDominatorTree &MDT; @@ -38,6 +110,15 @@ /// to minimize construction/destruction. std::vector PendingLoads; + /// LoopRegs - Track which registers are used for loop-carried dependencies. + /// + LoopDependencies LoopRegs; + + /// LoopLiveInRegs - Track which regs are live into a loop, to help guide + /// back-edge-aware scheduling. + /// + SmallSet LoopLiveInRegs; + public: explicit ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo &mli, @@ -68,11 +149,19 @@ virtual MachineBasicBlock *EmitSchedule(); + /// StartBlock - Prepare to perform scheduling in the given block. + /// + virtual void StartBlock(MachineBasicBlock *BB); + /// Schedule - Order nodes according to selected style, filling /// in the Sequence member. /// virtual void Schedule() = 0; + /// FinishBlock - Clean up after scheduling in the given block. + /// + virtual void FinishBlock(); + virtual void dumpNode(const SUnit *SU) const; virtual std::string getGraphNodeLabel(const SUnit *SU) const; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=64254&r1=64253&r2=64254&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Tue Feb 10 17:27:53 2009 @@ -90,6 +90,7 @@ private: void ReleasePred(SUnit *SU, SDep *PredEdge); + void ReleasePredecessors(SUnit *SU, unsigned CurCycle); void ScheduleNodeBottomUp(SUnit*, unsigned); SUnit *CopyAndMoveSuccessors(SUnit*); void InsertCopiesAndMoveSuccs(SUnit*, unsigned, @@ -142,23 +143,15 @@ } #endif - if (PredSU->NumSuccsLeft == 0) { + // If all the node's successors are scheduled, this node is ready + // to be scheduled. Ignore the special EntrySU node. + if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) { PredSU->isAvailable = true; AvailableQueue.push(PredSU); } } -/// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending -/// count of its predecessors. If a predecessor pending count is zero, add it to -/// the Available queue. -void ScheduleDAGFast::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { - DOUT << "*** Scheduling [" << CurCycle << "]: "; - DEBUG(SU->dump(this)); - - assert(CurCycle >= SU->getHeight() && "Node scheduled below its height!"); - SU->setHeightToAtLeast(CurCycle); - Sequence.push_back(SU); - +void ScheduleDAGFast::ReleasePredecessors(SUnit *SU, unsigned CurCycle) { // Bottom up: release predecessors for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) { @@ -175,6 +168,20 @@ } } } +} + +/// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending +/// count of its predecessors. If a predecessor pending count is zero, add it to +/// the Available queue. +void ScheduleDAGFast::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { + DOUT << "*** Scheduling [" << CurCycle << "]: "; + DEBUG(SU->dump(this)); + + assert(CurCycle >= SU->getHeight() && "Node scheduled below its height!"); + SU->setHeightToAtLeast(CurCycle); + Sequence.push_back(SU); + + ReleasePredecessors(SU, CurCycle); // Release all the implicit physical register defs that are live. for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); @@ -480,6 +487,10 @@ /// schedulers. void ScheduleDAGFast::ListScheduleBottomUp() { unsigned CurCycle = 0; + + // Release any predecessors of the special Exit node. + ReleasePredecessors(&ExitSU, CurCycle); + // Add root to Available queue. if (!SUnits.empty()) { SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()]; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=64254&r1=64253&r2=64254&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Tue Feb 10 17:27:53 2009 @@ -78,6 +78,7 @@ private: void ReleaseSucc(SUnit *SU, const SDep &D); + void ReleaseSuccessors(SUnit *SU); void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle); void ListScheduleTopDown(); }; @@ -118,8 +119,20 @@ SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency()); - if (SuccSU->NumPredsLeft == 0) { + // If all the node's predecessors are scheduled, this node is ready + // to be scheduled. Ignore the special ExitSU node. + if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) PendingQueue.push_back(SuccSU); +} + +void ScheduleDAGList::ReleaseSuccessors(SUnit *SU) { + // Top down: release successors. + for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); + I != E; ++I) { + assert(!I->isAssignedRegDep() && + "The list-td scheduler doesn't yet support physreg dependencies!"); + + ReleaseSucc(SU, *I); } } @@ -134,15 +147,7 @@ assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!"); SU->setDepthToAtLeast(CurCycle); - // Top down: release successors. - for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); - I != E; ++I) { - assert(!I->isAssignedRegDep() && - "The list-td scheduler doesn't yet support physreg dependencies!"); - - ReleaseSucc(SU, *I); - } - + ReleaseSuccessors(SU); SU->isScheduled = true; AvailableQueue->ScheduledNode(SU); } @@ -152,6 +157,9 @@ void ScheduleDAGList::ListScheduleTopDown() { unsigned CurCycle = 0; + // Release any successors of the special Entry node. + ReleaseSuccessors(&EntrySU); + // All leaves to Available queue. for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { // It is available if it has no predecessors. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=64254&r1=64253&r2=64254&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Feb 10 17:27:53 2009 @@ -114,7 +114,9 @@ private: void ReleasePred(SUnit *SU, const SDep *PredEdge); + void ReleasePredecessors(SUnit *SU, unsigned CurCycle); void ReleaseSucc(SUnit *SU, const SDep *SuccEdge); + void ReleaseSuccessors(SUnit *SU); void CapturePred(SDep *PredEdge); void ScheduleNodeBottomUp(SUnit*, unsigned); void ScheduleNodeTopDown(SUnit*, unsigned); @@ -204,23 +206,15 @@ } #endif - if (PredSU->NumSuccsLeft == 0) { + // If all the node's successors are scheduled, this node is ready + // to be scheduled. Ignore the special EntrySU node. + if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) { PredSU->isAvailable = true; AvailableQueue->push(PredSU); } } -/// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending -/// count of its predecessors. If a predecessor pending count is zero, add it to -/// the Available queue. -void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { - DOUT << "*** Scheduling [" << CurCycle << "]: "; - DEBUG(SU->dump(this)); - - assert(CurCycle >= SU->getHeight() && "Node scheduled below its height!"); - SU->setHeightToAtLeast(CurCycle); - Sequence.push_back(SU); - +void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU, unsigned CurCycle) { // Bottom up: release predecessors for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) { @@ -237,6 +231,20 @@ } } } +} + +/// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending +/// count of its predecessors. If a predecessor pending count is zero, add it to +/// the Available queue. +void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { + DOUT << "*** Scheduling [" << CurCycle << "]: "; + DEBUG(SU->dump(this)); + + assert(CurCycle >= SU->getHeight() && "Node scheduled below its height!"); + SU->setHeightToAtLeast(CurCycle); + Sequence.push_back(SU); + + ReleasePredecessors(SU, CurCycle); // Release all the implicit physical register defs that are live. for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); @@ -627,6 +635,10 @@ /// schedulers. void ScheduleDAGRRList::ListScheduleBottomUp() { unsigned CurCycle = 0; + + // Release any predecessors of the special Exit node. + ReleasePredecessors(&ExitSU, CurCycle); + // Add root to Available queue. if (!SUnits.empty()) { SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()]; @@ -789,12 +801,25 @@ } #endif - if (SuccSU->NumPredsLeft == 0) { + // If all the node's predecessors are scheduled, this node is ready + // to be scheduled. Ignore the special ExitSU node. + if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) { SuccSU->isAvailable = true; AvailableQueue->push(SuccSU); } } +void ScheduleDAGRRList::ReleaseSuccessors(SUnit *SU) { + // Top down: release successors + for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); + I != E; ++I) { + assert(!I->isAssignedRegDep() && + "The list-tdrr scheduler doesn't yet support physreg dependencies!"); + + ReleaseSucc(SU, &*I); + } +} + /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending /// count of its successors. If a successor pending count is zero, add it to /// the Available queue. @@ -806,15 +831,7 @@ SU->setDepthToAtLeast(CurCycle); Sequence.push_back(SU); - // Top down: release successors - for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); - I != E; ++I) { - assert(!I->isAssignedRegDep() && - "The list-tdrr scheduler doesn't yet support physreg dependencies!"); - - ReleaseSucc(SU, &*I); - } - + ReleaseSuccessors(SU); SU->isScheduled = true; AvailableQueue->ScheduledNode(SU); } @@ -824,6 +841,9 @@ void ScheduleDAGRRList::ListScheduleTopDown() { unsigned CurCycle = 0; + // Release any successors of the special Entry node. + ReleaseSuccessors(&EntrySU); + // All leaves to Available queue. for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { // It is available if it has no predecessors. From gohman at apple.com Tue Feb 10 17:29:38 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 10 Feb 2009 23:29:38 -0000 Subject: [llvm-commits] [llvm] r64255 - /llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Message-ID: <200902102329.n1ANTc67027128@zion.cs.uiuc.edu> Author: djg Date: Tue Feb 10 17:29:38 2009 New Revision: 64255 URL: http://llvm.org/viewvc/llvm-project?rev=64255&view=rev Log: Consider any instruction that modifies the stack pointer to be a scheduling region boundary. This isn't necessary for correctness; it helps with compile time, as it avoids the need for data- and anti-dependencies from all spills and reloads on the stack-pointer modification. Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=64255&r1=64254&r2=64255&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original) +++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Tue Feb 10 17:29:38 2009 @@ -28,6 +28,7 @@ #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/ScheduleHazardRecognizer.h" +#include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetRegisterInfo.h" @@ -221,6 +222,15 @@ if (MI->getDesc().isTerminator() || MI->isLabel()) return true; + // Don't attempt to schedule around any instruction that modifies + // a stack-oriented pointer, as it's unlikely to be profitable. This + // saves compile time, because it doesn't require every single + // stack slot reference to depend on the instruction that does the + // modification. + const TargetLowering &TLI = *MF.getTarget().getTargetLowering(); + if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore())) + return true; + return false; } From isanbard at gmail.com Tue Feb 10 18:06:19 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 11 Feb 2009 00:06:19 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r64260 - /llvm-gcc-4.2/tags/Apple/llvmgcc42-2098/ Message-ID: <200902110006.n1B06JpY028394@zion.cs.uiuc.edu> Author: void Date: Tue Feb 10 18:06:19 2009 New Revision: 64260 URL: http://llvm.org/viewvc/llvm-project?rev=64260&view=rev Log: Creating llvmgcc42-2098 from Dib branch. Added: llvm-gcc-4.2/tags/Apple/llvmgcc42-2098/ - copied from r64259, llvm-gcc-4.2/branches/Apple/Dib/ From isanbard at gmail.com Tue Feb 10 18:07:10 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 11 Feb 2009 00:07:10 -0000 Subject: [llvm-commits] [llvm] r64261 - /llvm/tags/Apple/llvmCore-2098/ Message-ID: <200902110007.n1B07AkD028428@zion.cs.uiuc.edu> Author: void Date: Tue Feb 10 18:07:10 2009 New Revision: 64261 URL: http://llvm.org/viewvc/llvm-project?rev=64261&view=rev Log: Creating llvmCore-2098 from Dib branch. Added: llvm/tags/Apple/llvmCore-2098/ - copied from r64260, llvm/branches/Apple/Dib/ From gohman at apple.com Tue Feb 10 18:12:29 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 11 Feb 2009 00:12:29 -0000 Subject: [llvm-commits] [llvm] r64262 - /llvm/trunk/lib/CodeGen/ScheduleDAG.cpp Message-ID: <200902110012.n1B0CUFW028586@zion.cs.uiuc.edu> Author: djg Date: Tue Feb 10 18:12:28 2009 New Revision: 64262 URL: http://llvm.org/viewvc/llvm-project?rev=64262&view=rev Log: Use iterators to iterate through the Preds array instead of an index. This code is on the hot-path because the current way SDep edges are uniqued has quadratic complexity. Modified: llvm/trunk/lib/CodeGen/ScheduleDAG.cpp Modified: llvm/trunk/lib/CodeGen/ScheduleDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAG.cpp?rev=64262&r1=64261&r2=64262&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAG.cpp Tue Feb 10 18:12:28 2009 @@ -74,8 +74,9 @@ /// specified node. void SUnit::addPred(const SDep &D) { // If this node already has this depenence, don't add a redundant one. - for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i) - if (Preds[i] == D) + for (SmallVector::const_iterator I = Preds.begin(), E = Preds.end(); + I != E; ++I) + if (*I == D) return; // Now add a corresponding succ to N. SDep P = D; From isanbard at gmail.com Tue Feb 10 18:14:53 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 11 Feb 2009 00:14:53 -0000 Subject: [llvm-commits] [llvm] r64263 - /llvm/trunk/utils/buildit/build_llvm Message-ID: <200902110014.n1B0Er6X028657@zion.cs.uiuc.edu> Author: void Date: Tue Feb 10 18:14:53 2009 New Revision: 64263 URL: http://llvm.org/viewvc/llvm-project?rev=64263&view=rev Log: Don't try to strip a file we just moved. Modified: llvm/trunk/utils/buildit/build_llvm Modified: llvm/trunk/utils/buildit/build_llvm URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=64263&r1=64262&r2=64263&view=diff ============================================================================== --- llvm/trunk/utils/buildit/build_llvm (original) +++ llvm/trunk/utils/buildit/build_llvm Tue Feb 10 18:14:53 2009 @@ -204,7 +204,7 @@ cd $DEST_DIR$DEST_ROOT mkdir -p $DT_HOME/lib mv lib/libLTO.dylib $DT_HOME/lib/libLTO.dylib -strip -S lib/libLTO.dylib $DT_HOME/lib/libLTO.dylib +strip -S $DT_HOME/lib/libLTO.dylib rm -f lib/libLTO.a lib/libLTO.la # Compress manpages From isanbard at gmail.com Tue Feb 10 18:15:08 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 11 Feb 2009 00:15:08 -0000 Subject: [llvm-commits] [llvm] r64264 - /llvm/branches/Apple/Dib/utils/buildit/build_llvm Message-ID: <200902110015.n1B0F8CW028674@zion.cs.uiuc.edu> Author: void Date: Tue Feb 10 18:15:08 2009 New Revision: 64264 URL: http://llvm.org/viewvc/llvm-project?rev=64264&view=rev Log: Don't try to strip a file we just moved. Modified: llvm/branches/Apple/Dib/utils/buildit/build_llvm Modified: llvm/branches/Apple/Dib/utils/buildit/build_llvm URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/utils/buildit/build_llvm?rev=64264&r1=64263&r2=64264&view=diff ============================================================================== --- llvm/branches/Apple/Dib/utils/buildit/build_llvm (original) +++ llvm/branches/Apple/Dib/utils/buildit/build_llvm Tue Feb 10 18:15:08 2009 @@ -204,7 +204,7 @@ cd $DEST_DIR$DEST_ROOT mkdir -p $DT_HOME/lib mv lib/libLTO.dylib $DT_HOME/lib/libLTO.dylib -strip -S lib/libLTO.dylib $DT_HOME/lib/libLTO.dylib +strip -S $DT_HOME/lib/libLTO.dylib rm -f lib/libLTO.a lib/libLTO.la # Compress manpages From gohman at apple.com Tue Feb 10 18:18:16 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 11 Feb 2009 00:18:16 -0000 Subject: [llvm-commits] [llvm] r64265 - /llvm/trunk/include/llvm/CodeGen/DebugLoc.h Message-ID: <200902110018.n1B0IGdW028757@zion.cs.uiuc.edu> Author: djg Date: Tue Feb 10 18:18:15 2009 New Revision: 64265 URL: http://llvm.org/viewvc/llvm-project?rev=64265&view=rev Log: It isn't necessary to explicitly clear the contents of std::vector and DenseMap members in a destructor. And tidy up a comment. Modified: llvm/trunk/include/llvm/CodeGen/DebugLoc.h Modified: llvm/trunk/include/llvm/CodeGen/DebugLoc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DebugLoc.h?rev=64265&r1=64264&r2=64265&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/DebugLoc.h (original) +++ llvm/trunk/include/llvm/CodeGen/DebugLoc.h Tue Feb 10 18:18:15 2009 @@ -82,16 +82,11 @@ /// std::vector DebugLocations; - /// DebugIdsMap - This maps DebugLocTuple's to indices into DebugLocations - /// vector. + /// DebugIdMap - This maps DebugLocTuple's to indices into the + /// DebugLocations vector. DenseMap DebugIdMap; DebugLocTracker() {} - - ~DebugLocTracker() { - DebugLocations.clear(); - DebugIdMap.clear(); - } }; } // end namespace llvm From gohman at apple.com Tue Feb 10 18:25:26 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 11 Feb 2009 00:25:26 -0000 Subject: [llvm-commits] [llvm] r64267 - /llvm/trunk/lib/VMCore/AsmWriter.cpp Message-ID: <200902110025.n1B0PQPg028970@zion.cs.uiuc.edu> Author: djg Date: Tue Feb 10 18:25:25 2009 New Revision: 64267 URL: http://llvm.org/viewvc/llvm-project?rev=64267&view=rev Log: Don't print extra spaces in vector and array constants. This makes them visually more consistent with vector and array types. Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=64267&r1=64266&r2=64267&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Tue Feb 10 18:25:25 2009 @@ -727,7 +727,6 @@ } else { // Cannot output in string format... Out << '['; if (CA->getNumOperands()) { - Out << ' '; printTypeInt(Out, ETy, TypeTable); Out << ' '; WriteAsOperandInternal(Out, CA->getOperand(0), @@ -738,7 +737,6 @@ Out << ' '; WriteAsOperandInternal(Out, CA->getOperand(i), TypeTable, Machine); } - Out << ' '; } Out << ']'; } @@ -777,7 +775,7 @@ const Type *ETy = CP->getType()->getElementType(); assert(CP->getNumOperands() > 0 && "Number of operands for a PackedConst must be > 0"); - Out << "< "; + Out << '<'; printTypeInt(Out, ETy, TypeTable); Out << ' '; WriteAsOperandInternal(Out, CP->getOperand(0), TypeTable, Machine); @@ -787,7 +785,7 @@ Out << ' '; WriteAsOperandInternal(Out, CP->getOperand(i), TypeTable, Machine); } - Out << " >"; + Out << '>'; return; } From isanbard at gmail.com Tue Feb 10 18:38:59 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 11 Feb 2009 00:38:59 -0000 Subject: [llvm-commits] [llvm] r64269 - /llvm/branches/Apple/Dib/utils/buildit/build_llvm Message-ID: <200902110038.n1B0cxP2029435@zion.cs.uiuc.edu> Author: void Date: Tue Feb 10 18:38:59 2009 New Revision: 64269 URL: http://llvm.org/viewvc/llvm-project?rev=64269&view=rev Log: 80-column violation. Modified: llvm/branches/Apple/Dib/utils/buildit/build_llvm Modified: llvm/branches/Apple/Dib/utils/buildit/build_llvm URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/utils/buildit/build_llvm?rev=64269&r1=64268&r2=64269&view=diff ============================================================================== --- llvm/branches/Apple/Dib/utils/buildit/build_llvm (original) +++ llvm/branches/Apple/Dib/utils/buildit/build_llvm Tue Feb 10 18:38:59 2009 @@ -235,7 +235,9 @@ rm -rf * || exit 1 # Generate .dSYM files -find $DEST_DIR -perm -0111 -type f ! \( -name '*.la' -o -name gccas -o -name gccld -o -name llvm-config \) -print \ +find $DEST_DIR -perm -0111 -type f \ + \! \( -name '*.la' -o -name gccas -o -name gccld -o -name llvm-config \) \ + -print \ | xargs -n 1 -P ${SYSCTL} dsymutil # Save .dSYM files and .a archives From dpatel at apple.com Tue Feb 10 19:29:06 2009 From: dpatel at apple.com (Devang Patel) Date: Wed, 11 Feb 2009 01:29:06 -0000 Subject: [llvm-commits] [llvm] r64278 - in /llvm/trunk: lib/Transforms/Utils/BasicBlockUtils.cpp lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/dbginfo.ll Message-ID: <200902110129.n1B1T7hl031164@zion.cs.uiuc.edu> Author: dpatel Date: Tue Feb 10 19:29:06 2009 New Revision: 64278 URL: http://llvm.org/viewvc/llvm-project?rev=64278&view=rev Log: If llvm.dbg.region.end is disappearing then remove corresponding llvm.dbg.func.start also. Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp llvm/trunk/test/Transforms/SimplifyCFG/dbginfo.ll Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=64278&r1=64277&r2=64278&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Tue Feb 10 19:29:06 2009 @@ -15,6 +15,7 @@ #include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Function.h" #include "llvm/Instructions.h" +#include "llvm/IntrinsicInst.h" #include "llvm/Constant.h" #include "llvm/Type.h" #include "llvm/Analysis/AliasAnalysis.h" @@ -31,7 +32,7 @@ // Can delete self loop. BB->getSinglePredecessor() == BB) && "Block is not dead!"); TerminatorInst *BBTerm = BB->getTerminator(); - + Value *DbgRegionEndContext = NULL; // Loop through all of our successors and make sure they know that one // of their predecessors is going away. for (unsigned i = 0, e = BBTerm->getNumSuccessors(); i != e; ++i) @@ -40,6 +41,10 @@ // Zap all the instructions in the block. while (!BB->empty()) { Instruction &I = BB->back(); + // It is possible to have multiple llvm.dbg.region.end in a block. + if (DbgRegionEndInst *DREI = dyn_cast(&I)) + DbgRegionEndContext = DREI->getContext(); + // If this instruction is used, replace uses with an arbitrary value. // Because control flow can't get here, we don't care what we replace the // value with. Note that since this block is unreachable, and all values @@ -49,7 +54,22 @@ I.replaceAllUsesWith(UndefValue::get(I.getType())); BB->getInstList().pop_back(); } - + + if (DbgRegionEndContext) { + // Delete corresponding llvm.dbg.func.start from entry block. + BasicBlock &Entry = BB->getParent()->getEntryBlock(); + DbgFuncStartInst *DbgFuncStart = NULL; + for (BasicBlock::iterator BI = Entry.begin(), BE = Entry.end(); + BI != BE; ++BI) { + if (DbgFuncStartInst *DFSI = dyn_cast(BI)) { + DbgFuncStart = DFSI; + break; + } + } + if (DbgFuncStart && DbgFuncStart->getSubprogram() == DbgRegionEndContext) + DbgFuncStart->eraseFromParent(); + } + // Zap the block! BB->eraseFromParent(); } Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=64278&r1=64277&r2=64278&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Feb 10 19:29:06 2009 @@ -1806,7 +1806,7 @@ // If we eliminated all predecessors of the block, delete the block now. if (pred_begin(BB) == pred_end(BB)) // We know there are no successors, so just nuke the block. - M->getBasicBlockList().erase(BB); + DeleteDeadBlock(BB); return true; } Modified: llvm/trunk/test/Transforms/SimplifyCFG/dbginfo.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/dbginfo.ll?rev=64278&r1=64277&r2=64278&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/dbginfo.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/dbginfo.ll Tue Feb 10 19:29:06 2009 @@ -1,4 +1,5 @@ ; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | grep region | count 1 +; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | grep func.start | count 1 %llvm.dbg.anchor.type = type { i32, i32 } %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 } %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } From isanbard at gmail.com Tue Feb 10 19:43:31 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 11 Feb 2009 01:43:31 -0000 Subject: [llvm-commits] [llvm] r64284 - in /llvm/branches/Apple/Dib: lib/Transforms/Utils/BasicBlockUtils.cpp lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/dbginfo.ll Message-ID: <200902110143.n1B1hV40031745@zion.cs.uiuc.edu> Author: void Date: Tue Feb 10 19:43:31 2009 New Revision: 64284 URL: http://llvm.org/viewvc/llvm-project?rev=64284&view=rev Log: Pull r64278 into Dib: If llvm.dbg.region.end is disappearing then remove corresponding llvm.dbg.func.start also. Modified: llvm/branches/Apple/Dib/lib/Transforms/Utils/BasicBlockUtils.cpp llvm/branches/Apple/Dib/lib/Transforms/Utils/SimplifyCFG.cpp llvm/branches/Apple/Dib/test/Transforms/SimplifyCFG/dbginfo.ll Modified: llvm/branches/Apple/Dib/lib/Transforms/Utils/BasicBlockUtils.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=64284&r1=64283&r2=64284&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Transforms/Utils/BasicBlockUtils.cpp (original) +++ llvm/branches/Apple/Dib/lib/Transforms/Utils/BasicBlockUtils.cpp Tue Feb 10 19:43:31 2009 @@ -15,6 +15,7 @@ #include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Function.h" #include "llvm/Instructions.h" +#include "llvm/IntrinsicInst.h" #include "llvm/Constant.h" #include "llvm/Type.h" #include "llvm/Analysis/AliasAnalysis.h" @@ -31,7 +32,7 @@ // Can delete self loop. BB->getSinglePredecessor() == BB) && "Block is not dead!"); TerminatorInst *BBTerm = BB->getTerminator(); - + Value *DbgRegionEndContext = NULL; // Loop through all of our successors and make sure they know that one // of their predecessors is going away. for (unsigned i = 0, e = BBTerm->getNumSuccessors(); i != e; ++i) @@ -40,6 +41,10 @@ // Zap all the instructions in the block. while (!BB->empty()) { Instruction &I = BB->back(); + // It is possible to have multiple llvm.dbg.region.end in a block. + if (DbgRegionEndInst *DREI = dyn_cast(&I)) + DbgRegionEndContext = DREI->getContext(); + // If this instruction is used, replace uses with an arbitrary value. // Because control flow can't get here, we don't care what we replace the // value with. Note that since this block is unreachable, and all values @@ -49,7 +54,22 @@ I.replaceAllUsesWith(UndefValue::get(I.getType())); BB->getInstList().pop_back(); } - + + if (DbgRegionEndContext) { + // Delete corresponding llvm.dbg.func.start from entry block. + BasicBlock &Entry = BB->getParent()->getEntryBlock(); + DbgFuncStartInst *DbgFuncStart = NULL; + for (BasicBlock::iterator BI = Entry.begin(), BE = Entry.end(); + BI != BE; ++BI) { + if (DbgFuncStartInst *DFSI = dyn_cast(BI)) { + DbgFuncStart = DFSI; + break; + } + } + if (DbgFuncStart && DbgFuncStart->getSubprogram() == DbgRegionEndContext) + DbgFuncStart->eraseFromParent(); + } + // Zap the block! BB->eraseFromParent(); } Modified: llvm/branches/Apple/Dib/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Transforms/Utils/SimplifyCFG.cpp?rev=64284&r1=64283&r2=64284&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/branches/Apple/Dib/lib/Transforms/Utils/SimplifyCFG.cpp Tue Feb 10 19:43:31 2009 @@ -1806,7 +1806,7 @@ // If we eliminated all predecessors of the block, delete the block now. if (pred_begin(BB) == pred_end(BB)) // We know there are no successors, so just nuke the block. - M->getBasicBlockList().erase(BB); + DeleteDeadBlock(BB); return true; } Modified: llvm/branches/Apple/Dib/test/Transforms/SimplifyCFG/dbginfo.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/Transforms/SimplifyCFG/dbginfo.ll?rev=64284&r1=64283&r2=64284&view=diff ============================================================================== --- llvm/branches/Apple/Dib/test/Transforms/SimplifyCFG/dbginfo.ll (original) +++ llvm/branches/Apple/Dib/test/Transforms/SimplifyCFG/dbginfo.ll Tue Feb 10 19:43:31 2009 @@ -1,4 +1,5 @@ ; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | grep region | count 1 +; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | grep func.start | count 1 %llvm.dbg.anchor.type = type { i32, i32 } %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 } %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } From dpatel at apple.com Tue Feb 10 20:34:33 2009 From: dpatel at apple.com (Devang Patel) Date: Wed, 11 Feb 2009 02:34:33 -0000 Subject: [llvm-commits] [llvm] r64285 - in /llvm/trunk/tools: Makefile lto/Makefile Message-ID: <200902110234.n1B2YXPZ001181@zion.cs.uiuc.edu> Author: dpatel Date: Tue Feb 10 20:34:33 2009 New Revision: 64285 URL: http://llvm.org/viewvc/llvm-project?rev=64285&view=rev Log: 62987 disables LTO build on darwin. Revert 62987 for now. Nicolas please investigate. Modified: llvm/trunk/tools/Makefile llvm/trunk/tools/lto/Makefile Modified: llvm/trunk/tools/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/Makefile?rev=64285&r1=64284&r2=64285&view=diff ============================================================================== --- llvm/trunk/tools/Makefile (original) +++ llvm/trunk/tools/Makefile Tue Feb 10 20:34:33 2009 @@ -25,7 +25,8 @@ include $(LEVEL)/Makefile.config -ifeq ($(ENABLE_PIC),1) +# only build new lto project on Darwin for now +ifeq ($(OS),Darwin) PARALLEL_DIRS += lto ifdef BINUTILS_INCDIR Modified: llvm/trunk/tools/lto/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/Makefile?rev=64285&r1=64284&r2=64285&view=diff ============================================================================== --- llvm/trunk/tools/lto/Makefile (original) +++ llvm/trunk/tools/lto/Makefile Tue Feb 10 20:34:33 2009 @@ -16,8 +16,12 @@ include $(LEVEL)/Makefile.config LINK_LIBS_IN_SHARED = 1 -SHARED_LIBRARY = 1 -DONT_BUILD_RELINKED = 1 +ifeq ($(OS),Darwin) + SHARED_LIBRARY = 1 + DONT_BUILD_RELINKED = 1 +else + BUILD_ARCHIVE = 1 +endif LINK_COMPONENTS := $(TARGETS_TO_BUILD) ipo scalaropts linker bitreader bitwriter From sanjiv.gupta at microchip.com Tue Feb 10 21:58:26 2009 From: sanjiv.gupta at microchip.com (sanjiv gupta) Date: Wed, 11 Feb 2009 09:28:26 +0530 Subject: [llvm-commits] r64000 breaks PIC16 In-Reply-To: <3BEE949D-7D28-4B3F-A69C-3E972C8716A9@apple.com> References: <1234292444.7110.7.camel@idc-lt-i00171.microchip.com> <3BEE949D-7D28-4B3F-A69C-3E972C8716A9@apple.com> Message-ID: <1234324706.4728.5.camel@idc-lt-i00171.microchip.com> On Tue, 2009-02-10 at 12:24 -0800, Dan Gohman wrote: > On Feb 10, 2009, at 11:00 AM, sanjiv gupta wrote: > > The correct assembly is: (as per r63998) > [snip] > > > > The incorrect assembly is : (as per r64000) > > [snip] > > It looks like 63999, enabling sinking, is more likely to be the > revision that > introduces the change. If it is, can you check to see if the problem > is fixed > in the latest trunk? > > Dan > Dan, It still breaks as per 64285. I have attached a .bc file. The problem with the generated assembly is that the branch (.blt) is happening before the test (subwf) insn. - Sanjiv > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- A non-text attachment was scrubbed... Name: a.bc Type: application/octet-stream Size: 428 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090211/443caf29/attachment.obj From gohman at apple.com Tue Feb 10 22:26:57 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 11 Feb 2009 04:26:57 -0000 Subject: [llvm-commits] [test-suite] r64287 - /test-suite/trunk/External/SPEC/CINT2000/186.crafty/Makefile Message-ID: <200902110426.n1B4QvwO004431@zion.cs.uiuc.edu> Author: djg Date: Tue Feb 10 22:26:53 2009 New Revision: 64287 URL: http://llvm.org/viewvc/llvm-project?rev=64287&view=rev Log: Fix 186.crafty's Makefile to handle ARCH=x86_64. Predefine the individual macros instead of using LINUX_i386, so that crafy's preset values don't override the Makefile's specified values. Modified: test-suite/trunk/External/SPEC/CINT2000/186.crafty/Makefile Modified: test-suite/trunk/External/SPEC/CINT2000/186.crafty/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2000/186.crafty/Makefile?rev=64287&r1=64286&r2=64287&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT2000/186.crafty/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT2000/186.crafty/Makefile Tue Feb 10 22:26:53 2009 @@ -17,7 +17,10 @@ CPPFLAGS += -DALPHA -DLINUX endif ifeq ($(ARCH),x86) - CPPFLAGS += -DLINUX_i386 + CPPFLAGS += -DHAS_LONGLONG +endif +ifeq ($(ARCH),x86_64) + CPPFLAGS += -DLONG_HAS_64BITS -DHAS_LONGLONG endif ifeq ($(ARCH),PowerPC) CPPFLAGS += -DLINUX_PPC32 @@ -26,13 +29,16 @@ CPPFLAGS += -DSUN_BSD endif ifeq ($(TARGET_ARCH),ARM) - CPPFLAGS += -DHAS_LONGLONG + CPPFLAGS += -DHAS_LONGLONG endif ifeq ($(OS),Darwin) - CPPFLAGS += -DUNIX -DLINUX + CPPFLAGS += -DUNIX -DLINUX +endif +ifeq ($(OS),Linux) + CPPFLAGS += -DUNIX -DLINUX endif ifeq ($(ENDIAN),little) - CPPFLAGS += -DLITTLE_ENDIAN_ARCH + CPPFLAGS += -DLITTLE_ENDIAN_ARCH endif include ../../Makefile.spec2000 From gohman at apple.com Tue Feb 10 22:27:20 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 11 Feb 2009 04:27:20 -0000 Subject: [llvm-commits] [llvm] r64288 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ Message-ID: <200902110427.n1B4RLU4004464@zion.cs.uiuc.edu> Author: djg Date: Tue Feb 10 22:27:20 2009 New Revision: 64288 URL: http://llvm.org/viewvc/llvm-project?rev=64288&view=rev Log: When scheduling a block in parts, keep track of the overall instruction index across each part. Instruction indices are used to make live range queries, and live ranges can extend beyond scheduling region boundaries. Refactor the ScheduleDAGSDNodes class some more so that it doesn't have to worry about this additional information. Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp llvm/trunk/lib/CodeGen/ScheduleDAG.cpp llvm/trunk/lib/CodeGen/ScheduleDAGEmit.cpp llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=64288&r1=64287&r2=64288&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Tue Feb 10 22:27:20 2009 @@ -31,7 +31,6 @@ class MachineInstr; class TargetRegisterInfo; class ScheduleDAG; - class SelectionDAG; class SDNode; class TargetInstrInfo; class TargetInstrDesc; @@ -426,10 +425,8 @@ class ScheduleDAG { public: - SelectionDAG *DAG; // DAG of the current basic block - MachineBasicBlock *BB; // Current basic block - MachineBasicBlock::iterator Begin; // The beginning of the range to be scheduled. - MachineBasicBlock::iterator End; // The end of the range to be scheduled. + MachineBasicBlock *BB; // The block in which to insert instructions. + MachineBasicBlock::iterator InsertPos;// The position to insert instructions. const TargetMachine &TM; // Target processor const TargetInstrInfo *TII; // Target instruction information const TargetRegisterInfo *TRI; // Target processor register info @@ -452,12 +449,6 @@ /// void viewGraph(); - /// Run - perform scheduling. - /// - void Run(SelectionDAG *DAG, MachineBasicBlock *MBB, - MachineBasicBlock::iterator Begin, - MachineBasicBlock::iterator End); - /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock /// according to the order specified in Sequence. /// @@ -482,6 +473,10 @@ #endif protected: + /// Run - perform scheduling. + /// + void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos); + /// BuildSchedGraph - Build SUnits and set up their Preds and Succs /// to form the scheduling dependency graph. /// Modified: llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h?rev=64288&r1=64287&r2=64288&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h (original) +++ llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h Tue Feb 10 22:27:20 2009 @@ -26,13 +26,13 @@ //===----------------------------------------------------------------------===// class SelectionDAGISel; -class ScheduleDAG; +class ScheduleDAGSDNodes; class SelectionDAG; class MachineBasicBlock; class RegisterScheduler : public MachinePassRegistryNode { public: - typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAGISel*, bool); + typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, bool); static MachinePassRegistry Registry; @@ -63,28 +63,28 @@ /// createBURRListDAGScheduler - This creates a bottom up register usage /// reduction list scheduler. -ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS, - bool Fast); +ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS, + bool Fast); /// createTDRRListDAGScheduler - This creates a top down register usage /// reduction list scheduler. -ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS, - bool Fast); +ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS, + bool Fast); /// createTDListDAGScheduler - This creates a top-down list scheduler with /// a hazard recognizer. -ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS, - bool Fast); +ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS, + bool Fast); /// createFastDAGScheduler - This creates a "fast" scheduler. /// -ScheduleDAG *createFastDAGScheduler(SelectionDAGISel *IS, - bool Fast); +ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS, + bool Fast); /// createDefaultScheduler - This creates an instruction scheduler appropriate /// for the target. -ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, - bool Fast); +ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS, + bool Fast); } // end namespace llvm Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=64288&r1=64287&r2=64288&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Tue Feb 10 22:27:20 2009 @@ -35,7 +35,7 @@ class FunctionLoweringInfo; class ScheduleHazardRecognizer; class GCFunctionInfo; - class ScheduleDAG; + class ScheduleDAGSDNodes; /// SelectionDAGISel - This is the common base class used for SelectionDAG-based /// pattern-matching instruction selectors. @@ -133,7 +133,7 @@ /// via the SchedulerRegistry, use it, otherwise select the /// one preferred by the target. /// - ScheduleDAG *CreateScheduler(); + ScheduleDAGSDNodes *CreateScheduler(); }; } Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=64288&r1=64287&r2=64288&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original) +++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Tue Feb 10 22:27:20 2009 @@ -139,7 +139,7 @@ /// Observe - Update liveness information to account for the current /// instruction, which will not be scheduled. /// - void Observe(MachineInstr *MI); + void Observe(MachineInstr *MI, unsigned Count); /// FinishBlock - Clean up register live-range state. /// @@ -254,19 +254,26 @@ // Schedule each sequence of instructions not interrupted by a label // or anything else that effectively needs to shut down scheduling. MachineBasicBlock::iterator Current = MBB->end(); + unsigned Count = MBB->size(), CurrentCount = Count; for (MachineBasicBlock::iterator I = Current; I != MBB->begin(); ) { MachineInstr *MI = prior(I); if (isSchedulingBoundary(MI, Fn)) { if (I != Current) { - Scheduler.Run(0, MBB, I, Current); + Scheduler.Run(MBB, I, Current, CurrentCount); Scheduler.EmitSchedule(); } - Scheduler.Observe(MI); + Scheduler.Observe(MI, Count); Current = MI; + CurrentCount = Count - 1; } I = MI; + --Count; + } + assert(Count == 0 && "Instruction count mismatch!"); + if (MBB->begin() != Current) { + assert(CurrentCount != 0 && "Instruction count mismatch!"); + Scheduler.Run(MBB, MBB->begin(), Current, CurrentCount); } - Scheduler.Run(0, MBB, MBB->begin(), Current); Scheduler.EmitSchedule(); // Clean up register live-range state. @@ -311,7 +318,7 @@ else // In a non-return block, examine the live-in regs of all successors. for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), - SE = BB->succ_end(); SI != SE; ++SI) + SE = BB->succ_end(); SI != SE; ++SI) for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(), E = (*SI)->livein_end(); I != E; ++I) { unsigned Reg = *I; @@ -384,9 +391,9 @@ /// Observe - Update liveness information to account for the current /// instruction, which will not be scheduled. /// -void SchedulePostRATDList::Observe(MachineInstr *MI) { +void SchedulePostRATDList::Observe(MachineInstr *MI, unsigned Count) { PrescanInstruction(MI); - ScanInstruction(MI, 0); + ScanInstruction(MI, Count); } /// FinishBlock - Clean up register live-range state. @@ -484,6 +491,9 @@ DefIndices[Reg] = Count; KillIndices[Reg] = ~0u; + assert(((KillIndices[Reg] == ~0u) != + (DefIndices[Reg] == ~0u)) && + "Kill and Def maps aren't consistent for Reg!"); Classes[Reg] = 0; RegRefs.erase(Reg); // Repeat, for all subregs. @@ -525,6 +535,9 @@ if (KillIndices[Reg] == ~0u) { KillIndices[Reg] = Count; DefIndices[Reg] = ~0u; + assert(((KillIndices[Reg] == ~0u) != + (DefIndices[Reg] == ~0u)) && + "Kill and Def maps aren't consistent for Reg!"); } // Repeat, for all aliases. for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { @@ -608,8 +621,8 @@ // instructions from the bottom up, tracking information about liveness // as we go to help determine which registers are available. bool Changed = false; - unsigned Count = SUnits.size() - 1; - for (MachineBasicBlock::iterator I = End, E = Begin; + unsigned Count = InsertPosIndex - 1; + for (MachineBasicBlock::iterator I = InsertPos, E = Begin; I != E; --Count) { MachineInstr *MI = --I; @@ -739,10 +752,16 @@ Classes[NewReg] = Classes[AntiDepReg]; DefIndices[NewReg] = DefIndices[AntiDepReg]; KillIndices[NewReg] = KillIndices[AntiDepReg]; + assert(((KillIndices[NewReg] == ~0u) != + (DefIndices[NewReg] == ~0u)) && + "Kill and Def maps aren't consistent for NewReg!"); Classes[AntiDepReg] = 0; DefIndices[AntiDepReg] = KillIndices[AntiDepReg]; KillIndices[AntiDepReg] = ~0u; + assert(((KillIndices[AntiDepReg] == ~0u) != + (DefIndices[AntiDepReg] == ~0u)) && + "Kill and Def maps aren't consistent for AntiDepReg!"); RegRefs.erase(AntiDepReg); Changed = true; @@ -754,7 +773,6 @@ ScanInstruction(MI, Count); } - assert(Count == ~0u && "Count mismatch!"); return Changed; } Modified: llvm/trunk/lib/CodeGen/ScheduleDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAG.cpp?rev=64288&r1=64287&r2=64288&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAG.cpp Tue Feb 10 22:27:20 2009 @@ -23,7 +23,7 @@ using namespace llvm; ScheduleDAG::ScheduleDAG(MachineFunction &mf) - : DAG(0), BB(0), TM(mf.getTarget()), + : TM(mf.getTarget()), TII(TM.getInstrInfo()), TRI(TM.getRegisterInfo()), TLI(TM.getTargetLowering()), @@ -47,23 +47,18 @@ /// Run - perform scheduling. /// -void ScheduleDAG::Run(SelectionDAG *dag, MachineBasicBlock *bb, - MachineBasicBlock::iterator begin, - MachineBasicBlock::iterator end) { - assert((!dag || begin == end) && - "An instruction range was given for SelectionDAG scheduling!"); +void ScheduleDAG::Run(MachineBasicBlock *bb, + MachineBasicBlock::iterator insertPos) { + BB = bb; + InsertPos = insertPos; SUnits.clear(); Sequence.clear(); - DAG = dag; - BB = bb; - Begin = begin; - End = end; EntrySU = SUnit(); ExitSU = SUnit(); Schedule(); - + DOUT << "*** Final schedule ***\n"; DEBUG(dumpSchedule()); DOUT << "\n"; Modified: llvm/trunk/lib/CodeGen/ScheduleDAGEmit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGEmit.cpp?rev=64288&r1=64287&r2=64288&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGEmit.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGEmit.cpp Tue Feb 10 22:27:20 2009 @@ -33,7 +33,7 @@ } void ScheduleDAG::EmitNoop() { - TII->insertNoop(*BB, End); + TII->insertNoop(*BB, InsertPos); } void ScheduleDAG::EmitPhysRegCopy(SUnit *SU, @@ -54,7 +54,7 @@ break; } } - TII->copyRegToReg(*BB, End, Reg, VRI->second, + TII->copyRegToReg(*BB, InsertPos, Reg, VRI->second, SU->CopyDstRC, SU->CopySrcRC); } else { // Copy from physical register. @@ -63,7 +63,7 @@ bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second; isNew = isNew; // Silence compiler warning. assert(isNew && "Node emitted out of order - early"); - TII->copyRegToReg(*BB, End, VRBase, I->getReg(), + TII->copyRegToReg(*BB, InsertPos, VRBase, I->getReg(), SU->CopyDstRC, SU->CopySrcRC); } break; Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=64288&r1=64287&r2=64288&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Tue Feb 10 22:27:20 2009 @@ -32,6 +32,19 @@ const MachineDominatorTree &mdt) : ScheduleDAG(mf), MLI(mli), MDT(mdt), LoopRegs(MLI, MDT) {} +/// Run - perform scheduling. +/// +void ScheduleDAGInstrs::Run(MachineBasicBlock *bb, + MachineBasicBlock::iterator begin, + MachineBasicBlock::iterator end, + unsigned endcount) { + BB = bb; + Begin = begin; + InsertPosIndex = endcount; + + ScheduleDAG::Run(bb, end); +} + /// getOpcode - If this is an Instruction or a ConstantExpr, return the /// opcode value. Otherwise return UserOp1. static unsigned getOpcode(const Value *V) { @@ -146,7 +159,7 @@ TM.getSubtarget().getSpecialAddressLatency(); // Walk the list of instructions, from bottom moving up. - for (MachineBasicBlock::iterator MII = End, MIE = Begin; + for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin; MII != MIE; --MII) { MachineInstr *MI = prior(MII); const TargetInstrDesc &TID = MI->getDesc(); @@ -428,7 +441,7 @@ MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() { // For MachineInstr-based scheduling, we're rescheduling the instructions in // the block, so start by removing them from the block. - while (Begin != End) { + while (Begin != InsertPos) { MachineBasicBlock::iterator I = Begin; ++Begin; BB->remove(I); @@ -443,7 +456,7 @@ continue; } - BB->insert(End, SU->getInstr()); + BB->insert(InsertPos, SU->getInstr()); } // Update the Begin iterator, as the first instruction in the block Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h?rev=64288&r1=64287&r2=64288&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h Tue Feb 10 22:27:20 2009 @@ -120,6 +120,12 @@ SmallSet LoopLiveInRegs; public: + MachineBasicBlock *BB; // Current basic block + MachineBasicBlock::iterator Begin; // The beginning of the range to + // be scheduled. The range extends + // to InsertPos. + unsigned InsertPosIndex; // The index in BB of InsertPos. + explicit ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo &mli, const MachineDominatorTree &mdt); @@ -139,6 +145,13 @@ return &SUnits.back(); } + /// Run - perform scheduling. + /// + void Run(MachineBasicBlock *bb, + MachineBasicBlock::iterator begin, + MachineBasicBlock::iterator end, + unsigned endindex); + /// BuildSchedGraph - Build SUnits from the MachineBasicBlock that we are /// input. virtual void BuildSchedGraph(); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=64288&r1=64287&r2=64288&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Tue Feb 10 22:27:20 2009 @@ -629,6 +629,7 @@ // Public Constructor Functions //===----------------------------------------------------------------------===// -llvm::ScheduleDAG* llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) { +llvm::ScheduleDAGSDNodes * +llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) { return new ScheduleDAGFast(*IS->MF); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=64288&r1=64287&r2=64288&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Tue Feb 10 22:27:20 2009 @@ -260,8 +260,8 @@ /// createTDListDAGScheduler - This creates a top-down list scheduler with a /// new hazard recognizer. This scheduler takes ownership of the hazard /// recognizer and deletes it when done. -ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAGISel *IS, - bool Fast) { +ScheduleDAGSDNodes * +llvm::createTDListDAGScheduler(SelectionDAGISel *IS, bool Fast) { return new ScheduleDAGList(*IS->MF, new LatencyPriorityQueue(), IS->CreateTargetHazardRecognizer()); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=64288&r1=64287&r2=64288&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Feb 10 22:27:20 2009 @@ -1358,8 +1358,8 @@ // Public Constructor Functions //===----------------------------------------------------------------------===// -llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, - bool) { +llvm::ScheduleDAGSDNodes * +llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) { const TargetMachine &TM = IS->TM; const TargetInstrInfo *TII = TM.getInstrInfo(); const TargetRegisterInfo *TRI = TM.getRegisterInfo(); @@ -1372,8 +1372,8 @@ return SD; } -llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, - bool) { +llvm::ScheduleDAGSDNodes * +llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) { const TargetMachine &TM = IS->TM; const TargetInstrInfo *TII = TM.getInstrInfo(); const TargetRegisterInfo *TRI = TM.getRegisterInfo(); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=64288&r1=64287&r2=64288&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Tue Feb 10 22:27:20 2009 @@ -26,6 +26,14 @@ : ScheduleDAG(mf) { } +/// Run - perform scheduling. +/// +void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb, + MachineBasicBlock::iterator insertPos) { + DAG = dag; + ScheduleDAG::Run(bb, insertPos); +} + SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) { SUnit *SU = NewSUnit(Old->getNode()); SU->OrigNode = Old->OrigNode; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h?rev=64288&r1=64287&r2=64288&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h Tue Feb 10 22:27:20 2009 @@ -35,10 +35,17 @@ /// class ScheduleDAGSDNodes : public ScheduleDAG { public: + SelectionDAG *DAG; // DAG of the current basic block + explicit ScheduleDAGSDNodes(MachineFunction &mf); virtual ~ScheduleDAGSDNodes() {} + /// Run - perform scheduling. + /// + void Run(SelectionDAG *dag, MachineBasicBlock *bb, + MachineBasicBlock::iterator insertPos); + /// isPassiveNode - Return true if the node is a non-scheduled leaf. /// static bool isPassiveNode(SDNode *Node) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp?rev=64288&r1=64287&r2=64288&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp Tue Feb 10 22:27:20 2009 @@ -125,7 +125,8 @@ } else { // Create the reg, emit the copy. VRBase = MRI.createVirtualRegister(DstRC); - bool Emitted = TII->copyRegToReg(*BB, End, VRBase, SrcReg, DstRC, SrcRC); + bool Emitted = TII->copyRegToReg(*BB, InsertPos, VRBase, SrcReg, + DstRC, SrcRC); if (!Emitted) { cerr << "Unable to issue a copy instruction!\n"; abort(); @@ -381,7 +382,7 @@ MI->addOperand(MachineOperand::CreateReg(VRBase, true)); AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); MI->addOperand(MachineOperand::CreateImm(SubIdx)); - BB->insert(End, MI); + BB->insert(InsertPos, MI); } else if (Opc == TargetInstrInfo::INSERT_SUBREG || Opc == TargetInstrInfo::SUBREG_TO_REG) { SDValue N0 = Node->getOperand(0); @@ -414,7 +415,7 @@ // Add the subregster being inserted AddOperand(MI, N1, 0, 0, VRBaseMap); MI->addOperand(MachineOperand::CreateImm(SubIdx)); - BB->insert(End, MI); + BB->insert(InsertPos, MI); } else assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg"); @@ -478,9 +479,9 @@ // Insert this instruction into the basic block using a target // specific inserter which may returns a new basic block. BB = TLI->EmitInstrWithCustomInserter(MI, BB); - Begin = End = BB->end(); + InsertPos = BB->end(); } else { - BB->insert(End, MI); + BB->insert(InsertPos, MI); } // Additional results must be an physical register def. @@ -530,7 +531,8 @@ else DstTRC = TRI->getPhysicalRegisterRegClass(DestReg, Node->getOperand(1).getValueType()); - bool Emitted = TII->copyRegToReg(*BB, End, DestReg, SrcReg, DstTRC, SrcTRC); + bool Emitted = TII->copyRegToReg(*BB, InsertPos, DestReg, SrcReg, + DstTRC, SrcTRC); if (!Emitted) { cerr << "Unable to issue a copy instruction!\n"; abort(); @@ -590,7 +592,7 @@ break; } } - BB->insert(End, MI); + BB->insert(InsertPos, MI); break; } } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=64288&r1=64287&r2=64288&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Feb 10 22:27:20 2009 @@ -137,8 +137,8 @@ //===--------------------------------------------------------------------===// /// createDefaultScheduler - This creates an instruction scheduler appropriate /// for the target. - ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, - bool Fast) { + ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, + bool Fast) { const TargetLowering &TLI = IS->getTargetLowering(); if (Fast) @@ -662,12 +662,12 @@ if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); // Schedule machine code. - ScheduleDAG *Scheduler = CreateScheduler(); + ScheduleDAGSDNodes *Scheduler = CreateScheduler(); if (TimePassesIsEnabled) { NamedRegionTimer T("Instruction Scheduling", GroupName); - Scheduler->Run(CurDAG, BB, BB->end(), BB->end()); + Scheduler->Run(CurDAG, BB, BB->end()); } else { - Scheduler->Run(CurDAG, BB, BB->end(), BB->end()); + Scheduler->Run(CurDAG, BB, BB->end()); } if (ViewSUnitDAGs) Scheduler->viewGraph(); @@ -1068,7 +1068,7 @@ /// via the SchedulerRegistry, use it, otherwise select the /// one preferred by the target. /// -ScheduleDAG *SelectionDAGISel::CreateScheduler() { +ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); if (!Ctor) { From clattner at apple.com Tue Feb 10 23:11:23 2009 From: clattner at apple.com (Chris Lattner) Date: Tue, 10 Feb 2009 21:11:23 -0800 Subject: [llvm-commits] [llvm] r64278 - in /llvm/trunk: lib/Transforms/Utils/BasicBlockUtils.cpp lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/dbginfo.ll In-Reply-To: <200902110129.n1B1T7hl031164@zion.cs.uiuc.edu> References: <200902110129.n1B1T7hl031164@zion.cs.uiuc.edu> Message-ID: <78BD012B-6299-4590-9DE9-BF14047EFA6B@apple.com> On Feb 10, 2009, at 5:29 PM, Devang Patel wrote: > Author: dpatel > Date: Tue Feb 10 19:29:06 2009 > New Revision: 64278 > > URL: http://llvm.org/viewvc/llvm-project?rev=64278&view=rev > Log: > If llvm.dbg.region.end is disappearing then remove corresponding > llvm.dbg.func.start also. Why? The dbg.region.end may be removed in cases where the end of function is unreachable, e.g.: void foo() { while (1) whatever(); } I still would like to step through foo. -Chris From nicholas at mxc.ca Tue Feb 10 23:35:10 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 10 Feb 2009 21:35:10 -0800 Subject: [llvm-commits] [llvm] r64285 - in /llvm/trunk/tools: Makefile lto/Makefile In-Reply-To: <200902110234.n1B2YXPZ001181@zion.cs.uiuc.edu> References: <200902110234.n1B2YXPZ001181@zion.cs.uiuc.edu> Message-ID: <4992638E.9080703@mxc.ca> Devang Patel wrote: > Author: dpatel > Date: Tue Feb 10 20:34:33 2009 > New Revision: 64285 > > URL: http://llvm.org/viewvc/llvm-project?rev=64285&view=rev > Log: > 62987 disables LTO build on darwin. > Revert 62987 for now. Nicolas please investigate. Interesting! I thought darwin builds PIC by default. Why isn't it setting ENABLE_PIC? Regardless, I'll fix this shortly... > > Modified: > llvm/trunk/tools/Makefile > llvm/trunk/tools/lto/Makefile > > Modified: llvm/trunk/tools/Makefile > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/Makefile?rev=64285&r1=64284&r2=64285&view=diff > > ============================================================================== > --- llvm/trunk/tools/Makefile (original) > +++ llvm/trunk/tools/Makefile Tue Feb 10 20:34:33 2009 > @@ -25,7 +25,8 @@ > > include $(LEVEL)/Makefile.config > > -ifeq ($(ENABLE_PIC),1) > +# only build new lto project on Darwin for now > +ifeq ($(OS),Darwin) > PARALLEL_DIRS += lto > > ifdef BINUTILS_INCDIR > > Modified: llvm/trunk/tools/lto/Makefile > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/Makefile?rev=64285&r1=64284&r2=64285&view=diff > > ============================================================================== > --- llvm/trunk/tools/lto/Makefile (original) > +++ llvm/trunk/tools/lto/Makefile Tue Feb 10 20:34:33 2009 > @@ -16,8 +16,12 @@ > include $(LEVEL)/Makefile.config > > LINK_LIBS_IN_SHARED = 1 > -SHARED_LIBRARY = 1 > -DONT_BUILD_RELINKED = 1 > +ifeq ($(OS),Darwin) > + SHARED_LIBRARY = 1 > + DONT_BUILD_RELINKED = 1 > +else > + BUILD_ARCHIVE = 1 > +endif How on Earth did this break anything? All I changed was to make it as if OS=Darwin was always true... I'm going to assume that it didn't, and you just backed out the whole revision (makes sense to me), and revert your reversion of this file... Nick > > LINK_COMPONENTS := $(TARGETS_TO_BUILD) ipo scalaropts linker bitreader bitwriter > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From kremenek at apple.com Wed Feb 11 01:19:39 2009 From: kremenek at apple.com (Ted Kremenek) Date: Wed, 11 Feb 2009 07:19:39 -0000 Subject: [llvm-commits] [llvm] r64293 - /llvm/tags/checker/checker-0.154/ Message-ID: <200902110719.n1B7Jd9D009625@zion.cs.uiuc.edu> Author: kremenek Date: Wed Feb 11 01:19:38 2009 New Revision: 64293 URL: http://llvm.org/viewvc/llvm-project?rev=64293&view=rev Log: Tagging checker-0.154. Added: llvm/tags/checker/checker-0.154/ - copied from r64292, llvm/trunk/ From evan.cheng at apple.com Wed Feb 11 02:24:22 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 11 Feb 2009 08:24:22 -0000 Subject: [llvm-commits] [llvm] r64298 - in /llvm/trunk: lib/CodeGen/VirtRegMap.cpp test/CodeGen/X86/pr3495.ll Message-ID: <200902110824.n1B8OMbb011771@zion.cs.uiuc.edu> Author: evancheng Date: Wed Feb 11 02:24:21 2009 New Revision: 64298 URL: http://llvm.org/viewvc/llvm-project?rev=64298&view=rev Log: Implement PR3495: local spiller optimization. The local spiller can now keep availability information over BB boundaries. It visits BB's in depth first order. After visiting a BB if it find a successor which has a single predecessor it visits the successor next without clearing the availability information. This allows the successor to omit reloads or change them into copies. Added: llvm/trunk/test/CodeGen/X86/pr3495.ll Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=64298&r1=64297&r2=64298&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Wed Feb 11 02:24:21 2009 @@ -26,10 +26,11 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Support/CommandLine.h" -#include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" +#include "llvm/Support/Debug.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/DepthFirstIterator.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallSet.h" @@ -47,6 +48,8 @@ STATISTIC(NumDCE , "Number of copies elided"); STATISTIC(NumDSS , "Number of dead spill slots removed"); STATISTIC(NumCommutes, "Number of instructions commuted"); +STATISTIC(NumOmitted , "Number of reloads omited"); +STATISTIC(NumCopified, "Number of available reloads turned into copies"); namespace { enum SpillerName { simple, local }; @@ -308,79 +311,6 @@ // Local Spiller Implementation //===----------------------------------------------------------------------===// -namespace { - class AvailableSpills; - - /// LocalSpiller - This spiller does a simple pass over the machine basic - /// block to attempt to keep spills in registers as much as possible for - /// blocks that have low register pressure (the vreg may be spilled due to - /// register pressure in other blocks). - class VISIBILITY_HIDDEN LocalSpiller : public Spiller { - MachineRegisterInfo *RegInfo; - const TargetRegisterInfo *TRI; - const TargetInstrInfo *TII; - DenseMap DistanceMap; - public: - bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { - RegInfo = &MF.getRegInfo(); - TRI = MF.getTarget().getRegisterInfo(); - TII = MF.getTarget().getInstrInfo(); - DOUT << "\n**** Local spiller rewriting function '" - << MF.getFunction()->getName() << "':\n"; - DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)" - " ****\n"; - DEBUG(MF.dump()); - - for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); - MBB != E; ++MBB) - RewriteMBB(*MBB, VRM); - - // Mark unused spill slots. - MachineFrameInfo *MFI = MF.getFrameInfo(); - int SS = VRM.getLowSpillSlot(); - if (SS != VirtRegMap::NO_STACK_SLOT) - for (int e = VRM.getHighSpillSlot(); SS <= e; ++SS) - if (!VRM.isSpillSlotUsed(SS)) { - MFI->RemoveStackObject(SS); - ++NumDSS; - } - - DOUT << "**** Post Machine Instrs ****\n"; - DEBUG(MF.dump()); - - return true; - } - private: - void TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist, - unsigned Reg, BitVector &RegKills, - std::vector &KillOps); - bool PrepForUnfoldOpti(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MII, - std::vector &MaybeDeadStores, - AvailableSpills &Spills, BitVector &RegKills, - std::vector &KillOps, - VirtRegMap &VRM); - bool CommuteToFoldReload(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MII, - unsigned VirtReg, unsigned SrcReg, int SS, - BitVector &RegKills, - std::vector &KillOps, - const TargetRegisterInfo *TRI, - VirtRegMap &VRM); - void SpillRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MII, - int Idx, unsigned PhysReg, int StackSlot, - const TargetRegisterClass *RC, - bool isAvailable, MachineInstr *&LastStore, - AvailableSpills &Spills, - SmallSet &ReMatDefs, - BitVector &RegKills, - std::vector &KillOps, - VirtRegMap &VRM); - void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM); - }; -} - /// AvailableSpills - As the local spiller is scanning and rewriting an MBB from /// top down, keep track of which spills slots or remat are available in each /// register. @@ -415,6 +345,12 @@ AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii) : TRI(tri), TII(tii) { } + + /// clear - Reset the state. + void clear() { + SpillSlotsOrReMatsAvailable.clear(); + PhysRegsAvailable.clear(); + } const TargetRegisterInfo *getRegInfo() const { return TRI; } @@ -433,8 +369,7 @@ /// addAvailable - Mark that the specified stack slot / remat is available in /// the specified physreg. If CanClobber is true, the physreg can be modified /// at any time without changing the semantics of the program. - void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg, - bool CanClobber = true) { + void addAvailable(int SlotOrReMat, unsigned Reg, bool CanClobber = true) { // If this stack slot is thought to be available in some other physreg, // remove its record. ModifyStackSlotOrReMat(SlotOrReMat); @@ -551,7 +486,126 @@ PhysRegsAvailable.erase(I); } +static void findSinglePredSuccessor(MachineBasicBlock *MBB, + SmallVectorImpl &Succs) { + for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), + SE = MBB->succ_end(); SI != SE; ++SI) { + MachineBasicBlock *SuccMBB = *SI; + if (SuccMBB->pred_size() == 1) + Succs.push_back(SuccMBB); + } +} + +namespace { + class AvailableSpills; + + /// LocalSpiller - This spiller does a simple pass over the machine basic + /// block to attempt to keep spills in registers as much as possible for + /// blocks that have low register pressure (the vreg may be spilled due to + /// register pressure in other blocks). + class VISIBILITY_HIDDEN LocalSpiller : public Spiller { + MachineRegisterInfo *RegInfo; + const TargetRegisterInfo *TRI; + const TargetInstrInfo *TII; + DenseMap DistanceMap; + public: + bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { + RegInfo = &MF.getRegInfo(); + TRI = MF.getTarget().getRegisterInfo(); + TII = MF.getTarget().getInstrInfo(); + DOUT << "\n**** Local spiller rewriting function '" + << MF.getFunction()->getName() << "':\n"; + DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)" + " ****\n"; + DEBUG(MF.dump()); + + // Spills - Keep track of which spilled values are available in physregs + // so that we can choose to reuse the physregs instead of emitting + // reloads. This is usually refreshed per basic block. + AvailableSpills Spills(TRI, TII); + + // SingleEntrySuccs - Successor blocks which have a single predecessor. + SmallVector SinglePredSuccs; + SmallPtrSet EarlyVisited; + + // Traverse the basic blocks depth first. + MachineBasicBlock *Entry = MF.begin(); + SmallPtrSet Visited; + for (df_ext_iterator > + DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited); + DFI != E; ++DFI) { + MachineBasicBlock *MBB = *DFI; + if (!EarlyVisited.count(MBB)) + RewriteMBB(*MBB, VRM, Spills); + + // If this MBB is the only predecessor of a successor. Keep the + // availability information and visit it next. + do { + // Keep visiting single predecessor successor as long as possible. + SinglePredSuccs.clear(); + findSinglePredSuccessor(MBB, SinglePredSuccs); + if (SinglePredSuccs.empty()) + MBB = 0; + else { + // FIXME: More than one successors, each of which has MBB has + // the only predecessor. + MBB = SinglePredSuccs[0]; + if (!Visited.count(MBB) && EarlyVisited.insert(MBB)) + RewriteMBB(*MBB, VRM, Spills); + } + } while (MBB); + // Clear the availability info. + Spills.clear(); + } + + DOUT << "**** Post Machine Instrs ****\n"; + DEBUG(MF.dump()); + + // Mark unused spill slots. + MachineFrameInfo *MFI = MF.getFrameInfo(); + int SS = VRM.getLowSpillSlot(); + if (SS != VirtRegMap::NO_STACK_SLOT) + for (int e = VRM.getHighSpillSlot(); SS <= e; ++SS) + if (!VRM.isSpillSlotUsed(SS)) { + MFI->RemoveStackObject(SS); + ++NumDSS; + } + + return true; + } + private: + void TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist, + unsigned Reg, BitVector &RegKills, + std::vector &KillOps); + bool PrepForUnfoldOpti(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MII, + std::vector &MaybeDeadStores, + AvailableSpills &Spills, BitVector &RegKills, + std::vector &KillOps, + VirtRegMap &VRM); + bool CommuteToFoldReload(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MII, + unsigned VirtReg, unsigned SrcReg, int SS, + BitVector &RegKills, + std::vector &KillOps, + const TargetRegisterInfo *TRI, + VirtRegMap &VRM); + void SpillRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MII, + int Idx, unsigned PhysReg, int StackSlot, + const TargetRegisterClass *RC, + bool isAvailable, MachineInstr *&LastStore, + AvailableSpills &Spills, + SmallSet &ReMatDefs, + BitVector &RegKills, + std::vector &KillOps, + VirtRegMap &VRM); + void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM, + AvailableSpills &Spills); + }; +} /// InvalidateKills - MI is going to be deleted. If any of its operands are /// marked kill, then invalidate the information. @@ -843,7 +897,7 @@ unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) : NewPhysReg; MI->getOperand(NewOp.Operand).setReg(RReg); - Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg); + Spills.addAvailable(NewOp.StackSlotOrReMat, NewPhysReg); --MII; UpdateKills(*MII, RegKills, KillOps, TRI); DOUT << '\t' << *MII; @@ -1152,7 +1206,7 @@ // in PhysReg. Spills.ModifyStackSlotOrReMat(StackSlot); Spills.ClobberPhysReg(PhysReg); - Spills.addAvailable(StackSlot, LastStore, PhysReg, isAvailable); + Spills.addAvailable(StackSlot, PhysReg, isAvailable); ++NumStores; } @@ -1201,15 +1255,13 @@ /// rewriteMBB - Keep track of which spills are available even after the /// register allocator is done with them. If possible, avid reloading vregs. -void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { - DOUT << MBB.getBasicBlock()->getName() << ":\n"; +void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM, + AvailableSpills &Spills) { + DOUT << "\n**** Local spiller rewriting MBB '" + << MBB.getBasicBlock()->getName() << ":\n"; MachineFunction &MF = *MBB.getParent(); - // Spills - Keep track of which spilled values are available in physregs so - // that we can choose to reuse the physregs instead of emitting reloads. - AvailableSpills Spills(TRI, TII); - // MaybeDeadStores - When we need to write a value back into a stack slot, // keep track of the inserted store. If the stack slot value is never read // (because the value was used from some available register, for example), and @@ -1277,18 +1329,82 @@ continue; // Split interval spilled again. unsigned Phys = VRM.getPhys(VirtReg); RegInfo->setPhysRegUsed(Phys); + + // Check if the value being restored if available. If so, it must be + // from a predecessor BB that fallthrough into this BB. We do not + // expect: + // BB1: + // r1 = load fi#1 + // ... + // = r1 + // ... # r1 not clobbered + // ... + // = load fi#1 + bool DoReMat = VRM.isReMaterialized(VirtReg); + int SSorRMId = DoReMat + ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg); + unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId); + assert((!InReg || !RegKills[InReg]) && + "Restoring a value that's previously defined in the same BB?"); + if (InReg == Phys) { + // If the value is already available in the expected register, save + // a reload / remat. + if (SSorRMId) + DOUT << "Reusing RM#" << SSorRMId-VirtRegMap::MAX_STACK_SLOT-1; + else + DOUT << "Reusing SS#" << SSorRMId; + DOUT << " from physreg " + << TRI->getName(InReg) << " for vreg" + << VirtReg <<" instead of reloading into physreg " + << TRI->getName(Phys) << "\n"; + ++NumOmitted; + continue; + } else if (InReg && InReg != Phys) { + if (SSorRMId) + DOUT << "Reusing RM#" << SSorRMId-VirtRegMap::MAX_STACK_SLOT-1; + else + DOUT << "Reusing SS#" << SSorRMId; + DOUT << " from physreg " + << TRI->getName(InReg) << " for vreg" + << VirtReg <<" by copying it into physreg " + << TRI->getName(Phys) << "\n"; + + // If the reloaded / remat value is available in another register, + // copy it to the desired register. + const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); + TII->copyRegToReg(MBB, &MI, Phys, InReg, RC, RC); + + // This invalidates Phys. + Spills.ClobberPhysReg(Phys); + // Remember it's available. + Spills.addAvailable(SSorRMId, Phys); + + // Mark is killed. + MachineInstr *CopyMI = prior(MII); + MachineOperand *KillOpnd = CopyMI->findRegisterUseOperand(InReg); + KillOpnd->setIsKill(); + UpdateKills(*CopyMI, RegKills, KillOps, TRI); + + DOUT << '\t' << *CopyMI; + ++NumCopified; + continue; + } + if (VRM.isReMaterialized(VirtReg)) { ReMaterialize(MBB, MII, Phys, VirtReg, TII, TRI, VRM); } else { const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); - int SS = VRM.getStackSlot(VirtReg); - TII->loadRegFromStackSlot(MBB, &MI, Phys, SS, RC); + TII->loadRegFromStackSlot(MBB, &MI, Phys, SSorRMId, RC); MachineInstr *LoadMI = prior(MII); - VRM.addSpillSlotUse(SS, LoadMI); + VRM.addSpillSlotUse(SSorRMId, LoadMI); ++NumLoads; } + // This invalidates Phys. Spills.ClobberPhysReg(Phys); + // Remember it's available. + Spills.addAvailable(SSorRMId, Phys); + UpdateKills(*prior(MII), RegKills, KillOps, TRI); DOUT << '\t' << *prior(MII); } @@ -1510,7 +1626,7 @@ // This invalidates DesignatedReg. Spills.ClobberPhysReg(DesignatedReg); - Spills.addAvailable(ReuseSlot, &MI, DesignatedReg); + Spills.addAvailable(ReuseSlot, DesignatedReg); unsigned RReg = SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg; MI.getOperand(i).setReg(RReg); @@ -1548,7 +1664,7 @@ // Any stores to this stack slot are not dead anymore. if (!DoReMat) MaybeDeadStores[SSorRMId] = NULL; - Spills.addAvailable(SSorRMId, &MI, PhysReg); + Spills.addAvailable(SSorRMId, PhysReg); // Assumes this is the last use. IsKill will be unset if reg is reused // unless it's a two-address operand. if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1) @@ -1738,7 +1854,7 @@ // If the stack slot value was previously available in some other // register, change it now. Otherwise, make the register // available in PhysReg. - Spills.addAvailable(StackSlot, &MI, SrcReg, false/*!clobber*/); + Spills.addAvailable(StackSlot, SrcReg, false/*!clobber*/); } } } @@ -1788,7 +1904,7 @@ // If it is a folded reference, then it's not safe to clobber. bool Folded = FoldedSS.count(FrameIdx); // Otherwise, if it wasn't available, remember that it is now! - Spills.addAvailable(FrameIdx, &MI, DestReg, !Folded); + Spills.addAvailable(FrameIdx, DestReg, !Folded); goto ProcessNextInst; } @@ -1863,6 +1979,7 @@ } MII = NextMII; } + } llvm::Spiller* llvm::createSpiller() { Added: llvm/trunk/test/CodeGen/X86/pr3495.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr3495.ll?rev=64298&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pr3495.ll (added) +++ llvm/trunk/test/CodeGen/X86/pr3495.ll Wed Feb 11 02:24:21 2009 @@ -0,0 +1,78 @@ +; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of reloads omited} +; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of available reloads turned into copies} +; PR3495 + +target triple = "i386-pc-linux-gnu" + at x = external global [8 x i32], align 32 ; <[8 x i32]*> [#uses=1] + at rows = external global [8 x i32], align 32 ; <[8 x i32]*> [#uses=2] + at up = external global [15 x i32], align 32 ; <[15 x i32]*> [#uses=2] + at down = external global [15 x i32], align 32 ; <[15 x i32]*> [#uses=1] + +define i32 @queens(i32 %c) nounwind { +entry: + %tmp91 = add i32 %c, 1 ; [#uses=3] + %tmp135 = getelementptr [8 x i32]* @x, i32 0, i32 %tmp91 ; [#uses=1] + br label %bb + +bb: ; preds = %bb569, %entry + %r25.0.reg2mem.0 = phi i32 [ 0, %entry ], [ %indvar.next715, %bb569 ] ; [#uses=4] + %tmp27 = getelementptr [8 x i32]* @rows, i32 0, i32 %r25.0.reg2mem.0 ; [#uses=1] + %tmp28 = load i32* %tmp27, align 4 ; [#uses=1] + %tmp29 = icmp eq i32 %tmp28, 0 ; [#uses=1] + br i1 %tmp29, label %bb569, label %bb31 + +bb31: ; preds = %bb + %tmp35 = sub i32 %r25.0.reg2mem.0, 0 ; [#uses=1] + %tmp36 = getelementptr [15 x i32]* @up, i32 0, i32 %tmp35 ; [#uses=1] + %tmp37 = load i32* %tmp36, align 4 ; [#uses=1] + %tmp38 = icmp eq i32 %tmp37, 0 ; [#uses=1] + br i1 %tmp38, label %bb569, label %bb41 + +bb41: ; preds = %bb31 + %tmp54 = sub i32 %r25.0.reg2mem.0, %c ; [#uses=1] + %tmp55 = add i32 %tmp54, 7 ; [#uses=1] + %tmp62 = getelementptr [15 x i32]* @up, i32 0, i32 %tmp55 ; [#uses=2] + store i32 0, i32* %tmp62, align 4 + br label %bb92 + +bb92: ; preds = %bb545, %bb41 + %r20.0.reg2mem.0 = phi i32 [ 0, %bb41 ], [ %indvar.next711, %bb545 ] ; [#uses=5] + %tmp94 = getelementptr [8 x i32]* @rows, i32 0, i32 %r20.0.reg2mem.0 ; [#uses=1] + %tmp95 = load i32* %tmp94, align 4 ; [#uses=0] + %tmp112 = add i32 %r20.0.reg2mem.0, %tmp91 ; [#uses=1] + %tmp113 = getelementptr [15 x i32]* @down, i32 0, i32 %tmp112 ; [#uses=2] + %tmp114 = load i32* %tmp113, align 4 ; [#uses=1] + %tmp115 = icmp eq i32 %tmp114, 0 ; [#uses=1] + br i1 %tmp115, label %bb545, label %bb118 + +bb118: ; preds = %bb92 + %tmp122 = sub i32 %r20.0.reg2mem.0, %tmp91 ; [#uses=0] + store i32 0, i32* %tmp113, align 4 + store i32 %r20.0.reg2mem.0, i32* %tmp135, align 4 + br label %bb142 + +bb142: ; preds = %bb142, %bb118 + %k18.0.reg2mem.0 = phi i32 [ 0, %bb118 ], [ %indvar.next709, %bb142 ] ; [#uses=1] + %indvar.next709 = add i32 %k18.0.reg2mem.0, 1 ; [#uses=2] + %exitcond710 = icmp eq i32 %indvar.next709, 8 ; [#uses=1] + br i1 %exitcond710, label %bb155, label %bb142 + +bb155: ; preds = %bb142 + %tmp156 = tail call i32 @putchar(i32 10) nounwind ; [#uses=0] + br label %bb545 + +bb545: ; preds = %bb155, %bb92 + %indvar.next711 = add i32 %r20.0.reg2mem.0, 1 ; [#uses=2] + %exitcond712 = icmp eq i32 %indvar.next711, 8 ; [#uses=1] + br i1 %exitcond712, label %bb553, label %bb92 + +bb553: ; preds = %bb545 + store i32 1, i32* %tmp62, align 4 + br label %bb569 + +bb569: ; preds = %bb553, %bb31, %bb + %indvar.next715 = add i32 %r25.0.reg2mem.0, 1 ; [#uses=1] + br label %bb +} + +declare i32 @putchar(i32) From nicholas at mxc.ca Wed Feb 11 02:44:13 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 11 Feb 2009 08:44:13 -0000 Subject: [llvm-commits] [llvm] r64299 - in /llvm/trunk/tools: Makefile lto/Makefile Message-ID: <200902110844.n1B8iDM0014795@zion.cs.uiuc.edu> Author: nicholas Date: Wed Feb 11 02:44:13 2009 New Revision: 64299 URL: http://llvm.org/viewvc/llvm-project?rev=64299&view=rev Log: Try this. Darwin -> LTO, PIC -> LTO + possibly gold too. Modified: llvm/trunk/tools/Makefile llvm/trunk/tools/lto/Makefile Modified: llvm/trunk/tools/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/Makefile?rev=64299&r1=64298&r2=64299&view=diff ============================================================================== --- llvm/trunk/tools/Makefile (original) +++ llvm/trunk/tools/Makefile Wed Feb 11 02:44:13 2009 @@ -25,10 +25,11 @@ include $(LEVEL)/Makefile.config -# only build new lto project on Darwin for now +# build lto project on Darwin or if PIC is enabled ifeq ($(OS),Darwin) PARALLEL_DIRS += lto - +else ($(ENABLE_PIC),1) +PARALLEL_DIRS += lto ifdef BINUTILS_INCDIR PARALLEL_DIRS += gold endif Modified: llvm/trunk/tools/lto/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/Makefile?rev=64299&r1=64298&r2=64299&view=diff ============================================================================== --- llvm/trunk/tools/lto/Makefile (original) +++ llvm/trunk/tools/lto/Makefile Wed Feb 11 02:44:13 2009 @@ -16,12 +16,8 @@ include $(LEVEL)/Makefile.config LINK_LIBS_IN_SHARED = 1 -ifeq ($(OS),Darwin) - SHARED_LIBRARY = 1 - DONT_BUILD_RELINKED = 1 -else - BUILD_ARCHIVE = 1 -endif +SHARED_LIBRARY = 1 +DONT_BUILD_RELINKED = 1 LINK_COMPONENTS := $(TARGETS_TO_BUILD) ipo scalaropts linker bitreader bitwriter From baldrick at free.fr Wed Feb 11 03:58:43 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 11 Feb 2009 09:58:43 -0000 Subject: [llvm-commits] [llvm] r64300 - in /llvm/trunk: lib/Analysis/IPA/CallGraphSCCPass.cpp test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll Message-ID: <200902110958.n1B9wiM7024990@zion.cs.uiuc.edu> Author: baldrick Date: Wed Feb 11 03:58:43 2009 New Revision: 64300 URL: http://llvm.org/viewvc/llvm-project?rev=64300&view=rev Log: Make sure the SCC pass manager initializes any contained function pass managers. Without this, simplify-libcalls would add nocapture attributes when run on its own, but not when run as part of -std-compile-opts or similar. Added: llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll Modified: llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp Modified: llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp?rev=64300&r1=64299&r2=64300&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp (original) +++ llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp Wed Feb 11 03:58:43 2009 @@ -40,8 +40,8 @@ /// whether any of the passes modifies the module, and if so, return true. bool runOnModule(Module &M); - bool doInitialization(CallGraph &CG); - bool doFinalization(CallGraph &CG); + bool doInitialization(CallGraph &CG, Module &M); + bool doFinalization(CallGraph &CG, Module &M); /// Pass Manager itself does not invalidate any analysis info. void getAnalysisUsage(AnalysisUsage &Info) const { @@ -82,7 +82,7 @@ /// whether any of the passes modifies the module, and if so, return true. bool CGPassManager::runOnModule(Module &M) { CallGraph &CG = getAnalysis(); - bool Changed = doInitialization(CG); + bool Changed = doInitialization(CG, M); // Walk SCC for (scc_iterator I = scc_begin(&CG), E = scc_end(&CG); @@ -126,28 +126,38 @@ removeDeadPasses(P, "", ON_CG_MSG); } } - Changed |= doFinalization(CG); + Changed |= doFinalization(CG, M); return Changed; } /// Initialize CG -bool CGPassManager::doInitialization(CallGraph &CG) { +bool CGPassManager::doInitialization(CallGraph &CG, Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { Pass *P = getContainedPass(Index); - if (CallGraphSCCPass *CGSP = dynamic_cast(P)) + if (CallGraphSCCPass *CGSP = dynamic_cast(P)) { Changed |= CGSP->doInitialization(CG); + } else { + FPPassManager *FP = dynamic_cast(P); + assert (FP && "Invalid CGPassManager member"); + Changed |= FP->doInitialization(M); + } } return Changed; } /// Finalize CG -bool CGPassManager::doFinalization(CallGraph &CG) { +bool CGPassManager::doFinalization(CallGraph &CG, Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { Pass *P = getContainedPass(Index); - if (CallGraphSCCPass *CGSP = dynamic_cast(P)) + if (CallGraphSCCPass *CGSP = dynamic_cast(P)) { Changed |= CGSP->doFinalization(CG); + } else { + FPPassManager *FP = dynamic_cast(P); + assert (FP && "Invalid CGPassManager member"); + Changed |= FP->doFinalization(M); + } } return Changed; } Added: llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll?rev=64300&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll (added) +++ llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll Wed Feb 11 03:58:43 2009 @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | opt -std-compile-opts | llvm-dis | grep nocapture | count 2 +; Check that nocapture attributes are added when run after an SCC pass. +; PR3520 + +define i32 @use(i8* %x) nounwind readonly { +entry: + %0 = tail call i64 @strlen(i8* %x) nounwind readonly ; [#uses=1] + %1 = trunc i64 %0 to i32 ; [#uses=1] + ret i32 %1 +} + +declare i64 @strlen(i8*) nounwind readonly From baldrick at free.fr Wed Feb 11 06:25:22 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 11 Feb 2009 12:25:22 -0000 Subject: [llvm-commits] [llvm] r64301 - /llvm/trunk/lib/VMCore/PassManager.cpp Message-ID: <200902111225.n1BCPO39030405@zion.cs.uiuc.edu> Author: baldrick Date: Wed Feb 11 06:25:15 2009 New Revision: 64301 URL: http://llvm.org/viewvc/llvm-project?rev=64301&view=rev Log: These uses of "inline" can cause strange link-time failures when building with optimization. Just get rid of them. Modified: llvm/trunk/lib/VMCore/PassManager.cpp Modified: llvm/trunk/lib/VMCore/PassManager.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=64301&r1=64300&r2=64301&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassManager.cpp (original) +++ llvm/trunk/lib/VMCore/PassManager.cpp Wed Feb 11 06:25:15 2009 @@ -1140,7 +1140,7 @@ } // Implement doInitialization and doFinalization -inline bool BBPassManager::doInitialization(Module &M) { +bool BBPassManager::doInitialization(Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { @@ -1151,7 +1151,7 @@ return Changed; } -inline bool BBPassManager::doFinalization(Module &M) { +bool BBPassManager::doFinalization(Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { @@ -1162,7 +1162,7 @@ return Changed; } -inline bool BBPassManager::doInitialization(Function &F) { +bool BBPassManager::doInitialization(Function &F) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { @@ -1173,7 +1173,7 @@ return Changed; } -inline bool BBPassManager::doFinalization(Function &F) { +bool BBPassManager::doFinalization(Function &F) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { @@ -1242,7 +1242,7 @@ //===----------------------------------------------------------------------===// // FunctionPassManagerImpl implementation // -inline bool FunctionPassManagerImpl::doInitialization(Module &M) { +bool FunctionPassManagerImpl::doInitialization(Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedManagers(); ++Index) { @@ -1253,7 +1253,7 @@ return Changed; } -inline bool FunctionPassManagerImpl::doFinalization(Module &M) { +bool FunctionPassManagerImpl::doFinalization(Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedManagers(); ++Index) { @@ -1348,7 +1348,7 @@ return Changed |= doFinalization(M); } -inline bool FPPassManager::doInitialization(Module &M) { +bool FPPassManager::doInitialization(Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { @@ -1359,7 +1359,7 @@ return Changed; } -inline bool FPPassManager::doFinalization(Module &M) { +bool FPPassManager::doFinalization(Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { From baldrick at free.fr Wed Feb 11 07:23:53 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 11 Feb 2009 13:23:53 -0000 Subject: [llvm-commits] [llvm] r64302 - in /llvm/trunk/tools: Makefile lto/Makefile Message-ID: <200902111323.n1BDNs0K032485@zion.cs.uiuc.edu> Author: baldrick Date: Wed Feb 11 07:23:49 2009 New Revision: 64302 URL: http://llvm.org/viewvc/llvm-project?rev=64302&view=rev Log: Revert r64299: it breaks the build when configured without --enable-pic, like my nightly tester. Modified: llvm/trunk/tools/Makefile llvm/trunk/tools/lto/Makefile Modified: llvm/trunk/tools/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/Makefile?rev=64302&r1=64301&r2=64302&view=diff ============================================================================== --- llvm/trunk/tools/Makefile (original) +++ llvm/trunk/tools/Makefile Wed Feb 11 07:23:49 2009 @@ -25,11 +25,10 @@ include $(LEVEL)/Makefile.config -# build lto project on Darwin or if PIC is enabled +# only build new lto project on Darwin for now ifeq ($(OS),Darwin) PARALLEL_DIRS += lto -else ($(ENABLE_PIC),1) -PARALLEL_DIRS += lto + ifdef BINUTILS_INCDIR PARALLEL_DIRS += gold endif Modified: llvm/trunk/tools/lto/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/Makefile?rev=64302&r1=64301&r2=64302&view=diff ============================================================================== --- llvm/trunk/tools/lto/Makefile (original) +++ llvm/trunk/tools/lto/Makefile Wed Feb 11 07:23:49 2009 @@ -16,8 +16,12 @@ include $(LEVEL)/Makefile.config LINK_LIBS_IN_SHARED = 1 -SHARED_LIBRARY = 1 -DONT_BUILD_RELINKED = 1 +ifeq ($(OS),Darwin) + SHARED_LIBRARY = 1 + DONT_BUILD_RELINKED = 1 +else + BUILD_ARCHIVE = 1 +endif LINK_COMPONENTS := $(TARGETS_TO_BUILD) ipo scalaropts linker bitreader bitwriter From nicholas at mxc.ca Wed Feb 11 11:24:32 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 11 Feb 2009 09:24:32 -0800 Subject: [llvm-commits] [llvm] r64300 - in /llvm/trunk: lib/Analysis/IPA/CallGraphSCCPass.cpp test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll In-Reply-To: <200902110958.n1B9wiM7024990@zion.cs.uiuc.edu> References: <200902110958.n1B9wiM7024990@zion.cs.uiuc.edu> Message-ID: <499309D0.4050706@mxc.ca> Duncan Sands wrote: > Author: baldrick > Date: Wed Feb 11 03:58:43 2009 > New Revision: 64300 > > URL: http://llvm.org/viewvc/llvm-project?rev=64300&view=rev > Log: > Make sure the SCC pass manager initializes any contained > function pass managers. Without this, simplify-libcalls > would add nocapture attributes when run on its own, but > not when run as part of -std-compile-opts or similar. Thanks for fixing this! > Added: > llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll > Modified: > llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp > > Modified: llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp?rev=64300&r1=64299&r2=64300&view=diff > > ============================================================================== > --- llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp (original) > +++ llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp Wed Feb 11 03:58:43 2009 > @@ -40,8 +40,8 @@ > /// whether any of the passes modifies the module, and if so, return true. > bool runOnModule(Module &M); > > - bool doInitialization(CallGraph &CG); > - bool doFinalization(CallGraph &CG); > + bool doInitialization(CallGraph &CG, Module &M); > + bool doFinalization(CallGraph &CG, Module &M); > > /// Pass Manager itself does not invalidate any analysis info. > void getAnalysisUsage(AnalysisUsage &Info) const { > @@ -82,7 +82,7 @@ > /// whether any of the passes modifies the module, and if so, return true. > bool CGPassManager::runOnModule(Module &M) { > CallGraph &CG = getAnalysis(); > - bool Changed = doInitialization(CG); > + bool Changed = doInitialization(CG, M); > > // Walk SCC > for (scc_iterator I = scc_begin(&CG), E = scc_end(&CG); > @@ -126,28 +126,38 @@ > removeDeadPasses(P, "", ON_CG_MSG); > } > } > - Changed |= doFinalization(CG); > + Changed |= doFinalization(CG, M); > return Changed; > } > > /// Initialize CG > -bool CGPassManager::doInitialization(CallGraph &CG) { > +bool CGPassManager::doInitialization(CallGraph &CG, Module &M) { > bool Changed = false; > for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { > Pass *P = getContainedPass(Index); > - if (CallGraphSCCPass *CGSP = dynamic_cast(P)) > + if (CallGraphSCCPass *CGSP = dynamic_cast(P)) { > Changed |= CGSP->doInitialization(CG); > + } else { > + FPPassManager *FP = dynamic_cast(P); > + assert (FP && "Invalid CGPassManager member"); > + Changed |= FP->doInitialization(M); I think you should just use CG.getModule() instead of passing the Module around. > + } > } > return Changed; > } > > /// Finalize CG > -bool CGPassManager::doFinalization(CallGraph &CG) { > +bool CGPassManager::doFinalization(CallGraph &CG, Module &M) { > bool Changed = false; > for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { > Pass *P = getContainedPass(Index); > - if (CallGraphSCCPass *CGSP = dynamic_cast(P)) > + if (CallGraphSCCPass *CGSP = dynamic_cast(P)) { > Changed |= CGSP->doFinalization(CG); > + } else { > + FPPassManager *FP = dynamic_cast(P); > + assert (FP && "Invalid CGPassManager member"); > + Changed |= FP->doFinalization(M); > + } > } > return Changed; > } > > Added: llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll?rev=64300&view=auto > > ============================================================================== > --- llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll (added) > +++ llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll Wed Feb 11 03:58:43 2009 > @@ -0,0 +1,12 @@ > +; RUN: llvm-as < %s | opt -std-compile-opts | llvm-dis | grep nocapture | count 2 > +; Check that nocapture attributes are added when run after an SCC pass. How about just '-inline -simplify-libcalls'? -std-compile-opts is slow enough that it should be avoided whenever possible. Nick > +; PR3520 > + > +define i32 @use(i8* %x) nounwind readonly { > +entry: > + %0 = tail call i64 @strlen(i8* %x) nounwind readonly ; [#uses=1] > + %1 = trunc i64 %0 to i32 ; [#uses=1] > + ret i32 %1 > +} > + > +declare i64 @strlen(i8*) nounwind readonly > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From clattner at apple.com Wed Feb 11 12:07:53 2009 From: clattner at apple.com (Chris Lattner) Date: Wed, 11 Feb 2009 10:07:53 -0800 Subject: [llvm-commits] [llvm] r64300 - in /llvm/trunk: lib/Analysis/IPA/CallGraphSCCPass.cpp test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll In-Reply-To: <499309D0.4050706@mxc.ca> References: <200902110958.n1B9wiM7024990@zion.cs.uiuc.edu> <499309D0.4050706@mxc.ca> Message-ID: <8E01C83D-91FE-48C1-85EA-782A97E33F50@apple.com> On Feb 11, 2009, at 9:24 AM, Nick Lewycky wrote: >> +++ llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11- >> NotInitialized.ll Wed Feb 11 03:58:43 2009 >> @@ -0,0 +1,12 @@ >> +; RUN: llvm-as < %s | opt -std-compile-opts | llvm-dis | grep >> nocapture | count 2 >> +; Check that nocapture attributes are added when run after an SCC >> pass. > > How about just '-inline -simplify-libcalls'? -std-compile-opts is slow > enough that it should be avoided whenever possible. Right, beyond that, its definition changes. Please don't use -std- compile-opts in a testcase, thanks! -Chris From isanbard at gmail.com Wed Feb 11 12:13:05 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 11 Feb 2009 18:13:05 -0000 Subject: [llvm-commits] [llvm] r64309 - in /llvm/branches/Apple/Dib/tools: Makefile lto/Makefile Message-ID: <200902111813.n1BID5VF010007@zion.cs.uiuc.edu> Author: void Date: Wed Feb 11 12:13:05 2009 New Revision: 64309 URL: http://llvm.org/viewvc/llvm-project?rev=64309&view=rev Log: Pull r64285 into Dib: 62987 disables LTO build on darwin. Revert 62987 for now. Nicolas please investigate. Modified: llvm/branches/Apple/Dib/tools/Makefile llvm/branches/Apple/Dib/tools/lto/Makefile Modified: llvm/branches/Apple/Dib/tools/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/tools/Makefile?rev=64309&r1=64308&r2=64309&view=diff ============================================================================== --- llvm/branches/Apple/Dib/tools/Makefile (original) +++ llvm/branches/Apple/Dib/tools/Makefile Wed Feb 11 12:13:05 2009 @@ -25,7 +25,8 @@ include $(LEVEL)/Makefile.config -ifeq ($(ENABLE_PIC),1) +# only build new lto project on Darwin for now +ifeq ($(OS),Darwin) PARALLEL_DIRS += lto endif Modified: llvm/branches/Apple/Dib/tools/lto/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/tools/lto/Makefile?rev=64309&r1=64308&r2=64309&view=diff ============================================================================== --- llvm/branches/Apple/Dib/tools/lto/Makefile (original) +++ llvm/branches/Apple/Dib/tools/lto/Makefile Wed Feb 11 12:13:05 2009 @@ -16,8 +16,12 @@ include $(LEVEL)/Makefile.config LINK_LIBS_IN_SHARED = 1 -SHARED_LIBRARY = 1 -DONT_BUILD_RELINKED = 1 +ifeq ($(OS),Darwin) + SHARED_LIBRARY = 1 + DONT_BUILD_RELINKED = 1 +else + BUILD_ARCHIVE = 1 +endif LINK_COMPONENTS := $(TARGETS_TO_BUILD) ipo scalaropts linker bitreader bitwriter From isanbard at gmail.com Wed Feb 11 12:19:25 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 11 Feb 2009 18:19:25 -0000 Subject: [llvm-commits] [llvm] r64311 - in /llvm/trunk: lib/Analysis/IPA/CallGraphSCCPass.cpp lib/VMCore/PassManager.cpp test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll Message-ID: <200902111819.n1BIJPCL010238@zion.cs.uiuc.edu> Author: void Date: Wed Feb 11 12:19:24 2009 New Revision: 64311 URL: http://llvm.org/viewvc/llvm-project?rev=64311&view=rev Log: Revert r64300 and r64301. These were causing the following errors respectively: During llvm-gcc bootstrap: Undefined symbols: "llvm::FPPassManager::doFinalization(llvm::Module&)", referenced from: (anonymous namespace)::CGPassManager::doFinalization(llvm::CallGraph&, llvm::Module&) in libLLVMipa.a(CallGraphSCCPass.o) "llvm::FPPassManager::doInitialization(llvm::Module&)", referenced from: (anonymous namespace)::CGPassManager::doInitialization(llvm::CallGraph&, llvm::Module&) in libLLVMipa.a(CallGraphSCCPass.o) ld: symbol(s) not found collect2: ld returned 1 exit status make[3]: *** [/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore.roots/llvmCore~obj/obj-llvm/Release/bin/opt] Error 1 During an LLVM release build: /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/Release/bin/tblgen -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target/X86 -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target -gen-register-desc -o /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Target/X86/Release/X86GenRegisterInfo.inc.tmp /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target/X86/X86.td llvm[3]: Building X86.td instruction names with tblgen /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/Release/bin/tblgen -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target/X86 -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target -gen-instr-enums -o /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Target/X86/Release/X86GenInstrNames.inc.tmp /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target/X86/X86.td llvm[3]: Building X86.td instruction information with tblgen /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/Release/bin/tblgen -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target/X86 -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target -gen-instr-desc -o /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Target/X86/Release/X86GenInstrInfo.inc.tmp /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target/X86/X86.td llvm[3]: Building X86.td assembly writer with tblgen /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/Release/bin/tblgen -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target/X86 -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target -gen-asm-writer -o /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Target/X86/Release/X86GenAsmWriter.inc.tmp /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target/X86/X86.td llvm[3]: Compiling InstructionCombining.cpp for Release build if /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~dst/Developer/usr/bin/llvm-g++-4.2 -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/include -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Transforms/Scalar -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Transforms/Scalar -D_DEBUG -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -O3 -fno-exceptions -Woverloaded-virtual -pedantic -Wall -W -Wwrite-strings -Wno-long-long -Wunused -Wno-unused-parameter -fstrict-aliasing -Wstrict-aliasing -c -MMD -MP -MF "/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Transforms/Scalar/Release/InstructionCombining.d.tmp" -MT "/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Transforms/Scalar/Release/InstructionCombining.lo" -MT "/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Transforms/Scala! r/Release/InstructionCombining.o" -MT "/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Transforms/Scalar/Release/InstructionCombining.d" /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Transforms/Scalar/InstructionCombining.cpp -o /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Transforms/Scalar/Release/InstructionCombining.o ; \ then /bin/mv -f "/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Transforms/Scalar/Release/InstructionCombining.d.tmp" "/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Trans Modified: llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp llvm/trunk/lib/VMCore/PassManager.cpp llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll Modified: llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp?rev=64311&r1=64310&r2=64311&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp (original) +++ llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp Wed Feb 11 12:19:24 2009 @@ -40,8 +40,8 @@ /// whether any of the passes modifies the module, and if so, return true. bool runOnModule(Module &M); - bool doInitialization(CallGraph &CG, Module &M); - bool doFinalization(CallGraph &CG, Module &M); + bool doInitialization(CallGraph &CG); + bool doFinalization(CallGraph &CG); /// Pass Manager itself does not invalidate any analysis info. void getAnalysisUsage(AnalysisUsage &Info) const { @@ -82,7 +82,7 @@ /// whether any of the passes modifies the module, and if so, return true. bool CGPassManager::runOnModule(Module &M) { CallGraph &CG = getAnalysis(); - bool Changed = doInitialization(CG, M); + bool Changed = doInitialization(CG); // Walk SCC for (scc_iterator I = scc_begin(&CG), E = scc_end(&CG); @@ -126,38 +126,28 @@ removeDeadPasses(P, "", ON_CG_MSG); } } - Changed |= doFinalization(CG, M); + Changed |= doFinalization(CG); return Changed; } /// Initialize CG -bool CGPassManager::doInitialization(CallGraph &CG, Module &M) { +bool CGPassManager::doInitialization(CallGraph &CG) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { Pass *P = getContainedPass(Index); - if (CallGraphSCCPass *CGSP = dynamic_cast(P)) { + if (CallGraphSCCPass *CGSP = dynamic_cast(P)) Changed |= CGSP->doInitialization(CG); - } else { - FPPassManager *FP = dynamic_cast(P); - assert (FP && "Invalid CGPassManager member"); - Changed |= FP->doInitialization(M); - } } return Changed; } /// Finalize CG -bool CGPassManager::doFinalization(CallGraph &CG, Module &M) { +bool CGPassManager::doFinalization(CallGraph &CG) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { Pass *P = getContainedPass(Index); - if (CallGraphSCCPass *CGSP = dynamic_cast(P)) { + if (CallGraphSCCPass *CGSP = dynamic_cast(P)) Changed |= CGSP->doFinalization(CG); - } else { - FPPassManager *FP = dynamic_cast(P); - assert (FP && "Invalid CGPassManager member"); - Changed |= FP->doFinalization(M); - } } return Changed; } Modified: llvm/trunk/lib/VMCore/PassManager.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=64311&r1=64310&r2=64311&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassManager.cpp (original) +++ llvm/trunk/lib/VMCore/PassManager.cpp Wed Feb 11 12:19:24 2009 @@ -1140,7 +1140,7 @@ } // Implement doInitialization and doFinalization -bool BBPassManager::doInitialization(Module &M) { +inline bool BBPassManager::doInitialization(Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { @@ -1151,7 +1151,7 @@ return Changed; } -bool BBPassManager::doFinalization(Module &M) { +inline bool BBPassManager::doFinalization(Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { @@ -1162,7 +1162,7 @@ return Changed; } -bool BBPassManager::doInitialization(Function &F) { +inline bool BBPassManager::doInitialization(Function &F) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { @@ -1173,7 +1173,7 @@ return Changed; } -bool BBPassManager::doFinalization(Function &F) { +inline bool BBPassManager::doFinalization(Function &F) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { @@ -1242,7 +1242,7 @@ //===----------------------------------------------------------------------===// // FunctionPassManagerImpl implementation // -bool FunctionPassManagerImpl::doInitialization(Module &M) { +inline bool FunctionPassManagerImpl::doInitialization(Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedManagers(); ++Index) { @@ -1253,7 +1253,7 @@ return Changed; } -bool FunctionPassManagerImpl::doFinalization(Module &M) { +inline bool FunctionPassManagerImpl::doFinalization(Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedManagers(); ++Index) { @@ -1348,7 +1348,7 @@ return Changed |= doFinalization(M); } -bool FPPassManager::doInitialization(Module &M) { +inline bool FPPassManager::doInitialization(Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { @@ -1359,7 +1359,7 @@ return Changed; } -bool FPPassManager::doFinalization(Module &M) { +inline bool FPPassManager::doFinalization(Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll?rev=64311&r1=64310&r2=64311&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll (original) +++ llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll Wed Feb 11 12:19:24 2009 @@ -1,6 +1,7 @@ ; RUN: llvm-as < %s | opt -std-compile-opts | llvm-dis | grep nocapture | count 2 ; Check that nocapture attributes are added when run after an SCC pass. ; PR3520 +; XFAIL: * define i32 @use(i8* %x) nounwind readonly { entry: From isanbard at gmail.com Wed Feb 11 12:20:15 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 11 Feb 2009 10:20:15 -0800 Subject: [llvm-commits] [llvm] r64301 - /llvm/trunk/lib/VMCore/PassManager.cpp In-Reply-To: <200902111225.n1BCPO39030405@zion.cs.uiuc.edu> References: <200902111225.n1BCPO39030405@zion.cs.uiuc.edu> Message-ID: <16e5fdf90902111020s2bfbdc1aid20241d3363980e6@mail.gmail.com> Duncan, This and 64300 were breaking the builds. I reverted them and put the compilation errors in the "Log" field. Please investigate them. Thanks! -bw On Wed, Feb 11, 2009 at 4:25 AM, Duncan Sands wrote: > Author: baldrick > Date: Wed Feb 11 06:25:15 2009 > New Revision: 64301 > > URL: http://llvm.org/viewvc/llvm-project?rev=64301&view=rev > Log: > These uses of "inline" can cause strange link-time > failures when building with optimization. Just get > rid of them. > > Modified: > llvm/trunk/lib/VMCore/PassManager.cpp > > Modified: llvm/trunk/lib/VMCore/PassManager.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=64301&r1=64300&r2=64301&view=diff > > ============================================================================== > --- llvm/trunk/lib/VMCore/PassManager.cpp (original) > +++ llvm/trunk/lib/VMCore/PassManager.cpp Wed Feb 11 06:25:15 2009 > @@ -1140,7 +1140,7 @@ > } > > // Implement doInitialization and doFinalization > -inline bool BBPassManager::doInitialization(Module &M) { > +bool BBPassManager::doInitialization(Module &M) { > bool Changed = false; > > for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { > @@ -1151,7 +1151,7 @@ > return Changed; > } > > -inline bool BBPassManager::doFinalization(Module &M) { > +bool BBPassManager::doFinalization(Module &M) { > bool Changed = false; > > for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { > @@ -1162,7 +1162,7 @@ > return Changed; > } > > -inline bool BBPassManager::doInitialization(Function &F) { > +bool BBPassManager::doInitialization(Function &F) { > bool Changed = false; > > for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { > @@ -1173,7 +1173,7 @@ > return Changed; > } > > -inline bool BBPassManager::doFinalization(Function &F) { > +bool BBPassManager::doFinalization(Function &F) { > bool Changed = false; > > for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { > @@ -1242,7 +1242,7 @@ > //===----------------------------------------------------------------------===// > // FunctionPassManagerImpl implementation > // > -inline bool FunctionPassManagerImpl::doInitialization(Module &M) { > +bool FunctionPassManagerImpl::doInitialization(Module &M) { > bool Changed = false; > > for (unsigned Index = 0; Index < getNumContainedManagers(); ++Index) { > @@ -1253,7 +1253,7 @@ > return Changed; > } > > -inline bool FunctionPassManagerImpl::doFinalization(Module &M) { > +bool FunctionPassManagerImpl::doFinalization(Module &M) { > bool Changed = false; > > for (unsigned Index = 0; Index < getNumContainedManagers(); ++Index) { > @@ -1348,7 +1348,7 @@ > return Changed |= doFinalization(M); > } > > -inline bool FPPassManager::doInitialization(Module &M) { > +bool FPPassManager::doInitialization(Module &M) { > bool Changed = false; > > for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { > @@ -1359,7 +1359,7 @@ > return Changed; > } > > -inline bool FPPassManager::doFinalization(Module &M) { > +bool FPPassManager::doFinalization(Module &M) { > bool Changed = false; > > for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From isanbard at gmail.com Wed Feb 11 12:24:10 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 11 Feb 2009 10:24:10 -0800 Subject: [llvm-commits] [llvm] r64311 - in /llvm/trunk: lib/Analysis/IPA/CallGraphSCCPass.cpp lib/VMCore/PassManager.cpp test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll In-Reply-To: <200902111819.n1BIJPCL010238@zion.cs.uiuc.edu> References: <200902111819.n1BIJPCL010238@zion.cs.uiuc.edu> Message-ID: <16e5fdf90902111024r42cd4fafma73cf49f2ecc1014@mail.gmail.com> The second failure has this error message: tblgen: for the -asmwriternum option: : '1' value invalid for uint argument! make[3]: *** [/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Target/X86/Release/X86GenAsmWriter1.inc.tmp] Error 1 make[2]: *** [X86/.makeall] Error 2 make[1]: *** [Target/.makeall] Error 2 make[1]: *** Waiting for unfinished jobs.... On Wed, Feb 11, 2009 at 10:19 AM, Bill Wendling wrote: > Author: void > Date: Wed Feb 11 12:19:24 2009 > New Revision: 64311 > > URL: http://llvm.org/viewvc/llvm-project?rev=64311&view=rev > Log: > Revert r64300 and r64301. These were causing the following errors respectively: > > During llvm-gcc bootstrap: > > Undefined symbols: > "llvm::FPPassManager::doFinalization(llvm::Module&)", referenced from: > (anonymous namespace)::CGPassManager::doFinalization(llvm::CallGraph&, llvm::Module&) > in libLLVMipa.a(CallGraphSCCPass.o) > "llvm::FPPassManager::doInitialization(llvm::Module&)", referenced from: > (anonymous namespace)::CGPassManager::doInitialization(llvm::CallGraph&, llvm::Module&) > in libLLVMipa.a(CallGraphSCCPass.o) > ld: symbol(s) not found > collect2: ld returned 1 exit status > make[3]: *** [/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore.roots/llvmCore~obj/obj-llvm/Release/bin/opt] Error 1 > > During an LLVM release build: > > /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/Release/bin/tblgen -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target/X86 -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target -gen-register-desc -o /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Target/X86/Release/X86GenRegisterInfo.inc.tmp /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target/X86/X86.td > llvm[3]: Building X86.td instruction names with tblgen > /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/Release/bin/tblgen -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target/X86 -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target -gen-instr-enums -o /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Target/X86/Release/X86GenInstrNames.inc.tmp /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target/X86/X86.td > llvm[3]: Building X86.td instruction information with tblgen > /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/Release/bin/tblgen -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target/X86 -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target -gen-instr-desc -o /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Target/X86/Release/X86GenInstrInfo.inc.tmp /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target/X86/X86.td > llvm[3]: Building X86.td assembly writer with tblgen > /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/Release/bin/tblgen -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target/X86 -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include -I /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target -gen-asm-writer -o /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Target/X86/Release/X86GenAsmWriter.inc.tmp /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Target/X86/X86.td > llvm[3]: Compiling InstructionCombining.cpp for Release build > if /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~dst/Developer/usr/bin/llvm-g++-4.2 -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/include -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Transforms/Scalar -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include -I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Transforms/Scalar -D_DEBUG -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -O3 -fno-exceptions -Woverloaded-virtual -pedantic -Wall -W -Wwrite-strings -Wno-long-long -Wunused -Wno-unused-parameter -fstrict-aliasing -Wstrict-aliasing -c -MMD -MP -MF "/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Transforms/Scalar/Release/InstructionCombining.d.tmp" -MT "/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Transforms/Scalar/Release/InstructionCombining.lo" -MT "/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Transforms/Scala! > r/Release/InstructionCombining.o" -MT "/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Transforms/Scalar/Release/InstructionCombining.d" /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Transforms/Scalar/InstructionCombining.cpp -o /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Transforms/Scalar/Release/InstructionCombining.o ; \ > then /bin/mv -f "/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Transforms/Scalar/Release/InstructionCombining.d.tmp" "/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Trans > > > Modified: > llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp > llvm/trunk/lib/VMCore/PassManager.cpp > llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll > > Modified: llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp?rev=64311&r1=64310&r2=64311&view=diff > > ============================================================================== > --- llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp (original) > +++ llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp Wed Feb 11 12:19:24 2009 > @@ -40,8 +40,8 @@ > /// whether any of the passes modifies the module, and if so, return true. > bool runOnModule(Module &M); > > - bool doInitialization(CallGraph &CG, Module &M); > - bool doFinalization(CallGraph &CG, Module &M); > + bool doInitialization(CallGraph &CG); > + bool doFinalization(CallGraph &CG); > > /// Pass Manager itself does not invalidate any analysis info. > void getAnalysisUsage(AnalysisUsage &Info) const { > @@ -82,7 +82,7 @@ > /// whether any of the passes modifies the module, and if so, return true. > bool CGPassManager::runOnModule(Module &M) { > CallGraph &CG = getAnalysis(); > - bool Changed = doInitialization(CG, M); > + bool Changed = doInitialization(CG); > > // Walk SCC > for (scc_iterator I = scc_begin(&CG), E = scc_end(&CG); > @@ -126,38 +126,28 @@ > removeDeadPasses(P, "", ON_CG_MSG); > } > } > - Changed |= doFinalization(CG, M); > + Changed |= doFinalization(CG); > return Changed; > } > > /// Initialize CG > -bool CGPassManager::doInitialization(CallGraph &CG, Module &M) { > +bool CGPassManager::doInitialization(CallGraph &CG) { > bool Changed = false; > for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { > Pass *P = getContainedPass(Index); > - if (CallGraphSCCPass *CGSP = dynamic_cast(P)) { > + if (CallGraphSCCPass *CGSP = dynamic_cast(P)) > Changed |= CGSP->doInitialization(CG); > - } else { > - FPPassManager *FP = dynamic_cast(P); > - assert (FP && "Invalid CGPassManager member"); > - Changed |= FP->doInitialization(M); > - } > } > return Changed; > } > > /// Finalize CG > -bool CGPassManager::doFinalization(CallGraph &CG, Module &M) { > +bool CGPassManager::doFinalization(CallGraph &CG) { > bool Changed = false; > for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { > Pass *P = getContainedPass(Index); > - if (CallGraphSCCPass *CGSP = dynamic_cast(P)) { > + if (CallGraphSCCPass *CGSP = dynamic_cast(P)) > Changed |= CGSP->doFinalization(CG); > - } else { > - FPPassManager *FP = dynamic_cast(P); > - assert (FP && "Invalid CGPassManager member"); > - Changed |= FP->doFinalization(M); > - } > } > return Changed; > } > > Modified: llvm/trunk/lib/VMCore/PassManager.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=64311&r1=64310&r2=64311&view=diff > > ============================================================================== > --- llvm/trunk/lib/VMCore/PassManager.cpp (original) > +++ llvm/trunk/lib/VMCore/PassManager.cpp Wed Feb 11 12:19:24 2009 > @@ -1140,7 +1140,7 @@ > } > > // Implement doInitialization and doFinalization > -bool BBPassManager::doInitialization(Module &M) { > +inline bool BBPassManager::doInitialization(Module &M) { > bool Changed = false; > > for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { > @@ -1151,7 +1151,7 @@ > return Changed; > } > > -bool BBPassManager::doFinalization(Module &M) { > +inline bool BBPassManager::doFinalization(Module &M) { > bool Changed = false; > > for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { > @@ -1162,7 +1162,7 @@ > return Changed; > } > > -bool BBPassManager::doInitialization(Function &F) { > +inline bool BBPassManager::doInitialization(Function &F) { > bool Changed = false; > > for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { > @@ -1173,7 +1173,7 @@ > return Changed; > } > > -bool BBPassManager::doFinalization(Function &F) { > +inline bool BBPassManager::doFinalization(Function &F) { > bool Changed = false; > > for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { > @@ -1242,7 +1242,7 @@ > //===----------------------------------------------------------------------===// > // FunctionPassManagerImpl implementation > // > -bool FunctionPassManagerImpl::doInitialization(Module &M) { > +inline bool FunctionPassManagerImpl::doInitialization(Module &M) { > bool Changed = false; > > for (unsigned Index = 0; Index < getNumContainedManagers(); ++Index) { > @@ -1253,7 +1253,7 @@ > return Changed; > } > > -bool FunctionPassManagerImpl::doFinalization(Module &M) { > +inline bool FunctionPassManagerImpl::doFinalization(Module &M) { > bool Changed = false; > > for (unsigned Index = 0; Index < getNumContainedManagers(); ++Index) { > @@ -1348,7 +1348,7 @@ > return Changed |= doFinalization(M); > } > > -bool FPPassManager::doInitialization(Module &M) { > +inline bool FPPassManager::doInitialization(Module &M) { > bool Changed = false; > > for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { > @@ -1359,7 +1359,7 @@ > return Changed; > } > > -bool FPPassManager::doFinalization(Module &M) { > +inline bool FPPassManager::doFinalization(Module &M) { > bool Changed = false; > > for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { > > Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll?rev=64311&r1=64310&r2=64311&view=diff > > ============================================================================== > --- llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll (original) > +++ llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll Wed Feb 11 12:19:24 2009 > @@ -1,6 +1,7 @@ > ; RUN: llvm-as < %s | opt -std-compile-opts | llvm-dis | grep nocapture | count 2 > ; Check that nocapture attributes are added when run after an SCC pass. > ; PR3520 > +; XFAIL: * > > define i32 @use(i8* %x) nounwind readonly { > entry: > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From dpatel at apple.com Wed Feb 11 12:56:04 2009 From: dpatel at apple.com (Devang Patel) Date: Wed, 11 Feb 2009 10:56:04 -0800 Subject: [llvm-commits] [llvm] r64285 - in /llvm/trunk/tools: Makefile lto/Makefile In-Reply-To: <4992638E.9080703@mxc.ca> References: <200902110234.n1B2YXPZ001181@zion.cs.uiuc.edu> <4992638E.9080703@mxc.ca> Message-ID: <51F56D1C-6CD2-479D-B08C-3E8FC5DA5E4E@apple.com> On Feb 10, 2009, at 9:35 PM, Nick Lewycky wrote: >> Modified: llvm/trunk/tools/lto/Makefile >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/Makefile?rev=64285&r1=64284&r2=64285&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/tools/lto/Makefile (original) >> +++ llvm/trunk/tools/lto/Makefile Tue Feb 10 20:34:33 2009 >> @@ -16,8 +16,12 @@ >> include $(LEVEL)/Makefile.config >> >> LINK_LIBS_IN_SHARED = 1 >> -SHARED_LIBRARY = 1 >> -DONT_BUILD_RELINKED = 1 >> +ifeq ($(OS),Darwin) >> + SHARED_LIBRARY = 1 >> + DONT_BUILD_RELINKED = 1 >> +else >> + BUILD_ARCHIVE = 1 >> +endif > > How on Earth did this break anything? All I changed was to make it > as if > OS=Darwin was always true... > > I'm going to assume that it didn't, and you just backed out the whole > revision (makes sense to me), yup > and revert your reversion of this file... -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090211/db0b08ff/attachment.html From dpatel at apple.com Wed Feb 11 12:56:48 2009 From: dpatel at apple.com (Devang Patel) Date: Wed, 11 Feb 2009 10:56:48 -0800 Subject: [llvm-commits] [llvm] r64299 - in /llvm/trunk/tools: Makefile lto/Makefile In-Reply-To: <200902110844.n1B8iDM0014795@zion.cs.uiuc.edu> References: <200902110844.n1B8iDM0014795@zion.cs.uiuc.edu> Message-ID: <589FA883-D4CE-43C3-BE7C-1EC07871B4ED@apple.com> Thanks! - Devang On Feb 11, 2009, at 12:44 AM, Nick Lewycky wrote: > Author: nicholas > Date: Wed Feb 11 02:44:13 2009 > New Revision: 64299 > > URL: http://llvm.org/viewvc/llvm-project?rev=64299&view=rev > Log: > Try this. Darwin -> LTO, PIC -> LTO + possibly gold too. > > Modified: > llvm/trunk/tools/Makefile > llvm/trunk/tools/lto/Makefile > > Modified: llvm/trunk/tools/Makefile > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/Makefile?rev=64299&r1=64298&r2=64299&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/tools/Makefile (original) > +++ llvm/trunk/tools/Makefile Wed Feb 11 02:44:13 2009 > @@ -25,10 +25,11 @@ > > include $(LEVEL)/Makefile.config > > -# only build new lto project on Darwin for now > +# build lto project on Darwin or if PIC is enabled > ifeq ($(OS),Darwin) > PARALLEL_DIRS += lto > - > +else ($(ENABLE_PIC),1) > +PARALLEL_DIRS += lto > ifdef BINUTILS_INCDIR > PARALLEL_DIRS += gold > endif > > Modified: llvm/trunk/tools/lto/Makefile > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/Makefile?rev=64299&r1=64298&r2=64299&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/tools/lto/Makefile (original) > +++ llvm/trunk/tools/lto/Makefile Wed Feb 11 02:44:13 2009 > @@ -16,12 +16,8 @@ > include $(LEVEL)/Makefile.config > > LINK_LIBS_IN_SHARED = 1 > -ifeq ($(OS),Darwin) > - SHARED_LIBRARY = 1 > - DONT_BUILD_RELINKED = 1 > -else > - BUILD_ARCHIVE = 1 > -endif > +SHARED_LIBRARY = 1 > +DONT_BUILD_RELINKED = 1 > > LINK_COMPONENTS := $(TARGETS_TO_BUILD) ipo scalaropts linker > bitreader bitwriter > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dalej at apple.com Wed Feb 11 13:19:42 2009 From: dalej at apple.com (Dale Johannesen) Date: Wed, 11 Feb 2009 19:19:42 -0000 Subject: [llvm-commits] [llvm] r64314 - in /llvm/trunk: lib/CodeGen/SelectionDAG/TargetLowering.cpp test/CodeGen/X86/nobt.ll Message-ID: <200902111919.n1BJJgZR012699@zion.cs.uiuc.edu> Author: johannes Date: Wed Feb 11 13:19:41 2009 New Revision: 64314 URL: http://llvm.org/viewvc/llvm-project?rev=64314&view=rev Log: Make a transformation added in 63266 a bit less aggressive. It was transforming (x&y)==y to (x&y)!=0 in the case where y is variable and known to have at most one bit set (e.g. z&1). This is not correct; the expressions are not equivalent when y==0. I believe this patch salvages what can be salvaged, including all the cases in bt.ll. Dan, please review. Fixes gcc.c-torture/execute/20040709-[12].c Added: llvm/trunk/test/CodeGen/X86/nobt.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=64314&r1=64313&r2=64314&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Feb 11 13:19:41 2009 @@ -1346,20 +1346,21 @@ return 1; } -static bool ValueHasAtMostOneBitSet(SDValue Val, const SelectionDAG &DAG) { +static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { // Logical shift right or left won't ever introduce new set bits. // We check for this case because we don't care which bits are // set, but ComputeMaskedBits won't know anything unless it can // determine which specific bits may be set. if (Val.getOpcode() == ISD::SHL || Val.getOpcode() == ISD::SRL) - return ValueHasAtMostOneBitSet(Val.getOperand(0), DAG); + return ValueHasExactlyOneBitSet(Val.getOperand(0), DAG); MVT OpVT = Val.getValueType(); unsigned BitWidth = OpVT.getSizeInBits(); APInt Mask = APInt::getAllOnesValue(BitWidth); APInt KnownZero, KnownOne; DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); - return KnownZero.countPopulation() == BitWidth - 1; + return (KnownZero.countPopulation() == BitWidth - 1) && + (KnownOne.countPopulation() == 1); } /// SimplifySetCC - Try to simplify a setcc built with the specified operands @@ -1832,9 +1833,12 @@ } // Simplify x&y == y to x&y != 0 if y has exactly one bit set. + // Note that where y is variable and is known to have at most + // one bit set (for example, if it is z&1) we cannot do this; + // the expressions are not equivalent when y==0. if (N0.getOpcode() == ISD::AND) if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { - if (ValueHasAtMostOneBitSet(N1, DAG)) { + if (ValueHasExactlyOneBitSet(N1, DAG)) { Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); SDValue Zero = DAG.getConstant(0, N1.getValueType()); return DAG.getSetCC(dl, VT, N0, Zero, Cond); @@ -1842,7 +1846,7 @@ } if (N1.getOpcode() == ISD::AND) if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { - if (ValueHasAtMostOneBitSet(N0, DAG)) { + if (ValueHasExactlyOneBitSet(N0, DAG)) { Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); SDValue Zero = DAG.getConstant(0, N0.getValueType()); return DAG.getSetCC(dl, VT, N1, Zero, Cond); Added: llvm/trunk/test/CodeGen/X86/nobt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/nobt.ll?rev=64314&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/nobt.ll (added) +++ llvm/trunk/test/CodeGen/X86/nobt.ll Wed Feb 11 13:19:41 2009 @@ -0,0 +1,70 @@ +; RUN: llvm-as < %s | llc -march=x86 | not grep btl + +; This tests some cases where BT must not be generated. See also bt.ll. +; Fixes 20040709-[12].c in gcc testsuite. + +define void @test2(i32 %x, i32 %n) nounwind { +entry: + %tmp1 = and i32 %x, 1 + %tmp2 = urem i32 %tmp1, 15 + %tmp3 = and i32 %tmp2, 1 ; [#uses=1] + %tmp4 = icmp eq i32 %tmp3, %tmp2 ; [#uses=1] + br i1 %tmp4, label %bb, label %UnifiedReturnBlock + +bb: ; preds = %entry + call void @foo() + ret void + +UnifiedReturnBlock: ; preds = %entry + ret void +} + +define void @test3(i32 %x, i32 %n) nounwind { +entry: + %tmp1 = and i32 %x, 1 + %tmp2 = urem i32 %tmp1, 15 + %tmp3 = and i32 %tmp2, 1 ; [#uses=1] + %tmp4 = icmp eq i32 %tmp2, %tmp3 ; [#uses=1] + br i1 %tmp4, label %bb, label %UnifiedReturnBlock + +bb: ; preds = %entry + call void @foo() + ret void + +UnifiedReturnBlock: ; preds = %entry + ret void +} + +define void @test4(i32 %x, i32 %n) nounwind { +entry: + %tmp1 = and i32 %x, 1 + %tmp2 = urem i32 %tmp1, 15 + %tmp3 = and i32 %tmp2, 1 ; [#uses=1] + %tmp4 = icmp ne i32 %tmp2, %tmp3 ; [#uses=1] + br i1 %tmp4, label %bb, label %UnifiedReturnBlock + +bb: ; preds = %entry + call void @foo() + ret void + +UnifiedReturnBlock: ; preds = %entry + ret void +} + +define void @test5(i32 %x, i32 %n) nounwind { +entry: + %tmp1 = and i32 %x, 1 + %tmp2 = urem i32 %tmp1, 15 + %tmp3 = and i32 %tmp2, 1 ; [#uses=1] + %tmp4 = icmp ne i32 %tmp2, %tmp3 ; [#uses=1] + br i1 %tmp4, label %bb, label %UnifiedReturnBlock + +bb: ; preds = %entry + call void @foo() + ret void + +UnifiedReturnBlock: ; preds = %entry + ret void +} + +declare void @foo() From isanbard at gmail.com Wed Feb 11 13:33:39 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 11 Feb 2009 19:33:39 -0000 Subject: [llvm-commits] [llvm] r64315 - in /llvm/branches/Apple/Dib: lib/CodeGen/SelectionDAG/TargetLowering.cpp test/CodeGen/X86/nobt.ll Message-ID: <200902111933.n1BJXdRp013235@zion.cs.uiuc.edu> Author: void Date: Wed Feb 11 13:33:38 2009 New Revision: 64315 URL: http://llvm.org/viewvc/llvm-project?rev=64315&view=rev Log: Pull r64314 into Dib: Make a transformation added in 63266 a bit less aggressive. It was transforming (x&y)==y to (x&y)!=0 in the case where y is variable and known to have at most one bit set (e.g. z&1). This is not correct; the expressions are not equivalent when y==0. I believe this patch salvages what can be salvaged, including all the cases in bt.ll. Dan, please review. Fixes gcc.c-torture/execute/20040709-[12].c Added: llvm/branches/Apple/Dib/test/CodeGen/X86/nobt.ll Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=64315&r1=64314&r2=64315&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Feb 11 13:33:38 2009 @@ -1346,20 +1346,21 @@ return 1; } -static bool ValueHasAtMostOneBitSet(SDValue Val, const SelectionDAG &DAG) { +static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { // Logical shift right or left won't ever introduce new set bits. // We check for this case because we don't care which bits are // set, but ComputeMaskedBits won't know anything unless it can // determine which specific bits may be set. if (Val.getOpcode() == ISD::SHL || Val.getOpcode() == ISD::SRL) - return ValueHasAtMostOneBitSet(Val.getOperand(0), DAG); + return ValueHasExactlyOneBitSet(Val.getOperand(0), DAG); MVT OpVT = Val.getValueType(); unsigned BitWidth = OpVT.getSizeInBits(); APInt Mask = APInt::getAllOnesValue(BitWidth); APInt KnownZero, KnownOne; DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); - return KnownZero.countPopulation() == BitWidth - 1; + return (KnownZero.countPopulation() == BitWidth - 1) && + (KnownOne.countPopulation() == 1); } /// SimplifySetCC - Try to simplify a setcc built with the specified operands @@ -1832,9 +1833,12 @@ } // Simplify x&y == y to x&y != 0 if y has exactly one bit set. + // Note that where y is variable and is known to have at most + // one bit set (for example, if it is z&1) we cannot do this; + // the expressions are not equivalent when y==0. if (N0.getOpcode() == ISD::AND) if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { - if (ValueHasAtMostOneBitSet(N1, DAG)) { + if (ValueHasExactlyOneBitSet(N1, DAG)) { Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); SDValue Zero = DAG.getConstant(0, N1.getValueType()); return DAG.getSetCC(dl, VT, N0, Zero, Cond); @@ -1842,7 +1846,7 @@ } if (N1.getOpcode() == ISD::AND) if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { - if (ValueHasAtMostOneBitSet(N0, DAG)) { + if (ValueHasExactlyOneBitSet(N0, DAG)) { Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); SDValue Zero = DAG.getConstant(0, N0.getValueType()); return DAG.getSetCC(dl, VT, N1, Zero, Cond); Added: llvm/branches/Apple/Dib/test/CodeGen/X86/nobt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/nobt.ll?rev=64315&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/X86/nobt.ll (added) +++ llvm/branches/Apple/Dib/test/CodeGen/X86/nobt.ll Wed Feb 11 13:33:38 2009 @@ -0,0 +1,70 @@ +; RUN: llvm-as < %s | llc -march=x86 | not grep btl + +; This tests some cases where BT must not be generated. See also bt.ll. +; Fixes 20040709-[12].c in gcc testsuite. + +define void @test2(i32 %x, i32 %n) nounwind { +entry: + %tmp1 = and i32 %x, 1 + %tmp2 = urem i32 %tmp1, 15 + %tmp3 = and i32 %tmp2, 1 ; [#uses=1] + %tmp4 = icmp eq i32 %tmp3, %tmp2 ; [#uses=1] + br i1 %tmp4, label %bb, label %UnifiedReturnBlock + +bb: ; preds = %entry + call void @foo() + ret void + +UnifiedReturnBlock: ; preds = %entry + ret void +} + +define void @test3(i32 %x, i32 %n) nounwind { +entry: + %tmp1 = and i32 %x, 1 + %tmp2 = urem i32 %tmp1, 15 + %tmp3 = and i32 %tmp2, 1 ; [#uses=1] + %tmp4 = icmp eq i32 %tmp2, %tmp3 ; [#uses=1] + br i1 %tmp4, label %bb, label %UnifiedReturnBlock + +bb: ; preds = %entry + call void @foo() + ret void + +UnifiedReturnBlock: ; preds = %entry + ret void +} + +define void @test4(i32 %x, i32 %n) nounwind { +entry: + %tmp1 = and i32 %x, 1 + %tmp2 = urem i32 %tmp1, 15 + %tmp3 = and i32 %tmp2, 1 ; [#uses=1] + %tmp4 = icmp ne i32 %tmp2, %tmp3 ; [#uses=1] + br i1 %tmp4, label %bb, label %UnifiedReturnBlock + +bb: ; preds = %entry + call void @foo() + ret void + +UnifiedReturnBlock: ; preds = %entry + ret void +} + +define void @test5(i32 %x, i32 %n) nounwind { +entry: + %tmp1 = and i32 %x, 1 + %tmp2 = urem i32 %tmp1, 15 + %tmp3 = and i32 %tmp2, 1 ; [#uses=1] + %tmp4 = icmp ne i32 %tmp2, %tmp3 ; [#uses=1] + br i1 %tmp4, label %bb, label %UnifiedReturnBlock + +bb: ; preds = %entry + call void @foo() + ret void + +UnifiedReturnBlock: ; preds = %entry + ret void +} + +declare void @foo() From gohman at apple.com Wed Feb 11 13:50:26 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 11 Feb 2009 19:50:26 -0000 Subject: [llvm-commits] [llvm] r64316 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <200902111950.n1BJoQh4013911@zion.cs.uiuc.edu> Author: djg Date: Wed Feb 11 13:50:24 2009 New Revision: 64316 URL: http://llvm.org/viewvc/llvm-project?rev=64316&view=rev Log: Don't try to set an EFLAGS operand to dead if no instruction was created. This fixes a bug introduced by r61215. Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=64316&r1=64315&r2=64316&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Wed Feb 11 13:50:24 2009 @@ -412,11 +412,13 @@ } } - // The EFLAGS implicit def is dead. - New->getOperand(3).setIsDead(); + if (New) { + // The EFLAGS implicit def is dead. + New->getOperand(3).setIsDead(); - // Replace the pseudo instruction with a new instruction... - if (New) MBB.insert(I, New); + // Replace the pseudo instruction with a new instruction... + MBB.insert(I, New); + } } } else if (I->getOpcode() == getCallFrameDestroyOpcode()) { // If we are performing frame pointer elimination and if the callee pops From gohman at apple.com Wed Feb 11 14:26:06 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 11 Feb 2009 20:26:06 -0000 Subject: [llvm-commits] [llvm] r64319 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Message-ID: <200902112026.n1BKQ7Mx015291@zion.cs.uiuc.edu> Author: djg Date: Wed Feb 11 14:25:59 2009 New Revision: 64319 URL: http://llvm.org/viewvc/llvm-project?rev=64319&view=rev Log: Delete the heuristic for non-livein CopyFromReg nodes. Non-liveinness is determined by whether the node has a Flag operand. However, if the node does have a Flag operand, it will be glued to its register's def, so the heuristic would end up spuriously applying to whatever node is the def. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=64319&r1=64318&r2=64319&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Feb 11 14:25:59 2009 @@ -899,12 +899,6 @@ }; } // end anonymous namespace -static inline bool isCopyFromLiveIn(const SUnit *SU) { - SDNode *N = SU->getNode(); - return N && N->getOpcode() == ISD::CopyFromReg && - N->getOperand(N->getNumOperands()-1).getValueType() != MVT::Flag; -} - /// CalcNodeSethiUllmanNumber - Compute Sethi Ullman number. /// Smaller number is the higher priority. static unsigned @@ -986,11 +980,6 @@ unsigned getNodePriority(const SUnit *SU) const { assert(SU->NodeNum < SethiUllmanNumbers.size()); unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0; - if (Opc == ISD::CopyFromReg && !isCopyFromLiveIn(SU)) - // CopyFromReg should be close to its def because it restricts - // allocation choices. But if it is a livein then perhaps we want it - // closer to its uses so it can be coalesced. - return 0xffff; if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) // CopyToReg should be close to its uses to facilitate coalescing and // avoid spilling. From baldrick at free.fr Wed Feb 11 14:31:06 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 11 Feb 2009 21:31:06 +0100 Subject: [llvm-commits] [llvm] r64300 - in /llvm/trunk: lib/Analysis/IPA/CallGraphSCCPass.cpp test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll In-Reply-To: <499309D0.4050706@mxc.ca> References: <200902110958.n1B9wiM7024990@zion.cs.uiuc.edu> <499309D0.4050706@mxc.ca> Message-ID: <200902112131.06788.baldrick@free.fr> Hi Nick, > I think you should just use CG.getModule() instead of passing the Module > around. well, ok. > > +; RUN: llvm-as < %s | opt -std-compile-opts | llvm-dis | grep nocapture | count 2 > > +; Check that nocapture attributes are added when run after an SCC pass. > > How about just '-inline -simplify-libcalls'? -std-compile-opts is slow > enough that it should be avoided whenever possible. I wanted to check that the calling function also got the nocapture attribute. I guess -functionattrs -simplify-libcalls would do the trick. Ciao, Duncan. From baldrick at free.fr Wed Feb 11 14:35:04 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 11 Feb 2009 21:35:04 +0100 Subject: [llvm-commits] [llvm] r64311 - in /llvm/trunk: lib/Analysis/IPA/CallGraphSCCPass.cpp lib/VMCore/PassManager.cpp test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll In-Reply-To: <200902111819.n1BIJPCL010238@zion.cs.uiuc.edu> References: <200902111819.n1BIJPCL010238@zion.cs.uiuc.edu> Message-ID: <200902112135.04466.baldrick@free.fr> Hi Bill, > Revert r64300 and r64301. These were causing the following errors respectively: > > During llvm-gcc bootstrap: > > Undefined symbols: > "llvm::FPPassManager::doFinalization(llvm::Module&)", referenced from: > (anonymous namespace)::CGPassManager::doFinalization(llvm::CallGraph&, llvm::Module&) > in libLLVMipa.a(CallGraphSCCPass.o) > "llvm::FPPassManager::doInitialization(llvm::Module&)", referenced from: > (anonymous namespace)::CGPassManager::doInitialization(llvm::CallGraph&, llvm::Module&) > in libLLVMipa.a(CallGraphSCCPass.o) this was some strangeness due to inlining. It was fixed by r64301. Ciao, Duncan. From baldrick at free.fr Wed Feb 11 14:38:15 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 11 Feb 2009 21:38:15 +0100 Subject: [llvm-commits] [llvm] r64311 - in /llvm/trunk: lib/Analysis/IPA/CallGraphSCCPass.cpp lib/VMCore/PassManager.cpp test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll In-Reply-To: <16e5fdf90902111024r42cd4fafma73cf49f2ecc1014@mail.gmail.com> References: <200902111819.n1BIJPCL010238@zion.cs.uiuc.edu> <16e5fdf90902111024r42cd4fafma73cf49f2ecc1014@mail.gmail.com> Message-ID: <200902112138.15383.baldrick@free.fr> Hi Bill, > The second failure has this error message: > > tblgen: for the -asmwriternum option: : '1' value invalid for uint argument! > make[3]: *** [/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Target/X86/Release/X86GenAsmWriter1.inc.tmp] > Error 1 > make[2]: *** [X86/.makeall] Error 2 > make[1]: *** [Target/.makeall] Error 2 > make[1]: *** Waiting for unfinished jobs.... this one is more exciting :) Is this llvm built using a just built llvm-gcc? I guess Nick should look into this. By the way, probably the right thing to do is to reapply my patches and temporarily turn off the part of SimplifyLibcalls that is causing trouble. I'll leave it to Nick. Ciao, Duncan. From baldrick at free.fr Wed Feb 11 14:41:33 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 11 Feb 2009 21:41:33 +0100 Subject: [llvm-commits] [llvm] r64300 - in /llvm/trunk: lib/Analysis/IPA/CallGraphSCCPass.cpp test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll In-Reply-To: <499309D0.4050706@mxc.ca> References: <200902110958.n1B9wiM7024990@zion.cs.uiuc.edu> <499309D0.4050706@mxc.ca> Message-ID: <200902112141.33661.baldrick@free.fr> Hi Nick, > > Make sure the SCC pass manager initializes any contained > > function pass managers. Without this, simplify-libcalls > > would add nocapture attributes when run on its own, but > > not when run as part of -std-compile-opts or similar. > > Thanks for fixing this! it seems Bill reverted this because it caused some bootstrap breakage. Most likely there is a mistake in your simplify libcalls stuff, or the nocapture logic, or alias analysis, that is now being seen because your pass is actually being run. My plan is to let you investigate :) Ciao, Duncan. From daniel at zuster.org Wed Feb 11 14:48:21 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 11 Feb 2009 20:48:21 -0000 Subject: [llvm-commits] [llvm] r64322 - /llvm/trunk/test/Bindings/Ocaml/vmcore.ml Message-ID: <200902112048.n1BKmL7P016169@zion.cs.uiuc.edu> Author: ddunbar Date: Wed Feb 11 14:48:21 2009 New Revision: 64322 URL: http://llvm.org/viewvc/llvm-project?rev=64322&view=rev Log: Update to match space changes in .ll Modified: llvm/trunk/test/Bindings/Ocaml/vmcore.ml Modified: llvm/trunk/test/Bindings/Ocaml/vmcore.ml URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bindings/Ocaml/vmcore.ml?rev=64322&r1=64321&r2=64322&view=diff ============================================================================== --- llvm/trunk/test/Bindings/Ocaml/vmcore.ml (original) +++ llvm/trunk/test/Bindings/Ocaml/vmcore.ml Wed Feb 11 14:48:21 2009 @@ -244,14 +244,14 @@ let three = const_int i32_type 3 in let four = const_int i32_type 4 in - (* RUN: grep {Const07.*\\\[ i32 3, i32 4 \\\]} < %t.ll + (* RUN: grep {Const07.*\\\[i32 3, i32 4\\\]} < %t.ll *) group "array"; let c = const_array i32_type [| three; four |] in ignore (define_global "Const07" c m); insist ((array_type i32_type 2) = (type_of c)); - (* RUN: grep {Const08.*< i16 1, i16 2.* >} < %t.ll + (* RUN: grep {Const08.*} < %t.ll *) group "vector"; let c = const_vector [| one; two; one; two; From kremenek at apple.com Wed Feb 11 14:53:17 2009 From: kremenek at apple.com (Ted Kremenek) Date: Wed, 11 Feb 2009 20:53:17 -0000 Subject: [llvm-commits] [llvm] r64324 - /llvm/trunk/include/llvm/ADT/FoldingSet.h Message-ID: <200902112053.n1BKrIOZ016393@zion.cs.uiuc.edu> Author: kremenek Date: Wed Feb 11 14:53:17 2009 New Revision: 64324 URL: http://llvm.org/viewvc/llvm-project?rev=64324&view=rev Log: Add FoldingSet profile method for bools. Patch by Ben Laurie! Modified: llvm/trunk/include/llvm/ADT/FoldingSet.h Modified: llvm/trunk/include/llvm/ADT/FoldingSet.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/FoldingSet.h?rev=64324&r1=64323&r2=64324&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/FoldingSet.h (original) +++ llvm/trunk/include/llvm/ADT/FoldingSet.h Wed Feb 11 14:53:17 2009 @@ -225,6 +225,7 @@ void AddInteger(unsigned long I); void AddInteger(long long I); void AddInteger(unsigned long long I); + void AddBoolean(bool B) { AddInteger(B ? 1U : 0U); } void AddString(const char* String, const char* End); void AddString(const std::string &String); void AddString(const char* String); From isanbard at gmail.com Wed Feb 11 14:55:37 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 11 Feb 2009 12:55:37 -0800 Subject: [llvm-commits] [llvm] r64311 - in /llvm/trunk: lib/Analysis/IPA/CallGraphSCCPass.cpp lib/VMCore/PassManager.cpp test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll In-Reply-To: <200902112138.15383.baldrick@free.fr> References: <200902111819.n1BIJPCL010238@zion.cs.uiuc.edu> <16e5fdf90902111024r42cd4fafma73cf49f2ecc1014@mail.gmail.com> <200902112138.15383.baldrick@free.fr> Message-ID: <16e5fdf90902111255y4e8a868dsdbbf9f0575ea684@mail.gmail.com> On Wed, Feb 11, 2009 at 12:38 PM, Duncan Sands wrote: > Hi Bill, > >> The second failure has this error message: >> >> tblgen: for the -asmwriternum option: : '1' value invalid for uint argument! >> make[3]: *** [/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Target/X86/Release/X86GenAsmWriter1.inc.tmp] >> Error 1 >> make[2]: *** [X86/.makeall] Error 2 >> make[1]: *** [Target/.makeall] Error 2 >> make[1]: *** Waiting for unfinished jobs.... > > this one is more exciting :) For one definition of exciting. :-) > Is this llvm built using a just built llvm-gcc? Yes. > I guess Nick should look into this. By the way, probably the right thing to > do is to reapply my patches and temporarily turn off the part of SimplifyLibcalls > that is causing trouble. I'll leave it to Nick. > I'm hesitant to do this. Let's wait until Nick can figure out what's happening here. -bw From gohman at apple.com Wed Feb 11 15:29:39 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 11 Feb 2009 21:29:39 -0000 Subject: [llvm-commits] [llvm] r64327 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/X86/2008-02-22-ReMatBug.ll test/CodeGen/X86/2008-08-05-SpillerBug.ll test/CodeGen/X86/pmul.ll test/CodeGen/X86/sse_reload_fold.ll Message-ID: <200902112129.n1BLTdEi018177@zion.cs.uiuc.edu> Author: djg Date: Wed Feb 11 15:29:39 2009 New Revision: 64327 URL: http://llvm.org/viewvc/llvm-project?rev=64327&view=rev Log: Don't use special heuristics for nodes with no data predecessors unless they actually have data successors, and likewise for nodes with no data successors unless they actually have data precessors. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp llvm/trunk/test/CodeGen/X86/2008-02-22-ReMatBug.ll llvm/trunk/test/CodeGen/X86/2008-08-05-SpillerBug.ll llvm/trunk/test/CodeGen/X86/pmul.ll llvm/trunk/test/CodeGen/X86/sse_reload_fold.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=64327&r1=64326&r2=64327&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Feb 11 15:29:39 2009 @@ -989,15 +989,16 @@ // EXTRACT_SUBREG / INSERT_SUBREG should be close to its use to // facilitate coalescing. return 0; - if (SU->NumSuccs == 0) - // If SU does not have a use, i.e. it doesn't produce a value that would - // be consumed (e.g. store), then it terminates a chain of computation. - // Give it a large SethiUllman number so it will be scheduled right - // before its predecessors that it doesn't lengthen their live ranges. + if (SU->NumSuccs == 0 && SU->NumPreds != 0) + // If SU does not have a register use, i.e. it doesn't produce a value + // that would be consumed (e.g. store), then it terminates a chain of + // computation. Give it a large SethiUllman number so it will be + // scheduled right before its predecessors that it doesn't lengthen + // their live ranges. return 0xffff; - if (SU->NumPreds == 0) - // If SU does not have a def, schedule it close to its uses because it - // does not lengthen any live ranges. + if (SU->NumPreds == 0 && SU->NumSuccs != 0) + // If SU does not have a register def, schedule it close to its uses + // because it does not lengthen any live ranges. return 0; return SethiUllmanNumbers[SU->NodeNum]; } Modified: llvm/trunk/test/CodeGen/X86/2008-02-22-ReMatBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-02-22-ReMatBug.ll?rev=64327&r1=64326&r2=64327&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-02-22-ReMatBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-02-22-ReMatBug.ll Wed Feb 11 15:29:39 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of re-materialization} | grep 4 +; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of re-materialization} | grep 3 ; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of dead spill slots removed} ; rdar://5761454 Modified: llvm/trunk/test/CodeGen/X86/2008-08-05-SpillerBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-05-SpillerBug.ll?rev=64327&r1=64326&r2=64327&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-08-05-SpillerBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-08-05-SpillerBug.ll Wed Feb 11 15:29:39 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -disable-fp-elim -stats -info-output-file - | not grep {Number of dead stores elided} +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -disable-fp-elim -stats -info-output-file - | grep {Number of dead stores elided} | count 1 ; PR2568 @g_3 = external global i16 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/X86/pmul.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pmul.ll?rev=64327&r1=64326&r2=64327&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/pmul.ll (original) +++ llvm/trunk/test/CodeGen/X86/pmul.ll Wed Feb 11 15:29:39 2009 @@ -1,6 +1,6 @@ ; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 -stack-alignment=16 > %t ; RUN: grep pmul %t | count 12 -; RUN: grep mov %t | count 15 +; RUN: grep mov %t | count 12 define <4 x i32> @a(<4 x i32> %i) nounwind { %A = mul <4 x i32> %i, < i32 117, i32 117, i32 117, i32 117 > Modified: llvm/trunk/test/CodeGen/X86/sse_reload_fold.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse_reload_fold.ll?rev=64327&r1=64326&r2=64327&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse_reload_fold.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse_reload_fold.ll Wed Feb 11 15:29:39 2009 @@ -2,9 +2,10 @@ ; RUN: llc -march=x86-64 -mattr=+64bit,+sse3 -print-failed-fuse-candidates |& \ ; RUN: grep fail | count 1 -declare void @bar() -declare <4 x float> @qux() -declare <2 x double> @pin() +declare float @test_f(float %f) +declare double @test_d(double %f) +declare <4 x float> @test_vf(<4 x float> %f) +declare <2 x double> @test_vd(<2 x double> %f) declare float @llvm.sqrt.f32(float) declare double @llvm.sqrt.f64(double) @@ -26,99 +27,99 @@ declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) define float @foo(float %f) { - call void @bar() + %a = call float @test_f(float %f) %t = call float @llvm.sqrt.f32(float %f) ret float %t } define double @doo(double %f) { - call void @bar() + %a = call double @test_d(double %f) %t = call double @llvm.sqrt.f64(double %f) ret double %t } define <4 x float> @a0(<4 x float> %f) { - call void @bar() + %a = call <4 x float> @test_vf(<4 x float> %f) %t = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> %f) ret <4 x float> %t } define <4 x float> @a1(<4 x float> %f) { - call void @bar() + %a = call <4 x float> @test_vf(<4 x float> %f) %t = call <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float> %f) ret <4 x float> %t } define <4 x float> @a2(<4 x float> %f) { - call void @bar() + %a = call <4 x float> @test_vf(<4 x float> %f) %t = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %f) ret <4 x float> %t } define <4 x float> @b3(<4 x float> %f) { - %y = call <4 x float> @qux() + %y = call <4 x float> @test_vf(<4 x float> %f) %t = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %y, <4 x float> %f) ret <4 x float> %t } define <4 x float> @b4(<4 x float> %f) { - %y = call <4 x float> @qux() + %y = call <4 x float> @test_vf(<4 x float> %f) %t = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %y, <4 x float> %f) ret <4 x float> %t } define <4 x float> @b5(<4 x float> %f) { - %y = call <4 x float> @qux() + %y = call <4 x float> @test_vf(<4 x float> %f) %t = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %y, <4 x float> %f, i8 7) ret <4 x float> %t } define <4 x float> @b6(<4 x float> %f) { - %y = call <4 x float> @qux() + %y = call <4 x float> @test_vf(<4 x float> %f) %t = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %y, <4 x float> %f) ret <4 x float> %t } define <4 x float> @b7(<4 x float> %f) { - %y = call <4 x float> @qux() + %y = call <4 x float> @test_vf(<4 x float> %f) %t = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %y, <4 x float> %f) ret <4 x float> %t } define <4 x float> @b8(<4 x float> %f) { - %y = call <4 x float> @qux() + %y = call <4 x float> @test_vf(<4 x float> %f) %t = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %y, <4 x float> %f) ret <4 x float> %t } define <2 x double> @c1(<2 x double> %f) { - call void @bar() + %a = call <2 x double> @test_vd(<2 x double> %f) %t = call <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double> %f) ret <2 x double> %t } define <2 x double> @d3(<2 x double> %f) { - %y = call <2 x double> @pin() + %y = call <2 x double> @test_vd(<2 x double> %f) %t = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %y, <2 x double> %f) ret <2 x double> %t } define <2 x double> @d4(<2 x double> %f) { - %y = call <2 x double> @pin() + %y = call <2 x double> @test_vd(<2 x double> %f) %t = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> %y, <2 x double> %f) ret <2 x double> %t } define <2 x double> @d5(<2 x double> %f) { - %y = call <2 x double> @pin() + %y = call <2 x double> @test_vd(<2 x double> %f) %t = call <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double> %y, <2 x double> %f, i8 7) ret <2 x double> %t } define <2 x double> @d6(<2 x double> %f) { - %y = call <2 x double> @pin() + %y = call <2 x double> @test_vd(<2 x double> %f) %t = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %y, <2 x double> %f) ret <2 x double> %t } define <2 x double> @d7(<2 x double> %f) { - %y = call <2 x double> @pin() + %y = call <2 x double> @test_vd(<2 x double> %f) %t = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %y, <2 x double> %f) ret <2 x double> %t } define <2 x double> @d8(<2 x double> %f) { - %y = call <2 x double> @pin() + %y = call <2 x double> @test_vd(<2 x double> %f) %t = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %y, <2 x double> %f) ret <2 x double> %t } ; This one should fail to fuse. define <2 x double> @z0(<2 x double> %f) { - %y = call <2 x double> @pin() + %y = call <2 x double> @test_vd(<2 x double> %f) %t = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %f, <2 x double> %y) ret <2 x double> %t } From gohman at apple.com Wed Feb 11 15:32:08 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 11 Feb 2009 21:32:08 -0000 Subject: [llvm-commits] [llvm] r64328 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Message-ID: <200902112132.n1BLW8uW018269@zion.cs.uiuc.edu> Author: djg Date: Wed Feb 11 15:32:08 2009 New Revision: 64328 URL: http://llvm.org/viewvc/llvm-project?rev=64328&view=rev Log: Fix a comment. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=64328&r1=64327&r2=64328&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Feb 11 15:32:08 2009 @@ -1252,8 +1252,8 @@ if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI)) continue; } - // Don't constraint extract_subreg / insert_subreg these may be - // coalesced away. We don't them close to their uses. + // Don't constrain extract_subreg / insert_subreg; these may be + // coalesced away. We want them close to their uses. unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode(); if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG || SuccOpc == TargetInstrInfo::INSERT_SUBREG) From isanbard at gmail.com Wed Feb 11 15:51:23 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 11 Feb 2009 21:51:23 -0000 Subject: [llvm-commits] [llvm] r64329 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Message-ID: <200902112151.n1BLpNOX019002@zion.cs.uiuc.edu> Author: void Date: Wed Feb 11 15:51:19 2009 New Revision: 64329 URL: http://llvm.org/viewvc/llvm-project?rev=64329&view=rev Log: Propagate DebugLoc info for spiller call-backs. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=64329&r1=64328&r2=64329&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed Feb 11 15:51:19 2009 @@ -905,6 +905,9 @@ MachineBasicBlock::iterator I, unsigned DestReg, const MachineInstr *Orig) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + unsigned SubIdx = Orig->getOperand(0).isReg() ? Orig->getOperand(0).getSubReg() : 0; bool ChangeSubIdx = SubIdx != 0; @@ -931,7 +934,7 @@ case X86::MOV32r0: Opc = X86::MOV32ri; break; case X86::MOV64r0: Opc = X86::MOV64ri32; break; } - BuildMI(MBB, I, get(Opc), DestReg).addImm(0); + BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0); Emitted = true; } break; @@ -1038,7 +1041,8 @@ if (B != C) return 0; unsigned A = MI->getOperand(0).getReg(); unsigned M = MI->getOperand(3).getImm(); - NewMI = BuildMI(MF, get(X86::PSHUFDri)).addReg(A, true, false, false, isDead) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) + .addReg(A, true, false, false, isDead) .addReg(B, false, false, isKill).addImm(M); break; } @@ -1049,7 +1053,8 @@ unsigned ShAmt = MI->getOperand(2).getImm(); if (ShAmt == 0 || ShAmt >= 4) return 0; - NewMI = BuildMI(MF, get(X86::LEA64r)).addReg(Dest, true, false, false, isDead) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) + .addReg(Dest, true, false, false, isDead) .addReg(0).addImm(1 << ShAmt).addReg(Src, false, false, isKill).addImm(0); break; } @@ -1062,7 +1067,8 @@ unsigned Opc = TM.getSubtarget().is64Bit() ? X86::LEA64_32r : X86::LEA32r; - NewMI = BuildMI(MF, get(Opc)).addReg(Dest, true, false, false, isDead) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) + .addReg(Dest, true, false, false, isDead) .addReg(0).addImm(1 << ShAmt) .addReg(Src, false, false, isKill).addImm(0); break; @@ -1084,17 +1090,21 @@ // Build and insert into an implicit UNDEF value. This is OK because // well be shifting and then extracting the lower 16-bits. - BuildMI(*MFI, MBBI, get(X86::IMPLICIT_DEF), leaInReg); - MachineInstr *InsMI = BuildMI(*MFI, MBBI, get(X86::INSERT_SUBREG),leaInReg) + BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); + MachineInstr *InsMI = + BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg) .addReg(leaInReg).addReg(Src, false, false, isKill) .addImm(X86::SUBREG_16BIT); - NewMI = BuildMI(*MFI, MBBI, get(Opc), leaOutReg).addReg(0).addImm(1 << ShAmt) + NewMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(Opc), leaOutReg) + .addReg(0).addImm(1 << ShAmt) .addReg(leaInReg, false, false, true).addImm(0); - MachineInstr *ExtMI = BuildMI(*MFI, MBBI, get(X86::EXTRACT_SUBREG)) + MachineInstr *ExtMI = + BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG)) .addReg(Dest, true, false, false, isDead) .addReg(leaOutReg, false, false, true).addImm(X86::SUBREG_16BIT); + if (LV) { // Update live variables LV->getVarInfo(leaInReg).Kills.push_back(NewMI); @@ -1106,7 +1116,8 @@ } return ExtMI; } else { - NewMI = BuildMI(MF, get(X86::LEA16r)).addReg(Dest, true, false, false, isDead) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) + .addReg(Dest, true, false, false, isDead) .addReg(0).addImm(1 << ShAmt) .addReg(Src, false, false, isKill).addImm(0); } @@ -1128,7 +1139,7 @@ assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r : (is64Bit ? X86::LEA64_32r : X86::LEA32r); - NewMI = addRegOffset(BuildMI(MF, get(Opc)) + NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) .addReg(Dest, true, false, false, isDead), Src, isKill, 1); break; @@ -1137,7 +1148,7 @@ case X86::INC64_16r: if (DisableLEA16) return 0; assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); - NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r)) + NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) .addReg(Dest, true, false, false, isDead), Src, isKill, 1); break; @@ -1147,7 +1158,7 @@ assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r : (is64Bit ? X86::LEA64_32r : X86::LEA32r); - NewMI = addRegOffset(BuildMI(MF, get(Opc)) + NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) .addReg(Dest, true, false, false, isDead), Src, isKill, -1); break; @@ -1156,7 +1167,7 @@ case X86::DEC64_16r: if (DisableLEA16) return 0; assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); - NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r)) + NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) .addReg(Dest, true, false, false, isDead), Src, isKill, -1); break; @@ -1167,7 +1178,7 @@ : (is64Bit ? X86::LEA64_32r : X86::LEA32r); unsigned Src2 = MI->getOperand(2).getReg(); bool isKill2 = MI->getOperand(2).isKill(); - NewMI = addRegReg(BuildMI(MF, get(Opc)) + NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc)) .addReg(Dest, true, false, false, isDead), Src, isKill, Src2, isKill2); if (LV && isKill2) @@ -1179,7 +1190,7 @@ assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); unsigned Src2 = MI->getOperand(2).getReg(); bool isKill2 = MI->getOperand(2).isKill(); - NewMI = addRegReg(BuildMI(MF, get(X86::LEA16r)) + NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) .addReg(Dest, true, false, false, isDead), Src, isKill, Src2, isKill2); if (LV && isKill2) @@ -1190,7 +1201,7 @@ case X86::ADD64ri8: assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); if (MI->getOperand(2).isImm()) - NewMI = addRegOffset(BuildMI(MF, get(X86::LEA64r)) + NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) .addReg(Dest, true, false, false, isDead), Src, isKill, MI->getOperand(2).getImm()); break; @@ -1199,7 +1210,7 @@ assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); if (MI->getOperand(2).isImm()) { unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; - NewMI = addRegOffset(BuildMI(MF, get(Opc)) + NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) .addReg(Dest, true, false, false, isDead), Src, isKill, MI->getOperand(2).getImm()); } @@ -1209,7 +1220,7 @@ if (DisableLEA16) return 0; assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); if (MI->getOperand(2).isImm()) - NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r)) + NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) .addReg(Dest, true, false, false, isDead), Src, isKill, MI->getOperand(2).getImm()); break; @@ -1227,7 +1238,7 @@ unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r : (MIOpc == X86::SHL32ri ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r); - NewMI = addFullAddress(BuildMI(MF, get(Opc)) + NewMI = addFullAddress(BuildMI(MF, MI->getDebugLoc(), get(Opc)) .addReg(Dest, true, false, false, isDead), AM); if (isKill) NewMI->getOperand(3).setIsKill(true); @@ -1668,6 +1679,9 @@ unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if (DestRC == SrcRC) { unsigned Opc; if (DestRC == &X86::GR64RegClass) { @@ -1699,7 +1713,7 @@ } else { return false; } - BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg); return true; } @@ -1708,24 +1722,24 @@ if (SrcReg != X86::EFLAGS) return false; if (DestRC == &X86::GR64RegClass) { - BuildMI(MBB, MI, get(X86::PUSHFQ)); - BuildMI(MBB, MI, get(X86::POP64r), DestReg); + BuildMI(MBB, MI, DL, get(X86::PUSHFQ)); + BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg); return true; } else if (DestRC == &X86::GR32RegClass) { - BuildMI(MBB, MI, get(X86::PUSHFD)); - BuildMI(MBB, MI, get(X86::POP32r), DestReg); + BuildMI(MBB, MI, DL, get(X86::PUSHFD)); + BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg); return true; } } else if (DestRC == &X86::CCRRegClass) { if (DestReg != X86::EFLAGS) return false; if (SrcRC == &X86::GR64RegClass) { - BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg); - BuildMI(MBB, MI, get(X86::POPFQ)); + BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(X86::POPFQ)); return true; } else if (SrcRC == &X86::GR32RegClass) { - BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg); - BuildMI(MBB, MI, get(X86::POPFD)); + BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(X86::POPFD)); return true; } } @@ -1747,7 +1761,7 @@ return false; Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80; } - BuildMI(MBB, MI, get(Opc), DestReg); + BuildMI(MBB, MI, DL, get(Opc), DestReg); return true; } @@ -1768,7 +1782,7 @@ return false; Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80; } - BuildMI(MBB, MI, get(Opc)).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg); return true; } @@ -1822,8 +1836,10 @@ bool isAligned = (RI.getStackAlignment() >= 16) || RI.needsStackRealignment(MF); unsigned Opc = getStoreRegOpcode(RC, isAligned); - addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx) - .addReg(SrcReg, false, false, isKill); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) + .addReg(SrcReg, false, false, isKill); } void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, @@ -1887,7 +1903,9 @@ bool isAligned = (RI.getStackAlignment() >= 16) || RI.needsStackRealignment(MF); unsigned Opc = getLoadRegOpcode(RC, isAligned); - addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); } void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, @@ -1904,11 +1922,14 @@ } bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, + MachineBasicBlock::iterator MI, const std::vector &CSI) const { if (CSI.empty()) return false; + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + bool is64Bit = TM.getSubtarget().is64Bit(); unsigned SlotSize = is64Bit ? 8 : 4; @@ -1928,17 +1949,20 @@ } bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, + MachineBasicBlock::iterator MI, const std::vector &CSI) const { if (CSI.empty()) return false; - + + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + bool is64Bit = TM.getSubtarget().is64Bit(); unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r; for (unsigned i = 0, e = CSI.size(); i != e; ++i) { unsigned Reg = CSI[i].getReg(); - BuildMI(MBB, MI, get(Opc), Reg); + BuildMI(MBB, MI, DL, get(Opc), Reg); } return true; } @@ -1998,7 +2022,7 @@ const SmallVectorImpl &MOs, MachineInstr *MI) { MachineFunction &MF = *MI->getParent()->getParent(); - MachineInstrBuilder MIB = BuildMI(MF, TII.get(Opcode)); + MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); unsigned NumAddrOps = MOs.size(); for (unsigned i = 0; i != NumAddrOps; ++i) @@ -2258,7 +2282,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, - SmallVectorImpl &NewMIs) const { + SmallVectorImpl &NewMIs) const { DenseMap >::iterator I = MemOp2RegOpTable.find((unsigned*)MI->getOpcode()); if (I == MemOp2RegOpTable.end()) @@ -2361,7 +2385,7 @@ bool X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, - SmallVectorImpl &NewNodes) const { + SmallVectorImpl &NewNodes) const { if (!N->isMachineOpcode()) return false; @@ -3078,13 +3102,16 @@ // Insert the set of GlobalBaseReg into the first MBB of the function MachineBasicBlock &FirstMBB = MF->front(); MachineBasicBlock::iterator MBBI = FirstMBB.begin(); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MBBI != FirstMBB.end()) DL = MBBI->getDebugLoc(); MachineRegisterInfo &RegInfo = MF->getRegInfo(); unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass); const TargetInstrInfo *TII = TM.getInstrInfo(); // Operand of MovePCtoStack is completely ignored by asm printer. It's // only used in JIT code emission as displacement to pc. - BuildMI(FirstMBB, MBBI, TII->get(X86::MOVPC32r), PC).addImm(0); + BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC) + .addImm(0); // If we're using vanilla 'GOT' PIC style, we should use relative addressing // not to pc, but to _GLOBAL_ADDRESS_TABLE_ external @@ -3092,7 +3119,7 @@ TM.getSubtarget().isPICStyleGOT()) { GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass); - BuildMI(FirstMBB, MBBI, TII->get(X86::ADD32ri), GlobalBaseReg) + BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_"); } else { GlobalBaseReg = PC; From ggreif at gmail.com Wed Feb 11 16:09:02 2009 From: ggreif at gmail.com (Gabor Greif) Date: Wed, 11 Feb 2009 22:09:02 -0000 Subject: [llvm-commits] [llvm] r64331 - /llvm/trunk/include/llvm/OperandTraits.h Message-ID: <200902112209.n1BM927O019627@zion.cs.uiuc.edu> Author: ggreif Date: Wed Feb 11 16:09:00 2009 New Revision: 64331 URL: http://llvm.org/viewvc/llvm-project?rev=64331&view=rev Log: Fill in a glaring omission in derived User classes, namely add efficient versions of op_begin and op_end. Up to now always those from User have been called, which in most cases follow an indirection (OperandList) even if the exact Instruction type is known. Modified: llvm/trunk/include/llvm/OperandTraits.h Modified: llvm/trunk/include/llvm/OperandTraits.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/OperandTraits.h?rev=64331&r1=64330&r2=64331&view=diff ============================================================================== --- llvm/trunk/include/llvm/OperandTraits.h (original) +++ llvm/trunk/include/llvm/OperandTraits.h Wed Feb 11 16:09:00 2009 @@ -119,6 +119,10 @@ public: \ inline VALUECLASS *getOperand(unsigned) const; \ inline void setOperand(unsigned, VALUECLASS*); \ + inline op_iterator op_begin(); \ + inline const_op_iterator op_begin() const; \ + inline op_iterator op_end(); \ + inline const_op_iterator op_end() const; \ protected: \ template inline Use &Op(); \ template inline const Use &Op() const; \ @@ -127,6 +131,18 @@ /// Macro for generating out-of-class operand accessor definitions #define DEFINE_TRANSPARENT_OPERAND_ACCESSORS(CLASS, VALUECLASS) \ +CLASS::op_iterator CLASS::op_begin() { \ + return OperandTraits::op_begin(this); \ +} \ +CLASS::const_op_iterator CLASS::op_begin() const { \ + return OperandTraits::op_begin(const_cast(this)); \ +} \ +CLASS::op_iterator CLASS::op_end() { \ + return OperandTraits::op_end(this); \ +} \ +CLASS::const_op_iterator CLASS::op_end() const { \ + return OperandTraits::op_end(const_cast(this)); \ +} \ VALUECLASS *CLASS::getOperand(unsigned i_nocapture) const { \ assert(i_nocapture < OperandTraits::operands(this) \ && "getOperand() out of range!"); \ @@ -153,6 +169,18 @@ /// Macro for generating out-of-class operand accessor /// definitions with casted result #define DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS(CLASS, VALUECLASS) \ +CLASS::op_iterator CLASS::op_begin() { \ + return OperandTraits::op_begin(this); \ +} \ +CLASS::const_op_iterator CLASS::op_begin() const { \ + return OperandTraits::op_begin(const_cast(this)); \ +} \ +CLASS::op_iterator CLASS::op_end() { \ + return OperandTraits::op_end(this); \ +} \ +CLASS::const_op_iterator CLASS::op_end() const { \ + return OperandTraits::op_end(const_cast(this)); \ +} \ VALUECLASS *CLASS::getOperand(unsigned i_nocapture) const { \ assert(i_nocapture < OperandTraits::operands(this) \ && "getOperand() out of range!"); \ From dalej at apple.com Wed Feb 11 16:14:51 2009 From: dalej at apple.com (Dale Johannesen) Date: Wed, 11 Feb 2009 22:14:51 -0000 Subject: [llvm-commits] [llvm] r64332 - /llvm/trunk/docs/LangRef.html Message-ID: <200902112214.n1BMEqfN019961@zion.cs.uiuc.edu> Author: johannes Date: Wed Feb 11 16:14:51 2009 New Revision: 64332 URL: http://llvm.org/viewvc/llvm-project?rev=64332&view=rev Log: Edit description of floating point constants to reflect reality. Acknowledgements to John Clements for prodding me into this. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=64332&r1=64331&r2=64332&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Wed Feb 11 16:14:51 2009 @@ -1760,16 +1760,31 @@ -

    The one non-intuitive notation for constants is the optional hexadecimal form +

    The one non-intuitive notation for constants is the hexadecimal form of floating point constants. For example, the form 'double 0x432ff973cafa8000' is equivalent to (but harder to read than) 'double 4.5e+15'. The only time hexadecimal floating point constants are required (and the only time that they are generated by the disassembler) is when a floating point constant must be emitted but it cannot be represented as a -decimal floating point number. For example, NaN's, infinities, and other +decimal floating point number in a reasonable number of digits. For example, +NaN's, infinities, and other special values are represented in their IEEE hexadecimal format so that assembly and disassembly do not cause any bits to change in the constants.

    - +

    When using the hexadecimal form, constants of types float and double are +represented using the 16-digit form shown above (which matches the IEEE754 +representation for double); float values must, however, be exactly representable +as IEE754 single precision. +Hexadecimal format is always used for long +double, and there are three forms of long double. The 80-bit +format used by x86 is represented as 0xK +followed by 20 hexadecimal digits. +The 128-bit format used by PowerPC (two adjacent doubles) is represented +by 0xM followed by 32 hexadecimal digits. The IEEE 128-bit +format is represented +by 0xL followed by 32 hexadecimal digits; no currently supported +target uses this format. Long doubles will only work if they match +the long double format on your target. All hexadecimal formats are big-endian +(sign bit at the left).

    From natebegeman at mac.com Wed Feb 11 16:36:25 2009 From: natebegeman at mac.com (Nate Begeman) Date: Wed, 11 Feb 2009 22:36:25 -0000 Subject: [llvm-commits] [llvm] r64335 - /llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200902112236.n1BMaPo4020702@zion.cs.uiuc.edu> Author: sampo Date: Wed Feb 11 16:36:25 2009 New Revision: 64335 URL: http://llvm.org/viewvc/llvm-project?rev=64335&view=rev Log: the two non-mask arguments to a shufflevector must be the same width, but they do not have to be the same width as the result value. Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=64335&r1=64334&r2=64335&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Wed Feb 11 16:36:25 2009 @@ -1538,11 +1538,12 @@ } } + APInt UndefElts4(LHSVWidth, 0); TmpV = SimplifyDemandedVectorElts(I->getOperand(0), LeftDemanded, - UndefElts2, Depth+1); + UndefElts4, Depth+1); if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; } - APInt UndefElts3(VWidth, 0); + APInt UndefElts3(LHSVWidth, 0); TmpV = SimplifyDemandedVectorElts(I->getOperand(1), RightDemanded, UndefElts3, Depth+1); if (TmpV) { I->setOperand(1, TmpV); MadeChange = true; } @@ -1553,7 +1554,7 @@ if (MaskVal == -1u) { UndefElts.set(i); } else if (MaskVal < LHSVWidth) { - if (UndefElts2[MaskVal]) { + if (UndefElts4[MaskVal]) { NewUndefElts = true; UndefElts.set(i); } From evan.cheng at apple.com Wed Feb 11 17:39:08 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 11 Feb 2009 15:39:08 -0800 Subject: [llvm-commits] [llvm] r64319 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp In-Reply-To: <200902112026.n1BKQ7Mx015291@zion.cs.uiuc.edu> References: <200902112026.n1BKQ7Mx015291@zion.cs.uiuc.edu> Message-ID: <9A93821B-CAC8-4EEF-B234-0144CE9F4212@apple.com> Ok. Is this targeting anything in particular? A test case? Evan On Feb 11, 2009, at 12:26 PM, Dan Gohman wrote: > Author: djg > Date: Wed Feb 11 14:25:59 2009 > New Revision: 64319 > > URL: http://llvm.org/viewvc/llvm-project?rev=64319&view=rev > Log: > Delete the heuristic for non-livein CopyFromReg nodes. Non-liveinness > is determined by whether the node has a Flag operand. However, if the > node does have a Flag operand, it will be glued to its register's > def, so the heuristic would end up spuriously applying to whatever > node is the def. > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=64319&r1=64318&r2=64319&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp > (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed > Feb 11 14:25:59 2009 > @@ -899,12 +899,6 @@ > }; > } // end anonymous namespace > > -static inline bool isCopyFromLiveIn(const SUnit *SU) { > - SDNode *N = SU->getNode(); > - return N && N->getOpcode() == ISD::CopyFromReg && > - N->getOperand(N->getNumOperands()-1).getValueType() != MVT::Flag; > -} > - > /// CalcNodeSethiUllmanNumber - Compute Sethi Ullman number. > /// Smaller number is the higher priority. > static unsigned > @@ -986,11 +980,6 @@ > unsigned getNodePriority(const SUnit *SU) const { > assert(SU->NodeNum < SethiUllmanNumbers.size()); > unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0; > - if (Opc == ISD::CopyFromReg && !isCopyFromLiveIn(SU)) > - // CopyFromReg should be close to its def because it > restricts > - // allocation choices. But if it is a livein then perhaps > we want it > - // closer to its uses so it can be coalesced. > - return 0xffff; > if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) > // CopyToReg should be close to its uses to facilitate > coalescing and > // avoid spilling. > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Wed Feb 11 17:41:58 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 11 Feb 2009 23:41:58 -0000 Subject: [llvm-commits] [llvm] r64339 - in /llvm/trunk: lib/CodeGen/VirtRegMap.cpp test/CodeGen/X86/pr3495-2.ll Message-ID: <200902112341.n1BNfxXu023693@zion.cs.uiuc.edu> Author: evancheng Date: Wed Feb 11 17:41:57 2009 New Revision: 64339 URL: http://llvm.org/viewvc/llvm-project?rev=64339&view=rev Log: Remove a bogus assertion. It's possible a live-in available value is used by a previous instruction. Added: llvm/trunk/test/CodeGen/X86/pr3495-2.ll Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=64339&r1=64338&r2=64339&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Wed Feb 11 17:41:57 2009 @@ -1344,8 +1344,6 @@ int SSorRMId = DoReMat ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg); unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId); - assert((!InReg || !RegKills[InReg]) && - "Restoring a value that's previously defined in the same BB?"); if (InReg == Phys) { // If the value is already available in the expected register, save // a reload / remat. Added: llvm/trunk/test/CodeGen/X86/pr3495-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr3495-2.ll?rev=64339&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pr3495-2.ll (added) +++ llvm/trunk/test/CodeGen/X86/pr3495-2.ll Wed Feb 11 17:41:57 2009 @@ -0,0 +1,49 @@ +; RUN: llvm-as < %s | llc -march=x86 -relocation-model=pic -disable-fp-elim -stats |& grep {Number of reloads omited} + +target triple = "i386-apple-darwin9.6" + %struct.constraintVCGType = type { i32, i32, i32, i32 } + %struct.nodeVCGType = type { %struct.constraintVCGType*, i32, i32, i32, %struct.constraintVCGType*, i32, i32, i32 } + +define fastcc void @SCC_DFSBelowVCG(%struct.nodeVCGType* %VCG, i32 %net, i32 %label) nounwind { +entry: + %0 = getelementptr %struct.nodeVCGType* %VCG, i32 %net, i32 5 ; [#uses=2] + %1 = load i32* %0, align 4 ; [#uses=1] + %2 = icmp eq i32 %1, 0 ; [#uses=1] + br i1 %2, label %bb5, label %bb.nph3 + +bb.nph3: ; preds = %entry + %3 = getelementptr %struct.nodeVCGType* %VCG, i32 %net, i32 4 ; <%struct.constraintVCGType**> [#uses=1] + br label %bb + +bb: ; preds = %bb3, %bb.nph3 + %s.02 = phi i32 [ 0, %bb.nph3 ], [ %12, %bb3 ] ; [#uses=2] + %4 = load %struct.constraintVCGType** %3, align 4 ; <%struct.constraintVCGType*> [#uses=1] + %5 = icmp eq i32 0, 0 ; [#uses=1] + br i1 %5, label %bb1, label %bb3 + +bb1: ; preds = %bb + %6 = getelementptr %struct.constraintVCGType* %4, i32 %s.02, i32 0 ; [#uses=1] + %7 = load i32* %6, align 4 ; [#uses=2] + %8 = getelementptr %struct.nodeVCGType* %VCG, i32 %7, i32 7 ; [#uses=1] + %9 = load i32* %8, align 4 ; [#uses=1] + %10 = icmp eq i32 %9, 0 ; [#uses=1] + br i1 %10, label %bb2, label %bb3 + +bb2: ; preds = %bb1 + %11 = getelementptr %struct.nodeVCGType* %VCG, i32 %7, i32 4 ; <%struct.constraintVCGType**> [#uses=0] + br label %bb.i + +bb.i: ; preds = %bb.i, %bb2 + br label %bb.i + +bb3: ; preds = %bb1, %bb + %12 = add i32 %s.02, 1 ; [#uses=2] + %13 = load i32* %0, align 4 ; [#uses=1] + %14 = icmp ugt i32 %13, %12 ; [#uses=1] + br i1 %14, label %bb, label %bb5 + +bb5: ; preds = %bb3, %entry + %15 = getelementptr %struct.nodeVCGType* %VCG, i32 %net, i32 6 ; [#uses=1] + store i32 %label, i32* %15, align 4 + ret void +} From evan.cheng at apple.com Wed Feb 11 17:42:39 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 11 Feb 2009 23:42:39 -0000 Subject: [llvm-commits] [llvm] r64340 - /llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp Message-ID: <200902112342.n1BNgdFD023732@zion.cs.uiuc.edu> Author: evancheng Date: Wed Feb 11 17:42:39 2009 New Revision: 64340 URL: http://llvm.org/viewvc/llvm-project?rev=64340&view=rev Log: Apparently some MachineBasicBlock's don't have corresponding llvm basic blocks. Modified: llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp Modified: llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp?rev=64340&r1=64339&r2=64340&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp Wed Feb 11 17:42:39 2009 @@ -83,9 +83,13 @@ void ScheduleDAG::viewGraph() { // This code is only for debugging! #ifndef NDEBUG - ViewGraph(this, "dag." + MF.getFunction()->getName(), - "Scheduling-Units Graph for " + MF.getFunction()->getName() + ':' + - BB->getBasicBlock()->getName()); + if (BB->getBasicBlock()) + ViewGraph(this, "dag." + MF.getFunction()->getName(), + "Scheduling-Units Graph for " + MF.getFunction()->getName() + ':' + + BB->getBasicBlock()->getName()); + else + ViewGraph(this, "dag." + MF.getFunction()->getName(), + "Scheduling-Units Graph for " + MF.getFunction()->getName()); #else cerr << "ScheduleDAG::viewGraph is only available in debug builds on " << "systems with Graphviz or gv!\n"; From isanbard at gmail.com Wed Feb 11 18:02:55 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 12 Feb 2009 00:02:55 -0000 Subject: [llvm-commits] [llvm] r64342 - in /llvm/trunk/lib/Target: ARM/ARMInstrInfo.cpp Alpha/AlphaInstrInfo.cpp CellSPU/SPUInstrInfo.cpp IA64/IA64InstrInfo.cpp Mips/MipsInstrInfo.cpp PIC16/PIC16InstrInfo.cpp PowerPC/PPCInstrInfo.cpp PowerPC/PPCInstrInfo.h Sparc/SparcInstrInfo.cpp XCore/XCoreInstrInfo.cpp Message-ID: <200902120002.n1C02ulJ024544@zion.cs.uiuc.edu> Author: void Date: Wed Feb 11 18:02:55 2009 New Revision: 64342 URL: http://llvm.org/viewvc/llvm-project?rev=64342&view=rev Log: Move debug loc info along when the spiller creates new instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=64342&r1=64341&r2=64342&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Wed Feb 11 18:02:55 2009 @@ -243,17 +243,20 @@ // Can't encode it in a so_imm operand. This transformation will // add more than 1 instruction. Abandon! return NULL; - UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) + UpdateMI = BuildMI(MF, MI->getDebugLoc(), + get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) .addReg(BaseReg).addImm(SOImmVal) .addImm(Pred).addReg(0).addReg(0); } else if (Amt != 0) { ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); - UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) + UpdateMI = BuildMI(MF, MI->getDebugLoc(), + get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) .addImm(Pred).addReg(0).addReg(0); } else - UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) + UpdateMI = BuildMI(MF, MI->getDebugLoc(), + get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) .addReg(BaseReg).addReg(OffReg) .addImm(Pred).addReg(0).addReg(0); break; @@ -263,11 +266,13 @@ unsigned Amt = ARM_AM::getAM3Offset(OffImm); if (OffReg == 0) // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. - UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) + UpdateMI = BuildMI(MF, MI->getDebugLoc(), + get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) .addReg(BaseReg).addImm(Amt) .addImm(Pred).addReg(0).addReg(0); else - UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) + UpdateMI = BuildMI(MF, MI->getDebugLoc(), + get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) .addReg(BaseReg).addReg(OffReg) .addImm(Pred).addReg(0).addReg(0); break; @@ -277,19 +282,23 @@ std::vector NewMIs; if (isPre) { if (isLoad) - MemMI = BuildMI(MF, get(MemOpc), MI->getOperand(0).getReg()) + MemMI = BuildMI(MF, MI->getDebugLoc(), + get(MemOpc), MI->getOperand(0).getReg()) .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); else - MemMI = BuildMI(MF, get(MemOpc)).addReg(MI->getOperand(1).getReg()) + MemMI = BuildMI(MF, MI->getDebugLoc(), + get(MemOpc)).addReg(MI->getOperand(1).getReg()) .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); NewMIs.push_back(MemMI); NewMIs.push_back(UpdateMI); } else { if (isLoad) - MemMI = BuildMI(MF, get(MemOpc), MI->getOperand(0).getReg()) + MemMI = BuildMI(MF, MI->getDebugLoc(), + get(MemOpc), MI->getOperand(0).getReg()) .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); else - MemMI = BuildMI(MF, get(MemOpc)).addReg(MI->getOperand(1).getReg()) + MemMI = BuildMI(MF, MI->getDebugLoc(), + get(MemOpc)).addReg(MI->getOperand(1).getReg()) .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); if (WB.isDead()) UpdateMI->getOperand(0).setIsDead(); @@ -474,19 +483,22 @@ return false; } + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (DestRC == ARM::GPRRegisterClass) { MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo(); if (AFI->isThumbFunction()) - BuildMI(MBB, I, get(ARM::tMOVr), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg); else - AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, get(ARM::MOVr), DestReg) + AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) .addReg(SrcReg))); } else if (DestRC == ARM::SPRRegisterClass) - AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYS), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg) .addReg(SrcReg)); else if (DestRC == ARM::DPRRegisterClass) - AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYD), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg) .addReg(SrcReg)); else return false; @@ -512,33 +524,37 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (RC == ARM::GPRRegisterClass) { MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo(); if (AFI->isThumbFunction()) - BuildMI(MBB, I, get(ARM::tSpill)).addReg(SrcReg, false, false, isKill) + BuildMI(MBB, I, DL, get(ARM::tSpill)) + .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addImm(0); else - AddDefaultPred(BuildMI(MBB, I, get(ARM::STR)) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addReg(0).addImm(0)); } else if (RC == ARM::DPRRegisterClass) { - AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTD)) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD)) .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addImm(0)); } else { assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); - AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTS)) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS)) .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addImm(0)); } } void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - bool isKill, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl &NewMIs) const { + bool isKill, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl &NewMIs) const{ unsigned Opc = 0; if (RC == ARM::GPRRegisterClass) { ARMFunctionInfo *AFI = MF.getInfo(); @@ -572,28 +588,31 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (RC == ARM::GPRRegisterClass) { MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo(); if (AFI->isThumbFunction()) - BuildMI(MBB, I, get(ARM::tRestore), DestReg) + BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg) .addFrameIndex(FI).addImm(0); else - AddDefaultPred(BuildMI(MBB, I, get(ARM::LDR), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) .addFrameIndex(FI).addReg(0).addImm(0)); } else if (RC == ARM::DPRRegisterClass) { - AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDD), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg) .addFrameIndex(FI).addImm(0)); } else { assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); - AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDS), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg) .addFrameIndex(FI).addImm(0)); } } void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; if (RC == ARM::GPRRegisterClass) { @@ -630,7 +649,10 @@ if (!AFI->isThumbFunction() || CSI.empty()) return false; - MachineInstrBuilder MIB = BuildMI(MBB, MI, get(ARM::tPUSH)); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + + MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH)); for (unsigned i = CSI.size(); i != 0; --i) { unsigned Reg = CSI[i-1].getReg(); // Add the callee-saved register as live-in. It's killed at the spill. @@ -686,12 +708,14 @@ if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = BuildMI(MF, get(ARM::STR)).addReg(SrcReg, false, false, isKill) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR)) + .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(MF, get(ARM::LDR)).addReg(DstReg, true, false, false, isDead) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR)) + .addReg(DstReg, true, false, false, isDead) .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); } break; @@ -703,7 +727,8 @@ if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg)) // tSpill cannot take a high register operand. break; - NewMI = BuildMI(MF, get(ARM::tSpill)).addReg(SrcReg, false, false, isKill) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill)) + .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addImm(0); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); @@ -711,7 +736,7 @@ // tRestore cannot target a high register operand. break; bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(MF, get(ARM::tRestore)) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore)) .addReg(DstReg, true, false, false, isDead) .addFrameIndex(FI).addImm(0); } @@ -722,11 +747,13 @@ unsigned PredReg = MI->getOperand(3).getReg(); if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); - NewMI = BuildMI(MF, get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS)) + .addReg(SrcReg).addFrameIndex(FI) .addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); - NewMI = BuildMI(MF, get(ARM::FLDS), DstReg).addFrameIndex(FI) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS), DstReg) + .addFrameIndex(FI) .addImm(0).addImm(Pred).addReg(PredReg); } break; @@ -737,12 +764,14 @@ if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = BuildMI(MF, get(ARM::FSTD)).addReg(SrcReg, false, false, isKill) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD)) + .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(MF, get(ARM::FLDD)).addReg(DstReg, true, false, false, isDead) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD)) + .addReg(DstReg, true, false, false, isDead) .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); } break; Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=64342&r1=64341&r2=64342&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Wed Feb 11 18:02:55 2009 @@ -105,8 +105,8 @@ } unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB, - MachineBasicBlock *TBB, - MachineBasicBlock *FBB, + MachineBasicBlock *TBB, + MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const { assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && @@ -138,22 +138,31 @@ } bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n"; if (DestRC != SrcRC) { // Not yet supported! return false; } + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if (DestRC == Alpha::GPRCRegisterClass) { - BuildMI(MBB, MI, get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(Alpha::BISr), DestReg) + .addReg(SrcReg) + .addReg(SrcReg); } else if (DestRC == Alpha::F4RCRegisterClass) { - BuildMI(MBB, MI, get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(Alpha::CPYSS), DestReg) + .addReg(SrcReg) + .addReg(SrcReg); } else if (DestRC == Alpha::F8RCRegisterClass) { - BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(Alpha::CPYST), DestReg) + .addReg(SrcReg) + .addReg(SrcReg); } else { // Attempt to copy register that is not GPR or FPR return false; @@ -164,22 +173,26 @@ void AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned SrcReg, bool isKill, int FrameIdx, - const TargetRegisterClass *RC) const { + MachineBasicBlock::iterator MI, + unsigned SrcReg, bool isKill, int FrameIdx, + const TargetRegisterClass *RC) const { //cerr << "Trying to store " << getPrettyName(SrcReg) << " to " // << FrameIdx << "\n"; //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); + + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if (RC == Alpha::F4RCRegisterClass) - BuildMI(MBB, MI, get(Alpha::STS)) + BuildMI(MBB, MI, DL, get(Alpha::STS)) .addReg(SrcReg, false, false, isKill) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::F8RCRegisterClass) - BuildMI(MBB, MI, get(Alpha::STT)) + BuildMI(MBB, MI, DL, get(Alpha::STT)) .addReg(SrcReg, false, false, isKill) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::GPRCRegisterClass) - BuildMI(MBB, MI, get(Alpha::STQ)) + BuildMI(MBB, MI, DL, get(Alpha::STQ)) .addReg(SrcReg, false, false, isKill) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else @@ -219,14 +232,17 @@ const TargetRegisterClass *RC) const { //cerr << "Trying to load " << getPrettyName(DestReg) << " to " // << FrameIdx << "\n"; + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if (RC == Alpha::F4RCRegisterClass) - BuildMI(MBB, MI, get(Alpha::LDS), DestReg) + BuildMI(MBB, MI, DL, get(Alpha::LDS), DestReg) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::F8RCRegisterClass) - BuildMI(MBB, MI, get(Alpha::LDT), DestReg) + BuildMI(MBB, MI, DL, get(Alpha::LDT), DestReg) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::GPRCRegisterClass) - BuildMI(MBB, MI, get(Alpha::LDQ), DestReg) + BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else abort(); @@ -279,7 +295,8 @@ bool isKill = MI->getOperand(1).isKill(); Opc = (Opc == Alpha::BISr) ? Alpha::STQ : ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT); - NewMI = BuildMI(MF, get(Opc)).addReg(InReg, false, false, isKill) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) + .addReg(InReg, false, false, isKill) .addFrameIndex(FrameIndex) .addReg(Alpha::F31); } else { // load -> move @@ -287,7 +304,8 @@ bool isDead = MI->getOperand(0).isDead(); Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT); - NewMI = BuildMI(MF, get(Opc)).addReg(OutReg, true, false, false, isDead) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) + .addReg(OutReg, true, false, false, isDead) .addFrameIndex(FrameIndex) .addReg(Alpha::F31); } @@ -410,7 +428,10 @@ void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { - BuildMI(MBB, MI, get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + BuildMI(MBB, MI, DL, get(Alpha::BISr), Alpha::R31) + .addReg(Alpha::R31) .addReg(Alpha::R31); } Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=64342&r1=64341&r2=64342&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Wed Feb 11 18:02:55 2009 @@ -259,22 +259,25 @@ // we instruction select bitconvert i64 -> f64 as a noop for example, so our // types have no specific meaning. + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if (DestRC == SPU::R8CRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRr8), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRr8), DestReg).addReg(SrcReg); } else if (DestRC == SPU::R16CRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRr16), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRr16), DestReg).addReg(SrcReg); } else if (DestRC == SPU::R32CRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRr32), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRr32), DestReg).addReg(SrcReg); } else if (DestRC == SPU::R32FPRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRf32), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRf32), DestReg).addReg(SrcReg); } else if (DestRC == SPU::R64CRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRr64), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRr64), DestReg).addReg(SrcReg); } else if (DestRC == SPU::R64FPRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRf64), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRf64), DestReg).addReg(SrcReg); } else if (DestRC == SPU::GPRCRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRr128), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRr128), DestReg).addReg(SrcReg); } else if (DestRC == SPU::VECREGRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRv16i8), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRv16i8), DestReg).addReg(SrcReg); } else { // Attempt to copy unknown/unsupported register class! return false; @@ -312,15 +315,17 @@ abort(); } - addFrameReference(BuildMI(MBB, MI, get(opc)) + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + addFrameReference(BuildMI(MBB, MI, DL, get(opc)) .addReg(SrcReg, false, false, isKill), FrameIdx); } void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - bool isKill, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl &NewMIs) const { + bool isKill, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl &NewMIs) const { cerr << "storeRegToAddr() invoked!\n"; abort(); @@ -388,7 +393,9 @@ abort(); } - addFrameReference(BuildMI(MBB, MI, get(opc)).addReg(DestReg), FrameIdx); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + addFrameReference(BuildMI(MBB, MI, DL, get(opc)).addReg(DestReg), FrameIdx); } /*! @@ -495,7 +502,8 @@ unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); if (FrameIndex < SPUFrameInfo::maxFrameOffset()) { - MachineInstrBuilder MIB = BuildMI(MF, get(SPU::STQDr32)); + MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), + get(SPU::STQDr32)); MIB.addReg(InReg, false, false, isKill); NewMI = addFrameReference(MIB, FrameIndex); @@ -503,7 +511,7 @@ } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)); + MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)); MIB.addReg(OutReg, true, false, false, isDead); Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset()) Modified: llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp?rev=64342&r1=64341&r2=64342&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp Wed Feb 11 18:02:55 2009 @@ -62,21 +62,24 @@ } bool IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { if (DestRC != SrcRC) { // Not yet supported! return false; } + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode // (SrcReg) DestReg = cmp.eq.unc(r0, r0) - BuildMI(MBB, MI, get(IA64::PCMPEQUNC), DestReg) + BuildMI(MBB, MI, DL, get(IA64::PCMPEQUNC), DestReg) .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg); else // otherwise, MOV works (for both gen. regs and FP regs) - BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(IA64::MOV), DestReg).addReg(SrcReg); return true; } @@ -86,30 +89,34 @@ unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC) const{ + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); if (RC == IA64::FPRegisterClass) { - BuildMI(MBB, MI, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx) + BuildMI(MBB, MI, DL, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx) .addReg(SrcReg, false, false, isKill); } else if (RC == IA64::GRRegisterClass) { - BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx) + BuildMI(MBB, MI, DL, get(IA64::ST8)).addFrameIndex(FrameIdx) .addReg(SrcReg, false, false, isKill); } else if (RC == IA64::PRRegisterClass) { /* we use IA64::r2 as a temporary register for doing this hackery. */ // first we load 0: - BuildMI(MBB, MI, get(IA64::MOV), IA64::r2).addReg(IA64::r0); + BuildMI(MBB, MI, DL, get(IA64::MOV), IA64::r2).addReg(IA64::r0); // then conditionally add 1: - BuildMI(MBB, MI, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2) + BuildMI(MBB, MI, DL, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2) .addImm(1).addReg(SrcReg, false, false, isKill); // and then store it to the stack - BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2); + BuildMI(MBB, MI, DL, get(IA64::ST8)) + .addFrameIndex(FrameIdx) + .addReg(IA64::r2); } else assert(0 && "sorry, I don't know how to store this sort of reg in the stack\n"); } void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - bool isKill, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, + bool isKill, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; if (RC == IA64::FPRegisterClass) { @@ -140,28 +147,34 @@ } void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, int FrameIdx, - const TargetRegisterClass *RC)const{ + MachineBasicBlock::iterator MI, + unsigned DestReg, int FrameIdx, + const TargetRegisterClass *RC)const{ + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); if (RC == IA64::FPRegisterClass) { - BuildMI(MBB, MI, get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx); + BuildMI(MBB, MI, DL, get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx); } else if (RC == IA64::GRRegisterClass) { - BuildMI(MBB, MI, get(IA64::LD8), DestReg).addFrameIndex(FrameIdx); - } else if (RC == IA64::PRRegisterClass) { - // first we load a byte from the stack into r2, our 'predicate hackery' - // scratch reg - BuildMI(MBB, MI, get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx); - // then we compare it to zero. If it _is_ zero, compare-not-equal to - // r0 gives us 0, which is what we want, so that's nice. - BuildMI(MBB, MI, get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0); - } else assert(0 && - "sorry, I don't know how to load this sort of reg from the stack\n"); + BuildMI(MBB, MI, DL, get(IA64::LD8), DestReg).addFrameIndex(FrameIdx); + } else if (RC == IA64::PRRegisterClass) { + // first we load a byte from the stack into r2, our 'predicate hackery' + // scratch reg + BuildMI(MBB, MI, DL, get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx); + // then we compare it to zero. If it _is_ zero, compare-not-equal to + // r0 gives us 0, which is what we want, so that's nice. + BuildMI(MBB, MI, DL, get(IA64::CMPNE), DestReg) + .addReg(IA64::r2) + .addReg(IA64::r0); + } else { + assert(0 && + "sorry, I don't know how to load this sort of reg from the stack\n"); + } } void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; if (RC == IA64::FPRegisterClass) { Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=64342&r1=64341&r2=64342&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Wed Feb 11 18:02:55 2009 @@ -118,7 +118,9 @@ void MipsInstrInfo:: insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { - BuildMI(MBB, MI, get(Mips::NOP)); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + BuildMI(MBB, MI, DL, get(Mips::NOP)); } bool MipsInstrInfo:: @@ -126,22 +128,25 @@ unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (DestRC != SrcRC) { if ((DestRC == Mips::CPURegsRegisterClass) && (SrcRC == Mips::FGR32RegisterClass)) - BuildMI(MBB, I, get(Mips::MFC1), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg); else if ((DestRC == Mips::CPURegsRegisterClass) && (SrcRC == Mips::AFGR32RegisterClass)) - BuildMI(MBB, I, get(Mips::MFC1A), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::MFC1A), DestReg).addReg(SrcReg); else if ((DestRC == Mips::FGR32RegisterClass) && (SrcRC == Mips::CPURegsRegisterClass)) - BuildMI(MBB, I, get(Mips::MTC1), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg); else if ((DestRC == Mips::AFGR32RegisterClass) && (SrcRC == Mips::CPURegsRegisterClass)) - BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::MTC1A), DestReg).addReg(SrcReg); else if ((DestRC == Mips::AFGR32RegisterClass) && (SrcRC == Mips::CPURegsRegisterClass)) - BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::MTC1A), DestReg).addReg(SrcReg); else if ((SrcRC == Mips::CCRRegisterClass) && (SrcReg == Mips::FCR31)) return true; // This register is used implicitly, no copy needed. @@ -151,11 +156,11 @@ else if ((DestRC == Mips::HILORegisterClass) && (SrcRC == Mips::CPURegsRegisterClass)) { unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO; - BuildMI(MBB, I, get(Opc), DestReg); + BuildMI(MBB, I, DL, get(Opc), DestReg); } else if ((SrcRC == Mips::HILORegisterClass) && (DestRC == Mips::CPURegsRegisterClass)) { unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO; - BuildMI(MBB, I, get(Opc), DestReg); + BuildMI(MBB, I, DL, get(Opc), DestReg); } else // DestRC != SrcRC, Can't copy this register return false; @@ -164,14 +169,14 @@ } if (DestRC == Mips::CPURegsRegisterClass) - BuildMI(MBB, I, get(Mips::ADDu), DestReg).addReg(Mips::ZERO) + BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO) .addReg(SrcReg); else if (DestRC == Mips::FGR32RegisterClass) - BuildMI(MBB, I, get(Mips::FMOV_SO32), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::FMOV_SO32), DestReg).addReg(SrcReg); else if (DestRC == Mips::AFGR32RegisterClass) - BuildMI(MBB, I, get(Mips::FMOV_AS32), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::FMOV_AS32), DestReg).addReg(SrcReg); else if (DestRC == Mips::AFGR64RegisterClass) - BuildMI(MBB, I, get(Mips::FMOV_D32), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg); else // Can't copy this register return false; @@ -181,10 +186,14 @@ void MipsInstrInfo:: storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned SrcReg, bool isKill, int FI, - const TargetRegisterClass *RC) const + unsigned SrcReg, bool isKill, int FI, + const TargetRegisterClass *RC) const { unsigned Opc; + + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (RC == Mips::CPURegsRegisterClass) Opc = Mips::SW; else if (RC == Mips::FGR32RegisterClass) @@ -196,7 +205,7 @@ else assert(0 && "Can't store this register to stack slot"); - BuildMI(MBB, I, get(Opc)).addReg(SrcReg, false, false, isKill) + BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, false, false, isKill) .addImm(0).addFrameIndex(FI); } @@ -248,12 +257,14 @@ else assert(0 && "Can't load this register from stack slot"); - BuildMI(MBB, I, get(Opc), DestReg).addImm(0).addFrameIndex(FI); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0).addFrameIndex(FI); } void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc; if (RC == Mips::CPURegsRegisterClass) @@ -299,12 +310,13 @@ if (Ops[0] == 0) { // COPY -> STORE unsigned SrcReg = MI->getOperand(2).getReg(); bool isKill = MI->getOperand(2).isKill(); - NewMI = BuildMI(MF, get(Mips::SW)).addReg(SrcReg, false, false, isKill) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW)) + .addReg(SrcReg, false, false, isKill) .addImm(0).addFrameIndex(FI); } else { // COPY -> LOAD unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(MF, get(Mips::LW)) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW)) .addReg(DstReg, true, false, false, isDead) .addImm(0).addFrameIndex(FI); } @@ -331,12 +343,13 @@ if (Ops[0] == 0) { // COPY -> STORE unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = BuildMI(MF, get(StoreOpc)).addReg(SrcReg, false, false, isKill) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc)) + .addReg(SrcReg, false, false, isKill) .addImm(0).addFrameIndex(FI) ; } else { // COPY -> LOAD unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(MF, get(LoadOpc)) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc)) .addReg(DstReg, true, false, false, isDead) .addImm(0).addFrameIndex(FI); } Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp?rev=64342&r1=64341&r2=64342&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp Wed Feb 11 18:02:55 2009 @@ -69,6 +69,8 @@ MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); const Function *Func = MBB.getParent()->getFunction(); const std::string FuncName = Func->getName(); @@ -80,7 +82,7 @@ if (RC == PIC16::GPRRegisterClass) { //MachineFunction &MF = *MBB.getParent(); //MachineRegisterInfo &RI = MF.getRegInfo(); - BuildMI(MBB, I, get(PIC16::movwf)) + BuildMI(MBB, I, DL, get(PIC16::movwf)) .addReg(SrcReg, false, false, isKill) .addImm(FI) .addExternalSymbol(tmpName) @@ -96,6 +98,8 @@ MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); const Function *Func = MBB.getParent()->getFunction(); const std::string FuncName = Func->getName(); @@ -107,7 +111,7 @@ if (RC == PIC16::GPRRegisterClass) { //MachineFunction &MF = *MBB.getParent(); //MachineRegisterInfo &RI = MF.getRegInfo(); - BuildMI(MBB, I, get(PIC16::movf), DestReg) + BuildMI(MBB, I, DL, get(PIC16::movf), DestReg) .addImm(FI) .addExternalSymbol(tmpName) .addImm(1); // Emit banksel for it. @@ -123,13 +127,16 @@ unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (DestRC == PIC16::FSR16RegisterClass) { - BuildMI(MBB, I, get(PIC16::copy_fsr), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(PIC16::copy_fsr), DestReg).addReg(SrcReg); return true; } if (DestRC == PIC16::GPRRegisterClass) { - BuildMI(MBB, I, get(PIC16::copy_w), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(PIC16::copy_w), DestReg).addReg(SrcReg); return true; } Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=64342&r1=64341&r2=64342&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Wed Feb 11 18:02:55 2009 @@ -174,7 +174,7 @@ // Create a new instruction. unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); bool Reg0IsDead = MI->getOperand(0).isDead(); - return BuildMI(MF, MI->getDesc()) + return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) .addReg(Reg0, true, false, false, Reg0IsDead) .addReg(Reg2, false, false, Reg2IsKill) .addReg(Reg1, false, false, Reg1IsKill) @@ -197,7 +197,10 @@ void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { - BuildMI(MBB, MI, get(PPC::NOP)); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + + BuildMI(MBB, MI, DL, get(PPC::NOP)); } @@ -321,20 +324,23 @@ return false; } + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if (DestRC == PPC::GPRCRegisterClass) { - BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); } else if (DestRC == PPC::G8RCRegisterClass) { - BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); } else if (DestRC == PPC::F4RCRegisterClass) { - BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::FMRS), DestReg).addReg(SrcReg); } else if (DestRC == PPC::F8RCRegisterClass) { - BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::FMRD), DestReg).addReg(SrcReg); } else if (DestRC == PPC::CRRCRegisterClass) { - BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg); } else if (DestRC == PPC::VRRCRegisterClass) { - BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); } else if (DestRC == PPC::CRBITRCRegisterClass) { - BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg); } else { // Attempt to copy register that is not GPR or FPR return false; @@ -515,37 +521,37 @@ } void -PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, +PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs)const{ if (RC == PPC::GPRCRegisterClass) { if (DestReg != PPC::LR) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), DestReg), - FrameIdx)); + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), + DestReg), FrameIdx)); } else { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R11), - FrameIdx)); - NewMIs.push_back(BuildMI(MF, get(PPC::MTLR)).addReg(PPC::R11)); + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), + PPC::R11), FrameIdx)); + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11)); } } else if (RC == PPC::G8RCRegisterClass) { if (DestReg != PPC::LR8) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), DestReg), + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg), FrameIdx)); } else { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), PPC::R11), - FrameIdx)); - NewMIs.push_back(BuildMI(MF, get(PPC::MTLR8)).addReg(PPC::R11)); + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), + PPC::R11), FrameIdx)); + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11)); } } else if (RC == PPC::F8RCRegisterClass) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFD), DestReg), + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg), FrameIdx)); } else if (RC == PPC::F4RCRegisterClass) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFS), DestReg), + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg), FrameIdx)); } else if (RC == PPC::CRRCRegisterClass) { // FIXME: We use R0 here, because it isn't available for RA. - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R0), + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), PPC::R0), FrameIdx)); // If the reloaded register isn't CR0, shift the bits right so that they are @@ -553,11 +559,11 @@ if (DestReg != PPC::CR0) { unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; // rlwinm r11, r11, 32-ShiftBits, 0, 31. - NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0) + NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0) .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31)); } - NewMIs.push_back(BuildMI(MF, get(PPC::MTCRF), DestReg).addReg(PPC::R0)); + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg).addReg(PPC::R0)); } else if (RC == PPC::CRBITRCRegisterClass) { unsigned Reg = 0; @@ -578,7 +584,7 @@ else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN) Reg = PPC::CR7; - return LoadRegFromStackSlot(MF, Reg, FrameIdx, + return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx, PPC::CRRCRegisterClass, NewMIs); } else if (RC == PPC::VRRCRegisterClass) { @@ -587,9 +593,9 @@ // Dest = LVX 0, R0 // // FIXME: We use R0 here, because it isn't available for RA. - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0), + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), FrameIdx, 0, 0)); - NewMIs.push_back(BuildMI(MF, get(PPC::LVX),DestReg).addReg(PPC::R0) + NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0) .addReg(PPC::R0)); } else { assert(0 && "Unknown regclass!"); @@ -604,7 +610,9 @@ const TargetRegisterClass *RC) const { MachineFunction &MF = *MBB.getParent(); SmallVector NewMIs; - LoadRegFromStackSlot(MF, DestReg, FrameIdx, RC, NewMIs); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs); for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) MBB.insert(MI, NewMIs[i]); } @@ -614,7 +622,8 @@ const TargetRegisterClass *RC, SmallVectorImpl &NewMIs)const{ if (Addr[0].isFI()) { - LoadRegFromStackSlot(MF, DestReg, Addr[0].getIndex(), RC, NewMIs); + LoadRegFromStackSlot(MF, DebugLoc::getUnknownLoc(), + DestReg, Addr[0].getIndex(), RC, NewMIs); return; } @@ -668,13 +677,13 @@ if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::STW)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW)) .addReg(InReg, false, false, isKill), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::LWZ)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ)) .addReg(OutReg, true, false, false, isDead), FrameIndex); } @@ -683,13 +692,13 @@ if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::STD)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD)) .addReg(InReg, false, false, isKill), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::LD)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD)) .addReg(OutReg, true, false, false, isDead), FrameIndex); } @@ -697,13 +706,13 @@ if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::STFD)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFD)) .addReg(InReg, false, false, isKill), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::LFD)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFD)) .addReg(OutReg, true, false, false, isDead), FrameIndex); } @@ -711,13 +720,13 @@ if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::STFS)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFS)) .addReg(InReg, false, false, isKill), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::LFS)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFS)) .addReg(OutReg, true, false, false, isDead), FrameIndex); } Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=64342&r1=64341&r2=64342&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Wed Feb 11 18:02:55 2009 @@ -69,7 +69,7 @@ unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; - void LoadRegFromStackSlot(MachineFunction &MF, + void LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=64342&r1=64341&r2=64342&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Wed Feb 11 18:02:55 2009 @@ -114,21 +114,24 @@ } bool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { + MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { if (DestRC != SrcRC) { // Not yet supported! return false; } + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (DestRC == SP::IntRegsRegisterClass) - BuildMI(MBB, I, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg); + BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg); else if (DestRC == SP::FPRegsRegisterClass) - BuildMI(MBB, I, get(SP::FMOVS), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg).addReg(SrcReg); else if (DestRC == SP::DFPRegsRegisterClass) - BuildMI(MBB, I, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg) + BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg) .addReg(SrcReg); else // Can't copy this register @@ -141,24 +144,27 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + // On the order of operands here: think "[FrameIdx + 0] = SrcReg". if (RC == SP::IntRegsRegisterClass) - BuildMI(MBB, I, get(SP::STri)).addFrameIndex(FI).addImm(0) + BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) .addReg(SrcReg, false, false, isKill); else if (RC == SP::FPRegsRegisterClass) - BuildMI(MBB, I, get(SP::STFri)).addFrameIndex(FI).addImm(0) + BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) .addReg(SrcReg, false, false, isKill); else if (RC == SP::DFPRegsRegisterClass) - BuildMI(MBB, I, get(SP::STDFri)).addFrameIndex(FI).addImm(0) + BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) .addReg(SrcReg, false, false, isKill); else assert(0 && "Can't store this register to stack slot"); } void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - bool isKill, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, + bool isKill, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; if (RC == SP::IntRegsRegisterClass) @@ -190,19 +196,22 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (RC == SP::IntRegsRegisterClass) - BuildMI(MBB, I, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0); + BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0); else if (RC == SP::FPRegsRegisterClass) - BuildMI(MBB, I, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0); + BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0); else if (RC == SP::DFPRegsRegisterClass) - BuildMI(MBB, I, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0); + BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0); else assert(0 && "Can't load this register from stack slot"); } void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; if (RC == SP::IntRegsRegisterClass) @@ -243,11 +252,15 @@ if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == SP::G0&& MI->getOperand(0).isReg() && MI->getOperand(2).isReg()) { if (OpNum == 0) // COPY -> STORE - NewMI = BuildMI(MF, get(SP::STri)).addFrameIndex(FI).addImm(0) - .addReg(MI->getOperand(2).getReg()); + NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::STri)) + .addFrameIndex(FI) + .addImm(0) + .addReg(MI->getOperand(2).getReg()); else // COPY -> LOAD - NewMI = BuildMI(MF, get(SP::LDri), MI->getOperand(0).getReg()) - .addFrameIndex(FI).addImm(0); + NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::LDri), + MI->getOperand(0).getReg()) + .addFrameIndex(FI) + .addImm(0); } break; case SP::FMOVS: @@ -257,13 +270,19 @@ if (OpNum == 0) { // COPY -> STORE unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = BuildMI(MF, get(isFloat ? SP::STFri : SP::STDFri)) - .addFrameIndex(FI).addImm(0).addReg(SrcReg, false, false, isKill); + NewMI = BuildMI(MF, MI->getDebugLoc(), + get(isFloat ? SP::STFri : SP::STDFri)) + .addFrameIndex(FI) + .addImm(0) + .addReg(SrcReg, false, false, isKill); } else { // COPY -> LOAD unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(MF, get(isFloat ? SP::LDFri : SP::LDDFri)) - .addReg(DstReg, true, false, false, isDead).addFrameIndex(FI).addImm(0); + NewMI = BuildMI(MF, MI->getDebugLoc(), + get(isFloat ? SP::LDFri : SP::LDDFri)) + .addReg(DstReg, true, false, false, isDead) + .addFrameIndex(FI) + .addImm(0); } break; } Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp?rev=64342&r1=64341&r2=64342&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp Wed Feb 11 18:02:55 2009 @@ -353,13 +353,18 @@ } bool XCoreInstrInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { + MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (DestRC == SrcRC) { if (DestRC == XCore::GRRegsRegisterClass) { - BuildMI(MBB, I, get(XCore::ADD_2rus), DestReg).addReg(SrcReg).addImm(0); + BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) + .addReg(SrcReg) + .addImm(0); return true; } else { return false; @@ -368,24 +373,31 @@ if (SrcRC == XCore::RRegsRegisterClass && SrcReg == XCore::SP && DestRC == XCore::GRRegsRegisterClass) { - BuildMI(MBB, I, get(XCore::LDAWSP_ru6), DestReg).addImm(0); + BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg) + .addImm(0); return true; } if (DestRC == XCore::RRegsRegisterClass && DestReg == XCore::SP && SrcRC == XCore::GRRegsRegisterClass) { - BuildMI(MBB, I, get(XCore::SETSP_1r)).addReg(SrcReg); + BuildMI(MBB, I, DL, get(XCore::SETSP_1r)) + .addReg(SrcReg); return true; } return false; } void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned SrcReg, bool isKill, int FrameIndex, - const TargetRegisterClass *RC) const -{ - BuildMI(MBB, I, get(XCore::STWFI)).addReg(SrcReg, false, false, isKill) - .addFrameIndex(FrameIndex).addImm(0); + MachineBasicBlock::iterator I, + unsigned SrcReg, bool isKill, + int FrameIndex, + const TargetRegisterClass *RC) const +{ + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + BuildMI(MBB, I, DL, get(XCore::STWFI)) + .addReg(SrcReg, false, false, isKill) + .addFrameIndex(FrameIndex) + .addImm(0); } void XCoreInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, @@ -397,12 +409,15 @@ } void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DestReg, int FrameIndex, - const TargetRegisterClass *RC) const -{ - BuildMI(MBB, I, get(XCore::LDWFI), DestReg).addFrameIndex(FrameIndex) - .addImm(0); + MachineBasicBlock::iterator I, + unsigned DestReg, int FrameIndex, + const TargetRegisterClass *RC) const +{ + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) + .addFrameIndex(FrameIndex) + .addImm(0); } void XCoreInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, @@ -426,6 +441,9 @@ XCoreFunctionInfo *XFI = MF->getInfo(); bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF); + + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); for (std::vector::const_iterator it = CSI.begin(); it != CSI.end(); ++it) { @@ -433,10 +451,10 @@ MBB.addLiveIn(it->getReg()); storeRegToStackSlot(MBB, MI, it->getReg(), true, - it->getFrameIdx(), it->getRegClass()); + it->getFrameIdx(), it->getRegClass()); if (emitFrameMoves) { unsigned SaveLabelId = MMI->NextLabelID(); - BuildMI(MBB, MI, get(XCore::DBG_LABEL)).addImm(SaveLabelId); + BuildMI(MBB, MI, DL, get(XCore::DBG_LABEL)).addImm(SaveLabelId); XFI->getSpillLabels().push_back( std::pair(SaveLabelId, *it)); } From nicholas at mxc.ca Wed Feb 11 21:00:09 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 11 Feb 2009 19:00:09 -0800 Subject: [llvm-commits] [llvm] r64300 - in /llvm/trunk: lib/Analysis/IPA/CallGraphSCCPass.cpp test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll In-Reply-To: <200902112141.33661.baldrick@free.fr> References: <200902110958.n1B9wiM7024990@zion.cs.uiuc.edu> <499309D0.4050706@mxc.ca> <200902112141.33661.baldrick@free.fr> Message-ID: <499390B9.6030401@mxc.ca> Duncan Sands wrote: > Hi Nick, > >>> Make sure the SCC pass manager initializes any contained >>> function pass managers. Without this, simplify-libcalls >>> would add nocapture attributes when run on its own, but >>> not when run as part of -std-compile-opts or similar. >> Thanks for fixing this! > > it seems Bill reverted this because it caused some bootstrap > breakage. Most likely there is a mistake in your simplify > libcalls stuff, or the nocapture logic, or alias analysis, > that is now being seen because your pass is actually being > run. My plan is to let you investigate :) Yup! I'm investigating. I've found one bug in simplify-libcalls so far and will commit a fix for it once make check passes. It also breaks the fannkuch benchmark, which I'm still working on. It's nice to see this pass making a difference in the generated code though! :) Nick From nicholas at mxc.ca Wed Feb 11 21:18:34 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 12 Feb 2009 03:18:34 -0000 Subject: [llvm-commits] [llvm] r64352 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Message-ID: <200902120318.n1C3IYrD031674@zion.cs.uiuc.edu> Author: nicholas Date: Wed Feb 11 21:18:34 2009 New Revision: 64352 URL: http://llvm.org/viewvc/llvm-project?rev=64352&view=rev Log: Don't mark all args to strtod and friends as nocapture. Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=64352&r1=64351&r2=64352&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Wed Feb 11 21:18:34 2009 @@ -1583,16 +1583,9 @@ setDoesNotCapture(F, 2); } else if ((NameLen == 6 && !strcmp(NameStr, "strcmp")) || (NameLen == 6 && !strcmp(NameStr, "strspn")) || - (NameLen == 6 && !strcmp(NameStr, "strtol")) || - (NameLen == 6 && !strcmp(NameStr, "strtod")) || - (NameLen == 6 && !strcmp(NameStr, "strtof")) || - (NameLen == 7 && !strcmp(NameStr, "strtoul")) || - (NameLen == 7 && !strcmp(NameStr, "strtoll")) || - (NameLen == 7 && !strcmp(NameStr, "strtold")) || (NameLen == 7 && !strcmp(NameStr, "strncmp")) || (NameLen == 7 && !strcmp(NameStr, "strcspn")) || (NameLen == 7 && !strcmp(NameStr, "strcoll")) || - (NameLen == 8 && !strcmp(NameStr, "strtoull")) || (NameLen == 10 && !strcmp(NameStr, "strcasecmp")) || (NameLen == 11 && !strcmp(NameStr, "strncasecmp"))) { if (FTy->getNumParams() < 2 || From kremenek at apple.com Wed Feb 11 22:09:46 2009 From: kremenek at apple.com (Ted Kremenek) Date: Thu, 12 Feb 2009 04:09:46 -0000 Subject: [llvm-commits] [llvm] r64357 - /llvm/tags/checker/checker-0.155/ Message-ID: <200902120409.n1C49kQl000925@zion.cs.uiuc.edu> Author: kremenek Date: Wed Feb 11 22:09:44 2009 New Revision: 64357 URL: http://llvm.org/viewvc/llvm-project?rev=64357&view=rev Log: Tagging checker-0.155. Added: llvm/tags/checker/checker-0.155/ - copied from r64356, llvm/trunk/ From kremenek at apple.com Wed Feb 11 23:17:03 2009 From: kremenek at apple.com (Ted Kremenek) Date: Thu, 12 Feb 2009 05:17:03 -0000 Subject: [llvm-commits] [llvm] r64359 - /llvm/trunk/include/llvm/ADT/ImmutableSet.h Message-ID: <200902120517.n1C5H3f3003002@zion.cs.uiuc.edu> Author: kremenek Date: Wed Feb 11 23:17:02 2009 New Revision: 64359 URL: http://llvm.org/viewvc/llvm-project?rev=64359&view=rev Log: Add method 'isSingleton()' to ImmutableSet. This returns true if the set contains exactly one element. Modified: llvm/trunk/include/llvm/ADT/ImmutableSet.h Modified: llvm/trunk/include/llvm/ADT/ImmutableSet.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/ImmutableSet.h?rev=64359&r1=64358&r2=64359&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/ImmutableSet.h (original) +++ llvm/trunk/include/llvm/ADT/ImmutableSet.h Wed Feb 11 23:17:02 2009 @@ -61,7 +61,6 @@ /// NULL if there is no right subtree. ImutAVLTree* getRight() const { return Right; } - /// getHeight - Returns the height of the tree. A tree with no subtrees /// has a height of 1. unsigned getHeight() const { return Height; } @@ -1001,6 +1000,10 @@ /// isEmpty - Return true if the set contains no elements. bool isEmpty() const { return !Root; } + + /// isSingleton - Return true if the set contains exactly one element. + /// This method runs in constant time. + bool isSingleton() const { return getHeight() == 1; } template void foreach(Callback& C) { if (Root) Root->foreach(C); } From Alireza.Moshtaghi at microchip.com Wed Feb 11 18:08:07 2009 From: Alireza.Moshtaghi at microchip.com (Alireza.Moshtaghi at microchip.com) Date: Wed, 11 Feb 2009 17:08:07 -0700 Subject: [llvm-commits] r64000 breaks PIC16 In-Reply-To: <1234324706.4728.5.camel@idc-lt-i00171.microchip.com> References: <1234292444.7110.7.camel@idc-lt-i00171.microchip.com><3BEE949D-7D28-4B3F-A69C-3E972C8716A9@apple.com> <1234324706.4728.5.camel@idc-lt-i00171.microchip.com> Message-ID: Looks like the problem is in sinking stuff; I disabled them and it worked. Too me it seems like sinker does not check if the instruction to sink is providing a flag to a successor, if so it shouldn't move the instruction. In our case, blt is linked to subwf only through a flag (no register is used... ) blt is kept in place and subwf is sinked, followed by all instructions that provided to it. How can we check if an instruction is used by a successor through a flag? Here is the correct (expected) code again: foo: movlw 128 banksel foo.arg.i xorwf foo.arg.i + 1, W movwf foo.tmp + 2 movlw 127 movwf foo.tmp + 1 movf foo.tmp + 2, W subwf foo.tmp + 1, W blt .BB1_2 ; if.else (correct - br after test) .BB1_1 ; if.then movlw 255 movwf foo.args + 0 movwf foo.args + 1 goto .BB1_3 ; return .BB1_2 ; if.else movlw 1 movwf foo.args + 0 ... Thanks Ali > -----Original Message----- > From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits- > bounces at cs.uiuc.edu] On Behalf Of sanjiv gupta > Sent: Tuesday, February 10, 2009 8:58 PM > To: gohman at apple.com > Cc: Commit Messages and Patches for LLVM > Subject: Re: [llvm-commits] r64000 breaks PIC16 > > > On Tue, 2009-02-10 at 12:24 -0800, Dan Gohman wrote: > > On Feb 10, 2009, at 11:00 AM, sanjiv gupta wrote: > > > The correct assembly is: (as per r63998) > > [snip] > > > > > > The incorrect assembly is : (as per r64000) > > > > [snip] > > > > It looks like 63999, enabling sinking, is more likely to be the > > revision that > > introduces the change. If it is, can you check to see if the problem > > is fixed > > in the latest trunk? > > > > Dan > > > Dan, > It still breaks as per 64285. > > I have attached a .bc file. > The problem with the generated assembly is that the branch (.blt) is > happening before the test (subwf) insn. > > > - Sanjiv > > > _______________________________________________ > > llvm-commits mailing list > > llvm-commits at cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Thu Feb 12 00:08:44 2009 From: clattner at apple.com (Chris Lattner) Date: Wed, 11 Feb 2009 22:08:44 -0800 Subject: [llvm-commits] r64000 breaks PIC16 In-Reply-To: References: <1234292444.7110.7.camel@idc-lt-i00171.microchip.com> <3BEE949D-7D28-4B3F-A69C-3E972C8716A9@apple.com> <1234324706.4728.5.camel@idc-lt-i00171.microchip.com> Message-ID: <9D65B45B-C932-40F7-BC02-991AB1817188@apple.com> On Feb 11, 2009, at 4:08 PM, Alireza.Moshtaghi at microchip.com wrote: > Looks like the problem is in sinking stuff; I disabled them and it > worked. > Too me it seems like sinker does not check if the instruction to > sink is > providing a flag to a successor, if so it shouldn't move the > instruction. > In our case, blt is linked to subwf only through a flag (no register > is > used... ) blt is kept in place and subwf is sinked, followed by all > instructions that provided to it. > How can we check if an instruction is used by a successor through a > flag? Hi Alireza, It looks like subfw isn't declared to implicitly set the flags register. On X86 for example, all the instructions that mutate the flags are defined to implicitly set FLAGS, and all instructions that read the flags implicitly read FLAGS. This prevents code motion from moving the instructions around. -Chris From sabre at nondot.org Thu Feb 12 00:18:09 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 12 Feb 2009 06:18:09 -0000 Subject: [llvm-commits] [test-suite] r64360 - /test-suite/trunk/MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio.c Message-ID: <200902120618.n1C6I97b005151@zion.cs.uiuc.edu> Author: lattner Date: Thu Feb 12 00:18:09 2009 New Revision: 64360 URL: http://llvm.org/viewvc/llvm-project?rev=64360&view=rev Log: add a missing header for better 64-bit cleanness :) Modified: test-suite/trunk/MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio.c Modified: test-suite/trunk/MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio.c?rev=64360&r1=64359&r2=64360&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio.c (original) +++ test-suite/trunk/MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio.c Thu Feb 12 00:18:09 2009 @@ -2,6 +2,7 @@ #include "adpcm.h" #include +#include struct adpcm_state state; From jlerouge at apple.com Thu Feb 12 00:19:54 2009 From: jlerouge at apple.com (Julien Lerouge) Date: Wed, 11 Feb 2009 22:19:54 -0800 Subject: [llvm-commits] [llvm] r62746 - /llvm/trunk/Makefile.rules In-Reply-To: <200901220324.n0M3OMbY009941@zion.cs.uiuc.edu> References: <200901220324.n0M3OMbY009941@zion.cs.uiuc.edu> Message-ID: <20090212061954.GA99037@pom.apple.com> On Thu, Jan 22, 2009 at 03:24:22AM +0000, Mike Stump wrote: > Author: mrs > Date: Wed Jan 21 21:24:22 2009 > New Revision: 62746 > > URL: http://llvm.org/viewvc/llvm-project?rev=62746&view=rev > Log: > Don't create .dir files in installation directories. Switch to using > order-only dependancies for installation directories. > Order-only dependencies are not supported by make 3.79 it seems. Are the minimum requirements going to change ? http://llvm.cs.uiuc.edu/docs/GettingStarted.html#software This breaks install target on my old MingW for example. I don't mind upgrading though. Thanks, Julien -- Julien Lerouge PGP Key Id: 0xB1964A62 PGP Fingerprint: 392D 4BAD DB8B CE7F 4E5F FA3C 62DB 4AA7 B196 4A62 PGP Public Key from: keyserver.pgp.com From sabre at nondot.org Thu Feb 12 00:54:55 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 12 Feb 2009 06:54:55 -0000 Subject: [llvm-commits] [llvm] r64361 - in /llvm/trunk/test/CodeGen/X86: 2to3-inc64.ll convert-2-addr-3-addr-inc64.ll Message-ID: <200902120654.n1C6stYZ006660@zion.cs.uiuc.edu> Author: lattner Date: Thu Feb 12 00:54:55 2009 New Revision: 64361 URL: http://llvm.org/viewvc/llvm-project?rev=64361&view=rev Log: rename test to avoid messing with tab completion of dates. Added: llvm/trunk/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll - copied unchanged from r64360, llvm/trunk/test/CodeGen/X86/2to3-inc64.ll Removed: llvm/trunk/test/CodeGen/X86/2to3-inc64.ll Removed: llvm/trunk/test/CodeGen/X86/2to3-inc64.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2to3-inc64.ll?rev=64360&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2to3-inc64.ll (original) +++ llvm/trunk/test/CodeGen/X86/2to3-inc64.ll (removed) @@ -1,21 +0,0 @@ -; RUN: llvm-as < %s | llc -march=x86-64 -o %t -f -stats -info-output-file - | \ -; RUN: grep {asm-printer} | grep {Number of machine instrs printed} | grep 5 -; RUN: grep {leal 1(\%rsi),} %t - -define fastcc zeroext i8 @fullGtU(i32 %i1, i32 %i2) nounwind { -entry: - %0 = add i32 %i2, 1 ; [#uses=1] - %1 = sext i32 %0 to i64 ; [#uses=1] - %2 = getelementptr i8* null, i64 %1 ; [#uses=1] - %3 = load i8* %2, align 1 ; [#uses=1] - %4 = icmp eq i8 0, %3 ; [#uses=1] - br i1 %4, label %bb3, label %bb34 - -bb3: ; preds = %entry - %5 = add i32 %i2, 4 ; [#uses=0] - ret i8 0 - -bb34: ; preds = %entry - ret i8 0 -} - From sabre at nondot.org Thu Feb 12 00:56:08 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 12 Feb 2009 06:56:08 -0000 Subject: [llvm-commits] [llvm] r64362 - in /llvm/trunk: lib/Transforms/Scalar/CodeGenPrepare.cpp test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll Message-ID: <200902120656.n1C6u9ZM006721@zion.cs.uiuc.edu> Author: lattner Date: Thu Feb 12 00:56:08 2009 New Revision: 64362 URL: http://llvm.org/viewvc/llvm-project?rev=64362&view=rev Log: fix PR3537: if resetting bbi back to the start of a block, we need to forget about already inserted expressions. Added: llvm/trunk/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=64362&r1=64361&r2=64362&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Thu Feb 12 00:56:08 2009 @@ -1241,11 +1241,13 @@ // computation. Value *&SunkAddr = SunkAddrs[Addr]; if (SunkAddr) { - DEBUG(cerr << "CGP: Reusing nonlocal addrmode: " << AddrMode << "\n"); + DEBUG(cerr << "CGP: Reusing nonlocal addrmode: " << AddrMode << " for " + << *MemoryInst); if (SunkAddr->getType() != Addr->getType()) SunkAddr = new BitCastInst(SunkAddr, Addr->getType(), "tmp", InsertPt); } else { - DEBUG(cerr << "CGP: SINKING nonlocal addrmode: " << AddrMode << "\n"); + DEBUG(cerr << "CGP: SINKING nonlocal addrmode: " << AddrMode << " for " + << *MemoryInst); const Type *IntPtrTy = TLI->getTargetData()->getIntPtrType(); Value *Result = 0; @@ -1505,9 +1507,12 @@ if (TLI && isa(CI->getCalledValue())) if (const TargetAsmInfo *TAI = TLI->getTargetMachine().getTargetAsmInfo()) { - if (TAI->ExpandInlineAsm(CI)) + if (TAI->ExpandInlineAsm(CI)) { BBI = BB.begin(); - else + // Avoid processing instructions out of order, which could cause + // reuse before a value is defined. + SunkAddrs.clear(); + } else // Sink address computing for memory operands into the block. MadeChange |= OptimizeInlineAsmInst(I, &(*CI), SunkAddrs); } Added: llvm/trunk/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll?rev=64362&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll (added) +++ llvm/trunk/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll Thu Feb 12 00:56:08 2009 @@ -0,0 +1,35 @@ +; RUN: llvm-as < %s | llc +; PR3537 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i386-apple-darwin9.6" + %struct.GetBitContext = type <{ i8*, i8*, i32, i32 }> + +define i32 @alac_decode_frame() nounwind { +entry: + %tmp2 = load i8** null ; [#uses=2] + %tmp34 = getelementptr i8* %tmp2, i32 4 ; [#uses=2] + %tmp5.i424 = bitcast i8* %tmp34 to i8** ; [#uses=2] + %tmp15.i = getelementptr i8* %tmp2, i32 12 ; [#uses=1] + %0 = bitcast i8* %tmp15.i to i32* ; [#uses=1] + br i1 false, label %if.then43, label %if.end47 + +if.then43: ; preds = %entry + ret i32 0 + +if.end47: ; preds = %entry + %tmp5.i590 = load i8** %tmp5.i424 ; [#uses=0] + store i32 19, i32* %0 + %tmp6.i569 = load i8** %tmp5.i424 ; [#uses=0] + %1 = call i32 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 0) nounwind ; [#uses=0] + br i1 false, label %bb.nph, label %if.then63 + +if.then63: ; preds = %if.end47 + unreachable + +bb.nph: ; preds = %if.end47 + %2 = bitcast i8* %tmp34 to %struct.GetBitContext* ; <%struct.GetBitContext*> [#uses=1] + %call9.i = call fastcc i32 @decode_scalar(%struct.GetBitContext* %2, i32 0, i32 0, i32 0) nounwind ; [#uses=0] + unreachable +} + +declare fastcc i32 @decode_scalar(%struct.GetBitContext* nocapture, i32, i32, i32) nounwind From sabre at nondot.org Thu Feb 12 01:00:36 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 12 Feb 2009 07:00:36 -0000 Subject: [llvm-commits] [llvm] r64363 - /llvm/trunk/lib/Transforms/Scalar/GVN.cpp Message-ID: <200902120700.n1C70aXt006890@zion.cs.uiuc.edu> Author: lattner Date: Thu Feb 12 01:00:35 2009 New Revision: 64363 URL: http://llvm.org/viewvc/llvm-project?rev=64363&view=rev Log: improve naming of values in GVN, patch by Jay Foad! Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=64363&r1=64362&r2=64363&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Thu Feb 12 01:00:35 2009 @@ -1035,7 +1035,7 @@ Value* v = GetValueForBlock(LI->getParent(), LI, BlockReplValues, true); LI->replaceAllUsesWith(v); - if (!isa(v)) + if (isa(v)) v->takeName(LI); if (isa(v->getType())) MD->invalidateCachedPointerInfo(v); @@ -1132,7 +1132,7 @@ // Perform PHI construction. Value* v = GetValueForBlock(LI->getParent(), LI, BlockReplValues, true); LI->replaceAllUsesWith(v); - if (!isa(v)) + if (isa(v)) v->takeName(LI); if (isa(v->getType())) MD->invalidateCachedPointerInfo(v); From sabre at nondot.org Thu Feb 12 01:06:42 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 12 Feb 2009 07:06:42 -0000 Subject: [llvm-commits] [llvm] r64364 - in /llvm/trunk: lib/Transforms/Utils/InlineFunction.cpp test/Transforms/Inline/inline-invoke-tail.ll Message-ID: <200902120706.n1C76gDa007120@zion.cs.uiuc.edu> Author: lattner Date: Thu Feb 12 01:06:42 2009 New Revision: 64364 URL: http://llvm.org/viewvc/llvm-project?rev=64364&view=rev Log: Fix a nasty bug (PR3550) where the inline pass could incorrectly mark calls with the tail marker when inlining them through an invoke. Patch, testcase, and perfect analysis by Jay Foad! Added: llvm/trunk/test/Transforms/Inline/inline-invoke-tail.ll Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=64364&r1=64363&r2=64364&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Thu Feb 12 01:06:42 2009 @@ -203,10 +203,10 @@ CalledFunc->getFunctionType()->isVarArg()) return false; - // If the call to the callee is a non-tail call, we must clear the 'tail' + // If the call to the callee is not a tail call, we must clear the 'tail' // flags on any calls that we inline. bool MustClearTailCallFlags = - isa(TheCall) && !cast(TheCall)->isTailCall(); + !(isa(TheCall) && cast(TheCall)->isTailCall()); // If the call to the callee cannot throw, set the 'nounwind' flag on any // calls that we inline. Added: llvm/trunk/test/Transforms/Inline/inline-invoke-tail.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Inline/inline-invoke-tail.ll?rev=64364&view=auto ============================================================================== --- llvm/trunk/test/Transforms/Inline/inline-invoke-tail.ll (added) +++ llvm/trunk/test/Transforms/Inline/inline-invoke-tail.ll Thu Feb 12 01:06:42 2009 @@ -0,0 +1,35 @@ +; RUN: llvm-as < %s | opt -inline | llvm-dis | not grep {tail call void @llvm.memcpy.i32} +; PR3550 + +define internal void @foo(i32* %p, i32* %q) { + %pp = bitcast i32* %p to i8* + %qq = bitcast i32* %q to i8* + tail call void @llvm.memcpy.i32(i8* %pp, i8* %qq, i32 4, i32 1) + ret void +} + +declare void @llvm.memcpy.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind + +define i32 @main() { + %a = alloca i32 ; [#uses=3] + %b = alloca i32 ; [#uses=2] + store i32 1, i32* %a, align 4 + store i32 0, i32* %b, align 4 + invoke void @foo(i32* %a, i32* %b) + to label %invcont unwind label %lpad + +invcont: + %retval = load i32* %a, align 4 + ret i32 %retval + +lpad: + %eh_ptr = call i8* @llvm.eh.exception() + %eh_select = call i32 (i8*, i8*, ...)* @llvm.eh.selector.i32(i8* %eh_ptr, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* null) + unreachable +} + +declare i8* @llvm.eh.exception() nounwind + +declare i32 @llvm.eh.selector.i32(i8*, i8*, ...) nounwind + +declare i32 @__gxx_personality_v0(...) From jlerouge at apple.com Thu Feb 12 01:39:10 2009 From: jlerouge at apple.com (Julien Lerouge) Date: Thu, 12 Feb 2009 07:39:10 -0000 Subject: [llvm-commits] [llvm] r64366 - /llvm/trunk/lib/System/Win32/Alarm.inc Message-ID: <200902120739.n1C7dAI9008328@zion.cs.uiuc.edu> Author: jlerouge Date: Thu Feb 12 01:39:10 2009 New Revision: 64366 URL: http://llvm.org/viewvc/llvm-project?rev=64366&view=rev Log: Fix MingW build, patch by Kenneth Boyd! Modified: llvm/trunk/lib/System/Win32/Alarm.inc Modified: llvm/trunk/lib/System/Win32/Alarm.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Alarm.inc?rev=64366&r1=64365&r2=64366&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Alarm.inc (original) +++ llvm/trunk/lib/System/Win32/Alarm.inc Thu Feb 12 01:39:10 2009 @@ -35,6 +35,9 @@ return 0; } -void Sleep(unsigned n) { +// Don't pull in all of the Windows headers. +extern "C" _stdcall void Sleep(unsigned long); + +void sys::Sleep(unsigned n) { Sleep(n*1000); } From jlerouge at apple.com Thu Feb 12 01:46:13 2009 From: jlerouge at apple.com (Julien Lerouge) Date: Wed, 11 Feb 2009 23:46:13 -0800 Subject: [llvm-commits] Win32/Alarm.inc rev. 64231 : MingW32 error In-Reply-To: <4991FB86.2020605@zaimoni.com> References: <4991FB86.2020605@zaimoni.com> Message-ID: <20090212074612.GB99037@pom.apple.com> On Tue, Feb 10, 2009 at 04:11:18PM -0600, Kenneth Boyd wrote: > This patch gets the build past this point, leaving only one error to > speak of. Applied, thanks ! http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090209/073643.html > appears to be because GTEST_OS_WINDOWS is not defined. Fixing appears to > be difficult (there is a todo note in gtest/internals/gtest-port.h that > GTEST_OS_WINDOWS should be split into more macros, as it currently means > both "OS is Windows" and "compiler is MSVC".) I have added a bunch of __MINGW32__ to fix this but never checked it in ... will do so now : http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-January/019716.html Thanks, Julien -- Julien Lerouge PGP Key Id: 0xB1964A62 PGP Fingerprint: 392D 4BAD DB8B CE7F 4E5F FA3C 62DB 4AA7 B196 4A62 PGP Public Key from: keyserver.pgp.com From jlerouge at apple.com Thu Feb 12 02:02:35 2009 From: jlerouge at apple.com (Julien Lerouge) Date: Thu, 12 Feb 2009 08:02:35 -0000 Subject: [llvm-commits] [llvm] r64367 - in /llvm/trunk/utils/unittest/googletest: Makefile gtest.cc Message-ID: <200902120802.n1C82adH009171@zion.cs.uiuc.edu> Author: jlerouge Date: Thu Feb 12 02:02:35 2009 New Revision: 64367 URL: http://llvm.org/viewvc/llvm-project?rev=64367&view=rev Log: Fix MingW build: define GTEST_OS_WINDOWS if OS is MingW, but disable exceptions. Modified: llvm/trunk/utils/unittest/googletest/Makefile llvm/trunk/utils/unittest/googletest/gtest.cc Modified: llvm/trunk/utils/unittest/googletest/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/Makefile?rev=64367&r1=64366&r2=64367&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/Makefile (original) +++ llvm/trunk/utils/unittest/googletest/Makefile Thu Feb 12 02:02:35 2009 @@ -18,4 +18,8 @@ CPP.Flags += -I$(LLVM_SRC_ROOT)/utils/unittest/googletest/include/ CPP.Flags += $(NO_MISSING_FIELD_INITIALIZERS) $(NO_VARIADIC_MACROS) +ifeq ($(OS),MingW) + CPP.Flags += -DGTEST_OS_WINDOWS=1 +endif + include $(LEVEL)/Makefile.common Modified: llvm/trunk/utils/unittest/googletest/gtest.cc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/gtest.cc?rev=64367&r1=64366&r2=64367&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/gtest.cc (original) +++ llvm/trunk/utils/unittest/googletest/gtest.cc Thu Feb 12 02:02:35 2009 @@ -1993,7 +1993,7 @@ if (!HasSameFixtureClass()) return; internal::UnitTestImpl* const impl = internal::GetUnitTestImpl(); -#ifdef GTEST_OS_WINDOWS +#if defined(GTEST_OS_WINDOWS) && !defined(__MINGW32__) // We are on Windows. impl->os_stack_trace_getter()->UponLeavingGTest(); __try { @@ -2025,7 +2025,7 @@ AddExceptionThrownFailure(GetExceptionCode(), "TearDown()"); } -#else // We are on Linux or Mac - exceptions are disabled. +#else // We are on Linux, Mac or MingW - exceptions are disabled. impl->os_stack_trace_getter()->UponLeavingGTest(); SetUp(); @@ -2227,7 +2227,7 @@ const TimeInMillis start = GetTimeInMillis(); impl->os_stack_trace_getter()->UponLeavingGTest(); -#ifdef GTEST_OS_WINDOWS +#if defined(GTEST_OS_WINDOWS) && !defined(__MINGW32__) // We are on Windows. Test* test = NULL; @@ -2240,7 +2240,7 @@ "the test fixture's constructor"); return; } -#else // We are on Linux or Mac OS - exceptions are disabled. +#else // We are on Linux, Mac OS or MingW - exceptions are disabled. // TODO(wan): If test->Run() throws, test won't be deleted. This is // not a problem now as we don't use exceptions. If we were to @@ -3271,7 +3271,7 @@ // We don't protect this under mutex_, as we only support calling it // from the main thread. int UnitTest::Run() { -#ifdef GTEST_OS_WINDOWS +#if defined(GTEST_OS_WINDOWS) && !defined(__MINGW32__) #if !defined(_WIN32_WCE) // SetErrorMode doesn't exist on CE. @@ -3294,7 +3294,7 @@ } #else - // We are on Linux or Mac OS. There is no exception of any kind. + // We are on Linux, Mac OS or MingW. There is no exception of any kind. return impl_->RunAllTests(); #endif // GTEST_OS_WINDOWS From baldrick at free.fr Thu Feb 12 02:38:35 2009 From: baldrick at free.fr (Duncan Sands) Date: Thu, 12 Feb 2009 09:38:35 +0100 Subject: [llvm-commits] [llvm] r64352 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp In-Reply-To: <200902120318.n1C3IYrD031674@zion.cs.uiuc.edu> References: <200902120318.n1C3IYrD031674@zion.cs.uiuc.edu> Message-ID: <200902120938.35272.baldrick@free.fr> Hi Nick, > Don't mark all args to strtod and friends as nocapture. if you're going to be that strict then you should eliminate sprintf and even printf (write pointer to file, read it in again elsewhere). Or did I misunderstand what the problem with these is? Ciao, Duncan. From baldrick at free.fr Thu Feb 12 02:49:36 2009 From: baldrick at free.fr (Duncan Sands) Date: Thu, 12 Feb 2009 09:49:36 +0100 Subject: [llvm-commits] [llvm] r64352 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp In-Reply-To: <200902120318.n1C3IYrD031674@zion.cs.uiuc.edu> References: <200902120318.n1C3IYrD031674@zion.cs.uiuc.edu> Message-ID: <200902120949.36539.baldrick@free.fr> Hi Nick, > Don't mark all args to strtod and friends as nocapture. I just discovered endptr: "If endptr is not NULL, a pointer to the character after the last character used in the conversion is stored in the location referenced by endptr". So you are right: these can capture the first argument. Sorry for the noise. Ciao, Duncan. From nicholas at mxc.ca Thu Feb 12 02:50:29 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 12 Feb 2009 00:50:29 -0800 Subject: [llvm-commits] [llvm] r64352 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp In-Reply-To: <200902120938.35272.baldrick@free.fr> References: <200902120318.n1C3IYrD031674@zion.cs.uiuc.edu> <200902120938.35272.baldrick@free.fr> Message-ID: <4993E2D5.6040907@mxc.ca> Duncan Sands wrote: > Hi Nick, > >> Don't mark all args to strtod and friends as nocapture. > > if you're going to be that strict then you should eliminate > sprintf and even printf (write pointer to file, read it in > again elsewhere). Or did I misunderstand what the problem > with these is? I'm going to guess that you misunderstood the problem. Taking strtod as an example, it has: double strtod(const char *nptr, char **endptr) { /* In a certain case, if (*nptr == 0) ... */ *endptr = nptr; } and that's an escape. We can't mark nptr as "nocapture" since it can certainly be captured by being written through endptr. printf and sprintf don't have that problem. If you write a pointer to a file, you're passing that pointer in an argument that isn't marked nocapture. We only mark the format string (and for sprintf, the output 'str') as nocapture. Nick From evan.cheng at apple.com Thu Feb 12 02:59:51 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 12 Feb 2009 08:59:51 -0000 Subject: [llvm-commits] [llvm] r64369 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll test/CodeGen/X86/2008-08-05-SpillerBug.ll Message-ID: <200902120859.n1C8xprn017627@zion.cs.uiuc.edu> Author: evancheng Date: Thu Feb 12 02:59:45 2009 New Revision: 64369 URL: http://llvm.org/viewvc/llvm-project?rev=64369&view=rev Log: Replace one of burr scheduling heuristic with something more sensible. Now calcMaxScratches simply compute the number of true data dependencies. This actually improve a couple of tests in dejagnu suite as many tests in llvm nightly test suite. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp llvm/trunk/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll llvm/trunk/test/CodeGen/X86/2008-08-05-SpillerBug.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=64369&r1=64368&r2=64369&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu Feb 12 02:59:45 2009 @@ -916,7 +916,7 @@ if (PredSethiUllman > SethiUllmanNumber) { SethiUllmanNumber = PredSethiUllman; Extra = 0; - } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl()) + } else if (PredSethiUllman == SethiUllmanNumber) ++Extra; } @@ -1070,24 +1070,13 @@ } /// calcMaxScratches - Returns an cost estimate of the worse case requirement -/// for scratch registers. Live-in operands and live-out results don't count -/// since they are "fixed". +/// for scratch registers, i.e. number of data dependencies. static unsigned calcMaxScratches(const SUnit *SU) { unsigned Scratches = 0; for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); - I != E; ++I) { + I != E; ++I) if (I->isCtrl()) continue; // ignore chain preds - if (!I->getSUnit()->getNode() || - I->getSUnit()->getNode()->getOpcode() != ISD::CopyFromReg) Scratches++; - } - for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); - I != E; ++I) { - if (I->isCtrl()) continue; // ignore chain succs - if (!I->getSUnit()->getNode() || - I->getSUnit()->getNode()->getOpcode() != ISD::CopyToReg) - Scratches += 10; - } return Scratches; } @@ -1120,10 +1109,7 @@ if (LDist != RDist) return LDist < RDist; - // Intuitively, it's good to push down instructions whose results are - // liveout so their long live ranges won't conflict with other values - // which are needed inside the BB. Further prioritize liveout instructions - // by the number of operands which are calculated within the BB. + // How many registers becomes live when the node is scheduled. unsigned LScratch = calcMaxScratches(left); unsigned RScratch = calcMaxScratches(right); if (LScratch != RScratch) Modified: llvm/trunk/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll?rev=64369&r1=64368&r2=64369&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll Thu Feb 12 02:59:45 2009 @@ -1,4 +1,5 @@ ; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin9 +; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin9 -stats |& grep asm-printer | grep 186 %"struct.Adv5::Ekin<3>" = type <{ i8 }> %"struct.Adv5::X::Energyflux<3>" = type { double } Modified: llvm/trunk/test/CodeGen/X86/2008-08-05-SpillerBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-05-SpillerBug.ll?rev=64369&r1=64368&r2=64369&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-08-05-SpillerBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-08-05-SpillerBug.ll Thu Feb 12 02:59:45 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -disable-fp-elim -stats -info-output-file - | grep {Number of dead stores elided} | count 1 +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -disable-fp-elim -stats |& grep asm-printer | grep 57 ; PR2568 @g_3 = external global i16 ; [#uses=1] From baldrick at free.fr Thu Feb 12 03:08:11 2009 From: baldrick at free.fr (Duncan Sands) Date: Thu, 12 Feb 2009 10:08:11 +0100 Subject: [llvm-commits] [llvm] r64352 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp In-Reply-To: <4993E2D5.6040907@mxc.ca> References: <200902120318.n1C3IYrD031674@zion.cs.uiuc.edu> <200902120938.35272.baldrick@free.fr> <4993E2D5.6040907@mxc.ca> Message-ID: <200902121008.13063.baldrick@free.fr> Hi Nick, > I'm going to guess that you misunderstood the problem. correct :) > Taking strtod as an example, it has: > > double strtod(const char *nptr, char **endptr) { > /* In a certain case, if (*nptr == 0) ... */ > *endptr = nptr; > } You could still mark endptr nocapure (maybe not worth it). > and that's an escape. We can't mark nptr as "nocapture" since it can > certainly be captured by being written through endptr. > > printf and sprintf don't have that problem. If you write a pointer to a > file, you're passing that pointer in an argument that isn't marked > nocapture. We only mark the format string (and for sprintf, the output > 'str') as nocapture. If we decided that nocapture means: "(really not captured) or (captured, but did something which results in undefined alias analysis results)", and say that pointer swizzling results in undefined alias analysis behavior, then all arguments to printf could be marked nocapture I guess. Ciao, Duncan. From evan.cheng at apple.com Thu Feb 12 03:43:33 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 12 Feb 2009 09:43:33 -0000 Subject: [llvm-commits] [llvm] r64372 - /llvm/trunk/lib/CodeGen/VirtRegMap.cpp Message-ID: <200902120943.n1C9hZZt022294@zion.cs.uiuc.edu> Author: evancheng Date: Thu Feb 12 03:43:23 2009 New Revision: 64372 URL: http://llvm.org/viewvc/llvm-project?rev=64372&view=rev Log: If availability info is kept when fallthrough into a bb, add the available registers to live-in set. Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=64372&r1=64371&r2=64372&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Thu Feb 12 03:43:23 2009 @@ -407,6 +407,8 @@ /// slot changes. This removes information about which register the previous /// value for this slot lives in (as the previous value is dead now). void ModifyStackSlotOrReMat(int SlotOrReMat); + + void AddAvailableRegsToLiveIn(MachineBasicBlock &MBB); }; } @@ -486,6 +488,22 @@ PhysRegsAvailable.erase(I); } +/// AddAvailableRegsToLiveIn - Availability information is being kept coming +/// into the specified MBB. Add available physical registers as live-in's +/// so register scavenger and post-allocation scheduler are happy. +void AvailableSpills::AddAvailableRegsToLiveIn(MachineBasicBlock &MBB) { + for (std::multimap::iterator + I = PhysRegsAvailable.begin(), E = PhysRegsAvailable.end(); + I != E; ++I) { + unsigned Reg = (*I).first; + if (!MBB.isLiveIn(Reg)) + MBB.addLiveIn(Reg); + } +} + +/// findSinglePredSuccessor - Return via reference a vector of machine basic +/// blocks each of which is a successor of the specified BB and has no other +/// predecessor. static void findSinglePredSuccessor(MachineBasicBlock *MBB, SmallVectorImpl &Succs) { for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), @@ -497,8 +515,6 @@ } namespace { - class AvailableSpills; - /// LocalSpiller - This spiller does a simple pass over the machine basic /// block to attempt to keep spills in registers as much as possible for /// blocks that have low register pressure (the vreg may be spilled due to @@ -551,8 +567,10 @@ // FIXME: More than one successors, each of which has MBB has // the only predecessor. MBB = SinglePredSuccs[0]; - if (!Visited.count(MBB) && EarlyVisited.insert(MBB)) + if (!Visited.count(MBB) && EarlyVisited.insert(MBB)) { + Spills.AddAvailableRegsToLiveIn(*MBB); RewriteMBB(*MBB, VRM, Spills); + } } } while (MBB); From evan.cheng at apple.com Thu Feb 12 03:52:16 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 12 Feb 2009 09:52:16 -0000 Subject: [llvm-commits] [llvm] r64373 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Message-ID: <200902120952.n1C9qHbq022622@zion.cs.uiuc.edu> Author: evancheng Date: Thu Feb 12 03:52:13 2009 New Revision: 64373 URL: http://llvm.org/viewvc/llvm-project?rev=64373&view=rev Log: Oops. Last second clean up messed things up. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=64373&r1=64372&r2=64373&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu Feb 12 03:52:13 2009 @@ -1074,9 +1074,10 @@ static unsigned calcMaxScratches(const SUnit *SU) { unsigned Scratches = 0; for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); - I != E; ++I) + I != E; ++I) { if (I->isCtrl()) continue; // ignore chain preds - Scratches++; + Scratches++; + } return Scratches; } From eli.friedman at gmail.com Thu Feb 12 03:57:03 2009 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 12 Feb 2009 01:57:03 -0800 Subject: [llvm-commits] [llvm] r64352 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp In-Reply-To: <200902121008.13063.baldrick@free.fr> References: <200902120318.n1C3IYrD031674@zion.cs.uiuc.edu> <200902120938.35272.baldrick@free.fr> <4993E2D5.6040907@mxc.ca> <200902121008.13063.baldrick@free.fr> Message-ID: On Thu, Feb 12, 2009 at 1:08 AM, Duncan Sands wrote: > If we decided that nocapture means: "(really not captured) or (captured, > but did something which results in undefined alias analysis results)", > and say that pointer swizzling results in undefined alias analysis behavior, > then all arguments to printf could be marked nocapture I guess. I think it's pretty clearly legal to printf the value of a pointer to a file, read it back in, and dereference it, although it's certainly a bit unusual. -Eli From baldrick at free.fr Thu Feb 12 04:03:35 2009 From: baldrick at free.fr (Duncan Sands) Date: Thu, 12 Feb 2009 11:03:35 +0100 Subject: [llvm-commits] [llvm] r64352 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp In-Reply-To: References: <200902120318.n1C3IYrD031674@zion.cs.uiuc.edu> <200902121008.13063.baldrick@free.fr> Message-ID: <200902121103.36116.baldrick@free.fr> On Thursday 12 February 2009 10:57:03 Eli Friedman wrote: > On Thu, Feb 12, 2009 at 1:08 AM, Duncan Sands wrote: > > If we decided that nocapture means: "(really not captured) or (captured, > > but did something which results in undefined alias analysis results)", > > and say that pointer swizzling results in undefined alias analysis behavior, > > then all arguments to printf could be marked nocapture I guess. > > I think it's pretty clearly legal to printf the value of a pointer to > a file, read it back in, and dereference it, although it's certainly a > bit unusual. I'm told that the C standard (not the only relevant standard, but an important one) says that you are allowed to assume that the resulting pointer does not alias the original pointer. Note that I'm only saying "undefined for the purposes of alias analysis", not that doing this kind of thing is undefined in the general sense. Ciao, Duncan. From evan.cheng at apple.com Thu Feb 12 04:32:38 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 12 Feb 2009 10:32:38 -0000 Subject: [llvm-commits] [llvm] r64374 - in /llvm/trunk: lib/CodeGen/VirtRegMap.cpp test/CodeGen/X86/2009-02-12-SpillerBug.ll Message-ID: <200902121032.n1CAWcUs024300@zion.cs.uiuc.edu> Author: evancheng Date: Thu Feb 12 04:32:17 2009 New Revision: 64374 URL: http://llvm.org/viewvc/llvm-project?rev=64374&view=rev Log: It's (currently) not safe to keep certain physical registers live across basic blocks, e.g. x86 fp stack registers. Added: llvm/trunk/test/CodeGen/X86/2009-02-12-SpillerBug.ll Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=64374&r1=64373&r2=64374&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Thu Feb 12 04:32:17 2009 @@ -496,6 +496,12 @@ I = PhysRegsAvailable.begin(), E = PhysRegsAvailable.end(); I != E; ++I) { unsigned Reg = (*I).first; + const TargetRegisterClass* RC = TRI->getPhysicalRegisterRegClass(Reg); + // FIXME: A temporary workaround. We can't reuse available value if it's + // not safe to move the def of the virtual register's class. e.g. + // X86::RFP* register classes. Do not add it as a live-in. + if (!TII->isSafeToMoveRegClassDefs(RC)) + continue; if (!MBB.isLiveIn(Reg)) MBB.addLiveIn(Reg); } @@ -1361,7 +1367,12 @@ bool DoReMat = VRM.isReMaterialized(VirtReg); int SSorRMId = DoReMat ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg); - unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId); + const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); + // FIXME: A temporary workaround. Don't reuse available value if it's + // not safe to move the def of the virtual register's class. e.g. + // X86::RFP* register classes. + unsigned InReg = TII->isSafeToMoveRegClassDefs(RC) ? + Spills.getSpillSlotOrReMatPhysReg(SSorRMId) : 0; if (InReg == Phys) { // If the value is already available in the expected register, save // a reload / remat. @@ -1387,7 +1398,6 @@ // If the reloaded / remat value is available in another register, // copy it to the desired register. - const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); TII->copyRegToReg(MBB, &MI, Phys, InReg, RC, RC); // This invalidates Phys. Added: llvm/trunk/test/CodeGen/X86/2009-02-12-SpillerBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-02-12-SpillerBug.ll?rev=64374&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-02-12-SpillerBug.ll (added) +++ llvm/trunk/test/CodeGen/X86/2009-02-12-SpillerBug.ll Thu Feb 12 04:32:17 2009 @@ -0,0 +1,28 @@ +; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-apple-darwin8 + +define hidden void @__mulxc3({ x86_fp80, x86_fp80 }* noalias nocapture sret %agg.result, x86_fp80 %a, x86_fp80 %b, x86_fp80 %c, x86_fp80 %d) nounwind { +entry: + %0 = mul x86_fp80 %b, %d ; [#uses=1] + %1 = sub x86_fp80 0xK00000000000000000000, %0 ; [#uses=1] + %2 = add x86_fp80 0xK00000000000000000000, 0xK00000000000000000000 ; [#uses=1] + %3 = fcmp uno x86_fp80 %1, 0xK00000000000000000000 ; [#uses=1] + %4 = fcmp uno x86_fp80 %2, 0xK00000000000000000000 ; [#uses=1] + %or.cond = and i1 %3, %4 ; [#uses=1] + br i1 %or.cond, label %bb47, label %bb71 + +bb47: ; preds = %entry + %5 = fcmp uno x86_fp80 %a, 0xK00000000000000000000 ; [#uses=1] + br i1 %5, label %bb60, label %bb62 + +bb60: ; preds = %bb47 + %6 = tail call x86_fp80 @copysignl(x86_fp80 0xK00000000000000000000, x86_fp80 %a) nounwind readnone ; [#uses=0] + br label %bb62 + +bb62: ; preds = %bb60, %bb47 + unreachable + +bb71: ; preds = %entry + ret void +} + +declare x86_fp80 @copysignl(x86_fp80, x86_fp80) nounwind readnone From gohman at apple.com Thu Feb 12 10:36:27 2009 From: gohman at apple.com (Dan Gohman) Date: Thu, 12 Feb 2009 16:36:27 -0000 Subject: [llvm-commits] [llvm] r64376 - /llvm/trunk/lib/Transforms/Scalar/LICM.cpp Message-ID: <200902121636.n1CGaRs1004427@zion.cs.uiuc.edu> Author: djg Date: Thu Feb 12 10:36:26 2009 New Revision: 64376 URL: http://llvm.org/viewvc/llvm-project?rev=64376&view=rev Log: This code doesn't actually use the ExitingBlocks list. Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=64376&r1=64375&r2=64376&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Thu Feb 12 10:36:26 2009 @@ -785,9 +785,6 @@ std::map &ValueToAllocaMap) { Instruction *FnStart = CurLoop->getHeader()->getParent()->begin()->begin(); - SmallVector ExitingBlocks; - CurLoop->getExitingBlocks(ExitingBlocks); - // Loop over all of the alias sets in the tracker object. for (AliasSetTracker::iterator I = CurAST->begin(), E = CurAST->end(); I != E; ++I) { From sabre at nondot.org Thu Feb 12 11:04:57 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 12 Feb 2009 17:04:57 -0000 Subject: [llvm-commits] [llvm] r64377 - /llvm/trunk/test/CodeGen/X86/2009-02-12-SpillerBug.ll Message-ID: <200902121704.n1CH4vZZ006427@zion.cs.uiuc.edu> Author: lattner Date: Thu Feb 12 11:04:57 2009 New Revision: 64377 URL: http://llvm.org/viewvc/llvm-project?rev=64377&view=rev Log: add PR Modified: llvm/trunk/test/CodeGen/X86/2009-02-12-SpillerBug.ll Modified: llvm/trunk/test/CodeGen/X86/2009-02-12-SpillerBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-02-12-SpillerBug.ll?rev=64377&r1=64376&r2=64377&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-02-12-SpillerBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-02-12-SpillerBug.ll Thu Feb 12 11:04:57 2009 @@ -1,4 +1,5 @@ ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-apple-darwin8 +; PR3561 define hidden void @__mulxc3({ x86_fp80, x86_fp80 }* noalias nocapture sret %agg.result, x86_fp80 %a, x86_fp80 %b, x86_fp80 %c, x86_fp80 %d) nounwind { entry: From sabre at nondot.org Thu Feb 12 11:14:50 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 12 Feb 2009 17:14:50 -0000 Subject: [llvm-commits] [llvm] r64378 - /llvm/trunk/include/llvm/ADT/ImmutableSet.h Message-ID: <200902121714.n1CHEoa0006876@zion.cs.uiuc.edu> Author: lattner Date: Thu Feb 12 11:14:49 2009 New Revision: 64378 URL: http://llvm.org/viewvc/llvm-project?rev=64378&view=rev Log: Add operator->, patch by Ben Laurie! Modified: llvm/trunk/include/llvm/ADT/ImmutableSet.h Modified: llvm/trunk/include/llvm/ADT/ImmutableSet.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/ImmutableSet.h?rev=64378&r1=64377&r2=64378&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/ImmutableSet.h (original) +++ llvm/trunk/include/llvm/ADT/ImmutableSet.h Thu Feb 12 11:14:49 2009 @@ -1029,6 +1029,7 @@ inline iterator operator--(int) { iterator tmp(*this); --itr; return tmp; } inline bool operator==(const iterator& RHS) const { return RHS.itr == itr; } inline bool operator!=(const iterator& RHS) const { return RHS.itr != itr; } + inline value_type *operator->() const { return &(operator*()); } }; iterator begin() const { return iterator(Root); } From sabre at nondot.org Thu Feb 12 11:23:20 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 12 Feb 2009 17:23:20 -0000 Subject: [llvm-commits] [llvm] r64379 - /llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Message-ID: <200902121723.n1CHNKq2007255@zion.cs.uiuc.edu> Author: lattner Date: Thu Feb 12 11:23:20 2009 New Revision: 64379 URL: http://llvm.org/viewvc/llvm-project?rev=64379&view=rev Log: make fast isel fall back to selectiondags for VLA llvm.declare intrinsics. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=64379&r1=64378&r2=64379&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Feb 12 11:23:20 2009 @@ -388,11 +388,11 @@ if (BitCastInst *BCI = dyn_cast(Address)) Address = BCI->getOperand(0); AllocaInst *AI = dyn_cast(Address); - // Don't handle byval struct arguments, for example. + // Don't handle byval struct arguments or VLAs, for example. if (!AI) break; DenseMap::iterator SI = StaticAllocaMap.find(AI); - assert(SI != StaticAllocaMap.end() && "Invalid dbg.declare!"); + if (SI == StaticAllocaMap.end()) break; // VLAs. int FI = SI->second; // Determine the debug globalvariable. From gohman at apple.com Thu Feb 12 11:29:01 2009 From: gohman at apple.com (Dan Gohman) Date: Thu, 12 Feb 2009 17:29:01 -0000 Subject: [llvm-commits] [llvm] r64381 - in /llvm/trunk/lib/CodeGen: RegAllocBigBlock.cpp VirtRegMap.cpp Message-ID: <200902121729.n1CHT1df007546@zion.cs.uiuc.edu> Author: djg Date: Thu Feb 12 11:29:01 2009 New Revision: 64381 URL: http://llvm.org/viewvc/llvm-project?rev=64381&view=rev Log: Adjust the sizes for a few SmallVectors to reflect their usage. Modified: llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp llvm/trunk/lib/CodeGen/VirtRegMap.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp?rev=64381&r1=64380&r2=64381&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp Thu Feb 12 11:29:01 2009 @@ -518,7 +518,7 @@ assignVirtToPhysReg(VirtReg, PhysReg); } else { // no free registers available. // try to fold the spill into the instruction - SmallVector Ops; + SmallVector Ops; Ops.push_back(OpNum); if(MachineInstr* FMI = TII->foldMemoryOperand(*MF, MI, Ops, FrameIndex)) { ++NumFolded; Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=64381&r1=64380&r2=64381&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Thu Feb 12 11:29:01 2009 @@ -1053,7 +1053,7 @@ NewMIs.clear(); int Idx = NewMI->findRegisterUseOperandIdx(VirtReg, false); assert(Idx != -1); - SmallVector Ops; + SmallVector Ops; Ops.push_back(Idx); MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, NewMI, Ops, SS); if (FoldedMI) { @@ -1124,7 +1124,7 @@ MachineInstr *CommutedMI = TII->commuteInstruction(DefMI, true); if (!CommutedMI) return false; - SmallVector Ops; + SmallVector Ops; Ops.push_back(NewDstIdx); MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, CommutedMI, Ops, SS); // Not needed since foldMemoryOperand returns new MI. From sabre at nondot.org Thu Feb 12 11:33:11 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 12 Feb 2009 17:33:11 -0000 Subject: [llvm-commits] [llvm] r64382 - in /llvm/trunk: lib/Target/X86/X86ISelDAGToDAG.cpp test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll Message-ID: <200902121733.n1CHXB7D007755@zion.cs.uiuc.edu> Author: lattner Date: Thu Feb 12 11:33:11 2009 New Revision: 64382 URL: http://llvm.org/viewvc/llvm-project?rev=64382&view=rev Log: fix the X86 backend to just drop llvm.declare nodes for VLAs instead of leaving them in the DAG and then getting selection errors. This is a fix for PR3538. Added: llvm/trunk/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=64382&r1=64381&r2=64382&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Feb 12 11:33:11 2009 @@ -1563,17 +1563,29 @@ SDValue N1 = Node->getOperand(1); SDValue N2 = Node->getOperand(2); FrameIndexSDNode *FINode = dyn_cast(N1); - if (!FINode) - break; + + // FIXME: We need to handle this for VLAs. + if (!FINode) { + ReplaceUses(N.getValue(0), Chain); + return NULL; + } + if (N2.getOpcode() == ISD::ADD && N2.getOperand(0).getOpcode() == X86ISD::GlobalBaseReg) N2 = N2.getOperand(1); - if (N2.getOpcode() != X86ISD::Wrapper) - break; + + // If N2 is not Wrapper(decriptor) then the llvm.declare is mangled + // somehow, just ignore it. + if (N2.getOpcode() != X86ISD::Wrapper) { + ReplaceUses(N.getValue(0), Chain); + return NULL; + } GlobalAddressSDNode *GVNode = dyn_cast(N2.getOperand(0)); - if (!GVNode) - break; + if (GVNode == 0) { + ReplaceUses(N.getValue(0), Chain); + return NULL; + } SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(), TLI.getPointerTy()); SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GVNode->getGlobal(), @@ -1581,7 +1593,6 @@ SDValue Ops[] = { Tmp1, Tmp2, Chain }; return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl, MVT::Other, Ops, 3); - break; } } Added: llvm/trunk/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll?rev=64382&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll (added) +++ llvm/trunk/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll Thu Feb 12 11:33:11 2009 @@ -0,0 +1,76 @@ +; RUN: llvm-as < %s | llc +; RUN: llvm-as < %s | llc -march=x86-64 +; PR3538 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i386-apple-darwin9" + %llvm.dbg.anchor.type = type { i32, i32 } + %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 } + %llvm.dbg.block.type = type { i32, { }* } + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } + %llvm.dbg.composite.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, { }* } + %llvm.dbg.subprogram.type = type { i32, { }*, { }*, i8*, i8*, i8*, { }*, i32, { }*, i1, i1 } + %llvm.dbg.subrange.type = type { i32, i64, i64 } + %llvm.dbg.variable.type = type { i32, { }*, i8*, { }*, i32, { }* } + at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] + at .str = internal constant [4 x i8] c"t.c\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at .str1 = internal constant [2 x i8] c".\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1] + at .str2 = internal constant [6 x i8] c"clang\00", section "llvm.metadata" ; <[6 x i8]*> [#uses=1] + at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([2 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([6 x i8]* @.str2, i32 0, i32 0), i1 false, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] + at .str3 = internal constant [4 x i8] c"int\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] + at llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, i32 5 }, section "llvm.metadata" ; <%llvm.dbg.basictype.type*> [#uses=1] + at llvm.dbg.subprograms = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 46 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] + at .str4 = internal constant [5 x i8] c"test\00", section "llvm.metadata" ; <[5 x i8]*> [#uses=1] + at llvm.dbg.subprogram = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([5 x i8]* @.str4, i32 0, i32 0), i8* getelementptr ([5 x i8]* @.str4, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 3, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), i1 false, i1 true }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at .str5 = internal constant [2 x i8] c"X\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1] + at llvm.dbg.variable = internal constant %llvm.dbg.variable.type { i32 459009, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([2 x i8]* @.str5, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 3, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=1] + at llvm.dbg.block = internal constant %llvm.dbg.block.type { i32 458763, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*) }, section "llvm.metadata" ; <%llvm.dbg.block.type*> [#uses=1] + at llvm.dbg.subrange = internal constant %llvm.dbg.subrange.type { i32 458785, i64 0, i64 0 }, section "llvm.metadata" ; <%llvm.dbg.subrange.type*> [#uses=1] + at llvm.dbg.array = internal constant [1 x { }*] [{ }* bitcast (%llvm.dbg.subrange.type* @llvm.dbg.subrange to { }*)], section "llvm.metadata" ; <[1 x { }*]*> [#uses=1] + at llvm.dbg.composite = internal constant %llvm.dbg.composite.type { i32 458753, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 0, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast ([1 x { }*]* @llvm.dbg.array to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1] + at .str6 = internal constant [2 x i8] c"Y\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1] + at llvm.dbg.variable7 = internal constant %llvm.dbg.variable.type { i32 459008, { }* bitcast (%llvm.dbg.block.type* @llvm.dbg.block to { }*), i8* getelementptr ([2 x i8]* @.str6, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 4, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=1] + +define i32 @test(i32 %X) nounwind { +entry: + %retval = alloca i32 ; [#uses=1] + %X.addr = alloca i32 ; [#uses=3] + %saved_stack = alloca i8* ; [#uses=2] + call void @llvm.dbg.func.start({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*)) + store i32 %X, i32* %X.addr + %0 = bitcast i32* %X.addr to { }* ; <{ }*> [#uses=1] + call void @llvm.dbg.declare({ }* %0, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable to { }*)) + call void @llvm.dbg.region.start({ }* bitcast (%llvm.dbg.block.type* @llvm.dbg.block to { }*)) + call void @llvm.dbg.stoppoint(i32 4, i32 3, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + %1 = call i8* @llvm.stacksave() ; [#uses=1] + store i8* %1, i8** %saved_stack + %tmp = load i32* %X.addr ; [#uses=1] + %2 = mul i32 4, %tmp ; [#uses=1] + %vla = alloca i8, i32 %2 ; [#uses=1] + %tmp1 = bitcast i8* %vla to i32* ; [#uses=1] + %3 = bitcast i32* %tmp1 to { }* ; <{ }*> [#uses=1] + call void @llvm.dbg.declare({ }* %3, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable7 to { }*)) + call void @llvm.dbg.stoppoint(i32 5, i32 1, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*)) + call void @llvm.dbg.region.end({ }* bitcast (%llvm.dbg.block.type* @llvm.dbg.block to { }*)) + br label %cleanup + +cleanup: ; preds = %entry + %tmp2 = load i8** %saved_stack ; [#uses=1] + call void @llvm.stackrestore(i8* %tmp2) + call void @llvm.dbg.region.end({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*)) + %4 = load i32* %retval ; [#uses=1] + ret i32 %4 +} + +declare void @llvm.dbg.func.start({ }*) nounwind + +declare void @llvm.dbg.declare({ }*, { }*) nounwind + +declare void @llvm.dbg.region.start({ }*) nounwind + +declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind + +declare i8* @llvm.stacksave() nounwind + +declare void @llvm.stackrestore(i8*) nounwind + +declare void @llvm.dbg.region.end({ }*) nounwind From sabre at nondot.org Thu Feb 12 11:37:15 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 12 Feb 2009 17:37:15 -0000 Subject: [llvm-commits] [llvm] r64383 - /llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Message-ID: <200902121737.n1CHbFa2007922@zion.cs.uiuc.edu> Author: lattner Date: Thu Feb 12 11:37:15 2009 New Revision: 64383 URL: http://llvm.org/viewvc/llvm-project?rev=64383&view=rev Log: fix PR3538 for PPC Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=64383&r1=64382&r2=64383&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Feb 12 11:37:15 2009 @@ -1110,8 +1110,13 @@ SDValue N1 = N->getOperand(1); SDValue N2 = N->getOperand(2); FrameIndexSDNode *FINode = dyn_cast(N1); - if (!FINode) - break; + + // FIXME: We need to handle this for VLAs. + if (!FINode) { + ReplaceUses(Op.getValue(0), Chain); + return NULL; + } + if (N2.getOpcode() == ISD::ADD) { if (N2.getOperand(0).getOpcode() == ISD::ADD && N2.getOperand(0).getOperand(0).getOpcode() == PPCISD::GlobalBaseReg && @@ -1127,8 +1132,13 @@ N2.getOperand(1).getOpcode() == PPCISD::Lo) N2 = N2.getOperand(0).getOperand(0); } - if (!isa(N2)) - break; + + // If we don't have a global address here, the debug info is mangled, just + // drop it. + if (!isa(N2)) { + ReplaceUses(Op.getValue(0), Chain); + return NULL; + } int FI = cast(N1)->getIndex(); GlobalValue *GV = cast(N2)->getGlobal(); SDValue Tmp1 = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); From sabre at nondot.org Thu Feb 12 11:38:23 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 12 Feb 2009 17:38:23 -0000 Subject: [llvm-commits] [llvm] r64384 - /llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Message-ID: <200902121738.n1CHcNmw007971@zion.cs.uiuc.edu> Author: lattner Date: Thu Feb 12 11:38:23 2009 New Revision: 64384 URL: http://llvm.org/viewvc/llvm-project?rev=64384&view=rev Log: fix PR3538 for ARM. Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=64384&r1=64383&r2=64384&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Feb 12 11:38:23 2009 @@ -837,13 +837,18 @@ SDValue N1 = Op.getOperand(1); SDValue N2 = Op.getOperand(2); FrameIndexSDNode *FINode = dyn_cast(N1); - if (!FINode) - break; + // FIXME: handle VLAs. + if (!FINode) { + ReplaceUses(Op.getValue(0), Chain); + return NULL; + } if (N2.getOpcode() == ARMISD::PIC_ADD && isa(N2.getOperand(0))) N2 = N2.getOperand(0); LoadSDNode *Ld = dyn_cast(N2); - if (!Ld) - break; + if (!Ld) { + ReplaceUses(Op.getValue(0), Chain); + return NULL; + } SDValue BasePtr = Ld->getBasePtr(); assert(BasePtr.getOpcode() == ARMISD::Wrapper && isa(BasePtr.getOperand(0)) && @@ -855,15 +860,17 @@ GV = ACPV->getGV(); } else GV = dyn_cast(CP->getConstVal()); - if (GV) { - SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(), - TLI.getPointerTy()); - SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy()); - SDValue Ops[] = { Tmp1, Tmp2, Chain }; - return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl, - MVT::Other, Ops, 3); + if (!GV) { + ReplaceUses(Op.getValue(0), Chain); + return NULL; } - break; + + SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(), + TLI.getPointerTy()); + SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy()); + SDValue Ops[] = { Tmp1, Tmp2, Chain }; + return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl, + MVT::Other, Ops, 3); } } From gohman at apple.com Thu Feb 12 12:08:24 2009 From: gohman at apple.com (Dan Gohman) Date: Thu, 12 Feb 2009 18:08:24 -0000 Subject: [llvm-commits] [llvm] r64388 - in /llvm/trunk: include/llvm/Analysis/LoopInfo.h lib/Transforms/Scalar/LoopIndexSplit.cpp Message-ID: <200902121808.n1CI8OM8009167@zion.cs.uiuc.edu> Author: djg Date: Thu Feb 12 12:08:24 2009 New Revision: 64388 URL: http://llvm.org/viewvc/llvm-project?rev=64388&view=rev Log: Add a utility function to LoopInfo to return the exit block when the loop has exactly one exit, and make use of it in LoopIndexSplit. Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopInfo.h?rev=64388&r1=64387&r2=64388&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/LoopInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/LoopInfo.h Thu Feb 12 12:08:24 2009 @@ -184,6 +184,16 @@ } } + /// getExitingBlock - If getExitingBlocks would return exactly one block, + /// return that block. Otherwise return null. + BlockT *getExitingBlock() const { + SmallVector ExitingBlocks; + getExitingBlocks(ExitingBlocks); + if (ExitingBlocks.size() == 1) + return ExitingBlocks[0]; + return 0; + } + /// getExitBlocks - Return all of the successor blocks of this loop. These /// are the blocks _outside of the current loop_ which are branched to. /// Modified: llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp?rev=64388&r1=64387&r2=64388&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp Thu Feb 12 12:08:24 2009 @@ -236,15 +236,14 @@ } // Reject loop if loop exit condition is not suitable. - SmallVector EBs; - L->getExitingBlocks(EBs); - if (EBs.size() != 1) + BasicBlock *ExitingBlock = L->getExitingBlock(); + if (!ExitingBlock) return false; - BranchInst *EBR = dyn_cast(EBs[0]->getTerminator()); + BranchInst *EBR = dyn_cast(ExitingBlock->getTerminator()); if (!EBR) return false; ExitCondition = dyn_cast(EBR->getCondition()); if (!ExitCondition) return false; - if (EBs[0] != L->getLoopLatch()) return false; + if (ExitingBlock != L->getLoopLatch()) return false; IVExitValue = ExitCondition->getOperand(1); if (!L->isLoopInvariant(IVExitValue)) IVExitValue = ExitCondition->getOperand(0); From mrs at apple.com Thu Feb 12 12:36:55 2009 From: mrs at apple.com (Mike Stump) Date: Thu, 12 Feb 2009 10:36:55 -0800 Subject: [llvm-commits] [llvm] r62746 - /llvm/trunk/Makefile.rules In-Reply-To: <20090212061954.GA99037@pom.apple.com> References: <200901220324.n0M3OMbY009941@zion.cs.uiuc.edu> <20090212061954.GA99037@pom.apple.com> Message-ID: On Feb 11, 2009, at 10:19 PM, Julien Lerouge wrote: > Order-only dependencies are not supported by make 3.79 it seems. Ick, that's kinda annoying. I didn't realize they were newer than 3.79. Should we update the requirements? 3.80 was around in the 10.4 timeframe, though, I don't know which version the feature came in on. From anton at korobeynikov.info Thu Feb 12 12:43:24 2009 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Thu, 12 Feb 2009 21:43:24 +0300 Subject: [llvm-commits] [llvm] r62746 - /llvm/trunk/Makefile.rules In-Reply-To: References: <200901220324.n0M3OMbY009941@zion.cs.uiuc.edu> <20090212061954.GA99037@pom.apple.com> Message-ID: <1234464204.6663.1.camel@aslstation> Hello, Mike > Ick, that's kinda annoying. I didn't realize they were newer than > 3.79. Should we update the requirements? 3.80 was around in the 10.4 > timeframe, though, I don't know which version the feature came in on. This is mingw32 (well, actually msys), not darwin. And it still has 3.79 shipped by default. -- With best regards, Anton Korobeynikov. Faculty of Mathematics & Mechanics, Saint Petersburg State University. From mrs at apple.com Thu Feb 12 12:56:40 2009 From: mrs at apple.com (Mike Stump) Date: Thu, 12 Feb 2009 10:56:40 -0800 Subject: [llvm-commits] [llvm] r64352 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp In-Reply-To: <200902121103.36116.baldrick@free.fr> References: <200902120318.n1C3IYrD031674@zion.cs.uiuc.edu> <200902121008.13063.baldrick@free.fr> <200902121103.36116.baldrick@free.fr> Message-ID: On Feb 12, 2009, at 2:03 AM, Duncan Sands wrote: > I'm told that the C standard (not the only relevant standard, but an > important one) says that you are allowed to assume that the resulting > pointer does not alias the original pointer. That sounds wrong, but maybe I'm missing something (probably due to the context of the discussion). Do you happen to have a quote or a reference? From jlerouge at apple.com Thu Feb 12 13:03:22 2009 From: jlerouge at apple.com (Julien Lerouge) Date: Thu, 12 Feb 2009 11:03:22 -0800 Subject: [llvm-commits] [llvm] r62746 - /llvm/trunk/Makefile.rules In-Reply-To: <1234464204.6663.1.camel@aslstation> References: <200901220324.n0M3OMbY009941@zion.cs.uiuc.edu> <20090212061954.GA99037@pom.apple.com> <1234464204.6663.1.camel@aslstation> Message-ID: <20090212190322.GB13334@pom.apple.com> On Thu, Feb 12, 2009 at 09:43:24PM +0300, Anton Korobeynikov wrote: > Hello, Mike > > > Ick, that's kinda annoying. I didn't realize they were newer than > > 3.79. Should we update the requirements? 3.80 was around in the 10.4 > > timeframe, though, I don't know which version the feature came in on. > This is mingw32 (well, actually msys), not darwin. And it still has 3.79 > shipped by default. order-only prerequisites appeared in make 3.80 I believe. There is a version of make 3.81 available for msys in "Technology Preview: MSYS-1.0.11" : http://sourceforge.net/project/showfiles.php?group_id=2435&package_id=24963 Thanks, Julien -- Julien Lerouge PGP Key Id: 0xB1964A62 PGP Fingerprint: 392D 4BAD DB8B CE7F 4E5F FA3C 62DB 4AA7 B196 4A62 PGP Public Key from: keyserver.pgp.com From isanbard at gmail.com Thu Feb 12 13:10:37 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 12 Feb 2009 19:10:37 -0000 Subject: [llvm-commits] [llvm] r64394 - in /llvm/branches/Apple/Dib: lib/Transforms/Scalar/CodeGenPrepare.cpp test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll Message-ID: <200902121910.n1CJAbQ1011796@zion.cs.uiuc.edu> Author: void Date: Thu Feb 12 13:10:37 2009 New Revision: 64394 URL: http://llvm.org/viewvc/llvm-project?rev=64394&view=rev Log: Pull r64362 into Dib: fix PR3537: if resetting bbi back to the start of a block, we need to forget about already inserted expressions. Added: llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll Modified: llvm/branches/Apple/Dib/lib/Transforms/Scalar/CodeGenPrepare.cpp Modified: llvm/branches/Apple/Dib/lib/Transforms/Scalar/CodeGenPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=64394&r1=64393&r2=64394&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Transforms/Scalar/CodeGenPrepare.cpp (original) +++ llvm/branches/Apple/Dib/lib/Transforms/Scalar/CodeGenPrepare.cpp Thu Feb 12 13:10:37 2009 @@ -1241,11 +1241,13 @@ // computation. Value *&SunkAddr = SunkAddrs[Addr]; if (SunkAddr) { - DEBUG(cerr << "CGP: Reusing nonlocal addrmode: " << AddrMode << "\n"); + DEBUG(cerr << "CGP: Reusing nonlocal addrmode: " << AddrMode << " for " + << *MemoryInst); if (SunkAddr->getType() != Addr->getType()) SunkAddr = new BitCastInst(SunkAddr, Addr->getType(), "tmp", InsertPt); } else { - DEBUG(cerr << "CGP: SINKING nonlocal addrmode: " << AddrMode << "\n"); + DEBUG(cerr << "CGP: SINKING nonlocal addrmode: " << AddrMode << " for " + << *MemoryInst); const Type *IntPtrTy = TLI->getTargetData()->getIntPtrType(); Value *Result = 0; @@ -1505,9 +1507,12 @@ if (TLI && isa(CI->getCalledValue())) if (const TargetAsmInfo *TAI = TLI->getTargetMachine().getTargetAsmInfo()) { - if (TAI->ExpandInlineAsm(CI)) + if (TAI->ExpandInlineAsm(CI)) { BBI = BB.begin(); - else + // Avoid processing instructions out of order, which could cause + // reuse before a value is defined. + SunkAddrs.clear(); + } else // Sink address computing for memory operands into the block. MadeChange |= OptimizeInlineAsmInst(I, &(*CI), SunkAddrs); } Added: llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll?rev=64394&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll (added) +++ llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll Thu Feb 12 13:10:37 2009 @@ -0,0 +1,35 @@ +; RUN: llvm-as < %s | llc +; PR3537 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i386-apple-darwin9.6" + %struct.GetBitContext = type <{ i8*, i8*, i32, i32 }> + +define i32 @alac_decode_frame() nounwind { +entry: + %tmp2 = load i8** null ; [#uses=2] + %tmp34 = getelementptr i8* %tmp2, i32 4 ; [#uses=2] + %tmp5.i424 = bitcast i8* %tmp34 to i8** ; [#uses=2] + %tmp15.i = getelementptr i8* %tmp2, i32 12 ; [#uses=1] + %0 = bitcast i8* %tmp15.i to i32* ; [#uses=1] + br i1 false, label %if.then43, label %if.end47 + +if.then43: ; preds = %entry + ret i32 0 + +if.end47: ; preds = %entry + %tmp5.i590 = load i8** %tmp5.i424 ; [#uses=0] + store i32 19, i32* %0 + %tmp6.i569 = load i8** %tmp5.i424 ; [#uses=0] + %1 = call i32 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 0) nounwind ; [#uses=0] + br i1 false, label %bb.nph, label %if.then63 + +if.then63: ; preds = %if.end47 + unreachable + +bb.nph: ; preds = %if.end47 + %2 = bitcast i8* %tmp34 to %struct.GetBitContext* ; <%struct.GetBitContext*> [#uses=1] + %call9.i = call fastcc i32 @decode_scalar(%struct.GetBitContext* %2, i32 0, i32 0, i32 0) nounwind ; [#uses=0] + unreachable +} + +declare fastcc i32 @decode_scalar(%struct.GetBitContext* nocapture, i32, i32, i32) nounwind From isanbard at gmail.com Thu Feb 12 13:12:08 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 12 Feb 2009 19:12:08 -0000 Subject: [llvm-commits] [llvm] r64395 - in /llvm/branches/Apple/Dib: lib/Transforms/Utils/InlineFunction.cpp test/Transforms/Inline/inline-invoke-tail.ll Message-ID: <200902121912.n1CJC8I7011875@zion.cs.uiuc.edu> Author: void Date: Thu Feb 12 13:12:08 2009 New Revision: 64395 URL: http://llvm.org/viewvc/llvm-project?rev=64395&view=rev Log: Pull r64364 into Dib: Fix a nasty bug (PR3550) where the inline pass could incorrectly mark calls with the tail marker when inlining them through an invoke. Patch, testcase, and perfect analysis by Jay Foad! Added: llvm/branches/Apple/Dib/test/Transforms/Inline/inline-invoke-tail.ll Modified: llvm/branches/Apple/Dib/lib/Transforms/Utils/InlineFunction.cpp Modified: llvm/branches/Apple/Dib/lib/Transforms/Utils/InlineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Transforms/Utils/InlineFunction.cpp?rev=64395&r1=64394&r2=64395&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Transforms/Utils/InlineFunction.cpp (original) +++ llvm/branches/Apple/Dib/lib/Transforms/Utils/InlineFunction.cpp Thu Feb 12 13:12:08 2009 @@ -203,10 +203,10 @@ CalledFunc->getFunctionType()->isVarArg()) return false; - // If the call to the callee is a non-tail call, we must clear the 'tail' + // If the call to the callee is not a tail call, we must clear the 'tail' // flags on any calls that we inline. bool MustClearTailCallFlags = - isa(TheCall) && !cast(TheCall)->isTailCall(); + !(isa(TheCall) && cast(TheCall)->isTailCall()); // If the call to the callee cannot throw, set the 'nounwind' flag on any // calls that we inline. Added: llvm/branches/Apple/Dib/test/Transforms/Inline/inline-invoke-tail.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/Transforms/Inline/inline-invoke-tail.ll?rev=64395&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/Transforms/Inline/inline-invoke-tail.ll (added) +++ llvm/branches/Apple/Dib/test/Transforms/Inline/inline-invoke-tail.ll Thu Feb 12 13:12:08 2009 @@ -0,0 +1,35 @@ +; RUN: llvm-as < %s | opt -inline | llvm-dis | not grep {tail call void @llvm.memcpy.i32} +; PR3550 + +define internal void @foo(i32* %p, i32* %q) { + %pp = bitcast i32* %p to i8* + %qq = bitcast i32* %q to i8* + tail call void @llvm.memcpy.i32(i8* %pp, i8* %qq, i32 4, i32 1) + ret void +} + +declare void @llvm.memcpy.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind + +define i32 @main() { + %a = alloca i32 ; [#uses=3] + %b = alloca i32 ; [#uses=2] + store i32 1, i32* %a, align 4 + store i32 0, i32* %b, align 4 + invoke void @foo(i32* %a, i32* %b) + to label %invcont unwind label %lpad + +invcont: + %retval = load i32* %a, align 4 + ret i32 %retval + +lpad: + %eh_ptr = call i8* @llvm.eh.exception() + %eh_select = call i32 (i8*, i8*, ...)* @llvm.eh.selector.i32(i8* %eh_ptr, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* null) + unreachable +} + +declare i8* @llvm.eh.exception() nounwind + +declare i32 @llvm.eh.selector.i32(i8*, i8*, ...) nounwind + +declare i32 @__gxx_personality_v0(...) From gohman at apple.com Thu Feb 12 14:25:38 2009 From: gohman at apple.com (Dan Gohman) Date: Thu, 12 Feb 2009 20:25:38 -0000 Subject: [llvm-commits] [test-suite] r64398 - /test-suite/trunk/SingleSource/UnitTests/Makefile Message-ID: <200902122025.n1CKPdIF014474@zion.cs.uiuc.edu> Author: djg Date: Thu Feb 12 14:25:37 2009 New Revision: 64398 URL: http://llvm.org/viewvc/llvm-project?rev=64398&view=rev Log: Test ObjC on Darwin when ARCH=x86_64 too. Modified: test-suite/trunk/SingleSource/UnitTests/Makefile Modified: test-suite/trunk/SingleSource/UnitTests/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Makefile?rev=64398&r1=64397&r2=64398&view=diff ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/Makefile (original) +++ test-suite/trunk/SingleSource/UnitTests/Makefile Thu Feb 12 14:25:37 2009 @@ -16,8 +16,11 @@ DIRS += SignlessTypes Threads # Only test Obj-C on darwin/x86 for time being. -ifeq ($(ARCH),x86) ifeq ($(OS),Darwin) +ifeq ($(ARCH),x86) +DIRS += ObjC ObjC++ +endif +ifeq ($(ARCH),x86_64) DIRS += ObjC ObjC++ endif endif From gohman at apple.com Thu Feb 12 14:53:27 2009 From: gohman at apple.com (Dan Gohman) Date: Thu, 12 Feb 2009 20:53:27 -0000 Subject: [llvm-commits] [llvm] r64399 - /llvm/trunk/tools/bugpoint/ToolRunner.cpp Message-ID: <200902122053.n1CKrROf015464@zion.cs.uiuc.edu> Author: djg Date: Thu Feb 12 14:53:27 2009 New Revision: 64399 URL: http://llvm.org/viewvc/llvm-project?rev=64399&view=rev Log: Rename bugpoint's error message file so that if it somehow gets left behind, it's less cryptic. Modified: llvm/trunk/tools/bugpoint/ToolRunner.cpp Modified: llvm/trunk/tools/bugpoint/ToolRunner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/ToolRunner.cpp?rev=64399&r1=64398&r2=64399&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/ToolRunner.cpp (original) +++ llvm/trunk/tools/bugpoint/ToolRunner.cpp Thu Feb 12 14:53:27 2009 @@ -80,7 +80,7 @@ OS << "\n"; // Rerun the compiler, capturing any error messages to print them. - sys::Path ErrorFilename("error_messages"); + sys::Path ErrorFilename("bugpoint.program_error_messages"); std::string ErrMsg; if (ErrorFilename.makeUnique(true, &ErrMsg)) { std::cerr << "Error making unique filename: " << ErrMsg << "\n"; From dalej at apple.com Thu Feb 12 14:58:09 2009 From: dalej at apple.com (Dale Johannesen) Date: Thu, 12 Feb 2009 20:58:09 -0000 Subject: [llvm-commits] [llvm] r64400 - in /llvm/trunk: lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll Message-ID: <200902122058.n1CKw9RW015665@zion.cs.uiuc.edu> Author: johannes Date: Thu Feb 12 14:58:09 2009 New Revision: 64400 URL: http://llvm.org/viewvc/llvm-project?rev=64400&view=rev Log: Arrange to print constants that match "n" and "i" constraints in inline asm as signed (what gcc does). Add partial support for x86-specific "e" and "Z" constraints, with appropriate signedness for printing. Added: llvm/trunk/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=64400&r1=64399&r2=64400&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Feb 12 14:58:09 2009 @@ -2082,8 +2082,11 @@ if (C) { // just C, no GV. // Simple constants are not allowed for 's'. if (ConstraintLetter != 's') { - Ops.push_back(DAG.getTargetConstant(C->getAPIntValue(), - Op.getValueType())); + // gcc prints these as sign extended. Sign extend value to 64 bits + // now; without this it would get ZExt'd later in + // ScheduleDAGSDNodes::EmitNode, which is very generic. + Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), + MVT::i64)); return; } } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=64400&r1=64399&r2=64400&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Feb 12 14:58:09 2009 @@ -8152,6 +8152,9 @@ case 'y': case 'Y': return C_RegisterClass; + case 'e': + case 'Z': + return C_Other; default: break; } @@ -8211,10 +8214,38 @@ } } return; + case 'e': { + // 32-bit signed value + if (ConstantSDNode *C = dyn_cast(Op)) { + const ConstantInt *CI = C->getConstantIntValue(); + if (CI->isValueValidForType(Type::Int32Ty, C->getSExtValue())) { + // Widen to 64 bits here to get it sign extended. + Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); + break; + } + // FIXME gcc accepts some relocatable values here too, but only in certain + // memory models; it's complicated. + } + return; + } + case 'Z': { + // 32-bit unsigned value + if (ConstantSDNode *C = dyn_cast(Op)) { + const ConstantInt *CI = C->getConstantIntValue(); + if (CI->isValueValidForType(Type::Int32Ty, C->getZExtValue())) { + Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); + break; + } + } + // FIXME gcc accepts some relocatable values here too, but only in certain + // memory models; it's complicated. + return; + } case 'i': { // Literal immediates are always ok. if (ConstantSDNode *CST = dyn_cast(Op)) { - Result = DAG.getTargetConstant(CST->getZExtValue(), Op.getValueType()); + // Widen to 64 bits here to get it sign extended. + Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); break; } Added: llvm/trunk/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll?rev=64400&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll (added) +++ llvm/trunk/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll Thu Feb 12 14:58:09 2009 @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llc -march=x86 | grep {\$-81920} | count 3 +; RUN: llvm-as < %s | llc -march=x86 | grep {\$4294885376} | count 1 + +; ModuleID = 'shant.c' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i386-apple-darwin9.6" + +define void @f() nounwind { +entry: + call void asm sideeffect "foo $0", "n,~{dirflag},~{fpsr},~{flags}"(i32 -81920) nounwind + call void asm sideeffect "foo $0", "i,~{dirflag},~{fpsr},~{flags}"(i32 -81920) nounwind + call void asm sideeffect "foo $0", "e,~{dirflag},~{fpsr},~{flags}"(i32 -81920) nounwind + call void asm sideeffect "foo $0", "Z,~{dirflag},~{fpsr},~{flags}"(i64 4294885376) nounwind + br label %return + +return: ; preds = %entry + ret void +} From natebegeman at mac.com Thu Feb 12 15:28:33 2009 From: natebegeman at mac.com (Nate Begeman) Date: Thu, 12 Feb 2009 21:28:33 -0000 Subject: [llvm-commits] [llvm] r64401 - in /llvm/trunk: include/llvm/Bitcode/LLVMBitCodes.h lib/Bitcode/Reader/BitcodeReader.cpp lib/Bitcode/Writer/BitcodeWriter.cpp lib/VMCore/Constants.cpp test/Transforms/InstCombine/shufflevec-constant.ll Message-ID: <200902122128.n1CLSXRi016840@zion.cs.uiuc.edu> Author: sampo Date: Thu Feb 12 15:28:33 2009 New Revision: 64401 URL: http://llvm.org/viewvc/llvm-project?rev=64401&view=rev Log: Add suppport for ConstantExprs of shufflevectors whose result type is not equal to the type of the vectors being shuffled. Added: llvm/trunk/test/Transforms/InstCombine/shufflevec-constant.ll Modified: llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp llvm/trunk/lib/VMCore/Constants.cpp Modified: llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h?rev=64401&r1=64400&r2=64401&view=diff ============================================================================== --- llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h (original) +++ llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h Thu Feb 12 15:28:33 2009 @@ -125,7 +125,8 @@ CST_CODE_CE_INSERTELT = 15, // CE_INSERTELT: [opval, opval, opval] CST_CODE_CE_SHUFFLEVEC = 16, // CE_SHUFFLEVEC: [opval, opval, opval] CST_CODE_CE_CMP = 17, // CE_CMP: [opty, opval, opval, pred] - CST_CODE_INLINEASM = 18 // INLINEASM: [sideeffect,asmstr,conststr] + CST_CODE_INLINEASM = 18, // INLINEASM: [sideeffect,asmstr,conststr] + CST_CODE_CE_SHUFVEC_EX = 19 // SHUFVEC_EX: [opty, opval, opval, opval] }; /// CastOpcodes - These are values used in the bitcode files to encode which Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=64401&r1=64400&r2=64401&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Thu Feb 12 15:28:33 2009 @@ -933,7 +933,7 @@ case bitc::CST_CODE_CE_SHUFFLEVEC: { // CE_SHUFFLEVEC: [opval, opval, opval] const VectorType *OpTy = dyn_cast(CurTy); if (Record.size() < 3 || OpTy == 0) - return Error("Invalid CE_INSERTELT record"); + return Error("Invalid CE_SHUFFLEVEC record"); Constant *Op0 = ValueList.getConstantFwdRef(Record[0], OpTy); Constant *Op1 = ValueList.getConstantFwdRef(Record[1], OpTy); const Type *ShufTy=VectorType::get(Type::Int32Ty, OpTy->getNumElements()); @@ -941,6 +941,18 @@ V = ConstantExpr::getShuffleVector(Op0, Op1, Op2); break; } + case bitc::CST_CODE_CE_SHUFVEC_EX: { // [opty, opval, opval, opval] + const VectorType *RTy = dyn_cast(CurTy); + const VectorType *OpTy = dyn_cast(getTypeByID(Record[0])); + if (Record.size() < 4 || RTy == 0 || OpTy == 0) + return Error("Invalid CE_SHUFVEC_EX record"); + Constant *Op0 = ValueList.getConstantFwdRef(Record[1], OpTy); + Constant *Op1 = ValueList.getConstantFwdRef(Record[2], OpTy); + const Type *ShufTy=VectorType::get(Type::Int32Ty, RTy->getNumElements()); + Constant *Op2 = ValueList.getConstantFwdRef(Record[3], ShufTy); + V = ConstantExpr::getShuffleVector(Op0, Op1, Op2); + break; + } case bitc::CST_CODE_CE_CMP: { // CE_CMP: [opty, opval, opval, pred] if (Record.size() < 4) return Error("Invalid CE_CMP record"); const Type *OpTy = getTypeByID(Record[0]); Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=64401&r1=64400&r2=64401&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original) +++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Thu Feb 12 15:28:33 2009 @@ -643,7 +643,16 @@ Record.push_back(VE.getValueID(C->getOperand(2))); break; case Instruction::ShuffleVector: - Code = bitc::CST_CODE_CE_SHUFFLEVEC; + // If the return type and argument types are the same, this is a + // standard shufflevector instruction. If the types are different, + // then the shuffle is widening or truncating the input vectors, and + // the argument type must also be encoded. + if (C->getType() == C->getOperand(0)->getType()) { + Code = bitc::CST_CODE_CE_SHUFFLEVEC; + } else { + Code = bitc::CST_CODE_CE_SHUFVEC_EX; + Record.push_back(VE.getTypeID(C->getOperand(0)->getType())); + } Record.push_back(VE.getValueID(C->getOperand(0))); Record.push_back(VE.getValueID(C->getOperand(1))); Record.push_back(VE.getValueID(C->getOperand(2))); Modified: llvm/trunk/lib/VMCore/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=64401&r1=64400&r2=64401&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Constants.cpp (original) +++ llvm/trunk/lib/VMCore/Constants.cpp Thu Feb 12 15:28:33 2009 @@ -554,7 +554,10 @@ return User::operator new(s, 3); } ShuffleVectorConstantExpr(Constant *C1, Constant *C2, Constant *C3) - : ConstantExpr(C1->getType(), Instruction::ShuffleVector, + : ConstantExpr(VectorType::get( + cast(C1->getType())->getElementType(), + cast(C3->getType())->getNumElements()), + Instruction::ShuffleVector, &Op<0>(), 3) { Op<0>() = C1; Op<1>() = C2; @@ -2349,7 +2352,11 @@ Constant *Mask) { assert(ShuffleVectorInst::isValidOperands(V1, V2, Mask) && "Invalid shuffle vector constant expr operands!"); - return getShuffleVectorTy(V1->getType(), V1, V2, Mask); + + unsigned NElts = cast(Mask->getType())->getNumElements(); + const Type *EltTy = cast(V1->getType())->getElementType(); + const Type *ShufTy = VectorType::get(EltTy, NElts); + return getShuffleVectorTy(ShufTy, V1, V2, Mask); } Constant *ConstantExpr::getInsertValueTy(const Type *ReqTy, Constant *Agg, Added: llvm/trunk/test/Transforms/InstCombine/shufflevec-constant.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/shufflevec-constant.ll?rev=64401&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/shufflevec-constant.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/shufflevec-constant.ll Thu Feb 12 15:28:33 2009 @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep "2 x float" + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i386-apple-darwin9" + +define <4 x float> @__inff4() nounwind readnone { +entry: + %tmp14 = extractelement <1 x double> bitcast (<2 x float> to <1 x double>), i32 0 ; [#uses=1] + %tmp4 = bitcast double %tmp14 to i64 ; [#uses=1] + %tmp3 = bitcast i64 %tmp4 to <2 x float> ; <<2 x float>> [#uses=1] + %tmp8 = shufflevector <2 x float> %tmp3, <2 x float> undef, <4 x i32> ; <<4 x float>> [#uses=1] + %tmp9 = shufflevector <4 x float> zeroinitializer, <4 x float> %tmp8, <4 x i32> ; <<4 x float>> [#uses=0] + ret <4 x float> %tmp9 +} From isanbard at gmail.com Thu Feb 12 15:38:40 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 12 Feb 2009 21:38:40 -0000 Subject: [llvm-commits] [llvm] r64402 - /llvm/branches/Apple/Dib/ Message-ID: <200902122138.n1CLceIT017228@zion.cs.uiuc.edu> Author: void Date: Thu Feb 12 15:38:39 2009 New Revision: 64402 URL: http://llvm.org/viewvc/llvm-project?rev=64402&view=rev Log: Initialized merge tracking via "svnmerge" with revisions "1-63820" from https://void at llvm.org/svn/llvm-project/llvm/branches/release_25 Modified: llvm/branches/Apple/Dib/ (props changed) Propchange: llvm/branches/Apple/Dib/ ------------------------------------------------------------------------------ svnmerge-integrated = /llvm/branches/release_25:1-63820 From isanbard at gmail.com Thu Feb 12 15:39:59 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 12 Feb 2009 21:39:59 -0000 Subject: [llvm-commits] [llvm] r64403 - /llvm/branches/Apple/Dib/utils/buildit/build_llvm Message-ID: <200902122139.n1CLdxOH017290@zion.cs.uiuc.edu> Author: void Date: Thu Feb 12 15:39:58 2009 New Revision: 64403 URL: http://llvm.org/viewvc/llvm-project?rev=64403&view=rev Log: Need to recommit build_llvm. Removed: llvm/branches/Apple/Dib/utils/buildit/build_llvm Removed: llvm/branches/Apple/Dib/utils/buildit/build_llvm URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/utils/buildit/build_llvm?rev=64402&view=auto ============================================================================== --- llvm/branches/Apple/Dib/utils/buildit/build_llvm (original) +++ llvm/branches/Apple/Dib/utils/buildit/build_llvm (removed) @@ -1,270 +0,0 @@ -#!/bin/sh -# LLVM LOCAL file B&I - -set -x - -# Build LLVM the "Apple way". -# Parameters: - -# The first parameter is a space-separated list of the architectures the -# compilers will run on. For instance, "ppc i386". If the current machine -# isn't in the list, it will (effectively) be added. -# FIXME: HOSTS is not used in this script. Use it or Remove it. -HOSTS="$1" - -# The second parameter is a space-separated list of the architectures the -# compilers will generate code for. If the current machine isn't in the list, a -# compiler for it will get built anyway, but won't be installed. -TARGETS="$2" - -# The third parameter is the path to the compiler sources. There should be a -# shell script named 'configure' in this directory. This script makes a copy... -ORIG_SRC_DIR="$3" - -# The fourth parameter is the location where the LLVM will be installed. You can -# move it once it's built, so this mostly controls the layout of $DEST_DIR. -DEST_ROOT="$4" - -# The fifth parameter is the place where the compiler will be copied once it's -# built. -DEST_DIR="$5" - -# The sixth parameter is a directory in which to place information (like -# unstripped executables and generated source files) helpful in debugging the -# resulting compiler. -SYM_DIR="$6" - -# The seventh parameter is a yes/no that indicates whether assertions should be -# enabled in the LLVM libs/tools. -LLVM_ASSERTIONS="$7" - -# The eighth parameter is a yes/no that indicates whether this is an optimized -# build. -LLVM_OPTIMIZED="$8" - -# The nineth parameter is the version number of the submission, e.g. 1007. -LLVM_SUBMIT_VERSION="$9" - -# The tenth parameter is the subversion number of the submission, e.g. 03. -LLVM_SUBMIT_SUBVERSION="${10}" - -# The current working directory is where the build will happen. It may already -# contain a partial result of an interrupted build, in which case this script -# will continue where it left off. -DIR=`pwd` - -DARWIN_VERS=`uname -r | sed 's/\..*//'` -echo DARWIN_VERS = $DARWIN_VERS - -# If the user has CC set in their environment unset it now -unset CC - -DT_HOME=$DEST_DIR/Developer/usr -DEST_ROOT="/Developer$DEST_ROOT" -if [ "x$DEVELOPER_BIN" != "x" ]; then - DT_HOME=$DEST_DIR/$DEVELOPER_DIR/usr - DEST_ROOT="/$DEVELOPER_DIR$DEST_ROOT" -fi - -################################################################################ -# Run the build. - -# Create the source tree we'll actually use to build, deleting -# tcl since it doesn't actually build properly in a cross environment -# and we don't really need it. -SRC_DIR=$DIR/src -rm -rf $SRC_DIR || exit 1 -mkdir $SRC_DIR || exit 1 -ln -s $ORIG_SRC_DIR/* $SRC_DIR/ || exit 1 - -# Build the LLVM tree universal. -mkdir -p $DIR/obj-llvm || exit 1 -cd $DIR/obj-llvm || exit 1 - -if [ \! -f Makefile.config ]; then - $SRC_DIR/configure --prefix=$DT_HOME/local \ - --enable-targets=arm,x86,powerpc,cbe \ - --enable-assertions=$LLVM_ASSERTIONS \ - --enable-optimized=$LLVM_OPTIMIZED \ - || exit 1 -fi - -SUBVERSION=`echo $RC_ProjectSourceVersion | sed -e 's/[^.]*\.\([0-9]*\).*/\1/'` - -if [ "x$SUBVERSION" != "x$RC_ProjectSourceVersion" ]; then - LLVM_SUBMIT_SUBVERSION=`printf "%02d" $SUBVERSION` - RC_ProjectSourceVersion=`echo $RC_ProjectSourceVersion | sed -e 's/\..*//'` - LLVM_SUBMIT_VERSION=$RC_ProjectSourceVersion -fi - -if [ "x$LLVM_SUBMIT_SUBVERSION" = "x00" -o "x$LLVM_SUBMIT_SUBVERSION" = "x0" ]; then - LLVM_VERSION="$LLVM_SUBMIT_VERSION" -else - LLVM_VERSION="$LLVM_SUBMIT_VERSION-$LLVM_SUBMIT_SUBVERSION" -fi - -GCC_VER=`cc --version 2>/dev/null | sed 1q` - -if echo "$GCC_VER" | grep GCC > /dev/null; then - GCC_VER=`echo $GCC_VER | sed -e 's/.*(GCC) \([0-9.][0-9.]*\).*/\1/'` - MAJ_VER=`echo $GCC_VER | sed 's/\..*//'` - MIN_VER=`echo $GCC_VER | sed 's/[^.]*\.\([0-9]*\).*/\1/'` -fi - -JOBS_FLAG="" - -# Note: If compiling with GCC 4.0, don't pass the -jN flag. Building universal -# already has parallelism and we don't want to make the builders hit swap by -# firing off too many gccs at the same time. -if [ "x$MAJ_VER" != "x4" -o "x$MIN_VER" != "x0" ]; then - # Figure out how many make processes to run. - SYSCTL=`sysctl -n hw.activecpu` - - # hw.activecpu only available in 10.2.6 and later - if [ -z "$SYSCTL" ]; then - SYSCTL=`sysctl -n hw.ncpu` - fi - - # sysctl -n hw.* does not work when invoked via B&I chroot /BuildRoot. - # Builders can default to 2, since even if they are single processor, - # nothing else is running on the machine. - if [ -z "$SYSCTL" ]; then - SYSCTL=2 - fi - - JOBS_FLAG="-j $SYSCTL" -fi - -make $JOBS_FLAG $OPTIMIZE_OPTS UNIVERSAL=1 UNIVERSAL_ARCH="$TARGETS" \ - LLVM_SUBMIT_VERSION=$LLVM_SUBMIT_VERSION \ - LLVM_SUBMIT_SUBVERSION=$LLVM_SUBMIT_SUBVERSION \ - CXXFLAGS="-DLLVM_VERSION_INFO='\" Apple Build #$LLVM_VERSION\"'" \ - VERBOSE=1 - -if ! test $? == 0 ; then - echo "error: LLVM 'make' failed!" - exit 1 -fi - -################################################################################ -# Construct the actual destination root, by copying stuff from $DIR/dst-* to -# $DEST_DIR, with occasional 'lipo' commands. - -cd $DEST_DIR || exit 1 - -# Clean out DEST_DIR in case -noclean was passed to buildit. -rm -rf * || exit 1 - -cd $DIR/obj-llvm || exit 1 - -# Install the tree into the destination directory. -make $LOCAL_MAKEFLAGS $OPTIMIZE_OPTS UNIVERSAL=1 UNIVERSAL_ARCH="$TARGETS" \ - LLVM_SUBMIT_VERSION=$LLVM_SUBMIT_VERSION \ - LLVM_SUBMIT_SUBVERSION=$LLVM_SUBMIT_SUBVERSION \ - OPTIMIZE_OPTION='-O2' VERBOSE=1 install - -if ! test $? == 0 ; then - echo "error: LLVM 'make install' failed!" - exit 1 -fi - -# Install Version.h -RC_ProjectSourceSubversion=`printf "%d" $LLVM_SUBMIT_SUBVERSION` -echo "#define LLVM_VERSION ${RC_ProjectSourceVersion}" > $DEST_DIR$DEST_ROOT/include/llvm/Version.h -echo "#define LLVM_MINOR_VERSION ${RC_ProjectSourceSubversion}" >> $DEST_DIR$DEST_ROOT/include/llvm/Version.h - -if [ "x$LLVM_DEBUG" != "x1" ]; then - # Strip local symbols from llvm libraries. - strip -S $DEST_DIR$DEST_ROOT/lib/*.[oa] - for f in `ls $DEST_DIR$DEST_ROOT/lib/*.so`; do - strip -Sx $f - done -fi - -# Copy over the tblgen utility. -cp `find $DIR -name tblgen` $DT_HOME/local/bin - -# Remove .dir files -cd $DEST_DIR$DEST_ROOT -rm -f bin/.dir etc/llvm/.dir lib/.dir - -# Remove PPC64 fat slices. -cd $DEST_DIR$DEST_ROOT/bin -if [ $MACOSX_DEPLOYMENT_TARGET = "10.4" ]; then - find . -perm 755 -type f \! \( -name '*gccas' -o -name '*gccld' -o -name llvm-config \) \ - -exec lipo -extract ppc -extract i386 {} -output {} \; -elif [ $MACOSX_DEPLOYMENT_TARGET = "10.5" ]; then - find . -perm 755 -type f \! \( -name '*gccas' -o -name '*gccld' -o -name llvm-config \) \ - -exec lipo -extract ppc7400 -extract i386 {} -output {} \; -else - find . -perm 755 -type f \! \( -name '*gccas' -o -name '*gccld' -o -name llvm-config \) \ - -exec lipo -extract ppc7400 -extract i386 -extract x86_64 {} -output {} \; -fi - -cd $DEST_DIR$DEST_ROOT -mkdir -p $DT_HOME/lib -mv lib/libLTO.dylib $DT_HOME/lib/libLTO.dylib -strip -S $DT_HOME/lib/libLTO.dylib -rm -f lib/libLTO.a lib/libLTO.la - -# Compress manpages -MDIR=$DEST_DIR$DEST_ROOT/share/man/man1 -gzip -f $MDIR/* - -################################################################################ -# Create SYM_DIR with information required for debugging. - -# Figure out how many make processes to run. -SYSCTL=`sysctl -n hw.activecpu` - -# hw.activecpu only available in 10.2.6 and later -if [ -z "$SYSCTL" ]; then - SYSCTL=`sysctl -n hw.ncpu` -fi - -# sysctl -n hw.* does not work when invoked via B&I chroot /BuildRoot. Builders -# can default to 2, since even if they are single processor, nothing else is -# running on the machine. -if [ -z "$SYSCTL" ]; then - SYSCTL=2 -fi - -cd $SYM_DIR || exit 1 - -# Clean out SYM_DIR in case -noclean was passed to buildit. -rm -rf * || exit 1 - -# Generate .dSYM files -find $DEST_DIR -perm -0111 -type f \ - \! \( -name '*.la' -o -name gccas -o -name gccld -o -name llvm-config \) \ - -print \ - | xargs -n 1 -P ${SYSCTL} dsymutil - -# Save .dSYM files and .a archives -cd $DEST_DIR || exit 1 -find . \( -path \*.dSYM/\* -or -name \*.a \) -print \ - | cpio -pdml $SYM_DIR || exit 1 - -# Save source files. -mkdir $SYM_DIR/src || exit 1 -cd $DIR || exit 1 -find obj-* -name \*.\[chy\] -o -name \*.cpp -print \ - | cpio -pdml $SYM_DIR/src || exit 1 - -################################################################################ -# Remove debugging information from DEST_DIR. - -find $DEST_DIR -name \*.a -print | xargs ranlib || exit 1 -find $DEST_DIR -name \*.dSYM -print | xargs rm -r || exit 1 -chgrp -h -R wheel $DEST_DIR -chgrp -R wheel $DEST_DIR - -################################################################################ -# Remove tar ball from docs directory - -find $DEST_DIR -name html.tar.gz -exec rm {} \; - -################################################################################ -# w00t! Done! - -exit 0 From isanbard at gmail.com Thu Feb 12 15:40:34 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 12 Feb 2009 21:40:34 -0000 Subject: [llvm-commits] [llvm] r64404 - /llvm/branches/Apple/Dib/utils/buildit/build_llvm Message-ID: <200902122140.n1CLeYgf017321@zion.cs.uiuc.edu> Author: void Date: Thu Feb 12 15:40:34 2009 New Revision: 64404 URL: http://llvm.org/viewvc/llvm-project?rev=64404&view=rev Log: Recommit build_llvm with executable bits enabled. Added: llvm/branches/Apple/Dib/utils/buildit/build_llvm (with props) Added: llvm/branches/Apple/Dib/utils/buildit/build_llvm URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/utils/buildit/build_llvm?rev=64404&view=auto ============================================================================== --- llvm/branches/Apple/Dib/utils/buildit/build_llvm (added) +++ llvm/branches/Apple/Dib/utils/buildit/build_llvm Thu Feb 12 15:40:34 2009 @@ -0,0 +1,270 @@ +#!/bin/sh +# LLVM LOCAL file B&I + +set -x + +# Build LLVM the "Apple way". +# Parameters: + +# The first parameter is a space-separated list of the architectures the +# compilers will run on. For instance, "ppc i386". If the current machine +# isn't in the list, it will (effectively) be added. +# FIXME: HOSTS is not used in this script. Use it or Remove it. +HOSTS="$1" + +# The second parameter is a space-separated list of the architectures the +# compilers will generate code for. If the current machine isn't in the list, a +# compiler for it will get built anyway, but won't be installed. +TARGETS="$2" + +# The third parameter is the path to the compiler sources. There should be a +# shell script named 'configure' in this directory. This script makes a copy... +ORIG_SRC_DIR="$3" + +# The fourth parameter is the location where the LLVM will be installed. You can +# move it once it's built, so this mostly controls the layout of $DEST_DIR. +DEST_ROOT="$4" + +# The fifth parameter is the place where the compiler will be copied once it's +# built. +DEST_DIR="$5" + +# The sixth parameter is a directory in which to place information (like +# unstripped executables and generated source files) helpful in debugging the +# resulting compiler. +SYM_DIR="$6" + +# The seventh parameter is a yes/no that indicates whether assertions should be +# enabled in the LLVM libs/tools. +LLVM_ASSERTIONS="$7" + +# The eighth parameter is a yes/no that indicates whether this is an optimized +# build. +LLVM_OPTIMIZED="$8" + +# The nineth parameter is the version number of the submission, e.g. 1007. +LLVM_SUBMIT_VERSION="$9" + +# The tenth parameter is the subversion number of the submission, e.g. 03. +LLVM_SUBMIT_SUBVERSION="${10}" + +# The current working directory is where the build will happen. It may already +# contain a partial result of an interrupted build, in which case this script +# will continue where it left off. +DIR=`pwd` + +DARWIN_VERS=`uname -r | sed 's/\..*//'` +echo DARWIN_VERS = $DARWIN_VERS + +# If the user has CC set in their environment unset it now +unset CC + +DT_HOME=$DEST_DIR/Developer/usr +DEST_ROOT="/Developer$DEST_ROOT" +if [ "x$DEVELOPER_BIN" != "x" ]; then + DT_HOME=$DEST_DIR/$DEVELOPER_DIR/usr + DEST_ROOT="/$DEVELOPER_DIR$DEST_ROOT" +fi + +################################################################################ +# Run the build. + +# Create the source tree we'll actually use to build, deleting +# tcl since it doesn't actually build properly in a cross environment +# and we don't really need it. +SRC_DIR=$DIR/src +rm -rf $SRC_DIR || exit 1 +mkdir $SRC_DIR || exit 1 +ln -s $ORIG_SRC_DIR/* $SRC_DIR/ || exit 1 + +# Build the LLVM tree universal. +mkdir -p $DIR/obj-llvm || exit 1 +cd $DIR/obj-llvm || exit 1 + +if [ \! -f Makefile.config ]; then + $SRC_DIR/configure --prefix=$DT_HOME/local \ + --enable-targets=arm,x86,powerpc,cbe \ + --enable-assertions=$LLVM_ASSERTIONS \ + --enable-optimized=$LLVM_OPTIMIZED \ + || exit 1 +fi + +SUBVERSION=`echo $RC_ProjectSourceVersion | sed -e 's/[^.]*\.\([0-9]*\).*/\1/'` + +if [ "x$SUBVERSION" != "x$RC_ProjectSourceVersion" ]; then + LLVM_SUBMIT_SUBVERSION=`printf "%02d" $SUBVERSION` + RC_ProjectSourceVersion=`echo $RC_ProjectSourceVersion | sed -e 's/\..*//'` + LLVM_SUBMIT_VERSION=$RC_ProjectSourceVersion +fi + +if [ "x$LLVM_SUBMIT_SUBVERSION" = "x00" -o "x$LLVM_SUBMIT_SUBVERSION" = "x0" ]; then + LLVM_VERSION="$LLVM_SUBMIT_VERSION" +else + LLVM_VERSION="$LLVM_SUBMIT_VERSION-$LLVM_SUBMIT_SUBVERSION" +fi + +GCC_VER=`cc --version 2>/dev/null | sed 1q` + +if echo "$GCC_VER" | grep GCC > /dev/null; then + GCC_VER=`echo $GCC_VER | sed -e 's/.*(GCC) \([0-9.][0-9.]*\).*/\1/'` + MAJ_VER=`echo $GCC_VER | sed 's/\..*//'` + MIN_VER=`echo $GCC_VER | sed 's/[^.]*\.\([0-9]*\).*/\1/'` +fi + +JOBS_FLAG="" + +# Note: If compiling with GCC 4.0, don't pass the -jN flag. Building universal +# already has parallelism and we don't want to make the builders hit swap by +# firing off too many gccs at the same time. +if [ "x$MAJ_VER" != "x4" -o "x$MIN_VER" != "x0" ]; then + # Figure out how many make processes to run. + SYSCTL=`sysctl -n hw.activecpu` + + # hw.activecpu only available in 10.2.6 and later + if [ -z "$SYSCTL" ]; then + SYSCTL=`sysctl -n hw.ncpu` + fi + + # sysctl -n hw.* does not work when invoked via B&I chroot /BuildRoot. + # Builders can default to 2, since even if they are single processor, + # nothing else is running on the machine. + if [ -z "$SYSCTL" ]; then + SYSCTL=2 + fi + + JOBS_FLAG="-j $SYSCTL" +fi + +make $JOBS_FLAG $OPTIMIZE_OPTS UNIVERSAL=1 UNIVERSAL_ARCH="$TARGETS" \ + LLVM_SUBMIT_VERSION=$LLVM_SUBMIT_VERSION \ + LLVM_SUBMIT_SUBVERSION=$LLVM_SUBMIT_SUBVERSION \ + CXXFLAGS="-DLLVM_VERSION_INFO='\" Apple Build #$LLVM_VERSION\"'" \ + VERBOSE=1 + +if ! test $? == 0 ; then + echo "error: LLVM 'make' failed!" + exit 1 +fi + +################################################################################ +# Construct the actual destination root, by copying stuff from $DIR/dst-* to +# $DEST_DIR, with occasional 'lipo' commands. + +cd $DEST_DIR || exit 1 + +# Clean out DEST_DIR in case -noclean was passed to buildit. +rm -rf * || exit 1 + +cd $DIR/obj-llvm || exit 1 + +# Install the tree into the destination directory. +make $LOCAL_MAKEFLAGS $OPTIMIZE_OPTS UNIVERSAL=1 UNIVERSAL_ARCH="$TARGETS" \ + LLVM_SUBMIT_VERSION=$LLVM_SUBMIT_VERSION \ + LLVM_SUBMIT_SUBVERSION=$LLVM_SUBMIT_SUBVERSION \ + OPTIMIZE_OPTION='-O2' VERBOSE=1 install + +if ! test $? == 0 ; then + echo "error: LLVM 'make install' failed!" + exit 1 +fi + +# Install Version.h +RC_ProjectSourceSubversion=`printf "%d" $LLVM_SUBMIT_SUBVERSION` +echo "#define LLVM_VERSION ${RC_ProjectSourceVersion}" > $DEST_DIR$DEST_ROOT/include/llvm/Version.h +echo "#define LLVM_MINOR_VERSION ${RC_ProjectSourceSubversion}" >> $DEST_DIR$DEST_ROOT/include/llvm/Version.h + +if [ "x$LLVM_DEBUG" != "x1" ]; then + # Strip local symbols from llvm libraries. + strip -S $DEST_DIR$DEST_ROOT/lib/*.[oa] + for f in `ls $DEST_DIR$DEST_ROOT/lib/*.so`; do + strip -Sx $f + done +fi + +# Copy over the tblgen utility. +cp `find $DIR -name tblgen` $DT_HOME/local/bin + +# Remove .dir files +cd $DEST_DIR$DEST_ROOT +rm -f bin/.dir etc/llvm/.dir lib/.dir + +# Remove PPC64 fat slices. +cd $DEST_DIR$DEST_ROOT/bin +if [ $MACOSX_DEPLOYMENT_TARGET = "10.4" ]; then + find . -perm 755 -type f \! \( -name '*gccas' -o -name '*gccld' -o -name llvm-config \) \ + -exec lipo -extract ppc -extract i386 {} -output {} \; +elif [ $MACOSX_DEPLOYMENT_TARGET = "10.5" ]; then + find . -perm 755 -type f \! \( -name '*gccas' -o -name '*gccld' -o -name llvm-config \) \ + -exec lipo -extract ppc7400 -extract i386 {} -output {} \; +else + find . -perm 755 -type f \! \( -name '*gccas' -o -name '*gccld' -o -name llvm-config \) \ + -exec lipo -extract ppc7400 -extract i386 -extract x86_64 {} -output {} \; +fi + +cd $DEST_DIR$DEST_ROOT +mkdir -p $DT_HOME/lib +mv lib/libLTO.dylib $DT_HOME/lib/libLTO.dylib +strip -S $DT_HOME/lib/libLTO.dylib +rm -f lib/libLTO.a lib/libLTO.la + +# Compress manpages +MDIR=$DEST_DIR$DEST_ROOT/share/man/man1 +gzip -f $MDIR/* + +################################################################################ +# Create SYM_DIR with information required for debugging. + +# Figure out how many make processes to run. +SYSCTL=`sysctl -n hw.activecpu` + +# hw.activecpu only available in 10.2.6 and later +if [ -z "$SYSCTL" ]; then + SYSCTL=`sysctl -n hw.ncpu` +fi + +# sysctl -n hw.* does not work when invoked via B&I chroot /BuildRoot. Builders +# can default to 2, since even if they are single processor, nothing else is +# running on the machine. +if [ -z "$SYSCTL" ]; then + SYSCTL=2 +fi + +cd $SYM_DIR || exit 1 + +# Clean out SYM_DIR in case -noclean was passed to buildit. +rm -rf * || exit 1 + +# Generate .dSYM files +find $DEST_DIR -perm -0111 -type f \ + \! \( -name '*.la' -o -name gccas -o -name gccld -o -name llvm-config \) \ + -print \ + | xargs -n 1 -P ${SYSCTL} dsymutil + +# Save .dSYM files and .a archives +cd $DEST_DIR || exit 1 +find . \( -path \*.dSYM/\* -or -name \*.a \) -print \ + | cpio -pdml $SYM_DIR || exit 1 + +# Save source files. +mkdir $SYM_DIR/src || exit 1 +cd $DIR || exit 1 +find obj-* -name \*.\[chy\] -o -name \*.cpp -print \ + | cpio -pdml $SYM_DIR/src || exit 1 + +################################################################################ +# Remove debugging information from DEST_DIR. + +find $DEST_DIR -name \*.a -print | xargs ranlib || exit 1 +find $DEST_DIR -name \*.dSYM -print | xargs rm -r || exit 1 +chgrp -h -R wheel $DEST_DIR +chgrp -R wheel $DEST_DIR + +################################################################################ +# Remove tar ball from docs directory + +find $DEST_DIR -name html.tar.gz -exec rm {} \; + +################################################################################ +# w00t! Done! + +exit 0 Propchange: llvm/branches/Apple/Dib/utils/buildit/build_llvm ------------------------------------------------------------------------------ svn:executable = * From gohman at apple.com Thu Feb 12 16:05:37 2009 From: gohman at apple.com (Dan Gohman) Date: Thu, 12 Feb 2009 14:05:37 -0800 Subject: [llvm-commits] [llvm] r64369 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll test/CodeGen/X86/2008-08-05-SpillerBug.ll In-Reply-To: <200902120859.n1C8xprn017627@zion.cs.uiuc.edu> References: <200902120859.n1C8xprn017627@zion.cs.uiuc.edu> Message-ID: On Feb 12, 2009, at 12:59 AM, Evan Cheng wrote: > Author: evancheng > Date: Thu Feb 12 02:59:45 2009 > New Revision: 64369 > > URL: http://llvm.org/viewvc/llvm-project?rev=64369&view=rev > Log: > Replace one of burr scheduling heuristic with something more > sensible. Now calcMaxScratches simply compute the number of true > data dependencies. This actually improve a couple of tests in > dejagnu suite as many tests in llvm nightly test suite. > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp > llvm/trunk/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll > llvm/trunk/test/CodeGen/X86/2008-08-05-SpillerBug.ll > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=64369&r1=64368&r2=64369&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp > (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu > Feb 12 02:59:45 2009 > @@ -916,7 +916,7 @@ > if (PredSethiUllman > SethiUllmanNumber) { > SethiUllmanNumber = PredSethiUllman; > Extra = 0; > - } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl()) > + } else if (PredSethiUllman == SethiUllmanNumber) > ++Extra; > } Hi Evan, this change doesn't seem to be related to the other changes. What is it for? Control edges don't correspond to registers, so why should they be counted in the sethi-ullman number? Dan From isanbard at gmail.com Thu Feb 12 16:12:13 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 12 Feb 2009 22:12:13 -0000 Subject: [llvm-commits] [llvm] r64405 - in /llvm/branches/Apple/Dib: lib/CodeGen/ScheduleDAGPrinter.cpp lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp lib/CodeGen/VirtRegMap.cpp test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll test/CodeGen/X86/2008-02-22-ReMatBug.ll test/CodeGen/X86/2008-08-05-SpillerBug.ll test/CodeGen/X86/pmul.ll test/CodeGen/X86/pr3495-2.ll test/CodeGen/X86/pr3495.ll test/CodeGen/X86/sse_reload_fold.ll Message-ID: <200902122212.n1CMCDsS018673@zion.cs.uiuc.edu> Author: void Date: Thu Feb 12 16:12:12 2009 New Revision: 64405 URL: http://llvm.org/viewvc/llvm-project?rev=64405&view=rev Log: Pulled revs 64184 64210 64298 64319 64327 64328 64339 64340 64369 64372 64373 into Dib: --- Merging (from foreign repository) r64184 into '.': U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp --- Merging (from foreign repository) r64210 into '.': A test/CodeGen/X86/pr3457.ll Skipped 'test/CodeGen/X86/pr3495.ll' --- Merging (from foreign repository) r64298 into '.': U lib/CodeGen/VirtRegMap.cpp --- Merging (from foreign repository) r64319 into '.': U lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp --- Merging (from foreign repository) r64327 into '.': U test/CodeGen/X86/2008-08-05-SpillerBug.ll U test/CodeGen/X86/pmul.ll U test/CodeGen/X86/sse_reload_fold.ll U test/CodeGen/X86/2008-02-22-ReMatBug.ll G lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp --- Merging (from foreign repository) r64328 into '.': G lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp --- Merging (from foreign repository) r64339 into '.': A test/CodeGen/X86/pr3495-2.ll G lib/CodeGen/VirtRegMap.cpp --- Merging (from foreign repository) r64340 into '.': U lib/CodeGen/ScheduleDAGPrinter.cpp --- Merging (from foreign repository) r64369 into '.': U test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll G test/CodeGen/X86/2008-08-05-SpillerBug.ll G lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp --- Merging (from foreign repository) r64372 into '.': G lib/CodeGen/VirtRegMap.cpp --- Merging (from foreign repository) r64373 into '.': G lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Added: llvm/branches/Apple/Dib/test/CodeGen/X86/pr3495-2.ll llvm/branches/Apple/Dib/test/CodeGen/X86/pr3495.ll Modified: llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGPrinter.cpp llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp llvm/branches/Apple/Dib/lib/CodeGen/VirtRegMap.cpp llvm/branches/Apple/Dib/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll llvm/branches/Apple/Dib/test/CodeGen/X86/2008-02-22-ReMatBug.ll llvm/branches/Apple/Dib/test/CodeGen/X86/2008-08-05-SpillerBug.ll llvm/branches/Apple/Dib/test/CodeGen/X86/pmul.ll llvm/branches/Apple/Dib/test/CodeGen/X86/sse_reload_fold.ll Modified: llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGPrinter.cpp?rev=64405&r1=64404&r2=64405&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGPrinter.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGPrinter.cpp Thu Feb 12 16:12:12 2009 @@ -83,9 +83,13 @@ void ScheduleDAG::viewGraph() { // This code is only for debugging! #ifndef NDEBUG - ViewGraph(this, "dag." + MF.getFunction()->getName(), - "Scheduling-Units Graph for " + MF.getFunction()->getName() + ':' + - BB->getBasicBlock()->getName()); + if (BB->getBasicBlock()) + ViewGraph(this, "dag." + MF.getFunction()->getName(), + "Scheduling-Units Graph for " + MF.getFunction()->getName() + ':' + + BB->getBasicBlock()->getName()); + else + ViewGraph(this, "dag." + MF.getFunction()->getName(), + "Scheduling-Units Graph for " + MF.getFunction()->getName()); #else cerr << "ScheduleDAG::viewGraph is only available in debug builds on " << "systems with Graphviz or gv!\n"; Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=64405&r1=64404&r2=64405&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu Feb 12 16:12:12 2009 @@ -879,12 +879,6 @@ }; } // end anonymous namespace -static inline bool isCopyFromLiveIn(const SUnit *SU) { - SDNode *N = SU->getNode(); - return N && N->getOpcode() == ISD::CopyFromReg && - N->getOperand(N->getNumOperands()-1).getValueType() != MVT::Flag; -} - /// CalcNodeSethiUllmanNumber - Compute Sethi Ullman number. /// Smaller number is the higher priority. static unsigned @@ -902,7 +896,7 @@ if (PredSethiUllman > SethiUllmanNumber) { SethiUllmanNumber = PredSethiUllman; Extra = 0; - } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl()) + } else if (PredSethiUllman == SethiUllmanNumber) ++Extra; } @@ -966,11 +960,6 @@ unsigned getNodePriority(const SUnit *SU) const { assert(SU->NodeNum < SethiUllmanNumbers.size()); unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0; - if (Opc == ISD::CopyFromReg && !isCopyFromLiveIn(SU)) - // CopyFromReg should be close to its def because it restricts - // allocation choices. But if it is a livein then perhaps we want it - // closer to its uses so it can be coalesced. - return 0xffff; if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) // CopyToReg should be close to its uses to facilitate coalescing and // avoid spilling. @@ -980,15 +969,16 @@ // EXTRACT_SUBREG / INSERT_SUBREG should be close to its use to // facilitate coalescing. return 0; - if (SU->NumSuccs == 0) - // If SU does not have a use, i.e. it doesn't produce a value that would - // be consumed (e.g. store), then it terminates a chain of computation. - // Give it a large SethiUllman number so it will be scheduled right - // before its predecessors that it doesn't lengthen their live ranges. + if (SU->NumSuccs == 0 && SU->NumPreds != 0) + // If SU does not have a register use, i.e. it doesn't produce a value + // that would be consumed (e.g. store), then it terminates a chain of + // computation. Give it a large SethiUllman number so it will be + // scheduled right before its predecessors that it doesn't lengthen + // their live ranges. return 0xffff; - if (SU->NumPreds == 0) - // If SU does not have a def, schedule it close to its uses because it - // does not lengthen any live ranges. + if (SU->NumPreds == 0 && SU->NumSuccs != 0) + // If SU does not have a register def, schedule it close to its uses + // because it does not lengthen any live ranges. return 0; return SethiUllmanNumbers[SU->NodeNum]; } @@ -1060,23 +1050,13 @@ } /// calcMaxScratches - Returns an cost estimate of the worse case requirement -/// for scratch registers. Live-in operands and live-out results don't count -/// since they are "fixed". +/// for scratch registers, i.e. number of data dependencies. static unsigned calcMaxScratches(const SUnit *SU) { unsigned Scratches = 0; for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) { if (I->isCtrl()) continue; // ignore chain preds - if (!I->getSUnit()->getNode() || - I->getSUnit()->getNode()->getOpcode() != ISD::CopyFromReg) - Scratches++; - } - for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); - I != E; ++I) { - if (I->isCtrl()) continue; // ignore chain succs - if (!I->getSUnit()->getNode() || - I->getSUnit()->getNode()->getOpcode() != ISD::CopyToReg) - Scratches += 10; + Scratches++; } return Scratches; } @@ -1110,10 +1090,7 @@ if (LDist != RDist) return LDist < RDist; - // Intuitively, it's good to push down instructions whose results are - // liveout so their long live ranges won't conflict with other values - // which are needed inside the BB. Further prioritize liveout instructions - // by the number of operands which are calculated within the BB. + // How many registers becomes live when the node is scheduled. unsigned LScratch = calcMaxScratches(left); unsigned RScratch = calcMaxScratches(right); if (LScratch != RScratch) @@ -1242,8 +1219,8 @@ if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI)) continue; } - // Don't constraint extract_subreg / insert_subreg these may be - // coalesced away. We don't them close to their uses. + // Don't constrain extract_subreg / insert_subreg; these may be + // coalesced away. We want them close to their uses. unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode(); if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG || SuccOpc == TargetInstrInfo::INSERT_SUBREG) Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp?rev=64405&r1=64404&r2=64405&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp Thu Feb 12 16:12:12 2009 @@ -125,10 +125,11 @@ } else { // Create the reg, emit the copy. VRBase = MRI.createVirtualRegister(DstRC); - bool Emitted = - TII->copyRegToReg(*BB, End, VRBase, SrcReg, DstRC, SrcRC); - Emitted = Emitted; // Silence compiler warning. - assert(Emitted && "Unable to issue a copy instruction!"); + bool Emitted = TII->copyRegToReg(*BB, End, VRBase, SrcReg, DstRC, SrcRC); + if (!Emitted) { + cerr << "Unable to issue a copy instruction!\n"; + abort(); + } } SDValue Op(Node, ResNo); @@ -529,7 +530,11 @@ else DstTRC = TRI->getPhysicalRegisterRegClass(DestReg, Node->getOperand(1).getValueType()); - TII->copyRegToReg(*BB, End, DestReg, SrcReg, DstTRC, SrcTRC); + bool Emitted = TII->copyRegToReg(*BB, End, DestReg, SrcReg, DstTRC, SrcTRC); + if (!Emitted) { + cerr << "Unable to issue a copy instruction!\n"; + abort(); + } break; } case ISD::CopyFromReg: { Modified: llvm/branches/Apple/Dib/lib/CodeGen/VirtRegMap.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/VirtRegMap.cpp?rev=64405&r1=64404&r2=64405&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/VirtRegMap.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/VirtRegMap.cpp Thu Feb 12 16:12:12 2009 @@ -26,10 +26,11 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Support/CommandLine.h" -#include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" +#include "llvm/Support/Debug.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/DepthFirstIterator.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallSet.h" @@ -47,6 +48,8 @@ STATISTIC(NumDCE , "Number of copies elided"); STATISTIC(NumDSS , "Number of dead spill slots removed"); STATISTIC(NumCommutes, "Number of instructions commuted"); +STATISTIC(NumOmitted , "Number of reloads omited"); +STATISTIC(NumCopified, "Number of available reloads turned into copies"); namespace { enum SpillerName { simple, local }; @@ -308,79 +311,6 @@ // Local Spiller Implementation //===----------------------------------------------------------------------===// -namespace { - class AvailableSpills; - - /// LocalSpiller - This spiller does a simple pass over the machine basic - /// block to attempt to keep spills in registers as much as possible for - /// blocks that have low register pressure (the vreg may be spilled due to - /// register pressure in other blocks). - class VISIBILITY_HIDDEN LocalSpiller : public Spiller { - MachineRegisterInfo *RegInfo; - const TargetRegisterInfo *TRI; - const TargetInstrInfo *TII; - DenseMap DistanceMap; - public: - bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { - RegInfo = &MF.getRegInfo(); - TRI = MF.getTarget().getRegisterInfo(); - TII = MF.getTarget().getInstrInfo(); - DOUT << "\n**** Local spiller rewriting function '" - << MF.getFunction()->getName() << "':\n"; - DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)" - " ****\n"; - DEBUG(MF.dump()); - - for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); - MBB != E; ++MBB) - RewriteMBB(*MBB, VRM); - - // Mark unused spill slots. - MachineFrameInfo *MFI = MF.getFrameInfo(); - int SS = VRM.getLowSpillSlot(); - if (SS != VirtRegMap::NO_STACK_SLOT) - for (int e = VRM.getHighSpillSlot(); SS <= e; ++SS) - if (!VRM.isSpillSlotUsed(SS)) { - MFI->RemoveStackObject(SS); - ++NumDSS; - } - - DOUT << "**** Post Machine Instrs ****\n"; - DEBUG(MF.dump()); - - return true; - } - private: - void TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist, - unsigned Reg, BitVector &RegKills, - std::vector &KillOps); - bool PrepForUnfoldOpti(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MII, - std::vector &MaybeDeadStores, - AvailableSpills &Spills, BitVector &RegKills, - std::vector &KillOps, - VirtRegMap &VRM); - bool CommuteToFoldReload(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MII, - unsigned VirtReg, unsigned SrcReg, int SS, - BitVector &RegKills, - std::vector &KillOps, - const TargetRegisterInfo *TRI, - VirtRegMap &VRM); - void SpillRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MII, - int Idx, unsigned PhysReg, int StackSlot, - const TargetRegisterClass *RC, - bool isAvailable, MachineInstr *&LastStore, - AvailableSpills &Spills, - SmallSet &ReMatDefs, - BitVector &RegKills, - std::vector &KillOps, - VirtRegMap &VRM); - void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM); - }; -} - /// AvailableSpills - As the local spiller is scanning and rewriting an MBB from /// top down, keep track of which spills slots or remat are available in each /// register. @@ -415,6 +345,12 @@ AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii) : TRI(tri), TII(tii) { } + + /// clear - Reset the state. + void clear() { + SpillSlotsOrReMatsAvailable.clear(); + PhysRegsAvailable.clear(); + } const TargetRegisterInfo *getRegInfo() const { return TRI; } @@ -433,8 +369,7 @@ /// addAvailable - Mark that the specified stack slot / remat is available in /// the specified physreg. If CanClobber is true, the physreg can be modified /// at any time without changing the semantics of the program. - void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg, - bool CanClobber = true) { + void addAvailable(int SlotOrReMat, unsigned Reg, bool CanClobber = true) { // If this stack slot is thought to be available in some other physreg, // remove its record. ModifyStackSlotOrReMat(SlotOrReMat); @@ -472,6 +407,8 @@ /// slot changes. This removes information about which register the previous /// value for this slot lives in (as the previous value is dead now). void ModifyStackSlotOrReMat(int SlotOrReMat); + + void AddAvailableRegsToLiveIn(MachineBasicBlock &MBB); }; } @@ -551,7 +488,142 @@ PhysRegsAvailable.erase(I); } +/// AddAvailableRegsToLiveIn - Availability information is being kept coming +/// into the specified MBB. Add available physical registers as live-in's +/// so register scavenger and post-allocation scheduler are happy. +void AvailableSpills::AddAvailableRegsToLiveIn(MachineBasicBlock &MBB) { + for (std::multimap::iterator + I = PhysRegsAvailable.begin(), E = PhysRegsAvailable.end(); + I != E; ++I) { + unsigned Reg = (*I).first; + if (!MBB.isLiveIn(Reg)) + MBB.addLiveIn(Reg); + } +} +/// findSinglePredSuccessor - Return via reference a vector of machine basic +/// blocks each of which is a successor of the specified BB and has no other +/// predecessor. +static void findSinglePredSuccessor(MachineBasicBlock *MBB, + SmallVectorImpl &Succs) { + for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), + SE = MBB->succ_end(); SI != SE; ++SI) { + MachineBasicBlock *SuccMBB = *SI; + if (SuccMBB->pred_size() == 1) + Succs.push_back(SuccMBB); + } +} + +namespace { + /// LocalSpiller - This spiller does a simple pass over the machine basic + /// block to attempt to keep spills in registers as much as possible for + /// blocks that have low register pressure (the vreg may be spilled due to + /// register pressure in other blocks). + class VISIBILITY_HIDDEN LocalSpiller : public Spiller { + MachineRegisterInfo *RegInfo; + const TargetRegisterInfo *TRI; + const TargetInstrInfo *TII; + DenseMap DistanceMap; + public: + bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { + RegInfo = &MF.getRegInfo(); + TRI = MF.getTarget().getRegisterInfo(); + TII = MF.getTarget().getInstrInfo(); + DOUT << "\n**** Local spiller rewriting function '" + << MF.getFunction()->getName() << "':\n"; + DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)" + " ****\n"; + DEBUG(MF.dump()); + + // Spills - Keep track of which spilled values are available in physregs + // so that we can choose to reuse the physregs instead of emitting + // reloads. This is usually refreshed per basic block. + AvailableSpills Spills(TRI, TII); + + // SingleEntrySuccs - Successor blocks which have a single predecessor. + SmallVector SinglePredSuccs; + SmallPtrSet EarlyVisited; + + // Traverse the basic blocks depth first. + MachineBasicBlock *Entry = MF.begin(); + SmallPtrSet Visited; + for (df_ext_iterator > + DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited); + DFI != E; ++DFI) { + MachineBasicBlock *MBB = *DFI; + if (!EarlyVisited.count(MBB)) + RewriteMBB(*MBB, VRM, Spills); + + // If this MBB is the only predecessor of a successor. Keep the + // availability information and visit it next. + do { + // Keep visiting single predecessor successor as long as possible. + SinglePredSuccs.clear(); + findSinglePredSuccessor(MBB, SinglePredSuccs); + if (SinglePredSuccs.empty()) + MBB = 0; + else { + // FIXME: More than one successors, each of which has MBB has + // the only predecessor. + MBB = SinglePredSuccs[0]; + if (!Visited.count(MBB) && EarlyVisited.insert(MBB)) { + Spills.AddAvailableRegsToLiveIn(*MBB); + RewriteMBB(*MBB, VRM, Spills); + } + } + } while (MBB); + + // Clear the availability info. + Spills.clear(); + } + + DOUT << "**** Post Machine Instrs ****\n"; + DEBUG(MF.dump()); + + // Mark unused spill slots. + MachineFrameInfo *MFI = MF.getFrameInfo(); + int SS = VRM.getLowSpillSlot(); + if (SS != VirtRegMap::NO_STACK_SLOT) + for (int e = VRM.getHighSpillSlot(); SS <= e; ++SS) + if (!VRM.isSpillSlotUsed(SS)) { + MFI->RemoveStackObject(SS); + ++NumDSS; + } + + return true; + } + private: + void TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist, + unsigned Reg, BitVector &RegKills, + std::vector &KillOps); + bool PrepForUnfoldOpti(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MII, + std::vector &MaybeDeadStores, + AvailableSpills &Spills, BitVector &RegKills, + std::vector &KillOps, + VirtRegMap &VRM); + bool CommuteToFoldReload(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MII, + unsigned VirtReg, unsigned SrcReg, int SS, + BitVector &RegKills, + std::vector &KillOps, + const TargetRegisterInfo *TRI, + VirtRegMap &VRM); + void SpillRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MII, + int Idx, unsigned PhysReg, int StackSlot, + const TargetRegisterClass *RC, + bool isAvailable, MachineInstr *&LastStore, + AvailableSpills &Spills, + SmallSet &ReMatDefs, + BitVector &RegKills, + std::vector &KillOps, + VirtRegMap &VRM); + void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM, + AvailableSpills &Spills); + }; +} /// InvalidateKills - MI is going to be deleted. If any of its operands are /// marked kill, then invalidate the information. @@ -843,7 +915,7 @@ unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) : NewPhysReg; MI->getOperand(NewOp.Operand).setReg(RReg); - Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg); + Spills.addAvailable(NewOp.StackSlotOrReMat, NewPhysReg); --MII; UpdateKills(*MII, RegKills, KillOps, TRI); DOUT << '\t' << *MII; @@ -1152,7 +1224,7 @@ // in PhysReg. Spills.ModifyStackSlotOrReMat(StackSlot); Spills.ClobberPhysReg(PhysReg); - Spills.addAvailable(StackSlot, LastStore, PhysReg, isAvailable); + Spills.addAvailable(StackSlot, PhysReg, isAvailable); ++NumStores; } @@ -1201,15 +1273,13 @@ /// rewriteMBB - Keep track of which spills are available even after the /// register allocator is done with them. If possible, avid reloading vregs. -void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { - DOUT << MBB.getBasicBlock()->getName() << ":\n"; +void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM, + AvailableSpills &Spills) { + DOUT << "\n**** Local spiller rewriting MBB '" + << MBB.getBasicBlock()->getName() << ":\n"; MachineFunction &MF = *MBB.getParent(); - // Spills - Keep track of which spilled values are available in physregs so - // that we can choose to reuse the physregs instead of emitting reloads. - AvailableSpills Spills(TRI, TII); - // MaybeDeadStores - When we need to write a value back into a stack slot, // keep track of the inserted store. If the stack slot value is never read // (because the value was used from some available register, for example), and @@ -1277,18 +1347,80 @@ continue; // Split interval spilled again. unsigned Phys = VRM.getPhys(VirtReg); RegInfo->setPhysRegUsed(Phys); + + // Check if the value being restored if available. If so, it must be + // from a predecessor BB that fallthrough into this BB. We do not + // expect: + // BB1: + // r1 = load fi#1 + // ... + // = r1 + // ... # r1 not clobbered + // ... + // = load fi#1 + bool DoReMat = VRM.isReMaterialized(VirtReg); + int SSorRMId = DoReMat + ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg); + unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId); + if (InReg == Phys) { + // If the value is already available in the expected register, save + // a reload / remat. + if (SSorRMId) + DOUT << "Reusing RM#" << SSorRMId-VirtRegMap::MAX_STACK_SLOT-1; + else + DOUT << "Reusing SS#" << SSorRMId; + DOUT << " from physreg " + << TRI->getName(InReg) << " for vreg" + << VirtReg <<" instead of reloading into physreg " + << TRI->getName(Phys) << "\n"; + ++NumOmitted; + continue; + } else if (InReg && InReg != Phys) { + if (SSorRMId) + DOUT << "Reusing RM#" << SSorRMId-VirtRegMap::MAX_STACK_SLOT-1; + else + DOUT << "Reusing SS#" << SSorRMId; + DOUT << " from physreg " + << TRI->getName(InReg) << " for vreg" + << VirtReg <<" by copying it into physreg " + << TRI->getName(Phys) << "\n"; + + // If the reloaded / remat value is available in another register, + // copy it to the desired register. + const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); + TII->copyRegToReg(MBB, &MI, Phys, InReg, RC, RC); + + // This invalidates Phys. + Spills.ClobberPhysReg(Phys); + // Remember it's available. + Spills.addAvailable(SSorRMId, Phys); + + // Mark is killed. + MachineInstr *CopyMI = prior(MII); + MachineOperand *KillOpnd = CopyMI->findRegisterUseOperand(InReg); + KillOpnd->setIsKill(); + UpdateKills(*CopyMI, RegKills, KillOps, TRI); + + DOUT << '\t' << *CopyMI; + ++NumCopified; + continue; + } + if (VRM.isReMaterialized(VirtReg)) { ReMaterialize(MBB, MII, Phys, VirtReg, TII, TRI, VRM); } else { const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); - int SS = VRM.getStackSlot(VirtReg); - TII->loadRegFromStackSlot(MBB, &MI, Phys, SS, RC); + TII->loadRegFromStackSlot(MBB, &MI, Phys, SSorRMId, RC); MachineInstr *LoadMI = prior(MII); - VRM.addSpillSlotUse(SS, LoadMI); + VRM.addSpillSlotUse(SSorRMId, LoadMI); ++NumLoads; } + // This invalidates Phys. Spills.ClobberPhysReg(Phys); + // Remember it's available. + Spills.addAvailable(SSorRMId, Phys); + UpdateKills(*prior(MII), RegKills, KillOps, TRI); DOUT << '\t' << *prior(MII); } @@ -1510,7 +1642,7 @@ // This invalidates DesignatedReg. Spills.ClobberPhysReg(DesignatedReg); - Spills.addAvailable(ReuseSlot, &MI, DesignatedReg); + Spills.addAvailable(ReuseSlot, DesignatedReg); unsigned RReg = SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg; MI.getOperand(i).setReg(RReg); @@ -1548,7 +1680,7 @@ // Any stores to this stack slot are not dead anymore. if (!DoReMat) MaybeDeadStores[SSorRMId] = NULL; - Spills.addAvailable(SSorRMId, &MI, PhysReg); + Spills.addAvailable(SSorRMId, PhysReg); // Assumes this is the last use. IsKill will be unset if reg is reused // unless it's a two-address operand. if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1) @@ -1738,7 +1870,7 @@ // If the stack slot value was previously available in some other // register, change it now. Otherwise, make the register // available in PhysReg. - Spills.addAvailable(StackSlot, &MI, SrcReg, false/*!clobber*/); + Spills.addAvailable(StackSlot, SrcReg, false/*!clobber*/); } } } @@ -1788,7 +1920,7 @@ // If it is a folded reference, then it's not safe to clobber. bool Folded = FoldedSS.count(FrameIdx); // Otherwise, if it wasn't available, remember that it is now! - Spills.addAvailable(FrameIdx, &MI, DestReg, !Folded); + Spills.addAvailable(FrameIdx, DestReg, !Folded); goto ProcessNextInst; } @@ -1863,6 +1995,7 @@ } MII = NextMII; } + } llvm::Spiller* llvm::createSpiller() { Modified: llvm/branches/Apple/Dib/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll?rev=64405&r1=64404&r2=64405&view=diff ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll (original) +++ llvm/branches/Apple/Dib/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll Thu Feb 12 16:12:12 2009 @@ -1,4 +1,5 @@ ; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin9 +; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin9 -stats |& grep asm-printer | grep 186 %"struct.Adv5::Ekin<3>" = type <{ i8 }> %"struct.Adv5::X::Energyflux<3>" = type { double } Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/2008-02-22-ReMatBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/2008-02-22-ReMatBug.ll?rev=64405&r1=64404&r2=64405&view=diff ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/X86/2008-02-22-ReMatBug.ll (original) +++ llvm/branches/Apple/Dib/test/CodeGen/X86/2008-02-22-ReMatBug.ll Thu Feb 12 16:12:12 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of re-materialization} | grep 4 +; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of re-materialization} | grep 3 ; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of dead spill slots removed} ; rdar://5761454 Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/2008-08-05-SpillerBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/2008-08-05-SpillerBug.ll?rev=64405&r1=64404&r2=64405&view=diff ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/X86/2008-08-05-SpillerBug.ll (original) +++ llvm/branches/Apple/Dib/test/CodeGen/X86/2008-08-05-SpillerBug.ll Thu Feb 12 16:12:12 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -disable-fp-elim -stats -info-output-file - | not grep {Number of dead stores elided} +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -disable-fp-elim -stats |& grep asm-printer | grep 57 ; PR2568 @g_3 = external global i16 ; [#uses=1] Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/pmul.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/pmul.ll?rev=64405&r1=64404&r2=64405&view=diff ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/X86/pmul.ll (original) +++ llvm/branches/Apple/Dib/test/CodeGen/X86/pmul.ll Thu Feb 12 16:12:12 2009 @@ -1,6 +1,6 @@ ; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 -stack-alignment=16 > %t ; RUN: grep pmul %t | count 12 -; RUN: grep mov %t | count 15 +; RUN: grep mov %t | count 12 define <4 x i32> @a(<4 x i32> %i) nounwind { %A = mul <4 x i32> %i, < i32 117, i32 117, i32 117, i32 117 > Added: llvm/branches/Apple/Dib/test/CodeGen/X86/pr3495-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/pr3495-2.ll?rev=64405&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/X86/pr3495-2.ll (added) +++ llvm/branches/Apple/Dib/test/CodeGen/X86/pr3495-2.ll Thu Feb 12 16:12:12 2009 @@ -0,0 +1,49 @@ +; RUN: llvm-as < %s | llc -march=x86 -relocation-model=pic -disable-fp-elim -stats |& grep {Number of reloads omited} + +target triple = "i386-apple-darwin9.6" + %struct.constraintVCGType = type { i32, i32, i32, i32 } + %struct.nodeVCGType = type { %struct.constraintVCGType*, i32, i32, i32, %struct.constraintVCGType*, i32, i32, i32 } + +define fastcc void @SCC_DFSBelowVCG(%struct.nodeVCGType* %VCG, i32 %net, i32 %label) nounwind { +entry: + %0 = getelementptr %struct.nodeVCGType* %VCG, i32 %net, i32 5 ; [#uses=2] + %1 = load i32* %0, align 4 ; [#uses=1] + %2 = icmp eq i32 %1, 0 ; [#uses=1] + br i1 %2, label %bb5, label %bb.nph3 + +bb.nph3: ; preds = %entry + %3 = getelementptr %struct.nodeVCGType* %VCG, i32 %net, i32 4 ; <%struct.constraintVCGType**> [#uses=1] + br label %bb + +bb: ; preds = %bb3, %bb.nph3 + %s.02 = phi i32 [ 0, %bb.nph3 ], [ %12, %bb3 ] ; [#uses=2] + %4 = load %struct.constraintVCGType** %3, align 4 ; <%struct.constraintVCGType*> [#uses=1] + %5 = icmp eq i32 0, 0 ; [#uses=1] + br i1 %5, label %bb1, label %bb3 + +bb1: ; preds = %bb + %6 = getelementptr %struct.constraintVCGType* %4, i32 %s.02, i32 0 ; [#uses=1] + %7 = load i32* %6, align 4 ; [#uses=2] + %8 = getelementptr %struct.nodeVCGType* %VCG, i32 %7, i32 7 ; [#uses=1] + %9 = load i32* %8, align 4 ; [#uses=1] + %10 = icmp eq i32 %9, 0 ; [#uses=1] + br i1 %10, label %bb2, label %bb3 + +bb2: ; preds = %bb1 + %11 = getelementptr %struct.nodeVCGType* %VCG, i32 %7, i32 4 ; <%struct.constraintVCGType**> [#uses=0] + br label %bb.i + +bb.i: ; preds = %bb.i, %bb2 + br label %bb.i + +bb3: ; preds = %bb1, %bb + %12 = add i32 %s.02, 1 ; [#uses=2] + %13 = load i32* %0, align 4 ; [#uses=1] + %14 = icmp ugt i32 %13, %12 ; [#uses=1] + br i1 %14, label %bb, label %bb5 + +bb5: ; preds = %bb3, %entry + %15 = getelementptr %struct.nodeVCGType* %VCG, i32 %net, i32 6 ; [#uses=1] + store i32 %label, i32* %15, align 4 + ret void +} Added: llvm/branches/Apple/Dib/test/CodeGen/X86/pr3495.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/pr3495.ll?rev=64405&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/X86/pr3495.ll (added) +++ llvm/branches/Apple/Dib/test/CodeGen/X86/pr3495.ll Thu Feb 12 16:12:12 2009 @@ -0,0 +1,78 @@ +; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of reloads omited} +; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of available reloads turned into copies} +; PR3495 + +target triple = "i386-pc-linux-gnu" + at x = external global [8 x i32], align 32 ; <[8 x i32]*> [#uses=1] + at rows = external global [8 x i32], align 32 ; <[8 x i32]*> [#uses=2] + at up = external global [15 x i32], align 32 ; <[15 x i32]*> [#uses=2] + at down = external global [15 x i32], align 32 ; <[15 x i32]*> [#uses=1] + +define i32 @queens(i32 %c) nounwind { +entry: + %tmp91 = add i32 %c, 1 ; [#uses=3] + %tmp135 = getelementptr [8 x i32]* @x, i32 0, i32 %tmp91 ; [#uses=1] + br label %bb + +bb: ; preds = %bb569, %entry + %r25.0.reg2mem.0 = phi i32 [ 0, %entry ], [ %indvar.next715, %bb569 ] ; [#uses=4] + %tmp27 = getelementptr [8 x i32]* @rows, i32 0, i32 %r25.0.reg2mem.0 ; [#uses=1] + %tmp28 = load i32* %tmp27, align 4 ; [#uses=1] + %tmp29 = icmp eq i32 %tmp28, 0 ; [#uses=1] + br i1 %tmp29, label %bb569, label %bb31 + +bb31: ; preds = %bb + %tmp35 = sub i32 %r25.0.reg2mem.0, 0 ; [#uses=1] + %tmp36 = getelementptr [15 x i32]* @up, i32 0, i32 %tmp35 ; [#uses=1] + %tmp37 = load i32* %tmp36, align 4 ; [#uses=1] + %tmp38 = icmp eq i32 %tmp37, 0 ; [#uses=1] + br i1 %tmp38, label %bb569, label %bb41 + +bb41: ; preds = %bb31 + %tmp54 = sub i32 %r25.0.reg2mem.0, %c ; [#uses=1] + %tmp55 = add i32 %tmp54, 7 ; [#uses=1] + %tmp62 = getelementptr [15 x i32]* @up, i32 0, i32 %tmp55 ; [#uses=2] + store i32 0, i32* %tmp62, align 4 + br label %bb92 + +bb92: ; preds = %bb545, %bb41 + %r20.0.reg2mem.0 = phi i32 [ 0, %bb41 ], [ %indvar.next711, %bb545 ] ; [#uses=5] + %tmp94 = getelementptr [8 x i32]* @rows, i32 0, i32 %r20.0.reg2mem.0 ; [#uses=1] + %tmp95 = load i32* %tmp94, align 4 ; [#uses=0] + %tmp112 = add i32 %r20.0.reg2mem.0, %tmp91 ; [#uses=1] + %tmp113 = getelementptr [15 x i32]* @down, i32 0, i32 %tmp112 ; [#uses=2] + %tmp114 = load i32* %tmp113, align 4 ; [#uses=1] + %tmp115 = icmp eq i32 %tmp114, 0 ; [#uses=1] + br i1 %tmp115, label %bb545, label %bb118 + +bb118: ; preds = %bb92 + %tmp122 = sub i32 %r20.0.reg2mem.0, %tmp91 ; [#uses=0] + store i32 0, i32* %tmp113, align 4 + store i32 %r20.0.reg2mem.0, i32* %tmp135, align 4 + br label %bb142 + +bb142: ; preds = %bb142, %bb118 + %k18.0.reg2mem.0 = phi i32 [ 0, %bb118 ], [ %indvar.next709, %bb142 ] ; [#uses=1] + %indvar.next709 = add i32 %k18.0.reg2mem.0, 1 ; [#uses=2] + %exitcond710 = icmp eq i32 %indvar.next709, 8 ; [#uses=1] + br i1 %exitcond710, label %bb155, label %bb142 + +bb155: ; preds = %bb142 + %tmp156 = tail call i32 @putchar(i32 10) nounwind ; [#uses=0] + br label %bb545 + +bb545: ; preds = %bb155, %bb92 + %indvar.next711 = add i32 %r20.0.reg2mem.0, 1 ; [#uses=2] + %exitcond712 = icmp eq i32 %indvar.next711, 8 ; [#uses=1] + br i1 %exitcond712, label %bb553, label %bb92 + +bb553: ; preds = %bb545 + store i32 1, i32* %tmp62, align 4 + br label %bb569 + +bb569: ; preds = %bb553, %bb31, %bb + %indvar.next715 = add i32 %r25.0.reg2mem.0, 1 ; [#uses=1] + br label %bb +} + +declare i32 @putchar(i32) Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/sse_reload_fold.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/sse_reload_fold.ll?rev=64405&r1=64404&r2=64405&view=diff ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/X86/sse_reload_fold.ll (original) +++ llvm/branches/Apple/Dib/test/CodeGen/X86/sse_reload_fold.ll Thu Feb 12 16:12:12 2009 @@ -2,9 +2,10 @@ ; RUN: llc -march=x86-64 -mattr=+64bit,+sse3 -print-failed-fuse-candidates |& \ ; RUN: grep fail | count 1 -declare void @bar() -declare <4 x float> @qux() -declare <2 x double> @pin() +declare float @test_f(float %f) +declare double @test_d(double %f) +declare <4 x float> @test_vf(<4 x float> %f) +declare <2 x double> @test_vd(<2 x double> %f) declare float @llvm.sqrt.f32(float) declare double @llvm.sqrt.f64(double) @@ -26,99 +27,99 @@ declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) define float @foo(float %f) { - call void @bar() + %a = call float @test_f(float %f) %t = call float @llvm.sqrt.f32(float %f) ret float %t } define double @doo(double %f) { - call void @bar() + %a = call double @test_d(double %f) %t = call double @llvm.sqrt.f64(double %f) ret double %t } define <4 x float> @a0(<4 x float> %f) { - call void @bar() + %a = call <4 x float> @test_vf(<4 x float> %f) %t = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> %f) ret <4 x float> %t } define <4 x float> @a1(<4 x float> %f) { - call void @bar() + %a = call <4 x float> @test_vf(<4 x float> %f) %t = call <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float> %f) ret <4 x float> %t } define <4 x float> @a2(<4 x float> %f) { - call void @bar() + %a = call <4 x float> @test_vf(<4 x float> %f) %t = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %f) ret <4 x float> %t } define <4 x float> @b3(<4 x float> %f) { - %y = call <4 x float> @qux() + %y = call <4 x float> @test_vf(<4 x float> %f) %t = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %y, <4 x float> %f) ret <4 x float> %t } define <4 x float> @b4(<4 x float> %f) { - %y = call <4 x float> @qux() + %y = call <4 x float> @test_vf(<4 x float> %f) %t = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %y, <4 x float> %f) ret <4 x float> %t } define <4 x float> @b5(<4 x float> %f) { - %y = call <4 x float> @qux() + %y = call <4 x float> @test_vf(<4 x float> %f) %t = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %y, <4 x float> %f, i8 7) ret <4 x float> %t } define <4 x float> @b6(<4 x float> %f) { - %y = call <4 x float> @qux() + %y = call <4 x float> @test_vf(<4 x float> %f) %t = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %y, <4 x float> %f) ret <4 x float> %t } define <4 x float> @b7(<4 x float> %f) { - %y = call <4 x float> @qux() + %y = call <4 x float> @test_vf(<4 x float> %f) %t = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %y, <4 x float> %f) ret <4 x float> %t } define <4 x float> @b8(<4 x float> %f) { - %y = call <4 x float> @qux() + %y = call <4 x float> @test_vf(<4 x float> %f) %t = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %y, <4 x float> %f) ret <4 x float> %t } define <2 x double> @c1(<2 x double> %f) { - call void @bar() + %a = call <2 x double> @test_vd(<2 x double> %f) %t = call <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double> %f) ret <2 x double> %t } define <2 x double> @d3(<2 x double> %f) { - %y = call <2 x double> @pin() + %y = call <2 x double> @test_vd(<2 x double> %f) %t = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %y, <2 x double> %f) ret <2 x double> %t } define <2 x double> @d4(<2 x double> %f) { - %y = call <2 x double> @pin() + %y = call <2 x double> @test_vd(<2 x double> %f) %t = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> %y, <2 x double> %f) ret <2 x double> %t } define <2 x double> @d5(<2 x double> %f) { - %y = call <2 x double> @pin() + %y = call <2 x double> @test_vd(<2 x double> %f) %t = call <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double> %y, <2 x double> %f, i8 7) ret <2 x double> %t } define <2 x double> @d6(<2 x double> %f) { - %y = call <2 x double> @pin() + %y = call <2 x double> @test_vd(<2 x double> %f) %t = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %y, <2 x double> %f) ret <2 x double> %t } define <2 x double> @d7(<2 x double> %f) { - %y = call <2 x double> @pin() + %y = call <2 x double> @test_vd(<2 x double> %f) %t = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %y, <2 x double> %f) ret <2 x double> %t } define <2 x double> @d8(<2 x double> %f) { - %y = call <2 x double> @pin() + %y = call <2 x double> @test_vd(<2 x double> %f) %t = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %y, <2 x double> %f) ret <2 x double> %t } ; This one should fail to fuse. define <2 x double> @z0(<2 x double> %f) { - %y = call <2 x double> @pin() + %y = call <2 x double> @test_vd(<2 x double> %f) %t = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %f, <2 x double> %y) ret <2 x double> %t } From isanbard at gmail.com Thu Feb 12 16:13:53 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 12 Feb 2009 22:13:53 -0000 Subject: [llvm-commits] [llvm] r64406 - in /llvm/branches/Apple/Dib: lib/CodeGen/VirtRegMap.cpp test/CodeGen/X86/2009-02-12-SpillerBug.ll Message-ID: <200902122213.n1CMDsMT018730@zion.cs.uiuc.edu> Author: void Date: Thu Feb 12 16:13:53 2009 New Revision: 64406 URL: http://llvm.org/viewvc/llvm-project?rev=64406&view=rev Log: --- Merging (from foreign repository) r64374 into '.': A test/CodeGen/X86/2009-02-12-SpillerBug.ll U lib/CodeGen/VirtRegMap.cpp Added: llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-12-SpillerBug.ll Modified: llvm/branches/Apple/Dib/lib/CodeGen/VirtRegMap.cpp Modified: llvm/branches/Apple/Dib/lib/CodeGen/VirtRegMap.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/VirtRegMap.cpp?rev=64406&r1=64405&r2=64406&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/VirtRegMap.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/VirtRegMap.cpp Thu Feb 12 16:13:53 2009 @@ -496,6 +496,12 @@ I = PhysRegsAvailable.begin(), E = PhysRegsAvailable.end(); I != E; ++I) { unsigned Reg = (*I).first; + const TargetRegisterClass* RC = TRI->getPhysicalRegisterRegClass(Reg); + // FIXME: A temporary workaround. We can't reuse available value if it's + // not safe to move the def of the virtual register's class. e.g. + // X86::RFP* register classes. Do not add it as a live-in. + if (!TII->isSafeToMoveRegClassDefs(RC)) + continue; if (!MBB.isLiveIn(Reg)) MBB.addLiveIn(Reg); } @@ -1361,7 +1367,12 @@ bool DoReMat = VRM.isReMaterialized(VirtReg); int SSorRMId = DoReMat ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg); - unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId); + const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); + // FIXME: A temporary workaround. Don't reuse available value if it's + // not safe to move the def of the virtual register's class. e.g. + // X86::RFP* register classes. + unsigned InReg = TII->isSafeToMoveRegClassDefs(RC) ? + Spills.getSpillSlotOrReMatPhysReg(SSorRMId) : 0; if (InReg == Phys) { // If the value is already available in the expected register, save // a reload / remat. @@ -1387,7 +1398,6 @@ // If the reloaded / remat value is available in another register, // copy it to the desired register. - const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); TII->copyRegToReg(MBB, &MI, Phys, InReg, RC, RC); // This invalidates Phys. Added: llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-12-SpillerBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-12-SpillerBug.ll?rev=64406&view=auto ============================================================================== --- llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-12-SpillerBug.ll (added) +++ llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-12-SpillerBug.ll Thu Feb 12 16:13:53 2009 @@ -0,0 +1,28 @@ +; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-apple-darwin8 + +define hidden void @__mulxc3({ x86_fp80, x86_fp80 }* noalias nocapture sret %agg.result, x86_fp80 %a, x86_fp80 %b, x86_fp80 %c, x86_fp80 %d) nounwind { +entry: + %0 = mul x86_fp80 %b, %d ; [#uses=1] + %1 = sub x86_fp80 0xK00000000000000000000, %0 ; [#uses=1] + %2 = add x86_fp80 0xK00000000000000000000, 0xK00000000000000000000 ; [#uses=1] + %3 = fcmp uno x86_fp80 %1, 0xK00000000000000000000 ; [#uses=1] + %4 = fcmp uno x86_fp80 %2, 0xK00000000000000000000 ; [#uses=1] + %or.cond = and i1 %3, %4 ; [#uses=1] + br i1 %or.cond, label %bb47, label %bb71 + +bb47: ; preds = %entry + %5 = fcmp uno x86_fp80 %a, 0xK00000000000000000000 ; [#uses=1] + br i1 %5, label %bb60, label %bb62 + +bb60: ; preds = %bb47 + %6 = tail call x86_fp80 @copysignl(x86_fp80 0xK00000000000000000000, x86_fp80 %a) nounwind readnone ; [#uses=0] + br label %bb62 + +bb62: ; preds = %bb60, %bb47 + unreachable + +bb71: ; preds = %entry + ret void +} + +declare x86_fp80 @copysignl(x86_fp80, x86_fp80) nounwind readnone From gohman at apple.com Thu Feb 12 16:19:27 2009 From: gohman at apple.com (Dan Gohman) Date: Thu, 12 Feb 2009 22:19:27 -0000 Subject: [llvm-commits] [llvm] r64407 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h lib/Analysis/ScalarEvolution.cpp lib/Transforms/Scalar/IndVarSimplify.cpp test/Transforms/IndVarsSimplify/promote-iv-to-eliminate-casts.ll Message-ID: <200902122219.n1CMJR3v018926@zion.cs.uiuc.edu> Author: djg Date: Thu Feb 12 16:19:27 2009 New Revision: 64407 URL: http://llvm.org/viewvc/llvm-project?rev=64407&view=rev Log: Teach IndVarSimplify to optimize code using the C "int" type for loop induction on LP64 targets. When the induction variable is used in addressing, IndVars now is usually able to inserst a 64-bit induction variable and eliminates the sign-extending cast. This is also useful for code using C "short" types for induction variables on targets with 32-bit addressing. Inserting a wider induction variable is easy; the tricky part is determining when trunc(sext(i)) expressions are no-ops. This requires range analysis of the loop trip count. A common case is when the original loop iteration starts at 0 and exits when the induction variable is signed-less-than a fixed value; this case is now handled. This replaces IndVarSimplify's OptimizeCanonicalIVType. It was doing the same optimization, but it was limited to loops with constant trip counts, because it was running after the loop rewrite, and the information about the original induction variable is lost by that point. Rename ScalarEvolution's executesAtLeastOnce to isLoopGuardedByCond, generalize it to be able to test for ICMP_NE conditions, and move it to be a public function so that IndVars can use it. Added: llvm/trunk/test/Transforms/IndVarsSimplify/promote-iv-to-eliminate-casts.ll Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h llvm/trunk/lib/Analysis/ScalarEvolution.cpp llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolution.h?rev=64407&r1=64406&r2=64407&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolution.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolution.h Thu Feb 12 16:19:27 2009 @@ -29,9 +29,7 @@ namespace llvm { class APInt; class ConstantInt; - class Instruction; class Type; - class ConstantRange; class SCEVHandle; class ScalarEvolution; @@ -282,6 +280,11 @@ /// object is returned. SCEVHandle getSCEVAtScope(Value *V, const Loop *L) const; + /// isLoopGuardedByCond - Test whether entry to the loop is protected by + /// a conditional between LHS and RHS. + bool isLoopGuardedByCond(const Loop *L, ICmpInst::Predicate Pred, + SCEV *LHS, SCEV *RHS); + /// getIterationCount - If the specified loop has a predictable iteration /// count, return it, otherwise return a SCEVCouldNotCompute object. SCEVHandle getIterationCount(const Loop *L) const; Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=64407&r1=64406&r2=64407&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Thu Feb 12 16:19:27 2009 @@ -1404,6 +1404,11 @@ SCEVHandle getSCEVAtScope(SCEV *V, const Loop *L); + /// isLoopGuardedByCond - Test whether entry to the loop is protected by + /// a conditional between LHS and RHS. + bool isLoopGuardedByCond(const Loop *L, ICmpInst::Predicate Pred, + SCEV *LHS, SCEV *RHS); + /// hasLoopInvariantIterationCount - Return true if the specified loop has /// an analyzable loop-invariant iteration count. bool hasLoopInvariantIterationCount(const Loop *L); @@ -1476,10 +1481,6 @@ /// found. BasicBlock* getPredecessorWithUniqueSuccessorForBB(BasicBlock *BB); - /// executesAtLeastOnce - Test whether entry to the loop is protected by - /// a conditional between LHS and RHS. - bool executesAtLeastOnce(const Loop *L, bool isSigned, SCEV *LHS, SCEV *RHS); - /// getConstantEvolutionLoopExitValue - If we know that the specified Phi is /// in the header of its containing loop, we know the loop executes a /// constant number of times, and the PHI node is just a recurrence @@ -2726,9 +2727,10 @@ return 0; } -/// executesAtLeastOnce - Test whether entry to the loop is protected by +/// isLoopGuardedByCond - Test whether entry to the loop is protected by /// a conditional between LHS and RHS. -bool ScalarEvolutionsImpl::executesAtLeastOnce(const Loop *L, bool isSigned, +bool ScalarEvolutionsImpl::isLoopGuardedByCond(const Loop *L, + ICmpInst::Predicate Pred, SCEV *LHS, SCEV *RHS) { BasicBlock *Preheader = L->getLoopPreheader(); BasicBlock *PreheaderDest = L->getHeader(); @@ -2759,26 +2761,62 @@ else Cond = ICI->getInversePredicate(); - switch (Cond) { - case ICmpInst::ICMP_UGT: - if (isSigned) continue; - std::swap(PreCondLHS, PreCondRHS); - Cond = ICmpInst::ICMP_ULT; - break; - case ICmpInst::ICMP_SGT: - if (!isSigned) continue; - std::swap(PreCondLHS, PreCondRHS); - Cond = ICmpInst::ICMP_SLT; - break; - case ICmpInst::ICMP_ULT: - if (isSigned) continue; - break; - case ICmpInst::ICMP_SLT: - if (!isSigned) continue; - break; - default: - continue; - } + if (Cond == Pred) + ; // An exact match. + else if (!ICmpInst::isTrueWhenEqual(Cond) && Pred == ICmpInst::ICMP_NE) + ; // The actual condition is beyond sufficient. + else + // Check a few special cases. + switch (Cond) { + case ICmpInst::ICMP_UGT: + if (Pred == ICmpInst::ICMP_ULT) { + std::swap(PreCondLHS, PreCondRHS); + Cond = ICmpInst::ICMP_ULT; + break; + } + continue; + case ICmpInst::ICMP_SGT: + if (Pred == ICmpInst::ICMP_SLT) { + std::swap(PreCondLHS, PreCondRHS); + Cond = ICmpInst::ICMP_SLT; + break; + } + continue; + case ICmpInst::ICMP_NE: + // Expressions like (x >u 0) are often canonicalized to (x != 0), + // so check for this case by checking if the NE is comparing against + // a minimum or maximum constant. + if (!ICmpInst::isTrueWhenEqual(Pred)) + if (ConstantInt *CI = dyn_cast(PreCondRHS)) { + const APInt &A = CI->getValue(); + switch (Pred) { + case ICmpInst::ICMP_SLT: + if (A.isMaxSignedValue()) break; + continue; + case ICmpInst::ICMP_SGT: + if (A.isMinSignedValue()) break; + continue; + case ICmpInst::ICMP_ULT: + if (A.isMaxValue()) break; + continue; + case ICmpInst::ICMP_UGT: + if (A.isMinValue()) break; + continue; + default: + continue; + } + Cond = ICmpInst::ICMP_NE; + // NE is symmetric but the original comparison may not be. Swap + // the operands if necessary so that they match below. + if (isa(LHS)) + std::swap(PreCondLHS, PreCondRHS); + break; + } + continue; + default: + // We weren't able to reconcile the condition. + continue; + } if (!PreCondLHS->getType()->isInteger()) continue; @@ -2819,7 +2857,8 @@ // First, we get the value of the LHS in the first iteration: n SCEVHandle Start = AddRec->getOperand(0); - if (executesAtLeastOnce(L, isSigned, + if (isLoopGuardedByCond(L, + isSigned ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT, SE.getMinusSCEV(AddRec->getOperand(0), One), RHS)) { // Since we know that the condition is true in order to enter the loop, // we know that it will run exactly m-n times. @@ -2997,6 +3036,13 @@ } +bool ScalarEvolution::isLoopGuardedByCond(const Loop *L, + ICmpInst::Predicate Pred, + SCEV *LHS, SCEV *RHS) { + return ((ScalarEvolutionsImpl*)Impl)->isLoopGuardedByCond(L, Pred, + LHS, RHS); +} + SCEVHandle ScalarEvolution::getIterationCount(const Loop *L) const { return ((ScalarEvolutionsImpl*)Impl)->getIterationCount(L); } Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=64407&r1=64406&r2=64407&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Thu Feb 12 16:19:27 2009 @@ -53,6 +53,7 @@ #include "llvm/Transforms/Utils/Local.h" #include "llvm/Support/CommandLine.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/Statistic.h" using namespace llvm; @@ -89,13 +90,14 @@ void EliminatePointerRecurrence(PHINode *PN, BasicBlock *Preheader, SmallPtrSet &DeadInsts); - Instruction *LinearFunctionTestReplace(Loop *L, SCEV *IterationCount, - SCEVExpander &RW); + void LinearFunctionTestReplace(Loop *L, SCEVHandle IterationCount, Value *IndVar, + BasicBlock *ExitingBlock, + BranchInst *BI, + SCEVExpander &Rewriter); void RewriteLoopExitValues(Loop *L, SCEV *IterationCount); void DeleteTriviallyDeadInstructions(SmallPtrSet &Insts); - void OptimizeCanonicalIVType(Loop *L); void HandleFloatingPointIV(Loop *L, PHINode *PH, SmallPtrSet &DeadInsts); }; @@ -225,68 +227,54 @@ /// variable. This pass is able to rewrite the exit tests of any loop where the /// SCEV analysis can determine a loop-invariant trip count of the loop, which /// is actually a much broader range than just linear tests. -/// -/// This method returns a "potentially dead" instruction whose computation chain -/// should be deleted when convenient. -Instruction *IndVarSimplify::LinearFunctionTestReplace(Loop *L, - SCEV *IterationCount, - SCEVExpander &RW) { - // Find the exit block for the loop. We can currently only handle loops with - // a single exit. - SmallVector ExitBlocks; - L->getExitBlocks(ExitBlocks); - if (ExitBlocks.size() != 1) return 0; - BasicBlock *ExitBlock = ExitBlocks[0]; - - // Make sure there is only one predecessor block in the loop. - BasicBlock *ExitingBlock = 0; - for (pred_iterator PI = pred_begin(ExitBlock), PE = pred_end(ExitBlock); - PI != PE; ++PI) - if (L->contains(*PI)) { - if (ExitingBlock == 0) - ExitingBlock = *PI; - else - return 0; // Multiple exits from loop to this block. - } - assert(ExitingBlock && "Loop info is broken"); - - if (!isa(ExitingBlock->getTerminator())) - return 0; // Can't rewrite non-branch yet - BranchInst *BI = cast(ExitingBlock->getTerminator()); - assert(BI->isConditional() && "Must be conditional to be part of loop!"); - - Instruction *PotentiallyDeadInst = dyn_cast(BI->getCondition()); - +void IndVarSimplify::LinearFunctionTestReplace(Loop *L, + SCEVHandle IterationCount, + Value *IndVar, + BasicBlock *ExitingBlock, + BranchInst *BI, + SCEVExpander &Rewriter) { // If the exiting block is not the same as the backedge block, we must compare // against the preincremented value, otherwise we prefer to compare against // the post-incremented value. - BasicBlock *Header = L->getHeader(); - pred_iterator HPI = pred_begin(Header); - assert(HPI != pred_end(Header) && "Loop with zero preds???"); - if (!L->contains(*HPI)) ++HPI; - assert(HPI != pred_end(Header) && L->contains(*HPI) && - "No backedge in loop?"); - - SCEVHandle TripCount = IterationCount; - Value *IndVar; - if (*HPI == ExitingBlock) { + Value *CmpIndVar; + if (ExitingBlock == L->getLoopLatch()) { + // What ScalarEvolution calls the "iteration count" is actually the + // number of times the branch is taken. Add one to get the number + // of times the branch is executed. If this addition may overflow, + // we have to be more pessimistic and cast the induction variable + // before doing the add. + SCEVHandle Zero = SE->getIntegerSCEV(0, IterationCount->getType()); + SCEVHandle N = + SE->getAddExpr(IterationCount, + SE->getIntegerSCEV(1, IterationCount->getType())); + if ((isa(N) && !N->isZero()) || + SE->isLoopGuardedByCond(L, ICmpInst::ICMP_NE, N, Zero)) { + // No overflow. Cast the sum. + IterationCount = SE->getTruncateOrZeroExtend(N, IndVar->getType()); + } else { + // Potential overflow. Cast before doing the add. + IterationCount = SE->getTruncateOrZeroExtend(IterationCount, + IndVar->getType()); + IterationCount = + SE->getAddExpr(IterationCount, + SE->getIntegerSCEV(1, IndVar->getType())); + } + // The IterationCount expression contains the number of times that the // backedge actually branches to the loop header. This is one less than the // number of times the loop executes, so add one to it. - ConstantInt *OneC = ConstantInt::get(IterationCount->getType(), 1); - TripCount = SE->getAddExpr(IterationCount, SE->getConstant(OneC)); - IndVar = L->getCanonicalInductionVariableIncrement(); + CmpIndVar = L->getCanonicalInductionVariableIncrement(); } else { // We have to use the preincremented value... - IndVar = L->getCanonicalInductionVariable(); + IterationCount = SE->getTruncateOrZeroExtend(IterationCount, + IndVar->getType()); + CmpIndVar = IndVar; } - - DOUT << "INDVARS: LFTR: TripCount = " << *TripCount - << " IndVar = " << *IndVar << "\n"; // Expand the code for the iteration count into the preheader of the loop. BasicBlock *Preheader = L->getLoopPreheader(); - Value *ExitCnt = RW.expandCodeFor(TripCount, Preheader->getTerminator()); + Value *ExitCnt = Rewriter.expandCodeFor(IterationCount, + Preheader->getTerminator()); // Insert a new icmp_ne or icmp_eq instruction before the branch. ICmpInst::Predicate Opcode; @@ -295,14 +283,18 @@ else Opcode = ICmpInst::ICMP_EQ; - Value *Cond = new ICmpInst(Opcode, IndVar, ExitCnt, "exitcond", BI); + DOUT << "INDVARS: Rewriting loop exit condition to:\n" + << " LHS:" << *CmpIndVar // includes a newline + << " op:\t" + << (Opcode == ICmpInst::ICMP_NE ? "!=" : "=") << "\n" + << " RHS:\t" << *IterationCount << "\n"; + + Value *Cond = new ICmpInst(Opcode, CmpIndVar, ExitCnt, "exitcond", BI); BI->setCondition(Cond); ++NumLFTR; Changed = true; - return PotentiallyDeadInst; } - /// RewriteLoopExitValues - Check to see if this loop has a computable /// loop-invariant execution count. If so, this means that we can compute the /// final value of any expressions that are recurrent in the loop, and @@ -444,15 +436,100 @@ return Changed; } -bool IndVarSimplify::runOnLoop(Loop *L, LPPassManager &LPM) { +/// getEffectiveIndvarType - Determine the widest type that the +/// induction-variable PHINode Phi is cast to. +/// +static const Type *getEffectiveIndvarType(const PHINode *Phi) { + const Type *Ty = Phi->getType(); + + for (Value::use_const_iterator UI = Phi->use_begin(), UE = Phi->use_end(); + UI != UE; ++UI) { + const Type *CandidateType = NULL; + if (const ZExtInst *ZI = dyn_cast(UI)) + CandidateType = ZI->getDestTy(); + else if (const SExtInst *SI = dyn_cast(UI)) + CandidateType = SI->getDestTy(); + if (CandidateType && + CandidateType->getPrimitiveSizeInBits() > + Ty->getPrimitiveSizeInBits()) + Ty = CandidateType; + } + return Ty; +} + +/// isOrigIVAlwaysNonNegative - Analyze the original induction variable +/// in the loop to determine whether it would ever have a negative +/// value. +/// +/// TODO: This duplicates a fair amount of ScalarEvolution logic. +/// Perhaps this can be merged with ScalarEvolution::getIterationCount. +/// +static bool isOrigIVAlwaysNonNegative(const Loop *L, + const Instruction *OrigCond) { + // Verify that the loop is sane and find the exit condition. + const ICmpInst *Cmp = dyn_cast(OrigCond); + if (!Cmp) return false; + + // For now, analyze only SLT loops for signed overflow. + if (Cmp->getPredicate() != ICmpInst::ICMP_SLT) return false; + + // Get the increment instruction. Look past SExtInsts if we will + // be able to prove that the original induction variable doesn't + // undergo signed overflow. + const Value *OrigIncrVal = Cmp->getOperand(0); + const Value *IncrVal = OrigIncrVal; + if (SExtInst *SI = dyn_cast(Cmp->getOperand(0))) { + if (!isa(Cmp->getOperand(1)) || + !cast(Cmp->getOperand(1))->getValue() + .isSignedIntN(IncrVal->getType()->getPrimitiveSizeInBits())) + return false; + IncrVal = SI->getOperand(0); + } + + // For now, only analyze induction variables that have simple increments. + const BinaryOperator *IncrOp = dyn_cast(IncrVal); + if (!IncrOp || + IncrOp->getOpcode() != Instruction::Add || + !isa(IncrOp->getOperand(1)) || + !cast(IncrOp->getOperand(1))->equalsInt(1)) + return false; + + // Make sure the PHI looks like a normal IV. + const PHINode *PN = dyn_cast(IncrOp->getOperand(0)); + if (!PN || PN->getNumIncomingValues() != 2) + return false; + unsigned IncomingEdge = L->contains(PN->getIncomingBlock(0)); + unsigned BackEdge = !IncomingEdge; + if (!L->contains(PN->getIncomingBlock(BackEdge)) || + PN->getIncomingValue(BackEdge) != IncrOp) + return false; + + // For now, only analyze loops with a constant start value, so that + // we can easily determine if the start value is non-negative and + // not a maximum value which would wrap on the first iteration. + const Value *InitialVal = PN->getIncomingValue(IncomingEdge); + if (!isa(InitialVal) || + cast(InitialVal)->getValue().isNegative() || + cast(InitialVal)->getValue().isMaxSignedValue()) + return false; + + // The original induction variable will start at some non-negative + // non-max value, it counts up by one, and the loop iterates only + // while it remans less than (signed) some value in the same type. + // As such, it will always be non-negative. + return true; +} + +bool IndVarSimplify::runOnLoop(Loop *L, LPPassManager &LPM) { LI = &getAnalysis(); SE = &getAnalysis(); Changed = false; - BasicBlock *Header = L->getHeader(); + BasicBlock *Header = L->getHeader(); + BasicBlock *ExitingBlock = L->getExitingBlock(); SmallPtrSet DeadInsts; - + // Verify the input to the pass in already in LCSSA form. assert(L->isLCSSAForm()); @@ -486,35 +563,23 @@ } } - // If there are no induction variables in the loop, there is nothing more to - // do. - if (IndVars.empty()) { - // Actually, if we know how many times the loop iterates, lets insert a - // canonical induction variable to help subsequent passes. - if (!isa(IterationCount)) { - SCEVExpander Rewriter(*SE, *LI); - Rewriter.getOrInsertCanonicalInductionVariable(L, - IterationCount->getType()); - if (Instruction *I = LinearFunctionTestReplace(L, IterationCount, - Rewriter)) { - SmallPtrSet InstructionsToDelete; - InstructionsToDelete.insert(I); - DeleteTriviallyDeadInstructions(InstructionsToDelete); - } - } - return Changed; + // Compute the type of the largest recurrence expression, and collect + // the set of the types of the other recurrence expressions. + const Type *LargestType = 0; + SmallSetVector SizesToInsert; + if (!isa(IterationCount)) { + LargestType = IterationCount->getType(); + SizesToInsert.insert(IterationCount->getType()); } - - // Compute the type of the largest recurrence expression. - // - const Type *LargestType = IndVars[0].first->getType(); - bool DifferingSizes = false; - for (unsigned i = 1, e = IndVars.size(); i != e; ++i) { - const Type *Ty = IndVars[i].first->getType(); - DifferingSizes |= - Ty->getPrimitiveSizeInBits() != LargestType->getPrimitiveSizeInBits(); - if (Ty->getPrimitiveSizeInBits() > LargestType->getPrimitiveSizeInBits()) - LargestType = Ty; + for (unsigned i = 0, e = IndVars.size(); i != e; ++i) { + const PHINode *PN = IndVars[i].first; + SizesToInsert.insert(PN->getType()); + const Type *EffTy = getEffectiveIndvarType(PN); + SizesToInsert.insert(EffTy); + if (!LargestType || + EffTy->getPrimitiveSizeInBits() > + LargestType->getPrimitiveSizeInBits()) + LargestType = EffTy; } // Create a rewriter object which we'll use to transform the code with. @@ -522,17 +587,32 @@ // Now that we know the largest of of the induction variables in this loop, // insert a canonical induction variable of the largest size. - Value *IndVar = Rewriter.getOrInsertCanonicalInductionVariable(L,LargestType); - ++NumInserted; - Changed = true; - DOUT << "INDVARS: New CanIV: " << *IndVar; - - if (!isa(IterationCount)) { - IterationCount = SE->getTruncateOrZeroExtend(IterationCount, LargestType); - if (Instruction *DI = LinearFunctionTestReplace(L, IterationCount,Rewriter)) - DeadInsts.insert(DI); + Value *IndVar = 0; + if (!SizesToInsert.empty()) { + IndVar = Rewriter.getOrInsertCanonicalInductionVariable(L,LargestType); + ++NumInserted; + Changed = true; + DOUT << "INDVARS: New CanIV: " << *IndVar; } + // If we have a trip count expression, rewrite the loop's exit condition + // using it. We can currently only handle loops with a single exit. + bool OrigIVAlwaysNonNegative = false; + if (!isa(IterationCount) && ExitingBlock) + // Can't rewrite non-branch yet. + if (BranchInst *BI = dyn_cast(ExitingBlock->getTerminator())) { + if (Instruction *OrigCond = dyn_cast(BI->getCondition())) { + // Determine if the OrigIV will ever have a non-zero sign bit. + OrigIVAlwaysNonNegative = isOrigIVAlwaysNonNegative(L, OrigCond); + + // We'll be replacing the original condition, so it'll be dead. + DeadInsts.insert(OrigCond); + } + + LinearFunctionTestReplace(L, IterationCount, IndVar, + ExitingBlock, BI, Rewriter); + } + // Now that we have a canonical induction variable, we can rewrite any // recurrences in terms of the induction variable. Start with the auxillary // induction variables, and recursively rewrite any of their uses. @@ -541,21 +621,13 @@ // If there were induction variables of other sizes, cast the primary // induction variable to the right size for them, avoiding the need for the // code evaluation methods to insert induction variables of different sizes. - if (DifferingSizes) { - SmallVector InsertedSizes; - InsertedSizes.push_back(LargestType->getPrimitiveSizeInBits()); - for (unsigned i = 0, e = IndVars.size(); i != e; ++i) { - unsigned ithSize = IndVars[i].first->getType()->getPrimitiveSizeInBits(); - if (std::find(InsertedSizes.begin(), InsertedSizes.end(), ithSize) - == InsertedSizes.end()) { - PHINode *PN = IndVars[i].first; - InsertedSizes.push_back(ithSize); - Instruction *New = new TruncInst(IndVar, PN->getType(), "indvar", - InsertPt); - Rewriter.addInsertedValue(New, SE->getSCEV(New)); - DOUT << "INDVARS: Made trunc IV for " << *PN - << " NewVal = " << *New << "\n"; - } + for (unsigned i = 0, e = SizesToInsert.size(); i != e; ++i) { + const Type *Ty = SizesToInsert[i]; + if (Ty != LargestType) { + Instruction *New = new TruncInst(IndVar, Ty, "indvar", InsertPt); + Rewriter.addInsertedValue(New, SE->getSCEV(New)); + DOUT << "INDVARS: Made trunc IV for type " << *Ty << ": " + << *New << "\n"; } } @@ -568,6 +640,23 @@ << " into = " << *NewVal << "\n"; NewVal->takeName(PN); + /// If the new canonical induction variable is wider than the original, + /// and the original has uses that are casts to wider types, see if the + /// truncate and extend can be omitted. + if (isa(NewVal)) + for (Value::use_iterator UI = PN->use_begin(), UE = PN->use_end(); + UI != UE; ++UI) + if (isa(UI) || + (isa(UI) && OrigIVAlwaysNonNegative)) { + Value *TruncIndVar = IndVar; + if (TruncIndVar->getType() != UI->getType()) + TruncIndVar = new TruncInst(IndVar, UI->getType(), "truncindvar", + InsertPt); + UI->replaceAllUsesWith(TruncIndVar); + if (Instruction *DeadUse = dyn_cast(*UI)) + DeadInsts.insert(DeadUse); + } + // Replace the old PHI Node with the inserted computation. PN->replaceAllUsesWith(NewVal); DeadInsts.insert(PN); @@ -603,125 +692,10 @@ #endif DeleteTriviallyDeadInstructions(DeadInsts); - OptimizeCanonicalIVType(L); assert(L->isLCSSAForm()); return Changed; } -/// OptimizeCanonicalIVType - If loop induction variable is always -/// sign or zero extended then extend the type of the induction -/// variable. -void IndVarSimplify::OptimizeCanonicalIVType(Loop *L) { - PHINode *PH = L->getCanonicalInductionVariable(); - if (!PH) return; - - // Check loop iteration count. - SCEVHandle IC = SE->getIterationCount(L); - if (isa(IC)) return; - SCEVConstant *IterationCount = dyn_cast(IC); - if (!IterationCount) return; - - unsigned IncomingEdge = L->contains(PH->getIncomingBlock(0)); - unsigned BackEdge = IncomingEdge^1; - - // Check IV uses. If all IV uses are either SEXT or ZEXT (except - // IV increment instruction) then this IV is suitable for this - // transformation. - bool isSEXT = false; - BinaryOperator *Incr = NULL; - const Type *NewType = NULL; - for(Value::use_iterator UI = PH->use_begin(), UE = PH->use_end(); - UI != UE; ++UI) { - const Type *CandidateType = NULL; - if (ZExtInst *ZI = dyn_cast(UI)) - CandidateType = ZI->getDestTy(); - else if (SExtInst *SI = dyn_cast(UI)) { - CandidateType = SI->getDestTy(); - isSEXT = true; - } - else if ((Incr = dyn_cast(UI))) { - // Validate IV increment instruction. - if (PH->getIncomingValue(BackEdge) == Incr) - continue; - } - if (!CandidateType) { - NewType = NULL; - break; - } - if (!NewType) - NewType = CandidateType; - else if (NewType != CandidateType) { - NewType = NULL; - break; - } - } - - // IV uses are not suitable then avoid this transformation. - if (!NewType || !Incr) - return; - - // IV increment instruction has two uses, one is loop exit condition - // and second is the IV (phi node) itself. - ICmpInst *Exit = NULL; - for(Value::use_iterator II = Incr->use_begin(), IE = Incr->use_end(); - II != IE; ++II) { - if (PH == *II) continue; - Exit = dyn_cast(*II); - break; - } - if (!Exit) return; - ConstantInt *EV = dyn_cast(Exit->getOperand(0)); - if (!EV) - EV = dyn_cast(Exit->getOperand(1)); - if (!EV) return; - - // Check iteration count max value to avoid loops that wrap around IV. - APInt ICount = IterationCount->getValue()->getValue(); - if (ICount.isNegative()) return; - uint32_t BW = PH->getType()->getPrimitiveSizeInBits(); - APInt Max = (isSEXT ? APInt::getSignedMaxValue(BW) : APInt::getMaxValue(BW)); - if (ICount.getZExtValue() > Max.getZExtValue()) return; - - // Extend IV type. - - SCEVExpander Rewriter(*SE, *LI); - Value *NewIV = Rewriter.getOrInsertCanonicalInductionVariable(L,NewType); - PHINode *NewPH = cast(NewIV); - Instruction *NewIncr = cast(NewPH->getIncomingValue(BackEdge)); - - // Replace all SEXT or ZEXT uses. - SmallVector PHUses; - for(Value::use_iterator UI = PH->use_begin(), UE = PH->use_end(); - UI != UE; ++UI) { - Instruction *I = cast(UI); - PHUses.push_back(I); - } - while (!PHUses.empty()){ - Instruction *Use = PHUses.back(); PHUses.pop_back(); - if (Incr == Use) continue; - - SE->deleteValueFromRecords(Use); - Use->replaceAllUsesWith(NewIV); - Use->eraseFromParent(); - } - - // Replace exit condition. - ConstantInt *NEV = ConstantInt::get(NewType, EV->getZExtValue()); - Instruction *NE = new ICmpInst(Exit->getPredicate(), - NewIncr, NEV, "new.exit", - Exit->getParent()->getTerminator()); - SE->deleteValueFromRecords(Exit); - Exit->replaceAllUsesWith(NE); - Exit->eraseFromParent(); - - // Remove old IV and increment instructions. - SE->deleteValueFromRecords(PH); - PH->removeIncomingValue((unsigned)0); - PH->removeIncomingValue((unsigned)0); - SE->deleteValueFromRecords(Incr); - Incr->eraseFromParent(); -} - /// Return true if it is OK to use SIToFPInst for an inducation variable /// with given inital and exit values. static bool useSIToFPInst(ConstantFP &InitV, ConstantFP &ExitV, Added: llvm/trunk/test/Transforms/IndVarsSimplify/promote-iv-to-eliminate-casts.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarsSimplify/promote-iv-to-eliminate-casts.ll?rev=64407&view=auto ============================================================================== --- llvm/trunk/test/Transforms/IndVarsSimplify/promote-iv-to-eliminate-casts.ll (added) +++ llvm/trunk/test/Transforms/IndVarsSimplify/promote-iv-to-eliminate-casts.ll Thu Feb 12 16:19:27 2009 @@ -0,0 +1,62 @@ +; RUN: llvm-as < %s | opt -indvars | llvm-dis | not grep sext + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" + +define i64 @test(i64* nocapture %first, i32 %count) nounwind readonly { +entry: + %t0 = icmp sgt i32 %count, 0 ; [#uses=1] + br i1 %t0, label %bb.nph, label %bb2 + +bb.nph: ; preds = %entry + br label %bb + +bb: ; preds = %bb1, %bb.nph + %result.02 = phi i64 [ %t5, %bb1 ], [ 0, %bb.nph ] ; [#uses=1] + %n.01 = phi i32 [ %t6, %bb1 ], [ 0, %bb.nph ] ; [#uses=2] + %t1 = sext i32 %n.01 to i64 ; [#uses=1] + %t2 = getelementptr i64* %first, i64 %t1 ; [#uses=1] + %t3 = load i64* %t2, align 8 ; [#uses=1] + %t4 = lshr i64 %t3, 4 ; [#uses=1] + %t5 = add i64 %t4, %result.02 ; [#uses=2] + %t6 = add i32 %n.01, 1 ; [#uses=2] + br label %bb1 + +bb1: ; preds = %bb + %t7 = icmp slt i32 %t6, %count ; [#uses=1] + br i1 %t7, label %bb, label %bb1.bb2_crit_edge + +bb1.bb2_crit_edge: ; preds = %bb1 + %.lcssa = phi i64 [ %t5, %bb1 ] ; [#uses=1] + br label %bb2 + +bb2: ; preds = %bb1.bb2_crit_edge, %entry + %result.0.lcssa = phi i64 [ %.lcssa, %bb1.bb2_crit_edge ], [ 0, %entry ] ; [#uses=1] + ret i64 %result.0.lcssa +} + +define void @foo(i16 signext %N, i32* nocapture %P) nounwind { +entry: + %t0 = icmp sgt i16 %N, 0 ; [#uses=1] + br i1 %t0, label %bb.nph, label %return + +bb.nph: ; preds = %entry + br label %bb + +bb: ; preds = %bb1, %bb.nph + %i.01 = phi i16 [ %t3, %bb1 ], [ 0, %bb.nph ] ; [#uses=2] + %t1 = sext i16 %i.01 to i64 ; [#uses=1] + %t2 = getelementptr i32* %P, i64 %t1 ; [#uses=1] + store i32 123, i32* %t2, align 4 + %t3 = add i16 %i.01, 1 ; [#uses=2] + br label %bb1 + +bb1: ; preds = %bb + %t4 = icmp slt i16 %t3, %N ; [#uses=1] + br i1 %t4, label %bb, label %bb1.return_crit_edge + +bb1.return_crit_edge: ; preds = %bb1 + br label %return + +return: ; preds = %bb1.return_crit_edge, %entry + ret void +} From lattner at apple.com Thu Feb 12 16:23:15 2009 From: lattner at apple.com (Tanya Lattner) Date: Thu, 12 Feb 2009 14:23:15 -0800 Subject: [llvm-commits] [llvm] r62746 - /llvm/trunk/Makefile.rules In-Reply-To: References: <200901220324.n0M3OMbY009941@zion.cs.uiuc.edu> <20090212061954.GA99037@pom.apple.com> Message-ID: <237DA711-0A3F-4ED5-996D-471281F97961@apple.com> On Feb 12, 2009, at 10:36 AM, Mike Stump wrote: > On Feb 11, 2009, at 10:19 PM, Julien Lerouge wrote: >> Order-only dependencies are not supported by make 3.79 it seems. > > Ick, that's kinda annoying. I didn't realize they were newer than > 3.79. Should we update the requirements? 3.80 was around in the 10.4 > timeframe, though, I don't know which version the feature came in on. LLVM has to support more than just Mac OS X, so if mingw is still shipping with 3.79 we should probably keep this as a minimum pre-req. Mike - Can you re-implement this another way? This impacts the 2.5 release. -Tanya > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090212/a9b5454d/attachment.html From dalej at apple.com Thu Feb 12 17:08:38 2009 From: dalej at apple.com (Dale Johannesen) Date: Thu, 12 Feb 2009 23:08:38 -0000 Subject: [llvm-commits] [llvm] r64409 - in /llvm/trunk: include/llvm/CodeGen/MachineInstrBuilder.h lib/Target/ARM/ARMInstrInfo.cpp lib/Target/Alpha/AlphaRegisterInfo.cpp lib/Target/CellSPU/SPUInstrInfo.cpp lib/Target/IA64/IA64InstrInfo.cpp lib/Target/Mips/MipsInstrInfo.cpp lib/Target/PowerPC/PPCInstrInfo.cpp lib/Target/Sparc/SparcInstrInfo.cpp lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86RegisterInfo.cpp lib/Target/XCore/XCoreRegisterInfo.cpp Message-ID: <200902122308.n1CN8d5i020992@zion.cs.uiuc.edu> Author: johannes Date: Thu Feb 12 17:08:38 2009 New Revision: 64409 URL: http://llvm.org/viewvc/llvm-project?rev=64409&view=rev Log: Eliminate a couple of non-DebugLoc BuildMI variants. Modify callers. Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=64409&r1=64408&r2=64409&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Thu Feb 12 17:08:38 2009 @@ -99,11 +99,6 @@ /// itself. /// inline MachineInstrBuilder BuildMI(MachineFunction &MF, - const TargetInstrDesc &TID) { - return MachineInstrBuilder(MF.CreateMachineInstr(TID, - DebugLoc::getUnknownLoc())); -} -inline MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const TargetInstrDesc &TID) { return MachineInstrBuilder(MF.CreateMachineInstr(TID, DL)); @@ -113,13 +108,6 @@ /// destination virtual register. /// inline MachineInstrBuilder BuildMI(MachineFunction &MF, - const TargetInstrDesc &TID, - unsigned DestReg) { - return MachineInstrBuilder(MF.CreateMachineInstr(TID, - DebugLoc::getUnknownLoc())) - .addReg(DestReg, true); -} -inline MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const TargetInstrDesc &TID, unsigned DestReg) { Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=64409&r1=64408&r2=64409&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Thu Feb 12 17:08:38 2009 @@ -555,13 +555,14 @@ SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const{ + DebugLoc DL = DebugLoc::getUnknownLoc(); unsigned Opc = 0; if (RC == ARM::GPRRegisterClass) { ARMFunctionInfo *AFI = MF.getInfo(); if (AFI->isThumbFunction()) { Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR; MachineInstrBuilder MIB = - BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill); + BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); NewMIs.push_back(MIB); @@ -576,7 +577,7 @@ } MachineInstrBuilder MIB = - BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill); + BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); AddDefaultPred(MIB); @@ -614,12 +615,13 @@ SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); unsigned Opc = 0; if (RC == ARM::GPRRegisterClass) { ARMFunctionInfo *AFI = MF.getInfo(); if (AFI->isThumbFunction()) { Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR; - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); NewMIs.push_back(MIB); @@ -633,7 +635,7 @@ Opc = ARM::FLDS; } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); AddDefaultPred(MIB); Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=64409&r1=64408&r2=64409&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Thu Feb 12 17:08:38 2009 @@ -125,11 +125,11 @@ MachineInstr *New; if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) { - New=BuildMI(MF, TII.get(Alpha::LDA), Alpha::R30) + New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30) .addImm(-Amount).addReg(Alpha::R30); } else { assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP); - New=BuildMI(MF, TII.get(Alpha::LDA), Alpha::R30) + New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30) .addImm(Amount).addReg(Alpha::R30); } @@ -188,7 +188,8 @@ MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false); MI.getOperand(i).ChangeToImmediate(getLower16(Offset)); //insert the new - MachineInstr* nMI=BuildMI(MF, TII.get(Alpha::LDAH), Alpha::R28) + MachineInstr* nMI=BuildMI(MF, MI.getDebugLoc(), + TII.get(Alpha::LDAH), Alpha::R28) .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); MBB.insert(II, nMI); } else { Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=64409&r1=64408&r2=64409&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Thu Feb 12 17:08:38 2009 @@ -349,7 +349,8 @@ assert(0 && "Unknown regclass!"); abort(); } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)) + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) .addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; @@ -431,7 +432,8 @@ assert(0 && "Unknown regclass!"); abort(); } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) Modified: llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp?rev=64409&r1=64408&r2=64409&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp Thu Feb 12 17:08:38 2009 @@ -130,7 +130,8 @@ "sorry, I don't know how to store this sort of reg\n"); } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) @@ -185,10 +186,11 @@ Opc = IA64::LD1; } else { assert(0 && - "sorry, I don't know how to store this sort of reg\n"); + "sorry, I don't know how to load this sort of reg\n"); } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=64409&r1=64408&r2=64409&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Thu Feb 12 17:08:38 2009 @@ -225,7 +225,8 @@ else assert(0 && "Can't store this register"); - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)) + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) .addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; @@ -278,7 +279,8 @@ else assert(0 && "Can't load this register"); - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=64409&r1=64408&r2=64409&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Thu Feb 12 17:08:38 2009 @@ -355,43 +355,44 @@ int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const{ + DebugLoc DL = DebugLoc::getUnknownLoc(); if (RC == PPC::GPRCRegisterClass) { if (SrcReg != PPC::LR) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW)) + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) .addReg(SrcReg, false, false, isKill), FrameIdx)); } else { // FIXME: this spills LR immediately to memory in one step. To do this, // we use R11, which we know cannot be used in the prolog/epilog. This is // a hack. - NewMIs.push_back(BuildMI(MF, get(PPC::MFLR), PPC::R11)); - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW)) + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) .addReg(PPC::R11, false, false, isKill), FrameIdx)); } } else if (RC == PPC::G8RCRegisterClass) { if (SrcReg != PPC::LR8) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD)) + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) .addReg(SrcReg, false, false, isKill), FrameIdx)); } else { // FIXME: this spills LR immediately to memory in one step. To do this, // we use R11, which we know cannot be used in the prolog/epilog. This is // a hack. - NewMIs.push_back(BuildMI(MF, get(PPC::MFLR8), PPC::X11)); - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD)) + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11)); + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) .addReg(PPC::X11, false, false, isKill), FrameIdx)); } } else if (RC == PPC::F8RCRegisterClass) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFD)) + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) .addReg(SrcReg, false, false, isKill), FrameIdx)); } else if (RC == PPC::F4RCRegisterClass) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFS)) + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) .addReg(SrcReg, false, false, isKill), FrameIdx)); } else if (RC == PPC::CRRCRegisterClass) { if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { // FIXME (64-bit): Enable - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::SPILL_CR)) + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) .addReg(SrcReg, false, false, isKill), FrameIdx)); return true; @@ -399,18 +400,18 @@ // FIXME: We use R0 here, because it isn't available for RA. We need to // store the CR in the low 4-bits of the saved value. First, issue a MFCR // to save all of the CRBits. - NewMIs.push_back(BuildMI(MF, get(PPC::MFCR), PPC::R0)); + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCR), PPC::R0)); // If the saved register wasn't CR0, shift the bits left so that they are // in CR0's slot. if (SrcReg != PPC::CR0) { unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; // rlwinm r0, r0, ShiftBits, 0, 31. - NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0) + NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0) .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31)); } - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW)) + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) .addReg(PPC::R0, false, false, isKill), FrameIdx)); } @@ -446,9 +447,9 @@ // STVX VAL, 0, R0 // // FIXME: We use R0 here, because it isn't available for RA. - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0), + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), FrameIdx, 0, 0)); - NewMIs.push_back(BuildMI(MF, get(PPC::STVX)) + NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX)) .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0)); } else { assert(0 && "Unknown regclass!"); @@ -490,6 +491,7 @@ return; } + DebugLoc DL = DebugLoc::getUnknownLoc(); unsigned Opc = 0; if (RC == PPC::GPRCRegisterClass) { Opc = PPC::STW; @@ -505,7 +507,7 @@ assert(0 && "Unknown regclass!"); abort(); } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)) + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) .addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; @@ -644,7 +646,8 @@ assert(0 && "Unknown regclass!"); abort(); } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=64409&r1=64408&r2=64409&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Thu Feb 12 17:08:38 2009 @@ -167,6 +167,7 @@ const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; + DebugLoc DL = DebugLoc::getUnknownLoc(); if (RC == SP::IntRegsRegisterClass) Opc = SP::STri; else if (RC == SP::FPRegsRegisterClass) @@ -175,7 +176,7 @@ Opc = SP::STDFri; else assert(0 && "Can't load this register"); - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) @@ -222,7 +223,8 @@ Opc = SP::LDDFri; else assert(0 && "Can't load this register"); - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=64409&r1=64408&r2=64409&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Feb 12 17:08:38 2009 @@ -1850,7 +1850,8 @@ bool isAligned = (RI.getStackAlignment() >= 16) || RI.needsStackRealignment(MF); unsigned Opc = getStoreRegOpcode(RC, isAligned); - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = X86InstrAddOperand(MIB, Addr[i]); MIB.addReg(SrcReg, false, false, isKill); @@ -1915,7 +1916,8 @@ bool isAligned = (RI.getStackAlignment() >= 16) || RI.needsStackRealignment(MF); unsigned Opc = getLoadRegOpcode(RC, isAligned); - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = X86InstrAddOperand(MIB, Addr[i]); NewMIs.push_back(MIB); @@ -2287,6 +2289,7 @@ MemOp2RegOpTable.find((unsigned*)MI->getOpcode()); if (I == MemOp2RegOpTable.end()) return false; + DebugLoc dl = MI->getDebugLoc(); unsigned Opc = I->second.first; unsigned Index = I->second.second & 0xf; bool FoldedLoad = I->second.second & (1 << 4); Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=64409&r1=64408&r2=64409&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Feb 12 17:08:38 2009 @@ -396,7 +396,8 @@ MachineInstr *New = 0; if (Old->getOpcode() == getCallFrameSetupOpcode()) { - New = BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), + New = BuildMI(MF, Old->getDebugLoc(), + TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr).addReg(StackPtr).addImm(Amount); } else { assert(Old->getOpcode() == getCallFrameDestroyOpcode()); @@ -407,7 +408,7 @@ unsigned Opc = (Amount < 128) ? (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) : (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri); - New = BuildMI(MF, TII.get(Opc), StackPtr) + New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr) .addReg(StackPtr).addImm(Amount); } } @@ -428,8 +429,10 @@ unsigned Opc = (CalleeAmt < 128) ? (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) : (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri); + MachineInstr *Old = I; MachineInstr *New = - BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt); + BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), + StackPtr).addReg(StackPtr).addImm(CalleeAmt); // The EFLAGS implicit def is dead. New->getOperand(3).setIsDead(); @@ -723,6 +726,7 @@ bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) || !Fn->doesNotThrow() || UnwindTablesMandatory; + DebugLoc DL = DebugLoc::getUnknownLoc(); // Prepare for frame info. unsigned FrameLabelId = 0; @@ -757,7 +761,7 @@ // size is bigger than the callers. if (TailCallReturnAddrDelta < 0) { MachineInstr *MI = - BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri), + BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri), StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta); // The EFLAGS implicit def is dead. MI->getOperand(3).setIsDead(); @@ -778,18 +782,19 @@ MFI->setOffsetAdjustment(-NumBytes); // Save EBP into the appropriate stack slot... - BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) + BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) .addReg(FramePtr, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); if (needsFrameMoves) { // Mark effective beginning of when frame pointer becomes valid. FrameLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId); + BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId); } // Update EBP with the new base value... - BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) - .addReg(StackPtr); + BuildMI(MBB, MBBI, DL, + TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) + .addReg(StackPtr); // Mark the FramePtr as live-in in every block except the entry. for (MachineFunction::iterator I = next(MF.begin()), E = MF.end(); @@ -799,7 +804,7 @@ // Realign stack if (needsStackRealignment(MF)) { MachineInstr *MI = - BuildMI(MBB, MBBI, + BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr).addReg(StackPtr).addImm(-MaxAlign); // The EFLAGS implicit def is dead. @@ -812,7 +817,7 @@ if (needsFrameMoves) { // Mark effective beginning of when frame pointer is ready. ReadyLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId); + BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId); } // Skip the callee-saved push instructions. @@ -838,20 +843,22 @@ // necessary to ensure that the guard pages used by the OS virtual memory // manager are allocated in correct sequence. if (!isEAXAlive) { - BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes); - BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)) + BuildMI(MBB, MBBI,DL, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes); + BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32)) .addExternalSymbol("_alloca"); } else { // Save EAX - BuildMI(MBB, MBBI, TII.get(X86::PUSH32r)) + BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r)) .addReg(X86::EAX, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); // Allocate NumBytes-4 bytes on stack. We'll also use 4 already // allocated bytes for EAX. - BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4); - BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)) + BuildMI(MBB, MBBI, DL, + TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4); + BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32)) .addExternalSymbol("_alloca"); // Restore EAX - MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(X86::MOV32rm),X86::EAX), + MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), + X86::EAX), StackPtr, false, NumBytes-4); MBB.insert(MBBI, MI); } @@ -879,6 +886,7 @@ X86MachineFunctionInfo *X86FI = MF.getInfo(); MachineBasicBlock::iterator MBBI = prior(MBB.end()); unsigned RetOpcode = MBBI->getOpcode(); + DebugLoc DL = DebugLoc::getUnknownLoc(); switch (RetOpcode) { case X86::RET: @@ -911,7 +919,8 @@ NumBytes = FrameSize - CSSize; // pop EBP. - BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr); + BuildMI(MBB, MBBI, DL, + TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr); } else NumBytes = StackSize - CSSize; @@ -942,17 +951,17 @@ MBBI = prior(LastCSPop); } - BuildMI(MBB, MBBI, + BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr).addReg(FramePtr); } else if (MFI->hasVarSizedObjects()) { if (CSSize) { unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r; - MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(Opc), StackPtr), + MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr), FramePtr, false, -CSSize); MBB.insert(MBBI, MI); } else - BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), + BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr).addReg(FramePtr); } else { @@ -966,7 +975,7 @@ MBBI = prior(MBB.end()); MachineOperand &DestAddr = MBBI->getOperand(0); assert(DestAddr.isReg() && "Offset should be in register!"); - BuildMI(MBB, MBBI, + BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr).addReg(DestAddr.getReg()); // Tail call return: adjust the stack pointer and jump to callee @@ -992,12 +1001,12 @@ } // Jump to label or value in register. if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64) - BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)). + BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)). addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); else if (RetOpcode== X86::TCRETURNri64) { - BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg()); + BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg()); } else - BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg()); + BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg()); // Delete the pseudo instruction TCRETURN. MBB.erase(MBBI); } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) && Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp?rev=64409&r1=64408&r2=64409&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp Thu Feb 12 17:08:38 2009 @@ -150,12 +150,12 @@ MachineInstr *New; if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) { int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; - New=BuildMI(MF, TII.get(Opcode)) + New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode)) .addImm(Amount); } else { assert(Old->getOpcode() == XCore::ADJCALLSTACKUP); int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs; - New=BuildMI(MF, TII.get(Opcode), XCore::SP) + New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP) .addImm(Amount); } From dalej at apple.com Thu Feb 12 17:24:45 2009 From: dalej at apple.com (Dale Johannesen) Date: Thu, 12 Feb 2009 23:24:45 -0000 Subject: [llvm-commits] [llvm] r64410 - /llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Message-ID: <200902122324.n1CNOj1j021635@zion.cs.uiuc.edu> Author: johannes Date: Thu Feb 12 17:24:44 2009 New Revision: 64410 URL: http://llvm.org/viewvc/llvm-project?rev=64410&view=rev Log: Check in missing file. Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=64410&r1=64409&r2=64410&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Thu Feb 12 17:24:44 2009 @@ -213,8 +213,9 @@ Opc = Alpha::STQ; else abort(); + DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = - BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill); + BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) @@ -261,8 +262,9 @@ Opc = Alpha::LDQ; else abort(); + DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = - BuildMI(MF, get(Opc), DestReg); + BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) From mrs at apple.com Thu Feb 12 17:45:12 2009 From: mrs at apple.com (Mike Stump) Date: Thu, 12 Feb 2009 23:45:12 -0000 Subject: [llvm-commits] [llvm] r64412 - /llvm/trunk/Makefile.rules Message-ID: <200902122345.n1CNjCR7022485@zion.cs.uiuc.edu> Author: mrs Date: Thu Feb 12 17:45:11 2009 New Revision: 64412 URL: http://llvm.org/viewvc/llvm-project?rev=64412&view=rev Log: Avoid order files for now, as they aren't supported in 3.79. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=64412&r1=64411&r2=64412&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Thu Feb 12 17:45:11 2009 @@ -560,7 +560,7 @@ # in the file so they get built before dependencies #--------------------------------------------------------- -$(PROJ_bindir) $(PROJ_libdir) $(PROJ_includedir) $(PROJ_etcdir): +$(PROJ_bindir) $(PROJ_libdir) $(PROJ_includedir) $(PROJ_etcdir):: $(Verb) $(MKDIR) $@ # To create other directories, as needed, and timestamp their creation @@ -868,7 +868,7 @@ install-local:: $(DestSharedLib) -$(DestSharedLib): $(LibName.LA) | $(PROJ_libdir) +$(DestSharedLib): $(LibName.LA) $(PROJ_libdir) $(Echo) Installing $(BuildMode) Shared Library $(DestSharedLib) $(Verb) $(LTInstall) $(LibName.LA) $(DestSharedLib) $(Verb) $(LIBTOOL) --finish $(PROJ_libdir) @@ -935,7 +935,7 @@ else install-local:: $(DestBytecodeLib) -$(DestBytecodeLib): $(LibName.BCA) | $(BytecodeDestDir) +$(DestBytecodeLib): $(LibName.BCA) $(BytecodeDestDir) $(Echo) Installing $(BuildMode) Bytecode Archive $(DestBytecodeLib) $(Verb) $(DataInstall) $(LibName.BCA) $(DestBytecodeLib) @@ -982,7 +982,7 @@ install-local:: $(DestRelinkedLib) -$(DestRelinkedLib): $(LibName.O) | $(PROJ_libdir) +$(DestRelinkedLib): $(LibName.O) $(PROJ_libdir) $(Echo) Installing $(BuildMode) Object Library $(DestRelinkedLib) $(Verb) $(LTInstall) $(LibName.O) $(DestRelinkedLib) @@ -1022,7 +1022,7 @@ install-local:: $(DestArchiveLib) -$(DestArchiveLib): $(LibName.A) | $(PROJ_libdir) +$(DestArchiveLib): $(LibName.A) $(PROJ_libdir) $(Echo) Installing $(BuildMode) Archive Library $(DestArchiveLib) $(Verb) $(MKDIR) $(PROJ_libdir) $(Verb) $(LTInstall) $(LibName.A) $(DestArchiveLib) @@ -1084,7 +1084,7 @@ install-local:: $(DestTool) -$(DestTool): $(ToolBuildPath) | $(PROJ_bindir) +$(DestTool): $(ToolBuildPath) $(PROJ_bindir) $(Echo) Installing $(BuildMode) $(DestTool) $(Verb) $(ProgInstall) $(ToolBuildPath) $(DestTool) From echeng at apple.com Thu Feb 12 17:53:05 2009 From: echeng at apple.com (Evan Cheng) Date: Thu, 12 Feb 2009 15:53:05 -0800 Subject: [llvm-commits] [llvm] r64369 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll test/CodeGen/X86/2008-08-05-SpillerBug.ll In-Reply-To: References: <200902120859.n1C8xprn017627@zion.cs.uiuc.edu> Message-ID: On Feb 12, 2009, at 2:05 PM, Dan Gohman wrote: >> >> = >> ===================================================================== >> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp >> (original) >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu >> Feb 12 02:59:45 2009 >> @@ -916,7 +916,7 @@ >> if (PredSethiUllman > SethiUllmanNumber) { >> SethiUllmanNumber = PredSethiUllman; >> Extra = 0; >> - } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl()) >> + } else if (PredSethiUllman == SethiUllmanNumber) >> ++Extra; >> } > > Hi Evan, this change doesn't seem to be related to the other changes. > What is > it for? Control edges don't correspond to registers, so why should > they be > counted in the sethi-ullman number? That's just a redundant check. There was this " if (I->isCtrl()) continue; // ignore chain preds" earlier. Evan > > > Dan > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From mrs at apple.com Thu Feb 12 17:58:47 2009 From: mrs at apple.com (Mike Stump) Date: Thu, 12 Feb 2009 15:58:47 -0800 Subject: [llvm-commits] [llvm] r62746 - /llvm/trunk/Makefile.rules In-Reply-To: <237DA711-0A3F-4ED5-996D-471281F97961@apple.com> References: <200901220324.n0M3OMbY009941@zion.cs.uiuc.edu> <20090212061954.GA99037@pom.apple.com> <237DA711-0A3F-4ED5-996D-471281F97961@apple.com> Message-ID: On Feb 12, 2009, at 2:23 PM, Tanya Lattner wrote: > Mike - Can you re-implement this another way? Sure, I checked in a patch to avoid them (to trunk). 2.80 is 6 years old already, hopefully msys will update to a newer make sometime, and we can push forward. Until then there's going to be a few extra mkdir - p during a make install, which isn't the end of the world. From mrs at apple.com Thu Feb 12 17:59:54 2009 From: mrs at apple.com (Mike Stump) Date: Thu, 12 Feb 2009 15:59:54 -0800 Subject: [llvm-commits] [llvm] r62746 - /llvm/trunk/Makefile.rules In-Reply-To: <20090212061954.GA99037@pom.apple.com> References: <200901220324.n0M3OMbY009941@zion.cs.uiuc.edu> <20090212061954.GA99037@pom.apple.com> Message-ID: <5A85247E-834A-4923-82C1-DAAD0525EE47@apple.com> On Feb 11, 2009, at 10:19 PM, Julien Lerouge wrote: > This breaks install target on my old MingW for example. I don't mind > upgrading though. If you're adventure some, you can try trunk and see if the problem has been fixed. It should be. From gohman at apple.com Thu Feb 12 18:26:43 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 13 Feb 2009 00:26:43 -0000 Subject: [llvm-commits] [llvm] r64415 - in /llvm/trunk: lib/Transforms/Scalar/LoopStrengthReduce.cpp test/CodeGen/X86/lsr-sort.ll Message-ID: <200902130026.n1D0QhAH024019@zion.cs.uiuc.edu> Author: djg Date: Thu Feb 12 18:26:43 2009 New Revision: 64415 URL: http://llvm.org/viewvc/llvm-project?rev=64415&view=rev Log: Fix LSR's IV sorting function to explicitly sort by bitwidth after sorting by stride value. This prevents it from missing IV reuse opportunities in a host-sensitive manner. Added: llvm/trunk/test/CodeGen/X86/lsr-sort.ll Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=64415&r1=64414&r2=64415&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Thu Feb 12 18:26:43 2009 @@ -1772,12 +1772,19 @@ int64_t RV = RHSC->getValue()->getSExtValue(); uint64_t ALV = (LV < 0) ? -LV : LV; uint64_t ARV = (RV < 0) ? -RV : RV; - if (ALV == ARV) - return LV > RV; - else + if (ALV == ARV) { + if (LV != RV) + return LV > RV; + } else { return ALV < ARV; + } + + // If it's the same value but different type, sort by bit width so + // that we emit larger induction variables before smaller + // ones, letting the smaller be re-written in terms of larger ones. + return RHS->getBitWidth() < LHS->getBitWidth(); } - return (LHSC && !RHSC); + return LHSC && !RHSC; } }; } Added: llvm/trunk/test/CodeGen/X86/lsr-sort.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-sort.ll?rev=64415&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/lsr-sort.ll (added) +++ llvm/trunk/test/CodeGen/X86/lsr-sort.ll Thu Feb 12 18:26:43 2009 @@ -0,0 +1,22 @@ +; RUN: llvm-as < %s | llc -march=x86-64 > %t +; RUN: grep inc %t | count 1 +; RUN: not grep incw %t + + at X = common global i16 0 ; [#uses=1] + +define void @foo(i32 %N) nounwind { +entry: + %0 = icmp sgt i32 %N, 0 ; [#uses=1] + br i1 %0, label %bb, label %return + +bb: ; preds = %bb, %entry + %i.03 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; [#uses=2] + %1 = trunc i32 %i.03 to i16 ; [#uses=1] + volatile store i16 %1, i16* @X, align 2 + %indvar.next = add i32 %i.03, 1 ; [#uses=2] + %exitcond = icmp eq i32 %indvar.next, %N ; [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb, %entry + ret void +} From lattner at apple.com Thu Feb 12 18:30:06 2009 From: lattner at apple.com (Tanya Lattner) Date: Thu, 12 Feb 2009 16:30:06 -0800 Subject: [llvm-commits] [llvm] r62746 - /llvm/trunk/Makefile.rules In-Reply-To: References: <200901220324.n0M3OMbY009941@zion.cs.uiuc.edu> <20090212061954.GA99037@pom.apple.com> <237DA711-0A3F-4ED5-996D-471281F97961@apple.com> Message-ID: On Feb 12, 2009, at 3:58 PM, Mike Stump wrote: > On Feb 12, 2009, at 2:23 PM, Tanya Lattner wrote: >> Mike - Can you re-implement this another way? > > Sure, I checked in a patch to avoid them (to trunk). 2.80 is 6 years > old already, hopefully msys will update to a newer make sometime, and > we can push forward. Until then there's going to be a few extra > mkdir - > p during a make install, which isn't the end of the world. > _______________________________________________ Thanks Mike! I totally agree that its ancient and it would be great to not worry about it. Hopefully they upgrade soon. -Tanya > > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090212/b1e44374/attachment.html From eli.friedman at gmail.com Thu Feb 12 18:39:03 2009 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 12 Feb 2009 16:39:03 -0800 Subject: [llvm-commits] [llvm] r62746 - /llvm/trunk/Makefile.rules In-Reply-To: <1234464204.6663.1.camel@aslstation> References: <200901220324.n0M3OMbY009941@zion.cs.uiuc.edu> <20090212061954.GA99037@pom.apple.com> <1234464204.6663.1.camel@aslstation> Message-ID: On Thu, Feb 12, 2009 at 10:43 AM, Anton Korobeynikov wrote: > Hello, Mike > >> Ick, that's kinda annoying. I didn't realize they were newer than >> 3.79. Should we update the requirements? 3.80 was around in the 10.4 >> timeframe, though, I don't know which version the feature came in on. > This is mingw32 (well, actually msys), not darwin. And it still has 3.79 > shipped by default. Really? I haven't tried installing recently, but the SourceForge makes it looks like mingw distributes make 3.81. -Eli From jlerouge at apple.com Thu Feb 12 19:31:50 2009 From: jlerouge at apple.com (Julien Lerouge) Date: Thu, 12 Feb 2009 17:31:50 -0800 Subject: [llvm-commits] [llvm] r62746 - /llvm/trunk/Makefile.rules In-Reply-To: <5A85247E-834A-4923-82C1-DAAD0525EE47@apple.com> References: <200901220324.n0M3OMbY009941@zion.cs.uiuc.edu> <20090212061954.GA99037@pom.apple.com> <5A85247E-834A-4923-82C1-DAAD0525EE47@apple.com> Message-ID: <20090213013150.GC13334@pom.apple.com> On Thu, Feb 12, 2009 at 03:59:54PM -0800, Mike Stump wrote: > On Feb 11, 2009, at 10:19 PM, Julien Lerouge wrote: >> This breaks install target on my old MingW for example. I don't mind >> upgrading though. > > If you're adventure some, you can try trunk and see if the problem has been > fixed. It should be. Yep, just tried, MingW make 3.79.1 is happy now. Thanks, Julien -- Julien Lerouge PGP Key Id: 0xB1964A62 PGP Fingerprint: 392D 4BAD DB8B CE7F 4E5F FA3C 62DB 4AA7 B196 4A62 PGP Public Key from: keyserver.pgp.com From isanbard at gmail.com Thu Feb 12 20:01:04 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 13 Feb 2009 02:01:04 -0000 Subject: [llvm-commits] [llvm] r64427 - in /llvm/trunk/lib: CodeGen/SelectionDAG/FastISel.cpp CodeGen/SelectionDAG/LegalizeDAG.cpp CodeGen/SelectionDAG/SelectionDAGBuild.cpp CodeGen/VirtRegMap.cpp Target/X86/X86RegisterInfo.cpp Message-ID: <200902130201.n1D214dW027309@zion.cs.uiuc.edu> Author: void Date: Thu Feb 12 20:01:04 2009 New Revision: 64427 URL: http://llvm.org/viewvc/llvm-project?rev=64427&view=rev Log: Turn off the old way of handling debug information in the code generator. Use the new way, where all of the information is passed on SDNodes and machine instructions. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp llvm/trunk/lib/CodeGen/VirtRegMap.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=64427&r1=64426&r2=64427&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Feb 12 20:01:04 2009 @@ -323,32 +323,21 @@ CU.getFilename()); unsigned Line = SPI->getLine(); unsigned Col = SPI->getColumn(); - unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile); unsigned Idx = MF.getOrCreateDebugLocID(SrcFile, Line, Col); setCurDebugLoc(DebugLoc::get(Idx)); - const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); - BuildMI(MBB, DL, II).addImm(ID); } return true; } case Intrinsic::dbg_region_start: { DbgRegionStartInst *RSI = cast(I); - if (DW && DW->ValidDebugInfo(RSI->getContext())) { - unsigned ID = - DW->RecordRegionStart(cast(RSI->getContext())); - const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); - BuildMI(MBB, DL, II).addImm(ID); - } + if (DW && DW->ValidDebugInfo(RSI->getContext())) + DW->RecordRegionStart(cast(RSI->getContext())); return true; } case Intrinsic::dbg_region_end: { DbgRegionEndInst *REI = cast(I); - if (DW && DW->ValidDebugInfo(REI->getContext())) { - unsigned ID = - DW->RecordRegionEnd(cast(REI->getContext())); - const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); - BuildMI(MBB, DL, II).addImm(ID); - } + if (DW && DW->ValidDebugInfo(REI->getContext())) + DW->RecordRegionEnd(cast(REI->getContext())); return true; } case Intrinsic::dbg_func_start: { @@ -368,42 +357,14 @@ // function start. It will be emitted at asm emission time. However, // create a label if this is a beginning of inlined function. unsigned Line = Subprogram.getLineNumber(); - unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile); setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0))); - - if (DW->getRecordSourceLineCount() != 1) { - const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); - BuildMI(MBB, DL, II).addImm(LabelID); - } } return true; } - case Intrinsic::dbg_declare: { - DbgDeclareInst *DI = cast(I); - Value *Variable = DI->getVariable(); - if (DW && DW->ValidDebugInfo(Variable)) { - // Determine the address of the declared object. - Value *Address = DI->getAddress(); - if (BitCastInst *BCI = dyn_cast(Address)) - Address = BCI->getOperand(0); - AllocaInst *AI = dyn_cast(Address); - // Don't handle byval struct arguments or VLAs, for example. - if (!AI) break; - DenseMap::iterator SI = - StaticAllocaMap.find(AI); - if (SI == StaticAllocaMap.end()) break; // VLAs. - int FI = SI->second; - - // Determine the debug globalvariable. - GlobalValue *GV = cast(Variable); - - // Build the DECLARE instruction. - const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE); - BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV); - } + case Intrinsic::dbg_declare: + // FIXME: Do something correct here when declare stuff is working again. return true; - } case Intrinsic::eh_exception: { MVT VT = TLI.getValueType(I->getType()); switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=64427&r1=64426&r2=64427&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Feb 12 20:01:04 2009 @@ -1274,38 +1274,9 @@ switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) { case TargetLowering::Promote: default: assert(0 && "This action is not supported yet!"); - case TargetLowering::Expand: { - DwarfWriter *DW = DAG.getDwarfWriter(); - bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC, - MVT::Other); - bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other); - - const DbgStopPointSDNode *DSP = cast(Node); - GlobalVariable *CU_GV = cast(DSP->getCompileUnit()); - if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) { - DICompileUnit CU(cast(DSP->getCompileUnit())); - unsigned SrcFile = DW->RecordSource(CU.getDirectory(), - CU.getFilename()); - - unsigned Line = DSP->getLine(); - unsigned Col = DSP->getColumn(); - - // A bit self-referential to have DebugLoc on Debug_Loc nodes, but - // it won't hurt anything. - if (useDEBUG_LOC) { - SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32), - DAG.getConstant(Col, MVT::i32), - DAG.getConstant(SrcFile, MVT::i32) }; - Result = DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Ops, 4); - } else { - unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile); - Result = DAG.getLabel(ISD::DBG_LABEL, dl, Tmp1, ID); - } - } else { - Result = Tmp1; // chain - } + case TargetLowering::Expand: + Result = Tmp1; // chain break; - } case TargetLowering::Legal: { LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); if (Action == Legal && Tmp1 == Node->getOperand(0)) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=64427&r1=64426&r2=64427&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Thu Feb 12 20:01:04 2009 @@ -3912,24 +3912,18 @@ case Intrinsic::dbg_region_start: { DwarfWriter *DW = DAG.getDwarfWriter(); DbgRegionStartInst &RSI = cast(I); - if (DW && DW->ValidDebugInfo(RSI.getContext())) { - unsigned LabelID = - DW->RecordRegionStart(cast(RSI.getContext())); - DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), - getRoot(), LabelID)); - } + + if (DW && DW->ValidDebugInfo(RSI.getContext())) + DW->RecordRegionStart(cast(RSI.getContext())); return 0; } case Intrinsic::dbg_region_end: { DwarfWriter *DW = DAG.getDwarfWriter(); DbgRegionEndInst &REI = cast(I); - if (DW && DW->ValidDebugInfo(REI.getContext())) { - unsigned LabelID = - DW->RecordRegionEnd(cast(REI.getContext())); - DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), - getRoot(), LabelID)); - } + + if (DW && DW->ValidDebugInfo(REI.getContext())) + DW->RecordRegionEnd(cast(REI.getContext())); return 0; } @@ -3950,27 +3944,15 @@ // function start. It will be emitted at asm emission time. However, // create a label if this is a beginning of inlined function. unsigned Line = Subprogram.getLineNumber(); - unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile); - - if (DW->getRecordSourceLineCount() != 1) - DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), - getRoot(), LabelID)); - setCurDebugLoc(DebugLoc::get(DAG.getMachineFunction(). - getOrCreateDebugLocID(SrcFile, Line, 0))); + getOrCreateDebugLocID(SrcFile, Line, 0))); } return 0; } - case Intrinsic::dbg_declare: { - DwarfWriter *DW = DAG.getDwarfWriter(); - DbgDeclareInst &DI = cast(I); - Value *Variable = DI.getVariable(); - if (DW && DW->ValidDebugInfo(Variable)) - DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(), - getValue(DI.getAddress()), getValue(Variable))); + case Intrinsic::dbg_declare: + // FIXME: Do something correct here when declare stuff is working again. return 0; - } case Intrinsic::eh_exception: { if (!CurMBB->isLandingPad()) { Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=64427&r1=64426&r2=64427&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Thu Feb 12 20:01:04 2009 @@ -1278,7 +1278,7 @@ } /// rewriteMBB - Keep track of which spills are available even after the -/// register allocator is done with them. If possible, avid reloading vregs. +/// register allocator is done with them. If possible, avoid reloading vregs. void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM, AvailableSpills &Spills) { DOUT << "\n**** Local spiller rewriting MBB '" Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=64427&r1=64426&r2=64427&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Feb 12 20:01:04 2009 @@ -785,12 +785,6 @@ BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) .addReg(FramePtr, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); - if (needsFrameMoves) { - // Mark effective beginning of when frame pointer becomes valid. - FrameLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId); - } - // Update EBP with the new base value... BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) @@ -814,11 +808,9 @@ NumBytes = StackSize - X86FI->getCalleeSavedFrameSize(); unsigned ReadyLabelId = 0; - if (needsFrameMoves) { + if (needsFrameMoves) // Mark effective beginning of when frame pointer is ready. ReadyLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId); - } // Skip the callee-saved push instructions. while (MBBI != MBB.end() && From isanbard at gmail.com Thu Feb 12 20:16:36 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 13 Feb 2009 02:16:36 -0000 Subject: [llvm-commits] [llvm] r64428 - in /llvm/trunk/lib: CodeGen/SelectionDAG/FastISel.cpp CodeGen/SelectionDAG/LegalizeDAG.cpp CodeGen/SelectionDAG/SelectionDAGBuild.cpp CodeGen/VirtRegMap.cpp Target/X86/X86RegisterInfo.cpp Message-ID: <200902130216.n1D2GbNa027809@zion.cs.uiuc.edu> Author: void Date: Thu Feb 12 20:16:35 2009 New Revision: 64428 URL: http://llvm.org/viewvc/llvm-project?rev=64428&view=rev Log: Revert this. It was breaking stuff. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp llvm/trunk/lib/CodeGen/VirtRegMap.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=64428&r1=64427&r2=64428&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Feb 12 20:16:35 2009 @@ -323,21 +323,32 @@ CU.getFilename()); unsigned Line = SPI->getLine(); unsigned Col = SPI->getColumn(); + unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile); unsigned Idx = MF.getOrCreateDebugLocID(SrcFile, Line, Col); setCurDebugLoc(DebugLoc::get(Idx)); + const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); + BuildMI(MBB, DL, II).addImm(ID); } return true; } case Intrinsic::dbg_region_start: { DbgRegionStartInst *RSI = cast(I); - if (DW && DW->ValidDebugInfo(RSI->getContext())) - DW->RecordRegionStart(cast(RSI->getContext())); + if (DW && DW->ValidDebugInfo(RSI->getContext())) { + unsigned ID = + DW->RecordRegionStart(cast(RSI->getContext())); + const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); + BuildMI(MBB, DL, II).addImm(ID); + } return true; } case Intrinsic::dbg_region_end: { DbgRegionEndInst *REI = cast(I); - if (DW && DW->ValidDebugInfo(REI->getContext())) - DW->RecordRegionEnd(cast(REI->getContext())); + if (DW && DW->ValidDebugInfo(REI->getContext())) { + unsigned ID = + DW->RecordRegionEnd(cast(REI->getContext())); + const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); + BuildMI(MBB, DL, II).addImm(ID); + } return true; } case Intrinsic::dbg_func_start: { @@ -357,14 +368,42 @@ // function start. It will be emitted at asm emission time. However, // create a label if this is a beginning of inlined function. unsigned Line = Subprogram.getLineNumber(); + unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile); setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0))); + + if (DW->getRecordSourceLineCount() != 1) { + const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); + BuildMI(MBB, DL, II).addImm(LabelID); + } } return true; } - case Intrinsic::dbg_declare: - // FIXME: Do something correct here when declare stuff is working again. + case Intrinsic::dbg_declare: { + DbgDeclareInst *DI = cast(I); + Value *Variable = DI->getVariable(); + if (DW && DW->ValidDebugInfo(Variable)) { + // Determine the address of the declared object. + Value *Address = DI->getAddress(); + if (BitCastInst *BCI = dyn_cast(Address)) + Address = BCI->getOperand(0); + AllocaInst *AI = dyn_cast(Address); + // Don't handle byval struct arguments or VLAs, for example. + if (!AI) break; + DenseMap::iterator SI = + StaticAllocaMap.find(AI); + if (SI == StaticAllocaMap.end()) break; // VLAs. + int FI = SI->second; + + // Determine the debug globalvariable. + GlobalValue *GV = cast(Variable); + + // Build the DECLARE instruction. + const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE); + BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV); + } return true; + } case Intrinsic::eh_exception: { MVT VT = TLI.getValueType(I->getType()); switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=64428&r1=64427&r2=64428&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Feb 12 20:16:35 2009 @@ -1274,9 +1274,38 @@ switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) { case TargetLowering::Promote: default: assert(0 && "This action is not supported yet!"); - case TargetLowering::Expand: - Result = Tmp1; // chain + case TargetLowering::Expand: { + DwarfWriter *DW = DAG.getDwarfWriter(); + bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC, + MVT::Other); + bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other); + + const DbgStopPointSDNode *DSP = cast(Node); + GlobalVariable *CU_GV = cast(DSP->getCompileUnit()); + if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) { + DICompileUnit CU(cast(DSP->getCompileUnit())); + unsigned SrcFile = DW->RecordSource(CU.getDirectory(), + CU.getFilename()); + + unsigned Line = DSP->getLine(); + unsigned Col = DSP->getColumn(); + + // A bit self-referential to have DebugLoc on Debug_Loc nodes, but + // it won't hurt anything. + if (useDEBUG_LOC) { + SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32), + DAG.getConstant(Col, MVT::i32), + DAG.getConstant(SrcFile, MVT::i32) }; + Result = DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Ops, 4); + } else { + unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile); + Result = DAG.getLabel(ISD::DBG_LABEL, dl, Tmp1, ID); + } + } else { + Result = Tmp1; // chain + } break; + } case TargetLowering::Legal: { LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); if (Action == Legal && Tmp1 == Node->getOperand(0)) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=64428&r1=64427&r2=64428&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Thu Feb 12 20:16:35 2009 @@ -3912,18 +3912,24 @@ case Intrinsic::dbg_region_start: { DwarfWriter *DW = DAG.getDwarfWriter(); DbgRegionStartInst &RSI = cast(I); - - if (DW && DW->ValidDebugInfo(RSI.getContext())) - DW->RecordRegionStart(cast(RSI.getContext())); + if (DW && DW->ValidDebugInfo(RSI.getContext())) { + unsigned LabelID = + DW->RecordRegionStart(cast(RSI.getContext())); + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), + getRoot(), LabelID)); + } return 0; } case Intrinsic::dbg_region_end: { DwarfWriter *DW = DAG.getDwarfWriter(); DbgRegionEndInst &REI = cast(I); - - if (DW && DW->ValidDebugInfo(REI.getContext())) - DW->RecordRegionEnd(cast(REI.getContext())); + if (DW && DW->ValidDebugInfo(REI.getContext())) { + unsigned LabelID = + DW->RecordRegionEnd(cast(REI.getContext())); + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), + getRoot(), LabelID)); + } return 0; } @@ -3944,15 +3950,27 @@ // function start. It will be emitted at asm emission time. However, // create a label if this is a beginning of inlined function. unsigned Line = Subprogram.getLineNumber(); + unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile); + + if (DW->getRecordSourceLineCount() != 1) + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), + getRoot(), LabelID)); + setCurDebugLoc(DebugLoc::get(DAG.getMachineFunction(). - getOrCreateDebugLocID(SrcFile, Line, 0))); + getOrCreateDebugLocID(SrcFile, Line, 0))); } return 0; } - case Intrinsic::dbg_declare: - // FIXME: Do something correct here when declare stuff is working again. + case Intrinsic::dbg_declare: { + DwarfWriter *DW = DAG.getDwarfWriter(); + DbgDeclareInst &DI = cast(I); + Value *Variable = DI.getVariable(); + if (DW && DW->ValidDebugInfo(Variable)) + DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(), + getValue(DI.getAddress()), getValue(Variable))); return 0; + } case Intrinsic::eh_exception: { if (!CurMBB->isLandingPad()) { Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=64428&r1=64427&r2=64428&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Thu Feb 12 20:16:35 2009 @@ -1278,7 +1278,7 @@ } /// rewriteMBB - Keep track of which spills are available even after the -/// register allocator is done with them. If possible, avoid reloading vregs. +/// register allocator is done with them. If possible, avid reloading vregs. void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM, AvailableSpills &Spills) { DOUT << "\n**** Local spiller rewriting MBB '" Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=64428&r1=64427&r2=64428&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Feb 12 20:16:35 2009 @@ -785,6 +785,12 @@ BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) .addReg(FramePtr, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); + if (needsFrameMoves) { + // Mark effective beginning of when frame pointer becomes valid. + FrameLabelId = MMI->NextLabelID(); + BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId); + } + // Update EBP with the new base value... BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) @@ -808,9 +814,11 @@ NumBytes = StackSize - X86FI->getCalleeSavedFrameSize(); unsigned ReadyLabelId = 0; - if (needsFrameMoves) + if (needsFrameMoves) { // Mark effective beginning of when frame pointer is ready. ReadyLabelId = MMI->NextLabelID(); + BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId); + } // Skip the callee-saved push instructions. while (MBBI != MBB.end() && From dalej at apple.com Thu Feb 12 20:25:57 2009 From: dalej at apple.com (Dale Johannesen) Date: Fri, 13 Feb 2009 02:25:57 -0000 Subject: [llvm-commits] [llvm] r64429 - in /llvm/trunk/lib/Target/ARM: ARMConstantIslandPass.cpp ARMISelLowering.cpp ARMInstrInfo.cpp ARMLoadStoreOptimizer.cpp ARMRegisterInfo.h Message-ID: <200902130225.n1D2Pw4M028084@zion.cs.uiuc.edu> Author: johannes Date: Thu Feb 12 20:25:56 2009 New Revision: 64429 URL: http://llvm.org/viewvc/llvm-project?rev=64429&view=rev Log: Remove refs to non-DebugLoc versions of BuildMI from ARM. Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=64429&r1=64428&r2=64429&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Thu Feb 12 20:25:56 2009 @@ -301,7 +301,7 @@ // aligned. assert((Size & 3) == 0 && "CP Entry not multiple of 4 bytes!"); MachineInstr *CPEMI = - BuildMI(BB, TII->get(ARM::CONSTPOOL_ENTRY)) + BuildMI(BB, DebugLoc::getUnknownLoc(), TII->get(ARM::CONSTPOOL_ENTRY)) .addImm(i).addConstantPoolIndex(i).addImm(Size); CPEMIs.push_back(CPEMI); @@ -567,7 +567,10 @@ // Add an unconditional branch from OrigBB to NewBB. // Note the new unconditional branch is not being recorded. - BuildMI(OrigBB, TII->get(isThumb ? ARM::tB : ARM::B)).addMBB(NewBB); + // There doesn't seem to be meaningful DebugInfo available; this doesn't + // correspond to anything in the source. + BuildMI(OrigBB, DebugLoc::getUnknownLoc(), + TII->get(isThumb ? ARM::tB : ARM::B)).addMBB(NewBB); NumSplit++; // Update the CFG. All succs of OrigBB are now succs of NewBB. @@ -931,7 +934,8 @@ // targets will be exchanged, and the altered branch may be out of // range, so the machinery has to know about it. int UncondBr = isThumb ? ARM::tB : ARM::B; - BuildMI(UserMBB, TII->get(UncondBr)).addMBB(*NewMBB); + BuildMI(UserMBB, DebugLoc::getUnknownLoc(), + TII->get(UncondBr)).addMBB(*NewMBB); unsigned MaxDisp = getUnconditionalBrDisp(UncondBr); ImmBranches.push_back(ImmBranch(&UserMBB->back(), MaxDisp, false, UncondBr)); @@ -1042,7 +1046,8 @@ // Now that we have an island to add the CPE to, clone the original CPE and // add it to the island. - U.CPEMI = BuildMI(NewIsland, TII->get(ARM::CONSTPOOL_ENTRY)) + U.CPEMI = BuildMI(NewIsland, DebugLoc::getUnknownLoc(), + TII->get(ARM::CONSTPOOL_ENTRY)) .addImm(ID).addConstantPoolIndex(CPI).addImm(Size); CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1)); NumCPEs++; @@ -1240,11 +1245,12 @@ // Insert a new conditional branch and a new unconditional branch. // Also update the ImmBranch as well as adding a new entry for the new branch. - BuildMI(MBB, TII->get(MI->getOpcode())).addMBB(NextBB) - .addImm(CC).addReg(CCReg); + BuildMI(MBB, DebugLoc::getUnknownLoc(), + TII->get(MI->getOpcode())) + .addMBB(NextBB).addImm(CC).addReg(CCReg); Br.MI = &MBB->back(); BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back()); - BuildMI(MBB, TII->get(Br.UncondBr)).addMBB(DestBB); + BuildMI(MBB, DebugLoc::getUnknownLoc(), TII->get(Br.UncondBr)).addMBB(DestBB); BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back()); unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr); ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr)); @@ -1268,7 +1274,7 @@ if (MI->getOpcode() == ARM::tPOP_RET && MI->getOperand(0).getReg() == ARM::PC && MI->getNumExplicitOperands() == 1) { - BuildMI(MI->getParent(), TII->get(ARM::tBX_RET)); + BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET)); MI->eraseFromParent(); MadeChange = true; } Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=64429&r1=64428&r2=64429&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Feb 12 20:25:56 2009 @@ -1498,6 +1498,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const { const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + DebugLoc dl = MI->getDebugLoc(); switch (MI->getOpcode()) { default: assert(false && "Unexpected instr type to insert"); case ARM::tMOVCCr: { @@ -1519,7 +1520,7 @@ MachineFunction *F = BB->getParent(); MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); - BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB) + BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB) .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); F->insert(It, copy0MBB); F->insert(It, sinkMBB); @@ -1547,7 +1548,7 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg()) + BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=64429&r1=64428&r2=64429&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Thu Feb 12 20:25:56 2009 @@ -147,10 +147,11 @@ MachineBasicBlock::iterator I, unsigned DestReg, const MachineInstr *Orig) const { + DebugLoc dl = Orig->getDebugLoc(); if (Orig->getOpcode() == ARM::MOVi2pieces) { RI.emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImm(), Orig->getOperand(2).getImm(), - Orig->getOperand(3).getReg(), this, false); + Orig->getOperand(3).getReg(), this, false, dl); return; } @@ -447,6 +448,8 @@ unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const { + // FIXME this should probably have a DebugLoc argument + DebugLoc dl = DebugLoc::getUnknownLoc(); MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo(); int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B; @@ -459,17 +462,17 @@ if (FBB == 0) { if (Cond.empty()) // Unconditional branch? - BuildMI(&MBB, get(BOpc)).addMBB(TBB); + BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB); else - BuildMI(&MBB, get(BccOpc)).addMBB(TBB) + BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); return 1; } // Two-way conditional branch. - BuildMI(&MBB, get(BccOpc)).addMBB(TBB) + BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); - BuildMI(&MBB, get(BOpc)).addMBB(FBB); + BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB); return 2; } Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=64429&r1=64428&r2=64429&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Thu Feb 12 20:25:56 2009 @@ -116,6 +116,8 @@ ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, SmallVector, 8> &Regs, const TargetInstrInfo *TII) { + // FIXME would it be better to take a DL from one of the loads arbitrarily? + DebugLoc dl = DebugLoc::getUnknownLoc(); // Only a single register to load / store. Don't bother. unsigned NumRegs = Regs.size(); if (NumRegs <= 1) @@ -156,7 +158,7 @@ if (ImmedOffset == -1) return false; // Probably not worth it then. - BuildMI(MBB, MBBI, TII->get(BaseOpc), NewBase) + BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase) .addReg(Base, false, false, BaseKill).addImm(ImmedOffset) .addImm(Pred).addReg(PredReg).addReg(0); Base = NewBase; @@ -167,9 +169,11 @@ bool isDef = Opcode == ARM::LDR || Opcode == ARM::FLDS || Opcode == ARM::FLDD; Opcode = getLoadStoreMultipleOpcode(Opcode); MachineInstrBuilder MIB = (isAM4) - ? BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill) + ? BuildMI(MBB, MBBI, dl, TII->get(Opcode)) + .addReg(Base, false, false, BaseKill) .addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred).addReg(PredReg) - : BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill) + : BuildMI(MBB, MBBI, dl, TII->get(Opcode)) + .addReg(Base, false, false, BaseKill) .addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs)) .addImm(Pred).addReg(PredReg); for (unsigned i = 0; i != NumRegs; ++i) @@ -450,6 +454,7 @@ bool BaseKill = MI->getOperand(1).isKill(); unsigned Bytes = getLSMultipleTransferSize(MI); int Opcode = MI->getOpcode(); + DebugLoc dl = MI->getDebugLoc(); bool isAM2 = Opcode == ARM::LDR || Opcode == ARM::STR; if ((isAM2 && ARM_AM::getAM2Offset(MI->getOperand(3).getImm()) != 0) || (!isAM2 && ARM_AM::getAM5Offset(MI->getOperand(2).getImm()) != 0)) @@ -510,24 +515,25 @@ if (isLd) { if (isAM2) // LDR_PRE, LDR_POST; - BuildMI(MBB, MBBI, TII->get(NewOpc), MI->getOperand(0).getReg()) + BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) .addReg(Base, true) .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg); else // FLDMS, FLDMD - BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base, false, false, BaseKill) + BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) + .addReg(Base, false, false, BaseKill) .addImm(Offset).addImm(Pred).addReg(PredReg) .addReg(MI->getOperand(0).getReg(), true); } else { MachineOperand &MO = MI->getOperand(0); if (isAM2) // STR_PRE, STR_POST; - BuildMI(MBB, MBBI, TII->get(NewOpc), Base) + BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base) .addReg(MO.getReg(), false, false, MO.isKill()) .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg); else // FSTMS, FSTMD - BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base).addImm(Offset) + BuildMI(MBB, MBBI, dl, TII->get(NewOpc)).addReg(Base).addImm(Offset) .addImm(Pred).addReg(PredReg) .addReg(MO.getReg(), false, false, MO.isKill()); } Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h?rev=64429&r1=64428&r2=64429&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h Thu Feb 12 20:25:56 2009 @@ -38,7 +38,8 @@ MachineBasicBlock::iterator &MBBI, unsigned DestReg, int Val, unsigned Pred, unsigned PredReg, - const TargetInstrInfo *TII, bool isThumb) const; + const TargetInstrInfo *TII, bool isThumb, + DebugLoc dl) const; /// getRegisterNumbering - Given the enum value for some register, e.g. /// ARM::LR, return the number that it corresponds to (e.g. 14). From dalej at apple.com Thu Feb 12 20:26:21 2009 From: dalej at apple.com (Dale Johannesen) Date: Fri, 13 Feb 2009 02:26:21 -0000 Subject: [llvm-commits] [llvm] r64430 - /llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Message-ID: <200902130226.n1D2QLhe028108@zion.cs.uiuc.edu> Author: johannes Date: Thu Feb 12 20:26:21 2009 New Revision: 64430 URL: http://llvm.org/viewvc/llvm-project?rev=64430&view=rev Log: and one more file Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp?rev=64430&r1=64429&r2=64430&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Thu Feb 12 20:26:21 2009 @@ -179,15 +179,18 @@ unsigned DestReg, int Val, unsigned Pred, unsigned PredReg, const TargetInstrInfo *TII, - bool isThumb) const { + bool isThumb, + DebugLoc dl) const { MachineFunction &MF = *MBB.getParent(); MachineConstantPool *ConstantPool = MF.getConstantPool(); Constant *C = ConstantInt::get(Type::Int32Ty, Val); unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); if (isThumb) - BuildMI(MBB, MBBI, TII->get(ARM::tLDRcp),DestReg).addConstantPoolIndex(Idx); + BuildMI(MBB, MBBI, dl, + TII->get(ARM::tLDRcp),DestReg).addConstantPoolIndex(Idx); else - BuildMI(MBB, MBBI, TII->get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx) + BuildMI(MBB, MBBI, dl, TII->get(ARM::LDRcp), DestReg) + .addConstantPoolIndex(Idx) .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); } @@ -321,7 +324,8 @@ MachineBasicBlock::iterator &MBBI, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, - const TargetInstrInfo &TII) { + const TargetInstrInfo &TII, + DebugLoc dl) { bool isSub = NumBytes < 0; if (isSub) NumBytes = -NumBytes; @@ -338,7 +342,7 @@ assert(SOImmVal != -1 && "Bit extraction didn't work?"); // Build the new ADD / SUB. - BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) + BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) .addReg(BaseReg, false, false, true).addImm(SOImmVal) .addImm((unsigned)Pred).addReg(PredReg).addReg(0); BaseReg = DestReg; @@ -379,7 +383,8 @@ unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, - const ARMRegisterInfo& MRI) { + const ARMRegisterInfo& MRI, + DebugLoc dl) { bool isHigh = !MRI.isLowRegister(DestReg) || (BaseReg != 0 && !MRI.isLowRegister(BaseReg)); bool isSub = false; @@ -395,28 +400,30 @@ if (DestReg == ARM::SP) { assert(BaseReg == ARM::SP && "Unexpected!"); LdReg = ARM::R3; - BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12) + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R12) .addReg(ARM::R3, false, false, true); } if (NumBytes <= 255 && NumBytes >= 0) - BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); else if (NumBytes < 0 && NumBytes >= -255) { - BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); - BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg) + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); + BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg) .addReg(LdReg, false, false, true); } else - MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0,&TII,true); + MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, &TII, + true, dl); // Emit add / sub. int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); - const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg); + const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, + TII.get(Opc), DestReg); if (DestReg == ARM::SP || isSub) MIB.addReg(BaseReg).addReg(LdReg, false, false, true); else MIB.addReg(LdReg).addReg(BaseReg, false, false, true); if (DestReg == ARM::SP) - BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3) + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R3) .addReg(ARM::R12, false, false, true); } @@ -427,7 +434,8 @@ MachineBasicBlock::iterator &MBBI, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, - const ARMRegisterInfo& MRI) { + const ARMRegisterInfo& MRI, + DebugLoc dl) { bool isSub = NumBytes < 0; unsigned Bytes = (unsigned)NumBytes; if (isSub) Bytes = -NumBytes; @@ -473,7 +481,8 @@ if (NumMIs > Threshold) { // This will expand into too many instructions. Load the immediate from a // constpool entry. - emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII, MRI); + emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII, + MRI, dl); return; } @@ -483,10 +492,10 @@ unsigned Chunk = (1 << 3) - 1; unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; Bytes -= ThisVal; - BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) + BuildMI(MBB, MBBI, dl,TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) .addReg(BaseReg, false, false, true).addImm(ThisVal); } else { - BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg) + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) .addReg(BaseReg, false, false, true); } BaseReg = DestReg; @@ -499,10 +508,11 @@ ThisVal /= Scale; // Build the new tADD / tSUB. if (isTwoAddr) - BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); + BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) + .addReg(DestReg).addImm(ThisVal); else { bool isKill = BaseReg != ARM::SP; - BuildMI(MBB, MBBI, TII.get(Opc), DestReg) + BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) .addReg(BaseReg, false, false, isKill).addImm(ThisVal); BaseReg = DestReg; @@ -520,7 +530,7 @@ } if (ExtraOpc) - BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg) + BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg) .addReg(DestReg, false, false, true) .addImm(((unsigned)NumBytes) & 3); } @@ -529,12 +539,14 @@ void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, bool isThumb, const TargetInstrInfo &TII, - const ARMRegisterInfo& MRI) { + const ARMRegisterInfo& MRI, + DebugLoc dl) { if (isThumb) - emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII, MRI); + emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII, + MRI, dl); else emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, - Pred, PredReg, TII); + Pred, PredReg, TII, dl); } void ARMRegisterInfo:: @@ -545,6 +557,7 @@ // ADJCALLSTACKDOWN -> sub, sp, sp, amount // ADJCALLSTACKUP -> add, sp, sp, amount MachineInstr *Old = I; + DebugLoc dl = Old->getDebugLoc(); unsigned Amount = Old->getOperand(0).getImm(); if (Amount != 0) { ARMFunctionInfo *AFI = MF.getInfo(); @@ -562,12 +575,12 @@ if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg(); - emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII, *this); + emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII, *this, dl); } else { // Note: PredReg is operand 3 for ADJCALLSTACKUP. unsigned PredReg = isThumb ? 0 : Old->getOperand(3).getReg(); assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); - emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII, *this); + emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII, *this, dl); } } } @@ -580,18 +593,19 @@ MachineBasicBlock::iterator &MBBI, unsigned DestReg, int Imm, const TargetInstrInfo &TII, - const ARMRegisterInfo& MRI) { + const ARMRegisterInfo& MRI, + DebugLoc dl) { bool isSub = Imm < 0; if (isSub) Imm = -Imm; int Chunk = (1 << 8) - 1; int ThisVal = (Imm > Chunk) ? Chunk : Imm; Imm -= ThisVal; - BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal); + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal); if (Imm > 0) - emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI); + emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl); if (isSub) - BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg) + BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), DestReg) .addReg(DestReg, false, false, true); } @@ -617,6 +631,7 @@ MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo(); bool isThumb = AFI->isThumbFunction(); + DebugLoc dl = MI.getDebugLoc(); while (!MI.getOperand(i).isFI()) { ++i; @@ -723,7 +738,8 @@ // MI would expand into a large number of instructions. Don't try to // simplify the immediate. if (NumMIs > 2) { - emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII, *this); + emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII, + *this, dl); MBB.erase(II); return; } @@ -736,12 +752,13 @@ MI.getOperand(i+1).ChangeToImmediate(Mask); Offset = (Offset - Mask * Scale); MachineBasicBlock::iterator NII = next(II); - emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII, *this); + emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII, + *this, dl); } else { // Translate r0 = add sp, -imm to // r0 = -imm (this is then translated into a series of instructons) // r0 = add r0, sp - emitThumbConstant(MBB, II, DestReg, Offset, TII, *this); + emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl); MI.setDesc(TII.get(ARM::tADDhirr)); MI.getOperand(i).ChangeToRegister(DestReg, false, false, true); MI.getOperand(i+1).ChangeToRegister(FrameReg, false); @@ -845,13 +862,15 @@ if (Opcode == ARM::tRestore) { if (FrameReg == ARM::SP) emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg, - Offset, false, TII, *this); + Offset, false, TII, *this, dl); else { - emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, true); + emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, + true, dl); UseRR = true; } } else - emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, *this); + emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, + *this, dl); MI.setDesc(TII.get(ARM::tLDR)); MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); if (UseRR) @@ -872,23 +891,25 @@ unsigned TmpReg = ARM::R3; bool UseRR = false; if (ValReg == ARM::R3) { - BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) + BuildMI(MBB, II, dl, TII.get(ARM::tMOVr), ARM::R12) .addReg(ARM::R2, false, false, true); TmpReg = ARM::R2; } if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) - BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) + BuildMI(MBB, II, dl, TII.get(ARM::tMOVr), ARM::R12) .addReg(ARM::R3, false, false, true); if (Opcode == ARM::tSpill) { if (FrameReg == ARM::SP) emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg, - Offset, false, TII, *this); + Offset, false, TII, *this, dl); else { - emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, true); + emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, + true, dl); UseRR = true; } } else - emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, *this); + emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, + *this, dl); MI.setDesc(TII.get(ARM::tSTR)); MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); if (UseRR) // Use [reg, reg] addrmode. @@ -898,10 +919,10 @@ MachineBasicBlock::iterator NII = next(II); if (ValReg == ARM::R3) - BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2) + BuildMI(MBB, NII, dl, TII.get(ARM::tMOVr), ARM::R2) .addReg(ARM::R12, false, false, true); if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) - BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3) + BuildMI(MBB, NII, dl, TII.get(ARM::tMOVr), ARM::R3) .addReg(ARM::R12, false, false, true); } else assert(false && "Unexpected opcode!"); @@ -919,7 +940,7 @@ ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, - isSub ? -Offset : Offset, Pred, PredReg, TII); + isSub ? -Offset : Offset, Pred, PredReg, TII, dl); MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); } } @@ -1201,6 +1222,7 @@ unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); unsigned NumBytes = MFI->getStackSize(); const std::vector &CSI = MFI->getCalleeSavedInfo(); + DebugLoc dl = DebugLoc::getUnknownLoc(); if (isThumb) { // Check if R3 is live in. It might have to be used as a scratch register. @@ -1223,11 +1245,12 @@ int FramePtrSpillFI = 0; if (VARegSaveSize) - emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII, *this); + emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII, + *this, dl); if (!AFI->hasStackFrame()) { if (NumBytes != 0) - emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this); + emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl); return; } @@ -1267,7 +1290,7 @@ if (!isThumb) { // Build the new SUBri to adjust SP for integer callee-save spill area 1. - emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII, *this); + emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII, *this, dl); movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) ++MBBI; @@ -1276,18 +1299,19 @@ // previous FP. if (STI.isTargetDarwin() || hasFP(MF)) { MachineInstrBuilder MIB = - BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr) + BuildMI(MBB, MBBI, dl, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), + FramePtr) .addFrameIndex(FramePtrSpillFI).addImm(0); if (!isThumb) AddDefaultCC(AddDefaultPred(MIB)); } if (!isThumb) { // Build the new SUBri to adjust SP for integer callee-save spill area 2. - emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII, *this); + emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII, *this, dl); // Build the new SUBri to adjust SP for FP callee-save spill area. movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); - emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII, *this); + emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII, *this, dl); } // Determine starting offsets of spill areas. @@ -1304,7 +1328,7 @@ // Insert it after all the callee-save spills. if (!isThumb) movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); - emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this); + emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl); } if(STI.isTargetELF() && hasFP(MF)) { @@ -1334,6 +1358,7 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { + DebugLoc dl = DebugLoc::getUnknownLoc(); MachineBasicBlock::iterator MBBI = prior(MBB.end()); assert((MBBI->getOpcode() == ARM::BX_RET || MBBI->getOpcode() == ARM::tBX_RET || @@ -1347,7 +1372,7 @@ int NumBytes = (int)MFI->getStackSize(); if (!AFI->hasStackFrame()) { if (NumBytes != 0) - emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this); + emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl); } else { // Unwind MBBI to point to first LDR / FLDD. const unsigned *CSRegs = getCalleeSavedRegs(); @@ -1370,17 +1395,19 @@ // frame pointer stack slot or target is ELF and the function has FP. if (NumBytes) emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, - TII, *this); + TII, *this, dl); else - BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr); + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr); } else { if (MBBI->getOpcode() == ARM::tBX_RET && &MBB.front() != MBBI && prior(MBBI)->getOpcode() == ARM::tPOP) { MachineBasicBlock::iterator PMBBI = prior(MBBI); - emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this); + emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, + *this, dl); } else - emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this); + emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, + *this, dl); } } else { // Darwin ABI requires FP to point to the stack slot that contains the @@ -1394,31 +1421,31 @@ AFI->getDPRCalleeSavedAreaOffset()|| hasFP(MF)) { if (NumBytes) - BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) + BuildMI(MBB, MBBI, dl, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) .addImm(NumBytes) .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); else - BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr) + BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr) .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); } } else if (NumBytes) { - emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII, *this); + emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII, *this, dl); } // Move SP to start of integer callee save spill area 2. movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0, - false, TII, *this); + false, TII, *this, dl); // Move SP to start of integer callee save spill area 1. movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0, - false, TII, *this); + false, TII, *this, dl); // Move SP to SP upon entry to the function. movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0, - false, TII, *this); + false, TII, *this, dl); } } @@ -1426,12 +1453,13 @@ if (isThumb) // Epilogue for vararg functions: pop LR to R3 and branch off it. // FIXME: Verify this is still ok when R3 is no longer being reserved. - BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3); + BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)).addReg(ARM::R3); - emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII, *this); + emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII, + *this, dl); if (isThumb) { - BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); + BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); MBB.erase(MBBI); } } From dalej at apple.com Thu Feb 12 20:27:39 2009 From: dalej at apple.com (Dale Johannesen) Date: Fri, 13 Feb 2009 02:27:39 -0000 Subject: [llvm-commits] [llvm] r64431 - in /llvm/trunk/lib/Target/PowerPC: PPCBranchSelector.cpp PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.cpp PPCRegisterInfo.cpp Message-ID: <200902130227.n1D2Reku028153@zion.cs.uiuc.edu> Author: johannes Date: Thu Feb 12 20:27:39 2009 New Revision: 64431 URL: http://llvm.org/viewvc/llvm-project?rev=64431&view=rev Log: Remove refs to non-DebugLoc version of BuildMI from PowerPC. Modified: llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp?rev=64431&r1=64430&r2=64431&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp Thu Feb 12 20:27:39 2009 @@ -145,13 +145,14 @@ unsigned CRReg = I->getOperand(1).getReg(); MachineInstr *OldBranch = I; + DebugLoc dl = OldBranch->getDebugLoc(); // Jump over the uncond branch inst (i.e. $PC+8) on opposite condition. - BuildMI(MBB, I, TII->get(PPC::BCC)) + BuildMI(MBB, I, dl, TII->get(PPC::BCC)) .addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2); // Uncond branch to the real destination. - I = BuildMI(MBB, I, TII->get(PPC::B)).addMBB(Dest); + I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest); // Remove the old branch from the function. OldBranch->eraseFromParent(); Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=64431&r1=64430&r2=64431&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Feb 12 20:27:39 2009 @@ -243,15 +243,16 @@ const TargetInstrInfo &TII = *TM.getInstrInfo(); MachineBasicBlock &EntryBB = *Fn.begin(); + DebugLoc dl = DebugLoc::getUnknownLoc(); // Emit the following code into the entry block: // InVRSAVE = MFVRSAVE // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE // MTVRSAVE UpdatedVRSAVE MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point - BuildMI(EntryBB, IP, TII.get(PPC::MFVRSAVE), InVRSAVE); - BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE), + BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE); + BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE), UpdatedVRSAVE).addReg(InVRSAVE); - BuildMI(EntryBB, IP, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); + BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); // Find all return blocks, outputting a restore in each epilog. for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { @@ -265,7 +266,7 @@ IP = I2; // Emit: MTVRSAVE InVRSave - BuildMI(*BB, IP, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); + BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); } } } @@ -280,15 +281,16 @@ // Insert the set of GlobalBaseReg into the first MBB of the function MachineBasicBlock &FirstMBB = BB->getParent()->front(); MachineBasicBlock::iterator MBBI = FirstMBB.begin(); + DebugLoc dl = DebugLoc::getUnknownLoc(); if (PPCLowering.getPointerTy() == MVT::i32) { GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass); - BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR); - BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg); + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR), PPC::LR); + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); } else { GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass); - BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8); - BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg); + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8), PPC::LR8); + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg); } } return CurDAG->getRegister(GlobalBaseReg, Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=64431&r1=64430&r2=64431&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Feb 12 20:27:39 2009 @@ -3966,6 +3966,7 @@ unsigned ptrA = MI->getOperand(1).getReg(); unsigned ptrB = MI->getOperand(2).getReg(); unsigned incr = MI->getOperand(3).getReg(); + DebugLoc dl = MI->getDebugLoc(); MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); @@ -3991,13 +3992,13 @@ // bne- loopMBB // fallthrough --> exitMBB BB = loopMBB; - BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) + BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) .addReg(ptrA).addReg(ptrB); if (BinOpcode) - BuildMI(BB, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); - BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) + BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); + BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) .addReg(TmpReg).addReg(ptrA).addReg(ptrB); - BuildMI(BB, TII->get(PPC::BCC)) + BuildMI(BB, dl, TII->get(PPC::BCC)) .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); BB->addSuccessor(loopMBB); BB->addSuccessor(exitMBB); @@ -4030,6 +4031,7 @@ unsigned ptrA = MI->getOperand(1).getReg(); unsigned ptrB = MI->getOperand(2).getReg(); unsigned incr = MI->getOperand(3).getReg(); + DebugLoc dl = MI->getDebugLoc(); MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); @@ -4082,47 +4084,47 @@ if (ptrA!=PPC::R0) { Ptr1Reg = RegInfo.createVirtualRegister(RC); - BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) + BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) .addReg(ptrA).addReg(ptrB); } else { Ptr1Reg = ptrB; } - BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) + BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); - BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) + BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); if (is64bit) - BuildMI(BB, TII->get(PPC::RLDICR), PtrReg) + BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) .addReg(Ptr1Reg).addImm(0).addImm(61); else - BuildMI(BB, TII->get(PPC::RLWINM), PtrReg) + BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); - BuildMI(BB, TII->get(PPC::SLW), Incr2Reg) + BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg) .addReg(incr).addReg(ShiftReg); if (is8bit) - BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255); + BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); else { - BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0); - BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535); + BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); + BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535); } - BuildMI(BB, TII->get(PPC::SLW), MaskReg) + BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) .addReg(Mask2Reg).addReg(ShiftReg); BB = loopMBB; - BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg) + BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) .addReg(PPC::R0).addReg(PtrReg); if (BinOpcode) - BuildMI(BB, TII->get(BinOpcode), TmpReg) + BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) .addReg(Incr2Reg).addReg(TmpDestReg); - BuildMI(BB, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) + BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) .addReg(TmpDestReg).addReg(MaskReg); - BuildMI(BB, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) + BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) .addReg(TmpReg).addReg(MaskReg); - BuildMI(BB, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) + BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) .addReg(Tmp3Reg).addReg(Tmp2Reg); - BuildMI(BB, TII->get(PPC::STWCX)) + BuildMI(BB, dl, TII->get(PPC::STWCX)) .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg); - BuildMI(BB, TII->get(PPC::BCC)) + BuildMI(BB, dl, TII->get(PPC::BCC)) .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); BB->addSuccessor(loopMBB); BB->addSuccessor(exitMBB); @@ -4130,7 +4132,7 @@ // exitMBB: // ... BB = exitMBB; - BuildMI(BB, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg); + BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg); return BB; } @@ -4167,7 +4169,8 @@ MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); unsigned SelectPred = MI->getOperand(4).getImm(); - BuildMI(BB, TII->get(PPC::BCC)) + DebugLoc dl = MI->getDebugLoc(); + BuildMI(BB, dl, TII->get(PPC::BCC)) .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); F->insert(It, copy0MBB); F->insert(It, sinkMBB); @@ -4190,7 +4193,7 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg()) + BuildMI(BB, dl, TII->get(PPC::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); } @@ -4266,6 +4269,7 @@ unsigned ptrB = MI->getOperand(2).getReg(); unsigned oldval = MI->getOperand(3).getReg(); unsigned newval = MI->getOperand(4).getReg(); + DebugLoc dl = MI->getDebugLoc(); MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); @@ -4294,26 +4298,26 @@ // st[wd]cx. dest, ptr // exitBB: BB = loop1MBB; - BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) + BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) .addReg(ptrA).addReg(ptrB); - BuildMI(BB, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) + BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) .addReg(oldval).addReg(dest); - BuildMI(BB, TII->get(PPC::BCC)) + BuildMI(BB, dl, TII->get(PPC::BCC)) .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); BB->addSuccessor(loop2MBB); BB->addSuccessor(midMBB); BB = loop2MBB; - BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) + BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) .addReg(newval).addReg(ptrA).addReg(ptrB); - BuildMI(BB, TII->get(PPC::BCC)) + BuildMI(BB, dl, TII->get(PPC::BCC)) .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); - BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB); + BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); BB->addSuccessor(loop1MBB); BB->addSuccessor(exitMBB); BB = midMBB; - BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) + BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) .addReg(dest).addReg(ptrA).addReg(ptrB); BB->addSuccessor(exitMBB); @@ -4333,6 +4337,7 @@ unsigned ptrB = MI->getOperand(2).getReg(); unsigned oldval = MI->getOperand(3).getReg(); unsigned newval = MI->getOperand(4).getReg(); + DebugLoc dl = MI->getDebugLoc(); MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); @@ -4397,69 +4402,73 @@ // srw dest, tmpDest, shift if (ptrA!=PPC::R0) { Ptr1Reg = RegInfo.createVirtualRegister(RC); - BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) + BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) .addReg(ptrA).addReg(ptrB); } else { Ptr1Reg = ptrB; } - BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) + BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); - BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) + BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); if (is64bit) - BuildMI(BB, TII->get(PPC::RLDICR), PtrReg) + BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) .addReg(Ptr1Reg).addImm(0).addImm(61); else - BuildMI(BB, TII->get(PPC::RLWINM), PtrReg) + BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); - BuildMI(BB, TII->get(PPC::SLW), NewVal2Reg) + BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) .addReg(newval).addReg(ShiftReg); - BuildMI(BB, TII->get(PPC::SLW), OldVal2Reg) + BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) .addReg(oldval).addReg(ShiftReg); if (is8bit) - BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255); + BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); else { - BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0); - BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535); + BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); + BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) + .addReg(Mask3Reg).addImm(65535); } - BuildMI(BB, TII->get(PPC::SLW), MaskReg) + BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) .addReg(Mask2Reg).addReg(ShiftReg); - BuildMI(BB, TII->get(PPC::AND), NewVal3Reg) + BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg) .addReg(NewVal2Reg).addReg(MaskReg); - BuildMI(BB, TII->get(PPC::AND), OldVal3Reg) + BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg) .addReg(OldVal2Reg).addReg(MaskReg); BB = loop1MBB; - BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg) + BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) .addReg(PPC::R0).addReg(PtrReg); - BuildMI(BB, TII->get(PPC::AND),TmpReg).addReg(TmpDestReg).addReg(MaskReg); - BuildMI(BB, TII->get(PPC::CMPW), PPC::CR0) + BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) + .addReg(TmpDestReg).addReg(MaskReg); + BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0) .addReg(TmpReg).addReg(OldVal3Reg); - BuildMI(BB, TII->get(PPC::BCC)) + BuildMI(BB, dl, TII->get(PPC::BCC)) .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); BB->addSuccessor(loop2MBB); BB->addSuccessor(midMBB); BB = loop2MBB; - BuildMI(BB, TII->get(PPC::ANDC),Tmp2Reg).addReg(TmpDestReg).addReg(MaskReg); - BuildMI(BB, TII->get(PPC::OR),Tmp4Reg).addReg(Tmp2Reg).addReg(NewVal3Reg); - BuildMI(BB, TII->get(PPC::STWCX)).addReg(Tmp4Reg) + BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg) + .addReg(TmpDestReg).addReg(MaskReg); + BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg) + .addReg(Tmp2Reg).addReg(NewVal3Reg); + BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg) .addReg(PPC::R0).addReg(PtrReg); - BuildMI(BB, TII->get(PPC::BCC)) + BuildMI(BB, dl, TII->get(PPC::BCC)) .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); - BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB); + BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); BB->addSuccessor(loop1MBB); BB->addSuccessor(exitMBB); BB = midMBB; - BuildMI(BB, TII->get(PPC::STWCX)).addReg(TmpDestReg) + BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg) .addReg(PPC::R0).addReg(PtrReg); BB->addSuccessor(exitMBB); // exitMBB: // ... BB = exitMBB; - BuildMI(BB, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg); + BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg); } else { assert(0 && "Unexpected instr type to insert"); } Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=64431&r1=64430&r2=64431&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Thu Feb 12 20:27:39 2009 @@ -292,6 +292,8 @@ PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const { + // FIXME this should probably have a DebugLoc argument + DebugLoc dl = DebugLoc::getUnknownLoc(); // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && @@ -300,17 +302,17 @@ // One-way branch. if (FBB == 0) { if (Cond.empty()) // Unconditional branch - BuildMI(&MBB, get(PPC::B)).addMBB(TBB); + BuildMI(&MBB, dl, get(PPC::B)).addMBB(TBB); else // Conditional branch - BuildMI(&MBB, get(PPC::BCC)) + BuildMI(&MBB, dl, get(PPC::BCC)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); return 1; } // Two-way Conditional Branch. - BuildMI(&MBB, get(PPC::BCC)) + BuildMI(&MBB, dl, get(PPC::BCC)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); - BuildMI(&MBB, get(PPC::B)).addMBB(FBB); + BuildMI(&MBB, dl, get(PPC::B)).addMBB(FBB); return 2; } Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=64431&r1=64430&r2=64431&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Feb 12 20:27:39 2009 @@ -426,18 +426,20 @@ unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; + MachineInstr *MI = I; + DebugLoc dl = MI->getDebugLoc(); if (isInt16(CalleeAmt)) { - BuildMI(MBB, I, TII.get(ADDIInstr), StackReg).addReg(StackReg). + BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg). addImm(CalleeAmt); } else { MachineBasicBlock::iterator MBBI = I; - BuildMI(MBB, MBBI, TII.get(LISInstr), TmpReg) + BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) .addImm(CalleeAmt >> 16); - BuildMI(MBB, MBBI, TII.get(ORIInstr), TmpReg) + BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) .addReg(TmpReg, false, false, true) .addImm(CalleeAmt & 0xFFFF); - BuildMI(MBB, MBBI, TII.get(ADDInstr)) + BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) .addReg(StackReg) .addReg(StackReg) .addReg(TmpReg); @@ -481,6 +483,7 @@ MachineFrameInfo *MFI = MF.getFrameInfo(); // Determine whether 64-bit pointers are used. bool LP64 = Subtarget.isPPC64(); + DebugLoc dl = MI.getDebugLoc(); // Get the maximum call stack size. unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); @@ -511,20 +514,20 @@ Reg = PPC::R0; if (MaxAlign < TargetAlign && isInt16(FrameSize)) { - BuildMI(MBB, II, TII.get(PPC::ADDI), Reg) + BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) .addReg(PPC::R31) .addImm(FrameSize); } else if (LP64) { if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. - BuildMI(MBB, II, TII.get(PPC::LD), Reg) + BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) .addImm(0) .addReg(PPC::X1); else - BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) + BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) .addImm(0) .addReg(PPC::X1); } else { - BuildMI(MBB, II, TII.get(PPC::LWZ), Reg) + BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) .addImm(0) .addReg(PPC::R1); } @@ -533,39 +536,39 @@ // address of new allocated space. if (LP64) { if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. - BuildMI(MBB, II, TII.get(PPC::STDUX)) + BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) .addReg(Reg, false, false, true) .addReg(PPC::X1) .addReg(MI.getOperand(1).getReg()); else - BuildMI(MBB, II, TII.get(PPC::STDUX)) + BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) .addReg(PPC::X0, false, false, true) .addReg(PPC::X1) .addReg(MI.getOperand(1).getReg()); if (!MI.getOperand(1).isKill()) - BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) + BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) .addReg(PPC::X1) .addImm(maxCallFrameSize); else // Implicitly kill the register. - BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) + BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) .addReg(PPC::X1) .addImm(maxCallFrameSize) .addReg(MI.getOperand(1).getReg(), false, true, true); } else { - BuildMI(MBB, II, TII.get(PPC::STWUX)) + BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) .addReg(Reg, false, false, true) .addReg(PPC::R1) .addReg(MI.getOperand(1).getReg()); if (!MI.getOperand(1).isKill()) - BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) + BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) .addReg(PPC::R1) .addImm(maxCallFrameSize); else // Implicitly kill the register. - BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) + BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) .addReg(PPC::R1) .addImm(maxCallFrameSize) .addReg(MI.getOperand(1).getReg(), false, true, true); @@ -590,6 +593,7 @@ MachineInstr &MI = *II; // ; SPILL_CR , , // Get the instruction's basic block. MachineBasicBlock &MBB = *MI.getParent(); + DebugLoc dl = MI.getDebugLoc(); const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; @@ -599,10 +603,10 @@ // We need to store the CR in the low 4-bits of the saved value. First, issue // an MFCR to save all of the CRBits. Add an implicit kill of the CR. if (!MI.getOperand(0).isKill()) - BuildMI(MBB, II, TII.get(PPC::MFCR), Reg); + BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg); else // Implicitly kill the CR register. - BuildMI(MBB, II, TII.get(PPC::MFCR), Reg) + BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg) .addReg(MI.getOperand(0).getReg(), false, true, true); // If the saved register wasn't CR0, shift the bits left so that they are in @@ -610,13 +614,13 @@ unsigned SrcReg = MI.getOperand(0).getReg(); if (SrcReg != PPC::CR0) // rlwinm rA, rA, ShiftBits, 0, 31. - BuildMI(MBB, II, TII.get(PPC::RLWINM), Reg) + BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) .addReg(Reg, false, false, true) .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) .addImm(0) .addImm(31); - addFrameReference(BuildMI(MBB, II, TII.get(PPC::STW)) + addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) .addReg(Reg, false, false, MI.getOperand(1).getImm()), FrameIndex); @@ -636,6 +640,7 @@ MachineFunction &MF = *MBB.getParent(); // Get the frame info. MachineFrameInfo *MFI = MF.getFrameInfo(); + DebugLoc dl = MI.getDebugLoc(); // Find out which operand is the frame index. unsigned FIOperandNo = 0; @@ -727,9 +732,9 @@ SReg = PPC::R0; // Insert a set of rA with the full offset value before the ld, st, or add - BuildMI(MBB, II, TII.get(PPC::LIS), SReg) + BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg) .addImm(Offset >> 16); - BuildMI(MBB, II, TII.get(PPC::ORI), SReg) + BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg) .addReg(SReg, false, false, true) .addImm(Offset); @@ -815,6 +820,7 @@ // transform this into the appropriate ORI instruction. static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { MachineFunction *MF = MI->getParent()->getParent(); + DebugLoc dl = MI->getDebugLoc(); unsigned UsedRegMask = 0; for (unsigned i = 0; i != 32; ++i) @@ -850,33 +856,33 @@ if ((UsedRegMask & 0xFFFF) == UsedRegMask) { if (DstReg != SrcReg) - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) + BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) .addReg(SrcReg) .addImm(UsedRegMask); else - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) + BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) .addReg(SrcReg, false, false, true) .addImm(UsedRegMask); } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { if (DstReg != SrcReg) - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) + BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) .addReg(SrcReg) .addImm(UsedRegMask >> 16); else - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) + BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) .addReg(SrcReg, false, false, true) .addImm(UsedRegMask >> 16); } else { if (DstReg != SrcReg) - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) + BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) .addReg(SrcReg) .addImm(UsedRegMask >> 16); else - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) + BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) .addReg(SrcReg, false, false, true) .addImm(UsedRegMask >> 16); - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) + BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) .addReg(DstReg, false, false, true) .addImm(UsedRegMask & 0xFFFF); } @@ -997,6 +1003,7 @@ MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); + DebugLoc dl = DebugLoc::getUnknownLoc(); bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) || !MF.getFunction()->doesNotThrow() || UnwindTablesMandatory; @@ -1037,31 +1044,31 @@ if (IsPPC64) { if (MustSaveLR) - BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0); + BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); if (HasFP) - BuildMI(MBB, MBBI, TII.get(PPC::STD)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) .addReg(PPC::X31) .addImm(FPOffset/4) .addReg(PPC::X1); if (MustSaveLR) - BuildMI(MBB, MBBI, TII.get(PPC::STD)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) .addReg(PPC::X0) .addImm(LROffset / 4) .addReg(PPC::X1); } else { if (MustSaveLR) - BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0); + BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); if (HasFP) - BuildMI(MBB, MBBI, TII.get(PPC::STW)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) .addReg(PPC::R31) .addImm(FPOffset) .addReg(PPC::R1); if (MustSaveLR) - BuildMI(MBB, MBBI, TII.get(PPC::STW)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) .addReg(PPC::R0) .addImm(LROffset) .addReg(PPC::R1); @@ -1077,7 +1084,7 @@ if (needsFrameMoves) { // Mark effective beginning of when frame pointer becomes valid. FrameLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId); + BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId); } // Adjust stack pointer: r1 += NegFrameSize. @@ -1088,30 +1095,30 @@ assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); - BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) .addReg(PPC::R1) .addImm(0) .addImm(32 - Log2_32(MaxAlign)) .addImm(31); - BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) .addReg(PPC::R0, false, false, true) .addImm(NegFrameSize); - BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) .addReg(PPC::R1) .addReg(PPC::R1) .addReg(PPC::R0); } else if (isInt16(NegFrameSize)) { - BuildMI(MBB, MBBI, TII.get(PPC::STWU), PPC::R1) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) .addReg(PPC::R1) .addImm(NegFrameSize) .addReg(PPC::R1); } else { - BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) .addImm(NegFrameSize >> 16); - BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) .addReg(PPC::R0, false, false, true) .addImm(NegFrameSize & 0xFFFF); - BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) .addReg(PPC::R1) .addReg(PPC::R1) .addReg(PPC::R0); @@ -1121,29 +1128,29 @@ assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); - BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) .addReg(PPC::X1) .addImm(0) .addImm(64 - Log2_32(MaxAlign)); - BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) .addReg(PPC::X0) .addImm(NegFrameSize); - BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) .addReg(PPC::X1) .addReg(PPC::X1) .addReg(PPC::X0); } else if (isInt16(NegFrameSize)) { - BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) .addReg(PPC::X1) .addImm(NegFrameSize / 4) .addReg(PPC::X1); } else { - BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) .addImm(NegFrameSize >> 16); - BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) .addReg(PPC::X0, false, false, true) .addImm(NegFrameSize & 0xFFFF); - BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) .addReg(PPC::X1) .addReg(PPC::X1) .addReg(PPC::X0); @@ -1186,7 +1193,7 @@ // Mark effective beginning of when frame pointer is ready. unsigned ReadyLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId); + BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId); MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) : (IsPPC64 ? PPC::X1 : PPC::R1)); @@ -1197,11 +1204,11 @@ // If there is a frame pointer, copy R1 into R31 if (HasFP) { if (!IsPPC64) { - BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31) + BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) .addReg(PPC::R1) .addReg(PPC::R1); } else { - BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31) + BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) .addReg(PPC::X1) .addReg(PPC::X1); } @@ -1212,6 +1219,7 @@ MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = prior(MBB.end()); unsigned RetOpcode = MBBI->getOpcode(); + DebugLoc dl = DebugLoc::getUnknownLoc(); assert( (RetOpcode == PPC::BLR || RetOpcode == PPC::TCRETURNri || @@ -1274,73 +1282,75 @@ // value of R31 in this case. if (FI->hasFastCall() && isInt16(FrameSize)) { assert(hasFP(MF) && "Expecting a valid the frame pointer."); - BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) .addReg(PPC::R31).addImm(FrameSize); } else if(FI->hasFastCall()) { - BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) .addImm(FrameSize >> 16); - BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) .addReg(PPC::R0, false, false, true) .addImm(FrameSize & 0xFFFF); - BuildMI(MBB, MBBI, TII.get(PPC::ADD4)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) .addReg(PPC::R1) .addReg(PPC::R31) .addReg(PPC::R0); } else if (isInt16(FrameSize) && (!ALIGN_STACK || TargetAlign >= MaxAlign) && !MFI->hasVarSizedObjects()) { - BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) .addReg(PPC::R1).addImm(FrameSize); } else { - BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1); + BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) + .addImm(0).addReg(PPC::R1); } } else { if (FI->hasFastCall() && isInt16(FrameSize)) { assert(hasFP(MF) && "Expecting a valid the frame pointer."); - BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) .addReg(PPC::X31).addImm(FrameSize); } else if(FI->hasFastCall()) { - BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) .addImm(FrameSize >> 16); - BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) .addReg(PPC::X0, false, false, true) .addImm(FrameSize & 0xFFFF); - BuildMI(MBB, MBBI, TII.get(PPC::ADD8)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) .addReg(PPC::X1) .addReg(PPC::X31) .addReg(PPC::X0); } else if (isInt16(FrameSize) && TargetAlign >= MaxAlign && !MFI->hasVarSizedObjects()) { - BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) .addReg(PPC::X1).addImm(FrameSize); } else { - BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1); + BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) + .addImm(0).addReg(PPC::X1); } } } if (IsPPC64) { if (MustSaveLR) - BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) .addImm(LROffset/4).addReg(PPC::X1); if (HasFP) - BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31) + BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) .addImm(FPOffset/4).addReg(PPC::X1); if (MustSaveLR) - BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0); + BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); } else { if (MustSaveLR) - BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) .addImm(LROffset).addReg(PPC::R1); if (HasFP) - BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31) + BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) .addImm(FPOffset).addReg(PPC::R1); if (MustSaveLR) - BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0); + BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); } // Callee pop calling convention. Pop parameter/linkage area. Used for tail @@ -1358,15 +1368,15 @@ unsigned ORIInstr = IsPPC64 ? PPC::ORI8 : PPC::ORI; if (CallerAllocatedAmt && isInt16(CallerAllocatedAmt)) { - BuildMI(MBB, MBBI, TII.get(ADDIInstr), StackReg) + BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) .addReg(StackReg).addImm(CallerAllocatedAmt); } else { - BuildMI(MBB, MBBI, TII.get(LISInstr), TmpReg) + BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) .addImm(CallerAllocatedAmt >> 16); - BuildMI(MBB, MBBI, TII.get(ORIInstr), TmpReg) + BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) .addReg(TmpReg, false, false, true) .addImm(CallerAllocatedAmt & 0xFFFF); - BuildMI(MBB, MBBI, TII.get(ADDInstr)) + BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) .addReg(StackReg) .addReg(FPReg) .addReg(TmpReg); @@ -1374,31 +1384,31 @@ } else if (RetOpcode == PPC::TCRETURNdi) { MBBI = prior(MBB.end()); MachineOperand &JumpTarget = MBBI->getOperand(0); - BuildMI(MBB, MBBI, TII.get(PPC::TAILB)). + BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); } else if (RetOpcode == PPC::TCRETURNri) { MBBI = prior(MBB.end()); MachineOperand &JumpTarget = MBBI->getOperand(0); assert(JumpTarget.isReg() && "Expecting register operand."); - BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR)); + BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); } else if (RetOpcode == PPC::TCRETURNai) { MBBI = prior(MBB.end()); MachineOperand &JumpTarget = MBBI->getOperand(0); - BuildMI(MBB, MBBI, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); + BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); } else if (RetOpcode == PPC::TCRETURNdi8) { MBBI = prior(MBB.end()); MachineOperand &JumpTarget = MBBI->getOperand(0); - BuildMI(MBB, MBBI, TII.get(PPC::TAILB8)). + BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); } else if (RetOpcode == PPC::TCRETURNri8) { MBBI = prior(MBB.end()); MachineOperand &JumpTarget = MBBI->getOperand(0); assert(JumpTarget.isReg() && "Expecting register operand."); - BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR8)); + BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); } else if (RetOpcode == PPC::TCRETURNai8) { MBBI = prior(MBB.end()); MachineOperand &JumpTarget = MBBI->getOperand(0); - BuildMI(MBB, MBBI, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); + BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); } } From dalej at apple.com Thu Feb 12 20:29:03 2009 From: dalej at apple.com (Dale Johannesen) Date: Fri, 13 Feb 2009 02:29:03 -0000 Subject: [llvm-commits] [llvm] r64432 - in /llvm/trunk/lib/Target: PIC16/PIC16ISelLowering.cpp XCore/XCoreInstrInfo.cpp XCore/XCoreRegisterInfo.cpp XCore/XCoreRegisterInfo.h Message-ID: <200902130229.n1D2T3mn028214@zion.cs.uiuc.edu> Author: johannes Date: Thu Feb 12 20:29:03 2009 New Revision: 64432 URL: http://llvm.org/viewvc/llvm-project?rev=64432&view=rev Log: Remove refs to non-DebugLoc version of BuildMI from XCore, PIC16. Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=64432&r1=64431&r2=64432&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Thu Feb 12 20:29:03 2009 @@ -1362,6 +1362,7 @@ MachineBasicBlock *BB) const { const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); unsigned CC = (PIC16CC::CondCodes)MI->getOperand(3).getImm(); + DebugLoc dl = MI->getDebugLoc(); // To "insert" a SELECT_CC instruction, we actually have to insert the diamond // control-flow pattern. The incoming instruction knows the destination vreg @@ -1380,7 +1381,7 @@ MachineFunction *F = BB->getParent(); MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); - BuildMI(BB, TII.get(PIC16::pic16brcond)).addMBB(sinkMBB).addImm(CC); + BuildMI(BB, dl, TII.get(PIC16::pic16brcond)).addMBB(sinkMBB).addImm(CC); F->insert(It, copy0MBB); F->insert(It, sinkMBB); @@ -1403,7 +1404,7 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(BB, TII.get(PIC16::PHI), MI->getOperand(0).getReg()) + BuildMI(BB, dl, TII.get(PIC16::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp?rev=64432&r1=64431&r2=64432&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp Thu Feb 12 20:29:03 2009 @@ -302,6 +302,8 @@ XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond)const{ + // FIXME there should probably be a DebugLoc argument here + DebugLoc dl = DebugLoc::getUnknownLoc(); // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && @@ -310,11 +312,11 @@ if (FBB == 0) { // One way branch. if (Cond.empty()) { // Unconditional branch - BuildMI(&MBB, get(XCore::BRFU_lu6)).addMBB(TBB); + BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(TBB); } else { // Conditional branch. unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); - BuildMI(&MBB, get(Opc)).addReg(Cond[1].getReg()) + BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg()) .addMBB(TBB); } return 1; @@ -323,9 +325,9 @@ // Two-way Conditional branch. assert(Cond.size() == 2 && "Unexpected number of components!"); unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); - BuildMI(&MBB, get(Opc)).addReg(Cond[1].getReg()) + BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg()) .addMBB(TBB); - BuildMI(&MBB, get(XCore::BRFU_lu6)).addMBB(FBB); + BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(FBB); return 2; } Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp?rev=64432&r1=64431&r2=64432&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp Thu Feb 12 20:29:03 2009 @@ -171,6 +171,7 @@ int SPAdj, RegScavenger *RS) const { assert(SPAdj == 0 && "Unexpected"); MachineInstr &MI = *II; + DebugLoc dl = MI.getDebugLoc(); unsigned i = 0; while (!MI.getOperand(i).isFI()) { @@ -231,21 +232,21 @@ } unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II, SPAdj); - loadConstant(MBB, II, ScratchReg, Offset); + loadConstant(MBB, II, ScratchReg, Offset, dl); switch (MI.getOpcode()) { case XCore::LDWFI: - New = BuildMI(MBB, II, TII.get(XCore::LDW_3r), Reg) + New = BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) .addReg(FramePtr) .addReg(ScratchReg, false, false, true); break; case XCore::STWFI: - New = BuildMI(MBB, II, TII.get(XCore::STW_3r)) + New = BuildMI(MBB, II, dl, TII.get(XCore::STW_3r)) .addReg(Reg, false, false, isKill) .addReg(FramePtr) .addReg(ScratchReg, false, false, true); break; case XCore::LDAWFI: - New = BuildMI(MBB, II, TII.get(XCore::LDAWF_l3r), Reg) + New = BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) .addReg(FramePtr) .addReg(ScratchReg, false, false, true); break; @@ -255,18 +256,18 @@ } else { switch (MI.getOpcode()) { case XCore::LDWFI: - New = BuildMI(MBB, II, TII.get(XCore::LDW_2rus), Reg) + New = BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) .addReg(FramePtr) .addImm(Offset); break; case XCore::STWFI: - New = BuildMI(MBB, II, TII.get(XCore::STW_2rus)) + New = BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) .addReg(Reg, false, false, isKill) .addReg(FramePtr) .addImm(Offset); break; case XCore::LDAWFI: - New = BuildMI(MBB, II, TII.get(XCore::LDAWF_l2rus), Reg) + New = BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) .addReg(FramePtr) .addImm(Offset); break; @@ -286,18 +287,18 @@ int NewOpcode; case XCore::LDWFI: NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; - BuildMI(MBB, II, TII.get(NewOpcode), Reg) + BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) .addImm(Offset); break; case XCore::STWFI: NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; - BuildMI(MBB, II, TII.get(NewOpcode)) + BuildMI(MBB, II, dl, TII.get(NewOpcode)) .addReg(Reg, false, false, isKill) .addImm(Offset); break; case XCore::LDAWFI: NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; - BuildMI(MBB, II, TII.get(NewOpcode), Reg) + BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) .addImm(Offset); break; default: @@ -349,7 +350,7 @@ void XCoreRegisterInfo:: loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned DstReg, int64_t Value) const { + unsigned DstReg, int64_t Value, DebugLoc dl) const { // TODO use mkmsk if possible. if (!isImmU16(Value)) { // TODO use constant pool. @@ -357,12 +358,12 @@ abort(); } int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6; - BuildMI(MBB, I, TII.get(Opcode), DstReg).addImm(Value); + BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value); } void XCoreRegisterInfo:: storeToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned SrcReg, int Offset) const { + unsigned SrcReg, int Offset, DebugLoc dl) const { assert(Offset%4 == 0 && "Misaligned stack offset"); Offset/=4; bool isU6 = isImmU6(Offset); @@ -371,23 +372,23 @@ abort(); } int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6; - BuildMI(MBB, I, TII.get(Opcode)) + BuildMI(MBB, I, dl, TII.get(Opcode)) .addReg(SrcReg) .addImm(Offset); } void XCoreRegisterInfo:: loadFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned DstReg, int Offset) const { + unsigned DstReg, int Offset, DebugLoc dl) const { assert(Offset%4 == 0 && "Misaligned stack offset"); Offset/=4; bool isU6 = isImmU6(Offset); if (!isU6 && !isImmU16(Offset)) { - cerr << "storeToStack offset too big " << Offset << "\n"; + cerr << "loadFromStack offset too big " << Offset << "\n"; abort(); } int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; - BuildMI(MBB, I, TII.get(Opcode), DstReg) + BuildMI(MBB, I, dl, TII.get(Opcode), DstReg) .addImm(Offset); } @@ -397,6 +398,7 @@ MachineFrameInfo *MFI = MF.getFrameInfo(); MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); XCoreFunctionInfo *XFI = MF.getInfo(); + DebugLoc dl = DebugLoc::getUnknownLoc(); bool FP = hasFP(MF); @@ -429,14 +431,14 @@ } else { Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; } - BuildMI(MBB, MBBI, TII.get(Opcode)).addImm(FrameSize); + BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize); if (emitFrameMoves) { std::vector &Moves = MMI->getFrameMoves(); // Show update of SP. unsigned FrameLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(XCore::DBG_LABEL)).addImm(FrameLabelId); + BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(FrameLabelId); MachineLocation SPDst(MachineLocation::VirtualFP); MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize * 4); @@ -450,12 +452,12 @@ } if (saveLR) { int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot()); - storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4); + storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl); MBB.addLiveIn(XCore::LR); if (emitFrameMoves) { unsigned SaveLRLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(XCore::DBG_LABEL)).addImm(SaveLRLabelId); + BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(SaveLRLabelId); MachineLocation CSDst(MachineLocation::VirtualFP, LRSpillOffset); MachineLocation CSSrc(XCore::LR); MMI->getFrameMoves().push_back(MachineMove(SaveLRLabelId, @@ -467,12 +469,12 @@ if (FP) { // Save R10 to the stack. int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot()); - storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4); + storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl); // R10 is live-in. It is killed at the spill. MBB.addLiveIn(XCore::R10); if (emitFrameMoves) { unsigned SaveR10LabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(XCore::DBG_LABEL)).addImm(SaveR10LabelId); + BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(SaveR10LabelId); MachineLocation CSDst(MachineLocation::VirtualFP, FPSpillOffset); MachineLocation CSSrc(XCore::R10); MMI->getFrameMoves().push_back(MachineMove(SaveR10LabelId, @@ -480,12 +482,12 @@ } // Set the FP from the SP. unsigned FramePtr = XCore::R10; - BuildMI(MBB, MBBI, TII.get(XCore::LDAWSP_ru6), FramePtr) + BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr) .addImm(0); if (emitFrameMoves) { // Show FP is now valid. unsigned FrameLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(XCore::DBG_LABEL)).addImm(FrameLabelId); + BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(FrameLabelId); MachineLocation SPDst(FramePtr); MachineLocation SPSrc(MachineLocation::VirtualFP); MMI->getFrameMoves().push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); @@ -513,13 +515,14 @@ MachineBasicBlock &MBB) const { MachineFrameInfo *MFI = MF.getFrameInfo(); MachineBasicBlock::iterator MBBI = prior(MBB.end()); + DebugLoc dl = DebugLoc::getUnknownLoc(); bool FP = hasFP(MF); if (FP) { // Restore the stack pointer. unsigned FramePtr = XCore::R10; - BuildMI(MBB, MBBI, TII.get(XCore::SETSP_1r)) + BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)) .addReg(FramePtr); } @@ -545,13 +548,13 @@ // Restore R10 int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot()); FPSpillOffset += FrameSize*4; - loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset); + loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl); } bool restoreLR = XFI->getUsesLR(); if (restoreLR && MFI->getObjectOffset(XFI->getLRSpillSlot()) != 0) { int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot()); LRSpillOffset += FrameSize*4; - loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset); + loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset, dl); restoreLR = false; } if (restoreLR) { @@ -559,11 +562,11 @@ assert(MBBI->getOpcode() == XCore::RETSP_u6 || MBBI->getOpcode() == XCore::RETSP_lu6); int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6; - BuildMI(MBB, MBBI, TII.get(Opcode)).addImm(FrameSize); + BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize); MBB.erase(MBBI); } else { int Opcode = (isU6) ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs; - BuildMI(MBB, MBBI, TII.get(Opcode), XCore::SP).addImm(FrameSize); + BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(FrameSize); } } } Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h?rev=64432&r1=64431&r2=64432&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h (original) +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h Thu Feb 12 20:29:03 2009 @@ -27,15 +27,15 @@ void loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned DstReg, int64_t Value) const; + unsigned DstReg, int64_t Value, DebugLoc dl) const; void storeToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned SrcReg, int Offset) const; + unsigned SrcReg, int Offset, DebugLoc dl) const; void loadFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned DstReg, int Offset) const; + unsigned DstReg, int Offset, DebugLoc dl) const; public: XCoreRegisterInfo(const TargetInstrInfo &tii); From dalej at apple.com Thu Feb 12 20:30:42 2009 From: dalej at apple.com (Dale Johannesen) Date: Fri, 13 Feb 2009 02:30:42 -0000 Subject: [llvm-commits] [llvm] r64433 - in /llvm/trunk/lib/Target: Alpha/AlphaISelLowering.cpp Alpha/AlphaInstrInfo.cpp Alpha/AlphaLLRP.cpp Alpha/AlphaRegisterInfo.cpp CellSPU/SPUInstrInfo.cpp CellSPU/SPURegisterInfo.cpp Message-ID: <200902130230.n1D2UghY028284@zion.cs.uiuc.edu> Author: johannes Date: Thu Feb 12 20:30:42 2009 New Revision: 64433 URL: http://llvm.org/viewvc/llvm-project?rev=64433&view=rev Log: Remove non-DebugLoc versions of BuildMI from Alpha and Cell. Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaLLRP.cpp llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=64433&r1=64432&r2=64433&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Thu Feb 12 20:30:42 2009 @@ -728,6 +728,7 @@ //test sc and maybe branck to start //exit: const BasicBlock *LLVM_BB = BB->getBasicBlock(); + DebugLoc dl = MI->getDebugLoc(); MachineFunction::iterator It = BB; ++It; @@ -741,46 +742,46 @@ F->insert(It, llscMBB); F->insert(It, sinkMBB); - BuildMI(thisMBB, TII->get(Alpha::BR)).addMBB(llscMBB); + BuildMI(thisMBB, dl, TII->get(Alpha::BR)).addMBB(llscMBB); unsigned reg_res = MI->getOperand(0).getReg(), reg_ptr = MI->getOperand(1).getReg(), reg_v2 = MI->getOperand(2).getReg(), reg_store = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass); - BuildMI(llscMBB, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L), + BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L), reg_res).addImm(0).addReg(reg_ptr); switch (MI->getOpcode()) { case Alpha::CAS32: case Alpha::CAS64: { unsigned reg_cmp = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass); - BuildMI(llscMBB, TII->get(Alpha::CMPEQ), reg_cmp) + BuildMI(llscMBB, dl, TII->get(Alpha::CMPEQ), reg_cmp) .addReg(reg_v2).addReg(reg_res); - BuildMI(llscMBB, TII->get(Alpha::BEQ)) + BuildMI(llscMBB, dl, TII->get(Alpha::BEQ)) .addImm(0).addReg(reg_cmp).addMBB(sinkMBB); - BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store) + BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store) .addReg(Alpha::R31).addReg(MI->getOperand(3).getReg()); break; } case Alpha::LAS32: case Alpha::LAS64: { - BuildMI(llscMBB, TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store) + BuildMI(llscMBB, dl,TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store) .addReg(reg_res).addReg(reg_v2); break; } case Alpha::SWAP32: case Alpha::SWAP64: { - BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store) + BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store) .addReg(reg_v2).addReg(reg_v2); break; } } - BuildMI(llscMBB, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store) + BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store) .addReg(reg_store).addImm(0).addReg(reg_ptr); - BuildMI(llscMBB, TII->get(Alpha::BEQ)) + BuildMI(llscMBB, dl, TII->get(Alpha::BEQ)) .addImm(0).addReg(reg_store).addMBB(llscMBB); - BuildMI(llscMBB, TII->get(Alpha::BR)).addMBB(sinkMBB); + BuildMI(llscMBB, dl, TII->get(Alpha::BR)).addMBB(sinkMBB); thisMBB->addSuccessor(llscMBB); llscMBB->addSuccessor(llscMBB); Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=64433&r1=64432&r2=64433&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Thu Feb 12 20:30:42 2009 @@ -108,6 +108,8 @@ MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const { + // FIXME this should probably have a DebugLoc argument + DebugLoc dl = DebugLoc::getUnknownLoc(); assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && "Alpha branch conditions have two components!"); @@ -115,25 +117,25 @@ // One-way branch. if (FBB == 0) { if (Cond.empty()) // Unconditional branch - BuildMI(&MBB, get(Alpha::BR)).addMBB(TBB); + BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(TBB); else // Conditional branch if (isAlphaIntCondCode(Cond[0].getImm())) - BuildMI(&MBB, get(Alpha::COND_BRANCH_I)) + BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); else - BuildMI(&MBB, get(Alpha::COND_BRANCH_F)) + BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); return 1; } // Two-way Conditional Branch. if (isAlphaIntCondCode(Cond[0].getImm())) - BuildMI(&MBB, get(Alpha::COND_BRANCH_I)) + BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); else - BuildMI(&MBB, get(Alpha::COND_BRANCH_F)) + BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); - BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB); + BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(FBB); return 2; } Modified: llvm/trunk/lib/Target/Alpha/AlphaLLRP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaLLRP.cpp?rev=64433&r1=64432&r2=64433&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaLLRP.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaLLRP.cpp Thu Feb 12 20:30:42 2009 @@ -49,6 +49,7 @@ const TargetInstrInfo *TII = F.getTarget().getInstrInfo(); bool Changed = false; MachineInstr* prev[3] = {0,0,0}; + DebugLoc dl = DebugLoc::getUnknownLoc(); unsigned count = 0; for (MachineFunction::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) { @@ -73,7 +74,7 @@ prev[0] = prev[1]; prev[1] = prev[2]; prev[2] = 0; - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 1; @@ -85,10 +86,10 @@ MI->getOperand(1).getImm()) { prev[0] = prev[2]; prev[1] = prev[2] = 0; - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31) .addReg(Alpha::R31); - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 2; @@ -99,12 +100,12 @@ && prev[2]->getOperand(1).getImm() == MI->getOperand(1).getImm()) { prev[0] = prev[1] = prev[2] = 0; - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) - .addReg(Alpha::R31); - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) - .addReg(Alpha::R31); - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) - .addReg(Alpha::R31); + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) + .addReg(Alpha::R31).addReg(Alpha::R31); + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) + .addReg(Alpha::R31).addReg(Alpha::R31); + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) + .addReg(Alpha::R31).addReg(Alpha::R31); Changed = true; nopintro += 3; count += 3; } @@ -136,7 +137,7 @@ if (ub || AlignAll) { //we can align stuff for free at this point while (count % 4) { - BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MBB.end(), dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31).addReg(Alpha::R31); ++count; ++nopalign; Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=64433&r1=64432&r2=64433&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Thu Feb 12 20:30:42 2009 @@ -202,20 +202,21 @@ MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); + DebugLoc dl = DebugLoc::getUnknownLoc(); bool FP = hasFP(MF); static int curgpdist = 0; //handle GOP offset - BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAHg), Alpha::R29) .addGlobalAddress(const_cast(MF.getFunction())) .addReg(Alpha::R27).addImm(++curgpdist); - BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAg), Alpha::R29) .addGlobalAddress(const_cast(MF.getFunction())) .addReg(Alpha::R29).addImm(curgpdist); //evil const_cast until MO stuff setup to handle const - BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT)) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::ALTENT)) .addGlobalAddress(const_cast(MF.getFunction())); // Get the number of bytes to allocate from the FrameInfo @@ -236,13 +237,13 @@ // adjust stack pointer: r30 -= numbytes NumBytes = -NumBytes; if (NumBytes >= IMM_LOW) { - BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) .addReg(Alpha::R30); } else if (getUpper16(NumBytes) >= IMM_LOW) { - BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes)) - .addReg(Alpha::R30); - BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes)) - .addReg(Alpha::R30); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30) + .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30) + .addImm(getLower16(NumBytes)).addReg(Alpha::R30); } else { cerr << "Too big a stack frame at " << NumBytes << "\n"; abort(); @@ -251,10 +252,10 @@ //now if we need to, save the old FP and set the new if (FP) { - BuildMI(MBB, MBBI, TII.get(Alpha::STQ)) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::STQ)) .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); //this must be the last instr in the prolog - BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R15) .addReg(Alpha::R30).addReg(Alpha::R30); } @@ -267,6 +268,7 @@ assert((MBBI->getOpcode() == Alpha::RETDAG || MBBI->getOpcode() == Alpha::RETDAGp) && "Can only insert epilog into returning blocks"); + DebugLoc dl = DebugLoc::getUnknownLoc(); bool FP = hasFP(MF); @@ -276,20 +278,21 @@ //now if we need to, restore the old FP if (FP) { //copy the FP into the SP (discards allocas) - BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) .addReg(Alpha::R15); //restore the FP - BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDQ), Alpha::R15) + .addImm(0).addReg(Alpha::R15); } if (NumBytes != 0) { if (NumBytes <= IMM_HIGH) { - BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) .addReg(Alpha::R30); } else if (getUpper16(NumBytes) <= IMM_HIGH) { - BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30) .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); - BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30) .addImm(getLower16(NumBytes)).addReg(Alpha::R30); } else { cerr << "Too big a stack frame at " << NumBytes << "\n"; Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=64433&r1=64432&r2=64433&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Thu Feb 12 20:30:42 2009 @@ -627,6 +627,8 @@ SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const { + // FIXME this should probably have a DebugLoc argument + DebugLoc dl = DebugLoc::getUnknownLoc(); // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && @@ -636,14 +638,14 @@ if (FBB == 0) { if (Cond.empty()) { // Unconditional branch - MachineInstrBuilder MIB = BuildMI(&MBB, get(SPU::BR)); + MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(SPU::BR)); MIB.addMBB(TBB); DEBUG(cerr << "Inserted one-way uncond branch: "); DEBUG((*MIB).dump()); } else { // Conditional branch - MachineInstrBuilder MIB = BuildMI(&MBB, get(Cond[0].getImm())); + MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm())); MIB.addReg(Cond[1].getReg()).addMBB(TBB); DEBUG(cerr << "Inserted one-way cond branch: "); @@ -651,8 +653,8 @@ } return 1; } else { - MachineInstrBuilder MIB = BuildMI(&MBB, get(Cond[0].getImm())); - MachineInstrBuilder MIB2 = BuildMI(&MBB, get(SPU::BR)); + MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm())); + MachineInstrBuilder MIB2 = BuildMI(&MBB, dl, get(SPU::BR)); // Two-way Conditional Branch. MIB.addReg(Cond[1].getReg()).addMBB(TBB); Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=64433&r1=64432&r2=64433&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Thu Feb 12 20:30:42 2009 @@ -428,6 +428,7 @@ MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); + DebugLoc dl = DebugLoc::getUnknownLoc(); // Prepare for debug frame info. bool hasDebugInfo = MMI && MMI->hasDebugInfo(); @@ -448,38 +449,38 @@ if (hasDebugInfo) { // Mark effective beginning of when frame pointer becomes valid. FrameLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(FrameLabelId); + BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addImm(FrameLabelId); } // Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp) // for the ABI - BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R0).addImm(16) + BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16) .addReg(SPU::R1); if (isS10Constant(FrameSize)) { // Spill $sp to adjusted $sp - BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize) + BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize) .addReg(SPU::R1); // Adjust $sp by required amout - BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1) + BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1) .addImm(FrameSize); } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) { // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use // $r2 to adjust $sp: - BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2) .addImm(-16) .addReg(SPU::R1); - BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2) .addImm(FrameSize); - BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1) + BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1) .addReg(SPU::R2) .addReg(SPU::R1); - BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1) + BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1) .addReg(SPU::R1) .addReg(SPU::R2); - BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2) .addReg(SPU::R2) .addImm(16); - BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2) .addReg(SPU::R2) .addReg(SPU::R1); } else { @@ -508,7 +509,7 @@ // Mark effective beginning of when frame pointer is ready. unsigned ReadyLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(ReadyLabelId); + BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addImm(ReadyLabelId); MachineLocation FPDst(SPU::R1); MachineLocation FPSrc(MachineLocation::VirtualFP); @@ -522,7 +523,7 @@ MachineBasicBlock::iterator MBBI = prior(MBB.end()); // Insert terminator label unsigned BranchLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(BranchLabelId); + BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addImm(BranchLabelId); } } } @@ -534,6 +535,7 @@ const MachineFrameInfo *MFI = MF.getFrameInfo(); int FrameSize = MFI->getStackSize(); int LinkSlotOffset = SPUFrameInfo::stackSlotSize(); + DebugLoc dl = DebugLoc::getUnknownLoc(); assert(MBBI->getOpcode() == SPU::RET && "Can only insert epilog into returning blocks"); @@ -545,30 +547,30 @@ // Reload $lr, adjust $sp by required amount // Note: We do this to slightly improve dual issue -- not by much, but it // is an opportunity for dual issue. - BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0) + BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0) .addImm(FrameSize + LinkSlotOffset) .addReg(SPU::R1); - BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1) + BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1) .addReg(SPU::R1) .addImm(FrameSize); } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) { // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use // $r2 to adjust $sp: - BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2) .addImm(16) .addReg(SPU::R1); - BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2) .addImm(FrameSize); - BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1) + BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1) .addReg(SPU::R1) .addReg(SPU::R2); - BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0) + BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0) .addImm(16) .addReg(SPU::R2); - BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2). + BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2). addReg(SPU::R2) .addImm(16); - BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2) .addReg(SPU::R2) .addReg(SPU::R1); } else { From dalej at apple.com Thu Feb 12 20:31:35 2009 From: dalej at apple.com (Dale Johannesen) Date: Fri, 13 Feb 2009 02:31:35 -0000 Subject: [llvm-commits] [llvm] r64435 - in /llvm/trunk/lib/Target/Sparc: DelaySlotFiller.cpp FPMover.cpp SparcISelLowering.cpp SparcInstrInfo.cpp SparcRegisterInfo.cpp Message-ID: <200902130231.n1D2Va3k028344@zion.cs.uiuc.edu> Author: johannes Date: Thu Feb 12 20:31:35 2009 New Revision: 64435 URL: http://llvm.org/viewvc/llvm-project?rev=64435&view=rev Log: Remove non-DebugLoc versions of buildMI from Sparc. Modified: llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp llvm/trunk/lib/Target/Sparc/FPMover.cpp llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Modified: llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp?rev=64435&r1=64434&r2=64435&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp (original) +++ llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp Thu Feb 12 20:31:35 2009 @@ -68,7 +68,7 @@ if (I->getDesc().hasDelaySlot()) { MachineBasicBlock::iterator J = I; ++J; - BuildMI(MBB, J, TII->get(SP::NOP)); + BuildMI(MBB, J, DebugLoc::getUnknownLoc(), TII->get(SP::NOP)); ++FilledSlots; Changed = true; } Modified: llvm/trunk/lib/Target/Sparc/FPMover.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/FPMover.cpp?rev=64435&r1=64434&r2=64435&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/FPMover.cpp (original) +++ llvm/trunk/lib/Target/Sparc/FPMover.cpp Thu Feb 12 20:31:35 2009 @@ -84,6 +84,7 @@ bool Changed = false; for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) { MachineInstr *MI = I++; + DebugLoc dl = MI->getDebugLoc(); if (MI->getOpcode() == SP::FpMOVD || MI->getOpcode() == SP::FpABSD || MI->getOpcode() == SP::FpNEGD) { Changed = true; @@ -114,7 +115,7 @@ DOUT << "FPMover: the modified instr is: " << *MI; // Insert copy for the other half of the double. if (DestDReg != SrcDReg) { - MI = BuildMI(MBB, I, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg) + MI = BuildMI(MBB, I, dl, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg) .addReg(OddSrcReg); DOUT << "FPMover: the inserted instr is: " << *MI; } Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=64435&r1=64434&r2=64435&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Thu Feb 12 20:31:35 2009 @@ -926,6 +926,7 @@ const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); unsigned BROpcode; unsigned CC; + DebugLoc dl = MI->getDebugLoc(); // Figure out the conditional branch opcode to use for this select_cc. switch (MI->getOpcode()) { default: assert(0 && "Unknown SELECT_CC!"); @@ -960,7 +961,7 @@ MachineFunction *F = BB->getParent(); MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); - BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); + BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); F->insert(It, copy0MBB); F->insert(It, sinkMBB); // Update machine-CFG edges by transferring all successors of the current @@ -982,7 +983,7 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg()) + BuildMI(BB, dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=64435&r1=64434&r2=64435&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Thu Feb 12 20:31:35 2009 @@ -107,9 +107,11 @@ SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond)const{ + // FIXME this should probably take a DebugLoc argument + DebugLoc dl = DebugLoc::getUnknownLoc(); // Can only insert uncond branches so far. assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!"); - BuildMI(&MBB, get(SP::BA)).addMBB(TBB); + BuildMI(&MBB, dl, get(SP::BA)).addMBB(TBB); return 1; } Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=64435&r1=64434&r2=64435&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Thu Feb 12 20:31:35 2009 @@ -66,11 +66,12 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { MachineInstr &MI = *I; + DebugLoc dl = MI.getDebugLoc(); int Size = MI.getOperand(0).getImm(); if (MI.getOpcode() == SP::ADJCALLSTACKDOWN) Size = -Size; if (Size) - BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size); + BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size); MBB.erase(I); } @@ -80,6 +81,7 @@ unsigned i = 0; MachineInstr &MI = *II; + DebugLoc dl = MI.getDebugLoc(); while (!MI.getOperand(i).isFI()) { ++i; assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); @@ -102,9 +104,9 @@ // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to // scavenge a register here instead of reserving G1 all of the time. unsigned OffHi = (unsigned)Offset >> 10U; - BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); + BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); // Emit G1 = G1 + I6 - BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) + BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) .addReg(SP::I6); // Insert: G1+%lo(offset) into the user. MI.getOperand(i).ChangeToRegister(SP::G1, false); @@ -118,6 +120,7 @@ void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); MachineFrameInfo *MFI = MF.getFrameInfo(); + DebugLoc dl = DebugLoc::getUnknownLoc(); // Get the number of bytes to allocate from the FrameInfo int NumBytes = (int) MFI->getStackSize(); @@ -136,18 +139,18 @@ NumBytes = -NumBytes; if (NumBytes >= -4096) { - BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri), + BuildMI(MBB, MBB.begin(), dl, TII.get(SP::SAVEri), SP::O6).addReg(SP::O6).addImm(NumBytes); } else { MachineBasicBlock::iterator InsertPt = MBB.begin(); // Emit this the hard way. This clobbers G1 which we always know is // available here. unsigned OffHi = (unsigned)NumBytes >> 10U; - BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); + BuildMI(MBB, InsertPt, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); // Emit G1 = G1 + I6 - BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1) + BuildMI(MBB, InsertPt, dl, TII.get(SP::ORri), SP::G1) .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1)); - BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6) + BuildMI(MBB, InsertPt, dl, TII.get(SP::SAVErr), SP::O6) .addReg(SP::O6).addReg(SP::G1); } } @@ -155,9 +158,10 @@ void SparcRegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = prior(MBB.end()); + DebugLoc dl = DebugLoc::getUnknownLoc(); assert(MBBI->getOpcode() == SP::RETL && "Can only put epilog before 'retl' instruction!"); - BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) + BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) .addReg(SP::G0); } From dalej at apple.com Thu Feb 12 20:32:04 2009 From: dalej at apple.com (Dale Johannesen) Date: Fri, 13 Feb 2009 02:32:04 -0000 Subject: [llvm-commits] [llvm] r64436 - /llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Message-ID: <200902130232.n1D2W4Gb028368@zion.cs.uiuc.edu> Author: johannes Date: Thu Feb 12 20:32:04 2009 New Revision: 64436 URL: http://llvm.org/viewvc/llvm-project?rev=64436&view=rev Log: missed file Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=64436&r1=64435&r2=64436&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Thu Feb 12 20:32:04 2009 @@ -784,6 +784,7 @@ XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const { const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); + DebugLoc dl = MI->getDebugLoc(); assert((MI->getOpcode() == XCore::SELECT_CC) && "Unexpected instr type to insert"); @@ -805,7 +806,7 @@ MachineFunction *F = BB->getParent(); MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); - BuildMI(BB, TII.get(XCore::BRFT_lru6)) + BuildMI(BB, dl, TII.get(XCore::BRFT_lru6)) .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); F->insert(It, copy0MBB); F->insert(It, sinkMBB); @@ -828,7 +829,7 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(BB, TII.get(XCore::PHI), MI->getOperand(0).getReg()) + BuildMI(BB, dl, TII.get(XCore::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); From dalej at apple.com Thu Feb 12 20:33:27 2009 From: dalej at apple.com (Dale Johannesen) Date: Fri, 13 Feb 2009 02:33:27 -0000 Subject: [llvm-commits] [llvm] r64437 - in /llvm/trunk/lib/Target/X86: X86FastISel.cpp X86FloatingPoint.cpp X86FloatingPointRegKill.cpp X86ISelDAGToDAG.cpp X86InstrInfo.cpp X86RegisterInfo.cpp Message-ID: <200902130233.n1D2XR6M028425@zion.cs.uiuc.edu> Author: johannes Date: Thu Feb 12 20:33:27 2009 New Revision: 64437 URL: http://llvm.org/viewvc/llvm-project?rev=64437&view=rev Log: Remove non-DebugLoc versions of BuildMI from X86. There were some that might even matter in X86FastISel. Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp llvm/trunk/lib/Target/X86/X86FloatingPointRegKill.cpp llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=64437&r1=64436&r2=64437&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Thu Feb 12 20:33:27 2009 @@ -231,7 +231,7 @@ } ResultReg = createResultReg(RC); - addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM); + addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); return true; } @@ -259,7 +259,7 @@ break; } - addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addReg(Val); + addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val); return true; } @@ -285,7 +285,8 @@ } if (Opc) { - addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addImm(CI->getSExtValue()); + addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM) + .addImm(CI->getSExtValue()); return true; } } @@ -463,7 +464,7 @@ StubAM.Base.Reg = AM.Base.Reg; StubAM.GV = AM.GV; unsigned ResultReg = createResultReg(RC); - addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), StubAM); + addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), StubAM); // Now construct the final address. Note that the Disp, Scale, // and Index values may already be set here. @@ -568,7 +569,7 @@ // CMPri, otherwise use CMPrr. if (ConstantInt *Op1C = dyn_cast(Op1)) { if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) { - BuildMI(MBB, TII.get(CompareImmOpc)).addReg(Op0Reg) + BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg) .addImm(Op1C->getSExtValue()); return true; } @@ -579,7 +580,7 @@ unsigned Op1Reg = getRegForValue(Op1); if (Op1Reg == 0) return false; - BuildMI(MBB, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg); + BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg); return true; } @@ -601,9 +602,10 @@ unsigned EReg = createResultReg(&X86::GR8RegClass); unsigned NPReg = createResultReg(&X86::GR8RegClass); - BuildMI(MBB, TII.get(X86::SETEr), EReg); - BuildMI(MBB, TII.get(X86::SETNPr), NPReg); - BuildMI(MBB, TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg); + BuildMI(MBB, DL, TII.get(X86::SETEr), EReg); + BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg); + BuildMI(MBB, DL, + TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg); UpdateValueMap(I, ResultReg); return true; } @@ -613,9 +615,9 @@ unsigned NEReg = createResultReg(&X86::GR8RegClass); unsigned PReg = createResultReg(&X86::GR8RegClass); - BuildMI(MBB, TII.get(X86::SETNEr), NEReg); - BuildMI(MBB, TII.get(X86::SETPr), PReg); - BuildMI(MBB, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg); + BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg); + BuildMI(MBB, DL, TII.get(X86::SETPr), PReg); + BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg); UpdateValueMap(I, ResultReg); return true; } @@ -654,7 +656,7 @@ if (!X86FastEmitCompare(Op0, Op1, VT)) return false; - BuildMI(MBB, TII.get(SetCCOpc), ResultReg); + BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg); UpdateValueMap(I, ResultReg); return true; } @@ -737,12 +739,12 @@ if (!X86FastEmitCompare(Op0, Op1, VT)) return false; - BuildMI(MBB, TII.get(BranchOpc)).addMBB(TrueMBB); + BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB); if (Predicate == CmpInst::FCMP_UNE) { // X86 requires a second branch to handle UNE (and OEQ, // which is mapped to UNE above). - BuildMI(MBB, TII.get(X86::JP)).addMBB(TrueMBB); + BuildMI(MBB, DL, TII.get(X86::JP)).addMBB(TrueMBB); } FastEmitBranch(FalseMBB); @@ -816,7 +818,7 @@ unsigned OpCode = SetMI->getOpcode(); if (OpCode == X86::SETOr || OpCode == X86::SETBr) { - BuildMI(MBB, TII.get((OpCode == X86::SETOr) ? + BuildMI(MBB, DL, TII.get((OpCode == X86::SETOr) ? X86::JO : X86::JB)).addMBB(TrueMBB); FastEmitBranch(FalseMBB); MBB->addSuccessor(TrueMBB); @@ -833,8 +835,8 @@ unsigned OpReg = getRegForValue(BI->getCondition()); if (OpReg == 0) return false; - BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg); - BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB); + BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg); + BuildMI(MBB, DL, TII.get(X86::JNE)).addMBB(TrueMBB); FastEmitBranch(FalseMBB); MBB->addSuccessor(TrueMBB); return true; @@ -893,7 +895,7 @@ // Fold immediate in shl(x,3). if (ConstantInt *CI = dyn_cast(I->getOperand(1))) { unsigned ResultReg = createResultReg(RC); - BuildMI(MBB, TII.get(OpImm), + BuildMI(MBB, DL, TII.get(OpImm), ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff); UpdateValueMap(I, ResultReg); return true; @@ -907,11 +909,11 @@ // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what // we're doing here. if (CReg != X86::CL) - BuildMI(MBB, TII.get(TargetInstrInfo::EXTRACT_SUBREG), X86::CL) + BuildMI(MBB, DL, TII.get(TargetInstrInfo::EXTRACT_SUBREG), X86::CL) .addReg(CReg).addImm(X86::SUBREG_8BIT); unsigned ResultReg = createResultReg(RC); - BuildMI(MBB, TII.get(OpReg), ResultReg).addReg(Op0Reg); + BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg); UpdateValueMap(I, ResultReg); return true; } @@ -943,9 +945,9 @@ unsigned Op2Reg = getRegForValue(I->getOperand(2)); if (Op2Reg == 0) return false; - BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg); + BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg); unsigned ResultReg = createResultReg(RC); - BuildMI(MBB, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg); + BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg); UpdateValueMap(I, ResultReg); return true; } @@ -958,7 +960,7 @@ unsigned OpReg = getRegForValue(V); if (OpReg == 0) return false; unsigned ResultReg = createResultReg(X86::FR64RegisterClass); - BuildMI(MBB, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg); + BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg); UpdateValueMap(I, ResultReg); return true; } @@ -975,7 +977,7 @@ unsigned OpReg = getRegForValue(V); if (OpReg == 0) return false; unsigned ResultReg = createResultReg(X86::FR32RegisterClass); - BuildMI(MBB, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg); + BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg); UpdateValueMap(I, ResultReg); return true; } @@ -1008,7 +1010,7 @@ const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16) ? X86::GR16_RegisterClass : X86::GR32_RegisterClass; unsigned CopyReg = createResultReg(CopyRC); - BuildMI(MBB, TII.get(CopyOpc), CopyReg).addReg(InputReg); + BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg); // Then issue an extract_subreg. unsigned ResultReg = FastEmitInst_extractsubreg(DstVT.getSimpleVT(), @@ -1083,11 +1085,11 @@ return false; unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); - BuildMI(MBB, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2); + BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2); UpdateValueMap(&I, ResultReg); ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8)); - BuildMI(MBB, TII.get((Intrinsic == Intrinsic::sadd_with_overflow) ? + BuildMI(MBB, DL, TII.get((Intrinsic == Intrinsic::sadd_with_overflow) ? X86::SETOr : X86::SETBr), ResultReg); return true; } @@ -1204,7 +1206,7 @@ // Issue CALLSEQ_START unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode(); - BuildMI(MBB, TII.get(AdjStackDown)).addImm(NumBytes); + BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes); // Process argument: walk the register/memloc assignments, inserting // copies / loads. @@ -1291,8 +1293,8 @@ ? (Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r) : (Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32); MachineInstrBuilder MIB = CalleeOp - ? BuildMI(MBB, TII.get(CallOpc)).addReg(CalleeOp) - : BuildMI(MBB, TII.get(CallOpc)).addGlobalAddress(GV); + ? BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp) + : BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV); // Add an implicit use GOT pointer in EBX. if (!Subtarget->is64Bit() && @@ -1306,7 +1308,7 @@ // Issue CALLSEQ_END unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode(); - BuildMI(MBB, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0); + BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0); // Now handle call return value (if any). if (RetVT.getSimpleVT() != MVT::isVoid) { @@ -1344,18 +1346,19 @@ unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; unsigned MemSize = ResVT.getSizeInBits()/8; int FI = MFI.CreateStackObject(MemSize, MemSize); - addFrameReference(BuildMI(MBB, TII.get(Opc)), FI).addReg(ResultReg); + addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg); DstRC = ResVT == MVT::f32 ? X86::FR32RegisterClass : X86::FR64RegisterClass; Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; ResultReg = createResultReg(DstRC); - addFrameReference(BuildMI(MBB, TII.get(Opc), ResultReg), FI); + addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI); } if (AndToI1) { // Mask out all but lowest bit for some call which produces an i1. unsigned AndResult = createResultReg(X86::GR8RegisterClass); - BuildMI(MBB, TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1); + BuildMI(MBB, DL, + TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1); ResultReg = AndResult; } @@ -1461,7 +1464,7 @@ else Opc = X86::LEA64r; unsigned ResultReg = createResultReg(RC); - addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM); + addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); return ResultReg; } return 0; @@ -1484,7 +1487,7 @@ // Create the load from the constant pool. unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align); unsigned ResultReg = createResultReg(RC); - addConstantPoolReference(BuildMI(MBB, TII.get(Opc), ResultReg), MCPOffset, + addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), MCPOffset, PICBase); return ResultReg; @@ -1507,7 +1510,7 @@ unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); unsigned ResultReg = createResultReg(RC); - addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM); + addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); return ResultReg; } Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=64437&r1=64436&r2=64437&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Thu Feb 12 20:33:27 2009 @@ -115,6 +115,8 @@ bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; } void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) { + MachineInstr *MI = I; + DebugLoc dl = MI->getDebugLoc(); if (isAtTop(RegNo)) return; unsigned STReg = getSTReg(RegNo); @@ -128,15 +130,16 @@ std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); // Emit an fxch to update the runtime processors version of the state. - BuildMI(*MBB, I, TII->get(X86::XCH_F)).addReg(STReg); + BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); NumFXCH++; } void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) { + DebugLoc dl = I->getDebugLoc(); unsigned STReg = getSTReg(RegNo); pushReg(AsReg); // New register on top of stack - BuildMI(*MBB, I, TII->get(X86::LD_Frr)).addReg(STReg); + BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); } // popStackAfter - Pop the current value off of the top of the FP stack @@ -549,6 +552,8 @@ /// instruction if it was modified in place. /// void FPS::popStackAfter(MachineBasicBlock::iterator &I) { + MachineInstr* MI = I; + DebugLoc dl = MI->getDebugLoc(); ASSERT_SORTED(PopTable); assert(StackTop > 0 && "Cannot pop empty stack!"); RegMap[Stack[--StackTop]] = ~0; // Update state @@ -560,7 +565,7 @@ if (Opcode == X86::UCOM_FPPr) I->RemoveOperand(0); } else { // Insert an explicit pop - I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(X86::ST0); + I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); } } @@ -584,7 +589,9 @@ RegMap[TopReg] = OldSlot; RegMap[FPRegNo] = ~0; Stack[--StackTop] = ~0; - I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(STReg); + MachineInstr *MI = I; + DebugLoc dl = MI->getDebugLoc(); + I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(STReg); } @@ -788,6 +795,7 @@ unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); bool KillsOp0 = MI->killsRegister(X86::FP0+Op0); bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); + DebugLoc dl = MI->getDebugLoc(); unsigned TOS = getStackEntry(0); @@ -853,7 +861,7 @@ // Replace the old instruction with a new instruction MBB->remove(I++); - I = BuildMI(*MBB, I, TII->get(Opcode)).addReg(getSTReg(NotTOS)); + I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS)); // If both operands are killed, pop one off of the stack in addition to // overwriting the other one. @@ -935,6 +943,7 @@ /// void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { MachineInstr *MI = I; + DebugLoc dl = MI->getDebugLoc(); switch (MI->getOpcode()) { default: assert(0 && "Unknown SpecialFP instruction!"); case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type! @@ -991,7 +1000,7 @@ case X86::FpSET_ST1_80: // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them. if (StackTop == 1) { - BuildMI(*MBB, I, TII->get(X86::XCH_F)).addReg(X86::ST1); + BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1); NumFXCH++; StackTop = 0; break; Modified: llvm/trunk/lib/Target/X86/X86FloatingPointRegKill.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPointRegKill.cpp?rev=64437&r1=64436&r2=64437&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FloatingPointRegKill.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FloatingPointRegKill.cpp Thu Feb 12 20:33:27 2009 @@ -128,7 +128,7 @@ } // Finally, if we found any FP code, emit the FP_REG_KILL instruction. if (ContainsFPCode) { - BuildMI(*MBB, MBBI->getFirstTerminator(), + BuildMI(*MBB, MBBI->getFirstTerminator(), DebugLoc::getUnknownLoc(), MF.getTarget().getInstrInfo()->get(X86::FP_REG_KILL)); ++NumFPKill; Changed = true; Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=64437&r1=64436&r2=64437&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Feb 12 20:33:27 2009 @@ -720,7 +720,8 @@ MachineFrameInfo *MFI) { const TargetInstrInfo *TII = TM.getInstrInfo(); if (Subtarget->isTargetCygMing()) - BuildMI(BB, TII->get(X86::CALLpcrel32)).addExternalSymbol("__main"); + BuildMI(BB, DebugLoc::getUnknownLoc(), + TII->get(X86::CALLpcrel32)).addExternalSymbol("__main"); } void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) { Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=64437&r1=64436&r2=64437&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Feb 12 20:33:27 2009 @@ -1630,6 +1630,8 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const { + // FIXME this should probably have a DebugLoc operand + DebugLoc dl = DebugLoc::getUnknownLoc(); // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 1 || Cond.size() == 0) && @@ -1638,7 +1640,7 @@ if (Cond.empty()) { // Unconditional branch? assert(!FBB && "Unconditional branch with multiple successors!"); - BuildMI(&MBB, get(X86::JMP)).addMBB(TBB); + BuildMI(&MBB, dl, get(X86::JMP)).addMBB(TBB); return 1; } @@ -1648,27 +1650,27 @@ switch (CC) { case X86::COND_NP_OR_E: // Synthesize NP_OR_E with two branches. - BuildMI(&MBB, get(X86::JNP)).addMBB(TBB); + BuildMI(&MBB, dl, get(X86::JNP)).addMBB(TBB); ++Count; - BuildMI(&MBB, get(X86::JE)).addMBB(TBB); + BuildMI(&MBB, dl, get(X86::JE)).addMBB(TBB); ++Count; break; case X86::COND_NE_OR_P: // Synthesize NE_OR_P with two branches. - BuildMI(&MBB, get(X86::JNE)).addMBB(TBB); + BuildMI(&MBB, dl, get(X86::JNE)).addMBB(TBB); ++Count; - BuildMI(&MBB, get(X86::JP)).addMBB(TBB); + BuildMI(&MBB, dl, get(X86::JP)).addMBB(TBB); ++Count; break; default: { unsigned Opc = GetCondBranchFromCond(CC); - BuildMI(&MBB, get(Opc)).addMBB(TBB); + BuildMI(&MBB, dl, get(Opc)).addMBB(TBB); ++Count; } } if (FBB) { // Two-way Conditional branch. Insert the second branch. - BuildMI(&MBB, get(X86::JMP)).addMBB(FBB); + BuildMI(&MBB, dl, get(X86::JMP)).addMBB(FBB); ++Count; } return Count; @@ -1944,7 +1946,7 @@ unsigned Reg = CSI[i-1].getReg(); // Add the callee-saved register as live-in. It's killed at the spill. MBB.addLiveIn(Reg); - BuildMI(MBB, MI, get(Opc)) + BuildMI(MBB, MI, DL, get(Opc)) .addReg(Reg, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); } return true; Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=64437&r1=64436&r2=64437&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Feb 12 20:33:27 2009 @@ -542,11 +542,14 @@ (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) : (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri)); uint64_t Chunk = (1LL << 31) - 1; + // We could pass in a DebugLoc, but this is only called from prolog/epilog. + DebugLoc DL = DebugLoc::getUnknownLoc(); while (Offset) { uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset; MachineInstr *MI = - BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal); + BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) + .addReg(StackPtr).addImm(ThisVal); // The EFLAGS implicit def is dead. MI->getOperand(3).setIsDead(); Offset -= ThisVal; From dalej at apple.com Thu Feb 12 20:34:40 2009 From: dalej at apple.com (Dale Johannesen) Date: Fri, 13 Feb 2009 02:34:40 -0000 Subject: [llvm-commits] [llvm] r64438 - in /llvm/trunk/lib/Target: IA64/IA64Bundling.cpp IA64/IA64ISelLowering.cpp IA64/IA64InstrInfo.cpp IA64/IA64RegisterInfo.cpp Mips/MipsDelaySlotFiller.cpp Mips/MipsISelLowering.cpp Mips/MipsInstrInfo.cpp Mips/MipsRegisterInfo.cpp Message-ID: <200902130234.n1D2YeDY028476@zion.cs.uiuc.edu> Author: johannes Date: Thu Feb 12 20:34:39 2009 New Revision: 64438 URL: http://llvm.org/viewvc/llvm-project?rev=64438&view=rev Log: Remove non-DebugLoc versions of BuildMI from IA64, Mips. Modified: llvm/trunk/lib/Target/IA64/IA64Bundling.cpp llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Modified: llvm/trunk/lib/Target/IA64/IA64Bundling.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64Bundling.cpp?rev=64438&r1=64437&r2=64438&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64Bundling.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64Bundling.cpp Thu Feb 12 20:34:39 2009 @@ -104,7 +104,7 @@ if(! (CurrentReads.empty() && CurrentWrites.empty()) ) { // there is a conflict, insert a stop and reset PendingRegWrites - CurrentInsn = BuildMI(MBB, CurrentInsn, + CurrentInsn = BuildMI(MBB, CurrentInsn, CurrentInsn->getDebugLoc(), TM.getInstrInfo()->get(IA64::STOP), 0); PendingRegWrites=OrigWrites; // carry over current writes to next insn Changed=true; StopBitsAdded++; // update stats Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp?rev=64438&r1=64437&r2=64438&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp Thu Feb 12 20:34:39 2009 @@ -243,7 +243,7 @@ // Create a vreg to hold the output of (what will become) // the "alloc" instruction VirtGPR = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); - BuildMI(&BB, TII->get(IA64::PSEUDO_ALLOC), VirtGPR); + BuildMI(&BB, dl, TII->get(IA64::PSEUDO_ALLOC), VirtGPR); // we create a PSEUDO_ALLOC (pseudo)instruction for now /* BuildMI(&BB, IA64::IDEF, 0, IA64::r1); @@ -273,14 +273,14 @@ // here we actually do the moving of args, and store them to the stack // too if this is a varargs function: for (int i = 0; i < count && i < 8; ++i) { - BuildMI(&BB, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]); + BuildMI(&BB, dl, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]); if(F.isVarArg()) { // if this is a varargs function, we copy the input registers to the stack int FI = MFI->CreateFixedObject(8, tempOffset); tempOffset+=8; //XXX: is it safe to use r22 like this? - BuildMI(&BB, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI); + BuildMI(&BB, dl, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI); // FIXME: we should use st8.spill here, one day - BuildMI(&BB, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]); + BuildMI(&BB, dl, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]); } } Modified: llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp?rev=64438&r1=64437&r2=64438&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp Thu Feb 12 20:34:39 2009 @@ -55,9 +55,11 @@ IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond)const { + // FIXME this should probably have a DebugLoc argument + DebugLoc dl = DebugLoc::getUnknownLoc(); // Can only insert uncond branches so far. assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!"); - BuildMI(&MBB, get(IA64::BRL_NOTCALL)).addMBB(TBB); + BuildMI(&MBB, dl, get(IA64::BRL_NOTCALL)).addMBB(TBB); return 1; } Modified: llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp?rev=64438&r1=64437&r2=64438&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp Thu Feb 12 20:34:39 2009 @@ -88,6 +88,7 @@ // ' MachineInstr *Old = I; unsigned Amount = Old->getOperand(0).getImm(); + DebugLoc dl = Old->getDebugLoc(); if (Amount != 0) { // We need to keep the stack aligned properly. To do this, we round the // amount of space needed for the outgoing arguments up to the next @@ -97,12 +98,12 @@ // Replace the pseudo instruction with a new instruction... if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) { - BuildMI(MBB, I, TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12) - .addImm(-Amount); + BuildMI(MBB, I, dl, TII.get(IA64::ADDIMM22), IA64::r12) + .addReg(IA64::r12).addImm(-Amount); } else { assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP); - BuildMI(MBB, I, TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12) - .addImm(Amount); + BuildMI(MBB, I, dl, TII.get(IA64::ADDIMM22), IA64::r12) + .addReg(IA64::r12).addImm(Amount); } } } @@ -118,6 +119,7 @@ MachineInstr &MI = *II; MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); + DebugLoc dl = MI.getDebugLoc(); bool FP = hasFP(MF); @@ -146,13 +148,13 @@ // Fix up the old: MI.getOperand(i).ChangeToRegister(IA64::r22, false); //insert the new - BuildMI(MBB, II, TII.get(IA64::ADDIMM22), IA64::r22) + BuildMI(MBB, II, dl, TII.get(IA64::ADDIMM22), IA64::r22) .addReg(BaseRegister).addImm(Offset); } else { // it's big //fix up the old: MI.getOperand(i).ChangeToRegister(IA64::r22, false); - BuildMI(MBB, II, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset); - BuildMI(MBB, II, TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister) + BuildMI(MBB, II, dl, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset); + BuildMI(MBB, II, dl, TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister) .addReg(IA64::r22); } @@ -163,6 +165,7 @@ MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); bool FP = hasFP(MF); + DebugLoc dl = DebugLoc::getUnknownLoc(); // first, we handle the 'alloc' instruction, that should be right up the // top of any function @@ -205,7 +208,7 @@ } } - BuildMI(MBB, MBBI, TII.get(IA64::ALLOC)). + BuildMI(MBB, MBBI, dl, TII.get(IA64::ALLOC)). addReg(dstRegOfPseudoAlloc).addImm(0). addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0); @@ -230,23 +233,24 @@ // adjust stack pointer: r12 -= numbytes if (NumBytes <= 8191) { - BuildMI(MBB, MBBI, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12). + BuildMI(MBB, MBBI, dl, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12). addImm(-NumBytes); } else { // we use r22 as a scratch register here // first load the decrement into r22 - BuildMI(MBB, MBBI, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes); + BuildMI(MBB, MBBI, dl, TII.get(IA64::MOVLIMM64), IA64::r22). + addImm(-NumBytes); // FIXME: MOVLSI32 expects a _u_32imm // then add (subtract) it to r12 (stack ptr) - BuildMI(MBB, MBBI, TII.get(IA64::ADD), IA64::r12) + BuildMI(MBB, MBBI, dl, TII.get(IA64::ADD), IA64::r12) .addReg(IA64::r12).addReg(IA64::r22); } // now if we need to, save the old FP and set the new if (FP) { - BuildMI(MBB, MBBI, TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5); + BuildMI(MBB, MBBI,dl,TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5); // this must be the last instr in the prolog ? (XXX: why??) - BuildMI(MBB, MBBI, TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12); + BuildMI(MBB, MBBI, dl, TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12); } } @@ -257,6 +261,7 @@ MachineBasicBlock::iterator MBBI = prior(MBB.end()); assert(MBBI->getOpcode() == IA64::RET && "Can only insert epilog into returning blocks"); + DebugLoc dl = DebugLoc::getUnknownLoc(); bool FP = hasFP(MF); @@ -267,20 +272,20 @@ if (FP) { //copy the FP into the SP (discards allocas) - BuildMI(MBB, MBBI, TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5); + BuildMI(MBB, MBBI, dl, TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5); //restore the FP - BuildMI(MBB, MBBI, TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5); + BuildMI(MBB, MBBI, dl, TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5); } if (NumBytes != 0) { if (NumBytes <= 8191) { - BuildMI(MBB, MBBI, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12). - addImm(NumBytes); + BuildMI(MBB, MBBI, dl, TII.get(IA64::ADDIMM22),IA64::r12). + addReg(IA64::r12).addImm(NumBytes); } else { - BuildMI(MBB, MBBI, TII.get(IA64::MOVLIMM64), IA64::r22). + BuildMI(MBB, MBBI, dl, TII.get(IA64::MOVLIMM64), IA64::r22). addImm(NumBytes); - BuildMI(MBB, MBBI, TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12). + BuildMI(MBB, MBBI, dl, TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12). addReg(IA64::r22); } } Modified: llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp?rev=64438&r1=64437&r2=64438&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp Thu Feb 12 20:34:39 2009 @@ -62,7 +62,7 @@ if (I->getDesc().hasDelaySlot()) { MachineBasicBlock::iterator J = I; ++J; - BuildMI(MBB, J, TII->get(Mips::NOP)); + BuildMI(MBB, J, I->getDebugLoc(), TII->get(Mips::NOP)); ++FilledSlots; Changed = true; } Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=64438&r1=64437&r2=64438&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Feb 12 20:34:39 2009 @@ -279,6 +279,7 @@ MachineBasicBlock *BB) const { const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); bool isFPCmp = false; + DebugLoc dl = MI->getDebugLoc(); switch (MI->getOpcode()) { default: assert(false && "Unexpected instr type to insert"); @@ -316,9 +317,9 @@ Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm(); // Get the branch opcode from the branch code. unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC)); - BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB); + BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); } else - BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg()) + BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg()) .addReg(Mips::ZERO).addMBB(sinkMBB); F->insert(It, copy0MBB); @@ -347,7 +348,7 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg()) + BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB); Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=64438&r1=64437&r2=64438&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Thu Feb 12 20:34:39 2009 @@ -554,6 +554,8 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const { + // FIXME this should probably have a DebugLoc argument + DebugLoc dl = DebugLoc::getUnknownLoc(); // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) && @@ -562,18 +564,18 @@ if (FBB == 0) { // One way branch. if (Cond.empty()) { // Unconditional branch? - BuildMI(&MBB, get(Mips::J)).addMBB(TBB); + BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB); } else { // Conditional branch. unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm()); const TargetInstrDesc &TID = get(Opc); if (TID.getNumOperands() == 3) - BuildMI(&MBB, TID).addReg(Cond[1].getReg()) + BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()) .addReg(Cond[2].getReg()) .addMBB(TBB); else - BuildMI(&MBB, TID).addReg(Cond[1].getReg()) + BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()) .addMBB(TBB); } @@ -585,12 +587,12 @@ const TargetInstrDesc &TID = get(Opc); if (TID.getNumOperands() == 3) - BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg()) + BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg()) .addMBB(TBB); else - BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addMBB(TBB); + BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB); - BuildMI(&MBB, get(Mips::J)).addMBB(FBB); + BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB); return 2; } Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=64438&r1=64437&r2=64438&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Thu Feb 12 20:34:39 2009 @@ -391,6 +391,7 @@ MachineFrameInfo *MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo(); MachineBasicBlock::iterator MBBI = MBB.begin(); + DebugLoc dl = DebugLoc::getUnknownLoc(); bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_); // Get the right frame order for Mips. @@ -405,21 +406,21 @@ int FPOffset = MipsFI->getFPStackOffset(); int RAOffset = MipsFI->getRAStackOffset(); - BuildMI(MBB, MBBI, TII.get(Mips::NOREORDER)); + BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER)); // TODO: check need from GP here. if (isPIC && Subtarget.isABI_O32()) - BuildMI(MBB, MBBI, TII.get(Mips::CPLOAD)).addReg(getPICCallReg()); - BuildMI(MBB, MBBI, TII.get(Mips::NOMACRO)); + BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD)).addReg(getPICCallReg()); + BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO)); // Adjust stack : addi sp, sp, (-imm) - BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP) + BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP) .addReg(Mips::SP).addImm(-StackSize); // Save the return address only if the function isnt a leaf one. // sw $ra, stack_loc($sp) if (MFI->hasCalls()) { - BuildMI(MBB, MBBI, TII.get(Mips::SW)) + BuildMI(MBB, MBBI, dl, TII.get(Mips::SW)) .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP); } @@ -427,17 +428,17 @@ // to point to the stack pointer if (hasFP(MF)) { // sw $fp,stack_loc($sp) - BuildMI(MBB, MBBI, TII.get(Mips::SW)) + BuildMI(MBB, MBBI, dl, TII.get(Mips::SW)) .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP); // move $fp, $sp - BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::FP) + BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP) .addReg(Mips::SP).addReg(Mips::ZERO); } // PIC speficic function prologue if ((isPIC) && (MFI->hasCalls())) { - BuildMI(MBB, MBBI, TII.get(Mips::CPRESTORE)) + BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE)) .addImm(MipsFI->getGPStackOffset()); } } @@ -448,6 +449,7 @@ MachineBasicBlock::iterator MBBI = prior(MBB.end()); MachineFrameInfo *MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo(); + DebugLoc dl = DebugLoc::getUnknownLoc(); // Get the number of bytes from FrameInfo int NumBytes = (int) MFI->getStackSize(); @@ -460,24 +462,24 @@ // stack pointer if (hasFP(MF)) { // move $sp, $fp - BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::SP) + BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::SP) .addReg(Mips::FP).addReg(Mips::ZERO); // lw $fp,stack_loc($sp) - BuildMI(MBB, MBBI, TII.get(Mips::LW)) + BuildMI(MBB, MBBI, dl, TII.get(Mips::LW)) .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP); } // Restore the return address only if the function isnt a leaf one. // lw $ra, stack_loc($sp) if (MFI->hasCalls()) { - BuildMI(MBB, MBBI, TII.get(Mips::LW)) + BuildMI(MBB, MBBI, dl, TII.get(Mips::LW)) .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP); } // adjust stack : insert addi sp, sp, (imm) if (NumBytes) { - BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP) + BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP) .addReg(Mips::SP).addImm(NumBytes); } } From dalej at apple.com Thu Feb 12 20:35:20 2009 From: dalej at apple.com (Dale Johannesen) Date: Fri, 13 Feb 2009 02:35:20 -0000 Subject: [llvm-commits] [llvm] r64439 - /llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Message-ID: <200902130235.n1D2ZLcp028503@zion.cs.uiuc.edu> Author: johannes Date: Thu Feb 12 20:35:20 2009 New Revision: 64439 URL: http://llvm.org/viewvc/llvm-project?rev=64439&view=rev Log: Remove non-DebugLoc versions of BuildMI. "I got blisters on my fingers." Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=64439&r1=64438&r2=64439&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Thu Feb 12 20:35:20 2009 @@ -121,15 +121,6 @@ /// inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, - const TargetInstrDesc &TID, - unsigned DestReg) { - MachineInstr *MI = - BB.getParent()->CreateMachineInstr(TID, DebugLoc::getUnknownLoc()); - BB.insert(I, MI); - return MachineInstrBuilder(MI).addReg(DestReg, true); -} -inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, - MachineBasicBlock::iterator I, DebugLoc DL, const TargetInstrDesc &TID, unsigned DestReg) { @@ -144,14 +135,6 @@ /// inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, - const TargetInstrDesc &TID) { - MachineInstr *MI = - BB.getParent()->CreateMachineInstr(TID, DebugLoc::getUnknownLoc()); - BB.insert(I, MI); - return MachineInstrBuilder(MI); -} -inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, - MachineBasicBlock::iterator I, DebugLoc DL, const TargetInstrDesc &TID) { MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID, DL); @@ -164,10 +147,6 @@ /// destination register. /// inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, - const TargetInstrDesc &TID) { - return BuildMI(*BB, BB->end(), TID); -} -inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, DebugLoc DL, const TargetInstrDesc &TID) { return BuildMI(*BB, BB->end(), DL, TID); @@ -178,11 +157,6 @@ /// operand as a destination virtual register. /// inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, - const TargetInstrDesc &TID, - unsigned DestReg) { - return BuildMI(*BB, BB->end(), TID, DestReg); -} -inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, DebugLoc DL, const TargetInstrDesc &TID, unsigned DestReg) { From gohman at apple.com Thu Feb 12 21:58:31 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 13 Feb 2009 03:58:31 -0000 Subject: [llvm-commits] [llvm] r64440 - in /llvm/trunk: lib/Transforms/Scalar/LoopStrengthReduce.cpp test/CodeGen/X86/iv-users-in-other-loops.ll Message-ID: <200902130358.n1D3wVeY031042@zion.cs.uiuc.edu> Author: djg Date: Thu Feb 12 21:58:31 2009 New Revision: 64440 URL: http://llvm.org/viewvc/llvm-project?rev=64440&view=rev Log: Fix the code that checked if a SCEVAddRecExpr Start contains an addrec in a different loop to check the value being added to the accumulated Start value, not the Start value before it has the new value added to it. This prevents LSR from going crazy on the included testcase. Dale, please review. Added: llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=64440&r1=64439&r2=64440&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Thu Feb 12 21:58:31 2009 @@ -432,7 +432,7 @@ // If Start contains an SCEVAddRecExpr from a different loop, other than an // outer loop of the current loop, reject it. SCEV has no concept of // operating on one loop at a time so don't confuse it with such expressions. - if (containsAddRecFromDifferentLoop(Start, L)) + if (containsAddRecFromDifferentLoop(AddRec->getOperand(0), L)) return false; Start = SE->getAddExpr(Start, AddRec->getOperand(0)); Added: llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll?rev=64440&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll (added) +++ llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll Thu Feb 12 21:58:31 2009 @@ -0,0 +1,292 @@ +; RUN: llvm-as < %s | llc -march=x86-64 -f -o %t +; RUN: grep inc %t | count 2 +; RUN: grep addq %t | count 11 + +; IV users in each of the loops from other loops shouldn't cause LSR +; to insert new induction variables. Previously it would create a +; flood of new induction variables. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-unknown-linux-gnu" + +define void @foo(float* %A, i32 %IA, float* %B, i32 %IB, float* nocapture %C, i32 %N) nounwind { +entry: + %0 = xor i32 %IA, 1 ; [#uses=1] + %1 = xor i32 %IB, 1 ; [#uses=1] + %2 = or i32 %1, %0 ; [#uses=1] + %3 = icmp eq i32 %2, 0 ; [#uses=1] + br i1 %3, label %bb2, label %bb13 + +bb: ; preds = %bb3 + %4 = load float* %A_addr.0, align 4 ; [#uses=1] + %5 = load float* %B_addr.0, align 4 ; [#uses=1] + %6 = mul float %4, %5 ; [#uses=1] + %7 = add float %6, %Sum0.0 ; [#uses=1] + %indvar.next154 = add i64 %B_addr.0.rec, 1 ; [#uses=1] + br label %bb2 + +bb2: ; preds = %entry, %bb + %B_addr.0.rec = phi i64 [ %indvar.next154, %bb ], [ 0, %entry ] ; [#uses=14] + %Sum0.0 = phi float [ %7, %bb ], [ 0.000000e+00, %entry ] ; [#uses=5] + %indvar146 = trunc i64 %B_addr.0.rec to i32 ; [#uses=1] + %N_addr.0 = sub i32 %N, %indvar146 ; [#uses=6] + %A_addr.0 = getelementptr float* %A, i64 %B_addr.0.rec ; [#uses=4] + %B_addr.0 = getelementptr float* %B, i64 %B_addr.0.rec ; [#uses=4] + %8 = icmp sgt i32 %N_addr.0, 0 ; [#uses=1] + br i1 %8, label %bb3, label %bb4 + +bb3: ; preds = %bb2 + %9 = ptrtoint float* %A_addr.0 to i64 ; [#uses=1] + %10 = and i64 %9, 15 ; [#uses=1] + %11 = icmp eq i64 %10, 0 ; [#uses=1] + br i1 %11, label %bb4, label %bb + +bb4: ; preds = %bb3, %bb2 + %12 = ptrtoint float* %B_addr.0 to i64 ; [#uses=1] + %13 = and i64 %12, 15 ; [#uses=1] + %14 = icmp eq i64 %13, 0 ; [#uses=1] + %15 = icmp sgt i32 %N_addr.0, 15 ; [#uses=2] + br i1 %14, label %bb6.preheader, label %bb10.preheader + +bb10.preheader: ; preds = %bb4 + br i1 %15, label %bb9, label %bb12.loopexit + +bb6.preheader: ; preds = %bb4 + br i1 %15, label %bb5, label %bb8.loopexit + +bb5: ; preds = %bb5, %bb6.preheader + %indvar143 = phi i64 [ 0, %bb6.preheader ], [ %indvar.next144, %bb5 ] ; [#uses=3] + %vSum0.072 = phi <4 x float> [ zeroinitializer, %bb6.preheader ], [ %21, %bb5 ] ; <<4 x float>> [#uses=1] + %vSum1.070 = phi <4 x float> [ zeroinitializer, %bb6.preheader ], [ %29, %bb5 ] ; <<4 x float>> [#uses=1] + %vSum2.069 = phi <4 x float> [ zeroinitializer, %bb6.preheader ], [ %37, %bb5 ] ; <<4 x float>> [#uses=1] + %vSum3.067 = phi <4 x float> [ zeroinitializer, %bb6.preheader ], [ %45, %bb5 ] ; <<4 x float>> [#uses=1] + %indvar145 = trunc i64 %indvar143 to i32 ; [#uses=1] + %tmp150 = mul i32 %indvar145, -16 ; [#uses=1] + %N_addr.268 = add i32 %tmp150, %N_addr.0 ; [#uses=1] + %A_addr.273.rec = shl i64 %indvar143, 4 ; [#uses=5] + %B_addr.0.sum180 = add i64 %B_addr.0.rec, %A_addr.273.rec ; [#uses=2] + %B_addr.271 = getelementptr float* %B, i64 %B_addr.0.sum180 ; [#uses=1] + %A_addr.273 = getelementptr float* %A, i64 %B_addr.0.sum180 ; [#uses=1] + tail call void asm sideeffect ";# foo", "~{dirflag},~{fpsr},~{flags}"() nounwind + %16 = bitcast float* %A_addr.273 to <4 x float>* ; <<4 x float>*> [#uses=1] + %17 = load <4 x float>* %16, align 16 ; <<4 x float>> [#uses=1] + %18 = bitcast float* %B_addr.271 to <4 x float>* ; <<4 x float>*> [#uses=1] + %19 = load <4 x float>* %18, align 16 ; <<4 x float>> [#uses=1] + %20 = mul <4 x float> %17, %19 ; <<4 x float>> [#uses=1] + %21 = add <4 x float> %20, %vSum0.072 ; <<4 x float>> [#uses=2] + %A_addr.273.sum163 = or i64 %A_addr.273.rec, 4 ; [#uses=1] + %A_addr.0.sum175 = add i64 %B_addr.0.rec, %A_addr.273.sum163 ; [#uses=2] + %22 = getelementptr float* %A, i64 %A_addr.0.sum175 ; [#uses=1] + %23 = bitcast float* %22 to <4 x float>* ; <<4 x float>*> [#uses=1] + %24 = load <4 x float>* %23, align 16 ; <<4 x float>> [#uses=1] + %25 = getelementptr float* %B, i64 %A_addr.0.sum175 ; [#uses=1] + %26 = bitcast float* %25 to <4 x float>* ; <<4 x float>*> [#uses=1] + %27 = load <4 x float>* %26, align 16 ; <<4 x float>> [#uses=1] + %28 = mul <4 x float> %24, %27 ; <<4 x float>> [#uses=1] + %29 = add <4 x float> %28, %vSum1.070 ; <<4 x float>> [#uses=2] + %A_addr.273.sum161 = or i64 %A_addr.273.rec, 8 ; [#uses=1] + %A_addr.0.sum174 = add i64 %B_addr.0.rec, %A_addr.273.sum161 ; [#uses=2] + %30 = getelementptr float* %A, i64 %A_addr.0.sum174 ; [#uses=1] + %31 = bitcast float* %30 to <4 x float>* ; <<4 x float>*> [#uses=1] + %32 = load <4 x float>* %31, align 16 ; <<4 x float>> [#uses=1] + %33 = getelementptr float* %B, i64 %A_addr.0.sum174 ; [#uses=1] + %34 = bitcast float* %33 to <4 x float>* ; <<4 x float>*> [#uses=1] + %35 = load <4 x float>* %34, align 16 ; <<4 x float>> [#uses=1] + %36 = mul <4 x float> %32, %35 ; <<4 x float>> [#uses=1] + %37 = add <4 x float> %36, %vSum2.069 ; <<4 x float>> [#uses=2] + %A_addr.273.sum159 = or i64 %A_addr.273.rec, 12 ; [#uses=1] + %A_addr.0.sum173 = add i64 %B_addr.0.rec, %A_addr.273.sum159 ; [#uses=2] + %38 = getelementptr float* %A, i64 %A_addr.0.sum173 ; [#uses=1] + %39 = bitcast float* %38 to <4 x float>* ; <<4 x float>*> [#uses=1] + %40 = load <4 x float>* %39, align 16 ; <<4 x float>> [#uses=1] + %41 = getelementptr float* %B, i64 %A_addr.0.sum173 ; [#uses=1] + %42 = bitcast float* %41 to <4 x float>* ; <<4 x float>*> [#uses=1] + %43 = load <4 x float>* %42, align 16 ; <<4 x float>> [#uses=1] + %44 = mul <4 x float> %40, %43 ; <<4 x float>> [#uses=1] + %45 = add <4 x float> %44, %vSum3.067 ; <<4 x float>> [#uses=2] + %.rec83 = add i64 %A_addr.273.rec, 16 ; [#uses=1] + %A_addr.0.sum172 = add i64 %B_addr.0.rec, %.rec83 ; [#uses=2] + %46 = getelementptr float* %A, i64 %A_addr.0.sum172 ; [#uses=1] + %47 = getelementptr float* %B, i64 %A_addr.0.sum172 ; [#uses=1] + %48 = add i32 %N_addr.268, -16 ; [#uses=2] + %49 = icmp sgt i32 %48, 15 ; [#uses=1] + %indvar.next144 = add i64 %indvar143, 1 ; [#uses=1] + br i1 %49, label %bb5, label %bb8.loopexit + +bb7: ; preds = %bb7, %bb8.loopexit + %indvar130 = phi i64 [ 0, %bb8.loopexit ], [ %indvar.next131, %bb7 ] ; [#uses=3] + %vSum0.260 = phi <4 x float> [ %vSum0.0.lcssa, %bb8.loopexit ], [ %55, %bb7 ] ; <<4 x float>> [#uses=1] + %indvar132 = trunc i64 %indvar130 to i32 ; [#uses=1] + %tmp133 = mul i32 %indvar132, -4 ; [#uses=1] + %N_addr.358 = add i32 %tmp133, %N_addr.2.lcssa ; [#uses=1] + %A_addr.361.rec = shl i64 %indvar130, 2 ; [#uses=3] + %B_addr.359 = getelementptr float* %B_addr.2.lcssa, i64 %A_addr.361.rec ; [#uses=1] + %A_addr.361 = getelementptr float* %A_addr.2.lcssa, i64 %A_addr.361.rec ; [#uses=1] + %50 = bitcast float* %A_addr.361 to <4 x float>* ; <<4 x float>*> [#uses=1] + %51 = load <4 x float>* %50, align 16 ; <<4 x float>> [#uses=1] + %52 = bitcast float* %B_addr.359 to <4 x float>* ; <<4 x float>*> [#uses=1] + %53 = load <4 x float>* %52, align 16 ; <<4 x float>> [#uses=1] + %54 = mul <4 x float> %51, %53 ; <<4 x float>> [#uses=1] + %55 = add <4 x float> %54, %vSum0.260 ; <<4 x float>> [#uses=2] + %.rec85 = add i64 %A_addr.361.rec, 4 ; [#uses=2] + %56 = getelementptr float* %A_addr.2.lcssa, i64 %.rec85 ; [#uses=1] + %57 = getelementptr float* %B_addr.2.lcssa, i64 %.rec85 ; [#uses=1] + %58 = add i32 %N_addr.358, -4 ; [#uses=2] + %59 = icmp sgt i32 %58, 3 ; [#uses=1] + %indvar.next131 = add i64 %indvar130, 1 ; [#uses=1] + br i1 %59, label %bb7, label %bb13 + +bb8.loopexit: ; preds = %bb5, %bb6.preheader + %A_addr.2.lcssa = phi float* [ %A_addr.0, %bb6.preheader ], [ %46, %bb5 ] ; [#uses=3] + %vSum0.0.lcssa = phi <4 x float> [ zeroinitializer, %bb6.preheader ], [ %21, %bb5 ] ; <<4 x float>> [#uses=2] + %B_addr.2.lcssa = phi float* [ %B_addr.0, %bb6.preheader ], [ %47, %bb5 ] ; [#uses=3] + %vSum1.0.lcssa = phi <4 x float> [ zeroinitializer, %bb6.preheader ], [ %29, %bb5 ] ; <<4 x float>> [#uses=2] + %vSum2.0.lcssa = phi <4 x float> [ zeroinitializer, %bb6.preheader ], [ %37, %bb5 ] ; <<4 x float>> [#uses=2] + %N_addr.2.lcssa = phi i32 [ %N_addr.0, %bb6.preheader ], [ %48, %bb5 ] ; [#uses=3] + %vSum3.0.lcssa = phi <4 x float> [ zeroinitializer, %bb6.preheader ], [ %45, %bb5 ] ; <<4 x float>> [#uses=2] + %60 = icmp sgt i32 %N_addr.2.lcssa, 3 ; [#uses=1] + br i1 %60, label %bb7, label %bb13 + +bb9: ; preds = %bb9, %bb10.preheader + %indvar106 = phi i64 [ 0, %bb10.preheader ], [ %indvar.next107, %bb9 ] ; [#uses=3] + %vSum0.339 = phi <4 x float> [ zeroinitializer, %bb10.preheader ], [ %75, %bb9 ] ; <<4 x float>> [#uses=1] + %vSum1.237 = phi <4 x float> [ zeroinitializer, %bb10.preheader ], [ %80, %bb9 ] ; <<4 x float>> [#uses=1] + %vSum2.236 = phi <4 x float> [ zeroinitializer, %bb10.preheader ], [ %85, %bb9 ] ; <<4 x float>> [#uses=1] + %vSum3.234 = phi <4 x float> [ zeroinitializer, %bb10.preheader ], [ %90, %bb9 ] ; <<4 x float>> [#uses=1] + %indvar108 = trunc i64 %indvar106 to i32 ; [#uses=1] + %tmp113 = mul i32 %indvar108, -16 ; [#uses=1] + %N_addr.435 = add i32 %tmp113, %N_addr.0 ; [#uses=1] + %A_addr.440.rec = shl i64 %indvar106, 4 ; [#uses=5] + %B_addr.0.sum = add i64 %B_addr.0.rec, %A_addr.440.rec ; [#uses=2] + %B_addr.438 = getelementptr float* %B, i64 %B_addr.0.sum ; [#uses=1] + %A_addr.440 = getelementptr float* %A, i64 %B_addr.0.sum ; [#uses=1] + %61 = bitcast float* %B_addr.438 to i8* ; [#uses=1] + %62 = tail call <4 x float> @llvm.x86.sse.loadu.ps(i8* %61) nounwind readonly ; <<4 x float>> [#uses=1] + %B_addr.438.sum169 = or i64 %A_addr.440.rec, 4 ; [#uses=1] + %B_addr.0.sum187 = add i64 %B_addr.0.rec, %B_addr.438.sum169 ; [#uses=2] + %63 = getelementptr float* %B, i64 %B_addr.0.sum187 ; [#uses=1] + %64 = bitcast float* %63 to i8* ; [#uses=1] + %65 = tail call <4 x float> @llvm.x86.sse.loadu.ps(i8* %64) nounwind readonly ; <<4 x float>> [#uses=1] + %B_addr.438.sum168 = or i64 %A_addr.440.rec, 8 ; [#uses=1] + %B_addr.0.sum186 = add i64 %B_addr.0.rec, %B_addr.438.sum168 ; [#uses=2] + %66 = getelementptr float* %B, i64 %B_addr.0.sum186 ; [#uses=1] + %67 = bitcast float* %66 to i8* ; [#uses=1] + %68 = tail call <4 x float> @llvm.x86.sse.loadu.ps(i8* %67) nounwind readonly ; <<4 x float>> [#uses=1] + %B_addr.438.sum167 = or i64 %A_addr.440.rec, 12 ; [#uses=1] + %B_addr.0.sum185 = add i64 %B_addr.0.rec, %B_addr.438.sum167 ; [#uses=2] + %69 = getelementptr float* %B, i64 %B_addr.0.sum185 ; [#uses=1] + %70 = bitcast float* %69 to i8* ; [#uses=1] + %71 = tail call <4 x float> @llvm.x86.sse.loadu.ps(i8* %70) nounwind readonly ; <<4 x float>> [#uses=1] + %72 = bitcast float* %A_addr.440 to <4 x float>* ; <<4 x float>*> [#uses=1] + %73 = load <4 x float>* %72, align 16 ; <<4 x float>> [#uses=1] + %74 = mul <4 x float> %73, %62 ; <<4 x float>> [#uses=1] + %75 = add <4 x float> %74, %vSum0.339 ; <<4 x float>> [#uses=2] + %76 = getelementptr float* %A, i64 %B_addr.0.sum187 ; [#uses=1] + %77 = bitcast float* %76 to <4 x float>* ; <<4 x float>*> [#uses=1] + %78 = load <4 x float>* %77, align 16 ; <<4 x float>> [#uses=1] + %79 = mul <4 x float> %78, %65 ; <<4 x float>> [#uses=1] + %80 = add <4 x float> %79, %vSum1.237 ; <<4 x float>> [#uses=2] + %81 = getelementptr float* %A, i64 %B_addr.0.sum186 ; [#uses=1] + %82 = bitcast float* %81 to <4 x float>* ; <<4 x float>*> [#uses=1] + %83 = load <4 x float>* %82, align 16 ; <<4 x float>> [#uses=1] + %84 = mul <4 x float> %83, %68 ; <<4 x float>> [#uses=1] + %85 = add <4 x float> %84, %vSum2.236 ; <<4 x float>> [#uses=2] + %86 = getelementptr float* %A, i64 %B_addr.0.sum185 ; [#uses=1] + %87 = bitcast float* %86 to <4 x float>* ; <<4 x float>*> [#uses=1] + %88 = load <4 x float>* %87, align 16 ; <<4 x float>> [#uses=1] + %89 = mul <4 x float> %88, %71 ; <<4 x float>> [#uses=1] + %90 = add <4 x float> %89, %vSum3.234 ; <<4 x float>> [#uses=2] + %.rec89 = add i64 %A_addr.440.rec, 16 ; [#uses=1] + %A_addr.0.sum170 = add i64 %B_addr.0.rec, %.rec89 ; [#uses=2] + %91 = getelementptr float* %A, i64 %A_addr.0.sum170 ; [#uses=1] + %92 = getelementptr float* %B, i64 %A_addr.0.sum170 ; [#uses=1] + %93 = add i32 %N_addr.435, -16 ; [#uses=2] + %94 = icmp sgt i32 %93, 15 ; [#uses=1] + %indvar.next107 = add i64 %indvar106, 1 ; [#uses=1] + br i1 %94, label %bb9, label %bb12.loopexit + +bb11: ; preds = %bb11, %bb12.loopexit + %indvar = phi i64 [ 0, %bb12.loopexit ], [ %indvar.next, %bb11 ] ; [#uses=3] + %vSum0.428 = phi <4 x float> [ %vSum0.3.lcssa, %bb12.loopexit ], [ %100, %bb11 ] ; <<4 x float>> [#uses=1] + %indvar96 = trunc i64 %indvar to i32 ; [#uses=1] + %tmp = mul i32 %indvar96, -4 ; [#uses=1] + %N_addr.526 = add i32 %tmp, %N_addr.4.lcssa ; [#uses=1] + %A_addr.529.rec = shl i64 %indvar, 2 ; [#uses=3] + %B_addr.527 = getelementptr float* %B_addr.4.lcssa, i64 %A_addr.529.rec ; [#uses=1] + %A_addr.529 = getelementptr float* %A_addr.4.lcssa, i64 %A_addr.529.rec ; [#uses=1] + %95 = bitcast float* %B_addr.527 to i8* ; [#uses=1] + %96 = tail call <4 x float> @llvm.x86.sse.loadu.ps(i8* %95) nounwind readonly ; <<4 x float>> [#uses=1] + %97 = bitcast float* %A_addr.529 to <4 x float>* ; <<4 x float>*> [#uses=1] + %98 = load <4 x float>* %97, align 16 ; <<4 x float>> [#uses=1] + %99 = mul <4 x float> %98, %96 ; <<4 x float>> [#uses=1] + %100 = add <4 x float> %99, %vSum0.428 ; <<4 x float>> [#uses=2] + %.rec91 = add i64 %A_addr.529.rec, 4 ; [#uses=2] + %101 = getelementptr float* %A_addr.4.lcssa, i64 %.rec91 ; [#uses=1] + %102 = getelementptr float* %B_addr.4.lcssa, i64 %.rec91 ; [#uses=1] + %103 = add i32 %N_addr.526, -4 ; [#uses=2] + %104 = icmp sgt i32 %103, 3 ; [#uses=1] + %indvar.next = add i64 %indvar, 1 ; [#uses=1] + br i1 %104, label %bb11, label %bb13 + +bb12.loopexit: ; preds = %bb9, %bb10.preheader + %A_addr.4.lcssa = phi float* [ %A_addr.0, %bb10.preheader ], [ %91, %bb9 ] ; [#uses=3] + %vSum0.3.lcssa = phi <4 x float> [ zeroinitializer, %bb10.preheader ], [ %75, %bb9 ] ; <<4 x float>> [#uses=2] + %B_addr.4.lcssa = phi float* [ %B_addr.0, %bb10.preheader ], [ %92, %bb9 ] ; [#uses=3] + %vSum1.2.lcssa = phi <4 x float> [ zeroinitializer, %bb10.preheader ], [ %80, %bb9 ] ; <<4 x float>> [#uses=2] + %vSum2.2.lcssa = phi <4 x float> [ zeroinitializer, %bb10.preheader ], [ %85, %bb9 ] ; <<4 x float>> [#uses=2] + %N_addr.4.lcssa = phi i32 [ %N_addr.0, %bb10.preheader ], [ %93, %bb9 ] ; [#uses=3] + %vSum3.2.lcssa = phi <4 x float> [ zeroinitializer, %bb10.preheader ], [ %90, %bb9 ] ; <<4 x float>> [#uses=2] + %105 = icmp sgt i32 %N_addr.4.lcssa, 3 ; [#uses=1] + br i1 %105, label %bb11, label %bb13 + +bb13: ; preds = %bb12.loopexit, %bb11, %bb8.loopexit, %bb7, %entry + %Sum0.1 = phi float [ 0.000000e+00, %entry ], [ %Sum0.0, %bb7 ], [ %Sum0.0, %bb8.loopexit ], [ %Sum0.0, %bb11 ], [ %Sum0.0, %bb12.loopexit ] ; [#uses=1] + %vSum3.1 = phi <4 x float> [ zeroinitializer, %entry ], [ %vSum3.0.lcssa, %bb7 ], [ %vSum3.0.lcssa, %bb8.loopexit ], [ %vSum3.2.lcssa, %bb11 ], [ %vSum3.2.lcssa, %bb12.loopexit ] ; <<4 x float>> [#uses=1] + %N_addr.1 = phi i32 [ %N, %entry ], [ %N_addr.2.lcssa, %bb8.loopexit ], [ %58, %bb7 ], [ %N_addr.4.lcssa, %bb12.loopexit ], [ %103, %bb11 ] ; [#uses=2] + %vSum2.1 = phi <4 x float> [ zeroinitializer, %entry ], [ %vSum2.0.lcssa, %bb7 ], [ %vSum2.0.lcssa, %bb8.loopexit ], [ %vSum2.2.lcssa, %bb11 ], [ %vSum2.2.lcssa, %bb12.loopexit ] ; <<4 x float>> [#uses=1] + %vSum1.1 = phi <4 x float> [ zeroinitializer, %entry ], [ %vSum1.0.lcssa, %bb7 ], [ %vSum1.0.lcssa, %bb8.loopexit ], [ %vSum1.2.lcssa, %bb11 ], [ %vSum1.2.lcssa, %bb12.loopexit ] ; <<4 x float>> [#uses=1] + %B_addr.1 = phi float* [ %B, %entry ], [ %B_addr.2.lcssa, %bb8.loopexit ], [ %57, %bb7 ], [ %B_addr.4.lcssa, %bb12.loopexit ], [ %102, %bb11 ] ; [#uses=1] + %vSum0.1 = phi <4 x float> [ zeroinitializer, %entry ], [ %vSum0.0.lcssa, %bb8.loopexit ], [ %55, %bb7 ], [ %vSum0.3.lcssa, %bb12.loopexit ], [ %100, %bb11 ] ; <<4 x float>> [#uses=1] + %A_addr.1 = phi float* [ %A, %entry ], [ %A_addr.2.lcssa, %bb8.loopexit ], [ %56, %bb7 ], [ %A_addr.4.lcssa, %bb12.loopexit ], [ %101, %bb11 ] ; [#uses=1] + %106 = add <4 x float> %vSum0.1, %vSum2.1 ; <<4 x float>> [#uses=1] + %107 = add <4 x float> %vSum1.1, %vSum3.1 ; <<4 x float>> [#uses=1] + %108 = add <4 x float> %106, %107 ; <<4 x float>> [#uses=4] + %tmp23 = extractelement <4 x float> %108, i32 0 ; [#uses=1] + %tmp21 = extractelement <4 x float> %108, i32 1 ; [#uses=1] + %109 = add float %tmp23, %tmp21 ; [#uses=1] + %tmp19 = extractelement <4 x float> %108, i32 2 ; [#uses=1] + %tmp17 = extractelement <4 x float> %108, i32 3 ; [#uses=1] + %110 = add float %tmp19, %tmp17 ; [#uses=1] + %111 = add float %109, %110 ; [#uses=1] + %Sum0.254 = add float %111, %Sum0.1 ; [#uses=2] + %112 = icmp sgt i32 %N_addr.1, 0 ; [#uses=1] + br i1 %112, label %bb.nph56, label %bb16 + +bb.nph56: ; preds = %bb13 + %tmp. = zext i32 %N_addr.1 to i64 ; [#uses=1] + br label %bb14 + +bb14: ; preds = %bb14, %bb.nph56 + %indvar117 = phi i64 [ 0, %bb.nph56 ], [ %indvar.next118, %bb14 ] ; [#uses=3] + %Sum0.255 = phi float [ %Sum0.254, %bb.nph56 ], [ %Sum0.2, %bb14 ] ; [#uses=1] + %tmp.122 = sext i32 %IB to i64 ; [#uses=1] + %B_addr.652.rec = mul i64 %indvar117, %tmp.122 ; [#uses=1] + %tmp.124 = sext i32 %IA to i64 ; [#uses=1] + %A_addr.653.rec = mul i64 %indvar117, %tmp.124 ; [#uses=1] + %B_addr.652 = getelementptr float* %B_addr.1, i64 %B_addr.652.rec ; [#uses=1] + %A_addr.653 = getelementptr float* %A_addr.1, i64 %A_addr.653.rec ; [#uses=1] + %113 = load float* %A_addr.653, align 4 ; [#uses=1] + %114 = load float* %B_addr.652, align 4 ; [#uses=1] + %115 = mul float %113, %114 ; [#uses=1] + %Sum0.2 = add float %115, %Sum0.255 ; [#uses=2] + %indvar.next118 = add i64 %indvar117, 1 ; [#uses=2] + %exitcond = icmp eq i64 %indvar.next118, %tmp. ; [#uses=1] + br i1 %exitcond, label %bb16, label %bb14 + +bb16: ; preds = %bb14, %bb13 + %Sum0.2.lcssa = phi float [ %Sum0.254, %bb13 ], [ %Sum0.2, %bb14 ] ; [#uses=1] + store float %Sum0.2.lcssa, float* %C, align 4 + ret void +} + +declare <4 x float> @llvm.x86.sse.loadu.ps(i8*) nounwind readonly From nicholas at mxc.ca Thu Feb 12 22:18:00 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 12 Feb 2009 20:18:00 -0800 Subject: [llvm-commits] [llvm] r64428 - in /llvm/trunk/lib: CodeGen/SelectionDAG/FastISel.cpp CodeGen/SelectionDAG/LegalizeDAG.cpp CodeGen/SelectionDAG/SelectionDAGBuild.cpp CodeGen/VirtRegMap.cpp Target/X86/X86RegisterInfo.cpp In-Reply-To: <200902130216.n1D2GbNa027809@zion.cs.uiuc.edu> References: <200902130216.n1D2GbNa027809@zion.cs.uiuc.edu> Message-ID: <4994F478.4050303@mxc.ca> Bill Wendling wrote: > Author: void > Date: Thu Feb 12 20:16:35 2009 > New Revision: 64428 > > URL: http://llvm.org/viewvc/llvm-project?rev=64428&view=rev > Log: > Revert this. It was breaking stuff. Revert what? Nick > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp > llvm/trunk/lib/CodeGen/VirtRegMap.cpp > llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=64428&r1=64427&r2=64428&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Feb 12 20:16:35 2009 > @@ -323,21 +323,32 @@ > CU.getFilename()); > unsigned Line = SPI->getLine(); > unsigned Col = SPI->getColumn(); > + unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile); > unsigned Idx = MF.getOrCreateDebugLocID(SrcFile, Line, Col); > setCurDebugLoc(DebugLoc::get(Idx)); > + const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); > + BuildMI(MBB, DL, II).addImm(ID); > } > return true; > } > case Intrinsic::dbg_region_start: { > DbgRegionStartInst *RSI = cast(I); > - if (DW && DW->ValidDebugInfo(RSI->getContext())) > - DW->RecordRegionStart(cast(RSI->getContext())); > + if (DW && DW->ValidDebugInfo(RSI->getContext())) { > + unsigned ID = > + DW->RecordRegionStart(cast(RSI->getContext())); > + const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); > + BuildMI(MBB, DL, II).addImm(ID); > + } > return true; > } > case Intrinsic::dbg_region_end: { > DbgRegionEndInst *REI = cast(I); > - if (DW && DW->ValidDebugInfo(REI->getContext())) > - DW->RecordRegionEnd(cast(REI->getContext())); > + if (DW && DW->ValidDebugInfo(REI->getContext())) { > + unsigned ID = > + DW->RecordRegionEnd(cast(REI->getContext())); > + const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); > + BuildMI(MBB, DL, II).addImm(ID); > + } > return true; > } > case Intrinsic::dbg_func_start: { > @@ -357,14 +368,42 @@ > // function start. It will be emitted at asm emission time. However, > // create a label if this is a beginning of inlined function. > unsigned Line = Subprogram.getLineNumber(); > + unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile); > setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0))); > + > + if (DW->getRecordSourceLineCount() != 1) { > + const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); > + BuildMI(MBB, DL, II).addImm(LabelID); > + } > } > > return true; > } > - case Intrinsic::dbg_declare: > - // FIXME: Do something correct here when declare stuff is working again. > + case Intrinsic::dbg_declare: { > + DbgDeclareInst *DI = cast(I); > + Value *Variable = DI->getVariable(); > + if (DW && DW->ValidDebugInfo(Variable)) { > + // Determine the address of the declared object. > + Value *Address = DI->getAddress(); > + if (BitCastInst *BCI = dyn_cast(Address)) > + Address = BCI->getOperand(0); > + AllocaInst *AI = dyn_cast(Address); > + // Don't handle byval struct arguments or VLAs, for example. > + if (!AI) break; > + DenseMap::iterator SI = > + StaticAllocaMap.find(AI); > + if (SI == StaticAllocaMap.end()) break; // VLAs. > + int FI = SI->second; > + > + // Determine the debug globalvariable. > + GlobalValue *GV = cast(Variable); > + > + // Build the DECLARE instruction. > + const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE); > + BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV); > + } > return true; > + } > case Intrinsic::eh_exception: { > MVT VT = TLI.getValueType(I->getType()); > switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=64428&r1=64427&r2=64428&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Feb 12 20:16:35 2009 > @@ -1274,9 +1274,38 @@ > switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) { > case TargetLowering::Promote: > default: assert(0 && "This action is not supported yet!"); > - case TargetLowering::Expand: > - Result = Tmp1; // chain > + case TargetLowering::Expand: { > + DwarfWriter *DW = DAG.getDwarfWriter(); > + bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC, > + MVT::Other); > + bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other); > + > + const DbgStopPointSDNode *DSP = cast(Node); > + GlobalVariable *CU_GV = cast(DSP->getCompileUnit()); > + if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) { > + DICompileUnit CU(cast(DSP->getCompileUnit())); > + unsigned SrcFile = DW->RecordSource(CU.getDirectory(), > + CU.getFilename()); > + > + unsigned Line = DSP->getLine(); > + unsigned Col = DSP->getColumn(); > + > + // A bit self-referential to have DebugLoc on Debug_Loc nodes, but > + // it won't hurt anything. > + if (useDEBUG_LOC) { > + SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32), > + DAG.getConstant(Col, MVT::i32), > + DAG.getConstant(SrcFile, MVT::i32) }; > + Result = DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Ops, 4); > + } else { > + unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile); > + Result = DAG.getLabel(ISD::DBG_LABEL, dl, Tmp1, ID); > + } > + } else { > + Result = Tmp1; // chain > + } > break; > + } > case TargetLowering::Legal: { > LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); > if (Action == Legal && Tmp1 == Node->getOperand(0)) > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=64428&r1=64427&r2=64428&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Thu Feb 12 20:16:35 2009 > @@ -3912,18 +3912,24 @@ > case Intrinsic::dbg_region_start: { > DwarfWriter *DW = DAG.getDwarfWriter(); > DbgRegionStartInst &RSI = cast(I); > - > - if (DW && DW->ValidDebugInfo(RSI.getContext())) > - DW->RecordRegionStart(cast(RSI.getContext())); > + if (DW && DW->ValidDebugInfo(RSI.getContext())) { > + unsigned LabelID = > + DW->RecordRegionStart(cast(RSI.getContext())); > + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), > + getRoot(), LabelID)); > + } > > return 0; > } > case Intrinsic::dbg_region_end: { > DwarfWriter *DW = DAG.getDwarfWriter(); > DbgRegionEndInst &REI = cast(I); > - > - if (DW && DW->ValidDebugInfo(REI.getContext())) > - DW->RecordRegionEnd(cast(REI.getContext())); > + if (DW && DW->ValidDebugInfo(REI.getContext())) { > + unsigned LabelID = > + DW->RecordRegionEnd(cast(REI.getContext())); > + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), > + getRoot(), LabelID)); > + } > > return 0; > } > @@ -3944,15 +3950,27 @@ > // function start. It will be emitted at asm emission time. However, > // create a label if this is a beginning of inlined function. > unsigned Line = Subprogram.getLineNumber(); > + unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile); > + > + if (DW->getRecordSourceLineCount() != 1) > + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), > + getRoot(), LabelID)); > + > setCurDebugLoc(DebugLoc::get(DAG.getMachineFunction(). > - getOrCreateDebugLocID(SrcFile, Line, 0))); > + getOrCreateDebugLocID(SrcFile, Line, 0))); > } > > return 0; > } > - case Intrinsic::dbg_declare: > - // FIXME: Do something correct here when declare stuff is working again. > + case Intrinsic::dbg_declare: { > + DwarfWriter *DW = DAG.getDwarfWriter(); > + DbgDeclareInst &DI = cast(I); > + Value *Variable = DI.getVariable(); > + if (DW && DW->ValidDebugInfo(Variable)) > + DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(), > + getValue(DI.getAddress()), getValue(Variable))); > return 0; > + } > > case Intrinsic::eh_exception: { > if (!CurMBB->isLandingPad()) { > > Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=64428&r1=64427&r2=64428&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original) > +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Thu Feb 12 20:16:35 2009 > @@ -1278,7 +1278,7 @@ > } > > /// rewriteMBB - Keep track of which spills are available even after the > -/// register allocator is done with them. If possible, avoid reloading vregs. > +/// register allocator is done with them. If possible, avid reloading vregs. > void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM, > AvailableSpills &Spills) { > DOUT << "\n**** Local spiller rewriting MBB '" > > Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=64428&r1=64427&r2=64428&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Feb 12 20:16:35 2009 > @@ -785,6 +785,12 @@ > BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) > .addReg(FramePtr, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); > > + if (needsFrameMoves) { > + // Mark effective beginning of when frame pointer becomes valid. > + FrameLabelId = MMI->NextLabelID(); > + BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId); > + } > + > // Update EBP with the new base value... > BuildMI(MBB, MBBI, DL, > TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) > @@ -808,9 +814,11 @@ > NumBytes = StackSize - X86FI->getCalleeSavedFrameSize(); > > unsigned ReadyLabelId = 0; > - if (needsFrameMoves) > + if (needsFrameMoves) { > // Mark effective beginning of when frame pointer is ready. > ReadyLabelId = MMI->NextLabelID(); > + BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId); > + } > > // Skip the callee-saved push instructions. > while (MBBI != MBB.end() && > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From nicholas at mxc.ca Fri Feb 13 01:06:28 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Fri, 13 Feb 2009 07:06:28 -0000 Subject: [llvm-commits] [llvm] r64442 - in /llvm/trunk: lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/2009-02-12-GEPNoalias.ll Message-ID: <200902130706.n1D76S6v004736@zion.cs.uiuc.edu> Author: nicholas Date: Fri Feb 13 01:06:27 2009 New Revision: 64442 URL: http://llvm.org/viewvc/llvm-project?rev=64442&view=rev Log: BasicAA was making the assumption that a local allocation which hadn't escaped couldn't ever be the return of call instruction. However, it's quite possible that said local allocation is itself the return of a function call. That's what malloc and calloc are for, actually. Added: llvm/trunk/test/Analysis/BasicAA/2009-02-12-GEPNoalias.ll Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=64442&r1=64441&r2=64442&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Fri Feb 13 01:06:27 2009 @@ -319,7 +319,7 @@ // If the pointer is to a locally allocated object that does not escape, // then the call can not mod/ref the pointer unless the call takes the // argument without capturing it. - if (isNonEscapingLocalObject(Object)) { + if (isNonEscapingLocalObject(Object) && CS.getInstruction() != Object) { bool passedAsArg = false; // TODO: Eventually only check 'nocapture' arguments. for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end(); @@ -414,10 +414,10 @@ // non-escaping local object, then we know the object couldn't escape to a // point where the call could return it. if ((isa(O1) || isa(O1)) && - isNonEscapingLocalObject(O2)) + isNonEscapingLocalObject(O2) && O1 != O2) return NoAlias; if ((isa(O2) || isa(O2)) && - isNonEscapingLocalObject(O1)) + isNonEscapingLocalObject(O1) && O1 != O2) return NoAlias; // If we have two gep instructions with must-alias'ing base pointers, figure Added: llvm/trunk/test/Analysis/BasicAA/2009-02-12-GEPNoalias.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/2009-02-12-GEPNoalias.ll?rev=64442&view=auto ============================================================================== --- llvm/trunk/test/Analysis/BasicAA/2009-02-12-GEPNoalias.ll (added) +++ llvm/trunk/test/Analysis/BasicAA/2009-02-12-GEPNoalias.ll Fri Feb 13 01:06:27 2009 @@ -0,0 +1,196 @@ +; RUN: llvm-as < %s | opt -gvn -debug |& grep {REMOVING NONLOCAL LOAD} | count 1 + +; The bug this is testing for is that BasicAA considered: +; alias(%a = noalias call, %b = gep(%a, %unknown)) +; to be NoAlias instead of MayAlias. + + at .str = external constant [3 x i8] ; <[3 x i8]*> [#uses=1] + at .str1 = external constant [23 x i8] ; <[23 x i8]*> [#uses=1] + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind { +entry: + %0 = tail call i8* @calloc(i32 11, i32 4) nounwind ; [#uses=1] + %1 = bitcast i8* %0 to i32* ; [#uses=7] + %2 = tail call i8* @calloc(i32 11, i32 4) nounwind ; [#uses=2] + %3 = bitcast i8* %2 to i32* ; [#uses=9] + %4 = tail call i8* @calloc(i32 11, i32 4) nounwind ; [#uses=1] + %5 = bitcast i8* %4 to i32* ; [#uses=3] + br label %bb3.i + +bb3.i: ; preds = %bb3.i, %entry + %i.0.reg2mem.0.i = phi i32 [ 0, %entry ], [ %7, %bb3.i ] ; [#uses=3] + %6 = getelementptr i32* %3, i32 %i.0.reg2mem.0.i ; [#uses=1] + store i32 %i.0.reg2mem.0.i, i32* %6, align 4 + %7 = add i32 %i.0.reg2mem.0.i, 1 ; [#uses=2] + %8 = icmp slt i32 %7, 11 ; [#uses=1] + br i1 %8, label %bb3.i, label %bb8.i.loopexit + +bb5.i: ; preds = %bb29.i + %9 = icmp sgt i32 %didpr.1.reg2mem.0.ph.i.ph, 29 ; [#uses=1] + br i1 %9, label %bb11.i.outer, label %bb8.loopexit21.i + +bb8.loopexit21.i: ; preds = %bb5.i + %phitmp = add i32 %didpr.1.reg2mem.0.ph.i.ph, 1 ; [#uses=1] + br label %bb8.i.outer + +bb8.i.loopexit: ; preds = %bb3.i + br label %bb8.i.outer + +bb8.i.outer: ; preds = %bb8.i.loopexit, %bb8.loopexit21.i + %didpr.1.reg2mem.0.ph.i.ph = phi i32 [ %phitmp, %bb8.loopexit21.i ], [ 1, %bb8.i.loopexit ] ; [#uses=2] + %r.1.reg2mem.0.ph.i.ph = phi i32 [ %r.2.i, %bb8.loopexit21.i ], [ 11, %bb8.i.loopexit ] ; [#uses=1] + %flipsMax.1.reg2mem.0.ph.i.ph = phi i32 [ %flipsMax.0.ph.i.ph, %bb8.loopexit21.i ], [ 0, %bb8.i.loopexit ] ; [#uses=1] + br label %bb8.i + +bb8.i: ; preds = %bb8.i, %bb8.i.outer + %i.1.reg2mem.0.i = phi i32 [ %14, %bb8.i ], [ 0, %bb8.i.outer ] ; [#uses=2] + %10 = getelementptr i32* %3, i32 %i.1.reg2mem.0.i ; [#uses=1] + %11 = load i32* %10, align 4 ; [#uses=1] + %12 = add i32 %11, 1 ; [#uses=1] + %13 = tail call i32 (i8*, ...)* @printf(i8* noalias getelementptr ([3 x i8]* @.str, i32 0, i32 0), i32 %12) nounwind ; [#uses=0] + %14 = add i32 %i.1.reg2mem.0.i, 1 ; [#uses=2] + %15 = icmp slt i32 %14, 11 ; [#uses=1] + br i1 %15, label %bb8.i, label %bb9.i + +bb9.i: ; preds = %bb8.i + %16 = tail call i32 @putchar(i32 10) nounwind ; [#uses=0] + br label %bb11.i.outer + +bb11.i.outer: ; preds = %bb9.i, %bb5.i + %flipsMax.1.reg2mem.1.ph.i.ph = phi i32 [ %flipsMax.1.reg2mem.0.ph.i.ph, %bb9.i ], [ %flipsMax.0.ph.i.ph, %bb5.i ] ; [#uses=4] + %r.0.i.ph = phi i32 [ %r.1.reg2mem.0.ph.i.ph, %bb9.i ], [ %r.2.i, %bb5.i ] ; [#uses=1] + br label %bb11.i + +bb10.i: ; preds = %bb11.i + %17 = add i32 %r.0.i, -1 ; [#uses=1] + %18 = getelementptr i32* %5, i32 %17 ; [#uses=1] + store i32 %r.0.i, i32* %18, align 4 + %19 = add i32 %r.0.i, -1 ; [#uses=1] + br label %bb11.i + +bb11.i: ; preds = %bb10.i, %bb11.i.outer + %r.0.i = phi i32 [ %19, %bb10.i ], [ %r.0.i.ph, %bb11.i.outer ] ; [#uses=5] + %20 = icmp eq i32 %r.0.i, 1 ; [#uses=1] + br i1 %20, label %bb12.i, label %bb10.i + +bb12.i: ; preds = %bb11.i + %21 = load i32* %3, align 4 ; [#uses=1] + %22 = icmp eq i32 %21, 0 ; [#uses=1] + br i1 %22, label %bb24.i.preheader, label %bb13.i + +bb13.i: ; preds = %bb12.i + %23 = getelementptr i8* %2, i32 40 ; [#uses=1] + %24 = bitcast i8* %23 to i32* ; [#uses=1] + %25 = load i32* %24, align 4 ; [#uses=1] + %26 = icmp eq i32 %25, 10 ; [#uses=1] + br i1 %26, label %bb24.i.preheader, label %bb16.i.preheader + +bb16.i.preheader: ; preds = %bb13.i + br label %bb16.i + +bb16.i: ; preds = %bb16.i, %bb16.i.preheader + %i.2.reg2mem.0.i = phi i32 [ %30, %bb16.i ], [ 1, %bb16.i.preheader ] ; [#uses=3] + %27 = getelementptr i32* %3, i32 %i.2.reg2mem.0.i ; [#uses=1] + %28 = load i32* %27, align 4 ; [#uses=1] + %29 = getelementptr i32* %1, i32 %i.2.reg2mem.0.i ; [#uses=1] + store i32 %28, i32* %29, align 4 + %30 = add i32 %i.2.reg2mem.0.i, 1 ; [#uses=2] + %31 = icmp slt i32 %30, 11 ; [#uses=1] + br i1 %31, label %bb16.i, label %bb17.i + +bb17.i: ; preds = %bb16.i + %32 = load i32* %3, align 4 ; [#uses=2] + br label %bb20.i.outer + +bb20.i.outer: ; preds = %bb21.i, %bb17.i + %k.0.ph.i.ph = phi i32 [ %32, %bb17.i ], [ %43, %bb21.i ] ; [#uses=3] + %flips.0.ph.i.ph = phi i32 [ 0, %bb17.i ], [ %41, %bb21.i ] ; [#uses=1] + %j.0.in.i.ph = phi i32 [ %32, %bb17.i ], [ %43, %bb21.i ] ; [#uses=1] + br label %bb20.i + +bb19.i: ; preds = %bb20.i + %33 = getelementptr i32* %1, i32 %i.3.i ; [#uses=1] + %34 = load i32* %33, align 4 ; [#uses=1] + %35 = getelementptr i32* %1, i32 %j.0.i ; [#uses=1] + %36 = load i32* %35, align 4 ; [#uses=1] + %37 = getelementptr i32* %1, i32 %i.3.i ; [#uses=1] + store i32 %36, i32* %37, align 4 + %38 = getelementptr i32* %1, i32 %j.0.i ; [#uses=1] + store i32 %34, i32* %38, align 4 + %39 = add i32 %i.3.i, 1 ; [#uses=1] + br label %bb20.i + +bb20.i: ; preds = %bb19.i, %bb20.i.outer + %i.3.i = phi i32 [ %39, %bb19.i ], [ 1, %bb20.i.outer ] ; [#uses=4] + %j.0.in.i = phi i32 [ %j.0.i, %bb19.i ], [ %j.0.in.i.ph, %bb20.i.outer ] ; [#uses=1] + %j.0.i = add i32 %j.0.in.i, -1 ; [#uses=4] + %40 = icmp slt i32 %i.3.i, %j.0.i ; [#uses=1] + br i1 %40, label %bb19.i, label %bb21.i + +bb21.i: ; preds = %bb20.i + %41 = add i32 %flips.0.ph.i.ph, 1 ; [#uses=3] + %42 = getelementptr i32* %1, i32 %k.0.ph.i.ph ; [#uses=1] + %43 = load i32* %42, align 4 ; [#uses=3] + %44 = getelementptr i32* %1, i32 %k.0.ph.i.ph ; [#uses=1] + store i32 %k.0.ph.i.ph, i32* %44, align 4 + %45 = icmp eq i32 %43, 0 ; [#uses=1] + br i1 %45, label %bb22.i, label %bb20.i.outer + +bb22.i: ; preds = %bb21.i + %46 = icmp slt i32 %flipsMax.1.reg2mem.1.ph.i.ph, %41 ; [#uses=1] + br i1 %46, label %bb23.i, label %bb24.i.preheader + +bb23.i: ; preds = %bb22.i + br label %bb24.i.preheader + +bb24.i.preheader: ; preds = %bb23.i, %bb22.i, %bb13.i, %bb12.i + %flipsMax.0.ph.i.ph = phi i32 [ %flipsMax.1.reg2mem.1.ph.i.ph, %bb22.i ], [ %flipsMax.1.reg2mem.1.ph.i.ph, %bb13.i ], [ %flipsMax.1.reg2mem.1.ph.i.ph, %bb12.i ], [ %41, %bb23.i ] ; [#uses=3] + br label %bb24.i + +bb24.i: ; preds = %bb30.i, %bb24.i.preheader + %r.2.i = phi i32 [ %60, %bb30.i ], [ %r.0.i, %bb24.i.preheader ] ; [#uses=8] + %47 = icmp eq i32 %r.2.i, 11 ; [#uses=1] + br i1 %47, label %fannkuch.exit, label %bb26.i + +bb26.i: ; preds = %bb24.i + %48 = load i32* %3, align 4 ; [#uses=1] + br label %bb28.i + +bb27.i: ; preds = %bb28.i + %49 = add i32 %i.4.i, 1 ; [#uses=2] + %50 = getelementptr i32* %3, i32 %49 ; [#uses=1] + %51 = load i32* %50, align 4 ; [#uses=1] + %52 = getelementptr i32* %3, i32 %i.4.i ; [#uses=1] + store i32 %51, i32* %52, align 4 + br label %bb28.i + +bb28.i: ; preds = %bb27.i, %bb26.i + %i.4.i = phi i32 [ 0, %bb26.i ], [ %49, %bb27.i ] ; [#uses=3] + %53 = icmp slt i32 %i.4.i, %r.2.i ; [#uses=1] + br i1 %53, label %bb27.i, label %bb29.i + +bb29.i: ; preds = %bb28.i + %54 = getelementptr i32* %3, i32 %r.2.i ; [#uses=1] + store i32 %48, i32* %54, align 4 + %55 = getelementptr i32* %5, i32 %r.2.i ; [#uses=1] + %56 = load i32* %55, align 4 ; [#uses=1] + %57 = add i32 %56, -1 ; [#uses=2] + %58 = getelementptr i32* %5, i32 %r.2.i ; [#uses=1] + store i32 %57, i32* %58, align 4 + %59 = icmp sgt i32 %57, 0 ; [#uses=1] + br i1 %59, label %bb5.i, label %bb30.i + +bb30.i: ; preds = %bb29.i + %60 = add i32 %r.2.i, 1 ; [#uses=1] + br label %bb24.i + +fannkuch.exit: ; preds = %bb24.i + %61 = tail call i32 (i8*, ...)* @printf(i8* noalias getelementptr ([23 x i8]* @.str1, i32 0, i32 0), i32 11, i32 %flipsMax.0.ph.i.ph) nounwind ; [#uses=0] + ret i32 0 +} + +declare noalias i8* @calloc(i32, i32) nounwind + +declare i32 @printf(i8* nocapture, ...) nounwind + +declare i32 @putchar(i32) nounwind From nicholas at mxc.ca Fri Feb 13 01:15:53 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Fri, 13 Feb 2009 07:15:53 -0000 Subject: [llvm-commits] [llvm] r64443 - in /llvm/trunk: lib/Analysis/IPA/CallGraphSCCPass.cpp test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll Message-ID: <200902130715.n1D7FrsU005048@zion.cs.uiuc.edu> Author: nicholas Date: Fri Feb 13 01:15:53 2009 New Revision: 64443 URL: http://llvm.org/viewvc/llvm-project?rev=64443&view=rev Log: Reapply r64300: Make sure the SCC pass manager initializes any contained function pass managers. Without this, simplify-libcalls would add nocapture attributes when run on its own, but not when run as part of -std-compile-opts or similar. Modified: llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll Modified: llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp?rev=64443&r1=64442&r2=64443&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp (original) +++ llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp Fri Feb 13 01:15:53 2009 @@ -135,8 +135,13 @@ bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { Pass *P = getContainedPass(Index); - if (CallGraphSCCPass *CGSP = dynamic_cast(P)) + if (CallGraphSCCPass *CGSP = dynamic_cast(P)) { Changed |= CGSP->doInitialization(CG); + } else { + FPPassManager *FP = dynamic_cast(P); + assert (FP && "Invalid CGPassManager member"); + Changed |= FP->doInitialization(CG.getModule()); + } } return Changed; } @@ -146,8 +151,13 @@ bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { Pass *P = getContainedPass(Index); - if (CallGraphSCCPass *CGSP = dynamic_cast(P)) + if (CallGraphSCCPass *CGSP = dynamic_cast(P)) { Changed |= CGSP->doFinalization(CG); + } else { + FPPassManager *FP = dynamic_cast(P); + assert (FP && "Invalid CGPassManager member"); + Changed |= FP->doFinalization(CG.getModule()); + } } return Changed; } Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll?rev=64443&r1=64442&r2=64443&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll (original) +++ llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-11-NotInitialized.ll Fri Feb 13 01:15:53 2009 @@ -1,7 +1,7 @@ -; RUN: llvm-as < %s | opt -std-compile-opts | llvm-dis | grep nocapture | count 2 +; RUN: llvm-as < %s | opt -inline -simplify-libcalls -functionattrs | \ +; RUN: llvm-dis | grep nocapture | count 2 ; Check that nocapture attributes are added when run after an SCC pass. ; PR3520 -; XFAIL: * define i32 @use(i8* %x) nounwind readonly { entry: From evan.cheng at apple.com Fri Feb 13 01:54:34 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 13 Feb 2009 07:54:34 -0000 Subject: [llvm-commits] [llvm] r64444 - /llvm/trunk/lib/Support/MemoryBuffer.cpp Message-ID: <200902130754.n1D7sY0E006272@zion.cs.uiuc.edu> Author: evancheng Date: Fri Feb 13 01:54:34 2009 New Revision: 64444 URL: http://llvm.org/viewvc/llvm-project?rev=64444&view=rev Log: If new[] fails, return 0 rather then trying to dereference a null pointer. Modified: llvm/trunk/lib/Support/MemoryBuffer.cpp Modified: llvm/trunk/lib/Support/MemoryBuffer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/MemoryBuffer.cpp?rev=64444&r1=64443&r2=64444&view=diff ============================================================================== --- llvm/trunk/lib/Support/MemoryBuffer.cpp (original) +++ llvm/trunk/lib/Support/MemoryBuffer.cpp Fri Feb 13 01:54:34 2009 @@ -109,6 +109,7 @@ MemoryBuffer *MemoryBuffer::getNewUninitMemBuffer(size_t Size, const char *BufferName) { char *Buf = new char[Size+1]; + if (!Buf) return 0; Buf[Size] = 0; MemoryBufferMem *SB = new MemoryBufferMem(Buf, Buf+Size, BufferName); // The memory for this buffer is owned by the MemoryBuffer. @@ -123,6 +124,7 @@ MemoryBuffer *MemoryBuffer::getNewMemBuffer(size_t Size, const char *BufferName) { MemoryBuffer *SB = getNewUninitMemBuffer(Size, BufferName); + if (!SB) return 0; memset(const_cast(SB->getBufferStart()), 0, Size+1); return SB; } @@ -209,9 +211,16 @@ return new MemoryBufferMMapFile(Filename, Pages, FileSize); } } - - OwningPtr SB; - SB.reset(MemoryBuffer::getNewUninitMemBuffer(FileSize, Filename)); + + MemoryBuffer *Buf = MemoryBuffer::getNewUninitMemBuffer(FileSize, Filename); + if (!Buf) { + // Failed to create a buffer. + if (ErrStr) *ErrStr = "could not allocate buffer"; + ::close(FD); + return 0; + } + + OwningPtr SB(Buf); char *BufPtr = const_cast(SB->getBufferStart()); size_t BytesLeft = FileSize; From evan.cheng at apple.com Fri Feb 13 02:24:55 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 13 Feb 2009 08:24:55 -0000 Subject: [llvm-commits] [llvm] r64448 - /llvm/trunk/lib/Support/MemoryBuffer.cpp Message-ID: <200902130824.n1D8Otjg007319@zion.cs.uiuc.edu> Author: evancheng Date: Fri Feb 13 02:24:55 2009 New Revision: 64448 URL: http://llvm.org/viewvc/llvm-project?rev=64448&view=rev Log: Switch from new[] + delete[] to malloc + free since llvm does not catch C++ exceptions. Modified: llvm/trunk/lib/Support/MemoryBuffer.cpp Modified: llvm/trunk/lib/Support/MemoryBuffer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/MemoryBuffer.cpp?rev=64448&r1=64447&r2=64448&view=diff ============================================================================== --- llvm/trunk/lib/Support/MemoryBuffer.cpp (original) +++ llvm/trunk/lib/Support/MemoryBuffer.cpp Fri Feb 13 02:24:55 2009 @@ -38,7 +38,7 @@ MemoryBuffer::~MemoryBuffer() { if (MustDeleteBuffer) - delete [] BufferStart; + free((void*)BufferStart); } /// initCopyOf - Initialize this source buffer with a copy of the specified @@ -46,7 +46,7 @@ /// successfully. void MemoryBuffer::initCopyOf(const char *BufStart, const char *BufEnd) { size_t Size = BufEnd-BufStart; - BufferStart = new char[Size+1]; + BufferStart = (char *)malloc((Size+1) * sizeof(char)); BufferEnd = BufferStart+Size; memcpy(const_cast(BufferStart), BufStart, Size); *const_cast(BufferEnd) = 0; // Null terminate buffer. @@ -108,7 +108,7 @@ /// the MemoryBuffer object. MemoryBuffer *MemoryBuffer::getNewUninitMemBuffer(size_t Size, const char *BufferName) { - char *Buf = new char[Size+1]; + char *Buf = (char *)malloc((Size+1) * sizeof(char)); if (!Buf) return 0; Buf[Size] = 0; MemoryBufferMem *SB = new MemoryBufferMem(Buf, Buf+Size, BufferName); From baldrick at free.fr Fri Feb 13 03:40:13 2009 From: baldrick at free.fr (Duncan Sands) Date: Fri, 13 Feb 2009 10:40:13 +0100 Subject: [llvm-commits] [llvm] r64407 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h lib/Analysis/ScalarEvolution.cpp lib/Transforms/Scalar/IndVarSimplify.cpp test/Transforms/IndVarsSimplify/promote-iv-to-eliminate-casts.ll In-Reply-To: <200902122219.n1CMJR3v018926@zion.cs.uiuc.edu> References: <200902122219.n1CMJR3v018926@zion.cs.uiuc.edu> Message-ID: <200902131040.14139.baldrick@free.fr> Hi Dan, > Teach IndVarSimplify to optimize code using the C "int" type for > loop induction on LP64 targets. When the induction variable is > used in addressing, IndVars now is usually able to inserst a > 64-bit induction variable and eliminates the sign-extending cast. > This is also useful for code using C "short" types for > induction variables on targets with 32-bit addressing. does this fix PR1301? Ciao, Duncan. From baldrick at free.fr Fri Feb 13 03:42:43 2009 From: baldrick at free.fr (Duncan Sands) Date: Fri, 13 Feb 2009 09:42:43 -0000 Subject: [llvm-commits] [llvm] r64449 - /llvm/trunk/lib/VMCore/PassManager.cpp Message-ID: <200902130942.n1D9ghND020001@zion.cs.uiuc.edu> Author: baldrick Date: Fri Feb 13 03:42:34 2009 New Revision: 64449 URL: http://llvm.org/viewvc/llvm-project?rev=64449&view=rev Log: Reapply r64301. These uses of "inline" can cause strange link-time failures when building with optimization. Just get rid of them. Modified: llvm/trunk/lib/VMCore/PassManager.cpp Modified: llvm/trunk/lib/VMCore/PassManager.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=64449&r1=64448&r2=64449&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassManager.cpp (original) +++ llvm/trunk/lib/VMCore/PassManager.cpp Fri Feb 13 03:42:34 2009 @@ -1140,7 +1140,7 @@ } // Implement doInitialization and doFinalization -inline bool BBPassManager::doInitialization(Module &M) { +bool BBPassManager::doInitialization(Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { @@ -1151,7 +1151,7 @@ return Changed; } -inline bool BBPassManager::doFinalization(Module &M) { +bool BBPassManager::doFinalization(Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { @@ -1162,7 +1162,7 @@ return Changed; } -inline bool BBPassManager::doInitialization(Function &F) { +bool BBPassManager::doInitialization(Function &F) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { @@ -1173,7 +1173,7 @@ return Changed; } -inline bool BBPassManager::doFinalization(Function &F) { +bool BBPassManager::doFinalization(Function &F) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { @@ -1242,7 +1242,7 @@ //===----------------------------------------------------------------------===// // FunctionPassManagerImpl implementation // -inline bool FunctionPassManagerImpl::doInitialization(Module &M) { +bool FunctionPassManagerImpl::doInitialization(Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedManagers(); ++Index) { @@ -1253,7 +1253,7 @@ return Changed; } -inline bool FunctionPassManagerImpl::doFinalization(Module &M) { +bool FunctionPassManagerImpl::doFinalization(Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedManagers(); ++Index) { @@ -1348,7 +1348,7 @@ return Changed |= doFinalization(M); } -inline bool FPPassManager::doInitialization(Module &M) { +bool FPPassManager::doInitialization(Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { @@ -1359,7 +1359,7 @@ return Changed; } -inline bool FPPassManager::doFinalization(Module &M) { +bool FPPassManager::doFinalization(Module &M) { bool Changed = false; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { From mrs at apple.com Fri Feb 13 08:28:18 2009 From: mrs at apple.com (Mike Stump) Date: Fri, 13 Feb 2009 06:28:18 -0800 Subject: [llvm-commits] [llvm] r64444 - /llvm/trunk/lib/Support/MemoryBuffer.cpp In-Reply-To: <200902130754.n1D7sY0E006272@zion.cs.uiuc.edu> References: <200902130754.n1D7sY0E006272@zion.cs.uiuc.edu> Message-ID: <75AE82E2-2D91-4449-9D7F-05BE5602A6D4@apple.com> On Feb 12, 2009, at 11:54 PM, Evan Cheng wrote: > If new[] fails, return 0 rather then trying to dereference a null > pointer. new [] never fails?! Use nothrow, if you want it to fail. From mrs at apple.com Fri Feb 13 08:31:08 2009 From: mrs at apple.com (Mike Stump) Date: Fri, 13 Feb 2009 06:31:08 -0800 Subject: [llvm-commits] [llvm] r64448 - /llvm/trunk/lib/Support/MemoryBuffer.cpp In-Reply-To: <200902130824.n1D8Otjg007319@zion.cs.uiuc.edu> References: <200902130824.n1D8Otjg007319@zion.cs.uiuc.edu> Message-ID: <6C55538A-DF6F-44FA-853B-BFFFCE34E638@apple.com> On Feb 13, 2009, at 12:24 AM, Evan Cheng wrote: > Switch from new[] + delete[] to malloc + free since llvm does not > catch C++ exceptions. As an added bonus new nothrow never throws exceptions. From nicholas at mxc.ca Fri Feb 13 09:31:46 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Fri, 13 Feb 2009 15:31:46 -0000 Subject: [llvm-commits] [llvm] r64453 - in /llvm/trunk: lib/Transforms/Scalar/SimplifyLibCalls.cpp test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll Message-ID: <200902131531.n1DFVkdF032511@zion.cs.uiuc.edu> Author: nicholas Date: Fri Feb 13 09:31:46 2009 New Revision: 64453 URL: http://llvm.org/viewvc/llvm-project?rev=64453&view=rev Log: On strtod and friends, mark 'endptr' nocapture in the function prototype, and mark the first argument nocapture if endptr=NULL for each particular call. Added: llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=64453&r1=64452&r2=64453&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Fri Feb 13 09:31:46 2009 @@ -722,6 +722,26 @@ }; //===---------------------------------------===// +// 'strto*' Optimizations + +struct VISIBILITY_HIDDEN StrToOpt : public LibCallOptimization { + virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) { + const FunctionType *FT = Callee->getFunctionType(); + if ((FT->getNumParams() != 2 && FT->getNumParams() != 3) || + !isa(FT->getParamType(0)) || + !isa(FT->getParamType(1))) + return 0; + + Value *EndPtr = CI->getOperand(2); + if (isa(EndPtr)) + CI->addAttribute(1, Attribute::NoCapture); + + return 0; + } +}; + + +//===---------------------------------------===// // 'memcmp' Optimizations struct VISIBILITY_HIDDEN MemCmpOpt : public LibCallOptimization { @@ -1329,8 +1349,8 @@ ExitOpt Exit; // String and Memory LibCall Optimizations StrCatOpt StrCat; StrChrOpt StrChr; StrCmpOpt StrCmp; StrNCmpOpt StrNCmp; - StrCpyOpt StrCpy; StrLenOpt StrLen; MemCmpOpt MemCmp; MemCpyOpt MemCpy; - MemMoveOpt MemMove; MemSetOpt MemSet; + StrCpyOpt StrCpy; StrLenOpt StrLen; StrToOpt StrTo; MemCmpOpt MemCmp; + MemCpyOpt MemCpy; MemMoveOpt MemMove; MemSetOpt MemSet; // Math Library Optimizations PowOpt Pow; Exp2Opt Exp2; UnaryDoubleFPOpt UnaryDoubleFP; // Integer Optimizations @@ -1383,6 +1403,13 @@ Optimizations["strncmp"] = &StrNCmp; Optimizations["strcpy"] = &StrCpy; Optimizations["strlen"] = &StrLen; + Optimizations["strtol"] = &StrTo; + Optimizations["strtod"] = &StrTo; + Optimizations["strtof"] = &StrTo; + Optimizations["strtoul"] = &StrTo; + Optimizations["strtoll"] = &StrTo; + Optimizations["strtold"] = &StrTo; + Optimizations["strtoull"] = &StrTo; Optimizations["memcmp"] = &MemCmp; Optimizations["memcpy"] = &MemCpy; Optimizations["memmove"] = &MemMove; @@ -1566,8 +1593,15 @@ } else if ((NameLen == 6 && !strcmp(NameStr, "strcpy")) || (NameLen == 6 && !strcmp(NameStr, "stpcpy")) || (NameLen == 6 && !strcmp(NameStr, "strcat")) || + (NameLen == 6 && !strcmp(NameStr, "strtol")) || + (NameLen == 6 && !strcmp(NameStr, "strtod")) || + (NameLen == 6 && !strcmp(NameStr, "strtof")) || + (NameLen == 7 && !strcmp(NameStr, "strtoul")) || + (NameLen == 7 && !strcmp(NameStr, "strtoll")) || + (NameLen == 7 && !strcmp(NameStr, "strtold")) || (NameLen == 7 && !strcmp(NameStr, "strncat")) || - (NameLen == 7 && !strcmp(NameStr, "strncpy"))) { + (NameLen == 7 && !strcmp(NameStr, "strncpy")) || + (NameLen == 8 && !strcmp(NameStr, "strtoull"))) { if (FTy->getNumParams() < 2 || !isa(FTy->getParamType(1))) continue; Added: llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll?rev=64453&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll (added) +++ llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll Fri Feb 13 09:31:46 2009 @@ -0,0 +1,13 @@ +; RUN: llvm-as < %s | opt -simplify-libcalls | llvm-dis > %t +; RUN: grep nocapture %t | count 2 +; RUN: grep null %t | grep nocapture | count 1 + +; Test that we do add nocapture to the declaration, and to the second call only. + +declare float @strtof(i8* %s, i8** %endptr, i32 %base) + +define void @foo(i8* %x, i8** %endptr) { + call float @strtof(i8* %x, i8** %endptr, i32 0) + call float @strtof(i8* %x, i8** null, i32 0) + ret void +} From duncan.sands at math.u-psud.fr Fri Feb 13 09:43:37 2009 From: duncan.sands at math.u-psud.fr (Duncan Sands) Date: Fri, 13 Feb 2009 16:43:37 +0100 Subject: [llvm-commits] [llvm] r64453 - in /llvm/trunk: lib/Transforms/Scalar/SimplifyLibCalls.cpp test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll In-Reply-To: <200902131531.n1DFVkdF032511@zion.cs.uiuc.edu> References: <200902131531.n1DFVkdF032511@zion.cs.uiuc.edu> Message-ID: <200902131643.37616.duncan.sands@math.u-psud.fr> Hi Nick, > On strtod and friends, mark 'endptr' nocapture in the function prototype, and > mark the first argument nocapture if endptr=NULL for each particular call. if endptr==NULL then you can also mark the call "readonly". Ciao, Duncan. From nicholas at mxc.ca Fri Feb 13 11:08:33 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Fri, 13 Feb 2009 17:08:33 -0000 Subject: [llvm-commits] [llvm] r64460 - in /llvm/trunk: lib/Transforms/Scalar/SimplifyLibCalls.cpp test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll Message-ID: <200902131708.n1DH8YER003750@zion.cs.uiuc.edu> Author: nicholas Date: Fri Feb 13 11:08:33 2009 New Revision: 64460 URL: http://llvm.org/viewvc/llvm-project?rev=64460&view=rev Log: Mark strto* as readonly when the endptr is null. Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=64460&r1=64459&r2=64460&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Fri Feb 13 11:08:33 2009 @@ -733,8 +733,10 @@ return 0; Value *EndPtr = CI->getOperand(2); - if (isa(EndPtr)) + if (isa(EndPtr)) { + CI->setOnlyReadsMemory(); CI->addAttribute(1, Attribute::NoCapture); + } return 0; } Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll?rev=64460&r1=64459&r2=64460&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll (original) +++ llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll Fri Feb 13 11:08:33 2009 @@ -1,13 +1,14 @@ ; RUN: llvm-as < %s | opt -simplify-libcalls | llvm-dis > %t ; RUN: grep nocapture %t | count 2 ; RUN: grep null %t | grep nocapture | count 1 +; RUN: grep null %t | grep call | grep readonly | count 1 -; Test that we do add nocapture to the declaration, and to the second call only. +; Test that we add nocapture to the declaration, and to the second call only. -declare float @strtof(i8* %s, i8** %endptr, i32 %base) +declare float @strtol(i8* %s, i8** %endptr, i32 %base) define void @foo(i8* %x, i8** %endptr) { - call float @strtof(i8* %x, i8** %endptr, i32 0) - call float @strtof(i8* %x, i8** null, i32 0) + call float @strtol(i8* %x, i8** %endptr, i32 10) + call float @strtol(i8* %x, i8** null, i32 10) ret void } From nicholas at mxc.ca Fri Feb 13 11:09:02 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Fri, 13 Feb 2009 09:09:02 -0800 Subject: [llvm-commits] [llvm] r64453 - in /llvm/trunk: lib/Transforms/Scalar/SimplifyLibCalls.cpp test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll In-Reply-To: <200902131643.37616.duncan.sands@math.u-psud.fr> References: <200902131531.n1DFVkdF032511@zion.cs.uiuc.edu> <200902131643.37616.duncan.sands@math.u-psud.fr> Message-ID: <4995A92E.9030309@mxc.ca> Duncan Sands wrote: > Hi Nick, > >> On strtod and friends, mark 'endptr' nocapture in the function prototype, and >> mark the first argument nocapture if endptr=NULL for each particular call. > > if endptr==NULL then you can also mark the call "readonly". Great catch! Added in r64460. Nick From baldrick at free.fr Fri Feb 13 11:24:47 2009 From: baldrick at free.fr (Duncan Sands) Date: Fri, 13 Feb 2009 18:24:47 +0100 Subject: [llvm-commits] [llvm] r64460 - in /llvm/trunk: lib/Transforms/Scalar/SimplifyLibCalls.cpp test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll In-Reply-To: <200902131708.n1DH8YER003750@zion.cs.uiuc.edu> References: <200902131708.n1DH8YER003750@zion.cs.uiuc.edu> Message-ID: <200902131824.47463.baldrick@free.fr> Hi Nick, > Mark strto* as readonly when the endptr is null. Thanks! I guess it also never throws... Ciao, Duncan. From criswell at uiuc.edu Fri Feb 13 11:27:21 2009 From: criswell at uiuc.edu (John Criswell) Date: Fri, 13 Feb 2009 17:27:21 -0000 Subject: [llvm-commits] [poolalloc] r64462 - in /poolalloc/trunk: include/dsa/DataStructure.h lib/DSA/DataStructure.cpp Message-ID: <200902131727.n1DHRLdR004595@zion.cs.uiuc.edu> Author: criswell Date: Fri Feb 13 11:27:20 2009 New Revision: 64462 URL: http://llvm.org/viewvc/llvm-project?rev=64462&view=rev Log: Do not free the DSGraph if it has been stolen by another DSA pass. Modified: poolalloc/trunk/include/dsa/DataStructure.h poolalloc/trunk/lib/DSA/DataStructure.cpp Modified: poolalloc/trunk/include/dsa/DataStructure.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DataStructure.h?rev=64462&r1=64461&r2=64462&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/DataStructure.h (original) +++ poolalloc/trunk/include/dsa/DataStructure.h Fri Feb 13 11:27:20 2009 @@ -55,6 +55,9 @@ /// do we reset the aux list to the func list? bool resetAuxCalls; + /// Were are DSGraphs stolen by another pass? + bool DSGraphsStolen; + void buildGlobalECs(std::set& ECGlobals); void eliminateUsesOfECGlobals(DSGraph& G, const std::set &ECGlobals); @@ -89,9 +92,12 @@ } DataStructures(intptr_t id, const char* name) - :ModulePass(id), TD(0), GraphSource(0), printname(name), GlobalsGraph(0) { + : ModulePass(id), TD(0), GraphSource(0), printname(name), GlobalsGraph(0) { //a dummy node for empty call sites ActualCallees[0]; + + // For now, the graphs are owned by this pass + DSGraphsStolen = false; } public: Modified: poolalloc/trunk/lib/DSA/DataStructure.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructure.cpp?rev=64462&r1=64461&r2=64462&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DataStructure.cpp (original) +++ poolalloc/trunk/lib/DSA/DataStructure.cpp Fri Feb 13 11:27:20 2009 @@ -2870,6 +2870,11 @@ GlobalsGraph = new DSGraph(D->getGlobalsGraph(), GlobalECs, copyGlobalAuxCalls?0:DSGraph::DontCloneAuxCallNodes); if (printAuxCalls) GlobalsGraph->setPrintAuxCalls(); + + // + // Tell the other DSA pass if we're stealing its graph. + // + if (!clone) D->DSGraphsStolen = true; } void DataStructures::init(TargetData* T) { @@ -2881,6 +2886,11 @@ } void DataStructures::releaseMemory() { + // + // If the DSGraphs were stolen by another pass, free nothing. + // + if (DSGraphsStolen) return; + hash_set toDelete; for (DSInfoTy::iterator I = DSInfo.begin(), E = DSInfo.end(); I != E; ++I) { I->second->getReturnNodes().clear(); From baldrick at free.fr Fri Feb 13 11:32:26 2009 From: baldrick at free.fr (Duncan Sands) Date: Fri, 13 Feb 2009 17:32:26 -0000 Subject: [llvm-commits] [llvm] r64463 - /llvm/trunk/lib/Analysis/AliasAnalysis.cpp Message-ID: <200902131732.n1DHWQnd004785@zion.cs.uiuc.edu> Author: baldrick Date: Fri Feb 13 11:32:26 2009 New Revision: 64463 URL: http://llvm.org/viewvc/llvm-project?rev=64463&view=rev Log: If a function only reads memory, then we know that... it only reads memory! The other change has no functional effect, it just seems more logical to go in order of decreasing knowledge. Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=64463&r1=64462&r2=64463&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Fri Feb 13 11:32:26 2009 @@ -120,9 +120,13 @@ AliasAnalysis::ModRefBehavior AliasAnalysis::getModRefBehavior(Function *F, std::vector *Info) { - if (F && F->doesNotAccessMemory()) - // Can't do better than this. - return DoesNotAccessMemory; + if (F) { + if (F->doesNotAccessMemory()) + // Can't do better than this. + return DoesNotAccessMemory; + else if (F->onlyReadsMemory()) + return OnlyReadsMemory; + } return UnknownModRefBehavior; } @@ -130,10 +134,10 @@ AliasAnalysis::getModRefInfo(CallSite CS, Value *P, unsigned Size) { ModRefResult Mask = ModRef; ModRefBehavior MRB = getModRefBehavior(CS); - if (MRB == OnlyReadsMemory) - Mask = Ref; - else if (MRB == DoesNotAccessMemory) + if (MRB == DoesNotAccessMemory) return NoModRef; + else if (MRB == OnlyReadsMemory) + Mask = Ref; else if (MRB == AliasAnalysis::AccessesArguments) { bool doesAlias = false; for (CallSite::arg_iterator AI = CS.arg_begin(), AE = CS.arg_end(); @@ -142,7 +146,7 @@ doesAlias = true; break; } - + if (!doesAlias) return NoModRef; } From baldrick at free.fr Fri Feb 13 11:36:13 2009 From: baldrick at free.fr (Duncan Sands) Date: Fri, 13 Feb 2009 17:36:13 -0000 Subject: [llvm-commits] [llvm] r64464 - /llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Message-ID: <200902131736.n1DHaEKv004952@zion.cs.uiuc.edu> Author: baldrick Date: Fri Feb 13 11:36:13 2009 New Revision: 64464 URL: http://llvm.org/viewvc/llvm-project?rev=64464&view=rev Log: Correct a comment: since AccessArguments is now being used for atomic intrinsics, it seems the access may be volatile. No code was exploiting the original non-volatile definition, so only the comment needs changing. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=64464&r1=64463&r2=64464&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Fri Feb 13 11:36:13 2009 @@ -126,15 +126,15 @@ // This property corresponds to the GCC 'const' attribute. DoesNotAccessMemory, - // AccessesArguments - This function accesses function arguments in - // non-volatile and well known ways, but does not access any other memory. + // AccessesArguments - This function accesses function arguments in well + // known (possibly volatile) ways, but does not access any other memory. // // Clients may use the Info parameter of getModRefBehavior to get specific // information about how pointer arguments are used. AccessesArguments, // AccessesArgumentsAndGlobals - This function has accesses function - // arguments and global variables in non-volatile and well-known ways, but + // arguments and global variables well known (possibly volatile) ways, but // does not access any other memory. // // Clients may use the Info parameter of getModRefBehavior to get specific From gohman at apple.com Fri Feb 13 11:36:42 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 13 Feb 2009 17:36:42 -0000 Subject: [llvm-commits] [llvm] r64465 - /llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <200902131736.n1DHagaP004977@zion.cs.uiuc.edu> Author: djg Date: Fri Feb 13 11:36:42 2009 New Revision: 64465 URL: http://llvm.org/viewvc/llvm-project?rev=64465&view=rev Log: Complete the sentance in this comment. I have reservations about the code it describes, but at least now the comment is right. Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=64465&r1=64464&r2=64465&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Fri Feb 13 11:36:42 2009 @@ -1912,6 +1912,7 @@ UsersToProcess); // Avoid rewriting the compare instruction with an iv of new stride // if it's likely the new stride uses will be rewritten using the + // stride of the compare instruction. if (AllUsesAreAddresses && ValidStride(!CommonExprs->isZero(), Scale, UsersToProcess)) { NewCmpVal = CmpVal; From gohman at apple.com Fri Feb 13 11:45:13 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 13 Feb 2009 17:45:13 -0000 Subject: [llvm-commits] [llvm] r64468 - /llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Message-ID: <200902131745.n1DHjDdi005310@zion.cs.uiuc.edu> Author: djg Date: Fri Feb 13 11:45:12 2009 New Revision: 64468 URL: http://llvm.org/viewvc/llvm-project?rev=64468&view=rev Log: In CodeGenPrepare's debug output, use WriteAsOperand instead of printing getName(), so that unnamed values are printed correctly. Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=64468&r1=64467&r2=64468&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Fri Feb 13 11:45:12 2009 @@ -29,6 +29,7 @@ #include "llvm/Transforms/Utils/Local.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallSet.h" +#include "llvm/Assembly/Writer.h" #include "llvm/Support/CallSite.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Compiler.h" @@ -574,19 +575,28 @@ void ExtAddrMode::print(OStream &OS) const { bool NeedPlus = false; OS << "["; - if (BaseGV) + if (BaseGV) { OS << (NeedPlus ? " + " : "") - << "GV:%" << BaseGV->getName(), NeedPlus = true; + << "GV:"; + WriteAsOperand(*OS.stream(), BaseGV, /*PrintType=*/false); + NeedPlus = true; + } if (BaseOffs) OS << (NeedPlus ? " + " : "") << BaseOffs, NeedPlus = true; - if (BaseReg) + if (BaseReg) { OS << (NeedPlus ? " + " : "") - << "Base:%" << BaseReg->getName(), NeedPlus = true; - if (Scale) + << "Base:"; + WriteAsOperand(*OS.stream(), BaseReg, /*PrintType=*/false); + NeedPlus = true; + } + if (Scale) { OS << (NeedPlus ? " + " : "") - << Scale << "*%" << ScaledReg->getName(), NeedPlus = true; + << Scale << "*"; + WriteAsOperand(*OS.stream(), ScaledReg, /*PrintType=*/false); + NeedPlus = true; + } OS << ']'; } From kremenek at apple.com Fri Feb 13 13:55:24 2009 From: kremenek at apple.com (Ted Kremenek) Date: Fri, 13 Feb 2009 19:55:24 -0000 Subject: [llvm-commits] [llvm] r64483 - /llvm/tags/checker/checker-0.156/ Message-ID: <200902131955.n1DJtOGm010252@zion.cs.uiuc.edu> Author: kremenek Date: Fri Feb 13 13:55:23 2009 New Revision: 64483 URL: http://llvm.org/viewvc/llvm-project?rev=64483&view=rev Log: Tagging checker-0.156. Added: llvm/tags/checker/checker-0.156/ - copied from r64482, llvm/trunk/ From evan.cheng at apple.com Fri Feb 13 16:36:39 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 13 Feb 2009 22:36:39 -0000 Subject: [llvm-commits] [llvm] r64496 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/soft-fp.ll Message-ID: <200902132236.n1DMadWb016804@zion.cs.uiuc.edu> Author: evancheng Date: Fri Feb 13 16:36:38 2009 New Revision: 64496 URL: http://llvm.org/viewvc/llvm-project?rev=64496&view=rev Log: Teach x86 target -soft-float. Added: llvm/trunk/test/CodeGen/X86/soft-fp.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=64496&r1=64495&r2=64496&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Feb 13 16:36:38 2009 @@ -375,7 +375,7 @@ else setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); - if (X86ScalarSSEf64) { + if (!UseSoftFloat && X86ScalarSSEf64) { // f32 and f64 use SSE. // Set up the FP register classes. addRegisterClass(MVT::f32, X86::FR32RegisterClass); @@ -413,7 +413,7 @@ setConvertAction(MVT::f80, MVT::f32, Expand); setConvertAction(MVT::f80, MVT::f64, Expand); } - } else if (X86ScalarSSEf32) { + } else if (!UseSoftFloat && X86ScalarSSEf32) { // Use SSE for f32, x87 for f64. // Set up the FP register classes. addRegisterClass(MVT::f32, X86::FR32RegisterClass); @@ -458,7 +458,7 @@ setOperationAction(ISD::FSIN , MVT::f64 , Expand); setOperationAction(ISD::FCOS , MVT::f64 , Expand); } - } else { + } else if (!UseSoftFloat) { // f32 and f64 in x87. // Set up the FP register classes. addRegisterClass(MVT::f64, X86::RFP64RegisterClass); @@ -493,28 +493,30 @@ } // Long double always uses X87. - addRegisterClass(MVT::f80, X86::RFP80RegisterClass); - setOperationAction(ISD::UNDEF, MVT::f80, Expand); - setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); - { - bool ignored; - APFloat TmpFlt(+0.0); - TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, - &ignored); - addLegalFPImmediate(TmpFlt); // FLD0 - TmpFlt.changeSign(); - addLegalFPImmediate(TmpFlt); // FLD0/FCHS - APFloat TmpFlt2(+1.0); - TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, - &ignored); - addLegalFPImmediate(TmpFlt2); // FLD1 - TmpFlt2.changeSign(); - addLegalFPImmediate(TmpFlt2); // FLD1/FCHS - } + if (!UseSoftFloat) { + addRegisterClass(MVT::f80, X86::RFP80RegisterClass); + setOperationAction(ISD::UNDEF, MVT::f80, Expand); + setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); + { + bool ignored; + APFloat TmpFlt(+0.0); + TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, + &ignored); + addLegalFPImmediate(TmpFlt); // FLD0 + TmpFlt.changeSign(); + addLegalFPImmediate(TmpFlt); // FLD0/FCHS + APFloat TmpFlt2(+1.0); + TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, + &ignored); + addLegalFPImmediate(TmpFlt2); // FLD1 + TmpFlt2.changeSign(); + addLegalFPImmediate(TmpFlt2); // FLD1/FCHS + } - if (!UnsafeFPMath) { - setOperationAction(ISD::FSIN , MVT::f80 , Expand); - setOperationAction(ISD::FCOS , MVT::f80 , Expand); + if (!UnsafeFPMath) { + setOperationAction(ISD::FSIN , MVT::f80 , Expand); + setOperationAction(ISD::FCOS , MVT::f80 , Expand); + } } // Always use a library call for pow. @@ -578,7 +580,9 @@ setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); } - if (!DisableMMX && Subtarget->hasMMX()) { + // FIXME: In order to prevent SSE instructions being expanded to MMX ones + // with -msoft-float, disable use of MMX as well. + if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) { addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); @@ -660,7 +664,7 @@ setOperationAction(ISD::SELECT, MVT::v1i64, Custom); } - if (Subtarget->hasSSE1()) { + if (!UseSoftFloat && Subtarget->hasSSE1()) { addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); setOperationAction(ISD::FADD, MVT::v4f32, Legal); @@ -677,8 +681,11 @@ setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); } - if (Subtarget->hasSSE2()) { + if (!UseSoftFloat && Subtarget->hasSSE2()) { addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); + + // FIXME: Unfortunately -soft-float means XMM registers cannot be used even + // for integer operations. addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); @@ -756,7 +763,7 @@ setOperationAction(ISD::SELECT, MVT::v2i64, Custom); } - + if (Subtarget->hasSSE41()) { // FIXME: Do we need to handle scalar-to-vector here? setOperationAction(ISD::MUL, MVT::v4i32, Legal); @@ -1399,9 +1406,11 @@ unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, TotalNumXMMRegs); - assert((Subtarget->hasSSE1() || !NumXMMRegs) && + assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && + "SSE register cannot be used when SSE is disabled!"); + assert(!(NumXMMRegs && UseSoftFloat) && "SSE register cannot be used when SSE is disabled!"); - if (!Subtarget->hasSSE1()) { + if (UseSoftFloat || !Subtarget->hasSSE1()) { // Kernel mode asks for SSE to be disabled, so don't push them // on the stack. TotalNumXMMRegs = 0; Added: llvm/trunk/test/CodeGen/X86/soft-fp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/soft-fp.ll?rev=64496&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/soft-fp.ll (added) +++ llvm/trunk/test/CodeGen/X86/soft-fp.ll Fri Feb 13 16:36:38 2009 @@ -0,0 +1,27 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -soft-float | not grep xmm +; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse2 -soft-float | not grep xmm + + %struct.__va_list_tag = type { i32, i32, i8*, i8* } + +define i32 @t1(i32 %a, ...) nounwind { +entry: + %va = alloca [1 x %struct.__va_list_tag], align 8 ; <[1 x %struct.__va_list_tag]*> [#uses=2] + %va12 = bitcast [1 x %struct.__va_list_tag]* %va to i8* ; [#uses=2] + call void @llvm.va_start(i8* %va12) + %va3 = getelementptr [1 x %struct.__va_list_tag]* %va, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + call void @bar(%struct.__va_list_tag* %va3) nounwind + call void @llvm.va_end(i8* %va12) + ret i32 undef +} + +declare void @llvm.va_start(i8*) nounwind + +declare void @bar(%struct.__va_list_tag*) + +declare void @llvm.va_end(i8*) nounwind + +define float @t2(float %a, float %b) nounwind readnone { +entry: + %0 = add float %a, %b ; [#uses=1] + ret float %0 +} From evan.cheng at apple.com Fri Feb 13 17:35:33 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 13 Feb 2009 23:35:33 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r64506 - in /llvm-gcc-4.2/trunk/gcc/config: arm/arm.h i386/i386.h rs6000/rs6000.h Message-ID: <200902132335.n1DNZXlO019348@zion.cs.uiuc.edu> Author: evancheng Date: Fri Feb 13 17:35:33 2009 New Revision: 64506 URL: http://llvm.org/viewvc/llvm-project?rev=64506&view=rev Log: Translate -msoft-float to -soft-float. Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.h llvm-gcc-4.2/trunk/gcc/config/i386/i386.h llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.h?rev=64506&r1=64505&r2=64506&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/arm.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.h Fri Feb 13 17:35:33 2009 @@ -2922,6 +2922,10 @@ #define LLVM_OVERRIDE_TARGET_ARCH() \ (TARGET_THUMB ? "thumb" : "") +#define LLVM_SET_MACHINE_OPTIONS(argvec) \ + if (TARGET_SOFT_FLAT) \ + argvec.push_back("-soft-float"); + /* Doing struct copy by partial-word loads and stores is not a good idea on ARM. */ #define TARGET_LLVM_MIN_BYTES_COPY_BY_MEMCPY 4 Modified: llvm-gcc-4.2/trunk/gcc/config/i386/i386.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/i386.h?rev=64506&r1=64505&r2=64506&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/i386.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/i386.h Fri Feb 13 17:35:33 2009 @@ -3892,6 +3892,10 @@ if (TARGET_3DNOW) F.AddFeature("3dnow"); \ if (TARGET_3DNOW_A) F.AddFeature("3dnowa"); \ } + +#define LLVM_SET_MACHINE_OPTIONS(argvec) \ + if (!TARGET_80387) \ + argvec.push_back("-soft-float"); /* LLVM ABI definition macros. */ Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h?rev=64506&r1=64505&r2=64506&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Fri Feb 13 17:35:33 2009 @@ -3463,6 +3463,10 @@ F.AddFeature("64bit", TARGET_POWERPC64); \ } +#define LLVM_SET_MACHINE_OPTIONS(argvec) \ + if (TARGET_SOFT_FLAT) \ + argvec.push_back("-soft-float"); + /* When -m64 is specified, set the architecture to powerpc64-os-blah even if the * compiler was configured for powerpc-os-blah. */ From tonic at nondot.org Fri Feb 13 17:52:54 2009 From: tonic at nondot.org (Tanya Lattner) Date: Fri, 13 Feb 2009 23:52:54 -0000 Subject: [llvm-commits] [llvm] r64508 - /llvm/branches/release_25/lib/CodeGen/PreAllocSplitting.cpp Message-ID: <200902132352.n1DNqsCa020043@zion.cs.uiuc.edu> Author: tbrethou Date: Fri Feb 13 17:52:54 2009 New Revision: 64508 URL: http://llvm.org/viewvc/llvm-project?rev=64508&view=rev Log: Merge from mainline. Pre-alloc splitting needs to be more careful to avoid inserting spills/restores between call frame setup/restore points. Unfortunately, this regresses code size a bit, but at least it's correct now! Modified: llvm/branches/release_25/lib/CodeGen/PreAllocSplitting.cpp Modified: llvm/branches/release_25/lib/CodeGen/PreAllocSplitting.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/CodeGen/PreAllocSplitting.cpp?rev=64508&r1=64507&r2=64508&view=diff ============================================================================== --- llvm/branches/release_25/lib/CodeGen/PreAllocSplitting.cpp (original) +++ llvm/branches/release_25/lib/CodeGen/PreAllocSplitting.cpp Fri Feb 13 17:52:54 2009 @@ -228,28 +228,52 @@ ++MII; unsigned Index = LIs->getInstructionIndex(MII); unsigned Gap = LIs->findGapBeforeInstr(Index); - if (Gap) { - Pt = MII; - SpillIndex = Gap; - break; // We can't insert the spill between the barrier (a call), and its - // corresponding call frame setup. - } else if (prior(MII)->getOpcode() == TRI->getCallFrameSetupOpcode() && - MII == MachineBasicBlock::iterator(MI)) + // corresponding call frame setup/teardown. + if (prior(MII)->getOpcode() == TRI->getCallFrameSetupOpcode()) { + bool reachedBarrier = false; + do { + if (MII == EndPt) { + reachedBarrier = true; + break; + } + ++MII; + } while (MII->getOpcode() != TRI->getCallFrameDestroyOpcode()); + + if (reachedBarrier) break; + } else if (Gap) { + Pt = MII; + SpillIndex = Gap; break; + } } while (MII != EndPt); } else { MachineBasicBlock::iterator MII = MI; MachineBasicBlock::iterator EndPt = DefMI ? MachineBasicBlock::iterator(DefMI) : MBB->begin(); - // We can't insert the spill between the barrier (a call), and its - // corresponding call frame setup. - if (prior(MII)->getOpcode() == TRI->getCallFrameSetupOpcode()) --MII; while (MII != EndPt && !RefsInMBB.count(MII)) { unsigned Index = LIs->getInstructionIndex(MII); - if (LIs->hasGapBeforeInstr(Index)) { + + // We can't insert the spill between the barrier (a call), and its + // corresponding call frame setup. + if (prior(MII)->getOpcode() == TRI->getCallFrameSetupOpcode()) { + --MII; + continue; + } if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode()) { + bool reachedBarrier = false; + while (MII->getOpcode() != TRI->getCallFrameSetupOpcode()) { + --MII; + if (MII == EndPt) { + reachedBarrier = true; + break; + } + } + + if (reachedBarrier) break; + else continue; + } else if (LIs->hasGapBeforeInstr(Index)) { Pt = MII; SpillIndex = LIs->findGapBeforeInstr(Index, true); } @@ -283,25 +307,32 @@ do { unsigned Index = LIs->getInstructionIndex(MII); unsigned Gap = LIs->findGapBeforeInstr(Index); - if (Gap) { - Pt = MII; - RestoreIndex = Gap; - break; // We can't insert a restore between the barrier (a call) and its // corresponding call frame teardown. - } else if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode() && - prior(MII) == MachineBasicBlock::iterator(MI)) + if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode()) { + bool reachedBarrier = false; + while (MII->getOpcode() != TRI->getCallFrameSetupOpcode()) { + --MII; + if (MII == EndPt) { + reachedBarrier = true; + break; + } + } + + if (reachedBarrier) break; + else continue; + } else if (Gap) { + Pt = MII; + RestoreIndex = Gap; break; + } + --MII; } while (MII != EndPt); } else { MachineBasicBlock::iterator MII = MI; MII = ++MII; - // We can't insert a restore between the barrier (a call) and its - // corresponding call frame teardown. - if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode()) - ++MII; // FIXME: Limit the number of instructions to examine to reduce // compile time? @@ -310,10 +341,29 @@ if (Index > LastIdx) break; unsigned Gap = LIs->findGapBeforeInstr(Index); - if (Gap) { + + // We can't insert a restore between the barrier (a call) and its + // corresponding call frame teardown. + if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode()) { + ++MII; + continue; + } else if (prior(MII)->getOpcode() == TRI->getCallFrameSetupOpcode()) { + bool reachedBarrier = false; + do { + if (MII == MBB->getFirstTerminator() || RefsInMBB.count(MII)) { + reachedBarrier = true; + break; + } + + ++MII; + } while (MII->getOpcode() != TRI->getCallFrameDestroyOpcode()); + + if (reachedBarrier) break; + } else if (Gap) { Pt = MII; RestoreIndex = Gap; } + if (RefsInMBB.count(MII)) break; ++MII; From tonic at nondot.org Fri Feb 13 17:53:41 2009 From: tonic at nondot.org (Tanya Lattner) Date: Fri, 13 Feb 2009 23:53:41 -0000 Subject: [llvm-commits] [llvm] r64509 - in /llvm/branches/release_25: include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/LiveIntervalAnalysis.cpp lib/CodeGen/SimpleRegisterCoalescing.cpp test/CodeGen/X86/2009-02-08-CoalescerBug.ll Message-ID: <200902132353.n1DNrfQv020092@zion.cs.uiuc.edu> Author: tbrethou Date: Fri Feb 13 17:53:40 2009 New Revision: 64509 URL: http://llvm.org/viewvc/llvm-project?rev=64509&view=rev Log: Merge from mainline. Fix PR3486. Fix a bug in code that manually patch physical register live interval after its sub-register is coalesced with a virtual register. Added: llvm/branches/release_25/test/CodeGen/X86/2009-02-08-CoalescerBug.ll - copied unchanged from r64082, llvm/trunk/test/CodeGen/X86/2009-02-08-CoalescerBug.ll Modified: llvm/branches/release_25/include/llvm/CodeGen/LiveIntervalAnalysis.h llvm/branches/release_25/lib/CodeGen/LiveIntervalAnalysis.cpp llvm/branches/release_25/lib/CodeGen/SimpleRegisterCoalescing.cpp Modified: llvm/branches/release_25/include/llvm/CodeGen/LiveIntervalAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=64509&r1=64508&r2=64509&view=diff ============================================================================== --- llvm/branches/release_25/include/llvm/CodeGen/LiveIntervalAnalysis.h (original) +++ llvm/branches/release_25/include/llvm/CodeGen/LiveIntervalAnalysis.h Fri Feb 13 17:53:40 2009 @@ -282,6 +282,10 @@ I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first; return *I->second; } + + /// dupInterval - Duplicate a live interval. The caller is responsible for + /// managing the allocated memory. + LiveInterval *dupInterval(LiveInterval *li); /// addLiveRangeToEndOfBlock - Given a register and an instruction, /// adds a live range from that instruction to the end of its MBB. Modified: llvm/branches/release_25/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=64509&r1=64508&r2=64509&view=diff ============================================================================== --- llvm/branches/release_25/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/branches/release_25/lib/CodeGen/LiveIntervalAnalysis.cpp Fri Feb 13 17:53:40 2009 @@ -824,11 +824,18 @@ } LiveInterval* LiveIntervals::createInterval(unsigned reg) { - float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? - HUGE_VALF : 0.0F; + float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F; return new LiveInterval(reg, Weight); } +/// dupInterval - Duplicate a live interval. The caller is responsible for +/// managing the allocated memory. +LiveInterval* LiveIntervals::dupInterval(LiveInterval *li) { + LiveInterval *NewLI = createInterval(li->reg); + NewLI->Copy(*li, getVNInfoAllocator()); + return NewLI; +} + /// getVNInfoSourceReg - Helper function that parses the specified VNInfo /// copy field and returns the source register that defines it. unsigned LiveIntervals::getVNInfoSourceReg(const VNInfo *VNI) const { Modified: llvm/branches/release_25/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=64509&r1=64508&r2=64509&view=diff ============================================================================== --- llvm/branches/release_25/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/branches/release_25/lib/CodeGen/SimpleRegisterCoalescing.cpp Fri Feb 13 17:53:40 2009 @@ -1322,6 +1322,15 @@ DOUT << " and "; DstInt.print(DOUT, tri_); DOUT << ": "; + // Save a copy of the virtual register live interval. We'll manually + // merge this into the "real" physical register live interval this is + // coalesced with. + LiveInterval *SavedLI = 0; + if (RealDstReg) + SavedLI = li_->dupInterval(&SrcInt); + else if (RealSrcReg) + SavedLI = li_->dupInterval(&DstInt); + // Check if it is necessary to propagate "isDead" property. if (!isExtSubReg && !isInsSubReg) { MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false); @@ -1413,21 +1422,17 @@ if (RealDstReg || RealSrcReg) { LiveInterval &RealInt = li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg); - SmallSet CopiedValNos; - for (LiveInterval::Ranges::const_iterator I = ResSrcInt->ranges.begin(), - E = ResSrcInt->ranges.end(); I != E; ++I) { - const LiveRange *DstLR = ResDstInt->getLiveRangeContaining(I->start); - assert(DstLR && "Invalid joined interval!"); - const VNInfo *DstValNo = DstLR->valno; - if (CopiedValNos.insert(DstValNo)) { - VNInfo *ValNo = RealInt.getNextValue(DstValNo->def, DstValNo->copy, - li_->getVNInfoAllocator()); - ValNo->hasPHIKill = DstValNo->hasPHIKill; - RealInt.addKills(ValNo, DstValNo->kills); - RealInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo); - } + for (LiveInterval::const_vni_iterator I = SavedLI->vni_begin(), + E = SavedLI->vni_end(); I != E; ++I) { + const VNInfo *ValNo = *I; + VNInfo *NewValNo = RealInt.getNextValue(ValNo->def, ValNo->copy, + li_->getVNInfoAllocator()); + NewValNo->hasPHIKill = ValNo->hasPHIKill; + NewValNo->redefByEC = ValNo->redefByEC; + RealInt.addKills(NewValNo, ValNo->kills); + RealInt.MergeValueInAsValue(*SavedLI, ValNo, NewValNo); } - + RealInt.weight += SavedLI->weight; DstReg = RealDstReg ? RealDstReg : RealSrcReg; } @@ -1497,6 +1502,12 @@ // being merged. li_->removeInterval(SrcReg); + // Manually deleted the live interval copy. + if (SavedLI) { + SavedLI->clear(); + delete SavedLI; + } + if (isEmpty) { // Now the copy is being coalesced away, the val# previously defined // by the copy is being defined by an IMPLICIT_DEF which defines a zero From dalej at apple.com Fri Feb 13 18:18:43 2009 From: dalej at apple.com (Dale Johannesen) Date: Sat, 14 Feb 2009 00:18:43 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r64510 - /llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Message-ID: <200902140018.n1E0Ih7Y021018@zion.cs.uiuc.edu> Author: johannes Date: Fri Feb 13 18:18:43 2009 New Revision: 64510 URL: http://llvm.org/viewvc/llvm-project?rev=64510&view=rev Log: Fix a bug handling zero-length fields in unions. Exposed by 64234, but it was always there if the zero-length field was the only one in the union. g{cc,++}.dg/compat/struct-layout-1.exp [several] Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=64510&r1=64509&r2=64510&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Fri Feb 13 18:18:43 2009 @@ -2239,6 +2239,13 @@ continue; tree TheGccTy = TREE_TYPE(Field); + + // Skip zero-length fields; ConvertType refuses to construct a type + // of size 0. + if (DECL_SIZE(Field) && + TREE_CODE(DECL_SIZE(Field))==INTEGER_CST && + TREE_INT_CST_LOW(DECL_SIZE(Field))==0) + continue; #ifdef TARGET_POWERPC // Normally gcc reduces the size of bitfields to the size necessary // to hold the bits, e.g. a 1-bit field becomes QI. It does not do From dalej at apple.com Fri Feb 13 18:19:28 2009 From: dalej at apple.com (Dale Johannesen) Date: Sat, 14 Feb 2009 00:19:28 -0000 Subject: [llvm-commits] [llvm] r64511 - /llvm/trunk/test/FrontendC/2009-02-13-zerosize-union-field.c Message-ID: <200902140019.n1E0JSK6021054@zion.cs.uiuc.edu> Author: johannes Date: Fri Feb 13 18:19:28 2009 New Revision: 64511 URL: http://llvm.org/viewvc/llvm-project?rev=64511&view=rev Log: Testcase for llvm-gcc 64510. Added: llvm/trunk/test/FrontendC/2009-02-13-zerosize-union-field.c Added: llvm/trunk/test/FrontendC/2009-02-13-zerosize-union-field.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2009-02-13-zerosize-union-field.c?rev=64511&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/2009-02-13-zerosize-union-field.c (added) +++ llvm/trunk/test/FrontendC/2009-02-13-zerosize-union-field.c Fri Feb 13 18:19:28 2009 @@ -0,0 +1,13 @@ +// RUN: %llvmgcc %s -m32 -S -o - | grep {i32 1} | count 1 +// RUN: %llvmgcc %s -m32 -S -o - | grep {i32 4} | count 2 +// Every printf has 'i32 0' for the GEP of the string; no point counting those. +typedef unsigned int Foo __attribute__((aligned(32))); +typedef union{Foo:0;}a; +typedef union{int x; Foo:0;}b; +extern int printf(const char*, ...); +main() { + printf("%ld\n", sizeof(a)); + printf("%ld\n", __alignof__(a)); + printf("%ld\n", sizeof(b)); + printf("%ld\n", __alignof__(b)); +} From clattner at apple.com Fri Feb 13 18:42:58 2009 From: clattner at apple.com (Chris Lattner) Date: Fri, 13 Feb 2009 16:42:58 -0800 Subject: [llvm-commits] [llvm] r64439 - /llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h In-Reply-To: <200902130235.n1D2ZLcp028503@zion.cs.uiuc.edu> References: <200902130235.n1D2ZLcp028503@zion.cs.uiuc.edu> Message-ID: <36224022-A9EB-48E3-9471-55AA7FF30F62@apple.com> On Feb 12, 2009, at 6:35 PM, Dale Johannesen wrote: > Author: johannes > Date: Thu Feb 12 20:35:20 2009 > New Revision: 64439 > > URL: http://llvm.org/viewvc/llvm-project?rev=64439&view=rev > Log: > Remove non-DebugLoc versions of BuildMI. > "I got blisters on my fingers." Woo, thanks a lot Dale! -Chris From tonic at nondot.org Fri Feb 13 18:43:29 2009 From: tonic at nondot.org (Tanya Lattner) Date: Sat, 14 Feb 2009 00:43:29 -0000 Subject: [llvm-commits] [llvm] r64514 - /llvm/branches/release_25/utils/unittest/googletest/Makefile Message-ID: <200902140043.n1E0hTPn021857@zion.cs.uiuc.edu> Author: tbrethou Date: Fri Feb 13 18:43:29 2009 New Revision: 64514 URL: http://llvm.org/viewvc/llvm-project?rev=64514&view=rev Log: Merge from mainline. Probe for flags before using them to try to help compiling with compilers that don't support those flags. This hopefully will help gcc 3.X compile this code. http://llvm.org/PR3487 Modified: llvm/branches/release_25/utils/unittest/googletest/Makefile Modified: llvm/branches/release_25/utils/unittest/googletest/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/utils/unittest/googletest/Makefile?rev=64514&r1=64513&r2=64514&view=diff ============================================================================== --- llvm/branches/release_25/utils/unittest/googletest/Makefile (original) +++ llvm/branches/release_25/utils/unittest/googletest/Makefile Fri Feb 13 18:43:29 2009 @@ -9,10 +9,13 @@ LEVEL := ../../.. include $(LEVEL)/Makefile.config +NO_MISSING_FIELD_INITIALIZERS := $(shell $(CXX) -Wno-missing-field-initializers -fsyntax-only -xc /dev/null 2>/dev/null && echo -Wno-missing-field-initializers) +NO_VAROADIC_MACROS := $(shell $(CXX) -Wno-variadic-macros -fsyntax-only -xc /dev/null 2>/dev/null && echo -Wno-variadic-macros) + LIBRARYNAME = GoogleTest BUILD_ARCHIVE = 1 CPP.Flags += -I$(LLVM_SRC_ROOT)/utils/unittest/googletest/include/ -CPP.Flags += -Wno-missing-field-initializers -Wno-variadic-macros +CPP.Flags += $(NO_MISSING_FIELD_INITIALIZERS) $(NO_VAROADIC_MACROS) include $(LEVEL)/Makefile.common From tonic at nondot.org Fri Feb 13 18:47:00 2009 From: tonic at nondot.org (Tanya Lattner) Date: Sat, 14 Feb 2009 00:47:00 -0000 Subject: [llvm-commits] [llvm] r64515 - /llvm/branches/release_25/utils/unittest/googletest/Makefile Message-ID: <200902140047.n1E0l0TC021974@zion.cs.uiuc.edu> Author: tbrethou Date: Fri Feb 13 18:47:00 2009 New Revision: 64515 URL: http://llvm.org/viewvc/llvm-project?rev=64515&view=rev Log: Merge from mainline. FIx spelling. Modified: llvm/branches/release_25/utils/unittest/googletest/Makefile Modified: llvm/branches/release_25/utils/unittest/googletest/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/utils/unittest/googletest/Makefile?rev=64515&r1=64514&r2=64515&view=diff ============================================================================== --- llvm/branches/release_25/utils/unittest/googletest/Makefile (original) +++ llvm/branches/release_25/utils/unittest/googletest/Makefile Fri Feb 13 18:47:00 2009 @@ -10,12 +10,12 @@ LEVEL := ../../.. include $(LEVEL)/Makefile.config NO_MISSING_FIELD_INITIALIZERS := $(shell $(CXX) -Wno-missing-field-initializers -fsyntax-only -xc /dev/null 2>/dev/null && echo -Wno-missing-field-initializers) -NO_VAROADIC_MACROS := $(shell $(CXX) -Wno-variadic-macros -fsyntax-only -xc /dev/null 2>/dev/null && echo -Wno-variadic-macros) +NO_VARIADIC_MACROS := $(shell $(CXX) -Wno-variadic-macros -fsyntax-only -xc /dev/null 2>/dev/null && echo -Wno-variadic-macros) LIBRARYNAME = GoogleTest BUILD_ARCHIVE = 1 CPP.Flags += -I$(LLVM_SRC_ROOT)/utils/unittest/googletest/include/ -CPP.Flags += $(NO_MISSING_FIELD_INITIALIZERS) $(NO_VAROADIC_MACROS) +CPP.Flags += $(NO_MISSING_FIELD_INITIALIZERS) $(NO_VARIADIC_MACROS) include $(LEVEL)/Makefile.common From tonic at nondot.org Fri Feb 13 18:50:29 2009 From: tonic at nondot.org (Tanya Lattner) Date: Sat, 14 Feb 2009 00:50:29 -0000 Subject: [llvm-commits] [llvm] r64516 - /llvm/branches/release_25/utils/Makefile Message-ID: <200902140050.n1E0oTvJ022099@zion.cs.uiuc.edu> Author: tbrethou Date: Fri Feb 13 18:50:29 2009 New Revision: 64516 URL: http://llvm.org/viewvc/llvm-project?rev=64516&view=rev Log: Revert disabling of building unittests. Modified: llvm/branches/release_25/utils/Makefile Modified: llvm/branches/release_25/utils/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/utils/Makefile?rev=64516&r1=64515&r2=64516&view=diff ============================================================================== --- llvm/branches/release_25/utils/Makefile (original) +++ llvm/branches/release_25/utils/Makefile Fri Feb 13 18:50:29 2009 @@ -8,7 +8,7 @@ ##===----------------------------------------------------------------------===## LEVEL = .. -PARALLEL_DIRS := TableGen fpcmp PerfectShuffle +PARALLEL_DIRS := TableGen fpcmp PerfectShuffle unittest EXTRA_DIST := cgiplotNLT.pl check-each-file codegen-diff countloc.sh cvsupdate \ DSAclean.py DSAextract.py emacs findsym.pl GenLibDeps.pl \ From tonic at nondot.org Fri Feb 13 18:57:30 2009 From: tonic at nondot.org (Tanya Lattner) Date: Sat, 14 Feb 2009 00:57:30 -0000 Subject: [llvm-commits] [llvm] r64517 - in /llvm/branches/release_25: lib/Transforms/Scalar/LoopStrengthReduce.cpp test/Transforms/LoopStrengthReduce/2009-02-09-ivs-different-sizes.ll Message-ID: <200902140057.n1E0vVZp022335@zion.cs.uiuc.edu> Author: tbrethou Date: Fri Feb 13 18:57:30 2009 New Revision: 64517 URL: http://llvm.org/viewvc/llvm-project?rev=64517&view=rev Log: Merge 64177 from mainline. Fix PR 3471, and some cleanups. Added: llvm/branches/release_25/test/Transforms/LoopStrengthReduce/2009-02-09-ivs-different-sizes.ll - copied unchanged from r64177, llvm/trunk/test/Transforms/LoopStrengthReduce/2009-02-09-ivs-different-sizes.ll Modified: llvm/branches/release_25/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/branches/release_25/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=64517&r1=64516&r2=64517&view=diff ============================================================================== --- llvm/branches/release_25/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/branches/release_25/lib/Transforms/Scalar/LoopStrengthReduce.cpp Fri Feb 13 18:57:30 2009 @@ -430,8 +430,8 @@ if (!AddRec->isAffine()) return false; // If Start contains an SCEVAddRecExpr from a different loop, other than an - // outer loop of the current loop, reject it. SCEV has no concept of operating - // on one loop at a time so don't confuse it with such expressions. + // outer loop of the current loop, reject it. SCEV has no concept of + // operating on one loop at a time so don't confuse it with such expressions. if (containsAddRecFromDifferentLoop(Start, L)) return false; @@ -774,14 +774,14 @@ // which need not be an immediate predecessor of this PHI. This way we // need only one copy of it even if it is referenced multiple times in // the PHI. We don't do this when the original expression is inside the - // loop because multiple copies sometimes do useful sinking of code in that - // case(?). + // loop because multiple copies sometimes do useful sinking of code in + // that case(?). Instruction *OldLoc = dyn_cast(OperandValToReplace); if (L->contains(OldLoc->getParent())) { - // If this is a critical edge, split the edge so that we do not insert the - // code on all predecessor/successor paths. We do this unless this is the - // canonical backedge for this loop, as this can make some inserted code - // be in an illegal position. + // If this is a critical edge, split the edge so that we do not insert + // the code on all predecessor/successor paths. We do this unless this + // is the canonical backedge for this loop, as this can make some + // inserted code be in an illegal position. BasicBlock *PHIPred = PN->getIncomingBlock(i); if (e != 1 && PHIPred->getTerminator()->getNumSuccessors() > 1 && (PN->getParent() != L->getHeader() || !L->contains(PHIPred))) { @@ -1224,19 +1224,21 @@ return true; } -/// RequiresTypeConversion - Returns true if converting Ty to NewTy is not +/// RequiresTypeConversion - Returns true if converting Ty1 to Ty2 is not /// a nop. bool LoopStrengthReduce::RequiresTypeConversion(const Type *Ty1, const Type *Ty2) { if (Ty1 == Ty2) return false; + if (Ty1->canLosslesslyBitCastTo(Ty2)) + return false; if (TLI && TLI->isTruncateFree(Ty1, Ty2)) return false; - return (!Ty1->canLosslesslyBitCastTo(Ty2) && - !(isa(Ty2) && - Ty1->canLosslesslyBitCastTo(UIntPtrTy)) && - !(isa(Ty1) && - Ty2->canLosslesslyBitCastTo(UIntPtrTy))); + if (isa(Ty2) && Ty1->canLosslesslyBitCastTo(UIntPtrTy)) + return false; + if (isa(Ty1) && Ty2->canLosslesslyBitCastTo(UIntPtrTy)) + return false; + return true; } /// CheckForIVReuse - Returns the multiple if the stride is the multiple @@ -1661,15 +1663,28 @@ Rewriter.clear(); // If we are reusing the iv, then it must be multiplied by a constant - // factor take advantage of addressing mode scale component. + // factor to take advantage of the addressing mode scale component. if (!isa(RewriteFactor) || !cast(RewriteFactor)->isZero()) { // If we're reusing an IV with a nonzero base (currently this happens // only when all reuses are outside the loop) subtract that base here. // The base has been used to initialize the PHI node but we don't want // it here. - if (!ReuseIV.Base->isZero()) - RewriteExpr = SE->getMinusSCEV(RewriteExpr, ReuseIV.Base); + if (!ReuseIV.Base->isZero()) { + SCEVHandle typedBase = ReuseIV.Base; + if (RewriteExpr->getType()->getPrimitiveSizeInBits() != + ReuseIV.Base->getType()->getPrimitiveSizeInBits()) { + // It's possible the original IV is a larger type than the new IV, + // in which case we have to truncate the Base. We checked in + // RequiresTypeConversion that this is valid. + assert (RewriteExpr->getType()->getPrimitiveSizeInBits() < + ReuseIV.Base->getType()->getPrimitiveSizeInBits() && + "Unexpected lengthening conversion!"); + typedBase = SE->getTruncateExpr(ReuseIV.Base, + RewriteExpr->getType()); + } + RewriteExpr = SE->getMinusSCEV(RewriteExpr, typedBase); + } // Multiply old variable, with base removed, by new scale factor. RewriteExpr = SE->getMulExpr(RewriteFactor, From tonic at nondot.org Fri Feb 13 18:59:48 2009 From: tonic at nondot.org (Tanya Lattner) Date: Sat, 14 Feb 2009 00:59:48 -0000 Subject: [llvm-commits] [llvm] r64518 - in /llvm/branches/release_25: include/llvm/Target/ lib/CodeGen/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/X86/ lib/Target/XCore/ Message-ID: <200902140059.n1E0xmtl022438@zion.cs.uiuc.edu> Author: tbrethou Date: Fri Feb 13 18:59:47 2009 New Revision: 64518 URL: http://llvm.org/viewvc/llvm-project?rev=64518&view=rev Log: Merge 64124 frm mainline. Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. Modified: llvm/branches/release_25/include/llvm/Target/TargetInstrInfo.h llvm/branches/release_25/lib/CodeGen/BranchFolding.cpp llvm/branches/release_25/lib/Target/ARM/ARMInstrInfo.cpp llvm/branches/release_25/lib/Target/ARM/ARMInstrInfo.h llvm/branches/release_25/lib/Target/Alpha/AlphaInstrInfo.cpp llvm/branches/release_25/lib/Target/Alpha/AlphaInstrInfo.h llvm/branches/release_25/lib/Target/CellSPU/SPUInstrInfo.cpp llvm/branches/release_25/lib/Target/CellSPU/SPUInstrInfo.h llvm/branches/release_25/lib/Target/Mips/MipsInstrInfo.cpp llvm/branches/release_25/lib/Target/Mips/MipsInstrInfo.h llvm/branches/release_25/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/branches/release_25/lib/Target/PowerPC/PPCInstrInfo.h llvm/branches/release_25/lib/Target/X86/X86InstrInfo.cpp llvm/branches/release_25/lib/Target/X86/X86InstrInfo.h llvm/branches/release_25/lib/Target/XCore/XCoreInstrInfo.cpp llvm/branches/release_25/lib/Target/XCore/XCoreInstrInfo.h Modified: llvm/branches/release_25/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/include/llvm/Target/TargetInstrInfo.h?rev=64518&r1=64517&r2=64518&view=diff ============================================================================== --- llvm/branches/release_25/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/branches/release_25/include/llvm/Target/TargetInstrInfo.h Fri Feb 13 18:59:47 2009 @@ -195,9 +195,13 @@ /// Note that RemoveBranch and InsertBranch must be implemented to support /// cases where this method returns success. /// + /// If AllowModify is true, then this routine is allowed to modify the basic + /// block (e.g. delete instructions after the unconditional branch). + /// virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + SmallVectorImpl &Cond, + bool AllowModify = false) const { return true; } Modified: llvm/branches/release_25/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/CodeGen/BranchFolding.cpp?rev=64518&r1=64517&r2=64518&view=diff ============================================================================== --- llvm/branches/release_25/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/branches/release_25/lib/CodeGen/BranchFolding.cpp Fri Feb 13 18:59:47 2009 @@ -191,7 +191,7 @@ for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; I++) { MachineBasicBlock *MBB = I, *TBB = 0, *FBB = 0; SmallVector Cond; - if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond)) + if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, true)) EverMadeChange |= MBB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty()); EverMadeChange |= OptimizeImpDefsBlock(MBB); } @@ -434,7 +434,7 @@ MachineBasicBlock *TBB = 0, *FBB = 0; SmallVector Cond; if (I != MF->end() && - !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond)) { + !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond, true)) { MachineBasicBlock *NextBB = I; if (TBB == NextBB && !Cond.empty() && !FBB) { if (!TII->ReverseBranchCondition(Cond)) { @@ -711,7 +711,7 @@ continue; MachineBasicBlock *TBB = 0, *FBB = 0; SmallVector Cond; - if (!TII->AnalyzeBranch(*PBB, TBB, FBB, Cond)) { + if (!TII->AnalyzeBranch(*PBB, TBB, FBB, Cond, true)) { // Failing case: IBB is the target of a cbr, and // we cannot reverse the branch. SmallVector NewCond(Cond); @@ -845,7 +845,7 @@ bool BranchFolder::CanFallThrough(MachineBasicBlock *CurBB) { MachineBasicBlock *TBB = 0, *FBB = 0; SmallVector Cond; - bool CurUnAnalyzable = TII->AnalyzeBranch(*CurBB, TBB, FBB, Cond); + bool CurUnAnalyzable = TII->AnalyzeBranch(*CurBB, TBB, FBB, Cond, true); return CanFallThrough(CurBB, CurUnAnalyzable, TBB, FBB, Cond); } @@ -910,7 +910,7 @@ MachineBasicBlock *PriorTBB = 0, *PriorFBB = 0; SmallVector PriorCond; bool PriorUnAnalyzable = - TII->AnalyzeBranch(PrevBB, PriorTBB, PriorFBB, PriorCond); + TII->AnalyzeBranch(PrevBB, PriorTBB, PriorFBB, PriorCond, true); if (!PriorUnAnalyzable) { // If the CFG for the prior block has extra edges, remove them. MadeChange |= PrevBB.CorrectExtraCFGEdges(PriorTBB, PriorFBB, @@ -1023,7 +1023,7 @@ // Analyze the branch in the current block. MachineBasicBlock *CurTBB = 0, *CurFBB = 0; SmallVector CurCond; - bool CurUnAnalyzable = TII->AnalyzeBranch(*MBB, CurTBB, CurFBB, CurCond); + bool CurUnAnalyzable= TII->AnalyzeBranch(*MBB, CurTBB, CurFBB, CurCond, true); if (!CurUnAnalyzable) { // If the CFG for the prior block has extra edges, remove them. MadeChange |= MBB->CorrectExtraCFGEdges(CurTBB, CurFBB, !CurCond.empty()); Modified: llvm/branches/release_25/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Target/ARM/ARMInstrInfo.cpp?rev=64518&r1=64517&r2=64518&view=diff ============================================================================== --- llvm/branches/release_25/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/branches/release_25/lib/Target/ARM/ARMInstrInfo.cpp Fri Feb 13 18:59:47 2009 @@ -338,7 +338,8 @@ // Branch analysis. bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) @@ -388,7 +389,8 @@ (LastOpc == ARM::B || LastOpc == ARM::tB)) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return false; } @@ -399,7 +401,8 @@ SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr) && (LastOpc == ARM::B || LastOpc == ARM::tB)) { I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return true; } Modified: llvm/branches/release_25/lib/Target/ARM/ARMInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Target/ARM/ARMInstrInfo.h?rev=64518&r1=64517&r2=64518&view=diff ============================================================================== --- llvm/branches/release_25/lib/Target/ARM/ARMInstrInfo.h (original) +++ llvm/branches/release_25/lib/Target/ARM/ARMInstrInfo.h Fri Feb 13 18:59:47 2009 @@ -176,7 +176,8 @@ // Branch analysis. virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, Modified: llvm/branches/release_25/lib/Target/Alpha/AlphaInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=64518&r1=64517&r2=64518&view=diff ============================================================================== --- llvm/branches/release_25/lib/Target/Alpha/AlphaInstrInfo.cpp (original) +++ llvm/branches/release_25/lib/Target/Alpha/AlphaInstrInfo.cpp Fri Feb 13 18:59:47 2009 @@ -321,8 +321,9 @@ // Branch analysis. bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, - MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) @@ -373,7 +374,8 @@ LastInst->getOpcode() == Alpha::BR) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return false; } Modified: llvm/branches/release_25/lib/Target/Alpha/AlphaInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Target/Alpha/AlphaInstrInfo.h?rev=64518&r1=64517&r2=64518&view=diff ============================================================================== --- llvm/branches/release_25/lib/Target/Alpha/AlphaInstrInfo.h (original) +++ llvm/branches/release_25/lib/Target/Alpha/AlphaInstrInfo.h Fri Feb 13 18:59:47 2009 @@ -83,7 +83,8 @@ bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; unsigned RemoveBranch(MachineBasicBlock &MBB) const; void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const; Modified: llvm/branches/release_25/lib/Target/CellSPU/SPUInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=64518&r1=64517&r2=64518&view=diff ============================================================================== --- llvm/branches/release_25/lib/Target/CellSPU/SPUInstrInfo.cpp (original) +++ llvm/branches/release_25/lib/Target/CellSPU/SPUInstrInfo.cpp Fri Feb 13 18:59:47 2009 @@ -532,7 +532,8 @@ bool SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) @@ -583,7 +584,8 @@ if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return false; } Modified: llvm/branches/release_25/lib/Target/CellSPU/SPUInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Target/CellSPU/SPUInstrInfo.h?rev=64518&r1=64517&r2=64518&view=diff ============================================================================== --- llvm/branches/release_25/lib/Target/CellSPU/SPUInstrInfo.h (original) +++ llvm/branches/release_25/lib/Target/CellSPU/SPUInstrInfo.h Fri Feb 13 18:59:47 2009 @@ -104,7 +104,8 @@ virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; Modified: llvm/branches/release_25/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Target/Mips/MipsInstrInfo.cpp?rev=64518&r1=64517&r2=64518&view=diff ============================================================================== --- llvm/branches/release_25/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/branches/release_25/lib/Target/Mips/MipsInstrInfo.cpp Fri Feb 13 18:59:47 2009 @@ -453,7 +453,8 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); @@ -525,7 +526,8 @@ if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return false; } Modified: llvm/branches/release_25/lib/Target/Mips/MipsInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Target/Mips/MipsInstrInfo.h?rev=64518&r1=64517&r2=64518&view=diff ============================================================================== --- llvm/branches/release_25/lib/Target/Mips/MipsInstrInfo.h (original) +++ llvm/branches/release_25/lib/Target/Mips/MipsInstrInfo.h Fri Feb 13 18:59:47 2009 @@ -166,7 +166,8 @@ /// Branch Analysis virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, Modified: llvm/branches/release_25/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=64518&r1=64517&r2=64518&view=diff ============================================================================== --- llvm/branches/release_25/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/branches/release_25/lib/Target/PowerPC/PPCInstrInfo.cpp Fri Feb 13 18:59:47 2009 @@ -214,7 +214,8 @@ // Branch analysis. bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) @@ -263,7 +264,8 @@ LastInst->getOpcode() == PPC::B) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return false; } Modified: llvm/branches/release_25/lib/Target/PowerPC/PPCInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Target/PowerPC/PPCInstrInfo.h?rev=64518&r1=64517&r2=64518&view=diff ============================================================================== --- llvm/branches/release_25/lib/Target/PowerPC/PPCInstrInfo.h (original) +++ llvm/branches/release_25/lib/Target/PowerPC/PPCInstrInfo.h Fri Feb 13 18:59:47 2009 @@ -108,7 +108,8 @@ // Branch analysis. virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, Modified: llvm/branches/release_25/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Target/X86/X86InstrInfo.cpp?rev=64518&r1=64517&r2=64518&view=diff ============================================================================== --- llvm/branches/release_25/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/branches/release_25/lib/Target/X86/X86InstrInfo.cpp Fri Feb 13 18:59:47 2009 @@ -1488,7 +1488,8 @@ bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + SmallVectorImpl &Cond, + bool AllowModify) const { // Start from the bottom of the block and work up, examining the // terminator instructions. MachineBasicBlock::iterator I = MBB.end(); @@ -1504,6 +1505,11 @@ return true; // Handle unconditional branches. if (I->getOpcode() == X86::JMP) { + if (!AllowModify) { + TBB = I->getOperand(0).getMBB(); + return false; + } + // If the block has any instructions after a JMP, delete them. while (next(I) != MBB.end()) next(I)->eraseFromParent(); Modified: llvm/branches/release_25/lib/Target/X86/X86InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Target/X86/X86InstrInfo.h?rev=64518&r1=64517&r2=64518&view=diff ============================================================================== --- llvm/branches/release_25/lib/Target/X86/X86InstrInfo.h (original) +++ llvm/branches/release_25/lib/Target/X86/X86InstrInfo.h Fri Feb 13 18:59:47 2009 @@ -323,7 +323,8 @@ virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, Modified: llvm/branches/release_25/lib/Target/XCore/XCoreInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Target/XCore/XCoreInstrInfo.cpp?rev=64518&r1=64517&r2=64518&view=diff ============================================================================== --- llvm/branches/release_25/lib/Target/XCore/XCoreInstrInfo.cpp (original) +++ llvm/branches/release_25/lib/Target/XCore/XCoreInstrInfo.cpp Fri Feb 13 18:59:47 2009 @@ -228,8 +228,9 @@ /// bool XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, - MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const { + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) @@ -288,7 +289,8 @@ IsBRU(LastInst->getOpcode())) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; - I->eraseFromParent(); + if (AllowModify) + I->eraseFromParent(); return false; } Modified: llvm/branches/release_25/lib/Target/XCore/XCoreInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Target/XCore/XCoreInstrInfo.h?rev=64518&r1=64517&r2=64518&view=diff ============================================================================== --- llvm/branches/release_25/lib/Target/XCore/XCoreInstrInfo.h (original) +++ llvm/branches/release_25/lib/Target/XCore/XCoreInstrInfo.h Fri Feb 13 18:59:47 2009 @@ -56,7 +56,8 @@ virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond) const; + SmallVectorImpl &Cond, + bool AllowModify) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, From tonic at nondot.org Fri Feb 13 19:04:03 2009 From: tonic at nondot.org (Tanya Lattner) Date: Sat, 14 Feb 2009 01:04:03 -0000 Subject: [llvm-commits] [llvm] r64520 - in /llvm/branches/release_25: lib/Transforms/Utils/InlineFunction.cpp test/Transforms/Inline/inline-invoke-tail.ll Message-ID: <200902140104.n1E143Xc022598@zion.cs.uiuc.edu> Author: tbrethou Date: Fri Feb 13 19:04:03 2009 New Revision: 64520 URL: http://llvm.org/viewvc/llvm-project?rev=64520&view=rev Log: Merge 64364 from mainline. Fix a nasty bug (PR3550) where the inline pass could incorrectly mark calls with the tail marker when inlining them through an invoke. Patch, testcase, and perfect analysis by Jay Foad! Added: llvm/branches/release_25/test/Transforms/Inline/inline-invoke-tail.ll - copied unchanged from r64364, llvm/trunk/test/Transforms/Inline/inline-invoke-tail.ll Modified: llvm/branches/release_25/lib/Transforms/Utils/InlineFunction.cpp Modified: llvm/branches/release_25/lib/Transforms/Utils/InlineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Transforms/Utils/InlineFunction.cpp?rev=64520&r1=64519&r2=64520&view=diff ============================================================================== --- llvm/branches/release_25/lib/Transforms/Utils/InlineFunction.cpp (original) +++ llvm/branches/release_25/lib/Transforms/Utils/InlineFunction.cpp Fri Feb 13 19:04:03 2009 @@ -203,10 +203,10 @@ CalledFunc->getFunctionType()->isVarArg()) return false; - // If the call to the callee is a non-tail call, we must clear the 'tail' + // If the call to the callee is not a tail call, we must clear the 'tail' // flags on any calls that we inline. bool MustClearTailCallFlags = - isa(TheCall) && !cast(TheCall)->isTailCall(); + !(isa(TheCall) && cast(TheCall)->isTailCall()); // If the call to the callee cannot throw, set the 'nounwind' flag on any // calls that we inline. From tonic at nondot.org Fri Feb 13 19:06:08 2009 From: tonic at nondot.org (Tanya Lattner) Date: Sat, 14 Feb 2009 01:06:08 -0000 Subject: [llvm-commits] [llvm] r64521 - in /llvm/branches/release_25/utils/unittest/googletest: Makefile gtest.cc Message-ID: <200902140106.n1E168k7022699@zion.cs.uiuc.edu> Author: tbrethou Date: Fri Feb 13 19:06:08 2009 New Revision: 64521 URL: http://llvm.org/viewvc/llvm-project?rev=64521&view=rev Log: Merge 64367 from mainline. Fix MingW build: define GTEST_OS_WINDOWS if OS is MingW, but disable exceptions. Modified: llvm/branches/release_25/utils/unittest/googletest/Makefile llvm/branches/release_25/utils/unittest/googletest/gtest.cc Modified: llvm/branches/release_25/utils/unittest/googletest/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/utils/unittest/googletest/Makefile?rev=64521&r1=64520&r2=64521&view=diff ============================================================================== --- llvm/branches/release_25/utils/unittest/googletest/Makefile (original) +++ llvm/branches/release_25/utils/unittest/googletest/Makefile Fri Feb 13 19:06:08 2009 @@ -18,4 +18,8 @@ CPP.Flags += -I$(LLVM_SRC_ROOT)/utils/unittest/googletest/include/ CPP.Flags += $(NO_MISSING_FIELD_INITIALIZERS) $(NO_VARIADIC_MACROS) +ifeq ($(OS),MingW) + CPP.Flags += -DGTEST_OS_WINDOWS=1 +endif + include $(LEVEL)/Makefile.common Modified: llvm/branches/release_25/utils/unittest/googletest/gtest.cc URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/utils/unittest/googletest/gtest.cc?rev=64521&r1=64520&r2=64521&view=diff ============================================================================== --- llvm/branches/release_25/utils/unittest/googletest/gtest.cc (original) +++ llvm/branches/release_25/utils/unittest/googletest/gtest.cc Fri Feb 13 19:06:08 2009 @@ -1993,7 +1993,7 @@ if (!HasSameFixtureClass()) return; internal::UnitTestImpl* const impl = internal::GetUnitTestImpl(); -#ifdef GTEST_OS_WINDOWS +#if defined(GTEST_OS_WINDOWS) && !defined(__MINGW32__) // We are on Windows. impl->os_stack_trace_getter()->UponLeavingGTest(); __try { @@ -2025,7 +2025,7 @@ AddExceptionThrownFailure(GetExceptionCode(), "TearDown()"); } -#else // We are on Linux or Mac - exceptions are disabled. +#else // We are on Linux, Mac or MingW - exceptions are disabled. impl->os_stack_trace_getter()->UponLeavingGTest(); SetUp(); @@ -2227,7 +2227,7 @@ const TimeInMillis start = GetTimeInMillis(); impl->os_stack_trace_getter()->UponLeavingGTest(); -#ifdef GTEST_OS_WINDOWS +#if defined(GTEST_OS_WINDOWS) && !defined(__MINGW32__) // We are on Windows. Test* test = NULL; @@ -2240,7 +2240,7 @@ "the test fixture's constructor"); return; } -#else // We are on Linux or Mac OS - exceptions are disabled. +#else // We are on Linux, Mac OS or MingW - exceptions are disabled. // TODO(wan): If test->Run() throws, test won't be deleted. This is // not a problem now as we don't use exceptions. If we were to @@ -3271,7 +3271,7 @@ // We don't protect this under mutex_, as we only support calling it // from the main thread. int UnitTest::Run() { -#ifdef GTEST_OS_WINDOWS +#if defined(GTEST_OS_WINDOWS) && !defined(__MINGW32__) #if !defined(_WIN32_WCE) // SetErrorMode doesn't exist on CE. @@ -3294,7 +3294,7 @@ } #else - // We are on Linux or Mac OS. There is no exception of any kind. + // We are on Linux, Mac OS or MingW. There is no exception of any kind. return impl_->RunAllTests(); #endif // GTEST_OS_WINDOWS From tonic at nondot.org Fri Feb 13 19:07:50 2009 From: tonic at nondot.org (Tanya Lattner) Date: Sat, 14 Feb 2009 01:07:50 -0000 Subject: [llvm-commits] [llvm] r64523 - /llvm/branches/release_25/Makefile.rules Message-ID: <200902140107.n1E17ou6022770@zion.cs.uiuc.edu> Author: tbrethou Date: Fri Feb 13 19:07:49 2009 New Revision: 64523 URL: http://llvm.org/viewvc/llvm-project?rev=64523&view=rev Log: Merge 64412 from mainline. Avoid order files for now, as they aren't supported in 3.79. Modified: llvm/branches/release_25/Makefile.rules Modified: llvm/branches/release_25/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/Makefile.rules?rev=64523&r1=64522&r2=64523&view=diff ============================================================================== --- llvm/branches/release_25/Makefile.rules (original) +++ llvm/branches/release_25/Makefile.rules Fri Feb 13 19:07:49 2009 @@ -560,7 +560,7 @@ # in the file so they get built before dependencies #--------------------------------------------------------- -$(PROJ_bindir) $(PROJ_libdir) $(PROJ_includedir) $(PROJ_etcdir): +$(PROJ_bindir) $(PROJ_libdir) $(PROJ_includedir) $(PROJ_etcdir):: $(Verb) $(MKDIR) $@ # To create other directories, as needed, and timestamp their creation @@ -868,7 +868,7 @@ install-local:: $(DestSharedLib) -$(DestSharedLib): $(LibName.LA) | $(PROJ_libdir) +$(DestSharedLib): $(LibName.LA) $(PROJ_libdir) $(Echo) Installing $(BuildMode) Shared Library $(DestSharedLib) $(Verb) $(LTInstall) $(LibName.LA) $(DestSharedLib) $(Verb) $(LIBTOOL) --finish $(PROJ_libdir) @@ -935,7 +935,7 @@ else install-local:: $(DestBytecodeLib) -$(DestBytecodeLib): $(LibName.BCA) | $(BytecodeDestDir) +$(DestBytecodeLib): $(LibName.BCA) $(BytecodeDestDir) $(Echo) Installing $(BuildMode) Bytecode Archive $(DestBytecodeLib) $(Verb) $(DataInstall) $(LibName.BCA) $(DestBytecodeLib) @@ -982,7 +982,7 @@ install-local:: $(DestRelinkedLib) -$(DestRelinkedLib): $(LibName.O) | $(PROJ_libdir) +$(DestRelinkedLib): $(LibName.O) $(PROJ_libdir) $(Echo) Installing $(BuildMode) Object Library $(DestRelinkedLib) $(Verb) $(LTInstall) $(LibName.O) $(DestRelinkedLib) @@ -1022,7 +1022,7 @@ install-local:: $(DestArchiveLib) -$(DestArchiveLib): $(LibName.A) | $(PROJ_libdir) +$(DestArchiveLib): $(LibName.A) $(PROJ_libdir) $(Echo) Installing $(BuildMode) Archive Library $(DestArchiveLib) $(Verb) $(MKDIR) $(PROJ_libdir) $(Verb) $(LTInstall) $(LibName.A) $(DestArchiveLib) @@ -1084,7 +1084,7 @@ install-local:: $(DestTool) -$(DestTool): $(ToolBuildPath) | $(PROJ_bindir) +$(DestTool): $(ToolBuildPath) $(PROJ_bindir) $(Echo) Installing $(BuildMode) $(DestTool) $(Verb) $(ProgInstall) $(ToolBuildPath) $(DestTool) From tonic at nondot.org Fri Feb 13 19:14:49 2009 From: tonic at nondot.org (Tanya Lattner) Date: Sat, 14 Feb 2009 01:14:49 -0000 Subject: [llvm-commits] [llvm] r64524 - /llvm/branches/release_25/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <200902140114.n1E1EnFR023038@zion.cs.uiuc.edu> Author: tbrethou Date: Fri Feb 13 19:14:49 2009 New Revision: 64524 URL: http://llvm.org/viewvc/llvm-project?rev=64524&view=rev Log: Merge r64316 from mainline. Don't try to set an EFLAGS operand to dead if no instruction was created. This fixes a bug introduced by r61215. Modified: llvm/branches/release_25/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/branches/release_25/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_25/lib/Target/X86/X86RegisterInfo.cpp?rev=64524&r1=64523&r2=64524&view=diff ============================================================================== --- llvm/branches/release_25/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/branches/release_25/lib/Target/X86/X86RegisterInfo.cpp Fri Feb 13 19:14:49 2009 @@ -404,11 +404,13 @@ } } - // The EFLAGS implicit def is dead. - New->getOperand(3).setIsDead(); + if (New) { + // The EFLAGS implicit def is dead. + New->getOperand(3).setIsDead(); - // Replace the pseudo instruction with a new instruction... - if (New) MBB.insert(I, New); + // Replace the pseudo instruction with a new instruction... + MBB.insert(I, New); + } } } else if (I->getOpcode() == getCallFrameDestroyOpcode()) { // If we are performing frame pointer elimination and if the callee pops From gohman at apple.com Fri Feb 13 20:25:20 2009 From: gohman at apple.com (Dan Gohman) Date: Sat, 14 Feb 2009 02:25:20 -0000 Subject: [llvm-commits] [llvm] r64530 - /llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Message-ID: <200902140225.n1E2PKBX025551@zion.cs.uiuc.edu> Author: djg Date: Fri Feb 13 20:25:19 2009 New Revision: 64530 URL: http://llvm.org/viewvc/llvm-project?rev=64530&view=rev Log: Simplify some code. hasComputableLoopEvolution is overkill in this case. No functionality change. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=64530&r1=64529&r2=64530&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Fri Feb 13 20:25:19 2009 @@ -551,15 +551,14 @@ PHINode *PN = cast(I); if (PN->getType()->isInteger()) { // FIXME: when we have fast-math, enable! SCEVHandle SCEV = SE->getSCEV(PN); - if (SCEV->hasComputableLoopEvolution(L)) - // FIXME: It is an extremely bad idea to indvar substitute anything more - // complex than affine induction variables. Doing so will put expensive - // polynomial evaluations inside of the loop, and the str reduction pass - // currently can only reduce affine polynomials. For now just disable - // indvar subst on anything more complex than an affine addrec. - if (SCEVAddRecExpr *AR = dyn_cast(SCEV)) - if (AR->isAffine()) - IndVars.push_back(std::make_pair(PN, SCEV)); + // FIXME: It is an extremely bad idea to indvar substitute anything more + // complex than affine induction variables. Doing so will put expensive + // polynomial evaluations inside of the loop, and the str reduction pass + // currently can only reduce affine polynomials. For now just disable + // indvar subst on anything more complex than an affine addrec. + if (SCEVAddRecExpr *AR = dyn_cast(SCEV)) + if (AR->getLoop() == L && AR->isAffine()) + IndVars.push_back(std::make_pair(PN, SCEV)); } } From gohman at apple.com Fri Feb 13 20:26:50 2009 From: gohman at apple.com (Dan Gohman) Date: Sat, 14 Feb 2009 02:26:50 -0000 Subject: [llvm-commits] [llvm] r64531 - /llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Message-ID: <200902140226.n1E2Qpr4025606@zion.cs.uiuc.edu> Author: djg Date: Fri Feb 13 20:26:50 2009 New Revision: 64531 URL: http://llvm.org/viewvc/llvm-project?rev=64531&view=rev Log: Clarify debug output. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=64531&r1=64530&r2=64531&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Fri Feb 13 20:26:50 2009 @@ -286,7 +286,7 @@ DOUT << "INDVARS: Rewriting loop exit condition to:\n" << " LHS:" << *CmpIndVar // includes a newline << " op:\t" - << (Opcode == ICmpInst::ICMP_NE ? "!=" : "=") << "\n" + << (Opcode == ICmpInst::ICMP_NE ? "!=" : "==") << "\n" << " RHS:\t" << *IterationCount << "\n"; Value *Cond = new ICmpInst(Opcode, CmpIndVar, ExitCnt, "exitcond", BI); From gohman at apple.com Fri Feb 13 20:31:09 2009 From: gohman at apple.com (Dan Gohman) Date: Sat, 14 Feb 2009 02:31:09 -0000 Subject: [llvm-commits] [llvm] r64532 - in /llvm/trunk: lib/Transforms/Scalar/IndVarSimplify.cpp test/Transforms/IndVarsSimplify/promote-iv-to-eliminate-casts.ll Message-ID: <200902140231.n1E2VA2i025743@zion.cs.uiuc.edu> Author: djg Date: Fri Feb 13 20:31:09 2009 New Revision: 64532 URL: http://llvm.org/viewvc/llvm-project?rev=64532&view=rev Log: Extend the IndVarSimplify support for promoting induction variables: - Test for signed and unsigned wrapping conditions, instead of just testing for non-negative induction ranges. - Handle loops with GT comparisons, in addition to LT comparisons. - Support more cases of induction variables that don't start at 0. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp llvm/trunk/test/Transforms/IndVarsSimplify/promote-iv-to-eliminate-casts.ll Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=64532&r1=64531&r2=64532&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Fri Feb 13 20:31:09 2009 @@ -458,33 +458,98 @@ return Ty; } -/// isOrigIVAlwaysNonNegative - Analyze the original induction variable -/// in the loop to determine whether it would ever have a negative -/// value. +/// TestOrigIVForWrap - Analyze the original induction variable +/// in the loop to determine whether it would ever undergo signed +/// or unsigned overflow. /// /// TODO: This duplicates a fair amount of ScalarEvolution logic. -/// Perhaps this can be merged with ScalarEvolution::getIterationCount. +/// Perhaps this can be merged with ScalarEvolution::getIterationCount +/// and/or ScalarEvolution::get{Sign,Zero}ExtendExpr. /// -static bool isOrigIVAlwaysNonNegative(const Loop *L, - const Instruction *OrigCond) { +static void TestOrigIVForWrap(const Loop *L, + const BranchInst *BI, + const Instruction *OrigCond, + bool &NoSignedWrap, + bool &NoUnsignedWrap) { // Verify that the loop is sane and find the exit condition. const ICmpInst *Cmp = dyn_cast(OrigCond); - if (!Cmp) return false; + if (!Cmp) return; - // For now, analyze only SLT loops for signed overflow. - if (Cmp->getPredicate() != ICmpInst::ICMP_SLT) return false; + const Value *CmpLHS = Cmp->getOperand(0); + const Value *CmpRHS = Cmp->getOperand(1); + const BasicBlock *TrueBB = BI->getSuccessor(0); + const BasicBlock *FalseBB = BI->getSuccessor(1); + ICmpInst::Predicate Pred = Cmp->getPredicate(); + + // Canonicalize a constant to the RHS. + if (isa(CmpLHS)) { + Pred = ICmpInst::getSwappedPredicate(Pred); + std::swap(CmpLHS, CmpRHS); + } + // Canonicalize SLE to SLT. + if (Pred == ICmpInst::ICMP_SLE) + if (const ConstantInt *CI = dyn_cast(CmpRHS)) + if (!CI->getValue().isMaxSignedValue()) { + CmpRHS = ConstantInt::get(CI->getValue() + 1); + Pred = ICmpInst::ICMP_SLT; + } + // Canonicalize SGT to SGE. + if (Pred == ICmpInst::ICMP_SGT) + if (const ConstantInt *CI = dyn_cast(CmpRHS)) + if (!CI->getValue().isMaxSignedValue()) { + CmpRHS = ConstantInt::get(CI->getValue() + 1); + Pred = ICmpInst::ICMP_SGE; + } + // Canonicalize SGE to SLT. + if (Pred == ICmpInst::ICMP_SGE) { + std::swap(TrueBB, FalseBB); + Pred = ICmpInst::ICMP_SLT; + } + // Canonicalize ULE to ULT. + if (Pred == ICmpInst::ICMP_ULE) + if (const ConstantInt *CI = dyn_cast(CmpRHS)) + if (!CI->getValue().isMaxValue()) { + CmpRHS = ConstantInt::get(CI->getValue() + 1); + Pred = ICmpInst::ICMP_ULT; + } + // Canonicalize UGT to UGE. + if (Pred == ICmpInst::ICMP_UGT) + if (const ConstantInt *CI = dyn_cast(CmpRHS)) + if (!CI->getValue().isMaxValue()) { + CmpRHS = ConstantInt::get(CI->getValue() + 1); + Pred = ICmpInst::ICMP_UGE; + } + // Canonicalize UGE to ULT. + if (Pred == ICmpInst::ICMP_UGE) { + std::swap(TrueBB, FalseBB); + Pred = ICmpInst::ICMP_ULT; + } + // For now, analyze only LT loops for signed overflow. + if (Pred != ICmpInst::ICMP_SLT && Pred != ICmpInst::ICMP_ULT) + return; + + bool isSigned = Pred == ICmpInst::ICMP_SLT; - // Get the increment instruction. Look past SExtInsts if we will + // Get the increment instruction. Look past casts if we will // be able to prove that the original induction variable doesn't - // undergo signed overflow. - const Value *OrigIncrVal = Cmp->getOperand(0); - const Value *IncrVal = OrigIncrVal; - if (SExtInst *SI = dyn_cast(Cmp->getOperand(0))) { - if (!isa(Cmp->getOperand(1)) || - !cast(Cmp->getOperand(1))->getValue() - .isSignedIntN(IncrVal->getType()->getPrimitiveSizeInBits())) - return false; - IncrVal = SI->getOperand(0); + // undergo signed or unsigned overflow, respectively. + const Value *IncrVal = CmpLHS; + if (isSigned) { + if (const SExtInst *SI = dyn_cast(CmpLHS)) { + if (!isa(CmpRHS) || + !cast(CmpRHS)->getValue() + .isSignedIntN(IncrVal->getType()->getPrimitiveSizeInBits())) + return; + IncrVal = SI->getOperand(0); + } + } else { + if (const ZExtInst *ZI = dyn_cast(CmpLHS)) { + if (!isa(CmpRHS) || + !cast(CmpRHS)->getValue() + .isIntN(IncrVal->getType()->getPrimitiveSizeInBits())) + return; + IncrVal = ZI->getOperand(0); + } } // For now, only analyze induction variables that have simple increments. @@ -493,32 +558,36 @@ IncrOp->getOpcode() != Instruction::Add || !isa(IncrOp->getOperand(1)) || !cast(IncrOp->getOperand(1))->equalsInt(1)) - return false; + return; // Make sure the PHI looks like a normal IV. const PHINode *PN = dyn_cast(IncrOp->getOperand(0)); if (!PN || PN->getNumIncomingValues() != 2) - return false; + return; unsigned IncomingEdge = L->contains(PN->getIncomingBlock(0)); unsigned BackEdge = !IncomingEdge; if (!L->contains(PN->getIncomingBlock(BackEdge)) || PN->getIncomingValue(BackEdge) != IncrOp) - return false; + return; + if (!L->contains(TrueBB)) + return; // For now, only analyze loops with a constant start value, so that - // we can easily determine if the start value is non-negative and - // not a maximum value which would wrap on the first iteration. + // we can easily determine if the start value is not a maximum value + // which would wrap on the first iteration. const Value *InitialVal = PN->getIncomingValue(IncomingEdge); - if (!isa(InitialVal) || - cast(InitialVal)->getValue().isNegative() || - cast(InitialVal)->getValue().isMaxSignedValue()) - return false; + if (!isa(InitialVal)) + return; - // The original induction variable will start at some non-negative - // non-max value, it counts up by one, and the loop iterates only - // while it remans less than (signed) some value in the same type. - // As such, it will always be non-negative. - return true; + // The original induction variable will start at some non-max value, + // it counts up by one, and the loop iterates only while it remans + // less than some value in the same type. As such, it will never wrap. + if (isSigned && + !cast(InitialVal)->getValue().isMaxSignedValue()) + NoSignedWrap = true; + else if (!isSigned && + !cast(InitialVal)->getValue().isMaxValue()) + NoUnsignedWrap = true; } bool IndVarSimplify::runOnLoop(Loop *L, LPPassManager &LPM) { @@ -596,13 +665,15 @@ // If we have a trip count expression, rewrite the loop's exit condition // using it. We can currently only handle loops with a single exit. - bool OrigIVAlwaysNonNegative = false; + bool NoSignedWrap = false; + bool NoUnsignedWrap = false; if (!isa(IterationCount) && ExitingBlock) // Can't rewrite non-branch yet. if (BranchInst *BI = dyn_cast(ExitingBlock->getTerminator())) { if (Instruction *OrigCond = dyn_cast(BI->getCondition())) { - // Determine if the OrigIV will ever have a non-zero sign bit. - OrigIVAlwaysNonNegative = isOrigIVAlwaysNonNegative(L, OrigCond); + // Determine if the OrigIV will ever undergo overflow. + TestOrigIVForWrap(L, BI, OrigCond, + NoSignedWrap, NoUnsignedWrap); // We'll be replacing the original condition, so it'll be dead. DeadInsts.insert(OrigCond); @@ -642,19 +713,38 @@ /// If the new canonical induction variable is wider than the original, /// and the original has uses that are casts to wider types, see if the /// truncate and extend can be omitted. - if (isa(NewVal)) + if (PN->getType() != LargestType) for (Value::use_iterator UI = PN->use_begin(), UE = PN->use_end(); - UI != UE; ++UI) - if (isa(UI) || - (isa(UI) && OrigIVAlwaysNonNegative)) { - Value *TruncIndVar = IndVar; - if (TruncIndVar->getType() != UI->getType()) - TruncIndVar = new TruncInst(IndVar, UI->getType(), "truncindvar", - InsertPt); + UI != UE; ++UI) { + if (isa(UI) && NoSignedWrap) { + SCEVHandle ExtendedStart = + SE->getSignExtendExpr(cast(IndVars.back().second)->getStart(), LargestType); + SCEVHandle ExtendedStep = + SE->getSignExtendExpr(cast(IndVars.back().second)->getStepRecurrence(*SE), LargestType); + SCEVHandle ExtendedAddRec = + SE->getAddRecExpr(ExtendedStart, ExtendedStep, L); + if (LargestType != UI->getType()) + ExtendedAddRec = SE->getTruncateExpr(ExtendedAddRec, UI->getType()); + Value *TruncIndVar = Rewriter.expandCodeFor(ExtendedAddRec, InsertPt); + UI->replaceAllUsesWith(TruncIndVar); + if (Instruction *DeadUse = dyn_cast(*UI)) + DeadInsts.insert(DeadUse); + } + if (isa(UI) && NoUnsignedWrap) { + SCEVHandle ExtendedStart = + SE->getZeroExtendExpr(cast(IndVars.back().second)->getStart(), LargestType); + SCEVHandle ExtendedStep = + SE->getZeroExtendExpr(cast(IndVars.back().second)->getStepRecurrence(*SE), LargestType); + SCEVHandle ExtendedAddRec = + SE->getAddRecExpr(ExtendedStart, ExtendedStep, L); + if (LargestType != UI->getType()) + ExtendedAddRec = SE->getTruncateExpr(ExtendedAddRec, UI->getType()); + Value *TruncIndVar = Rewriter.expandCodeFor(ExtendedAddRec, InsertPt); UI->replaceAllUsesWith(TruncIndVar); if (Instruction *DeadUse = dyn_cast(*UI)) DeadInsts.insert(DeadUse); } + } // Replace the old PHI Node with the inserted computation. PN->replaceAllUsesWith(NewVal); Modified: llvm/trunk/test/Transforms/IndVarsSimplify/promote-iv-to-eliminate-casts.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarsSimplify/promote-iv-to-eliminate-casts.ll?rev=64532&r1=64531&r2=64532&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarsSimplify/promote-iv-to-eliminate-casts.ll (original) +++ llvm/trunk/test/Transforms/IndVarsSimplify/promote-iv-to-eliminate-casts.ll Fri Feb 13 20:31:09 2009 @@ -60,3 +60,41 @@ return: ; preds = %bb1.return_crit_edge, %entry ret void } + +; Test cases from PR1301: + +define void @kinds__srangezero([21 x i32]* nocapture %a) nounwind { +bb.thread: + br label %bb + +bb: ; preds = %bb, %bb.thread + %i.0.reg2mem.0 = phi i8 [ -10, %bb.thread ], [ %tmp7, %bb ] ; [#uses=2] + %tmp12 = sext i8 %i.0.reg2mem.0 to i32 ; [#uses=1] + %tmp4 = add i32 %tmp12, 10 ; [#uses=1] + %tmp5 = getelementptr [21 x i32]* %a, i32 0, i32 %tmp4 ; [#uses=1] + store i32 0, i32* %tmp5 + %tmp7 = add i8 %i.0.reg2mem.0, 1 ; [#uses=2] + %0 = icmp sgt i8 %tmp7, 10 ; [#uses=1] + br i1 %0, label %return, label %bb + +return: ; preds = %bb + ret void +} + +define void @kinds__urangezero([21 x i32]* nocapture %a) nounwind { +bb.thread: + br label %bb + +bb: ; preds = %bb, %bb.thread + %i.0.reg2mem.0 = phi i8 [ 10, %bb.thread ], [ %tmp7, %bb ] ; [#uses=2] + %tmp12 = sext i8 %i.0.reg2mem.0 to i32 ; [#uses=1] + %tmp4 = add i32 %tmp12, -10 ; [#uses=1] + %tmp5 = getelementptr [21 x i32]* %a, i32 0, i32 %tmp4 ; [#uses=1] + store i32 0, i32* %tmp5 + %tmp7 = add i8 %i.0.reg2mem.0, 1 ; [#uses=2] + %0 = icmp sgt i8 %tmp7, 30 ; [#uses=1] + br i1 %0, label %return, label %bb + +return: ; preds = %bb + ret void +} From deeppatel1987 at gmail.com Fri Feb 13 20:43:11 2009 From: deeppatel1987 at gmail.com (Sandeep Patel) Date: Fri, 13 Feb 2009 18:43:11 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r64506 - in /llvm-gcc-4.2/trunk/gcc/config: arm/arm.h i386/i386.h rs6000/rs6000.h In-Reply-To: <200902132335.n1DNZXlO019348@zion.cs.uiuc.edu> References: <200902132335.n1DNZXlO019348@zion.cs.uiuc.edu> Message-ID: <305d6f60902131843n59b6f25ekc79054a6b8716cf1@mail.gmail.com> You probably meant TARGET_SOFT_FLOAT here. deep On Fri, Feb 13, 2009 at 3:35 PM, Evan Cheng wrote: > Author: evancheng > Date: Fri Feb 13 17:35:33 2009 > New Revision: 64506 > > URL: http://llvm.org/viewvc/llvm-project?rev=64506&view=rev > Log: > Translate -msoft-float to -soft-float. > > Modified: > llvm-gcc-4.2/trunk/gcc/config/arm/arm.h > llvm-gcc-4.2/trunk/gcc/config/i386/i386.h > llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h > > Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.h > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.h?rev=64506&r1=64505&r2=64506&view=diff > > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/config/arm/arm.h (original) > +++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.h Fri Feb 13 17:35:33 2009 > @@ -2922,6 +2922,10 @@ > #define LLVM_OVERRIDE_TARGET_ARCH() \ > (TARGET_THUMB ? "thumb" : "") > > +#define LLVM_SET_MACHINE_OPTIONS(argvec) \ > + if (TARGET_SOFT_FLAT) \ > + argvec.push_back("-soft-float"); > + > /* Doing struct copy by partial-word loads and stores is not a good idea on ARM. */ > #define TARGET_LLVM_MIN_BYTES_COPY_BY_MEMCPY 4 > > > Modified: llvm-gcc-4.2/trunk/gcc/config/i386/i386.h > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/i386.h?rev=64506&r1=64505&r2=64506&view=diff > > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/config/i386/i386.h (original) > +++ llvm-gcc-4.2/trunk/gcc/config/i386/i386.h Fri Feb 13 17:35:33 2009 > @@ -3892,6 +3892,10 @@ > if (TARGET_3DNOW) F.AddFeature("3dnow"); \ > if (TARGET_3DNOW_A) F.AddFeature("3dnowa"); \ > } > + > +#define LLVM_SET_MACHINE_OPTIONS(argvec) \ > + if (!TARGET_80387) \ > + argvec.push_back("-soft-float"); > > /* LLVM ABI definition macros. */ > > > Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h?rev=64506&r1=64505&r2=64506&view=diff > > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h (original) > +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Fri Feb 13 17:35:33 2009 > @@ -3463,6 +3463,10 @@ > F.AddFeature("64bit", TARGET_POWERPC64); \ > } > > +#define LLVM_SET_MACHINE_OPTIONS(argvec) \ > + if (TARGET_SOFT_FLAT) \ > + argvec.push_back("-soft-float"); > + > /* When -m64 is specified, set the architecture to powerpc64-os-blah even if the > * compiler was configured for powerpc-os-blah. > */ > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From gohman at apple.com Fri Feb 13 21:30:05 2009 From: gohman at apple.com (Dan Gohman) Date: Sat, 14 Feb 2009 03:30:05 -0000 Subject: [llvm-commits] [llvm] r64535 - /llvm/trunk/lib/Target/X86/README-X86-64.txt Message-ID: <200902140330.n1E3U5Ph027618@zion.cs.uiuc.edu> Author: djg Date: Fri Feb 13 21:30:05 2009 New Revision: 64535 URL: http://llvm.org/viewvc/llvm-project?rev=64535&view=rev Log: The x86-64 red zone is now being used. Modified: llvm/trunk/lib/Target/X86/README-X86-64.txt Modified: llvm/trunk/lib/Target/X86/README-X86-64.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-X86-64.txt?rev=64535&r1=64534&r2=64535&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/README-X86-64.txt (original) +++ llvm/trunk/lib/Target/X86/README-X86-64.txt Fri Feb 13 21:30:05 2009 @@ -5,10 +5,6 @@ //===---------------------------------------------------------------------===// -Make use of "Red Zone". - -//===---------------------------------------------------------------------===// - For this: extern void xx(void); From baldrick at free.fr Fri Feb 13 23:16:26 2009 From: baldrick at free.fr (Duncan Sands) Date: Sat, 14 Feb 2009 05:16:26 -0000 Subject: [llvm-commits] [llvm] r64539 - /llvm/trunk/include/llvm/Intrinsics.td Message-ID: <200902140516.n1E5GQOb030649@zion.cs.uiuc.edu> Author: baldrick Date: Fri Feb 13 23:16:25 2009 New Revision: 64539 URL: http://llvm.org/viewvc/llvm-project?rev=64539&view=rev Log: IntrWriteArgMem implies nocapture, but this wasn't taken advantage of anywhere. Change the definition of IntrWriteArgMem to no longer imply nocapture, and explicitly add nocapture attributes everywhere (well, not quite everywhere, because some of these intrinsics did capture their arguments!). Also, make clear that the lack of other side-effects does not exclude doing volatile loads or stores - the atomic intrinsics do these, yet they are all marked IntrWriteArgMem (this change is safe because nothing exploited it). Modified: llvm/trunk/include/llvm/Intrinsics.td Modified: llvm/trunk/include/llvm/Intrinsics.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=64539&r1=64538&r2=64539&view=diff ============================================================================== --- llvm/trunk/include/llvm/Intrinsics.td (original) +++ llvm/trunk/include/llvm/Intrinsics.td Fri Feb 13 23:16:25 2009 @@ -38,9 +38,8 @@ def IntrReadMem : IntrinsicProperty; // IntrWriteArgMem - This intrinsic reads and writes only from memory that one -// of its arguments points to, but may access an unspecified amount. It has no -// other side effects. This may only be used if the intrinsic doesn't "capture" -// the argument pointer (e.g. storing it someplace). +// of its arguments points to, but may access an unspecified amount. The reads +// and writes may be volatile, but except for this it has no other side effects. def IntrWriteArgMem : IntrinsicProperty; // IntrWriteMem - This intrinsic may read or modify unspecified memory or has @@ -173,7 +172,7 @@ [IntrReadArgMem]>; def int_gcwrite : Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_ptr_ty, llvm_ptrptr_ty], - [IntrWriteArgMem]>; + [IntrWriteArgMem, NoCapture<1>, NoCapture<2>]>; //===--------------------- Code Generator Intrinsics ----------------------===// // @@ -192,7 +191,7 @@ // with respect to nearby accesses to the same memory. def int_prefetch : Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], - [IntrWriteArgMem]>; + [IntrWriteArgMem, NoCapture<0>]>; def int_pcmarker : Intrinsic<[llvm_void_ty], [llvm_i32_ty]>; def int_readcyclecounter : Intrinsic<[llvm_i64_ty]>; @@ -340,62 +339,62 @@ def int_atomic_cmp_swap : Intrinsic<[llvm_anyint_ty], [LLVMAnyPointerType>, LLVMMatchType<0>, LLVMMatchType<0>], - [IntrWriteArgMem]>, + [IntrWriteArgMem, NoCapture<0>]>, GCCBuiltin<"__sync_val_compare_and_swap">; def int_atomic_load_add : Intrinsic<[llvm_anyint_ty], [LLVMAnyPointerType>, LLVMMatchType<0>], - [IntrWriteArgMem]>, + [IntrWriteArgMem, NoCapture<0>]>, GCCBuiltin<"__sync_fetch_and_add">; def int_atomic_swap : Intrinsic<[llvm_anyint_ty], [LLVMAnyPointerType>, LLVMMatchType<0>], - [IntrWriteArgMem]>, + [IntrWriteArgMem, NoCapture<0>]>, GCCBuiltin<"__sync_lock_test_and_set">; def int_atomic_load_sub : Intrinsic<[llvm_anyint_ty], [LLVMAnyPointerType>, LLVMMatchType<0>], - [IntrWriteArgMem]>, + [IntrWriteArgMem, NoCapture<0>]>, GCCBuiltin<"__sync_fetch_and_sub">; def int_atomic_load_and : Intrinsic<[llvm_anyint_ty], [LLVMAnyPointerType>, LLVMMatchType<0>], - [IntrWriteArgMem]>, + [IntrWriteArgMem, NoCapture<0>]>, GCCBuiltin<"__sync_fetch_and_and">; def int_atomic_load_or : Intrinsic<[llvm_anyint_ty], [LLVMAnyPointerType>, LLVMMatchType<0>], - [IntrWriteArgMem]>, + [IntrWriteArgMem, NoCapture<0>]>, GCCBuiltin<"__sync_fetch_and_or">; def int_atomic_load_xor : Intrinsic<[llvm_anyint_ty], [LLVMAnyPointerType>, LLVMMatchType<0>], - [IntrWriteArgMem]>, + [IntrWriteArgMem, NoCapture<0>]>, GCCBuiltin<"__sync_fetch_and_xor">; def int_atomic_load_nand : Intrinsic<[llvm_anyint_ty], [LLVMAnyPointerType>, LLVMMatchType<0>], - [IntrWriteArgMem]>, + [IntrWriteArgMem, NoCapture<0>]>, GCCBuiltin<"__sync_fetch_and_nand">; def int_atomic_load_min : Intrinsic<[llvm_anyint_ty], [LLVMAnyPointerType>, LLVMMatchType<0>], - [IntrWriteArgMem]>, + [IntrWriteArgMem, NoCapture<0>]>, GCCBuiltin<"__sync_fetch_and_min">; def int_atomic_load_max : Intrinsic<[llvm_anyint_ty], [LLVMAnyPointerType>, LLVMMatchType<0>], - [IntrWriteArgMem]>, + [IntrWriteArgMem, NoCapture<0>]>, GCCBuiltin<"__sync_fetch_and_max">; def int_atomic_load_umin : Intrinsic<[llvm_anyint_ty], [LLVMAnyPointerType>, LLVMMatchType<0>], - [IntrWriteArgMem]>, + [IntrWriteArgMem, NoCapture<0>]>, GCCBuiltin<"__sync_fetch_and_umin">; def int_atomic_load_umax : Intrinsic<[llvm_anyint_ty], [LLVMAnyPointerType>, LLVMMatchType<0>], - [IntrWriteArgMem]>, + [IntrWriteArgMem, NoCapture<0>]>, GCCBuiltin<"__sync_fetch_and_umax">; //===-------------------------- Other Intrinsics --------------------------===// From baldrick at free.fr Fri Feb 13 23:33:26 2009 From: baldrick at free.fr (Duncan Sands) Date: Sat, 14 Feb 2009 05:33:26 -0000 Subject: [llvm-commits] [llvm] r64540 - /llvm/trunk/include/llvm/Intrinsics.td Message-ID: <200902140533.n1E5XQIC031184@zion.cs.uiuc.edu> Author: baldrick Date: Fri Feb 13 23:33:26 2009 New Revision: 64540 URL: http://llvm.org/viewvc/llvm-project?rev=64540&view=rev Log: The trampoline intrinsic can be marked IntrWriteArgMem, now that this no longer implies nocapture. Modified: llvm/trunk/include/llvm/Intrinsics.td Modified: llvm/trunk/include/llvm/Intrinsics.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=64540&r1=64539&r2=64540&view=diff ============================================================================== --- llvm/trunk/include/llvm/Intrinsics.td (original) +++ llvm/trunk/include/llvm/Intrinsics.td Fri Feb 13 23:33:26 2009 @@ -307,7 +307,7 @@ // def int_init_trampoline : Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty, llvm_ptr_ty], - []>, + [IntrWriteArgMem]>, GCCBuiltin<"__builtin_init_trampoline">; //===------------------------ Overflow Intrinsics -------------------------===// From evan.cheng at apple.com Sat Feb 14 01:39:18 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 14 Feb 2009 07:39:18 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r64544 - in /llvm-gcc-4.2/trunk/gcc/config: arm/arm.h rs6000/rs6000.h Message-ID: <200902140739.n1E7dISB002445@zion.cs.uiuc.edu> Author: evancheng Date: Sat Feb 14 01:39:17 2009 New Revision: 64544 URL: http://llvm.org/viewvc/llvm-project?rev=64544&view=rev Log: Typo. Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.h llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.h?rev=64544&r1=64543&r2=64544&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/arm.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.h Sat Feb 14 01:39:17 2009 @@ -2923,7 +2923,7 @@ (TARGET_THUMB ? "thumb" : "") #define LLVM_SET_MACHINE_OPTIONS(argvec) \ - if (TARGET_SOFT_FLAT) \ + if (TARGET_SOFT_FLOAT) \ argvec.push_back("-soft-float"); /* Doing struct copy by partial-word loads and stores is not a good idea on ARM. */ Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h?rev=64544&r1=64543&r2=64544&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Sat Feb 14 01:39:17 2009 @@ -3464,7 +3464,7 @@ } #define LLVM_SET_MACHINE_OPTIONS(argvec) \ - if (TARGET_SOFT_FLAT) \ + if (TARGET_SOFT_FLOAT) \ argvec.push_back("-soft-float"); /* When -m64 is specified, set the architecture to powerpc64-os-blah even if the From foldr at codedgers.com Sat Feb 14 02:41:25 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Sat, 14 Feb 2009 08:41:25 -0000 Subject: [llvm-commits] [llvm] r64550 - /llvm/trunk/include/llvm/DerivedTypes.h Message-ID: <200902140841.n1E8fPGu006073@zion.cs.uiuc.edu> Author: foldr Date: Sat Feb 14 02:41:25 2009 New Revision: 64550 URL: http://llvm.org/viewvc/llvm-project?rev=64550&view=rev Log: 80-column violation. Modified: llvm/trunk/include/llvm/DerivedTypes.h Modified: llvm/trunk/include/llvm/DerivedTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/DerivedTypes.h?rev=64550&r1=64549&r2=64550&view=diff ============================================================================== --- llvm/trunk/include/llvm/DerivedTypes.h (original) +++ llvm/trunk/include/llvm/DerivedTypes.h Sat Feb 14 02:41:25 2009 @@ -75,7 +75,7 @@ /// Class to represent integer types. Note that this class is also used to /// represent the built-in integer types: Int1Ty, Int8Ty, Int16Ty, Int32Ty and -/// Int64Ty. +/// Int64Ty. /// @brief Integer representation type class IntegerType : public DerivedType { protected: @@ -92,7 +92,7 @@ ///< which has 23 bits. This yields a maximum bit width of 8,388,607 bits. }; - /// This static method is the primary way of constructing an IntegerType. + /// This static method is the primary way of constructing an IntegerType. /// If an IntegerType with the same NumBits value was previously instantiated, /// that instance will be returned. Otherwise a new one will be created. Only /// one instance with a given NumBits value is ever created. @@ -114,14 +114,14 @@ uint64_t getSignBit() const { return 1ULL << (getBitWidth()-1); } - + /// For example, this is 0xFF for an 8 bit integer, 0xFFFF for i16, etc. /// @returns a bit mask with ones set for all the bits of this type. /// @brief Get a bit mask for this type. APInt getMask() const; /// This method determines if the width of this IntegerType is a power-of-2 - /// in terms of 8 bit bytes. + /// in terms of 8 bit bytes. /// @returns true if this is a power-of-2 byte width. /// @brief Is this a power-of-2 byte-width IntegerType ? bool isPowerOf2ByteWidth() const; @@ -147,14 +147,14 @@ public: /// FunctionType::get - This static method is the primary way of constructing - /// a FunctionType. + /// a FunctionType. /// static FunctionType *get( const Type *Result, ///< The result type const std::vector &Params, ///< The types of the parameters bool isVarArg ///< Whether this is a variable argument length function ); - + /// isValidReturnType - Return true if the specified type is valid as a return /// type. static bool isValidReturnType(const Type *RetTy); @@ -223,7 +223,7 @@ /// StructType::get - This static method is the primary way to create a /// StructType. /// - static StructType *get(const std::vector &Params, + static StructType *get(const std::vector &Params, bool isPacked=false); /// StructType::get - This static method is a convenience method for @@ -282,9 +282,9 @@ // avoiding warning: 'this' : used in base member initializer list SequentialType* this_() { return this; } protected: - SequentialType(TypeID TID, const Type *ElType) + SequentialType(TypeID TID, const Type *ElType) : CompositeType(TID), ContainedType(ElType, this_()) { - ContainedTys = &ContainedType; + ContainedTys = &ContainedType; NumContainedTys = 1; } @@ -395,7 +395,7 @@ inline unsigned getNumElements() const { return NumElements; } /// @brief Return the number of bits in the Vector type. - inline unsigned getBitWidth() const { + inline unsigned getBitWidth() const { return NumElements *getElementType()->getPrimitiveSizeInBits(); } @@ -416,21 +416,21 @@ class PointerType : public SequentialType { friend class TypeMap; unsigned AddressSpace; - + PointerType(const PointerType &); // Do not implement const PointerType &operator=(const PointerType &); // Do not implement explicit PointerType(const Type *ElType, unsigned AddrSpace); public: - /// PointerType::get - This constructs a pointer to an object of the specified + /// PointerType::get - This constructs a pointer to an object of the specified /// type in a numbered address space. static PointerType *get(const Type *ElementType, unsigned AddressSpace); - - /// PointerType::getUnqual - This constructs a pointer to an object of the + + /// PointerType::getUnqual - This constructs a pointer to an object of the /// specified type in the generic address space (address space zero). - static PointerType *getUnqual(const Type *ElementType) { + static PointerType *getUnqual(const Type *ElementType) { return PointerType::get(ElementType, 0); } - + /// @brief Return the address space of the Pointer type. inline unsigned getAddressSpace() const { return AddressSpace; } From evan.cheng at apple.com Sat Feb 14 04:16:36 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 14 Feb 2009 02:16:36 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r64506 - in /llvm-gcc-4.2/trunk/gcc/config: arm/arm.h i386/i386.h rs6000/rs6000.h In-Reply-To: <305d6f60902131843n59b6f25ekc79054a6b8716cf1@mail.gmail.com> References: <200902132335.n1DNZXlO019348@zion.cs.uiuc.edu> <305d6f60902131843n59b6f25ekc79054a6b8716cf1@mail.gmail.com> Message-ID: <582BFD72-1E65-49EC-B7CF-30834563AE4C@apple.com> Yes, of course. Thanks. Evan On Feb 13, 2009, at 6:43 PM, Sandeep Patel wrote: > You probably meant TARGET_SOFT_FLOAT here. > > deep > > On Fri, Feb 13, 2009 at 3:35 PM, Evan Cheng > wrote: >> Author: evancheng >> Date: Fri Feb 13 17:35:33 2009 >> New Revision: 64506 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=64506&view=rev >> Log: >> Translate -msoft-float to -soft-float. >> >> Modified: >> llvm-gcc-4.2/trunk/gcc/config/arm/arm.h >> llvm-gcc-4.2/trunk/gcc/config/i386/i386.h >> llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h >> >> Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.h >> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.h?rev=64506&r1=64505&r2=64506&view=diff >> >> === >> === >> === >> ===================================================================== >> --- llvm-gcc-4.2/trunk/gcc/config/arm/arm.h (original) >> +++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.h Fri Feb 13 17:35:33 2009 >> @@ -2922,6 +2922,10 @@ >> #define LLVM_OVERRIDE_TARGET_ARCH() \ >> (TARGET_THUMB ? "thumb" : "") >> >> +#define LLVM_SET_MACHINE_OPTIONS(argvec) \ >> + if (TARGET_SOFT_FLAT) \ >> + argvec.push_back("-soft-float"); >> + >> /* Doing struct copy by partial-word loads and stores is not a good >> idea on ARM. */ >> #define TARGET_LLVM_MIN_BYTES_COPY_BY_MEMCPY 4 >> >> >> Modified: llvm-gcc-4.2/trunk/gcc/config/i386/i386.h >> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/i386.h?rev=64506&r1=64505&r2=64506&view=diff >> >> === >> === >> === >> ===================================================================== >> --- llvm-gcc-4.2/trunk/gcc/config/i386/i386.h (original) >> +++ llvm-gcc-4.2/trunk/gcc/config/i386/i386.h Fri Feb 13 17:35:33 >> 2009 >> @@ -3892,6 +3892,10 @@ >> if (TARGET_3DNOW) F.AddFeature("3dnow"); \ >> if (TARGET_3DNOW_A) F.AddFeature("3dnowa"); \ >> } >> + >> +#define LLVM_SET_MACHINE_OPTIONS(argvec) \ >> + if (!TARGET_80387) \ >> + argvec.push_back("-soft-float"); >> >> /* LLVM ABI definition macros. */ >> >> >> Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h >> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h?rev=64506&r1=64505&r2=64506&view=diff >> >> === >> === >> === >> ===================================================================== >> --- llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h (original) >> +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Fri Feb 13 >> 17:35:33 2009 >> @@ -3463,6 +3463,10 @@ >> F.AddFeature("64bit", TARGET_POWERPC64); \ >> } >> >> +#define LLVM_SET_MACHINE_OPTIONS(argvec) \ >> + if (TARGET_SOFT_FLAT) \ >> + argvec.push_back("-soft-float"); >> + >> /* When -m64 is specified, set the architecture to powerpc64-os- >> blah even if the >> * compiler was configured for powerpc-os-blah. >> */ >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Sat Feb 14 04:56:45 2009 From: baldrick at free.fr (Duncan Sands) Date: Sat, 14 Feb 2009 10:56:45 -0000 Subject: [llvm-commits] [llvm] r64551 - in /llvm/trunk: lib/Analysis/AliasAnalysis.cpp lib/Analysis/BasicAliasAnalysis.cpp utils/TableGen/IntrinsicEmitter.cpp utils/TableGen/IntrinsicEmitter.h Message-ID: <200902141056.n1EAul6P019216@zion.cs.uiuc.edu> Author: baldrick Date: Sat Feb 14 04:56:35 2009 New Revision: 64551 URL: http://llvm.org/viewvc/llvm-project?rev=64551&view=rev Log: Generalize some alias analysis logic from atomic intrinsics to any IntrWriteArgMem intrinsics. Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp llvm/trunk/utils/TableGen/IntrinsicEmitter.h Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=64551&r1=64550&r2=64551&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Sat Feb 14 04:56:35 2009 @@ -124,8 +124,13 @@ if (F->doesNotAccessMemory()) // Can't do better than this. return DoesNotAccessMemory; - else if (F->onlyReadsMemory()) + if (F->onlyReadsMemory()) return OnlyReadsMemory; + if (unsigned id = F->getIntrinsicID()) { +#define GET_INTRINSIC_MODREF_BEHAVIOR +#include "llvm/Intrinsics.gen" +#undef GET_INTRINSIC_MODREF_BEHAVIOR + } } return UnknownModRefBehavior; } Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=64551&r1=64550&r2=64551&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Sat Feb 14 04:56:35 2009 @@ -201,13 +201,7 @@ ModRefResult getModRefInfo(CallSite CS, Value *P, unsigned Size); ModRefResult getModRefInfo(CallSite CS1, CallSite CS2); - - virtual ModRefBehavior getModRefBehavior(CallSite CS, - std::vector *Info = 0); - virtual ModRefBehavior getModRefBehavior(Function *F, - std::vector *Info = 0); - /// hasNoModRefInfoForCalls - We can provide mod/ref information against /// non-escaping allocations. virtual bool hasNoModRefInfoForCalls() const { return false; } @@ -251,51 +245,6 @@ } -static bool isAtomicRMW(Function* F) { - if (!F) return false; - if (F->isIntrinsic()) { - switch (F->getIntrinsicID()) { - case Intrinsic::atomic_cmp_swap: - case Intrinsic::atomic_load_add: - case Intrinsic::atomic_load_and: - case Intrinsic::atomic_load_max: - case Intrinsic::atomic_load_min: - case Intrinsic::atomic_load_nand: - case Intrinsic::atomic_load_or: - case Intrinsic::atomic_load_sub: - case Intrinsic::atomic_load_umax: - case Intrinsic::atomic_load_umin: - case Intrinsic::atomic_load_xor: - case Intrinsic::atomic_swap: - return true; - default: - return false; - } - } - - return false; -} - -AliasAnalysis::ModRefBehavior -BasicAliasAnalysis::getModRefBehavior(CallSite CS, - std::vector *Info) { - if (isAtomicRMW(CS.getCalledFunction())) - // CAS and related intrinsics only access their arguments. - return AliasAnalysis::AccessesArguments; - - return AliasAnalysis::getModRefBehavior(CS, Info); -} - -AliasAnalysis::ModRefBehavior -BasicAliasAnalysis::getModRefBehavior(Function *F, - std::vector *Info) { - if (isAtomicRMW(F)) - // CAS and related intrinsics only access their arguments. - return AliasAnalysis::AccessesArguments; - - return AliasAnalysis::getModRefBehavior(F, Info); -} - // getModRefInfo - Check to see if the specified callsite can clobber the // specified memory object. Since we only look at local properties of this // function, we really can't say much about this query. We do, however, use Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=64551&r1=64550&r2=64551&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Sat Feb 14 04:56:35 2009 @@ -48,6 +48,9 @@ // Emit the intrinsic parameter attributes. EmitAttributes(Ints, OS); + // Emit intrinsic alias analysis mod/ref behavior. + EmitModRefBehavior(Ints, OS); + // Emit a list of intrinsics with corresponding GCC builtins. EmitGCCBuiltinList(Ints, OS); @@ -481,6 +484,37 @@ OS << "#endif // GET_INTRINSIC_ATTRIBUTES\n\n"; } +/// EmitModRefBehavior - Determine intrinsic alias analysis mod/ref behavior. +void IntrinsicEmitter:: +EmitModRefBehavior(const std::vector &Ints, std::ostream &OS){ + OS << "// Determine intrinsic alias analysis mod/ref behavior.\n"; + OS << "#ifdef GET_INTRINSIC_MODREF_BEHAVIOR\n"; + OS << "switch (id) {\n"; + OS << "default:\n return UnknownModRefBehavior;\n"; + for (unsigned i = 0, e = Ints.size(); i != e; ++i) { + if (Ints[i].ModRef == CodeGenIntrinsic::WriteMem) + continue; + OS << "case " << TargetPrefix << "Intrinsic::" << Ints[i].EnumName + << ":\n"; + switch (Ints[i].ModRef) { + default: + assert(false && "Unknown Mod/Ref type!"); + case CodeGenIntrinsic::NoMem: + OS << " return DoesNotAccessMemory;\n"; + break; + case CodeGenIntrinsic::ReadArgMem: + case CodeGenIntrinsic::ReadMem: + OS << " return OnlyReadsMemory;\n"; + break; + case CodeGenIntrinsic::WriteArgMem: + OS << " return AccessesArguments;\n"; + break; + } + } + OS << "}\n"; + OS << "#endif // GET_INTRINSIC_MODREF_BEHAVIOR\n\n"; +} + void IntrinsicEmitter:: EmitGCCBuiltinList(const std::vector &Ints, std::ostream &OS){ OS << "// Get the GCC builtin that corresponds to an LLVM intrinsic.\n"; Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.h?rev=64551&r1=64550&r2=64551&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/IntrinsicEmitter.h (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.h Sat Feb 14 04:56:35 2009 @@ -42,6 +42,8 @@ std::ostream &OS); void EmitAttributes(const std::vector &Ints, std::ostream &OS); + void EmitModRefBehavior(const std::vector &Ints, + std::ostream &OS); void EmitGCCBuiltinList(const std::vector &Ints, std::ostream &OS); void EmitIntrinsicToGCCBuiltinMap(const std::vector &Ints, From foldr at codedgers.com Sat Feb 14 07:05:44 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Sat, 14 Feb 2009 14:05:44 +0100 Subject: [llvm-commits] [PATCH 1/2] Whitespace fixes. Message-ID: <1234616745-26120-1-git-send-email-foldr@codedgers.com> --- lib/System/Unix/Path.inc | 116 +++++++++++++++++++++++----------------------- 1 files changed, 58 insertions(+), 58 deletions(-) diff --git a/lib/System/Unix/Path.inc b/lib/System/Unix/Path.inc index cdb574f..8efa2e0 100644 --- a/lib/System/Unix/Path.inc +++ b/lib/System/Unix/Path.inc @@ -1,10 +1,10 @@ //===- llvm/System/Unix/Path.cpp - Unix Path Implementation -----*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file implements the Unix specific portion of the Path class. @@ -87,10 +87,10 @@ Path::operator=(const std::string &that) { return *this; } -bool +bool Path::isValid() const { // Check some obvious things - if (path.empty()) + if (path.empty()) return false; else if (path.length() >= MAXPATHLEN) return false; @@ -98,17 +98,17 @@ Path::isValid() const { // Check that the characters are ascii chars size_t len = path.length(); unsigned i = 0; - while (i < len && isascii(path[i])) + while (i < len && isascii(path[i])) ++i; - return i >= len; + return i >= len; } -bool +bool Path::isAbsolute() const { if (path.empty()) return false; return path[0] == '/'; -} +} Path Path::GetRootDirectory() { Path result; @@ -119,12 +119,12 @@ Path::GetRootDirectory() { Path Path::GetTemporaryDirectory(std::string* ErrMsg ) { #if defined(HAVE_MKDTEMP) - // The best way is with mkdtemp but that's not available on many systems, + // The best way is with mkdtemp but that's not available on many systems, // Linux and FreeBSD have it. Others probably won't. char pathname[MAXPATHLEN]; strcpy(pathname,"/tmp/llvm_XXXXXX"); if (0 == mkdtemp(pathname)) { - MakeErrMsg(ErrMsg, + MakeErrMsg(ErrMsg, std::string(pathname) + ": can't create temporary directory"); return Path(); } @@ -137,19 +137,19 @@ Path::GetTemporaryDirectory(std::string* ErrMsg ) { // which is then removed and created as a directory. We prefer this over // mktemp because of mktemp's inherent security and threading risks. We still // have a slight race condition from the time the temporary file is created to - // the time it is re-created as a directoy. + // the time it is re-created as a directoy. char pathname[MAXPATHLEN]; strcpy(pathname, "/tmp/llvm_XXXXXX"); int fd = 0; if (-1 == (fd = mkstemp(pathname))) { - MakeErrMsg(ErrMsg, + MakeErrMsg(ErrMsg, std::string(pathname) + ": can't create temporary directory"); return Path(); } ::close(fd); ::unlink(pathname); // start race condition, ignore errors if (-1 == ::mkdir(pathname, S_IRWXU)) { // end race condition - MakeErrMsg(ErrMsg, + MakeErrMsg(ErrMsg, std::string(pathname) + ": can't create temporary directory"); return Path(); } @@ -167,12 +167,12 @@ Path::GetTemporaryDirectory(std::string* ErrMsg ) { strcpy(pathname, "/tmp/llvm_XXXXXX"); char *TmpName = ::mktemp(pathname); if (TmpName == 0) { - MakeErrMsg(ErrMsg, + MakeErrMsg(ErrMsg, std::string(TmpName) + ": can't create unique directory name"); return Path(); } if (-1 == ::mkdir(TmpName, S_IRWXU)) { - MakeErrMsg(ErrMsg, + MakeErrMsg(ErrMsg, std::string(TmpName) + ": can't create temporary directory"); return Path(); } @@ -184,7 +184,7 @@ Path::GetTemporaryDirectory(std::string* ErrMsg ) { // This is the worst case implementation. tempnam(3) leaks memory unless its // on an SVID2 (or later) system. On BSD 4.3 it leaks. tmpnam(3) has thread // issues. The mktemp(3) function doesn't have enough variability in the - // temporary name generated. So, we provide our own implementation that + // temporary name generated. So, we provide our own implementation that // increments an integer from a random number seeded by the current time. This // should be sufficiently unique that we don't have many collisions between // processes. Generally LLVM processes don't run very long and don't use very @@ -196,7 +196,7 @@ Path::GetTemporaryDirectory(std::string* ErrMsg ) { sprintf(pathname, "/tmp/llvm_%010u", unsigned(num)); } while ( 0 == access(pathname, F_OK ) ); if (-1 == ::mkdir(pathname, S_IRWXU)) { - MakeErrMsg(ErrMsg, + MakeErrMsg(ErrMsg, std::string(pathname) + ": can't create temporary directory"); return Path(); } @@ -207,7 +207,7 @@ Path::GetTemporaryDirectory(std::string* ErrMsg ) { #endif } -void +void Path::GetSystemLibraryPaths(std::vector& Paths) { #ifdef LTDL_SHLIBPATH_VAR char* env_var = getenv(LTDL_SHLIBPATH_VAR); @@ -239,7 +239,7 @@ Path::GetBitcodeLibraryPaths(std::vector& Paths) { GetSystemLibraryPaths(Paths); } -Path +Path Path::GetLLVMDefaultConfigDir() { return Path("/etc/llvm/"); } @@ -262,7 +262,7 @@ Path::GetCurrentDirectory() { assert (false && "Could not query current working directory."); return Path(""); } - + return Path(pathname); } @@ -374,7 +374,7 @@ Path::canExecute() const { return true; } -std::string +std::string Path::getLast() const { // Find the last slash size_t pos = path.rfind('/'); @@ -427,7 +427,7 @@ static bool AddPermissionBits(const Path &File, int bits) { // Get the file's current mode. struct stat buf; - if (0 != stat(File.toString().c_str(), &buf)) + if (0 != stat(File.toString().c_str(), &buf)) return false; // Change the file to have whichever permissions bits from 'bits' // that the umask would not disable. @@ -437,7 +437,7 @@ static bool AddPermissionBits(const Path &File, int bits) { } bool Path::makeReadableOnDisk(std::string* ErrMsg) { - if (!AddPermissionBits(*this, 0444)) + if (!AddPermissionBits(*this, 0444)) return MakeErrMsg(ErrMsg, path + ": can't make file readable"); return false; } @@ -473,13 +473,13 @@ Path::getDirectoryContents(std::set& result, std::string* ErrMsg) const { if (0 != lstat(aPath.path.c_str(), &st)) { if (S_ISLNK(st.st_mode)) continue; // dangling symlink -- ignore - return MakeErrMsg(ErrMsg, + return MakeErrMsg(ErrMsg, aPath.path + ": can't determine file object type"); } result.insert(aPath); } } - + closedir(direntries); return false; } @@ -558,30 +558,30 @@ Path::eraseSuffix() { } static bool createDirectoryHelper(char* beg, char* end, bool create_parents) { - + if (access(beg, F_OK | R_OK | W_OK) == 0) return false; - + if (create_parents) { - + char* c = end; - + for (; c != beg; --c) if (*c == '/') { - + // Recurse to handling the parent directory. - *c = '\0'; + *c = '\0'; bool x = createDirectoryHelper(beg, c, create_parents); *c = '/'; - + // Return if we encountered an error. if (x) return true; - + break; } - } - + } + return mkdir(beg, S_IRWXU | S_IRWXG) != 0; } @@ -593,16 +593,16 @@ Path::createDirectoryOnDisk( bool create_parents, std::string* ErrMsg ) { // Null-terminate the last component size_t lastchar = path.length() - 1 ; - + if (pathname[lastchar] != '/') ++lastchar; - + pathname[lastchar] = 0; - + if (createDirectoryHelper(pathname, pathname+lastchar, create_parents)) - return MakeErrMsg(ErrMsg, + return MakeErrMsg(ErrMsg, std::string(pathname) + ": can't create directory"); - + return false; } @@ -624,7 +624,7 @@ Path::createTemporaryFileOnDisk(bool reuse_current, std::string* ErrMsg) { // create the file int fd = ::open(path.c_str(), O_WRONLY|O_CREAT|O_TRUNC, 0666); - if (fd < 0) + if (fd < 0) return MakeErrMsg(ErrMsg, path + ": can't create temporary file"); ::close(fd); return false; @@ -639,17 +639,17 @@ Path::eraseFromDisk(bool remove_contents, std::string *ErrStr) const { return true; } - // Note: this check catches strange situations. In all cases, LLVM should - // only be involved in the creation and deletion of regular files. This - // check ensures that what we're trying to erase is a regular file. It - // effectively prevents LLVM from erasing things like /dev/null, any block - // special file, or other things that aren't "regular" files. + // Note: this check catches strange situations. In all cases, LLVM should + // only be involved in the creation and deletion of regular files. This + // check ensures that what we're trying to erase is a regular file. It + // effectively prevents LLVM from erasing things like /dev/null, any block + // special file, or other things that aren't "regular" files. if (S_ISREG(buf.st_mode)) { if (unlink(path.c_str()) != 0) return MakeErrMsg(ErrStr, path + ": can't destroy file"); return false; } - + if (!S_ISDIR(buf.st_mode)) { if (ErrStr) *ErrStr = "not a file or directory"; return true; @@ -666,13 +666,13 @@ Path::eraseFromDisk(bool remove_contents, std::string *ErrStr) const { char pathname[MAXPATHLEN]; path.copy(pathname, MAXPATHLEN); size_t lastchar = path.length() - 1; - if (pathname[lastchar] == '/') + if (pathname[lastchar] == '/') pathname[lastchar] = 0; else pathname[lastchar+1] = 0; - + if (rmdir(pathname) != 0) - return MakeErrMsg(ErrStr, + return MakeErrMsg(ErrStr, std::string(pathname) + ": can't erase directory"); return false; } @@ -680,12 +680,12 @@ Path::eraseFromDisk(bool remove_contents, std::string *ErrStr) const { bool Path::renamePathOnDisk(const Path& newName, std::string* ErrMsg) { if (0 != ::rename(path.c_str(), newName.c_str())) - return MakeErrMsg(ErrMsg, std::string("can't rename '") + path + "' as '" + + return MakeErrMsg(ErrMsg, std::string("can't rename '") + path + "' as '" + newName.toString() + "' "); return false; } -bool +bool Path::setStatusInfoOnDisk(const FileStatus &si, std::string *ErrStr) const { struct utimbuf utb; utb.actime = si.modTime.toPosixTime(); @@ -697,13 +697,13 @@ Path::setStatusInfoOnDisk(const FileStatus &si, std::string *ErrStr) const { return false; } -bool +bool sys::CopyFile(const sys::Path &Dest, const sys::Path &Src, std::string* ErrMsg){ int inFile = -1; int outFile = -1; inFile = ::open(Src.c_str(), O_RDONLY); if (inFile == -1) - return MakeErrMsg(ErrMsg, Src.toString() + + return MakeErrMsg(ErrMsg, Src.toString() + ": can't open source file to copy"); outFile = ::open(Dest.c_str(), O_WRONLY|O_CREAT, 0666); @@ -729,7 +729,7 @@ sys::CopyFile(const sys::Path &Dest, const sys::Path &Src, std::string* ErrMsg){ if (errno != EINTR && errno != EAGAIN) { ::close(inFile); ::close(outFile); - return MakeErrMsg(ErrMsg, Dest.toString() + + return MakeErrMsg(ErrMsg, Dest.toString() + ": can't write destination file: "); } } else { @@ -744,12 +744,12 @@ sys::CopyFile(const sys::Path &Dest, const sys::Path &Src, std::string* ErrMsg){ return false; } -bool +bool Path::makeUnique(bool reuse_current, std::string* ErrMsg) { if (reuse_current && !exists()) return false; // File doesn't exist already, just use it! - // Append an XXXXXX pattern to the end of the file for use with mkstemp, + // Append an XXXXXX pattern to the end of the file for use with mkstemp, // mktemp or our own implementation. char *FNBuffer = (char*) alloca(path.size()+8); path.copy(FNBuffer,path.size()); @@ -785,7 +785,7 @@ Path::makeUnique(bool reuse_current, std::string* ErrMsg) { path = FNBuffer; } if (FCounter > 999999) - return MakeErrMsg(ErrMsg, + return MakeErrMsg(ErrMsg, path + ": can't make unique filename: too many files"); #endif return false; -- 1.6.1.2 From foldr at codedgers.com Sat Feb 14 07:05:45 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Sat, 14 Feb 2009 14:05:45 +0100 Subject: [llvm-commits] [PATCH 2/2] Fix warning on gcc 4.3. In-Reply-To: <1234616745-26120-1-git-send-email-foldr@codedgers.com> References: <1234616745-26120-1-git-send-email-foldr@codedgers.com> Message-ID: <1234616745-26120-2-git-send-email-foldr@codedgers.com> "system() declared with attribute warn_unused_result." --- lib/System/Unix/Path.inc | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/lib/System/Unix/Path.inc b/lib/System/Unix/Path.inc index 8efa2e0..a8dcedb 100644 --- a/lib/System/Unix/Path.inc +++ b/lib/System/Unix/Path.inc @@ -658,7 +658,10 @@ Path::eraseFromDisk(bool remove_contents, std::string *ErrStr) const { if (remove_contents) { // Recursively descend the directory to remove its contents. std::string cmd = "/bin/rm -rf " + path; - system(cmd.c_str()); + if (system(cmd.c_str()) != 0) { + MakeErrMsg(ErrStr, path + ": failed to recursively remove directory."); + return true; + } return false; } -- 1.6.1.2 From isanbard at gmail.com Sat Feb 14 07:20:35 2009 From: isanbard at gmail.com (Bill Wendling) Date: Sat, 14 Feb 2009 13:20:35 -0000 Subject: [llvm-commits] [llvm] r64552 [1/2] - in /llvm/branches/Apple/Dib: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ lib/Target/X86/AsmPrinter/ lib/Target/XCore/ utils/TableGen/ Message-ID: <200902141320.n1EDKkVo023871@zion.cs.uiuc.edu> Author: void Date: Sat Feb 14 07:20:23 2009 New Revision: 64552 URL: http://llvm.org/viewvc/llvm-project?rev=64552&view=rev Log: Merged these revisions into Dib: --- Merging (from foreign repository) r63650 into '.': --- Merging (from foreign repository) r63656 into '.': --- Merging (from foreign repository) r63660 into '.': --- Merging (from foreign repository) r63663 into '.': --- Merging (from foreign repository) r63664 into '.': --- Merging (from foreign repository) r63673 into '.': --- Merging (from foreign repository) r63674 into '.': --- Merging (from foreign repository) r63675 into '.': --- Merging (from foreign repository) r63676 into '.': --- Merging (from foreign repository) r63677 into '.': --- Merging (from foreign repository) r63680 into '.': --- Merging (from foreign repository) r63689 into '.': --- Merging (from foreign repository) r63690 into '.': --- Merging (from foreign repository) r63693 into '.': --- Merging (from foreign repository) r63703 into '.': --- Merging (from foreign repository) r63704 into '.': --- Merging (from foreign repository) r63705 into '.': --- Merging (from foreign repository) r63716 into '.': --- Merging (from foreign repository) r63767 into '.': --- Merging (from foreign repository) r63789 into '.': --- Merging (from foreign repository) r63800 into '.': --- Merging (from foreign repository) r63808 into '.': --- Merging (from foreign repository) r63886 into '.': --- Merging (from foreign repository) r63889 into '.': --- Merging (from foreign repository) r63904 into '.': --- Merging (from foreign repository) r63909 into '.': --- Merging (from foreign repository) r63951 into '.': --- Merging (from foreign repository) r63966 into '.': --- Merging (from foreign repository) r63967 into '.': --- Merging (from foreign repository) r63968 into '.': --- Merging (from foreign repository) r63969 into '.': --- Merging (from foreign repository) r63971 into '.': --- Merging (from foreign repository) r63978 into '.': --- Merging (from foreign repository) r63979 into '.': --- Merging (from foreign repository) r63992 into '.': --- Merging (from foreign repository) r63993 into '.': --- Merging (from foreign repository) r63995 into '.': --- Merging (from foreign repository) r63996 into '.': --- Merging (from foreign repository) r64000 into '.': --- Merging (from foreign repository) r64026 into '.': --- Merging (from foreign repository) r64329 into '.': --- Merging (from foreign repository) r64342 into '.': --- Merging (from foreign repository) r64409 into '.': --- Merging (from foreign repository) r64410 into '.': --- Merging (from foreign repository) r64429 into '.': --- Merging (from foreign repository) r64430 into '.': --- Merging (from foreign repository) r64431 into '.': --- Merging (from foreign repository) r64432 into '.': --- Merging (from foreign repository) r64433 into '.': --- Merging (from foreign repository) r64435 into '.': --- Merging (from foreign repository) r64436 into '.': --- Merging (from foreign repository) r64437 into '.': --- Merging (from foreign repository) r64438 into '.': --- Merging (from foreign repository) r64439 into '.': Modified: llvm/branches/Apple/Dib/include/llvm/CodeGen/DebugLoc.h llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineFunction.h llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineInstrBuilder.h llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAG.h llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAGNodes.h llvm/branches/Apple/Dib/include/llvm/Target/TargetLowering.h llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp llvm/branches/Apple/Dib/lib/CodeGen/GCStrategy.cpp llvm/branches/Apple/Dib/lib/CodeGen/MachineFunction.cpp llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/branches/Apple/Dib/lib/Target/ARM/ARMConstantIslandPass.cpp llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.cpp llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.h llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp llvm/branches/Apple/Dib/lib/Target/ARM/ARMLoadStoreOptimizer.cpp llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.cpp llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.h llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelDAGToDAG.cpp llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelLowering.cpp llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.cpp llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaLLRP.cpp llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaRegisterInfo.cpp llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelDAGToDAG.cpp llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.cpp llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.h llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.cpp llvm/branches/Apple/Dib/lib/Target/IA64/IA64Bundling.cpp llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelDAGToDAG.cpp llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelLowering.cpp llvm/branches/Apple/Dib/lib/Target/IA64/IA64InstrInfo.cpp llvm/branches/Apple/Dib/lib/Target/IA64/IA64RegisterInfo.cpp llvm/branches/Apple/Dib/lib/Target/Mips/MipsDelaySlotFiller.cpp llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelDAGToDAG.cpp llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelLowering.cpp llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.cpp llvm/branches/Apple/Dib/lib/Target/Mips/MipsRegisterInfo.cpp llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.cpp llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.h llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16InstrInfo.cpp llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCBranchSelector.cpp llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelDAGToDAG.cpp llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.cpp llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.h llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.cpp llvm/branches/Apple/Dib/lib/Target/Sparc/DelaySlotFiller.cpp llvm/branches/Apple/Dib/lib/Target/Sparc/FPMover.cpp llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelDAGToDAG.cpp llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelLowering.cpp llvm/branches/Apple/Dib/lib/Target/Sparc/SparcInstrInfo.cpp llvm/branches/Apple/Dib/lib/Target/Sparc/SparcRegisterInfo.cpp llvm/branches/Apple/Dib/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp llvm/branches/Apple/Dib/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp llvm/branches/Apple/Dib/lib/Target/X86/X86FloatingPoint.cpp llvm/branches/Apple/Dib/lib/Target/X86/X86FloatingPointRegKill.cpp llvm/branches/Apple/Dib/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.h llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.cpp llvm/branches/Apple/Dib/lib/Target/XCore/XCoreISelDAGToDAG.cpp llvm/branches/Apple/Dib/lib/Target/XCore/XCoreISelLowering.cpp llvm/branches/Apple/Dib/lib/Target/XCore/XCoreInstrInfo.cpp llvm/branches/Apple/Dib/lib/Target/XCore/XCoreRegisterInfo.cpp llvm/branches/Apple/Dib/lib/Target/XCore/XCoreRegisterInfo.h llvm/branches/Apple/Dib/utils/TableGen/DAGISelEmitter.cpp Modified: llvm/branches/Apple/Dib/include/llvm/CodeGen/DebugLoc.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/CodeGen/DebugLoc.h?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/include/llvm/CodeGen/DebugLoc.h (original) +++ llvm/branches/Apple/Dib/include/llvm/CodeGen/DebugLoc.h Sat Feb 14 07:20:23 2009 @@ -40,12 +40,17 @@ static DebugLoc getUnknownLoc() { DebugLoc L; L.Idx = 0; return L; } static DebugLoc get(unsigned idx) { DebugLoc L; L.Idx = idx; return L; } + unsigned getIndex() const { return Idx; } + /// isInvalid - Return true if the DebugLoc is invalid. bool isInvalid() const { return Idx == ~0U; } /// isUnknown - Return true if there is no debug info for the SDNode / /// MachineInstr. bool isUnknown() const { return Idx == 0; } + + bool operator==(const DebugLoc &DL) const { return Idx == DL.Idx; } + bool operator!=(const DebugLoc &DL) const { return !(*this == DL); } }; // Partially specialize DenseMapInfo for DebugLocTyple. Modified: llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineFunction.h?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineFunction.h (original) +++ llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineFunction.h Sat Feb 14 07:20:23 2009 @@ -313,9 +313,12 @@ // /// getOrCreateDebugLocID - Look up the DebugLocTuple index with the given - /// source file, line, and column. If none currently exists, create add a new - /// new DebugLocTuple and insert it into the DebugIdMap. + /// source file, line, and column. If none currently exists, create a new + /// DebugLocTuple, and insert it into the DebugIdMap. unsigned getOrCreateDebugLocID(unsigned Src, unsigned Line, unsigned Col); + + /// getDebugLocTuple - Get the DebugLocTuple for a given DebugLoc object. + DebugLocTuple getDebugLocTuple(DebugLoc DL) const; }; //===--------------------------------------------------------------------===// Modified: llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineInstrBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineInstrBuilder.h?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineInstrBuilder.h (original) +++ llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineInstrBuilder.h Sat Feb 14 07:20:23 2009 @@ -99,11 +99,6 @@ /// itself. /// inline MachineInstrBuilder BuildMI(MachineFunction &MF, - const TargetInstrDesc &TID) { - return MachineInstrBuilder(MF.CreateMachineInstr(TID, - DebugLoc::getUnknownLoc())); -} -inline MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const TargetInstrDesc &TID) { return MachineInstrBuilder(MF.CreateMachineInstr(TID, DL)); @@ -113,13 +108,6 @@ /// destination virtual register. /// inline MachineInstrBuilder BuildMI(MachineFunction &MF, - const TargetInstrDesc &TID, - unsigned DestReg) { - return MachineInstrBuilder(MF.CreateMachineInstr(TID, - DebugLoc::getUnknownLoc())) - .addReg(DestReg, true); -} -inline MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const TargetInstrDesc &TID, unsigned DestReg) { @@ -133,15 +121,6 @@ /// inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, - const TargetInstrDesc &TID, - unsigned DestReg) { - MachineInstr *MI = - BB.getParent()->CreateMachineInstr(TID, DebugLoc::getUnknownLoc()); - BB.insert(I, MI); - return MachineInstrBuilder(MI).addReg(DestReg, true); -} -inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, - MachineBasicBlock::iterator I, DebugLoc DL, const TargetInstrDesc &TID, unsigned DestReg) { @@ -156,14 +135,6 @@ /// inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, - const TargetInstrDesc &TID) { - MachineInstr *MI = - BB.getParent()->CreateMachineInstr(TID, DebugLoc::getUnknownLoc()); - BB.insert(I, MI); - return MachineInstrBuilder(MI); -} -inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, - MachineBasicBlock::iterator I, DebugLoc DL, const TargetInstrDesc &TID) { MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID, DL); @@ -176,10 +147,6 @@ /// destination register. /// inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, - const TargetInstrDesc &TID) { - return BuildMI(*BB, BB->end(), TID); -} -inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, DebugLoc DL, const TargetInstrDesc &TID) { return BuildMI(*BB, BB->end(), DL, TID); @@ -190,11 +157,6 @@ /// operand as a destination virtual register. /// inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, - const TargetInstrDesc &TID, - unsigned DestReg) { - return BuildMI(*BB, BB->end(), TID, DestReg); -} -inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, DebugLoc DL, const TargetInstrDesc &TID, unsigned DestReg) { Modified: llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAG.h?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAG.h Sat Feb 14 07:20:23 2009 @@ -41,7 +41,8 @@ private: mutable SDNode Sentinel; public: - ilist_traits() : Sentinel(ISD::DELETED_NODE, SDVTList()) {} + ilist_traits() : Sentinel(ISD::DELETED_NODE, DebugLoc::getUnknownLoc(), + SDVTList()) {} SDNode *createSentinel() const { return &Sentinel; @@ -306,6 +307,8 @@ int Offset = 0) { return getConstantPool(C, VT, Align, Offset, true); } + // When generating a branch to a BB, we don't in general know enough + // to provide debug info for the BB at that time, so keep this one around. SDValue getBasicBlock(MachineBasicBlock *MBB); SDValue getBasicBlock(MachineBasicBlock *MBB, DebugLoc dl); SDValue getExternalSymbol(const char *Sym, MVT VT); @@ -317,74 +320,76 @@ SDValue getRegister(unsigned Reg, MVT VT); SDValue getDbgStopPoint(SDValue Root, unsigned Line, unsigned Col, Value *CU); - SDValue getLabel(unsigned Opcode, SDValue Root, unsigned LabelID); SDValue getLabel(unsigned Opcode, DebugLoc dl, SDValue Root, unsigned LabelID); - SDValue getCopyToReg(SDValue Chain, unsigned Reg, SDValue N) { - return getNode(ISD::CopyToReg, MVT::Other, Chain, + SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) { + return getNode(ISD::CopyToReg, dl, MVT::Other, Chain, getRegister(Reg, N.getValueType()), N); } // This version of the getCopyToReg method takes an extra operand, which // indicates that there is potentially an incoming flag value (if Flag is not // null) and that there should be a flag result. - SDValue getCopyToReg(SDValue Chain, unsigned Reg, SDValue N, + SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N, SDValue Flag) { const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag); SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag }; - return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.getNode() ? 4 : 3); + return getNode(ISD::CopyToReg, dl, VTs, 2, Ops, Flag.getNode() ? 4 : 3); } // Similar to last getCopyToReg() except parameter Reg is a SDValue - SDValue getCopyToReg(SDValue Chain, SDValue Reg, SDValue N, + SDValue getCopyToReg(SDValue Chain, DebugLoc dl, SDValue Reg, SDValue N, SDValue Flag) { const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag); SDValue Ops[] = { Chain, Reg, N, Flag }; - return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.getNode() ? 4 : 3); + return getNode(ISD::CopyToReg, dl, VTs, 2, Ops, Flag.getNode() ? 4 : 3); } - SDValue getCopyFromReg(SDValue Chain, unsigned Reg, MVT VT) { + SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, MVT VT) { const MVT *VTs = getNodeValueTypes(VT, MVT::Other); SDValue Ops[] = { Chain, getRegister(Reg, VT) }; - return getNode(ISD::CopyFromReg, VTs, 2, Ops, 2); + return getNode(ISD::CopyFromReg, dl, VTs, 2, Ops, 2); } // This version of the getCopyFromReg method takes an extra operand, which // indicates that there is potentially an incoming flag value (if Flag is not // null) and that there should be a flag result. - SDValue getCopyFromReg(SDValue Chain, unsigned Reg, MVT VT, + SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, MVT VT, SDValue Flag) { const MVT *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag); SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag }; - return getNode(ISD::CopyFromReg, VTs, 3, Ops, Flag.getNode() ? 3 : 2); + return getNode(ISD::CopyFromReg, dl, VTs, 3, Ops, Flag.getNode() ? 3 : 2); } SDValue getCondCode(ISD::CondCode Cond); /// Returns the ConvertRndSat Note: Avoid using this node because it may /// disappear in the future and most targets don't support it. - SDValue getConvertRndSat(MVT VT, SDValue Val, SDValue DTy, SDValue STy, + SDValue getConvertRndSat(MVT VT, DebugLoc dl, SDValue Val, SDValue DTy, + SDValue STy, SDValue Rnd, SDValue Sat, ISD::CvtCode Code); /// getZeroExtendInReg - Return the expression required to zero extend the Op /// value assuming it was the smaller SrcTy value. - SDValue getZeroExtendInReg(SDValue Op, MVT SrcTy); SDValue getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT SrcTy); /// getNOT - Create a bitwise NOT operation as (XOR Val, -1). SDValue getNOT(DebugLoc DL, SDValue Val, MVT VT); /// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have - /// a flag result (to ensure it's not CSE'd). + /// a flag result (to ensure it's not CSE'd). CALLSEQ_START does not have a + /// useful DebugLoc. SDValue getCALLSEQ_START(SDValue Chain, SDValue Op) { const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag); SDValue Ops[] = { Chain, Op }; - return getNode(ISD::CALLSEQ_START, VTs, 2, Ops, 2); + return getNode(ISD::CALLSEQ_START, DebugLoc::getUnknownLoc(), + VTs, 2, Ops, 2); } /// getCALLSEQ_END - Return a new CALLSEQ_END node, which always must have a - /// flag result (to ensure it's not CSE'd). + /// flag result (to ensure it's not CSE'd). CALLSEQ_END does not have + /// a useful DebugLoc. SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InFlag) { SDVTList NodeTys = getVTList(MVT::Other, MVT::Flag); @@ -393,98 +398,74 @@ Ops.push_back(Op1); Ops.push_back(Op2); Ops.push_back(InFlag); - return getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], + return getNode(ISD::CALLSEQ_END, DebugLoc::getUnknownLoc(), NodeTys, + &Ops[0], (unsigned)Ops.size() - (InFlag.getNode() == 0 ? 1 : 0)); } + /// getUNDEF - Return an UNDEF node. UNDEF does not have a useful DebugLoc. + SDValue getUNDEF(MVT VT) { + return getNode(ISD::UNDEF, DebugLoc::getUnknownLoc(), VT); + } + + /// getGLOBAL_OFFSET_TABLE - Return a GLOBAL_OFFSET_TABLE node. This does + /// not have a useful DebugLoc. + SDValue getGLOBAL_OFFSET_TABLE(MVT VT) { + return getNode(ISD::GLOBAL_OFFSET_TABLE, DebugLoc::getUnknownLoc(), VT); + } + /// getNode - Gets or creates the specified node. /// - SDValue getNode(unsigned Opcode, MVT VT); SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT); - SDValue getNode(unsigned Opcode, MVT VT, SDValue N); SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N); - SDValue getNode(unsigned Opcode, MVT VT, SDValue N1, SDValue N2); SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N1, SDValue N2); - SDValue getNode(unsigned Opcode, MVT VT, - SDValue N1, SDValue N2, SDValue N3); SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N1, SDValue N2, SDValue N3); - SDValue getNode(unsigned Opcode, MVT VT, - SDValue N1, SDValue N2, SDValue N3, SDValue N4); SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4); - SDValue getNode(unsigned Opcode, MVT VT, - SDValue N1, SDValue N2, SDValue N3, SDValue N4, - SDValue N5); SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5); - SDValue getNode(unsigned Opcode, MVT VT, - const SDUse *Ops, unsigned NumOps); SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, const SDUse *Ops, unsigned NumOps); - SDValue getNode(unsigned Opcode, MVT VT, - const SDValue *Ops, unsigned NumOps); SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, const SDValue *Ops, unsigned NumOps); - SDValue getNode(unsigned Opcode, const std::vector &ResultTys, - const SDValue *Ops, unsigned NumOps); SDValue getNode(unsigned Opcode, DebugLoc DL, const std::vector &ResultTys, const SDValue *Ops, unsigned NumOps); - SDValue getNode(unsigned Opcode, const MVT *VTs, unsigned NumVTs, - const SDValue *Ops, unsigned NumOps); SDValue getNode(unsigned Opcode, DebugLoc DL, const MVT *VTs, unsigned NumVTs, const SDValue *Ops, unsigned NumOps); - SDValue getNode(unsigned Opcode, SDVTList VTs, - const SDValue *Ops, unsigned NumOps); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, const SDValue *Ops, unsigned NumOps); - - SDValue getNode(unsigned Opcode, SDVTList VTs); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs); - SDValue getNode(unsigned Opcode, SDVTList VTs, SDValue N); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N); - SDValue getNode(unsigned Opcode, SDVTList VTs, SDValue N1, SDValue N2); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N1, SDValue N2); - SDValue getNode(unsigned Opcode, SDVTList VTs, - SDValue N1, SDValue N2, SDValue N3); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N1, SDValue N2, SDValue N3); - SDValue getNode(unsigned Opcode, SDVTList VTs, - SDValue N1, SDValue N2, SDValue N3, SDValue N4); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N1, SDValue N2, SDValue N3, SDValue N4); - SDValue getNode(unsigned Opcode, SDVTList VTs, - SDValue N1, SDValue N2, SDValue N3, SDValue N4, - SDValue N5); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5); - SDValue getMemcpy(SDValue Chain, SDValue Dst, SDValue Src, + SDValue getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool AlwaysInline, const Value *DstSV, uint64_t DstSVOff, const Value *SrcSV, uint64_t SrcSVOff); - SDValue getMemmove(SDValue Chain, SDValue Dst, SDValue Src, + SDValue getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, const Value *DstSV, uint64_t DstOSVff, const Value *SrcSV, uint64_t SrcSVOff); - SDValue getMemset(SDValue Chain, SDValue Dst, SDValue Src, + SDValue getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, const Value *DstSV, uint64_t DstSVOff); /// getSetCC - Helper function to make it easier to build SetCC's if you just /// have an ISD::CondCode instead of an SDValue. /// - SDValue getSetCC(MVT VT, SDValue LHS, SDValue RHS, - ISD::CondCode Cond) { - return getNode(ISD::SETCC, DebugLoc::getUnknownLoc(), VT, - LHS, RHS, getCondCode(Cond)); - } SDValue getSetCC(DebugLoc DL, MVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond) { return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond)); @@ -493,11 +474,6 @@ /// getVSetCC - Helper function to make it easier to build VSetCC's nodes /// if you just have an ISD::CondCode instead of an SDValue. /// - SDValue getVSetCC(MVT VT, SDValue LHS, SDValue RHS, - ISD::CondCode Cond) { - return getNode(ISD::VSETCC, DebugLoc::getUnknownLoc(), VT, - LHS, RHS, getCondCode(Cond)); - } SDValue getVSetCC(DebugLoc DL, MVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond) { return getNode(ISD::VSETCC, DL, VT, LHS, RHS, getCondCode(Cond)); @@ -506,11 +482,6 @@ /// getSelectCC - Helper function to make it easier to build SelectCC's if you /// just have an ISD::CondCode instead of an SDValue. /// - SDValue getSelectCC(SDValue LHS, SDValue RHS, - SDValue True, SDValue False, ISD::CondCode Cond) { - return getNode(ISD::SELECT_CC, DebugLoc::getUnknownLoc(), True.getValueType(), - LHS, RHS, True, False, getCondCode(Cond)); - } SDValue getSelectCC(DebugLoc DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond) { return getNode(ISD::SELECT_CC, DL, True.getValueType(), @@ -519,35 +490,23 @@ /// getVAArg - VAArg produces a result and token chain, and takes a pointer /// and a source value as input. - SDValue getVAArg(MVT VT, SDValue Chain, SDValue Ptr, + SDValue getVAArg(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, SDValue SV); /// getAtomic - Gets a node for an atomic op, produces result and chain and /// takes 3 operands - SDValue getAtomic(unsigned Opcode, MVT MemVT, SDValue Chain, SDValue Ptr, - SDValue Cmp, SDValue Swp, const Value* PtrVal, - unsigned Alignment=0); SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, const Value* PtrVal, unsigned Alignment=0); /// getAtomic - Gets a node for an atomic op, produces result and chain and /// takes 2 operands. - SDValue getAtomic(unsigned Opcode, MVT MemVT, SDValue Chain, SDValue Ptr, - SDValue Val, const Value* PtrVal, - unsigned Alignment = 0); SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, const Value* PtrVal, unsigned Alignment = 0); /// getMemIntrinsicNode - Creates a MemIntrinsicNode that may produce a /// result and takes a list of operands. - SDValue getMemIntrinsicNode(unsigned Opcode, - const MVT *VTs, unsigned NumVTs, - const SDValue *Ops, unsigned NumOps, - MVT MemVT, const Value *srcValue, int SVOff, - unsigned Align = 0, bool Vol = false, - bool ReadMem = true, bool WriteMem = true); SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, const MVT *VTs, unsigned NumVTs, const SDValue *Ops, unsigned NumOps, @@ -555,11 +514,6 @@ unsigned Align = 0, bool Vol = false, bool ReadMem = true, bool WriteMem = true); - SDValue getMemIntrinsicNode(unsigned Opcode, SDVTList VTList, - const SDValue *Ops, unsigned NumOps, - MVT MemVT, const Value *srcValue, int SVOff, - unsigned Align = 0, bool Vol = false, - bool ReadMem = true, bool WriteMem = true); SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, const SDValue *Ops, unsigned NumOps, MVT MemVT, const Value *srcValue, int SVOff, @@ -567,14 +521,10 @@ bool ReadMem = true, bool WriteMem = true); /// getMergeValues - Create a MERGE_VALUES node from the given operands. - SDValue getMergeValues(const SDValue *Ops, unsigned NumOps); SDValue getMergeValues(const SDValue *Ops, unsigned NumOps, DebugLoc dl); /// getCall - Create a CALL node from the given information. /// - SDValue getCall(unsigned CallingConv, bool IsVarArgs, bool IsTailCall, - bool isInreg, SDVTList VTs, const SDValue *Operands, - unsigned NumOperands); SDValue getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, bool IsTailCall, bool isInreg, SDVTList VTs, const SDValue *Operands, unsigned NumOperands); @@ -582,29 +532,15 @@ /// getLoad - Loads are not normal binary operators: their result type is not /// determined by their operands, and they produce a value AND a token chain. /// - SDValue getLoad(MVT VT, SDValue Chain, SDValue Ptr, - const Value *SV, int SVOffset, bool isVolatile=false, - unsigned Alignment=0); SDValue getLoad(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, const Value *SV, int SVOffset, bool isVolatile=false, unsigned Alignment=0); - SDValue getExtLoad(ISD::LoadExtType ExtType, MVT VT, - SDValue Chain, SDValue Ptr, const Value *SV, - int SVOffset, MVT EVT, bool isVolatile=false, - unsigned Alignment=0); SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT, SDValue Chain, SDValue Ptr, const Value *SV, int SVOffset, MVT EVT, bool isVolatile=false, unsigned Alignment=0); - SDValue getIndexedLoad(SDValue OrigLoad, SDValue Base, - SDValue Offset, ISD::MemIndexedMode AM); SDValue getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM); - SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, - MVT VT, SDValue Chain, - SDValue Ptr, SDValue Offset, - const Value *SV, int SVOffset, MVT EVT, - bool isVolatile=false, unsigned Alignment=0); SDValue getLoad(ISD::MemIndexedMode AM, DebugLoc dl, ISD::LoadExtType ExtType, MVT VT, SDValue Chain, SDValue Ptr, SDValue Offset, @@ -613,20 +549,12 @@ /// getStore - Helper function to build ISD::STORE nodes. /// - SDValue getStore(SDValue Chain, SDValue Val, SDValue Ptr, - const Value *SV, int SVOffset, bool isVolatile=false, - unsigned Alignment=0); SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr, const Value *SV, int SVOffset, bool isVolatile=false, unsigned Alignment=0); - SDValue getTruncStore(SDValue Chain, SDValue Val, SDValue Ptr, - const Value *SV, int SVOffset, MVT TVT, - bool isVolatile=false, unsigned Alignment=0); SDValue getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr, const Value *SV, int SVOffset, MVT TVT, bool isVolatile=false, unsigned Alignment=0); - SDValue getIndexedStore(SDValue OrigStoe, SDValue Base, - SDValue Offset, ISD::MemIndexedMode AM); SDValue getIndexedStore(SDValue OrigStoe, DebugLoc dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM); @@ -719,70 +647,31 @@ /// Note that getTargetNode returns the resultant node. If there is already a /// node of the specified opcode and operands, it returns that node instead of /// the current one. - SDNode *getTargetNode(unsigned Opcode, MVT VT); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT); - - SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1); - - SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1, SDValue Op2); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1, SDValue Op2); - - SDNode *getTargetNode(unsigned Opcode, MVT VT, - SDValue Op1, SDValue Op2, SDValue Op3); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1, SDValue Op2, SDValue Op3); - - SDNode *getTargetNode(unsigned Opcode, MVT VT, - const SDValue *Ops, unsigned NumOps); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, const SDValue *Ops, unsigned NumOps); - - SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2); - - SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDValue Op1); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, SDValue Op1); - - SDNode *getTargetNode(unsigned Opcode, MVT VT1, - MVT VT2, SDValue Op1, SDValue Op2); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, SDValue Op1, SDValue Op2); - - SDNode *getTargetNode(unsigned Opcode, MVT VT1, - MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3); - - SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, - const SDValue *Ops, unsigned NumOps); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, const SDValue *Ops, unsigned NumOps); - - SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, - SDValue Op1, SDValue Op2); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3, SDValue Op1, SDValue Op2); - - SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, - SDValue Op1, SDValue Op2, SDValue Op3); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3, SDValue Op1, SDValue Op2, SDValue Op3); - - SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, - const SDValue *Ops, unsigned NumOps); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3, const SDValue *Ops, unsigned NumOps); - - SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, MVT VT4, - const SDValue *Ops, unsigned NumOps); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3, MVT VT4, const SDValue *Ops, unsigned NumOps); - - SDNode *getTargetNode(unsigned Opcode, const std::vector &ResultTys, - const SDValue *Ops, unsigned NumOps); SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, const std::vector &ResultTys, const SDValue *Ops, unsigned NumOps); Modified: llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAGNodes.h?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAGNodes.h Sat Feb 14 07:20:23 2009 @@ -1349,33 +1349,6 @@ return Ret; } - /// The constructors that supply DebugLoc explicitly should be preferred - /// for new code. - SDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, unsigned NumOps) - : NodeType(Opc), OperandsNeedDelete(true), SubclassData(0), - NodeId(-1), - OperandList(NumOps ? new SDUse[NumOps] : 0), - ValueList(VTs.VTs), - UseList(NULL), - NumOperands(NumOps), NumValues(VTs.NumVTs), - debugLoc(DebugLoc::getUnknownLoc()) { - for (unsigned i = 0; i != NumOps; ++i) { - OperandList[i].setUser(this); - OperandList[i].setInitial(Ops[i]); - } - } - - /// This constructor adds no operands itself; operands can be - /// set later with InitOperands. - SDNode(unsigned Opc, SDVTList VTs) - : NodeType(Opc), OperandsNeedDelete(false), SubclassData(0), - NodeId(-1), OperandList(0), ValueList(VTs.VTs), UseList(NULL), - NumOperands(0), NumValues(VTs.NumVTs), - debugLoc(DebugLoc::getUnknownLoc()) {} - - /// The next two constructors specify DebugLoc explicitly; the intent - /// is that they will replace the above two over time, and eventually - /// the ones above can be removed. SDNode(unsigned Opc, const DebugLoc dl, SDVTList VTs, const SDValue *Ops, unsigned NumOps) : NodeType(Opc), OperandsNeedDelete(true), SubclassData(0), @@ -1520,10 +1493,6 @@ class UnarySDNode : public SDNode { SDUse Op; public: - UnarySDNode(unsigned Opc, SDVTList VTs, SDValue X) - : SDNode(Opc, VTs) { - InitOperands(&Op, X); - } UnarySDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, SDValue X) : SDNode(Opc, dl, VTs) { InitOperands(&Op, X); @@ -1535,10 +1504,6 @@ class BinarySDNode : public SDNode { SDUse Ops[2]; public: - BinarySDNode(unsigned Opc, SDVTList VTs, SDValue X, SDValue Y) - : SDNode(Opc, VTs) { - InitOperands(Ops, X, Y); - } BinarySDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, SDValue X, SDValue Y) : SDNode(Opc, dl, VTs) { InitOperands(Ops, X, Y); @@ -1550,11 +1515,6 @@ class TernarySDNode : public SDNode { SDUse Ops[3]; public: - TernarySDNode(unsigned Opc, SDVTList VTs, SDValue X, SDValue Y, - SDValue Z) - : SDNode(Opc, VTs) { - InitOperands(Ops, X, Y, Z); - } TernarySDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, SDValue X, SDValue Y, SDValue Z) : SDNode(Opc, dl, VTs) { @@ -1577,7 +1537,8 @@ #else explicit HandleSDNode(SDValue X) #endif - : SDNode(ISD::HANDLENODE, getSDVTList(MVT::Other)) { + : SDNode(ISD::HANDLENODE, DebugLoc::getUnknownLoc(), + getSDVTList(MVT::Other)) { InitOperands(&Op, X); } ~HandleSDNode(); @@ -1597,14 +1558,6 @@ int SVOffset; public: - MemSDNode(unsigned Opc, SDVTList VTs, MVT MemoryVT, - const Value *srcValue, int SVOff, - unsigned alignment, bool isvolatile); - - MemSDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, unsigned NumOps, - MVT MemoryVT, const Value *srcValue, int SVOff, - unsigned alignment, bool isvolatile); - MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT MemoryVT, const Value *srcValue, int SVOff, unsigned alignment, bool isvolatile); @@ -1680,21 +1633,6 @@ // Swp: swap value // SrcVal: address to update as a Value (used for MemOperand) // Align: alignment of memory - AtomicSDNode(unsigned Opc, SDVTList VTL, MVT MemVT, - SDValue Chain, SDValue Ptr, - SDValue Cmp, SDValue Swp, const Value* SrcVal, - unsigned Align=0) - : MemSDNode(Opc, VTL, MemVT, SrcVal, /*SVOffset=*/0, - Align, /*isVolatile=*/true) { - InitOperands(Ops, Chain, Ptr, Cmp, Swp); - } - AtomicSDNode(unsigned Opc, SDVTList VTL, MVT MemVT, - SDValue Chain, SDValue Ptr, - SDValue Val, const Value* SrcVal, unsigned Align=0) - : MemSDNode(Opc, VTL, MemVT, SrcVal, /*SVOffset=*/0, - Align, /*isVolatile=*/true) { - InitOperands(Ops, Chain, Ptr, Val); - } AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, MVT MemVT, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, const Value* SrcVal, @@ -1744,13 +1682,6 @@ bool ReadMem; // Intrinsic reads memory bool WriteMem; // Intrinsic writes memory public: - MemIntrinsicSDNode(unsigned Opc, SDVTList VTs, - const SDValue *Ops, unsigned NumOps, - MVT MemoryVT, const Value *srcValue, int SVO, - unsigned Align, bool Vol, bool ReadMem, bool WriteMem) - : MemSDNode(Opc, VTs, Ops, NumOps, MemoryVT, srcValue, SVO, Align, Vol), - ReadMem(ReadMem), WriteMem(WriteMem) { - } MemIntrinsicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, const SDValue *Ops, unsigned NumOps, MVT MemoryVT, const Value *srcValue, int SVO, @@ -1778,8 +1709,8 @@ protected: friend class SelectionDAG; ConstantSDNode(bool isTarget, const ConstantInt *val, MVT VT) - : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, getSDVTList(VT)), - Value(val) { + : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, + DebugLoc::getUnknownLoc(), getSDVTList(VT)), Value(val) { } public: @@ -1804,7 +1735,7 @@ friend class SelectionDAG; ConstantFPSDNode(bool isTarget, const ConstantFP *val, MVT VT) : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, - getSDVTList(VT)), Value(val) { + DebugLoc::getUnknownLoc(), getSDVTList(VT)), Value(val) { } public: @@ -1866,8 +1797,8 @@ protected: friend class SelectionDAG; FrameIndexSDNode(int fi, MVT VT, bool isTarg) - : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex, getSDVTList(VT)), - FI(fi) { + : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex, + DebugLoc::getUnknownLoc(), getSDVTList(VT)), FI(fi) { } public: @@ -1885,8 +1816,8 @@ protected: friend class SelectionDAG; JumpTableSDNode(int jti, MVT VT, bool isTarg) - : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable, getSDVTList(VT)), - JTI(jti) { + : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable, + DebugLoc::getUnknownLoc(), getSDVTList(VT)), JTI(jti) { } public: @@ -1910,12 +1841,14 @@ friend class SelectionDAG; ConstantPoolSDNode(bool isTarget, Constant *c, MVT VT, int o=0) : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, + DebugLoc::getUnknownLoc(), getSDVTList(VT)), Offset(o), Alignment(0) { assert((int)Offset >= 0 && "Offset is too large"); Val.ConstVal = c; } ConstantPoolSDNode(bool isTarget, Constant *c, MVT VT, int o, unsigned Align) - : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, + : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, + DebugLoc::getUnknownLoc(), getSDVTList(VT)), Offset(o), Alignment(Align) { assert((int)Offset >= 0 && "Offset is too large"); Val.ConstVal = c; @@ -1923,6 +1856,7 @@ ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v, MVT VT, int o=0) : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, + DebugLoc::getUnknownLoc(), getSDVTList(VT)), Offset(o), Alignment(0) { assert((int)Offset >= 0 && "Offset is too large"); Val.MachineCPVal = v; @@ -1931,6 +1865,7 @@ ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v, MVT VT, int o, unsigned Align) : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, + DebugLoc::getUnknownLoc(), getSDVTList(VT)), Offset(o), Alignment(Align) { assert((int)Offset >= 0 && "Offset is too large"); Val.MachineCPVal = v; @@ -1973,11 +1908,12 @@ MachineBasicBlock *MBB; protected: friend class SelectionDAG; + /// Debug info is meaningful and potentially useful here, but we create + /// blocks out of order when they're jumped to, which makes it a bit + /// harder. Let's see if we need it first. explicit BasicBlockSDNode(MachineBasicBlock *mbb) - : SDNode(ISD::BasicBlock, getSDVTList(MVT::Other)), MBB(mbb) { - } - explicit BasicBlockSDNode(MachineBasicBlock *mbb, DebugLoc dl) - : SDNode(ISD::BasicBlock, dl, getSDVTList(MVT::Other)), MBB(mbb) { + : SDNode(ISD::BasicBlock, DebugLoc::getUnknownLoc(), + getSDVTList(MVT::Other)), MBB(mbb) { } public: @@ -2003,7 +1939,8 @@ friend class SelectionDAG; /// Create a SrcValue for a general value. explicit SrcValueSDNode(const Value *v) - : SDNode(ISD::SRCVALUE, getSDVTList(MVT::Other)), V(v) {} + : SDNode(ISD::SRCVALUE, DebugLoc::getUnknownLoc(), + getSDVTList(MVT::Other)), V(v) {} public: /// getValue - return the contained Value. @@ -2025,7 +1962,8 @@ friend class SelectionDAG; /// Create a MachineMemOperand node explicit MemOperandSDNode(const MachineMemOperand &mo) - : SDNode(ISD::MEMOPERAND, getSDVTList(MVT::Other)), MO(mo) {} + : SDNode(ISD::MEMOPERAND, DebugLoc::getUnknownLoc(), + getSDVTList(MVT::Other)), MO(mo) {} public: /// MO - The contained MachineMemOperand. @@ -2043,7 +1981,8 @@ protected: friend class SelectionDAG; RegisterSDNode(unsigned reg, MVT VT) - : SDNode(ISD::Register, getSDVTList(VT)), Reg(reg) { + : SDNode(ISD::Register, DebugLoc::getUnknownLoc(), + getSDVTList(VT)), Reg(reg) { } public: @@ -2064,8 +2003,8 @@ friend class SelectionDAG; DbgStopPointSDNode(SDValue ch, unsigned l, unsigned c, Value *cu) - : SDNode(ISD::DBG_STOPPOINT, getSDVTList(MVT::Other)), - Line(l), Column(c), CU(cu) { + : SDNode(ISD::DBG_STOPPOINT, DebugLoc::getUnknownLoc(), + getSDVTList(MVT::Other)), Line(l), Column(c), CU(cu) { InitOperands(&Chain, ch); } public: @@ -2084,11 +2023,7 @@ unsigned LabelID; protected: friend class SelectionDAG; - LabelSDNode(unsigned NodeTy, SDValue ch, unsigned id) - : SDNode(NodeTy, getSDVTList(MVT::Other)), LabelID(id) { - InitOperands(&Chain, ch); - } - LabelSDNode(unsigned NodeTy, DebugLoc dl, SDValue ch, unsigned id) +LabelSDNode(unsigned NodeTy, DebugLoc dl, SDValue ch, unsigned id) : SDNode(NodeTy, dl, getSDVTList(MVT::Other)), LabelID(id) { InitOperands(&Chain, ch); } @@ -2108,10 +2043,7 @@ friend class SelectionDAG; ExternalSymbolSDNode(bool isTarget, const char *Sym, MVT VT) : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, - getSDVTList(VT)), Symbol(Sym) { - } - ExternalSymbolSDNode(bool isTarget, DebugLoc dl, const char *Sym, MVT VT) - : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, dl, + DebugLoc::getUnknownLoc(), getSDVTList(VT)), Symbol(Sym) { } public: @@ -2130,7 +2062,8 @@ protected: friend class SelectionDAG; explicit CondCodeSDNode(ISD::CondCode Cond) - : SDNode(ISD::CONDCODE, getSDVTList(MVT::Other)), Condition(Cond) { + : SDNode(ISD::CONDCODE, DebugLoc::getUnknownLoc(), + getSDVTList(MVT::Other)), Condition(Cond) { } public: @@ -2148,9 +2081,10 @@ ISD::CvtCode CvtCode; protected: friend class SelectionDAG; - explicit CvtRndSatSDNode(MVT VT, const SDValue *Ops, unsigned NumOps, - ISD::CvtCode Code) - : SDNode(ISD::CONVERT_RNDSAT, getSDVTList(VT), Ops, NumOps), CvtCode(Code) { + explicit CvtRndSatSDNode(MVT VT, DebugLoc dl, const SDValue *Ops, + unsigned NumOps, ISD::CvtCode Code) + : SDNode(ISD::CONVERT_RNDSAT, dl, getSDVTList(VT), Ops, NumOps), + CvtCode(Code) { assert(NumOps == 5 && "wrong number of operations"); } public: @@ -2253,7 +2187,8 @@ protected: friend class SelectionDAG; explicit ARG_FLAGSSDNode(ISD::ArgFlagsTy Flags) - : SDNode(ISD::ARG_FLAGS, getSDVTList(MVT::Other)), TheFlags(Flags) { + : SDNode(ISD::ARG_FLAGS, DebugLoc::getUnknownLoc(), + getSDVTList(MVT::Other)), TheFlags(Flags) { } public: ISD::ArgFlagsTy getArgFlags() const { return TheFlags; } @@ -2275,11 +2210,6 @@ bool Inreg; protected: friend class SelectionDAG; - CallSDNode(unsigned cc, bool isvararg, bool istailcall, bool isinreg, - SDVTList VTs, const SDValue *Operands, unsigned numOperands) - : SDNode(ISD::CALL, VTs, Operands, numOperands), - CallingConv(cc), IsVarArg(isvararg), IsTailCall(istailcall), - Inreg(isinreg) {} CallSDNode(unsigned cc, DebugLoc dl, bool isvararg, bool istailcall, bool isinreg, SDVTList VTs, const SDValue *Operands, unsigned numOperands) @@ -2326,7 +2256,8 @@ protected: friend class SelectionDAG; explicit VTSDNode(MVT VT) - : SDNode(ISD::VALUETYPE, getSDVTList(MVT::Other)), ValueType(VT) { + : SDNode(ISD::VALUETYPE, DebugLoc::getUnknownLoc(), + getSDVTList(MVT::Other)), ValueType(VT) { } public: @@ -2350,17 +2281,6 @@ */ SDUse Ops[4]; public: - LSBaseSDNode(ISD::NodeType NodeTy, SDValue *Operands, unsigned numOperands, - SDVTList VTs, ISD::MemIndexedMode AM, MVT VT, - const Value *SV, int SVO, unsigned Align, bool Vol) - : MemSDNode(NodeTy, VTs, VT, SV, SVO, Align, Vol) { - assert(Align != 0 && "Loads and stores should have non-zero aligment"); - SubclassData |= AM << 2; - assert(getAddressingMode() == AM && "MemIndexedMode encoding error!"); - InitOperands(Ops, Operands, numOperands); - assert((getOffset().getOpcode() == ISD::UNDEF || isIndexed()) && - "Only indexed loads and stores have a non-undef offset operand"); - } LSBaseSDNode(ISD::NodeType NodeTy, DebugLoc dl, SDValue *Operands, unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM, MVT VT, const Value *SV, int SVO, unsigned Align, bool Vol) @@ -2401,14 +2321,6 @@ class LoadSDNode : public LSBaseSDNode { protected: friend class SelectionDAG; - LoadSDNode(SDValue *ChainPtrOff, SDVTList VTs, - ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT LVT, - const Value *SV, int O=0, unsigned Align=0, bool Vol=false) - : LSBaseSDNode(ISD::LOAD, ChainPtrOff, 3, - VTs, AM, LVT, SV, O, Align, Vol) { - SubclassData |= (unsigned short)ETy; - assert(getExtensionType() == ETy && "LoadExtType encoding error!"); - } LoadSDNode(SDValue *ChainPtrOff, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT LVT, const Value *SV, int O=0, unsigned Align=0, bool Vol=false) @@ -2439,14 +2351,6 @@ class StoreSDNode : public LSBaseSDNode { protected: friend class SelectionDAG; - StoreSDNode(SDValue *ChainValuePtrOff, SDVTList VTs, - ISD::MemIndexedMode AM, bool isTrunc, MVT SVT, - const Value *SV, int O=0, unsigned Align=0, bool Vol=false) - : LSBaseSDNode(ISD::STORE, ChainValuePtrOff, 4, - VTs, AM, SVT, SV, O, Align, Vol) { - SubclassData |= (unsigned short)isTrunc; - assert(isTruncatingStore() == isTrunc && "isTrunc encoding error!"); - } StoreSDNode(SDValue *ChainValuePtrOff, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, MVT SVT, const Value *SV, int O=0, unsigned Align=0, bool Vol=false) Modified: llvm/branches/Apple/Dib/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/Target/TargetLowering.h?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/include/llvm/Target/TargetLowering.h (original) +++ llvm/branches/Apple/Dib/include/llvm/Target/TargetLowering.h Sat Feb 14 07:20:23 2009 @@ -1101,7 +1101,7 @@ /// for another call). If the target chooses to decline an AlwaysInline /// request here, legalize will resort to using simple loads and stores. virtual SDValue - EmitTargetCodeForMemcpy(SelectionDAG &DAG, + EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, @@ -1118,7 +1118,7 @@ /// SDValue if the target declines to use custom code and a different /// lowering strategy should be used. virtual SDValue - EmitTargetCodeForMemmove(SelectionDAG &DAG, + EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, @@ -1134,7 +1134,7 @@ /// SDValue if the target declines to use custom code and a different /// lowering strategy should be used. virtual SDValue - EmitTargetCodeForMemset(SelectionDAG &DAG, + EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, Modified: llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Sat Feb 14 07:20:23 2009 @@ -54,9 +54,9 @@ /// Configuration values for initial hash set sizes (log2). /// -static const unsigned InitDiesSetSize = 9; // 512 -static const unsigned InitAbbreviationsSetSize = 9; // 512 -static const unsigned InitValuesSetSize = 9; // 512 +static const unsigned InitDiesSetSize = 9; // log2(512) +static const unsigned InitAbbreviationsSetSize = 9; // log2(512) +static const unsigned InitValuesSetSize = 9; // log2(512) //===----------------------------------------------------------------------===// /// Forward declarations. @@ -855,9 +855,7 @@ /// Dwarf - Emits general Dwarf directives. /// class Dwarf { - protected: - //===--------------------------------------------------------------------===// // Core attributes used by the Dwarf writer. // @@ -918,7 +916,6 @@ } public: - //===--------------------------------------------------------------------===// // Accessors. // @@ -1166,7 +1163,7 @@ unsigned LabelID; // Label in code ID number. public: SrcLineInfo(unsigned L, unsigned C, unsigned S, unsigned I) - : Line(L), Column(C), SourceID(S), LabelID(I) {} + : Line(L), Column(C), SourceID(S), LabelID(I) {} // Accessors unsigned getLine() const { return Line; } @@ -1175,7 +1172,6 @@ unsigned getLabelID() const { return LabelID; } }; - //===----------------------------------------------------------------------===// /// SrcFileInfo - This class is used to track source information. /// @@ -1207,10 +1203,8 @@ /// DbgVariable - This class is used to track local variable information. /// class DbgVariable { -private: DIVariable Var; // Variable Descriptor. unsigned FrameIndex; // Variable frame index. - public: DbgVariable(DIVariable V, unsigned I) : Var(V), FrameIndex(I) {} @@ -1223,7 +1217,6 @@ /// DbgScope - This class is used to track scope information. /// class DbgScope { -private: DbgScope *Parent; // Parent to this scope. DIDescriptor Desc; // Debug info descriptor for scope. // Either subprogram or block. @@ -1231,7 +1224,6 @@ unsigned EndLabelID; // Label ID of the end of scope. SmallVector Scopes; // Scopes defined in scope. SmallVector Variables;// Variables declared in scope. - public: DbgScope(DbgScope *P, DIDescriptor D) : Parent(P), Desc(D), StartLabelID(0), EndLabelID(0), Scopes(), Variables() @@ -1264,8 +1256,6 @@ /// DwarfDebug - Emits Dwarf debug directives. /// class DwarfDebug : public Dwarf { - -private: //===--------------------------------------------------------------------===// // Attributes used to construct specific Dwarf sections. // @@ -1641,7 +1631,7 @@ else if (Ty.isDerivedType(Ty.getTag())) ConstructTypeDIE(DW_Unit, Buffer, DIDerivedType(Ty.getGV())); else { - assert (Ty.isCompositeType(Ty.getTag()) && "Unknown kind of DIType"); + assert(Ty.isCompositeType(Ty.getTag()) && "Unknown kind of DIType"); ConstructTypeDIE(DW_Unit, Buffer, DICompositeType(Ty.getGV())); } @@ -1656,8 +1646,7 @@ Die->AddChild(Child); Buffer.Detach(); SetDIEntry(Slot, Child); - } - else { + } else { Die = DW_Unit->AddDie(Buffer); SetDIEntry(Slot, Die); } @@ -1806,8 +1795,8 @@ } } - // ConstructSubrangeDIE - Construct subrange DIE from DISubrange. - void ConstructSubrangeDIE (DIE &Buffer, DISubrange SR, DIE *IndexTy) { + /// ConstructSubrangeDIE - Construct subrange DIE from DISubrange. + void ConstructSubrangeDIE(DIE &Buffer, DISubrange SR, DIE *IndexTy) { int64_t L = SR.getLo(); int64_t H = SR.getHi(); DIE *DW_Subrange = new DIE(DW_TAG_subrange_type); @@ -1845,8 +1834,7 @@ } } - /// ConstructEnumTypeDIE - Construct enum type DIE from - /// DIEnumerator. + /// ConstructEnumTypeDIE - Construct enum type DIE from DIEnumerator. DIE *ConstructEnumTypeDIE(CompileUnit *DW_Unit, DIEnumerator *ETy) { DIE *Enumerator = new DIE(DW_TAG_enumerator); @@ -1857,7 +1845,7 @@ } /// CreateGlobalVariableDIE - Create new DIE using GV. - DIE *CreateGlobalVariableDIE(CompileUnit *DW_Unit, const DIGlobalVariable &GV) + DIE *CreateGlobalVariableDIE(CompileUnit *DW_Unit, const DIGlobalVariable &GV) { DIE *GVDie = new DIE(DW_TAG_variable); AddString(GVDie, DW_AT_name, DW_FORM_string, GV.getName()); @@ -2101,9 +2089,9 @@ std::string SPName = "llvm.dbg.subprograms"; std::vector Result; getGlobalVariablesUsing(*M, SPName, Result); + for (std::vector::iterator I = Result.begin(), E = Result.end(); I != E; ++I) { - DISubprogram SPD(*I); if (SPD.getName() == MF->getFunction()->getName()) { @@ -2795,7 +2783,7 @@ CompileUnit *Unit = new CompileUnit(ID, Die); if (DIUnit.isMain()) { - assert (!MainCU && "Multiple main compile units are found!"); + assert(!MainCU && "Multiple main compile units are found!"); MainCU = Unit; } DW_CUs[DIUnit.getGV()] = Unit; @@ -2901,41 +2889,40 @@ /// SetDebugInfo - Create global DIEs and emit initial debug info sections. /// This is inovked by the target AsmPrinter. void SetDebugInfo(MachineModuleInfo *mmi) { - - // Create all the compile unit DIEs. - ConstructCompileUnits(); + // Create all the compile unit DIEs. + ConstructCompileUnits(); - if (DW_CUs.empty()) - return; + if (DW_CUs.empty()) + return; - MMI = mmi; - shouldEmit = true; - MMI->setDebugInfoAvailability(true); - - // Create DIEs for each of the externally visible global variables. - ConstructGlobalVariableDIEs(); - - // Create DIEs for each of the externally visible subprograms. - ConstructSubprograms(); - - // Prime section data. - SectionMap.insert(TAI->getTextSection()); - - // Print out .file directives to specify files for .loc directives. These - // are printed out early so that they precede any .loc directives. - if (TAI->hasDotLocAndDotFile()) { - for (unsigned i = 1, e = SrcFiles.size(); i <= e; ++i) { - sys::Path FullPath(Directories[SrcFiles[i].getDirectoryID()]); - bool AppendOk = FullPath.appendComponent(SrcFiles[i].getName()); - assert(AppendOk && "Could not append filename to directory!"); - AppendOk = false; - Asm->EmitFile(i, FullPath.toString()); - Asm->EOL(); - } + MMI = mmi; + shouldEmit = true; + MMI->setDebugInfoAvailability(true); + + // Create DIEs for each of the externally visible global variables. + ConstructGlobalVariableDIEs(); + + // Create DIEs for each of the externally visible subprograms. + ConstructSubprograms(); + + // Prime section data. + SectionMap.insert(TAI->getTextSection()); + + // Print out .file directives to specify files for .loc directives. These + // are printed out early so that they precede any .loc directives. + if (TAI->hasDotLocAndDotFile()) { + for (unsigned i = 1, e = SrcFiles.size(); i <= e; ++i) { + sys::Path FullPath(Directories[SrcFiles[i].getDirectoryID()]); + bool AppendOk = FullPath.appendComponent(SrcFiles[i].getName()); + assert(AppendOk && "Could not append filename to directory!"); + AppendOk = false; + Asm->EmitFile(i, FullPath.toString()); + Asm->EOL(); } + } - // Emit initial sections - EmitInitial(); + // Emit initial sections + EmitInitial(); } /// BeginModule - Emit all Dwarf sections that should come prior to the @@ -3094,13 +3081,13 @@ unsigned Tag = DI.getTag(); switch (Tag) { case DW_TAG_variable: - assert (DIVariable(GV).Verify() && "Invalid DebugInfo value"); + assert(DIVariable(GV).Verify() && "Invalid DebugInfo value"); break; case DW_TAG_compile_unit: - assert (DICompileUnit(GV).Verify() && "Invalid DebugInfo value"); + assert(DICompileUnit(GV).Verify() && "Invalid DebugInfo value"); break; case DW_TAG_subprogram: - assert (DISubprogram(GV).Verify() && "Invalid DebugInfo value"); + assert(DISubprogram(GV).Verify() && "Invalid DebugInfo value"); break; default: break; @@ -3114,7 +3101,7 @@ /// correspondence to the source line list. unsigned RecordSourceLine(Value *V, unsigned Line, unsigned Col) { CompileUnit *Unit = DW_CUs[V]; - assert (Unit && "Unable to find CompileUnit"); + assert(Unit && "Unable to find CompileUnit"); unsigned ID = MMI->NextLabelID(); Lines.push_back(SrcLineInfo(Line, Col, Unit->getID(), ID)); return ID; @@ -3173,7 +3160,7 @@ DIVariable DV(GV); Scope = getOrCreateScope(DV.getContext().getGV()); } - assert (Scope && "Unable to find variable' scope"); + assert(Scope && "Unable to find variable' scope"); DbgVariable *DV = new DbgVariable(DIVariable(GV), FrameIndex); Scope->AddVariable(DV); } @@ -3183,8 +3170,6 @@ /// DwarfException - Emits Dwarf exception handling directives. /// class DwarfException : public Dwarf { - -private: struct FunctionEHFrameInfo { std::string FnName; unsigned Number; Modified: llvm/branches/Apple/Dib/lib/CodeGen/GCStrategy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/GCStrategy.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/GCStrategy.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/GCStrategy.cpp Sat Feb 14 07:20:23 2009 @@ -329,6 +329,7 @@ unsigned MachineCodeAnalysis::InsertLabel(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { unsigned Label = MMI->NextLabelID(); + // N.B. we assume that MI is *not* equal to the "end()" iterator. BuildMI(MBB, MI, MI->getDebugLoc(), TII->get(TargetInstrInfo::GC_LABEL)).addImm(Label); return Label; Modified: llvm/branches/Apple/Dib/lib/CodeGen/MachineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/MachineFunction.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/MachineFunction.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/MachineFunction.cpp Sat Feb 14 07:20:23 2009 @@ -380,11 +380,11 @@ } /// getOrCreateDebugLocID - Look up the DebugLocTuple index with the given -/// source file, line, and column. If none currently exists, create add a new -/// new DebugLocTuple and insert it into the DebugIdMap. +/// source file, line, and column. If none currently exists, create a new +/// DebugLocTuple, and insert it into the DebugIdMap. unsigned MachineFunction::getOrCreateDebugLocID(unsigned Src, unsigned Line, unsigned Col) { - struct DebugLocTuple Tuple(Src, Line, Col); + DebugLocTuple Tuple(Src, Line, Col); DenseMap::iterator II = DebugLocInfo.DebugIdMap.find(Tuple); if (II != DebugLocInfo.DebugIdMap.end()) @@ -396,6 +396,14 @@ return Id; } +/// getDebugLocTuple - Get the DebugLocTuple for a given DebugLoc object. +DebugLocTuple MachineFunction::getDebugLocTuple(DebugLoc DL) const { + unsigned Idx = DL.getIndex(); + assert(Idx < DebugLocInfo.DebugLocations.size() && + "Invalid index into debug locations!"); + return DebugLocInfo.DebugLocations[Idx]; +} + //===----------------------------------------------------------------------===// // MachineFrameInfo implementation //===----------------------------------------------------------------------===// Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Feb 14 07:20:23 2009 @@ -2490,7 +2490,7 @@ return N0; // fold (shl x, c >= size(x)) -> undef if (N1C && N1C->getZExtValue() >= OpSizeInBits) - return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT); + return DAG.getUNDEF(VT); // fold (shl x, 0) -> x if (N1C && N1C->isNullValue()) return N0; @@ -2571,7 +2571,7 @@ return N0; // fold (sra x, (setge c, size(x))) -> undef if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) - return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT); + return DAG.getUNDEF(VT); // fold (sra x, 0) -> x if (N1C && N1C->isNullValue()) return N0; @@ -2679,7 +2679,7 @@ return N0; // fold (srl x, c >= size(x)) -> undef if (N1C && N1C->getZExtValue() >= OpSizeInBits) - return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT); + return DAG.getUNDEF(VT); // fold (srl x, 0) -> x if (N1C && N1C->isNullValue()) return N0; @@ -2704,7 +2704,7 @@ // Shifting in all undef bits? MVT SmallVT = N0.getOperand(0).getValueType(); if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) - return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT); + return DAG.getUNDEF(VT); SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, N0.getOperand(0), N1); @@ -3909,7 +3909,7 @@ } if (EltIsUndef) - Ops.push_back(DAG.getNode(ISD::UNDEF, BV->getDebugLoc(), DstEltVT)); + Ops.push_back(DAG.getUNDEF(DstEltVT)); else Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); } @@ -3929,7 +3929,7 @@ for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { for (unsigned j = 0; j != NumOutputsPerInput; ++j) - Ops.push_back(DAG.getNode(ISD::UNDEF, BV->getDebugLoc(), DstEltVT)); + Ops.push_back(DAG.getUNDEF(DstEltVT)); continue; } @@ -4075,7 +4075,8 @@ if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && N0.getNode()->hasOneUse() && isa(N0.getOperand(1))) return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), - DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); + DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, + N0.getOperand(1), N1)); return SDValue(); } @@ -4809,16 +4810,14 @@ // Indexed loads. assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { - SDValue Undef = DAG.getNode(ISD::UNDEF, N->getDebugLoc(), - N->getValueType(0)); + SDValue Undef = DAG.getUNDEF(N->getValueType(0)); DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); DOUT << " and 2 other values\n"; WorkListRemover DeadNodes(*this); DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), - DAG.getNode(ISD::UNDEF, N->getDebugLoc(), - N->getValueType(1)), + DAG.getUNDEF(N->getValueType(1)), &DeadNodes); DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); removeFromWorkList(N); @@ -5239,9 +5238,7 @@ SmallVector BuildVecIndices; for (unsigned i = 0; i != NumInScalars; ++i) { if (N->getOperand(i).getOpcode() == ISD::UNDEF) { - BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, - N->getDebugLoc(), - TLI.getPointerTy())); + BuildVecIndices.push_back(DAG.getUNDEF(TLI.getPointerTy())); continue; } @@ -5272,8 +5269,7 @@ } else { // Use an undef build_vector as input for the second operand. std::vector UnOps(NumInScalars, - DAG.getNode(ISD::UNDEF, N->getDebugLoc(), - EltType)); + DAG.getUNDEF(EltType)); Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, &UnOps[0], UnOps.size()); AddToWorkList(Ops[1].getNode()); @@ -5429,8 +5425,7 @@ AddToWorkList(ShufMask.getNode()); return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), N->getValueType(0), N0, - DAG.getNode(ISD::UNDEF, N->getDebugLoc(), - N->getValueType(0)), + DAG.getUNDEF(N->getValueType(0)), ShufMask); } Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Feb 14 07:20:23 2009 @@ -345,15 +345,14 @@ SDValue InOp = Mask.getOperand(i); for (unsigned j = 0; j != NumEltsGrowth; ++j) { if (InOp.getOpcode() == ISD::UNDEF) - Ops.push_back(DAG.getNode(ISD::UNDEF, - InOp.getNode()->getDebugLoc(), EltVT)); + Ops.push_back(DAG.getUNDEF(EltVT)); else { unsigned InEltNo = cast(InOp)->getZExtValue(); Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT)); } } } - Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getNode()->getDebugLoc(), + Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getDebugLoc(), NVT, &Ops[0], Ops.size()); } VT = NVT; @@ -556,6 +555,7 @@ static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, SelectionDAG &DAG, const TargetLowering &TLI) { bool Extend = false; + DebugLoc dl = CFP->getDebugLoc(); // If a FP immediate is precise when represented as a float and if the // target can do an extending load from float to double, we put it into @@ -591,10 +591,11 @@ SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); unsigned Alignment = 1 << cast(CPIdx)->getAlignment(); if (Extend) - return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(), + return DAG.getExtLoad(ISD::EXTLOAD, dl, + OrigVT, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, VT, false, Alignment); - return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, + return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, false, Alignment); } @@ -892,7 +893,7 @@ "Can't unroll a vector with multiple results!"); unsigned NE = VT.getVectorNumElements(); MVT EltVT = VT.getVectorElementType(); - DebugLoc dl = Op.getNode()->getDebugLoc(); + DebugLoc dl = Op.getDebugLoc(); SmallVector Scalars; SmallVector Operands(Op.getNumOperands()); @@ -1114,7 +1115,7 @@ default: assert(0 && "This action is not supported yet!"); case TargetLowering::Expand: { unsigned Reg = TLI.getExceptionAddressRegister(); - Result = DAG.getCopyFromReg(Tmp1, Reg, VT); + Result = DAG.getCopyFromReg(Tmp1, dl, Reg, VT); } break; case TargetLowering::Custom: @@ -1148,7 +1149,7 @@ default: assert(0 && "This action is not supported yet!"); case TargetLowering::Expand: { unsigned Reg = TLI.getExceptionSelectorRegister(); - Result = DAG.getCopyFromReg(Tmp2, Reg, VT); + Result = DAG.getCopyFromReg(Tmp2, dl, Reg, VT); } break; case TargetLowering::Custom: @@ -1736,7 +1737,7 @@ for (unsigned i = 0; i != NumElems; ++i) { SDValue Arg = Mask.getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) { - Ops.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT)); + Ops.push_back(DAG.getUNDEF(EltVT)); } else { assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); unsigned Idx = cast(Arg)->getZExtValue(); @@ -1919,7 +1920,7 @@ Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); SDValue Size = Tmp2.getOperand(1); - SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT); + SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); Chain = SP.getValue(1); unsigned Align = cast(Tmp3)->getZExtValue(); unsigned StackAlign = @@ -1928,7 +1929,7 @@ SP = DAG.getNode(ISD::AND, dl, VT, SP, DAG.getConstant(-(uint64_t)Align, VT)); Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value - Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain + Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), DAG.getIntPtrConstant(0, true), SDValue()); @@ -2188,7 +2189,7 @@ Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), LD->getSrcValueOffset(), LD->isVolatile(), LD->getAlignment()); - Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); + Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); Tmp4 = LegalizeOp(Tmp1.getValue(1)); break; } @@ -2890,11 +2891,11 @@ // Expand to CopyFromReg if the target set // StackPointerRegisterToSaveRestore. if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { - Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, + Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), dl, SP, Node->getValueType(0)); Tmp2 = Tmp1.getValue(1); } else { - Tmp1 = DAG.getNode(ISD::UNDEF, dl, Node->getValueType(0)); + Tmp1 = DAG.getUNDEF(Node->getValueType(0)); Tmp2 = Node->getOperand(0); } break; @@ -2922,7 +2923,7 @@ // Expand to CopyToReg if the target set // StackPointerRegisterToSaveRestore. if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { - Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); + Result = DAG.getCopyToReg(Tmp1, dl, SP, Tmp2); } else { Result = Tmp1; } @@ -3428,7 +3429,7 @@ // Select between the nabs and abs value based on the sign bit of // the input. Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, - DAG.getNode(ISD::FNEG, AbsVal.getValueType(), + DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), AbsVal); Result = LegalizeOp(Result); @@ -4037,7 +4038,7 @@ Result = PromoteOp(Node->getOperand(0)); // For FP, make Op1 a i32 - Result = DAG.getConvertRndSat(Op.getValueType(), Result, + Result = DAG.getConvertRndSat(Op.getValueType(), dl, Result, DTyOp, STyOp, RndOp, SatOp, CvtCode); break; } @@ -4530,7 +4531,7 @@ assert(0 && "Do not know how to promote this operator!"); abort(); case ISD::UNDEF: - Result = DAG.getNode(ISD::UNDEF, dl, NVT); + Result = DAG.getUNDEF(NVT); break; case ISD::Constant: if (VT != MVT::i1) @@ -4601,7 +4602,7 @@ CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && "can only promote integers"); - Result = DAG.getConvertRndSat(NVT, Node->getOperand(0), + Result = DAG.getConvertRndSat(NVT, dl, Node->getOperand(0), Node->getOperand(1), Node->getOperand(2), Node->getOperand(3), Node->getOperand(4), CvtCode); @@ -4885,11 +4886,11 @@ Tmp1 = Node->getOperand(0); // Get the chain. Tmp2 = Node->getOperand(1); // Get the pointer. if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { - Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); + Tmp3 = DAG.getVAArg(VT, dl, Tmp1, Tmp2, Node->getOperand(2)); Result = TLI.LowerOperation(Tmp3, DAG); } else { const Value *V = cast(Node->getOperand(2))->getValue(); - SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); + SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0); // Increment the pointer, VAList, to the next vaarg Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, DAG.getConstant(VT.getSizeInBits()/8, @@ -5000,7 +5001,7 @@ // lower to a store then an indexed load. SDValue Vec = Op.getOperand(0); SDValue Idx = Op.getOperand(1); - DebugLoc dl = Op.getNode()->getDebugLoc(); + DebugLoc dl = Op.getDebugLoc(); MVT TVT = Vec.getValueType(); unsigned NumElems = TVT.getVectorNumElements(); @@ -5512,7 +5513,7 @@ if (isOnlyLowElement) { // If the low element is an undef too, then this whole things is an undef. if (Node->getOperand(0).getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, dl, Node->getValueType(0)); + return DAG.getUNDEF(Node->getValueType(0)); // Otherwise, turn this into a scalar_to_vector node. return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, Node->getValueType(0), Node->getOperand(0)); @@ -5562,7 +5563,7 @@ // Return shuffle(LowValVec, undef, <0,0,0,0>) return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Node->getValueType(0), LowValVec, - DAG.getNode(ISD::UNDEF, Node->getValueType(0)), + DAG.getUNDEF(Node->getValueType(0)), SplatMask); } } @@ -5600,7 +5601,7 @@ if (Val2.getOpcode() != ISD::UNDEF) MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT); else - MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, dl, MaskEltVT); + MaskVec[Val2Elts[i]] = DAG.getUNDEF(MaskEltVT); SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], MaskVec.size()); @@ -5986,7 +5987,7 @@ case TargetLowering::Expand: break; // This case is handled below. case TargetLowering::Custom: { - SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy, + SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, dl, DestTy, Source), DAG); if (NV.getNode()) return LegalizeOp(NV); @@ -6374,7 +6375,8 @@ VT.getVectorElementType().getSizeInBits() : len; SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); - Op = DAG.getNode(ISD::ADD, dl, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), + Op = DAG.getNode(ISD::ADD, dl, VT, + DAG.getNode(ISD::AND, dl, VT, Op, Tmp2), DAG.getNode(ISD::AND, dl, VT, DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), Tmp2)); @@ -6397,7 +6399,7 @@ for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); Op = DAG.getNode(ISD::OR, dl, VT, Op, - DAG.getNode(ISD::SRL, VT, Op, Tmp3)); + DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); } Op = DAG.getNOT(dl, Op, VT); return DAG.getNode(ISD::CTPOP, dl, VT, Op); @@ -6480,8 +6482,8 @@ Lo = ExpandEXTRACT_VECTOR_ELT(Op); return ExpandOp(Lo, Lo, Hi); case ISD::UNDEF: - Lo = DAG.getNode(ISD::UNDEF, dl, NVT); - Hi = DAG.getNode(ISD::UNDEF, dl, NVT); + Lo = DAG.getUNDEF(NVT); + Hi = DAG.getUNDEF(NVT); break; case ISD::Constant: { unsigned NVTBits = NVT.getSizeInBits(); @@ -6586,8 +6588,8 @@ case ISD::VAARG: { SDValue Ch = Node->getOperand(0); // Legalize the chain. SDValue Ptr = Node->getOperand(1); // Legalize the pointer. - Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); - Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); + Lo = DAG.getVAArg(NVT, dl, Ch, Ptr, Node->getOperand(2)); + Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, Node->getOperand(2)); // Remember that we legalized the chain. Hi = LegalizeOp(Hi); @@ -6674,7 +6676,7 @@ Hi = DAG.getConstant(0, NVT); } else /* if (ExtType == ISD::EXTLOAD) */ { // The high part is undefined. - Hi = DAG.getNode(ISD::UNDEF, dl, NVT); + Hi = DAG.getUNDEF(NVT); } } break; @@ -6717,7 +6719,7 @@ // The low part is any extension of the input (which degenerates to a copy). Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0)); // The high part is undefined. - Hi = DAG.getNode(ISD::UNDEF, dl, NVT); + Hi = DAG.getUNDEF(NVT); break; case ISD::SIGN_EXTEND: { // The low part is just a sign extension of the input (which degenerates to @@ -6944,7 +6946,7 @@ // If the target wants custom lowering, do so. SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { - SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); + SDValue Op = DAG.getNode(ISD::SRA, dl, VT, Node->getOperand(0), ShiftAmt); Op = TLI.LowerOperation(Op, DAG); if (Op.getNode()) { // Now that the custom expander is done, expand the result, which is @@ -7513,8 +7515,8 @@ #endif assert(0 && "Unhandled operation in SplitVectorOp!"); case ISD::UNDEF: - Lo = DAG.getNode(ISD::UNDEF, dl, NewVT_Lo); - Hi = DAG.getNode(ISD::UNDEF, dl, NewVT_Hi); + Lo = DAG.getUNDEF(NewVT_Lo); + Hi = DAG.getUNDEF(NewVT_Hi); break; case ISD::BUILD_PAIR: Lo = Node->getOperand(0); @@ -7551,7 +7553,7 @@ for (unsigned i = 0; i != NewNumElts_Lo; ++i) { SDValue IdxNode = Mask.getOperand(i); if (IdxNode.getOpcode() == ISD::UNDEF) { - Ops.push_back(DAG.getNode(ISD::UNDEF, dl, NewEltVT)); + Ops.push_back(DAG.getUNDEF(NewEltVT)); continue; } unsigned Idx = cast(IdxNode)->getZExtValue(); @@ -7569,7 +7571,7 @@ for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { SDValue IdxNode = Mask.getOperand(i); if (IdxNode.getOpcode() == ISD::UNDEF) { - Ops.push_back(DAG.getNode(ISD::UNDEF, dl, NewEltVT)); + Ops.push_back(DAG.getUNDEF(NewEltVT)); continue; } unsigned Idx = cast(IdxNode)->getZExtValue(); @@ -7752,9 +7754,9 @@ SDValue RndOp = Node->getOperand(3); SDValue SatOp = Node->getOperand(4); - Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL, + Lo = DAG.getConvertRndSat(NewVT_Lo, dl, L, DTyOpL, STyOpL, RndOp, SatOp, CvtCode); - Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH, + Hi = DAG.getConvertRndSat(NewVT_Hi, dl, H, DTyOpH, STyOpH, RndOp, SatOp, CvtCode); break; } @@ -7770,7 +7772,7 @@ bool isVolatile = LD->isVolatile(); assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); - SDValue Offset = DAG.getNode(ISD::UNDEF, dl, Ptr.getValueType()); + SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); MVT MemNewEltVT = MemoryVT.getVectorElementType(); MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo); @@ -7900,7 +7902,7 @@ break; case ISD::CONVERT_RNDSAT: { SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0)); - Result = DAG.getConvertRndSat(NewVT, Op0, + Result = DAG.getConvertRndSat(NewVT, dl, Op0, DAG.getValueType(NewVT), DAG.getValueType(Op0.getValueType()), Node->getOperand(3), @@ -7927,7 +7929,7 @@ bool isVolatile = LD->isVolatile(); assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); - SDValue Offset = DAG.getNode(ISD::UNDEF, dl, Ptr.getValueType()); + SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); Result = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, NewVT, Ch, Ptr, Offset, SV, SVOffset, @@ -8049,13 +8051,13 @@ assert(0 && "Unexpected operation in WidenVectorOp!"); break; case ISD::UNDEF: - Result = DAG.getNode(ISD::UNDEF, dl, WidenVT); + Result = DAG.getUNDEF(WidenVT); break; case ISD::BUILD_VECTOR: { // Build a vector with undefined for the new nodes SDValueVector NewOps(Node->op_begin(), Node->op_end()); for (unsigned i = NumElts; i < NewNumElts; ++i) { - NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, EVT)); + NewOps.push_back(DAG.getUNDEF(EVT)); } Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size()); @@ -8092,7 +8094,7 @@ } } for (unsigned i = NumElts; i < NewNumElts; ++i) { - NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, PVT)); + NewOps.push_back(DAG.getUNDEF(PVT)); } SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR, dl, @@ -8137,7 +8139,7 @@ "can not widen bit convert that are not multiple of element type"); unsigned NewNumElts = WidenSize / InSize; SmallVector Ops(NewNumElts); - SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT); + SDValue UndefVal = DAG.getUNDEF(InVT); Ops[0] = Tmp1; for (unsigned i = 1; i < NewNumElts; ++i) Ops[i] = UndefVal; @@ -8207,7 +8209,7 @@ SDValue STyOp = DAG.getValueType(SrcOp.getValueType()); ISD::CvtCode CvtCode = cast(Node)->getCvtCode(); - Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp, + Result = DAG.getConvertRndSat(WidenVT, dl, SrcOp, DTyOp, STyOp, RndOp, SatOp, CvtCode); break; } @@ -8266,7 +8268,7 @@ // We could widen on a multiple of the incoming operand if necessary. unsigned NumConcat = NewNumElts / NumElts; assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector"); - SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, VT); + SDValue UndefVal = DAG.getUNDEF(VT); SmallVector MOps; MOps.push_back(Op); for (unsigned i = 1; i != NumConcat; ++i) { @@ -8296,7 +8298,7 @@ } else if (NewNumElts % NumElts == 0) { // Widen the extracted subvector. unsigned NumConcat = NewNumElts / NumElts; - SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, VT); + SDValue UndefVal = DAG.getUNDEF(VT); SmallVector MOps; MOps.push_back(Op); for (unsigned i = 1; i != NumConcat; ++i) { Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Sat Feb 14 07:20:23 2009 @@ -1107,7 +1107,7 @@ MVT::i64, Src); LC = RTLIB::SINTTOFP_I64_PPCF128; } else if (SrcVT.bitsLE(MVT::i128)) { - Src = DAG.getNode(ISD::SIGN_EXTEND, MVT::i128, Src); + Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src); LC = RTLIB::SINTTOFP_I128_PPCF128; } assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!"); Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Sat Feb 14 07:20:23 2009 @@ -150,8 +150,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { SDValue Op2 = GetPromotedInteger(N->getOperand(2)); SDValue Op3 = GetPromotedInteger(N->getOperand(3)); - SDValue Res = DAG.getAtomic(N->getOpcode(), N->getMemoryVT(), - N->getChain(), N->getBasePtr(), + SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), + N->getMemoryVT(), N->getChain(), N->getBasePtr(), Op2, Op3, N->getSrcValue(), N->getAlignment()); // Legalized the chain result - switch anything that used the old chain to // use the new one. @@ -246,10 +246,12 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { MVT VT = N->getValueType(0); + // FIXME there is no actual debug info here + DebugLoc dl = N->getDebugLoc(); // Zero extend things like i1, sign extend everything else. It shouldn't // matter in theory which one we pick, but this tends to give better code? unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; - SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT), + SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(VT), SDValue(N, 0)); assert(isa(Result) && "Didn't constant fold ext?"); return Result; @@ -262,7 +264,7 @@ CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && "can only promote integers"); MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); - return DAG.getConvertRndSat(OutVT, N->getOperand(0), + return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3), N->getOperand(4), CvtCode); } @@ -270,11 +272,12 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { // Zero extend to the promoted type and do the count there. SDValue Op = ZExtPromotedInteger(N->getOperand(0)); + DebugLoc dl = N->getDebugLoc(); MVT OVT = N->getValueType(0); MVT NVT = Op.getValueType(); - Op = DAG.getNode(ISD::CTLZ, NVT, Op); + Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op); // Subtract off the extra leading bits in the bigger type. - return DAG.getNode(ISD::SUB, N->getDebugLoc(), NVT, Op, + return DAG.getNode(ISD::SUB, dl, NVT, Op, DAG.getConstant(NVT.getSizeInBits() - OVT.getSizeInBits(), NVT)); } @@ -389,7 +392,7 @@ return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, DAG.getValueType(N->getOperand(0).getValueType())); if (N->getOpcode() == ISD::ZERO_EXTEND) - return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType()); + return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType()); assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); return Res; } @@ -573,7 +576,7 @@ // Calculate the overflow flag: zero extend the arithmetic result from // the original type. - SDValue Ofl = DAG.getZeroExtendInReg(Res, OVT); + SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT); // Overflowed if and only if this is not equal to Res. Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); @@ -592,8 +595,7 @@ } SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { - return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), - TLI.getTypeToTransformTo(N->getValueType(0))); + return DAG.getUNDEF(TLI.getTypeToTransformTo(N->getValueType(0))); } SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { @@ -608,7 +610,7 @@ SmallVector Parts(NumRegs); for (unsigned i = 0; i < NumRegs; ++i) { - Parts[i] = DAG.getVAArg(RegVT, Chain, Ptr, N->getOperand(2)); + Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2)); Chain = Parts[i].getValue(1); } @@ -823,7 +825,7 @@ CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) && "can only promote integer arguments"); SDValue InOp = GetPromotedInteger(N->getOperand(0)); - return DAG.getConvertRndSat(N->getValueType(0), InOp, + return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp, N->getOperand(1), N->getOperand(2), N->getOperand(3), N->getOperand(4), CvtCode); } @@ -853,10 +855,11 @@ SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { SDValue NewOps[6]; + DebugLoc dl = N->getDebugLoc(); NewOps[0] = N->getOperand(0); for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { SDValue Flag = GetPromotedInteger(N->getOperand(i)); - NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1); + NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1); } return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps, array_lengthof(NewOps)); @@ -941,9 +944,10 @@ } SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { + DebugLoc dl = N->getDebugLoc(); SDValue Op = GetPromotedInteger(N->getOperand(0)); - Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); - return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType()); + Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); + return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType()); } @@ -1108,7 +1112,7 @@ Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(NVTBits-1, ShTy)); } else { - Lo = DAG.getNode(ISD::OR, NVT, + Lo = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Amt, ShTy)), DAG.getNode(ISD::SHL, dl, NVT, InH, @@ -1248,7 +1252,7 @@ Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2); SDValue Cmp = - DAG.getSetCC(TLI.getSetCCResultType(LoOps[0].getValueType()), + DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()), LoOps[0], LoOps[1], ISD::SETULT); SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, DAG.getConstant(1, NVT), @@ -1312,7 +1316,7 @@ if (Op.getValueType().bitsLE(NVT)) { // The low part is any extension of the input (which degenerates to a copy). Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op); - Hi = DAG.getNode(ISD::UNDEF, dl, NVT); // The high part is undefined. + Hi = DAG.getUNDEF(NVT); // The high part is undefined. } else { // For example, extension of an i48 to an i64. The operand type necessarily // promotes to the result type, so will end up being expanded too. @@ -1407,7 +1411,7 @@ // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) GetExpandedInteger(N->getOperand(0), Lo, Hi); MVT NVT = Lo.getValueType(); - Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo), + Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo), DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); Hi = DAG.getConstant(0, NVT); } @@ -1493,7 +1497,7 @@ } else { assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); // The high part is undefined. - Hi = DAG.getNode(ISD::UNDEF, dl, NVT); + Hi = DAG.getUNDEF(NVT); } } else if (TLI.isLittleEndian()) { // Little-endian - low bits are at low addresses. @@ -1905,7 +1909,7 @@ SplitInteger(Res, Lo, Hi); unsigned ExcessBits = Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); - Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits)); + Hi = DAG.getZeroExtendInReg(Hi, dl, MVT::getIntegerVT(ExcessBits)); } } @@ -2203,7 +2207,7 @@ DAG.getConstant(NVT.getSizeInBits() - ExcessBits, TLI.getPointerTy())); Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, - DAG.getNode(ISD::SRL, NVT, Lo, + DAG.getNode(ISD::SRL, dl, NVT, Lo, DAG.getConstant(ExcessBits, TLI.getPointerTy()))); } Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Sat Feb 14 07:20:23 2009 @@ -852,13 +852,13 @@ /// BitConvertToInteger - Convert to an integer of the same size. SDValue DAGTypeLegalizer::BitConvertToInteger(SDValue Op) { unsigned BitWidth = Op.getValueType().getSizeInBits(); - return DAG.getNode(ISD::BIT_CONVERT, Op.getNode()->getDebugLoc(), + return DAG.getNode(ISD::BIT_CONVERT, Op.getDebugLoc(), MVT::getIntegerVT(BitWidth), Op); } SDValue DAGTypeLegalizer::CreateStackStoreLoad(SDValue Op, MVT DestVT) { - DebugLoc dl = Op.getNode()->getDebugLoc(); + DebugLoc dl = Op.getDebugLoc(); // Create the stack frame object. Make sure it is aligned for both // the source and destination types. SDValue StackPtr = DAG.CreateStackTemporary(Op.getValueType(), DestVT); @@ -922,7 +922,7 @@ SDValue DAGTypeLegalizer::GetVectorElementPointer(SDValue VecPtr, MVT EltVT, SDValue Index) { - DebugLoc dl = Index.getNode()->getDebugLoc(); + DebugLoc dl = Index.getDebugLoc(); // Make sure the index type is big enough to compute in. if (Index.getValueType().bitsGT(TLI.getPointerTy())) Index = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Index); @@ -940,8 +940,8 @@ /// JoinIntegers - Build an integer with low bits Lo and high bits Hi. SDValue DAGTypeLegalizer::JoinIntegers(SDValue Lo, SDValue Hi) { // Arbitrarily use dlHi for result DebugLoc - DebugLoc dlHi = Hi.getNode()->getDebugLoc(); - DebugLoc dlLo = Lo.getNode()->getDebugLoc(); + DebugLoc dlHi = Hi.getDebugLoc(); + DebugLoc dlLo = Lo.getDebugLoc(); MVT LVT = Lo.getValueType(); MVT HVT = Hi.getValueType(); MVT NVT = MVT::getIntegerVT(LVT.getSizeInBits() + HVT.getSizeInBits()); @@ -1004,7 +1004,7 @@ /// of the given type. A target boolean is an integer value, not necessarily of /// type i1, the bits of which conform to getBooleanContents. SDValue DAGTypeLegalizer::PromoteTargetBoolean(SDValue Bool, MVT VT) { - DebugLoc dl = Bool.getNode()->getDebugLoc(); + DebugLoc dl = Bool.getDebugLoc(); ISD::NodeType ExtendCode; switch (TLI.getBooleanContents()) { default: @@ -1031,7 +1031,7 @@ void DAGTypeLegalizer::SplitInteger(SDValue Op, MVT LoVT, MVT HiVT, SDValue &Lo, SDValue &Hi) { - DebugLoc dl = Op.getNode()->getDebugLoc(); + DebugLoc dl = Op.getDebugLoc(); assert(LoVT.getSizeInBits() + HiVT.getSizeInBits() == Op.getValueType().getSizeInBits() && "Invalid integer splitting!"); Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Op); Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.h Sat Feb 14 07:20:23 2009 @@ -231,8 +231,9 @@ /// final size. SDValue SExtPromotedInteger(SDValue Op) { MVT OldVT = Op.getValueType(); + DebugLoc dl = Op.getDebugLoc(); Op = GetPromotedInteger(Op); - return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, + return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op, DAG.getValueType(OldVT)); } @@ -240,8 +241,9 @@ /// final size. SDValue ZExtPromotedInteger(SDValue Op) { MVT OldVT = Op.getValueType(); + DebugLoc dl = Op.getDebugLoc(); Op = GetPromotedInteger(Op); - return DAG.getZeroExtendInReg(Op, OldVT); + return DAG.getZeroExtendInReg(Op, dl, OldVT); } // Integer Result Promotion. Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Sat Feb 14 07:20:23 2009 @@ -154,7 +154,7 @@ if (Idx.getValueType().bitsLT(TLI.getPointerTy())) Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); - Idx = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, Idx); + Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, Idx); Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, @@ -209,9 +209,10 @@ MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Chain = N->getOperand(0); SDValue Ptr = N->getOperand(1); + DebugLoc dl = N->getDebugLoc(); - Lo = DAG.getVAArg(NVT, Chain, Ptr, N->getOperand(2)); - Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, N->getOperand(2)); + Lo = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2)); + Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, N->getOperand(2)); // Handle endianness of the load. if (TLI.isBigEndian()) @@ -331,7 +332,7 @@ unsigned NumElts = VT.getVectorNumElements(); SmallVector Ops(NumElts); Ops[0] = N->getOperand(0); - SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, Ops[0].getValueType()); + SDValue UndefVal = DAG.getUNDEF(Ops[0].getValueType()); for (unsigned i = 1; i < NumElts; ++i) Ops[i] = UndefVal; return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); @@ -432,6 +433,6 @@ MVT LoVT, HiVT; DebugLoc dl = N->getDebugLoc(); GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); - Lo = DAG.getNode(ISD::UNDEF, dl, LoVT); - Hi = DAG.getNode(ISD::UNDEF, dl, HiVT); + Lo = DAG.getUNDEF(LoVT); + Hi = DAG.getUNDEF(HiVT); } Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Sat Feb 14 07:20:23 2009 @@ -126,7 +126,8 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) { MVT NewVT = N->getValueType(0).getVectorElementType(); SDValue Op0 = GetScalarizedVector(N->getOperand(0)); - return DAG.getConvertRndSat(NewVT, Op0, DAG.getValueType(NewVT), + return DAG.getConvertRndSat(NewVT, N->getDebugLoc(), + Op0, DAG.getValueType(NewVT), DAG.getValueType(Op0.getValueType()), N->getOperand(3), N->getOperand(4), @@ -163,8 +164,7 @@ N->getExtensionType(), N->getValueType(0).getVectorElementType(), N->getChain(), N->getBasePtr(), - DAG.getNode(ISD::UNDEF, N->getDebugLoc(), - N->getBasePtr().getValueType()), + DAG.getUNDEF(N->getBasePtr().getValueType()), N->getSrcValue(), N->getSrcValueOffset(), N->getMemoryVT().getVectorElementType(), N->isVolatile(), N->getAlignment()); @@ -202,16 +202,14 @@ } SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) { - return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), - N->getValueType(0).getVectorElementType()); + return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); } SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) { // Figure out if the scalar is the LHS or RHS and return it. SDValue Arg = N->getOperand(2).getOperand(0); if (Arg.getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), - N->getValueType(0).getVectorElementType()); + return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); unsigned Op = !cast(Arg)->isNullValue(); return GetScalarizedVector(N->getOperand(Op)); } @@ -533,6 +531,7 @@ void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo, SDValue &Hi) { MVT LoVT, HiVT; + DebugLoc dl = N->getDebugLoc(); GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); SDValue VLo, VHi; GetSplitVector(N->getOperand(0), VLo, VHi); @@ -545,8 +544,10 @@ SDValue SatOp = N->getOperand(4); ISD::CvtCode CvtCode = cast(N)->getCvtCode(); - Lo = DAG.getConvertRndSat(LoVT, VLo, DTyOpLo, STyOpLo, RndOp, SatOp, CvtCode); - Hi = DAG.getConvertRndSat(HiVT, VHi, DTyOpHi, STyOpHi, RndOp, SatOp, CvtCode); + Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp, + CvtCode); + Hi = DAG.getConvertRndSat(HiVT, dl, VHi, DTyOpHi, STyOpHi, RndOp, SatOp, + CvtCode); } void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, @@ -628,7 +629,7 @@ DebugLoc dl = N->getDebugLoc(); GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0)); - Hi = DAG.getNode(ISD::UNDEF, dl, HiVT); + Hi = DAG.getUNDEF(HiVT); } void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, @@ -641,7 +642,7 @@ ISD::LoadExtType ExtType = LD->getExtensionType(); SDValue Ch = LD->getChain(); SDValue Ptr = LD->getBasePtr(); - SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType()); + SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); const Value *SV = LD->getSrcValue(); int SVOffset = LD->getSrcValueOffset(); MVT MemoryVT = LD->getMemoryVT(); @@ -743,7 +744,7 @@ if (Input >= array_lengthof(Inputs)) { // The mask element does not index into any input vector. - Ops.push_back(DAG.getNode(ISD::UNDEF, dl, IdxVT)); + Ops.push_back(DAG.getUNDEF(IdxVT)); continue; } @@ -791,7 +792,7 @@ if (Input >= array_lengthof(Inputs)) { // The mask element is "undef" or indexes off the end of the input. - Ops.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT)); + Ops.push_back(DAG.getUNDEF(EltVT)); continue; } @@ -807,7 +808,7 @@ Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, &Ops[0], Ops.size()); } else if (InputUsed[0] == -1U) { // No input vectors were used! The result is undefined. - Output = DAG.getNode(ISD::UNDEF, dl, NewVT); + Output = DAG.getUNDEF(NewVT); } else { // At least one input vector was used. Create a new shuffle vector. SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, dl, @@ -816,7 +817,7 @@ SDValue Op0 = Inputs[InputUsed[0]]; // If only one input was used, use an undefined vector for the other. SDValue Op1 = InputUsed[1] == -1U ? - DAG.getNode(ISD::UNDEF, dl, NewVT) : Inputs[InputUsed[1]]; + DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]]; Output = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NewVT, Op0, Op1, NewMask); } @@ -1071,7 +1072,7 @@ for (unsigned i = 0; i < MaskLength; ++i) { SDValue Arg = Mask.getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) { - Ops[i] = DAG.getNode(ISD::UNDEF, dl, OpVT); + Ops[i] = DAG.getUNDEF(OpVT); } else { uint64_t Idx = cast(Arg)->getZExtValue(); Ops[i] = DAG.getConstant(Idx, OpVT); @@ -1215,7 +1216,7 @@ unsigned NumConcat = WidenNumElts/InVTNumElts; SmallVector Ops(NumConcat); Ops[0] = InOp; - SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT); + SDValue UndefVal = DAG.getUNDEF(InVT); for (unsigned i = 1; i != NumConcat; ++i) Ops[i] = UndefVal; return DAG.getNode(Opcode, dl, WidenVT, @@ -1241,7 +1242,7 @@ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, DAG.getIntPtrConstant(i))); - SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT); + SDValue UndefVal = DAG.getUNDEF(EltVT); for (; i < WidenNumElts; ++i) Ops[i] = UndefVal; @@ -1333,7 +1334,7 @@ // and then widening it. To avoid this, we widen the input only if // it results in a legal type. SmallVector Ops(NewNumElts); - SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT); + SDValue UndefVal = DAG.getUNDEF(InVT); Ops[0] = InOp; for (unsigned i = 1; i < NewNumElts; ++i) Ops[i] = UndefVal; @@ -1376,7 +1377,7 @@ SmallVector NewOps(N->op_begin(), N->op_end()); NewOps.reserve(WidenNumElts); for (unsigned i = NumElts; i < WidenNumElts; ++i) - NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT)); + NewOps.push_back(DAG.getUNDEF(EltVT)); return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size()); } @@ -1394,7 +1395,7 @@ // Add undef vectors to widen to correct length. unsigned NumConcat = WidenVT.getVectorNumElements() / InVT.getVectorNumElements(); - SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT); + SDValue UndefVal = DAG.getUNDEF(InVT); SmallVector Ops(NumConcat); for (unsigned i=0; i < NumOperands; ++i) Ops[i] = N->getOperand(i); @@ -1447,13 +1448,14 @@ Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, DAG.getIntPtrConstant(j)); } - SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT); + SDValue UndefVal = DAG.getUNDEF(EltVT); for (; Idx < WidenNumElts; ++Idx) Ops[Idx] = UndefVal; return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); } SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) { + DebugLoc dl = N->getDebugLoc(); SDValue InOp = N->getOperand(0); SDValue RndOp = N->getOperand(3); SDValue SatOp = N->getOperand(4); @@ -1475,7 +1477,7 @@ InVT = InOp.getValueType(); InVTNumElts = InVT.getVectorNumElements(); if (InVTNumElts == WidenNumElts) - return DAG.getConvertRndSat(WidenVT, InOp, DTyOp, STyOp, RndOp, + return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, SatOp, CvtCode); } @@ -1490,20 +1492,20 @@ unsigned NumConcat = WidenNumElts/InVTNumElts; SmallVector Ops(NumConcat); Ops[0] = InOp; - SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT); + SDValue UndefVal = DAG.getUNDEF(InVT); for (unsigned i = 1; i != NumConcat; ++i) { Ops[i] = UndefVal; } - InOp = DAG.getNode(ISD::CONCAT_VECTORS, InWidenVT, &Ops[0], NumConcat); - return DAG.getConvertRndSat(WidenVT, InOp, DTyOp, STyOp, RndOp, + InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat); + return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, SatOp, CvtCode); } if (InVTNumElts % WidenNumElts == 0) { // Extract the input and convert the shorten input vector. - InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InWidenVT, InOp, + InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp, DAG.getIntPtrConstant(0)); - return DAG.getConvertRndSat(WidenVT, InOp, DTyOp, STyOp, RndOp, + return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, SatOp, CvtCode); } } @@ -1517,17 +1519,17 @@ unsigned MinElts = std::min(InVTNumElts, WidenNumElts); unsigned i; for (i=0; i < MinElts; ++i) { - SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, InEltVT, InOp, + SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, DAG.getIntPtrConstant(i)); - Ops[i] = DAG.getConvertRndSat(WidenVT, ExtVal, DTyOp, STyOp, RndOp, + Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp, SatOp, CvtCode); } - SDValue UndefVal = DAG.getNode(ISD::UNDEF, EltVT); + SDValue UndefVal = DAG.getUNDEF(EltVT); for (; i < WidenNumElts; ++i) Ops[i] = UndefVal; - return DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &Ops[0], WidenNumElts); + return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); } SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) { @@ -1577,7 +1579,7 @@ } } - SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT); + SDValue UndefVal = DAG.getUNDEF(EltVT); for (; i < WidenNumElts; ++i) Ops[i] = UndefVal; return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); @@ -1633,7 +1635,7 @@ } // Fill the rest with undefs - SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT); + SDValue UndefVal = DAG.getUNDEF(EltVT); for (; i != WidenNumElts; ++i) Ops[i] = UndefVal; @@ -1701,7 +1703,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) { MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); - return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), WidenVT); + return DAG.getUNDEF(WidenVT); } SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(SDNode *N) { @@ -1732,7 +1734,7 @@ } } for (unsigned i = NumElts; i < WidenNumElts; ++i) - MaskOps[i] = DAG.getNode(ISD::UNDEF, dl, IdxVT); + MaskOps[i] = DAG.getUNDEF(IdxVT); SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::getVectorVT(IdxVT, WidenNumElts), &MaskOps[0], WidenNumElts); @@ -2142,7 +2144,7 @@ MVT InVT = InOp.getValueType(); assert(InVT.getVectorElementType() == NVT.getVectorElementType() && "input and widen element type must match"); - DebugLoc dl = InOp.getNode()->getDebugLoc(); + DebugLoc dl = InOp.getDebugLoc(); // Check if InOp already has the right width. if (InVT == NVT) @@ -2153,7 +2155,7 @@ if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) { unsigned NumConcat = WidenNumElts / InNumElts; SmallVector Ops(NumConcat); - SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT); + SDValue UndefVal = DAG.getUNDEF(InVT); Ops[0] = InOp; for (unsigned i = 1; i != NumConcat; ++i) Ops[i] = UndefVal; @@ -2174,7 +2176,7 @@ Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, DAG.getIntPtrConstant(Idx)); - SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT); + SDValue UndefVal = DAG.getUNDEF(EltVT); for ( ; Idx < WidenNumElts; ++Idx) Ops[Idx] = UndefVal; return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts); Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat Feb 14 07:20:23 2009 @@ -786,10 +786,11 @@ return TLI.getTargetData()->getABITypeAlignment(Ty); } +// EntryNode could meaningfully have debug info if we can find it... SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) : TLI(tli), FLI(fli), DW(0), - EntryNode(ISD::EntryToken, getVTList(MVT::Other)), - Root(getEntryNode()) { + EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(), + getVTList(MVT::Other)), Root(getEntryNode()) { AllNodes.push_back(&EntryNode); } @@ -829,14 +830,6 @@ Root = getEntryNode(); } -SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) { - if (Op.getValueType() == VT) return Op; - APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), - VT.getSizeInBits()); - return getNode(ISD::AND, Op.getValueType(), Op, - getConstant(Imm, Op.getValueType())); -} - SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) { if (Op.getValueType() == VT) return Op; APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), @@ -900,7 +893,8 @@ if (VT.isVector()) { SmallVector Ops; Ops.assign(VT.getVectorNumElements(), Result); - Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); + Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), + VT, &Ops[0], Ops.size()); } return Result; } @@ -943,7 +937,9 @@ if (VT.isVector()) { SmallVector Ops; Ops.assign(VT.getVectorNumElements(), Result); - Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); + // FIXME DebugLoc info might be appropriate here + Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), + VT, &Ops[0], Ops.size()); } return Result; } @@ -1068,7 +1064,6 @@ return SDValue(N, 0); } - SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); @@ -1083,20 +1078,6 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB, DebugLoc dl) { - FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); - ID.AddPointer(MBB); - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - SDNode *N = NodeAllocator.Allocate(); - new (N) BasicBlockSDNode(MBB, dl); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); @@ -1134,15 +1115,6 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getExternalSymbol(const char *Sym, DebugLoc dl, MVT VT) { - SDNode *&N = ExternalSymbols[Sym]; - if (N) return SDValue(N, 0); - N = NodeAllocator.Allocate(); - new (N) ExternalSymbolSDNode(false, dl, Sym, VT); - AllNodes.push_back(N); - return SDValue(N, 0); -} - SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { SDNode *&N = TargetExternalSymbols[Sym]; if (N) return SDValue(N, 0); @@ -1152,16 +1124,6 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, DebugLoc dl, - MVT VT) { - SDNode *&N = TargetExternalSymbols[Sym]; - if (N) return SDValue(N, 0); - N = NodeAllocator.Allocate(); - new (N) ExternalSymbolSDNode(true, dl, Sym, VT); - AllNodes.push_back(N); - return SDValue(N, 0); -} - SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { if ((unsigned)Cond >= CondCodeNodes.size()) CondCodeNodes.resize(Cond+1); @@ -1175,7 +1137,8 @@ return SDValue(CondCodeNodes[Cond], 0); } -SDValue SelectionDAG::getConvertRndSat(MVT VT, SDValue Val, SDValue DTy, +SDValue SelectionDAG::getConvertRndSat(MVT VT, + SDValue Val, SDValue DTy, SDValue STy, SDValue Rnd, SDValue Sat, ISD::CvtCode Code) { // If the src and dest types are the same and the conversion is between @@ -1219,23 +1182,6 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getLabel(unsigned Opcode, - SDValue Root, - unsigned LabelID) { - FoldingSetNodeID ID; - SDValue Ops[] = { Root }; - AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); - ID.AddInteger(LabelID); - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - SDNode *N = NodeAllocator.Allocate(); - new (N) LabelSDNode(Opcode, Root, LabelID); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl, SDValue Root, unsigned LabelID) { @@ -1302,7 +1248,7 @@ if (OpTy == ShTy || OpTy.isVector()) return Op; ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; - return getNode(Opcode, ShTy, Op); + return getNode(Opcode, Op.getDebugLoc(), ShTy, Op); } /// CreateStackTemporary - Create a stack temporary, suitable for holding the @@ -1388,29 +1334,29 @@ switch (Cond) { default: break; case ISD::SETEQ: if (R==APFloat::cmpUnordered) - return getNode(ISD::UNDEF, dl, VT); + return getUNDEF(VT); // fall through case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); case ISD::SETNE: if (R==APFloat::cmpUnordered) - return getNode(ISD::UNDEF, dl, VT); + return getUNDEF(VT); // fall through case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || R==APFloat::cmpLessThan, VT); case ISD::SETLT: if (R==APFloat::cmpUnordered) - return getNode(ISD::UNDEF, dl, VT); + return getUNDEF(VT); // fall through case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); case ISD::SETGT: if (R==APFloat::cmpUnordered) - return getNode(ISD::UNDEF, dl, VT); + return getUNDEF(VT); // fall through case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); case ISD::SETLE: if (R==APFloat::cmpUnordered) - return getNode(ISD::UNDEF, dl, VT); + return getUNDEF(VT); // fall through case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || R==APFloat::cmpEqual, VT); case ISD::SETGE: if (R==APFloat::cmpUnordered) - return getNode(ISD::UNDEF, dl, VT); + return getUNDEF(VT); // fall through case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || R==APFloat::cmpEqual, VT); @@ -2155,7 +2101,7 @@ SDValue PermMask = N->getOperand(2); SDValue Idx = PermMask.getOperand(i); if (Idx.getOpcode() == ISD::UNDEF) - return getNode(ISD::UNDEF, dl, VT.getVectorElementType()); + return getUNDEF(VT.getVectorElementType()); unsigned Index = cast(Idx)->getZExtValue(); unsigned NumElems = PermMask.getNumOperands(); SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); @@ -2169,7 +2115,7 @@ } if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) return (Index == 0) ? V.getOperand(0) - : getNode(ISD::UNDEF, dl, VT.getVectorElementType()); + : getUNDEF(VT.getVectorElementType()); if (V.getOpcode() == ISD::BUILD_VECTOR) return V.getOperand(Index); if (V.getOpcode() == ISD::VECTOR_SHUFFLE) @@ -2180,10 +2126,6 @@ /// getNode - Gets or creates the specified node. /// -SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VT); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) { FoldingSetNodeID ID; AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); @@ -2201,10 +2143,6 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, Operand); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue Operand) { // Constant fold unary operations with an integer constant operand. @@ -2303,7 +2241,7 @@ Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); if (Operand.getValueType() == VT) return Operand; // noop conversion. if (Operand.getOpcode() == ISD::UNDEF) - return getNode(ISD::UNDEF, DL, VT); + return getUNDEF(VT); break; case ISD::SIGN_EXTEND: assert(VT.isInteger() && Operand.getValueType().isInteger() && @@ -2361,14 +2299,14 @@ if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0)); if (OpOpcode == ISD::UNDEF) - return getNode(ISD::UNDEF, DL, VT); + return getUNDEF(VT); break; case ISD::SCALAR_TO_VECTOR: assert(VT.isVector() && !Operand.getValueType().isVector() && VT.getVectorElementType() == Operand.getValueType() && "Illegal SCALAR_TO_VECTOR node!"); if (OpOpcode == ISD::UNDEF) - return getNode(ISD::UNDEF, DL, VT); + return getUNDEF(VT); // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && isa(Operand.getOperand(1)) && @@ -2450,11 +2388,6 @@ return SDValue(); } -SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, - SDValue N1, SDValue N2) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N1, SDValue N2) { ConstantSDNode *N1C = dyn_cast(N1.getNode()); @@ -2602,7 +2535,7 @@ case ISD::EXTRACT_VECTOR_ELT: // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. if (N1.getOpcode() == ISD::UNDEF) - return getNode(ISD::UNDEF, DL, VT); + return getUNDEF(VT); // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is // expanding copies of large vectors from registers. @@ -2815,11 +2748,6 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, - SDValue N1, SDValue N2, SDValue N3) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2, N3); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N1, SDValue N2, SDValue N3) { // Perform various simplifications. @@ -2901,12 +2829,6 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, - SDValue N1, SDValue N2, SDValue N3, - SDValue N4) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2, N3, N4); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4) { @@ -2914,12 +2836,6 @@ return getNode(Opcode, DL, VT, Ops, 4); } -SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, - SDValue N1, SDValue N2, SDValue N3, - SDValue N4, SDValue N5) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2, N3, N4, N5); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) { @@ -2929,7 +2845,8 @@ /// getMemsetValue - Vectorized representation of the memset value /// operand. -static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG) { +static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG, + DebugLoc dl) { unsigned NumBits = VT.isVector() ? VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); if (ConstantSDNode *C = dyn_cast(Value)) { @@ -2945,11 +2862,11 @@ } const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); + Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value); unsigned Shift = 8; for (unsigned i = NumBits; i > 8; i >>= 1) { - Value = DAG.getNode(ISD::OR, VT, - DAG.getNode(ISD::SHL, VT, Value, + Value = DAG.getNode(ISD::OR, dl, VT, + DAG.getNode(ISD::SHL, dl, VT, Value, DAG.getConstant(Shift, TLI.getShiftAmountTy())), Value); @@ -2962,7 +2879,7 @@ /// getMemsetStringVal - Similar to getMemsetValue. Except this is only /// used when a memcpy is turned into a memset when the source is a constant /// string ptr. -static SDValue getMemsetStringVal(MVT VT, SelectionDAG &DAG, +static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG, const TargetLowering &TLI, std::string &Str, unsigned Offset) { // Handle vector with all elements zero. @@ -2971,7 +2888,7 @@ return DAG.getConstant(0, VT); unsigned NumElts = VT.getVectorNumElements(); MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; - return DAG.getNode(ISD::BIT_CONVERT, VT, + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); } @@ -2993,7 +2910,7 @@ static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, SelectionDAG &DAG) { MVT VT = Base.getValueType(); - return DAG.getNode(ISD::ADD, Base.getNode()->getDebugLoc(), + return DAG.getNode(ISD::ADD, Base.getDebugLoc(), VT, Base, DAG.getConstant(Offset, VT)); } @@ -3106,7 +3023,7 @@ return true; } -static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, +static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, unsigned Align, bool AlwaysInline, @@ -3143,15 +3060,15 @@ // We also handle store a vector with all zero's. // FIXME: Handle other cases where store of vector immediate is done in // a single instruction. - Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); - Store = DAG.getStore(Chain, Value, + Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff); + Store = DAG.getStore(Chain, dl, Value, getMemBasePlusOffset(Dst, DstOff, DAG), DstSV, DstSVOff + DstOff, false, DstAlign); } else { - Value = DAG.getLoad(VT, Chain, + Value = DAG.getLoad(VT, dl, Chain, getMemBasePlusOffset(Src, SrcOff, DAG), SrcSV, SrcSVOff + SrcOff, false, Align); - Store = DAG.getStore(Chain, Value, + Store = DAG.getStore(Chain, dl, Value, getMemBasePlusOffset(Dst, DstOff, DAG), DstSV, DstSVOff + DstOff, false, DstAlign); } @@ -3160,11 +3077,11 @@ DstOff += VTSize; } - return DAG.getNode(ISD::TokenFactor, MVT::Other, + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &OutChains[0], OutChains.size()); } -static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, +static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, unsigned Align, bool AlwaysInline, @@ -3196,14 +3113,14 @@ unsigned VTSize = VT.getSizeInBits() / 8; SDValue Value, Store; - Value = DAG.getLoad(VT, Chain, + Value = DAG.getLoad(VT, dl, Chain, getMemBasePlusOffset(Src, SrcOff, DAG), SrcSV, SrcSVOff + SrcOff, false, Align); LoadValues.push_back(Value); LoadChains.push_back(Value.getValue(1)); SrcOff += VTSize; } - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LoadChains[0], LoadChains.size()); OutChains.clear(); for (unsigned i = 0; i < NumMemOps; i++) { @@ -3211,18 +3128,18 @@ unsigned VTSize = VT.getSizeInBits() / 8; SDValue Value, Store; - Store = DAG.getStore(Chain, LoadValues[i], + Store = DAG.getStore(Chain, dl, LoadValues[i], getMemBasePlusOffset(Dst, DstOff, DAG), DstSV, DstSVOff + DstOff, false, DstAlign); OutChains.push_back(Store); DstOff += VTSize; } - return DAG.getNode(ISD::TokenFactor, MVT::Other, + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &OutChains[0], OutChains.size()); } -static SDValue getMemsetStores(SelectionDAG &DAG, +static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, unsigned Align, @@ -3245,19 +3162,19 @@ for (unsigned i = 0; i < NumMemOps; i++) { MVT VT = MemOps[i]; unsigned VTSize = VT.getSizeInBits() / 8; - SDValue Value = getMemsetValue(Src, VT, DAG); - SDValue Store = DAG.getStore(Chain, Value, + SDValue Value = getMemsetValue(Src, VT, DAG, dl); + SDValue Store = DAG.getStore(Chain, dl, Value, getMemBasePlusOffset(Dst, DstOff, DAG), DstSV, DstSVOff + DstOff); OutChains.push_back(Store); DstOff += VTSize; } - return DAG.getNode(ISD::TokenFactor, MVT::Other, + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &OutChains[0], OutChains.size()); } -SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst, +SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool AlwaysInline, const Value *DstSV, uint64_t DstSVOff, @@ -3272,7 +3189,7 @@ return Chain; SDValue Result = - getMemcpyLoadsAndStores(*this, Chain, Dst, Src, + getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); if (Result.getNode()) @@ -3282,7 +3199,7 @@ // Then check to see if we should lower the memcpy with target-specific // code. If the target chooses to do this, this is the next best. SDValue Result = - TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align, + TLI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align, AlwaysInline, DstSV, DstSVOff, SrcSV, SrcSVOff); if (Result.getNode()) @@ -3292,7 +3209,7 @@ // use a (potentially long) sequence of loads and stores. if (AlwaysInline) { assert(ConstantSize && "AlwaysInline requires a constant size!"); - return getMemcpyLoadsAndStores(*this, Chain, Dst, Src, + return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), Align, true, DstSV, DstSVOff, SrcSV, SrcSVOff); } @@ -3309,11 +3226,11 @@ TLI.LowerCallTo(Chain, Type::VoidTy, false, false, false, false, CallingConv::C, false, getExternalSymbol("memcpy", TLI.getPointerTy()), - Args, *this, DebugLoc::getUnknownLoc()); + Args, *this, dl); return CallResult.second; } -SDValue SelectionDAG::getMemmove(SDValue Chain, SDValue Dst, +SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, const Value *DstSV, uint64_t DstSVOff, @@ -3328,7 +3245,7 @@ return Chain; SDValue Result = - getMemmoveLoadsAndStores(*this, Chain, Dst, Src, + getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); if (Result.getNode()) @@ -3338,7 +3255,7 @@ // Then check to see if we should lower the memmove with target-specific // code. If the target chooses to do this, this is the next best. SDValue Result = - TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align, + TLI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align, DstSV, DstSVOff, SrcSV, SrcSVOff); if (Result.getNode()) return Result; @@ -3355,11 +3272,11 @@ TLI.LowerCallTo(Chain, Type::VoidTy, false, false, false, false, CallingConv::C, false, getExternalSymbol("memmove", TLI.getPointerTy()), - Args, *this, DebugLoc::getUnknownLoc()); + Args, *this, dl); return CallResult.second; } -SDValue SelectionDAG::getMemset(SDValue Chain, SDValue Dst, +SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, const Value *DstSV, uint64_t DstSVOff) { @@ -3373,7 +3290,7 @@ return Chain; SDValue Result = - getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getZExtValue(), + getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), Align, DstSV, DstSVOff); if (Result.getNode()) return Result; @@ -3382,7 +3299,7 @@ // Then check to see if we should lower the memset with target-specific // code. If the target chooses to do this, this is the next best. SDValue Result = - TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align, + TLI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align, DstSV, DstSVOff); if (Result.getNode()) return Result; @@ -3395,9 +3312,9 @@ Args.push_back(Entry); // Extend or truncate the argument to be an i32 value for the call. if (Src.getValueType().bitsGT(MVT::i32)) - Src = getNode(ISD::TRUNCATE, MVT::i32, Src); + Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src); else - Src = getNode(ISD::ZERO_EXTEND, MVT::i32, Src); + Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; Args.push_back(Entry); Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; @@ -3407,39 +3324,10 @@ TLI.LowerCallTo(Chain, Type::VoidTy, false, false, false, false, CallingConv::C, false, getExternalSymbol("memset", TLI.getPointerTy()), - Args, *this, DebugLoc::getUnknownLoc()); + Args, *this, dl); return CallResult.second; } -SDValue SelectionDAG::getAtomic(unsigned Opcode, MVT MemVT, - SDValue Chain, - SDValue Ptr, SDValue Cmp, - SDValue Swp, const Value* PtrVal, - unsigned Alignment) { - assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op"); - assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); - - MVT VT = Cmp.getValueType(); - - if (Alignment == 0) // Ensure that codegen never sees alignment 0 - Alignment = getMVTAlignment(MemVT); - - SDVTList VTs = getVTList(VT, MVT::Other); - FoldingSetNodeID ID; - ID.AddInteger(MemVT.getRawBits()); - SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; - AddNodeIDNode(ID, Opcode, VTs, Ops, 4); - void* IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - SDNode* N = NodeAllocator.Allocate(); - new (N) AtomicSDNode(Opcode, VTs, MemVT, - Chain, Ptr, Cmp, Swp, PtrVal, Alignment); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain, SDValue Ptr, SDValue Cmp, @@ -3469,45 +3357,6 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getAtomic(unsigned Opcode, MVT MemVT, - SDValue Chain, - SDValue Ptr, SDValue Val, - const Value* PtrVal, - unsigned Alignment) { - assert((Opcode == ISD::ATOMIC_LOAD_ADD || - Opcode == ISD::ATOMIC_LOAD_SUB || - Opcode == ISD::ATOMIC_LOAD_AND || - Opcode == ISD::ATOMIC_LOAD_OR || - Opcode == ISD::ATOMIC_LOAD_XOR || - Opcode == ISD::ATOMIC_LOAD_NAND || - Opcode == ISD::ATOMIC_LOAD_MIN || - Opcode == ISD::ATOMIC_LOAD_MAX || - Opcode == ISD::ATOMIC_LOAD_UMIN || - Opcode == ISD::ATOMIC_LOAD_UMAX || - Opcode == ISD::ATOMIC_SWAP) && - "Invalid Atomic Op"); - - MVT VT = Val.getValueType(); - - if (Alignment == 0) // Ensure that codegen never sees alignment 0 - Alignment = getMVTAlignment(MemVT); - - SDVTList VTs = getVTList(VT, MVT::Other); - FoldingSetNodeID ID; - ID.AddInteger(MemVT.getRawBits()); - SDValue Ops[] = {Chain, Ptr, Val}; - AddNodeIDNode(ID, Opcode, VTs, Ops, 3); - void* IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - SDNode* N = NodeAllocator.Allocate(); - new (N) AtomicSDNode(Opcode, VTs, MemVT, - Chain, Ptr, Val, PtrVal, Alignment); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, @@ -3549,18 +3398,6 @@ /// getMergeValues - Create a MERGE_VALUES node from the given operands. /// Allowed to return something different (and simpler) if Simplify is true. -SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps) { - if (NumOps == 1) - return Ops[0]; - - SmallVector VTs; - VTs.reserve(NumOps); - for (unsigned i = 0; i < NumOps; ++i) - VTs.push_back(Ops[i].getValueType()); - return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps); -} - -/// DebugLoc-aware version. SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, DebugLoc dl) { if (NumOps == 1) @@ -3575,18 +3412,6 @@ } SDValue -SelectionDAG::getMemIntrinsicNode(unsigned Opcode, - const MVT *VTs, unsigned NumVTs, - const SDValue *Ops, unsigned NumOps, - MVT MemVT, const Value *srcValue, int SVOff, - unsigned Align, bool Vol, - bool ReadMem, bool WriteMem) { - return getMemIntrinsicNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps, - MemVT, srcValue, SVOff, Align, Vol, - ReadMem, WriteMem); -} - -SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, const MVT *VTs, unsigned NumVTs, const SDValue *Ops, unsigned NumOps, @@ -3599,34 +3424,6 @@ } SDValue -SelectionDAG::getMemIntrinsicNode(unsigned Opcode, SDVTList VTList, - const SDValue *Ops, unsigned NumOps, - MVT MemVT, const Value *srcValue, int SVOff, - unsigned Align, bool Vol, - bool ReadMem, bool WriteMem) { - // Memoize the node unless it returns a flag. - MemIntrinsicSDNode *N; - if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { - FoldingSetNodeID ID; - AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - - N = NodeAllocator.Allocate(); - new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, - srcValue, SVOff, Align, Vol, ReadMem, WriteMem); - CSEMap.InsertNode(N, IP); - } else { - N = NodeAllocator.Allocate(); - new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, - srcValue, SVOff, Align, Vol, ReadMem, WriteMem); - } - AllNodes.push_back(N); - return SDValue(N, 0); -} - -SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, const SDValue *Ops, unsigned NumOps, MVT MemVT, const Value *srcValue, int SVOff, @@ -3655,31 +3452,6 @@ } SDValue -SelectionDAG::getCall(unsigned CallingConv, bool IsVarArgs, bool IsTailCall, - bool IsInreg, SDVTList VTs, - const SDValue *Operands, unsigned NumOperands) { - // Do not include isTailCall in the folding set profile. - FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); - ID.AddInteger(CallingConv); - ID.AddInteger(IsVarArgs); - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { - // Instead of including isTailCall in the folding set, we just - // set the flag of the existing node. - if (!IsTailCall) - cast(E)->setNotTailCall(); - return SDValue(E, 0); - } - SDNode *N = NodeAllocator.Allocate(); - new (N) CallSDNode(CallingConv, IsVarArgs, IsTailCall, IsInreg, - VTs, Operands, NumOperands); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - -SDValue SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, bool IsTailCall, bool IsInreg, SDVTList VTs, const SDValue *Operands, unsigned NumOperands) { @@ -3705,55 +3477,6 @@ } SDValue -SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, - MVT VT, SDValue Chain, - SDValue Ptr, SDValue Offset, - const Value *SV, int SVOffset, MVT EVT, - bool isVolatile, unsigned Alignment) { - if (Alignment == 0) // Ensure that codegen never sees alignment 0 - Alignment = getMVTAlignment(VT); - - if (VT == EVT) { - ExtType = ISD::NON_EXTLOAD; - } else if (ExtType == ISD::NON_EXTLOAD) { - assert(VT == EVT && "Non-extending load from different memory type!"); - } else { - // Extending load. - if (VT.isVector()) - assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && - "Invalid vector extload!"); - else - assert(EVT.bitsLT(VT) && - "Should only be an extending load, not truncating!"); - assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && - "Cannot sign/zero extend a FP/Vector load!"); - assert(VT.isInteger() == EVT.isInteger() && - "Cannot convert from FP to Int or Int -> FP!"); - } - - bool Indexed = AM != ISD::UNINDEXED; - assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && - "Unindexed load with an offset!"); - - SDVTList VTs = Indexed ? - getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); - SDValue Ops[] = { Chain, Ptr, Offset }; - FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); - ID.AddInteger(EVT.getRawBits()); - ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment)); - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - SDNode *N = NodeAllocator.Allocate(); - new (N) LoadSDNode(Ops, VTs, AM, ExtType, EVT, SV, SVOffset, - Alignment, isVolatile); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - -SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, ISD::LoadExtType ExtType, MVT VT, SDValue Chain, SDValue Ptr, SDValue Offset, @@ -3802,57 +3525,26 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getLoad(MVT VT, - SDValue Chain, SDValue Ptr, - const Value *SV, int SVOffset, - bool isVolatile, unsigned Alignment) { - SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); - return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, - SV, SVOffset, VT, isVolatile, Alignment); -} - SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, const Value *SV, int SVOffset, bool isVolatile, unsigned Alignment) { - SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); + SDValue Undef = getUNDEF(Ptr.getValueType()); return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, SV, SVOffset, VT, isVolatile, Alignment); } -SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT, - SDValue Chain, SDValue Ptr, - const Value *SV, - int SVOffset, MVT EVT, - bool isVolatile, unsigned Alignment) { - SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); - return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef, - SV, SVOffset, EVT, isVolatile, Alignment); -} - SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT, SDValue Chain, SDValue Ptr, const Value *SV, int SVOffset, MVT EVT, bool isVolatile, unsigned Alignment) { - SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); + SDValue Undef = getUNDEF(Ptr.getValueType()); return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef, SV, SVOffset, EVT, isVolatile, Alignment); } SDValue -SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base, - SDValue Offset, ISD::MemIndexedMode AM) { - LoadSDNode *LD = cast(OrigLoad); - assert(LD->getOffset().getOpcode() == ISD::UNDEF && - "Load is already a indexed load!"); - return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), - LD->getChain(), Base, Offset, LD->getSrcValue(), - LD->getSrcValueOffset(), LD->getMemoryVT(), - LD->isVolatile(), LD->getAlignment()); -} - -SDValue SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) { LoadSDNode *LD = cast(OrigLoad); @@ -3864,33 +3556,6 @@ LD->isVolatile(), LD->getAlignment()); } -SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val, - SDValue Ptr, const Value *SV, int SVOffset, - bool isVolatile, unsigned Alignment) { - MVT VT = Val.getValueType(); - - if (Alignment == 0) // Ensure that codegen never sees alignment 0 - Alignment = getMVTAlignment(VT); - - SDVTList VTs = getVTList(MVT::Other); - SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); - SDValue Ops[] = { Chain, Val, Ptr, Undef }; - FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); - ID.AddInteger(VT.getRawBits()); - ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, - isVolatile, Alignment)); - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - SDNode *N = NodeAllocator.Allocate(); - new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, false, - VT, SV, SVOffset, Alignment, isVolatile); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr, const Value *SV, int SVOffset, bool isVolatile, unsigned Alignment) { @@ -3900,7 +3565,7 @@ Alignment = getMVTAlignment(VT); SDVTList VTs = getVTList(MVT::Other); - SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); + SDValue Undef = getUNDEF(Ptr.getValueType()); SDValue Ops[] = { Chain, Val, Ptr, Undef }; FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); @@ -3918,41 +3583,6 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val, - SDValue Ptr, const Value *SV, - int SVOffset, MVT SVT, - bool isVolatile, unsigned Alignment) { - MVT VT = Val.getValueType(); - - if (VT == SVT) - return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment); - - assert(VT.bitsGT(SVT) && "Not a truncation?"); - assert(VT.isInteger() == SVT.isInteger() && - "Can't do FP-INT conversion!"); - - if (Alignment == 0) // Ensure that codegen never sees alignment 0 - Alignment = getMVTAlignment(VT); - - SDVTList VTs = getVTList(MVT::Other); - SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); - SDValue Ops[] = { Chain, Val, Ptr, Undef }; - FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); - ID.AddInteger(SVT.getRawBits()); - ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, - isVolatile, Alignment)); - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - SDNode *N = NodeAllocator.Allocate(); - new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, true, - SVT, SV, SVOffset, Alignment, isVolatile); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr, const Value *SV, int SVOffset, MVT SVT, @@ -3970,7 +3600,7 @@ Alignment = getMVTAlignment(VT); SDVTList VTs = getVTList(MVT::Other); - SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); + SDValue Undef = getUNDEF(Ptr.getValueType()); SDValue Ops[] = { Chain, Val, Ptr, Undef }; FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); @@ -3989,31 +3619,6 @@ } SDValue -SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base, - SDValue Offset, ISD::MemIndexedMode AM) { - StoreSDNode *ST = cast(OrigStore); - assert(ST->getOffset().getOpcode() == ISD::UNDEF && - "Store is already a indexed store!"); - SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); - SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; - FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); - ID.AddInteger(ST->getMemoryVT().getRawBits()); - ID.AddInteger(ST->getRawSubclassData()); - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - SDNode *N = NodeAllocator.Allocate(); - new (N) StoreSDNode(Ops, VTs, AM, - ST->isTruncatingStore(), ST->getMemoryVT(), - ST->getSrcValue(), ST->getSrcValueOffset(), - ST->getAlignment(), ST->isVolatile()); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - -SDValue SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) { StoreSDNode *ST = cast(OrigStore); @@ -4038,16 +3643,11 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getVAArg(MVT VT, +SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, SDValue SV) { SDValue Ops[] = { Chain, Ptr, SV }; - return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3); -} - -SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, - const SDUse *Ops, unsigned NumOps) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, Ops, NumOps); + return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3); } SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, @@ -4066,11 +3666,6 @@ return getNode(Opcode, DL, VT, &NewOps[0], NumOps); } -SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, - const SDValue *Ops, unsigned NumOps) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, Ops, NumOps); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, const SDValue *Ops, unsigned NumOps) { switch (NumOps) { @@ -4128,12 +3723,6 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getNode(unsigned Opcode, - const std::vector &ResultTys, - const SDValue *Ops, unsigned NumOps) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), ResultTys, Ops, NumOps); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, const std::vector &ResultTys, const SDValue *Ops, unsigned NumOps) { @@ -4141,12 +3730,6 @@ Ops, NumOps); } -SDValue SelectionDAG::getNode(unsigned Opcode, - const MVT *VTs, unsigned NumVTs, - const SDValue *Ops, unsigned NumOps) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VTs, NumVTs, Ops, NumOps); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, const MVT *VTs, unsigned NumVTs, const SDValue *Ops, unsigned NumOps) { @@ -4155,11 +3738,6 @@ return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps); } -SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, - const SDValue *Ops, unsigned NumOps) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, Ops, NumOps); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, const SDValue *Ops, unsigned NumOps) { if (VTList.NumVTs == 1) @@ -4232,53 +3810,28 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) { return getNode(Opcode, DL, VTList, 0, 0); } -SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, - SDValue N1) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1) { SDValue Ops[] = { N1 }; return getNode(Opcode, DL, VTList, Ops, 1); } -SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, - SDValue N1, SDValue N2) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2) { SDValue Ops[] = { N1, N2 }; return getNode(Opcode, DL, VTList, Ops, 2); } -SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, - SDValue N1, SDValue N2, SDValue N3) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2, N3); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3) { SDValue Ops[] = { N1, N2, N3 }; return getNode(Opcode, DL, VTList, Ops, 3); } -SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, - SDValue N1, SDValue N2, SDValue N3, - SDValue N4) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2, N3, N4); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4) { @@ -4286,12 +3839,6 @@ return getNode(Opcode, DL, VTList, Ops, 4); } -SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, - SDValue N1, SDValue N2, SDValue N3, - SDValue N4, SDValue N5) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2, N3, N4, N5); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) { @@ -4704,7 +4251,7 @@ /// /// Note that MorphNodeTo returns the resultant node. If there is already a /// node of the specified opcode and operands, it returns that node instead of -/// the current one. +/// the current one. Note that the DebugLoc need not be the same. /// /// Using MorphNodeTo is faster than creating a new node and swapping it in /// with ReplaceAllUsesWith both because it often avoids allocating a new @@ -4788,55 +4335,31 @@ /// Note that getTargetNode returns the resultant node. If there is already a /// node of the specified opcode and operands, it returns that node instead of /// the current one. -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) { - return getNode(~Opcode, VT).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) { return getNode(~Opcode, dl, VT).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) { - return getNode(~Opcode, VT, Op1).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1) { return getNode(~Opcode, dl, VT, Op1).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, - SDValue Op1, SDValue Op2) { - return getNode(~Opcode, VT, Op1, Op2).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1, SDValue Op2) { return getNode(~Opcode, dl, VT, Op1, Op2).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, - SDValue Op1, SDValue Op2, - SDValue Op3) { - return getNode(~Opcode, VT, Op1, Op2, Op3).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1, SDValue Op2, SDValue Op3) { return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, - const SDValue *Ops, unsigned NumOps) { - return getNode(~Opcode, VT, Ops, NumOps).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, const SDValue *Ops, unsigned NumOps) { return getNode(~Opcode, dl, VT, Ops, NumOps).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) { - const MVT *VTs = getNodeValueTypes(VT1, VT2); - SDValue Op; - return getNode(~Opcode, VTs, 2, &Op, 0).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2) { const MVT *VTs = getNodeValueTypes(VT1, VT2); @@ -4844,24 +4367,12 @@ return getNode(~Opcode, dl, VTs, 2, &Op, 0).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, - MVT VT2, SDValue Op1) { - const MVT *VTs = getNodeValueTypes(VT1, VT2); - return getNode(~Opcode, VTs, 2, &Op1, 1).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, SDValue Op1) { const MVT *VTs = getNodeValueTypes(VT1, VT2); return getNode(~Opcode, dl, VTs, 2, &Op1, 1).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, - MVT VT2, SDValue Op1, - SDValue Op2) { - const MVT *VTs = getNodeValueTypes(VT1, VT2); - SDValue Ops[] = { Op1, Op2 }; - return getNode(~Opcode, VTs, 2, Ops, 2).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, SDValue Op1, SDValue Op2) { @@ -4870,13 +4381,6 @@ return getNode(~Opcode, dl, VTs, 2, Ops, 2).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, - MVT VT2, SDValue Op1, - SDValue Op2, SDValue Op3) { - const MVT *VTs = getNodeValueTypes(VT1, VT2); - SDValue Ops[] = { Op1, Op2, Op3 }; - return getNode(~Opcode, VTs, 2, Ops, 3).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) { @@ -4885,11 +4389,6 @@ return getNode(~Opcode, dl, VTs, 2, Ops, 3).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, - const SDValue *Ops, unsigned NumOps) { - const MVT *VTs = getNodeValueTypes(VT1, VT2); - return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, const SDValue *Ops, unsigned NumOps) { @@ -4897,12 +4396,6 @@ return getNode(~Opcode, dl, VTs, 2, Ops, NumOps).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, - SDValue Op1, SDValue Op2) { - const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); - SDValue Ops[] = { Op1, Op2 }; - return getNode(~Opcode, VTs, 3, Ops, 2).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3, SDValue Op1, SDValue Op2) { @@ -4911,13 +4404,6 @@ return getNode(~Opcode, dl, VTs, 3, Ops, 2).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, - SDValue Op1, SDValue Op2, - SDValue Op3) { - const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); - SDValue Ops[] = { Op1, Op2, Op3 }; - return getNode(~Opcode, VTs, 3, Ops, 3).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3, SDValue Op1, SDValue Op2, @@ -4927,11 +4413,6 @@ return getNode(~Opcode, dl, VTs, 3, Ops, 3).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, - const SDValue *Ops, unsigned NumOps) { - const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); - return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3, const SDValue *Ops, unsigned NumOps) { @@ -4939,17 +4420,6 @@ return getNode(~Opcode, dl, VTs, 3, Ops, NumOps).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, - MVT VT2, MVT VT3, MVT VT4, - const SDValue *Ops, unsigned NumOps) { - std::vector VTList; - VTList.push_back(VT1); - VTList.push_back(VT2); - VTList.push_back(VT3); - VTList.push_back(VT4); - const MVT *VTs = getNodeValueTypes(VTList); - return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3, MVT VT4, const SDValue *Ops, unsigned NumOps) { @@ -4962,13 +4432,6 @@ return getNode(~Opcode, dl, VTs, 4, Ops, NumOps).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, - const std::vector &ResultTys, - const SDValue *Ops, unsigned NumOps) { - const MVT *VTs = getNodeValueTypes(ResultTys); - return getNode(~Opcode, VTs, ResultTys.size(), - Ops, NumOps).getNode(); -} SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, const std::vector &ResultTys, const SDValue *Ops, unsigned NumOps) { @@ -5333,31 +4796,10 @@ (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : // Non Thread Local (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), - getSDVTList(VT)), Offset(o) { + DebugLoc::getUnknownLoc(), getSDVTList(VT)), Offset(o) { TheGlobal = const_cast(GA); } -MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, MVT memvt, - const Value *srcValue, int SVO, - unsigned alignment, bool vol) - : SDNode(Opc, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { - SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); - assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); - assert(getAlignment() == alignment && "Alignment representation error!"); - assert(isVolatile() == vol && "Volatile representation error!"); -} - -MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, - unsigned NumOps, MVT memvt, const Value *srcValue, - int SVO, unsigned alignment, bool vol) - : SDNode(Opc, VTs, Ops, NumOps), - MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { - SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); - assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); - assert(getAlignment() == alignment && "Alignment representation error!"); - assert(isVolatile() == vol && "Volatile representation error!"); -} - MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt, const Value *srcValue, int SVO, unsigned alignment, bool vol) Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Sat Feb 14 07:20:23 2009 @@ -757,6 +757,7 @@ PendingLoads.clear(); PendingExports.clear(); DAG.clear(); + CurDebugLoc = DebugLoc::getUnknownLoc(); } /// getRoot - Return the current virtual root of the Selection DAG, @@ -866,7 +867,7 @@ if (isa(C) && !isa(V->getType()) && !V->getType()->isAggregateType()) - return N = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT); + return N = DAG.getUNDEF(VT); if (ConstantExpr *CE = dyn_cast(C)) { visit(CE->getOpcode(), *CE); @@ -883,7 +884,8 @@ for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) Constants.push_back(SDValue(Val, i)); } - return DAG.getMergeValues(&Constants[0], Constants.size()); + return DAG.getMergeValues(&Constants[0], Constants.size(), + getCurDebugLoc()); } if (isa(C->getType()) || isa(C->getType())) { @@ -899,13 +901,13 @@ for (unsigned i = 0; i != NumElts; ++i) { MVT EltVT = ValueVTs[i]; if (isa(C)) - Constants[i] = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT); + Constants[i] = DAG.getUNDEF(EltVT); else if (EltVT.isFloatingPoint()) Constants[i] = DAG.getConstantFP(0, EltVT); else Constants[i] = DAG.getConstant(0, EltVT); } - return DAG.getMergeValues(&Constants[0], NumElts); + return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc()); } const VectorType *VecTy = cast(V->getType()); @@ -924,7 +926,7 @@ SDValue Op; if (isa(C)) - Op = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT); + Op = DAG.getUNDEF(EltVT); else if (EltVT.isFloatingPoint()) Op = DAG.getConstantFP(0, EltVT); else @@ -1319,6 +1321,7 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { SDValue Cond; SDValue CondLHS = getValue(CB.CmpLHS); + DebugLoc dl = getCurDebugLoc(); // Build the setcc now. if (CB.CmpMHS == NULL) { @@ -1328,10 +1331,9 @@ Cond = CondLHS; else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { SDValue True = DAG.getConstant(1, CondLHS.getValueType()); - Cond = DAG.getNode(ISD::XOR, getCurDebugLoc(), - CondLHS.getValueType(), CondLHS, True); + Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); } else - Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); + Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); } else { assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); @@ -1342,11 +1344,12 @@ MVT VT = CmpOp.getValueType(); if (cast(CB.CmpLHS)->isMinValue(true)) { - Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); + Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), + ISD::SETLE); } else { - SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), + SDValue SUB = DAG.getNode(ISD::SUB, dl, VT, CmpOp, DAG.getConstant(Low, VT)); - Cond = DAG.getSetCC(MVT::i1, SUB, + Cond = DAG.getSetCC(dl, MVT::i1, SUB, DAG.getConstant(High-Low, VT), ISD::SETULE); } } @@ -1367,10 +1370,9 @@ if (CB.TrueBB == NextBlock) { std::swap(CB.TrueBB, CB.FalseBB); SDValue True = DAG.getConstant(1, Cond.getValueType()); - Cond = DAG.getNode(ISD::XOR, getCurDebugLoc(), - Cond.getValueType(), Cond, True); + Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); } - SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), + SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, MVT::Other, getControlRoot(), Cond, DAG.getBasicBlock(CB.TrueBB)); @@ -1386,7 +1388,7 @@ if (CB.FalseBB == NextBlock) DAG.setRoot(BrCond); else - DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, + DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, DAG.getBasicBlock(CB.FalseBB))); } } @@ -1396,7 +1398,8 @@ // Emit the code for the jump table assert(JT.Reg != -1U && "Should lower JT Header first!"); MVT PTy = TLI.getPointerTy(); - SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy); + SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), + JT.Reg, PTy); SDValue Table = DAG.getJumpTable(JT.JTI, PTy); DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(), MVT::Other, Index.getValue(1), @@ -1428,13 +1431,15 @@ TLI.getPointerTy(), SUB); unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); - SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp); + SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), + JumpTableReg, SwitchOp); JT.Reg = JumpTableReg; // Emit the range check for the jump table, and branch to the default block // for the switch statement if the value being switched on exceeds the largest // case in the switch. - SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB.getValueType()), SUB, + SDValue CMP = DAG.getSetCC(getCurDebugLoc(), + TLI.getSetCCResultType(SUB.getValueType()), SUB, DAG.getConstant(JTH.Last-JTH.First,VT), ISD::SETUGT); @@ -1466,8 +1471,9 @@ DAG.getConstant(B.First, VT)); // Check range - SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB.getValueType()), SUB, - DAG.getConstant(B.Range, VT), + SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), + TLI.getSetCCResultType(SUB.getValueType()), + SUB, DAG.getConstant(B.Range, VT), ISD::SETUGT); SDValue ShiftOp; @@ -1479,7 +1485,8 @@ TLI.getPointerTy(), SUB); B.Reg = FuncInfo.MakeReg(TLI.getPointerTy()); - SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), B.Reg, ShiftOp); + SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), + B.Reg, ShiftOp); // Set NextBlock to be the MBB immediately after the current one, if any. // This is used to avoid emitting unnecessary branches to the next block. @@ -1509,7 +1516,7 @@ unsigned Reg, BitTestCase &B) { // Make desired shift - SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), Reg, + SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg, TLI.getPointerTy()); SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), TLI.getPointerTy(), @@ -1520,7 +1527,8 @@ SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), TLI.getPointerTy(), SwitchVal, DAG.getConstant(B.Mask, TLI.getPointerTy())); - SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp.getValueType()), + SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(), + TLI.getSetCCResultType(AndOp.getValueType()), AndOp, DAG.getConstant(0, TLI.getPointerTy()), ISD::SETNE); @@ -2189,7 +2197,7 @@ SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); ISD::CondCode Opcode = getICmpCondCode(predicate); - setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); + setValue(&I, DAG.getSetCC(getCurDebugLoc(),MVT::i1, Op1, Op2, Opcode)); } void SelectionDAGLowering::visitFCmp(User &I) { @@ -2201,7 +2209,7 @@ SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); ISD::CondCode Condition = getFCmpCondCode(predicate); - setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); + setValue(&I, DAG.getSetCC(getCurDebugLoc(), MVT::i1, Op1, Op2, Condition)); } void SelectionDAGLowering::visitVICmp(User &I) { @@ -2213,7 +2221,8 @@ SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); ISD::CondCode Opcode = getICmpCondCode(predicate); - setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode)); + setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(), + Op1, Op2, Opcode)); } void SelectionDAGLowering::visitVFCmp(User &I) { @@ -2227,7 +2236,7 @@ ISD::CondCode Condition = getFCmpCondCode(predicate); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition)); + setValue(&I, DAG.getVSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); } void SelectionDAGLowering::visitSelect(User &I) { @@ -2429,7 +2438,7 @@ // Pad both vectors with undefs to make them the same length as the mask. unsigned NumConcat = MaskNumElts / SrcNumElts; - SDValue UndefVal = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), SrcVT); + SDValue UndefVal = DAG.getUNDEF(SrcVT); SDValue* MOps1 = new SDValue[NumConcat]; SDValue* MOps2 = new SDValue[NumConcat]; @@ -2531,8 +2540,7 @@ } if (RangeUse[0] == 0 && RangeUse[0] == 0) { - setValue(&I, DAG.getNode(ISD::UNDEF, - getCurDebugLoc(), VT)); // Vectors are not used. + setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. return; } else if (RangeUse[0] < 2 && RangeUse[1] < 2) { @@ -2540,7 +2548,7 @@ for (int Input=0; Input < 2; ++Input) { SDValue& Src = Input == 0 ? Src1 : Src2; if (RangeUse[Input] == 0) { - Src = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT); + Src = DAG.getUNDEF(VT); } else { Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, Src, DAG.getIntPtrConstant(StartIdx[Input])); @@ -2580,7 +2588,7 @@ for (int i = 0; i != MaskNumElts; ++i) { SDValue Arg = Mask.getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) { - Ops.push_back(DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT)); + Ops.push_back(DAG.getUNDEF(EltVT)); } else { assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); int Idx = cast(Arg)->getZExtValue(); @@ -2622,18 +2630,15 @@ unsigned i = 0; // Copy the beginning value(s) from the original aggregate. for (; i != LinearIndex; ++i) - Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(), - AggValueVTs[i]) : + Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : SDValue(Agg.getNode(), Agg.getResNo() + i); // Copy values from the inserted value(s). for (; i != LinearIndex + NumValValues; ++i) - Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(), - AggValueVTs[i]) : + Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); // Copy remaining value(s) from the original aggregate. for (; i != NumAggValues; ++i) - Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(), - AggValueVTs[i]) : + Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : SDValue(Agg.getNode(), Agg.getResNo() + i); setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), @@ -2661,8 +2666,7 @@ for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) Values[i - LinearIndex] = OutOfUndef ? - DAG.getNode(ISD::UNDEF, getCurDebugLoc(), - Agg.getNode()->getValueType(Agg.getResNo() + i)) : + DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : SDValue(Agg.getNode(), Agg.getResNo() + i); setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), @@ -3852,7 +3856,7 @@ SDValue Op2 = getValue(I.getOperand(2)); SDValue Op3 = getValue(I.getOperand(3)); unsigned Align = cast(I.getOperand(4))->getZExtValue(); - DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false, + DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false, I.getOperand(1), 0, I.getOperand(2), 0)); return 0; } @@ -3861,7 +3865,7 @@ SDValue Op2 = getValue(I.getOperand(2)); SDValue Op3 = getValue(I.getOperand(3)); unsigned Align = cast(I.getOperand(4))->getZExtValue(); - DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align, + DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, I.getOperand(1), 0)); return 0; } @@ -3878,12 +3882,12 @@ Size = C->getZExtValue(); if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) == AliasAnalysis::NoAlias) { - DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false, + DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false, I.getOperand(1), 0, I.getOperand(2), 0)); return 0; } - DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align, + DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, I.getOperand(1), 0, I.getOperand(2), 0)); return 0; } @@ -3911,7 +3915,8 @@ if (DW && DW->ValidDebugInfo(RSI.getContext())) { unsigned LabelID = DW->RecordRegionStart(cast(RSI.getContext())); - DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), + getRoot(), LabelID)); } return 0; @@ -3922,7 +3927,8 @@ if (DW && DW->ValidDebugInfo(REI.getContext())) { unsigned LabelID = DW->RecordRegionEnd(cast(REI.getContext())); - DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), + getRoot(), LabelID)); } return 0; @@ -3947,7 +3953,8 @@ unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile); if (DW->getRecordSourceLineCount() != 1) - DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), + getRoot(), LabelID)); setCurDebugLoc(DebugLoc::get(DAG.getMachineFunction(). getOrCreateDebugLocID(SrcFile, Line, 0))); @@ -4103,7 +4110,7 @@ } MVT DestVT = TLI.getValueType(I.getType()); Value* Op1 = I.getOperand(1); - setValue(&I, DAG.getConvertRndSat(DestVT, getValue(Op1), + setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), DAG.getValueType(DestVT), DAG.getValueType(getValue(Op1).getValueType()), getValue(I.getOperand(2)), @@ -4392,7 +4399,8 @@ // Both PendingLoads and PendingExports must be flushed here; // this call might not return. (void)getRoot(); - DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel)); + DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(), + getControlRoot(), BeginLabel)); } std::pair Result = @@ -4411,7 +4419,8 @@ // Insert a label at the end of the invoke call to mark the try range. This // can be used to detect deletion of the invoke via the MachineModuleInfo. EndLabel = MMI->NextLabelID(); - DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel)); + DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(), + getRoot(), EndLabel)); // Inform MachineModuleInfo of range. MMI->addInvoke(LandingPad, BeginLabel, EndLabel); @@ -4529,9 +4538,9 @@ for (unsigned i = 0; i != NumRegs; ++i) { SDValue P; if (Flag == 0) - P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT); + P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); else { - P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag); + P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); *Flag = P.getValue(2); } Chain = P.getValue(1); @@ -4616,9 +4625,9 @@ for (unsigned i = 0; i != NumRegs; ++i) { SDValue Part; if (Flag == 0) - Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]); + Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); else { - Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag); + Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); *Flag = Part.getValue(1); } Chains[i] = Part.getValue(0); @@ -5453,9 +5462,9 @@ } void SelectionDAGLowering::visitVAArg(VAArgInst &I) { - SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), - getValue(I.getOperand(0)), - DAG.getSrcValue(I.getOperand(0))); + SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), + getRoot(), getValue(I.getOperand(0)), + DAG.getSrcValue(I.getOperand(0))); setValue(&I, V); DAG.setRoot(V.getValue(1)); } @@ -5791,7 +5800,8 @@ ComputeValueVTs(TLI, AI->getType(), ValueVTs); unsigned NumValues = ValueVTs.size(); if (!AI->use_empty()) { - SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues)); + SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues, + SDL->getCurDebugLoc())); // If this argument is live outside of the entry block, insert a copy from // whereever we got it to the vreg that other BB's will reference it as. DenseMap::iterator VMI=FuncInfo->ValueMap.find(AI); Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Feb 14 07:20:23 2009 @@ -440,9 +440,11 @@ MVT VT = Arg.getValueType(); unsigned VReg = MF.getRegInfo(). createVirtualRegister(TLI.getRegClassFor(VT)); - Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag); + Chain = DAG.getCopyToReg(Chain, Arg.getDebugLoc(), + VReg, Arg, InFlag); InFlag = Chain.getValue(1); - Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag); + Arg = DAG.getCopyFromReg(Chain, Arg.getDebugLoc(), + VReg, VT, InFlag); Chain = Arg.getValue(1); InFlag = Arg.getValue(2); } Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sat Feb 14 07:20:23 2009 @@ -692,7 +692,7 @@ SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const { if (usesGlobalOffsetTable()) - return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); + return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); return Table; } @@ -723,6 +723,7 @@ /// constant and return true. bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, const APInt &Demanded) { + DebugLoc dl = Op.getDebugLoc(); // FIXME: ISD::SELECT, ISD::SELECT_CC switch (Op.getOpcode()) { default: break; @@ -732,7 +733,7 @@ if (ConstantSDNode *C = dyn_cast(Op.getOperand(1))) if (C->getAPIntValue().intersects(~Demanded)) { MVT VT = Op.getValueType(); - SDValue New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), + SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), DAG.getConstant(Demanded & C->getAPIntValue(), VT)); @@ -760,7 +761,7 @@ assert(Op.getValueSizeInBits() == BitWidth && "Mask size mismatches value type size!"); APInt NewMask = DemandedMask; - DebugLoc dl = Op.getNode()->getDebugLoc(); + DebugLoc dl = Op.getDebugLoc(); // Don't know anything. KnownZero = KnownOne = APInt(BitWidth, 0); @@ -779,8 +780,7 @@ } else if (DemandedMask == 0) { // Not demanding any bits from Op. if (Op.getOpcode() != ISD::UNDEF) - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, dl, - Op.getValueType())); + return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); return false; } else if (Depth == 6) { // Limit search depth. return false; @@ -890,7 +890,7 @@ // (but not both) turn this into an *inclusive* or. // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), + return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), Op.getOperand(0), Op.getOperand(1))); @@ -1704,7 +1704,7 @@ case 1: // Known true. return DAG.getConstant(1, VT); case 2: // Undefined. - return DAG.getNode(ISD::UNDEF, VT); + return DAG.getUNDEF(VT); } } @@ -1871,7 +1871,7 @@ case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y case ISD::SETULT: // X X == 0 & Y == 1 --> ~X & Y Temp = DAG.getNOT(dl, N0, MVT::i1); - N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); + N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMConstantIslandPass.cpp Sat Feb 14 07:20:23 2009 @@ -301,7 +301,7 @@ // aligned. assert((Size & 3) == 0 && "CP Entry not multiple of 4 bytes!"); MachineInstr *CPEMI = - BuildMI(BB, TII->get(ARM::CONSTPOOL_ENTRY)) + BuildMI(BB, DebugLoc::getUnknownLoc(), TII->get(ARM::CONSTPOOL_ENTRY)) .addImm(i).addConstantPoolIndex(i).addImm(Size); CPEMIs.push_back(CPEMI); @@ -567,7 +567,10 @@ // Add an unconditional branch from OrigBB to NewBB. // Note the new unconditional branch is not being recorded. - BuildMI(OrigBB, TII->get(isThumb ? ARM::tB : ARM::B)).addMBB(NewBB); + // There doesn't seem to be meaningful DebugInfo available; this doesn't + // correspond to anything in the source. + BuildMI(OrigBB, DebugLoc::getUnknownLoc(), + TII->get(isThumb ? ARM::tB : ARM::B)).addMBB(NewBB); NumSplit++; // Update the CFG. All succs of OrigBB are now succs of NewBB. @@ -931,7 +934,8 @@ // targets will be exchanged, and the altered branch may be out of // range, so the machinery has to know about it. int UncondBr = isThumb ? ARM::tB : ARM::B; - BuildMI(UserMBB, TII->get(UncondBr)).addMBB(*NewMBB); + BuildMI(UserMBB, DebugLoc::getUnknownLoc(), + TII->get(UncondBr)).addMBB(*NewMBB); unsigned MaxDisp = getUnconditionalBrDisp(UncondBr); ImmBranches.push_back(ImmBranch(&UserMBB->back(), MaxDisp, false, UncondBr)); @@ -1042,7 +1046,8 @@ // Now that we have an island to add the CPE to, clone the original CPE and // add it to the island. - U.CPEMI = BuildMI(NewIsland, TII->get(ARM::CONSTPOOL_ENTRY)) + U.CPEMI = BuildMI(NewIsland, DebugLoc::getUnknownLoc(), + TII->get(ARM::CONSTPOOL_ENTRY)) .addImm(ID).addConstantPoolIndex(CPI).addImm(Size); CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1)); NumCPEs++; @@ -1240,11 +1245,12 @@ // Insert a new conditional branch and a new unconditional branch. // Also update the ImmBranch as well as adding a new entry for the new branch. - BuildMI(MBB, TII->get(MI->getOpcode())).addMBB(NextBB) - .addImm(CC).addReg(CCReg); + BuildMI(MBB, DebugLoc::getUnknownLoc(), + TII->get(MI->getOpcode())) + .addMBB(NextBB).addImm(CC).addReg(CCReg); Br.MI = &MBB->back(); BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back()); - BuildMI(MBB, TII->get(Br.UncondBr)).addMBB(DestBB); + BuildMI(MBB, DebugLoc::getUnknownLoc(), TII->get(Br.UncondBr)).addMBB(DestBB); BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back()); unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr); ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr)); @@ -1268,7 +1274,7 @@ if (MI->getOpcode() == ARM::tPOP_RET && MI->getOperand(0).getReg() == ARM::PC && MI->getNumExplicitOperands() == 1) { - BuildMI(MI->getParent(), TII->get(ARM::tBX_RET)); + BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET)); MI->eraseFromParent(); MadeChange = true; } Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelDAGToDAG.cpp Sat Feb 14 07:20:23 2009 @@ -379,13 +379,15 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base, SDValue &Offset){ + // FIXME dl should come from the parent load or store, not the address + DebugLoc dl = Op.getDebugLoc(); if (N.getOpcode() != ISD::ADD) { Base = N; // We must materialize a zero in a reg! Returning a constant here // wouldn't work without additional code to position the node within // ISel's topological ordering in a place where ISel will process it // normally. Instead, just explicitly issue a tMOVri8 node! - Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32, + Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, dl, MVT::i32, CurDAG->getTargetConstant(0, MVT::i32)), 0); return true; } @@ -532,6 +534,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { SDNode *N = Op.getNode(); + DebugLoc dl = N->getDebugLoc(); if (N->isMachineOpcode()) return NULL; // Already selected. @@ -556,7 +559,7 @@ SDNode *ResNode; if (Subtarget->isThumb()) - ResNode = CurDAG->getTargetNode(ARM::tLDRcp, MVT::i32, MVT::Other, + ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other, CPIdx, CurDAG->getEntryNode()); else { SDValue Ops[] = { @@ -567,7 +570,8 @@ CurDAG->getRegister(0, MVT::i32), CurDAG->getEntryNode() }; - ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 6); + ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other, + Ops, 6); } ReplaceUses(Op, SDValue(ResNode, 0)); return NULL; @@ -632,20 +636,20 @@ } break; case ARMISD::FMRRD: - return CurDAG->getTargetNode(ARM::FMRRD, MVT::i32, MVT::i32, + return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32, Op.getOperand(0), getAL(CurDAG), CurDAG->getRegister(0, MVT::i32)); case ISD::UMUL_LOHI: { SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), CurDAG->getRegister(0, MVT::i32) }; - return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32, Ops, 5); + return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5); } case ISD::SMUL_LOHI: { SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), CurDAG->getRegister(0, MVT::i32) }; - return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32, Ops, 5); + return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5); } case ISD::LOAD: { LoadSDNode *LD = cast(Op); @@ -685,7 +689,7 @@ SDValue Base = LD->getBasePtr(); SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), Chain }; - return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32, + return CurDAG->getTargetNode(Opcode, dl, MVT::i32, MVT::i32, MVT::Other, Ops, 6); } } @@ -715,7 +719,8 @@ cast(N2)->getZExtValue()), MVT::i32); SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag }; - SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other, MVT::Flag, Ops, 5); + SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other, + MVT::Flag, Ops, 5); Chain = SDValue(ResNode, 0); if (Op.getNode()->getNumValues() == 2) { InFlag = SDValue(ResNode, 1); @@ -855,7 +860,7 @@ TLI.getPointerTy()); SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy()); SDValue Ops[] = { Tmp1, Tmp2, Chain }; - return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, + return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl, MVT::Other, Ops, 3); } break; Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.cpp Sat Feb 14 07:20:23 2009 @@ -403,7 +403,8 @@ TheCall->getCallingConv() == CallingConv::Fast) && "unknown calling convention"); SDValue Callee = TheCall->getCallee(); - unsigned NumOps = TheCall->getNumArgs(); + unsigned NumOps = TheCall->getNumArgs(); + DebugLoc dl = TheCall->getDebugLoc(); unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot unsigned NumGPRs = 0; // GPRs used for parameter passing. @@ -458,25 +459,25 @@ break; case MVT::f32: RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], - DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg))); + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg))); break; case MVT::i64: { - SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg, DAG.getConstant(0, getPointerTy())); - SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg, DAG.getConstant(1, getPointerTy())); RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo)); if (ObjGPRs == 2) RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi)); else { SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); - PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); - MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0)); + PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); + MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, NULL, 0)); } break; } case MVT::f64: { - SDValue Cvt = DAG.getNode(ARMISD::FMRRD, + SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt)); @@ -485,8 +486,8 @@ Cvt.getValue(1))); else { SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); - PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); - MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff, + PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); + MemOpChains.push_back(DAG.getStore(Chain, dl, Cvt.getValue(1), PtrOff, NULL, 0)); } break; @@ -495,8 +496,8 @@ } else { assert(ObjSize != 0); SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); - PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); } NumGPRs += ObjGPRs; @@ -504,15 +505,15 @@ } if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token chain // and flag operands which copy the outgoing args into the appropriate regs. SDValue InFlag; for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, - InFlag); + Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, + RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } @@ -537,10 +538,12 @@ ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPStub, 4); SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); - CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); + CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); + Callee = DAG.getLoad(getPointerTy(), dl, + DAG.getEntryNode(), CPAddr, NULL, 0); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); - Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); + Callee = DAG.getNode(ARMISD::PIC_ADD, dl, + getPointerTy(), Callee, PICLabel); } else Callee = DAG.getTargetGlobalAddress(GV, getPointerTy()); } else if (ExternalSymbolSDNode *S = dyn_cast(Callee)) { @@ -554,10 +557,12 @@ ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex, ARMCP::CPStub, 4); SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); - CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); + CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); + Callee = DAG.getLoad(getPointerTy(), dl, + DAG.getEntryNode(), CPAddr, NULL, 0); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); - Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); + Callee = DAG.getNode(ARMISD::PIC_ADD, dl, + getPointerTy(), Callee, PICLabel); } else Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); } @@ -576,8 +581,7 @@ } if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) { // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK - Chain = DAG.getCopyToReg(Chain, ARM::LR, - DAG.getNode(ISD::UNDEF, MVT::i32), InFlag); + Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag); InFlag = Chain.getValue(1); } @@ -594,7 +598,7 @@ if (InFlag.getNode()) Ops.push_back(InFlag); // Returns a chain and a flag for retval copy to use. - Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag), + Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag), &Ops[0], Ops.size()); InFlag = Chain.getValue(1); @@ -611,25 +615,27 @@ case MVT::Other: break; case MVT::i32: - Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, ARM::R0, + MVT::i32, InFlag).getValue(1); ResultVals.push_back(Chain.getValue(0)); if (TheCall->getNumRetVals() > 1 && TheCall->getRetValType(1) == MVT::i32) { // Returns a i64 value. - Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, + Chain = DAG.getCopyFromReg(Chain, dl, ARM::R1, MVT::i32, Chain.getValue(2)).getValue(1); ResultVals.push_back(Chain.getValue(0)); } break; case MVT::f32: - Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); - ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32, + Chain = DAG.getCopyFromReg(Chain, dl, ARM::R0, + MVT::i32, InFlag).getValue(1); + ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Chain.getValue(0))); break; case MVT::f64: { - SDValue Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag); - SDValue Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2)); - ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi)); + SDValue Lo = DAG.getCopyFromReg(Chain, dl, ARM::R0, MVT::i32, InFlag); + SDValue Hi = DAG.getCopyFromReg(Lo, dl, ARM::R1, MVT::i32, Lo.getValue(2)); + ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi)); break; } } @@ -638,40 +644,43 @@ return Chain; ResultVals.push_back(Chain); - SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size()); + SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl); return Res.getValue(Op.getResNo()); } static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { SDValue Copy; SDValue Chain = Op.getOperand(0); + DebugLoc dl = Op.getDebugLoc(); switch(Op.getNumOperands()) { default: assert(0 && "Do not know how to return this many arguments!"); abort(); case 1: { SDValue LR = DAG.getRegister(ARM::LR, MVT::i32); - return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain); + return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain); } case 3: Op = Op.getOperand(1); if (Op.getValueType() == MVT::f32) { - Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); + Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); } else if (Op.getValueType() == MVT::f64) { // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is // available. - Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1); + Op = DAG.getNode(ARMISD::FMRRD, dl, + DAG.getVTList(MVT::i32, MVT::i32), &Op,1); SDValue Sign = DAG.getConstant(0, MVT::i32); - return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign, + return DAG.getNode(ISD::RET, dl, MVT::Other, Chain, Op, Sign, Op.getValue(1), Sign); } - Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDValue()); + Copy = DAG.getCopyToReg(Chain, dl, ARM::R0, Op, SDValue()); if (DAG.getMachineFunction().getRegInfo().liveout_empty()) DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); break; case 5: - Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDValue()); - Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1)); + Copy = DAG.getCopyToReg(Chain, dl, ARM::R1, Op.getOperand(3), SDValue()); + Copy = DAG.getCopyToReg(Copy, dl, ARM::R0, Op.getOperand(1), + Copy.getValue(1)); // If we haven't noted the R0+R1 are live out, do so now. if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); @@ -679,10 +688,13 @@ } break; case 9: // i128 -> 4 regs - Copy = DAG.getCopyToReg(Chain, ARM::R3, Op.getOperand(7), SDValue()); - Copy = DAG.getCopyToReg(Copy , ARM::R2, Op.getOperand(5), Copy.getValue(1)); - Copy = DAG.getCopyToReg(Copy , ARM::R1, Op.getOperand(3), Copy.getValue(1)); - Copy = DAG.getCopyToReg(Copy , ARM::R0, Op.getOperand(1), Copy.getValue(1)); + Copy = DAG.getCopyToReg(Chain, dl, ARM::R3, Op.getOperand(7), SDValue()); + Copy = DAG.getCopyToReg(Copy , dl, ARM::R2, Op.getOperand(5), + Copy.getValue(1)); + Copy = DAG.getCopyToReg(Copy , dl, ARM::R1, Op.getOperand(3), + Copy.getValue(1)); + Copy = DAG.getCopyToReg(Copy , dl, ARM::R0, Op.getOperand(1), + Copy.getValue(1)); // If we haven't noted the R0+R1 are live out, do so now. if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); @@ -695,7 +707,7 @@ } //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag - return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); + return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Copy, Copy.getValue(1)); } // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as @@ -706,6 +718,8 @@ // into MOVi. static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { MVT PtrVT = Op.getValueType(); + // FIXME there is no actual debug info here + DebugLoc dl = Op.getDebugLoc(); ConstantPoolSDNode *CP = cast(Op); SDValue Res; if (CP->isMachineConstantPoolEntry()) @@ -714,25 +728,26 @@ else Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment()); - return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res); + return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); } // Lower ISD::GlobalTLSAddress using the "general dynamic" model SDValue ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) { + DebugLoc dl = GA->getDebugLoc(); MVT PtrVT = getPointerTy(); unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, PCAdj, "tlsgd", true); SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2); - Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument); - Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0); + Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); + Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0); SDValue Chain = Argument.getValue(1); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); - Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel); + Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); // call __tls_get_addr. ArgListTy Args; @@ -744,8 +759,7 @@ std::pair CallResult = LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false, CallingConv::C, false, - DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, - DebugLoc::getUnknownLoc()); + DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); return CallResult.first; } @@ -755,11 +769,12 @@ ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, SelectionDAG &DAG) { GlobalValue *GV = GA->getGlobal(); + DebugLoc dl = GA->getDebugLoc(); SDValue Offset; SDValue Chain = DAG.getEntryNode(); MVT PtrVT = getPointerTy(); // Get the Thread Pointer - SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); + SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); if (GV->isDeclaration()){ // initial exec model @@ -768,26 +783,26 @@ new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, PCAdj, "gottpoff", true); Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); - Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); - Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); + Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); + Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0); Chain = Offset.getValue(1); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); - Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel); + Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); - Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); + Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0); } else { // local exec model ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff"); Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); - Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); - Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); + Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); + Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0); } // The address of the thread local variable is the add of the thread // pointer with the offset of the variable. - return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); + return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); } SDValue @@ -807,6 +822,7 @@ SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) { MVT PtrVT = getPointerTy(); + DebugLoc dl = Op.getDebugLoc(); GlobalValue *GV = cast(Op)->getGlobal(); Reloc::Model RelocM = getTargetMachine().getRelocationModel(); if (RelocM == Reloc::PIC_) { @@ -814,18 +830,19 @@ ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT"); SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); - CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); + CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); + SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), + CPAddr, NULL, 0); SDValue Chain = Result.getValue(1); - SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT); - Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT); + SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); + Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); if (!UseGOTOFF) - Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); + Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0); return Result; } else { SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); - CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); + CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); + return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); } } @@ -843,6 +860,7 @@ SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) { MVT PtrVT = getPointerTy(); + DebugLoc dl = Op.getDebugLoc(); GlobalValue *GV = cast(Op)->getGlobal(); Reloc::Model RelocM = getTargetMachine().getRelocationModel(); bool IsIndirect = GVIsIndirectSymbol(GV, RelocM); @@ -858,17 +876,17 @@ Kind, PCAdj); CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); } - CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); + CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); - SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); + SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); SDValue Chain = Result.getValue(1); if (RelocM == Reloc::PIC_) { SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); - Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); + Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); } if (IsIndirect) - Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); + Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0); return Result; } @@ -878,15 +896,16 @@ assert(Subtarget->isTargetELF() && "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); MVT PtrVT = getPointerTy(); + DebugLoc dl = Op.getDebugLoc(); unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_", ARMPCLabelIndex, ARMCP::CPValue, PCAdj); SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); - CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); + CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); + SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); - return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); + return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); } static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { @@ -895,7 +914,8 @@ switch (IntNo) { default: return SDValue(); // Don't custom lower most intrinsics. case Intrinsic::arm_thread_pointer: - return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); + return DAG.getNode(ARMISD::THREAD_POINTER, DebugLoc::getUnknownLoc(), + PtrVT); } } @@ -903,15 +923,16 @@ unsigned VarArgsFrameIndex) { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. + DebugLoc dl = Op.getDebugLoc(); MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); const Value *SV = cast(Op.getOperand(2))->getValue(); - return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); + return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); } static SDValue LowerFORMAL_ARGUMENT(SDValue Op, SelectionDAG &DAG, unsigned ArgNo, unsigned &NumGPRs, - unsigned &ArgOffset) { + unsigned &ArgOffset, DebugLoc dl) { MachineFunction &MF = DAG.getMachineFunction(); MVT ObjectVT = Op.getValue(ArgNo).getValueType(); SDValue Root = Op.getOperand(0); @@ -936,20 +957,20 @@ if (ObjGPRs == 1) { unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); - ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); + ArgValue = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); if (ObjectVT == MVT::f32) - ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue); + ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue); } else if (ObjGPRs == 2) { unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); - ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); + ArgValue = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg); - SDValue ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32); + SDValue ArgValue2 = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); assert(ObjectVT != MVT::i64 && "i64 should already be lowered"); - ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); + ArgValue = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2); } NumGPRs += ObjGPRs; @@ -958,11 +979,11 @@ int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); if (ObjGPRs == 0) - ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); + ArgValue = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0); else { - SDValue ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0); + SDValue ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0); assert(ObjectVT != MVT::i64 && "i64 should already be lowered"); - ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); + ArgValue = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2); } ArgOffset += ObjSize; // Move on to the next argument. @@ -975,13 +996,14 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { std::vector ArgValues; SDValue Root = Op.getOperand(0); + DebugLoc dl = Op.getDebugLoc(); unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot unsigned NumGPRs = 0; // GPRs used for parameter passing. unsigned NumArgs = Op.getNode()->getNumValues()-1; for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo, - NumGPRs, ArgOffset)); + NumGPRs, ArgOffset, dl)); bool isVarArg = cast(Op.getOperand(2))->getZExtValue() != 0; if (isVarArg) { @@ -1009,14 +1031,14 @@ for (; NumGPRs < 4; ++NumGPRs) { unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); - SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); - SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); + SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); + SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); MemOps.push_back(Store); - FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, + FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, DAG.getConstant(4, getPointerTy())); } if (!MemOps.empty()) - Root = DAG.getNode(ISD::TokenFactor, MVT::Other, + Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0], MemOps.size()); } else // This will point to the next argument passed via stack. @@ -1026,7 +1048,7 @@ ArgValues.push_back(Root); // Return the new list of results. - return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), &ArgValues[0], ArgValues.size()); } @@ -1054,7 +1076,8 @@ /// Returns appropriate ARM CMP (cmp) and corresponding condition code for /// the given operands. static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, - SDValue &ARMCC, SelectionDAG &DAG, bool isThumb) { + SDValue &ARMCC, SelectionDAG &DAG, bool isThumb, + DebugLoc dl) { if (ConstantSDNode *RHSC = dyn_cast(RHS.getNode())) { unsigned C = RHSC->getZExtValue(); if (!isLegalCmpImmediate(C, isThumb)) { @@ -1108,17 +1131,18 @@ break; } ARMCC = DAG.getConstant(CondCode, MVT::i32); - return DAG.getNode(CompareType, MVT::Flag, LHS, RHS); + return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS); } /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. -static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG) { +static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, + DebugLoc dl) { SDValue Cmp; if (!isFloatingPointZero(RHS)) - Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS); + Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS); else - Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS); - return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp); + Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS); + return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp); } static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, @@ -1129,12 +1153,13 @@ ISD::CondCode CC = cast(Op.getOperand(4))->get(); SDValue TrueVal = Op.getOperand(2); SDValue FalseVal = Op.getOperand(3); + DebugLoc dl = Op.getDebugLoc(); if (LHS.getValueType() == MVT::i32) { SDValue ARMCC; SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); - SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); - return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp); + SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl); + return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp); } ARMCC::CondCodes CondCode, CondCode2; @@ -1143,14 +1168,15 @@ SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); - SDValue Cmp = getVFPCmp(LHS, RHS, DAG); - SDValue Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, + SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); + SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp); if (CondCode2 != ARMCC::AL) { SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); // FIXME: Needs another CMP because flag can have but one use. - SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG); - Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2); + SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl); + Result = DAG.getNode(ARMISD::CMOV, dl, VT, + Result, TrueVal, ARMCC2, CCR, Cmp2); } return Result; } @@ -1162,12 +1188,14 @@ SDValue LHS = Op.getOperand(2); SDValue RHS = Op.getOperand(3); SDValue Dest = Op.getOperand(4); + DebugLoc dl = Op.getDebugLoc(); if (LHS.getValueType() == MVT::i32) { SDValue ARMCC; SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); - SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); - return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp); + SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl); + return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, + Chain, Dest, ARMCC, CCR,Cmp); } assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); @@ -1176,16 +1204,16 @@ // Swap the LHS/RHS of the comparison if needed. std::swap(LHS, RHS); - SDValue Cmp = getVFPCmp(LHS, RHS, DAG); + SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp }; - SDValue Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); + SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); if (CondCode2 != ARMCC::AL) { ARMCC = DAG.getConstant(CondCode2, MVT::i32); SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) }; - Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); + Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); } return Res; } @@ -1194,55 +1222,59 @@ SDValue Chain = Op.getOperand(0); SDValue Table = Op.getOperand(1); SDValue Index = Op.getOperand(2); + DebugLoc dl = Op.getDebugLoc(); MVT PTy = getPointerTy(); JumpTableSDNode *JT = cast(Table); ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo(); SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); - Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId); - Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy)); - SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); + Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId); + Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); + SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; - Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, + Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, dl, Chain, Addr, NULL, 0); Chain = Addr.getValue(1); if (isPIC) - Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table); - return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId); + Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); + return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); } static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); unsigned Opc = Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI; - Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0)); - return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); + Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0)); + return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); } static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); + DebugLoc dl = Op.getDebugLoc(); unsigned Opc = Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF; - Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); - return DAG.getNode(Opc, VT, Op); + Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0)); + return DAG.getNode(Opc, dl, VT, Op); } static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { // Implement fcopysign with a fabs and a conditional fneg. SDValue Tmp0 = Op.getOperand(0); SDValue Tmp1 = Op.getOperand(1); + DebugLoc dl = Op.getDebugLoc(); MVT VT = Op.getValueType(); MVT SrcVT = Tmp1.getValueType(); - SDValue AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0); - SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG); + SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0); + SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl); SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); - return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); + return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); } SDValue -ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, +ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, @@ -1279,24 +1311,24 @@ while (EmittedNumMemOps < NumMemOps) { for (i = 0; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { - Loads[i] = DAG.getLoad(VT, Chain, - DAG.getNode(ISD::ADD, MVT::i32, Src, + Loads[i] = DAG.getLoad(VT, dl, Chain, + DAG.getNode(ISD::ADD, dl, MVT::i32, Src, DAG.getConstant(SrcOff, MVT::i32)), SrcSV, SrcSVOff + SrcOff); TFOps[i] = Loads[i].getValue(1); SrcOff += VTSize; } - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); for (i = 0; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { - TFOps[i] = DAG.getStore(Chain, Loads[i], - DAG.getNode(ISD::ADD, MVT::i32, Dst, + TFOps[i] = DAG.getStore(Chain, dl, Loads[i], + DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, DAG.getConstant(DstOff, MVT::i32)), DstSV, DstSVOff + DstOff); DstOff += VTSize; } - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); EmittedNumMemOps += i; } @@ -1316,8 +1348,8 @@ VTSize = 1; } - Loads[i] = DAG.getLoad(VT, Chain, - DAG.getNode(ISD::ADD, MVT::i32, Src, + Loads[i] = DAG.getLoad(VT, dl, Chain, + DAG.getNode(ISD::ADD, dl, MVT::i32, Src, DAG.getConstant(SrcOff, MVT::i32)), SrcSV, SrcSVOff + SrcOff); TFOps[i] = Loads[i].getValue(1); @@ -1325,7 +1357,7 @@ SrcOff += VTSize; BytesLeft -= VTSize; } - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); i = 0; BytesLeft = BytesLeftSave; @@ -1338,34 +1370,35 @@ VTSize = 1; } - TFOps[i] = DAG.getStore(Chain, Loads[i], - DAG.getNode(ISD::ADD, MVT::i32, Dst, + TFOps[i] = DAG.getStore(Chain, dl, Loads[i], + DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, DAG.getConstant(DstOff, MVT::i32)), DstSV, DstSVOff + DstOff); ++i; DstOff += VTSize; BytesLeft -= VTSize; } - return DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); } static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) { SDValue Op = N->getOperand(0); + DebugLoc dl = N->getDebugLoc(); if (N->getValueType(0) == MVT::f64) { // Turn i64->f64 into FMDRR. - SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, DAG.getConstant(0, MVT::i32)); - SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, DAG.getConstant(1, MVT::i32)); - return DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi); + return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi); } // Turn f64->i64 into FMRRD. - SDValue Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), - &Op, 1); + SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl, + DAG.getVTList(MVT::i32, MVT::i32), &Op, 1); // Merge the pieces into a single i64 value. - return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)); + return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); } static SDValue ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) { @@ -1382,21 +1415,22 @@ if (ST->isThumb()) return SDValue(); // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. - SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), + DebugLoc dl = N->getDebugLoc(); + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), DAG.getConstant(0, MVT::i32)); - SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), DAG.getConstant(1, MVT::i32)); // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and // captures the result into a carry flag. unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; - Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); + Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); // The low part is an ARMISD::RRX operand, which shifts the carry in. - Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1)); + Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); // Merge the pieces into a single i64 value. - return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); + return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); } @@ -1464,6 +1498,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) { const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + DebugLoc dl = MI->getDebugLoc(); switch (MI->getOpcode()) { default: assert(false && "Unexpected instr type to insert"); case ARM::tMOVCCr: { @@ -1485,7 +1520,7 @@ MachineFunction *F = BB->getParent(); MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); - BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB) + BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB) .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); F->insert(It, copy0MBB); F->insert(It, sinkMBB); @@ -1513,7 +1548,7 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg()) + BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.h?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.h Sat Feb 14 07:20:23 2009 @@ -149,7 +149,7 @@ SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG); SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG); - SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, + SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp Sat Feb 14 07:20:23 2009 @@ -147,10 +147,11 @@ MachineBasicBlock::iterator I, unsigned DestReg, const MachineInstr *Orig) const { + DebugLoc dl = Orig->getDebugLoc(); if (Orig->getOpcode() == ARM::MOVi2pieces) { RI.emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImm(), Orig->getOperand(2).getImm(), - Orig->getOperand(3).getReg(), this, false); + Orig->getOperand(3).getReg(), this, false, dl); return; } @@ -243,17 +244,20 @@ // Can't encode it in a so_imm operand. This transformation will // add more than 1 instruction. Abandon! return NULL; - UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) + UpdateMI = BuildMI(MF, MI->getDebugLoc(), + get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) .addReg(BaseReg).addImm(SOImmVal) .addImm(Pred).addReg(0).addReg(0); } else if (Amt != 0) { ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); - UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) + UpdateMI = BuildMI(MF, MI->getDebugLoc(), + get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) .addImm(Pred).addReg(0).addReg(0); } else - UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) + UpdateMI = BuildMI(MF, MI->getDebugLoc(), + get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) .addReg(BaseReg).addReg(OffReg) .addImm(Pred).addReg(0).addReg(0); break; @@ -263,11 +267,13 @@ unsigned Amt = ARM_AM::getAM3Offset(OffImm); if (OffReg == 0) // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. - UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) + UpdateMI = BuildMI(MF, MI->getDebugLoc(), + get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) .addReg(BaseReg).addImm(Amt) .addImm(Pred).addReg(0).addReg(0); else - UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) + UpdateMI = BuildMI(MF, MI->getDebugLoc(), + get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) .addReg(BaseReg).addReg(OffReg) .addImm(Pred).addReg(0).addReg(0); break; @@ -277,19 +283,23 @@ std::vector NewMIs; if (isPre) { if (isLoad) - MemMI = BuildMI(MF, get(MemOpc), MI->getOperand(0).getReg()) + MemMI = BuildMI(MF, MI->getDebugLoc(), + get(MemOpc), MI->getOperand(0).getReg()) .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); else - MemMI = BuildMI(MF, get(MemOpc)).addReg(MI->getOperand(1).getReg()) + MemMI = BuildMI(MF, MI->getDebugLoc(), + get(MemOpc)).addReg(MI->getOperand(1).getReg()) .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); NewMIs.push_back(MemMI); NewMIs.push_back(UpdateMI); } else { if (isLoad) - MemMI = BuildMI(MF, get(MemOpc), MI->getOperand(0).getReg()) + MemMI = BuildMI(MF, MI->getDebugLoc(), + get(MemOpc), MI->getOperand(0).getReg()) .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); else - MemMI = BuildMI(MF, get(MemOpc)).addReg(MI->getOperand(1).getReg()) + MemMI = BuildMI(MF, MI->getDebugLoc(), + get(MemOpc)).addReg(MI->getOperand(1).getReg()) .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); if (WB.isDead()) UpdateMI->getOperand(0).setIsDead(); @@ -438,6 +448,8 @@ unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const { + // FIXME this should probably have a DebugLoc argument + DebugLoc dl = DebugLoc::getUnknownLoc(); MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo(); int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B; @@ -450,17 +462,17 @@ if (FBB == 0) { if (Cond.empty()) // Unconditional branch? - BuildMI(&MBB, get(BOpc)).addMBB(TBB); + BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB); else - BuildMI(&MBB, get(BccOpc)).addMBB(TBB) + BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); return 1; } // Two-way conditional branch. - BuildMI(&MBB, get(BccOpc)).addMBB(TBB) + BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); - BuildMI(&MBB, get(BOpc)).addMBB(FBB); + BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB); return 2; } @@ -474,19 +486,22 @@ return false; } + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (DestRC == ARM::GPRRegisterClass) { MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo(); if (AFI->isThumbFunction()) - BuildMI(MBB, I, get(ARM::tMOVr), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg); else - AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, get(ARM::MOVr), DestReg) + AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) .addReg(SrcReg))); } else if (DestRC == ARM::SPRRegisterClass) - AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYS), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg) .addReg(SrcReg)); else if (DestRC == ARM::DPRRegisterClass) - AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYD), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg) .addReg(SrcReg)); else return false; @@ -512,40 +527,45 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (RC == ARM::GPRRegisterClass) { MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo(); if (AFI->isThumbFunction()) - BuildMI(MBB, I, get(ARM::tSpill)).addReg(SrcReg, false, false, isKill) + BuildMI(MBB, I, DL, get(ARM::tSpill)) + .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addImm(0); else - AddDefaultPred(BuildMI(MBB, I, get(ARM::STR)) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addReg(0).addImm(0)); } else if (RC == ARM::DPRRegisterClass) { - AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTD)) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD)) .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addImm(0)); } else { assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); - AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTS)) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS)) .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addImm(0)); } } void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - bool isKill, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl &NewMIs) const { + bool isKill, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl &NewMIs) const{ + DebugLoc DL = DebugLoc::getUnknownLoc(); unsigned Opc = 0; if (RC == ARM::GPRRegisterClass) { ARMFunctionInfo *AFI = MF.getInfo(); if (AFI->isThumbFunction()) { Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR; MachineInstrBuilder MIB = - BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill); + BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); NewMIs.push_back(MIB); @@ -560,7 +580,7 @@ } MachineInstrBuilder MIB = - BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill); + BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); AddDefaultPred(MIB); @@ -572,35 +592,39 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (RC == ARM::GPRRegisterClass) { MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo(); if (AFI->isThumbFunction()) - BuildMI(MBB, I, get(ARM::tRestore), DestReg) + BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg) .addFrameIndex(FI).addImm(0); else - AddDefaultPred(BuildMI(MBB, I, get(ARM::LDR), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) .addFrameIndex(FI).addReg(0).addImm(0)); } else if (RC == ARM::DPRRegisterClass) { - AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDD), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg) .addFrameIndex(FI).addImm(0)); } else { assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); - AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDS), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg) .addFrameIndex(FI).addImm(0)); } } void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); unsigned Opc = 0; if (RC == ARM::GPRRegisterClass) { ARMFunctionInfo *AFI = MF.getInfo(); if (AFI->isThumbFunction()) { Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR; - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); NewMIs.push_back(MIB); @@ -614,7 +638,7 @@ Opc = ARM::FLDS; } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); AddDefaultPred(MIB); @@ -630,7 +654,10 @@ if (!AFI->isThumbFunction() || CSI.empty()) return false; - MachineInstrBuilder MIB = BuildMI(MBB, MI, get(ARM::tPUSH)); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + + MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH)); for (unsigned i = CSI.size(); i != 0; --i) { unsigned Reg = CSI[i-1].getReg(); // Add the callee-saved register as live-in. It's killed at the spill. @@ -686,12 +713,14 @@ if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = BuildMI(MF, get(ARM::STR)).addReg(SrcReg, false, false, isKill) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR)) + .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(MF, get(ARM::LDR)).addReg(DstReg, true, false, false, isDead) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR)) + .addReg(DstReg, true, false, false, isDead) .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); } break; @@ -703,7 +732,8 @@ if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg)) // tSpill cannot take a high register operand. break; - NewMI = BuildMI(MF, get(ARM::tSpill)).addReg(SrcReg, false, false, isKill) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill)) + .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addImm(0); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); @@ -711,7 +741,7 @@ // tRestore cannot target a high register operand. break; bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(MF, get(ARM::tRestore)) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore)) .addReg(DstReg, true, false, false, isDead) .addFrameIndex(FI).addImm(0); } @@ -722,11 +752,13 @@ unsigned PredReg = MI->getOperand(3).getReg(); if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); - NewMI = BuildMI(MF, get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS)) + .addReg(SrcReg).addFrameIndex(FI) .addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); - NewMI = BuildMI(MF, get(ARM::FLDS), DstReg).addFrameIndex(FI) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS), DstReg) + .addFrameIndex(FI) .addImm(0).addImm(Pred).addReg(PredReg); } break; @@ -737,12 +769,14 @@ if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = BuildMI(MF, get(ARM::FSTD)).addReg(SrcReg, false, false, isKill) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD)) + .addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(MF, get(ARM::FLDD)).addReg(DstReg, true, false, false, isDead) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD)) + .addReg(DstReg, true, false, false, isDead) .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); } break; Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Sat Feb 14 07:20:23 2009 @@ -116,6 +116,8 @@ ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, SmallVector, 8> &Regs, const TargetInstrInfo *TII) { + // FIXME would it be better to take a DL from one of the loads arbitrarily? + DebugLoc dl = DebugLoc::getUnknownLoc(); // Only a single register to load / store. Don't bother. unsigned NumRegs = Regs.size(); if (NumRegs <= 1) @@ -156,7 +158,7 @@ if (ImmedOffset == -1) return false; // Probably not worth it then. - BuildMI(MBB, MBBI, TII->get(BaseOpc), NewBase) + BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase) .addReg(Base, false, false, BaseKill).addImm(ImmedOffset) .addImm(Pred).addReg(PredReg).addReg(0); Base = NewBase; @@ -167,9 +169,11 @@ bool isDef = Opcode == ARM::LDR || Opcode == ARM::FLDS || Opcode == ARM::FLDD; Opcode = getLoadStoreMultipleOpcode(Opcode); MachineInstrBuilder MIB = (isAM4) - ? BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill) + ? BuildMI(MBB, MBBI, dl, TII->get(Opcode)) + .addReg(Base, false, false, BaseKill) .addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred).addReg(PredReg) - : BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill) + : BuildMI(MBB, MBBI, dl, TII->get(Opcode)) + .addReg(Base, false, false, BaseKill) .addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs)) .addImm(Pred).addReg(PredReg); for (unsigned i = 0; i != NumRegs; ++i) @@ -450,6 +454,7 @@ bool BaseKill = MI->getOperand(1).isKill(); unsigned Bytes = getLSMultipleTransferSize(MI); int Opcode = MI->getOpcode(); + DebugLoc dl = MI->getDebugLoc(); bool isAM2 = Opcode == ARM::LDR || Opcode == ARM::STR; if ((isAM2 && ARM_AM::getAM2Offset(MI->getOperand(3).getImm()) != 0) || (!isAM2 && ARM_AM::getAM5Offset(MI->getOperand(2).getImm()) != 0)) @@ -510,24 +515,25 @@ if (isLd) { if (isAM2) // LDR_PRE, LDR_POST; - BuildMI(MBB, MBBI, TII->get(NewOpc), MI->getOperand(0).getReg()) + BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) .addReg(Base, true) .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg); else // FLDMS, FLDMD - BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base, false, false, BaseKill) + BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) + .addReg(Base, false, false, BaseKill) .addImm(Offset).addImm(Pred).addReg(PredReg) .addReg(MI->getOperand(0).getReg(), true); } else { MachineOperand &MO = MI->getOperand(0); if (isAM2) // STR_PRE, STR_POST; - BuildMI(MBB, MBBI, TII->get(NewOpc), Base) + BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base) .addReg(MO.getReg(), false, false, MO.isKill()) .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg); else // FSTMS, FSTMD - BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base).addImm(Offset) + BuildMI(MBB, MBBI, dl, TII->get(NewOpc)).addReg(Base).addImm(Offset) .addImm(Pred).addReg(PredReg) .addReg(MO.getReg(), false, false, MO.isKill()); } Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.cpp Sat Feb 14 07:20:23 2009 @@ -179,15 +179,18 @@ unsigned DestReg, int Val, unsigned Pred, unsigned PredReg, const TargetInstrInfo *TII, - bool isThumb) const { + bool isThumb, + DebugLoc dl) const { MachineFunction &MF = *MBB.getParent(); MachineConstantPool *ConstantPool = MF.getConstantPool(); Constant *C = ConstantInt::get(Type::Int32Ty, Val); unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); if (isThumb) - BuildMI(MBB, MBBI, TII->get(ARM::tLDRcp),DestReg).addConstantPoolIndex(Idx); + BuildMI(MBB, MBBI, dl, + TII->get(ARM::tLDRcp),DestReg).addConstantPoolIndex(Idx); else - BuildMI(MBB, MBBI, TII->get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx) + BuildMI(MBB, MBBI, dl, TII->get(ARM::LDRcp), DestReg) + .addConstantPoolIndex(Idx) .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); } @@ -321,7 +324,8 @@ MachineBasicBlock::iterator &MBBI, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, - const TargetInstrInfo &TII) { + const TargetInstrInfo &TII, + DebugLoc dl) { bool isSub = NumBytes < 0; if (isSub) NumBytes = -NumBytes; @@ -338,7 +342,7 @@ assert(SOImmVal != -1 && "Bit extraction didn't work?"); // Build the new ADD / SUB. - BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) + BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) .addReg(BaseReg, false, false, true).addImm(SOImmVal) .addImm((unsigned)Pred).addReg(PredReg).addReg(0); BaseReg = DestReg; @@ -379,7 +383,8 @@ unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, - const ARMRegisterInfo& MRI) { + const ARMRegisterInfo& MRI, + DebugLoc dl) { bool isHigh = !MRI.isLowRegister(DestReg) || (BaseReg != 0 && !MRI.isLowRegister(BaseReg)); bool isSub = false; @@ -395,28 +400,30 @@ if (DestReg == ARM::SP) { assert(BaseReg == ARM::SP && "Unexpected!"); LdReg = ARM::R3; - BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12) + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R12) .addReg(ARM::R3, false, false, true); } if (NumBytes <= 255 && NumBytes >= 0) - BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); else if (NumBytes < 0 && NumBytes >= -255) { - BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); - BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg) + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); + BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg) .addReg(LdReg, false, false, true); } else - MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0,&TII,true); + MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, &TII, + true, dl); // Emit add / sub. int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); - const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg); + const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, + TII.get(Opc), DestReg); if (DestReg == ARM::SP || isSub) MIB.addReg(BaseReg).addReg(LdReg, false, false, true); else MIB.addReg(LdReg).addReg(BaseReg, false, false, true); if (DestReg == ARM::SP) - BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3) + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R3) .addReg(ARM::R12, false, false, true); } @@ -427,7 +434,8 @@ MachineBasicBlock::iterator &MBBI, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, - const ARMRegisterInfo& MRI) { + const ARMRegisterInfo& MRI, + DebugLoc dl) { bool isSub = NumBytes < 0; unsigned Bytes = (unsigned)NumBytes; if (isSub) Bytes = -NumBytes; @@ -473,7 +481,8 @@ if (NumMIs > Threshold) { // This will expand into too many instructions. Load the immediate from a // constpool entry. - emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII, MRI); + emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII, + MRI, dl); return; } @@ -483,10 +492,10 @@ unsigned Chunk = (1 << 3) - 1; unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; Bytes -= ThisVal; - BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) + BuildMI(MBB, MBBI, dl,TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) .addReg(BaseReg, false, false, true).addImm(ThisVal); } else { - BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg) + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) .addReg(BaseReg, false, false, true); } BaseReg = DestReg; @@ -499,10 +508,11 @@ ThisVal /= Scale; // Build the new tADD / tSUB. if (isTwoAddr) - BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); + BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) + .addReg(DestReg).addImm(ThisVal); else { bool isKill = BaseReg != ARM::SP; - BuildMI(MBB, MBBI, TII.get(Opc), DestReg) + BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) .addReg(BaseReg, false, false, isKill).addImm(ThisVal); BaseReg = DestReg; @@ -520,7 +530,7 @@ } if (ExtraOpc) - BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg) + BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg) .addReg(DestReg, false, false, true) .addImm(((unsigned)NumBytes) & 3); } @@ -529,12 +539,14 @@ void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, bool isThumb, const TargetInstrInfo &TII, - const ARMRegisterInfo& MRI) { + const ARMRegisterInfo& MRI, + DebugLoc dl) { if (isThumb) - emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII, MRI); + emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII, + MRI, dl); else emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, - Pred, PredReg, TII); + Pred, PredReg, TII, dl); } void ARMRegisterInfo:: @@ -545,6 +557,7 @@ // ADJCALLSTACKDOWN -> sub, sp, sp, amount // ADJCALLSTACKUP -> add, sp, sp, amount MachineInstr *Old = I; + DebugLoc dl = Old->getDebugLoc(); unsigned Amount = Old->getOperand(0).getImm(); if (Amount != 0) { ARMFunctionInfo *AFI = MF.getInfo(); @@ -562,12 +575,12 @@ if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg(); - emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII, *this); + emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII, *this, dl); } else { // Note: PredReg is operand 3 for ADJCALLSTACKUP. unsigned PredReg = isThumb ? 0 : Old->getOperand(3).getReg(); assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); - emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII, *this); + emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII, *this, dl); } } } @@ -580,18 +593,19 @@ MachineBasicBlock::iterator &MBBI, unsigned DestReg, int Imm, const TargetInstrInfo &TII, - const ARMRegisterInfo& MRI) { + const ARMRegisterInfo& MRI, + DebugLoc dl) { bool isSub = Imm < 0; if (isSub) Imm = -Imm; int Chunk = (1 << 8) - 1; int ThisVal = (Imm > Chunk) ? Chunk : Imm; Imm -= ThisVal; - BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal); + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal); if (Imm > 0) - emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI); + emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl); if (isSub) - BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg) + BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), DestReg) .addReg(DestReg, false, false, true); } @@ -617,6 +631,7 @@ MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo(); bool isThumb = AFI->isThumbFunction(); + DebugLoc dl = MI.getDebugLoc(); while (!MI.getOperand(i).isFI()) { ++i; @@ -723,7 +738,8 @@ // MI would expand into a large number of instructions. Don't try to // simplify the immediate. if (NumMIs > 2) { - emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII, *this); + emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII, + *this, dl); MBB.erase(II); return; } @@ -736,12 +752,13 @@ MI.getOperand(i+1).ChangeToImmediate(Mask); Offset = (Offset - Mask * Scale); MachineBasicBlock::iterator NII = next(II); - emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII, *this); + emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII, + *this, dl); } else { // Translate r0 = add sp, -imm to // r0 = -imm (this is then translated into a series of instructons) // r0 = add r0, sp - emitThumbConstant(MBB, II, DestReg, Offset, TII, *this); + emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl); MI.setDesc(TII.get(ARM::tADDhirr)); MI.getOperand(i).ChangeToRegister(DestReg, false, false, true); MI.getOperand(i+1).ChangeToRegister(FrameReg, false); @@ -845,13 +862,15 @@ if (Opcode == ARM::tRestore) { if (FrameReg == ARM::SP) emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg, - Offset, false, TII, *this); + Offset, false, TII, *this, dl); else { - emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, true); + emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, + true, dl); UseRR = true; } } else - emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, *this); + emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, + *this, dl); MI.setDesc(TII.get(ARM::tLDR)); MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); if (UseRR) @@ -872,23 +891,25 @@ unsigned TmpReg = ARM::R3; bool UseRR = false; if (ValReg == ARM::R3) { - BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) + BuildMI(MBB, II, dl, TII.get(ARM::tMOVr), ARM::R12) .addReg(ARM::R2, false, false, true); TmpReg = ARM::R2; } if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) - BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) + BuildMI(MBB, II, dl, TII.get(ARM::tMOVr), ARM::R12) .addReg(ARM::R3, false, false, true); if (Opcode == ARM::tSpill) { if (FrameReg == ARM::SP) emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg, - Offset, false, TII, *this); + Offset, false, TII, *this, dl); else { - emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, true); + emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, + true, dl); UseRR = true; } } else - emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, *this); + emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, + *this, dl); MI.setDesc(TII.get(ARM::tSTR)); MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); if (UseRR) // Use [reg, reg] addrmode. @@ -898,10 +919,10 @@ MachineBasicBlock::iterator NII = next(II); if (ValReg == ARM::R3) - BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2) + BuildMI(MBB, NII, dl, TII.get(ARM::tMOVr), ARM::R2) .addReg(ARM::R12, false, false, true); if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) - BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3) + BuildMI(MBB, NII, dl, TII.get(ARM::tMOVr), ARM::R3) .addReg(ARM::R12, false, false, true); } else assert(false && "Unexpected opcode!"); @@ -919,7 +940,7 @@ ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, - isSub ? -Offset : Offset, Pred, PredReg, TII); + isSub ? -Offset : Offset, Pred, PredReg, TII, dl); MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); } } @@ -1201,6 +1222,7 @@ unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); unsigned NumBytes = MFI->getStackSize(); const std::vector &CSI = MFI->getCalleeSavedInfo(); + DebugLoc dl = DebugLoc::getUnknownLoc(); if (isThumb) { // Check if R3 is live in. It might have to be used as a scratch register. @@ -1223,11 +1245,12 @@ int FramePtrSpillFI = 0; if (VARegSaveSize) - emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII, *this); + emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII, + *this, dl); if (!AFI->hasStackFrame()) { if (NumBytes != 0) - emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this); + emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl); return; } @@ -1267,7 +1290,7 @@ if (!isThumb) { // Build the new SUBri to adjust SP for integer callee-save spill area 1. - emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII, *this); + emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII, *this, dl); movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) ++MBBI; @@ -1276,18 +1299,19 @@ // previous FP. if (STI.isTargetDarwin() || hasFP(MF)) { MachineInstrBuilder MIB = - BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr) + BuildMI(MBB, MBBI, dl, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), + FramePtr) .addFrameIndex(FramePtrSpillFI).addImm(0); if (!isThumb) AddDefaultCC(AddDefaultPred(MIB)); } if (!isThumb) { // Build the new SUBri to adjust SP for integer callee-save spill area 2. - emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII, *this); + emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII, *this, dl); // Build the new SUBri to adjust SP for FP callee-save spill area. movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); - emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII, *this); + emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII, *this, dl); } // Determine starting offsets of spill areas. @@ -1304,7 +1328,7 @@ // Insert it after all the callee-save spills. if (!isThumb) movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); - emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this); + emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl); } if(STI.isTargetELF() && hasFP(MF)) { @@ -1334,6 +1358,7 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { + DebugLoc dl = DebugLoc::getUnknownLoc(); MachineBasicBlock::iterator MBBI = prior(MBB.end()); assert((MBBI->getOpcode() == ARM::BX_RET || MBBI->getOpcode() == ARM::tBX_RET || @@ -1347,7 +1372,7 @@ int NumBytes = (int)MFI->getStackSize(); if (!AFI->hasStackFrame()) { if (NumBytes != 0) - emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this); + emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl); } else { // Unwind MBBI to point to first LDR / FLDD. const unsigned *CSRegs = getCalleeSavedRegs(); @@ -1370,17 +1395,19 @@ // frame pointer stack slot or target is ELF and the function has FP. if (NumBytes) emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, - TII, *this); + TII, *this, dl); else - BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr); + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr); } else { if (MBBI->getOpcode() == ARM::tBX_RET && &MBB.front() != MBBI && prior(MBBI)->getOpcode() == ARM::tPOP) { MachineBasicBlock::iterator PMBBI = prior(MBBI); - emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this); + emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, + *this, dl); } else - emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this); + emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, + *this, dl); } } else { // Darwin ABI requires FP to point to the stack slot that contains the @@ -1394,31 +1421,31 @@ AFI->getDPRCalleeSavedAreaOffset()|| hasFP(MF)) { if (NumBytes) - BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) + BuildMI(MBB, MBBI, dl, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) .addImm(NumBytes) .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); else - BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr) + BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr) .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); } } else if (NumBytes) { - emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII, *this); + emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII, *this, dl); } // Move SP to start of integer callee save spill area 2. movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0, - false, TII, *this); + false, TII, *this, dl); // Move SP to start of integer callee save spill area 1. movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0, - false, TII, *this); + false, TII, *this, dl); // Move SP to SP upon entry to the function. movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0, - false, TII, *this); + false, TII, *this, dl); } } @@ -1426,12 +1453,13 @@ if (isThumb) // Epilogue for vararg functions: pop LR to R3 and branch off it. // FIXME: Verify this is still ok when R3 is no longer being reserved. - BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3); + BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)).addReg(ARM::R3); - emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII, *this); + emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII, + *this, dl); if (isThumb) { - BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); + BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); MBB.erase(MBBI); } } Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.h?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.h (original) +++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.h Sat Feb 14 07:20:23 2009 @@ -38,7 +38,8 @@ MachineBasicBlock::iterator &MBBI, unsigned DestReg, int Val, unsigned Pred, unsigned PredReg, - const TargetInstrInfo *TII, bool isThumb) const; + const TargetInstrInfo *TII, bool isThumb, + DebugLoc dl) const; /// getRegisterNumbering - Given the enum value for some register, e.g. /// ARM::LR, return the number that it corresponds to (e.g. 14). Modified: llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelDAGToDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelDAGToDAG.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Sat Feb 14 07:20:23 2009 @@ -204,8 +204,9 @@ break; } assert(GP && "GOT PTR not in liveins"); + // FIXME is there anywhere sensible to get a DebugLoc here? return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), - GP, MVT::i64); + DebugLoc::getUnknownLoc(), GP, MVT::i64); } /// getRASaveReg - Grab the return address @@ -219,8 +220,9 @@ break; } assert(RA && "RA PTR not in liveins"); + // FIXME is there anywhere sensible to get a DebugLoc here? return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), - RA, MVT::i64); + DebugLoc::getUnknownLoc(), RA, MVT::i64); } /// InstructionSelect - This callback is invoked by @@ -240,6 +242,7 @@ if (N->isMachineOpcode()) { return NULL; // Already selected. } + DebugLoc dl = N->getDebugLoc(); switch (N->getOpcode()) { default: break; @@ -269,23 +272,23 @@ SDValue N0 = Op.getOperand(0); SDValue N1 = Op.getOperand(1); SDValue N2 = Op.getOperand(2); - Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1, + Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R24, N1, SDValue(0,0)); - Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2, + Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R25, N2, Chain.getValue(1)); - Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0, + Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, N0, Chain.getValue(1)); SDNode *CNode = - CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag, + CurDAG->getTargetNode(Alpha::JSRs, dl, MVT::Other, MVT::Flag, Chain, Chain.getValue(1)); - Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64, + Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, MVT::i64, SDValue(CNode, 1)); return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain); } case ISD::READCYCLECOUNTER: { SDValue Chain = N->getOperand(0); - return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other, + return CurDAG->getTargetNode(Alpha::RPCC, dl, MVT::i64, MVT::Other, Chain); } @@ -293,7 +296,7 @@ uint64_t uval = cast(N)->getZExtValue(); if (uval == 0) { - SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), + SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, Alpha::R31, MVT::i64); ReplaceUses(Op, Result); return NULL; @@ -311,7 +314,7 @@ //Else use the constant pool ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval); SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64); - SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, + SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, dl, MVT::i64, CPI, getGlobalBaseReg()); return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, CPI, SDValue(Tmp, 0), CurDAG->getEntryNode()); @@ -363,25 +366,27 @@ }; SDValue tmp1 = N->getOperand(rev?1:0); SDValue tmp2 = N->getOperand(rev?0:1); - SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64, tmp1, tmp2); + SDNode *cmp = CurDAG->getTargetNode(Opc, dl, MVT::f64, tmp1, tmp2); if (inv) - cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDValue(cmp, 0), + cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, dl, + MVT::f64, SDValue(cmp, 0), CurDAG->getRegister(Alpha::F31, MVT::f64)); switch(CC) { case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE: case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE: { - SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64, + SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, dl, MVT::f64, tmp1, tmp2); - cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64, + cmp = CurDAG->getTargetNode(Alpha::ADDT, dl, MVT::f64, SDValue(cmp2, 0), SDValue(cmp, 0)); break; } default: break; } - SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, SDValue(cmp, 0)); - return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64, + SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, dl, + MVT::i64, SDValue(cmp, 0)); + return CurDAG->getTargetNode(Alpha::CMPULT, dl, MVT::i64, CurDAG->getRegister(Alpha::R31, MVT::i64), SDValue(LD,0)); } @@ -400,9 +405,9 @@ SDValue TV = N->getOperand(1); SDValue FV = N->getOperand(2); - SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, MVT::f64, cond); + SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, dl, MVT::f64, cond); return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES, - MVT::f64, FV, TV, SDValue(LD,0)); + dl, MVT::f64, FV, TV, SDValue(LD,0)); } break; @@ -427,10 +432,10 @@ if (get_zapImm(mask)) { SDValue Z = - SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64, + SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, dl, MVT::i64, N->getOperand(0).getOperand(0), getI64Imm(get_zapImm(mask))), 0); - return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z, + return CurDAG->getTargetNode(Alpha::SRLr, dl, MVT::i64, Z, getI64Imm(sval)); } } @@ -449,6 +454,7 @@ SDValue Chain = N->getOperand(0); SDValue Addr = N->getOperand(1); SDValue InFlag(0,0); // Null incoming flag value. + DebugLoc dl = N->getDebugLoc(); std::vector CallOperands; std::vector TypeOperands; @@ -477,16 +483,18 @@ assert(0 && "Unknown operand"); SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8), - CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64), - Chain }; - Chain = SDValue(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0); + CurDAG->getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64), + Chain }; + Chain = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 4), 0); } for (int i = 0; i < std::min(6, count); ++i) { if (TypeOperands[i].isInteger()) { - Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag); + Chain = CurDAG->getCopyToReg(Chain, dl, args_int[i], + CallOperands[i], InFlag); InFlag = Chain.getValue(1); } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) { - Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag); + Chain = CurDAG->getCopyToReg(Chain, dl, args_float[i], + CallOperands[i], InFlag); InFlag = Chain.getValue(1); } else assert(0 && "Unknown operand"); @@ -496,15 +504,16 @@ // call itself. if (Addr.getOpcode() == AlphaISD::GPRelLo) { SDValue GOT = getGlobalBaseReg(); - Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag); + Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R29, GOT, InFlag); InFlag = Chain.getValue(1); - Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag, - Addr.getOperand(0), Chain, InFlag), 0); + Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, dl, MVT::Other, + MVT::Flag, Addr.getOperand(0), + Chain, InFlag), 0); } else { - Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag); + Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, Addr, InFlag); InFlag = Chain.getValue(1); - Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag, - Chain, InFlag), 0); + Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, dl, MVT::Other, + MVT::Flag, Chain, InFlag), 0); } InFlag = Chain.getValue(1); @@ -514,15 +523,18 @@ default: assert(0 && "Unexpected ret value!"); case MVT::Other: break; case MVT::i64: - Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1); + Chain = CurDAG->getCopyFromReg(Chain, dl, + Alpha::R0, MVT::i64, InFlag).getValue(1); CallResults.push_back(Chain.getValue(0)); break; case MVT::f32: - Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1); + Chain = CurDAG->getCopyFromReg(Chain, dl, + Alpha::F0, MVT::f32, InFlag).getValue(1); CallResults.push_back(Chain.getValue(0)); break; case MVT::f64: - Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1); + Chain = CurDAG->getCopyFromReg(Chain, dl, + Alpha::F0, MVT::f64, InFlag).getValue(1); CallResults.push_back(Chain.getValue(0)); break; } Modified: llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelLowering.cpp Sat Feb 14 07:20:23 2009 @@ -186,10 +186,12 @@ JumpTableSDNode *JT = cast(Op); SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); SDValue Zero = DAG.getConstant(0, PtrVT); + // FIXME there isn't really any debug info here + DebugLoc dl = Op.getDebugLoc(); - SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI, - DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); - SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi); + SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI, + DAG.getGLOBAL_OFFSET_TABLE(MVT::i64)); + SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi); return Lo; } @@ -219,6 +221,7 @@ MachineFrameInfo *MFI = MF.getFrameInfo(); std::vector ArgValues; SDValue Root = Op.getOperand(0); + DebugLoc dl = Op.getDebugLoc(); AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA @@ -240,17 +243,17 @@ case MVT::f64: args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo], &Alpha::F8RCRegClass); - ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT); + ArgVal = DAG.getCopyFromReg(Root, dl, args_float[ArgNo], ObjectVT); break; case MVT::f32: args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo], &Alpha::F4RCRegClass); - ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT); + ArgVal = DAG.getCopyFromReg(Root, dl, args_float[ArgNo], ObjectVT); break; case MVT::i64: args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo], &Alpha::GPRCRegClass); - ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64); + ArgVal = DAG.getCopyFromReg(Root, dl, args_int[ArgNo], MVT::i64); break; } } else { //more args @@ -260,7 +263,7 @@ // Create the SelectionDAG nodes corresponding to a load //from this parameter SDValue FIN = DAG.getFrameIndex(FI, MVT::i64); - ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); + ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0); } ArgValues.push_back(ArgVal); } @@ -273,34 +276,36 @@ for (int i = 0; i < 6; ++i) { if (TargetRegisterInfo::isPhysicalRegister(args_int[i])) args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass); - SDValue argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64); + SDValue argt = DAG.getCopyFromReg(Root, dl, args_int[i], MVT::i64); int FI = MFI->CreateFixedObject(8, -8 * (6 - i)); if (i == 0) VarArgsBase = FI; SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64); - LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0)); + LS.push_back(DAG.getStore(Root, dl, argt, SDFI, NULL, 0)); if (TargetRegisterInfo::isPhysicalRegister(args_float[i])) args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass); - argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64); + argt = DAG.getCopyFromReg(Root, dl, args_float[i], MVT::f64); FI = MFI->CreateFixedObject(8, - 8 * (12 - i)); SDFI = DAG.getFrameIndex(FI, MVT::i64); - LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0)); + LS.push_back(DAG.getStore(Root, dl, argt, SDFI, NULL, 0)); } //Set up a token factor with all the stack traffic - Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size()); + Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LS[0], LS.size()); } ArgValues.push_back(Root); // Return the new list of results. - return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), &ArgValues[0], ArgValues.size()); } static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { - SDValue Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26, + DebugLoc dl = Op.getDebugLoc(); + SDValue Copy = DAG.getCopyToReg(Op.getOperand(0), dl, Alpha::R26, DAG.getNode(AlphaISD::GlobalRetAddr, + DebugLoc::getUnknownLoc(), MVT::i64), SDValue()); switch (Op.getNumOperands()) { @@ -319,7 +324,8 @@ assert(ArgVT.isFloatingPoint()); ArgReg = Alpha::F0; } - Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1)); + Copy = DAG.getCopyToReg(Copy, dl, ArgReg, + Op.getOperand(1), Copy.getValue(1)); if (DAG.getMachineFunction().getRegInfo().liveout_empty()) DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg); break; @@ -335,12 +341,14 @@ ArgReg1 = Alpha::F0; ArgReg2 = Alpha::F1; } - Copy = DAG.getCopyToReg(Copy, ArgReg1, Op.getOperand(1), Copy.getValue(1)); + Copy = DAG.getCopyToReg(Copy, dl, ArgReg1, + Op.getOperand(1), Copy.getValue(1)); if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(), DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1) == DAG.getMachineFunction().getRegInfo().liveout_end()) DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1); - Copy = DAG.getCopyToReg(Copy, ArgReg2, Op.getOperand(3), Copy.getValue(1)); + Copy = DAG.getCopyToReg(Copy, dl, ArgReg2, + Op.getOperand(3), Copy.getValue(1)); if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(), DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2) == DAG.getMachineFunction().getRegInfo().liveout_end()) @@ -348,7 +356,8 @@ break; } } - return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); + return DAG.getNode(AlphaISD::RET_FLAG, dl, + MVT::Other, Copy, Copy.getValue(1)); } std::pair @@ -434,32 +443,34 @@ Chain = N->getOperand(0); SDValue VAListP = N->getOperand(1); const Value *VAListS = cast(N->getOperand(2))->getValue(); + DebugLoc dl = N->getDebugLoc(); - SDValue Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0); - SDValue Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP, + SDValue Base = DAG.getLoad(MVT::i64, dl, Chain, VAListP, VAListS, 0); + SDValue Tmp = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP, DAG.getConstant(8, MVT::i64)); - SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1), + SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Base.getValue(1), Tmp, NULL, 0, MVT::i32); - DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset); + DataPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Base, Offset); if (N->getValueType(0).isFloatingPoint()) { //if fp && Offset < 6*8, then subtract 6*8 from DataPtr - SDValue FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr, + SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, MVT::i64, DataPtr, DAG.getConstant(8*6, MVT::i64)); - SDValue CC = DAG.getSetCC(MVT::i64, Offset, + SDValue CC = DAG.getSetCC(dl, MVT::i64, Offset, DAG.getConstant(8*6, MVT::i64), ISD::SETLT); - DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr); + DataPtr = DAG.getNode(ISD::SELECT, dl, MVT::i64, CC, FPDataPtr, DataPtr); } - SDValue NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset, + SDValue NewOffset = DAG.getNode(ISD::ADD, dl, MVT::i64, Offset, DAG.getConstant(8, MVT::i64)); - Chain = DAG.getTruncStore(Offset.getValue(1), NewOffset, Tmp, NULL, 0, + Chain = DAG.getTruncStore(Offset.getValue(1), dl, NewOffset, Tmp, NULL, 0, MVT::i32); } /// LowerOperation - Provide custom lowering hooks for some operations. /// SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); switch (Op.getOpcode()) { default: assert(0 && "Wasn't expecting to be able to lower this!"); case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG, @@ -474,7 +485,8 @@ switch (IntNo) { default: break; // Don't custom lower most intrinsics. case Intrinsic::alpha_umulh: - return DAG.getNode(ISD::MULHU, MVT::i64, Op.getOperand(1), Op.getOperand(2)); + return DAG.getNode(ISD::MULHU, dl, MVT::i64, + Op.getOperand(1), Op.getOperand(2)); } } @@ -483,8 +495,8 @@ "Unhandled SINT_TO_FP type in custom expander!"); SDValue LD; bool isDouble = Op.getValueType() == MVT::f64; - LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); - SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, + LD = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op.getOperand(0)); + SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, dl, isDouble?MVT::f64:MVT::f32, LD); return FP; } @@ -493,20 +505,21 @@ SDValue src = Op.getOperand(0); if (!isDouble) //Promote - src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src); + src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, src); - src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src); + src = DAG.getNode(AlphaISD::CVTTQ_, dl, MVT::f64, src); - return DAG.getNode(ISD::BIT_CONVERT, MVT::i64, src); + return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, src); } case ISD::ConstantPool: { ConstantPoolSDNode *CP = cast(Op); Constant *C = CP->getConstVal(); SDValue CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment()); + // FIXME there isn't really any debug info here - SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI, - DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); - SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi); + SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, CPI, + DAG.getGLOBAL_OFFSET_TABLE(MVT::i64)); + SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, CPI, Hi); return Lo; } case ISD::GlobalTLSAddress: @@ -515,22 +528,23 @@ GlobalAddressSDNode *GSDN = cast(Op); GlobalValue *GV = GSDN->getGlobal(); SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset()); + // FIXME there isn't really any debug info here // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) { if (GV->hasLocalLinkage()) { - SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA, - DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); - SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi); + SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, GA, + DAG.getGLOBAL_OFFSET_TABLE(MVT::i64)); + SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, GA, Hi); return Lo; } else - return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, - DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); + return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64, GA, + DAG.getGLOBAL_OFFSET_TABLE(MVT::i64)); } case ISD::ExternalSymbol: { - return DAG.getNode(AlphaISD::RelLit, MVT::i64, + return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64, DAG.getTargetExternalSymbol(cast(Op) ->getSymbol(), MVT::i64), - DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); + DAG.getGLOBAL_OFFSET_TABLE(MVT::i64)); } case ISD::UREM: @@ -541,8 +555,8 @@ SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ? BuildUDIV(Op.getNode(), DAG, NULL) : BuildSDIV(Op.getNode(), DAG, NULL); - Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1)); - Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1); + Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Op.getOperand(1)); + Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Op.getOperand(0), Tmp1); return Tmp1; } //fall through @@ -562,7 +576,7 @@ SDValue Tmp1 = Op.getOperand(0), Tmp2 = Op.getOperand(1), Addr = DAG.getExternalSymbol(opstr, MVT::i64); - return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2); + return DAG.getNode(AlphaISD::DivCall, dl, MVT::i64, Addr, Tmp1, Tmp2); } break; @@ -572,10 +586,10 @@ SDValue Result; if (Op.getValueType() == MVT::i32) - Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Chain, DataPtr, + Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Chain, DataPtr, NULL, 0, MVT::i32); else - Result = DAG.getLoad(Op.getValueType(), Chain, DataPtr, NULL, 0); + Result = DAG.getLoad(Op.getValueType(), dl, Chain, DataPtr, NULL, 0); return Result; } case ISD::VACOPY: { @@ -585,14 +599,15 @@ const Value *DestS = cast(Op.getOperand(3))->getValue(); const Value *SrcS = cast(Op.getOperand(4))->getValue(); - SDValue Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0); - SDValue Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0); - SDValue NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP, + SDValue Val = DAG.getLoad(getPointerTy(), dl, Chain, SrcP, SrcS, 0); + SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP, DestS, 0); + SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP, DAG.getConstant(8, MVT::i64)); - Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32); - SDValue NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP, + Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Result, + NP, NULL,0, MVT::i32); + SDValue NPD = DAG.getNode(ISD::ADD, dl, MVT::i64, DestP, DAG.getConstant(8, MVT::i64)); - return DAG.getTruncStore(Val.getValue(1), Val, NPD, NULL, 0, MVT::i32); + return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD, NULL, 0, MVT::i32); } case ISD::VASTART: { SDValue Chain = Op.getOperand(0); @@ -601,14 +616,15 @@ // vastart stores the address of the VarArgsBase and VarArgsOffset SDValue FR = DAG.getFrameIndex(VarArgsBase, MVT::i64); - SDValue S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0); - SDValue SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP, + SDValue S1 = DAG.getStore(Chain, dl, FR, VAListP, VAListS, 0); + SDValue SA2 = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP, DAG.getConstant(8, MVT::i64)); - return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64), + return DAG.getTruncStore(S1, dl, DAG.getConstant(VarArgsOffset, MVT::i64), SA2, NULL, 0, MVT::i32); } case ISD::RETURNADDR: - return DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64); + return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc::getUnknownLoc(), + MVT::i64); //FIXME: implement case ISD::FRAMEADDR: break; } @@ -619,13 +635,14 @@ void AlphaTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl&Results, SelectionDAG &DAG) { + DebugLoc dl = N->getDebugLoc(); assert(N->getValueType(0) == MVT::i32 && N->getOpcode() == ISD::VAARG && "Unknown node to custom promote!"); SDValue Chain, DataPtr; LowerVAARG(N, Chain, DataPtr, DAG); - SDValue Res = DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL, 0); + SDValue Res = DAG.getLoad(N->getValueType(0), dl, Chain, DataPtr, NULL, 0); Results.push_back(Res); Results.push_back(SDValue(Res.getNode(), 1)); } @@ -711,6 +728,7 @@ //test sc and maybe branck to start //exit: const BasicBlock *LLVM_BB = BB->getBasicBlock(); + DebugLoc dl = MI->getDebugLoc(); MachineFunction::iterator It = BB; ++It; @@ -724,46 +742,46 @@ F->insert(It, llscMBB); F->insert(It, sinkMBB); - BuildMI(thisMBB, TII->get(Alpha::BR)).addMBB(llscMBB); + BuildMI(thisMBB, dl, TII->get(Alpha::BR)).addMBB(llscMBB); unsigned reg_res = MI->getOperand(0).getReg(), reg_ptr = MI->getOperand(1).getReg(), reg_v2 = MI->getOperand(2).getReg(), reg_store = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass); - BuildMI(llscMBB, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L), + BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L), reg_res).addImm(0).addReg(reg_ptr); switch (MI->getOpcode()) { case Alpha::CAS32: case Alpha::CAS64: { unsigned reg_cmp = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass); - BuildMI(llscMBB, TII->get(Alpha::CMPEQ), reg_cmp) + BuildMI(llscMBB, dl, TII->get(Alpha::CMPEQ), reg_cmp) .addReg(reg_v2).addReg(reg_res); - BuildMI(llscMBB, TII->get(Alpha::BEQ)) + BuildMI(llscMBB, dl, TII->get(Alpha::BEQ)) .addImm(0).addReg(reg_cmp).addMBB(sinkMBB); - BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store) + BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store) .addReg(Alpha::R31).addReg(MI->getOperand(3).getReg()); break; } case Alpha::LAS32: case Alpha::LAS64: { - BuildMI(llscMBB, TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store) + BuildMI(llscMBB, dl,TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store) .addReg(reg_res).addReg(reg_v2); break; } case Alpha::SWAP32: case Alpha::SWAP64: { - BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store) + BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store) .addReg(reg_v2).addReg(reg_v2); break; } } - BuildMI(llscMBB, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store) + BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store) .addReg(reg_store).addImm(0).addReg(reg_ptr); - BuildMI(llscMBB, TII->get(Alpha::BEQ)) + BuildMI(llscMBB, dl, TII->get(Alpha::BEQ)) .addImm(0).addReg(reg_store).addMBB(llscMBB); - BuildMI(llscMBB, TII->get(Alpha::BR)).addMBB(sinkMBB); + BuildMI(llscMBB, dl, TII->get(Alpha::BR)).addMBB(sinkMBB); thisMBB->addSuccessor(llscMBB); llscMBB->addSuccessor(llscMBB); Modified: llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.cpp Sat Feb 14 07:20:23 2009 @@ -105,9 +105,11 @@ } unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB, - MachineBasicBlock *TBB, - MachineBasicBlock *FBB, + MachineBasicBlock *TBB, + MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const { + // FIXME this should probably have a DebugLoc argument + DebugLoc dl = DebugLoc::getUnknownLoc(); assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && "Alpha branch conditions have two components!"); @@ -115,45 +117,54 @@ // One-way branch. if (FBB == 0) { if (Cond.empty()) // Unconditional branch - BuildMI(&MBB, get(Alpha::BR)).addMBB(TBB); + BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(TBB); else // Conditional branch if (isAlphaIntCondCode(Cond[0].getImm())) - BuildMI(&MBB, get(Alpha::COND_BRANCH_I)) + BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); else - BuildMI(&MBB, get(Alpha::COND_BRANCH_F)) + BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); return 1; } // Two-way Conditional Branch. if (isAlphaIntCondCode(Cond[0].getImm())) - BuildMI(&MBB, get(Alpha::COND_BRANCH_I)) + BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); else - BuildMI(&MBB, get(Alpha::COND_BRANCH_F)) + BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); - BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB); + BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(FBB); return 2; } bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n"; if (DestRC != SrcRC) { // Not yet supported! return false; } + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if (DestRC == Alpha::GPRCRegisterClass) { - BuildMI(MBB, MI, get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(Alpha::BISr), DestReg) + .addReg(SrcReg) + .addReg(SrcReg); } else if (DestRC == Alpha::F4RCRegisterClass) { - BuildMI(MBB, MI, get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(Alpha::CPYSS), DestReg) + .addReg(SrcReg) + .addReg(SrcReg); } else if (DestRC == Alpha::F8RCRegisterClass) { - BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(Alpha::CPYST), DestReg) + .addReg(SrcReg) + .addReg(SrcReg); } else { // Attempt to copy register that is not GPR or FPR return false; @@ -164,22 +175,26 @@ void AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned SrcReg, bool isKill, int FrameIdx, - const TargetRegisterClass *RC) const { + MachineBasicBlock::iterator MI, + unsigned SrcReg, bool isKill, int FrameIdx, + const TargetRegisterClass *RC) const { //cerr << "Trying to store " << getPrettyName(SrcReg) << " to " // << FrameIdx << "\n"; //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); + + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if (RC == Alpha::F4RCRegisterClass) - BuildMI(MBB, MI, get(Alpha::STS)) + BuildMI(MBB, MI, DL, get(Alpha::STS)) .addReg(SrcReg, false, false, isKill) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::F8RCRegisterClass) - BuildMI(MBB, MI, get(Alpha::STT)) + BuildMI(MBB, MI, DL, get(Alpha::STT)) .addReg(SrcReg, false, false, isKill) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::GPRCRegisterClass) - BuildMI(MBB, MI, get(Alpha::STQ)) + BuildMI(MBB, MI, DL, get(Alpha::STQ)) .addReg(SrcReg, false, false, isKill) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else @@ -200,8 +215,9 @@ Opc = Alpha::STQ; else abort(); + DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = - BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill); + BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) @@ -219,14 +235,17 @@ const TargetRegisterClass *RC) const { //cerr << "Trying to load " << getPrettyName(DestReg) << " to " // << FrameIdx << "\n"; + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if (RC == Alpha::F4RCRegisterClass) - BuildMI(MBB, MI, get(Alpha::LDS), DestReg) + BuildMI(MBB, MI, DL, get(Alpha::LDS), DestReg) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::F8RCRegisterClass) - BuildMI(MBB, MI, get(Alpha::LDT), DestReg) + BuildMI(MBB, MI, DL, get(Alpha::LDT), DestReg) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::GPRCRegisterClass) - BuildMI(MBB, MI, get(Alpha::LDQ), DestReg) + BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else abort(); @@ -245,8 +264,9 @@ Opc = Alpha::LDQ; else abort(); + DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = - BuildMI(MF, get(Opc), DestReg); + BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) @@ -279,7 +299,8 @@ bool isKill = MI->getOperand(1).isKill(); Opc = (Opc == Alpha::BISr) ? Alpha::STQ : ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT); - NewMI = BuildMI(MF, get(Opc)).addReg(InReg, false, false, isKill) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) + .addReg(InReg, false, false, isKill) .addFrameIndex(FrameIndex) .addReg(Alpha::F31); } else { // load -> move @@ -287,7 +308,8 @@ bool isDead = MI->getOperand(0).isDead(); Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT); - NewMI = BuildMI(MF, get(Opc)).addReg(OutReg, true, false, false, isDead) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) + .addReg(OutReg, true, false, false, isDead) .addFrameIndex(FrameIndex) .addReg(Alpha::F31); } @@ -410,7 +432,10 @@ void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { - BuildMI(MBB, MI, get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + BuildMI(MBB, MI, DL, get(Alpha::BISr), Alpha::R31) + .addReg(Alpha::R31) .addReg(Alpha::R31); } Modified: llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaLLRP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaLLRP.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaLLRP.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaLLRP.cpp Sat Feb 14 07:20:23 2009 @@ -49,6 +49,7 @@ const TargetInstrInfo *TII = F.getTarget().getInstrInfo(); bool Changed = false; MachineInstr* prev[3] = {0,0,0}; + DebugLoc dl = DebugLoc::getUnknownLoc(); unsigned count = 0; for (MachineFunction::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) { @@ -73,7 +74,7 @@ prev[0] = prev[1]; prev[1] = prev[2]; prev[2] = 0; - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 1; @@ -85,10 +86,10 @@ MI->getOperand(1).getImm()) { prev[0] = prev[2]; prev[1] = prev[2] = 0; - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31) .addReg(Alpha::R31); - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 2; @@ -99,12 +100,12 @@ && prev[2]->getOperand(1).getImm() == MI->getOperand(1).getImm()) { prev[0] = prev[1] = prev[2] = 0; - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) - .addReg(Alpha::R31); - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) - .addReg(Alpha::R31); - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) - .addReg(Alpha::R31); + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) + .addReg(Alpha::R31).addReg(Alpha::R31); + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) + .addReg(Alpha::R31).addReg(Alpha::R31); + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) + .addReg(Alpha::R31).addReg(Alpha::R31); Changed = true; nopintro += 3; count += 3; } @@ -136,7 +137,7 @@ if (ub || AlignAll) { //we can align stuff for free at this point while (count % 4) { - BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MBB.end(), dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31).addReg(Alpha::R31); ++count; ++nopalign; Modified: llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaRegisterInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaRegisterInfo.cpp Sat Feb 14 07:20:23 2009 @@ -125,11 +125,11 @@ MachineInstr *New; if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) { - New=BuildMI(MF, TII.get(Alpha::LDA), Alpha::R30) + New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30) .addImm(-Amount).addReg(Alpha::R30); } else { assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP); - New=BuildMI(MF, TII.get(Alpha::LDA), Alpha::R30) + New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30) .addImm(Amount).addReg(Alpha::R30); } @@ -188,7 +188,8 @@ MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false); MI.getOperand(i).ChangeToImmediate(getLower16(Offset)); //insert the new - MachineInstr* nMI=BuildMI(MF, TII.get(Alpha::LDAH), Alpha::R28) + MachineInstr* nMI=BuildMI(MF, MI.getDebugLoc(), + TII.get(Alpha::LDAH), Alpha::R28) .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); MBB.insert(II, nMI); } else { @@ -201,20 +202,21 @@ MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); + DebugLoc dl = DebugLoc::getUnknownLoc(); bool FP = hasFP(MF); static int curgpdist = 0; //handle GOP offset - BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAHg), Alpha::R29) .addGlobalAddress(const_cast(MF.getFunction())) .addReg(Alpha::R27).addImm(++curgpdist); - BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAg), Alpha::R29) .addGlobalAddress(const_cast(MF.getFunction())) .addReg(Alpha::R29).addImm(curgpdist); //evil const_cast until MO stuff setup to handle const - BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT)) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::ALTENT)) .addGlobalAddress(const_cast(MF.getFunction())); // Get the number of bytes to allocate from the FrameInfo @@ -235,13 +237,13 @@ // adjust stack pointer: r30 -= numbytes NumBytes = -NumBytes; if (NumBytes >= IMM_LOW) { - BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) .addReg(Alpha::R30); } else if (getUpper16(NumBytes) >= IMM_LOW) { - BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes)) - .addReg(Alpha::R30); - BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes)) - .addReg(Alpha::R30); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30) + .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30) + .addImm(getLower16(NumBytes)).addReg(Alpha::R30); } else { cerr << "Too big a stack frame at " << NumBytes << "\n"; abort(); @@ -250,10 +252,10 @@ //now if we need to, save the old FP and set the new if (FP) { - BuildMI(MBB, MBBI, TII.get(Alpha::STQ)) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::STQ)) .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); //this must be the last instr in the prolog - BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R15) .addReg(Alpha::R30).addReg(Alpha::R30); } @@ -266,6 +268,7 @@ assert((MBBI->getOpcode() == Alpha::RETDAG || MBBI->getOpcode() == Alpha::RETDAGp) && "Can only insert epilog into returning blocks"); + DebugLoc dl = DebugLoc::getUnknownLoc(); bool FP = hasFP(MF); @@ -275,20 +278,21 @@ //now if we need to, restore the old FP if (FP) { //copy the FP into the SP (discards allocas) - BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) .addReg(Alpha::R15); //restore the FP - BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDQ), Alpha::R15) + .addImm(0).addReg(Alpha::R15); } if (NumBytes != 0) { if (NumBytes <= IMM_HIGH) { - BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) .addReg(Alpha::R30); } else if (getUpper16(NumBytes) <= IMM_HIGH) { - BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30) .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); - BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30) .addImm(getLower16(NumBytes)).addReg(Alpha::R30); } else { cerr << "Too big a stack frame at " << NumBytes << "\n"; Modified: llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Sat Feb 14 07:20:23 2009 @@ -249,6 +249,7 @@ SDNode *emitBuildVector(SDValue build_vec) { MVT vecVT = build_vec.getValueType(); SDNode *bvNode = build_vec.getNode(); + DebugLoc dl = bvNode->getDebugLoc(); // Check to see if this vector can be represented as a CellSPU immediate // constant by invoking all of the instruction selection predicates: @@ -279,7 +280,7 @@ SDValue CGPoolOffset = SPU::LowerConstantPool(CPIdx, *CurDAG, SPUtli.getSPUTargetMachine()); - return SelectCode(CurDAG->getLoad(build_vec.getValueType(), + return SelectCode(CurDAG->getLoad(build_vec.getValueType(), dl, CurDAG->getEntryNode(), CGPoolOffset, PseudoSourceValue::getConstantPool(), 0, false, Alignment)); @@ -661,6 +662,7 @@ unsigned NewOpc; MVT OpVT = Op.getValueType(); SDValue Ops[8]; + DebugLoc dl = N->getDebugLoc(); if (N->isMachineOpcode()) { return NULL; // Already selected. @@ -679,7 +681,7 @@ } else { NewOpc = SPU::Ar32; Ops[0] = CurDAG->getRegister(SPU::R1, Op.getValueType()); - Ops[1] = SDValue(CurDAG->getTargetNode(SPU::ILAr32, Op.getValueType(), + Ops[1] = SDValue(CurDAG->getTargetNode(SPU::ILAr32, dl, Op.getValueType(), TFI, Imm0), 0); n_ops = 2; } @@ -703,7 +705,7 @@ /*NOTREACHED*/ break; case MVT::i32: - shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32, + shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, CurDAG->getConstant(0x80808080, MVT::i32), CurDAG->getConstant(0x00010203, MVT::i32), CurDAG->getConstant(0x80808080, MVT::i32), @@ -711,7 +713,7 @@ break; case MVT::i16: - shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32, + shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, CurDAG->getConstant(0x80808080, MVT::i32), CurDAG->getConstant(0x80800203, MVT::i32), CurDAG->getConstant(0x80808080, MVT::i32), @@ -719,7 +721,7 @@ break; case MVT::i8: - shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32, + shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, CurDAG->getConstant(0x80808080, MVT::i32), CurDAG->getConstant(0x80808003, MVT::i32), CurDAG->getConstant(0x80808080, MVT::i32), @@ -729,10 +731,10 @@ SDNode *shufMaskLoad = emitBuildVector(shufMask); SDNode *PromoteScalar = - SelectCode(CurDAG->getNode(SPUISD::PREFSLOT2VEC, Op0VecVT, Op0)); + SelectCode(CurDAG->getNode(SPUISD::PREFSLOT2VEC, dl, Op0VecVT, Op0)); SDValue zextShuffle = - CurDAG->getNode(SPUISD::SHUFB, OpVecVT, + CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT, SDValue(PromoteScalar, 0), SDValue(PromoteScalar, 0), SDValue(shufMaskLoad, 0)); @@ -740,28 +742,28 @@ // N.B.: BIT_CONVERT replaces and updates the zextShuffle node, so we // re-use it in the VEC2PREFSLOT selection without needing to explicitly // call SelectCode (it's already done for us.) - SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, OpVecVT, zextShuffle)); - return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, OpVT, + SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, dl, OpVecVT, zextShuffle)); + return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT, zextShuffle)); } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) { SDNode *CGLoad = - emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG)); + emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG, dl)); - return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, OpVT, + return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT, Op.getOperand(0), Op.getOperand(1), SDValue(CGLoad, 0))); } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) { SDNode *CGLoad = - emitBuildVector(SPU::getBorrowGenerateShufMask(*CurDAG)); + emitBuildVector(SPU::getBorrowGenerateShufMask(*CurDAG, dl)); - return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, OpVT, + return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT, Op.getOperand(0), Op.getOperand(1), SDValue(CGLoad, 0))); } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) { SDNode *CGLoad = - emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG)); + emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG, dl)); - return SelectCode(CurDAG->getNode(SPUISD::MUL64_MARKER, OpVT, + return SelectCode(CurDAG->getNode(SPUISD::MUL64_MARKER, dl, OpVT, Op.getOperand(0), Op.getOperand(1), SDValue(CGLoad, 0))); } else if (Opc == ISD::TRUNCATE) { @@ -779,7 +781,8 @@ if (shift_amt >= 32) { SDNode *hi32 = - CurDAG->getTargetNode(SPU::ORr32_r64, OpVT, Op0.getOperand(0)); + CurDAG->getTargetNode(SPU::ORr32_r64, dl, OpVT, + Op0.getOperand(0)); shift_amt -= 32; if (shift_amt > 0) { @@ -790,7 +793,8 @@ if (Op0.getOpcode() == ISD::SRL) Opc = SPU::ROTMr32; - hi32 = CurDAG->getTargetNode(Opc, OpVT, SDValue(hi32, 0), shift); + hi32 = CurDAG->getTargetNode(Opc, dl, OpVT, SDValue(hi32, 0), + shift); } return hi32; @@ -828,9 +832,9 @@ if (vtm->ldresult_imm) { SDValue Zero = CurDAG->getTargetConstant(0, VT); - Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain); + Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Zero, Chain); } else { - Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Arg, Chain); + Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Arg, Chain); } return Result; @@ -866,7 +870,7 @@ if (N->hasOneUse()) return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops); else - return CurDAG->getTargetNode(NewOpc, OpVT, Ops, n_ops); + return CurDAG->getTargetNode(NewOpc, dl, OpVT, Ops, n_ops); } else return SelectCode(Op); } @@ -891,13 +895,14 @@ MVT ShiftAmtVT = ShiftAmt.getValueType(); SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0; SDValue SelMaskVal; + DebugLoc dl = Op.getDebugLoc(); - VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op0); + VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op0); SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16); - SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, VecVT, SelMaskVal); - ZeroFill = CurDAG->getTargetNode(SPU::ILv2i64, VecVT, + SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal); + ZeroFill = CurDAG->getTargetNode(SPU::ILv2i64, dl, VecVT, CurDAG->getTargetConstant(0, OpVT)); - VecOp0 = CurDAG->getTargetNode(SPU::SELBv2i64, VecVT, + VecOp0 = CurDAG->getTargetNode(SPU::SELBv2i64, dl, VecVT, SDValue(ZeroFill, 0), SDValue(VecOp0, 0), SDValue(SelMask, 0)); @@ -908,35 +913,35 @@ if (bytes > 0) { Shift = - CurDAG->getTargetNode(SPU::SHLQBYIv2i64, VecVT, + CurDAG->getTargetNode(SPU::SHLQBYIv2i64, dl, VecVT, SDValue(VecOp0, 0), CurDAG->getTargetConstant(bytes, ShiftAmtVT)); } if (bits > 0) { Shift = - CurDAG->getTargetNode(SPU::SHLQBIIv2i64, VecVT, + CurDAG->getTargetNode(SPU::SHLQBIIv2i64, dl, VecVT, SDValue((Shift != 0 ? Shift : VecOp0), 0), CurDAG->getTargetConstant(bits, ShiftAmtVT)); } } else { SDNode *Bytes = - CurDAG->getTargetNode(SPU::ROTMIr32, ShiftAmtVT, + CurDAG->getTargetNode(SPU::ROTMIr32, dl, ShiftAmtVT, ShiftAmt, CurDAG->getTargetConstant(3, ShiftAmtVT)); SDNode *Bits = - CurDAG->getTargetNode(SPU::ANDIr32, ShiftAmtVT, + CurDAG->getTargetNode(SPU::ANDIr32, dl, ShiftAmtVT, ShiftAmt, CurDAG->getTargetConstant(7, ShiftAmtVT)); Shift = - CurDAG->getTargetNode(SPU::SHLQBYv2i64, VecVT, + CurDAG->getTargetNode(SPU::SHLQBYv2i64, dl, VecVT, SDValue(VecOp0, 0), SDValue(Bytes, 0)); Shift = - CurDAG->getTargetNode(SPU::SHLQBIv2i64, VecVT, + CurDAG->getTargetNode(SPU::SHLQBIv2i64, dl, VecVT, SDValue(Shift, 0), SDValue(Bits, 0)); } - return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(Shift, 0)); + return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0)); } /*! @@ -954,8 +959,9 @@ SDValue ShiftAmt = Op.getOperand(1); MVT ShiftAmtVT = ShiftAmt.getValueType(); SDNode *VecOp0, *Shift = 0; + DebugLoc dl = Op.getDebugLoc(); - VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op0); + VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op0); if (ConstantSDNode *CN = dyn_cast(ShiftAmt)) { unsigned bytes = unsigned(CN->getZExtValue()) >> 3; @@ -963,45 +969,45 @@ if (bytes > 0) { Shift = - CurDAG->getTargetNode(SPU::ROTQMBYIv2i64, VecVT, + CurDAG->getTargetNode(SPU::ROTQMBYIv2i64, dl, VecVT, SDValue(VecOp0, 0), CurDAG->getTargetConstant(bytes, ShiftAmtVT)); } if (bits > 0) { Shift = - CurDAG->getTargetNode(SPU::ROTQMBIIv2i64, VecVT, + CurDAG->getTargetNode(SPU::ROTQMBIIv2i64, dl, VecVT, SDValue((Shift != 0 ? Shift : VecOp0), 0), CurDAG->getTargetConstant(bits, ShiftAmtVT)); } } else { SDNode *Bytes = - CurDAG->getTargetNode(SPU::ROTMIr32, ShiftAmtVT, + CurDAG->getTargetNode(SPU::ROTMIr32, dl, ShiftAmtVT, ShiftAmt, CurDAG->getTargetConstant(3, ShiftAmtVT)); SDNode *Bits = - CurDAG->getTargetNode(SPU::ANDIr32, ShiftAmtVT, + CurDAG->getTargetNode(SPU::ANDIr32, dl, ShiftAmtVT, ShiftAmt, CurDAG->getTargetConstant(7, ShiftAmtVT)); // Ensure that the shift amounts are negated! - Bytes = CurDAG->getTargetNode(SPU::SFIr32, ShiftAmtVT, + Bytes = CurDAG->getTargetNode(SPU::SFIr32, dl, ShiftAmtVT, SDValue(Bytes, 0), CurDAG->getTargetConstant(0, ShiftAmtVT)); - Bits = CurDAG->getTargetNode(SPU::SFIr32, ShiftAmtVT, + Bits = CurDAG->getTargetNode(SPU::SFIr32, dl, ShiftAmtVT, SDValue(Bits, 0), CurDAG->getTargetConstant(0, ShiftAmtVT)); Shift = - CurDAG->getTargetNode(SPU::ROTQMBYv2i64, VecVT, + CurDAG->getTargetNode(SPU::ROTQMBYv2i64, dl, VecVT, SDValue(VecOp0, 0), SDValue(Bytes, 0)); Shift = - CurDAG->getTargetNode(SPU::ROTQMBIv2i64, VecVT, + CurDAG->getTargetNode(SPU::ROTQMBIv2i64, dl, VecVT, SDValue(Shift, 0), SDValue(Bits, 0)); } - return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(Shift, 0)); + return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0)); } /*! @@ -1018,24 +1024,25 @@ MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits())); SDValue ShiftAmt = Op.getOperand(1); MVT ShiftAmtVT = ShiftAmt.getValueType(); + DebugLoc dl = Op.getDebugLoc(); SDNode *VecOp0 = - CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op.getOperand(0)); + CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op.getOperand(0)); SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT); SDNode *SignRot = - CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, MVT::v2i64, + CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64, SDValue(VecOp0, 0), SignRotAmt); SDNode *UpperHalfSign = - CurDAG->getTargetNode(SPU::ORi32_v4i32, MVT::i32, SDValue(SignRot, 0)); + CurDAG->getTargetNode(SPU::ORi32_v4i32, dl, MVT::i32, SDValue(SignRot, 0)); SDNode *UpperHalfSignMask = - CurDAG->getTargetNode(SPU::FSM64r32, VecVT, SDValue(UpperHalfSign, 0)); + CurDAG->getTargetNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0)); SDNode *UpperLowerMask = - CurDAG->getTargetNode(SPU::FSMBIv2i64, VecVT, + CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT, CurDAG->getTargetConstant(0xff00ULL, MVT::i16)); SDNode *UpperLowerSelect = - CurDAG->getTargetNode(SPU::SELBv2i64, VecVT, + CurDAG->getTargetNode(SPU::SELBv2i64, dl, VecVT, SDValue(UpperHalfSignMask, 0), SDValue(VecOp0, 0), SDValue(UpperLowerMask, 0)); @@ -1049,7 +1056,7 @@ if (bytes > 0) { bytes = 31 - bytes; Shift = - CurDAG->getTargetNode(SPU::ROTQBYIv2i64, VecVT, + CurDAG->getTargetNode(SPU::ROTQBYIv2i64, dl, VecVT, SDValue(UpperLowerSelect, 0), CurDAG->getTargetConstant(bytes, ShiftAmtVT)); } @@ -1057,24 +1064,24 @@ if (bits > 0) { bits = 8 - bits; Shift = - CurDAG->getTargetNode(SPU::ROTQBIIv2i64, VecVT, + CurDAG->getTargetNode(SPU::ROTQBIIv2i64, dl, VecVT, SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0), CurDAG->getTargetConstant(bits, ShiftAmtVT)); } } else { SDNode *NegShift = - CurDAG->getTargetNode(SPU::SFIr32, ShiftAmtVT, + CurDAG->getTargetNode(SPU::SFIr32, dl, ShiftAmtVT, ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT)); Shift = - CurDAG->getTargetNode(SPU::ROTQBYBIv2i64_r32, VecVT, + CurDAG->getTargetNode(SPU::ROTQBYBIv2i64_r32, dl, VecVT, SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0)); Shift = - CurDAG->getTargetNode(SPU::ROTQBIv2i64, VecVT, + CurDAG->getTargetNode(SPU::ROTQBIv2i64, dl, VecVT, SDValue(Shift, 0), SDValue(NegShift, 0)); } - return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(Shift, 0)); + return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0)); } /*! @@ -1082,9 +1089,11 @@ */ SDNode *SPUDAGToDAGISel::SelectI64Constant(SDValue& Op, MVT OpVT) { ConstantSDNode *CN = cast(Op.getNode()); + // Currently there's no DL on the input, but won't hurt to pretend. + DebugLoc dl = Op.getDebugLoc(); MVT OpVecVT = MVT::getVectorVT(OpVT, 2); SDValue i64vec = - SPU::LowerSplat_v2i64(OpVecVT, *CurDAG, CN->getZExtValue()); + SPU::LowerSplat_v2i64(OpVecVT, *CurDAG, CN->getZExtValue(), dl); // Here's where it gets interesting, because we have to parse out the // subtree handed back in i64vec: @@ -1095,7 +1104,7 @@ SDValue Op0 = i64vec.getOperand(0); ReplaceUses(i64vec, Op0); - return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, + return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(emitBuildVector(Op0), 0)); } else if (i64vec.getOpcode() == SPUISD::SHUFB) { SDValue lhs = i64vec.getOperand(0); @@ -1130,11 +1139,12 @@ : emitBuildVector(shufmask)); SDNode *shufNode = - Select(CurDAG->getNode(SPUISD::SHUFB, OpVecVT, + Select(CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT, SDValue(lhsNode, 0), SDValue(rhsNode, 0), SDValue(shufMaskNode, 0))); - return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(shufNode, 0)); + return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, + SDValue(shufNode, 0)); } else { cerr << "SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec condition\n"; abort(); Modified: llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.cpp Sat Feb 14 07:20:23 2009 @@ -114,7 +114,7 @@ std::pair CallInfo = TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, CallingConv::C, false, Callee, Args, DAG, - Op.getNode()->getDebugLoc()); + Op.getDebugLoc()); return CallInfo.first; } @@ -507,6 +507,7 @@ ISD::LoadExtType ExtType = LN->getExtensionType(); unsigned alignment = LN->getAlignment(); const valtype_map_s *vtm = getValueTypeMapEntry(InVT); + DebugLoc dl = Op.getDebugLoc(); switch (LN->getAddressingMode()) { case ISD::UNINDEXED: { @@ -533,7 +534,7 @@ // Simplify the base pointer for this case: basePtr = basePtr.getOperand(0); if ((offset & ~0xf) > 0) { - basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, + basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, basePtr, DAG.getConstant((offset & ~0xf), PtrVT)); } @@ -553,7 +554,7 @@ int64_t rotamt = -vtm->prefslot_byte; if (rotamt < 0) rotamt += 16; - rotate = DAG.getNode(ISD::ADD, PtrVT, + rotate = DAG.getNode(ISD::ADD, dl, PtrVT, basePtr, DAG.getConstant(rotamt, PtrVT)); } @@ -572,29 +573,29 @@ // Convert the (add , ) to an indirect address contained // in a register. Note that this is done because we need to avoid // creating a 0(reg) d-form address due to the SPU's block loads. - basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, Op0, Op1); - the_chain = DAG.getCopyToReg(the_chain, VReg, basePtr, Flag); - basePtr = DAG.getCopyFromReg(the_chain, VReg, PtrVT); + basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1); + the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag); + basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT); } else { // Convert the (add , ) to an indirect address, which // will likely be lowered as a reg(reg) x-form address. - basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, Op0, Op1); + basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1); } } else { - basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, + basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, basePtr, DAG.getConstant(0, PtrVT)); } // Offset the rotate amount by the basePtr and the preferred slot // byte offset - rotate = DAG.getNode(ISD::ADD, PtrVT, + rotate = DAG.getNode(ISD::ADD, dl, PtrVT, basePtr, DAG.getConstant(-vtm->prefslot_byte, PtrVT)); } // Re-emit as a v16i8 vector load - result = DAG.getLoad(MVT::v16i8, the_chain, basePtr, + result = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr, LN->getSrcValue(), LN->getSrcValueOffset(), LN->isVolatile(), 16); @@ -602,27 +603,27 @@ the_chain = result.getValue(1); // Rotate into the preferred slot: - result = DAG.getNode(SPUISD::ROTBYTES_LEFT, MVT::v16i8, + result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, MVT::v16i8, result.getValue(0), rotate); // Convert the loaded v16i8 vector to the appropriate vector type // specified by the operand: MVT vecVT = MVT::getVectorVT(InVT, (128 / InVT.getSizeInBits())); - result = DAG.getNode(SPUISD::VEC2PREFSLOT, InVT, - DAG.getNode(ISD::BIT_CONVERT, vecVT, result)); + result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT, + DAG.getNode(ISD::BIT_CONVERT, dl, vecVT, result)); // Handle extending loads by extending the scalar result: if (ExtType == ISD::SEXTLOAD) { - result = DAG.getNode(ISD::SIGN_EXTEND, OutVT, result); + result = DAG.getNode(ISD::SIGN_EXTEND, dl, OutVT, result); } else if (ExtType == ISD::ZEXTLOAD) { - result = DAG.getNode(ISD::ZERO_EXTEND, OutVT, result); + result = DAG.getNode(ISD::ZERO_EXTEND, dl, OutVT, result); } else if (ExtType == ISD::EXTLOAD) { unsigned NewOpc = ISD::ANY_EXTEND; if (OutVT.isFloatingPoint()) NewOpc = ISD::FP_EXTEND; - result = DAG.getNode(NewOpc, OutVT, result); + result = DAG.getNode(NewOpc, dl, OutVT, result); } SDVTList retvts = DAG.getVTList(OutVT, MVT::Other); @@ -631,7 +632,7 @@ the_chain }; - result = DAG.getNode(SPUISD::LDRESULT, retvts, + result = DAG.getNode(SPUISD::LDRESULT, dl, retvts, retops, sizeof(retops) / sizeof(retops[0])); return result; } @@ -663,6 +664,7 @@ MVT VT = Value.getValueType(); MVT StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT()); MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + DebugLoc dl = Op.getDebugLoc(); unsigned alignment = SN->getAlignment(); switch (SN->getAddressingMode()) { @@ -688,18 +690,18 @@ // Simplify the base pointer for this case: basePtr = basePtr.getOperand(0); - insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, PtrVT, + insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, basePtr, DAG.getConstant((offset & 0xf), PtrVT)); if ((offset & ~0xf) > 0) { - basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, + basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, basePtr, DAG.getConstant((offset & ~0xf), PtrVT)); } } else { // Otherwise, assume it's at byte 0 of basePtr - insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, PtrVT, + insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, basePtr, DAG.getConstant(0, PtrVT)); } @@ -718,28 +720,28 @@ // Convert the (add , ) to an indirect address contained // in a register. Note that this is done because we need to avoid // creating a 0(reg) d-form address due to the SPU's block loads. - basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, Op0, Op1); - the_chain = DAG.getCopyToReg(the_chain, VReg, basePtr, Flag); - basePtr = DAG.getCopyFromReg(the_chain, VReg, PtrVT); + basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1); + the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag); + basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT); } else { // Convert the (add , ) to an indirect address, which // will likely be lowered as a reg(reg) x-form address. - basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, Op0, Op1); + basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1); } } else { - basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, + basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, basePtr, DAG.getConstant(0, PtrVT)); } // Insertion point is solely determined by basePtr's contents - insertEltOffs = DAG.getNode(ISD::ADD, PtrVT, + insertEltOffs = DAG.getNode(ISD::ADD, dl, PtrVT, basePtr, DAG.getConstant(0, PtrVT)); } // Re-emit as a v16i8 vector load - alignLoadVec = DAG.getLoad(MVT::v16i8, the_chain, basePtr, + alignLoadVec = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr, SN->getSrcValue(), SN->getSrcValueOffset(), SN->isVolatile(), 16); @@ -771,15 +773,16 @@ #endif SDValue insertEltOp = - DAG.getNode(SPUISD::SHUFFLE_MASK, vecVT, insertEltOffs); + DAG.getNode(SPUISD::SHUFFLE_MASK, dl, vecVT, insertEltOffs); SDValue vectorizeOp = - DAG.getNode(ISD::SCALAR_TO_VECTOR, vecVT, theValue); + DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, vecVT, theValue); - result = DAG.getNode(SPUISD::SHUFB, vecVT, + result = DAG.getNode(SPUISD::SHUFB, dl, vecVT, vectorizeOp, alignLoadVec, - DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, insertEltOp)); + DAG.getNode(ISD::BIT_CONVERT, dl, + MVT::v4i32, insertEltOp)); - result = DAG.getStore(the_chain, result, basePtr, + result = DAG.getStore(the_chain, dl, result, basePtr, LN->getSrcValue(), LN->getSrcValueOffset(), LN->isVolatile(), LN->getAlignment()); @@ -822,15 +825,17 @@ SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); SDValue Zero = DAG.getConstant(0, PtrVT); const TargetMachine &TM = DAG.getTarget(); + // FIXME there is no actual debug info here + DebugLoc dl = Op.getDebugLoc(); if (TM.getRelocationModel() == Reloc::Static) { if (!ST->usingLargeMem()) { // Just return the SDValue with the constant pool address in it. - return DAG.getNode(SPUISD::AFormAddr, PtrVT, CPI, Zero); + return DAG.getNode(SPUISD::AFormAddr, dl, PtrVT, CPI, Zero); } else { - SDValue Hi = DAG.getNode(SPUISD::Hi, PtrVT, CPI, Zero); - SDValue Lo = DAG.getNode(SPUISD::Lo, PtrVT, CPI, Zero); - return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo); + SDValue Hi = DAG.getNode(SPUISD::Hi, dl, PtrVT, CPI, Zero); + SDValue Lo = DAG.getNode(SPUISD::Lo, dl, PtrVT, CPI, Zero); + return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo); } } @@ -853,14 +858,16 @@ SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); SDValue Zero = DAG.getConstant(0, PtrVT); const TargetMachine &TM = DAG.getTarget(); + // FIXME there is no actual debug info here + DebugLoc dl = Op.getDebugLoc(); if (TM.getRelocationModel() == Reloc::Static) { if (!ST->usingLargeMem()) { - return DAG.getNode(SPUISD::AFormAddr, PtrVT, JTI, Zero); + return DAG.getNode(SPUISD::AFormAddr, dl, PtrVT, JTI, Zero); } else { - SDValue Hi = DAG.getNode(SPUISD::Hi, PtrVT, JTI, Zero); - SDValue Lo = DAG.getNode(SPUISD::Lo, PtrVT, JTI, Zero); - return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo); + SDValue Hi = DAG.getNode(SPUISD::Hi, dl, PtrVT, JTI, Zero); + SDValue Lo = DAG.getNode(SPUISD::Lo, dl, PtrVT, JTI, Zero); + return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo); } } @@ -877,14 +884,16 @@ SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); const TargetMachine &TM = DAG.getTarget(); SDValue Zero = DAG.getConstant(0, PtrVT); + // FIXME there is no actual debug info here + DebugLoc dl = Op.getDebugLoc(); if (TM.getRelocationModel() == Reloc::Static) { if (!ST->usingLargeMem()) { - return DAG.getNode(SPUISD::AFormAddr, PtrVT, GA, Zero); + return DAG.getNode(SPUISD::AFormAddr, dl, PtrVT, GA, Zero); } else { - SDValue Hi = DAG.getNode(SPUISD::Hi, PtrVT, GA, Zero); - SDValue Lo = DAG.getNode(SPUISD::Lo, PtrVT, GA, Zero); - return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo); + SDValue Hi = DAG.getNode(SPUISD::Hi, dl, PtrVT, GA, Zero); + SDValue Lo = DAG.getNode(SPUISD::Lo, dl, PtrVT, GA, Zero); + return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo); } } else { cerr << "LowerGlobalAddress: Relocation model other than static not " @@ -900,6 +909,8 @@ static SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); + // FIXME there is no actual debug info here + DebugLoc dl = Op.getDebugLoc(); if (VT == MVT::f64) { ConstantFPSDNode *FP = cast(Op.getNode()); @@ -909,9 +920,9 @@ uint64_t dbits = DoubleToBits(FP->getValueAPF().convertToDouble()); SDValue T = DAG.getConstant(dbits, MVT::i64); - SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i64, T, T); - return DAG.getNode(SPUISD::VEC2PREFSLOT, VT, - DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Tvec)); + SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T); + return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Tvec)); } return SDValue(); @@ -926,6 +937,7 @@ SmallVector ArgValues; SDValue Root = Op.getOperand(0); bool isVarArg = cast(Op.getOperand(2))->getZExtValue() != 0; + DebugLoc dl = Op.getDebugLoc(); const unsigned *ArgRegs = SPURegisterInfo::getArgRegs(); const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs(); @@ -986,7 +998,7 @@ unsigned VReg = RegInfo.createVirtualRegister(ArgRegClass); RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); - ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); + ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT); ++ArgRegIdx; } else { // We need to load the argument to a virtual register if we determined @@ -994,7 +1006,7 @@ // or we're forced to do vararg int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); SDValue FIN = DAG.getFrameIndex(FI, PtrVT); - ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); + ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0); ArgOffset += StackSlotSize; } @@ -1015,7 +1027,7 @@ VarArgsFrameIndex = MFI->CreateFixedObject(StackSlotSize, ArgOffset); SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); SDValue ArgVal = DAG.getRegister(ArgRegs[ArgRegIdx], MVT::v16i8); - SDValue Store = DAG.getStore(Root, ArgVal, FIN, NULL, 0); + SDValue Store = DAG.getStore(Root, dl, ArgVal, FIN, NULL, 0); Root = Store.getOperand(0); MemOps.push_back(Store); @@ -1023,13 +1035,14 @@ ArgOffset += StackSlotSize; } if (!MemOps.empty()) - Root = DAG.getNode(ISD::TokenFactor,MVT::Other,&MemOps[0],MemOps.size()); + Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + &MemOps[0], MemOps.size()); } ArgValues.push_back(Root); // Return the new list of results. - return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), &ArgValues[0], ArgValues.size()); } @@ -1056,6 +1069,7 @@ unsigned StackSlotSize = SPUFrameInfo::stackSlotSize(); const unsigned *ArgRegs = SPURegisterInfo::getArgRegs(); const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs(); + DebugLoc dl = TheCall->getDebugLoc(); // Handy pointer type MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); @@ -1086,7 +1100,7 @@ // PtrOff will be used to store the current argument to the stack if a // register cannot be found for it. SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); - PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); + PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); switch (Arg.getValueType().getSimpleVT()) { default: assert(0 && "Unexpected ValueType for argument!"); @@ -1098,7 +1112,7 @@ if (ArgRegIdx != NumArgRegs) { RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg)); } else { - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); ArgOffset += StackSlotSize; } break; @@ -1107,7 +1121,7 @@ if (ArgRegIdx != NumArgRegs) { RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg)); } else { - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); ArgOffset += StackSlotSize; } break; @@ -1120,7 +1134,7 @@ if (ArgRegIdx != NumArgRegs) { RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg)); } else { - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); ArgOffset += StackSlotSize; } break; @@ -1134,7 +1148,7 @@ if (!MemOpChains.empty()) { // Adjust the stack pointer for the stack arguments. - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); } @@ -1142,8 +1156,8 @@ // and flag operands which copy the outgoing args into the appropriate regs. SDValue InFlag; for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, - InFlag); + Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, + RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } @@ -1169,14 +1183,14 @@ // This may be an unsafe assumption for JIT and really large compilation // units. if (GV->isDeclaration()) { - Callee = DAG.getNode(SPUISD::AFormAddr, CalleeVT, GA, Zero); + Callee = DAG.getNode(SPUISD::AFormAddr, dl, CalleeVT, GA, Zero); } else { - Callee = DAG.getNode(SPUISD::PCRelAddr, CalleeVT, GA, Zero); + Callee = DAG.getNode(SPUISD::PCRelAddr, dl, CalleeVT, GA, Zero); } } else { // "Large memory" mode: Turn all calls into indirect calls with a X-form // address pairs: - Callee = DAG.getNode(SPUISD::IndirectAddr, PtrVT, GA, Zero); + Callee = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, GA, Zero); } } else if (ExternalSymbolSDNode *S = dyn_cast(Callee)) { MVT CalleeVT = Callee.getValueType(); @@ -1185,9 +1199,9 @@ Callee.getValueType()); if (!ST->usingLargeMem()) { - Callee = DAG.getNode(SPUISD::AFormAddr, CalleeVT, ExtSym, Zero); + Callee = DAG.getNode(SPUISD::AFormAddr, dl, CalleeVT, ExtSym, Zero); } else { - Callee = DAG.getNode(SPUISD::IndirectAddr, PtrVT, ExtSym, Zero); + Callee = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, ExtSym, Zero); } } else if (SDNode *Dest = isLSAAddress(Callee, DAG)) { // If this is an absolute destination address that appears to be a legal @@ -1207,7 +1221,7 @@ if (InFlag.getNode()) Ops.push_back(InFlag); // Returns a chain and a flag for retval copy to use. - Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag), + Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag), &Ops[0], Ops.size()); InFlag = Chain.getValue(1); @@ -1225,31 +1239,35 @@ case MVT::Other: break; case MVT::i32: if (TheCall->getValueType(1) == MVT::i32) { - Chain = DAG.getCopyFromReg(Chain, SPU::R4, MVT::i32, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R4, + MVT::i32, InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); - Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i32, + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32, Chain.getValue(2)).getValue(1); ResultVals[1] = Chain.getValue(0); NumResults = 2; } else { - Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i32, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32, + InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; } break; case MVT::i64: - Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i64, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i64, + InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; break; case MVT::i128: - Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i128, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i128, + InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; break; case MVT::f32: case MVT::f64: - Chain = DAG.getCopyFromReg(Chain, SPU::R3, TheCall->getValueType(0), + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, TheCall->getValueType(0), InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; @@ -1260,7 +1278,7 @@ case MVT::v4i32: case MVT::v8i16: case MVT::v16i8: - Chain = DAG.getCopyFromReg(Chain, SPU::R3, TheCall->getValueType(0), + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, TheCall->getValueType(0), InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; @@ -1273,7 +1291,7 @@ // Otherwise, merge everything together with a MERGE_VALUES node. ResultVals[NumResults++] = Chain; - SDValue Res = DAG.getMergeValues(ResultVals, NumResults); + SDValue Res = DAG.getMergeValues(ResultVals, NumResults, dl); return Res.getValue(Op.getResNo()); } @@ -1282,6 +1300,7 @@ SmallVector RVLocs; unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); + DebugLoc dl = Op.getDebugLoc(); CCState CCInfo(CC, isVarArg, TM, RVLocs); CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SPU); @@ -1299,14 +1318,15 @@ for (unsigned i = 0; i != RVLocs.size(); ++i) { CCValAssign &VA = RVLocs[i]; assert(VA.isRegLoc() && "Can only return in registers!"); - Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); + Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), + Op.getOperand(i*2+1), Flag); Flag = Chain.getValue(1); } if (Flag.getNode()) - return DAG.getNode(SPUISD::RET_FLAG, MVT::Other, Chain, Flag); + return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain, Flag); else - return DAG.getNode(SPUISD::RET_FLAG, MVT::Other, Chain); + return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain); } @@ -1571,6 +1591,7 @@ SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); + DebugLoc dl = Op.getDebugLoc(); // If this is a vector of constants or undefs, get the bits. A bit in // UndefBits is set if the corresponding element of the vector is an // ISD::UNDEF value. For undefs, the corresponding VectorBits values are @@ -1598,8 +1619,9 @@ && "LowerBUILD_VECTOR: Unexpected floating point vector element."); // NOTE: pretend the constant is an integer. LLVM won't load FP constants SDValue T = DAG.getConstant(Value32, MVT::i32); - return DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, - DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, T, T, T, T)); + return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, + DAG.getNode(ISD::BUILD_VECTOR, dl, + MVT::v4i32, T, T, T, T)); break; } case MVT::v2f64: { @@ -1608,8 +1630,8 @@ && "LowerBUILD_VECTOR: 64-bit float vector size > 8 bytes."); // NOTE: pretend the constant is an integer. LLVM won't load FP constants SDValue T = DAG.getConstant(f64val, MVT::i64); - return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, - DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i64, T, T)); + return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, + DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T)); break; } case MVT::v16i8: { @@ -1618,8 +1640,8 @@ SDValue Ops[8]; for (int i = 0; i < 8; ++i) Ops[i] = DAG.getConstant(Value16, MVT::i16); - return DAG.getNode(ISD::BIT_CONVERT, VT, - DAG.getNode(ISD::BUILD_VECTOR, MVT::v8i16, Ops, 8)); + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, + DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16, Ops, 8)); } case MVT::v8i16: { unsigned short Value16; @@ -1630,20 +1652,20 @@ SDValue T = DAG.getConstant(Value16, VT.getVectorElementType()); SDValue Ops[8]; for (int i = 0; i < 8; ++i) Ops[i] = T; - return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops, 8); + return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops, 8); } case MVT::v4i32: { unsigned int Value = SplatBits; SDValue T = DAG.getConstant(Value, VT.getVectorElementType()); - return DAG.getNode(ISD::BUILD_VECTOR, VT, T, T, T, T); + return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T, T, T); } case MVT::v2i32: { unsigned int Value = SplatBits; SDValue T = DAG.getConstant(Value, VT.getVectorElementType()); - return DAG.getNode(ISD::BUILD_VECTOR, VT, T, T); + return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T); } case MVT::v2i64: { - return SPU::LowerSplat_v2i64(VT, DAG, SplatBits); + return SPU::LowerSplat_v2i64(VT, DAG, SplatBits, dl); } } @@ -1651,15 +1673,16 @@ } SDValue -SPU::LowerSplat_v2i64(MVT OpVT, SelectionDAG& DAG, uint64_t SplatVal) { +SPU::LowerSplat_v2i64(MVT OpVT, SelectionDAG& DAG, uint64_t SplatVal, + DebugLoc dl) { uint32_t upper = uint32_t(SplatVal >> 32); uint32_t lower = uint32_t(SplatVal); if (upper == lower) { // Magic constant that can be matched by IL, ILA, et. al. SDValue Val = DAG.getTargetConstant(upper, MVT::i32); - return DAG.getNode(ISD::BIT_CONVERT, OpVT, - DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, + return DAG.getNode(ISD::BIT_CONVERT, dl, OpVT, + DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Val, Val, Val, Val)); } else { SDValue LO32; @@ -1679,16 +1702,16 @@ // Create lower vector if not a special pattern if (!lower_special) { SDValue LO32C = DAG.getConstant(lower, MVT::i32); - LO32 = DAG.getNode(ISD::BIT_CONVERT, OpVT, - DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, + LO32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT, + DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, LO32C, LO32C, LO32C, LO32C)); } // Create upper vector if not a special pattern if (!upper_special) { SDValue HI32C = DAG.getConstant(upper, MVT::i32); - HI32 = DAG.getNode(ISD::BIT_CONVERT, OpVT, - DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, + HI32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT, + DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, HI32C, HI32C, HI32C, HI32C)); } @@ -1702,7 +1725,7 @@ // Unhappy situation... both upper and lower are special, so punt with // a target constant: SDValue Zero = DAG.getConstant(0, MVT::i32); - HI32 = LO32 = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Zero, Zero, + HI32 = LO32 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Zero, Zero, Zero, Zero); } @@ -1732,8 +1755,8 @@ ShufBytes.push_back(DAG.getConstant(val, MVT::i32)); } - return DAG.getNode(SPUISD::SHUFB, OpVT, HI32, LO32, - DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, + return DAG.getNode(SPUISD::SHUFB, dl, OpVT, HI32, LO32, + DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShufBytes[0], ShufBytes.size())); } } @@ -1755,6 +1778,7 @@ SDValue V1 = Op.getOperand(0); SDValue V2 = Op.getOperand(1); SDValue PermMask = Op.getOperand(2); + DebugLoc dl = Op.getDebugLoc(); if (V2.getOpcode() == ISD::UNDEF) V2 = V1; @@ -1829,18 +1853,19 @@ MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Initialize temporary register to 0 SDValue InitTempReg = - DAG.getCopyToReg(DAG.getEntryNode(), VReg, DAG.getConstant(0, PtrVT)); + DAG.getCopyToReg(DAG.getEntryNode(), dl, VReg, DAG.getConstant(0, PtrVT)); // Copy register's contents as index in SHUFFLE_MASK: SDValue ShufMaskOp = - DAG.getNode(SPUISD::SHUFFLE_MASK, MVT::v4i32, + DAG.getNode(SPUISD::SHUFFLE_MASK, dl, MVT::v4i32, DAG.getTargetConstant(V2Elt, MVT::i32), - DAG.getCopyFromReg(InitTempReg, VReg, PtrVT)); + DAG.getCopyFromReg(InitTempReg, dl, VReg, PtrVT)); // Use shuffle mask in SHUFB synthetic instruction: - return DAG.getNode(SPUISD::SHUFB, V1.getValueType(), V2, V1, ShufMaskOp); + return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V2, V1, + ShufMaskOp); } else if (rotate) { int rotamt = (MaxElts - V0Elt) * EltVT.getSizeInBits()/8; - return DAG.getNode(SPUISD::ROTBYTES_LEFT, V1.getValueType(), + return DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, V1.getValueType(), V1, DAG.getConstant(rotamt, MVT::i16)); } else { // Convert the SHUFFLE_VECTOR mask's input element units to the @@ -1861,14 +1886,15 @@ } } - SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, + SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, &ResultMask[0], ResultMask.size()); - return DAG.getNode(SPUISD::SHUFB, V1.getValueType(), V1, V2, VPermMask); + return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V1, V2, VPermMask); } } static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { SDValue Op0 = Op.getOperand(0); // Op0 = the scalar + DebugLoc dl = Op.getDebugLoc(); if (Op0.getNode()->getOpcode() == ISD::Constant) { // For a constant, build the appropriate constant vector, which will @@ -1895,7 +1921,7 @@ for (size_t j = 0; j < n_copies; ++j) ConstVecValues.push_back(CValue); - return DAG.getNode(ISD::BUILD_VECTOR, Op.getValueType(), + return DAG.getNode(ISD::BUILD_VECTOR, dl, Op.getValueType(), &ConstVecValues[0], ConstVecValues.size()); } else { // Otherwise, copy the value from one register to another: @@ -1907,7 +1933,7 @@ case MVT::i64: case MVT::f32: case MVT::f64: - return DAG.getNode(SPUISD::PREFSLOT2VEC, Op.getValueType(), Op0, Op0); + return DAG.getNode(SPUISD::PREFSLOT2VEC, dl, Op.getValueType(), Op0, Op0); } } @@ -1918,6 +1944,7 @@ MVT VT = Op.getValueType(); SDValue N = Op.getOperand(0); SDValue Elt = Op.getOperand(1); + DebugLoc dl = Op.getDebugLoc(); SDValue retval; if (ConstantSDNode *C = dyn_cast(Elt)) { @@ -1936,7 +1963,7 @@ if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) { // i32 and i64: Element 0 is the preferred slot - return DAG.getNode(SPUISD::VEC2PREFSLOT, VT, N); + return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, N); } // Need to generate shuffle mask and extract: @@ -1995,12 +2022,12 @@ ShufMask[i] = DAG.getConstant(bits, MVT::i32); } - SDValue ShufMaskVec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, + SDValue ShufMaskVec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShufMask[0], sizeof(ShufMask) / sizeof(ShufMask[0])); - retval = DAG.getNode(SPUISD::VEC2PREFSLOT, VT, - DAG.getNode(SPUISD::SHUFB, N.getValueType(), + retval = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, + DAG.getNode(SPUISD::SHUFB, dl, N.getValueType(), N, N, ShufMaskVec)); } else { // Variable index: Rotate the requested element into slot 0, then replicate @@ -2013,7 +2040,7 @@ // Make life easier by making sure the index is zero-extended to i32 if (Elt.getValueType() != MVT::i32) - Elt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Elt); + Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Elt); // Scale the index to a bit/byte shift quantity APInt scaleFactor = @@ -2023,11 +2050,11 @@ if (scaleShift > 0) { // Scale the shift factor: - Elt = DAG.getNode(ISD::SHL, MVT::i32, Elt, + Elt = DAG.getNode(ISD::SHL, dl, MVT::i32, Elt, DAG.getConstant(scaleShift, MVT::i32)); } - vecShift = DAG.getNode(SPUISD::SHLQUAD_L_BYTES, VecVT, N, Elt); + vecShift = DAG.getNode(SPUISD::SHLQUAD_L_BYTES, dl, VecVT, N, Elt); // Replicate the bytes starting at byte 0 across the entire vector (for // consistency with the notion of a unified register set) @@ -2040,20 +2067,20 @@ /*NOTREACHED*/ case MVT::i8: { SDValue factor = DAG.getConstant(0x00000000, MVT::i32); - replicate = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, factor, factor, + replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, factor, factor, factor, factor); break; } case MVT::i16: { SDValue factor = DAG.getConstant(0x00010001, MVT::i32); - replicate = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, factor, factor, + replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, factor, factor, factor, factor); break; } case MVT::i32: case MVT::f32: { SDValue factor = DAG.getConstant(0x00010203, MVT::i32); - replicate = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, factor, factor, + replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, factor, factor, factor, factor); break; } @@ -2061,14 +2088,14 @@ case MVT::f64: { SDValue loFactor = DAG.getConstant(0x00010203, MVT::i32); SDValue hiFactor = DAG.getConstant(0x04050607, MVT::i32); - replicate = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, loFactor, hiFactor, - loFactor, hiFactor); + replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + loFactor, hiFactor, loFactor, hiFactor); break; } } - retval = DAG.getNode(SPUISD::VEC2PREFSLOT, VT, - DAG.getNode(SPUISD::SHUFB, VecVT, + retval = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, + DAG.getNode(SPUISD::SHUFB, dl, VecVT, vecShift, vecShift, replicate)); } @@ -2079,6 +2106,7 @@ SDValue VecOp = Op.getOperand(0); SDValue ValOp = Op.getOperand(1); SDValue IdxOp = Op.getOperand(2); + DebugLoc dl = Op.getDebugLoc(); MVT VT = Op.getValueType(); ConstantSDNode *CN = cast(IdxOp); @@ -2086,16 +2114,16 @@ MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Use $sp ($1) because it's always 16-byte aligned and it's available: - SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, PtrVT, + SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, DAG.getRegister(SPU::R1, PtrVT), DAG.getConstant(CN->getSExtValue(), PtrVT)); - SDValue ShufMask = DAG.getNode(SPUISD::SHUFFLE_MASK, VT, Pointer); + SDValue ShufMask = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, VT, Pointer); SDValue result = - DAG.getNode(SPUISD::SHUFB, VT, - DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, ValOp), + DAG.getNode(SPUISD::SHUFB, dl, VT, + DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, ValOp), VecOp, - DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, ShufMask)); + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, ShufMask)); return result; } @@ -2104,6 +2132,7 @@ const TargetLowering &TLI) { SDValue N0 = Op.getOperand(0); // Everything has at least one operand + DebugLoc dl = Op.getDebugLoc(); MVT ShiftVT = TLI.getShiftAmountTy(); assert(Op.getValueType() == MVT::i8); @@ -2116,10 +2145,10 @@ // 8-bit addition: Promote the arguments up to 16-bits and truncate // the result: SDValue N1 = Op.getOperand(1); - N0 = DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0); - N1 = DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N1); - return DAG.getNode(ISD::TRUNCATE, MVT::i8, - DAG.getNode(Opc, MVT::i16, N0, N1)); + N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0); + N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1); + return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, + DAG.getNode(Opc, dl, MVT::i16, N0, N1)); } @@ -2127,81 +2156,81 @@ // 8-bit subtraction: Promote the arguments up to 16-bits and truncate // the result: SDValue N1 = Op.getOperand(1); - N0 = DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0); - N1 = DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N1); - return DAG.getNode(ISD::TRUNCATE, MVT::i8, - DAG.getNode(Opc, MVT::i16, N0, N1)); + N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0); + N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1); + return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, + DAG.getNode(Opc, dl, MVT::i16, N0, N1)); } case ISD::ROTR: case ISD::ROTL: { SDValue N1 = Op.getOperand(1); unsigned N1Opc; N0 = (N0.getOpcode() != ISD::Constant - ? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0) + ? DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0) : DAG.getConstant(cast(N0)->getZExtValue(), MVT::i16)); N1Opc = N1.getValueType().bitsLT(ShiftVT) ? ISD::ZERO_EXTEND : ISD::TRUNCATE; N1 = (N1.getOpcode() != ISD::Constant - ? DAG.getNode(N1Opc, ShiftVT, N1) + ? DAG.getNode(N1Opc, dl, ShiftVT, N1) : DAG.getConstant(cast(N1)->getZExtValue(), TLI.getShiftAmountTy())); SDValue ExpandArg = - DAG.getNode(ISD::OR, MVT::i16, N0, - DAG.getNode(ISD::SHL, MVT::i16, + DAG.getNode(ISD::OR, dl, MVT::i16, N0, + DAG.getNode(ISD::SHL, dl, MVT::i16, N0, DAG.getConstant(8, MVT::i32))); - return DAG.getNode(ISD::TRUNCATE, MVT::i8, - DAG.getNode(Opc, MVT::i16, ExpandArg, N1)); + return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, + DAG.getNode(Opc, dl, MVT::i16, ExpandArg, N1)); } case ISD::SRL: case ISD::SHL: { SDValue N1 = Op.getOperand(1); unsigned N1Opc; N0 = (N0.getOpcode() != ISD::Constant - ? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0) + ? DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0) : DAG.getConstant(cast(N0)->getZExtValue(), MVT::i32)); N1Opc = N1.getValueType().bitsLT(ShiftVT) ? ISD::ZERO_EXTEND : ISD::TRUNCATE; N1 = (N1.getOpcode() != ISD::Constant - ? DAG.getNode(N1Opc, ShiftVT, N1) + ? DAG.getNode(N1Opc, dl, ShiftVT, N1) : DAG.getConstant(cast(N1)->getZExtValue(), ShiftVT)); - return DAG.getNode(ISD::TRUNCATE, MVT::i8, - DAG.getNode(Opc, MVT::i16, N0, N1)); + return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, + DAG.getNode(Opc, dl, MVT::i16, N0, N1)); } case ISD::SRA: { SDValue N1 = Op.getOperand(1); unsigned N1Opc; N0 = (N0.getOpcode() != ISD::Constant - ? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0) + ? DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0) : DAG.getConstant(cast(N0)->getSExtValue(), MVT::i16)); N1Opc = N1.getValueType().bitsLT(ShiftVT) ? ISD::SIGN_EXTEND : ISD::TRUNCATE; N1 = (N1.getOpcode() != ISD::Constant - ? DAG.getNode(N1Opc, ShiftVT, N1) + ? DAG.getNode(N1Opc, dl, ShiftVT, N1) : DAG.getConstant(cast(N1)->getZExtValue(), ShiftVT)); - return DAG.getNode(ISD::TRUNCATE, MVT::i8, - DAG.getNode(Opc, MVT::i16, N0, N1)); + return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, + DAG.getNode(Opc, dl, MVT::i16, N0, N1)); } case ISD::MUL: { SDValue N1 = Op.getOperand(1); unsigned N1Opc; N0 = (N0.getOpcode() != ISD::Constant - ? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0) + ? DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0) : DAG.getConstant(cast(N0)->getZExtValue(), MVT::i16)); N1Opc = N1.getValueType().bitsLT(MVT::i16) ? ISD::SIGN_EXTEND : ISD::TRUNCATE; N1 = (N1.getOpcode() != ISD::Constant - ? DAG.getNode(N1Opc, MVT::i16, N1) + ? DAG.getNode(N1Opc, dl, MVT::i16, N1) : DAG.getConstant(cast(N1)->getSExtValue(), MVT::i16)); - return DAG.getNode(ISD::TRUNCATE, MVT::i8, - DAG.getNode(Opc, MVT::i16, N0, N1)); + return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, + DAG.getNode(Opc, dl, MVT::i16, N0, N1)); break; } } @@ -2210,7 +2239,7 @@ } //! Generate the carry-generate shuffle mask. -SDValue SPU::getCarryGenerateShufMask(SelectionDAG &DAG) { +SDValue SPU::getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) { SmallVector ShufBytes; // Create the shuffle mask for "rotating" the borrow up one register slot @@ -2220,12 +2249,12 @@ ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32)); ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32)); - return DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, + return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShufBytes[0], ShufBytes.size()); } //! Generate the borrow-generate shuffle mask -SDValue SPU::getBorrowGenerateShufMask(SelectionDAG &DAG) { +SDValue SPU::getBorrowGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) { SmallVector ShufBytes; // Create the shuffle mask for "rotating" the borrow up one register slot @@ -2235,7 +2264,7 @@ ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32)); ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32)); - return DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, + return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShufBytes[0], ShufBytes.size()); } @@ -2245,6 +2274,7 @@ SDValue ConstVec; SDValue Arg; MVT VT = Op.getValueType(); + DebugLoc dl = Op.getDebugLoc(); ConstVec = Op.getOperand(0); Arg = Op.getOperand(1); @@ -2278,8 +2308,9 @@ for (size_t i = 0; i < tcVecSize; ++i) tcVec[i] = tc; - return DAG.getNode(Op.getNode()->getOpcode(), VT, Arg, - DAG.getNode(ISD::BUILD_VECTOR, VT, tcVec, tcVecSize)); + return DAG.getNode(Op.getNode()->getOpcode(), dl, VT, Arg, + DAG.getNode(ISD::BUILD_VECTOR, dl, VT, + tcVec, tcVecSize)); } } @@ -2297,6 +2328,7 @@ static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); MVT vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits())); + DebugLoc dl = Op.getDebugLoc(); switch (VT.getSimpleVT()) { default: @@ -2305,10 +2337,10 @@ SDValue N = Op.getOperand(0); SDValue Elt0 = DAG.getConstant(0, MVT::i32); - SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, vecVT, N, N); - SDValue CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote); + SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N); + SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote); - return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i8, CNTB, Elt0); + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i8, CNTB, Elt0); } case MVT::i16: { @@ -2322,22 +2354,22 @@ SDValue Mask0 = DAG.getConstant(0x0f, MVT::i16); SDValue Shift1 = DAG.getConstant(8, MVT::i32); - SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, vecVT, N, N); - SDValue CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote); + SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N); + SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote); // CNTB_result becomes the chain to which all of the virtual registers // CNTB_reg, SUM1_reg become associated: SDValue CNTB_result = - DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, CNTB, Elt0); + DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, CNTB, Elt0); SDValue CNTB_rescopy = - DAG.getCopyToReg(CNTB_result, CNTB_reg, CNTB_result); + DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result); - SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i16); + SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i16); - return DAG.getNode(ISD::AND, MVT::i16, - DAG.getNode(ISD::ADD, MVT::i16, - DAG.getNode(ISD::SRL, MVT::i16, + return DAG.getNode(ISD::AND, dl, MVT::i16, + DAG.getNode(ISD::ADD, dl, MVT::i16, + DAG.getNode(ISD::SRL, dl, MVT::i16, Tmp1, Shift1), Tmp1), Mask0); @@ -2356,37 +2388,38 @@ SDValue Shift1 = DAG.getConstant(16, MVT::i32); SDValue Shift2 = DAG.getConstant(8, MVT::i32); - SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, vecVT, N, N); - SDValue CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote); + SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N); + SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote); // CNTB_result becomes the chain to which all of the virtual registers // CNTB_reg, SUM1_reg become associated: SDValue CNTB_result = - DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, CNTB, Elt0); + DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, CNTB, Elt0); SDValue CNTB_rescopy = - DAG.getCopyToReg(CNTB_result, CNTB_reg, CNTB_result); + DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result); SDValue Comp1 = - DAG.getNode(ISD::SRL, MVT::i32, - DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i32), Shift1); + DAG.getNode(ISD::SRL, dl, MVT::i32, + DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32), + Shift1); SDValue Sum1 = - DAG.getNode(ISD::ADD, MVT::i32, - Comp1, DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i32)); + DAG.getNode(ISD::ADD, dl, MVT::i32, Comp1, + DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32)); SDValue Sum1_rescopy = - DAG.getCopyToReg(CNTB_result, SUM1_reg, Sum1); + DAG.getCopyToReg(CNTB_result, dl, SUM1_reg, Sum1); SDValue Comp2 = - DAG.getNode(ISD::SRL, MVT::i32, - DAG.getCopyFromReg(Sum1_rescopy, SUM1_reg, MVT::i32), + DAG.getNode(ISD::SRL, dl, MVT::i32, + DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32), Shift2); SDValue Sum2 = - DAG.getNode(ISD::ADD, MVT::i32, Comp2, - DAG.getCopyFromReg(Sum1_rescopy, SUM1_reg, MVT::i32)); + DAG.getNode(ISD::ADD, dl, MVT::i32, Comp2, + DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32)); - return DAG.getNode(ISD::AND, MVT::i32, Sum2, Mask0); + return DAG.getNode(ISD::AND, dl, MVT::i32, Sum2, Mask0); } case MVT::i64: @@ -2455,6 +2488,7 @@ static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) { CondCodeSDNode *CC = dyn_cast(Op.getOperand(2)); + DebugLoc dl = Op.getDebugLoc(); assert(CC != 0 && "LowerSETCC: CondCodeSDNode should not be null here!\n"); SDValue lhs = Op.getOperand(0); @@ -2468,62 +2502,62 @@ // Take advantage of the fact that (truncate (sra arg, 32)) is efficiently // selected to a NOP: - SDValue i64lhs = DAG.getNode(ISD::BIT_CONVERT, IntVT, lhs); + SDValue i64lhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, lhs); SDValue lhsHi32 = - DAG.getNode(ISD::TRUNCATE, MVT::i32, - DAG.getNode(ISD::SRL, IntVT, + DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, + DAG.getNode(ISD::SRL, dl, IntVT, i64lhs, DAG.getConstant(32, MVT::i32))); SDValue lhsHi32abs = - DAG.getNode(ISD::AND, MVT::i32, + DAG.getNode(ISD::AND, dl, MVT::i32, lhsHi32, DAG.getConstant(0x7fffffff, MVT::i32)); SDValue lhsLo32 = - DAG.getNode(ISD::TRUNCATE, MVT::i32, i64lhs); + DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, i64lhs); // SETO and SETUO only use the lhs operand: if (CC->get() == ISD::SETO) { // Evaluates to true if Op0 is not [SQ]NaN - lowers to the inverse of // SETUO APInt ccResultAllOnes = APInt::getAllOnesValue(ccResultVT.getSizeInBits()); - return DAG.getNode(ISD::XOR, ccResultVT, - DAG.getSetCC(ccResultVT, + return DAG.getNode(ISD::XOR, dl, ccResultVT, + DAG.getSetCC(dl, ccResultVT, lhs, DAG.getConstantFP(0.0, lhsVT), ISD::SETUO), DAG.getConstant(ccResultAllOnes, ccResultVT)); } else if (CC->get() == ISD::SETUO) { // Evaluates to true if Op0 is [SQ]NaN - return DAG.getNode(ISD::AND, ccResultVT, - DAG.getSetCC(ccResultVT, + return DAG.getNode(ISD::AND, dl, ccResultVT, + DAG.getSetCC(dl, ccResultVT, lhsHi32abs, DAG.getConstant(0x7ff00000, MVT::i32), ISD::SETGE), - DAG.getSetCC(ccResultVT, + DAG.getSetCC(dl, ccResultVT, lhsLo32, DAG.getConstant(0, MVT::i32), ISD::SETGT)); } - SDValue i64rhs = DAG.getNode(ISD::BIT_CONVERT, IntVT, rhs); + SDValue i64rhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, rhs); SDValue rhsHi32 = - DAG.getNode(ISD::TRUNCATE, MVT::i32, - DAG.getNode(ISD::SRL, IntVT, + DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, + DAG.getNode(ISD::SRL, dl, IntVT, i64rhs, DAG.getConstant(32, MVT::i32))); // If a value is negative, subtract from the sign magnitude constant: SDValue signMag2TC = DAG.getConstant(0x8000000000000000ULL, IntVT); // Convert the sign-magnitude representation into 2's complement: - SDValue lhsSelectMask = DAG.getNode(ISD::SRA, ccResultVT, + SDValue lhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT, lhsHi32, DAG.getConstant(31, MVT::i32)); - SDValue lhsSignMag2TC = DAG.getNode(ISD::SUB, IntVT, signMag2TC, i64lhs); + SDValue lhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64lhs); SDValue lhsSelect = - DAG.getNode(ISD::SELECT, IntVT, + DAG.getNode(ISD::SELECT, dl, IntVT, lhsSelectMask, lhsSignMag2TC, i64lhs); - SDValue rhsSelectMask = DAG.getNode(ISD::SRA, ccResultVT, + SDValue rhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT, rhsHi32, DAG.getConstant(31, MVT::i32)); - SDValue rhsSignMag2TC = DAG.getNode(ISD::SUB, IntVT, signMag2TC, i64rhs); + SDValue rhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64rhs); SDValue rhsSelect = - DAG.getNode(ISD::SELECT, IntVT, + DAG.getNode(ISD::SELECT, dl, IntVT, rhsSelectMask, rhsSignMag2TC, i64rhs); unsigned compareOp; @@ -2554,19 +2588,20 @@ } SDValue result = - DAG.getSetCC(ccResultVT, lhsSelect, rhsSelect, (ISD::CondCode) compareOp); + DAG.getSetCC(dl, ccResultVT, lhsSelect, rhsSelect, + (ISD::CondCode) compareOp); if ((CC->get() & 0x8) == 0) { // Ordered comparison: - SDValue lhsNaN = DAG.getSetCC(ccResultVT, + SDValue lhsNaN = DAG.getSetCC(dl, ccResultVT, lhs, DAG.getConstantFP(0.0, MVT::f64), ISD::SETO); - SDValue rhsNaN = DAG.getSetCC(ccResultVT, + SDValue rhsNaN = DAG.getSetCC(dl, ccResultVT, rhs, DAG.getConstantFP(0.0, MVT::f64), ISD::SETO); - SDValue ordered = DAG.getNode(ISD::AND, ccResultVT, lhsNaN, rhsNaN); + SDValue ordered = DAG.getNode(ISD::AND, dl, ccResultVT, lhsNaN, rhsNaN); - result = DAG.getNode(ISD::AND, ccResultVT, ordered, result); + result = DAG.getNode(ISD::AND, dl, ccResultVT, ordered, result); } return result; @@ -2592,6 +2627,7 @@ SDValue trueval = Op.getOperand(2); SDValue falseval = Op.getOperand(3); SDValue condition = Op.getOperand(4); + DebugLoc dl = Op.getDebugLoc(); // NOTE: SELB's arguments: $rA, $rB, $mask // @@ -2604,10 +2640,10 @@ // legalizer insists on combining SETCC/SELECT into SELECT_CC, so we end up // with another "cannot select select_cc" assert: - SDValue compare = DAG.getNode(ISD::SETCC, + SDValue compare = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(Op.getValueType()), lhs, rhs, condition); - return DAG.getNode(SPUISD::SELB, VT, falseval, trueval, compare); + return DAG.getNode(SPUISD::SELB, dl, VT, falseval, trueval, compare); } //! Custom lower ISD::TRUNCATE @@ -2616,6 +2652,7 @@ MVT VT = Op.getValueType(); MVT::SimpleValueType simpleVT = VT.getSimpleVT(); MVT VecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits())); + DebugLoc dl = Op.getDebugLoc(); SDValue Op0 = Op.getOperand(0); MVT Op0VT = Op0.getValueType(); @@ -2626,20 +2663,21 @@ unsigned maskHigh = 0x08090a0b; unsigned maskLow = 0x0c0d0e0f; // Use a shuffle to perform the truncation - SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, + SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, DAG.getConstant(maskHigh, MVT::i32), DAG.getConstant(maskLow, MVT::i32), DAG.getConstant(maskHigh, MVT::i32), DAG.getConstant(maskLow, MVT::i32)); - SDValue PromoteScalar = DAG.getNode(SPUISD::PREFSLOT2VEC, Op0VecVT, Op0); + SDValue PromoteScalar = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, + Op0VecVT, Op0); - SDValue truncShuffle = DAG.getNode(SPUISD::SHUFB, Op0VecVT, + SDValue truncShuffle = DAG.getNode(SPUISD::SHUFB, dl, Op0VecVT, PromoteScalar, PromoteScalar, shufMask); - return DAG.getNode(SPUISD::VEC2PREFSLOT, VT, - DAG.getNode(ISD::BIT_CONVERT, VecVT, truncShuffle)); + return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, + DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, truncShuffle)); } return SDValue(); // Leave the truncate unmolested @@ -2785,6 +2823,7 @@ MVT NodeVT = N->getValueType(0); // The node's value type MVT Op0VT = Op0.getValueType(); // The first operand's result SDValue Result; // Initially, empty result + DebugLoc dl = N->getDebugLoc(); switch (N->getOpcode()) { default: break; @@ -2835,7 +2874,7 @@ } #endif - return DAG.getNode(SPUISD::IndirectAddr, Op0VT, + return DAG.getNode(SPUISD::IndirectAddr, dl, Op0VT, IndirectArg, combinedValue); } } @@ -2893,7 +2932,7 @@ } #endif - return DAG.getNode(SPUISD::IndirectAddr, Op0VT, + return DAG.getNode(SPUISD::IndirectAddr, dl, Op0VT, Op0.getOperand(0), Op0.getOperand(1)); } } Modified: llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.h?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.h (original) +++ llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.h Sat Feb 14 07:20:23 2009 @@ -78,10 +78,11 @@ SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUTargetMachine &TM); - SDValue LowerSplat_v2i64(MVT OpVT, SelectionDAG &DAG, uint64_t splat); + SDValue LowerSplat_v2i64(MVT OpVT, SelectionDAG &DAG, uint64_t splat, + DebugLoc dl); - SDValue getBorrowGenerateShufMask(SelectionDAG &DAG); - SDValue getCarryGenerateShufMask(SelectionDAG &DAG); + SDValue getBorrowGenerateShufMask(SelectionDAG &DAG, DebugLoc dl); + SDValue getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl); } class SPUTargetMachine; // forward dec'l. Modified: llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp Sat Feb 14 07:20:23 2009 @@ -259,22 +259,25 @@ // we instruction select bitconvert i64 -> f64 as a noop for example, so our // types have no specific meaning. + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if (DestRC == SPU::R8CRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRr8), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRr8), DestReg).addReg(SrcReg); } else if (DestRC == SPU::R16CRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRr16), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRr16), DestReg).addReg(SrcReg); } else if (DestRC == SPU::R32CRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRr32), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRr32), DestReg).addReg(SrcReg); } else if (DestRC == SPU::R32FPRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRf32), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRf32), DestReg).addReg(SrcReg); } else if (DestRC == SPU::R64CRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRr64), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRr64), DestReg).addReg(SrcReg); } else if (DestRC == SPU::R64FPRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRf64), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRf64), DestReg).addReg(SrcReg); } else if (DestRC == SPU::GPRCRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRr128), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRr128), DestReg).addReg(SrcReg); } else if (DestRC == SPU::VECREGRegisterClass) { - BuildMI(MBB, MI, get(SPU::LRv16i8), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(SPU::LRv16i8), DestReg).addReg(SrcReg); } else { // Attempt to copy unknown/unsupported register class! return false; @@ -312,15 +315,17 @@ abort(); } - addFrameReference(BuildMI(MBB, MI, get(opc)) + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + addFrameReference(BuildMI(MBB, MI, DL, get(opc)) .addReg(SrcReg, false, false, isKill), FrameIdx); } void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - bool isKill, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl &NewMIs) const { + bool isKill, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl &NewMIs) const { cerr << "storeRegToAddr() invoked!\n"; abort(); @@ -344,7 +349,8 @@ assert(0 && "Unknown regclass!"); abort(); } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)) + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) .addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; @@ -388,7 +394,9 @@ abort(); } - addFrameReference(BuildMI(MBB, MI, get(opc)).addReg(DestReg), FrameIdx); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + addFrameReference(BuildMI(MBB, MI, DL, get(opc)).addReg(DestReg), FrameIdx); } /*! @@ -424,7 +432,8 @@ assert(0 && "Unknown regclass!"); abort(); } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) @@ -495,7 +504,8 @@ unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); if (FrameIndex < SPUFrameInfo::maxFrameOffset()) { - MachineInstrBuilder MIB = BuildMI(MF, get(SPU::STQDr32)); + MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), + get(SPU::STQDr32)); MIB.addReg(InReg, false, false, isKill); NewMI = addFrameReference(MIB, FrameIndex); @@ -503,7 +513,7 @@ } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)); + MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)); MIB.addReg(OutReg, true, false, false, isDead); Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset()) @@ -617,6 +627,8 @@ SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const { + // FIXME this should probably have a DebugLoc argument + DebugLoc dl = DebugLoc::getUnknownLoc(); // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && @@ -626,14 +638,14 @@ if (FBB == 0) { if (Cond.empty()) { // Unconditional branch - MachineInstrBuilder MIB = BuildMI(&MBB, get(SPU::BR)); + MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(SPU::BR)); MIB.addMBB(TBB); DEBUG(cerr << "Inserted one-way uncond branch: "); DEBUG((*MIB).dump()); } else { // Conditional branch - MachineInstrBuilder MIB = BuildMI(&MBB, get(Cond[0].getImm())); + MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm())); MIB.addReg(Cond[1].getReg()).addMBB(TBB); DEBUG(cerr << "Inserted one-way cond branch: "); @@ -641,8 +653,8 @@ } return 1; } else { - MachineInstrBuilder MIB = BuildMI(&MBB, get(Cond[0].getImm())); - MachineInstrBuilder MIB2 = BuildMI(&MBB, get(SPU::BR)); + MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm())); + MachineInstrBuilder MIB2 = BuildMI(&MBB, dl, get(SPU::BR)); // Two-way Conditional Branch. MIB.addReg(Cond[1].getReg()).addMBB(TBB); Modified: llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.cpp Sat Feb 14 07:20:23 2009 @@ -428,6 +428,7 @@ MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); + DebugLoc dl = DebugLoc::getUnknownLoc(); // Prepare for debug frame info. bool hasDebugInfo = MMI && MMI->hasDebugInfo(); @@ -448,38 +449,38 @@ if (hasDebugInfo) { // Mark effective beginning of when frame pointer becomes valid. FrameLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(FrameLabelId); + BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addImm(FrameLabelId); } // Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp) // for the ABI - BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R0).addImm(16) + BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16) .addReg(SPU::R1); if (isS10Constant(FrameSize)) { // Spill $sp to adjusted $sp - BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize) + BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize) .addReg(SPU::R1); // Adjust $sp by required amout - BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1) + BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1) .addImm(FrameSize); } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) { // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use // $r2 to adjust $sp: - BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2) .addImm(-16) .addReg(SPU::R1); - BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2) .addImm(FrameSize); - BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1) + BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1) .addReg(SPU::R2) .addReg(SPU::R1); - BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1) + BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1) .addReg(SPU::R1) .addReg(SPU::R2); - BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2) .addReg(SPU::R2) .addImm(16); - BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2) .addReg(SPU::R2) .addReg(SPU::R1); } else { @@ -508,7 +509,7 @@ // Mark effective beginning of when frame pointer is ready. unsigned ReadyLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(ReadyLabelId); + BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addImm(ReadyLabelId); MachineLocation FPDst(SPU::R1); MachineLocation FPSrc(MachineLocation::VirtualFP); @@ -522,7 +523,7 @@ MachineBasicBlock::iterator MBBI = prior(MBB.end()); // Insert terminator label unsigned BranchLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(BranchLabelId); + BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addImm(BranchLabelId); } } } @@ -534,6 +535,7 @@ const MachineFrameInfo *MFI = MF.getFrameInfo(); int FrameSize = MFI->getStackSize(); int LinkSlotOffset = SPUFrameInfo::stackSlotSize(); + DebugLoc dl = DebugLoc::getUnknownLoc(); assert(MBBI->getOpcode() == SPU::RET && "Can only insert epilog into returning blocks"); @@ -545,30 +547,30 @@ // Reload $lr, adjust $sp by required amount // Note: We do this to slightly improve dual issue -- not by much, but it // is an opportunity for dual issue. - BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0) + BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0) .addImm(FrameSize + LinkSlotOffset) .addReg(SPU::R1); - BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1) + BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1) .addReg(SPU::R1) .addImm(FrameSize); } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) { // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use // $r2 to adjust $sp: - BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2) .addImm(16) .addReg(SPU::R1); - BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2) .addImm(FrameSize); - BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1) + BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1) .addReg(SPU::R1) .addReg(SPU::R2); - BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0) + BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0) .addImm(16) .addReg(SPU::R2); - BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2). + BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2). addReg(SPU::R2) .addImm(16); - BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2) .addReg(SPU::R2) .addReg(SPU::R1); } else { Modified: llvm/branches/Apple/Dib/lib/Target/IA64/IA64Bundling.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/IA64/IA64Bundling.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/IA64/IA64Bundling.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/IA64/IA64Bundling.cpp Sat Feb 14 07:20:23 2009 @@ -104,7 +104,7 @@ if(! (CurrentReads.empty() && CurrentWrites.empty()) ) { // there is a conflict, insert a stop and reset PendingRegWrites - CurrentInsn = BuildMI(MBB, CurrentInsn, + CurrentInsn = BuildMI(MBB, CurrentInsn, CurrentInsn->getDebugLoc(), TM.getInstrInfo()->get(IA64::STOP), 0); PendingRegWrites=OrigWrites; // carry over current writes to next insn Changed=true; StopBitsAdded++; // update stats Modified: llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelDAGToDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelDAGToDAG.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sat Feb 14 07:20:23 2009 @@ -106,6 +106,7 @@ SDValue Chain = N->getOperand(0); SDValue Tmp1 = N->getOperand(0); SDValue Tmp2 = N->getOperand(1); + DebugLoc dl = N->getDebugLoc(); bool isFP=false; @@ -140,26 +141,28 @@ if(!isFP) { // first, load the inputs into FP regs. TmpF1 = - SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0); + SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, Tmp1), 0); Chain = TmpF1.getValue(1); TmpF2 = - SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0); + SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, Tmp2), 0); Chain = TmpF2.getValue(1); // next, convert the inputs to FP if(isSigned) { TmpF3 = - SDValue(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0); + SDValue(CurDAG->getTargetNode(IA64::FCVTXF, dl, MVT::f64, TmpF1), 0); Chain = TmpF3.getValue(1); TmpF4 = - SDValue(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0); + SDValue(CurDAG->getTargetNode(IA64::FCVTXF, dl, MVT::f64, TmpF2), 0); Chain = TmpF4.getValue(1); } else { // is unsigned TmpF3 = - SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0); + SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, dl, MVT::f64, TmpF1), + 0); Chain = TmpF3.getValue(1); TmpF4 = - SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0); + SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, dl, MVT::f64, TmpF2), + 0); Chain = TmpF4.getValue(1); } @@ -172,11 +175,11 @@ // we start by computing an approximate reciprocal (good to 9 bits?) // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate) if(isFP) - TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1, - TmpF3, TmpF4), 0); + TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS0, dl, MVT::f64, + MVT::i1, TmpF3, TmpF4), 0); else - TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1, - TmpF3, TmpF4), 0); + TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS1, dl, MVT::f64, + MVT::i1, TmpF3, TmpF4), 0); TmpPR = TmpF5.getValue(1); Chain = TmpF5.getValue(2); @@ -184,7 +187,7 @@ SDValue minusB; if(isModulus) { // for remainders, it'll be handy to have // copies of -input_b - minusB = SDValue(CurDAG->getTargetNode(IA64::SUB, MVT::i64, + minusB = SDValue(CurDAG->getTargetNode(IA64::SUB, dl, MVT::i64, CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0); Chain = minusB.getValue(1); } @@ -192,19 +195,19 @@ SDValue TmpE0, TmpY1, TmpE1, TmpY2; SDValue OpsE0[] = { TmpF4, TmpF5, F1, TmpPR }; - TmpE0 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64, + TmpE0 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, dl, MVT::f64, OpsE0, 4), 0); Chain = TmpE0.getValue(1); SDValue OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR }; - TmpY1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + TmpY1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64, OpsY1, 4), 0); Chain = TmpY1.getValue(1); SDValue OpsE1[] = { TmpE0, TmpE0, F0, TmpPR }; - TmpE1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + TmpE1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64, OpsE1, 4), 0); Chain = TmpE1.getValue(1); SDValue OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR }; - TmpY2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + TmpY2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64, OpsY2, 4), 0); Chain = TmpY2.getValue(1); @@ -215,30 +218,30 @@ SDValue TmpE2, TmpY3, TmpQ0, TmpR0; SDValue OpsE2[] = { TmpE1, TmpE1, F0, TmpPR }; - TmpE2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + TmpE2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64, OpsE2, 4), 0); Chain = TmpE2.getValue(1); SDValue OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR }; - TmpY3 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + TmpY3 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64, OpsY3, 4), 0); Chain = TmpY3.getValue(1); SDValue OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR }; TmpQ0 = - SDValue(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec! - OpsQ0, 4), 0); + SDValue(CurDAG->getTargetNode(IA64::CFMADS1, dl, // double prec! + MVT::f64, OpsQ0, 4), 0); Chain = TmpQ0.getValue(1); SDValue OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR }; TmpR0 = - SDValue(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec! - OpsR0, 4), 0); + SDValue(CurDAG->getTargetNode(IA64::CFNMADS1, dl, // double prec! + MVT::f64, OpsR0, 4), 0); Chain = TmpR0.getValue(1); // we want Result to have the same target register as the frcpa, so // we two-address hack it. See the comment "for this to work..." on // page 48 of Intel application note #245415 SDValue Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR }; - Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg! - Ops, 5); + Result = CurDAG->getTargetNode(IA64::TCFMADS0, dl, // d.p. s0 rndg! + MVT::f64, Ops, 5); Chain = SDValue(Result, 1); return Result; // XXX: early exit! } else { // this is *not* an FP divide, so there's a bit left to do: @@ -246,11 +249,11 @@ SDValue TmpQ2, TmpR2, TmpQ3, TmpQ; SDValue OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR }; - TmpQ2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + TmpQ2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64, OpsQ2, 4), 0); Chain = TmpQ2.getValue(1); SDValue OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR }; - TmpR2 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64, + TmpR2 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, dl, MVT::f64, OpsR2, 4), 0); Chain = TmpR2.getValue(1); @@ -258,7 +261,7 @@ // should two-address hack it. See the comment "for this to work..." on page // 48 of Intel application note #245415 SDValue OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR }; - TmpQ3 = SDValue(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64, + TmpQ3 = SDValue(CurDAG->getTargetNode(IA64::TCFMAS1, dl, MVT::f64, OpsQ3, 5), 0); Chain = TmpQ3.getValue(1); @@ -267,26 +270,27 @@ // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0. if(isSigned) - TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, + TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, dl, MVT::f64, TmpQ3), 0); else - TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, + TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, dl, MVT::f64, TmpQ3), 0); Chain = TmpQ.getValue(1); if(isModulus) { SDValue FPminusB = - SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0); + SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, minusB), + 0); Chain = FPminusB.getValue(1); SDValue Remainder = - SDValue(CurDAG->getTargetNode(IA64::XMAL, MVT::f64, + SDValue(CurDAG->getTargetNode(IA64::XMAL, dl, MVT::f64, TmpQ, FPminusB, TmpF1), 0); Chain = Remainder.getValue(1); - Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder); + Result = CurDAG->getTargetNode(IA64::GETFSIG, dl, MVT::i64, Remainder); Chain = SDValue(Result, 1); } else { // just an integer divide - Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ); + Result = CurDAG->getTargetNode(IA64::GETFSIG, dl, MVT::i64, TmpQ); Chain = SDValue(Result, 1); } @@ -300,6 +304,7 @@ SDNode *N = Op.getNode(); if (N->isMachineOpcode()) return NULL; // Already selected. + DebugLoc dl = Op.getDebugLoc(); switch (N->getOpcode()) { default: break; @@ -334,22 +339,22 @@ // load the branch target's entry point [mem] and // GP value [mem+8] SDValue targetEntryPoint= - SDValue(CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other, + SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other, FnDescriptor, CurDAG->getEntryNode()), 0); Chain = targetEntryPoint.getValue(1); SDValue targetGPAddr= - SDValue(CurDAG->getTargetNode(IA64::ADDS, MVT::i64, + SDValue(CurDAG->getTargetNode(IA64::ADDS, dl, MVT::i64, FnDescriptor, CurDAG->getConstant(8, MVT::i64)), 0); Chain = targetGPAddr.getValue(1); SDValue targetGP = - SDValue(CurDAG->getTargetNode(IA64::LD8, MVT::i64,MVT::Other, + SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64,MVT::Other, targetGPAddr, CurDAG->getEntryNode()), 0); Chain = targetGP.getValue(1); - Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag); + Chain = CurDAG->getCopyToReg(Chain, dl, IA64::r1, targetGP, InFlag); InFlag = Chain.getValue(1); - Chain = CurDAG->getCopyToReg(Chain, IA64::B6, + Chain = CurDAG->getCopyToReg(Chain, dl, IA64::B6, targetEntryPoint, InFlag); // FLAG these? InFlag = Chain.getValue(1); @@ -359,11 +364,11 @@ // Finally, once everything is setup, emit the call itself if (InFlag.getNode()) - Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, - CallOperand, InFlag), 0); + Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other, + MVT::Flag, CallOperand, InFlag), 0); else // there might be no arguments - Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, - CallOperand, Chain), 0); + Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other, + MVT::Flag, CallOperand, Chain), 0); InFlag = Chain.getValue(1); std::vector CallResults; @@ -378,7 +383,7 @@ case IA64ISD::GETFD: { SDValue Input = N->getOperand(0); - return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input); + return CurDAG->getTargetNode(IA64::GETFD, dl, MVT::i64, Input); } case ISD::FDIV: @@ -394,10 +399,10 @@ SDValue V; ConstantFPSDNode* N2 = cast(N); if (N2->getValueAPF().isPosZero()) { - V = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64); + V = CurDAG->getCopyFromReg(Chain, dl, IA64::F0, MVT::f64); } else if (N2->isExactlyValue(N2->getValueType(0) == MVT::f32 ? APFloat(+1.0f) : APFloat(+1.0))) { - V = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64); + V = CurDAG->getCopyFromReg(Chain, dl, IA64::F1, MVT::f64); } else assert(0 && "Unexpected FP constant!"); @@ -411,7 +416,7 @@ return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64, CurDAG->getTargetFrameIndex(FI, MVT::i64)); else - return CurDAG->getTargetNode(IA64::MOV, MVT::i64, + return CurDAG->getTargetNode(IA64::MOV, dl, MVT::i64, CurDAG->getTargetFrameIndex(FI, MVT::i64)); } @@ -421,7 +426,7 @@ Constant *C = CP->getConstVal(); SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64, CP->getAlignment()); - return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ? + return CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64, // ? CurDAG->getRegister(IA64::r1, MVT::i64), CPI); } @@ -429,10 +434,10 @@ GlobalValue *GV = cast(N)->getGlobal(); SDValue GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64); SDValue Tmp = - SDValue(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, + SDValue(CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64, CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0); - return CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other, Tmp, + return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other, Tmp, CurDAG->getEntryNode()); } @@ -441,11 +446,11 @@ SDValue EA = CurDAG->getTargetExternalSymbol( cast(N)->getSymbol(), MVT::i64); - SDValue Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64, + SDValue Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, dl, MVT::i64, CurDAG->getRegister(IA64::r1, MVT::i64), EA); - return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp); + return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, Tmp); } */ @@ -465,9 +470,11 @@ case MVT::i1: { // this is a bool Opc = IA64::LD1; // first we load a byte, then compare for != 0 if(N->getValueType(0) == MVT::i1) { // XXX: early exit! - return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other, - SDValue(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0), - CurDAG->getRegister(IA64::r0, MVT::i64), + return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other, + SDValue(CurDAG->getTargetNode(Opc, dl, + MVT::i64, + Address), 0), + CurDAG->getRegister(IA64::r0, MVT::i64), Chain); } /* otherwise, we want to load a bool into something bigger: LD1 @@ -499,12 +506,12 @@ case MVT::i1: { // this is a bool Opc = IA64::ST1; // we store either 0 or 1 as a byte // first load zero! - SDValue Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64); + SDValue Initial = CurDAG->getCopyFromReg(Chain, dl, IA64::r0, MVT::i64); Chain = Initial.getValue(1); // then load 1 into the same reg iff the predicate to store is 1 SDValue Tmp = ST->getValue(); Tmp = - SDValue(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial, + SDValue(CurDAG->getTargetNode(IA64::TPCADDS, dl, MVT::i64, Initial, CurDAG->getTargetConstant(1, MVT::i64), Tmp), 0); Modified: llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelLowering.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelLowering.cpp Sat Feb 14 07:20:23 2009 @@ -197,8 +197,8 @@ // FP args go into f8..f15 as needed: (hence the ++) argPreg[count] = args_FP[used_FPArgs++]; argOpc[count] = IA64::FMOV; - argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], - MVT::f64); + argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), dl, + argVreg[count], MVT::f64); if (I->getType() == Type::FloatTy) argt = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, argt, DAG.getIntPtrConstant(0)); @@ -217,7 +217,7 @@ argPreg[count] = args_int[count]; argOpc[count] = IA64::MOV; argt = newroot = - DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64); + DAG.getCopyFromReg(DAG.getRoot(), dl, argVreg[count], MVT::i64); if ( getValueType(I->getType()) != MVT::i64) argt = DAG.getNode(ISD::TRUNCATE, dl, getValueType(I->getType()), newroot); @@ -243,7 +243,7 @@ // Create a vreg to hold the output of (what will become) // the "alloc" instruction VirtGPR = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); - BuildMI(&BB, TII->get(IA64::PSEUDO_ALLOC), VirtGPR); + BuildMI(&BB, dl, TII->get(IA64::PSEUDO_ALLOC), VirtGPR); // we create a PSEUDO_ALLOC (pseudo)instruction for now /* BuildMI(&BB, IA64::IDEF, 0, IA64::r1); @@ -273,14 +273,14 @@ // here we actually do the moving of args, and store them to the stack // too if this is a varargs function: for (int i = 0; i < count && i < 8; ++i) { - BuildMI(&BB, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]); + BuildMI(&BB, dl, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]); if(F.isVarArg()) { // if this is a varargs function, we copy the input registers to the stack int FI = MFI->CreateFixedObject(8, tempOffset); tempOffset+=8; //XXX: is it safe to use r22 like this? - BuildMI(&BB, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI); + BuildMI(&BB, dl, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI); // FIXME: we should use st8.spill here, one day - BuildMI(&BB, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]); + BuildMI(&BB, dl, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]); } } @@ -423,13 +423,16 @@ SDValue InFlag; // save the current GP, SP and RP : FIXME: do we need to do all 3 always? - SDValue GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag); + SDValue GPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::r1, + MVT::i64, InFlag); Chain = GPBeforeCall.getValue(1); InFlag = Chain.getValue(2); - SDValue SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag); + SDValue SPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::r12, + MVT::i64, InFlag); Chain = SPBeforeCall.getValue(1); InFlag = Chain.getValue(2); - SDValue RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag); + SDValue RPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::rp, + MVT::i64, InFlag); Chain = RPBeforeCall.getValue(1); InFlag = Chain.getValue(2); @@ -444,8 +447,8 @@ unsigned seenConverts = 0; for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { if(RegValuesToPass[i].getValueType().isFloatingPoint()) { - Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++], - InFlag); + Chain = DAG.getCopyToReg(Chain, dl, IntArgRegs[i], + Converts[seenConverts++], InFlag); InFlag = Chain.getValue(1); } } @@ -453,7 +456,7 @@ // next copy args into the usual places, these are flagged unsigned usedFPArgs = 0; for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, + Chain = DAG.getCopyToReg(Chain, dl, RegValuesToPass[i].getValueType().isInteger() ? IntArgRegs[i] : FPArgRegs[usedFPArgs++], RegValuesToPass[i], InFlag); InFlag = Chain.getValue(1); @@ -486,11 +489,11 @@ InFlag = Chain.getValue(1); // restore the GP, SP and RP after the call - Chain = DAG.getCopyToReg(Chain, IA64::r1, GPBeforeCall, InFlag); + Chain = DAG.getCopyToReg(Chain, dl, IA64::r1, GPBeforeCall, InFlag); InFlag = Chain.getValue(1); - Chain = DAG.getCopyToReg(Chain, IA64::r12, SPBeforeCall, InFlag); + Chain = DAG.getCopyToReg(Chain, dl, IA64::r12, SPBeforeCall, InFlag); InFlag = Chain.getValue(1); - Chain = DAG.getCopyToReg(Chain, IA64::rp, RPBeforeCall, InFlag); + Chain = DAG.getCopyToReg(Chain, dl, IA64::rp, RPBeforeCall, InFlag); InFlag = Chain.getValue(1); std::vector RetVals; @@ -505,10 +508,12 @@ case MVT::i1: { // bools are just like other integers (returned in r8) // we *could* fall through to the truncate below, but this saves a // few redundant predicate ops - SDValue boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,InFlag); + SDValue boolInR8 = DAG.getCopyFromReg(Chain, dl, IA64::r8, + MVT::i64,InFlag); InFlag = boolInR8.getValue(2); Chain = boolInR8.getValue(1); - SDValue zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag); + SDValue zeroReg = DAG.getCopyFromReg(Chain, dl, IA64::r0, + MVT::i64, InFlag); InFlag = zeroReg.getValue(2); Chain = zeroReg.getValue(1); @@ -518,7 +523,7 @@ case MVT::i8: case MVT::i16: case MVT::i32: - RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag); + RetVal = DAG.getCopyFromReg(Chain, dl, IA64::r8, MVT::i64, InFlag); Chain = RetVal.getValue(1); // keep track of whether it is sign or zero extended (todo: bools?) @@ -529,18 +534,18 @@ RetVal = DAG.getNode(ISD::TRUNCATE, dl, RetTyVT, RetVal); break; case MVT::i64: - RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag); + RetVal = DAG.getCopyFromReg(Chain, dl, IA64::r8, MVT::i64, InFlag); Chain = RetVal.getValue(1); InFlag = RetVal.getValue(2); // XXX dead break; case MVT::f32: - RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag); + RetVal = DAG.getCopyFromReg(Chain, dl, IA64::F8, MVT::f64, InFlag); Chain = RetVal.getValue(1); RetVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, RetVal, DAG.getIntPtrConstant(0)); break; case MVT::f64: - RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag); + RetVal = DAG.getCopyFromReg(Chain, dl, IA64::F8, MVT::f64, InFlag); Chain = RetVal.getValue(1); InFlag = RetVal.getValue(2); // XXX dead break; @@ -554,6 +559,7 @@ SDValue IA64TargetLowering:: LowerOperation(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); switch (Op.getOpcode()) { default: assert(0 && "Should not custom lower this!"); case ISD::GlobalTLSAddress: @@ -566,21 +572,21 @@ assert(0 && "Do not know how to return this many arguments!"); abort(); case 1: - AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64); - AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), IA64::AR_PFS, + AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64); + AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, IA64::AR_PFS, AR_PFSVal); - return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal); + return DAG.getNode(IA64ISD::RET_FLAG, dl, MVT::Other, AR_PFSVal); case 3: { // Copy the result into the output register & restore ar.pfs MVT ArgVT = Op.getOperand(1).getValueType(); unsigned ArgReg = ArgVT.isInteger() ? IA64::r8 : IA64::F8; - AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64); - Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), ArgReg, Op.getOperand(1), - SDValue()); - AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), IA64::AR_PFS, AR_PFSVal, - Copy.getValue(1)); - return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, + AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64); + Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, ArgReg, + Op.getOperand(1), SDValue()); + AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), dl, + IA64::AR_PFS, AR_PFSVal, Copy.getValue(1)); + return DAG.getNode(IA64ISD::RET_FLAG, dl, MVT::Other, AR_PFSVal, AR_PFSVal.getValue(1)); } } @@ -589,24 +595,24 @@ case ISD::VAARG: { MVT VT = getPointerTy(); const Value *SV = cast(Op.getOperand(2))->getValue(); - SDValue VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1), + SDValue VAList = DAG.getLoad(VT, dl, Op.getOperand(0), Op.getOperand(1), SV, 0); // Increment the pointer, VAList, to the next vaarg - SDValue VAIncr = DAG.getNode(ISD::ADD, VT, VAList, + SDValue VAIncr = DAG.getNode(ISD::ADD, dl, VT, VAList, DAG.getConstant(VT.getSizeInBits()/8, VT)); // Store the incremented VAList to the legalized pointer - VAIncr = DAG.getStore(VAList.getValue(1), VAIncr, + VAIncr = DAG.getStore(VAList.getValue(1), dl, VAIncr, Op.getOperand(1), SV, 0); // Load the actual argument out of the pointer VAList - return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0); + return DAG.getLoad(Op.getValueType(), dl, VAIncr, VAList, NULL, 0); } case ISD::VASTART: { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64); const Value *SV = cast(Op.getOperand(2))->getValue(); - return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); + return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); } // Frame & Return address. Currently unimplemented case ISD::RETURNADDR: break; Modified: llvm/branches/Apple/Dib/lib/Target/IA64/IA64InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/IA64/IA64InstrInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/IA64/IA64InstrInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/IA64/IA64InstrInfo.cpp Sat Feb 14 07:20:23 2009 @@ -55,28 +55,33 @@ IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond)const { + // FIXME this should probably have a DebugLoc argument + DebugLoc dl = DebugLoc::getUnknownLoc(); // Can only insert uncond branches so far. assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!"); - BuildMI(&MBB, get(IA64::BRL_NOTCALL)).addMBB(TBB); + BuildMI(&MBB, dl, get(IA64::BRL_NOTCALL)).addMBB(TBB); return 1; } bool IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { if (DestRC != SrcRC) { // Not yet supported! return false; } + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode // (SrcReg) DestReg = cmp.eq.unc(r0, r0) - BuildMI(MBB, MI, get(IA64::PCMPEQUNC), DestReg) + BuildMI(MBB, MI, DL, get(IA64::PCMPEQUNC), DestReg) .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg); else // otherwise, MOV works (for both gen. regs and FP regs) - BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(IA64::MOV), DestReg).addReg(SrcReg); return true; } @@ -86,30 +91,34 @@ unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC) const{ + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); if (RC == IA64::FPRegisterClass) { - BuildMI(MBB, MI, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx) + BuildMI(MBB, MI, DL, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx) .addReg(SrcReg, false, false, isKill); } else if (RC == IA64::GRRegisterClass) { - BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx) + BuildMI(MBB, MI, DL, get(IA64::ST8)).addFrameIndex(FrameIdx) .addReg(SrcReg, false, false, isKill); } else if (RC == IA64::PRRegisterClass) { /* we use IA64::r2 as a temporary register for doing this hackery. */ // first we load 0: - BuildMI(MBB, MI, get(IA64::MOV), IA64::r2).addReg(IA64::r0); + BuildMI(MBB, MI, DL, get(IA64::MOV), IA64::r2).addReg(IA64::r0); // then conditionally add 1: - BuildMI(MBB, MI, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2) + BuildMI(MBB, MI, DL, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2) .addImm(1).addReg(SrcReg, false, false, isKill); // and then store it to the stack - BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2); + BuildMI(MBB, MI, DL, get(IA64::ST8)) + .addFrameIndex(FrameIdx) + .addReg(IA64::r2); } else assert(0 && "sorry, I don't know how to store this sort of reg in the stack\n"); } void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - bool isKill, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, + bool isKill, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; if (RC == IA64::FPRegisterClass) { @@ -123,7 +132,8 @@ "sorry, I don't know how to store this sort of reg\n"); } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) @@ -140,28 +150,34 @@ } void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, int FrameIdx, - const TargetRegisterClass *RC)const{ + MachineBasicBlock::iterator MI, + unsigned DestReg, int FrameIdx, + const TargetRegisterClass *RC)const{ + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); if (RC == IA64::FPRegisterClass) { - BuildMI(MBB, MI, get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx); + BuildMI(MBB, MI, DL, get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx); } else if (RC == IA64::GRRegisterClass) { - BuildMI(MBB, MI, get(IA64::LD8), DestReg).addFrameIndex(FrameIdx); - } else if (RC == IA64::PRRegisterClass) { - // first we load a byte from the stack into r2, our 'predicate hackery' - // scratch reg - BuildMI(MBB, MI, get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx); - // then we compare it to zero. If it _is_ zero, compare-not-equal to - // r0 gives us 0, which is what we want, so that's nice. - BuildMI(MBB, MI, get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0); - } else assert(0 && - "sorry, I don't know how to load this sort of reg from the stack\n"); + BuildMI(MBB, MI, DL, get(IA64::LD8), DestReg).addFrameIndex(FrameIdx); + } else if (RC == IA64::PRRegisterClass) { + // first we load a byte from the stack into r2, our 'predicate hackery' + // scratch reg + BuildMI(MBB, MI, DL, get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx); + // then we compare it to zero. If it _is_ zero, compare-not-equal to + // r0 gives us 0, which is what we want, so that's nice. + BuildMI(MBB, MI, DL, get(IA64::CMPNE), DestReg) + .addReg(IA64::r2) + .addReg(IA64::r0); + } else { + assert(0 && + "sorry, I don't know how to load this sort of reg from the stack\n"); + } } void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; if (RC == IA64::FPRegisterClass) { @@ -172,10 +188,11 @@ Opc = IA64::LD1; } else { assert(0 && - "sorry, I don't know how to store this sort of reg\n"); + "sorry, I don't know how to load this sort of reg\n"); } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) Modified: llvm/branches/Apple/Dib/lib/Target/IA64/IA64RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/IA64/IA64RegisterInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/IA64/IA64RegisterInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/IA64/IA64RegisterInfo.cpp Sat Feb 14 07:20:23 2009 @@ -88,6 +88,7 @@ // ' MachineInstr *Old = I; unsigned Amount = Old->getOperand(0).getImm(); + DebugLoc dl = Old->getDebugLoc(); if (Amount != 0) { // We need to keep the stack aligned properly. To do this, we round the // amount of space needed for the outgoing arguments up to the next @@ -97,12 +98,12 @@ // Replace the pseudo instruction with a new instruction... if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) { - BuildMI(MBB, I, TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12) - .addImm(-Amount); + BuildMI(MBB, I, dl, TII.get(IA64::ADDIMM22), IA64::r12) + .addReg(IA64::r12).addImm(-Amount); } else { assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP); - BuildMI(MBB, I, TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12) - .addImm(Amount); + BuildMI(MBB, I, dl, TII.get(IA64::ADDIMM22), IA64::r12) + .addReg(IA64::r12).addImm(Amount); } } } @@ -118,6 +119,7 @@ MachineInstr &MI = *II; MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); + DebugLoc dl = MI.getDebugLoc(); bool FP = hasFP(MF); @@ -146,13 +148,13 @@ // Fix up the old: MI.getOperand(i).ChangeToRegister(IA64::r22, false); //insert the new - BuildMI(MBB, II, TII.get(IA64::ADDIMM22), IA64::r22) + BuildMI(MBB, II, dl, TII.get(IA64::ADDIMM22), IA64::r22) .addReg(BaseRegister).addImm(Offset); } else { // it's big //fix up the old: MI.getOperand(i).ChangeToRegister(IA64::r22, false); - BuildMI(MBB, II, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset); - BuildMI(MBB, II, TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister) + BuildMI(MBB, II, dl, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset); + BuildMI(MBB, II, dl, TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister) .addReg(IA64::r22); } @@ -163,6 +165,7 @@ MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); bool FP = hasFP(MF); + DebugLoc dl = DebugLoc::getUnknownLoc(); // first, we handle the 'alloc' instruction, that should be right up the // top of any function @@ -205,7 +208,7 @@ } } - BuildMI(MBB, MBBI, TII.get(IA64::ALLOC)). + BuildMI(MBB, MBBI, dl, TII.get(IA64::ALLOC)). addReg(dstRegOfPseudoAlloc).addImm(0). addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0); @@ -230,23 +233,24 @@ // adjust stack pointer: r12 -= numbytes if (NumBytes <= 8191) { - BuildMI(MBB, MBBI, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12). + BuildMI(MBB, MBBI, dl, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12). addImm(-NumBytes); } else { // we use r22 as a scratch register here // first load the decrement into r22 - BuildMI(MBB, MBBI, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes); + BuildMI(MBB, MBBI, dl, TII.get(IA64::MOVLIMM64), IA64::r22). + addImm(-NumBytes); // FIXME: MOVLSI32 expects a _u_32imm // then add (subtract) it to r12 (stack ptr) - BuildMI(MBB, MBBI, TII.get(IA64::ADD), IA64::r12) + BuildMI(MBB, MBBI, dl, TII.get(IA64::ADD), IA64::r12) .addReg(IA64::r12).addReg(IA64::r22); } // now if we need to, save the old FP and set the new if (FP) { - BuildMI(MBB, MBBI, TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5); + BuildMI(MBB, MBBI,dl,TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5); // this must be the last instr in the prolog ? (XXX: why??) - BuildMI(MBB, MBBI, TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12); + BuildMI(MBB, MBBI, dl, TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12); } } @@ -257,6 +261,7 @@ MachineBasicBlock::iterator MBBI = prior(MBB.end()); assert(MBBI->getOpcode() == IA64::RET && "Can only insert epilog into returning blocks"); + DebugLoc dl = DebugLoc::getUnknownLoc(); bool FP = hasFP(MF); @@ -267,20 +272,20 @@ if (FP) { //copy the FP into the SP (discards allocas) - BuildMI(MBB, MBBI, TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5); + BuildMI(MBB, MBBI, dl, TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5); //restore the FP - BuildMI(MBB, MBBI, TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5); + BuildMI(MBB, MBBI, dl, TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5); } if (NumBytes != 0) { if (NumBytes <= 8191) { - BuildMI(MBB, MBBI, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12). - addImm(NumBytes); + BuildMI(MBB, MBBI, dl, TII.get(IA64::ADDIMM22),IA64::r12). + addReg(IA64::r12).addImm(NumBytes); } else { - BuildMI(MBB, MBBI, TII.get(IA64::MOVLIMM64), IA64::r22). + BuildMI(MBB, MBBI, dl, TII.get(IA64::MOVLIMM64), IA64::r22). addImm(NumBytes); - BuildMI(MBB, MBBI, TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12). + BuildMI(MBB, MBBI, dl, TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12). addReg(IA64::r22); } } Modified: llvm/branches/Apple/Dib/lib/Target/Mips/MipsDelaySlotFiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Mips/MipsDelaySlotFiller.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/Mips/MipsDelaySlotFiller.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/Mips/MipsDelaySlotFiller.cpp Sat Feb 14 07:20:23 2009 @@ -62,7 +62,7 @@ if (I->getDesc().hasDelaySlot()) { MachineBasicBlock::iterator J = I; ++J; - BuildMI(MBB, J, TII->get(Mips::NOP)); + BuildMI(MBB, J, I->getDebugLoc(), TII->get(Mips::NOP)); ++FilledSlots; Changed = true; } Modified: llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelDAGToDAG.cpp Sat Feb 14 07:20:23 2009 @@ -126,8 +126,9 @@ break; } assert(GP && "GOT PTR not in liveins"); + // FIXME is there a sensible place to get debug info for this? return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), - GP, MVT::i32); + DebugLoc::getUnknownLoc(), GP, MVT::i32); } /// ComplexPattern used on MipsInstrInfo @@ -187,6 +188,7 @@ { SDNode *Node = N.getNode(); unsigned Opcode = Node->getOpcode(); + DebugLoc dl = Node->getDebugLoc(); // Dump information about the Node being selected #ifndef NDEBUG @@ -238,8 +240,8 @@ SDValue RHS = Node->getOperand(1); MVT VT = LHS.getValueType(); - SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, VT, Ops, 2); - SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT, + SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, dl, VT, Ops, 2); + SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, dl, VT, SDValue(Carry,0), RHS); return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, MVT::Flag, @@ -260,13 +262,13 @@ else Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV); - SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2); + SDNode *Node = CurDAG->getTargetNode(Op, dl, MVT::Flag, Op1, Op2); SDValue InFlag = SDValue(Node, 0); - SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, MVT::i32, + SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, dl, MVT::i32, MVT::Flag, InFlag); InFlag = SDValue(Lo,1); - SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, MVT::i32, InFlag); + SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, dl, MVT::i32, InFlag); if (!N.getValue(0).use_empty()) ReplaceUses(N.getValue(0), SDValue(Lo,0)); @@ -285,14 +287,15 @@ SDValue MulOp2 = Node->getOperand(1); unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT); - SDNode *MulNode = CurDAG->getTargetNode(MulOp, MVT::Flag, MulOp1, MulOp2); + SDNode *MulNode = CurDAG->getTargetNode(MulOp, dl, + MVT::Flag, MulOp1, MulOp2); SDValue InFlag = SDValue(MulNode, 0); if (MulOp == ISD::MUL) - return CurDAG->getTargetNode(Mips::MFLO, MVT::i32, InFlag); + return CurDAG->getTargetNode(Mips::MFLO, dl, MVT::i32, InFlag); else - return CurDAG->getTargetNode(Mips::MFHI, MVT::i32, InFlag); + return CurDAG->getTargetNode(Mips::MFHI, dl, MVT::i32, InFlag); } /// Div/Rem operations @@ -311,10 +314,10 @@ Op = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu); MOp = Mips::MFHI; } - SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2); + SDNode *Node = CurDAG->getTargetNode(Op, dl, MVT::Flag, Op1, Op2); SDValue InFlag = SDValue(Node, 0); - return CurDAG->getTargetNode(MOp, MVT::i32, InFlag); + return CurDAG->getTargetNode(MOp, dl, MVT::i32, InFlag); } // Get target GOT address. @@ -344,18 +347,18 @@ // Use load to get GOT target SDValue Ops[] = { Callee, GPReg, Chain }; - SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, MVT::i32, + SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, dl, MVT::i32, MVT::Other, Ops, 3), 0); Chain = Load.getValue(1); // Call target must be on T9 - Chain = CurDAG->getCopyToReg(Chain, T9Reg, Load, InFlag); + Chain = CurDAG->getCopyToReg(Chain, dl, T9Reg, Load, InFlag); } else /// Indirect call - Chain = CurDAG->getCopyToReg(Chain, T9Reg, Callee, InFlag); + Chain = CurDAG->getCopyToReg(Chain, dl, T9Reg, Callee, InFlag); // Emit Jump and Link Register - SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, MVT::Other, + SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, dl, MVT::Other, MVT::Flag, T9Reg, Chain); Chain = SDValue(ResNode, 0); InFlag = SDValue(ResNode, 1); Modified: llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelLowering.cpp Sat Feb 14 07:20:23 2009 @@ -280,6 +280,7 @@ { const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); bool isFPCmp = false; + DebugLoc dl = MI->getDebugLoc(); switch (MI->getOpcode()) { default: assert(false && "Unexpected instr type to insert"); @@ -317,9 +318,9 @@ Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm(); // Get the branch opcode from the branch code. unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC)); - BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB); + BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); } else - BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg()) + BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg()) .addReg(Mips::ZERO).addMBB(sinkMBB); F->insert(It, copy0MBB); @@ -348,7 +349,7 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg()) + BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB); @@ -367,22 +368,23 @@ { SDValue Chain = Op.getOperand(0); SDValue Size = Op.getOperand(1); + DebugLoc dl = Op.getDebugLoc(); // Get a reference from Mips stack pointer - SDValue StackPointer = DAG.getCopyFromReg(Chain, Mips::SP, MVT::i32); + SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32); // Subtract the dynamic size from the actual stack size to // obtain the new stack size. - SDValue Sub = DAG.getNode(ISD::SUB, MVT::i32, StackPointer, Size); + SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size); // The Sub result contains the new stack start address, so it // must be placed in the stack pointer register. - Chain = DAG.getCopyToReg(StackPointer.getValue(1), Mips::SP, Sub); + Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub); // This node always has two return values: a new stack pointer // value and a chain SDValue Ops[2] = { Sub, Chain }; - return DAG.getMergeValues(Ops, 2); + return DAG.getMergeValues(Ops, 2, dl); } SDValue MipsTargetLowering:: @@ -390,19 +392,20 @@ { SDValue LHS = Op.getOperand(0); SDValue RHS = Op.getOperand(1); - + DebugLoc dl = Op.getDebugLoc(); + if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp) return Op; SDValue True = DAG.getConstant(1, MVT::i32); SDValue False = DAG.getConstant(0, MVT::i32); - SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(), + SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(), LHS, True, False, LHS.getOperand(2)); - SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(), + SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(), RHS, True, False, RHS.getOperand(2)); - return DAG.getNode(Op.getOpcode(), MVT::i32, LSEL, RSEL); + return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL); } SDValue MipsTargetLowering:: @@ -412,6 +415,7 @@ // the block to branch to if the condition is true. SDValue Chain = Op.getOperand(0); SDValue Dest = Op.getOperand(2); + DebugLoc dl = Op.getDebugLoc(); if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp) return Op; @@ -422,7 +426,7 @@ (Mips::CondCode)cast(CCNode)->getZExtValue(); SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); - return DAG.getNode(MipsISD::FPBrcond, Op.getValueType(), Chain, BrCode, + return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, Dest, CondRes); } @@ -433,11 +437,12 @@ // and #1) and the condition code to compare them with (op #2) as a // CondCodeSDNode. SDValue LHS = Op.getOperand(0); - SDValue RHS = Op.getOperand(1); + SDValue RHS = Op.getOperand(1); + DebugLoc dl = Op.getDebugLoc(); ISD::CondCode CC = cast(Op.getOperand(2))->get(); - return DAG.getNode(MipsISD::FPCmp, Op.getValueType(), LHS, RHS, + return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS, DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); } @@ -447,6 +452,7 @@ SDValue Cond = Op.getOperand(0); SDValue True = Op.getOperand(1); SDValue False = Op.getOperand(2); + DebugLoc dl = Op.getDebugLoc(); // if the incomming condition comes from a integer compare, the select // operation must be SelectCC or a conditional move if the subtarget @@ -454,20 +460,22 @@ if (Cond.getOpcode() != MipsISD::FPCmp) { if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint()) return Op; - return DAG.getNode(MipsISD::SelectCC, True.getValueType(), + return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(), Cond, True, False); } // if the incomming condition comes from fpcmp, the select // operation must use FPSelectCC. SDValue CCNode = Cond.getOperand(2); - return DAG.getNode(MipsISD::FPSelectCC, True.getValueType(), + return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(), Cond, True, False, CCNode); } SDValue MipsTargetLowering:: LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { + // FIXME there isn't actually debug info here + DebugLoc dl = Op.getDebugLoc(); GlobalValue *GV = cast(Op)->getGlobal(); SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); @@ -476,23 +484,24 @@ SDValue Ops[] = { GA }; // %gp_rel relocation if (!isa(GV) && IsGlobalInSmallSection(GV)) { - SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1); - SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32); - return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); + SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, 1, Ops, 1); + SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); + return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); } // %hi/%lo relocation - SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1); - SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA); - return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo); + SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, 1, Ops, 1); + SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA); + return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); } else { // Abicall relocations, TODO: make this cleaner. - SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0); + SDValue ResNode = DAG.getLoad(MVT::i32, dl, + DAG.getEntryNode(), GA, NULL, 0); // On functions and global targets not internal linked only // a load from got/GP is necessary for PIC to work. if (!GV->hasLocalLinkage() || isa(GV)) return ResNode; - SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA); - return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo); + SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA); + return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo); } assert(0 && "Dont know how to handle GlobalAddress"); @@ -511,6 +520,8 @@ { SDValue ResNode; SDValue HiPart; + // FIXME there isn't actually debug info here + DebugLoc dl = Op.getDebugLoc(); MVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast(Op); @@ -519,12 +530,12 @@ if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { const MVT *VTs = DAG.getNodeValueTypes(MVT::i32); SDValue Ops[] = { JTI }; - HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1); + HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, 1, Ops, 1); } else // Emit Load from Global Pointer - HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0); + HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0); - SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI); - ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo); + SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI); + ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); return ResNode; } @@ -536,6 +547,8 @@ ConstantPoolSDNode *N = cast(Op); Constant *C = N->getConstVal(); SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); + // FIXME there isn't actually debug info here + DebugLoc dl = Op.getDebugLoc(); // gp_rel relocation // FIXME: we should reference the constant pool using small data sections, @@ -545,12 +558,12 @@ //if (!Subtarget->hasABICall() && // IsInSmallSection(getTargetData()->getTypePaddedSize(C->getType()))) { // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); - // SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32); + // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); //} else { // %hi/%lo relocation - SDValue HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP); - SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP); - ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo); + SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP); + SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP); + ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); //} return ResNode; @@ -586,6 +599,7 @@ SDValue Callee = TheCall->getCallee(); bool isVarArg = TheCall->isVarArg(); unsigned CC = TheCall->getCallingConv(); + DebugLoc dl = TheCall->getDebugLoc(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -627,13 +641,13 @@ default: assert(0 && "Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: - Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); + Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); break; case CCValAssign::ZExt: - Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); + Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); break; case CCValAssign::AExt: - Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); + Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); break; } @@ -659,13 +673,13 @@ // emit ISD::STORE whichs stores the // parameter value to a stack Location - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); } // Transform all store nodes into one single node because all store // nodes are independent of each other. if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token @@ -674,7 +688,7 @@ // stuck together. SDValue InFlag; for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, + Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } @@ -706,7 +720,7 @@ if (InFlag.getNode()) Ops.push_back(InFlag); - Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size()); + Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); InFlag = Chain.getValue(1); // Create the CALLSEQ_END node. @@ -736,9 +750,9 @@ // Reload GP value. FI = MipsFI->getGPFI(); SDValue FIN = DAG.getFrameIndex(FI,getPointerTy()); - SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0); + SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0); Chain = GPLoad.getValue(1); - Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32), + Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32), GPLoad, SDValue(0,0)); InFlag = Chain.getValue(1); } @@ -758,6 +772,7 @@ unsigned CallingConv, SelectionDAG &DAG) { bool isVarArg = TheCall->isVarArg(); + DebugLoc dl = TheCall->getDebugLoc(); // Assign locations to each value returned by this call. SmallVector RVLocs; @@ -768,7 +783,7 @@ // Copy all of the result registers out of their specified physreg. for (unsigned i = 0; i != RVLocs.size(); ++i) { - Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(), + Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), RVLocs[i].getValVT(), InFlag).getValue(1); InFlag = Chain.getValue(2); ResultVals.push_back(Chain.getValue(0)); @@ -777,7 +792,7 @@ ResultVals.push_back(Chain); // Merge everything together with a MERGE_VALUES node. - return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(), &ResultVals[0], ResultVals.size()).getNode(); } @@ -796,6 +811,7 @@ MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo(); + DebugLoc dl = Op.getDebugLoc(); bool isVarArg = cast(Op.getOperand(2))->getZExtValue() != 0; unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); @@ -840,20 +856,20 @@ // Transform the arguments stored on // physical registers into virtual ones unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); - SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); + SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT); // If this is an 8 or 16-bit value, it is really passed promoted // to 32 bits. Insert an assert[sz]ext to capture this, then // truncate to the right size. if (VA.getLocInfo() == CCValAssign::SExt) - ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue, + ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, DAG.getValueType(VA.getValVT())); else if (VA.getLocInfo() == CCValAssign::ZExt) - ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue, + ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, DAG.getValueType(VA.getValVT())); if (VA.getLocInfo() != CCValAssign::Full) - ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue); + ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); ArgValues.push_back(ArgValue); @@ -877,7 +893,7 @@ // emit ISD::STORE whichs stores the // parameter value to a stack Location - ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0)); + ArgValues.push_back(DAG.getStore(Root, dl, ArgValue, PtrOff, NULL, 0)); } } else { // VA.isRegLoc() @@ -900,7 +916,7 @@ // Create load nodes to retrieve arguments from the stack SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); - ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0)); + ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0)); } } @@ -913,14 +929,14 @@ Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); MipsFI->setSRetReturnReg(Reg); } - SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]); - Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root); + SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]); + Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root); } ArgValues.push_back(Root); // Return the new list of results. - return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), &ArgValues[0], ArgValues.size()).getValue(Op.getResNo()); } @@ -936,6 +952,7 @@ SmallVector RVLocs; unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); + DebugLoc dl = Op.getDebugLoc(); // CCState - Info about the registers and stack slot. CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs); @@ -962,7 +979,8 @@ // ISD::RET => ret chain, (regnum1,val1), ... // So i*2+1 index only the regnums - Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); + Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), + Op.getOperand(i*2+1), Flag); // guarantee that all emitted copies are // stuck together, avoiding something bad @@ -980,18 +998,18 @@ if (!Reg) assert(0 && "sret virtual register not created in the entry block"); - SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy()); + SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); - Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag); + Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); Flag = Chain.getValue(1); } // Return on Mips is always a "jr $ra" if (Flag.getNode()) - return DAG.getNode(MipsISD::Ret, MVT::Other, + return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); else // Return Void - return DAG.getNode(MipsISD::Ret, MVT::Other, + return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(Mips::RA, MVT::i32)); } Modified: llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.cpp Sat Feb 14 07:20:23 2009 @@ -118,7 +118,9 @@ void MipsInstrInfo:: insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { - BuildMI(MBB, MI, get(Mips::NOP)); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + BuildMI(MBB, MI, DL, get(Mips::NOP)); } bool MipsInstrInfo:: @@ -126,22 +128,25 @@ unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (DestRC != SrcRC) { if ((DestRC == Mips::CPURegsRegisterClass) && (SrcRC == Mips::FGR32RegisterClass)) - BuildMI(MBB, I, get(Mips::MFC1), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg); else if ((DestRC == Mips::CPURegsRegisterClass) && (SrcRC == Mips::AFGR32RegisterClass)) - BuildMI(MBB, I, get(Mips::MFC1A), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::MFC1A), DestReg).addReg(SrcReg); else if ((DestRC == Mips::FGR32RegisterClass) && (SrcRC == Mips::CPURegsRegisterClass)) - BuildMI(MBB, I, get(Mips::MTC1), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg); else if ((DestRC == Mips::AFGR32RegisterClass) && (SrcRC == Mips::CPURegsRegisterClass)) - BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::MTC1A), DestReg).addReg(SrcReg); else if ((DestRC == Mips::AFGR32RegisterClass) && (SrcRC == Mips::CPURegsRegisterClass)) - BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::MTC1A), DestReg).addReg(SrcReg); else if ((SrcRC == Mips::CCRRegisterClass) && (SrcReg == Mips::FCR31)) return true; // This register is used implicitly, no copy needed. @@ -151,11 +156,11 @@ else if ((DestRC == Mips::HILORegisterClass) && (SrcRC == Mips::CPURegsRegisterClass)) { unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO; - BuildMI(MBB, I, get(Opc), DestReg); + BuildMI(MBB, I, DL, get(Opc), DestReg); } else if ((SrcRC == Mips::HILORegisterClass) && (DestRC == Mips::CPURegsRegisterClass)) { unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO; - BuildMI(MBB, I, get(Opc), DestReg); + BuildMI(MBB, I, DL, get(Opc), DestReg); } else // DestRC != SrcRC, Can't copy this register return false; @@ -164,14 +169,14 @@ } if (DestRC == Mips::CPURegsRegisterClass) - BuildMI(MBB, I, get(Mips::ADDu), DestReg).addReg(Mips::ZERO) + BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO) .addReg(SrcReg); else if (DestRC == Mips::FGR32RegisterClass) - BuildMI(MBB, I, get(Mips::FMOV_SO32), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::FMOV_SO32), DestReg).addReg(SrcReg); else if (DestRC == Mips::AFGR32RegisterClass) - BuildMI(MBB, I, get(Mips::FMOV_AS32), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::FMOV_AS32), DestReg).addReg(SrcReg); else if (DestRC == Mips::AFGR64RegisterClass) - BuildMI(MBB, I, get(Mips::FMOV_D32), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg); else // Can't copy this register return false; @@ -181,10 +186,14 @@ void MipsInstrInfo:: storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned SrcReg, bool isKill, int FI, - const TargetRegisterClass *RC) const + unsigned SrcReg, bool isKill, int FI, + const TargetRegisterClass *RC) const { unsigned Opc; + + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (RC == Mips::CPURegsRegisterClass) Opc = Mips::SW; else if (RC == Mips::FGR32RegisterClass) @@ -196,7 +205,7 @@ else assert(0 && "Can't store this register to stack slot"); - BuildMI(MBB, I, get(Opc)).addReg(SrcReg, false, false, isKill) + BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, false, false, isKill) .addImm(0).addFrameIndex(FI); } @@ -216,7 +225,8 @@ else assert(0 && "Can't store this register"); - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)) + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) .addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; @@ -248,12 +258,14 @@ else assert(0 && "Can't load this register from stack slot"); - BuildMI(MBB, I, get(Opc), DestReg).addImm(0).addFrameIndex(FI); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0).addFrameIndex(FI); } void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc; if (RC == Mips::CPURegsRegisterClass) @@ -267,7 +279,8 @@ else assert(0 && "Can't load this register"); - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) @@ -299,12 +312,13 @@ if (Ops[0] == 0) { // COPY -> STORE unsigned SrcReg = MI->getOperand(2).getReg(); bool isKill = MI->getOperand(2).isKill(); - NewMI = BuildMI(MF, get(Mips::SW)).addReg(SrcReg, false, false, isKill) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW)) + .addReg(SrcReg, false, false, isKill) .addImm(0).addFrameIndex(FI); } else { // COPY -> LOAD unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(MF, get(Mips::LW)) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW)) .addReg(DstReg, true, false, false, isDead) .addImm(0).addFrameIndex(FI); } @@ -331,12 +345,13 @@ if (Ops[0] == 0) { // COPY -> STORE unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = BuildMI(MF, get(StoreOpc)).addReg(SrcReg, false, false, isKill) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc)) + .addReg(SrcReg, false, false, isKill) .addImm(0).addFrameIndex(FI) ; } else { // COPY -> LOAD unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(MF, get(LoadOpc)) + NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc)) .addReg(DstReg, true, false, false, isDead) .addImm(0).addFrameIndex(FI); } @@ -539,6 +554,8 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const { + // FIXME this should probably have a DebugLoc argument + DebugLoc dl = DebugLoc::getUnknownLoc(); // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) && @@ -547,18 +564,18 @@ if (FBB == 0) { // One way branch. if (Cond.empty()) { // Unconditional branch? - BuildMI(&MBB, get(Mips::J)).addMBB(TBB); + BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB); } else { // Conditional branch. unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm()); const TargetInstrDesc &TID = get(Opc); if (TID.getNumOperands() == 3) - BuildMI(&MBB, TID).addReg(Cond[1].getReg()) + BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()) .addReg(Cond[2].getReg()) .addMBB(TBB); else - BuildMI(&MBB, TID).addReg(Cond[1].getReg()) + BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()) .addMBB(TBB); } @@ -570,12 +587,12 @@ const TargetInstrDesc &TID = get(Opc); if (TID.getNumOperands() == 3) - BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg()) + BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg()) .addMBB(TBB); else - BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addMBB(TBB); + BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB); - BuildMI(&MBB, get(Mips::J)).addMBB(FBB); + BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB); return 2; } Modified: llvm/branches/Apple/Dib/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Mips/MipsRegisterInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/Mips/MipsRegisterInfo.cpp Sat Feb 14 07:20:23 2009 @@ -391,6 +391,7 @@ MachineFrameInfo *MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo(); MachineBasicBlock::iterator MBBI = MBB.begin(); + DebugLoc dl = DebugLoc::getUnknownLoc(); bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_); // Get the right frame order for Mips. @@ -405,21 +406,21 @@ int FPOffset = MipsFI->getFPStackOffset(); int RAOffset = MipsFI->getRAStackOffset(); - BuildMI(MBB, MBBI, TII.get(Mips::NOREORDER)); + BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER)); // TODO: check need from GP here. if (isPIC && Subtarget.isABI_O32()) - BuildMI(MBB, MBBI, TII.get(Mips::CPLOAD)).addReg(getPICCallReg()); - BuildMI(MBB, MBBI, TII.get(Mips::NOMACRO)); + BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD)).addReg(getPICCallReg()); + BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO)); // Adjust stack : addi sp, sp, (-imm) - BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP) + BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP) .addReg(Mips::SP).addImm(-StackSize); // Save the return address only if the function isnt a leaf one. // sw $ra, stack_loc($sp) if (MFI->hasCalls()) { - BuildMI(MBB, MBBI, TII.get(Mips::SW)) + BuildMI(MBB, MBBI, dl, TII.get(Mips::SW)) .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP); } @@ -427,17 +428,17 @@ // to point to the stack pointer if (hasFP(MF)) { // sw $fp,stack_loc($sp) - BuildMI(MBB, MBBI, TII.get(Mips::SW)) + BuildMI(MBB, MBBI, dl, TII.get(Mips::SW)) .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP); // move $fp, $sp - BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::FP) + BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP) .addReg(Mips::SP).addReg(Mips::ZERO); } // PIC speficic function prologue if ((isPIC) && (MFI->hasCalls())) { - BuildMI(MBB, MBBI, TII.get(Mips::CPRESTORE)) + BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE)) .addImm(MipsFI->getGPStackOffset()); } } @@ -448,6 +449,7 @@ MachineBasicBlock::iterator MBBI = prior(MBB.end()); MachineFrameInfo *MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo(); + DebugLoc dl = DebugLoc::getUnknownLoc(); // Get the number of bytes from FrameInfo int NumBytes = (int) MFI->getStackSize(); @@ -460,24 +462,24 @@ // stack pointer if (hasFP(MF)) { // move $sp, $fp - BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::SP) + BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::SP) .addReg(Mips::FP).addReg(Mips::ZERO); // lw $fp,stack_loc($sp) - BuildMI(MBB, MBBI, TII.get(Mips::LW)) + BuildMI(MBB, MBBI, dl, TII.get(Mips::LW)) .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP); } // Restore the return address only if the function isnt a leaf one. // lw $ra, stack_loc($sp) if (MFI->hasCalls()) { - BuildMI(MBB, MBBI, TII.get(Mips::LW)) + BuildMI(MBB, MBBI, dl, TII.get(Mips::LW)) .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP); } // adjust stack : insert addi sp, sp, (imm) if (NumBytes) { - BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP) + BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP) .addReg(Mips::SP).addImm(NumBytes); } } Modified: llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.cpp Sat Feb 14 07:20:23 2009 @@ -305,14 +305,16 @@ MachineFunction &MF = DAG.getMachineFunction(); const Function *Func = MF.getFunction(); const std::string Name = Func->getName(); - + FrameIndexSDNode *FR = dyn_cast(SDValue(N,0)); + // FIXME there isn't really debug info here + DebugLoc dl = FR->getDebugLoc(); int Index = FR->getIndex(); SDValue FI[2]; FI[0] = DAG.getTargetFrameIndex(Index, MVT::i8); FI[1] = DAG.getTargetFrameIndex(Index + 1, MVT::i8); - return DAG.getNode(ISD::BUILD_PAIR, N->getValueType(0), FI[0], FI[1]); + return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), FI[0], FI[1]); } @@ -323,12 +325,13 @@ SDValue Ptr = St->getBasePtr(); MVT ValueType = Src.getValueType(); unsigned StoreOffset = 0; + DebugLoc dl = N->getDebugLoc(); SDValue PtrLo, PtrHi; - LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset); + LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset, dl); if (ValueType == MVT::i8) { - return DAG.getNode (PIC16ISD::PIC16Store, MVT::Other, Chain, Src, + return DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, Src, PtrLo, PtrHi, DAG.getConstant (0 + StoreOffset, MVT::i8)); } @@ -341,16 +344,16 @@ ChainLo = Chain.getOperand(0); ChainHi = Chain.getOperand(1); } - SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, + SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo, SrcLo, PtrLo, PtrHi, DAG.getConstant (0 + StoreOffset, MVT::i8)); - SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, ChainHi, + SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi, SrcHi, PtrLo, PtrHi, DAG.getConstant (1 + StoreOffset, MVT::i8)); - return DAG.getNode(ISD::TokenFactor, MVT::Other, getChain(Store1), + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, getChain(Store1), getChain(Store2)); } else if (ValueType == MVT::i32) { @@ -378,28 +381,28 @@ ChainHi1 = ChainHi.getOperand(0); ChainHi2 = ChainHi.getOperand(1); } - SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, + SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo1, SrcLo1, PtrLo, PtrHi, DAG.getConstant (0 + StoreOffset, MVT::i8)); - SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, ChainLo2, + SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo2, SrcLo2, PtrLo, PtrHi, DAG.getConstant (1 + StoreOffset, MVT::i8)); - SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, ChainHi1, + SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi1, SrcHi1, PtrLo, PtrHi, DAG.getConstant (2 + StoreOffset, MVT::i8)); - SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, ChainHi2, + SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi2, SrcHi2, PtrLo, PtrHi, DAG.getConstant (3 + StoreOffset, MVT::i8)); - SDValue RetLo = DAG.getNode(ISD::TokenFactor, MVT::Other, getChain(Store1), - getChain(Store2)); - SDValue RetHi = DAG.getNode(ISD::TokenFactor, MVT::Other, getChain(Store3), - getChain(Store4)); - return DAG.getNode(ISD::TokenFactor, MVT::Other, RetLo, RetHi); + SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + getChain(Store1), getChain(Store2)); + SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + getChain(Store3), getChain(Store4)); + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, RetLo, RetHi); } else { @@ -411,26 +414,30 @@ SDValue PIC16TargetLowering::ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG) { ExternalSymbolSDNode *ES = dyn_cast(SDValue(N, 0)); + // FIXME there isn't really debug info here + DebugLoc dl = ES->getDebugLoc(); SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8); - SDValue Lo = DAG.getNode(PIC16ISD::Lo, MVT::i8, TES); - SDValue Hi = DAG.getNode(PIC16ISD::Hi, MVT::i8, TES); + SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TES); + SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TES); - return DAG.getNode(ISD::BUILD_PAIR, MVT::i16, Lo, Hi); + return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi); } // ExpandGlobalAddress - SDValue PIC16TargetLowering::ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG) { GlobalAddressSDNode *G = dyn_cast(SDValue(N, 0)); + // FIXME there isn't really debug info here + DebugLoc dl = G->getDebugLoc(); SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i8, G->getOffset()); - SDValue Lo = DAG.getNode(PIC16ISD::Lo, MVT::i8, TGA); - SDValue Hi = DAG.getNode(PIC16ISD::Hi, MVT::i8, TGA); + SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TGA); + SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TGA); - return DAG.getNode(ISD::BUILD_PAIR, MVT::i16, Lo, Hi); + return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi); } bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) { @@ -499,9 +506,9 @@ } void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG, - SDValue &Lo, SDValue &Hi) { SDNode *N = Op.getNode(); + DebugLoc dl = N->getDebugLoc(); MVT NewVT; std::vector Opers; NewVT = getTypeToTransformTo(N->getValueType(0)); @@ -509,12 +516,12 @@ // extract the lo component Opers.push_back(Op); Opers.push_back(DAG.getConstant(0,MVT::i8)); - Lo = DAG.getNode(ISD::EXTRACT_ELEMENT,NewVT,&Opers[0],Opers.size()); + Lo = DAG.getNode(ISD::EXTRACT_ELEMENT,dl,NewVT,&Opers[0],Opers.size()); // extract the hi component Opers.clear(); Opers.push_back(Op); Opers.push_back(DAG.getConstant(1,MVT::i8)); - Hi = DAG.getNode(ISD::EXTRACT_ELEMENT,NewVT,&Opers[0],Opers.size()); + Hi = DAG.getNode(ISD::EXTRACT_ELEMENT,dl,NewVT,&Opers[0],Opers.size()); } // Legalize FrameIndex into ExternalSymbol and offset. @@ -549,7 +556,7 @@ void PIC16TargetLowering:: LegalizeAddress(SDValue Ptr, SelectionDAG &DAG, SDValue &Lo, SDValue &Hi, - unsigned &Offset) { + unsigned &Offset, DebugLoc dl) { // Offset, by default, should be 0 Offset = 0; @@ -608,8 +615,8 @@ GetExpandedParts(Ptr, DAG, Lo, Hi); // Put the hi and lo parts into FSR. - Lo = DAG.getNode(PIC16ISD::MTLO, MVT::i8, Lo); - Hi = DAG.getNode(PIC16ISD::MTHI, MVT::i8, Hi); + Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Lo); + Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Hi); return; } @@ -631,6 +638,7 @@ LoadSDNode *LD = dyn_cast(SDValue(N, 0)); SDValue Chain = LD->getChain(); SDValue Ptr = LD->getBasePtr(); + DebugLoc dl = LD->getDebugLoc(); SDValue Load, Offset; SDVTList Tys; @@ -640,7 +648,7 @@ // Legalize direct/indirect addresses. This will give the lo and hi parts // of the address and the offset. - LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, LoadOffset); + LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, LoadOffset, dl); // Load from the pointer (direct address or FSR) VT = N->getValueType(0); @@ -653,7 +661,7 @@ // Add the pointer offset if any Offset = DAG.getConstant(iter + LoadOffset, MVT::i8); Tys = DAG.getVTList(MVT::i8, MVT::Other); - Load = DAG.getNode(PIC16ISD::PIC16Load, Tys, Chain, PtrLo, PtrHi, + Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi, Offset); PICLoads.push_back(Load); } @@ -675,7 +683,7 @@ for (iter=0; iter(Op); unsigned NumOps = TheCall->getNumArgs(); + DebugLoc dl = TheCall->getDebugLoc(); std::string Name; SDValue Arg, StoreAt; MVT ArgVT; @@ -885,7 +897,7 @@ SDValue PtrLo, PtrHi; unsigned AddressOffset; int StoreOffset = 0; - LegalizeAddress(FrameAddress, DAG, PtrLo, PtrHi, AddressOffset); + LegalizeAddress(FrameAddress, DAG, PtrLo, PtrHi, AddressOffset, dl); SDValue StoreRet; std::vector Ops; @@ -906,7 +918,7 @@ Ops.push_back(DAG.getConstant(StoreOffset, MVT::i8)); Ops.push_back(InFlag); - StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, Tys, &Ops[0], Ops.size()); + StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size()); Chain = getChain(StoreRet); InFlag = getOutFlag(StoreRet); @@ -926,6 +938,7 @@ SDValue InFlag, SelectionDAG &DAG) { CallSDNode *TheCall = dyn_cast(Op); + DebugLoc dl = TheCall->getDebugLoc(); // Currently handling primitive types only. They will come in // i8 parts unsigned RetVals = TheCall->getNumRetVals(); @@ -941,14 +954,14 @@ // Legalize the address before use SDValue LdLo, LdHi; unsigned LdOffset; - LegalizeAddress(FrameAddress, DAG, LdLo, LdHi, LdOffset); + LegalizeAddress(FrameAddress, DAG, LdLo, LdHi, LdOffset, dl); SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag); SDValue LoadRet; for(unsigned i=0, Offset=0;i(Op); SDValue Chain = TheCall->getChain(); SDValue Callee = TheCall->getCallee(); + DebugLoc dl = TheCall->getDebugLoc(); unsigned i =0; if (Callee.getValueType() == MVT::i16 && Callee.getOpcode() == ISD::BUILD_PAIR) { @@ -1005,9 +1019,9 @@ SDVTList VTs = DAG.getVTList(&NodeTys[0], NodeTys.size()); SDValue NewCall = - DAG.getCall(TheCall->getCallingConv(), TheCall->isVarArg(), - TheCall->isTailCall(), TheCall->isInreg(), VTs, - &Ops[0], Ops.size()); + DAG.getCall(TheCall->getCallingConv(), dl, + TheCall->isVarArg(), TheCall->isTailCall(), + TheCall->isInreg(), VTs, &Ops[0], Ops.size()); return NewCall; } @@ -1060,7 +1074,7 @@ OperFlag = getOutFlag(CallArgs); SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); - SDValue PICCall = DAG.getNode(PIC16ISD::CALL, Tys, Chain, Callee, + SDValue PICCall = DAG.getNode(PIC16ISD::CALL, dl, Tys, Chain, Callee, OperFlag); Chain = getChain(PICCall); OperFlag = getOutFlag(PICCall); @@ -1107,14 +1121,15 @@ } SDValue PIC16TargetLowering:: LowerBinOp(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); // We should have handled larger operands in type legalizer itself. assert (Op.getValueType() == MVT::i8 && "illegal Op to lower"); unsigned MemOp = 1; if (NeedToConvertToMemOp(Op, MemOp)) { // Put one value on stack. - SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG); + SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl); - return DAG.getNode(Op.getOpcode(), MVT::i8, Op.getOperand(MemOp ^ 1), + return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1), NewVal); } else { @@ -1125,18 +1140,20 @@ SDValue PIC16TargetLowering:: LowerADD(SDValue Op, SelectionDAG &DAG) { // We should have handled larger operands in type legalizer itself. assert (Op.getValueType() == MVT::i8 && "illegal add to lower"); + DebugLoc dl = Op.getDebugLoc(); unsigned MemOp = 1; if (NeedToConvertToMemOp(Op, MemOp)) { // Put one value on stack. - SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG); + SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl); SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag); if (Op.getOpcode() == ISD::ADDE) - return DAG.getNode(Op.getOpcode(), Tys, Op.getOperand(MemOp ^ 1), NewVal, - Op.getOperand(2)); + return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1), + NewVal, Op.getOperand(2)); else - return DAG.getNode(Op.getOpcode(), Tys, Op.getOperand(MemOp ^ 1), NewVal); + return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1), + NewVal); } else if (Op.getOpcode() == ISD::ADD) { return Op; @@ -1147,6 +1164,7 @@ } SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); // We should have handled larger operands in type legalizer itself. assert (Op.getValueType() == MVT::i8 && "illegal sub to lower"); @@ -1156,14 +1174,14 @@ return SDValue(); // Put first operand on stack. - SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG); + SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG, dl); SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag); if (Op.getOpcode() == ISD::SUBE) - return DAG.getNode(Op.getOpcode(), Tys, NewVal, Op.getOperand(1), + return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1), Op.getOperand(2)); else - return DAG.getNode(Op.getOpcode(), Tys, NewVal, Op.getOperand(1)); + return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1)); } // LowerFORMAL_ARGUMENTS - In Lowering FORMAL ARGUMENTS - MERGE_VALUES nodes @@ -1175,15 +1193,16 @@ SelectionDAG &DAG) { SmallVector ArgValues; unsigned NumArgs = Op.getNumOperands() - 3; + DebugLoc dl = Op.getDebugLoc(); // Creating UNDEF nodes to meet the requirement of MERGE_VALUES node. for(unsigned i = 0 ; igetValueType(i)); + SDValue TempNode = DAG.getUNDEF(Op.getNode()->getValueType(i)); ArgValues.push_back(TempNode); } ArgValues.push_back(Op.getOperand(0)); - return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), &ArgValues[0], ArgValues.size()).getValue(Op.getResNo()); } @@ -1248,7 +1267,7 @@ // Returns appropriate CMP insn and corresponding condition code in PIC16CC SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS, unsigned CC, SDValue &PIC16CC, - SelectionDAG &DAG) { + SelectionDAG &DAG, DebugLoc dl) { PIC16CC::CondCodes CondCode = (PIC16CC::CondCodes) CC; // PIC16 sub is literal - W. So Swap the operands and condition if needed. @@ -1293,8 +1312,8 @@ // These are signed comparisons. SDValue Mask = DAG.getConstant(128, MVT::i8); if (isSignedComparison(CondCode)) { - LHS = DAG.getNode (ISD::XOR, MVT::i8, LHS, Mask); - RHS = DAG.getNode (ISD::XOR, MVT::i8, RHS, Mask); + LHS = DAG.getNode (ISD::XOR, dl, MVT::i8, LHS, Mask); + RHS = DAG.getNode (ISD::XOR, dl, MVT::i8, RHS, Mask); } SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag); @@ -1304,11 +1323,11 @@ // for subwf and literal for sublw) and it is used by this operation only. if ((LHS.getOpcode() == ISD::Constant || isDirectLoad(LHS)) && LHS.hasOneUse()) - return DAG.getNode(PIC16ISD::SUBCC, VTs, LHS, RHS); + return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS); // else convert the first operand to mem. - LHS = ConvertToMemOperand (LHS, DAG); - return DAG.getNode(PIC16ISD::SUBCC, VTs, LHS, RHS); + LHS = ConvertToMemOperand (LHS, DAG, dl); + return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS); } @@ -1319,6 +1338,7 @@ SDValue TrueVal = Op.getOperand(2); SDValue FalseVal = Op.getOperand(3); unsigned ORIGCC = ~0; + DebugLoc dl = Op.getDebugLoc(); // If this is a select_cc of a "setcc", and if the setcc got lowered into // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. @@ -1331,9 +1351,9 @@ if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC); SDValue PIC16CC; - SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG); + SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl); - return DAG.getNode (PIC16ISD::SELECT_ICC, TrueVal.getValueType(), TrueVal, + return DAG.getNode (PIC16ISD::SELECT_ICC, dl, TrueVal.getValueType(), TrueVal, FalseVal, PIC16CC, Cmp.getValue(1)); } @@ -1342,6 +1362,7 @@ MachineBasicBlock *BB) { const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); unsigned CC = (PIC16CC::CondCodes)MI->getOperand(3).getImm(); + DebugLoc dl = MI->getDebugLoc(); // To "insert" a SELECT_CC instruction, we actually have to insert the diamond // control-flow pattern. The incoming instruction knows the destination vreg @@ -1360,7 +1381,7 @@ MachineFunction *F = BB->getParent(); MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); - BuildMI(BB, TII.get(PIC16::pic16brcond)).addMBB(sinkMBB).addImm(CC); + BuildMI(BB, dl, TII.get(PIC16::pic16brcond)).addMBB(sinkMBB).addImm(CC); F->insert(It, copy0MBB); F->insert(It, sinkMBB); @@ -1383,7 +1404,7 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(BB, TII.get(PIC16::PHI), MI->getOperand(0).getReg()) + BuildMI(BB, dl, TII.get(PIC16::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); @@ -1399,6 +1420,7 @@ SDValue RHS = Op.getOperand(3); // RHS of the condition. SDValue Dest = Op.getOperand(4); // BB to jump to unsigned ORIGCC = ~0; + DebugLoc dl = Op.getDebugLoc(); // If this is a br_cc of a "setcc", and if the setcc got lowered into // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. @@ -1407,9 +1429,9 @@ // Get the Compare insn and condition code. SDValue PIC16CC; - SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG); + SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl); - return DAG.getNode(PIC16ISD::BRCOND, MVT::Other, Chain, Dest, PIC16CC, + return DAG.getNode(PIC16ISD::BRCOND, dl, MVT::Other, Chain, Dest, PIC16CC, Cmp.getValue(1)); } Modified: llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.h?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.h (original) +++ llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.h Sat Feb 14 07:20:23 2009 @@ -88,7 +88,7 @@ SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG); SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); SDValue getPIC16Cmp(SDValue LHS, SDValue RHS, unsigned OrigCC, SDValue &CC, - SelectionDAG &DAG); + SelectionDAG &DAG, DebugLoc dl); virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB); @@ -138,7 +138,7 @@ // addresses need Banksel and Indirect addresses need to be loaded to // FSR first. Handle address specific cases here. void LegalizeAddress(SDValue Ptr, SelectionDAG &DAG, SDValue &Chain, - SDValue &NewPtr, unsigned &Offset); + SDValue &NewPtr, unsigned &Offset, DebugLoc dl); // FrameIndex should be broken down into ExternalSymbol and FrameOffset. void LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG, SDValue &ES, @@ -146,7 +146,7 @@ // We can not have both operands of a binary operation in W. // This function is used to put one operand on stack and generate a load. - SDValue ConvertToMemOperand(SDValue Op, SelectionDAG &DAG); + SDValue ConvertToMemOperand(SDValue Op, SelectionDAG &DAG, DebugLoc dl); // This function checks if we need to put an operand of an operation on // stack and generate a load or not. Modified: llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16InstrInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16InstrInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16InstrInfo.cpp Sat Feb 14 07:20:23 2009 @@ -69,6 +69,8 @@ MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); const Function *Func = MBB.getParent()->getFunction(); const std::string FuncName = Func->getName(); @@ -80,7 +82,7 @@ if (RC == PIC16::GPRRegisterClass) { //MachineFunction &MF = *MBB.getParent(); //MachineRegisterInfo &RI = MF.getRegInfo(); - BuildMI(MBB, I, get(PIC16::movwf)) + BuildMI(MBB, I, DL, get(PIC16::movwf)) .addReg(SrcReg, false, false, isKill) .addImm(FI) .addExternalSymbol(tmpName) @@ -96,6 +98,8 @@ MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); const Function *Func = MBB.getParent()->getFunction(); const std::string FuncName = Func->getName(); @@ -107,7 +111,7 @@ if (RC == PIC16::GPRRegisterClass) { //MachineFunction &MF = *MBB.getParent(); //MachineRegisterInfo &RI = MF.getRegInfo(); - BuildMI(MBB, I, get(PIC16::movf), DestReg) + BuildMI(MBB, I, DL, get(PIC16::movf), DestReg) .addImm(FI) .addExternalSymbol(tmpName) .addImm(1); // Emit banksel for it. @@ -123,13 +127,16 @@ unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + if (DestRC == PIC16::FSR16RegisterClass) { - BuildMI(MBB, I, get(PIC16::copy_fsr), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(PIC16::copy_fsr), DestReg).addReg(SrcReg); return true; } if (DestRC == PIC16::GPRRegisterClass) { - BuildMI(MBB, I, get(PIC16::copy_w), DestReg).addReg(SrcReg); + BuildMI(MBB, I, DL, get(PIC16::copy_w), DestReg).addReg(SrcReg); return true; } Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCBranchSelector.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCBranchSelector.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCBranchSelector.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCBranchSelector.cpp Sat Feb 14 07:20:23 2009 @@ -145,13 +145,14 @@ unsigned CRReg = I->getOperand(1).getReg(); MachineInstr *OldBranch = I; + DebugLoc dl = OldBranch->getDebugLoc(); // Jump over the uncond branch inst (i.e. $PC+8) on opposite condition. - BuildMI(MBB, I, TII->get(PPC::BCC)) + BuildMI(MBB, I, dl, TII->get(PPC::BCC)) .addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2); // Uncond branch to the real destination. - I = BuildMI(MBB, I, TII->get(PPC::B)).addMBB(Dest); + I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest); // Remove the old branch from the function. OldBranch->eraseFromParent(); Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Sat Feb 14 07:20:23 2009 @@ -98,7 +98,7 @@ /// SelectCC - Select a comparison of the specified values with the /// specified condition code, returning the CR# of the expression. - SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC); + SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl); /// SelectAddrImm - Returns true if the address N can be represented by /// a base register plus a signed 16-bit displacement [r+imm]. @@ -243,15 +243,16 @@ const TargetInstrInfo &TII = *TM.getInstrInfo(); MachineBasicBlock &EntryBB = *Fn.begin(); + DebugLoc dl = DebugLoc::getUnknownLoc(); // Emit the following code into the entry block: // InVRSAVE = MFVRSAVE // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE // MTVRSAVE UpdatedVRSAVE MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point - BuildMI(EntryBB, IP, TII.get(PPC::MFVRSAVE), InVRSAVE); - BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE), + BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE); + BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE), UpdatedVRSAVE).addReg(InVRSAVE); - BuildMI(EntryBB, IP, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); + BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); // Find all return blocks, outputting a restore in each epilog. for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { @@ -265,7 +266,7 @@ IP = I2; // Emit: MTVRSAVE InVRSave - BuildMI(*BB, IP, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); + BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); } } } @@ -280,15 +281,16 @@ // Insert the set of GlobalBaseReg into the first MBB of the function MachineBasicBlock &FirstMBB = BB->getParent()->front(); MachineBasicBlock::iterator MBBI = FirstMBB.begin(); + DebugLoc dl = DebugLoc::getUnknownLoc(); if (PPCLowering.getPointerTy() == MVT::i32) { GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass); - BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR); - BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg); + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR), PPC::LR); + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); } else { GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass); - BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8); - BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg); + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8), PPC::LR8); + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg); } } return CurDAG->getRegister(GlobalBaseReg, @@ -418,6 +420,7 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { SDValue Op0 = N->getOperand(0); SDValue Op1 = N->getOperand(1); + DebugLoc dl = N->getDebugLoc(); APInt LKZ, LKO, RKZ, RKO; CurDAG->ComputeMaskedBits(Op0, APInt::getAllOnesValue(32), LKZ, LKO); @@ -479,7 +482,7 @@ SH &= 31; SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; - return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5); + return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5); } } return 0; @@ -488,7 +491,7 @@ /// SelectCC - Select a comparison of the specified values with the specified /// condition code, returning the CR# of the expression. SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, - ISD::CondCode CC) { + ISD::CondCode CC, DebugLoc dl) { // Always select the LHS. unsigned Opc; @@ -498,11 +501,11 @@ if (isInt32Immediate(RHS, Imm)) { // SETEQ/SETNE comparison with 16-bit immediate, fold it. if (isUInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0); // If this is a 16-bit signed immediate, fold it. if (isInt16((int)Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0); // For non-equality comparisons, the default code would materialize the @@ -514,21 +517,21 @@ // xoris r0,r3,0x1234 // cmplwi cr0,r0,0x5678 // beq cr0,L6 - SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, MVT::i32, LHS, + SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, dl, MVT::i32, LHS, getI32Imm(Imm >> 16)), 0); - return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, Xor, + return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, Xor, getI32Imm(Imm & 0xFFFF)), 0); } Opc = PPC::CMPLW; } else if (ISD::isUnsignedIntSetCC(CC)) { if (isInt32Immediate(RHS, Imm) && isUInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0); Opc = PPC::CMPLW; } else { short SImm; if (isIntS16Immediate(RHS, SImm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS, getI32Imm((int)SImm & 0xFFFF)), 0); Opc = PPC::CMPW; @@ -539,11 +542,11 @@ if (isInt64Immediate(RHS.getNode(), Imm)) { // SETEQ/SETNE comparison with 16-bit immediate, fold it. if (isUInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS, getI32Imm(Imm & 0xFFFF)), 0); // If this is a 16-bit signed immediate, fold it. if (isInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS, getI32Imm(Imm & 0xFFFF)), 0); // For non-equality comparisons, the default code would materialize the @@ -556,22 +559,22 @@ // cmpldi cr0,r0,0x5678 // beq cr0,L6 if (isUInt32(Imm)) { - SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, MVT::i64, LHS, + SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, dl, MVT::i64, LHS, getI64Imm(Imm >> 16)), 0); - return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, Xor, + return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, Xor, getI64Imm(Imm & 0xFFFF)), 0); } } Opc = PPC::CMPLD; } else if (ISD::isUnsignedIntSetCC(CC)) { if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS, getI64Imm(Imm & 0xFFFF)), 0); Opc = PPC::CMPLD; } else { short SImm; if (isIntS16Immediate(RHS, SImm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS, getI64Imm(SImm & 0xFFFF)), 0); Opc = PPC::CMPD; @@ -582,7 +585,7 @@ assert(LHS.getValueType() == MVT::f64 && "Unknown vt!"); Opc = PPC::FCMPUD; } - return SDValue(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0); + return SDValue(CurDAG->getTargetNode(Opc, dl, MVT::i32, LHS, RHS), 0); } static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { @@ -652,6 +655,7 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) { SDNode *N = Op.getNode(); + DebugLoc dl = N->getDebugLoc(); unsigned Imm; ISD::CondCode CC = cast(N->getOperand(2))->get(); if (isInt32Immediate(N->getOperand(1), Imm)) { @@ -663,13 +667,13 @@ switch (CC) { default: break; case ISD::SETEQ: { - Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0); + Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, dl, MVT::i32, Op), 0); SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } case ISD::SETNE: { SDValue AD = - SDValue(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, + SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, Op, getI32Imm(~0U)), 0); return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1)); @@ -680,8 +684,8 @@ } case ISD::SETGT: { SDValue T = - SDValue(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0); - T = SDValue(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0); + SDValue(CurDAG->getTargetNode(PPC::NEG, dl, MVT::i32, Op), 0); + T = SDValue(CurDAG->getTargetNode(PPC::ANDC, dl, MVT::i32, T, Op), 0); SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } @@ -691,30 +695,32 @@ switch (CC) { default: break; case ISD::SETEQ: - Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, + Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, Op, getI32Imm(1)), 0); return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, - SDValue(CurDAG->getTargetNode(PPC::LI, MVT::i32, - getI32Imm(0)), 0), - Op.getValue(1)); + SDValue(CurDAG->getTargetNode(PPC::LI, dl, + MVT::i32, + getI32Imm(0)), 0), + Op.getValue(1)); case ISD::SETNE: { - Op = SDValue(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0); - SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, + Op = SDValue(CurDAG->getTargetNode(PPC::NOR, dl, MVT::i32, Op, Op), 0); + SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, Op, getI32Imm(~0U)); return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), Op, SDValue(AD, 1)); } case ISD::SETLT: { - SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op, + SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, dl, MVT::i32, Op, getI32Imm(1)), 0); - SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, + SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, dl, MVT::i32, AD, Op), 0); SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } case ISD::SETGT: { SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; - Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0); + Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), + 0); return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1)); } @@ -725,21 +731,21 @@ bool Inv; int OtherCondIdx; unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx); - SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC); + SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); SDValue IntCR; // Force the ccreg into CR7. SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32); SDValue InFlag(0, 0); // Null incoming flag value. - CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg, + CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg, InFlag).getValue(1); if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1) - IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, + IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg, CCReg), 0); else - IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0); + IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, CCReg), 0); SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31), getI32Imm(31), getI32Imm(31) }; @@ -748,7 +754,7 @@ // Get the specified bit. SDValue Tmp = - SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0); + SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); if (Inv) { assert(OtherCondIdx == -1 && "Can't have split plus negation"); return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); @@ -760,7 +766,7 @@ // Get the other bit of the comparison. Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31); SDValue OtherCond = - SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0); + SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond); } @@ -770,6 +776,7 @@ // target-specific node if it hasn't already been changed. SDNode *PPCDAGToDAGISel::Select(SDValue Op) { SDNode *N = Op.getNode(); + DebugLoc dl = Op.getDebugLoc(); if (N->isMachineOpcode()) return NULL; // Already selected. @@ -812,17 +819,17 @@ // Simple value. if (isInt16(Imm)) { // Just the Lo bits. - Result = CurDAG->getTargetNode(PPC::LI8, MVT::i64, getI32Imm(Lo)); + Result = CurDAG->getTargetNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo)); } else if (Lo) { // Handle the Hi bits. unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8; - Result = CurDAG->getTargetNode(OpC, MVT::i64, getI32Imm(Hi)); + Result = CurDAG->getTargetNode(OpC, dl, MVT::i64, getI32Imm(Hi)); // And Lo bits. - Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64, + Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64, SDValue(Result, 0), getI32Imm(Lo)); } else { // Just the Hi bits. - Result = CurDAG->getTargetNode(PPC::LIS8, MVT::i64, getI32Imm(Hi)); + Result = CurDAG->getTargetNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi)); } // If no shift, we're done. @@ -830,18 +837,18 @@ // Shift for next step if the upper 32-bits were not zero. if (Imm) { - Result = CurDAG->getTargetNode(PPC::RLDICR, MVT::i64, + Result = CurDAG->getTargetNode(PPC::RLDICR, dl, MVT::i64, SDValue(Result, 0), getI32Imm(Shift), getI32Imm(63 - Shift)); } // Add in the last bits as required. if ((Hi = (Remainder >> 16) & 0xFFFF)) { - Result = CurDAG->getTargetNode(PPC::ORIS8, MVT::i64, + Result = CurDAG->getTargetNode(PPC::ORIS8, dl, MVT::i64, SDValue(Result, 0), getI32Imm(Hi)); } if ((Lo = Remainder & 0xFFFF)) { - Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64, + Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64, SDValue(Result, 0), getI32Imm(Lo)); } @@ -862,7 +869,7 @@ if (N->hasOneUse()) return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI, getSmallIPtrImm(0)); - return CurDAG->getTargetNode(Opc, Op.getValueType(), TFI, + return CurDAG->getTargetNode(Opc, dl, Op.getValueType(), TFI, getSmallIPtrImm(0)); } @@ -870,10 +877,10 @@ SDValue InFlag = N->getOperand(1); // Use MFOCRF if supported. if (PPCSubTarget.isGigaProcessor()) - return CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, + return CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32, N->getOperand(0), InFlag); else - return CurDAG->getTargetNode(PPC::MFCR, MVT::i32, InFlag); + return CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, InFlag); } case ISD::SDIV: { @@ -887,16 +894,16 @@ SDValue N0 = N->getOperand(0); if ((signed)Imm > 0 && isPowerOf2_32(Imm)) { SDNode *Op = - CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag, + CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag, N0, getI32Imm(Log2_32(Imm))); return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, SDValue(Op, 0), SDValue(Op, 1)); } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) { SDNode *Op = - CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag, + CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag, N0, getI32Imm(Log2_32(-Imm))); SDValue PT = - SDValue(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, + SDValue(CurDAG->getTargetNode(PPC::ADDZE, dl, MVT::i32, SDValue(Op, 0), SDValue(Op, 1)), 0); return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT); @@ -951,7 +958,7 @@ SDValue Base = LD->getBasePtr(); SDValue Ops[] = { Offset, Base, Chain }; // FIXME: PPC64 - return CurDAG->getTargetNode(Opcode, LD->getValueType(0), + return CurDAG->getTargetNode(Opcode, dl, LD->getValueType(0), PPCLowering.getPointerTy(), MVT::Other, Ops, 3); } else { @@ -995,7 +1002,7 @@ SDValue Ops[] = { N->getOperand(0).getOperand(0), N->getOperand(0).getOperand(1), getI32Imm(0), getI32Imm(MB),getI32Imm(ME) }; - return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5); + return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5); } } @@ -1045,14 +1052,14 @@ // FIXME: Implement this optzn for PPC64. N->getValueType(0) == MVT::i32) { SDNode *Tmp = - CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, + CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, N->getOperand(0), getI32Imm(~0U)); return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(Tmp, 0), N->getOperand(0), SDValue(Tmp, 1)); } - SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC); + SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); unsigned BROpc = getPredicateForSetCC(CC); unsigned SelectCCOp; @@ -1086,7 +1093,7 @@ } case ISD::BR_CC: { ISD::CondCode CC = cast(N->getOperand(1))->get(); - SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC); + SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode, N->getOperand(4), N->getOperand(0) }; return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4); @@ -1096,7 +1103,7 @@ SDValue Chain = N->getOperand(0); SDValue Target = N->getOperand(1); unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8; - Chain = SDValue(CurDAG->getTargetNode(Opc, MVT::Other, Target, + Chain = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Target, Chain), 0); return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain); } Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.cpp Sat Feb 14 07:20:23 2009 @@ -815,6 +815,8 @@ bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const { + // FIXME dl should come from parent load or store, not from address + DebugLoc dl = N.getDebugLoc(); // If this can be more profitably realized as r+r, fail. if (SelectAddressRegReg(N, Disp, Base, DAG)) return false; @@ -882,7 +884,7 @@ Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; - Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); + Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base), 0); return true; } } @@ -927,6 +929,8 @@ bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const { + // FIXME dl should come from the parent load or store, not the address + DebugLoc dl = N.getDebugLoc(); // If this can be more profitably realized as r+r, fail. if (SelectAddressRegReg(N, Disp, Base, DAG)) return false; @@ -990,10 +994,9 @@ // Otherwise, break this down into an LIS + disp. Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); - Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; - Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); + Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base),0); return true; } } @@ -1072,11 +1075,13 @@ Constant *C = CP->getConstVal(); SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); SDValue Zero = DAG.getConstant(0, PtrVT); + // FIXME there isn't really any debug info here + DebugLoc dl = Op.getDebugLoc(); const TargetMachine &TM = DAG.getTarget(); - SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); - SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); + SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero); + SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero); // If this is a non-darwin platform, we don't support non-static relo models // yet. @@ -1084,16 +1089,17 @@ !TM.getSubtarget().isDarwin()) { // Generate non-pic code that has direct accesses to the constant pool. // The address of the global is just (hi(&g)+lo(&g)). - return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); + return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); } if (TM.getRelocationModel() == Reloc::PIC_) { // With PIC, the first instruction is actually "GR+hi(&G)". - Hi = DAG.getNode(ISD::ADD, PtrVT, - DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); + Hi = DAG.getNode(ISD::ADD, dl, PtrVT, + DAG.getNode(PPCISD::GlobalBaseReg, + DebugLoc::getUnknownLoc(), PtrVT), Hi); } - Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); + Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); return Lo; } @@ -1102,11 +1108,13 @@ JumpTableSDNode *JT = cast(Op); SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); SDValue Zero = DAG.getConstant(0, PtrVT); + // FIXME there isn't really any debug loc here + DebugLoc dl = Op.getDebugLoc(); const TargetMachine &TM = DAG.getTarget(); - SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); - SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); + SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero); + SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, JTI, Zero); // If this is a non-darwin platform, we don't support non-static relo models // yet. @@ -1114,16 +1122,17 @@ !TM.getSubtarget().isDarwin()) { // Generate non-pic code that has direct accesses to the constant pool. // The address of the global is just (hi(&g)+lo(&g)). - return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); + return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); } if (TM.getRelocationModel() == Reloc::PIC_) { // With PIC, the first instruction is actually "GR+hi(&G)". - Hi = DAG.getNode(ISD::ADD, PtrVT, - DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); + Hi = DAG.getNode(ISD::ADD, dl, PtrVT, + DAG.getNode(PPCISD::GlobalBaseReg, + DebugLoc::getUnknownLoc(), PtrVT), Hi); } - Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); + Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); return Lo; } @@ -1140,11 +1149,13 @@ GlobalValue *GV = GSDN->getGlobal(); SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); SDValue Zero = DAG.getConstant(0, PtrVT); + // FIXME there isn't really any debug info here + DebugLoc dl = GSDN->getDebugLoc(); const TargetMachine &TM = DAG.getTarget(); - SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); - SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); + SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero); + SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero); // If this is a non-darwin platform, we don't support non-static relo models // yet. @@ -1152,27 +1163,29 @@ !TM.getSubtarget().isDarwin()) { // Generate non-pic code that has direct accesses to globals. // The address of the global is just (hi(&g)+lo(&g)). - return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); + return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); } if (TM.getRelocationModel() == Reloc::PIC_) { // With PIC, the first instruction is actually "GR+hi(&G)". - Hi = DAG.getNode(ISD::ADD, PtrVT, - DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); + Hi = DAG.getNode(ISD::ADD, dl, PtrVT, + DAG.getNode(PPCISD::GlobalBaseReg, + DebugLoc::getUnknownLoc(), PtrVT), Hi); } - Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); + Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); if (!TM.getSubtarget().hasLazyResolverStub(GV)) return Lo; // If the global is weak or external, we have to go through the lazy // resolution stub. - return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); + return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0); } SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { ISD::CondCode CC = cast(Op.getOperand(2))->get(); + DebugLoc dl = Op.getDebugLoc(); // If we're comparing for equality to zero, expose the fact that this is // implented as a ctlz/srl pair on ppc, so that the dag combiner can @@ -1183,13 +1196,13 @@ SDValue Zext = Op.getOperand(0); if (VT.bitsLT(MVT::i32)) { VT = MVT::i32; - Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); + Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); } unsigned Log2b = Log2_32(VT.getSizeInBits()); - SDValue Clz = DAG.getNode(ISD::CTLZ, VT, Zext); - SDValue Scc = DAG.getNode(ISD::SRL, VT, Clz, + SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); + SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, DAG.getConstant(Log2b, MVT::i32)); - return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); + return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); } // Leave comparisons against 0 and -1 alone for now, since they're usually // optimized. FIXME: revisit this when we can custom lower all setcc @@ -1206,9 +1219,9 @@ MVT LHSVT = Op.getOperand(0).getValueType(); if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { MVT VT = Op.getValueType(); - SDValue Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), + SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), Op.getOperand(1)); - return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); + return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); } return SDValue(); } @@ -1229,7 +1242,7 @@ SDValue Trmp = Op.getOperand(1); // trampoline SDValue FPtr = Op.getOperand(2); // nested function SDValue Nest = Op.getOperand(3); // 'nest' parameter value - DebugLoc dl = Op.getNode()->getDebugLoc(); + DebugLoc dl = Op.getDebugLoc(); MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); bool isPPC64 = (PtrVT == MVT::i64); @@ -1260,7 +1273,7 @@ SDValue Ops[] = { CallResult.first, CallResult.second }; - return DAG.getMergeValues(Ops, 2); + return DAG.getMergeValues(Ops, 2, dl); } SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, @@ -1269,6 +1282,7 @@ unsigned VarArgsNumGPR, unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget) { + DebugLoc dl = Op.getDebugLoc(); if (Subtarget.isMachoABI()) { // vastart just stores the address of the VarArgsFrameIndex slot into the @@ -1276,7 +1290,7 @@ MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); const Value *SV = cast(Op.getOperand(2))->getValue(); - return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); + return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); } // For ELF 32 ABI we follow the layout of the va_list struct. @@ -1325,26 +1339,26 @@ const Value *SV = cast(Op.getOperand(2))->getValue(); // Store first byte : number of int regs - SDValue firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, + SDValue firstStore = DAG.getStore(Op.getOperand(0), dl, ArgGPR, Op.getOperand(1), SV, 0); uint64_t nextOffset = FPROffset; - SDValue nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), + SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), ConstFPROffset); // Store second byte : number of float regs SDValue secondStore = - DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset); + DAG.getStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset); nextOffset += StackOffset; - nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset); + nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); // Store second word : arguments given on stack SDValue thirdStore = - DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset); + DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset); nextOffset += FrameOffset; - nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset); + nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset); // Store third word : arguments given in registers - return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset); + return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset); } @@ -1398,6 +1412,7 @@ SmallVector ArgValues; SDValue Root = Op.getOperand(0); bool isVarArg = cast(Op.getOperand(2))->getZExtValue() != 0; + DebugLoc dl = Op.getDebugLoc(); MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); bool isPPC64 = PtrVT == MVT::i64; @@ -1550,8 +1565,8 @@ if (GPR_idx != Num_GPR_Regs) { unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); RegInfo.addLiveIn(GPR[GPR_idx], VReg); - SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT); - SDValue Store = DAG.getTruncStore(Val.getValue(1), Val, FIN, + SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT); + SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 ); MemOps.push_back(Store); ++GPR_idx; @@ -1570,8 +1585,8 @@ RegInfo.addLiveIn(GPR[GPR_idx], VReg); int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset); SDValue FIN = DAG.getFrameIndex(FI, PtrVT); - SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT); - SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); + SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT); + SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); MemOps.push_back(Store); ++GPR_idx; if (isMachoABI) ArgOffset += PtrByteSize; @@ -1593,7 +1608,7 @@ if (GPR_idx != Num_GPR_Regs) { unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); RegInfo.addLiveIn(GPR[GPR_idx], VReg); - ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); + ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); ++GPR_idx; } else { needsLoad = true; @@ -1611,19 +1626,19 @@ if (GPR_idx != Num_GPR_Regs) { unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); RegInfo.addLiveIn(GPR[GPR_idx], VReg); - ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); + ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64); if (ObjectVT == MVT::i32) { // PPC64 passes i8, i16, and i32 values in i64 registers. Promote // value to MVT::i64 and then truncate to the correct register size. if (Flags.isSExt()) - ArgVal = DAG.getNode(ISD::AssertSext, MVT::i64, ArgVal, + ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, DAG.getValueType(ObjectVT)); else if (Flags.isZExt()) - ArgVal = DAG.getNode(ISD::AssertZext, MVT::i64, ArgVal, + ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, DAG.getValueType(ObjectVT)); - ArgVal = DAG.getNode(ISD::TRUNCATE, MVT::i32, ArgVal); + ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); } ++GPR_idx; @@ -1651,7 +1666,7 @@ else VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); RegInfo.addLiveIn(FPR[FPR_idx], VReg); - ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); + ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT); ++FPR_idx; } else { needsLoad = true; @@ -1672,7 +1687,7 @@ if (VR_idx != Num_VR_Regs) { unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass); RegInfo.addLiveIn(VR[VR_idx], VReg); - ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); + ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT); if (isVarArg) { while ((ArgOffset % 16) != 0) { ArgOffset += PtrByteSize; @@ -1706,7 +1721,7 @@ CurArgOffset + (ArgSize - ObjSize), isImmutable); SDValue FIN = DAG.getFrameIndex(FI, PtrVT); - ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); + ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0); } ArgValues.push_back(ArgVal); @@ -1762,11 +1777,11 @@ if (isELF32_ABI) { for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) { SDValue Val = DAG.getRegister(GPR[GPR_idx], PtrVT); - SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0); + SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by four for the next argument to store SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); - FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); + FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); } } @@ -1781,12 +1796,12 @@ VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); RegInfo.addLiveIn(GPR[GPR_idx], VReg); - SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT); - SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); + SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT); + SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by four for the next argument to store SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); - FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); + FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); } // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex @@ -1794,12 +1809,12 @@ if (isELF32_ABI) { for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) { SDValue Val = DAG.getRegister(FPR[FPR_idx], MVT::f64); - SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0); + SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by eight for the next argument to store SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, PtrVT); - FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); + FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); } for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) { @@ -1807,24 +1822,25 @@ VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); RegInfo.addLiveIn(FPR[FPR_idx], VReg); - SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::f64); - SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); + SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::f64); + SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by eight for the next argument to store SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, PtrVT); - FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); + FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); } } } if (!MemOps.empty()) - Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); + Root = DAG.getNode(ISD::TokenFactor, dl, + MVT::Other, &MemOps[0], MemOps.size()); ArgValues.push_back(Root); // Return the new list of results. - return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), &ArgValues[0], ArgValues.size()); } @@ -1984,13 +2000,14 @@ StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, SDValue Chain, const SmallVector &TailCallArgs, - SmallVector &MemOpChains) { + SmallVector &MemOpChains, + DebugLoc dl) { for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { SDValue Arg = TailCallArgs[i].Arg; SDValue FIN = TailCallArgs[i].FrameIdxOp; int FI = TailCallArgs[i].FrameIdx; // Store relative to framepointer. - MemOpChains.push_back(DAG.getStore(Chain, Arg, FIN, + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN, PseudoSourceValue::getFixedStack(FI), 0)); } @@ -2005,7 +2022,8 @@ SDValue OldFP, int SPDiff, bool isPPC64, - bool isMachoABI) { + bool isMachoABI, + DebugLoc dl) { if (SPDiff) { // Calculate the new stack slot for the return address. int SlotSize = isPPC64 ? 8 : 4; @@ -2019,10 +2037,10 @@ MVT VT = isPPC64 ? MVT::i64 : MVT::i32; SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); - Chain = DAG.getStore(Chain, OldRetAddr, NewRetAddrFrIdx, + Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, PseudoSourceValue::getFixedStack(NewRetAddr), 0); SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); - Chain = DAG.getStore(Chain, OldFP, NewFramePtrIdx, + Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, PseudoSourceValue::getFixedStack(NewFPIdx), 0); } return Chain; @@ -2050,18 +2068,19 @@ /// stack slot. Returns the chain as result and the loaded frame pointers in /// LROpOut/FPOpout. Used when tail calling. SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, - int SPDiff, - SDValue Chain, - SDValue &LROpOut, - SDValue &FPOpOut) { + int SPDiff, + SDValue Chain, + SDValue &LROpOut, + SDValue &FPOpOut, + DebugLoc dl) { if (SPDiff) { // Load the LR and FP stack slot for later adjusting. MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; LROpOut = getReturnAddrFrameIndex(DAG); - LROpOut = DAG.getLoad(VT, Chain, LROpOut, NULL, 0); + LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0); Chain = SDValue(LROpOut.getNode(), 1); FPOpOut = getFramePointerFrameIndex(DAG); - FPOpOut = DAG.getLoad(VT, Chain, FPOpOut, NULL, 0); + FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0); Chain = SDValue(FPOpOut.getNode(), 1); } return Chain; @@ -2076,10 +2095,10 @@ static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, - unsigned Size) { + unsigned Size, DebugLoc dl) { SDValue SizeNode = DAG.getConstant(Size, MVT::i32); - return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), false, - NULL, 0, NULL, 0); + return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), + false, NULL, 0, NULL, 0); } /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of @@ -2089,7 +2108,8 @@ SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVector &MemOpChains, - SmallVector& TailCallArguments) { + SmallVector& TailCallArguments, + DebugLoc dl) { MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); if (!isTailCall) { if (isVector) { @@ -2098,10 +2118,10 @@ StackPtr = DAG.getRegister(PPC::X1, MVT::i64); else StackPtr = DAG.getRegister(PPC::R1, MVT::i32); - PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, + PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, DAG.getConstant(ArgOffset, PtrVT)); } - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); // Calculate and remember argument location. } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, TailCallArguments); @@ -2118,6 +2138,7 @@ && CC == CallingConv::Fast && PerformTailCallOpt; SDValue Callee = TheCall->getCallee(); unsigned NumOps = TheCall->getNumArgs(); + DebugLoc dl = TheCall->getDebugLoc(); bool isMachoABI = Subtarget.isMachoABI(); bool isELF32_ABI = Subtarget.isELF32_ABI(); @@ -2161,7 +2182,7 @@ // Load the return address and frame pointer so it can be move somewhere else // later. SDValue LROp, FPOp; - Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp); + Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl); // Set up a copy of the stack pointer for use loading and storing any // arguments that may not fit in the registers available for argument @@ -2221,13 +2242,13 @@ else PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); - PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); + PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); // On PPC64, promote integers to 64-bit values. if (isPPC64 && Arg.getValueType() == MVT::i32) { // FIXME: Should this use ANY_EXTEND if neither sext nor zext? unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; - Arg = DAG.getNode(ExtOp, MVT::i64, Arg); + Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); } // FIXME Elf untested, what are alignment rules? @@ -2240,7 +2261,7 @@ // Everything else is passed left-justified. MVT VT = (Size==1) ? MVT::i8 : MVT::i16; if (GPR_idx != NumGPRs) { - SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg, + SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, NULL, 0, VT); MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); @@ -2248,10 +2269,10 @@ ArgOffset += PtrByteSize; } else { SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType()); - SDValue AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const); + SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, CallSeqStart.getNode()->getOperand(0), - Flags, DAG, Size); + Flags, DAG, Size, dl); // This must go outside the CALLSEQ_START..END. SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, CallSeqStart.getNode()->getOperand(1)); @@ -2267,7 +2288,7 @@ // registers. (This is not what the doc says.) SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, CallSeqStart.getNode()->getOperand(0), - Flags, DAG, Size); + Flags, DAG, Size, dl); // This must go outside the CALLSEQ_START..END. SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, CallSeqStart.getNode()->getOperand(1)); @@ -2276,9 +2297,9 @@ // And copy the pieces of it that fit into registers. for (unsigned j=0; j CallSeqOps; - SDVTList CallSeqNodeTys = DAG.getVTList(MVT::Other, MVT::Flag); - CallSeqOps.push_back(Chain); - CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes, true)); - CallSeqOps.push_back(DAG.getIntPtrConstant(0, true)); - if (InFlag.getNode()) - CallSeqOps.push_back(InFlag); - Chain = DAG.getNode(ISD::CALLSEQ_END, CallSeqNodeTys, &CallSeqOps[0], - CallSeqOps.size()); + Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), + DAG.getIntPtrConstant(0, true), InFlag); InFlag = Chain.getValue(1); } @@ -2518,14 +2532,14 @@ // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair // to do the call, we can't use PPCISD::CALL. SDValue MTCTROps[] = {Chain, Callee, InFlag}; - Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, + Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps, 2 + (InFlag.getNode() != 0)); InFlag = Chain.getValue(1); // Copy the callee address into R12/X12 on darwin. if (isMachoABI) { unsigned Reg = Callee.getValueType() == MVT::i32 ? PPC::R12 : PPC::X12; - Chain = DAG.getCopyToReg(Chain, Reg, Callee, InFlag); + Chain = DAG.getCopyToReg(Chain, dl, Reg, Callee, InFlag); InFlag = Chain.getValue(1); } @@ -2568,12 +2582,12 @@ if (isTailCall) { assert(InFlag.getNode() && "Flag must be set. Depend on flag being set in LowerRET"); - Chain = DAG.getNode(PPCISD::TAILCALL, + Chain = DAG.getNode(PPCISD::TAILCALL, dl, TheCall->getVTList(), &Ops[0], Ops.size()); return SDValue(Chain.getNode(), Op.getResNo()); } - Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); + Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); InFlag = Chain.getValue(1); Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), @@ -2593,7 +2607,8 @@ CCValAssign &VA = RVLocs[i]; MVT VT = VA.getValVT(); assert(VA.isRegLoc() && "Can only return in registers!"); - Chain = DAG.getCopyFromReg(Chain, VA.getLocReg(), VT, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, + VA.getLocReg(), VT, InFlag).getValue(1); ResultVals.push_back(Chain.getValue(0)); InFlag = Chain.getValue(2); } @@ -2604,7 +2619,7 @@ // Otherwise, merge everything together with a MERGE_VALUES node. ResultVals.push_back(Chain); - SDValue Res = DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), + SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(), &ResultVals[0], ResultVals.size()); return Res.getValue(Op.getResNo()); } @@ -2614,6 +2629,7 @@ SmallVector RVLocs; unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); + DebugLoc dl = Op.getDebugLoc(); CCState CCInfo(CC, isVarArg, TM, RVLocs); CCInfo.AnalyzeReturn(Op.getNode(), RetCC_PPC); @@ -2651,7 +2667,7 @@ for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) { Operands.push_back(Chain.getOperand(i)); } - return DAG.getNode(PPCISD::TC_RETURN, MVT::Other, &Operands[0], + return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Operands[0], Operands.size()); } @@ -2661,19 +2677,21 @@ for (unsigned i = 0; i != RVLocs.size(); ++i) { CCValAssign &VA = RVLocs[i]; assert(VA.isRegLoc() && "Can only return in registers!"); - Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); + Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), + Op.getOperand(i*2+1), Flag); Flag = Chain.getValue(1); } if (Flag.getNode()) - return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag); + return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag); else - return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain); + return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain); } SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) { // When we pop the dynamic allocation we need to restore the SP link. + DebugLoc dl = Op.getDebugLoc(); // Get the corect type for pointers. MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); @@ -2688,13 +2706,13 @@ SDValue SaveSP = Op.getOperand(1); // Load the old link SP. - SDValue LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0); + SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0); // Restore the stack pointer. - Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP); + Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); // Store the old link SP. - return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0); + return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0); } @@ -2754,18 +2772,19 @@ // Get the inputs. SDValue Chain = Op.getOperand(0); SDValue Size = Op.getOperand(1); - + DebugLoc dl = Op.getDebugLoc(); + // Get the corect type for pointers. MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Negate the size. - SDValue NegSize = DAG.getNode(ISD::SUB, PtrVT, + SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, DAG.getConstant(0, PtrVT), Size); // Construct a node for the frame pointer save index. SDValue FPSIdx = getFramePointerFrameIndex(DAG); // Build a DYNALLOC node. SDValue Ops[3] = { Chain, NegSize, FPSIdx }; SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); - return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3); + return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3); } /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when @@ -2785,6 +2804,7 @@ MVT CmpVT = Op.getOperand(0).getValueType(); SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); + DebugLoc dl = Op.getDebugLoc(); // If the RHS of the comparison is a 0.0, we don't need to do the // subtraction at all. @@ -2797,17 +2817,17 @@ case ISD::SETOGE: case ISD::SETGE: if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits - LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); - return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); + LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); + return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); case ISD::SETUGT: case ISD::SETGT: std::swap(TV, FV); // fsel is natively setge, swap operands for setlt case ISD::SETOLE: case ISD::SETLE: if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits - LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); - return DAG.getNode(PPCISD::FSEL, ResVT, - DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); + LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); + return DAG.getNode(PPCISD::FSEL, dl, ResVT, + DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); } SDValue Cmp; @@ -2815,47 +2835,48 @@ default: break; // SETUO etc aren't handled by fsel. case ISD::SETULT: case ISD::SETLT: - Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); + Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits - Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); - return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); + Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); + return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); case ISD::SETOGE: case ISD::SETGE: - Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); + Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits - Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); - return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); + Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); + return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); case ISD::SETUGT: case ISD::SETGT: - Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); + Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits - Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); - return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); + Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); + return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); case ISD::SETOLE: case ISD::SETLE: - Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); + Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits - Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); - return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); + Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); + return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); } return SDValue(); } // FIXME: Split this code up when LegalizeDAGTypes lands. -SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { +SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, + DebugLoc dl) { assert(Op.getOperand(0).getValueType().isFloatingPoint()); SDValue Src = Op.getOperand(0); if (Src.getValueType() == MVT::f32) - Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); + Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); SDValue Tmp; switch (Op.getValueType().getSimpleVT()) { default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); case MVT::i32: - Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); + Tmp = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Src); break; case MVT::i64: - Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); + Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src); break; } @@ -2863,26 +2884,29 @@ SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); // Emit a store to the stack slot. - SDValue Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0); + SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0); // Result is a load from the stack slot. If loading 4 bytes, make sure to // add in a bias. if (Op.getValueType() == MVT::i32) - FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, + FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, DAG.getConstant(4, FIPtr.getValueType())); - return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0); + return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0); } SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); // Don't handle ppc_fp128 here; let it be lowered to a libcall. if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) return SDValue(); if (Op.getOperand(0).getValueType() == MVT::i64) { - SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); - SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); + SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl, + MVT::f64, Op.getOperand(0)); + SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); if (Op.getValueType() == MVT::f32) - FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); + FP = DAG.getNode(ISD::FP_ROUND, dl, + MVT::f32, FP, DAG.getIntPtrConstant(0)); return FP; } @@ -2897,26 +2921,27 @@ MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); - SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, + SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32, Op.getOperand(0)); // STD the extended value into the stack slot. MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx), MachineMemOperand::MOStore, 0, 8, 8); - SDValue Store = DAG.getNode(PPCISD::STD_32, MVT::Other, + SDValue Store = DAG.getNode(PPCISD::STD_32, dl, MVT::Other, DAG.getEntryNode(), Ext64, FIdx, DAG.getMemOperand(MO)); // Load the value as a double. - SDValue Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); + SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0); // FCFID it and return it. - SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); + SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); if (Op.getValueType() == MVT::f32) - FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); + FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); return FP; } SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); /* The rounding mode is in bits 30:31 of FPSR, and has the following settings: @@ -2945,41 +2970,42 @@ // Save FP Control Word to register NodeTys.push_back(MVT::f64); // return register NodeTys.push_back(MVT::Flag); // unused in this context - SDValue Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); + SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); // Save FP register to stack slot int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); - SDValue Store = DAG.getStore(DAG.getEntryNode(), Chain, + SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, StackSlot, NULL, 0); // Load FP Control Word from low 32 bits of stack slot. SDValue Four = DAG.getConstant(4, PtrVT); - SDValue Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four); - SDValue CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0); + SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); + SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0); // Transform as necessary SDValue CWD1 = - DAG.getNode(ISD::AND, MVT::i32, + DAG.getNode(ISD::AND, dl, MVT::i32, CWD, DAG.getConstant(3, MVT::i32)); SDValue CWD2 = - DAG.getNode(ISD::SRL, MVT::i32, - DAG.getNode(ISD::AND, MVT::i32, - DAG.getNode(ISD::XOR, MVT::i32, + DAG.getNode(ISD::SRL, dl, MVT::i32, + DAG.getNode(ISD::AND, dl, MVT::i32, + DAG.getNode(ISD::XOR, dl, MVT::i32, CWD, DAG.getConstant(3, MVT::i32)), DAG.getConstant(3, MVT::i32)), DAG.getConstant(1, MVT::i32)); SDValue RetVal = - DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2); + DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); return DAG.getNode((VT.getSizeInBits() < 16 ? - ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); + ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); } SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); unsigned BitWidth = VT.getSizeInBits(); + DebugLoc dl = Op.getDebugLoc(); assert(Op.getNumOperands() == 3 && VT == Op.getOperand(1).getValueType() && "Unexpected SHL!"); @@ -2991,22 +3017,23 @@ SDValue Amt = Op.getOperand(2); MVT AmtVT = Amt.getValueType(); - SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT, + SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, DAG.getConstant(BitWidth, AmtVT), Amt); - SDValue Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt); - SDValue Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1); - SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); - SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, + SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); + SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); + SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); + SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, DAG.getConstant(-BitWidth, AmtVT)); - SDValue Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5); - SDValue OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); - SDValue OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt); + SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); + SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); + SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); SDValue OutOps[] = { OutLo, OutHi }; - return DAG.getMergeValues(OutOps, 2); + return DAG.getMergeValues(OutOps, 2, dl); } SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); + DebugLoc dl = Op.getDebugLoc(); unsigned BitWidth = VT.getSizeInBits(); assert(Op.getNumOperands() == 3 && VT == Op.getOperand(1).getValueType() && @@ -3019,21 +3046,22 @@ SDValue Amt = Op.getOperand(2); MVT AmtVT = Amt.getValueType(); - SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT, + SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, DAG.getConstant(BitWidth, AmtVT), Amt); - SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt); - SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1); - SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); - SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, + SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); + SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); + SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); + SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, DAG.getConstant(-BitWidth, AmtVT)); - SDValue Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5); - SDValue OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); - SDValue OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt); + SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); + SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); + SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); SDValue OutOps[] = { OutLo, OutHi }; - return DAG.getMergeValues(OutOps, 2); + return DAG.getMergeValues(OutOps, 2, dl); } SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); MVT VT = Op.getValueType(); unsigned BitWidth = VT.getSizeInBits(); assert(Op.getNumOperands() == 3 && @@ -3046,19 +3074,19 @@ SDValue Amt = Op.getOperand(2); MVT AmtVT = Amt.getValueType(); - SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT, + SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, DAG.getConstant(BitWidth, AmtVT), Amt); - SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt); - SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1); - SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); - SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, + SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); + SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); + SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); + SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, DAG.getConstant(-BitWidth, AmtVT)); - SDValue Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5); - SDValue OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt); - SDValue OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT), + SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); + SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); + SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), Tmp4, Tmp6, ISD::SETLE); SDValue OutOps[] = { OutLo, OutHi }; - return DAG.getMergeValues(OutOps, 2); + return DAG.getMergeValues(OutOps, 2, dl); } //===----------------------------------------------------------------------===// @@ -3162,7 +3190,7 @@ /// BuildSplatI - Build a canonical splati of Val with an element size of /// SplatSize. Cast the result to VT. static SDValue BuildSplatI(int Val, unsigned SplatSize, MVT VT, - SelectionDAG &DAG) { + SelectionDAG &DAG, DebugLoc dl) { assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); static const MVT VTys[] = { // canonical VT to use for each size. @@ -3181,28 +3209,28 @@ SDValue Elt = DAG.getConstant(Val, CanonicalVT.getVectorElementType()); SmallVector Ops; Ops.assign(CanonicalVT.getVectorNumElements(), Elt); - SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, + SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0], Ops.size()); - return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res); + return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res); } /// BuildIntrinsicOp - Return a binary operator intrinsic node with the /// specified intrinsic ID. static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, - SelectionDAG &DAG, - MVT DestVT = MVT::Other) { + SelectionDAG &DAG, DebugLoc dl, + MVT DestVT = MVT::Other) { if (DestVT == MVT::Other) DestVT = LHS.getValueType(); - return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, + return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, DAG.getConstant(IID, MVT::i32), LHS, RHS); } /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the /// specified intrinsic ID. static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, - SDValue Op2, SelectionDAG &DAG, - MVT DestVT = MVT::Other) { + SDValue Op2, SelectionDAG &DAG, + DebugLoc dl, MVT DestVT = MVT::Other) { if (DestVT == MVT::Other) DestVT = Op0.getValueType(); - return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, + return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); } @@ -3210,17 +3238,17 @@ /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified /// amount. The result has the specified value type. static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, - MVT VT, SelectionDAG &DAG) { + MVT VT, SelectionDAG &DAG, DebugLoc dl) { // Force LHS/RHS to be the right type. - LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); - RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); + LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS); + RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS); SDValue Ops[16]; for (unsigned i = 0; i != 16; ++i) Ops[i] = DAG.getConstant(i+Amt, MVT::i8); - SDValue T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, - DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16)); - return DAG.getNode(ISD::BIT_CONVERT, VT, T); + SDValue T = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v16i8, LHS, RHS, + DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops,16)); + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T); } // If this is a case we can't handle, return null and let the default @@ -3236,6 +3264,7 @@ // zero. uint64_t VectorBits[2]; uint64_t UndefBits[2]; + DebugLoc dl = Op.getDebugLoc(); if (GetConstantBuildVectorBits(Op.getNode(), VectorBits, UndefBits)) return SDValue(); // Not a constant vector. @@ -3254,8 +3283,8 @@ // Canonicalize all zero vectors to be v4i32. if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { SDValue Z = DAG.getConstant(0, MVT::i32); - Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); - Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); + Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); + Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z); } return Op; } @@ -3263,7 +3292,7 @@ // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); if (SextVal >= -16 && SextVal <= 15) - return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG); + return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl); // Two instruction sequences. @@ -3271,9 +3300,9 @@ // If this value is in the range [-32,30] and is even, use: // tmp = VSPLTI[bhw], result = add tmp, tmp if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { - SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG); - Res = DAG.getNode(ISD::ADD, Res.getValueType(), Res, Res); - return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); + SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl); + Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res); + return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); } // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is @@ -3281,15 +3310,15 @@ // for fneg/fabs. if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { // Make -1 and vspltisw -1: - SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); + SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); // Make the VSLW intrinsic, computing 0x8000_0000. SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, - OnesV, DAG); + OnesV, DAG, dl); // xor by OnesV to invert it. - Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); - return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); + Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); + return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); } // Check to see if this is a wide variety of vsplti*, binop self cases. @@ -3310,63 +3339,63 @@ // vsplti + shl self. if (SextVal == (i << (int)TypeShiftAmt)) { - SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); + SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); static const unsigned IIDs[] = { // Intrinsic to use for each size. Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, Intrinsic::ppc_altivec_vslw }; - Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); - return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); + Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); + return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); } // vsplti + srl self. if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { - SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); + SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); static const unsigned IIDs[] = { // Intrinsic to use for each size. Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, Intrinsic::ppc_altivec_vsrw }; - Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); - return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); + Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); + return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); } // vsplti + sra self. if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { - SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); + SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); static const unsigned IIDs[] = { // Intrinsic to use for each size. Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, Intrinsic::ppc_altivec_vsraw }; - Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); - return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); + Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); + return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); } // vsplti + rol self. if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { - SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); + SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); static const unsigned IIDs[] = { // Intrinsic to use for each size. Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, Intrinsic::ppc_altivec_vrlw }; - Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); - return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); + Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); + return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); } // t = vsplti c, result = vsldoi t, t, 1 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { - SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); - return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG); + SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); + return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); } // t = vsplti c, result = vsldoi t, t, 2 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { - SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); - return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG); + SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); + return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); } // t = vsplti c, result = vsldoi t, t, 3 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { - SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); - return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG); + SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); + return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); } } @@ -3374,17 +3403,17 @@ // Odd, in range [17,31]: (vsplti C)-(vsplti -16). if (SextVal >= 0 && SextVal <= 31) { - SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG); - SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); - LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS); - return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); + SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl); + SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); + LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS); + return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS); } // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). if (SextVal >= -31 && SextVal <= 0) { - SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG); - SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); - LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS); - return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); + SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl); + SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); + LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS); + return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS); } } @@ -3394,7 +3423,8 @@ /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit /// the specified operations to build the shuffle. static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, - SDValue RHS, SelectionDAG &DAG) { + SDValue RHS, SelectionDAG &DAG, + DebugLoc dl) { unsigned OpNum = (PFEntry >> 26) & 0x0F; unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); @@ -3419,8 +3449,8 @@ } SDValue OpLHS, OpRHS; - OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG); - OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG); + OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); + OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); unsigned ShufIdxs[16]; switch (OpNum) { @@ -3454,18 +3484,19 @@ ShufIdxs[i] = (i&3)+12; break; case OP_VSLDOI4: - return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG); + return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl); case OP_VSLDOI8: - return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG); + return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl); case OP_VSLDOI12: - return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); + return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl); } SDValue Ops[16]; for (unsigned i = 0; i != 16; ++i) Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i8); - return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS, - DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); + return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, OpLHS.getValueType(), + OpLHS, OpRHS, + DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops, 16)); } /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this @@ -3474,6 +3505,7 @@ /// lowered into a vperm. SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); SDValue V1 = Op.getOperand(0); SDValue V2 = Op.getOperand(1); SDValue PermMask = Op.getOperand(2); @@ -3562,7 +3594,7 @@ // available, if this block is within a loop, we should avoid using vperm // for 3-operation perms and use a constant pool load instead. if (Cost < 3) - return GeneratePerfectShuffle(PFEntry, V1, V2, DAG); + return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); } // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant @@ -3587,9 +3619,9 @@ MVT::i8)); } - SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, + SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, &ResultMask[0], ResultMask.size()); - return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); + return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); } /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an @@ -3642,6 +3674,7 @@ SelectionDAG &DAG) { // If this is a lowered altivec predicate compare, CompareOpc is set to the // opcode number of the comparison. + DebugLoc dl = Op.getDebugLoc(); int CompareOpc; bool isDot; if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) @@ -3649,10 +3682,10 @@ // If this is a non-dot comparison, make the VCMP node and we are done. if (!isDot) { - SDValue Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), + SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), Op.getOperand(1), Op.getOperand(2), DAG.getConstant(CompareOpc, MVT::i32)); - return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); + return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp); } // Create the PPCISD altivec 'dot' comparison node. @@ -3664,11 +3697,11 @@ std::vector VTs; VTs.push_back(Op.getOperand(2).getValueType()); VTs.push_back(MVT::Flag); - SDValue CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); + SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); // Now that we have the comparison, emit a copy from the CR to a GPR. // This is flagged to the above dot comparison. - SDValue Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, + SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32, DAG.getRegister(PPC::CR6, MVT::i32), CompNode.getValue(1)); @@ -3692,21 +3725,22 @@ } // Shift the bit into the low position. - Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, + Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, DAG.getConstant(8-(3-BitNo), MVT::i32)); // Isolate the bit. - Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, + Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, DAG.getConstant(1, MVT::i32)); // If we are supposed to, toggle the bit. if (InvertBit) - Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, + Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, DAG.getConstant(1, MVT::i32)); return Flags; } SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); // Create a stack slot that is 16-byte aligned. MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); int FrameIdx = FrameInfo->CreateStackObject(16, 16); @@ -3714,56 +3748,58 @@ SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); // Store the input value into Value#0 of the stack slot. - SDValue Store = DAG.getStore(DAG.getEntryNode(), + SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx, NULL, 0); // Load it out. - return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); + return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0); } SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); if (Op.getValueType() == MVT::v4i32) { SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); - SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); - SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. + SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); + SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. SDValue RHSSwap = // = vrlw RHS, 16 - BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG); + BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); // Shrinkify inputs to v8i16. - LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS); - RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS); - RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap); + LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS); + RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS); + RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap); // Low parts multiplied together, generating 32-bit results (we ignore the // top parts). SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, - LHS, RHS, DAG, MVT::v4i32); + LHS, RHS, DAG, dl, MVT::v4i32); SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, - LHS, RHSSwap, Zero, DAG, MVT::v4i32); + LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); // Shift the high parts up 16 bits. - HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG); - return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd); + HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, + Neg16, DAG, dl); + return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); } else if (Op.getValueType() == MVT::v8i16) { SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); - SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); + SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, - LHS, RHS, Zero, DAG); + LHS, RHS, Zero, DAG, dl); } else if (Op.getValueType() == MVT::v16i8) { SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); // Multiply the even 8-bit parts, producing 16-bit sums. SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, - LHS, RHS, DAG, MVT::v8i16); - EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts); + LHS, RHS, DAG, dl, MVT::v8i16); + EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts); // Multiply the odd 8-bit parts, producing 16-bit sums. SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, - LHS, RHS, DAG, MVT::v8i16); - OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); + LHS, RHS, DAG, dl, MVT::v8i16); + OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts); // Merge the results together. SDValue Ops[16]; @@ -3771,8 +3807,8 @@ Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); } - return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts, - DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); + return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v16i8, EvenParts, OddParts, + DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops, 16)); } else { assert(0 && "Unknown mul to lower!"); abort(); @@ -3811,7 +3847,8 @@ return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); - case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); + case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, + Op.getDebugLoc()); case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); @@ -3837,6 +3874,7 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl&Results, SelectionDAG &DAG) { + DebugLoc dl = N->getDebugLoc(); switch (N->getOpcode()) { default: assert(false && "Do not know how to custom type legalize this operation!"); @@ -3844,9 +3882,11 @@ case ISD::FP_ROUND_INREG: { assert(N->getValueType(0) == MVT::ppcf128); assert(N->getOperand(0).getValueType() == MVT::ppcf128); - SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::f64, N->getOperand(0), + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, + MVT::f64, N->getOperand(0), DAG.getIntPtrConstant(0)); - SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::f64, N->getOperand(0), + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, + MVT::f64, N->getOperand(0), DAG.getIntPtrConstant(1)); // This sequence changes FPSCR to do round-to-zero, adds the two halves @@ -3857,7 +3897,7 @@ NodeTys.push_back(MVT::f64); // Return register NodeTys.push_back(MVT::Flag); // Returns a flag for later insns - Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); + Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); MFFSreg = Result.getValue(0); InFlag = Result.getValue(1); @@ -3865,14 +3905,14 @@ NodeTys.push_back(MVT::Flag); // Returns a flag Ops[0] = DAG.getConstant(31, MVT::i32); Ops[1] = InFlag; - Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2); + Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2); InFlag = Result.getValue(0); NodeTys.clear(); NodeTys.push_back(MVT::Flag); // Returns a flag Ops[0] = DAG.getConstant(30, MVT::i32); Ops[1] = InFlag; - Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2); + Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2); InFlag = Result.getValue(0); NodeTys.clear(); @@ -3881,7 +3921,7 @@ Ops[0] = Lo; Ops[1] = Hi; Ops[2] = InFlag; - Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3); + Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3); FPreg = Result.getValue(0); InFlag = Result.getValue(1); @@ -3891,16 +3931,17 @@ Ops[1] = MFFSreg; Ops[2] = FPreg; Ops[3] = InFlag; - Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4); + Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4); FPreg = Result.getValue(0); // We know the low half is about to be thrown away, so just use something // convenient. - Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::ppcf128, FPreg, FPreg)); + Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, + FPreg, FPreg)); return; } case ISD::FP_TO_SINT: - Results.push_back(LowerFP_TO_SINT(SDValue(N, 0), DAG)); + Results.push_back(LowerFP_TO_SINT(SDValue(N, 0), DAG, dl)); return; } } @@ -3925,6 +3966,7 @@ unsigned ptrA = MI->getOperand(1).getReg(); unsigned ptrB = MI->getOperand(2).getReg(); unsigned incr = MI->getOperand(3).getReg(); + DebugLoc dl = MI->getDebugLoc(); MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); @@ -3950,13 +3992,13 @@ // bne- loopMBB // fallthrough --> exitMBB BB = loopMBB; - BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) + BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) .addReg(ptrA).addReg(ptrB); if (BinOpcode) - BuildMI(BB, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); - BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) + BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); + BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) .addReg(TmpReg).addReg(ptrA).addReg(ptrB); - BuildMI(BB, TII->get(PPC::BCC)) + BuildMI(BB, dl, TII->get(PPC::BCC)) .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); BB->addSuccessor(loopMBB); BB->addSuccessor(exitMBB); @@ -3989,6 +4031,7 @@ unsigned ptrA = MI->getOperand(1).getReg(); unsigned ptrB = MI->getOperand(2).getReg(); unsigned incr = MI->getOperand(3).getReg(); + DebugLoc dl = MI->getDebugLoc(); MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); @@ -4041,47 +4084,47 @@ if (ptrA!=PPC::R0) { Ptr1Reg = RegInfo.createVirtualRegister(RC); - BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) + BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) .addReg(ptrA).addReg(ptrB); } else { Ptr1Reg = ptrB; } - BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) + BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); - BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) + BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); if (is64bit) - BuildMI(BB, TII->get(PPC::RLDICR), PtrReg) + BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) .addReg(Ptr1Reg).addImm(0).addImm(61); else - BuildMI(BB, TII->get(PPC::RLWINM), PtrReg) + BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); - BuildMI(BB, TII->get(PPC::SLW), Incr2Reg) + BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg) .addReg(incr).addReg(ShiftReg); if (is8bit) - BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255); + BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); else { - BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0); - BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535); + BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); + BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535); } - BuildMI(BB, TII->get(PPC::SLW), MaskReg) + BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) .addReg(Mask2Reg).addReg(ShiftReg); BB = loopMBB; - BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg) + BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) .addReg(PPC::R0).addReg(PtrReg); if (BinOpcode) - BuildMI(BB, TII->get(BinOpcode), TmpReg) + BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) .addReg(Incr2Reg).addReg(TmpDestReg); - BuildMI(BB, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) + BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) .addReg(TmpDestReg).addReg(MaskReg); - BuildMI(BB, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) + BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) .addReg(TmpReg).addReg(MaskReg); - BuildMI(BB, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) + BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) .addReg(Tmp3Reg).addReg(Tmp2Reg); - BuildMI(BB, TII->get(PPC::STWCX)) + BuildMI(BB, dl, TII->get(PPC::STWCX)) .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg); - BuildMI(BB, TII->get(PPC::BCC)) + BuildMI(BB, dl, TII->get(PPC::BCC)) .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); BB->addSuccessor(loopMBB); BB->addSuccessor(exitMBB); @@ -4089,7 +4132,7 @@ // exitMBB: // ... BB = exitMBB; - BuildMI(BB, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg); + BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg); return BB; } @@ -4126,7 +4169,8 @@ MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); unsigned SelectPred = MI->getOperand(4).getImm(); - BuildMI(BB, TII->get(PPC::BCC)) + DebugLoc dl = MI->getDebugLoc(); + BuildMI(BB, dl, TII->get(PPC::BCC)) .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); F->insert(It, copy0MBB); F->insert(It, sinkMBB); @@ -4149,7 +4193,7 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg()) + BuildMI(BB, dl, TII->get(PPC::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); } @@ -4225,6 +4269,7 @@ unsigned ptrB = MI->getOperand(2).getReg(); unsigned oldval = MI->getOperand(3).getReg(); unsigned newval = MI->getOperand(4).getReg(); + DebugLoc dl = MI->getDebugLoc(); MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); @@ -4253,26 +4298,26 @@ // st[wd]cx. dest, ptr // exitBB: BB = loop1MBB; - BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) + BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) .addReg(ptrA).addReg(ptrB); - BuildMI(BB, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) + BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) .addReg(oldval).addReg(dest); - BuildMI(BB, TII->get(PPC::BCC)) + BuildMI(BB, dl, TII->get(PPC::BCC)) .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); BB->addSuccessor(loop2MBB); BB->addSuccessor(midMBB); BB = loop2MBB; - BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) + BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) .addReg(newval).addReg(ptrA).addReg(ptrB); - BuildMI(BB, TII->get(PPC::BCC)) + BuildMI(BB, dl, TII->get(PPC::BCC)) .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); - BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB); + BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); BB->addSuccessor(loop1MBB); BB->addSuccessor(exitMBB); BB = midMBB; - BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) + BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) .addReg(dest).addReg(ptrA).addReg(ptrB); BB->addSuccessor(exitMBB); @@ -4292,6 +4337,7 @@ unsigned ptrB = MI->getOperand(2).getReg(); unsigned oldval = MI->getOperand(3).getReg(); unsigned newval = MI->getOperand(4).getReg(); + DebugLoc dl = MI->getDebugLoc(); MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); @@ -4356,69 +4402,73 @@ // srw dest, tmpDest, shift if (ptrA!=PPC::R0) { Ptr1Reg = RegInfo.createVirtualRegister(RC); - BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) + BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) .addReg(ptrA).addReg(ptrB); } else { Ptr1Reg = ptrB; } - BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) + BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); - BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) + BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); if (is64bit) - BuildMI(BB, TII->get(PPC::RLDICR), PtrReg) + BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) .addReg(Ptr1Reg).addImm(0).addImm(61); else - BuildMI(BB, TII->get(PPC::RLWINM), PtrReg) + BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); - BuildMI(BB, TII->get(PPC::SLW), NewVal2Reg) + BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) .addReg(newval).addReg(ShiftReg); - BuildMI(BB, TII->get(PPC::SLW), OldVal2Reg) + BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) .addReg(oldval).addReg(ShiftReg); if (is8bit) - BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255); + BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); else { - BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0); - BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535); + BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); + BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) + .addReg(Mask3Reg).addImm(65535); } - BuildMI(BB, TII->get(PPC::SLW), MaskReg) + BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) .addReg(Mask2Reg).addReg(ShiftReg); - BuildMI(BB, TII->get(PPC::AND), NewVal3Reg) + BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg) .addReg(NewVal2Reg).addReg(MaskReg); - BuildMI(BB, TII->get(PPC::AND), OldVal3Reg) + BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg) .addReg(OldVal2Reg).addReg(MaskReg); BB = loop1MBB; - BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg) + BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) .addReg(PPC::R0).addReg(PtrReg); - BuildMI(BB, TII->get(PPC::AND),TmpReg).addReg(TmpDestReg).addReg(MaskReg); - BuildMI(BB, TII->get(PPC::CMPW), PPC::CR0) + BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) + .addReg(TmpDestReg).addReg(MaskReg); + BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0) .addReg(TmpReg).addReg(OldVal3Reg); - BuildMI(BB, TII->get(PPC::BCC)) + BuildMI(BB, dl, TII->get(PPC::BCC)) .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); BB->addSuccessor(loop2MBB); BB->addSuccessor(midMBB); BB = loop2MBB; - BuildMI(BB, TII->get(PPC::ANDC),Tmp2Reg).addReg(TmpDestReg).addReg(MaskReg); - BuildMI(BB, TII->get(PPC::OR),Tmp4Reg).addReg(Tmp2Reg).addReg(NewVal3Reg); - BuildMI(BB, TII->get(PPC::STWCX)).addReg(Tmp4Reg) + BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg) + .addReg(TmpDestReg).addReg(MaskReg); + BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg) + .addReg(Tmp2Reg).addReg(NewVal3Reg); + BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg) .addReg(PPC::R0).addReg(PtrReg); - BuildMI(BB, TII->get(PPC::BCC)) + BuildMI(BB, dl, TII->get(PPC::BCC)) .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); - BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB); + BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); BB->addSuccessor(loop1MBB); BB->addSuccessor(exitMBB); BB = midMBB; - BuildMI(BB, TII->get(PPC::STWCX)).addReg(TmpDestReg) + BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg) .addReg(PPC::R0).addReg(PtrReg); BB->addSuccessor(exitMBB); // exitMBB: // ... BB = exitMBB; - BuildMI(BB, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg); + BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg); } else { assert(0 && "Unexpected instr type to insert"); } @@ -4435,6 +4485,7 @@ DAGCombinerInfo &DCI) const { TargetMachine &TM = getTargetMachine(); SelectionDAG &DAG = DCI.DAG; + DebugLoc dl = N->getDebugLoc(); switch (N->getOpcode()) { default: break; case PPCISD::SHL: @@ -4467,16 +4518,16 @@ N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { SDValue Val = N->getOperand(0).getOperand(0); if (Val.getValueType() == MVT::f32) { - Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); + Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); DCI.AddToWorklist(Val.getNode()); } - Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); + Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val); DCI.AddToWorklist(Val.getNode()); - Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); + Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val); DCI.AddToWorklist(Val.getNode()); if (N->getValueType(0) == MVT::f32) { - Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val, + Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val, DAG.getIntPtrConstant(0)); DCI.AddToWorklist(Val.getNode()); } @@ -4497,13 +4548,13 @@ N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { SDValue Val = N->getOperand(1).getOperand(0); if (Val.getValueType() == MVT::f32) { - Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); + Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); DCI.AddToWorklist(Val.getNode()); } - Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); + Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); DCI.AddToWorklist(Val.getNode()); - Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, + Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val, N->getOperand(2), N->getOperand(3)); DCI.AddToWorklist(Val.getNode()); return Val; @@ -4517,10 +4568,10 @@ SDValue BSwapOp = N->getOperand(1).getOperand(0); // Do an any-extend to 32-bits if this is a half-word input. if (BSwapOp.getValueType() == MVT::i16) - BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp); + BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); - return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp, - N->getOperand(2), N->getOperand(3), + return DAG.getNode(PPCISD::STBRX, dl, MVT::Other, N->getOperand(0), + BSwapOp, N->getOperand(2), N->getOperand(3), DAG.getValueType(N->getOperand(1).getValueType())); } break; @@ -4542,12 +4593,12 @@ MO, // MemOperand DAG.getValueType(N->getValueType(0)) // VT }; - SDValue BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); + SDValue BSLoad = DAG.getNode(PPCISD::LBRX, dl, VTs, Ops, 4); // If this is an i16 load, insert the truncate. SDValue ResVal = BSLoad; if (N->getValueType(0) == MVT::i16) - ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad); + ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); // First, combine the bswap away. This makes the value produced by the // load dead. @@ -4635,7 +4686,7 @@ if (CC == ISD::SETEQ) // Cond never true, remove branch. return N->getOperand(0); // Always !=, turn it into an unconditional branch. - return DAG.getNode(ISD::BR, MVT::Other, + return DAG.getNode(ISD::BR, dl, MVT::Other, N->getOperand(0), N->getOperand(4)); } @@ -4650,7 +4701,7 @@ }; VTs.push_back(LHS.getOperand(2).getValueType()); VTs.push_back(MVT::Flag); - SDValue CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); + SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); // Unpack the result based on how the target uses it. PPC::Predicate CompOpc; @@ -4670,7 +4721,7 @@ break; } - return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), + return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), DAG.getConstant(CompOpc, MVT::i32), DAG.getRegister(PPC::CR6, MVT::i32), N->getOperand(4), CompNode.getValue(1)); @@ -4887,6 +4938,7 @@ } SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); // Depths > 0 not supported yet! if (cast(Op.getOperand(0))->getZExtValue() > 0) return SDValue(); @@ -4900,10 +4952,12 @@ // Make sure the function really does not optimize away the store of the RA // to the stack. FuncInfo->setLRStoreRequired(); - return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); + return DAG.getLoad(getPointerTy(), dl, + DAG.getEntryNode(), RetAddrFI, NULL, 0); } SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); // Depths > 0 not supported yet! if (cast(Op.getOperand(0))->getZExtValue() > 0) return SDValue(); @@ -4917,10 +4971,10 @@ && MFI->getStackSize(); if (isPPC64) - return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1, + return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1, MVT::i64); else - return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1, + return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1, MVT::i32); } Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.h?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.h (original) +++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.h Sat Feb 14 07:20:23 2009 @@ -340,10 +340,11 @@ SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, - int SPDiff, - SDValue Chain, - SDValue &LROpOut, - SDValue &FPOpOut); + int SPDiff, + SDValue Chain, + SDValue &LROpOut, + SDValue &FPOpOut, + DebugLoc dl); SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG); SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); @@ -374,7 +375,7 @@ SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget); SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); - SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG); + SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, DebugLoc dl); SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG); SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG); SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG); Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp Sat Feb 14 07:20:23 2009 @@ -174,7 +174,7 @@ // Create a new instruction. unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); bool Reg0IsDead = MI->getOperand(0).isDead(); - return BuildMI(MF, MI->getDesc()) + return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) .addReg(Reg0, true, false, false, Reg0IsDead) .addReg(Reg2, false, false, Reg2IsKill) .addReg(Reg1, false, false, Reg1IsKill) @@ -197,7 +197,10 @@ void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { - BuildMI(MBB, MI, get(PPC::NOP)); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + + BuildMI(MBB, MI, DL, get(PPC::NOP)); } @@ -289,6 +292,8 @@ PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const { + // FIXME this should probably have a DebugLoc argument + DebugLoc dl = DebugLoc::getUnknownLoc(); // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && @@ -297,17 +302,17 @@ // One-way branch. if (FBB == 0) { if (Cond.empty()) // Unconditional branch - BuildMI(&MBB, get(PPC::B)).addMBB(TBB); + BuildMI(&MBB, dl, get(PPC::B)).addMBB(TBB); else // Conditional branch - BuildMI(&MBB, get(PPC::BCC)) + BuildMI(&MBB, dl, get(PPC::BCC)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); return 1; } // Two-way Conditional Branch. - BuildMI(&MBB, get(PPC::BCC)) + BuildMI(&MBB, dl, get(PPC::BCC)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); - BuildMI(&MBB, get(PPC::B)).addMBB(FBB); + BuildMI(&MBB, dl, get(PPC::B)).addMBB(FBB); return 2; } @@ -321,20 +326,23 @@ return false; } + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if (DestRC == PPC::GPRCRegisterClass) { - BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); } else if (DestRC == PPC::G8RCRegisterClass) { - BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); } else if (DestRC == PPC::F4RCRegisterClass) { - BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::FMRS), DestReg).addReg(SrcReg); } else if (DestRC == PPC::F8RCRegisterClass) { - BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::FMRD), DestReg).addReg(SrcReg); } else if (DestRC == PPC::CRRCRegisterClass) { - BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg); } else if (DestRC == PPC::VRRCRegisterClass) { - BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); } else if (DestRC == PPC::CRBITRCRegisterClass) { - BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg); } else { // Attempt to copy register that is not GPR or FPR return false; @@ -349,43 +357,44 @@ int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const{ + DebugLoc DL = DebugLoc::getUnknownLoc(); if (RC == PPC::GPRCRegisterClass) { if (SrcReg != PPC::LR) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW)) + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) .addReg(SrcReg, false, false, isKill), FrameIdx)); } else { // FIXME: this spills LR immediately to memory in one step. To do this, // we use R11, which we know cannot be used in the prolog/epilog. This is // a hack. - NewMIs.push_back(BuildMI(MF, get(PPC::MFLR), PPC::R11)); - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW)) + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) .addReg(PPC::R11, false, false, isKill), FrameIdx)); } } else if (RC == PPC::G8RCRegisterClass) { if (SrcReg != PPC::LR8) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD)) + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) .addReg(SrcReg, false, false, isKill), FrameIdx)); } else { // FIXME: this spills LR immediately to memory in one step. To do this, // we use R11, which we know cannot be used in the prolog/epilog. This is // a hack. - NewMIs.push_back(BuildMI(MF, get(PPC::MFLR8), PPC::X11)); - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD)) + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11)); + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) .addReg(PPC::X11, false, false, isKill), FrameIdx)); } } else if (RC == PPC::F8RCRegisterClass) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFD)) + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) .addReg(SrcReg, false, false, isKill), FrameIdx)); } else if (RC == PPC::F4RCRegisterClass) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFS)) + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) .addReg(SrcReg, false, false, isKill), FrameIdx)); } else if (RC == PPC::CRRCRegisterClass) { if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { // FIXME (64-bit): Enable - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::SPILL_CR)) + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) .addReg(SrcReg, false, false, isKill), FrameIdx)); return true; @@ -393,18 +402,18 @@ // FIXME: We use R0 here, because it isn't available for RA. We need to // store the CR in the low 4-bits of the saved value. First, issue a MFCR // to save all of the CRBits. - NewMIs.push_back(BuildMI(MF, get(PPC::MFCR), PPC::R0)); + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCR), PPC::R0)); // If the saved register wasn't CR0, shift the bits left so that they are // in CR0's slot. if (SrcReg != PPC::CR0) { unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; // rlwinm r0, r0, ShiftBits, 0, 31. - NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0) + NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0) .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31)); } - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW)) + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) .addReg(PPC::R0, false, false, isKill), FrameIdx)); } @@ -440,9 +449,9 @@ // STVX VAL, 0, R0 // // FIXME: We use R0 here, because it isn't available for RA. - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0), + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), FrameIdx, 0, 0)); - NewMIs.push_back(BuildMI(MF, get(PPC::STVX)) + NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX)) .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0)); } else { assert(0 && "Unknown regclass!"); @@ -484,6 +493,7 @@ return; } + DebugLoc DL = DebugLoc::getUnknownLoc(); unsigned Opc = 0; if (RC == PPC::GPRCRegisterClass) { Opc = PPC::STW; @@ -499,7 +509,7 @@ assert(0 && "Unknown regclass!"); abort(); } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)) + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) .addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; @@ -515,37 +525,37 @@ } void -PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, +PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs)const{ if (RC == PPC::GPRCRegisterClass) { if (DestReg != PPC::LR) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), DestReg), - FrameIdx)); + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), + DestReg), FrameIdx)); } else { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R11), - FrameIdx)); - NewMIs.push_back(BuildMI(MF, get(PPC::MTLR)).addReg(PPC::R11)); + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), + PPC::R11), FrameIdx)); + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11)); } } else if (RC == PPC::G8RCRegisterClass) { if (DestReg != PPC::LR8) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), DestReg), + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg), FrameIdx)); } else { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), PPC::R11), - FrameIdx)); - NewMIs.push_back(BuildMI(MF, get(PPC::MTLR8)).addReg(PPC::R11)); + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), + PPC::R11), FrameIdx)); + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11)); } } else if (RC == PPC::F8RCRegisterClass) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFD), DestReg), + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg), FrameIdx)); } else if (RC == PPC::F4RCRegisterClass) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFS), DestReg), + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg), FrameIdx)); } else if (RC == PPC::CRRCRegisterClass) { // FIXME: We use R0 here, because it isn't available for RA. - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R0), + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), PPC::R0), FrameIdx)); // If the reloaded register isn't CR0, shift the bits right so that they are @@ -553,11 +563,11 @@ if (DestReg != PPC::CR0) { unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; // rlwinm r11, r11, 32-ShiftBits, 0, 31. - NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0) + NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0) .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31)); } - NewMIs.push_back(BuildMI(MF, get(PPC::MTCRF), DestReg).addReg(PPC::R0)); + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg).addReg(PPC::R0)); } else if (RC == PPC::CRBITRCRegisterClass) { unsigned Reg = 0; @@ -578,7 +588,7 @@ else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN) Reg = PPC::CR7; - return LoadRegFromStackSlot(MF, Reg, FrameIdx, + return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx, PPC::CRRCRegisterClass, NewMIs); } else if (RC == PPC::VRRCRegisterClass) { @@ -587,9 +597,9 @@ // Dest = LVX 0, R0 // // FIXME: We use R0 here, because it isn't available for RA. - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0), + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), FrameIdx, 0, 0)); - NewMIs.push_back(BuildMI(MF, get(PPC::LVX),DestReg).addReg(PPC::R0) + NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0) .addReg(PPC::R0)); } else { assert(0 && "Unknown regclass!"); @@ -604,7 +614,9 @@ const TargetRegisterClass *RC) const { MachineFunction &MF = *MBB.getParent(); SmallVector NewMIs; - LoadRegFromStackSlot(MF, DestReg, FrameIdx, RC, NewMIs); + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs); for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) MBB.insert(MI, NewMIs[i]); } @@ -614,7 +626,8 @@ const TargetRegisterClass *RC, SmallVectorImpl &NewMIs)const{ if (Addr[0].isFI()) { - LoadRegFromStackSlot(MF, DestReg, Addr[0].getIndex(), RC, NewMIs); + LoadRegFromStackSlot(MF, DebugLoc::getUnknownLoc(), + DestReg, Addr[0].getIndex(), RC, NewMIs); return; } @@ -635,7 +648,8 @@ assert(0 && "Unknown regclass!"); abort(); } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) @@ -668,13 +682,13 @@ if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::STW)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW)) .addReg(InReg, false, false, isKill), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::LWZ)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ)) .addReg(OutReg, true, false, false, isDead), FrameIndex); } @@ -683,13 +697,13 @@ if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::STD)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD)) .addReg(InReg, false, false, isKill), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::LD)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD)) .addReg(OutReg, true, false, false, isDead), FrameIndex); } @@ -697,13 +711,13 @@ if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::STFD)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFD)) .addReg(InReg, false, false, isKill), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::LFD)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFD)) .addReg(OutReg, true, false, false, isDead), FrameIndex); } @@ -711,13 +725,13 @@ if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::STFS)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFS)) .addReg(InReg, false, false, isKill), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = addFrameReference(BuildMI(MF, get(PPC::LFS)) + NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFS)) .addReg(OutReg, true, false, false, isDead), FrameIndex); } Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h (original) +++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h Sat Feb 14 07:20:23 2009 @@ -69,7 +69,7 @@ unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; - void LoadRegFromStackSlot(MachineFunction &MF, + void LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.cpp Sat Feb 14 07:20:23 2009 @@ -426,18 +426,20 @@ unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; + MachineInstr *MI = I; + DebugLoc dl = MI->getDebugLoc(); if (isInt16(CalleeAmt)) { - BuildMI(MBB, I, TII.get(ADDIInstr), StackReg).addReg(StackReg). + BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg). addImm(CalleeAmt); } else { MachineBasicBlock::iterator MBBI = I; - BuildMI(MBB, MBBI, TII.get(LISInstr), TmpReg) + BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) .addImm(CalleeAmt >> 16); - BuildMI(MBB, MBBI, TII.get(ORIInstr), TmpReg) + BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) .addReg(TmpReg, false, false, true) .addImm(CalleeAmt & 0xFFFF); - BuildMI(MBB, MBBI, TII.get(ADDInstr)) + BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) .addReg(StackReg) .addReg(StackReg) .addReg(TmpReg); @@ -481,6 +483,7 @@ MachineFrameInfo *MFI = MF.getFrameInfo(); // Determine whether 64-bit pointers are used. bool LP64 = Subtarget.isPPC64(); + DebugLoc dl = MI.getDebugLoc(); // Get the maximum call stack size. unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); @@ -511,20 +514,20 @@ Reg = PPC::R0; if (MaxAlign < TargetAlign && isInt16(FrameSize)) { - BuildMI(MBB, II, TII.get(PPC::ADDI), Reg) + BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) .addReg(PPC::R31) .addImm(FrameSize); } else if (LP64) { if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. - BuildMI(MBB, II, TII.get(PPC::LD), Reg) + BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) .addImm(0) .addReg(PPC::X1); else - BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) + BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) .addImm(0) .addReg(PPC::X1); } else { - BuildMI(MBB, II, TII.get(PPC::LWZ), Reg) + BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) .addImm(0) .addReg(PPC::R1); } @@ -533,39 +536,39 @@ // address of new allocated space. if (LP64) { if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. - BuildMI(MBB, II, TII.get(PPC::STDUX)) + BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) .addReg(Reg, false, false, true) .addReg(PPC::X1) .addReg(MI.getOperand(1).getReg()); else - BuildMI(MBB, II, TII.get(PPC::STDUX)) + BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) .addReg(PPC::X0, false, false, true) .addReg(PPC::X1) .addReg(MI.getOperand(1).getReg()); if (!MI.getOperand(1).isKill()) - BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) + BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) .addReg(PPC::X1) .addImm(maxCallFrameSize); else // Implicitly kill the register. - BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) + BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) .addReg(PPC::X1) .addImm(maxCallFrameSize) .addReg(MI.getOperand(1).getReg(), false, true, true); } else { - BuildMI(MBB, II, TII.get(PPC::STWUX)) + BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) .addReg(Reg, false, false, true) .addReg(PPC::R1) .addReg(MI.getOperand(1).getReg()); if (!MI.getOperand(1).isKill()) - BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) + BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) .addReg(PPC::R1) .addImm(maxCallFrameSize); else // Implicitly kill the register. - BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) + BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) .addReg(PPC::R1) .addImm(maxCallFrameSize) .addReg(MI.getOperand(1).getReg(), false, true, true); @@ -590,6 +593,7 @@ MachineInstr &MI = *II; // ; SPILL_CR , , // Get the instruction's basic block. MachineBasicBlock &MBB = *MI.getParent(); + DebugLoc dl = MI.getDebugLoc(); const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; @@ -599,10 +603,10 @@ // We need to store the CR in the low 4-bits of the saved value. First, issue // an MFCR to save all of the CRBits. Add an implicit kill of the CR. if (!MI.getOperand(0).isKill()) - BuildMI(MBB, II, TII.get(PPC::MFCR), Reg); + BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg); else // Implicitly kill the CR register. - BuildMI(MBB, II, TII.get(PPC::MFCR), Reg) + BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg) .addReg(MI.getOperand(0).getReg(), false, true, true); // If the saved register wasn't CR0, shift the bits left so that they are in @@ -610,13 +614,13 @@ unsigned SrcReg = MI.getOperand(0).getReg(); if (SrcReg != PPC::CR0) // rlwinm rA, rA, ShiftBits, 0, 31. - BuildMI(MBB, II, TII.get(PPC::RLWINM), Reg) + BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) .addReg(Reg, false, false, true) .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) .addImm(0) .addImm(31); - addFrameReference(BuildMI(MBB, II, TII.get(PPC::STW)) + addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) .addReg(Reg, false, false, MI.getOperand(1).getImm()), FrameIndex); @@ -636,6 +640,7 @@ MachineFunction &MF = *MBB.getParent(); // Get the frame info. MachineFrameInfo *MFI = MF.getFrameInfo(); + DebugLoc dl = MI.getDebugLoc(); // Find out which operand is the frame index. unsigned FIOperandNo = 0; @@ -727,9 +732,9 @@ SReg = PPC::R0; // Insert a set of rA with the full offset value before the ld, st, or add - BuildMI(MBB, II, TII.get(PPC::LIS), SReg) + BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg) .addImm(Offset >> 16); - BuildMI(MBB, II, TII.get(PPC::ORI), SReg) + BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg) .addReg(SReg, false, false, true) .addImm(Offset); @@ -815,6 +820,7 @@ // transform this into the appropriate ORI instruction. static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { MachineFunction *MF = MI->getParent()->getParent(); + DebugLoc dl = MI->getDebugLoc(); unsigned UsedRegMask = 0; for (unsigned i = 0; i != 32; ++i) @@ -850,33 +856,33 @@ if ((UsedRegMask & 0xFFFF) == UsedRegMask) { if (DstReg != SrcReg) - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) + BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) .addReg(SrcReg) .addImm(UsedRegMask); else - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) + BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) .addReg(SrcReg, false, false, true) .addImm(UsedRegMask); } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { if (DstReg != SrcReg) - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) + BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) .addReg(SrcReg) .addImm(UsedRegMask >> 16); else - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) + BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) .addReg(SrcReg, false, false, true) .addImm(UsedRegMask >> 16); } else { if (DstReg != SrcReg) - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) + BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) .addReg(SrcReg) .addImm(UsedRegMask >> 16); else - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) + BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) .addReg(SrcReg, false, false, true) .addImm(UsedRegMask >> 16); - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) + BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) .addReg(DstReg, false, false, true) .addImm(UsedRegMask & 0xFFFF); } @@ -997,6 +1003,7 @@ MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); + DebugLoc dl = DebugLoc::getUnknownLoc(); bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) || !MF.getFunction()->doesNotThrow() || UnwindTablesMandatory; @@ -1037,31 +1044,31 @@ if (IsPPC64) { if (MustSaveLR) - BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0); + BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); if (HasFP) - BuildMI(MBB, MBBI, TII.get(PPC::STD)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) .addReg(PPC::X31) .addImm(FPOffset/4) .addReg(PPC::X1); if (MustSaveLR) - BuildMI(MBB, MBBI, TII.get(PPC::STD)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) .addReg(PPC::X0) .addImm(LROffset / 4) .addReg(PPC::X1); } else { if (MustSaveLR) - BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0); + BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); if (HasFP) - BuildMI(MBB, MBBI, TII.get(PPC::STW)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) .addReg(PPC::R31) .addImm(FPOffset) .addReg(PPC::R1); if (MustSaveLR) - BuildMI(MBB, MBBI, TII.get(PPC::STW)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) .addReg(PPC::R0) .addImm(LROffset) .addReg(PPC::R1); @@ -1077,7 +1084,7 @@ if (needsFrameMoves) { // Mark effective beginning of when frame pointer becomes valid. FrameLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId); + BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId); } // Adjust stack pointer: r1 += NegFrameSize. @@ -1088,30 +1095,30 @@ assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); - BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) .addReg(PPC::R1) .addImm(0) .addImm(32 - Log2_32(MaxAlign)) .addImm(31); - BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) .addReg(PPC::R0, false, false, true) .addImm(NegFrameSize); - BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) .addReg(PPC::R1) .addReg(PPC::R1) .addReg(PPC::R0); } else if (isInt16(NegFrameSize)) { - BuildMI(MBB, MBBI, TII.get(PPC::STWU), PPC::R1) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) .addReg(PPC::R1) .addImm(NegFrameSize) .addReg(PPC::R1); } else { - BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) .addImm(NegFrameSize >> 16); - BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) .addReg(PPC::R0, false, false, true) .addImm(NegFrameSize & 0xFFFF); - BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) .addReg(PPC::R1) .addReg(PPC::R1) .addReg(PPC::R0); @@ -1121,29 +1128,29 @@ assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); - BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) .addReg(PPC::X1) .addImm(0) .addImm(64 - Log2_32(MaxAlign)); - BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) .addReg(PPC::X0) .addImm(NegFrameSize); - BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) .addReg(PPC::X1) .addReg(PPC::X1) .addReg(PPC::X0); } else if (isInt16(NegFrameSize)) { - BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) .addReg(PPC::X1) .addImm(NegFrameSize / 4) .addReg(PPC::X1); } else { - BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) .addImm(NegFrameSize >> 16); - BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) .addReg(PPC::X0, false, false, true) .addImm(NegFrameSize & 0xFFFF); - BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) .addReg(PPC::X1) .addReg(PPC::X1) .addReg(PPC::X0); @@ -1186,7 +1193,7 @@ // Mark effective beginning of when frame pointer is ready. unsigned ReadyLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId); + BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId); MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) : (IsPPC64 ? PPC::X1 : PPC::R1)); @@ -1197,11 +1204,11 @@ // If there is a frame pointer, copy R1 into R31 if (HasFP) { if (!IsPPC64) { - BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31) + BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) .addReg(PPC::R1) .addReg(PPC::R1); } else { - BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31) + BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) .addReg(PPC::X1) .addReg(PPC::X1); } @@ -1212,6 +1219,7 @@ MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = prior(MBB.end()); unsigned RetOpcode = MBBI->getOpcode(); + DebugLoc dl = DebugLoc::getUnknownLoc(); assert( (RetOpcode == PPC::BLR || RetOpcode == PPC::TCRETURNri || @@ -1274,73 +1282,75 @@ // value of R31 in this case. if (FI->hasFastCall() && isInt16(FrameSize)) { assert(hasFP(MF) && "Expecting a valid the frame pointer."); - BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) .addReg(PPC::R31).addImm(FrameSize); } else if(FI->hasFastCall()) { - BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) .addImm(FrameSize >> 16); - BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) .addReg(PPC::R0, false, false, true) .addImm(FrameSize & 0xFFFF); - BuildMI(MBB, MBBI, TII.get(PPC::ADD4)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) .addReg(PPC::R1) .addReg(PPC::R31) .addReg(PPC::R0); } else if (isInt16(FrameSize) && (!ALIGN_STACK || TargetAlign >= MaxAlign) && !MFI->hasVarSizedObjects()) { - BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) .addReg(PPC::R1).addImm(FrameSize); } else { - BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1); + BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) + .addImm(0).addReg(PPC::R1); } } else { if (FI->hasFastCall() && isInt16(FrameSize)) { assert(hasFP(MF) && "Expecting a valid the frame pointer."); - BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) .addReg(PPC::X31).addImm(FrameSize); } else if(FI->hasFastCall()) { - BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) .addImm(FrameSize >> 16); - BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) .addReg(PPC::X0, false, false, true) .addImm(FrameSize & 0xFFFF); - BuildMI(MBB, MBBI, TII.get(PPC::ADD8)) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) .addReg(PPC::X1) .addReg(PPC::X31) .addReg(PPC::X0); } else if (isInt16(FrameSize) && TargetAlign >= MaxAlign && !MFI->hasVarSizedObjects()) { - BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) + BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) .addReg(PPC::X1).addImm(FrameSize); } else { - BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1); + BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) + .addImm(0).addReg(PPC::X1); } } } if (IsPPC64) { if (MustSaveLR) - BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) .addImm(LROffset/4).addReg(PPC::X1); if (HasFP) - BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31) + BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) .addImm(FPOffset/4).addReg(PPC::X1); if (MustSaveLR) - BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0); + BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); } else { if (MustSaveLR) - BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0) + BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) .addImm(LROffset).addReg(PPC::R1); if (HasFP) - BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31) + BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) .addImm(FPOffset).addReg(PPC::R1); if (MustSaveLR) - BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0); + BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); } // Callee pop calling convention. Pop parameter/linkage area. Used for tail @@ -1358,15 +1368,15 @@ unsigned ORIInstr = IsPPC64 ? PPC::ORI8 : PPC::ORI; if (CallerAllocatedAmt && isInt16(CallerAllocatedAmt)) { - BuildMI(MBB, MBBI, TII.get(ADDIInstr), StackReg) + BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) .addReg(StackReg).addImm(CallerAllocatedAmt); } else { - BuildMI(MBB, MBBI, TII.get(LISInstr), TmpReg) + BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) .addImm(CallerAllocatedAmt >> 16); - BuildMI(MBB, MBBI, TII.get(ORIInstr), TmpReg) + BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) .addReg(TmpReg, false, false, true) .addImm(CallerAllocatedAmt & 0xFFFF); - BuildMI(MBB, MBBI, TII.get(ADDInstr)) + BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) .addReg(StackReg) .addReg(FPReg) .addReg(TmpReg); @@ -1374,31 +1384,31 @@ } else if (RetOpcode == PPC::TCRETURNdi) { MBBI = prior(MBB.end()); MachineOperand &JumpTarget = MBBI->getOperand(0); - BuildMI(MBB, MBBI, TII.get(PPC::TAILB)). + BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); } else if (RetOpcode == PPC::TCRETURNri) { MBBI = prior(MBB.end()); MachineOperand &JumpTarget = MBBI->getOperand(0); assert(JumpTarget.isReg() && "Expecting register operand."); - BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR)); + BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); } else if (RetOpcode == PPC::TCRETURNai) { MBBI = prior(MBB.end()); MachineOperand &JumpTarget = MBBI->getOperand(0); - BuildMI(MBB, MBBI, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); + BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); } else if (RetOpcode == PPC::TCRETURNdi8) { MBBI = prior(MBB.end()); MachineOperand &JumpTarget = MBBI->getOperand(0); - BuildMI(MBB, MBBI, TII.get(PPC::TAILB8)). + BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); } else if (RetOpcode == PPC::TCRETURNri8) { MBBI = prior(MBB.end()); MachineOperand &JumpTarget = MBBI->getOperand(0); assert(JumpTarget.isReg() && "Expecting register operand."); - BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR8)); + BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); } else if (RetOpcode == PPC::TCRETURNai8) { MBBI = prior(MBB.end()); MachineOperand &JumpTarget = MBBI->getOperand(0); - BuildMI(MBB, MBBI, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); + BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); } } Modified: llvm/branches/Apple/Dib/lib/Target/Sparc/DelaySlotFiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Sparc/DelaySlotFiller.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/Sparc/DelaySlotFiller.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/Sparc/DelaySlotFiller.cpp Sat Feb 14 07:20:23 2009 @@ -68,7 +68,7 @@ if (I->getDesc().hasDelaySlot()) { MachineBasicBlock::iterator J = I; ++J; - BuildMI(MBB, J, TII->get(SP::NOP)); + BuildMI(MBB, J, DebugLoc::getUnknownLoc(), TII->get(SP::NOP)); ++FilledSlots; Changed = true; } Modified: llvm/branches/Apple/Dib/lib/Target/Sparc/FPMover.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Sparc/FPMover.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/Sparc/FPMover.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/Sparc/FPMover.cpp Sat Feb 14 07:20:23 2009 @@ -84,6 +84,7 @@ bool Changed = false; for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) { MachineInstr *MI = I++; + DebugLoc dl = MI->getDebugLoc(); if (MI->getOpcode() == SP::FpMOVD || MI->getOpcode() == SP::FpABSD || MI->getOpcode() == SP::FpNEGD) { Changed = true; @@ -114,7 +115,7 @@ DOUT << "FPMover: the modified instr is: " << *MI; // Insert copy for the other half of the double. if (DestDReg != SrcDReg) { - MI = BuildMI(MBB, I, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg) + MI = BuildMI(MBB, I, dl, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg) .addReg(OddSrcReg); DOUT << "FPMover: the inserted instr is: " << *MI; } Modified: llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelDAGToDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelDAGToDAG.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelDAGToDAG.cpp Sat Feb 14 07:20:23 2009 @@ -141,6 +141,7 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) { SDNode *N = Op.getNode(); + DebugLoc dl = N->getDebugLoc(); if (N->isMachineOpcode()) return NULL; // Already selected. @@ -155,12 +156,12 @@ // Set the Y register to the high-part. SDValue TopPart; if (N->getOpcode() == ISD::SDIV) { - TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, + TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, dl, MVT::i32, DivLHS, CurDAG->getTargetConstant(31, MVT::i32)), 0); } else { TopPart = CurDAG->getRegister(SP::G0, MVT::i32); } - TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, + TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, dl, MVT::Flag, TopPart, CurDAG->getRegister(SP::G0, MVT::i32)), 0); // FIXME: Handle div by immediate. @@ -174,7 +175,7 @@ SDValue MulLHS = N->getOperand(0); SDValue MulRHS = N->getOperand(1); unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; - SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, + SDNode *Mul = CurDAG->getTargetNode(Opcode, dl, MVT::i32, MVT::Flag, MulLHS, MulRHS); // The high part is in the Y register. return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1)); Modified: llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff ============================================================================== --- llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelLowering.cpp Sat Feb 14 07:20:23 2009 @@ -36,6 +36,7 @@ SmallVector RVLocs; unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); + DebugLoc dl = Op.getDebugLoc(); // CCState - Info about the registers and stack slot. CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs); @@ -61,15 +62,16 @@ // ISD::RET => ret chain, (regnum1,val1), ... // So i*2+1 index only the regnums. - Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); + Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), + Op.getOperand(i*2+1), Flag); // Guarantee that all emitted copies are stuck together with flags. Flag = Chain.getValue(1); } if (Flag.getNode()) - return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain, Flag); - return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain); + return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, Flag); + return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain); } /// LowerArguments - V8 uses a very simple ABI, where all values are passed in @@ -103,16 +105,16 @@ case MVT::i32: if (I->use_empty()) { // Argument is dead. if (CurArgReg < ArgRegEnd) ++CurArgReg; - ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); + ArgValues.push_back(DAG.getUNDEF(ObjectVT)); } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); - SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); + SDValue Arg = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); if (ObjectVT != MVT::i32) { unsigned AssertOp = ISD::AssertSext; - Arg = DAG.getNode(AssertOp, MVT::i32, Arg, + Arg = DAG.getNode(AssertOp, dl, MVT::i32, Arg, DAG.getValueType(ObjectVT)); - Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); + Arg = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Arg); } ArgValues.push_back(Arg); } else { @@ -120,17 +122,17 @@ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); SDValue Load; if (ObjectVT == MVT::i32) { - Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); + Load = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0); } else { ISD::LoadExtType LoadOp = ISD::SEXTLOAD; // Sparc is big endian, so add an offset based on the ObjectVT. unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8); - FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, + FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, DAG.getConstant(Offset, MVT::i32)); - Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, + Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Root, FIPtr, NULL, 0, ObjectVT); - Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); + Load = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Load); } ArgValues.push_back(Load); } @@ -140,19 +142,19 @@ case MVT::f32: if (I->use_empty()) { // Argument is dead. if (CurArgReg < ArgRegEnd) ++CurArgReg; - ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); + ArgValues.push_back(DAG.getUNDEF(ObjectVT)); } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR // FP value is passed in an integer register. unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); - SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); + SDValue Arg = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); - Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); + Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Arg); ArgValues.push_back(Arg); } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - SDValue Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0); + SDValue Load = DAG.getLoad(MVT::f32, dl, Root, FIPtr, NULL, 0); ArgValues.push_back(Load); } ArgOffset += 4; @@ -163,37 +165,37 @@ if (I->use_empty()) { // Argument is dead. if (CurArgReg < ArgRegEnd) ++CurArgReg; if (CurArgReg < ArgRegEnd) ++CurArgReg; - ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); + ArgValues.push_back(DAG.getUNDEF(ObjectVT)); } else { SDValue HiVal; if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi); - HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); + HiVal = DAG.getCopyFromReg(Root, dl, VRegHi, MVT::i32); } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - HiVal = DAG.getLoad(