From sanjiv.gupta at microchip.com  Mon Apr  6 05:55:06 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Mon, 06 Apr 2009 10:55:06 -0000
Subject: [llvm-commits] [llvm] r68442 - in /llvm/trunk/lib/Target/PIC16:
 PIC16AsmPrinter.cpp PIC16AsmPrinter.h PIC16ISelLowering.cpp
 PIC16ISelLowering.h PIC16InstrInfo.cpp
Message-ID: <200904061055.n36AtBPH027278@zion.cs.uiuc.edu>

Author: sgupta
Date: Mon Apr  6 05:54:50 2009
New Revision: 68442

URL: http://llvm.org/viewvc/llvm-project?rev=68442&view=rev
Log:
Map stack based frameindices for spills to zero based indices that can be accessed based on an external symbol defining the location of temporary data for a function. For example: we have spill slots addressed as foo.tmp + 0, foo.tmp + 1 etc.

Modified:
    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h
    llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp

Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=68442&r1=68441&r2=68442&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Mon Apr  6 05:54:50 2009
@@ -343,7 +343,6 @@
 void PIC16AsmPrinter::emitFunctionData(MachineFunction &MF) {
   const Function *F = MF.getFunction();
   std::string FuncName = Mang->getValueName(F);
-  MachineFrameInfo *MFI= MF.getFrameInfo();
   Module *M = const_cast<Module *>(F->getParent());
   const TargetData *TD = TM.getTargetData();
   unsigned FrameSize = 0;
@@ -406,15 +405,7 @@
     O << VarName << "  RES  " << Size << "\n";
   }
 
-
-  // Emit the variable to hold the space for temporary locations
-  // in function frame.
-  if (MFI->hasStackObjects()) {
-    int indexBegin = MFI->getObjectIndexBegin();
-    int indexEnd = MFI->getObjectIndexEnd();
-    if (indexBegin < indexEnd) {
-      int TempSize = indexEnd - indexBegin; 
-      O << CurrentFnName << ".tmp       RES  " << TempSize <<"\n";
-    }
-  }
+  int TempSize = PTLI->GetTmpSize();
+  if (TempSize > 0 )
+    O << CurrentFnName << ".tmp       RES  " << TempSize <<"\n";
 }

Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h?rev=68442&r1=68441&r2=68442&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h Mon Apr  6 05:54:50 2009
@@ -24,11 +24,12 @@
 
 namespace llvm {
   struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
-  PIC16AsmPrinter(raw_ostream &O, TargetMachine &TM,
+  PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
                     const TargetAsmInfo *T, bool F, bool V)
       : AsmPrinter(O, TM, T, F, V) {
       CurBank = "";
       IsRomData = false;
+      PTLI = TM.getTargetLowering();
     }
     private :
     virtual const char *getPassName() const {
@@ -51,6 +52,7 @@
     bool doFinalization(Module &M);
 
     private:
+    PIC16TargetLowering *PTLI;
     std::string CurBank;
     bool IsRomData;
   };

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=68442&r1=68441&r2=68442&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Mon Apr  6 05:54:50 2009
@@ -31,7 +31,7 @@
 
 // PIC16TargetLowering Constructor.
 PIC16TargetLowering::PIC16TargetLowering(PIC16TargetMachine &TM)
-  : TargetLowering(TM) {
+  : TargetLowering(TM), TmpSize(0) {
   
   Subtarget = &TM.getSubtarget<PIC16Subtarget>();
 
@@ -154,6 +154,17 @@
 
   return Flag;
 }
+// Get the TmpOffset for FrameIndex
+unsigned PIC16TargetLowering::GetTmpOffsetForFI(unsigned FI) {
+  std::map<unsigned, unsigned>::iterator 
+            MapIt = FiTmpOffsetMap.find(FI);
+  if (MapIt != FiTmpOffsetMap.end())
+      return MapIt->second;
+
+  // This FI (FrameIndex) is not yet mapped, so map it
+  FiTmpOffsetMap[FI] = TmpSize; 
+  return TmpSize++;
+}
 
 // To extract chain value from the SDValue Nodes
 // This function will help to maintain the chain extracting
@@ -541,9 +552,9 @@
 //         and non-constant operand of ADD will be treated as pointer.
 // Returns the high and lo part of the address, and the offset(in case of ADD).
 
-void PIC16TargetLowering:: LegalizeAddress(SDValue Ptr, SelectionDAG &DAG, 
-                                           SDValue &Lo, SDValue &Hi,
-                                           unsigned &Offset, DebugLoc dl) {
+void PIC16TargetLowering::LegalizeAddress(SDValue Ptr, SelectionDAG &DAG, 
+                                          SDValue &Lo, SDValue &Hi,
+                                          unsigned &Offset, DebugLoc dl) {
 
   // Offset, by default, should be 0
   Offset = 0;
@@ -849,13 +860,15 @@
                                DAG.getEntryNode(),
                                Op, ES, 
                                DAG.getConstant (1, MVT::i8), // Banksel.
-                               DAG.getConstant (FI, MVT::i8));
+                               DAG.getConstant (GetTmpOffsetForFI(FI), 
+                                                MVT::i8));
 
   // Load the value from ES.
   SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other);
   SDValue Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Store,
                              ES, DAG.getConstant (1, MVT::i8),
-                             DAG.getConstant (FI, MVT::i8));
+                             DAG.getConstant (GetTmpOffsetForFI(FI), 
+                             MVT::i8));
     
   return Load.getValue(0);
 }
@@ -1212,40 +1225,45 @@
     return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1));
 }
 
-// LowerFORMAL_ARGUMENTS - In Lowering FORMAL ARGUMENTS - MERGE_VALUES nodes
-// is returned. MERGE_VALUES nodes number of operands and number of values are
-// equal. Therefore to construct MERGE_VALUE node, UNDEF nodes equal to the
-// number of arguments of function have been created.
+// LowerFORMAL_ARGUMENTS - Argument values are loaded from the
+// <fname>.args + offset. All arguments are already broken to leaglized
+// types, so the offset just runs from 0 to NumArgVals - 1.
 
 SDValue PIC16TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, 
-                                                    SelectionDAG &DAG) {
+                                                   SelectionDAG &DAG) {
   SmallVector<SDValue, 8> ArgValues;
-  unsigned NumArgs = Op.getNode()->getNumValues()-1;
+  unsigned NumArgVals = Op.getNode()->getNumValues() - 1;
   DebugLoc dl = Op.getDebugLoc();
   SDValue Chain = Op.getOperand(0);    // Formal arguments' chain
 
+
+  // Reset the map of FI and TmpOffset 
+  ResetTmpOffsetMap();
+  // Get the callee's name to create the <fname>.args label to pass args.
   MachineFunction &MF = DAG.getMachineFunction();
-  //const TargetData *TD = getTargetData();
   const Function *F = MF.getFunction();
   std::string FuncName = F->getName();
 
+  // Create the <fname>.args external symbol.
   char *tmpName = new char [strlen(FuncName.c_str()) +  6];
   sprintf(tmpName, "%s.args", FuncName.c_str());
-  SDVTList VTs  = DAG.getVTList (MVT::i8, MVT::Other);
   SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
+
+  // Load arg values from the label + offset.
+  SDVTList VTs  = DAG.getVTList (MVT::i8, MVT::Other);
   SDValue BS = DAG.getConstant(1, MVT::i8);
-  for (unsigned i=0; i<NumArgs ; ++i) {
+  for (unsigned i = 0; i < NumArgVals ; ++i) {
     SDValue Offset = DAG.getConstant(i, MVT::i8);
     SDValue PICLoad = DAG.getNode(PIC16ISD::PIC16LdArg, dl, VTs, Chain, ES, BS,
-                                     Offset);
+                                  Offset);
     Chain = getChain(PICLoad);
     ArgValues.push_back(PICLoad);
   }
 
+  // Return a MERGE_VALUE node.
   ArgValues.push_back(Op.getOperand(0));
   return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), 
-                     &ArgValues[0],
-                     ArgValues.size()).getValue(Op.getResNo());
+                     &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
 }
 
 // Perform DAGCombine of PIC16Load.

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h?rev=68442&r1=68441&r2=68442&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h Mon Apr  6 05:54:50 2009
@@ -19,6 +19,7 @@
 #include "PIC16Subtarget.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/Target/TargetLowering.h"
+#include <map>
 
 namespace llvm {
   namespace PIC16ISD {
@@ -117,6 +118,16 @@
     SDValue PerformPIC16LoadCombine(SDNode *N, DAGCombinerInfo &DCI) const; 
     SDValue PerformStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const; 
 
+    // This function returns the Tmp Offset for FrameIndex. If any TmpOffset 
+    // already exists for the FI then it returns the same else it creates the 
+    // new offset and returns.
+    unsigned GetTmpOffsetForFI(unsigned FI); 
+    void ResetTmpOffsetMap() { FiTmpOffsetMap.clear(); SetTmpSize(0); }
+
+    // Return the size of Tmp variable 
+    unsigned GetTmpSize() { return TmpSize; }
+    void SetTmpSize(unsigned Size) { TmpSize = Size; }
+
   private:
     // If the Node is a BUILD_PAIR representing a direct Address,
     // then this function will return true.
@@ -170,6 +181,11 @@
     // Check if operation has a direct load operand.
     inline bool isDirectLoad(const SDValue Op);
 
+  private:
+    // The frameindexes generated for spill/reload are stack based.
+    // This maps maintain zero based indexes for these FIs.
+    std::map<unsigned, unsigned> FiTmpOffsetMap;
+    unsigned TmpSize;
   };
 } // namespace llvm
 

Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp?rev=68442&r1=68441&r2=68442&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp Mon Apr  6 05:54:50 2009
@@ -69,6 +69,7 @@
                                          MachineBasicBlock::iterator I,
                                          unsigned SrcReg, bool isKill, int FI,
                                          const TargetRegisterClass *RC) const {
+  PIC16TargetLowering *PTLI = TM.getTargetLowering();
   DebugLoc DL = DebugLoc::getUnknownLoc();
   if (I != MBB.end()) DL = I->getDebugLoc();
 
@@ -84,7 +85,7 @@
     //MachineRegisterInfo &RI = MF.getRegInfo();
     BuildMI(MBB, I, DL, get(PIC16::movwf))
       .addReg(SrcReg, false, false, isKill)
-      .addImm(FI)
+      .addImm(PTLI->GetTmpOffsetForFI(FI))
       .addExternalSymbol(tmpName)
       .addImm(1); // Emit banksel for it.
   }
@@ -98,6 +99,7 @@
                                           MachineBasicBlock::iterator I,
                                           unsigned DestReg, int FI,
                                           const TargetRegisterClass *RC) const {
+  PIC16TargetLowering *PTLI = TM.getTargetLowering();
   DebugLoc DL = DebugLoc::getUnknownLoc();
   if (I != MBB.end()) DL = I->getDebugLoc();
 
@@ -112,7 +114,7 @@
     //MachineFunction &MF = *MBB.getParent();
     //MachineRegisterInfo &RI = MF.getRegInfo();
     BuildMI(MBB, I, DL, get(PIC16::movf), DestReg)
-      .addImm(FI)
+      .addImm(PTLI->GetTmpOffsetForFI(FI))
       .addExternalSymbol(tmpName)
       .addImm(1); // Emit banksel for it.
   }




From gohman at apple.com  Mon Apr  6 13:48:00 2009
From: gohman at apple.com (Dan Gohman)
Date: Mon, 6 Apr 2009 11:48:00 -0700
Subject: [llvm-commits] [llvm] r66922 - in /llvm/trunk:
	lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/tls13.ll
	test/CodeGen/X86/tls14.ll
In-Reply-To: <38a0d8450904050541r5e13b580o3a66bfa69069a455@mail.gmail.com>
References: <200903131837.n2DIb7PC008719@zion.cs.uiuc.edu>
	<B409E5EA-50A1-4CD2-9E5E-E48DDE5D9731@apple.com>
	<EBD80AAC-81C6-46A8-B124-2286DCC7E0C8@apple.com>
	<38a0d8450903311517m60b40486wc1af6a391faa6b6f@mail.gmail.com>
	<01131E67-E237-482B-BBBE-843A1F6DE0D0@apple.com>
	<38a0d8450904021346y48f1d13ds2c23c13fca2a886a@mail.gmail.com>
	<6FC4BA6E-0E41-47E4-B4E1-D984E9A08B41@apple.com>
	<38a0d8450904030915g2e92040clb9c60b173f044c52@mail.gmail.com>
	<38a0d8450904050541r5e13b580o3a66bfa69069a455@mail.gmail.com>
Message-ID: <BE69A386-8D50-46F1-B182-A44F43BAB7D0@apple.com>


On Apr 5, 2009, at 5:41 AM, Rafael Espindola wrote:

>> I think I will try the idea of always lowering to (load gs:0) + ADDR
>> and then implementing some instruction folding after Select. I assume
>> that is possible, right?
>
> The attached patch does that. I like it a lot more. All that was
> needed to get performance back was a small change to MatchAddress to
> handle a load inside a load.
>
> The only possible issue is that now we produce
>
> movl    $i at NTPOFF, %eax
> addl    %gs:0, %eax
>
> Instead of
>
> movl       %gs:0, %eax
> leal       i at NTPOFF(%eax), %eax
>
> I don't have enough experience with X86 to know which one is best.

It probably depends on the context. The latter at least has the
advantage of allowing the load from %gs:0 of being CSE'd when
there are multiple TLS address computations.

Can this be fixed with code in
X86DAGToDAGISel::IsLegalAndProfitableToFold ? The code at the
top of the function is a heuristic with a similar purpose.

In any event, I don't consider this a show-stopper; we can
continue to tune things like this after the patch is in.

>
>
> What do you think of the current approach?

I think this patch looks like a good approach. I think there are
some tuning things that can be addressed later; I just have a few
minor comments for now.

In this code in isMem in X86InstrInfo.h:

@@ -256,6 +256,7 @@
    return Op+4 <= MI->getNumOperands() &&
      MI->getOperand(Op  ).isReg() && isScale(MI->getOperand(Op+1)) &&
      MI->getOperand(Op+2).isReg() &&
+    MI->getOperand(Op+4).isReg() &&
      (MI->getOperand(Op+3).isImm() ||
       MI->getOperand(Op+3).isGlobal() ||
       MI->getOperand(Op+3).isCPI() ||

The code here only checks for getNumOperands being >= Op+4, so the
call to getOperand(Op+4) could potentially go out of bounds. A simple
fix would be to create a separate isLeaMem function which only expects
4 operands so that isMem can expect 5 (or X86AddrNumOperands)
operands. A more involved fix would be to make all addresses have 5
operands, and just require the fifth operand in an lea to be %reg0.
I don't have a strong preference at this point.

Please add a comment in MatchLoad explaining why it's safe to
do what it's doing.

Please use spaces instead of tabs for indentation.

Thanks for working on this!

Dan



From mrs at apple.com  Mon Apr  6 14:58:12 2009
From: mrs at apple.com (Mike Stump)
Date: Mon, 06 Apr 2009 19:58:12 -0000
Subject: [llvm-commits] [llvm] r68455 - /llvm/trunk/Makefile.rules
Message-ID: <200904061958.n36JwC1F016795@zion.cs.uiuc.edu>

Author: mrs
Date: Mon Apr  6 14:58:11 2009
New Revision: 68455

URL: http://llvm.org/viewvc/llvm-project?rev=68455&view=rev
Log:
Avoid -O3 on Darwin for now.

Modified:
    llvm/trunk/Makefile.rules

Modified: llvm/trunk/Makefile.rules
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=68455&r1=68454&r2=68455&view=diff

==============================================================================
--- llvm/trunk/Makefile.rules (original)
+++ llvm/trunk/Makefile.rules Mon Apr  6 14:58:11 2009
@@ -229,10 +229,12 @@
 CPP.Defines :=
 # OPTIMIZE_OPTION - The optimization level option we want to build LLVM with
 # this can be overridden on the make command line.
-ifneq ($(OS),MingW)
-  OPTIMIZE_OPTION := -O3
-else
+# Avoid -O3 on Darwin, there are unresolved issues with
+# -fstrict-aliasing and ipa-type-escape radr://6756684
+ifeq ($(OS), $(filter $(OS), MingW Darwin))
   OPTIMIZE_OPTION := -O2
+else
+  OPTIMIZE_OPTION := -O3
 endif
 
 ifdef ENABLE_PROFILING




From sabre at nondot.org  Mon Apr  6 15:35:21 2009
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 06 Apr 2009 20:35:21 -0000
Subject: [llvm-commits] [llvm] r68456 - /llvm/trunk/docs/BitCodeFormat.html
Message-ID: <200904062035.n36KZLsK018209@zion.cs.uiuc.edu>

Author: lattner
Date: Mon Apr  6 15:35:19 2009
New Revision: 68456

URL: http://llvm.org/viewvc/llvm-project?rev=68456&view=rev
Log:
clean up some html

Modified:
    llvm/trunk/docs/BitCodeFormat.html

Modified: llvm/trunk/docs/BitCodeFormat.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/BitCodeFormat.html?rev=68456&r1=68455&r2=68456&view=diff

==============================================================================
--- llvm/trunk/docs/BitCodeFormat.html (original)
+++ llvm/trunk/docs/BitCodeFormat.html Mon Apr  6 15:35:19 2009
@@ -461,24 +461,24 @@
 
 <p>The possible operand encodings are:</p>
 
-<ul>
-<li>1 &mdash; Fixed &mdash; The field should be emitted as
+<ol>
+<li value="1">Fixed: The field should be emitted as
     a <a href="#fixedwidth">fixed-width value</a>, whose width is specified by
     the operand's extra data.</li>
-<li>2 &mdash; VBR &mdash; The field should be emitted as
+<li value="2">VBR: The field should be emitted as
     a <a href="#variablewidth">variable-width value</a>, whose width is
     specified by the operand's extra data.</li>
-<li>3 &mdash; Array &mdash; This field is an array of values.  The array operand
+<li value="3">Array: This field is an array of values.  The array operand
     has no extra data, but expects another operand to follow it which indicates
     the element type of the array.  When reading an array in an abbreviated
     record, the first integer is a vbr6 that indicates the array length,
     followed by the encoded elements of the array.  An array may only occur as
     the last operand of an abbreviation (except for the one final operand that
     gives the array's type).</li>
-<li>4 &mdash; Char6 &mdash; This field should be emitted as
+<li value="4">Char6: This field should be emitted as
     a <a href="#char6">char6-encoded value</a>.  This operand type takes no
     extra data.</li>
-</ul>
+</ol>
 
 <p>
 For example, target triples in LLVM modules are encoded as a record of the




From edwintorok at gmail.com  Mon Apr  6 15:49:21 2009
From: edwintorok at gmail.com (Torok Edwin)
Date: Mon, 06 Apr 2009 20:49:21 -0000
Subject: [llvm-commits] [llvm] r68457 - in /llvm/trunk:
 examples/HowToUseJIT/HowToUseJIT.cpp lib/VMCore/Type.cpp
Message-ID: <200904062049.n36KnMDn018714@zion.cs.uiuc.edu>

Author: edwin
Date: Mon Apr  6 15:49:21 2009
New Revision: 68457

URL: http://llvm.org/viewvc/llvm-project?rev=68457&view=rev
Log:
fix (part of) memory leak on shutdown. See PR2975.

Modified:
    llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp
    llvm/trunk/lib/VMCore/Type.cpp

Modified: llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp?rev=68457&r1=68456&r2=68457&view=diff

==============================================================================
--- llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp (original)
+++ llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp Mon Apr  6 15:49:21 2009
@@ -42,6 +42,7 @@
 #include "llvm/ExecutionEngine/JIT.h"
 #include "llvm/ExecutionEngine/Interpreter.h"
 #include "llvm/ExecutionEngine/GenericValue.h"
+#include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
@@ -109,5 +110,8 @@
 
   // Import result of execution:
   outs() << "Result: " << gv.IntVal << "\n";
+  EE->freeMachineCodeForFunction(FooF);
+  delete EE;
+  llvm_shutdown();
   return 0;
 }

Modified: llvm/trunk/lib/VMCore/Type.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Type.cpp?rev=68457&r1=68456&r2=68457&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/Type.cpp (original)
+++ llvm/trunk/lib/VMCore/Type.cpp Mon Apr  6 15:49:21 2009
@@ -666,6 +666,22 @@
   std::multimap<unsigned, PATypeHolder> TypesByHash;
 
 public:
+  ~TypeMapBase()
+  {
+    for (std::multimap<unsigned, PATypeHolder>::iterator I
+         = TypesByHash.begin(), E = TypesByHash.end(); I != E;) {
+      Type *Ty = I->second.get();
+      if (!Ty->isAbstract() && (isa<PointerType>(Ty) || isa<FunctionType>(Ty) ||
+                                isa<VectorType>(Ty))) {
+        TypesByHash.erase(I++);
+        // PATypeHolder won't destroy it, so we must
+        Ty->destroy();
+      }
+      else
+        ++I;
+    }
+  }
+
   void RemoveFromTypesByHash(unsigned Hash, const Type *Ty) {
     std::multimap<unsigned, PATypeHolder>::iterator I =
       TypesByHash.lower_bound(Hash);




From sabre at nondot.org  Mon Apr  6 15:54:32 2009
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 06 Apr 2009 20:54:32 -0000
Subject: [llvm-commits] [llvm] r68458 - in /llvm/trunk:
 include/llvm/Bitcode/ReaderWriter.h lib/Bitcode/Reader/BitcodeReader.cpp
 tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
Message-ID: <200904062054.n36KsWXj018907@zion.cs.uiuc.edu>

Author: lattner
Date: Mon Apr  6 15:54:32 2009
New Revision: 68458

URL: http://llvm.org/viewvc/llvm-project?rev=68458&view=rev
Log:
Teach llvm-bcanalyzer to skip over the header we use on LLVM IR files.

Modified:
    llvm/trunk/include/llvm/Bitcode/ReaderWriter.h
    llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
    llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp

Modified: llvm/trunk/include/llvm/Bitcode/ReaderWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/ReaderWriter.h?rev=68458&r1=68457&r2=68458&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Bitcode/ReaderWriter.h (original)
+++ llvm/trunk/include/llvm/Bitcode/ReaderWriter.h Mon Apr  6 15:54:32 2009
@@ -24,7 +24,7 @@
   class ModulePass;
   class BitstreamWriter;
   class raw_ostream;
-
+  
   /// getBitcodeModuleProvider - Read the header of the specified bitcode buffer
   /// and prepare for lazy deserialization of function bodies.  If successful,
   /// this takes ownership of 'buffer' and returns a non-null pointer.  On
@@ -57,6 +57,57 @@
   /// createBitcodeWriterPass - Create and return a pass that writes the module
   /// to the specified ostream.
   ModulePass *createBitcodeWriterPass(raw_ostream &Str);
+  
+  
+  /// isBitcodeWrapper - Return true fi this is a wrapper for LLVM IR bitcode
+  /// files.
+  static bool inline isBitcodeWrapper(unsigned char *BufPtr,
+                                      unsigned char *BufEnd) {
+    return (BufPtr != BufEnd && BufPtr[0] == 0xDE && BufPtr[1] == 0xC0 && 
+            BufPtr[2] == 0x17 && BufPtr[3] == 0x0B);
+  }
+  
+  /// SkipBitcodeWrapperHeader - Some systems wrap bc files with a special
+  /// header for padding or other reasons.  The format of this header is:
+  ///
+  /// struct bc_header {
+  ///   uint32_t Magic;         // 0x0B17C0DE
+  ///   uint32_t Version;       // Version, currently always 0.
+  ///   uint32_t BitcodeOffset; // Offset to traditional bitcode file.
+  ///   uint32_t BitcodeSize;   // Size of traditional bitcode file.
+  ///   ... potentially other gunk ...
+  /// };
+  /// 
+  /// This function is called when we find a file with a matching magic number.
+  /// In this case, skip down to the subsection of the file that is actually a
+  /// BC file.
+  static inline bool SkipBitcodeWrapperHeader(unsigned char *&BufPtr,
+                                              unsigned char *&BufEnd) {
+    enum {
+      KnownHeaderSize = 4*4,  // Size of header we read.
+      OffsetField = 2*4,      // Offset in bytes to Offset field.
+      SizeField = 3*4         // Offset in bytes to Size field.
+    };
+    
+    // Must contain the header!
+    if (BufEnd-BufPtr < KnownHeaderSize) return true;
+    
+    unsigned Offset = ( BufPtr[OffsetField  ]        |
+                       (BufPtr[OffsetField+1] << 8)  |
+                       (BufPtr[OffsetField+2] << 16) |
+                       (BufPtr[OffsetField+3] << 24));
+    unsigned Size   = ( BufPtr[SizeField    ]        |
+                       (BufPtr[SizeField  +1] << 8)  |
+                       (BufPtr[SizeField  +2] << 16) |
+                       (BufPtr[SizeField  +3] << 24));
+    
+    // Verify that Offset+Size fits in the file.
+    if (Offset+Size > unsigned(BufEnd-BufPtr))
+      return true;
+    BufPtr += Offset;
+    BufEnd = BufPtr+Size;
+    return false;
+  }
 } // End llvm namespace
 
 #endif

Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=68458&r1=68457&r2=68458&view=diff

==============================================================================
--- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original)
+++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Mon Apr  6 15:54:32 2009
@@ -1330,48 +1330,6 @@
   return Error("Premature end of bitstream");
 }
 
-/// SkipWrapperHeader - Some systems wrap bc files with a special header for
-/// padding or other reasons.  The format of this header is:
-///
-/// struct bc_header {
-///   uint32_t Magic;         // 0x0B17C0DE
-///   uint32_t Version;       // Version, currently always 0.
-///   uint32_t BitcodeOffset; // Offset to traditional bitcode file.
-///   uint32_t BitcodeSize;   // Size of traditional bitcode file.
-///   ... potentially other gunk ...
-/// };
-/// 
-/// This function is called when we find a file with a matching magic number.
-/// In this case, skip down to the subsection of the file that is actually a BC
-/// file.
-static bool SkipWrapperHeader(unsigned char *&BufPtr, unsigned char *&BufEnd) {
-  enum {
-    KnownHeaderSize = 4*4,  // Size of header we read.
-    OffsetField = 2*4,      // Offset in bytes to Offset field.
-    SizeField = 3*4         // Offset in bytes to Size field.
-  };
-  
-  
-  // Must contain the header!
-  if (BufEnd-BufPtr < KnownHeaderSize) return true;
-  
-  unsigned Offset = ( BufPtr[OffsetField  ]        |
-                     (BufPtr[OffsetField+1] << 8)  |
-                     (BufPtr[OffsetField+2] << 16) |
-                     (BufPtr[OffsetField+3] << 24));
-  unsigned Size   = ( BufPtr[SizeField    ]        |
-                     (BufPtr[SizeField  +1] << 8)  |
-                     (BufPtr[SizeField  +2] << 16) |
-                     (BufPtr[SizeField  +3] << 24));
-  
-  // Verify that Offset+Size fits in the file.
-  if (Offset+Size > unsigned(BufEnd-BufPtr))
-    return true;
-  BufPtr += Offset;
-  BufEnd = BufPtr+Size;
-  return false;
-}
-
 bool BitcodeReader::ParseBitcode() {
   TheModule = 0;
   
@@ -1383,9 +1341,8 @@
   
   // If we have a wrapper header, parse it and ignore the non-bc file contents.
   // The magic number is 0x0B17C0DE stored in little endian.
-  if (BufPtr != BufEnd && BufPtr[0] == 0xDE && BufPtr[1] == 0xC0 && 
-      BufPtr[2] == 0x17 && BufPtr[3] == 0x0B)
-    if (SkipWrapperHeader(BufPtr, BufEnd))
+  if (isBitcodeWrapper(BufPtr, BufEnd))
+    if (SkipBitcodeWrapperHeader(BufPtr, BufEnd))
       return Error("Invalid bitcode wrapper header");
   
   Stream.init(BufPtr, BufEnd);

Modified: llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp?rev=68458&r1=68457&r2=68458&view=diff

==============================================================================
--- llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp (original)
+++ llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Mon Apr  6 15:54:32 2009
@@ -30,6 +30,7 @@
 #include "llvm/Analysis/Verifier.h"
 #include "llvm/Bitcode/BitstreamReader.h"
 #include "llvm/Bitcode/LLVMBitCodes.h"
+#include "llvm/Bitcode/ReaderWriter.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/MemoryBuffer.h"
@@ -382,16 +383,24 @@
 /// AnalyzeBitcode - Analyze the bitcode file specified by InputFilename.
 static int AnalyzeBitcode() {
   // Read the input file.
-  MemoryBuffer *Buffer = MemoryBuffer::getFileOrSTDIN(InputFilename.c_str());
+  MemoryBuffer *MemBuf = MemoryBuffer::getFileOrSTDIN(InputFilename.c_str());
 
-  if (Buffer == 0)
+  if (MemBuf == 0)
     return Error("Error reading '" + InputFilename + "'.");
   
-  if (Buffer->getBufferSize() & 3)
+  if (MemBuf->getBufferSize() & 3)
     return Error("Bitcode stream should be a multiple of 4 bytes in length");
   
-  unsigned char *BufPtr = (unsigned char *)Buffer->getBufferStart();
-  BitstreamReader Stream(BufPtr, BufPtr+Buffer->getBufferSize());
+  unsigned char *BufPtr = (unsigned char *)MemBuf->getBufferStart();
+  unsigned char *EndBufPtr = BufPtr+MemBuf->getBufferSize();
+  
+  // If we have a wrapper header, parse it and ignore the non-bc file contents.
+  // The magic number is 0x0B17C0DE stored in little endian.
+  if (isBitcodeWrapper(BufPtr, EndBufPtr))
+    if (SkipBitcodeWrapperHeader(BufPtr, EndBufPtr))
+      return Error("Invalid bitcode wrapper header");
+  
+  BitstreamReader Stream(BufPtr, EndBufPtr);
 
   
   // Read the stream signature.
@@ -425,7 +434,7 @@
   
   if (Dump) std::cerr << "\n\n";
   
-  uint64_t BufferSizeBits = Buffer->getBufferSize()*CHAR_BIT;
+  uint64_t BufferSizeBits = (EndBufPtr-BufPtr)*CHAR_BIT;
   // Print a summary of the read file.
   std::cerr << "Summary of " << InputFilename << ":\n";
   std::cerr << "         Total size: ";




From edwintorok at gmail.com  Mon Apr  6 15:57:34 2009
From: edwintorok at gmail.com (Torok Edwin)
Date: Mon, 06 Apr 2009 20:57:34 -0000
Subject: [llvm-commits] [llvm] r68459 - in /llvm/trunk:
 examples/HowToUseJIT/HowToUseJIT.cpp lib/VMCore/Type.cpp
Message-ID: <200904062057.n36KvZjD018998@zion.cs.uiuc.edu>

Author: edwin
Date: Mon Apr  6 15:57:34 2009
New Revision: 68459

URL: http://llvm.org/viewvc/llvm-project?rev=68459&view=rev
Log:
revert r68457, its crashing in make check.

Modified:
    llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp
    llvm/trunk/lib/VMCore/Type.cpp

Modified: llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp?rev=68459&r1=68458&r2=68459&view=diff

==============================================================================
--- llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp (original)
+++ llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp Mon Apr  6 15:57:34 2009
@@ -42,7 +42,6 @@
 #include "llvm/ExecutionEngine/JIT.h"
 #include "llvm/ExecutionEngine/Interpreter.h"
 #include "llvm/ExecutionEngine/GenericValue.h"
-#include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
@@ -110,8 +109,5 @@
 
   // Import result of execution:
   outs() << "Result: " << gv.IntVal << "\n";
-  EE->freeMachineCodeForFunction(FooF);
-  delete EE;
-  llvm_shutdown();
   return 0;
 }

Modified: llvm/trunk/lib/VMCore/Type.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Type.cpp?rev=68459&r1=68458&r2=68459&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/Type.cpp (original)
+++ llvm/trunk/lib/VMCore/Type.cpp Mon Apr  6 15:57:34 2009
@@ -666,22 +666,6 @@
   std::multimap<unsigned, PATypeHolder> TypesByHash;
 
 public:
-  ~TypeMapBase()
-  {
-    for (std::multimap<unsigned, PATypeHolder>::iterator I
-         = TypesByHash.begin(), E = TypesByHash.end(); I != E;) {
-      Type *Ty = I->second.get();
-      if (!Ty->isAbstract() && (isa<PointerType>(Ty) || isa<FunctionType>(Ty) ||
-                                isa<VectorType>(Ty))) {
-        TypesByHash.erase(I++);
-        // PATypeHolder won't destroy it, so we must
-        Ty->destroy();
-      }
-      else
-        ++I;
-    }
-  }
-
   void RemoveFromTypesByHash(unsigned Hash, const Type *Ty) {
     std::multimap<unsigned, PATypeHolder>::iterator I =
       TypesByHash.lower_bound(Hash);




From sabre at nondot.org  Mon Apr  6 16:12:29 2009
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 06 Apr 2009 21:12:29 -0000
Subject: [llvm-commits] [llvm] r68460 -
	/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
Message-ID: <200904062112.n36LCTiX019618@zion.cs.uiuc.edu>

Author: lattner
Date: Mon Apr  6 16:12:29 2009
New Revision: 68460

URL: http://llvm.org/viewvc/llvm-project?rev=68460&view=rev
Log:
simplify to reduce indentation.

Modified:
    llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h

Modified: llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h?rev=68460&r1=68459&r2=68460&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h (original)
+++ llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h Mon Apr  6 16:12:29 2009
@@ -285,39 +285,7 @@
   template<typename uintty>
   void EmitRecord(unsigned Code, SmallVectorImpl<uintty> &Vals,
                   unsigned Abbrev = 0) {
-    if (Abbrev) {
-      unsigned AbbrevNo = Abbrev-bitc::FIRST_APPLICATION_ABBREV;
-      assert(AbbrevNo < CurAbbrevs.size() && "Invalid abbrev #!");
-      BitCodeAbbrev *Abbv = CurAbbrevs[AbbrevNo];
-
-      EmitCode(Abbrev);
-
-      // Insert the code into Vals to treat it uniformly.
-      Vals.insert(Vals.begin(), Code);
-
-      unsigned RecordIdx = 0;
-      for (unsigned i = 0, e = static_cast<unsigned>(Abbv->getNumOperandInfos());
-           i != e; ++i) {
-        const BitCodeAbbrevOp &Op = Abbv->getOperandInfo(i);
-        if (Op.isLiteral() || Op.getEncoding() != BitCodeAbbrevOp::Array) {
-          assert(RecordIdx < Vals.size() && "Invalid abbrev/record");
-          EmitAbbreviatedField(Op, Vals[RecordIdx]);
-          ++RecordIdx;
-        } else {
-          // Array case.
-          assert(i+2 == e && "array op not second to last?");
-          const BitCodeAbbrevOp &EltEnc = Abbv->getOperandInfo(++i);
-
-          // Emit a vbr6 to indicate the number of elements present.
-          EmitVBR(static_cast<uint32_t>(Vals.size()-RecordIdx), 6);
-
-          // Emit each field.
-          for (; RecordIdx != Vals.size(); ++RecordIdx)
-            EmitAbbreviatedField(EltEnc, Vals[RecordIdx]);
-        }
-      }
-      assert(RecordIdx == Vals.size() && "Not all record operands emitted!");
-    } else {
+    if (!Abbrev) {
       // If we don't have an abbrev to use, emit this in its fully unabbreviated
       // form.
       EmitCode(bitc::UNABBREV_RECORD);
@@ -325,7 +293,40 @@
       EmitVBR(static_cast<uint32_t>(Vals.size()), 6);
       for (unsigned i = 0, e = static_cast<unsigned>(Vals.size()); i != e; ++i)
         EmitVBR64(Vals[i], 6);
+      return;
+    }
+    
+    unsigned AbbrevNo = Abbrev-bitc::FIRST_APPLICATION_ABBREV;
+    assert(AbbrevNo < CurAbbrevs.size() && "Invalid abbrev #!");
+    BitCodeAbbrev *Abbv = CurAbbrevs[AbbrevNo];
+
+    EmitCode(Abbrev);
+
+    // Insert the code into Vals to treat it uniformly.
+    Vals.insert(Vals.begin(), Code);
+
+    unsigned RecordIdx = 0;
+    for (unsigned i = 0, e = static_cast<unsigned>(Abbv->getNumOperandInfos());
+         i != e; ++i) {
+      const BitCodeAbbrevOp &Op = Abbv->getOperandInfo(i);
+      if (Op.isLiteral() || Op.getEncoding() != BitCodeAbbrevOp::Array) {
+        assert(RecordIdx < Vals.size() && "Invalid abbrev/record");
+        EmitAbbreviatedField(Op, Vals[RecordIdx]);
+        ++RecordIdx;
+      } else {
+        // Array case.
+        assert(i+2 == e && "array op not second to last?");
+        const BitCodeAbbrevOp &EltEnc = Abbv->getOperandInfo(++i);
+
+        // Emit a vbr6 to indicate the number of elements present.
+        EmitVBR(static_cast<uint32_t>(Vals.size()-RecordIdx), 6);
+
+        // Emit each field.
+        for (; RecordIdx != Vals.size(); ++RecordIdx)
+          EmitAbbreviatedField(EltEnc, Vals[RecordIdx]);
+      }
     }
+    assert(RecordIdx == Vals.size() && "Not all record operands emitted!");
   }
 
   //===--------------------------------------------------------------------===//




From sabre at nondot.org  Mon Apr  6 16:20:02 2009
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 06 Apr 2009 21:20:02 -0000
Subject: [llvm-commits] [llvm] r68461 -
	/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
Message-ID: <200904062120.n36LK2KB019967@zion.cs.uiuc.edu>

Author: lattner
Date: Mon Apr  6 16:20:01 2009
New Revision: 68461

URL: http://llvm.org/viewvc/llvm-project?rev=68461&view=rev
Log:
simplify code a bit.

Modified:
    llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h

Modified: llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h?rev=68461&r1=68460&r2=68461&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h (original)
+++ llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h Mon Apr  6 16:20:01 2009
@@ -252,18 +252,23 @@
   //===--------------------------------------------------------------------===//
 
 private:
+  /// EmitAbbreviatedLiteral - Emit a literal value according to its abbrev
+  /// record.  This is a no-op, since the abbrev specifies the literal to use. 
+  template<typename uintty>
+  void EmitAbbreviatedLiteral(const BitCodeAbbrevOp &Op, uintty V) {
+    assert(Op.isLiteral() && "Not a literal");
+    // If the abbrev specifies the literal value to use, don't emit
+    // anything.
+    assert(V == Op.getLiteralValue() &&
+           "Invalid abbrev for record!");
+  }
+  
   /// EmitAbbreviatedField - Emit a single scalar field value with the specified
   /// encoding.
   template<typename uintty>
   void EmitAbbreviatedField(const BitCodeAbbrevOp &Op, uintty V) {
-    if (Op.isLiteral()) {
-      // If the abbrev specifies the literal value to use, don't emit
-      // anything.
-      assert(V == Op.getLiteralValue() &&
-             "Invalid abbrev for record!");
-      return;
-    }
-
+    assert(!Op.isLiteral() && "Literals should use EmitAbbreviatedLiteral!");
+    
     // Encode the value as we are commanded.
     switch (Op.getEncoding()) {
     default: assert(0 && "Unknown encoding!");
@@ -278,6 +283,7 @@
       break;
     }
   }
+  
 public:
 
   /// EmitRecord - Emit the specified record to the stream, using an abbrev if
@@ -309,7 +315,11 @@
     for (unsigned i = 0, e = static_cast<unsigned>(Abbv->getNumOperandInfos());
          i != e; ++i) {
       const BitCodeAbbrevOp &Op = Abbv->getOperandInfo(i);
-      if (Op.isLiteral() || Op.getEncoding() != BitCodeAbbrevOp::Array) {
+      if (Op.isLiteral()) {
+        assert(RecordIdx < Vals.size() && "Invalid abbrev/record");
+        EmitAbbreviatedLiteral(Op, Vals[RecordIdx]);
+        ++RecordIdx;
+      } else if (Op.getEncoding() != BitCodeAbbrevOp::Array) {
         assert(RecordIdx < Vals.size() && "Invalid abbrev/record");
         EmitAbbreviatedField(Op, Vals[RecordIdx]);
         ++RecordIdx;




From sabre at nondot.org  Mon Apr  6 16:34:59 2009
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 06 Apr 2009 21:34:59 -0000
Subject: [llvm-commits] [llvm] r68462 -
	/llvm/trunk/include/llvm/Bitcode/BitstreamReader.h
Message-ID: <200904062134.n36LYxVm020536@zion.cs.uiuc.edu>

Author: lattner
Date: Mon Apr  6 16:34:58 2009
New Revision: 68462

URL: http://llvm.org/viewvc/llvm-project?rev=68462&view=rev
Log:
reduce indentation with early-out

Modified:
    llvm/trunk/include/llvm/Bitcode/BitstreamReader.h

Modified: llvm/trunk/include/llvm/Bitcode/BitstreamReader.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitstreamReader.h?rev=68462&r1=68461&r2=68462&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Bitcode/BitstreamReader.h (original)
+++ llvm/trunk/include/llvm/Bitcode/BitstreamReader.h Mon Apr  6 16:34:58 2009
@@ -342,20 +342,20 @@
     if (Op.isLiteral()) {
       // If the abbrev specifies the literal value to use, use it.
       Vals.push_back(Op.getLiteralValue());
-    } else {
-      // Decode the value as we are commanded.
-      switch (Op.getEncoding()) {
-      default: assert(0 && "Unknown encoding!");
-      case BitCodeAbbrevOp::Fixed:
-        Vals.push_back(Read((unsigned)Op.getEncodingData()));
-        break;
-      case BitCodeAbbrevOp::VBR:
-        Vals.push_back(ReadVBR64((unsigned)Op.getEncodingData()));
-        break;
-      case BitCodeAbbrevOp::Char6:
-        Vals.push_back(BitCodeAbbrevOp::DecodeChar6(Read(6)));
-        break;
-      }
+      return;
+    }
+    // Decode the value as we are commanded.
+    switch (Op.getEncoding()) {
+    default: assert(0 && "Unknown encoding!");
+    case BitCodeAbbrevOp::Fixed:
+      Vals.push_back(Read((unsigned)Op.getEncodingData()));
+      break;
+    case BitCodeAbbrevOp::VBR:
+      Vals.push_back(ReadVBR64((unsigned)Op.getEncodingData()));
+      break;
+    case BitCodeAbbrevOp::Char6:
+      Vals.push_back(BitCodeAbbrevOp::DecodeChar6(Read(6)));
+      break;
     }
   }
 public:




From sabre at nondot.org  Mon Apr  6 16:37:10 2009
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 06 Apr 2009 21:37:10 -0000
Subject: [llvm-commits] [llvm] r68463 -
	/llvm/trunk/include/llvm/Bitcode/BitstreamReader.h
Message-ID: <200904062137.n36LbBJX020620@zion.cs.uiuc.edu>

Author: lattner
Date: Mon Apr  6 16:37:10 2009
New Revision: 68463

URL: http://llvm.org/viewvc/llvm-project?rev=68463&view=rev
Log:
split ReadAbbreviatedLiteral out of ReadAbbreviatedField.

Modified:
    llvm/trunk/include/llvm/Bitcode/BitstreamReader.h

Modified: llvm/trunk/include/llvm/Bitcode/BitstreamReader.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitstreamReader.h?rev=68463&r1=68462&r2=68463&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Bitcode/BitstreamReader.h (original)
+++ llvm/trunk/include/llvm/Bitcode/BitstreamReader.h Mon Apr  6 16:37:10 2009
@@ -337,13 +337,17 @@
   //===--------------------------------------------------------------------===//
 
 private:
+  void ReadAbbreviatedLiteral(const BitCodeAbbrevOp &Op,
+                              SmallVectorImpl<uint64_t> &Vals) {
+    assert(Op.isLiteral() && "Not a literal");
+    // If the abbrev specifies the literal value to use, use it.
+    Vals.push_back(Op.getLiteralValue());
+  }
+  
   void ReadAbbreviatedField(const BitCodeAbbrevOp &Op,
                             SmallVectorImpl<uint64_t> &Vals) {
-    if (Op.isLiteral()) {
-      // If the abbrev specifies the literal value to use, use it.
-      Vals.push_back(Op.getLiteralValue());
-      return;
-    }
+    assert(!Op.isLiteral() && "Use ReadAbbreviatedLiteral for literals!");
+    
     // Decode the value as we are commanded.
     switch (Op.getEncoding()) {
     default: assert(0 && "Unknown encoding!");
@@ -374,7 +378,9 @@
 
     for (unsigned i = 0, e = Abbv->getNumOperandInfos(); i != e; ++i) {
       const BitCodeAbbrevOp &Op = Abbv->getOperandInfo(i);
-      if (Op.isLiteral() || Op.getEncoding() != BitCodeAbbrevOp::Array) {
+      if (Op.isLiteral()) {
+        ReadAbbreviatedLiteral(Op, Vals); 
+      } else if (Op.getEncoding() != BitCodeAbbrevOp::Array) {
         ReadAbbreviatedField(Op, Vals);
       } else {
         // Array case.  Read the number of elements as a vbr6.




From bob.wilson at apple.com  Mon Apr  6 16:46:51 2009
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 06 Apr 2009 21:46:51 -0000
Subject: [llvm-commits] [llvm] r68464 - in /llvm/trunk:
 lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
 test/CodeGen/ARM/2009-04-06-AsmModifier.ll
Message-ID: <200904062146.n36Lkpv2021018@zion.cs.uiuc.edu>

Author: bwilson
Date: Mon Apr  6 16:46:51 2009
New Revision: 68464

URL: http://llvm.org/viewvc/llvm-project?rev=68464&view=rev
Log:
Handle 'a' modifier in ARM inline assembly.
Patch by Richard Pennington.

Added:
    llvm/trunk/test/CodeGen/ARM/2009-04-06-AsmModifier.ll
Modified:
    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=68464&r1=68463&r2=68464&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Mon Apr  6 16:46:51 2009
@@ -739,7 +739,10 @@
     
     switch (ExtraCode[0]) {
     default: return true;  // Unknown modifier.
+    case 'a': // Don't print "#" before a global var name or constant.
     case 'c': // Don't print "$" before a global var name or constant.
+      printOperand(MI, OpNo, "no_hash");
+      return false;
     case 'P': // Print a VFP double precision register.
       printOperand(MI, OpNo);
       return false;

Added: llvm/trunk/test/CodeGen/ARM/2009-04-06-AsmModifier.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-04-06-AsmModifier.ll?rev=68464&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-04-06-AsmModifier.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2009-04-06-AsmModifier.ll Mon Apr  6 16:46:51 2009
@@ -0,0 +1,19 @@
+; RUN: llvm-as < %s | llc -march=arm | grep {swi 107}
+
+define i32 @_swilseek(i32) nounwind {
+entry:
+	%ptr = alloca i32		; <i32*> [#uses=2]
+	store i32 %0, i32* %ptr
+	%retval = alloca i32		; <i32*> [#uses=2]
+	store i32 0, i32* %retval
+	%res = alloca i32		; <i32*> [#uses=0]
+	%fh = alloca i32		; <i32*> [#uses=1]
+	%1 = load i32* %fh		; <i32> [#uses=1]
+	%2 = load i32* %ptr		; <i32> [#uses=1]
+	%3 = call i32* asm "mov r0, $2; mov r1, $3; swi ${1:a}; mov $0, r0", "=r,i,r,r,~{r0},~{r1}"(i32 107, i32 %1, i32 %2) nounwind		; <i32*> [#uses=0]
+	br label %return
+
+return:		; preds = %entry
+	%4 = load i32* %retval		; <i32> [#uses=1]
+	ret i32 %4
+}




From sabre at nondot.org  Mon Apr  6 16:50:40 2009
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 06 Apr 2009 21:50:40 -0000
Subject: [llvm-commits] [llvm] r68465 - in /llvm/trunk:
 docs/BitCodeFormat.html include/llvm/Bitcode/BitCodes.h
 include/llvm/Bitcode/BitstreamReader.h
 include/llvm/Bitcode/BitstreamWriter.h
Message-ID: <200904062150.n36LoeCY021210@zion.cs.uiuc.edu>

Author: lattner
Date: Mon Apr  6 16:50:39 2009
New Revision: 68465

URL: http://llvm.org/viewvc/llvm-project?rev=68465&view=rev
Log:
add a new Blob encoding abbreviation for bitcode files that emits
elements in a form that is efficient for the reader to just get a
pointer in memory and start reading.  APIs to do efficient reading
and writing are still todo.

Modified:
    llvm/trunk/docs/BitCodeFormat.html
    llvm/trunk/include/llvm/Bitcode/BitCodes.h
    llvm/trunk/include/llvm/Bitcode/BitstreamReader.h
    llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h

Modified: llvm/trunk/docs/BitCodeFormat.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/BitCodeFormat.html?rev=68465&r1=68464&r2=68465&view=diff

==============================================================================
--- llvm/trunk/docs/BitCodeFormat.html (original)
+++ llvm/trunk/docs/BitCodeFormat.html Mon Apr  6 16:50:39 2009
@@ -478,6 +478,13 @@
 <li value="4">Char6: This field should be emitted as
     a <a href="#char6">char6-encoded value</a>.  This operand type takes no
     extra data.</li>
+<li value="5">Blob: This field is emitted as a vbr6, followed by padding to a
+    32-bit boundary (for alignment) and an array of 8-bit objects.  The array of
+    bytes is further followed by tail padding to ensure that its total length is
+    a multiple of 4 bytes.  This makes it very efficient for the reader to
+    decode the data without having to make a copy of it: it can use a pointer to
+    the data in the mapped in file and poke directly at it.  A blob may only
+    occur as the last operand of an abbreviation.</li>
 </ol>
 
 <p>

Modified: llvm/trunk/include/llvm/Bitcode/BitCodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitCodes.h?rev=68465&r1=68464&r2=68465&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Bitcode/BitCodes.h (original)
+++ llvm/trunk/include/llvm/Bitcode/BitCodes.h Mon Apr  6 16:50:39 2009
@@ -88,7 +88,8 @@
     Fixed = 1,  // A fixed width field, Val specifies number of bits.
     VBR   = 2,  // A VBR field where Val specifies the width of each chunk.
     Array = 3,  // A sequence of fields, next field species elt encoding.
-    Char6 = 4   // A 6-bit fixed field which maps to [a-zA-Z0-9._].
+    Char6 = 4,  // A 6-bit fixed field which maps to [a-zA-Z0-9._].
+    Blob  = 5   // 8-bit aligned array of 8-bit characters.
   };
 
   explicit BitCodeAbbrevOp(uint64_t V) :  Val(V), IsLiteral(true) {}
@@ -117,6 +118,7 @@
       return true;
     case Array:
     case Char6:
+    case Blob:
       return false;
     }
   }

Modified: llvm/trunk/include/llvm/Bitcode/BitstreamReader.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitstreamReader.h?rev=68465&r1=68464&r2=68465&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Bitcode/BitstreamReader.h (original)
+++ llvm/trunk/include/llvm/Bitcode/BitstreamReader.h Mon Apr  6 16:50:39 2009
@@ -149,7 +149,7 @@
     }
 
     // If we run out of data, stop at the end of the stream.
-    if (LastChar == NextChar) {
+    if (NextChar == LastChar) {
       CurWord = 0;
       BitsInCurWord = 0;
       return 0;
@@ -380,9 +380,7 @@
       const BitCodeAbbrevOp &Op = Abbv->getOperandInfo(i);
       if (Op.isLiteral()) {
         ReadAbbreviatedLiteral(Op, Vals); 
-      } else if (Op.getEncoding() != BitCodeAbbrevOp::Array) {
-        ReadAbbreviatedField(Op, Vals);
-      } else {
+      } else if (Op.getEncoding() == BitCodeAbbrevOp::Array) {
         // Array case.  Read the number of elements as a vbr6.
         unsigned NumElts = ReadVBR(6);
 
@@ -393,6 +391,29 @@
         // Read all the elements.
         for (; NumElts; --NumElts)
           ReadAbbreviatedField(EltEnc, Vals);
+      } else if (Op.getEncoding() == BitCodeAbbrevOp::Blob) {
+        // Blob case.  Read the number of bytes as a vbr6.
+        unsigned NumElts = ReadVBR(6);
+        SkipToWord();  // 32-bit alignment
+
+        // Figure out where the end of this blob will be including tail padding.
+        const unsigned char *NewEnd = NextChar+((NumElts+3)&~3);
+        
+        // If this would read off the end of the bitcode file, just set the
+        // record to empty and return.
+        if (NewEnd > LastChar) {
+          Vals.append(NumElts, 0);
+          NextChar = LastChar;
+          break;
+        }
+        
+        // Otherwise, read the number of bytes.
+        for (; NumElts; ++NextChar, --NumElts)
+          Vals.push_back(*NextChar);
+        // Skip over tail padding.
+        NextChar = NewEnd;
+      } else {
+        ReadAbbreviatedField(Op, Vals);
       }
     }
 

Modified: llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h?rev=68465&r1=68464&r2=68465&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h (original)
+++ llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h Mon Apr  6 16:50:39 2009
@@ -319,11 +319,7 @@
         assert(RecordIdx < Vals.size() && "Invalid abbrev/record");
         EmitAbbreviatedLiteral(Op, Vals[RecordIdx]);
         ++RecordIdx;
-      } else if (Op.getEncoding() != BitCodeAbbrevOp::Array) {
-        assert(RecordIdx < Vals.size() && "Invalid abbrev/record");
-        EmitAbbreviatedField(Op, Vals[RecordIdx]);
-        ++RecordIdx;
-      } else {
+      } else if (Op.getEncoding() == BitCodeAbbrevOp::Array) {
         // Array case.
         assert(i+2 == e && "array op not second to last?");
         const BitCodeAbbrevOp &EltEnc = Abbv->getOperandInfo(++i);
@@ -334,6 +330,26 @@
         // Emit each field.
         for (; RecordIdx != Vals.size(); ++RecordIdx)
           EmitAbbreviatedField(EltEnc, Vals[RecordIdx]);
+      } else if (Op.getEncoding() == BitCodeAbbrevOp::Blob) {
+        // Emit a vbr6 to indicate the number of elements present.
+        EmitVBR(static_cast<uint32_t>(Vals.size()-RecordIdx), 6);
+        // Flush to a 32-bit alignment boundary.
+        FlushToWord();
+        assert((Out.size() & 3) == 0 && "Not 32-bit aligned");
+
+        // Emit each field as a literal byte.
+        for (; RecordIdx != Vals.size(); ++RecordIdx) {
+          assert(Vals[RecordIdx] < 256 && "Value too large to emit as blob");
+          Out.push_back((unsigned char)Vals[RecordIdx]);
+        }
+        // Align end to 32-bits.
+        while (Out.size() & 3)
+          Out.push_back(0);
+        
+      } else {  // Single scalar field.
+        assert(RecordIdx < Vals.size() && "Invalid abbrev/record");
+        EmitAbbreviatedField(Op, Vals[RecordIdx]);
+        ++RecordIdx;
       }
     }
     assert(RecordIdx == Vals.size() && "Not all record operands emitted!");




From sabre at nondot.org  Mon Apr  6 17:26:26 2009
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 06 Apr 2009 22:26:26 -0000
Subject: [llvm-commits] [llvm] r68469 -
	/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
Message-ID: <200904062226.n36MQQpH022512@zion.cs.uiuc.edu>

Author: lattner
Date: Mon Apr  6 17:26:26 2009
New Revision: 68469

URL: http://llvm.org/viewvc/llvm-project?rev=68469&view=rev
Log:
Add a new EmitRecordWithBlob API that allows a blob to be emitted 
without converting each byte to a uint64_t to stick in a SmallVector.

Modified:
    llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h

Modified: llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h?rev=68469&r1=68468&r2=68469&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h (original)
+++ llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h Mon Apr  6 17:26:26 2009
@@ -284,33 +284,19 @@
     }
   }
   
-public:
-
-  /// EmitRecord - Emit the specified record to the stream, using an abbrev if
-  /// we have one to compress the output.
+  /// EmitRecordWithAbbrevImpl - This is the core implementation of the record
+  /// emission code.  If BlobData is non-null, then it specifies an array of
+  /// data that should be emitted as part of the Blob or Array operand that is
+  /// known to exist at the end of the the record.
   template<typename uintty>
-  void EmitRecord(unsigned Code, SmallVectorImpl<uintty> &Vals,
-                  unsigned Abbrev = 0) {
-    if (!Abbrev) {
-      // If we don't have an abbrev to use, emit this in its fully unabbreviated
-      // form.
-      EmitCode(bitc::UNABBREV_RECORD);
-      EmitVBR(Code, 6);
-      EmitVBR(static_cast<uint32_t>(Vals.size()), 6);
-      for (unsigned i = 0, e = static_cast<unsigned>(Vals.size()); i != e; ++i)
-        EmitVBR64(Vals[i], 6);
-      return;
-    }
-    
+  void EmitRecordWithAbbrevImpl(unsigned Abbrev, SmallVectorImpl<uintty> &Vals,
+                                const char *BlobData, unsigned BlobLen) {
     unsigned AbbrevNo = Abbrev-bitc::FIRST_APPLICATION_ABBREV;
     assert(AbbrevNo < CurAbbrevs.size() && "Invalid abbrev #!");
     BitCodeAbbrev *Abbv = CurAbbrevs[AbbrevNo];
 
     EmitCode(Abbrev);
 
-    // Insert the code into Vals to treat it uniformly.
-    Vals.insert(Vals.begin(), Code);
-
     unsigned RecordIdx = 0;
     for (unsigned i = 0, e = static_cast<unsigned>(Abbv->getNumOperandInfos());
          i != e; ++i) {
@@ -324,23 +310,57 @@
         assert(i+2 == e && "array op not second to last?");
         const BitCodeAbbrevOp &EltEnc = Abbv->getOperandInfo(++i);
 
-        // Emit a vbr6 to indicate the number of elements present.
-        EmitVBR(static_cast<uint32_t>(Vals.size()-RecordIdx), 6);
-
-        // Emit each field.
-        for (; RecordIdx != Vals.size(); ++RecordIdx)
-          EmitAbbreviatedField(EltEnc, Vals[RecordIdx]);
+        // If this record has blob data, emit it, otherwise we must have record
+        // entries to encode this way.
+        if (BlobData) {
+          assert(RecordIdx == Vals.size() &&
+                 "Blob data and record entries specified for array!");
+          // Emit a vbr6 to indicate the number of elements present.
+          EmitVBR(static_cast<uint32_t>(BlobLen), 6);
+          
+          // Emit each field.
+          for (unsigned i = 0; i != BlobLen; ++i)
+            EmitAbbreviatedField(EltEnc, (unsigned char)BlobData[i]);
+          
+          // Know that blob data is consumed for assertion below.
+          BlobData = 0;
+        } else {
+          // Emit a vbr6 to indicate the number of elements present.
+          EmitVBR(static_cast<uint32_t>(Vals.size()-RecordIdx), 6);
+
+          // Emit each field.
+          for (unsigned e = Vals.size(); RecordIdx != e; ++RecordIdx)
+            EmitAbbreviatedField(EltEnc, Vals[RecordIdx]);
+        }
       } else if (Op.getEncoding() == BitCodeAbbrevOp::Blob) {
+        // If this record has blob data, emit it, otherwise we must have record
+        // entries to encode this way.
+        
         // Emit a vbr6 to indicate the number of elements present.
-        EmitVBR(static_cast<uint32_t>(Vals.size()-RecordIdx), 6);
+        if (BlobData) {
+          EmitVBR(static_cast<uint32_t>(BlobLen), 6);
+          assert(RecordIdx == Vals.size() &&
+                 "Blob data and record entries specified for blob operand!");
+        } else {
+          EmitVBR(static_cast<uint32_t>(Vals.size()-RecordIdx), 6);
+        }
+        
         // Flush to a 32-bit alignment boundary.
         FlushToWord();
         assert((Out.size() & 3) == 0 && "Not 32-bit aligned");
 
         // Emit each field as a literal byte.
-        for (; RecordIdx != Vals.size(); ++RecordIdx) {
-          assert(Vals[RecordIdx] < 256 && "Value too large to emit as blob");
-          Out.push_back((unsigned char)Vals[RecordIdx]);
+        if (BlobData) {
+          for (unsigned i = 0; i != BlobLen; ++i)
+            Out.push_back((unsigned char)BlobData[i]);
+          
+          // Know that blob data is consumed for assertion below.
+          BlobData = 0;
+        } else {
+          for (unsigned e = Vals.size(); RecordIdx != e; ++RecordIdx) {
+            assert(Vals[RecordIdx] < 256 && "Value too large to emit as blob");
+            Out.push_back((unsigned char)Vals[RecordIdx]);
+          }
         }
         // Align end to 32-bits.
         while (Out.size() & 3)
@@ -353,8 +373,61 @@
       }
     }
     assert(RecordIdx == Vals.size() && "Not all record operands emitted!");
+    assert(BlobData == 0 &&
+           "Blob data specified for record that doesn't use it!");
+  }
+  
+public:
+
+  /// EmitRecord - Emit the specified record to the stream, using an abbrev if
+  /// we have one to compress the output.
+  template<typename uintty>
+  void EmitRecord(unsigned Code, SmallVectorImpl<uintty> &Vals,
+                  unsigned Abbrev = 0) {
+    if (!Abbrev) {
+      // If we don't have an abbrev to use, emit this in its fully unabbreviated
+      // form.
+      EmitCode(bitc::UNABBREV_RECORD);
+      EmitVBR(Code, 6);
+      EmitVBR(static_cast<uint32_t>(Vals.size()), 6);
+      for (unsigned i = 0, e = static_cast<unsigned>(Vals.size()); i != e; ++i)
+        EmitVBR64(Vals[i], 6);
+      return;
+    }
+
+    // Insert the code into Vals to treat it uniformly.
+    Vals.insert(Vals.begin(), Code);
+    
+    EmitRecordWithAbbrev(Abbrev, Vals);
+  }
+  
+  /// EmitRecordWithAbbrev - Emit a record with the specified abbreviation.
+  /// Unlike EmitRecord, the code for the record should be included in Vals as
+  /// the first entry.
+  template<typename uintty>
+  void EmitRecordWithAbbrev(unsigned Abbrev, SmallVectorImpl<uintty> &Vals) {
+    EmitRecordWithAbbrevImpl(Abbrev, Vals, 0, 0);
+  }
+  
+  /// EmitRecordWithBlob - Emit the specified record to the stream, using an
+  /// abbrev that includes a blob at the end.  The blob data to emit is
+  /// specified by the pointer and length specified at the end.  In contrast to
+  /// EmitRecord, this routine expects that the first entry in Vals is the code
+  /// of the record.
+  template<typename uintty>
+  void EmitRecordWithBlob(unsigned Abbrev, SmallVectorImpl<uintty> &Vals,
+                          const char *BlobData, unsigned BlobLen) {
+    EmitRecordWithAbbrevImpl(Abbrev, Vals, BlobData, BlobLen);
   }
 
+  /// EmitRecordWithArray - Just like EmitRecordWithBlob, works with records
+  /// that end with an array.
+  template<typename uintty>
+  void EmitRecordWithArray(unsigned Abbrev, SmallVectorImpl<uintty> &Vals,
+                          const char *ArrayData, unsigned ArrayLen) {
+    EmitRecordWithAbbrevImpl(Abbrev, Vals, ArrayData, ArrayLen);
+  }
+  
   //===--------------------------------------------------------------------===//
   // Abbrev Emission
   //===--------------------------------------------------------------------===//




From sabre at nondot.org  Mon Apr  6 17:43:46 2009
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 06 Apr 2009 22:43:46 -0000
Subject: [llvm-commits] [llvm] r68471 -
	/llvm/trunk/include/llvm/Bitcode/BitstreamReader.h
Message-ID: <200904062243.n36MhkX5023209@zion.cs.uiuc.edu>

Author: lattner
Date: Mon Apr  6 17:43:46 2009
New Revision: 68471

URL: http://llvm.org/viewvc/llvm-project?rev=68471&view=rev
Log:
allow clients to look up abbrev id's

Modified:
    llvm/trunk/include/llvm/Bitcode/BitstreamReader.h

Modified: llvm/trunk/include/llvm/Bitcode/BitstreamReader.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitstreamReader.h?rev=68471&r1=68470&r2=68471&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Bitcode/BitstreamReader.h (original)
+++ llvm/trunk/include/llvm/Bitcode/BitstreamReader.h Mon Apr  6 17:43:46 2009
@@ -363,6 +363,14 @@
     }
   }
 public:
+
+  /// getAbbrev - Return the abbreviation for the specified AbbrevId. 
+  const BitCodeAbbrev *getAbbrev(unsigned AbbrevID) {
+    unsigned AbbrevNo = AbbrevID-bitc::FIRST_APPLICATION_ABBREV;
+    assert(AbbrevNo < CurAbbrevs.size() && "Invalid abbrev #!");
+    return CurAbbrevs[AbbrevNo];
+  }
+  
   unsigned ReadRecord(unsigned AbbrevID, SmallVectorImpl<uint64_t> &Vals) {
     if (AbbrevID == bitc::UNABBREV_RECORD) {
       unsigned Code = ReadVBR(6);
@@ -372,9 +380,7 @@
       return Code;
     }
 
-    unsigned AbbrevNo = AbbrevID-bitc::FIRST_APPLICATION_ABBREV;
-    assert(AbbrevNo < CurAbbrevs.size() && "Invalid abbrev #!");
-    BitCodeAbbrev *Abbv = CurAbbrevs[AbbrevNo];
+    const BitCodeAbbrev *Abbv = getAbbrev(AbbrevID);
 
     for (unsigned i = 0, e = Abbv->getNumOperandInfos(); i != e; ++i) {
       const BitCodeAbbrevOp &Op = Abbv->getOperandInfo(i);




From sabre at nondot.org  Mon Apr  6 17:44:40 2009
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 06 Apr 2009 22:44:40 -0000
Subject: [llvm-commits] [llvm] r68472 -
	/llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
Message-ID: <200904062244.n36Miebw023252@zion.cs.uiuc.edu>

Author: lattner
Date: Mon Apr  6 17:44:40 2009
New Revision: 68472

URL: http://llvm.org/viewvc/llvm-project?rev=68472&view=rev
Log:
stub out code for reading record with blobs as blobs.  Not active yet.

Modified:
    llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp

Modified: llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp?rev=68472&r1=68471&r2=68472&view=diff

==============================================================================
--- llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp (original)
+++ llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Mon Apr  6 17:44:40 2009
@@ -341,12 +341,33 @@
       ++BlockStats.NumAbbrevs;
       break;
     default:
+      Record.clear();
+      bool HasBlob = false;
+
       ++BlockStats.NumRecords;
-      if (AbbrevID != bitc::UNABBREV_RECORD)
+      if (AbbrevID != bitc::UNABBREV_RECORD) {
         ++BlockStats.NumAbbreviatedRecords;
-      
-      Record.clear();
-      unsigned Code = Stream.ReadRecord(AbbrevID, Record);
+        const BitCodeAbbrev *Abbv = Stream.getAbbrev(AbbrevID);
+        if (Abbv->getNumOperandInfos() != 0) {
+          const BitCodeAbbrevOp &LastOp =  
+            Abbv->getOperandInfo(Abbv->getNumOperandInfos()-1);
+          // If the last operand is a blob, then this record has blob data.
+          if (LastOp.isEncoding() && 
+              LastOp.getEncoding() == BitCodeAbbrevOp::Blob)
+            HasBlob = true;
+        }
+      }
+        
+      unsigned Code;
+      const char *BlobStart = 0;
+      unsigned BlobLen = 0;
+      if (!HasBlob)
+        Code = Stream.ReadRecord(AbbrevID, Record);
+      else {
+        Code = Stream.ReadRecord(AbbrevID, Record);
+        BlobStart = BlobStart;
+        BlobLen = BlobLen;
+      }
 
       // Increment the # occurrences of this code.
       if (BlockStats.CodeFreq.size() <= Code)




From ed at 80386.nl  Mon Apr  6 08:07:12 2009
From: ed at 80386.nl (Ed Schouten)
Date: Mon, 06 Apr 2009 13:07:12 -0000
Subject: [llvm-commits] [llvm] r68443 - in /llvm/trunk:
 lib/Transforms/Scalar/SimplifyLibCalls.cpp
 test/Transforms/SimplifyLibCalls/StrCat.ll
Message-ID: <200904061307.n36D7Gqo032412@zion.cs.uiuc.edu>

Author: ed
Date: Mon Apr  6 08:06:48 2009
New Revision: 68443

URL: http://llvm.org/viewvc/llvm-project?rev=68443&view=rev
Log:
Let the strcat optimizer return the pointer to the start of the buffer,
instead of the place where it started to perform the string copy.

- PR3661
- Patch by Benjamin Kramer!

Modified:
    llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
    llvm/trunk/test/Transforms/SimplifyLibCalls/StrCat.ll

Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=68443&r1=68442&r2=68443&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Mon Apr  6 08:06:48 2009
@@ -514,11 +514,11 @@
     // Now that we have the destination's length, we must index into the
     // destination's pointer to get the actual memcpy destination (end of
     // the string .. we're concatenating).
-    Dst = B.CreateGEP(Dst, DstLen, "endptr");
+    Value *CpyDst = B.CreateGEP(Dst, DstLen, "endptr");
     
     // We have enough information to now generate the memcpy call to do the
     // concatenation for us.  Make a memcpy to copy the nul byte with align = 1.
-    EmitMemCpy(Dst, Src, ConstantInt::get(TD->getIntPtrType(), Len+1), 1, B);
+    EmitMemCpy(CpyDst, Src, ConstantInt::get(TD->getIntPtrType(), Len+1), 1, B);
     return Dst;
   }
 };

Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/StrCat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/StrCat.ll?rev=68443&r1=68442&r2=68443&view=diff

==============================================================================
--- llvm/trunk/test/Transforms/SimplifyLibCalls/StrCat.ll (original)
+++ llvm/trunk/test/Transforms/SimplifyLibCalls/StrCat.ll Mon Apr  6 08:06:48 2009
@@ -1,6 +1,9 @@
 ; Test that the StrCatOptimizer works correctly
+; PR3661
 ; RUN: llvm-as < %s | opt -simplify-libcalls | llvm-dis | \
 ; RUN:   not grep {call.*strcat}
+; RUN: llvm-as < %s | opt -simplify-libcalls | llvm-dis | \
+; RUN:   grep {puts.*%arg1}
 
 @hello = constant [6 x i8] c"hello\00"		; <[6 x i8]*> [#uses=1]
 @null = constant [1 x i8] zeroinitializer		; <[1 x i8]*> [#uses=1]




From gohman at apple.com  Mon Apr  6 19:26:30 2009
From: gohman at apple.com (Dan Gohman)
Date: Tue, 07 Apr 2009 00:26:30 -0000
Subject: [llvm-commits] [llvm] r68479 - in /llvm/trunk/lib/Target:
	IA64/AsmPrinter/ Mips/AsmPrinter/
Message-ID: <200904070026.n370QUwG027547@zion.cs.uiuc.edu>

Author: djg
Date: Mon Apr  6 19:26:29 2009
New Revision: 68479

URL: http://llvm.org/viewvc/llvm-project?rev=68479&view=rev
Log:
Add svn:ignore properties.

Modified:
    llvm/trunk/lib/Target/IA64/AsmPrinter/   (props changed)
    llvm/trunk/lib/Target/Mips/AsmPrinter/   (props changed)

Propchange: llvm/trunk/lib/Target/IA64/AsmPrinter/

------------------------------------------------------------------------------
--- svn:ignore (added)
+++ svn:ignore Mon Apr  6 19:26:29 2009
@@ -0,0 +1,3 @@
+Debug
+Release
+Release-Asserts

Propchange: llvm/trunk/lib/Target/Mips/AsmPrinter/

------------------------------------------------------------------------------
--- svn:ignore (added)
+++ svn:ignore Mon Apr  6 19:26:29 2009
@@ -0,0 +1,3 @@
+Debug
+Release
+Release-Asserts




From sabre at nondot.org  Mon Apr  6 21:55:54 2009
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 07 Apr 2009 02:55:54 -0000
Subject: [llvm-commits] [llvm] r68485 -
	/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
Message-ID: <200904070255.n372ts3m000767@zion.cs.uiuc.edu>

Author: lattner
Date: Mon Apr  6 21:55:53 2009
New Revision: 68485

URL: http://llvm.org/viewvc/llvm-project?rev=68485&view=rev
Log:
remove empty section

Modified:
    llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=68485&r1=68484&r2=68485&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Mon Apr  6 21:55:53 2009
@@ -569,10 +569,6 @@
 }
 
 //===----------------------------------------------------------------------===//
-// Addressing Mode Analysis and Optimization
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
 // Memory Optimization
 //===----------------------------------------------------------------------===//
 




From sabre at nondot.org  Mon Apr  6 21:56:46 2009
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 07 Apr 2009 02:56:46 -0000
Subject: [llvm-commits] [llvm] r68486 - in /llvm/trunk:
 include/llvm/Bitcode/BitstreamReader.h
 tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
Message-ID: <200904070256.n372ukTT000833@zion.cs.uiuc.edu>

Author: lattner
Date: Mon Apr  6 21:56:46 2009
New Revision: 68486

URL: http://llvm.org/viewvc/llvm-project?rev=68486&view=rev
Log:
Add an API for the bitstream reader to read blobs and return
them by reference, instead of packing each byte into a
smallvector.

Modified:
    llvm/trunk/include/llvm/Bitcode/BitstreamReader.h
    llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp

Modified: llvm/trunk/include/llvm/Bitcode/BitstreamReader.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitstreamReader.h?rev=68486&r1=68485&r2=68486&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Bitcode/BitstreamReader.h (original)
+++ llvm/trunk/include/llvm/Bitcode/BitstreamReader.h Mon Apr  6 21:56:46 2009
@@ -371,7 +371,8 @@
     return CurAbbrevs[AbbrevNo];
   }
   
-  unsigned ReadRecord(unsigned AbbrevID, SmallVectorImpl<uint64_t> &Vals) {
+  unsigned ReadRecord(unsigned AbbrevID, SmallVectorImpl<uint64_t> &Vals,
+                      const char **BlobStart = 0, unsigned *BlobLen = 0) {
     if (AbbrevID == bitc::UNABBREV_RECORD) {
       unsigned Code = ReadVBR(6);
       unsigned NumElts = ReadVBR(6);
@@ -413,9 +414,15 @@
           break;
         }
         
-        // Otherwise, read the number of bytes.
-        for (; NumElts; ++NextChar, --NumElts)
-          Vals.push_back(*NextChar);
+        // Otherwise, read the number of bytes.  If we can return a reference to
+        // the data, do so to avoid copying it.
+        if (BlobStart) {
+          *BlobStart = (const char*)NextChar;
+          *BlobLen = NumElts;
+        } else {
+          for (; NumElts; ++NextChar, --NumElts)
+            Vals.push_back(*NextChar);
+        }
         // Skip over tail padding.
         NextChar = NewEnd;
       } else {
@@ -428,6 +435,12 @@
     return Code;
   }
 
+  unsigned ReadRecord(unsigned AbbrevID, SmallVectorImpl<uint64_t> &Vals,
+                      const char *&BlobStart, unsigned &BlobLen) {
+    return ReadRecord(AbbrevID, Vals, &BlobStart, &BlobLen);
+  }
+
+  
   //===--------------------------------------------------------------------===//
   // Abbrev Processing
   //===--------------------------------------------------------------------===//

Modified: llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp?rev=68486&r1=68485&r2=68486&view=diff

==============================================================================
--- llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp (original)
+++ llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Mon Apr  6 21:56:46 2009
@@ -342,32 +342,14 @@
       break;
     default:
       Record.clear();
-      bool HasBlob = false;
 
       ++BlockStats.NumRecords;
-      if (AbbrevID != bitc::UNABBREV_RECORD) {
+      if (AbbrevID != bitc::UNABBREV_RECORD)
         ++BlockStats.NumAbbreviatedRecords;
-        const BitCodeAbbrev *Abbv = Stream.getAbbrev(AbbrevID);
-        if (Abbv->getNumOperandInfos() != 0) {
-          const BitCodeAbbrevOp &LastOp =  
-            Abbv->getOperandInfo(Abbv->getNumOperandInfos()-1);
-          // If the last operand is a blob, then this record has blob data.
-          if (LastOp.isEncoding() && 
-              LastOp.getEncoding() == BitCodeAbbrevOp::Blob)
-            HasBlob = true;
-        }
-      }
         
-      unsigned Code;
       const char *BlobStart = 0;
       unsigned BlobLen = 0;
-      if (!HasBlob)
-        Code = Stream.ReadRecord(AbbrevID, Record);
-      else {
-        Code = Stream.ReadRecord(AbbrevID, Record);
-        BlobStart = BlobStart;
-        BlobLen = BlobLen;
-      }
+      unsigned Code = Stream.ReadRecord(AbbrevID, Record, BlobStart, BlobLen);
 
       // Increment the # occurrences of this code.
       if (BlockStats.CodeFreq.size() <= Code)
@@ -388,7 +370,24 @@
         for (unsigned i = 0, e = Record.size(); i != e; ++i)
           std::cerr << " op" << i << "=" << (int64_t)Record[i];
         
-        std::cerr << "/>\n";
+        std::cerr << "/>";
+        
+        if (BlobStart) {
+          std::cerr << " blob data = ";
+          bool BlobIsPrintable = true;
+          for (unsigned i = 0; i != BlobLen; ++i)
+            if (!isprint(BlobStart[i])) {
+              BlobIsPrintable = false;
+              break;
+            }
+          
+          if (BlobIsPrintable)
+            std::cerr << "'" << std::string(BlobStart, BlobStart+BlobLen) <<"'";
+          else
+            std::cerr << "unprintable, " << BlobLen << " bytes.";
+        }
+        
+        std::cerr << "\n";
       }
       
       break;




From kremenek at apple.com  Mon Apr  6 23:59:19 2009
From: kremenek at apple.com (Ted Kremenek)
Date: Tue, 07 Apr 2009 04:59:19 -0000
Subject: [llvm-commits] [llvm] r68498 - /llvm/tags/checker/checker-0.183/
Message-ID: <200904070459.n374xJ6H004959@zion.cs.uiuc.edu>

Author: kremenek
Date: Mon Apr  6 23:59:19 2009
New Revision: 68498

URL: http://llvm.org/viewvc/llvm-project?rev=68498&view=rev
Log:
Tagging checker-0.183.

Added:
    llvm/tags/checker/checker-0.183/
      - copied from r68497, llvm/trunk/



From sabre at nondot.org  Tue Apr  7 00:03:34 2009
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 07 Apr 2009 05:03:34 -0000
Subject: [llvm-commits] [llvm] r68500 - in /llvm/trunk:
 lib/Transforms/Scalar/InstructionCombining.cpp
 test/Transforms/InstCombine/2009-04-06-GEP-Index-Crash.ll
Message-ID: <200904070503.n3753YLS005129@zion.cs.uiuc.edu>

Author: lattner
Date: Tue Apr  7 00:03:34 2009
New Revision: 68500

URL: http://llvm.org/viewvc/llvm-project?rev=68500&view=rev
Log:
fix rdar://6762290, a crash compiling cxx filt with clang.

Added:
    llvm/trunk/test/Transforms/InstCombine/2009-04-06-GEP-Index-Crash.ll
Modified:
    llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=68500&r1=68499&r2=68500&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Tue Apr  7 00:03:34 2009
@@ -5223,10 +5223,11 @@
     // Convert to correct type.
     if (Op->getType() != IntPtrTy) {
       if (Constant *OpC = dyn_cast<Constant>(Op))
-        Op = ConstantExpr::getSExt(OpC, IntPtrTy);
+        Op = ConstantExpr::getIntegerCast(OpC, IntPtrTy, true);
       else
-        Op = IC.InsertNewInstBefore(new SExtInst(Op, IntPtrTy,
-                                                 Op->getName()+".c"), I);
+        Op = IC.InsertNewInstBefore(CastInst::CreateIntegerCast(Op, IntPtrTy,
+                                                                true,
+                                                      Op->getName()+".c"), I);
     }
     if (Size != 1) {
       Constant *Scale = ConstantInt::get(IntPtrTy, Size);

Added: llvm/trunk/test/Transforms/InstCombine/2009-04-06-GEP-Index-Crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2009-04-06-GEP-Index-Crash.ll?rev=68500&view=auto

==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/2009-04-06-GEP-Index-Crash.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/2009-04-06-GEP-Index-Crash.ll Tue Apr  7 00:03:34 2009
@@ -0,0 +1,24 @@
+; RUN: llvm-as < %s | opt -instcombine | llvm-dis
+; rdar://6762290
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9"
+	%T = type <{ i64, i64, i64 }>
+
+define i32 @test(i8* %start, i32 %X) nounwind {
+entry:
+	%tmp3 = load i64* null		; <i64> [#uses=1]
+	%add.ptr = getelementptr i8* %start, i64 %tmp3		; <i8*> [#uses=1]
+	%tmp158 = load i32* null		; <i32> [#uses=1]
+	%add.ptr159 = getelementptr %T* null, i32 %tmp158
+	%add.ptr209 = getelementptr i8* %start, i64 0		; <i8*> [#uses=1]
+	%add.ptr212 = getelementptr i8* %add.ptr209, i32 %X		; <i8*> [#uses=1]
+	%cmp214 = icmp ugt i8* %add.ptr212, %add.ptr		; <i1> [#uses=1]
+	br i1 %cmp214, label %if.then216, label %if.end363
+
+if.then216:		; preds = %for.body162
+	ret i32 1
+
+if.end363:		; preds = %for.body162
+	ret i32 0
+}




From kremenek at apple.com  Tue Apr  7 00:34:05 2009
From: kremenek at apple.com (Ted Kremenek)
Date: Tue, 07 Apr 2009 05:34:05 -0000
Subject: [llvm-commits] [llvm] r68506 - /llvm/tags/checker/checker-0.183/
Message-ID: <200904070534.n375Y5eZ006092@zion.cs.uiuc.edu>

Author: kremenek
Date: Tue Apr  7 00:34:05 2009
New Revision: 68506

URL: http://llvm.org/viewvc/llvm-project?rev=68506&view=rev
Log:
Removing checker-0.183.

Removed:
    llvm/tags/checker/checker-0.183/



From kremenek at apple.com  Tue Apr  7 00:35:24 2009
From: kremenek at apple.com (Ted Kremenek)
Date: Tue, 07 Apr 2009 05:35:24 -0000
Subject: [llvm-commits] [llvm] r68508 - /llvm/tags/checker/checker-0.183/
Message-ID: <200904070535.n375ZOSd006155@zion.cs.uiuc.edu>

Author: kremenek
Date: Tue Apr  7 00:35:24 2009
New Revision: 68508

URL: http://llvm.org/viewvc/llvm-project?rev=68508&view=rev
Log:
Tagging checker-0.183.

Added:
    llvm/tags/checker/checker-0.183/
      - copied from r68507, llvm/trunk/



From baldrick at free.fr  Tue Apr  7 02:47:34 2009
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 7 Apr 2009 09:47:34 +0200
Subject: [llvm-commits] [llvm] r68465 - in /llvm/trunk:
	docs/BitCodeFormat.html include/llvm/Bitcode/BitCodes.h
	include/llvm/Bitcode/BitstreamReader.h
	include/llvm/Bitcode/BitstreamWriter.h
In-Reply-To: <200904062150.n36LoeCY021210@zion.cs.uiuc.edu>
References: <200904062150.n36LoeCY021210@zion.cs.uiuc.edu>
Message-ID: <200904070947.34963.baldrick@free.fr>

Hi Chris,

> +<li value="5">Blob: This field is emitted as a vbr6, followed by padding to a
> +    32-bit boundary (for alignment) and an array of 8-bit objects.  The array of
> +    bytes is further followed by tail padding to ensure that its total length is
> +    a multiple of 4 bytes.  This makes it very efficient for the reader to
> +    decode the data without having to make a copy of it: it can use a pointer to
> +    the data in the mapped in file and poke directly at it.  A blob may only
> +    occur as the last operand of an abbreviation.</li>

...

> +    Blob  = 5   // 8-bit aligned array of 8-bit characters.

in the docs it says 32-bit aligned, but here it says 8-bit...

> +        // Align end to 32-bits.
> +        while (Out.size() & 3)
> +          Out.push_back(0);

Can you use FlushToWord() here instead?

Ciao,

Duncan.



From baldrick at free.fr  Tue Apr  7 02:54:36 2009
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 7 Apr 2009 09:54:36 +0200
Subject: [llvm-commits] [llvm] r68464 - in /llvm/trunk:
	lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
	test/CodeGen/ARM/2009-04-06-AsmModifier.ll
In-Reply-To: <200904062146.n36Lkpv2021018@zion.cs.uiuc.edu>
References: <200904062146.n36Lkpv2021018@zion.cs.uiuc.edu>
Message-ID: <200904070954.36539.baldrick@free.fr>

Hi Bob,

> Handle 'a' modifier in ARM inline assembly.
> Patch by Richard Pennington.
...
> +    case 'a': // Don't print "#" before a global var name or constant.
>      case 'c': // Don't print "$" before a global var name or constant.
> +      printOperand(MI, OpNo, "no_hash");
> +      return false;

is this correct?  I talked with Richard on IRC, and some
testing with gcc on ARM seemed to show gcc doing something
different with this modifier to what Richard expected.

Ciao,

Duncan.


From baldrick at free.fr  Tue Apr  7 02:59:00 2009
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 7 Apr 2009 09:59:00 +0200
Subject: [llvm-commits] [llvm] r68455 - /llvm/trunk/Makefile.rules
In-Reply-To: <200904061958.n36JwC1F016795@zion.cs.uiuc.edu>
References: <200904061958.n36JwC1F016795@zion.cs.uiuc.edu>
Message-ID: <200904070959.00884.baldrick@free.fr>

Hi Mike,

> Avoid -O3 on Darwin for now.

is this really a Darwin issue?  If it's not clear,
how about using -O2 on all platforms?  People using
FC8 have regularly been reporting miscompilations of
llvm-2.5 when building with optimization for example.
So perhaps this is a more general problem.

Ciao,

Duncan.


From rich at pennware.com  Tue Apr  7 08:18:24 2009
From: rich at pennware.com (Richard Pennington)
Date: Tue, 07 Apr 2009 08:18:24 -0500
Subject: [llvm-commits] [llvm] r68464 - in /llvm/trunk:
 lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
 test/CodeGen/ARM/2009-04-06-AsmModifier.ll
In-Reply-To: <200904070954.36539.baldrick@free.fr>
References: <200904062146.n36Lkpv2021018@zion.cs.uiuc.edu>
	<200904070954.36539.baldrick@free.fr>
Message-ID: <49DB52A0.8040307@pennware.com>

Duncan Sands wrote:
> Hi Bob,
> 
>> Handle 'a' modifier in ARM inline assembly.
>> Patch by Richard Pennington.
> ...
>> +    case 'a': // Don't print "#" before a global var name or constant.
>>      case 'c': // Don't print "$" before a global var name or constant.
>> +      printOperand(MI, OpNo, "no_hash");
>> +      return false;
> 
> is this correct?  I talked with Richard on IRC, and some
> testing with gcc on ARM seemed to show gcc doing something
> different with this modifier to what Richard expected.
> 
> Ciao,
> 
> Duncan.
> 
Duncan,

Bob put me on the right path. It was the "no_hash" that was needed.
We match gcc now.

-Rich


From sabre at nondot.org  Tue Apr  7 11:30:33 2009
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 07 Apr 2009 16:30:33 -0000
Subject: [llvm-commits] [llvm] r68518 -
	/llvm/trunk/include/llvm/Bitcode/BitCodes.h
Message-ID: <200904071630.n37GUYu3008545@zion.cs.uiuc.edu>

Author: lattner
Date: Tue Apr  7 11:30:31 2009
New Revision: 68518

URL: http://llvm.org/viewvc/llvm-project?rev=68518&view=rev
Log:
fix comment to reflect the implementation I ended up settling on.
Thanks to Duncan for noticing this

Modified:
    llvm/trunk/include/llvm/Bitcode/BitCodes.h

Modified: llvm/trunk/include/llvm/Bitcode/BitCodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitCodes.h?rev=68518&r1=68517&r2=68518&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Bitcode/BitCodes.h (original)
+++ llvm/trunk/include/llvm/Bitcode/BitCodes.h Tue Apr  7 11:30:31 2009
@@ -89,7 +89,7 @@
     VBR   = 2,  // A VBR field where Val specifies the width of each chunk.
     Array = 3,  // A sequence of fields, next field species elt encoding.
     Char6 = 4,  // A 6-bit fixed field which maps to [a-zA-Z0-9._].
-    Blob  = 5   // 8-bit aligned array of 8-bit characters.
+    Blob  = 5   // 32-bit aligned array of 8-bit characters.
   };
 
   explicit BitCodeAbbrevOp(uint64_t V) :  Val(V), IsLiteral(true) {}




From clattner at apple.com  Tue Apr  7 11:31:04 2009
From: clattner at apple.com (Chris Lattner)
Date: Tue, 7 Apr 2009 09:31:04 -0700
Subject: [llvm-commits] [llvm] r68465 - in /llvm/trunk:
	docs/BitCodeFormat.html include/llvm/Bitcode/BitCodes.h
	include/llvm/Bitcode/BitstreamReader.h	include/llvm/Bitcode/BitstreamWriter.h
In-Reply-To: <200904070947.34963.baldrick@free.fr>
References: <200904062150.n36LoeCY021210@zion.cs.uiuc.edu>
	<200904070947.34963.baldrick@free.fr>
Message-ID: <382957AF-0F53-49B8-A506-5830D9DE2EE6@apple.com>

On Apr 7, 2009, at 12:47 AM, Duncan Sands wrote:
>> +    Blob  = 5   // 8-bit aligned array of 8-bit characters.
>
> in the docs it says 32-bit aligned, but here it says 8-bit...

Nice catch, fixed!

>> +        // Align end to 32-bits.
>> +        while (Out.size() & 3)
>> +          Out.push_back(0);
>
> Can you use FlushToWord() here instead?

Unfortunately no, by directly pushing bytes onto the output stream,  
we're subverting the bit-wise mechanism that flushtoword uses.

-Chris


From clattner at apple.com  Tue Apr  7 11:31:56 2009
From: clattner at apple.com (Chris Lattner)
Date: Tue, 7 Apr 2009 09:31:56 -0700
Subject: [llvm-commits] [llvm] r68455 - /llvm/trunk/Makefile.rules
In-Reply-To: <200904070959.00884.baldrick@free.fr>
References: <200904061958.n36JwC1F016795@zion.cs.uiuc.edu>
	<200904070959.00884.baldrick@free.fr>
Message-ID: <45AFC928-ABB7-4CF5-890C-DB614B8E0604@apple.com>

On Apr 7, 2009, at 12:59 AM, Duncan Sands wrote:
> Hi Mike,
>> Avoid -O3 on Darwin for now.
>
> is this really a Darwin issue?  If it's not clear,
> how about using -O2 on all platforms?  People using
> FC8 have regularly been reporting miscompilations of
> llvm-2.5 when building with optimization for example.
> So perhaps this is a more general problem.

I would be supportive of using -O2 everywhere, but this will  
significantly impact our compile times (llvm will compile slower).

-Chris


From sabre at nondot.org  Tue Apr  7 11:39:01 2009
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 7 Apr 2009 11:39:01 -0500
Subject: [llvm-commits] CVS: llvm-www/header.incl
Message-ID: <200904071639.n37Gd0LN008866@zion.cs.uiuc.edu>



Changes in directory llvm-www:

header.incl updated: 1.79 -> 1.80
---
Log message:

add a link to the wiki


---
Diffs of the changes:  (+1 -0)

 header.incl |    1 +
 1 files changed, 1 insertion(+)


Index: llvm-www/header.incl
diff -u llvm-www/header.incl:1.79 llvm-www/header.incl:1.80
--- llvm-www/header.incl:1.79	Fri Apr  3 12:30:10 2009
+++ llvm-www/header.incl	Tue Apr  7 11:34:46 2009
@@ -32,6 +32,7 @@
 <a href="/Users.html">LLVM&nbsp;Users</a><br>
 <a href="/developers.cgi">LLVM&nbsp;Developers</a><br>
 <a href="/bugs/">Bug&nbsp;Database</a><br>
+<a href="http://wiki.llvm.org/Main_Page">Wiki</a><br>
 </div>
 
 <br>





From bob.wilson at apple.com  Tue Apr  7 11:45:29 2009
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 7 Apr 2009 09:45:29 -0700
Subject: [llvm-commits] [llvm] r68464 - in /llvm/trunk:
	lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
	test/CodeGen/ARM/2009-04-06-AsmModifier.ll
In-Reply-To: <49DB52A0.8040307@pennware.com>
References: <200904062146.n36Lkpv2021018@zion.cs.uiuc.edu>
	<200904070954.36539.baldrick@free.fr>
	<49DB52A0.8040307@pennware.com>
Message-ID: <E3D15704-8C4D-4675-9A9B-ACBAEBCB6D9F@apple.com>


On Apr 7, 2009, at 6:18 AM, Richard Pennington wrote:

> Duncan Sands wrote:
>> Hi Bob,
>>> Handle 'a' modifier in ARM inline assembly.
>>> Patch by Richard Pennington.
>> ...
>>> +    case 'a': // Don't print "#" before a global var name or  
>>> constant.
>>>     case 'c': // Don't print "$" before a global var name or  
>>> constant.
>>> +      printOperand(MI, OpNo, "no_hash");
>>> +      return false;
>> is this correct?  I talked with Richard on IRC, and some
>> testing with gcc on ARM seemed to show gcc doing something
>> different with this modifier to what Richard expected.
>> Ciao,
>> Duncan.
> Duncan,
>
> Bob put me on the right path. It was the "no_hash" that was needed.
> We match gcc now.

There is more that could be done here.  I added some comments in the  
bug report.  GCC does all sorts of elaborate things with these operand  
modifiers.  LLVM doesn't recognize most of them.  For ARM, the "a"  
modifier handles all the different ARM and Thumb addressing modes.   
The testcase in the bug report was for an immediate operand, and for  
that case, I do think Richard's patch is correct.  (One could argue  
that the testcase is not so great.  The "a" modifier is supposed to be  
used for addresses, but the argument to an SWI instruction is not an  
address.  A "c" modifier would make more sense in this case.  But, we  
want to be compatible with GCC and either "a" or "c" will do the same  
thing in this particular case.)


From edwintorok at gmail.com  Tue Apr  7 12:23:03 2009
From: edwintorok at gmail.com (Torok Edwin)
Date: Tue, 07 Apr 2009 17:23:03 -0000
Subject: [llvm-commits] [llvm] r68523 - in /llvm/trunk:
 examples/HowToUseJIT/HowToUseJIT.cpp include/llvm/AbstractTypeUser.h
 lib/VMCore/Type.cpp
Message-ID: <200904071723.n37HN4s8018418@zion.cs.uiuc.edu>

Author: edwin
Date: Tue Apr  7 12:23:02 2009
New Revision: 68523

URL: http://llvm.org/viewvc/llvm-project?rev=68523&view=rev
Log:
Another attempt at fixing PR2975.
Types can have references to eachother, so we can't just call destroy on them.

Modified:
    llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp
    llvm/trunk/include/llvm/AbstractTypeUser.h
    llvm/trunk/lib/VMCore/Type.cpp

Modified: llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp?rev=68523&r1=68522&r2=68523&view=diff

==============================================================================
--- llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp (original)
+++ llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp Tue Apr  7 12:23:02 2009
@@ -42,6 +42,7 @@
 #include "llvm/ExecutionEngine/JIT.h"
 #include "llvm/ExecutionEngine/Interpreter.h"
 #include "llvm/ExecutionEngine/GenericValue.h"
+#include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
@@ -109,5 +110,8 @@
 
   // Import result of execution:
   outs() << "Result: " << gv.IntVal << "\n";
+  EE->freeMachineCodeForFunction(FooF);
+  delete EE;
+  llvm_shutdown();
   return 0;
 }

Modified: llvm/trunk/include/llvm/AbstractTypeUser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/AbstractTypeUser.h?rev=68523&r1=68522&r2=68523&view=diff

==============================================================================
--- llvm/trunk/include/llvm/AbstractTypeUser.h (original)
+++ llvm/trunk/include/llvm/AbstractTypeUser.h Tue Apr  7 12:23:02 2009
@@ -137,6 +137,7 @@
 ///
 class PATypeHolder {
   mutable const Type *Ty;
+  void destroy();
 public:
   PATypeHolder(const Type *ty) : Ty(ty) {
     addRef();
@@ -145,7 +146,7 @@
     addRef();
   }
 
-  ~PATypeHolder() { dropRef(); }
+  ~PATypeHolder() { if (Ty) dropRef(); }
 
   operator Type *() const { return get(); }
   Type *get() const;
@@ -173,6 +174,7 @@
 private:
   void addRef();
   void dropRef();
+  friend class TypeMapBase;
 };
 
 // simplify_type - Allow clients to treat uses just like values when using

Modified: llvm/trunk/lib/VMCore/Type.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Type.cpp?rev=68523&r1=68522&r2=68523&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/Type.cpp (original)
+++ llvm/trunk/lib/VMCore/Type.cpp Tue Apr  7 12:23:02 2009
@@ -388,6 +388,10 @@
 #endif
 }
 
+void PATypeHolder::destroy() {
+  Ty = 0;
+}
+
 // dropAllTypeUses - When this (abstract) type is resolved to be equal to
 // another (more concrete) type, we must eliminate all references to other
 // types, to avoid some circular reference problems.
@@ -666,6 +670,27 @@
   std::multimap<unsigned, PATypeHolder> TypesByHash;
 
 public:
+  ~TypeMapBase()
+  {
+    //PATypeHolder won't destroy non-abstract types.
+    //We can't destroy them by simply iterating,  because
+    //they may contain references to each-other
+
+    for (std::multimap<unsigned, PATypeHolder>::iterator I
+         = TypesByHash.begin(), E = TypesByHash.end(); I != E; ++I) {
+      Type *Ty = const_cast<Type*>(I->second.Ty);
+      I->second.destroy();
+      // We can't invoke destroy or delete, because the type may
+      // contain references to already freed types.
+      // So we have to destruct the object the ugly way.
+      if (Ty) {
+        Ty->AbstractTypeUsers.clear();
+        static_cast<const Type*>(Ty)->Type::~Type();
+        operator delete(Ty);
+      }
+    }
+  }
+
   void RemoveFromTypesByHash(unsigned Hash, const Type *Ty) {
     std::multimap<unsigned, PATypeHolder>::iterator I =
       TypesByHash.lower_bound(Hash);




From lattner at apple.com  Tue Apr  7 12:44:22 2009
From: lattner at apple.com (Tanya Lattner)
Date: Tue, 7 Apr 2009 10:44:22 -0700
Subject: [llvm-commits] [llvm] r68187 - /llvm/trunk/autoconf/configure.ac
In-Reply-To: <200904010439.n314dP2p010541@zion.cs.uiuc.edu>
References: <200904010439.n314dP2p010541@zion.cs.uiuc.edu>
Message-ID: <1BBB1B35-3F44-4021-B115-258C3D8814B1@apple.com>

Regenerate configure?

On Mar 31, 2009, at 9:39 PM, Nick Lewycky wrote:

> Author: nicholas
> Date: Tue Mar 31 23:39:25 2009
> New Revision: 68187
>
> URL: http://llvm.org/viewvc/llvm-project?rev=68187&view=rev
> Log:
> Detect that we're building from a git checkout like we do for cvs  
> and svn.
> Based on a patch by Nicolas Trangez on the unladen-swallow mailing  
> list!
>
> Modified:
>    llvm/trunk/autoconf/configure.ac
>
> Modified: llvm/trunk/autoconf/configure.ac
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=68187&r1=68186&r2=68187&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/autoconf/configure.ac (original)
> +++ llvm/trunk/autoconf/configure.ac Tue Mar 31 23:39:25 2009
> @@ -255,13 +255,13 @@
>   AC_SUBST(LLVM_CROSS_COMPILING, [0])
> fi
>
> -dnl Check to see if there's a "CVS" (or .svn) directory indicating  
> that this
> -dnl build is being done from a checkout. This sets up several  
> defaults for the
> -dnl command line switches. When we build with a CVS directory, we  
> get a
> -dnl debug with assertions turned on. Without, we assume a source  
> release and we
> -dnl get an optimized build without assertions. See --enable- 
> optimized and
> -dnl --enable-assertions below
> -if test -d "CVS" -o -d "${srcdir}/CVS" -o -d ".svn" -o -d "$ 
> {srcdir}/.svn"; then
> +dnl Check to see if there's a "CVS" (or .svn or .git) directory  
> indicating
> +dnl that this build is being done from a checkout. This sets up  
> several
> +dnl defaults for the command line switches. When we build with a  
> CVS directory,
> +dnl we get a debug with assertions turned on. Without, we assume a  
> source
> +dnl release and we get an optimized build without assertions.
> +dnl See --enable-optimized and --enable-assertions below
> +if test -d "CVS" -o -d "${srcdir}/CVS" -o -d ".svn" -o -d "$ 
> {srcdir}/.svn" -o -d ".git" -o -d "${srcdir}/.git"; then
>   cvsbuild="yes"
>   optimize="no"
>   AC_SUBST(CVSBUILD,[[CVSBUILD=1]])
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From baldrick at free.fr  Tue Apr  7 13:36:50 2009
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 7 Apr 2009 20:36:50 +0200
Subject: [llvm-commits] [llvm] r68523 - in /llvm/trunk:
	examples/HowToUseJIT/HowToUseJIT.cpp
	include/llvm/AbstractTypeUser.h lib/VMCore/Type.cpp
In-Reply-To: <200904071723.n37HN4s8018418@zion.cs.uiuc.edu>
References: <200904071723.n37HN4s8018418@zion.cs.uiuc.edu>
Message-ID: <200904072036.50777.baldrick@free.fr>

Hi Edwin,

> +    //PATypeHolder won't destroy non-abstract types.
> +    //We can't destroy them by simply iterating,  because
> +    //they may contain references to each-other

there should be a space after //.

Ciao,

Duncan.


From isanbard at gmail.com  Tue Apr  7 13:40:56 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 07 Apr 2009 18:40:56 -0000
Subject: [llvm-commits] [llvm] r68528 - /llvm/trunk/docs/FAQ.html
Message-ID: <200904071840.n37Ieuun022299@zion.cs.uiuc.edu>

Author: void
Date: Tue Apr  7 13:40:56 2009
New Revision: 68528

URL: http://llvm.org/viewvc/llvm-project?rev=68528&view=rev
Log:
Another reformatting. No change in docs.

Modified:
    llvm/trunk/docs/FAQ.html

Modified: llvm/trunk/docs/FAQ.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/FAQ.html?rev=68528&r1=68527&r2=68528&view=diff

==============================================================================
--- llvm/trunk/docs/FAQ.html (original)
+++ llvm/trunk/docs/FAQ.html Tue Apr  7 13:40:56 2009
@@ -2,6 +2,7 @@
                       "http://www.w3.org/TR/html4/strict.dtd">
 <html>
 <head>
+  <meta http-equiv="Content-Type" content="text/html; charset=utf-8">
   <title>LLVM: Frequently Asked Questions</title>
   <style type="text/css">
     @import url("llvm.css");
@@ -18,78 +19,95 @@
 <ol>
   <li><a href="#license">License</a>
   <ol>
-  <li>Why are the LLVM source code and the front-end distributed under different
-  licenses?</li>
-  <li>Does the University of Illinois Open Source License really qualify as an
-  "open source" license?</li>
-  <li>Can I modify LLVM source code and redistribute the modified source?</li>
-  <li>Can I modify LLVM source code and redistribute binaries or other tools
-  based on it, without redistributing the source?</li>
+    <li>Why are the LLVM source code and the front-end distributed under
+        different licenses?</li>
+
+    <li>Does the University of Illinois Open Source License really qualify as an
+       "open source" license?</li>
+
+    <li>Can I modify LLVM source code and redistribute the modified source?</li>
+
+    <li>Can I modify LLVM source code and redistribute binaries or other tools
+        based on it, without redistributing the source?</li>
   </ol></li>
 
   <li><a href="#source">Source code</a>
   <ol>
-  <li>In what language is LLVM written?</li>
-  <li>How portable is the LLVM source code?</li>
+    <li>In what language is LLVM written?</li>
+
+    <li>How portable is the LLVM source code?</li>
   </ol></li>
 
   <li><a href="#build">Build Problems</a>
   <ol>
-  <li>When I run configure, it finds the wrong C compiler.</li>
-  <li>The <tt>configure</tt> script finds the right C compiler, but it uses the
-  LLVM linker from a previous build.  What do I do?</li>
-  <li>When creating a dynamic library, I get a strange GLIBC error.</li>
-  <li>I've updated my source tree from Subversion, and now my build is trying 
-  to use a file/directory that doesn't exist.</li>
-  <li>I've modified a Makefile in my source tree, but my build tree keeps using
-  the old version.  What do I do?</li>
-  <li>I've upgraded to a new version of LLVM, and I get strange build
-  errors.</li>
-  <li>I've built LLVM and am testing it, but the tests freeze.</li>
-  <li>Why do test results differ when I perform different types of builds?</li>
-  <li>Compiling LLVM with GCC 3.3.2 fails, what should I do?</li>
-  <li>Compiling LLVM with GCC succeeds, but the resulting tools do not work, what can be wrong?</li>
-  <li>When I use the test suite, all of the C Backend tests fail.  What is
-      wrong?</li>
-  <li>After Subversion update, rebuilding gives the error "No rule to make
-      target".</li>
-  <li><a href="#llvmc">The <tt>llvmc</tt> program gives me errors/doesn't
-      work.</a></li>
+    <li>When I run configure, it finds the wrong C compiler.</li>
+
+    <li>The <tt>configure</tt> script finds the right C compiler, but it uses
+        the LLVM linker from a previous build.  What do I do?</li>
+
+    <li>When creating a dynamic library, I get a strange GLIBC error.</li>
+
+    <li>I've updated my source tree from Subversion, and now my build is trying
+        to use a file/directory that doesn't exist.</li>
+
+    <li>I've modified a Makefile in my source tree, but my build tree keeps
+        using the old version.  What do I do?</li>
+
+    <li>I've upgraded to a new version of LLVM, and I get strange build
+        errors.</li>
+
+    <li>I've built LLVM and am testing it, but the tests freeze.</li>
+
+    <li>Why do test results differ when I perform different types of
+        builds?</li>
+
+    <li>Compiling LLVM with GCC 3.3.2 fails, what should I do?</li>
+
+    <li>Compiling LLVM with GCC succeeds, but the resulting tools do not work,
+        what can be wrong?</li>
+
+    <li>When I use the test suite, all of the C Backend tests fail.  What is
+        wrong?</li>
+
+    <li>After Subversion update, rebuilding gives the error "No rule to make
+        target".</li>
+
+    <li><a href="#llvmc">The <tt>llvmc</tt> program gives me errors/doesn't
+        work.</a></li>
   </ol></li>
 
   <li><a href="#felangs">Source Languages</a>
   <ol>
     <li><a href="#langs">What source languages are supported?</a></li>
+
     <li><a href="#langirgen">I'd like to write a self-hosting LLVM compiler. How
-      should I interface with the LLVM middle-end optimizers and back-end code 
-      generators?</a></li>
+        should I interface with the LLVM middle-end optimizers and back-end code
+        generators?</a></li>
+
     <li><a href="#langhlsupp">What support is there for higher level source
-      language constructs for building a compiler?</a></li>
+        language constructs for building a compiler?</a></li>
+
     <li><a href="GetElementPtr.html">I don't understand the GetElementPtr
       instruction. Help!</a></li>
   </ol>
 
   <li><a href="#cfe">Using the GCC Front End</a>
   <ol>
-    <li>
-    When I compile software that uses a configure script, the configure script
-    thinks my system has all of the header files and libraries it is testing
-    for.  How do I get configure to work correctly?
-    </li>
-
-    <li>
-    When I compile code using the LLVM GCC front end, it complains that it
-    cannot find libcrtend.a.
-    </li>
-
-    <li>
-    How can I disable all optimizations when compiling code using the LLVM GCC front end?
-    </li>
+    <li>When I compile software that uses a configure script, the configure
+        script thinks my system has all of the header files and libraries it is
+        testing for.  How do I get configure to work correctly?</li>
 
-    <li><a href="#translatecxx">Can I use LLVM to convert C++ code to C code?</a></li>
+    <li>When I compile code using the LLVM GCC front end, it complains that it
+        cannot find libcrtend.a?</li>
 
-    <li><a href="#platformindependent">Can I compile C or C++ code to platform-independent LLVM bitcode?</a></li>
+    <li>How can I disable all optimizations when compiling code using the LLVM
+        GCC front end?</li>
 
+    <li><a href="#translatecxx">Can I use LLVM to convert C++ code to C
+        code?</a></li>
+
+    <li><a href="#platformindependent">Can I compile C or C++ code to
+        platform-independent LLVM bitcode?</a></li>
   </ol>
   </li>
 
@@ -98,8 +116,11 @@
      <li><a href="#iosinit">What is this <tt>llvm.global_ctors</tt> and
           <tt>_GLOBAL__I__tmp_webcompile...</tt> stuff that happens when I
           #include &lt;iostream&gt;?</a></li>
+
      <li><a href="#codedce">Where did all of my code go??</a></li>
-     <li><a href="#undef">What is this "<tt>undef</tt>" thing that shows up in my code?</a></li>
+
+     <li><a href="#undef">What is this "<tt>undef</tt>" thing that shows up in
+         my code?</a></li>
   </ol>
   </li>
 </ol>
@@ -117,25 +138,26 @@
 
 <div class="question">
 <p>Why are the LLVM source code and the front-end distributed under different
-licenses?</p>
+   licenses?</p>
 </div>
 	
 <div class="answer">
 <p>The C/C++ front-ends are based on GCC and must be distributed under the GPL.
-Our aim is to distribute LLVM source code under a <em>much less restrictive</em>
-license, in particular one that does not compel users who distribute tools based
-on modifying the source to redistribute the modified source code as well.</p>
+   Our aim is to distribute LLVM source code under a <em>much less
+   restrictive</em> license, in particular one that does not compel users who
+   distribute tools based on modifying the source to redistribute the modified
+   source code as well.</p>
 </div>
 
 <div class="question">
 <p>Does the University of Illinois Open Source License really qualify as an
-"open source" license?</p>
+   "open source" license?</p>
 </div>
 
 <div class="answer">
-<p>Yes, the license is <a
-href="http://www.opensource.org/licenses/UoI-NCSA.php">certified</a> by the Open
-Source Initiative (OSI).</p>
+<p>Yes, the license
+   is <a href="http://www.opensource.org/licenses/UoI-NCSA.php">certified</a> by
+   the Open Source Initiative (OSI).</p>
 </div>
 
 <div class="question">
@@ -144,18 +166,19 @@
 
 <div class="answer">
 <p>Yes.  The modified source distribution must retain the copyright notice and
-follow the three bulletted conditions listed in the <a
-href="http://llvm.org/svn/llvm-project/llvm/trunk/LICENSE.TXT">LLVM license</a>.</p>
+   follow the three bulletted conditions listed in
+   the <a href="http://llvm.org/svn/llvm-project/llvm/trunk/LICENSE.TXT">LLVM
+   license</a>.</p>
 </div>
 
 <div class="question">
 <p>Can I modify LLVM source code and redistribute binaries or other tools based
-on it, without redistributing the source?</p>
+   on it, without redistributing the source?</p>
 </div>
 
 <div class="answer">
-<p>Yes, this is why we distribute LLVM under a less restrictive license than
-GPL, as explained in the first question above.</p>
+<p>Yes. This is why we distribute LLVM under a less restrictive license than
+   GPL, as explained in the first question above.</p>
 </div>
 
 <!-- *********************************************************************** -->
@@ -170,7 +193,7 @@
 
 <div class="answer">
 <p>All of the LLVM tools and libraries are written in C++ with extensive use of
-the STL.</p>
+   the STL.</p>
 </div>
 
 <div class="question">
@@ -207,26 +230,25 @@
 </div>
 
 <div class="answer">
-
 <p>The <tt>configure</tt> script attempts to locate first <tt>gcc</tt> and then
-<tt>cc</tt>, unless it finds compiler paths set in <tt>CC</tt> and <tt>CXX</tt>
-for the C and C++ compiler, respectively.</p>
+   <tt>cc</tt>, unless it finds compiler paths set in <tt>CC</tt>
+   and <tt>CXX</tt> for the C and C++ compiler, respectively.</p>
 
 <p>If <tt>configure</tt> finds the wrong compiler, either adjust your
-<tt>PATH</tt> environment variable or set <tt>CC</tt> and <tt>CXX</tt>
-explicitly.</p>
+   <tt>PATH</tt> environment variable or set <tt>CC</tt> and <tt>CXX</tt>
+   explicitly.</p>
 
 </div>
 
 <div class="question">
 <p>The <tt>configure</tt> script finds the right C compiler, but it uses the
-LLVM linker from a previous build.  What do I do?</p>
+   LLVM linker from a previous build.  What do I do?</p>
 </div>
 
 <div class="answer">
 <p>The <tt>configure</tt> script uses the <tt>PATH</tt> to find executables, so
-if it's grabbing the wrong linker/assembler/etc, there are two ways to fix
-it:</p>
+   if it's grabbing the wrong linker/assembler/etc, there are two ways to fix
+   it:</p>
 
 <ol>
   <li><p>Adjust your <tt>PATH</tt> environment variable so that the correct
@@ -245,7 +267,6 @@
          to do its work without having to adjust your <tt>PATH</tt>
          permanently.</p></li>
 </ol>
-
 </div>
 
 <div class="question">
@@ -254,38 +275,37 @@
 
 <div class="answer">
 <p>Under some operating systems (i.e. Linux), libtool does not work correctly if
-GCC was compiled with the --disable-shared option.  To work around this, install
-your own version of GCC that has shared libraries enabled by default.</p>
+   GCC was compiled with the --disable-shared option.  To work around this,
+   install your own version of GCC that has shared libraries enabled by
+   default.</p>
 </div>
 
 <div class="question">
-<p>I've updated my source tree from Subversion, and now my build is trying to 
-use a file/directory that doesn't exist.</p>
+<p>I've updated my source tree from Subversion, and now my build is trying to
+   use a file/directory that doesn't exist.</p>
 </div>
 
 <div class="answer">
 <p>You need to re-run configure in your object directory.  When new Makefiles
-are added to the source tree, they have to be copied over to the object tree in
-order to be used by the build.</p>
+   are added to the source tree, they have to be copied over to the object tree
+   in order to be used by the build.</p>
 </div>
 
 <div class="question">
 <p>I've modified a Makefile in my source tree, but my build tree keeps using the
-old version.  What do I do?</p>
+   old version.  What do I do?</p>
 </div>
 
 <div class="answer">
-<p>If the Makefile already exists in your object tree, you
-can just run the following command in the top level directory of your object
-tree:</p>
+<p>If the Makefile already exists in your object tree, you can just run the
+   following command in the top level directory of your object tree:</p>
 
 <pre class="doc_code">
 % ./config.status &lt;relative path to Makefile&gt;
 </pre>
 
 <p>If the Makefile is new, you will have to modify the configure script to copy
-it over.</p>
-
+   it over.</p>
 </div>
 
 <div class="question">
@@ -295,13 +315,12 @@
 <div class="answer">
 
 <p>Sometimes, changes to the LLVM source code alters how the build system works.
-Changes in libtool, autoconf, or header file dependencies are especially prone
-to this sort of problem.</p>
+   Changes in libtool, autoconf, or header file dependencies are especially
+   prone to this sort of problem.</p>
 
 <p>The best thing to try is to remove the old files and re-build.  In most
-cases, this takes care of the problem.  To do this, just type <tt>make
-clean</tt> and then <tt>make</tt> in the directory that fails to build.</p>
-
+   cases, this takes care of the problem.  To do this, just type <tt>make
+   clean</tt> and then <tt>make</tt> in the directory that fails to build.</p>
 </div>
 
 <div class="question">
@@ -309,10 +328,9 @@
 </div>
 
 <div class="answer">
-
 <p>This is most likely occurring because you built a profile or release
-(optimized) build of LLVM and have not specified the same information on the
-<tt>gmake</tt> command line.</p>
+   (optimized) build of LLVM and have not specified the same information on the
+   <tt>gmake</tt> command line.</p>
 
 <p>For example, if you built LLVM with the command:</p>
 
@@ -326,7 +344,6 @@
 % cd llvm/test
 % gmake ENABLE_PROFILING=1
 </pre>
-
 </div>
 
 <div class="question">
@@ -334,17 +351,15 @@
 </div>
 
 <div class="answer">
-
 <p>The LLVM test suite is dependent upon several features of the LLVM tools and
-libraries.</p>
+   libraries.</p>
 
 <p>First, the debugging assertions in code are not enabled in optimized or
-profiling builds.  Hence, tests that used to fail may pass.</p>
+   profiling builds.  Hence, tests that used to fail may pass.</p>
 	
 <p>Second, some tests may rely upon debugging options or behavior that is only
-available in the debug build.  These tests will fail in an optimized or profile
-build.</p>
-
+   available in the debug build.  These tests will fail in an optimized or
+   profile build.</p>
 </div>
 
 <div class="question">
@@ -352,24 +367,26 @@
 </div>
 
 <div class="answer">
-<p>This is <a href="http://gcc.gnu.org/bugzilla/show_bug.cgi?id=13392">a bug in GCC</a>, and 
-affects projects other than LLVM.  Try upgrading or downgrading your GCC.</p>
+<p>This is <a href="http://gcc.gnu.org/bugzilla/show_bug.cgi?id=13392">a bug in
+   GCC</a>, and affects projects other than LLVM.  Try upgrading or downgrading
+   your GCC.</p>
 </div>
 
 <div class="question">
-<p>Compiling LLVM with GCC succeeds, but the resulting tools do not work, what can be wrong?</p>
+<p>Compiling LLVM with GCC succeeds, but the resulting tools do not work, what
+   can be wrong?</p>
 </div>
 
 <div class="answer">
-<p>Several versions of GCC have shown a weakness in miscompiling the LLVM codebase. Please
-consult your compiler version (<tt>gcc --version</tt>) to find out whether it is
-<a href="GettingStarted.html#brokengcc">broken</a>. If so, your only option is to upgrade
-GCC to a known good version.</p>
+<p>Several versions of GCC have shown a weakness in miscompiling the LLVM
+   codebase. Please consult your compiler version (<tt>gcc --version</tt>) to
+   find out whether it is <a href="GettingStarted.html#brokengcc">broken</a>.
+   If so, your only option is to upgrade GCC to a known good version.</p>
 </div>
 
 <div class="question">
 <p>After Subversion update, rebuilding gives the error "No rule to make
-target".</p>
+   target".</p>
 </div>
 
 <div class="answer">
@@ -381,9 +398,9 @@
 Stop.
 </pre>
 
-<p>This may occur anytime files are moved within the Subversion repository or 
-removed entirely.  In this case, the best solution is to erase all 
-<tt>.d</tt> files, which list dependencies for source files, and rebuild:</p>
+<p>This may occur anytime files are moved within the Subversion repository or
+   removed entirely.  In this case, the best solution is to erase all
+   <tt>.d</tt> files, which list dependencies for source files, and rebuild:</p>
 
 <pre class="doc_code">
 % cd $LLVM_OBJ_DIR
@@ -392,105 +409,121 @@
 </pre>
 
 <p>In other cases, it may be necessary to run <tt>make clean</tt> before
-rebuilding.</p>
+   rebuilding.</p>
 </div>
 
 <div class="question"><p><a name="llvmc">
-The <tt>llvmc</tt> program gives me errors/doesn't work.</a></p>
+<p>The <tt>llvmc</tt> program gives me errors/doesn't work.</a></p>
 </div>
 
 <div class="answer">
 <p><tt>llvmc</tt> is experimental and isn't really supported. We suggest
-using <tt>llvm-gcc</tt> instead.</p>
+   using <tt>llvm-gcc</tt> instead.</p>
 </div>
 
 <!-- *********************************************************************** -->
 <div class="doc_section"><a name="felangs">Source Languages</a></div>
 
-<div class="question"><p>
-  <a name="langs">What source languages are supported?</a></p>
+<div class="question">
+<p><a name="langs">What source languages are supported?</a></p>
+</div>
+
+<div class="answer">
+<p>LLVM currently has full support for C and C++ source languages. These are
+   available through a special version of GCC that LLVM calls the
+   <a href="#cfe">C Front End</a></p>
+
+<p>There is an incomplete version of a Java front end available in the
+   <tt>java</tt> module. There is no documentation on this yet so you'll need to
+   download the code, compile it, and try it.</p>
+
+<p>The PyPy developers are working on integrating LLVM into the PyPy backend so
+   that PyPy language can translate to LLVM.</p>
+</div>
+
+<div class="question">
+<p><a name="langirgen">I'd like to write a self-hosting LLVM compiler. How
+   should I interface with the LLVM middle-end optimizers and back-end code
+   generators?</a></p>
+</div>
+
+<div class="answer">
+<p>Your compiler front-end will communicate with LLVM by creating a module in
+   the LLVM intermediate representation (IR) format. Assuming you want to write
+   your language's compiler in the language itself (rather than C++), there are
+   3 major ways to tackle generating LLVM IR from a front-end:</p>
+
+<ul>
+  <li><strong>Call into the LLVM libraries code using your language's FFI
+      (foreign function interface).</strong>
+
+    <ul>
+      <li><em>for:</em> best tracks changes to the LLVM IR, .ll syntax, and .bc
+          format</li>
+
+      <li><em>for:</em> enables running LLVM optimization passes without a
+          emit/parse overhead</li>
+
+      <li><em>for:</em> adapts well to a JIT context</li>
+
+      <li><em>against:</em> lots of ugly glue code to write</li>
+    </ul></li>
+
+  <li>  <strong>Emit LLVM assembly from your compiler's native language.</strong>
+    <ul>
+      <li><em>for:</em> very straightforward to get started</li>
+
+      <li><em>against:</em> the .ll parser is slower than the bitcode reader
+          when interfacing to the middle end</li>
+
+      <li><em>against:</em> you'll have to re-engineer the LLVM IR object model
+          and asm writer in your language</li>
+
+      <li><em>against:</em> it may be harder to track changes to the IR</li>
+    </ul></li>
+
+  <li><strong>Emit LLVM bitcode from your compiler's native language.</strong>
+
+    <ul>
+      <li><em>for:</em> can use the more-efficient bitcode reader when
+          interfacing to the middle end</li>
+
+      <li><em>against:</em> you'll have to re-engineer the LLVM IR object 
+          model and bitcode writer in your language</li>
+
+      <li><em>against:</em> it may be harder to track changes to the IR</li>
+    </ul></li>
+</ul>
+
+<p>If you go with the first option, the C bindings in include/llvm-c should help
+   a lot, since most languages have strong support for interfacing with C. The
+   most common hurdle with calling C from managed code is interfacing with the
+   garbage collector. The C interface was designed to require very little memory
+   management, and so is straightforward in this regard.</p>
 </div>
+
+<div class="question">
+<p><a name="langhlsupp">What support is there for a higher level source language
+   constructs for building a compiler?</a></p>
+</div>
+
 <div class="answer">
-  <p>LLVM currently has full support for C and C++ source languages. These are
-  available through a special version of GCC that LLVM calls the 
-  <a href="#cfe">C Front End</a></p>
-  <p>There is an incomplete version of a Java front end available in the
-  <tt>java</tt> module. There is no documentation on this yet so
-  you'll need to download the code, compile it, and try it.</p>
-  <p>The PyPy developers are working on integrating LLVM into the PyPy backend
-  so that PyPy language can translate to LLVM.</p>
-</div>
-
-<div class="question"><p><a name="langirgen">
-  I'd like to write a self-hosting LLVM compiler. How should I interface with 
-  the LLVM middle-end optimizers and back-end code generators?
-</a></p></div>
-<div class="answer">
-  <p>Your compiler front-end will communicate with LLVM by creating a module in
-     the LLVM intermediate representation (IR) format. Assuming you want to 
-     write your language's compiler in the language itself (rather than C++), 
-     there are 3 major ways to tackle generating LLVM IR from a front-end:</p>
-  <ul>
-    <li>
-      <strong>Call into the LLVM libraries code using your language's FFI 
-              (foreign function interface).</strong>
-      <ul>
-        <li><em>for:</em> best tracks changes to the LLVM IR, .ll syntax, 
-            and .bc format</li>
-        <li><em>for:</em> enables running LLVM optimization passes without a 
-            emit/parse overhead</li>
-        <li><em>for:</em> adapts well to a JIT context</li>
-        <li><em>against:</em> lots of ugly glue code to write</li>
-      </ul>
-    </li>
-    <li>
-      <strong>Emit LLVM assembly from your compiler's native language.</strong>
-      <ul>
-        <li><em>for:</em> very straightforward to get started</li>
-        <li><em>against:</em> the .ll parser is slower than the bitcode reader 
-            when interfacing to the middle end</li>
-        <li><em>against:</em> you'll have to re-engineer the LLVM IR object 
-            model and asm writer in your language</li>
-        <li><em>against:</em> it may be harder to track changes to the IR</li>
-      </ul>
-    </li>
-    <li>
-      <strong>Emit LLVM bitcode from your compiler's native language.</strong>
-      <ul>
-        <li><em>for:</em> can use the more-efficient bitcode reader when 
-            interfacing to the middle end</li>
-        <li><em>against:</em> you'll have to re-engineer the LLVM IR object 
-            model and bitcode writer in your language</li>
-        <li><em>against:</em> it may be harder to track changes to the IR</li>
-      </ul>
-    </li>
-  </ul>
-  <p>If you go with the first option, the C bindings in include/llvm-c should
-     help a lot, since most languages have strong support for interfacing with 
-     C. The most common hurdle with calling C from managed code is interfacing
-     with the garbage collector. The C interface was designed to require very 
-     little memory management, and so is straightforward in this regard.</p>
-</div>
-
-<div class="question"><p><a name="langhlsupp">
-  What support is there for a higher level source language constructs for 
-  building a compiler?</a></p>
-</div>
-<div class="answer">
-  <p>Currently, there isn't much. LLVM supports an intermediate representation
-  which is useful for code representation but will not support the high level
-  (abstract syntax tree) representation needed by most compilers. There are no
-  facilities for lexical nor semantic analysis. There is, however, a <i>mostly
-    implemented</i> configuration-driven 
-  <a href="CompilerDriver.html">compiler driver</a> which simplifies the task
-  of running optimizations, linking, and executable generation.</p>
+<p>Currently, there isn't much. LLVM supports an intermediate representation
+   which is useful for code representation but will not support the high level
+   (abstract syntax tree) representation needed by most compilers. There are no
+   facilities for lexical nor semantic analysis. There is, however, a <i>mostly
+   implemented</i> configuration-driven
+   <a href="CompilerDriver.html">compiler driver</a> which simplifies the task
+   of running optimizations, linking, and executable generation.</p>
 </div>
 
-<div class="question"><p><a name="getelementptr">
-  I don't understand the GetElementPtr instruction. Help!</a></p>
+<div class="question">
+<p><a name="getelementptr">I don't understand the GetElementPtr
+   instruction. Help!</a></p>
 </div>
+
 <div class="answer">
-  <p>See <a href="GetElementPtr.html">The Often Misunderstood GEP
+<p>See <a href="GetElementPtr.html">The Often Misunderstood GEP
    Instruction</a>.</p>
 </div>
 
@@ -500,51 +533,44 @@
 </div>
 
 <div class="question">
-<p>
-When I compile software that uses a configure script, the configure script
-thinks my system has all of the header files and libraries it is testing for.
-How do I get configure to work correctly?
-</p>
+<p>When I compile software that uses a configure script, the configure script
+   thinks my system has all of the header files and libraries it is testing for.
+   How do I get configure to work correctly?</p>
 </div>
 
 <div class="answer">
-<p>
-The configure script is getting things wrong because the LLVM linker allows
-symbols to be undefined at link time (so that they can be resolved during JIT
-or translation to the C back end).  That is why configure thinks your system
-"has everything."
-</p>
-<p>
-To work around this, perform the following steps:
-</p>
+<p>The configure script is getting things wrong because the LLVM linker allows
+   symbols to be undefined at link time (so that they can be resolved during JIT
+   or translation to the C back end).  That is why configure thinks your system
+   "has everything."</p>
+
+<p>To work around this, perform the following steps:</p>
+
 <ol>
-  <li>Make sure the CC and CXX environment variables contains the full path to 
-  the LLVM GCC front end.</li>
+  <li>Make sure the CC and CXX environment variables contains the full path to
+      the LLVM GCC front end.</li>
 
   <li>Make sure that the regular C compiler is first in your PATH. </li>
 
   <li>Add the string "-Wl,-native" to your CFLAGS environment variable.</li>
 </ol>
 
-<p>
-This will allow the <tt>llvm-ld</tt> linker to create a native code executable 
-instead of shell script that runs the JIT.  Creating native code requires 
-standard linkage, which in turn will allow the configure script to find out if 
-code is not linking on your system because the feature isn't available on your 
-system.</p>
+<p>This will allow the <tt>llvm-ld</tt> linker to create a native code
+   executable instead of shell script that runs the JIT.  Creating native code
+   requires standard linkage, which in turn will allow the configure script to
+   find out if code is not linking on your system because the feature isn't
+   available on your system.</p>
 </div>
 
 <div class="question">
-<p>
-When I compile code using the LLVM GCC front end, it complains that it cannot
-find libcrtend.a.
+<p>When I compile code using the LLVM GCC front end, it complains that it cannot
+   find libcrtend.a.
 </p>
 </div>
 
 <div class="answer">
-<p>
-The only way this can happen is if you haven't installed the runtime library. To
-correct this, do:</p>
+<p>The only way this can happen is if you haven't installed the runtime
+   library. To correct this, do:</p>
 
 <pre class="doc_code">
 % cd llvm/runtime
@@ -553,33 +579,28 @@
 </div>
 
 <div class="question">
-<p>
-How can I disable all optimizations when compiling code using the LLVM GCC front end?
-</p>
+<p>How can I disable all optimizations when compiling code using the LLVM GCC
+   front end?</p>
 </div>
 
 <div class="answer">
-<p>
-Passing "-Wa,-disable-opt -Wl,-disable-opt" will disable *all* cleanup and
-optimizations done at the llvm level, leaving you with the truly horrible
-code that you desire.
-</p>
+<p>Passing "-Wa,-disable-opt -Wl,-disable-opt" will disable *all* cleanup and
+   optimizations done at the llvm level, leaving you with the truly horrible
+   code that you desire.</p>
 </div>
 
 
 <div class="question">
-<p>
-<a name="translatecxx">Can I use LLVM to convert C++ code to C code?</a>
-</p>
+<p><a name="translatecxx">Can I use LLVM to convert C++ code to C code?</a></p>
 </div>
 
 <div class="answer">
 <p>Yes, you can use LLVM to convert code from any language LLVM supports to C.
-Note that the generated C code will be very low level (all loops are lowered
-to gotos, etc) and not very pretty (comments are stripped, original source
-formatting is totally lost, variables are renamed, expressions are regrouped), 
-so this may not be what you're looking for. Also, there are several
-limitations noted below.<p>
+   Note that the generated C code will be very low level (all loops are lowered
+   to gotos, etc) and not very pretty (comments are stripped, original source
+   formatting is totally lost, variables are renamed, expressions are
+   regrouped), so this may not be what you're looking for. Also, there are
+   several limitations noted below.<p>
 
 <p>Use commands like this:</p>
 
@@ -590,7 +611,7 @@
 % llvm-g++ x.cpp -o program
 </pre>
 
-  <p>or:</p>
+      <p>or:</p>
 
 <pre class="doc_code">
 % llvm-g++ a.cpp -c
@@ -608,7 +629,7 @@
 % llc -march=c program.bc -o program.c
 </pre></li>
 
-<li><p>Finally, compile the C file:</p>
+  <li><p>Finally, compile the C file:</p>
 
 <pre class="doc_code">
 % cc x.c
@@ -616,56 +637,51 @@
 
 </ol>
 
-<p>Using LLVM does not eliminate the need for C++ library support.
-If you use the llvm-g++ front-end, the generated code will depend on
-g++'s C++ support libraries in the same way that code generated from
-g++ would.  If you use another C++ front-end, the generated code will
-depend on whatever library that front-end would normally require.</p>
-
-<p>If you are working on a platform that does not provide any C++
-libraries, you may be able to manually compile libstdc++ to LLVM
-bitcode, statically link it into your program, then use the commands above to
-convert the whole result into C code.  Alternatively, you might compile the
-libraries and your application into two different chunks of C code and link
-them.</p>
-
-<p>Note that, by default, the C back end does not support exception handling.  If
-you want/need it for a certain program, you can enable it by passing
-"-enable-correct-eh-support" to the llc program.  The resultant code will use
-setjmp/longjmp to implement exception support that is relatively slow, and
-not C++-ABI-conforming on most platforms, but otherwise correct.</p>
-
-<p>Also, there are a number of other limitations of the C backend that
-cause it to produce code that does not fully conform to the C++ ABI on
-most platforms. Some of the C++ programs in LLVM's test suite are known
-to fail when compiled with the C back end because of ABI incompatiblities
-with standard C++ libraries.</p>
-
+<p>Using LLVM does not eliminate the need for C++ library support.  If you use
+   the llvm-g++ front-end, the generated code will depend on g++'s C++ support
+   libraries in the same way that code generated from g++ would.  If you use
+   another C++ front-end, the generated code will depend on whatever library
+   that front-end would normally require.</p>
+
+<p>If you are working on a platform that does not provide any C++ libraries, you
+   may be able to manually compile libstdc++ to LLVM bitcode, statically link it
+   into your program, then use the commands above to convert the whole result
+   into C code.  Alternatively, you might compile the libraries and your
+   application into two different chunks of C code and link them.</p>
+
+<p>Note that, by default, the C back end does not support exception handling.
+   If you want/need it for a certain program, you can enable it by passing
+   "-enable-correct-eh-support" to the llc program.  The resultant code will use
+   setjmp/longjmp to implement exception support that is relatively slow, and
+   not C++-ABI-conforming on most platforms, but otherwise correct.</p>
+
+<p>Also, there are a number of other limitations of the C backend that cause it
+   to produce code that does not fully conform to the C++ ABI on most
+   platforms. Some of the C++ programs in LLVM's test suite are known to fail
+   when compiled with the C back end because of ABI incompatiblities with
+   standard C++ libraries.</p>
 </div>
 
 <div class="question">
-<p>
-<a name="platformindependent">Can I compile C or C++ code to platform-independent LLVM bitcode?</a>
-</p>
+<p><a name="platformindependent">Can I compile C or C++ code to
+   platform-independent LLVM bitcode?</a></p>
 </div>
 
 <div class="answer">
-
-<p>No. C and C++ are inherently platform-dependent languages. The most
-obvious example of this is the preprocessor. A very common way that C code
-is made portable is by using the preprocessor to include platform-specific
-code. In practice, information about other platforms is lost after
-preprocessing, so the result is inherently dependent on the platform that
-the preprocessing was targetting.</p>
-
-<p>Another example is <tt>sizeof</tt>. It's common for <tt>sizeof(long)</tt>
-to vary between platforms. In most C front-ends, <tt>sizeof</tt> is expanded
-to a constant immediately, thus hardwaring a platform-specific detail.</p>
-
-<p>Also, since many platforms define their ABIs in terms of C, and since
-LLVM is lower-level than C, front-ends currently must emit platform-specific
-IR in order to have the result conform to the platform ABI.</p>
-
+<p>No. C and C++ are inherently platform-dependent languages. The most obvious
+   example of this is the preprocessor. A very common way that C code is made
+   portable is by using the preprocessor to include platform-specific code. In
+   practice, information about other platforms is lost after preprocessing, so
+   the result is inherently dependent on the platform that the preprocessing was
+   targetting.</p>
+
+<p>Another example is <tt>sizeof</tt>. It's common for <tt>sizeof(long)</tt> to
+   vary between platforms. In most C front-ends, <tt>sizeof</tt> is expanded to
+   a constant immediately, thus hardwaring a platform-specific detail.</p>
+
+<p>Also, since many platforms define their ABIs in terms of C, and since LLVM is
+   lower-level than C, front-ends currently must emit platform-specific IR in
+   order to have the result conform to the platform ABI.</p>
 </div>
 
 <!-- *********************************************************************** -->
@@ -674,77 +690,71 @@
 </div>
 
 <div class="question">
-<a name="iosinit"></a>
-<p> What is this <tt>llvm.global_ctors</tt> and
-<tt>_GLOBAL__I__tmp_webcompile...</tt> stuff that happens when I #include
-&lt;iostream&gt;?</p>
+<p><a name="iosinit">What is this <tt>llvm.global_ctors</tt> and
+   <tt>_GLOBAL__I__tmp_webcompile...</tt> stuff that happens when I <tt>#include
+   &lt;iostream&gt;</tt>?</a></p>
 </div>
 
 <div class="answer">
-
-<p>If you #include the &lt;iostream&gt; header into a C++ translation unit, the
-file will probably use the <tt>std::cin</tt>/<tt>std::cout</tt>/... global
-objects.  However, C++ does not guarantee an order of initialization between
-static objects in different translation units, so if a static ctor/dtor in your
-.cpp file used <tt>std::cout</tt>, for example, the object would not necessarily
-be automatically initialized before your use.</p>
+<p>If you <tt>#include</tt> the <tt>&lt;iostream&gt;</tt> header into a C++
+   translation unit, the file will probably use
+   the <tt>std::cin</tt>/<tt>std::cout</tt>/... global objects.  However, C++
+   does not guarantee an order of initialization between static objects in
+   different translation units, so if a static ctor/dtor in your .cpp file
+   used <tt>std::cout</tt>, for example, the object would not necessarily be
+   automatically initialized before your use.</p>
 
 <p>To make <tt>std::cout</tt> and friends work correctly in these scenarios, the
-STL that we use declares a static object that gets created in every translation
-unit that includes <tt>&lt;iostream&gt;</tt>.  This object has a static
-constructor and destructor that initializes and destroys the global iostream
-objects before they could possibly be used in the file.  The code that you see
-in the .ll file corresponds to the constructor and destructor registration code.
+   STL that we use declares a static object that gets created in every
+   translation unit that includes <tt>&lt;iostream&gt;</tt>.  This object has a
+   static constructor and destructor that initializes and destroys the global
+   iostream objects before they could possibly be used in the file.  The code
+   that you see in the .ll file corresponds to the constructor and destructor
+   registration code.
 </p>
 
 <p>If you would like to make it easier to <b>understand</b> the LLVM code
-generated by the compiler in the demo page, consider using <tt>printf()</tt>
-instead of <tt>iostream</tt>s to print values.</p>
-
+   generated by the compiler in the demo page, consider using <tt>printf()</tt>
+   instead of <tt>iostream</tt>s to print values.</p>
 </div>
 
 <!--=========================================================================-->
 
-<div class="question"><p>
-<a name="codedce"></a>
-Where did all of my code go??
-</p></div>
+<div class="question">
+<p><a name="codedce">Where did all of my code go??</a></p>
+</div>
 
 <div class="answer">
-<p>
-If you are using the LLVM demo page, you may often wonder what happened to all
-of the code that you typed in.  Remember that the demo script is running the
-code through the LLVM optimizers, so if your code doesn't actually do anything
-useful, it might all be deleted.
-</p>
+<p>If you are using the LLVM demo page, you may often wonder what happened to
+   all of the code that you typed in.  Remember that the demo script is running
+   the code through the LLVM optimizers, so if your code doesn't actually do
+   anything useful, it might all be deleted.</p>
 
-<p>
-To prevent this, make sure that the code is actually needed.  For example, if
-you are computing some expression, return the value from the function instead of
-leaving it in a local variable.  If you really want to constrain the optimizer,
-you can read from and assign to <tt>volatile</tt> global variables.
-</p>
+<p>To prevent this, make sure that the code is actually needed.  For example, if
+   you are computing some expression, return the value from the function instead
+   of leaving it in a local variable.  If you really want to constrain the
+   optimizer, you can read from and assign to <tt>volatile</tt> global
+   variables.</p>
 </div>
 
 <!--=========================================================================-->
 
-<div class="question"><p>
-<a name="undef"></a>
-<p>What is this "<tt>undef</tt>" thing that shows up in my code?
-</p></div>
+<div class="question">
+<p><a name="undef">What is this "<tt>undef</tt>" thing that shows up in my
+   code?</p>
+</div>
 
 <div class="answer">
-<p>
-<a href="LangRef.html#undef"><tt>undef</tt></a> is the LLVM way of representing
-a value that is not defined.  You can get these if you do not initialize a 
-variable before you use it.  For example, the C function:</p>
+<p><a href="LangRef.html#undef"><tt>undef</tt></a> is the LLVM way of
+   representing a value that is not defined.  You can get these if you do not
+   initialize a variable before you use it.  For example, the C function:</p>
 
 <pre class="doc_code">
 int X() { int i; return i; }
 </pre>
 
-<p>Is compiled to "<tt>ret i32 undef</tt>" because "<tt>i</tt>" never has
-a value specified for it.</p>
+<p>Is compiled to "<tt>ret i32 undef</tt>" because "<tt>i</tt>" never has a
+   value specified for it.</p>
 </div>
 
 <!-- *********************************************************************** -->




From gohman at apple.com  Tue Apr  7 13:43:59 2009
From: gohman at apple.com (Dan Gohman)
Date: Tue, 07 Apr 2009 18:43:59 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r68529 -
	/llvm-gcc-4.2/trunk/README.LLVM
Message-ID: <200904071843.n37Ihx2o022402@zion.cs.uiuc.edu>

Author: djg
Date: Tue Apr  7 13:43:59 2009
New Revision: 68529

URL: http://llvm.org/viewvc/llvm-project?rev=68529&view=rev
Log:
Add a note about srcdir==objdir being broken. This is not as nice
as fixing the problem, but it may at least help someone avoid
trouble.

Modified:
    llvm-gcc-4.2/trunk/README.LLVM

Modified: llvm-gcc-4.2/trunk/README.LLVM
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/README.LLVM?rev=68529&r1=68528&r2=68529&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/README.LLVM (original)
+++ llvm-gcc-4.2/trunk/README.LLVM Tue Apr  7 13:43:59 2009
@@ -129,6 +129,10 @@
 $ make $BUILDOPTIONS
 $ make install
 
+Note that it is currently necessary to use a separate object directory for
+building llvm-gcc. Running configure and make from within the llvm-gcc
+source directory does not work.
+
 //===-----------------------
 Darwin/Mac OS X Specific part:
 




From isanbard at gmail.com  Tue Apr  7 13:51:13 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 07 Apr 2009 18:51:13 -0000
Subject: [llvm-commits] [llvm] r68530 - /llvm/trunk/docs/FAQ.html
Message-ID: <200904071851.n37IpDBC022704@zion.cs.uiuc.edu>

Author: void
Date: Tue Apr  7 13:51:13 2009
New Revision: 68530

URL: http://llvm.org/viewvc/llvm-project?rev=68530&view=rev
Log:
Offer an explanation of why building LLVM-GCC with objdir == srcdir doesn't
work.

Modified:
    llvm/trunk/docs/FAQ.html

Modified: llvm/trunk/docs/FAQ.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/FAQ.html?rev=68530&r1=68529&r2=68530&view=diff

==============================================================================
--- llvm/trunk/docs/FAQ.html (original)
+++ llvm/trunk/docs/FAQ.html Tue Apr  7 13:51:13 2009
@@ -74,6 +74,9 @@
 
     <li><a href="#llvmc">The <tt>llvmc</tt> program gives me errors/doesn't
         work.</a></li>
+
+    <li><a href="#srcdir-objdir">When I compile LLVM-GCC with srcdir == objdir,
+        it fails. Why?</a></li>
   </ol></li>
 
   <li><a href="#felangs">Source Languages</a>
@@ -412,8 +415,9 @@
    rebuilding.</p>
 </div>
 
-<div class="question"><p><a name="llvmc">
-<p>The <tt>llvmc</tt> program gives me errors/doesn't work.</a></p>
+<div class="question">
+<p><a name="llvmc">The <tt>llvmc</tt> program gives me errors/doesn't
+   work.</a></p>
 </div>
 
 <div class="answer">
@@ -421,6 +425,25 @@
    using <tt>llvm-gcc</tt> instead.</p>
 </div>
 
+<div class="question">
+<p><a href="srcdir-objdir">When I compile LLVM-GCC with srcdir == objdir, it
+   fails. Why?</a></p>
+</div>
+
+<div class="answer">
+<p>The <tt>GNUmakefile</tt> in the top-level directory of LLVM-GCC is a special
+   <tt>Makefile</tt> used by Apple to invoke the <tt>build_gcc</tt> script after
+   setting up a special environment. This has the unforunate side-effect that
+   trying to build LLVM-GCC with srcdir == objdir in a "non-Apple way" invokes
+   the <tt>GNUmakefile</tt> instead of <tt>Makefile</tt>. Because the
+   environment isn't set up correctly to do this, the build fails.</p>
+
+<p>People not building LLVM-GCC the "Apple way" need to build LLVM-GCC with
+   srcdir != objdir, or simply remove the GNUmakefile entirely.</p>
+
+<p>We regret the inconvenience.</p>
+</div>
+
 <!-- *********************************************************************** -->
 <div class="doc_section"><a name="felangs">Source Languages</a></div>
 




From isanbard at gmail.com  Tue Apr  7 13:52:32 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 07 Apr 2009 18:52:32 -0000
Subject: [llvm-commits] [llvm] r68531 - /llvm/trunk/docs/FAQ.html
Message-ID: <200904071852.n37IqWKk022766@zion.cs.uiuc.edu>

Author: void
Date: Tue Apr  7 13:52:30 2009
New Revision: 68531

URL: http://llvm.org/viewvc/llvm-project?rev=68531&view=rev
Log:
Fix verification failure.

Modified:
    llvm/trunk/docs/FAQ.html

Modified: llvm/trunk/docs/FAQ.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/FAQ.html?rev=68531&r1=68530&r2=68531&view=diff

==============================================================================
--- llvm/trunk/docs/FAQ.html (original)
+++ llvm/trunk/docs/FAQ.html Tue Apr  7 13:52:30 2009
@@ -764,7 +764,7 @@
 
 <div class="question">
 <p><a name="undef">What is this "<tt>undef</tt>" thing that shows up in my
-   code?</p>
+   code?</a></p>
 </div>
 
 <div class="answer">




From isanbard at gmail.com  Tue Apr  7 13:54:06 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 07 Apr 2009 18:54:06 -0000
Subject: [llvm-commits] [llvm] r68534 - /llvm/trunk/docs/FAQ.html
Message-ID: <200904071854.n37Is6aP022839@zion.cs.uiuc.edu>

Author: void
Date: Tue Apr  7 13:54:06 2009
New Revision: 68534

URL: http://llvm.org/viewvc/llvm-project?rev=68534&view=rev
Log:
Use 'name' instead of 'href'.

Modified:
    llvm/trunk/docs/FAQ.html

Modified: llvm/trunk/docs/FAQ.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/FAQ.html?rev=68534&r1=68533&r2=68534&view=diff

==============================================================================
--- llvm/trunk/docs/FAQ.html (original)
+++ llvm/trunk/docs/FAQ.html Tue Apr  7 13:54:06 2009
@@ -426,7 +426,7 @@
 </div>
 
 <div class="question">
-<p><a href="srcdir-objdir">When I compile LLVM-GCC with srcdir == objdir, it
+<p><a name="srcdir-objdir">When I compile LLVM-GCC with srcdir == objdir, it
    fails. Why?</a></p>
 </div>
 




From edwintorok at gmail.com  Tue Apr  7 14:34:48 2009
From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=)
Date: Tue, 07 Apr 2009 22:34:48 +0300
Subject: [llvm-commits] [llvm] r68530 - /llvm/trunk/docs/FAQ.html
In-Reply-To: <200904071851.n37IpDBC022704@zion.cs.uiuc.edu>
References: <200904071851.n37IpDBC022704@zion.cs.uiuc.edu>
Message-ID: <49DBAAD8.8050500@gmail.com>

On 2009-04-07 21:51, Bill Wendling wrote:
> Author: void
> Date: Tue Apr  7 13:51:13 2009
> New Revision: 68530
>
> URL: http://llvm.org/viewvc/llvm-project?rev=68530&view=rev
> Log:
> Offer an explanation of why building LLVM-GCC with objdir == srcdir doesn't
> work.
>
> Modified:
>     llvm/trunk/docs/FAQ.html
>
> Modified: llvm/trunk/docs/FAQ.html
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/FAQ.html?rev=68530&r1=68529&r2=68530&view=diff
>
> ==============================================================================
> --- llvm/trunk/docs/FAQ.html (original)
> +++ llvm/trunk/docs/FAQ.html Tue Apr  7 13:51:13 2009
> @@ -74,6 +74,9 @@
>  
>      <li><a href="#llvmc">The <tt>llvmc</tt> program gives me errors/doesn't
>          work.</a></li>
> +
> +    <li><a href="#srcdir-objdir">When I compile LLVM-GCC with srcdir == objdir,
> +        it fails. Why?</a></li>
>    </ol></li>
>  
>    <li><a href="#felangs">Source Languages</a>
> @@ -412,8 +415,9 @@
>     rebuilding.</p>
>  </div>
>  
> -<div class="question"><p><a name="llvmc">
> -<p>The <tt>llvmc</tt> program gives me errors/doesn't work.</a></p>
> +<div class="question">
> +<p><a name="llvmc">The <tt>llvmc</tt> program gives me errors/doesn't
> +   work.</a></p>
>  </div>
>  
>  <div class="answer">
> @@ -421,6 +425,25 @@
>     using <tt>llvm-gcc</tt> instead.</p>
>  </div>
>  
> +<div class="question">
> +<p><a href="srcdir-objdir">When I compile LLVM-GCC with srcdir == objdir, it
> +   fails. Why?</a></p>
> +</div>
> +
> +<div class="answer">
> +<p>The <tt>GNUmakefile</tt> in the top-level directory of LLVM-GCC is a special
> +   <tt>Makefile</tt> used by Apple to invoke the <tt>build_gcc</tt> script after
> +   setting up a special environment. 

Maybe I am missing something, but why not simply make build_gcc call
"make -f GNUMakefile.Apple"?


Best regards,
--Edwin


From edwintorok at gmail.com  Tue Apr  7 14:45:59 2009
From: edwintorok at gmail.com (Torok Edwin)
Date: Tue, 07 Apr 2009 19:45:59 -0000
Subject: [llvm-commits] [llvm] r68542 - /llvm/trunk/lib/VMCore/Type.cpp
Message-ID: <200904071945.n37JjxUI024867@zion.cs.uiuc.edu>

Author: edwin
Date: Tue Apr  7 14:45:59 2009
New Revision: 68542

URL: http://llvm.org/viewvc/llvm-project?rev=68542&view=rev
Log:
fix style.

Modified:
    llvm/trunk/lib/VMCore/Type.cpp

Modified: llvm/trunk/lib/VMCore/Type.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Type.cpp?rev=68542&r1=68541&r2=68542&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/Type.cpp (original)
+++ llvm/trunk/lib/VMCore/Type.cpp Tue Apr  7 14:45:59 2009
@@ -672,9 +672,9 @@
 public:
   ~TypeMapBase()
   {
-    //PATypeHolder won't destroy non-abstract types.
-    //We can't destroy them by simply iterating,  because
-    //they may contain references to each-other
+    // PATypeHolder won't destroy non-abstract types.
+    // We can't destroy them by simply iterating, because
+    // they may contain references to each-other.
 
     for (std::multimap<unsigned, PATypeHolder>::iterator I
          = TypesByHash.begin(), E = TypesByHash.end(); I != E; ++I) {




From edwintorok at gmail.com  Tue Apr  7 14:46:37 2009
From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=)
Date: Tue, 07 Apr 2009 22:46:37 +0300
Subject: [llvm-commits] [llvm] r68523 - in /llvm/trunk:
 examples/HowToUseJIT/HowToUseJIT.cpp include/llvm/AbstractTypeUser.h
 lib/VMCore/Type.cpp
In-Reply-To: <200904072036.50777.baldrick@free.fr>
References: <200904071723.n37HN4s8018418@zion.cs.uiuc.edu>
	<200904072036.50777.baldrick@free.fr>
Message-ID: <49DBAD9D.5040502@gmail.com>

On 2009-04-07 21:36, Duncan Sands wrote:
> Hi Edwin,
>
>   
>> +    //PATypeHolder won't destroy non-abstract types.
>> +    //We can't destroy them by simply iterating,  because
>> +    //they may contain references to each-other
>>     
>
> there should be a space after //.
>   

Fixed.

Thanks,
--Edwin


From mrs at apple.com  Tue Apr  7 15:29:25 2009
From: mrs at apple.com (Mike Stump)
Date: Tue, 07 Apr 2009 20:29:25 -0000
Subject: [llvm-commits] [llvm] r68544 - /llvm/trunk/Makefile
Message-ID: <200904072029.n37KTQba026482@zion.cs.uiuc.edu>

Author: mrs
Date: Tue Apr  7 15:29:25 2009
New Revision: 68544

URL: http://llvm.org/viewvc/llvm-project?rev=68544&view=rev
Log:
Remove ccc now.  Radar 6737767

Modified:
    llvm/trunk/Makefile

Modified: llvm/trunk/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile?rev=68544&r1=68543&r2=68544&view=diff

==============================================================================
--- llvm/trunk/Makefile (original)
+++ llvm/trunk/Makefile Tue Apr  7 15:29:25 2009
@@ -56,7 +56,7 @@
 
 ifeq ($(MAKECMDGOALS),install-clang)
   DIRS := tools/clang/tools/driver tools/clang/tools/clang-cc \
-	tools/clang/lib/Headers tools/clang/tools/ccc
+	tools/clang/lib/Headers
   OPTIONAL_DIRS :=
   NO_INSTALL = 1
 endif




From grosbach at apple.com  Tue Apr  7 15:34:09 2009
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 07 Apr 2009 20:34:09 -0000
Subject: [llvm-commits] [llvm] r68545 - in /llvm/trunk:
 include/llvm/Target/TargetRegisterInfo.h lib/Target/ARM/ARMISelDAGToDAG.cpp
 lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.cpp
 lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/ARMRegisterInfo.cpp
 lib/Target/ARM/ARMRegisterInfo.h lib/Target/ARM/ARMRegisterInfo.td
Message-ID: <200904072034.n37KYAJU026667@zion.cs.uiuc.edu>

Author: grosbach
Date: Tue Apr  7 15:34:09 2009
New Revision: 68545

URL: http://llvm.org/viewvc/llvm-project?rev=68545&view=rev
Log:
PR2985 / <rdar://problem/6584986>

When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.


Modified:
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h
    llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=68545&r1=68544&r2=68545&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Tue Apr  7 15:34:09 2009
@@ -273,8 +273,8 @@
   /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
   /// register of the given type. If type is MVT::Other, then just return any
   /// register class the register belongs to.
-  const TargetRegisterClass *getPhysicalRegisterRegClass(unsigned Reg,
-                                          MVT VT = MVT::Other) const;
+  virtual const TargetRegisterClass *
+    getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
 
   /// getAllocatableSet - Returns a bitset indexed by register number
   /// indicating if a register is allocatable or not. If a register class is

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=68545&r1=68544&r2=68545&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Apr  7 15:34:09 2009
@@ -584,10 +584,10 @@
     // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
     int FI = cast<FrameIndexSDNode>(N)->getIndex();
     SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
-    if (Subtarget->isThumb())
+    if (Subtarget->isThumb()) {
       return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
                                   CurDAG->getTargetConstant(0, MVT::i32));
-    else {
+    } else {
       SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
                           getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
                           CurDAG->getRegister(0, MVT::i32) };
@@ -607,7 +607,9 @@
       std::swap(LHSR, RHSR);
     }
     if (RHSR && RHSR->getReg() == ARM::SP) {
-      return CurDAG->SelectNodeTo(N, ARM::tADDhirr, Op.getValueType(), N0, N1);
+      SDValue Val = SDValue(CurDAG->getTargetNode(ARM::tMOVlor2hir, dl,
+                                  Op.getValueType(), N0, N0), 0);
+      return CurDAG->SelectNodeTo(N, ARM::tADDhirr, Op.getValueType(), Val, N1);
     }
     break;
   }

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=68545&r1=68544&r2=68545&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Apr  7 15:34:09 2009
@@ -117,7 +117,10 @@
     }
   }
 
-  addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
+  if (Subtarget->isThumb())
+    addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
+  else
+    addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
   if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
     addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
     addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
@@ -937,6 +940,7 @@
   MVT ObjectVT = Op.getValue(ArgNo).getValueType();
   SDValue Root = Op.getOperand(0);
   MachineRegisterInfo &RegInfo = MF.getRegInfo();
+  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
 
   static const unsigned GPRArgRegs[] = {
     ARM::R0, ARM::R1, ARM::R2, ARM::R3
@@ -955,17 +959,28 @@
 
   SDValue ArgValue;
   if (ObjGPRs == 1) {
-    unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
+    unsigned VReg;
+    if (AFI->isThumbFunction())
+      VReg = RegInfo.createVirtualRegister(ARM::tGPRRegisterClass);
+    else
+      VReg = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
     RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
     ArgValue = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
     if (ObjectVT == MVT::f32)
       ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
   } else if (ObjGPRs == 2) {
-    unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
+    unsigned VReg;
+    if (AFI->isThumbFunction())
+      VReg = RegInfo.createVirtualRegister(ARM::tGPRRegisterClass);
+    else
+      VReg = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
     RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
     ArgValue = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
 
-    VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
+    if (AFI->isThumbFunction())
+      VReg = RegInfo.createVirtualRegister(ARM::tGPRRegisterClass);
+    else
+      VReg = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
     RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
     SDValue ArgValue2 = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
 
@@ -1029,7 +1044,11 @@
 
       SmallVector<SDValue, 4> MemOps;
       for (; NumGPRs < 4; ++NumGPRs) {
-        unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
+        unsigned VReg;
+        if (AFI->isThumbFunction())
+          VReg = RegInfo.createVirtualRegister(ARM::tGPRRegisterClass);
+        else
+          VReg = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
         RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
         SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
         SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
@@ -1965,8 +1984,10 @@
     // GCC RS6000 Constraint Letters
     switch (Constraint[0]) {
     case 'l':
-    // FIXME: in thumb mode, 'l' is only low-regs.
-    // FALL THROUGH.
+      if (Subtarget->isThumb())
+        return std::make_pair(0U, ARM::tGPRRegisterClass);
+      else
+        return std::make_pair(0U, ARM::GPRRegisterClass);
     case 'r':
       return std::make_pair(0U, ARM::GPRRegisterClass);
     case 'w':
@@ -1989,6 +2010,9 @@
   switch (Constraint[0]) {      // GCC ARM Constraint Letters
   default: break;
   case 'l':
+    return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+                                 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
+                                 0);
   case 'r':
     return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
                                  ARM::R4, ARM::R5, ARM::R6, ARM::R7,

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=68545&r1=68544&r2=68545&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Tue Apr  7 15:34:09 2009
@@ -64,6 +64,9 @@
     return true;
   case ARM::MOVr:
   case ARM::tMOVr:
+  case ARM::tMOVhir2lor:
+  case ARM::tMOVlor2hir:
+  case ARM::tMOVhir2hir:
     assert(MI.getDesc().getNumOperands() >= 2 &&
            MI.getOperand(0).isReg() &&
            MI.getOperand(1).isReg() &&
@@ -483,23 +486,43 @@
                                 unsigned DestReg, unsigned SrcReg,
                                 const TargetRegisterClass *DestRC,
                                 const TargetRegisterClass *SrcRC) const {
+  MachineFunction &MF = *MBB.getParent();
+  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
+  DebugLoc DL = DebugLoc::getUnknownLoc();
+  if (I != MBB.end()) DL = I->getDebugLoc();
+
+  if (!AFI->isThumbFunction()) {
+    if (DestRC == ARM::GPRRegisterClass) {
+      AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
+                                  .addReg(SrcReg)));
+      return true;
+    }
+  } else {
+    if (DestRC == ARM::GPRRegisterClass) {
+      if (SrcRC == ARM::GPRRegisterClass) {
+        BuildMI(MBB, I, DL, get(ARM::tMOVhir2hir), DestReg).addReg(SrcReg);
+        return true;
+      } else if (SrcRC == ARM::tGPRRegisterClass) {
+        BuildMI(MBB, I, DL, get(ARM::tMOVlor2hir), DestReg).addReg(SrcReg);
+        return true;
+      }
+    } else if (DestRC == ARM::tGPRRegisterClass) {
+      if (SrcRC == ARM::GPRRegisterClass) {
+        BuildMI(MBB, I, DL, get(ARM::tMOVhir2lor), DestReg).addReg(SrcReg);
+        return true;
+      } else if (SrcRC == ARM::tGPRRegisterClass) {
+        BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
+        return true;
+      }
+    }
+  }
   if (DestRC != SrcRC) {
     // Not yet supported!
     return false;
   }
 
-  DebugLoc DL = DebugLoc::getUnknownLoc();
-  if (I != MBB.end()) DL = I->getDebugLoc();
 
-  if (DestRC == ARM::GPRRegisterClass) {
-    MachineFunction &MF = *MBB.getParent();
-    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
-    if (AFI->isThumbFunction())
-      BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
-    else
-      AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
-                                  .addReg(SrcReg)));
-  } else if (DestRC == ARM::SPRRegisterClass)
+  if (DestRC == ARM::SPRRegisterClass)
     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
                    .addReg(SrcReg));
   else if (DestRC == ARM::DPRRegisterClass)
@@ -521,14 +544,17 @@
   if (RC == ARM::GPRRegisterClass) {
     MachineFunction &MF = *MBB.getParent();
     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
-    if (AFI->isThumbFunction())
-      BuildMI(MBB, I, DL, get(ARM::tSpill))
-        .addReg(SrcReg, false, false, isKill)
-        .addFrameIndex(FI).addImm(0);
-    else
-      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
-                     .addReg(SrcReg, false, false, isKill)
-                     .addFrameIndex(FI).addReg(0).addImm(0));
+    assert (!AFI->isThumbFunction());
+    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
+                   .addReg(SrcReg, false, false, isKill)
+                   .addFrameIndex(FI).addReg(0).addImm(0));
+  } else if (RC == ARM::tGPRRegisterClass) {
+    MachineFunction &MF = *MBB.getParent();
+    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
+    assert (AFI->isThumbFunction());
+    BuildMI(MBB, I, DL, get(ARM::tSpill))
+      .addReg(SrcReg, false, false, isKill)
+      .addFrameIndex(FI).addImm(0);
   } else if (RC == ARM::DPRRegisterClass) {
     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
                    .addReg(SrcReg, false, false, isKill)
@@ -586,12 +612,15 @@
   if (RC == ARM::GPRRegisterClass) {
     MachineFunction &MF = *MBB.getParent();
     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
-    if (AFI->isThumbFunction())
-      BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
-        .addFrameIndex(FI).addImm(0);
-    else
-      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
-                     .addFrameIndex(FI).addReg(0).addImm(0));
+    assert (!AFI->isThumbFunction());
+    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
+                   .addFrameIndex(FI).addReg(0).addImm(0));
+  } else if (RC == ARM::tGPRRegisterClass) {
+    MachineFunction &MF = *MBB.getParent();
+    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
+    assert (AFI->isThumbFunction());
+    BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
+      .addFrameIndex(FI).addImm(0);
   } else if (RC == ARM::DPRRegisterClass) {
     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
                    .addFrameIndex(FI).addImm(0));
@@ -715,7 +744,10 @@
     }
     break;
   }
-  case ARM::tMOVr: {
+  case ARM::tMOVr:
+  case ARM::tMOVlor2hir:
+  case ARM::tMOVhir2lor:
+  case ARM::tMOVhir2hir: {
     if (OpNum == 0) { // move -> store
       unsigned SrcReg = MI->getOperand(1).getReg();
       bool isKill = MI->getOperand(1).isKill();
@@ -788,7 +820,10 @@
   case ARM::MOVr:
     // If it is updating CPSR, then it cannot be folded.
     return MI->getOperand(4).getReg() != ARM::CPSR;
-  case ARM::tMOVr: {
+  case ARM::tMOVr:
+  case ARM::tMOVlor2hir:
+  case ARM::tMOVhir2lor:
+  case ARM::tMOVhir2hir: {
     if (OpNum == 0) { // move -> store
       unsigned SrcReg = MI->getOperand(1).getReg();
       if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=68545&r1=68544&r2=68545&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Apr  7 15:34:09 2009
@@ -73,7 +73,7 @@
 def t_addrmode_rr : Operand<i32>,
                     ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
   let PrintMethod = "printThumbAddrModeRROperand";
-  let MIOperandInfo = (ops GPR:$base, GPR:$offsreg);
+  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
 }
 
 // t_addrmode_s4 := reg + reg
@@ -82,7 +82,7 @@
 def t_addrmode_s4 : Operand<i32>,
                     ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
   let PrintMethod = "printThumbAddrModeS4Operand";
-  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
+  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
 }
 
 // t_addrmode_s2 := reg + reg
@@ -91,7 +91,7 @@
 def t_addrmode_s2 : Operand<i32>,
                     ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
   let PrintMethod = "printThumbAddrModeS2Operand";
-  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
+  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
 }
 
 // t_addrmode_s1 := reg + reg
@@ -100,7 +100,7 @@
 def t_addrmode_s1 : Operand<i32>,
                     ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
   let PrintMethod = "printThumbAddrModeS1Operand";
-  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
+  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
 }
 
 // t_addrmode_sp := sp + imm8 * 4
@@ -108,7 +108,7 @@
 def t_addrmode_sp : Operand<i32>,
                     ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
   let PrintMethod = "printThumbAddrModeSPOperand";
-  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
+  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
 }
 
 //===----------------------------------------------------------------------===//
@@ -128,9 +128,9 @@
 }
 
 let isNotDuplicable = 1 in
-def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp),
+def tPICADD : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
                   "$cp:\n\tadd $dst, pc",
-                  [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
+                  [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
 
 //===----------------------------------------------------------------------===//
 //  Control Flow Instructions.
@@ -139,7 +139,7 @@
 let isReturn = 1, isTerminator = 1 in {
   def tBX_RET : TI<(outs), (ins), "bx lr", [(ARMretflag)]>;
   // Alternative return instruction used by vararg functions.
-  def tBX_RET_vararg : TI<(outs), (ins GPR:$target), "bx $target", []>;
+  def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), "bx $target", []>;
 }
 
 // FIXME: remove when we have a way to marking a MI with these properties.
@@ -157,13 +157,13 @@
   def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops),
                     "blx ${func:call}",
                     [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
-  def tBLXr : TI<(outs), (ins GPR:$func, variable_ops),
+  def tBLXr : TI<(outs), (ins tGPR:$func, variable_ops),
                   "blx $func",
-                  [(ARMtcall GPR:$func)]>, Requires<[HasV5T]>;
+                  [(ARMtcall tGPR:$func)]>, Requires<[HasV5T]>;
   // ARMv4T
-  def tBX : TIx2<(outs), (ins GPR:$func, variable_ops),
+  def tBX : TIx2<(outs), (ins tGPR:$func, variable_ops),
                   "cpy lr, pc\n\tbx $func",
-                  [(ARMcall_nolink GPR:$func)]>;
+                  [(ARMcall_nolink tGPR:$func)]>;
 }
 
 let isBranch = 1, isTerminator = 1 in {
@@ -176,9 +176,9 @@
   def tBfar : TIx2<(outs), (ins brtarget:$target), "bl $target\t@ far jump",[]>;
 
   def tBR_JTr : TJTI<(outs),
-                     (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
+                     (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
                      "cpy pc, $target \n\t.align\t2\n$jt",
-                     [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
+                     [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
   }
 }
 
@@ -193,68 +193,68 @@
 //
 
 let canFoldAsLoad = 1 in
-def tLDR : TI4<(outs GPR:$dst), (ins t_addrmode_s4:$addr),
+def tLDR : TI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr),
                "ldr $dst, $addr",
-               [(set GPR:$dst, (load t_addrmode_s4:$addr))]>;
+               [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
 
-def tLDRB : TI1<(outs GPR:$dst), (ins t_addrmode_s1:$addr),
+def tLDRB : TI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr),
                 "ldrb $dst, $addr",
-                [(set GPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
+                [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
 
-def tLDRH : TI2<(outs GPR:$dst), (ins t_addrmode_s2:$addr),
+def tLDRH : TI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr),
                 "ldrh $dst, $addr",
-                [(set GPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
+                [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
 
-def tLDRSB : TI1<(outs GPR:$dst), (ins t_addrmode_rr:$addr),
+def tLDRSB : TI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
                  "ldrsb $dst, $addr",
-                 [(set GPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
+                 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
 
-def tLDRSH : TI2<(outs GPR:$dst), (ins t_addrmode_rr:$addr),
+def tLDRSH : TI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
                  "ldrsh $dst, $addr",
-                 [(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
+                 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
 
 let canFoldAsLoad = 1 in
-def tLDRspi : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
+def tLDRspi : TIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
                   "ldr $dst, $addr",
-                  [(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
+                  [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
 
 // Special instruction for restore. It cannot clobber condition register
 // when it's expanded by eliminateCallFramePseudoInstr().
 let canFoldAsLoad = 1, mayLoad = 1 in
-def tRestore : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
+def tRestore : TIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
                     "ldr $dst, $addr", []>;
 
 // Load tconstpool
 let canFoldAsLoad = 1 in
-def tLDRpci : TIs<(outs GPR:$dst), (ins i32imm:$addr),
+def tLDRpci : TIs<(outs tGPR:$dst), (ins i32imm:$addr),
                   "ldr $dst, $addr",
-                  [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
+                  [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
 
 // Special LDR for loads from non-pc-relative constpools.
 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
-def tLDRcp  : TIs<(outs GPR:$dst), (ins i32imm:$addr),
+def tLDRcp  : TIs<(outs tGPR:$dst), (ins i32imm:$addr),
                   "ldr $dst, $addr", []>;
 
-def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr),
+def tSTR : TI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr),
                "str $src, $addr",
-               [(store GPR:$src, t_addrmode_s4:$addr)]>;
+               [(store tGPR:$src, t_addrmode_s4:$addr)]>;
 
-def tSTRB : TI1<(outs), (ins GPR:$src, t_addrmode_s1:$addr),
+def tSTRB : TI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr),
                  "strb $src, $addr",
-                 [(truncstorei8 GPR:$src, t_addrmode_s1:$addr)]>;
+                 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
 
-def tSTRH : TI2<(outs), (ins GPR:$src, t_addrmode_s2:$addr),
+def tSTRH : TI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr),
                  "strh $src, $addr",
-                 [(truncstorei16 GPR:$src, t_addrmode_s2:$addr)]>;
+                 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
 
-def tSTRspi : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
+def tSTRspi : TIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
                    "str $src, $addr",
-                   [(store GPR:$src, t_addrmode_sp:$addr)]>;
+                   [(store tGPR:$src, t_addrmode_sp:$addr)]>;
 
 let mayStore = 1 in {
 // Special instruction for spill. It cannot clobber condition register
 // when it's expanded by eliminateCallFramePseudoInstr().
-def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
+def tSpill : TIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
                   "str $src, $addr", []>;
 }
 
@@ -277,205 +277,213 @@
 //
 
 // Add with carry
-def tADC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
+def tADC : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
                "adc $dst, $rhs",
-               [(set GPR:$dst, (adde GPR:$lhs, GPR:$rhs))]>;
+               [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
 
-def tADDS : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
+def tADDS : TI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
                "add $dst, $lhs, $rhs",
-               [(set GPR:$dst, (addc GPR:$lhs, GPR:$rhs))]>;
+               [(set tGPR:$dst, (addc tGPR:$lhs, tGPR:$rhs))]>;
 
 
-def tADDi3 : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
+def tADDi3 : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
                 "add $dst, $lhs, $rhs",
-                [(set GPR:$dst, (add GPR:$lhs, imm0_7:$rhs))]>;
+                [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
 
-def tADDi8 : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
+def tADDi8 : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
                  "add $dst, $rhs",
-                 [(set GPR:$dst, (add GPR:$lhs, imm8_255:$rhs))]>;
+                 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
 
-def tADDrr : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
+def tADDrr : TI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
                 "add $dst, $lhs, $rhs",
-                [(set GPR:$dst, (add GPR:$lhs, GPR:$rhs))]>;
+                [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
 
-def tADDhirr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
-                   "add $dst, $rhs", []>;
+def tADDhirr : TIt<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs),
+                   "add $dst, $rhs @ addhirr", []>;
 
-def tADDrPCi : TI<(outs GPR:$dst), (ins i32imm:$rhs),
+def tADDrPCi : TI<(outs tGPR:$dst), (ins i32imm:$rhs),
                   "add $dst, pc, $rhs * 4", []>;
-def tADDrSPi : TI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$rhs),
-                  "add $dst, $sp, $rhs * 4", []>;
-def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
+
+def tADDrSPi : TI<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs),
+                  "add $dst, $sp, $rhs * 4 @ addrspi", []>;
+
+def tADDspi : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
                   "add $dst, $rhs * 4", []>;
 
-def tAND : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
+def tAND : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
                 "and $dst, $rhs",
-                [(set GPR:$dst, (and GPR:$lhs, GPR:$rhs))]>;
+                [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
 
-def tASRri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
+def tASRri : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
                 "asr $dst, $lhs, $rhs",
-                [(set GPR:$dst, (sra GPR:$lhs, imm:$rhs))]>;
+                [(set tGPR:$dst, (sra tGPR:$lhs, imm:$rhs))]>;
 
-def tASRrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
+def tASRrr : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
                  "asr $dst, $rhs",
-                 [(set GPR:$dst, (sra GPR:$lhs, GPR:$rhs))]>;
+                 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
 
-def tBIC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
+def tBIC : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
                "bic $dst, $rhs",
-               [(set GPR:$dst, (and GPR:$lhs, (not GPR:$rhs)))]>;
+               [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
 
 
-def tCMN : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
+def tCMN : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
               "cmn $lhs, $rhs",
-              [(ARMcmp GPR:$lhs, (ineg GPR:$rhs))]>;
+              [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
 
-def tCMPi8 : TI<(outs), (ins GPR:$lhs, i32imm:$rhs),
+def tCMPi8 : TI<(outs), (ins tGPR:$lhs, i32imm:$rhs),
                "cmp $lhs, $rhs",
-               [(ARMcmp GPR:$lhs, imm0_255:$rhs)]>;
+               [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
 
-def tCMPr : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
+def tCMPr : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
                "cmp $lhs, $rhs",
-               [(ARMcmp GPR:$lhs, GPR:$rhs)]>;
+               [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
 
-def tTST  : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
+def tTST  : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
                "tst $lhs, $rhs",
-               [(ARMcmpNZ (and GPR:$lhs, GPR:$rhs), 0)]>;
+               [(ARMcmpNZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
 
-def tCMNNZ : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
+def tCMNNZ : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
                 "cmn $lhs, $rhs",
-                [(ARMcmpNZ GPR:$lhs, (ineg GPR:$rhs))]>;
+                [(ARMcmpNZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
 
-def tCMPNZi8 : TI<(outs), (ins GPR:$lhs, i32imm:$rhs),
+def tCMPNZi8 : TI<(outs), (ins tGPR:$lhs, i32imm:$rhs),
                  "cmp $lhs, $rhs",
-                 [(ARMcmpNZ GPR:$lhs, imm0_255:$rhs)]>;
+                 [(ARMcmpNZ tGPR:$lhs, imm0_255:$rhs)]>;
 
-def tCMPNZr : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
+def tCMPNZr : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
                  "cmp $lhs, $rhs",
-                 [(ARMcmpNZ GPR:$lhs, GPR:$rhs)]>;
+                 [(ARMcmpNZ tGPR:$lhs, tGPR:$rhs)]>;
 
 // TODO: A7-37: CMP(3) - cmp hi regs
 
-def tEOR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
+def tEOR : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
                "eor $dst, $rhs",
-               [(set GPR:$dst, (xor GPR:$lhs, GPR:$rhs))]>;
+               [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
 
-def tLSLri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
+def tLSLri : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
                 "lsl $dst, $lhs, $rhs",
-                [(set GPR:$dst, (shl GPR:$lhs, imm:$rhs))]>;
+                [(set tGPR:$dst, (shl tGPR:$lhs, imm:$rhs))]>;
 
-def tLSLrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
+def tLSLrr : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
                  "lsl $dst, $rhs",
-                 [(set GPR:$dst, (shl GPR:$lhs, GPR:$rhs))]>;
+                 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
 
-def tLSRri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
+def tLSRri : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
                 "lsr $dst, $lhs, $rhs",
-                [(set GPR:$dst, (srl GPR:$lhs, imm:$rhs))]>;
+                [(set tGPR:$dst, (srl tGPR:$lhs, imm:$rhs))]>;
 
-def tLSRrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
+def tLSRrr : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
                  "lsr $dst, $rhs",
-                 [(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>;
+                 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
 
 // FIXME: This is not rematerializable because mov changes the condition code.
-def tMOVi8 : TI<(outs GPR:$dst), (ins i32imm:$src),
+def tMOVi8 : TI<(outs tGPR:$dst), (ins i32imm:$src),
                  "mov $dst, $src",
-                 [(set GPR:$dst, imm0_255:$src)]>;
+                 [(set tGPR:$dst, imm0_255:$src)]>;
 
 // TODO: A7-73: MOV(2) - mov setting flag.
 
 
 // Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
 // which is MOV(3).  This also supports high registers.
-def tMOVr  : TI<(outs GPR:$dst), (ins GPR:$src),
-                 "cpy $dst, $src", []>;
+def tMOVr       : TI<(outs tGPR:$dst), (ins tGPR:$src),
+                      "cpy $dst, $src", []>;
+def tMOVhir2lor : TI<(outs tGPR:$dst), (ins GPR:$src),
+                      "cpy $dst, $src\t@ hir2lor", []>;
+def tMOVlor2hir : TI<(outs GPR:$dst), (ins tGPR:$src),
+                      "cpy $dst, $src\t@ lor2hir", []>;
+def tMOVhir2hir : TI<(outs GPR:$dst), (ins GPR:$src),
+                      "cpy $dst, $src\t@ hir2hir", []>;
 
-def tMUL : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
+def tMUL : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
                "mul $dst, $rhs",
-               [(set GPR:$dst, (mul GPR:$lhs, GPR:$rhs))]>;
+               [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
 
-def tMVN : TI<(outs GPR:$dst), (ins GPR:$src),
+def tMVN : TI<(outs tGPR:$dst), (ins tGPR:$src),
               "mvn $dst, $src",
-              [(set GPR:$dst, (not GPR:$src))]>;
+              [(set tGPR:$dst, (not tGPR:$src))]>;
 
-def tNEG : TI<(outs GPR:$dst), (ins GPR:$src),
+def tNEG : TI<(outs tGPR:$dst), (ins tGPR:$src),
               "neg $dst, $src",
-              [(set GPR:$dst, (ineg GPR:$src))]>;
+              [(set tGPR:$dst, (ineg tGPR:$src))]>;
 
-def tORR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
+def tORR : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
                "orr $dst, $rhs",
-               [(set GPR:$dst, (or GPR:$lhs, GPR:$rhs))]>;
+               [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
 
 
-def tREV : TI<(outs GPR:$dst), (ins GPR:$src),
+def tREV : TI<(outs tGPR:$dst), (ins tGPR:$src),
               "rev $dst, $src",
-              [(set GPR:$dst, (bswap GPR:$src))]>,
+              [(set tGPR:$dst, (bswap tGPR:$src))]>,
               Requires<[IsThumb, HasV6]>;
 
-def tREV16 : TI<(outs GPR:$dst), (ins GPR:$src),
+def tREV16 : TI<(outs tGPR:$dst), (ins tGPR:$src),
                 "rev16 $dst, $src",
-                [(set GPR:$dst,
-                    (or (and (srl GPR:$src, 8), 0xFF),
-                        (or (and (shl GPR:$src, 8), 0xFF00),
-                            (or (and (srl GPR:$src, 8), 0xFF0000),
-                                (and (shl GPR:$src, 8), 0xFF000000)))))]>,
+                [(set tGPR:$dst,
+                    (or (and (srl tGPR:$src, 8), 0xFF),
+                        (or (and (shl tGPR:$src, 8), 0xFF00),
+                            (or (and (srl tGPR:$src, 8), 0xFF0000),
+                                (and (shl tGPR:$src, 8), 0xFF000000)))))]>,
                 Requires<[IsThumb, HasV6]>;
 
-def tREVSH : TI<(outs GPR:$dst), (ins GPR:$src),
+def tREVSH : TI<(outs tGPR:$dst), (ins tGPR:$src),
                 "revsh $dst, $src",
-                [(set GPR:$dst,
+                [(set tGPR:$dst,
                    (sext_inreg
-                     (or (srl (and GPR:$src, 0xFFFF), 8),
-                         (shl GPR:$src, 8)), i16))]>,
+                     (or (srl (and tGPR:$src, 0xFFFF), 8),
+                         (shl tGPR:$src, 8)), i16))]>,
                 Requires<[IsThumb, HasV6]>;
 
-def tROR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
+def tROR : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
                 "ror $dst, $rhs",
-                [(set GPR:$dst, (rotr GPR:$lhs, GPR:$rhs))]>;
+                [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
 
 
 // Subtract with carry
-def tSBC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
+def tSBC : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
                 "sbc $dst, $rhs",
-                [(set GPR:$dst, (sube GPR:$lhs, GPR:$rhs))]>;
+                [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
 
-def tSUBS : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
+def tSUBS : TI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
                 "sub $dst, $lhs, $rhs",
-               [(set GPR:$dst, (subc GPR:$lhs, GPR:$rhs))]>;
+               [(set tGPR:$dst, (subc tGPR:$lhs, tGPR:$rhs))]>;
 
 
 // TODO: A7-96: STMIA - store multiple.
 
-def tSUBi3 : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
+def tSUBi3 : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
                 "sub $dst, $lhs, $rhs",
-                [(set GPR:$dst, (add GPR:$lhs, imm0_7_neg:$rhs))]>;
+                [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
 
-def tSUBi8 : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
+def tSUBi8 : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
                   "sub $dst, $rhs",
-                  [(set GPR:$dst, (add GPR:$lhs, imm8_255_neg:$rhs))]>;
+                  [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
 
-def tSUBrr : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
+def tSUBrr : TI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
                 "sub $dst, $lhs, $rhs",
-                [(set GPR:$dst, (sub GPR:$lhs, GPR:$rhs))]>;
+                [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
 
-def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
+def tSUBspi : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
                   "sub $dst, $rhs * 4", []>;
 
-def tSXTB  : TI<(outs GPR:$dst), (ins GPR:$src),
+def tSXTB  : TI<(outs tGPR:$dst), (ins tGPR:$src),
                 "sxtb $dst, $src",
-                [(set GPR:$dst, (sext_inreg GPR:$src, i8))]>,
+                [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
                 Requires<[IsThumb, HasV6]>;
-def tSXTH  : TI<(outs GPR:$dst), (ins GPR:$src),
+def tSXTH  : TI<(outs tGPR:$dst), (ins tGPR:$src),
                 "sxth $dst, $src",
-                [(set GPR:$dst, (sext_inreg GPR:$src, i16))]>,
+                [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
                 Requires<[IsThumb, HasV6]>;
 
 
-def tUXTB  : TI<(outs GPR:$dst), (ins GPR:$src),
+def tUXTB  : TI<(outs tGPR:$dst), (ins tGPR:$src),
                 "uxtb $dst, $src",
-                [(set GPR:$dst, (and GPR:$src, 0xFF))]>,
+                [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
                 Requires<[IsThumb, HasV6]>;
-def tUXTH  : TI<(outs GPR:$dst), (ins GPR:$src),
+def tUXTH  : TI<(outs tGPR:$dst), (ins tGPR:$src),
                 "uxth $dst, $src",
-                [(set GPR:$dst, (and GPR:$src, 0xFFFF))]>,
+                [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
                 Requires<[IsThumb, HasV6]>;
 
 
@@ -483,20 +491,20 @@
 // Expanded by the scheduler into a branch sequence.
 let usesCustomDAGSchedInserter = 1 in  // Expanded by the scheduler.
   def tMOVCCr :
-  PseudoInst<(outs GPR:$dst), (ins GPR:$false, GPR:$true, pred:$cc),
+  PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
               "@ tMOVCCr $cc",
-              [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))*/]>;
+              [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
 
 // tLEApcrel - Load a pc-relative address into a register without offending the
 // assembler.
-def tLEApcrel : TIx2<(outs GPR:$dst), (ins i32imm:$label),
+def tLEApcrel : TIx2<(outs tGPR:$dst), (ins i32imm:$label),
                     !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
                                           "${:private}PCRELL${:uid}+4))\n"),
                                !strconcat("\tmov $dst, #PCRELV${:uid}\n",
                                   "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
                     []>;
 
-def tLEApcrelJT : TIx2<(outs GPR:$dst), (ins i32imm:$label, i32imm:$id),
+def tLEApcrelJT : TIx2<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id),
           !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
                                          "${:private}PCRELL${:uid}+4))\n"),
                      !strconcat("\tmov $dst, #PCRELV${:uid}\n",
@@ -532,7 +540,7 @@
 def : ThumbV5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
 
 // Indirect calls to ARM routines
-def : ThumbV5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>;
+def : ThumbV5Pat<(ARMcall tGPR:$dst), (tBLXr tGPR:$dst)>;
 
 // zextload i1 -> zextload i8
 def : ThumbPat<(zextloadi1 t_addrmode_s1:$addr),

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp?rev=68545&r1=68544&r2=68545&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Tue Apr  7 15:34:09 2009
@@ -211,6 +211,22 @@
   }
 }
 
+const TargetRegisterClass*
+ARMRegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, MVT VT) const {
+  if (STI.isThumb()) {
+    if (isLowRegister(Reg))
+      return ARM::tGPRRegisterClass;
+    switch (Reg) {
+    default:
+      break;
+    case ARM::R8:  case ARM::R9:  case ARM::R10:  case ARM::R11:
+    case ARM::R12: case ARM::SP:  case ARM::LR:   case ARM::PC:
+      return ARM::GPRRegisterClass;
+    }
+  }
+  return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
+}
+
 const unsigned*
 ARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   static const unsigned CalleeSavedRegs[] = {
@@ -244,7 +260,16 @@
     &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
     0
   };
-  return CalleeSavedRegClasses;
+  static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
+    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
+    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
+    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
+
+    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
+    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
+    0
+  };
+  return STI.isThumb() ? ThumbCalleeSavedRegClasses : CalleeSavedRegClasses;
 }
 
 BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
@@ -400,7 +425,7 @@
     if (DestReg == ARM::SP) {
       assert(BaseReg == ARM::SP && "Unexpected!");
       LdReg = ARM::R3;
-      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R12)
+      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
         .addReg(ARM::R3, false, false, true);
     }
 
@@ -423,7 +448,7 @@
     else
       MIB.addReg(LdReg).addReg(BaseReg, false, false, true);
     if (DestReg == ARM::SP)
-      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R3)
+      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
         .addReg(ARM::R12, false, false, true);
 }
 
@@ -616,6 +641,7 @@
 unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
                              ARMFunctionInfo *AFI) {
   unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
+  assert (!AFI->isThumbFunction());
   if (Reg == 0)
     // Try a already spilled CS register.
     Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
@@ -717,7 +743,7 @@
 
     if (Offset == 0) {
       // Turn it into a move.
-      MI.setDesc(TII.get(ARM::tMOVr));
+      MI.setDesc(TII.get(ARM::tMOVhir2lor));
       MI.getOperand(i).ChangeToRegister(FrameReg, false);
       MI.RemoveOperand(i+1);
       return;
@@ -891,12 +917,12 @@
       unsigned TmpReg = ARM::R3;
       bool UseRR = false;
       if (ValReg == ARM::R3) {
-        BuildMI(MBB, II, dl, TII.get(ARM::tMOVr), ARM::R12)
+        BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
           .addReg(ARM::R2, false, false, true);
         TmpReg = ARM::R2;
       }
       if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
-        BuildMI(MBB, II, dl, TII.get(ARM::tMOVr), ARM::R12)
+        BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
           .addReg(ARM::R3, false, false, true);
       if (Opcode == ARM::tSpill) {
         if (FrameReg == ARM::SP)
@@ -919,10 +945,10 @@
 
       MachineBasicBlock::iterator NII = next(II);
       if (ValReg == ARM::R3)
-        BuildMI(MBB, NII, dl, TII.get(ARM::tMOVr), ARM::R2)
+        BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R2)
           .addReg(ARM::R12, false, false, true);
       if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
-        BuildMI(MBB, NII, dl, TII.get(ARM::tMOVr), ARM::R3)
+        BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
           .addReg(ARM::R12, false, false, true);
     } else
       assert(false && "Unexpected opcode!");
@@ -1401,7 +1427,8 @@
           emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
                                     TII, *this, dl);
         else
-          BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr);
+          BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::SP)
+            .addReg(FramePtr);
       } else {
         if (MBBI->getOpcode() == ARM::tBX_RET &&
             &MBB.front() != MBBI &&

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h?rev=68545&r1=68544&r2=68545&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h Tue Apr  7 15:34:09 2009
@@ -54,6 +54,8 @@
   const TargetRegisterClass *getPointerRegClass() const;
 
   /// Code Generation virtual methods...
+  const TargetRegisterClass *
+    getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
   const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
 
   const TargetRegisterClass* const*

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=68545&r1=68544&r2=68545&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Tue Apr  7 15:34:09 2009
@@ -130,17 +130,10 @@
       ARM::R8, ARM::R10,ARM::R11,
       ARM::R7 };
 
-    // FP is R7, only low registers available.
-    static const unsigned THUMB_GPR_AO[] = {
-      ARM::R2, ARM::R1, ARM::R0,
-      ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
-
     GPRClass::iterator
     GPRClass::allocation_order_begin(const MachineFunction &MF) const {
       const TargetMachine &TM = MF.getTarget();
       const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
-      if (Subtarget.isThumb())
-        return THUMB_GPR_AO;
       if (Subtarget.useThumbBacktraces()) {
         if (Subtarget.isR9Reserved())
           return ARM_GPR_AO_4;
@@ -160,9 +153,8 @@
       const TargetRegisterInfo *RI = TM.getRegisterInfo();
       const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
       GPRClass::iterator I;
-      if (Subtarget.isThumb())
-        I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
-      else if (Subtarget.useThumbBacktraces()) {
+
+      if (Subtarget.useThumbBacktraces()) {
         if (Subtarget.isR9Reserved()) {
           I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
         } else {
@@ -182,6 +174,40 @@
   }];
 }
 
+// Thumb registers are R0-R7 normally. Some instructions can still use
+// the general GPR register class above (MOV, e.g.)
+def tGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7]> {
+  let MethodProtos = [{
+    iterator allocation_order_begin(const MachineFunction &MF) const;
+    iterator allocation_order_end(const MachineFunction &MF) const;
+  }];
+  // FIXME: We are reserving r3 in Thumb mode in case the PEI needs to use it
+  // to generate large stack offset. Make it available once we have register
+  // scavenging.
+  let MethodBodies = [{
+    static const unsigned THUMB_tGPR_AO[] = {
+      ARM::R2, ARM::R1, ARM::R0,
+      ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
+
+    // FP is R7, only low registers available.
+    tGPRClass::iterator
+    tGPRClass::allocation_order_begin(const MachineFunction &MF) const {
+      return THUMB_tGPR_AO;
+    }
+
+    tGPRClass::iterator
+    tGPRClass::allocation_order_end(const MachineFunction &MF) const {
+      const TargetMachine &TM = MF.getTarget();
+      const TargetRegisterInfo *RI = TM.getRegisterInfo();
+      const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
+      tGPRClass::iterator I =
+        THUMB_tGPR_AO + (sizeof(THUMB_tGPR_AO)/sizeof(unsigned));
+      // Mac OS X requires FP not to be clobbered for backtracing purpose.
+      return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
+    }
+  }];
+}
+
 def SPR : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8,
   S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22,
   S23, S24, S25, S26, S27, S28, S29, S30, S31]>;




From isanbard at gmail.com  Tue Apr  7 15:34:44 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 7 Apr 2009 13:34:44 -0700
Subject: [llvm-commits] [llvm] r68530 - /llvm/trunk/docs/FAQ.html
In-Reply-To: <49DBAAD8.8050500@gmail.com>
References: <200904071851.n37IpDBC022704@zion.cs.uiuc.edu>
	<49DBAAD8.8050500@gmail.com>
Message-ID: <16e5fdf90904071334o21a9c417yc78f9cd604d47dcd@mail.gmail.com>

2009/4/7 T?r?k Edwin <edwintorok at gmail.com>:
> Maybe I am missing something, but why not simply make build_gcc call
> "make -f GNUMakefile.Apple"?
>
It's build_gcc that gets called from GNUmakefile. Not the other way around.

-bw



From gohman at apple.com  Tue Apr  7 15:40:11 2009
From: gohman at apple.com (Dan Gohman)
Date: Tue, 07 Apr 2009 20:40:11 -0000
Subject: [llvm-commits] [llvm] r68546 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/FastISel.cpp test/CodeGen/X86/fast-isel-bail.ll
Message-ID: <200904072040.n37KeBtJ026886@zion.cs.uiuc.edu>

Author: djg
Date: Tue Apr  7 15:40:11 2009
New Revision: 68546

URL: http://llvm.org/viewvc/llvm-project?rev=68546&view=rev
Log:
Don't attempt to handle aggregate argument values in FastISel; let
SelectionDAG do those. This fixes PR3955.

Added:
    llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=68546&r1=68545&r2=68546&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Apr  7 15:40:11 2009
@@ -57,11 +57,15 @@
 using namespace llvm;
 
 unsigned FastISel::getRegForValue(Value *V) {
-  MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
+  MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
+  // Don't handle non-simple values in FastISel.
+  if (!RealVT.isSimple())
+    return 0;
 
   // Ignore illegal types. We must do this before looking up the value
   // in ValueMap because Arguments are given virtual registers regardless
   // of whether FastISel can handle them.
+  MVT::SimpleValueType VT = RealVT.getSimpleVT();
   if (!TLI.isTypeLegal(VT)) {
     // Promote MVT::i1 to a legal type though, because it's common and easy.
     if (VT == MVT::i1)

Added: llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll?rev=68546&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll (added)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll Tue Apr  7 15:40:11 2009
@@ -0,0 +1,14 @@
+; RUN: llvm-as < %s | llc -march=x86 -fast
+
+; This file is for regression tests for cases where FastISel needs
+; to gracefully bail out and let SelectionDAGISel take over.
+
+	type { i64, i8* }		; type %0
+
+declare void @bar(%0)
+
+define fastcc void @foo() nounwind {
+entry:
+	call void @bar(%0 zeroinitializer)
+	unreachable
+}




From espindola at google.com  Tue Apr  7 16:31:37 2009
From: espindola at google.com (Rafael Espindola)
Date: Tue, 7 Apr 2009 22:31:37 +0100
Subject: [llvm-commits] [llvm] r66922 - in /llvm/trunk:
	lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/tls13.ll
	test/CodeGen/X86/tls14.ll
In-Reply-To: <BE69A386-8D50-46F1-B182-A44F43BAB7D0@apple.com>
References: <200903131837.n2DIb7PC008719@zion.cs.uiuc.edu>
	<B409E5EA-50A1-4CD2-9E5E-E48DDE5D9731@apple.com>
	<EBD80AAC-81C6-46A8-B124-2286DCC7E0C8@apple.com>
	<38a0d8450903311517m60b40486wc1af6a391faa6b6f@mail.gmail.com>
	<01131E67-E237-482B-BBBE-843A1F6DE0D0@apple.com>
	<38a0d8450904021346y48f1d13ds2c23c13fca2a886a@mail.gmail.com>
	<6FC4BA6E-0E41-47E4-B4E1-D984E9A08B41@apple.com>
	<38a0d8450904030915g2e92040clb9c60b173f044c52@mail.gmail.com>
	<38a0d8450904050541r5e13b580o3a66bfa69069a455@mail.gmail.com>
	<BE69A386-8D50-46F1-B182-A44F43BAB7D0@apple.com>
Message-ID: <38a0d8450904071431u413e00ado66451b6996017e59@mail.gmail.com>

> It probably depends on the context. The latter at least has the
> advantage of allowing the load from %gs:0 of being CSE'd when
> there are multiple TLS address computations.
>
> Can this be fixed with code in
> X86DAGToDAGISel::IsLegalAndProfitableToFold ? The code at the
> top of the function is a heuristic with a similar purpose.

Yes. Doing a "ret 1" makes we try to use a lea.

> In any event, I don't consider this a show-stopper; we can
> continue to tune things like this after the patch is in.

OK. Will update the tests and commit.

> I think this patch looks like a good approach. I think there are
> some tuning things that can be addressed later; I just have a few
> minor comments for now.
>
> In this code in isMem in X86InstrInfo.h:
>
> @@ -256,6 +256,7 @@
> ? ?return Op+4 <= MI->getNumOperands() &&
> ? ? ?MI->getOperand(Op ?).isReg() && isScale(MI->getOperand(Op+1)) &&
> ? ? ?MI->getOperand(Op+2).isReg() &&
> + ? ?MI->getOperand(Op+4).isReg() &&
> ? ? ?(MI->getOperand(Op+3).isImm() ||
> ? ? ? MI->getOperand(Op+3).isGlobal() ||
> ? ? ? MI->getOperand(Op+3).isCPI() ||
>
> The code here only checks for getNumOperands being >= Op+4, so the
> call to getOperand(Op+4) could potentially go out of bounds. A simple
> fix would be to create a separate isLeaMem function which only expects
> 4 operands so that isMem can expect 5 (or X86AddrNumOperands)
> operands. A more involved fix would be to make all addresses have 5
> operands, and just require the fifth operand in an lea to be %reg0.
> I don't have a strong preference at this point.

I added isLeaMem.

> Please add a comment in MatchLoad explaining why it's safe to
> do what it's doing.

Done.

> Please use spaces instead of tabs for indentation.

Done.

> Thanks for working on this!

Thanks for the tip on how to fix this.

> Dan
>

Cheers,
-- 
Rafael Avila de Espindola

Google | Gordon House | Barrow Street | Dublin 4 | Ireland
Registered in Dublin, Ireland | Registration Number: 368047



From rafael.espindola at gmail.com  Tue Apr  7 16:37:46 2009
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Tue, 07 Apr 2009 21:37:46 -0000
Subject: [llvm-commits] [llvm] r68552 - in /llvm/trunk: lib/Target/X86/
 lib/Target/X86/AsmPrinter/ test/CodeGen/X86/
Message-ID: <200904072137.n37Lbll0029223@zion.cs.uiuc.edu>

Author: rafael
Date: Tue Apr  7 16:37:46 2009
New Revision: 68552

URL: http://llvm.org/viewvc/llvm-project?rev=68552&view=rev
Log:
Reduce code duplication on the TLS implementation.
This introduces a small regression on the generated code
quality in the case we are just computing addresses, not
loading values.

Will work on it and on X86-64 support.


Modified:
    llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
    llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
    llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
    llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
    llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
    llvm/trunk/lib/Target/X86/X86FastISel.cpp
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86Instr64bit.td
    llvm/trunk/lib/Target/X86/X86InstrBuilder.h
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.h
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
    llvm/trunk/lib/Target/X86/X86RegisterInfo.td
    llvm/trunk/test/CodeGen/X86/tls10.ll
    llvm/trunk/test/CodeGen/X86/tls2.ll
    llvm/trunk/test/CodeGen/X86/tls6.ll
    llvm/trunk/test/CodeGen/X86/tls8.ll

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Tue Apr  7 16:37:46 2009
@@ -566,9 +566,8 @@
   }
 }
 
-void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
-                                         const char *Modifier){
-  assert(isMem(MI, Op) && "Invalid memory reference!");
+void X86ATTAsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op,
+                                            const char *Modifier){
   MachineOperand BaseReg  = MI->getOperand(Op);
   MachineOperand IndexReg = MI->getOperand(Op+2);
   const MachineOperand &DispSpec = MI->getOperand(Op+3);
@@ -611,6 +610,17 @@
   }
 }
 
+void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
+                                         const char *Modifier){
+  assert(isMem(MI, Op) && "Invalid memory reference!");
+  MachineOperand Segment = MI->getOperand(Op+4);
+  if (Segment.getReg()) {
+      printOperand(MI, Op+4, Modifier);
+      O << ':';
+    }
+  printLeaMemReference(MI, Op, Modifier);
+}
+
 void X86ATTAsmPrinter::printPICJumpTableSetLabel(unsigned uid,
                                            const MachineBasicBlock *MBB) const {
   if (!TAI->getSetDirective())

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Tue Apr  7 16:37:46 2009
@@ -93,8 +93,14 @@
   void printf128mem(const MachineInstr *MI, unsigned OpNo) {
     printMemReference(MI, OpNo);
   }
+  void printlea32mem(const MachineInstr *MI, unsigned OpNo) {
+    printLeaMemReference(MI, OpNo);
+  }
+  void printlea64mem(const MachineInstr *MI, unsigned OpNo) {
+    printLeaMemReference(MI, OpNo);
+  }
   void printlea64_32mem(const MachineInstr *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo, "subreg64");
+    printLeaMemReference(MI, OpNo, "subreg64");
   }
 
   bool printAsmMRegister(const MachineOperand &MO, const char Mode);
@@ -107,6 +113,8 @@
   void printSSECC(const MachineInstr *MI, unsigned Op);
   void printMemReference(const MachineInstr *MI, unsigned Op,
                          const char *Modifier=NULL);
+  void printLeaMemReference(const MachineInstr *MI, unsigned Op,
+                            const char *Modifier=NULL);
   void printPICJumpTableSetLabel(unsigned uid,
                                  const MachineBasicBlock *MBB) const;
   void printPICJumpTableSetLabel(unsigned uid, unsigned uid2,

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp Tue Apr  7 16:37:46 2009
@@ -271,10 +271,9 @@
   }
 }
 
-void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
-                                           const char *Modifier) {
-  assert(isMem(MI, Op) && "Invalid memory reference!");
-
+void X86IntelAsmPrinter::printLeaMemReference(const MachineInstr *MI,
+                                              unsigned Op,
+                                              const char *Modifier) {
   const MachineOperand &BaseReg  = MI->getOperand(Op);
   int ScaleVal                   = MI->getOperand(Op+1).getImm();
   const MachineOperand &IndexReg = MI->getOperand(Op+2);
@@ -317,6 +316,17 @@
   O << "]";
 }
 
+void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
+                                           const char *Modifier) {
+  assert(isMem(MI, Op) && "Invalid memory reference!");
+  MachineOperand Segment = MI->getOperand(Op+4);
+  if (Segment.getReg()) {
+      printOperand(MI, Op+4, Modifier);
+      O << ':';
+    }
+  printLeaMemReference(MI, Op, Modifier);
+}
+
 void X86IntelAsmPrinter::printPICJumpTableSetLabel(unsigned uid,
                                            const MachineBasicBlock *MBB) const {
   if (!TAI->getSetDirective())

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h Tue Apr  7 16:37:46 2009
@@ -88,9 +88,17 @@
     O << "XMMWORD PTR ";
     printMemReference(MI, OpNo);
   }
+  void printlea32mem(const MachineInstr *MI, unsigned OpNo) {
+    O << "DWORD PTR ";
+    printLeaMemReference(MI, OpNo);
+  }
+  void printlea64mem(const MachineInstr *MI, unsigned OpNo) {
+    O << "QWORD PTR ";
+    printLeaMemReference(MI, OpNo);
+  }
   void printlea64_32mem(const MachineInstr *MI, unsigned OpNo) {
     O << "QWORD PTR ";
-    printMemReference(MI, OpNo, "subreg64");
+    printLeaMemReference(MI, OpNo, "subreg64");
   }
 
   bool printAsmMRegister(const MachineOperand &MO, const char Mode);
@@ -103,6 +111,8 @@
   void printSSECC(const MachineInstr *MI, unsigned Op);
   void printMemReference(const MachineInstr *MI, unsigned Op,
                          const char *Modifier=NULL);
+  void printLeaMemReference(const MachineInstr *MI, unsigned Op,
+                            const char *Modifier=NULL);
   void printPICJumpTableSetLabel(unsigned uid,
                                  const MachineBasicBlock *MBB) const;
   void printPICJumpTableSetLabel(unsigned uid, unsigned uid2,

Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Tue Apr  7 16:37:46 2009
@@ -533,23 +533,6 @@
     case X86::DWARF_LOC:
     case X86::FP_REG_KILL:
       break;
-    case X86::TLS_tp: {
-      MCE.emitByte(BaseOpcode);
-      unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg());
-      MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
-      emitConstant(0, 4);
-      break;
-    }
-    case X86::TLS_gs_ri: {
-      MCE.emitByte(BaseOpcode);
-      unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg());
-      MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
-      GlobalValue* GV = MI.getOperand(1).getGlobal();
-      unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
-        : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
-      emitGlobalAddress(GV, rt);
-      break;
-    }
     case X86::MOVPC32r: {
       // This emits the "call" portion of this pseudo instruction.
       MCE.emitByte(BaseOpcode);
@@ -661,13 +644,21 @@
     break;
 
   case X86II::MRMSrcMem: {
-    intptr_t PCAdj = (CurOp + X86AddrNumOperands + 1 != NumOps) ?
+    // FIXME: Maybe lea should have its own form?
+    int AddrOperands;
+    if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
+        Opcode == X86::LEA16r || Opcode == X86::LEA32r)
+      AddrOperands = X86AddrNumOperands - 1; // No segment register
+    else
+      AddrOperands = X86AddrNumOperands;
+
+    intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
       X86InstrInfo::sizeOfImm(Desc) : 0;
 
     MCE.emitByte(BaseOpcode);
     emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
                      PCAdj);
-    CurOp += X86AddrNumOperands + 1;
+    CurOp += AddrOperands + 1;
     if (CurOp != NumOps)
       emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
     break;

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Tue Apr  7 16:37:46 2009
@@ -1490,7 +1490,7 @@
       else
         Opc = X86::LEA64r;
       unsigned ResultReg = createResultReg(RC);
-      addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
+      addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
       return ResultReg;
     }
     return 0;
@@ -1535,7 +1535,7 @@
   unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
   TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
   unsigned ResultReg = createResultReg(RC);
-  addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
+  addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
   return ResultReg;
 }
 

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Apr  7 16:37:46 2009
@@ -69,6 +69,7 @@
     unsigned Scale;
     SDValue IndexReg; 
     int32_t Disp;
+    SDValue Segment;
     GlobalValue *GV;
     Constant *CP;
     const char *ES;
@@ -77,7 +78,7 @@
 
     X86ISelAddressMode()
       : BaseType(RegBase), isRIPRel(false), Scale(1), IndexReg(), Disp(0),
-        GV(0), CP(0), ES(0), JT(-1), Align(0) {
+        Segment(), GV(0), CP(0), ES(0), JT(-1), Align(0) {
     }
 
     bool hasSymbolicDisplacement() const {
@@ -159,20 +160,25 @@
     SDNode *Select(SDValue N);
     SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
 
+    bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM);
+    bool MatchLoad(SDValue N, X86ISelAddressMode &AM);
     bool MatchAddress(SDValue N, X86ISelAddressMode &AM,
                       unsigned Depth = 0);
     bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
     bool SelectAddr(SDValue Op, SDValue N, SDValue &Base,
-                    SDValue &Scale, SDValue &Index, SDValue &Disp);
+                    SDValue &Scale, SDValue &Index, SDValue &Disp,
+                    SDValue &Segment);
     bool SelectLEAAddr(SDValue Op, SDValue N, SDValue &Base,
                        SDValue &Scale, SDValue &Index, SDValue &Disp);
     bool SelectScalarSSELoad(SDValue Op, SDValue Pred,
                              SDValue N, SDValue &Base, SDValue &Scale,
                              SDValue &Index, SDValue &Disp,
+                             SDValue &Segment,
                              SDValue &InChain, SDValue &OutChain);
     bool TryFoldLoad(SDValue P, SDValue N,
                      SDValue &Base, SDValue &Scale,
-                     SDValue &Index, SDValue &Disp);
+                     SDValue &Index, SDValue &Disp,
+                     SDValue &Segment);
     void PreprocessForRMW();
     void PreprocessForFPConvert();
 
@@ -186,7 +192,7 @@
 
     inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base, 
                                    SDValue &Scale, SDValue &Index,
-                                   SDValue &Disp) {
+                                   SDValue &Disp, SDValue &Segment) {
       Base  = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
         CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
         AM.Base.Reg;
@@ -205,6 +211,11 @@
         Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32);
       else
         Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
+
+      if (AM.Segment.getNode())
+        Segment = AM.Segment;
+      else
+        Segment = CurDAG->getRegister(0, MVT::i32);
     }
 
     /// getI8Imm - Return a target constant with the specified value, of type
@@ -726,6 +737,33 @@
     EmitSpecialCodeForMain(BB, MF.getFrameInfo());
 }
 
+
+bool X86DAGToDAGISel::MatchSegmentBaseAddress(SDValue N,
+                                              X86ISelAddressMode &AM) {
+  assert(N.getOpcode() == X86ISD::SegmentBaseAddress);
+  SDValue Segment = N.getOperand(0);
+
+  if (AM.Segment.getNode() == 0) {
+    AM.Segment = Segment;
+    return false;
+  }
+
+  return true;
+}
+
+bool X86DAGToDAGISel::MatchLoad(SDValue N, X86ISelAddressMode &AM) {
+  // This optimization is valid because the GNU TLS model defines that
+  // gs:0 (or fs:0 on X86-64) contains its own address.
+  // For more information see http://people.redhat.com/drepper/tls.pdf
+
+  SDValue Address = N.getOperand(1);
+  if (Address.getOpcode() == X86ISD::SegmentBaseAddress &&
+      !MatchSegmentBaseAddress (Address, AM))
+    return false;
+
+  return true;
+}
+
 /// MatchAddress - Add the specified node to the specified addressing mode,
 /// returning true if it cannot be done.  This just pattern matches for the
 /// addressing mode.
@@ -761,6 +799,11 @@
     break;
   }
 
+  case X86ISD::SegmentBaseAddress:
+    if (!MatchSegmentBaseAddress(N, AM))
+      return false;
+    break;
+
   case X86ISD::Wrapper: {
     DOUT << "Wrapper: 64bit " << is64Bit;
     DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n";
@@ -807,6 +850,11 @@
     break;
   }
 
+  case ISD::LOAD:
+    if (!MatchLoad(N, AM))
+      return false;
+    break;
+
   case ISD::FrameIndex:
     if (AM.BaseType == X86ISelAddressMode::RegBase
         && AM.Base.Reg.getNode() == 0) {
@@ -1034,7 +1082,7 @@
 /// match by reference.
 bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base,
                                  SDValue &Scale, SDValue &Index,
-                                 SDValue &Disp) {
+                                 SDValue &Disp, SDValue &Segment) {
   X86ISelAddressMode AM;
   bool Done = false;
   if (AvoidDupAddrCompute && !N.hasOneUse()) {
@@ -1069,7 +1117,7 @@
   if (!AM.IndexReg.getNode())
     AM.IndexReg = CurDAG->getRegister(0, VT);
 
-  getAddressOperands(AM, Base, Scale, Index, Disp);
+  getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
   return true;
 }
 
@@ -1079,7 +1127,8 @@
 bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred,
                                           SDValue N, SDValue &Base,
                                           SDValue &Scale, SDValue &Index,
-                                          SDValue &Disp, SDValue &InChain,
+                                          SDValue &Disp, SDValue &Segment,
+                                          SDValue &InChain,
                                           SDValue &OutChain) {
   if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
     InChain = N.getOperand(0).getValue(1);
@@ -1088,7 +1137,7 @@
         N.hasOneUse() &&
         IsLegalAndProfitableToFold(N.getNode(), Pred.getNode(), Op.getNode())) {
       LoadSDNode *LD = cast<LoadSDNode>(InChain);
-      if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
+      if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
         return false;
       OutChain = LD->getChain();
       return true;
@@ -1105,7 +1154,7 @@
       N.getOperand(0).getOperand(0).hasOneUse()) {
     // Okay, this is a zero extending load.  Fold it.
     LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
-    if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
+    if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
       return false;
     OutChain = LD->getChain();
     InChain = SDValue(LD, 1);
@@ -1124,6 +1173,11 @@
   if (MatchAddress(N, AM))
     return false;
 
+  //Is it better to set AM.Segment before calling MatchAddress to
+  //prevent it from adding a segment?
+  if (AM.Segment.getNode())
+    return false;
+
   MVT VT = N.getValueType();
   unsigned Complexity = 0;
   if (AM.BaseType == X86ISelAddressMode::RegBase)
@@ -1162,7 +1216,8 @@
     Complexity++;
 
   if (Complexity > 2) {
-    getAddressOperands(AM, Base, Scale, Index, Disp);
+    SDValue Segment;
+    getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
     return true;
   }
   return false;
@@ -1170,11 +1225,12 @@
 
 bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
                                   SDValue &Base, SDValue &Scale,
-                                  SDValue &Index, SDValue &Disp) {
+                                  SDValue &Index, SDValue &Disp,
+                                  SDValue &Segment) {
   if (ISD::isNON_EXTLoad(N.getNode()) &&
       N.hasOneUse() &&
       IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
-    return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp);
+    return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp, Segment);
   return false;
 }
 
@@ -1230,11 +1286,11 @@
   SDValue In1 = Node->getOperand(1);
   SDValue In2L = Node->getOperand(2);
   SDValue In2H = Node->getOperand(3);
-  SDValue Tmp0, Tmp1, Tmp2, Tmp3;
-  if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3))
+  SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
+  if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
     return NULL;
   SDValue LSI = Node->getOperand(4);    // MemOperand
-  const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, In2L, In2H, LSI, Chain };
+  const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, LSI, Chain};
   return CurDAG->getTargetNode(Opc, Node->getDebugLoc(),
                                MVT::i32, MVT::i32, MVT::Other, Ops,
                                array_lengthof(Ops));
@@ -1316,11 +1372,11 @@
       case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
       }
 
-      SDValue Tmp0, Tmp1, Tmp2, Tmp3;
-      bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
+      SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
+      bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
       // multiplty is commmutative
       if (!foldedLoad) {
-        foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
+        foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
         if (foldedLoad)
           std::swap(N0, N1);
       }
@@ -1329,7 +1385,8 @@
                                               N0, SDValue()).getValue(1);
 
       if (foldedLoad) {
-        SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
+        SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
+                          InFlag };
         SDNode *CNode =
           CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
                                 array_lengthof(Ops));
@@ -1438,17 +1495,17 @@
         break;
       }
 
-      SDValue Tmp0, Tmp1, Tmp2, Tmp3;
-      bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
+      SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
+      bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
       bool signBitIsZero = CurDAG->SignBitIsZero(N0);
 
       SDValue InFlag;
       if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
         // Special case for div8, just use a move with zero extension to AX to
         // clear the upper 8 bits (AH).
-        SDValue Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
-        if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) {
-          SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
+        SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
+        if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
+          SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
           Move =
             SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, MVT::i16, 
                                           MVT::Other, Ops,
@@ -1480,7 +1537,8 @@
       }
 
       if (foldedLoad) {
-        SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
+        SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
+                          InFlag };
         SDNode *CNode =
           CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
                                 array_lengthof(Ops));
@@ -1649,13 +1707,13 @@
 bool X86DAGToDAGISel::
 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
                              std::vector<SDValue> &OutOps) {
-  SDValue Op0, Op1, Op2, Op3;
+  SDValue Op0, Op1, Op2, Op3, Op4;
   switch (ConstraintCode) {
   case 'o':   // offsetable        ??
   case 'v':   // not offsetable    ??
   default: return true;
   case 'm':   // memory
-    if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3))
+    if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3, Op4))
       return true;
     break;
   }
@@ -1664,6 +1722,7 @@
   OutOps.push_back(Op1);
   OutOps.push_back(Op2);
   OutOps.push_back(Op3);
+  OutOps.push_back(Op4);
   return false;
 }
 

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Apr  7 16:37:46 2009
@@ -4834,8 +4834,13 @@
                                    const MVT PtrVT, TLSModel::Model model) {
   DebugLoc dl = GA->getDebugLoc();
   // Get the Thread Pointer
-  SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER,
-                                      DebugLoc::getUnknownLoc(), PtrVT);
+  SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
+                             DebugLoc::getUnknownLoc(), PtrVT,
+                             DAG.getRegister(X86::GS, MVT::i32));
+
+  SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
+                                      NULL, 0);
+
   // emit "addl x at ntpoff,%eax" (local exec) or "addl x at indntpoff,%eax" (initial
   // exec)
   SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
@@ -7149,7 +7154,7 @@
   case X86ISD::FRSQRT:             return "X86ISD::FRSQRT";
   case X86ISD::FRCP:               return "X86ISD::FRCP";
   case X86ISD::TLSADDR:            return "X86ISD::TLSADDR";
-  case X86ISD::THREAD_POINTER:     return "X86ISD::THREAD_POINTER";
+  case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
   case X86ISD::EH_RETURN:          return "X86ISD::EH_RETURN";
   case X86ISD::TC_RETURN:          return "X86ISD::TC_RETURN";
   case X86ISD::FNSTCW16m:          return "X86ISD::FNSTCW16m";
@@ -7473,7 +7478,7 @@
   unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
   MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
   // add 4 to displacement.
-  for (int i=0; i <= lastAddrIndx-1; ++i)
+  for (int i=0; i <= lastAddrIndx-2; ++i)
     (*MIB).addOperand(*argOpers[i]);
   MachineOperand newOp3 = *(argOpers[3]);
   if (newOp3.isImm())
@@ -7481,6 +7486,7 @@
   else
     newOp3.setOffset(newOp3.getOffset()+4);
   (*MIB).addOperand(newOp3);
+  (*MIB).addOperand(*argOpers[lastAddrIndx]);
 
   // t3/4 are defined later, at the bottom of the loop
   unsigned t3 = F->getRegInfo().createVirtualRegister(RC);

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Apr  7 16:37:46 2009
@@ -188,8 +188,11 @@
       /// in order to obtain suitable precision.
       FRSQRT, FRCP,
 
-      // TLSADDR, THREAD_POINTER - Thread Local Storage.
-      TLSADDR, THREAD_POINTER,
+      // TLSADDR - Thread Local Storage.
+      TLSADDR,
+
+      // SegmentBaseAddress - The address segment:0
+      SegmentBaseAddress,
 
       // EH_RETURN - Exception Handling helpers.
       EH_RETURN,

Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Tue Apr  7 16:37:46 2009
@@ -23,7 +23,7 @@
 def i64i8imm   : Operand<i64>;
 
 def lea64mem : Operand<i64> {
-  let PrintMethod = "printi64mem";
+  let PrintMethod = "printlea64mem";
   let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
 }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrBuilder.h?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrBuilder.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrBuilder.h Tue Apr  7 16:37:46 2009
@@ -66,6 +66,15 @@
   return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0);
 }
 
+inline const MachineInstrBuilder &addLeaOffset(const MachineInstrBuilder &MIB,
+                                            int Offset) {
+  return MIB.addImm(1).addReg(0).addImm(Offset);
+}
+
+inline const MachineInstrBuilder &addOffset(const MachineInstrBuilder &MIB,
+                                            int Offset) {
+  return addLeaOffset(MIB, Offset).addReg(0);
+}
 
 /// addRegOffset - This function is used to add a memory reference of the form
 /// [Reg + Offset], i.e., one with no scale or index, but with a
@@ -74,8 +83,13 @@
 inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB,
                                                unsigned Reg, bool isKill,
                                                int Offset) {
-  return MIB.addReg(Reg, false, false, isKill)
-    .addImm(1).addReg(0).addImm(Offset);
+  return addOffset(MIB.addReg(Reg, false, false, isKill), Offset);
+}
+
+inline const MachineInstrBuilder &addLeaRegOffset(const MachineInstrBuilder &MIB,
+                                                  unsigned Reg, bool isKill,
+                                                  int Offset) {
+  return addLeaOffset(MIB.addReg(Reg, false, false, isKill), Offset);
 }
 
 /// addRegReg - This function is used to add a memory reference of the form:
@@ -87,8 +101,8 @@
     .addReg(Reg2, false, false, isKill2).addImm(0);
 }
 
-inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
-                                                 const X86AddressMode &AM) {
+inline const MachineInstrBuilder &addLeaAddress(const MachineInstrBuilder &MIB,
+                                                const X86AddressMode &AM) {
   assert (AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
 
   if (AM.BaseType == X86AddressMode::RegBase)
@@ -104,6 +118,11 @@
     return MIB.addImm(AM.Disp);
 }
 
+inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
+                                                 const X86AddressMode &AM) {
+  return addLeaAddress(MIB, AM).addReg(0);
+}
+
 /// addFrameReference - This function is used to add a reference to the base of
 /// an abstract object on the stack frame of the current function.  This
 /// reference has base register as the FrameIndex offset until it is resolved.
@@ -125,7 +144,7 @@
                         MFI.getObjectOffset(FI) + Offset,
                         MFI.getObjectSize(FI),
                         MFI.getObjectAlignment(FI));
-  return MIB.addFrameIndex(FI).addImm(1).addReg(0).addImm(Offset)
+  return addOffset(MIB.addFrameIndex(FI), Offset)
             .addMemOperand(MMO);
 }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Apr  7 16:37:46 2009
@@ -1138,9 +1138,9 @@
       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
       unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
-      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
-                           .addReg(Dest, true, false, false, isDead),
-                           Src, isKill, 1);
+      NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
+                              .addReg(Dest, true, false, false, isDead),
+                              Src, isKill, 1);
       break;
     }
     case X86::INC16r:
@@ -1157,9 +1157,9 @@
       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
       unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
-      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
-                           .addReg(Dest, true, false, false, isDead),
-                           Src, isKill, -1);
+      NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
+                              .addReg(Dest, true, false, false, isDead),
+                              Src, isKill, -1);
       break;
     }
     case X86::DEC16r:
@@ -1200,18 +1200,18 @@
     case X86::ADD64ri8:
       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
       if (MI->getOperand(2).isImm())
-        NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
-                             .addReg(Dest, true, false, false, isDead),
-                             Src, isKill, MI->getOperand(2).getImm());
+        NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
+                                .addReg(Dest, true, false, false, isDead),
+                                Src, isKill, MI->getOperand(2).getImm());
       break;
     case X86::ADD32ri:
     case X86::ADD32ri8:
       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
       if (MI->getOperand(2).isImm()) {
         unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
-        NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
-                             .addReg(Dest, true, false, false, isDead),
-                             Src, isKill, MI->getOperand(2).getImm());
+        NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
+                                .addReg(Dest, true, false, false, isDead),
+                                Src, isKill, MI->getOperand(2).getImm());
       }
       break;
     case X86::ADD16ri:
@@ -1959,7 +1959,7 @@
   for (unsigned i = 0; i != NumAddrOps; ++i)
     MIB.addOperand(MOs[i]);
   if (NumAddrOps < 4)  // FrameIndex only
-    MIB.addImm(1).addReg(0).addImm(0);
+    addOffset(MIB, 0);
   
   // Loop over the rest of the ri operands, converting them over.
   unsigned NumOps = MI->getDesc().getNumOperands()-2;
@@ -1990,7 +1990,7 @@
       for (unsigned i = 0; i != NumAddrOps; ++i)
         MIB.addOperand(MOs[i]);
       if (NumAddrOps < 4)  // FrameIndex only
-        MIB.addImm(1).addReg(0).addImm(0);
+        addOffset(MIB, 0);
     } else {
       MIB.addOperand(MO);
     }
@@ -2008,7 +2008,7 @@
   for (unsigned i = 0; i != NumAddrOps; ++i)
     MIB.addOperand(MOs[i]);
   if (NumAddrOps < 4)  // FrameIndex only
-    MIB.addImm(1).addReg(0).addImm(0);
+    addOffset(MIB, 0);
   return MIB.addImm(0);
 }
 
@@ -2164,7 +2164,7 @@
   } else if (Ops.size() != 1)
     return NULL;
 
-  SmallVector<MachineOperand,4> MOs;
+  SmallVector<MachineOperand,X86AddrNumOperands> MOs;
   if (LoadMI->getOpcode() == X86::V_SET0 ||
       LoadMI->getOpcode() == X86::V_SETALLONES) {
     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
@@ -2193,6 +2193,7 @@
     MOs.push_back(MachineOperand::CreateImm(1));
     MOs.push_back(MachineOperand::CreateReg(0, false));
     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
+    MOs.push_back(MachineOperand::CreateReg(0, false));
   } else {
     // Folding a normal load. Just copy the load's address operands.
     unsigned NumOps = LoadMI->getDesc().getNumOperands();
@@ -2882,11 +2883,6 @@
       FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
       break;
     }
-    case X86::TLS_tp:
-    case X86::TLS_gs_ri:
-      FinalSize += 2;
-      FinalSize += sizeGlobalAddress(false);
-      break;
     }
     CurOp = NumOps;
     break;

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Tue Apr  7 16:37:46 2009
@@ -243,7 +243,7 @@
   };
 }
 
-const int X86AddrNumOperands = 4;
+const int X86AddrNumOperands = 5;
 
 inline static bool isScale(const MachineOperand &MO) {
   return MO.isImm() &&
@@ -251,7 +251,7 @@
      MO.getImm() == 4 || MO.getImm() == 8);
 }
 
-inline static bool isMem(const MachineInstr *MI, unsigned Op) {
+inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
   if (MI->getOperand(Op).isFI()) return true;
   return Op+4 <= MI->getNumOperands() &&
     MI->getOperand(Op  ).isReg() && isScale(MI->getOperand(Op+1)) &&
@@ -262,6 +262,13 @@
      MI->getOperand(Op+3).isJTI());
 }
 
+inline static bool isMem(const MachineInstr *MI, unsigned Op) {
+  if (MI->getOperand(Op).isFI()) return true;
+  return Op+5 <= MI->getNumOperands() &&
+    MI->getOperand(Op+4).isReg() &&
+    isLeaMem(MI, Op);
+}
+
 class X86InstrInfo : public TargetInstrInfoImpl {
   X86TargetMachine &TM;
   const X86RegisterInfo RI;

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Apr  7 16:37:46 2009
@@ -65,7 +65,7 @@
 
 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
 
-def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
+def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
 
 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 
@@ -142,7 +142,8 @@
 
 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
                         [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
-def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
+def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
+                                 SDT_X86SegmentBaseAddress, []>;
 
 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
                         [SDNPHasChain]>;
@@ -167,7 +168,7 @@
 //
 class X86MemOperand<string printMethod> : Operand<iPTR> {
   let PrintMethod = printMethod;
-  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
+  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
 }
 
 def i8mem   : X86MemOperand<"printi8mem">;
@@ -181,7 +182,7 @@
 def f128mem : X86MemOperand<"printf128mem">;
 
 def lea32mem : Operand<i32> {
-  let PrintMethod = "printi32mem";
+  let PrintMethod = "printlea32mem";
   let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
 }
 
@@ -207,7 +208,7 @@
 //
 
 // Define X86 specific addressing mode.
-def addr      : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
+def addr      : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
                                [add, mul, shl, or, frameindex], []>;
 
@@ -2922,101 +2923,11 @@
 // Thread Local Storage Instructions
 //
 
-// FIXME: there is duplication with the non-TLS case.
-// There is a suggestion on how to fix this at
-// http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090309/075212.html
-
 let Uses = [EBX] in
 def TLS_addr32 : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
                   "leal\t${sym:mem}(,%ebx,1), $dst",
                   [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
 
-let AddedComplexity = 10 in
-def TLS_gs_rr  : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
-                  "movl\t%gs:($src), $dst",
-                  [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
-
-let AddedComplexity = 15 in
-def TLS_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
-                  "movl\t%gs:${src:mem}, $dst",
-                  [(set GR32:$dst,
-                    (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>,
-                  SegGS;
-
-let AddedComplexity = 15 in
-def TLS16_gs_ri : I<0x8B, Pseudo, (outs GR16:$dst), (ins i32imm:$src),
-                    "movw\t%gs:${src:mem}, $dst",
-                    [(set GR16:$dst,
-                      (load (add X86TLStp,
-                        (X86Wrapper tglobaltlsaddr:$src))))]>,
-                    SegGS;
-
-let AddedComplexity = 15 in
-def TLS8_gs_ri : I<0x8B, Pseudo, (outs GR8:$dst), (ins i32imm:$src),
-                   "movb\t%gs:${src:mem}, $dst",
-                   [(set GR8:$dst,
-                     (load (add X86TLStp,
-                       (X86Wrapper tglobaltlsaddr:$src))))]>,
-                   SegGS;
-
-let AddedComplexity = 15 in
-def TLS_ext16_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
-                        "movzwl\t%gs:${src:mem}, $dst",
-                        [(set GR32:$dst,
-                          (extloadi32i16
-                            (add X86TLStp,
-                              (X86Wrapper tglobaltlsaddr:$src))))]>,
-                        SegGS;
-
-let AddedComplexity = 15 in
-def TLS_sext16_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
-                         "movswl\t%gs:${src:mem}, $dst",
-                         [(set GR32:$dst,
-                           (sextloadi32i16
-                             (add X86TLStp,
-                               (X86Wrapper tglobaltlsaddr:$src))))]>,
-                         SegGS;
-
-let AddedComplexity = 15 in
-def TLS_zext16_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
-                         "movzwl\t%gs:${src:mem}, $dst",
-                         [(set GR32:$dst,
-                           (zextloadi32i16
-                             (add X86TLStp,
-                               (X86Wrapper tglobaltlsaddr:$src))))]>,
-                         SegGS;
-
-let AddedComplexity = 15 in
-def TLS_ext8_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
-                        "movzbl\t%gs:${src:mem}, $dst",
-                        [(set GR32:$dst,
-                          (extloadi32i8
-                            (add X86TLStp,
-                              (X86Wrapper tglobaltlsaddr:$src))))]>,
-                        SegGS;
-
-let AddedComplexity = 15 in
-def TLS_sext8_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
-                         "movsbl\t%gs:${src:mem}, $dst",
-                         [(set GR32:$dst,
-                           (sextloadi32i8
-                             (add X86TLStp,
-                               (X86Wrapper tglobaltlsaddr:$src))))]>,
-                         SegGS;
-
-let AddedComplexity = 15 in
-def TLS_zext8_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
-                         "movzbl\t%gs:${src:mem}, $dst",
-                         [(set GR32:$dst,
-                           (zextloadi32i8
-                             (add X86TLStp,
-                              (X86Wrapper tglobaltlsaddr:$src))))]>,
-                         SegGS;
-
-def TLS_tp : I<0x8B, Pseudo, (outs GR32:$dst), (ins),
-               "movl\t%gs:0, $dst",
-               [(set GR32:$dst, X86TLStp)]>, SegGS;
-
 let AddedComplexity = 5 in
 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
                    "movl\t%gs:$src, $dst",

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Apr  7 16:37:46 2009
@@ -76,18 +76,18 @@
 // These are 'extloads' from a scalar to the low element of a vector, zeroing
 // the top elements.  These are used for the SSE 'ss' and 'sd' instruction
 // forms.
-def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
+def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
                                   [SDNPHasChain, SDNPMayLoad]>;
-def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
+def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
                                   [SDNPHasChain, SDNPMayLoad]>;
 
 def ssmem : Operand<v4f32> {
   let PrintMethod = "printf32mem";
-  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
+  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
 }
 def sdmem : Operand<v2f64> {
   let PrintMethod = "printf64mem";
-  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
+  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Tue Apr  7 16:37:46 2009
@@ -971,8 +971,8 @@
   } else if (MFI->hasVarSizedObjects()) {
     if (CSSize) {
       unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
-      MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
-                                      FramePtr, false, -CSSize);
+      MachineInstr *MI = addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
+                                         FramePtr, false, -CSSize);
       MBB.insert(MBBI, MI);
     } else
       BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Tue Apr  7 16:37:46 2009
@@ -168,6 +168,14 @@
 
   // Status flags register
   def EFLAGS : Register<"flags">;
+
+  // Segment registers
+  def CS : Register<"cs">;
+  def DS : Register<"ds">;
+  def SS : Register<"ss">;
+  def ES : Register<"es">;
+  def FS : Register<"fs">;
+  def GS : Register<"gs">;
 }
 
 

Modified: llvm/trunk/test/CodeGen/X86/tls10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls10.ll?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls10.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls10.ll Tue Apr  7 16:37:46 2009
@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movl	%gs:0, %eax} %t
-; RUN: grep {leal	i at NTPOFF(%eax), %eax} %t
+; RUN: grep {movl	\$i at NTPOFF, %eax} %t
+; RUN: grep {addl	%gs:0, %eax} %t
 
 @i = external hidden thread_local global i32
 

Modified: llvm/trunk/test/CodeGen/X86/tls2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls2.ll?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls2.ll Tue Apr  7 16:37:46 2009
@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movl	%gs:0, %eax} %t
-; RUN: grep {leal	i at NTPOFF(%eax), %eax} %t
+; RUN: grep {movl	\$i at NTPOFF, %eax} %t
+; RUN: grep {addl	%gs:0, %eax} %t
 
 @i = thread_local global i32 15
 

Modified: llvm/trunk/test/CodeGen/X86/tls6.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls6.ll?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls6.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls6.ll Tue Apr  7 16:37:46 2009
@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movl	%gs:0, %eax} %t
-; RUN: grep {leal	i at NTPOFF(%eax), %eax} %t
+; RUN: grep {movl	\$i at NTPOFF, %eax} %t
+; RUN: grep {addl	%gs:0, %eax} %t
 
 @i = internal thread_local global i32 15
 

Modified: llvm/trunk/test/CodeGen/X86/tls8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls8.ll?rev=68552&r1=68551&r2=68552&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls8.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls8.ll Tue Apr  7 16:37:46 2009
@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movl	%gs:0, %eax} %t
-; RUN: grep {leal	i at NTPOFF(%eax), %eax} %t
+; RUN: grep {movl	\$i at NTPOFF, %eax} %t
+; RUN: grep {addl	%gs:0, %eax} %t
 
 @i = hidden thread_local global i32 15
 




From isanbard at gmail.com  Tue Apr  7 17:17:51 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 7 Apr 2009 15:17:51 -0700
Subject: [llvm-commits] [llvm] r68552 - in /llvm/trunk: lib/Target/X86/
	lib/Target/X86/AsmPrinter/ test/CodeGen/X86/
In-Reply-To: <200904072137.n37Lbll0029223@zion.cs.uiuc.edu>
References: <200904072137.n37Lbll0029223@zion.cs.uiuc.edu>
Message-ID: <16e5fdf90904071517r30afc273o26a0f3ffa1662194@mail.gmail.com>

Rafael,

This is causing a self-hosting LLVM to fail to build:

llvm[1]: Compiling IsInf.cpp for Release build
if /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~dst/Developer/usr/bin/llvm-g++-4.2
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Support
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Support
-D_DEBUG  -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS
-O2  -fno-exceptions -fno-common  -Woverloaded-virtual  -m32 -pedantic
-Wall -W -Wwrite-strings -Wno-long-long -Wunused -Wno-unused-parameter
 -fstrict-aliasing -Wstrict-aliasing -c -MMD -MP -MF
"/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Support/Release/IsInf.d.tmp"
-MT "/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Support/Release/IsInf.o"
-MT "/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Support/Release/IsInf.d"
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Support/IsInf.cpp
-o /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Support/Release/IsInf.o
; \
	        then /bin/mv -f
"/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Support/Release/IsInf.d.tmp"
"/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Support/Release/IsInf.d";
else /bin/rm "/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Support/Release/IsInf.d.tmp";
exit 1; fi
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Support/IsInf.cpp:41:3:
error: #error "Don't know how to get isinf()"
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Support/IsInf.cpp:
In function 'int llvm::IsInf(float)':
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Support/IsInf.cpp:46:
error: 'isinf' was not declared in this scope
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Support/IsInf.cpp:
In function 'int llvm::IsInf(double)':
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Support/IsInf.cpp:47:
error: 'isinf' was not declared in this scope
make[1]: *** [/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Support/Release/IsInf.o]
Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [all] Error 1

Please investigate. Thanks!

-bw

On Tue, Apr 7, 2009 at 2:37 PM, Rafael Espindola
<rafael.espindola at gmail.com> wrote:
> Author: rafael
> Date: Tue Apr ?7 16:37:46 2009
> New Revision: 68552
>
> URL: http://llvm.org/viewvc/llvm-project?rev=68552&view=rev
> Log:
> Reduce code duplication on the TLS implementation.
> This introduces a small regression on the generated code
> quality in the case we are just computing addresses, not
> loading values.
>
> Will work on it and on X86-64 support.
>
>
> Modified:
> ? ?llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
> ? ?llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
> ? ?llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
> ? ?llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
> ? ?llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
> ? ?llvm/trunk/lib/Target/X86/X86FastISel.cpp
> ? ?llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.h
> ? ?llvm/trunk/lib/Target/X86/X86Instr64bit.td
> ? ?llvm/trunk/lib/Target/X86/X86InstrBuilder.h
> ? ?llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
> ? ?llvm/trunk/lib/Target/X86/X86InstrInfo.h
> ? ?llvm/trunk/lib/Target/X86/X86InstrInfo.td
> ? ?llvm/trunk/lib/Target/X86/X86InstrSSE.td
> ? ?llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
> ? ?llvm/trunk/lib/Target/X86/X86RegisterInfo.td
> ? ?llvm/trunk/test/CodeGen/X86/tls10.ll
> ? ?llvm/trunk/test/CodeGen/X86/tls2.ll
> ? ?llvm/trunk/test/CodeGen/X86/tls6.ll
> ? ?llvm/trunk/test/CodeGen/X86/tls8.ll
>
> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Tue Apr ?7 16:37:46 2009
> @@ -566,9 +566,8 @@
> ? }
> ?}
>
> -void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char *Modifier){
> - ?assert(isMem(MI, Op) && "Invalid memory reference!");
> +void X86ATTAsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char *Modifier){
> ? MachineOperand BaseReg ?= MI->getOperand(Op);
> ? MachineOperand IndexReg = MI->getOperand(Op+2);
> ? const MachineOperand &DispSpec = MI->getOperand(Op+3);
> @@ -611,6 +610,17 @@
> ? }
> ?}
>
> +void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char *Modifier){
> + ?assert(isMem(MI, Op) && "Invalid memory reference!");
> + ?MachineOperand Segment = MI->getOperand(Op+4);
> + ?if (Segment.getReg()) {
> + ? ? ?printOperand(MI, Op+4, Modifier);
> + ? ? ?O << ':';
> + ? ?}
> + ?printLeaMemReference(MI, Op, Modifier);
> +}
> +
> ?void X86ATTAsmPrinter::printPICJumpTableSetLabel(unsigned uid,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MachineBasicBlock *MBB) const {
> ? if (!TAI->getSetDirective())
>
> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original)
> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Tue Apr ?7 16:37:46 2009
> @@ -93,8 +93,14 @@
> ? void printf128mem(const MachineInstr *MI, unsigned OpNo) {
> ? ? printMemReference(MI, OpNo);
> ? }
> + ?void printlea32mem(const MachineInstr *MI, unsigned OpNo) {
> + ? ?printLeaMemReference(MI, OpNo);
> + ?}
> + ?void printlea64mem(const MachineInstr *MI, unsigned OpNo) {
> + ? ?printLeaMemReference(MI, OpNo);
> + ?}
> ? void printlea64_32mem(const MachineInstr *MI, unsigned OpNo) {
> - ? ?printMemReference(MI, OpNo, "subreg64");
> + ? ?printLeaMemReference(MI, OpNo, "subreg64");
> ? }
>
> ? bool printAsmMRegister(const MachineOperand &MO, const char Mode);
> @@ -107,6 +113,8 @@
> ? void printSSECC(const MachineInstr *MI, unsigned Op);
> ? void printMemReference(const MachineInstr *MI, unsigned Op,
> ? ? ? ? ? ? ? ? ? ? ? ? ?const char *Modifier=NULL);
> + ?void printLeaMemReference(const MachineInstr *MI, unsigned Op,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char *Modifier=NULL);
> ? void printPICJumpTableSetLabel(unsigned uid,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MachineBasicBlock *MBB) const;
> ? void printPICJumpTableSetLabel(unsigned uid, unsigned uid2,
>
> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp Tue Apr ?7 16:37:46 2009
> @@ -271,10 +271,9 @@
> ? }
> ?}
>
> -void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char *Modifier) {
> - ?assert(isMem(MI, Op) && "Invalid memory reference!");
> -
> +void X86IntelAsmPrinter::printLeaMemReference(const MachineInstr *MI,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned Op,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char *Modifier) {
> ? const MachineOperand &BaseReg ?= MI->getOperand(Op);
> ? int ScaleVal ? ? ? ? ? ? ? ? ? = MI->getOperand(Op+1).getImm();
> ? const MachineOperand &IndexReg = MI->getOperand(Op+2);
> @@ -317,6 +316,17 @@
> ? O << "]";
> ?}
>
> +void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char *Modifier) {
> + ?assert(isMem(MI, Op) && "Invalid memory reference!");
> + ?MachineOperand Segment = MI->getOperand(Op+4);
> + ?if (Segment.getReg()) {
> + ? ? ?printOperand(MI, Op+4, Modifier);
> + ? ? ?O << ':';
> + ? ?}
> + ?printLeaMemReference(MI, Op, Modifier);
> +}
> +
> ?void X86IntelAsmPrinter::printPICJumpTableSetLabel(unsigned uid,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MachineBasicBlock *MBB) const {
> ? if (!TAI->getSetDirective())
>
> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h (original)
> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h Tue Apr ?7 16:37:46 2009
> @@ -88,9 +88,17 @@
> ? ? O << "XMMWORD PTR ";
> ? ? printMemReference(MI, OpNo);
> ? }
> + ?void printlea32mem(const MachineInstr *MI, unsigned OpNo) {
> + ? ?O << "DWORD PTR ";
> + ? ?printLeaMemReference(MI, OpNo);
> + ?}
> + ?void printlea64mem(const MachineInstr *MI, unsigned OpNo) {
> + ? ?O << "QWORD PTR ";
> + ? ?printLeaMemReference(MI, OpNo);
> + ?}
> ? void printlea64_32mem(const MachineInstr *MI, unsigned OpNo) {
> ? ? O << "QWORD PTR ";
> - ? ?printMemReference(MI, OpNo, "subreg64");
> + ? ?printLeaMemReference(MI, OpNo, "subreg64");
> ? }
>
> ? bool printAsmMRegister(const MachineOperand &MO, const char Mode);
> @@ -103,6 +111,8 @@
> ? void printSSECC(const MachineInstr *MI, unsigned Op);
> ? void printMemReference(const MachineInstr *MI, unsigned Op,
> ? ? ? ? ? ? ? ? ? ? ? ? ?const char *Modifier=NULL);
> + ?void printLeaMemReference(const MachineInstr *MI, unsigned Op,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char *Modifier=NULL);
> ? void printPICJumpTableSetLabel(unsigned uid,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MachineBasicBlock *MBB) const;
> ? void printPICJumpTableSetLabel(unsigned uid, unsigned uid2,
>
> Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Tue Apr ?7 16:37:46 2009
> @@ -533,23 +533,6 @@
> ? ? case X86::DWARF_LOC:
> ? ? case X86::FP_REG_KILL:
> ? ? ? break;
> - ? ?case X86::TLS_tp: {
> - ? ? ?MCE.emitByte(BaseOpcode);
> - ? ? ?unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg());
> - ? ? ?MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
> - ? ? ?emitConstant(0, 4);
> - ? ? ?break;
> - ? ?}
> - ? ?case X86::TLS_gs_ri: {
> - ? ? ?MCE.emitByte(BaseOpcode);
> - ? ? ?unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg());
> - ? ? ?MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
> - ? ? ?GlobalValue* GV = MI.getOperand(1).getGlobal();
> - ? ? ?unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
> - ? ? ? ?: (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
> - ? ? ?emitGlobalAddress(GV, rt);
> - ? ? ?break;
> - ? ?}
> ? ? case X86::MOVPC32r: {
> ? ? ? // This emits the "call" portion of this pseudo instruction.
> ? ? ? MCE.emitByte(BaseOpcode);
> @@ -661,13 +644,21 @@
> ? ? break;
>
> ? case X86II::MRMSrcMem: {
> - ? ?intptr_t PCAdj = (CurOp + X86AddrNumOperands + 1 != NumOps) ?
> + ? ?// FIXME: Maybe lea should have its own form?
> + ? ?int AddrOperands;
> + ? ?if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
> + ? ? ? ?Opcode == X86::LEA16r || Opcode == X86::LEA32r)
> + ? ? ?AddrOperands = X86AddrNumOperands - 1; // No segment register
> + ? ?else
> + ? ? ?AddrOperands = X86AddrNumOperands;
> +
> + ? ?intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
> ? ? ? X86InstrInfo::sizeOfImm(Desc) : 0;
>
> ? ? MCE.emitByte(BaseOpcode);
> ? ? emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
> ? ? ? ? ? ? ? ? ? ? ?PCAdj);
> - ? ?CurOp += X86AddrNumOperands + 1;
> + ? ?CurOp += AddrOperands + 1;
> ? ? if (CurOp != NumOps)
> ? ? ? emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
> ? ? break;
>
> Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Tue Apr ?7 16:37:46 2009
> @@ -1490,7 +1490,7 @@
> ? ? ? else
> ? ? ? ? Opc = X86::LEA64r;
> ? ? ? unsigned ResultReg = createResultReg(RC);
> - ? ? ?addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
> + ? ? ?addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
> ? ? ? return ResultReg;
> ? ? }
> ? ? return 0;
> @@ -1535,7 +1535,7 @@
> ? unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
> ? TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
> ? unsigned ResultReg = createResultReg(RC);
> - ?addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
> + ?addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
> ? return ResultReg;
> ?}
>
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Apr ?7 16:37:46 2009
> @@ -69,6 +69,7 @@
> ? ? unsigned Scale;
> ? ? SDValue IndexReg;
> ? ? int32_t Disp;
> + ? ?SDValue Segment;
> ? ? GlobalValue *GV;
> ? ? Constant *CP;
> ? ? const char *ES;
> @@ -77,7 +78,7 @@
>
> ? ? X86ISelAddressMode()
> ? ? ? : BaseType(RegBase), isRIPRel(false), Scale(1), IndexReg(), Disp(0),
> - ? ? ? ?GV(0), CP(0), ES(0), JT(-1), Align(0) {
> + ? ? ? ?Segment(), GV(0), CP(0), ES(0), JT(-1), Align(0) {
> ? ? }
>
> ? ? bool hasSymbolicDisplacement() const {
> @@ -159,20 +160,25 @@
> ? ? SDNode *Select(SDValue N);
> ? ? SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
>
> + ? ?bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM);
> + ? ?bool MatchLoad(SDValue N, X86ISelAddressMode &AM);
> ? ? bool MatchAddress(SDValue N, X86ISelAddressMode &AM,
> ? ? ? ? ? ? ? ? ? ? ? unsigned Depth = 0);
> ? ? bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
> ? ? bool SelectAddr(SDValue Op, SDValue N, SDValue &Base,
> - ? ? ? ? ? ? ? ? ? ?SDValue &Scale, SDValue &Index, SDValue &Disp);
> + ? ? ? ? ? ? ? ? ? ?SDValue &Scale, SDValue &Index, SDValue &Disp,
> + ? ? ? ? ? ? ? ? ? ?SDValue &Segment);
> ? ? bool SelectLEAAddr(SDValue Op, SDValue N, SDValue &Base,
> ? ? ? ? ? ? ? ? ? ? ? ?SDValue &Scale, SDValue &Index, SDValue &Disp);
> ? ? bool SelectScalarSSELoad(SDValue Op, SDValue Pred,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SDValue N, SDValue &Base, SDValue &Scale,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SDValue &Index, SDValue &Disp,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDValue &Segment,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SDValue &InChain, SDValue &OutChain);
> ? ? bool TryFoldLoad(SDValue P, SDValue N,
> ? ? ? ? ? ? ? ? ? ? ?SDValue &Base, SDValue &Scale,
> - ? ? ? ? ? ? ? ? ? ? SDValue &Index, SDValue &Disp);
> + ? ? ? ? ? ? ? ? ? ? SDValue &Index, SDValue &Disp,
> + ? ? ? ? ? ? ? ? ? ? SDValue &Segment);
> ? ? void PreprocessForRMW();
> ? ? void PreprocessForFPConvert();
>
> @@ -186,7 +192,7 @@
>
> ? ? inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SDValue &Scale, SDValue &Index,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDValue &Disp) {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDValue &Disp, SDValue &Segment) {
> ? ? ? Base ?= (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
> ? ? ? ? CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
> ? ? ? ? AM.Base.Reg;
> @@ -205,6 +211,11 @@
> ? ? ? ? Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32);
> ? ? ? else
> ? ? ? ? Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
> +
> + ? ? ?if (AM.Segment.getNode())
> + ? ? ? ?Segment = AM.Segment;
> + ? ? ?else
> + ? ? ? ?Segment = CurDAG->getRegister(0, MVT::i32);
> ? ? }
>
> ? ? /// getI8Imm - Return a target constant with the specified value, of type
> @@ -726,6 +737,33 @@
> ? ? EmitSpecialCodeForMain(BB, MF.getFrameInfo());
> ?}
>
> +
> +bool X86DAGToDAGISel::MatchSegmentBaseAddress(SDValue N,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?X86ISelAddressMode &AM) {
> + ?assert(N.getOpcode() == X86ISD::SegmentBaseAddress);
> + ?SDValue Segment = N.getOperand(0);
> +
> + ?if (AM.Segment.getNode() == 0) {
> + ? ?AM.Segment = Segment;
> + ? ?return false;
> + ?}
> +
> + ?return true;
> +}
> +
> +bool X86DAGToDAGISel::MatchLoad(SDValue N, X86ISelAddressMode &AM) {
> + ?// This optimization is valid because the GNU TLS model defines that
> + ?// gs:0 (or fs:0 on X86-64) contains its own address.
> + ?// For more information see http://people.redhat.com/drepper/tls.pdf
> +
> + ?SDValue Address = N.getOperand(1);
> + ?if (Address.getOpcode() == X86ISD::SegmentBaseAddress &&
> + ? ? ?!MatchSegmentBaseAddress (Address, AM))
> + ? ?return false;
> +
> + ?return true;
> +}
> +
> ?/// MatchAddress - Add the specified node to the specified addressing mode,
> ?/// returning true if it cannot be done. ?This just pattern matches for the
> ?/// addressing mode.
> @@ -761,6 +799,11 @@
> ? ? break;
> ? }
>
> + ?case X86ISD::SegmentBaseAddress:
> + ? ?if (!MatchSegmentBaseAddress(N, AM))
> + ? ? ?return false;
> + ? ?break;
> +
> ? case X86ISD::Wrapper: {
> ? ? DOUT << "Wrapper: 64bit " << is64Bit;
> ? ? DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n";
> @@ -807,6 +850,11 @@
> ? ? break;
> ? }
>
> + ?case ISD::LOAD:
> + ? ?if (!MatchLoad(N, AM))
> + ? ? ?return false;
> + ? ?break;
> +
> ? case ISD::FrameIndex:
> ? ? if (AM.BaseType == X86ISelAddressMode::RegBase
> ? ? ? ? && AM.Base.Reg.getNode() == 0) {
> @@ -1034,7 +1082,7 @@
> ?/// match by reference.
> ?bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SDValue &Scale, SDValue &Index,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDValue &Disp) {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDValue &Disp, SDValue &Segment) {
> ? X86ISelAddressMode AM;
> ? bool Done = false;
> ? if (AvoidDupAddrCompute && !N.hasOneUse()) {
> @@ -1069,7 +1117,7 @@
> ? if (!AM.IndexReg.getNode())
> ? ? AM.IndexReg = CurDAG->getRegister(0, VT);
>
> - ?getAddressOperands(AM, Base, Scale, Index, Disp);
> + ?getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
> ? return true;
> ?}
>
> @@ -1079,7 +1127,8 @@
> ?bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDValue N, SDValue &Base,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDValue &Scale, SDValue &Index,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SDValue &Disp, SDValue &InChain,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SDValue &Disp, SDValue &Segment,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SDValue &InChain,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDValue &OutChain) {
> ? if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
> ? ? InChain = N.getOperand(0).getValue(1);
> @@ -1088,7 +1137,7 @@
> ? ? ? ? N.hasOneUse() &&
> ? ? ? ? IsLegalAndProfitableToFold(N.getNode(), Pred.getNode(), Op.getNode())) {
> ? ? ? LoadSDNode *LD = cast<LoadSDNode>(InChain);
> - ? ? ?if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
> + ? ? ?if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
> ? ? ? ? return false;
> ? ? ? OutChain = LD->getChain();
> ? ? ? return true;
> @@ -1105,7 +1154,7 @@
> ? ? ? N.getOperand(0).getOperand(0).hasOneUse()) {
> ? ? // Okay, this is a zero extending load. ?Fold it.
> ? ? LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
> - ? ?if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
> + ? ?if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
> ? ? ? return false;
> ? ? OutChain = LD->getChain();
> ? ? InChain = SDValue(LD, 1);
> @@ -1124,6 +1173,11 @@
> ? if (MatchAddress(N, AM))
> ? ? return false;
>
> + ?//Is it better to set AM.Segment before calling MatchAddress to
> + ?//prevent it from adding a segment?
> + ?if (AM.Segment.getNode())
> + ? ?return false;
> +
> ? MVT VT = N.getValueType();
> ? unsigned Complexity = 0;
> ? if (AM.BaseType == X86ISelAddressMode::RegBase)
> @@ -1162,7 +1216,8 @@
> ? ? Complexity++;
>
> ? if (Complexity > 2) {
> - ? ?getAddressOperands(AM, Base, Scale, Index, Disp);
> + ? ?SDValue Segment;
> + ? ?getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
> ? ? return true;
> ? }
> ? return false;
> @@ -1170,11 +1225,12 @@
>
> ?bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDValue &Base, SDValue &Scale,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SDValue &Index, SDValue &Disp) {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SDValue &Index, SDValue &Disp,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SDValue &Segment) {
> ? if (ISD::isNON_EXTLoad(N.getNode()) &&
> ? ? ? N.hasOneUse() &&
> ? ? ? IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
> - ? ?return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp);
> + ? ?return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp, Segment);
> ? return false;
> ?}
>
> @@ -1230,11 +1286,11 @@
> ? SDValue In1 = Node->getOperand(1);
> ? SDValue In2L = Node->getOperand(2);
> ? SDValue In2H = Node->getOperand(3);
> - ?SDValue Tmp0, Tmp1, Tmp2, Tmp3;
> - ?if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3))
> + ?SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
> + ?if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
> ? ? return NULL;
> ? SDValue LSI = Node->getOperand(4); ? ?// MemOperand
> - ?const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, In2L, In2H, LSI, Chain };
> + ?const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, LSI, Chain};
> ? return CurDAG->getTargetNode(Opc, Node->getDebugLoc(),
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MVT::i32, MVT::i32, MVT::Other, Ops,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?array_lengthof(Ops));
> @@ -1316,11 +1372,11 @@
> ? ? ? case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
> ? ? ? }
>
> - ? ? ?SDValue Tmp0, Tmp1, Tmp2, Tmp3;
> - ? ? ?bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
> + ? ? ?SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
> + ? ? ?bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
> ? ? ? // multiplty is commmutative
> ? ? ? if (!foldedLoad) {
> - ? ? ? ?foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
> + ? ? ? ?foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
> ? ? ? ? if (foldedLoad)
> ? ? ? ? ? std::swap(N0, N1);
> ? ? ? }
> @@ -1329,7 +1385,8 @@
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? N0, SDValue()).getValue(1);
>
> ? ? ? if (foldedLoad) {
> - ? ? ? ?SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
> + ? ? ? ?SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
> + ? ? ? ? ? ? ? ? ? ? ? ? ?InFlag };
> ? ? ? ? SDNode *CNode =
> ? ? ? ? ? CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? array_lengthof(Ops));
> @@ -1438,17 +1495,17 @@
> ? ? ? ? break;
> ? ? ? }
>
> - ? ? ?SDValue Tmp0, Tmp1, Tmp2, Tmp3;
> - ? ? ?bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
> + ? ? ?SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
> + ? ? ?bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
> ? ? ? bool signBitIsZero = CurDAG->SignBitIsZero(N0);
>
> ? ? ? SDValue InFlag;
> ? ? ? if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
> ? ? ? ? // Special case for div8, just use a move with zero extension to AX to
> ? ? ? ? // clear the upper 8 bits (AH).
> - ? ? ? ?SDValue Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
> - ? ? ? ?if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) {
> - ? ? ? ? ?SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
> + ? ? ? ?SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
> + ? ? ? ?if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
> + ? ? ? ? ?SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
> ? ? ? ? ? Move =
> ? ? ? ? ? ? SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, MVT::i16,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MVT::Other, Ops,
> @@ -1480,7 +1537,8 @@
> ? ? ? }
>
> ? ? ? if (foldedLoad) {
> - ? ? ? ?SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
> + ? ? ? ?SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
> + ? ? ? ? ? ? ? ? ? ? ? ? ?InFlag };
> ? ? ? ? SDNode *CNode =
> ? ? ? ? ? CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? array_lengthof(Ops));
> @@ -1649,13 +1707,13 @@
> ?bool X86DAGToDAGISel::
> ?SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?std::vector<SDValue> &OutOps) {
> - ?SDValue Op0, Op1, Op2, Op3;
> + ?SDValue Op0, Op1, Op2, Op3, Op4;
> ? switch (ConstraintCode) {
> ? case 'o': ? // offsetable ? ? ? ???
> ? case 'v': ? // not offsetable ? ???
> ? default: return true;
> ? case 'm': ? // memory
> - ? ?if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3))
> + ? ?if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3, Op4))
> ? ? ? return true;
> ? ? break;
> ? }
> @@ -1664,6 +1722,7 @@
> ? OutOps.push_back(Op1);
> ? OutOps.push_back(Op2);
> ? OutOps.push_back(Op3);
> + ?OutOps.push_back(Op4);
> ? return false;
> ?}
>
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Apr ?7 16:37:46 2009
> @@ -4834,8 +4834,13 @@
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MVT PtrVT, TLSModel::Model model) {
> ? DebugLoc dl = GA->getDebugLoc();
> ? // Get the Thread Pointer
> - ?SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DebugLoc::getUnknownLoc(), PtrVT);
> + ?SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? DebugLoc::getUnknownLoc(), PtrVT,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? DAG.getRegister(X86::GS, MVT::i32));
> +
> + ?SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?NULL, 0);
> +
> ? // emit "addl x at ntpoff,%eax" (local exec) or "addl x at indntpoff,%eax" (initial
> ? // exec)
> ? SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
> @@ -7149,7 +7154,7 @@
> ? case X86ISD::FRSQRT: ? ? ? ? ? ? return "X86ISD::FRSQRT";
> ? case X86ISD::FRCP: ? ? ? ? ? ? ? return "X86ISD::FRCP";
> ? case X86ISD::TLSADDR: ? ? ? ? ? ?return "X86ISD::TLSADDR";
> - ?case X86ISD::THREAD_POINTER: ? ? return "X86ISD::THREAD_POINTER";
> + ?case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
> ? case X86ISD::EH_RETURN: ? ? ? ? ?return "X86ISD::EH_RETURN";
> ? case X86ISD::TC_RETURN: ? ? ? ? ?return "X86ISD::TC_RETURN";
> ? case X86ISD::FNSTCW16m: ? ? ? ? ?return "X86ISD::FNSTCW16m";
> @@ -7473,7 +7478,7 @@
> ? unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
> ? MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
> ? // add 4 to displacement.
> - ?for (int i=0; i <= lastAddrIndx-1; ++i)
> + ?for (int i=0; i <= lastAddrIndx-2; ++i)
> ? ? (*MIB).addOperand(*argOpers[i]);
> ? MachineOperand newOp3 = *(argOpers[3]);
> ? if (newOp3.isImm())
> @@ -7481,6 +7486,7 @@
> ? else
> ? ? newOp3.setOffset(newOp3.getOffset()+4);
> ? (*MIB).addOperand(newOp3);
> + ?(*MIB).addOperand(*argOpers[lastAddrIndx]);
>
> ? // t3/4 are defined later, at the bottom of the loop
> ? unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Apr ?7 16:37:46 2009
> @@ -188,8 +188,11 @@
> ? ? ? /// in order to obtain suitable precision.
> ? ? ? FRSQRT, FRCP,
>
> - ? ? ?// TLSADDR, THREAD_POINTER - Thread Local Storage.
> - ? ? ?TLSADDR, THREAD_POINTER,
> + ? ? ?// TLSADDR - Thread Local Storage.
> + ? ? ?TLSADDR,
> +
> + ? ? ?// SegmentBaseAddress - The address segment:0
> + ? ? ?SegmentBaseAddress,
>
> ? ? ? // EH_RETURN - Exception Handling helpers.
> ? ? ? EH_RETURN,
>
> Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
> +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Tue Apr ?7 16:37:46 2009
> @@ -23,7 +23,7 @@
> ?def i64i8imm ? : Operand<i64>;
>
> ?def lea64mem : Operand<i64> {
> - ?let PrintMethod = "printi64mem";
> + ?let PrintMethod = "printlea64mem";
> ? let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
> ?}
>
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrBuilder.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrBuilder.h?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrBuilder.h (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrBuilder.h Tue Apr ?7 16:37:46 2009
> @@ -66,6 +66,15 @@
> ? return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0);
> ?}
>
> +inline const MachineInstrBuilder &addLeaOffset(const MachineInstrBuilder &MIB,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int Offset) {
> + ?return MIB.addImm(1).addReg(0).addImm(Offset);
> +}
> +
> +inline const MachineInstrBuilder &addOffset(const MachineInstrBuilder &MIB,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int Offset) {
> + ?return addLeaOffset(MIB, Offset).addReg(0);
> +}
>
> ?/// addRegOffset - This function is used to add a memory reference of the form
> ?/// [Reg + Offset], i.e., one with no scale or index, but with a
> @@ -74,8 +83,13 @@
> ?inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned Reg, bool isKill,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int Offset) {
> - ?return MIB.addReg(Reg, false, false, isKill)
> - ? ?.addImm(1).addReg(0).addImm(Offset);
> + ?return addOffset(MIB.addReg(Reg, false, false, isKill), Offset);
> +}
> +
> +inline const MachineInstrBuilder &addLeaRegOffset(const MachineInstrBuilder &MIB,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned Reg, bool isKill,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int Offset) {
> + ?return addLeaOffset(MIB.addReg(Reg, false, false, isKill), Offset);
> ?}
>
> ?/// addRegReg - This function is used to add a memory reference of the form:
> @@ -87,8 +101,8 @@
> ? ? .addReg(Reg2, false, false, isKill2).addImm(0);
> ?}
>
> -inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const X86AddressMode &AM) {
> +inline const MachineInstrBuilder &addLeaAddress(const MachineInstrBuilder &MIB,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const X86AddressMode &AM) {
> ? assert (AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
>
> ? if (AM.BaseType == X86AddressMode::RegBase)
> @@ -104,6 +118,11 @@
> ? ? return MIB.addImm(AM.Disp);
> ?}
>
> +inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const X86AddressMode &AM) {
> + ?return addLeaAddress(MIB, AM).addReg(0);
> +}
> +
> ?/// addFrameReference - This function is used to add a reference to the base of
> ?/// an abstract object on the stack frame of the current function. ?This
> ?/// reference has base register as the FrameIndex offset until it is resolved.
> @@ -125,7 +144,7 @@
> ? ? ? ? ? ? ? ? ? ? ? ? MFI.getObjectOffset(FI) + Offset,
> ? ? ? ? ? ? ? ? ? ? ? ? MFI.getObjectSize(FI),
> ? ? ? ? ? ? ? ? ? ? ? ? MFI.getObjectAlignment(FI));
> - ?return MIB.addFrameIndex(FI).addImm(1).addReg(0).addImm(Offset)
> + ?return addOffset(MIB.addFrameIndex(FI), Offset)
> ? ? ? ? ? ? .addMemOperand(MMO);
> ?}
>
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Apr ?7 16:37:46 2009
> @@ -1138,9 +1138,9 @@
> ? ? ? assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
> ? ? ? unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
> ? ? ? ? : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
> - ? ? ?NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
> - ? ? ? ? ? ? ? ? ? ? ? ? ? .addReg(Dest, true, false, false, isDead),
> - ? ? ? ? ? ? ? ? ? ? ? ? ? Src, isKill, 1);
> + ? ? ?NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?.addReg(Dest, true, false, false, isDead),
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Src, isKill, 1);
> ? ? ? break;
> ? ? }
> ? ? case X86::INC16r:
> @@ -1157,9 +1157,9 @@
> ? ? ? assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
> ? ? ? unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
> ? ? ? ? : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
> - ? ? ?NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
> - ? ? ? ? ? ? ? ? ? ? ? ? ? .addReg(Dest, true, false, false, isDead),
> - ? ? ? ? ? ? ? ? ? ? ? ? ? Src, isKill, -1);
> + ? ? ?NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?.addReg(Dest, true, false, false, isDead),
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Src, isKill, -1);
> ? ? ? break;
> ? ? }
> ? ? case X86::DEC16r:
> @@ -1200,18 +1200,18 @@
> ? ? case X86::ADD64ri8:
> ? ? ? assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
> ? ? ? if (MI->getOperand(2).isImm())
> - ? ? ? ?NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? .addReg(Dest, true, false, false, isDead),
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? Src, isKill, MI->getOperand(2).getImm());
> + ? ? ? ?NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?.addReg(Dest, true, false, false, isDead),
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Src, isKill, MI->getOperand(2).getImm());
> ? ? ? break;
> ? ? case X86::ADD32ri:
> ? ? case X86::ADD32ri8:
> ? ? ? assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
> ? ? ? if (MI->getOperand(2).isImm()) {
> ? ? ? ? unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
> - ? ? ? ?NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? .addReg(Dest, true, false, false, isDead),
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? Src, isKill, MI->getOperand(2).getImm());
> + ? ? ? ?NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?.addReg(Dest, true, false, false, isDead),
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Src, isKill, MI->getOperand(2).getImm());
> ? ? ? }
> ? ? ? break;
> ? ? case X86::ADD16ri:
> @@ -1959,7 +1959,7 @@
> ? for (unsigned i = 0; i != NumAddrOps; ++i)
> ? ? MIB.addOperand(MOs[i]);
> ? if (NumAddrOps < 4) ?// FrameIndex only
> - ? ?MIB.addImm(1).addReg(0).addImm(0);
> + ? ?addOffset(MIB, 0);
>
> ? // Loop over the rest of the ri operands, converting them over.
> ? unsigned NumOps = MI->getDesc().getNumOperands()-2;
> @@ -1990,7 +1990,7 @@
> ? ? ? for (unsigned i = 0; i != NumAddrOps; ++i)
> ? ? ? ? MIB.addOperand(MOs[i]);
> ? ? ? if (NumAddrOps < 4) ?// FrameIndex only
> - ? ? ? ?MIB.addImm(1).addReg(0).addImm(0);
> + ? ? ? ?addOffset(MIB, 0);
> ? ? } else {
> ? ? ? MIB.addOperand(MO);
> ? ? }
> @@ -2008,7 +2008,7 @@
> ? for (unsigned i = 0; i != NumAddrOps; ++i)
> ? ? MIB.addOperand(MOs[i]);
> ? if (NumAddrOps < 4) ?// FrameIndex only
> - ? ?MIB.addImm(1).addReg(0).addImm(0);
> + ? ?addOffset(MIB, 0);
> ? return MIB.addImm(0);
> ?}
>
> @@ -2164,7 +2164,7 @@
> ? } else if (Ops.size() != 1)
> ? ? return NULL;
>
> - ?SmallVector<MachineOperand,4> MOs;
> + ?SmallVector<MachineOperand,X86AddrNumOperands> MOs;
> ? if (LoadMI->getOpcode() == X86::V_SET0 ||
> ? ? ? LoadMI->getOpcode() == X86::V_SETALLONES) {
> ? ? // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
> @@ -2193,6 +2193,7 @@
> ? ? MOs.push_back(MachineOperand::CreateImm(1));
> ? ? MOs.push_back(MachineOperand::CreateReg(0, false));
> ? ? MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
> + ? ?MOs.push_back(MachineOperand::CreateReg(0, false));
> ? } else {
> ? ? // Folding a normal load. Just copy the load's address operands.
> ? ? unsigned NumOps = LoadMI->getDesc().getNumOperands();
> @@ -2882,11 +2883,6 @@
> ? ? ? FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
> ? ? ? break;
> ? ? }
> - ? ?case X86::TLS_tp:
> - ? ?case X86::TLS_gs_ri:
> - ? ? ?FinalSize += 2;
> - ? ? ?FinalSize += sizeGlobalAddress(false);
> - ? ? ?break;
> ? ? }
> ? ? CurOp = NumOps;
> ? ? break;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Tue Apr ?7 16:37:46 2009
> @@ -243,7 +243,7 @@
> ? };
> ?}
>
> -const int X86AddrNumOperands = 4;
> +const int X86AddrNumOperands = 5;
>
> ?inline static bool isScale(const MachineOperand &MO) {
> ? return MO.isImm() &&
> @@ -251,7 +251,7 @@
> ? ? ?MO.getImm() == 4 || MO.getImm() == 8);
> ?}
>
> -inline static bool isMem(const MachineInstr *MI, unsigned Op) {
> +inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
> ? if (MI->getOperand(Op).isFI()) return true;
> ? return Op+4 <= MI->getNumOperands() &&
> ? ? MI->getOperand(Op ?).isReg() && isScale(MI->getOperand(Op+1)) &&
> @@ -262,6 +262,13 @@
> ? ? ?MI->getOperand(Op+3).isJTI());
> ?}
>
> +inline static bool isMem(const MachineInstr *MI, unsigned Op) {
> + ?if (MI->getOperand(Op).isFI()) return true;
> + ?return Op+5 <= MI->getNumOperands() &&
> + ? ?MI->getOperand(Op+4).isReg() &&
> + ? ?isLeaMem(MI, Op);
> +}
> +
> ?class X86InstrInfo : public TargetInstrInfoImpl {
> ? X86TargetMachine &TM;
> ? const X86RegisterInfo RI;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Apr ?7 16:37:46 2009
> @@ -65,7 +65,7 @@
>
> ?def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
>
> -def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
> +def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
>
> ?def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
>
> @@ -142,7 +142,8 @@
>
> ?def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
> ? ? ? ? ? ? ? ? ? ? ? ? [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
> -def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
> +def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDT_X86SegmentBaseAddress, []>;
>
> ?def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
> ? ? ? ? ? ? ? ? ? ? ? ? [SDNPHasChain]>;
> @@ -167,7 +168,7 @@
> ?//
> ?class X86MemOperand<string printMethod> : Operand<iPTR> {
> ? let PrintMethod = printMethod;
> - ?let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
> + ?let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
> ?}
>
> ?def i8mem ? : X86MemOperand<"printi8mem">;
> @@ -181,7 +182,7 @@
> ?def f128mem : X86MemOperand<"printf128mem">;
>
> ?def lea32mem : Operand<i32> {
> - ?let PrintMethod = "printi32mem";
> + ?let PrintMethod = "printlea32mem";
> ? let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
> ?}
>
> @@ -207,7 +208,7 @@
> ?//
>
> ?// Define X86 specific addressing mode.
> -def addr ? ? ?: ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
> +def addr ? ? ?: ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
> ?def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?[add, mul, shl, or, frameindex], []>;
>
> @@ -2922,101 +2923,11 @@
> ?// Thread Local Storage Instructions
> ?//
>
> -// FIXME: there is duplication with the non-TLS case.
> -// There is a suggestion on how to fix this at
> -// http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090309/075212.html
> -
> ?let Uses = [EBX] in
> ?def TLS_addr32 : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
> ? ? ? ? ? ? ? ? ? "leal\t${sym:mem}(,%ebx,1), $dst",
> ? ? ? ? ? ? ? ? ? [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
>
> -let AddedComplexity = 10 in
> -def TLS_gs_rr ?: I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
> - ? ? ? ? ? ? ? ? ?"movl\t%gs:($src), $dst",
> - ? ? ? ? ? ? ? ? ?[(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
> -
> -let AddedComplexity = 15 in
> -def TLS_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
> - ? ? ? ? ? ? ? ? ?"movl\t%gs:${src:mem}, $dst",
> - ? ? ? ? ? ? ? ? ?[(set GR32:$dst,
> - ? ? ? ? ? ? ? ? ? ?(load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>,
> - ? ? ? ? ? ? ? ? ?SegGS;
> -
> -let AddedComplexity = 15 in
> -def TLS16_gs_ri : I<0x8B, Pseudo, (outs GR16:$dst), (ins i32imm:$src),
> - ? ? ? ? ? ? ? ? ? ?"movw\t%gs:${src:mem}, $dst",
> - ? ? ? ? ? ? ? ? ? ?[(set GR16:$dst,
> - ? ? ? ? ? ? ? ? ? ? ?(load (add X86TLStp,
> - ? ? ? ? ? ? ? ? ? ? ? ?(X86Wrapper tglobaltlsaddr:$src))))]>,
> - ? ? ? ? ? ? ? ? ? ?SegGS;
> -
> -let AddedComplexity = 15 in
> -def TLS8_gs_ri : I<0x8B, Pseudo, (outs GR8:$dst), (ins i32imm:$src),
> - ? ? ? ? ? ? ? ? ? "movb\t%gs:${src:mem}, $dst",
> - ? ? ? ? ? ? ? ? ? [(set GR8:$dst,
> - ? ? ? ? ? ? ? ? ? ? (load (add X86TLStp,
> - ? ? ? ? ? ? ? ? ? ? ? (X86Wrapper tglobaltlsaddr:$src))))]>,
> - ? ? ? ? ? ? ? ? ? SegGS;
> -
> -let AddedComplexity = 15 in
> -def TLS_ext16_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
> - ? ? ? ? ? ? ? ? ? ? ? ?"movzwl\t%gs:${src:mem}, $dst",
> - ? ? ? ? ? ? ? ? ? ? ? ?[(set GR32:$dst,
> - ? ? ? ? ? ? ? ? ? ? ? ? ?(extloadi32i16
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ?(add X86TLStp,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(X86Wrapper tglobaltlsaddr:$src))))]>,
> - ? ? ? ? ? ? ? ? ? ? ? ?SegGS;
> -
> -let AddedComplexity = 15 in
> -def TLS_sext16_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
> - ? ? ? ? ? ? ? ? ? ? ? ? "movswl\t%gs:${src:mem}, $dst",
> - ? ? ? ? ? ? ? ? ? ? ? ? [(set GR32:$dst,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? (sextloadi32i16
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? (add X86TLStp,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (X86Wrapper tglobaltlsaddr:$src))))]>,
> - ? ? ? ? ? ? ? ? ? ? ? ? SegGS;
> -
> -let AddedComplexity = 15 in
> -def TLS_zext16_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
> - ? ? ? ? ? ? ? ? ? ? ? ? "movzwl\t%gs:${src:mem}, $dst",
> - ? ? ? ? ? ? ? ? ? ? ? ? [(set GR32:$dst,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? (zextloadi32i16
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? (add X86TLStp,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (X86Wrapper tglobaltlsaddr:$src))))]>,
> - ? ? ? ? ? ? ? ? ? ? ? ? SegGS;
> -
> -let AddedComplexity = 15 in
> -def TLS_ext8_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
> - ? ? ? ? ? ? ? ? ? ? ? ?"movzbl\t%gs:${src:mem}, $dst",
> - ? ? ? ? ? ? ? ? ? ? ? ?[(set GR32:$dst,
> - ? ? ? ? ? ? ? ? ? ? ? ? ?(extloadi32i8
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ?(add X86TLStp,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(X86Wrapper tglobaltlsaddr:$src))))]>,
> - ? ? ? ? ? ? ? ? ? ? ? ?SegGS;
> -
> -let AddedComplexity = 15 in
> -def TLS_sext8_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
> - ? ? ? ? ? ? ? ? ? ? ? ? "movsbl\t%gs:${src:mem}, $dst",
> - ? ? ? ? ? ? ? ? ? ? ? ? [(set GR32:$dst,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? (sextloadi32i8
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? (add X86TLStp,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (X86Wrapper tglobaltlsaddr:$src))))]>,
> - ? ? ? ? ? ? ? ? ? ? ? ? SegGS;
> -
> -let AddedComplexity = 15 in
> -def TLS_zext8_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
> - ? ? ? ? ? ? ? ? ? ? ? ? "movzbl\t%gs:${src:mem}, $dst",
> - ? ? ? ? ? ? ? ? ? ? ? ? [(set GR32:$dst,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? (zextloadi32i8
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? (add X86TLStp,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(X86Wrapper tglobaltlsaddr:$src))))]>,
> - ? ? ? ? ? ? ? ? ? ? ? ? SegGS;
> -
> -def TLS_tp : I<0x8B, Pseudo, (outs GR32:$dst), (ins),
> - ? ? ? ? ? ? ? "movl\t%gs:0, $dst",
> - ? ? ? ? ? ? ? [(set GR32:$dst, X86TLStp)]>, SegGS;
> -
> ?let AddedComplexity = 5 in
> ?def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
> ? ? ? ? ? ? ? ? ? ?"movl\t%gs:$src, $dst",
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Apr ?7 16:37:46 2009
> @@ -76,18 +76,18 @@
> ?// These are 'extloads' from a scalar to the low element of a vector, zeroing
> ?// the top elements. ?These are used for the SSE 'ss' and 'sd' instruction
> ?// forms.
> -def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
> +def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? [SDNPHasChain, SDNPMayLoad]>;
> -def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
> +def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? [SDNPHasChain, SDNPMayLoad]>;
>
> ?def ssmem : Operand<v4f32> {
> ? let PrintMethod = "printf32mem";
> - ?let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
> + ?let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
> ?}
> ?def sdmem : Operand<v2f64> {
> ? let PrintMethod = "printf64mem";
> - ?let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
> + ?let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
> ?}
>
> ?//===----------------------------------------------------------------------===//
>
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Tue Apr ?7 16:37:46 2009
> @@ -971,8 +971,8 @@
> ? } else if (MFI->hasVarSizedObjects()) {
> ? ? if (CSSize) {
> ? ? ? unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
> - ? ? ?MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?FramePtr, false, -CSSize);
> + ? ? ?MachineInstr *MI = addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? FramePtr, false, -CSSize);
> ? ? ? MBB.insert(MBBI, MI);
> ? ? } else
> ? ? ? BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
>
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Tue Apr ?7 16:37:46 2009
> @@ -168,6 +168,14 @@
>
> ? // Status flags register
> ? def EFLAGS : Register<"flags">;
> +
> + ?// Segment registers
> + ?def CS : Register<"cs">;
> + ?def DS : Register<"ds">;
> + ?def SS : Register<"ss">;
> + ?def ES : Register<"es">;
> + ?def FS : Register<"fs">;
> + ?def GS : Register<"gs">;
> ?}
>
>
>
> Modified: llvm/trunk/test/CodeGen/X86/tls10.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls10.ll?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/tls10.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/tls10.ll Tue Apr ?7 16:37:46 2009
> @@ -1,6 +1,6 @@
> ?; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
> -; RUN: grep {movl ? ? ?%gs:0, %eax} %t
> -; RUN: grep {leal ? ? ?i at NTPOFF(%eax), %eax} %t
> +; RUN: grep {movl ? ? ?\$i at NTPOFF, %eax} %t
> +; RUN: grep {addl ? ? ?%gs:0, %eax} %t
>
> ?@i = external hidden thread_local global i32
>
>
> Modified: llvm/trunk/test/CodeGen/X86/tls2.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls2.ll?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/tls2.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/tls2.ll Tue Apr ?7 16:37:46 2009
> @@ -1,6 +1,6 @@
> ?; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
> -; RUN: grep {movl ? ? ?%gs:0, %eax} %t
> -; RUN: grep {leal ? ? ?i at NTPOFF(%eax), %eax} %t
> +; RUN: grep {movl ? ? ?\$i at NTPOFF, %eax} %t
> +; RUN: grep {addl ? ? ?%gs:0, %eax} %t
>
> ?@i = thread_local global i32 15
>
>
> Modified: llvm/trunk/test/CodeGen/X86/tls6.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls6.ll?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/tls6.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/tls6.ll Tue Apr ?7 16:37:46 2009
> @@ -1,6 +1,6 @@
> ?; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
> -; RUN: grep {movl ? ? ?%gs:0, %eax} %t
> -; RUN: grep {leal ? ? ?i at NTPOFF(%eax), %eax} %t
> +; RUN: grep {movl ? ? ?\$i at NTPOFF, %eax} %t
> +; RUN: grep {addl ? ? ?%gs:0, %eax} %t
>
> ?@i = internal thread_local global i32 15
>
>
> Modified: llvm/trunk/test/CodeGen/X86/tls8.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls8.ll?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/tls8.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/tls8.ll Tue Apr ?7 16:37:46 2009
> @@ -1,6 +1,6 @@
> ?; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
> -; RUN: grep {movl ? ? ?%gs:0, %eax} %t
> -; RUN: grep {leal ? ? ?i at NTPOFF(%eax), %eax} %t
> +; RUN: grep {movl ? ? ?\$i at NTPOFF, %eax} %t
> +; RUN: grep {addl ? ? ?%gs:0, %eax} %t
>
> ?@i = hidden thread_local global i32 15
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



From skabet at gmail.com  Tue Apr  7 09:00:41 2009
From: skabet at gmail.com (Anders Johnsen)
Date: Tue, 7 Apr 2009 16:00:41 +0200
Subject: [llvm-commits] Type::getPointerTo()
Message-ID: <5be2d90904070700n6709afd7t1a6e8c08c3ef7361@mail.gmail.com>

Hi,

I'd like to suggest this patch which adds a getPointerTo() method to llvm::Type.

This will allow the following code:

myType->getPointerTo(0);  (1)

that is 100% identical to

llvm::PointerType::get(myType, 0);   (2)

My motivation for the patch is that my code is full of (2) and it's
getting somewhat ugly.

- Anders
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From dpatel at apple.com  Tue Apr  7 17:27:57 2009
From: dpatel at apple.com (Devang Patel)
Date: Tue, 07 Apr 2009 22:27:57 -0000
Subject: [llvm-commits] [llvm] r68559 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
Message-ID: <200904072227.n37MRveC031112@zion.cs.uiuc.edu>

Author: dpatel
Date: Tue Apr  7 17:27:56 2009
New Revision: 68559

URL: http://llvm.org/viewvc/llvm-project?rev=68559&view=rev
Log:
Right now DBG_LABEL are required for llvm.dbg.region_start and llvm.dbg.region_end in non-fast mode also.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=68559&r1=68558&r2=68559&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Tue Apr  7 17:27:56 2009
@@ -3926,9 +3926,8 @@
     if (DW && DW->ValidDebugInfo(RSI.getContext())) {
       unsigned LabelID =
         DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
-      if (Fast)
-        DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
-                                 getRoot(), LabelID));
+      DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
+                               getRoot(), LabelID));
     }
 
     return 0;
@@ -3939,9 +3938,8 @@
     if (DW && DW->ValidDebugInfo(REI.getContext())) {
       unsigned LabelID =
         DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
-      if (Fast)
-        DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
-                                 getRoot(), LabelID));
+      DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
+                               getRoot(), LabelID));
     }
 
     return 0;




From isanbard at gmail.com  Tue Apr  7 17:35:25 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 07 Apr 2009 22:35:25 -0000
Subject: [llvm-commits] [llvm] r68560 - in /llvm/trunk: lib/Target/X86/
 lib/Target/X86/AsmPrinter/ test/CodeGen/X86/
Message-ID: <200904072235.n37MZQlt031411@zion.cs.uiuc.edu>

Author: void
Date: Tue Apr  7 17:35:25 2009
New Revision: 68560

URL: http://llvm.org/viewvc/llvm-project?rev=68560&view=rev
Log:
Temporarily revert r68552. This was causing a failure in the self-hosting LLVM
builds.

--- Reverse-merging (from foreign repository) r68552 into '.':
U    test/CodeGen/X86/tls8.ll
U    test/CodeGen/X86/tls10.ll
U    test/CodeGen/X86/tls2.ll
U    test/CodeGen/X86/tls6.ll
U    lib/Target/X86/X86Instr64bit.td
U    lib/Target/X86/X86InstrSSE.td
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86RegisterInfo.cpp
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86CodeEmitter.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86InstrInfo.h
U    lib/Target/X86/X86ISelDAGToDAG.cpp
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U    lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U    lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U    lib/Target/X86/X86ISelLowering.h
U    lib/Target/X86/X86InstrInfo.cpp
U    lib/Target/X86/X86InstrBuilder.h
U    lib/Target/X86/X86RegisterInfo.td


Modified:
    llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
    llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
    llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
    llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
    llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
    llvm/trunk/lib/Target/X86/X86FastISel.cpp
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86Instr64bit.td
    llvm/trunk/lib/Target/X86/X86InstrBuilder.h
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.h
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
    llvm/trunk/lib/Target/X86/X86RegisterInfo.td
    llvm/trunk/test/CodeGen/X86/tls10.ll
    llvm/trunk/test/CodeGen/X86/tls2.ll
    llvm/trunk/test/CodeGen/X86/tls6.ll
    llvm/trunk/test/CodeGen/X86/tls8.ll

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Tue Apr  7 17:35:25 2009
@@ -566,8 +566,9 @@
   }
 }
 
-void X86ATTAsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op,
-                                            const char *Modifier){
+void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
+                                         const char *Modifier){
+  assert(isMem(MI, Op) && "Invalid memory reference!");
   MachineOperand BaseReg  = MI->getOperand(Op);
   MachineOperand IndexReg = MI->getOperand(Op+2);
   const MachineOperand &DispSpec = MI->getOperand(Op+3);
@@ -610,17 +611,6 @@
   }
 }
 
-void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
-                                         const char *Modifier){
-  assert(isMem(MI, Op) && "Invalid memory reference!");
-  MachineOperand Segment = MI->getOperand(Op+4);
-  if (Segment.getReg()) {
-      printOperand(MI, Op+4, Modifier);
-      O << ':';
-    }
-  printLeaMemReference(MI, Op, Modifier);
-}
-
 void X86ATTAsmPrinter::printPICJumpTableSetLabel(unsigned uid,
                                            const MachineBasicBlock *MBB) const {
   if (!TAI->getSetDirective())

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Tue Apr  7 17:35:25 2009
@@ -93,14 +93,8 @@
   void printf128mem(const MachineInstr *MI, unsigned OpNo) {
     printMemReference(MI, OpNo);
   }
-  void printlea32mem(const MachineInstr *MI, unsigned OpNo) {
-    printLeaMemReference(MI, OpNo);
-  }
-  void printlea64mem(const MachineInstr *MI, unsigned OpNo) {
-    printLeaMemReference(MI, OpNo);
-  }
   void printlea64_32mem(const MachineInstr *MI, unsigned OpNo) {
-    printLeaMemReference(MI, OpNo, "subreg64");
+    printMemReference(MI, OpNo, "subreg64");
   }
 
   bool printAsmMRegister(const MachineOperand &MO, const char Mode);
@@ -113,8 +107,6 @@
   void printSSECC(const MachineInstr *MI, unsigned Op);
   void printMemReference(const MachineInstr *MI, unsigned Op,
                          const char *Modifier=NULL);
-  void printLeaMemReference(const MachineInstr *MI, unsigned Op,
-                            const char *Modifier=NULL);
   void printPICJumpTableSetLabel(unsigned uid,
                                  const MachineBasicBlock *MBB) const;
   void printPICJumpTableSetLabel(unsigned uid, unsigned uid2,

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp Tue Apr  7 17:35:25 2009
@@ -271,9 +271,10 @@
   }
 }
 
-void X86IntelAsmPrinter::printLeaMemReference(const MachineInstr *MI,
-                                              unsigned Op,
-                                              const char *Modifier) {
+void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
+                                           const char *Modifier) {
+  assert(isMem(MI, Op) && "Invalid memory reference!");
+
   const MachineOperand &BaseReg  = MI->getOperand(Op);
   int ScaleVal                   = MI->getOperand(Op+1).getImm();
   const MachineOperand &IndexReg = MI->getOperand(Op+2);
@@ -316,17 +317,6 @@
   O << "]";
 }
 
-void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
-                                           const char *Modifier) {
-  assert(isMem(MI, Op) && "Invalid memory reference!");
-  MachineOperand Segment = MI->getOperand(Op+4);
-  if (Segment.getReg()) {
-      printOperand(MI, Op+4, Modifier);
-      O << ':';
-    }
-  printLeaMemReference(MI, Op, Modifier);
-}
-
 void X86IntelAsmPrinter::printPICJumpTableSetLabel(unsigned uid,
                                            const MachineBasicBlock *MBB) const {
   if (!TAI->getSetDirective())

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h Tue Apr  7 17:35:25 2009
@@ -88,17 +88,9 @@
     O << "XMMWORD PTR ";
     printMemReference(MI, OpNo);
   }
-  void printlea32mem(const MachineInstr *MI, unsigned OpNo) {
-    O << "DWORD PTR ";
-    printLeaMemReference(MI, OpNo);
-  }
-  void printlea64mem(const MachineInstr *MI, unsigned OpNo) {
-    O << "QWORD PTR ";
-    printLeaMemReference(MI, OpNo);
-  }
   void printlea64_32mem(const MachineInstr *MI, unsigned OpNo) {
     O << "QWORD PTR ";
-    printLeaMemReference(MI, OpNo, "subreg64");
+    printMemReference(MI, OpNo, "subreg64");
   }
 
   bool printAsmMRegister(const MachineOperand &MO, const char Mode);
@@ -111,8 +103,6 @@
   void printSSECC(const MachineInstr *MI, unsigned Op);
   void printMemReference(const MachineInstr *MI, unsigned Op,
                          const char *Modifier=NULL);
-  void printLeaMemReference(const MachineInstr *MI, unsigned Op,
-                            const char *Modifier=NULL);
   void printPICJumpTableSetLabel(unsigned uid,
                                  const MachineBasicBlock *MBB) const;
   void printPICJumpTableSetLabel(unsigned uid, unsigned uid2,

Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Tue Apr  7 17:35:25 2009
@@ -533,6 +533,23 @@
     case X86::DWARF_LOC:
     case X86::FP_REG_KILL:
       break;
+    case X86::TLS_tp: {
+      MCE.emitByte(BaseOpcode);
+      unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg());
+      MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
+      emitConstant(0, 4);
+      break;
+    }
+    case X86::TLS_gs_ri: {
+      MCE.emitByte(BaseOpcode);
+      unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg());
+      MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
+      GlobalValue* GV = MI.getOperand(1).getGlobal();
+      unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
+        : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
+      emitGlobalAddress(GV, rt);
+      break;
+    }
     case X86::MOVPC32r: {
       // This emits the "call" portion of this pseudo instruction.
       MCE.emitByte(BaseOpcode);
@@ -644,21 +661,13 @@
     break;
 
   case X86II::MRMSrcMem: {
-    // FIXME: Maybe lea should have its own form?
-    int AddrOperands;
-    if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
-        Opcode == X86::LEA16r || Opcode == X86::LEA32r)
-      AddrOperands = X86AddrNumOperands - 1; // No segment register
-    else
-      AddrOperands = X86AddrNumOperands;
-
-    intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
+    intptr_t PCAdj = (CurOp + X86AddrNumOperands + 1 != NumOps) ?
       X86InstrInfo::sizeOfImm(Desc) : 0;
 
     MCE.emitByte(BaseOpcode);
     emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
                      PCAdj);
-    CurOp += AddrOperands + 1;
+    CurOp += X86AddrNumOperands + 1;
     if (CurOp != NumOps)
       emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
     break;

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Tue Apr  7 17:35:25 2009
@@ -1490,7 +1490,7 @@
       else
         Opc = X86::LEA64r;
       unsigned ResultReg = createResultReg(RC);
-      addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
+      addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
       return ResultReg;
     }
     return 0;
@@ -1535,7 +1535,7 @@
   unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
   TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
   unsigned ResultReg = createResultReg(RC);
-  addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
+  addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
   return ResultReg;
 }
 

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Apr  7 17:35:25 2009
@@ -69,7 +69,6 @@
     unsigned Scale;
     SDValue IndexReg; 
     int32_t Disp;
-    SDValue Segment;
     GlobalValue *GV;
     Constant *CP;
     const char *ES;
@@ -78,7 +77,7 @@
 
     X86ISelAddressMode()
       : BaseType(RegBase), isRIPRel(false), Scale(1), IndexReg(), Disp(0),
-        Segment(), GV(0), CP(0), ES(0), JT(-1), Align(0) {
+        GV(0), CP(0), ES(0), JT(-1), Align(0) {
     }
 
     bool hasSymbolicDisplacement() const {
@@ -160,25 +159,20 @@
     SDNode *Select(SDValue N);
     SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
 
-    bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM);
-    bool MatchLoad(SDValue N, X86ISelAddressMode &AM);
     bool MatchAddress(SDValue N, X86ISelAddressMode &AM,
                       unsigned Depth = 0);
     bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
     bool SelectAddr(SDValue Op, SDValue N, SDValue &Base,
-                    SDValue &Scale, SDValue &Index, SDValue &Disp,
-                    SDValue &Segment);
+                    SDValue &Scale, SDValue &Index, SDValue &Disp);
     bool SelectLEAAddr(SDValue Op, SDValue N, SDValue &Base,
                        SDValue &Scale, SDValue &Index, SDValue &Disp);
     bool SelectScalarSSELoad(SDValue Op, SDValue Pred,
                              SDValue N, SDValue &Base, SDValue &Scale,
                              SDValue &Index, SDValue &Disp,
-                             SDValue &Segment,
                              SDValue &InChain, SDValue &OutChain);
     bool TryFoldLoad(SDValue P, SDValue N,
                      SDValue &Base, SDValue &Scale,
-                     SDValue &Index, SDValue &Disp,
-                     SDValue &Segment);
+                     SDValue &Index, SDValue &Disp);
     void PreprocessForRMW();
     void PreprocessForFPConvert();
 
@@ -192,7 +186,7 @@
 
     inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base, 
                                    SDValue &Scale, SDValue &Index,
-                                   SDValue &Disp, SDValue &Segment) {
+                                   SDValue &Disp) {
       Base  = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
         CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
         AM.Base.Reg;
@@ -211,11 +205,6 @@
         Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32);
       else
         Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
-
-      if (AM.Segment.getNode())
-        Segment = AM.Segment;
-      else
-        Segment = CurDAG->getRegister(0, MVT::i32);
     }
 
     /// getI8Imm - Return a target constant with the specified value, of type
@@ -737,33 +726,6 @@
     EmitSpecialCodeForMain(BB, MF.getFrameInfo());
 }
 
-
-bool X86DAGToDAGISel::MatchSegmentBaseAddress(SDValue N,
-                                              X86ISelAddressMode &AM) {
-  assert(N.getOpcode() == X86ISD::SegmentBaseAddress);
-  SDValue Segment = N.getOperand(0);
-
-  if (AM.Segment.getNode() == 0) {
-    AM.Segment = Segment;
-    return false;
-  }
-
-  return true;
-}
-
-bool X86DAGToDAGISel::MatchLoad(SDValue N, X86ISelAddressMode &AM) {
-  // This optimization is valid because the GNU TLS model defines that
-  // gs:0 (or fs:0 on X86-64) contains its own address.
-  // For more information see http://people.redhat.com/drepper/tls.pdf
-
-  SDValue Address = N.getOperand(1);
-  if (Address.getOpcode() == X86ISD::SegmentBaseAddress &&
-      !MatchSegmentBaseAddress (Address, AM))
-    return false;
-
-  return true;
-}
-
 /// MatchAddress - Add the specified node to the specified addressing mode,
 /// returning true if it cannot be done.  This just pattern matches for the
 /// addressing mode.
@@ -799,11 +761,6 @@
     break;
   }
 
-  case X86ISD::SegmentBaseAddress:
-    if (!MatchSegmentBaseAddress(N, AM))
-      return false;
-    break;
-
   case X86ISD::Wrapper: {
     DOUT << "Wrapper: 64bit " << is64Bit;
     DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n";
@@ -850,11 +807,6 @@
     break;
   }
 
-  case ISD::LOAD:
-    if (!MatchLoad(N, AM))
-      return false;
-    break;
-
   case ISD::FrameIndex:
     if (AM.BaseType == X86ISelAddressMode::RegBase
         && AM.Base.Reg.getNode() == 0) {
@@ -1082,7 +1034,7 @@
 /// match by reference.
 bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base,
                                  SDValue &Scale, SDValue &Index,
-                                 SDValue &Disp, SDValue &Segment) {
+                                 SDValue &Disp) {
   X86ISelAddressMode AM;
   bool Done = false;
   if (AvoidDupAddrCompute && !N.hasOneUse()) {
@@ -1117,7 +1069,7 @@
   if (!AM.IndexReg.getNode())
     AM.IndexReg = CurDAG->getRegister(0, VT);
 
-  getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
+  getAddressOperands(AM, Base, Scale, Index, Disp);
   return true;
 }
 
@@ -1127,8 +1079,7 @@
 bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred,
                                           SDValue N, SDValue &Base,
                                           SDValue &Scale, SDValue &Index,
-                                          SDValue &Disp, SDValue &Segment,
-                                          SDValue &InChain,
+                                          SDValue &Disp, SDValue &InChain,
                                           SDValue &OutChain) {
   if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
     InChain = N.getOperand(0).getValue(1);
@@ -1137,7 +1088,7 @@
         N.hasOneUse() &&
         IsLegalAndProfitableToFold(N.getNode(), Pred.getNode(), Op.getNode())) {
       LoadSDNode *LD = cast<LoadSDNode>(InChain);
-      if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
+      if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
         return false;
       OutChain = LD->getChain();
       return true;
@@ -1154,7 +1105,7 @@
       N.getOperand(0).getOperand(0).hasOneUse()) {
     // Okay, this is a zero extending load.  Fold it.
     LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
-    if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
+    if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
       return false;
     OutChain = LD->getChain();
     InChain = SDValue(LD, 1);
@@ -1173,11 +1124,6 @@
   if (MatchAddress(N, AM))
     return false;
 
-  //Is it better to set AM.Segment before calling MatchAddress to
-  //prevent it from adding a segment?
-  if (AM.Segment.getNode())
-    return false;
-
   MVT VT = N.getValueType();
   unsigned Complexity = 0;
   if (AM.BaseType == X86ISelAddressMode::RegBase)
@@ -1216,8 +1162,7 @@
     Complexity++;
 
   if (Complexity > 2) {
-    SDValue Segment;
-    getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
+    getAddressOperands(AM, Base, Scale, Index, Disp);
     return true;
   }
   return false;
@@ -1225,12 +1170,11 @@
 
 bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
                                   SDValue &Base, SDValue &Scale,
-                                  SDValue &Index, SDValue &Disp,
-                                  SDValue &Segment) {
+                                  SDValue &Index, SDValue &Disp) {
   if (ISD::isNON_EXTLoad(N.getNode()) &&
       N.hasOneUse() &&
       IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
-    return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp, Segment);
+    return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp);
   return false;
 }
 
@@ -1286,11 +1230,11 @@
   SDValue In1 = Node->getOperand(1);
   SDValue In2L = Node->getOperand(2);
   SDValue In2H = Node->getOperand(3);
-  SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
-  if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
+  SDValue Tmp0, Tmp1, Tmp2, Tmp3;
+  if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3))
     return NULL;
   SDValue LSI = Node->getOperand(4);    // MemOperand
-  const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, LSI, Chain};
+  const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, In2L, In2H, LSI, Chain };
   return CurDAG->getTargetNode(Opc, Node->getDebugLoc(),
                                MVT::i32, MVT::i32, MVT::Other, Ops,
                                array_lengthof(Ops));
@@ -1372,11 +1316,11 @@
       case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
       }
 
-      SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
-      bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
+      SDValue Tmp0, Tmp1, Tmp2, Tmp3;
+      bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
       // multiplty is commmutative
       if (!foldedLoad) {
-        foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
+        foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
         if (foldedLoad)
           std::swap(N0, N1);
       }
@@ -1385,8 +1329,7 @@
                                               N0, SDValue()).getValue(1);
 
       if (foldedLoad) {
-        SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
-                          InFlag };
+        SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
         SDNode *CNode =
           CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
                                 array_lengthof(Ops));
@@ -1495,17 +1438,17 @@
         break;
       }
 
-      SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
-      bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
+      SDValue Tmp0, Tmp1, Tmp2, Tmp3;
+      bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
       bool signBitIsZero = CurDAG->SignBitIsZero(N0);
 
       SDValue InFlag;
       if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
         // Special case for div8, just use a move with zero extension to AX to
         // clear the upper 8 bits (AH).
-        SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
-        if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
-          SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
+        SDValue Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
+        if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) {
+          SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
           Move =
             SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, MVT::i16, 
                                           MVT::Other, Ops,
@@ -1537,8 +1480,7 @@
       }
 
       if (foldedLoad) {
-        SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
-                          InFlag };
+        SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
         SDNode *CNode =
           CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
                                 array_lengthof(Ops));
@@ -1707,13 +1649,13 @@
 bool X86DAGToDAGISel::
 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
                              std::vector<SDValue> &OutOps) {
-  SDValue Op0, Op1, Op2, Op3, Op4;
+  SDValue Op0, Op1, Op2, Op3;
   switch (ConstraintCode) {
   case 'o':   // offsetable        ??
   case 'v':   // not offsetable    ??
   default: return true;
   case 'm':   // memory
-    if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3, Op4))
+    if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3))
       return true;
     break;
   }
@@ -1722,7 +1664,6 @@
   OutOps.push_back(Op1);
   OutOps.push_back(Op2);
   OutOps.push_back(Op3);
-  OutOps.push_back(Op4);
   return false;
 }
 

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Apr  7 17:35:25 2009
@@ -4834,13 +4834,8 @@
                                    const MVT PtrVT, TLSModel::Model model) {
   DebugLoc dl = GA->getDebugLoc();
   // Get the Thread Pointer
-  SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
-                             DebugLoc::getUnknownLoc(), PtrVT,
-                             DAG.getRegister(X86::GS, MVT::i32));
-
-  SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
-                                      NULL, 0);
-
+  SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER,
+                                      DebugLoc::getUnknownLoc(), PtrVT);
   // emit "addl x at ntpoff,%eax" (local exec) or "addl x at indntpoff,%eax" (initial
   // exec)
   SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
@@ -7154,7 +7149,7 @@
   case X86ISD::FRSQRT:             return "X86ISD::FRSQRT";
   case X86ISD::FRCP:               return "X86ISD::FRCP";
   case X86ISD::TLSADDR:            return "X86ISD::TLSADDR";
-  case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
+  case X86ISD::THREAD_POINTER:     return "X86ISD::THREAD_POINTER";
   case X86ISD::EH_RETURN:          return "X86ISD::EH_RETURN";
   case X86ISD::TC_RETURN:          return "X86ISD::TC_RETURN";
   case X86ISD::FNSTCW16m:          return "X86ISD::FNSTCW16m";
@@ -7478,7 +7473,7 @@
   unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
   MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
   // add 4 to displacement.
-  for (int i=0; i <= lastAddrIndx-2; ++i)
+  for (int i=0; i <= lastAddrIndx-1; ++i)
     (*MIB).addOperand(*argOpers[i]);
   MachineOperand newOp3 = *(argOpers[3]);
   if (newOp3.isImm())
@@ -7486,7 +7481,6 @@
   else
     newOp3.setOffset(newOp3.getOffset()+4);
   (*MIB).addOperand(newOp3);
-  (*MIB).addOperand(*argOpers[lastAddrIndx]);
 
   // t3/4 are defined later, at the bottom of the loop
   unsigned t3 = F->getRegInfo().createVirtualRegister(RC);

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Apr  7 17:35:25 2009
@@ -188,11 +188,8 @@
       /// in order to obtain suitable precision.
       FRSQRT, FRCP,
 
-      // TLSADDR - Thread Local Storage.
-      TLSADDR,
-
-      // SegmentBaseAddress - The address segment:0
-      SegmentBaseAddress,
+      // TLSADDR, THREAD_POINTER - Thread Local Storage.
+      TLSADDR, THREAD_POINTER,
 
       // EH_RETURN - Exception Handling helpers.
       EH_RETURN,

Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Tue Apr  7 17:35:25 2009
@@ -23,7 +23,7 @@
 def i64i8imm   : Operand<i64>;
 
 def lea64mem : Operand<i64> {
-  let PrintMethod = "printlea64mem";
+  let PrintMethod = "printi64mem";
   let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
 }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrBuilder.h?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrBuilder.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrBuilder.h Tue Apr  7 17:35:25 2009
@@ -66,15 +66,6 @@
   return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0);
 }
 
-inline const MachineInstrBuilder &addLeaOffset(const MachineInstrBuilder &MIB,
-                                            int Offset) {
-  return MIB.addImm(1).addReg(0).addImm(Offset);
-}
-
-inline const MachineInstrBuilder &addOffset(const MachineInstrBuilder &MIB,
-                                            int Offset) {
-  return addLeaOffset(MIB, Offset).addReg(0);
-}
 
 /// addRegOffset - This function is used to add a memory reference of the form
 /// [Reg + Offset], i.e., one with no scale or index, but with a
@@ -83,13 +74,8 @@
 inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB,
                                                unsigned Reg, bool isKill,
                                                int Offset) {
-  return addOffset(MIB.addReg(Reg, false, false, isKill), Offset);
-}
-
-inline const MachineInstrBuilder &addLeaRegOffset(const MachineInstrBuilder &MIB,
-                                                  unsigned Reg, bool isKill,
-                                                  int Offset) {
-  return addLeaOffset(MIB.addReg(Reg, false, false, isKill), Offset);
+  return MIB.addReg(Reg, false, false, isKill)
+    .addImm(1).addReg(0).addImm(Offset);
 }
 
 /// addRegReg - This function is used to add a memory reference of the form:
@@ -101,8 +87,8 @@
     .addReg(Reg2, false, false, isKill2).addImm(0);
 }
 
-inline const MachineInstrBuilder &addLeaAddress(const MachineInstrBuilder &MIB,
-                                                const X86AddressMode &AM) {
+inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
+                                                 const X86AddressMode &AM) {
   assert (AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
 
   if (AM.BaseType == X86AddressMode::RegBase)
@@ -118,11 +104,6 @@
     return MIB.addImm(AM.Disp);
 }
 
-inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
-                                                 const X86AddressMode &AM) {
-  return addLeaAddress(MIB, AM).addReg(0);
-}
-
 /// addFrameReference - This function is used to add a reference to the base of
 /// an abstract object on the stack frame of the current function.  This
 /// reference has base register as the FrameIndex offset until it is resolved.
@@ -144,7 +125,7 @@
                         MFI.getObjectOffset(FI) + Offset,
                         MFI.getObjectSize(FI),
                         MFI.getObjectAlignment(FI));
-  return addOffset(MIB.addFrameIndex(FI), Offset)
+  return MIB.addFrameIndex(FI).addImm(1).addReg(0).addImm(Offset)
             .addMemOperand(MMO);
 }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Apr  7 17:35:25 2009
@@ -1138,9 +1138,9 @@
       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
       unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
-      NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
-                              .addReg(Dest, true, false, false, isDead),
-                              Src, isKill, 1);
+      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
+                           .addReg(Dest, true, false, false, isDead),
+                           Src, isKill, 1);
       break;
     }
     case X86::INC16r:
@@ -1157,9 +1157,9 @@
       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
       unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
-      NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
-                              .addReg(Dest, true, false, false, isDead),
-                              Src, isKill, -1);
+      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
+                           .addReg(Dest, true, false, false, isDead),
+                           Src, isKill, -1);
       break;
     }
     case X86::DEC16r:
@@ -1200,18 +1200,18 @@
     case X86::ADD64ri8:
       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
       if (MI->getOperand(2).isImm())
-        NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
-                                .addReg(Dest, true, false, false, isDead),
-                                Src, isKill, MI->getOperand(2).getImm());
+        NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
+                             .addReg(Dest, true, false, false, isDead),
+                             Src, isKill, MI->getOperand(2).getImm());
       break;
     case X86::ADD32ri:
     case X86::ADD32ri8:
       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
       if (MI->getOperand(2).isImm()) {
         unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
-        NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
-                                .addReg(Dest, true, false, false, isDead),
-                                Src, isKill, MI->getOperand(2).getImm());
+        NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
+                             .addReg(Dest, true, false, false, isDead),
+                             Src, isKill, MI->getOperand(2).getImm());
       }
       break;
     case X86::ADD16ri:
@@ -1959,7 +1959,7 @@
   for (unsigned i = 0; i != NumAddrOps; ++i)
     MIB.addOperand(MOs[i]);
   if (NumAddrOps < 4)  // FrameIndex only
-    addOffset(MIB, 0);
+    MIB.addImm(1).addReg(0).addImm(0);
   
   // Loop over the rest of the ri operands, converting them over.
   unsigned NumOps = MI->getDesc().getNumOperands()-2;
@@ -1990,7 +1990,7 @@
       for (unsigned i = 0; i != NumAddrOps; ++i)
         MIB.addOperand(MOs[i]);
       if (NumAddrOps < 4)  // FrameIndex only
-        addOffset(MIB, 0);
+        MIB.addImm(1).addReg(0).addImm(0);
     } else {
       MIB.addOperand(MO);
     }
@@ -2008,7 +2008,7 @@
   for (unsigned i = 0; i != NumAddrOps; ++i)
     MIB.addOperand(MOs[i]);
   if (NumAddrOps < 4)  // FrameIndex only
-    addOffset(MIB, 0);
+    MIB.addImm(1).addReg(0).addImm(0);
   return MIB.addImm(0);
 }
 
@@ -2164,7 +2164,7 @@
   } else if (Ops.size() != 1)
     return NULL;
 
-  SmallVector<MachineOperand,X86AddrNumOperands> MOs;
+  SmallVector<MachineOperand,4> MOs;
   if (LoadMI->getOpcode() == X86::V_SET0 ||
       LoadMI->getOpcode() == X86::V_SETALLONES) {
     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
@@ -2193,7 +2193,6 @@
     MOs.push_back(MachineOperand::CreateImm(1));
     MOs.push_back(MachineOperand::CreateReg(0, false));
     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
-    MOs.push_back(MachineOperand::CreateReg(0, false));
   } else {
     // Folding a normal load. Just copy the load's address operands.
     unsigned NumOps = LoadMI->getDesc().getNumOperands();
@@ -2883,6 +2882,11 @@
       FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
       break;
     }
+    case X86::TLS_tp:
+    case X86::TLS_gs_ri:
+      FinalSize += 2;
+      FinalSize += sizeGlobalAddress(false);
+      break;
     }
     CurOp = NumOps;
     break;

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Tue Apr  7 17:35:25 2009
@@ -243,7 +243,7 @@
   };
 }
 
-const int X86AddrNumOperands = 5;
+const int X86AddrNumOperands = 4;
 
 inline static bool isScale(const MachineOperand &MO) {
   return MO.isImm() &&
@@ -251,7 +251,7 @@
      MO.getImm() == 4 || MO.getImm() == 8);
 }
 
-inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
+inline static bool isMem(const MachineInstr *MI, unsigned Op) {
   if (MI->getOperand(Op).isFI()) return true;
   return Op+4 <= MI->getNumOperands() &&
     MI->getOperand(Op  ).isReg() && isScale(MI->getOperand(Op+1)) &&
@@ -262,13 +262,6 @@
      MI->getOperand(Op+3).isJTI());
 }
 
-inline static bool isMem(const MachineInstr *MI, unsigned Op) {
-  if (MI->getOperand(Op).isFI()) return true;
-  return Op+5 <= MI->getNumOperands() &&
-    MI->getOperand(Op+4).isReg() &&
-    isLeaMem(MI, Op);
-}
-
 class X86InstrInfo : public TargetInstrInfoImpl {
   X86TargetMachine &TM;
   const X86RegisterInfo RI;

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Apr  7 17:35:25 2009
@@ -65,7 +65,7 @@
 
 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
 
-def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
+def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
 
 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 
@@ -142,8 +142,7 @@
 
 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
                         [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
-def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
-                                 SDT_X86SegmentBaseAddress, []>;
+def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
 
 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
                         [SDNPHasChain]>;
@@ -168,7 +167,7 @@
 //
 class X86MemOperand<string printMethod> : Operand<iPTR> {
   let PrintMethod = printMethod;
-  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
+  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
 }
 
 def i8mem   : X86MemOperand<"printi8mem">;
@@ -182,7 +181,7 @@
 def f128mem : X86MemOperand<"printf128mem">;
 
 def lea32mem : Operand<i32> {
-  let PrintMethod = "printlea32mem";
+  let PrintMethod = "printi32mem";
   let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
 }
 
@@ -208,7 +207,7 @@
 //
 
 // Define X86 specific addressing mode.
-def addr      : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
+def addr      : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
                                [add, mul, shl, or, frameindex], []>;
 
@@ -2923,11 +2922,101 @@
 // Thread Local Storage Instructions
 //
 
+// FIXME: there is duplication with the non-TLS case.
+// There is a suggestion on how to fix this at
+// http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090309/075212.html
+
 let Uses = [EBX] in
 def TLS_addr32 : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
                   "leal\t${sym:mem}(,%ebx,1), $dst",
                   [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
 
+let AddedComplexity = 10 in
+def TLS_gs_rr  : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
+                  "movl\t%gs:($src), $dst",
+                  [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
+
+let AddedComplexity = 15 in
+def TLS_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
+                  "movl\t%gs:${src:mem}, $dst",
+                  [(set GR32:$dst,
+                    (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>,
+                  SegGS;
+
+let AddedComplexity = 15 in
+def TLS16_gs_ri : I<0x8B, Pseudo, (outs GR16:$dst), (ins i32imm:$src),
+                    "movw\t%gs:${src:mem}, $dst",
+                    [(set GR16:$dst,
+                      (load (add X86TLStp,
+                        (X86Wrapper tglobaltlsaddr:$src))))]>,
+                    SegGS;
+
+let AddedComplexity = 15 in
+def TLS8_gs_ri : I<0x8B, Pseudo, (outs GR8:$dst), (ins i32imm:$src),
+                   "movb\t%gs:${src:mem}, $dst",
+                   [(set GR8:$dst,
+                     (load (add X86TLStp,
+                       (X86Wrapper tglobaltlsaddr:$src))))]>,
+                   SegGS;
+
+let AddedComplexity = 15 in
+def TLS_ext16_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
+                        "movzwl\t%gs:${src:mem}, $dst",
+                        [(set GR32:$dst,
+                          (extloadi32i16
+                            (add X86TLStp,
+                              (X86Wrapper tglobaltlsaddr:$src))))]>,
+                        SegGS;
+
+let AddedComplexity = 15 in
+def TLS_sext16_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
+                         "movswl\t%gs:${src:mem}, $dst",
+                         [(set GR32:$dst,
+                           (sextloadi32i16
+                             (add X86TLStp,
+                               (X86Wrapper tglobaltlsaddr:$src))))]>,
+                         SegGS;
+
+let AddedComplexity = 15 in
+def TLS_zext16_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
+                         "movzwl\t%gs:${src:mem}, $dst",
+                         [(set GR32:$dst,
+                           (zextloadi32i16
+                             (add X86TLStp,
+                               (X86Wrapper tglobaltlsaddr:$src))))]>,
+                         SegGS;
+
+let AddedComplexity = 15 in
+def TLS_ext8_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
+                        "movzbl\t%gs:${src:mem}, $dst",
+                        [(set GR32:$dst,
+                          (extloadi32i8
+                            (add X86TLStp,
+                              (X86Wrapper tglobaltlsaddr:$src))))]>,
+                        SegGS;
+
+let AddedComplexity = 15 in
+def TLS_sext8_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
+                         "movsbl\t%gs:${src:mem}, $dst",
+                         [(set GR32:$dst,
+                           (sextloadi32i8
+                             (add X86TLStp,
+                               (X86Wrapper tglobaltlsaddr:$src))))]>,
+                         SegGS;
+
+let AddedComplexity = 15 in
+def TLS_zext8_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
+                         "movzbl\t%gs:${src:mem}, $dst",
+                         [(set GR32:$dst,
+                           (zextloadi32i8
+                             (add X86TLStp,
+                              (X86Wrapper tglobaltlsaddr:$src))))]>,
+                         SegGS;
+
+def TLS_tp : I<0x8B, Pseudo, (outs GR32:$dst), (ins),
+               "movl\t%gs:0, $dst",
+               [(set GR32:$dst, X86TLStp)]>, SegGS;
+
 let AddedComplexity = 5 in
 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
                    "movl\t%gs:$src, $dst",

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Apr  7 17:35:25 2009
@@ -76,18 +76,18 @@
 // These are 'extloads' from a scalar to the low element of a vector, zeroing
 // the top elements.  These are used for the SSE 'ss' and 'sd' instruction
 // forms.
-def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
+def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
                                   [SDNPHasChain, SDNPMayLoad]>;
-def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
+def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
                                   [SDNPHasChain, SDNPMayLoad]>;
 
 def ssmem : Operand<v4f32> {
   let PrintMethod = "printf32mem";
-  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
+  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
 }
 def sdmem : Operand<v2f64> {
   let PrintMethod = "printf64mem";
-  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
+  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Tue Apr  7 17:35:25 2009
@@ -971,8 +971,8 @@
   } else if (MFI->hasVarSizedObjects()) {
     if (CSSize) {
       unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
-      MachineInstr *MI = addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
-                                         FramePtr, false, -CSSize);
+      MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
+                                      FramePtr, false, -CSSize);
       MBB.insert(MBBI, MI);
     } else
       BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Tue Apr  7 17:35:25 2009
@@ -168,14 +168,6 @@
 
   // Status flags register
   def EFLAGS : Register<"flags">;
-
-  // Segment registers
-  def CS : Register<"cs">;
-  def DS : Register<"ds">;
-  def SS : Register<"ss">;
-  def ES : Register<"es">;
-  def FS : Register<"fs">;
-  def GS : Register<"gs">;
 }
 
 

Modified: llvm/trunk/test/CodeGen/X86/tls10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls10.ll?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls10.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls10.ll Tue Apr  7 17:35:25 2009
@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movl	\$i at NTPOFF, %eax} %t
-; RUN: grep {addl	%gs:0, %eax} %t
+; RUN: grep {movl	%gs:0, %eax} %t
+; RUN: grep {leal	i at NTPOFF(%eax), %eax} %t
 
 @i = external hidden thread_local global i32
 

Modified: llvm/trunk/test/CodeGen/X86/tls2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls2.ll?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls2.ll Tue Apr  7 17:35:25 2009
@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movl	\$i at NTPOFF, %eax} %t
-; RUN: grep {addl	%gs:0, %eax} %t
+; RUN: grep {movl	%gs:0, %eax} %t
+; RUN: grep {leal	i at NTPOFF(%eax), %eax} %t
 
 @i = thread_local global i32 15
 

Modified: llvm/trunk/test/CodeGen/X86/tls6.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls6.ll?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls6.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls6.ll Tue Apr  7 17:35:25 2009
@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movl	\$i at NTPOFF, %eax} %t
-; RUN: grep {addl	%gs:0, %eax} %t
+; RUN: grep {movl	%gs:0, %eax} %t
+; RUN: grep {leal	i at NTPOFF(%eax), %eax} %t
 
 @i = internal thread_local global i32 15
 

Modified: llvm/trunk/test/CodeGen/X86/tls8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls8.ll?rev=68560&r1=68559&r2=68560&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls8.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls8.ll Tue Apr  7 17:35:25 2009
@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movl	\$i at NTPOFF, %eax} %t
-; RUN: grep {addl	%gs:0, %eax} %t
+; RUN: grep {movl	%gs:0, %eax} %t
+; RUN: grep {leal	i at NTPOFF(%eax), %eax} %t
 
 @i = hidden thread_local global i32 15
 




From dpatel at apple.com  Tue Apr  7 18:00:04 2009
From: dpatel at apple.com (Devang Patel)
Date: Tue, 07 Apr 2009 23:00:04 -0000
Subject: [llvm-commits] [llvm] r68569 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
Message-ID: <200904072300.n37N04BT032415@zion.cs.uiuc.edu>

Author: dpatel
Date: Tue Apr  7 18:00:04 2009
New Revision: 68569

URL: http://llvm.org/viewvc/llvm-project?rev=68569&view=rev
Log:
Revert prev. patch for now.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=68569&r1=68568&r2=68569&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Tue Apr  7 18:00:04 2009
@@ -3926,8 +3926,9 @@
     if (DW && DW->ValidDebugInfo(RSI.getContext())) {
       unsigned LabelID =
         DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
-      DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
-                               getRoot(), LabelID));
+      if (Fast)
+        DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
+                                 getRoot(), LabelID));
     }
 
     return 0;
@@ -3938,8 +3939,9 @@
     if (DW && DW->ValidDebugInfo(REI.getContext())) {
       unsigned LabelID =
         DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
-      DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
-                               getRoot(), LabelID));
+      if (Fast)
+        DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
+                                 getRoot(), LabelID));
     }
 
     return 0;




From gohman at apple.com  Tue Apr  7 19:15:30 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 08 Apr 2009 00:15:30 -0000
Subject: [llvm-commits] [llvm] r68576 - in /llvm/trunk: include/llvm/Target/
 lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/X86/ test/CodeGen/X86/
Message-ID: <200904080015.n380FVD1002889@zion.cs.uiuc.edu>

Author: djg
Date: Tue Apr  7 19:15:30 2009
New Revision: 68576

URL: http://llvm.org/viewvc/llvm-project?rev=68576&view=rev
Log:
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.

This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.

Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.

Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.

Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.

Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.

Added:
    llvm/trunk/test/CodeGen/X86/subreg-to-reg-3.ll
    llvm/trunk/test/CodeGen/X86/subreg-to-reg-4.ll
    llvm/trunk/test/CodeGen/X86/subreg-to-reg-5.ll
    llvm/trunk/test/CodeGen/X86/subreg-to-reg-6.ll
Removed:
    llvm/trunk/test/CodeGen/X86/2008-05-06-SpillerBug.ll
Modified:
    llvm/trunk/include/llvm/Target/TargetLowering.h
    llvm/trunk/lib/CodeGen/LiveInterval.cpp
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86Instr64bit.td
    llvm/trunk/test/CodeGen/X86/byval7.ll
    llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll
    llvm/trunk/test/CodeGen/X86/subreg-to-reg-1.ll
    llvm/trunk/test/CodeGen/X86/twoaddr-coalesce.ll

Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=68576&r1=68575&r2=68576&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Tue Apr  7 19:15:30 2009
@@ -747,6 +747,13 @@
     /// there are any bits set in the constant that are not demanded.  If so,
     /// shrink the constant and return true.
     bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
+
+    /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
+    /// casts are free.  This uses isZExtFree and ZERO_EXTEND for the widening
+    /// cast, but it could be generalized for targets with other types of
+    /// implicit widening casts.
+    bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
+                          DebugLoc dl);
   };
                                                 
   /// SimplifyDemandedBits - Look at Op.  At this point, we know that only the
@@ -1386,7 +1393,23 @@
   virtual bool isTruncateFree(MVT VT1, MVT VT2) const {
     return false;
   }
-  
+
+  /// isZExtFree - Return true if any actual instruction that defines a
+  /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
+  /// register. This does not necessarily include registers defined in
+  /// unknown ways, such as incoming arguments, or copies from unknown
+  /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
+  /// does not necessarily apply to truncate instructions. e.g. on x86-64,
+  /// all instructions that define 32-bit values implicit zero-extend the
+  /// result out to 64 bits.
+  virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
+    return false;
+  }
+
+  virtual bool isZExtFree(MVT VT1, MVT VT2) const {
+    return false;
+  }
+
   //===--------------------------------------------------------------------===//
   // Div utility functions
   //

Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=68576&r1=68575&r2=68576&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Tue Apr  7 19:15:30 2009
@@ -579,24 +579,41 @@
   
   iterator IP = begin();
   for (const_iterator I = Clobbers.begin(), E = Clobbers.end(); I != E; ++I) {
+    bool Done = false;
     unsigned Start = I->start, End = I->end;
-    IP = std::upper_bound(IP, end(), Start);
-    
-    // If the start of this range overlaps with an existing liverange, trim it.
-    if (IP != begin() && IP[-1].end > Start) {
-      Start = IP[-1].end;
-      // Trimmed away the whole range?
-      if (Start >= End) continue;
-    }
-    // If the end of this range overlaps with an existing liverange, trim it.
-    if (IP != end() && End > IP->start) {
-      End = IP->start;
-      // If this trimmed away the whole range, ignore it.
-      if (Start == End) continue;
+    // If a clobber range starts before an existing range and ends after
+    // it, the clobber range will need to be split into multiple ranges.
+    // Loop until the entire clobber range is handled.
+    while (!Done) {
+      Done = true;
+      IP = std::upper_bound(IP, end(), Start);
+      unsigned SubRangeStart = Start;
+      unsigned SubRangeEnd = End;
+
+      // If the start of this range overlaps with an existing liverange, trim it.
+      if (IP != begin() && IP[-1].end > SubRangeStart) {
+        SubRangeStart = IP[-1].end;
+        // Trimmed away the whole range?
+        if (SubRangeStart >= SubRangeEnd) continue;
+      }
+      // If the end of this range overlaps with an existing liverange, trim it.
+      if (IP != end() && SubRangeEnd > IP->start) {
+        // If the clobber live range extends beyond the existing live range,
+        // it'll need at least another live range, so set the flag to keep
+        // iterating.
+        if (SubRangeEnd > IP->end) {
+          Start = IP->end;
+          Done = false;
+        }
+        SubRangeEnd = IP->start;
+        // If this trimmed away the whole range, ignore it.
+        if (SubRangeStart == SubRangeEnd) continue;
+      }
+
+      // Insert the clobber interval.
+      IP = addRangeFrom(LiveRange(SubRangeStart, SubRangeEnd, ClobberValNo),
+                        IP);
     }
-    
-    // Insert the clobber interval.
-    IP = addRangeFrom(LiveRange(Start, End, ClobberValNo), IP);
   }
 }
 

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=68576&r1=68575&r2=68576&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Tue Apr  7 19:15:30 2009
@@ -399,6 +399,7 @@
     unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
     if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
         mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+        mi->getOpcode() == TargetInstrInfo::SUBREG_TO_REG ||
         tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg))
       CopyMI = mi;
     // Earlyclobbers move back one.
@@ -556,6 +557,7 @@
       unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
       if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
           mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+          mi->getOpcode() == TargetInstrInfo::SUBREG_TO_REG ||
           tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg))
         CopyMI = mi;
       ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator);
@@ -658,6 +660,7 @@
     unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
     if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
         MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+        MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG ||
         tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg))
       CopyMI = MI;
     handlePhysicalRegisterDef(MBB, MI, MIIdx, MO, 
@@ -855,7 +858,8 @@
     if (TargetRegisterInfo::isPhysicalRegister(Reg))
       Reg = tri_->getSubReg(Reg, VNI->copy->getOperand(2).getImm());
     return Reg;
-  } else if (VNI->copy->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
+  } else if (VNI->copy->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+             VNI->copy->getOpcode() == TargetInstrInfo::SUBREG_TO_REG)
     return VNI->copy->getOperand(2).getReg();
 
   unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=68576&r1=68575&r2=68576&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Apr  7 19:15:30 2009
@@ -1666,9 +1666,11 @@
   // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
   // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
   // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
-  // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
+  // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
   if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
-       N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
+       N0.getOpcode() == ISD::SIGN_EXTEND ||
+       (N0.getOpcode() == ISD::TRUNCATE &&
+        !TLI.isTruncateFree(N0.getOperand(0).getValueType(), VT))) &&
       N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
     SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
                                  N0.getOperand(0).getValueType(),
@@ -3121,10 +3123,14 @@
     return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType());
   }
 
-  // fold (zext (and (trunc x), cst)) -> (and x, cst).
+  // Fold (zext (and (trunc x), cst)) -> (and x, cst),
+  // if either of the casts is not free.
   if (N0.getOpcode() == ISD::AND &&
       N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
-      N0.getOperand(1).getOpcode() == ISD::Constant) {
+      N0.getOperand(1).getOpcode() == ISD::Constant &&
+      (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
+                           N0.getValueType()) ||
+       !TLI.isZExtFree(N0.getValueType(), VT))) {
     SDValue X = N0.getOperand(0).getOperand(0);
     if (X.getValueType().bitsLT(VT)) {
       X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
@@ -3252,10 +3258,13 @@
     return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
   }
 
-  // fold (aext (and (trunc x), cst)) -> (and x, cst).
+  // Fold (aext (and (trunc x), cst)) -> (and x, cst)
+  // if the trunc is not free.
   if (N0.getOpcode() == ISD::AND &&
       N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
-      N0.getOperand(1).getOpcode() == ISD::Constant) {
+      N0.getOperand(1).getOpcode() == ISD::Constant &&
+      !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
+                          N0.getValueType())) {
     SDValue X = N0.getOperand(0).getOperand(0);
     if (X.getValueType().bitsLT(VT)) {
       X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=68576&r1=68575&r2=68576&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Apr  7 19:15:30 2009
@@ -777,6 +777,48 @@
   return false;
 }
 
+/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
+/// casts are free.  This uses isZExtFree and ZERO_EXTEND for the widening
+/// cast, but it could be generalized for targets with other types of
+/// implicit widening casts.
+bool
+TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
+                                                    unsigned BitWidth,
+                                                    const APInt &Demanded,
+                                                    DebugLoc dl) {
+  assert(Op.getNumOperands() == 2 &&
+         "ShrinkDemandedOp only supports binary operators!");
+  assert(Op.getNode()->getNumValues() == 1 &&
+         "ShrinkDemandedOp only supports nodes with one result!");
+
+  // Don't do this if the node has another user, which may require the
+  // full value.
+  if (!Op.getNode()->hasOneUse())
+    return false;
+
+  // Search for the smallest integer type with free casts to and from
+  // Op's type. For expedience, just check power-of-2 integer types.
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
+  if (!isPowerOf2_32(SmallVTBits))
+    SmallVTBits = NextPowerOf2(SmallVTBits);
+  for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
+    MVT SmallVT = MVT::getIntegerVT(SmallVTBits);
+    if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
+        TLI.isZExtFree(SmallVT, Op.getValueType())) {
+      // We found a type with free casts.
+      SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
+                              DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
+                                          Op.getNode()->getOperand(0)),
+                              DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
+                                          Op.getNode()->getOperand(1)));
+      SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
+      return CombineTo(Op, Z);
+    }
+  }
+  return false;
+}
+
 /// SimplifyDemandedBits - Look at Op.  At this point, we know that only the
 /// DemandedMask bits of the result of Op are ever used downstream.  If we can
 /// use this information to simplify Op, create a new simplified DAG node and
@@ -865,7 +907,10 @@
     // If the RHS is a constant, see if we can simplify it.
     if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
       return true;
-      
+    // If the operation can be done in a smaller type, do so.
+    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
+      return true;
+
     // Output known-1 bits are only known if set in both the LHS & RHS.
     KnownOne &= KnownOne2;
     // Output known-0 are known to be clear if zero in either the LHS | RHS.
@@ -896,7 +941,10 @@
     // If the RHS is a constant, see if we can simplify it.
     if (TLO.ShrinkDemandedConstant(Op, NewMask))
       return true;
-          
+    // If the operation can be done in a smaller type, do so.
+    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
+      return true;
+
     // Output known-0 bits are only known if clear in both the LHS & RHS.
     KnownZero &= KnownZero2;
     // Output known-1 are known to be set if set in either the LHS | RHS.
@@ -918,7 +966,10 @@
       return TLO.CombineTo(Op, Op.getOperand(0));
     if ((KnownZero2 & NewMask) == NewMask)
       return TLO.CombineTo(Op, Op.getOperand(1));
-      
+    // If the operation can be done in a smaller type, do so.
+    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
+      return true;
+
     // If all of the unknown bits are known to be zero on one side or the other
     // (but not both) turn this into an *inclusive* or.
     //    e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
@@ -1333,6 +1384,24 @@
     }
 #endif
     break;
+  case ISD::ADD:
+  case ISD::MUL:
+  case ISD::SUB: {
+    // Add, Sub, and Mul don't demand any bits in positions beyond that
+    // of the highest bit demanded of them.
+    APInt LoMask = APInt::getLowBitsSet(BitWidth,
+                                        BitWidth - NewMask.countLeadingZeros());
+    if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
+                             KnownOne2, TLO, Depth+1))
+      return true;
+    if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
+                             KnownOne2, TLO, Depth+1))
+      return true;
+    // See if the operation should be performed at a smaller bit width.
+    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
+      return true;
+  }
+  // FALL THROUGH
   default:
     // Just use ComputeMaskedBits to compute output bits.
     TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=68576&r1=68575&r2=68576&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Tue Apr  7 19:15:30 2009
@@ -1070,7 +1070,8 @@
           return true;
       }
     }
-    if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
+    if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+        MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
       SubIdx = MI->getOperand(3).getImm();
       if (VirtReg == MI->getOperand(0).getReg()) {
         if (!tri_->getSubReg(PhysReg, SubIdx))
@@ -1164,11 +1165,12 @@
   unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
   bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
   bool isInsSubReg = CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG;
+  bool isSubRegToReg = CopyMI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG;
   unsigned SubIdx = 0;
   if (isExtSubReg) {
     DstReg = CopyMI->getOperand(0).getReg();
     SrcReg = CopyMI->getOperand(1).getReg();
-  } else if (isInsSubReg) {
+  } else if (isInsSubReg || isSubRegToReg) {
     if (CopyMI->getOperand(2).getSubReg()) {
       DOUT << "\tSource of insert_subreg is already coalesced "
            << "to another register.\n";
@@ -1212,7 +1214,7 @@
   MachineBasicBlock *CopyMBB = CopyMI->getParent();
   unsigned RealDstReg = 0;
   unsigned RealSrcReg = 0;
-  if (isExtSubReg || isInsSubReg) {
+  if (isExtSubReg || isInsSubReg || isSubRegToReg) {
     SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
     if (SrcIsPhys && isExtSubReg) {
       // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
@@ -1228,7 +1230,7 @@
       } else
         SrcReg = tri_->getSubReg(SrcReg, SubIdx);
       SubIdx = 0;
-    } else if (DstIsPhys && isInsSubReg) {
+    } else if (DstIsPhys && (isInsSubReg || isSubRegToReg)) {
       // EAX = INSERT_SUBREG EAX, r1024, 0
       unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
       if (SrcSubIdx) {
@@ -1241,8 +1243,9 @@
       } else
         DstReg = tri_->getSubReg(DstReg, SubIdx);
       SubIdx = 0;
-    } else if ((DstIsPhys && isExtSubReg) || (SrcIsPhys && isInsSubReg)) {
-      if (CopyMI->getOperand(1).getSubReg()) {
+    } else if ((DstIsPhys && isExtSubReg) ||
+               (SrcIsPhys && (isInsSubReg || isSubRegToReg))) {
+      if (!isSubRegToReg && CopyMI->getOperand(1).getSubReg()) {
         DOUT << "\tSrc of extract_subreg already coalesced with reg"
              << " of a super-class.\n";
         return false; // Not coalescable.
@@ -1295,20 +1298,32 @@
 
     // Process moves where one of the registers have a sub-register index.
     MachineOperand *DstMO = CopyMI->findRegisterDefOperand(DstReg);
-    if (DstMO->getSubReg())
-      // FIXME: Can we handle this?
-      return false;
     MachineOperand *SrcMO = CopyMI->findRegisterUseOperand(SrcReg);
-    SubIdx = SrcMO->getSubReg();
+    SubIdx = DstMO->getSubReg();
     if (SubIdx) {
-      // This is not a extract_subreg but it looks like one.
-      // e.g. %cl = MOV16rr %reg1024:2
-      isExtSubReg = true;
-      if (DstIsPhys) {
-        if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx,RealDstReg))
+      if (SrcMO->getSubReg())
+        // FIXME: can we handle this?
+        return false;
+      // This is not an insert_subreg but it looks like one.
+      // e.g. %reg1024:3 = MOV32rr %EAX
+      isInsSubReg = true;
+      if (SrcIsPhys) {
+        if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
           return false; // Not coalescable
         SubIdx = 0;
       }
+    } else {
+      SubIdx = SrcMO->getSubReg();
+      if (SubIdx) {
+        // This is not a extract_subreg but it looks like one.
+        // e.g. %cl = MOV16rr %reg1024:2
+        isExtSubReg = true;
+        if (DstIsPhys) {
+          if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx,RealDstReg))
+            return false; // Not coalescable
+          SubIdx = 0;
+        }
+      }
     }
 
     const TargetRegisterClass *SrcRC= SrcIsPhys ? 0 : mri_->getRegClass(SrcReg);
@@ -1393,7 +1408,7 @@
     SavedLI = li_->dupInterval(&DstInt);
 
   // Check if it is necessary to propagate "isDead" property.
-  if (!isExtSubReg && !isInsSubReg) {
+  if (!isExtSubReg && !isInsSubReg && !isSubRegToReg) {
     MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
     bool isDead = mopd->isDead();
 
@@ -1446,12 +1461,12 @@
 
     // If definition of source is defined by trivial computation, try
     // rematerializing it.
-    if (!isExtSubReg && !isInsSubReg &&
+    if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
         ReMaterializeTrivialDef(SrcInt, DstInt.reg, CopyMI))
       return true;
     
     // If we can eliminate the copy without merging the live ranges, do so now.
-    if (!isExtSubReg && !isInsSubReg &&
+    if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
         (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
          RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
       JoinedCopies.insert(CopyMI);
@@ -1505,8 +1520,10 @@
 
   // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
   // larger super-register.
-  if ((isExtSubReg || isInsSubReg) && !SrcIsPhys && !DstIsPhys) {
-    if ((isExtSubReg && !Swapped) || (isInsSubReg && Swapped)) {
+  if ((isExtSubReg || isInsSubReg || isSubRegToReg) &&
+      !SrcIsPhys && !DstIsPhys) {
+    if ((isExtSubReg && !Swapped) ||
+        ((isInsSubReg || isSubRegToReg) && Swapped)) {
       ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator());
       std::swap(SrcReg, DstReg);
       std::swap(ResSrcInt, ResDstInt);
@@ -1594,7 +1611,7 @@
 
   // If resulting interval has a preference that no longer fits because of subreg
   // coalescing, just clear the preference.
-  if (ResDstInt->preference && (isExtSubReg || isInsSubReg) &&
+  if (ResDstInt->preference && (isExtSubReg || isInsSubReg || isSubRegToReg) &&
       TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) {
     const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
     if (!RC->contains(ResDstInt->preference))
@@ -1847,7 +1864,13 @@
   LHS.weight += RHS.weight;
   if (RHS.preference && !LHS.preference)
     LHS.preference = RHS.preference;
-  
+
+  // Update the liveintervals of sub-registers.
+  if (TargetRegisterInfo::isPhysicalRegister(LHS.reg))
+    for (const unsigned *AS = tri_->getSubRegisters(LHS.reg); *AS; ++AS)
+      li_->getOrCreateInterval(*AS).MergeInClobberRanges(LHS,
+                                                    li_->getVNInfoAllocator());
+
   return true;
 }
 
@@ -2183,7 +2206,8 @@
     if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
       DstReg = Inst->getOperand(0).getReg();
       SrcReg = Inst->getOperand(1).getReg();
-    } else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
+    } else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+               Inst->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
       DstReg = Inst->getOperand(0).getReg();
       SrcReg = Inst->getOperand(2).getReg();
     } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
@@ -2498,7 +2522,8 @@
         // Delete all coalesced copies.
         if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
           assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
-                  MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) &&
+                  MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+                  MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
                  "Unrecognized copy instruction");
           DstReg = MI->getOperand(0).getReg();
         }

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=68576&r1=68575&r2=68576&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Tue Apr  7 19:15:30 2009
@@ -177,7 +177,7 @@
     break;
   }
 
-  if (!KillMI || KillMI->getParent() != MBB)
+  if (!KillMI || KillMI->getParent() != MBB || KillMI == MI)
     return false;
 
   // If any of the definitions are used by another instruction between the
@@ -326,6 +326,9 @@
     } else if (MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
       DstReg = MI.getOperand(0).getReg();
       SrcReg = MI.getOperand(2).getReg();
+    } else if (MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
+      DstReg = MI.getOperand(0).getReg();
+      SrcReg = MI.getOperand(2).getReg();
     }
   }
 
@@ -337,6 +340,46 @@
   return false;
 }
 
+/// isKilled - Test if the given register value, which is used by the given
+/// instruction, is killed by the given instruction. This looks through
+/// coalescable copies to see if the original value is potentially not killed.
+///
+/// For example, in this code:
+///
+///   %reg1034 = copy %reg1024
+///   %reg1035 = copy %reg1025<kill>
+///   %reg1036 = add %reg1034<kill>, %reg1035<kill>
+///
+/// %reg1034 is not considered to be killed, since it is copied from a
+/// register which is not killed. Treating it as not killed lets the
+/// normal heuristics commute the (two-address) add, which lets
+/// coalescing eliminate the extra copy.
+///
+static bool isKilled(MachineInstr &MI, unsigned Reg,
+                     const MachineRegisterInfo *MRI,
+                     const TargetInstrInfo *TII) {
+  MachineInstr *DefMI = &MI;
+  for (;;) {
+    if (!DefMI->killsRegister(Reg))
+      return false;
+    if (TargetRegisterInfo::isPhysicalRegister(Reg))
+      return true;
+    MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
+    // If there are multiple defs, we can't do a simple analysis, so just
+    // go with what the kill flag says.
+    if (next(Begin) != MRI->def_end())
+      return true;
+    DefMI = &*Begin;
+    bool IsSrcPhys, IsDstPhys;
+    unsigned SrcReg,  DstReg;
+    // If the def is something other than a copy, then it isn't going to
+    // be coalesced, so follow the kill flag.
+    if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
+      return true;
+    Reg = SrcReg;
+  }
+}
+
 /// isTwoAddrUse - Return true if the specified MI uses the specified register
 /// as a two-address use. If so, return the destination register by reference.
 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
@@ -735,7 +778,7 @@
           // rearrange the code to make it so.  Making it the killing user will
           // allow us to coalesce A and B together, eliminating the copy we are
           // about to insert.
-          if (!mi->killsRegister(regB)) {
+          if (!isKilled(*mi, regB, MRI, TII)) {
             // If regA is dead and the instruction can be deleted, just delete
             // it so it doesn't clobber regB.
             if (mi->getOperand(ti).isDead() && isSafeToDelete(mi, TII)) {
@@ -753,7 +796,7 @@
               assert(mi->getOperand(3-si).isReg() &&
                      "Not a proper commutative instruction!");
               unsigned regC = mi->getOperand(3-si).getReg();
-              if (mi->killsRegister(regC)) {
+              if (isKilled(*mi, regC, MRI, TII)) {
                 if (CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
                   ++NumCommuted;
                   regB = regC;

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=68576&r1=68575&r2=68576&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Apr  7 19:15:30 2009
@@ -7258,6 +7258,16 @@
   return Subtarget->is64Bit() || NumBits1 < 64;
 }
 
+bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
+  // x86-64 has implicitly zero-extends 32-bit results in 64-bit registers.
+  return Ty1 == Type::Int32Ty && Ty2 == Type::Int64Ty && Subtarget->is64Bit();
+}
+
+bool X86TargetLowering::isZExtFree(MVT VT1, MVT VT2) const {
+  // x86-64 has implicitly zero-extends 32-bit results in 64-bit registers.
+  return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
+}
+
 /// isShuffleMaskLegal - Targets can use this to indicate that they only
 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=68576&r1=68575&r2=68576&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Apr  7 19:15:30 2009
@@ -458,7 +458,18 @@
     /// register EAX to i16 by referencing its sub-register AX.
     virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
     virtual bool isTruncateFree(MVT VT1, MVT VT2) const;
-  
+
+    /// isZExtFree - Return true if any actual instruction that defines a
+    /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
+    /// register. This does not necessarily include registers defined in
+    /// unknown ways, such as incoming arguments, or copies from unknown
+    /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
+    /// does not necessarily apply to truncate instructions. e.g. on x86-64,
+    /// all instructions that define 32-bit values implicit zero-extend the
+    /// result out to 64 bits.
+    virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const;
+    virtual bool isZExtFree(MVT VT1, MVT VT2) const;
+
     /// isShuffleMaskLegal - Targets can use this to indicate that they only
     /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
     /// By default, if a target supports the VECTOR_SHUFFLE node, all mask

Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=68576&r1=68575&r2=68576&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Tue Apr  7 19:15:30 2009
@@ -292,10 +292,12 @@
                    [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
 
 // There's no movzlq instruction, but movl can be used for this purpose, using
-// implicit zero-extension. We need this because the seeming alternative for
-// implementing zext from 32 to 64, an EXTRACT_SUBREG/SUBREG_TO_REG pair, isn't
-// safe because both instructions could be optimized away in the
-// register-to-register case, leaving nothing behind to do the zero extension.
+// implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
+// extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
+// zero-extension, however this isn't possible when the 32-bit value is
+// defined by a truncate or is copied from something where the high bits aren't
+// necessarily all zero. In such cases, we fall back to these explicit zext
+// instructions.
 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
                     "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
                     [(set GR64:$dst, (zext GR32:$src))]>;
@@ -303,6 +305,21 @@
                     "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
                     [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
 
+// Any instruction that defines a 32-bit result leaves the high half of the
+// register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
+// be copying from a truncate, but any other 32-bit operation will zero-extend
+// up to 64 bits.
+def def32 : PatLeaf<(i32 GR32:$src), [{
+  return N->getOpcode() != ISD::TRUNCATE &&
+         N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
+         N->getOpcode() != ISD::CopyFromReg;
+}]>;
+
+// In the case of a 32-bit def that is known to implicitly zero-extend,
+// we can use a SUBREG_TO_REG.
+def : Pat<(i64 (zext def32:$src)),
+          (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
+
 let neverHasSideEffects = 1 in {
   let Defs = [RAX], Uses = [EAX] in
   def CDQE : RI<0x98, RawFrm, (outs), (ins),
@@ -1443,10 +1460,6 @@
 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
           (CMOVO64rm GR64:$src2, addr:$src1)>;
 
-// Zero-extension
-def : Pat<(i64 (zext GR32:$src)), 
-          (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
-
 // zextload bool -> zextload byte
 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
 

Removed: llvm/trunk/test/CodeGen/X86/2008-05-06-SpillerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-05-06-SpillerBug.ll?rev=68575&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-05-06-SpillerBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-05-06-SpillerBug.ll (removed)
@@ -1,39 +0,0 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -relocation-model=pic -disable-fp-elim | grep addb | grep ebp
-
-	%struct.rc4_state = type { i32, i32, [256 x i32] }
- at .str1 = internal constant [65 x i8] c"m[%d] = 0x%02x, m[%d] = 0x%02x, 0x%02x, k = %d, key[k] = 0x%02x\0A\00"		; <[65 x i8]*> [#uses=1]
- at keys = internal constant [7 x [30 x i8]] [ [30 x i8] c"\08\01#Eg\89\AB\CD\EF\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", [30 x i8] c"\08\01#Eg\89\AB\CD\EF\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", [30 x i8] c"\08\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", [30 x i8] c"\04\EF\01#E\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", [30 x i8] c"\08\01#Eg\89\AB\CD\EF\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", [30 x i8] c"\04\EF\01#E\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", [30 x i8] zeroinitializer ]		; <[7 x [30 x i8]]*> [#uses=1]
-
-declare i32 @printf(i8*, ...) nounwind 
-
-define i32 @main(i32 %argc, i8** %argv) nounwind  {
-entry:
-	br label %bb25
-
-bb25:		; preds = %bb25, %entry
-  %foo = phi i1 [ 0, %bb25], [ 1, %entry]
-	br i1 %foo, label %bb.i, label %bb25
-
-bb.i:		; preds = %bb.i, %bb25
-  %foo2 = phi i1 [ 0, %bb.i], [1, %bb25]
-	br i1 %foo2, label %bb21.i, label %bb.i
-
-bb21.i:		; preds = %bb21.i, %bb.i
-	%k.0.reg2mem.0.i = phi i32 [ %k.1.i, %bb21.i ], [ 0, %bb.i ]		; <i32> [#uses=2]
-	%j.0.reg2mem.0.i = phi i8 [ %tmp35.i, %bb21.i ], [ 0, %bb.i ]		; <i8> [#uses=1]
-	%tmp25.i = load i32* null, align 4		; <i32> [#uses=4]
-	%tmp2829.i = trunc i32 %tmp25.i to i8		; <i8> [#uses=1]
-	%.sum = add i32 %k.0.reg2mem.0.i, 1		; <i32> [#uses=3]
-	%tmp33.i = getelementptr [7 x [30 x i8]]* @keys, i32 0, i32 0, i32 %.sum		; <i8*> [#uses=1]
-	%tmp34.i = load i8* %tmp33.i, align 1		; <i8> [#uses=1]
-	%tmp30.i = add i8 %tmp2829.i, %j.0.reg2mem.0.i		; <i8> [#uses=1]
-	%tmp35.i = add i8 %tmp30.i, %tmp34.i		; <i8> [#uses=2]
-	%tmp3536.i = zext i8 %tmp35.i to i32		; <i32> [#uses=2]
-	%tmp39.i = getelementptr %struct.rc4_state* null, i32 0, i32 2, i32 %tmp3536.i		; <i32*> [#uses=1]
-	store i32 %tmp25.i, i32* %tmp39.i, align 4
-	%tmp60.i = load i32* null, align 4		; <i32> [#uses=1]
-	%tmp65.i = call i32 (i8*, ...)* @printf( i8* getelementptr ([65 x i8]* @.str1, i32 0, i32 0), i32 0, i32 %tmp60.i, i32 %tmp3536.i, i32 %tmp25.i, i32 %tmp25.i, i32 %k.0.reg2mem.0.i, i32 0 ) nounwind 		; <i32> [#uses=0]
-	%tmp70.i = icmp slt i32 %.sum, 8		; <i1> [#uses=1]
-	%k.1.i = select i1 %tmp70.i, i32 %.sum, i32 0		; <i32> [#uses=1]
-	br label %bb21.i
-}

Modified: llvm/trunk/test/CodeGen/X86/byval7.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/byval7.ll?rev=68576&r1=68575&r2=68576&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/byval7.ll (original)
+++ llvm/trunk/test/CodeGen/X86/byval7.ll Tue Apr  7 19:15:30 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | grep add | grep 16
+; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | egrep {add|lea} | grep 16
 
 	%struct.S = type { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>,
                            <2 x i64> }

Modified: llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll?rev=68576&r1=68575&r2=68576&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll (original)
+++ llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll Tue Apr  7 19:15:30 2009
@@ -1,7 +1,7 @@
 ; RUN: llvm-as < %s | llc -march=x86-64 -f -o %t
 ; RUN: grep inc %t | count 2
 ; RUN: grep addq %t | count 13
-; RUN: grep leaq %t | count 10
+; RUN: grep leaq %t | count 9
 ; RUN: grep movq %t | count 5
 
 ; IV users in each of the loops from other loops shouldn't cause LSR

Modified: llvm/trunk/test/CodeGen/X86/subreg-to-reg-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/subreg-to-reg-1.ll?rev=68576&r1=68575&r2=68576&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/subreg-to-reg-1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/subreg-to-reg-1.ll Tue Apr  7 19:15:30 2009
@@ -1,6 +1,9 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {movl	%e.\*, %e.\*} | count 1
+; RUN: llvm-as < %s | llc -march=x86-64 | grep {leal	.*), %e.\*} | count 1
 
 ; Don't eliminate or coalesce away the explicit zero-extension!
+; This is currently using an leal because of a 3-addressification detail,
+; though this isn't necessary; The point of this test is to make sure
+; a 32-bit add is used.
 
 define i64 @foo(i64 %a) {
   %b = add i64 %a, 4294967295

Added: llvm/trunk/test/CodeGen/X86/subreg-to-reg-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/subreg-to-reg-3.ll?rev=68576&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/subreg-to-reg-3.ll (added)
+++ llvm/trunk/test/CodeGen/X86/subreg-to-reg-3.ll Tue Apr  7 19:15:30 2009
@@ -0,0 +1,10 @@
+; RUN: llvm-as < %s | llc -march=x86-64 | grep imull
+
+; Don't eliminate or coalesce away the explicit zero-extension!
+
+define i64 @foo(i64 %a) {
+  %b = mul i64 %a, 7823
+  %c = and i64 %b, 4294967295
+  %d = add i64 %c, 1
+  ret i64 %d
+}

Added: llvm/trunk/test/CodeGen/X86/subreg-to-reg-4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/subreg-to-reg-4.ll?rev=68576&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/subreg-to-reg-4.ll (added)
+++ llvm/trunk/test/CodeGen/X86/subreg-to-reg-4.ll Tue Apr  7 19:15:30 2009
@@ -0,0 +1,135 @@
+; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: not grep leaq %t
+; RUN: not grep incq %t
+; RUN: not grep decq %t
+; RUN: not grep negq %t
+; RUN: not grep addq %t
+; RUN: not grep subq %t
+; RUN: not grep {movl	%} %t
+
+; Utilize implicit zero-extension on x86-64 to eliminate explicit
+; zero-extensions. Shrink 64-bit adds to 32-bit when the high
+; 32-bits will be zeroed.
+
+define void @bar(i64 %x, i64 %y, i64* %z) nounwind readnone {
+entry:
+	%t0 = add i64 %x, %y
+	%t1 = and i64 %t0, 4294967295
+        store i64 %t1, i64* %z
+	ret void
+}
+define void @easy(i32 %x, i32 %y, i64* %z) nounwind readnone {
+entry:
+	%t0 = add i32 %x, %y
+        %tn = zext i32 %t0 to i64
+	%t1 = and i64 %tn, 4294967295
+        store i64 %t1, i64* %z
+	ret void
+}
+define void @cola(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone {
+entry:
+        %p = load i64* %x
+	%t0 = add i64 %p, %y
+	%t1 = and i64 %t0, 4294967295
+        %t2 = xor i64 %t1, %u
+        store i64 %t2, i64* %z
+	ret void
+}
+define void @yaks(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone {
+entry:
+        %p = load i64* %x
+	%t0 = add i64 %p, %y
+        %t1 = xor i64 %t0, %u
+	%t2 = and i64 %t1, 4294967295
+        store i64 %t2, i64* %z
+	ret void
+}
+define void @foo(i64 *%x, i64 *%y, i64* %z) nounwind readnone {
+entry:
+        %a = load i64* %x
+        %b = load i64* %y
+	%t0 = add i64 %a, %b
+	%t1 = and i64 %t0, 4294967295
+        store i64 %t1, i64* %z
+	ret void
+}
+define void @avo(i64 %x, i64* %z, i64 %u) nounwind readnone {
+entry:
+	%t0 = add i64 %x, 734847
+	%t1 = and i64 %t0, 4294967295
+        %t2 = xor i64 %t1, %u
+        store i64 %t2, i64* %z
+	ret void
+}
+define void @phe(i64 %x, i64* %z, i64 %u) nounwind readnone {
+entry:
+	%t0 = add i64 %x, 734847
+        %t1 = xor i64 %t0, %u
+	%t2 = and i64 %t1, 4294967295
+        store i64 %t2, i64* %z
+	ret void
+}
+define void @oze(i64 %y, i64* %z) nounwind readnone {
+entry:
+	%t0 = add i64 %y, 1
+	%t1 = and i64 %t0, 4294967295
+        store i64 %t1, i64* %z
+	ret void
+}
+
+define void @sbar(i64 %x, i64 %y, i64* %z) nounwind readnone {
+entry:
+	%t0 = sub i64 %x, %y
+	%t1 = and i64 %t0, 4294967295
+        store i64 %t1, i64* %z
+	ret void
+}
+define void @seasy(i32 %x, i32 %y, i64* %z) nounwind readnone {
+entry:
+	%t0 = sub i32 %x, %y
+        %tn = zext i32 %t0 to i64
+	%t1 = and i64 %tn, 4294967295
+        store i64 %t1, i64* %z
+	ret void
+}
+define void @scola(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone {
+entry:
+        %p = load i64* %x
+	%t0 = sub i64 %p, %y
+	%t1 = and i64 %t0, 4294967295
+        %t2 = xor i64 %t1, %u
+        store i64 %t2, i64* %z
+	ret void
+}
+define void @syaks(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone {
+entry:
+        %p = load i64* %x
+	%t0 = sub i64 %p, %y
+        %t1 = xor i64 %t0, %u
+	%t2 = and i64 %t1, 4294967295
+        store i64 %t2, i64* %z
+	ret void
+}
+define void @sfoo(i64 *%x, i64 *%y, i64* %z) nounwind readnone {
+entry:
+        %a = load i64* %x
+        %b = load i64* %y
+	%t0 = sub i64 %a, %b
+	%t1 = and i64 %t0, 4294967295
+        store i64 %t1, i64* %z
+	ret void
+}
+define void @swya(i64 %y, i64* %z) nounwind readnone {
+entry:
+	%t0 = sub i64 0, %y
+	%t1 = and i64 %t0, 4294967295
+        store i64 %t1, i64* %z
+	ret void
+}
+define void @soze(i64 %y, i64* %z) nounwind readnone {
+entry:
+	%t0 = sub i64 %y, 1
+	%t1 = and i64 %t0, 4294967295
+        store i64 %t1, i64* %z
+	ret void
+}

Added: llvm/trunk/test/CodeGen/X86/subreg-to-reg-5.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/subreg-to-reg-5.ll?rev=68576&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/subreg-to-reg-5.ll (added)
+++ llvm/trunk/test/CodeGen/X86/subreg-to-reg-5.ll Tue Apr  7 19:15:30 2009
@@ -0,0 +1,34 @@
+; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: grep addl %t
+; RUN: not egrep {movl|movq} %t
+
+define float @foo(float* %B) nounwind {
+entry:
+	br label %bb2
+
+bb2:		; preds = %bb3, %entry
+	%B_addr.0.rec = phi i64 [ %indvar.next154, %bb3 ], [ 0, %entry ]		; <i64> [#uses=2]
+	br i1 false, label %bb3, label %bb4
+
+bb3:		; preds = %bb2
+	%indvar.next154 = add i64 %B_addr.0.rec, 1		; <i64> [#uses=1]
+	br label %bb2
+
+bb4:		; preds = %bb2
+	%B_addr.0 = getelementptr float* %B, i64 %B_addr.0.rec		; <float*> [#uses=1]
+	%t1 = ptrtoint float* %B_addr.0 to i64		; <i64> [#uses=1]
+	%t2 = and i64 %t1, 15		; <i64> [#uses=1]
+	%t3 = icmp eq i64 %t2, 0		; <i1> [#uses=1]
+	br i1 %t3, label %bb5, label %bb10.preheader
+
+bb10.preheader:		; preds = %bb4
+	br label %bb9
+
+bb5:		; preds = %bb4
+	unreachable
+
+bb9:		; preds = %bb10.preheader
+	%t5 = getelementptr float* %B, i64 0		; <float*> [#uses=1]
+	%t7 = load float* %t5		; <float> [#uses=1]
+	ret float %t7
+}

Added: llvm/trunk/test/CodeGen/X86/subreg-to-reg-6.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/subreg-to-reg-6.ll?rev=68576&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/subreg-to-reg-6.ll (added)
+++ llvm/trunk/test/CodeGen/X86/subreg-to-reg-6.ll Tue Apr  7 19:15:30 2009
@@ -0,0 +1,29 @@
+; RUN: llvm-as < %s | llc -march=x86-64
+
+define i64 @foo() nounwind {
+entry:
+	%t0 = load i32* null, align 8
+	switch i32 %t0, label %bb65 [
+		i32 16, label %bb
+		i32 12, label %bb56
+	]
+
+bb:
+	br label %bb65
+
+bb56:
+	unreachable
+
+bb65:
+	%a = phi i64 [ 0, %bb ], [ 0, %entry ]
+	tail call void asm "", "{cx}"(i64 %a) nounwind
+	%t15 = and i64 %a, 4294967295
+	ret i64 %t15
+}
+
+define i64 @bar(i64 %t0) nounwind {
+	call void asm "", "{cx}"(i64 0) nounwind
+	%t1 = sub i64 0, %t0
+	%t2 = and i64 %t1, 4294967295
+	ret i64 %t2
+}

Modified: llvm/trunk/test/CodeGen/X86/twoaddr-coalesce.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/twoaddr-coalesce.ll?rev=68576&r1=68575&r2=68576&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/twoaddr-coalesce.ll (original)
+++ llvm/trunk/test/CodeGen/X86/twoaddr-coalesce.ll Tue Apr  7 19:15:30 2009
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -stats |& \
-; RUN:   grep {twoaddrinstr} | grep {Number of instructions aggressively commuted}
+; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 5
 ; rdar://6523745
 
 @"\01LC" = internal constant [4 x i8] c"%d\0A\00"		; <[4 x i8]*> [#uses=1]




From sabre at nondot.org  Tue Apr  7 19:28:40 2009
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 08 Apr 2009 00:28:40 -0000
Subject: [llvm-commits] [llvm] r68577 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
Message-ID: <200904080028.n380SeiL003341@zion.cs.uiuc.edu>

Author: lattner
Date: Tue Apr  7 19:28:38 2009
New Revision: 68577

URL: http://llvm.org/viewvc/llvm-project?rev=68577&view=rev
Log:
change printStringChar to emit characters as unsigned char instead of char,
avoiding sign extension for the top octet.  For "negative" chars, we'd print
stuff like:

.asciz	"\702...
now we print:
.asciz	"\302...


Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=68577&r1=68576&r2=68577&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Apr  7 19:28:38 2009
@@ -699,7 +699,7 @@
 
 /// printStringChar - Print a char, escaped if necessary.
 ///
-static void printStringChar(raw_ostream &O, char C) {
+static void printStringChar(raw_ostream &O, unsigned char C) {
   if (C == '"') {
     O << "\\\"";
   } else if (C == '\\') {
@@ -733,10 +733,8 @@
   else
     O << TAI->getAsciiDirective();
   O << '\"';
-  for (unsigned i = 0, N = String.size(); i < N; ++i) {
-    unsigned char C = String[i];
-    printStringChar(O, C);
-  }
+  for (unsigned i = 0, N = String.size(); i < N; ++i)
+    printStringChar(O, String[i]);
   if (AscizDirective)
     O << '\"';
   else
@@ -747,10 +745,8 @@
 /// EmitFile - Emit a .file directive.
 void AsmPrinter::EmitFile(unsigned Number, const std::string &Name) const {
   O << "\t.file\t" << Number << " \"";
-  for (unsigned i = 0, N = Name.size(); i < N; ++i) {
-    unsigned char C = Name[i];
-    printStringChar(O, C);
-  }
+  for (unsigned i = 0, N = Name.size(); i < N; ++i)
+    printStringChar(O, Name[i]);
   O << '\"';
 }
 




From gohman at apple.com  Tue Apr  7 19:51:11 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 08 Apr 2009 00:51:11 -0000
Subject: [llvm-commits] [llvm] r68579 -
	/llvm/trunk/test/CodeGen/X86/dyn-stackalloc.ll
Message-ID: <200904080051.n380pCw3004305@zion.cs.uiuc.edu>

Author: djg
Date: Tue Apr  7 19:51:11 2009
New Revision: 68579

URL: http://llvm.org/viewvc/llvm-project?rev=68579&view=rev
Log:
Update this test for recent codegen improvements. CodeGen is now
using an lea in place of a mov and an add for this test.

Modified:
    llvm/trunk/test/CodeGen/X86/dyn-stackalloc.ll

Modified: llvm/trunk/test/CodeGen/X86/dyn-stackalloc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dyn-stackalloc.ll?rev=68579&r1=68578&r2=68579&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/dyn-stackalloc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/dyn-stackalloc.ll Tue Apr  7 19:51:11 2009
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep 4294967289
-; RUN: llvm-as < %s | llc -march=x86 | grep 4294967280
+; RUN: llvm-as < %s | llc -march=x86 | not egrep {\$4294967289|-7\\(}
+; RUN: llvm-as < %s | llc -march=x86 | egrep {\$4294967280|-16\\(}
 ; RUN: llvm-as < %s | llc -march=x86-64 | grep {\\-16}
 
 define void @t() {




From gohman at apple.com  Tue Apr  7 19:54:41 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 08 Apr 2009 00:54:41 -0000
Subject: [llvm-commits] [llvm] r68580 -
	/llvm/trunk/test/CodeGen/X86/dyn-stackalloc.ll
Message-ID: <200904080054.n380sfS7004464@zion.cs.uiuc.edu>

Author: djg
Date: Tue Apr  7 19:54:40 2009
New Revision: 68580

URL: http://llvm.org/viewvc/llvm-project?rev=68580&view=rev
Log:
Fully escape the grep string for this test.

Modified:
    llvm/trunk/test/CodeGen/X86/dyn-stackalloc.ll

Modified: llvm/trunk/test/CodeGen/X86/dyn-stackalloc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dyn-stackalloc.ll?rev=68580&r1=68579&r2=68580&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/dyn-stackalloc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/dyn-stackalloc.ll Tue Apr  7 19:54:40 2009
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | not egrep {\$4294967289|-7\\(}
-; RUN: llvm-as < %s | llc -march=x86 | egrep {\$4294967280|-16\\(}
+; RUN: llvm-as < %s | llc -march=x86 | not egrep {\\\$4294967289|-7\\(}
+; RUN: llvm-as < %s | llc -march=x86 | egrep {\\\$4294967280|-16\\(}
 ; RUN: llvm-as < %s | llc -march=x86-64 | grep {\\-16}
 
 define void @t() {




From sabre at nondot.org  Tue Apr  7 22:43:51 2009
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 08 Apr 2009 03:43:51 -0000
Subject: [llvm-commits] [llvm] r68588 - in /llvm/trunk:
 docs/CommandLine.html include/llvm/Support/CommandLine.h
 lib/Support/CommandLine.cpp
Message-ID: <200904080343.n383hqb0010896@zion.cs.uiuc.edu>

Author: lattner
Date: Tue Apr  7 22:43:51 2009
New Revision: 68588

URL: http://llvm.org/viewvc/llvm-project?rev=68588&view=rev
Log:
Remove AllowInverse: it leaks memory and is not the right
abstraction for CommandLine.

Modified:
    llvm/trunk/docs/CommandLine.html
    llvm/trunk/include/llvm/Support/CommandLine.h
    llvm/trunk/lib/Support/CommandLine.cpp

Modified: llvm/trunk/docs/CommandLine.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CommandLine.html?rev=68588&r1=68587&r2=68588&view=diff

==============================================================================
--- llvm/trunk/docs/CommandLine.html (original)
+++ llvm/trunk/docs/CommandLine.html Tue Apr  7 22:43:51 2009
@@ -1447,17 +1447,6 @@
 error. As with <b><tt>cl::CommaSeparated</tt></b></a>, this modifier
 only makes sense with a <a href="#cl::list">cl::list</a> option.</li>
 
-<li><a name="cl::AllowInverse">The <b><tt>cl::AllowInverse</tt></b></a>
-modifier can be used on options that have the form <tt>-fopt</tt> to
-automatically create a corresponding
-<tt>-fno-opt</tt> option.  The <tt>f</tt> can be any single
-character, and the <tt>opt</tt> can be any one or more characters.
-The value of the created option is the logical complement of the value
-that would have been used if the base form of the option was used.
-This modifier only makes sense with an option that uses
-a <a href="#boolparser">bool parser</a>.</li>
-
-
 </ul>
 
 <p>So far, these are the only three miscellaneous option modifiers.</p>
@@ -1755,11 +1744,7 @@
 <li><a name="boolparser">The <b><tt>parser&lt;bool&gt;</tt> specialization</b></a>
 is used to convert boolean strings to a boolean value.  Currently accepted
 strings are "<tt>true</tt>", "<tt>TRUE</tt>", "<tt>True</tt>", "<tt>1</tt>",
-"<tt>false</tt>", "<tt>FALSE</tt>", "<tt>False</tt>", and "<tt>0</tt>".  The
-<b><tt>cl::AllowInverse</tt></b> modifier can be used on an option of the form
-<tt>-fopt</tt> that uses the <tt>parser&lt;bool&gt;</tt> specialization
-to create a corresponding option with the form <tt>-fno-opt</tt>.  See
-<a href="#cl::AllowInverse"><tt>cl::AllowInverse</tt></a> for details.</li>
+"<tt>false</tt>", "<tt>FALSE</tt>", "<tt>False</tt>", and "<tt>0</tt>".</li>
 
 <li><a name="boolOrDefaultparser">The <b><tt>parser&lt;boolOrDefault&gt;</tt>
  specialization</b></a> is used for cases where the value is boolean,

Modified: llvm/trunk/include/llvm/Support/CommandLine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CommandLine.h?rev=68588&r1=68587&r2=68588&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Support/CommandLine.h (original)
+++ llvm/trunk/include/llvm/Support/CommandLine.h Tue Apr  7 22:43:51 2009
@@ -127,8 +127,7 @@
   CommaSeparated     = 0x200,  // Should this cl::list split between commas?
   PositionalEatsArgs = 0x400,  // Should this positional cl::list eat -args?
   Sink               = 0x800,  // Should this cl::list eat all unknown options?
-  AllowInverse	     = 0x1000, // Can this option take a -Xno- form?
-  MiscMask           = 0x1E00  // Union of the above flags.
+  MiscMask           = 0xE00   // Union of the above flags.
 };
 
 
@@ -538,17 +537,14 @@
 //
 template<>
 class parser<bool> : public basic_parser<bool> {
-  bool IsInvertible;	// Should we synthesize a -xno- style option?
   const char *ArgStr;
 public:
-  void getExtraOptionNames(std::vector<const char*> &OptionNames);
   
   // parse - Return true on error.
   bool parse(Option &O, const char *ArgName, const std::string &Arg, bool &Val);
 
   template <class Opt>
   void initialize(Opt &O) {
-    IsInvertible = (O.getMiscFlags() & llvm::cl::AllowInverse);
     ArgStr = O.ArgStr;
   }
 

Modified: llvm/trunk/lib/Support/CommandLine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CommandLine.cpp?rev=68588&r1=68587&r2=68588&view=diff

==============================================================================
--- llvm/trunk/lib/Support/CommandLine.cpp (original)
+++ llvm/trunk/lib/Support/CommandLine.cpp Tue Apr  7 22:43:51 2009
@@ -872,30 +872,9 @@
     return O.error(": '" + Arg +
                    "' is invalid value for boolean argument! Try 0 or 1");
   }
-  if (IsInvertible && strncmp(ArgName+1, "no-", 3) == 0)
-    Value = !Value;
   return false;
 }
 
-void parser<bool>::getExtraOptionNames(std::vector<const char*> &OptionNames) {
-  if (!IsInvertible)
-    return;
-  
-  char *s = new char [strlen(ArgStr) + 3 + 1];
-  s[0] = ArgStr[0];
-  if (strncmp(ArgStr+1, "no-", 3) == 0)
-    strcpy(&s[1], &ArgStr[4]);
-  else {
-    s[1] = 'n';
-    s[2] = 'o';
-    s[3] = '-';
-    strcpy(&s[4], ArgStr+1);
-  }
-  OptionNames.push_back(s);
-}
-
-
-
 // parser<boolOrDefault> implementation
 //
 bool parser<boolOrDefault>::parse(Option &O, const char *ArgName,




From sabre at nondot.org  Tue Apr  7 23:37:00 2009
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 08 Apr 2009 04:37:00 -0000
Subject: [llvm-commits] [llvm] r68592 - /llvm/trunk/lib/VMCore/Type.cpp
Message-ID: <200904080437.n384b0SB012965@zion.cs.uiuc.edu>

Author: lattner
Date: Tue Apr  7 23:36:59 2009
New Revision: 68592

URL: http://llvm.org/viewvc/llvm-project?rev=68592&view=rev
Log:
disable this code for now, re-breaking PR2975, but fixing
a testcase I'm about to attach to that pr.

Modified:
    llvm/trunk/lib/VMCore/Type.cpp

Modified: llvm/trunk/lib/VMCore/Type.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Type.cpp?rev=68592&r1=68591&r2=68592&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/Type.cpp (original)
+++ llvm/trunk/lib/VMCore/Type.cpp Tue Apr  7 23:36:59 2009
@@ -670,12 +670,11 @@
   std::multimap<unsigned, PATypeHolder> TypesByHash;
 
 public:
-  ~TypeMapBase()
-  {
+  ~TypeMapBase() {
     // PATypeHolder won't destroy non-abstract types.
     // We can't destroy them by simply iterating, because
     // they may contain references to each-other.
-
+#if 0
     for (std::multimap<unsigned, PATypeHolder>::iterator I
          = TypesByHash.begin(), E = TypesByHash.end(); I != E; ++I) {
       Type *Ty = const_cast<Type*>(I->second.Ty);
@@ -689,6 +688,7 @@
         operator delete(Ty);
       }
     }
+#endif
   }
 
   void RemoveFromTypesByHash(unsigned Hash, const Type *Ty) {




From sanjiv.gupta at microchip.com  Wed Apr  8 00:38:48 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Wed, 08 Apr 2009 05:38:48 -0000
Subject: [llvm-commits] [llvm] r68597 - in /llvm/trunk/lib/Target/PIC16:
 PIC16AsmPrinter.cpp PIC16ISelLowering.cpp PIC16ISelLowering.h
 PIC16InstrInfo.td PIC16RegisterInfo.td
Message-ID: <200904080538.n385cmsB015433@zion.cs.uiuc.edu>

Author: sgupta
Date: Wed Apr  8 00:38:48 2009
New Revision: 68597

URL: http://llvm.org/viewvc/llvm-project?rev=68597&view=rev
Log:
Handle indirect function calls.
Every function has the address of its frame in the beginning of code section.
The frame address is retrieved and used to pass arguments.


Modified:
    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h
    llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td
    llvm/trunk/lib/Target/PIC16/PIC16RegisterInfo.td

Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=68597&r1=68596&r2=68597&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Wed Apr  8 00:38:48 2009
@@ -113,6 +113,10 @@
                                                SectionFlags::Code);
   O <<  "\n";
   SwitchToSection (fCodeSection);
+  O << CurrentFnName << ":\n";
+  O << "    retlw  low(" << CurrentFnName << ".frame)\n";
+  O << "    retlw  high(" << CurrentFnName << ".frame)\n"; 
+
 
   // Print out code for the function.
   for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
@@ -122,8 +126,6 @@
       printBasicBlockLabel(I, true);
       O << '\n';
     }
-    else
-      O << CurrentFnName << ":\n";
     CurBank = "";
     for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
          II != E; ++II) {

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=68597&r1=68596&r2=68597&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Wed Apr  8 00:38:48 2009
@@ -255,6 +255,8 @@
   case PIC16ISD::Hi:               return "PIC16ISD::Hi";
   case PIC16ISD::MTLO:             return "PIC16ISD::MTLO";
   case PIC16ISD::MTHI:             return "PIC16ISD::MTHI";
+  case PIC16ISD::MTPCLATH:         return "PIC16ISD::MTPCLATH";
+  case PIC16ISD::PIC16Connect:     return "PIC16ISD::PIC16Connect";
   case PIC16ISD::Banksel:          return "PIC16ISD::Banksel";
   case PIC16ISD::PIC16Load:        return "PIC16ISD::PIC16Load";
   case PIC16ISD::PIC16LdArg:       return "PIC16ISD::PIC16LdArg";
@@ -267,6 +269,7 @@
   case PIC16ISD::RLF:              return "PIC16ISD::RLF";
   case PIC16ISD::RRF:              return "PIC16ISD::RRF";
   case PIC16ISD::CALL:             return "PIC16ISD::CALL";
+  case PIC16ISD::CALLW:            return "PIC16ISD::CALLW";
   case PIC16ISD::SUBCC:            return "PIC16ISD::SUBCC";
   case PIC16ISD::SELECT_ICC:       return "PIC16ISD::SELECT_ICC";
   case PIC16ISD::BRCOND:           return "PIC16ISD::BRCOND";
@@ -872,12 +875,44 @@
     
   return Load.getValue(0);
 }
+
+SDValue PIC16TargetLowering::
+LowerIndirectCallArguments(SDValue Op, SDValue Chain, SDValue InFlag,
+                           SDValue DataAddr_Lo, SDValue DataAddr_Hi,
+                           SelectionDAG &DAG) {
+  CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
+  unsigned NumOps = TheCall->getNumArgs();
+  DebugLoc dl = TheCall->getDebugLoc();
+
+  // If call has no arguments then do nothing and return.
+  if (NumOps == 0)
+    return Chain;
+
+  std::vector<SDValue> Ops;
+  SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
+  SDValue Arg, StoreRet;
+  for (unsigned i=0; i<NumOps; i++) {
+    // Get the arguments
+    Arg = TheCall->getArg(i);
+    Ops.clear();
+    Ops.push_back(Chain);
+    Ops.push_back(Arg);
+    Ops.push_back(DataAddr_Lo);
+    Ops.push_back(DataAddr_Hi);
+    Ops.push_back(DAG.getConstant(i, MVT::i8));
+    Ops.push_back(InFlag);
+
+    StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
+
+    Chain = getChain(StoreRet);
+    InFlag = getOutFlag(StoreRet);
+  }
+  return Chain;
+}
           
-SDValue
-PIC16TargetLowering::LowerCallArguments(SDValue Op, SDValue Chain,
-                                        SDValue FrameAddress, 
-                                        SDValue InFlag,
-                                        SelectionDAG &DAG) {
+SDValue PIC16TargetLowering::
+LowerDirectCallArguments(SDValue Op, SDValue Chain, SDValue FrameAddress, 
+                         SDValue InFlag, SelectionDAG &DAG) {
   CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
   unsigned NumOps = TheCall->getNumArgs();
   DebugLoc dl = TheCall->getDebugLoc();
@@ -887,6 +922,9 @@
   unsigned Size=0;
   unsigned ArgCount=0;
 
+  // If call has no arguments then do nothing and return.
+  if (NumOps == 0)
+    return Chain; 
 
   // FIXME: This portion of code currently assumes only
   // primitive types being passed as arguments.
@@ -930,11 +968,40 @@
   return Chain;
 }
 
-SDValue
-PIC16TargetLowering::LowerCallReturn(SDValue Op, SDValue Chain,
-                                     SDValue FrameAddress,
-                                     SDValue InFlag,
-                                     SelectionDAG &DAG) {
+SDValue PIC16TargetLowering::
+LowerIndirectCallReturn (SDValue Op, SDValue Chain, SDValue InFlag,
+                         SDValue DataAddr_Lo, SDValue DataAddr_Hi,
+                         SelectionDAG &DAG) {
+  CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
+  DebugLoc dl = TheCall->getDebugLoc();
+  unsigned RetVals = TheCall->getNumRetVals();
+
+  // If call does not have anything to return
+  // then do nothing and go back.
+  if (RetVals == 0)
+    return Chain;
+
+  // Call has something to return
+  std::vector<SDValue> ResultVals;
+  SDValue LoadRet;
+
+  SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
+  for(unsigned i=0;i<RetVals;i++) {
+    LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, DataAddr_Lo,
+                          DataAddr_Hi, DAG.getConstant(i, MVT::i8),
+                          InFlag);
+    InFlag = getOutFlag(LoadRet);
+    Chain = getChain(LoadRet);
+    ResultVals.push_back(LoadRet);
+  }
+  ResultVals.push_back(Chain);
+  SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl);
+  return Res;
+}
+
+SDValue PIC16TargetLowering::
+LowerDirectCallReturn(SDValue Op, SDValue Chain, SDValue FrameAddress,
+                      SDValue InFlag, SelectionDAG &DAG) {
   CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
   DebugLoc dl = TheCall->getDebugLoc();
   // Currently handling primitive types only. They will come in
@@ -1014,46 +1081,147 @@
   return DAG.getNode(ISD::RET, dl, MVT::Other, Chain);
 }
 
-SDValue PIC16TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
+// CALL node may have some operands non-legal to PIC16. Generate new CALL
+// node with all the operands legal.
+// Currently only Callee operand of the CALL node is non-legal. This function
+// legalizes the Callee operand and uses all other operands as are to generate
+// new CALL node.
+
+SDValue PIC16TargetLowering::LegalizeCALL(SDValue Op, SelectionDAG &DAG) {
     CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
     SDValue Chain = TheCall->getChain();
     SDValue Callee = TheCall->getCallee();
     DebugLoc dl = TheCall->getDebugLoc();
     unsigned i =0;
-    if (Callee.getValueType() == MVT::i16 &&
-      Callee.getOpcode() == ISD::BUILD_PAIR) {
-      // It has come from TypeLegalizer for lowering
 
-      Callee = Callee.getOperand(0).getOperand(0);
+    assert(Callee.getValueType() == MVT::i16 &&
+           "Don't know how to legalize this call node!!!");
+    assert(Callee.getOpcode() == ISD::BUILD_PAIR &&
+           "Don't know how to legalize this call node!!!");
+
+    if (isDirectAddress(Callee)) {
+       // Come here for direct calls
+       Callee = Callee.getOperand(0).getOperand(0);
+    } else {
+      // Come here for indirect calls
+      SDValue Lo, Hi;
+      // Indirect addresses. Get the hi and lo parts of ptr.
+      GetExpandedParts(Callee, DAG, Lo, Hi);
+      // Connect Lo and Hi parts of the callee with the PIC16Connect
+      Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Lo, Hi);
+    }
+    std::vector<SDValue> Ops;
+    Ops.push_back(Chain);
+    Ops.push_back(Callee);
 
-      std::vector<SDValue> Ops;
-      Ops.push_back(Chain);
-      Ops.push_back(Callee);
-
-      // Add the call arguments and their flags
-      unsigned NumArgs = TheCall->getNumArgs();
-      for(i=0;i<NumArgs;i++) { 
-        Ops.push_back(TheCall->getArg(i));
-        Ops.push_back(TheCall->getArgFlagsVal(i));
-      }
+    // Add the call arguments and their flags
+    unsigned NumArgs = TheCall->getNumArgs();
+    for(i=0;i<NumArgs;i++) {
+       Ops.push_back(TheCall->getArg(i));
+       Ops.push_back(TheCall->getArgFlagsVal(i));
+    }
+    std::vector<MVT> NodeTys;
+    unsigned NumRets = TheCall->getNumRetVals();
+    for(i=0;i<NumRets;i++)
+       NodeTys.push_back(TheCall->getRetValType(i));
 
-      std::vector<MVT> NodeTys;
-      unsigned NumRets = TheCall->getNumRetVals();
-      for(i=0;i<NumRets;i++)
-        NodeTys.push_back(TheCall->getRetValType(i));
-
-      // Return a Chain as well
-      NodeTys.push_back(MVT::Other);
-
-      SDVTList VTs = DAG.getVTList(&NodeTys[0], NodeTys.size());
-      SDValue NewCall = 
-              DAG.getCall(TheCall->getCallingConv(), dl,
-                          TheCall->isVarArg(), TheCall->isTailCall(), 
-                          TheCall->isInreg(), VTs, &Ops[0], Ops.size());
+   // Return a Chain as well
+   NodeTys.push_back(MVT::Other);
+   
+   SDVTList VTs = DAG.getVTList(&NodeTys[0], NodeTys.size());
+   // Generate new call with all the operands legal
+   return DAG.getCall(TheCall->getCallingConv(), dl,
+                      TheCall->isVarArg(), TheCall->isTailCall(),
+                      TheCall->isInreg(), VTs, &Ops[0], Ops.size());
+}
+
+void PIC16TargetLowering::
+GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain, 
+               SDValue &DataAddr_Lo, SDValue &DataAddr_Hi,
+               SelectionDAG &DAG) {
+   assert (Callee.getOpcode() == PIC16ISD::PIC16Connect
+           && "Don't know what to do of such callee!!");
+   SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
+   SDValue SeqStart  = DAG.getCALLSEQ_START(Chain, ZeroOperand);
+   Chain = getChain(SeqStart);
+   SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
+
+   // Get the Lo and Hi part of code address
+   SDValue Lo = Callee.getOperand(0);
+   SDValue Hi = Callee.getOperand(1);
+
+   SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
+   Hi = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Hi);
+   // Use the Lo part as is and make CALLW
+   Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Lo, Hi);
+   SDValue Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee,
+                              OperFlag);
+   Chain = getChain(Call);
+   OperFlag = getOutFlag(Call);
+   SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
+                                       OperFlag);
+   Chain = getChain(SeqEnd);
+   OperFlag = getOutFlag(SeqEnd);
+
+   // Low part of Data Address 
+   DataAddr_Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Call, OperFlag);
+
+   // Make the second call.
+   SeqStart  = DAG.getCALLSEQ_START(Chain, ZeroOperand);
+   Chain = getChain(SeqStart);
+   OperFlag = getOutFlag(SeqStart); // To manage the data dependency
+
+   // Add 1 to Lo part for the second code word.
+   Lo = DAG.getNode(ISD::ADD, dl, MVT::i8, Lo, DAG.getConstant(1, MVT::i8));
+   // Use new Lo to make another CALLW
+   Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Lo, Hi);
+   Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee, OperFlag);
+   Chain = getChain(Call);
+   OperFlag = getOutFlag(Call);
+   SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
+                                        OperFlag);
+   Chain = getChain(SeqEnd);
+   OperFlag = getOutFlag(SeqEnd);
+   // Hi part of Data Address
+   DataAddr_Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Call, OperFlag);
+}
 
-      return NewCall;
+
+SDValue PIC16TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
+    CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
+    SDValue Chain = TheCall->getChain();
+    SDValue Callee = TheCall->getCallee();
+    DebugLoc dl = TheCall->getDebugLoc();
+    if (Callee.getValueType() == MVT::i16 &&
+      Callee.getOpcode() == ISD::BUILD_PAIR) {
+          // Control should come here only from TypeLegalizer for lowering
+          
+          // Legalize the non-legal arguments of call and return the
+          // new call with legal arguments.
+          return LegalizeCALL(Op, DAG);
     }
+    // Control should come here from Legalize DAG.
+    // Here all the operands of CALL node should be legal.
     
+    // If this is an indirect call then to pass the arguments
+    // and read the return value back, we need the data address
+    // of the function being called. 
+    // To get the data address two more calls need to be made.
+
+    // The flag to track if this is a direct or indirect call.
+    bool IsDirectCall = true;    
+    unsigned RetVals = TheCall->getNumRetVals();
+    unsigned NumArgs = TheCall->getNumArgs();
+
+    SDValue DataAddr_Lo, DataAddr_Hi; 
+    if (Callee.getOpcode() == PIC16ISD::PIC16Connect) { 
+       IsDirectCall = false;    // This is indirect call
+       // Read DataAddress only if we have to pass arguments or 
+       // read return value. 
+       if ((RetVals > 0) || (NumArgs > 0)) 
+         GetDataAddress(dl, Callee, Chain, DataAddr_Lo, DataAddr_Hi, DAG);
+    }
+
     SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
 
     // Start the call sequence.
@@ -1061,45 +1229,59 @@
     // because there is nothing else to carry.
     SDValue SeqStart  = DAG.getCALLSEQ_START(Chain, ZeroOperand);
     Chain = getChain(SeqStart);
+    SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
+    std::string Name;
 
     // For any direct call - callee will be GlobalAddressNode or
     // ExternalSymbol
-
-    // Considering the GlobalAddressNode case here.
-    if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
-      GlobalValue *GV = G->getGlobal();
-      Callee = DAG.getTargetGlobalAddress(GV, MVT::i8);
-    }
-
-    // Considering the ExternalSymbol case here
-    if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee)) {
-      Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8); 
-    }
-
-    SDValue OperFlag = getOutFlag(Chain); // To manage the data dependency
-
-    std::string Name;
-
-    // Considering GlobalAddress here
-    if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
-       Name = G->getGlobal()->getName();
-
-    // Considering ExternalSymbol here
-    if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee))
-       Name = ES->getSymbol();
-
-    char *argFrame = new char [strlen(Name.c_str()) +  8];
-    sprintf(argFrame, "%s.args", Name.c_str());
-    SDValue ArgLabel = DAG.getTargetExternalSymbol(argFrame, MVT::i8);
-
-    char *retName = new char [strlen(Name.c_str()) +  8];
-    sprintf(retName, "%s.retval", Name.c_str());
-    SDValue RetLabel = DAG.getTargetExternalSymbol(retName, MVT::i8);
+    SDValue ArgLabel, RetLabel;
+    if (IsDirectCall) { 
+       // Considering the GlobalAddressNode case here.
+       if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
+          GlobalValue *GV = G->getGlobal();
+          Callee = DAG.getTargetGlobalAddress(GV, MVT::i8);
+          Name = G->getGlobal()->getName();
+       } else {// Considering the ExternalSymbol case here
+          ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee);
+          Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8); 
+          Name = ES->getSymbol();
+       }
+
+       // Label for argument passing
+       char *argFrame = new char [strlen(Name.c_str()) +  8];
+       sprintf(argFrame, "%s.args", Name.c_str());
+       ArgLabel = DAG.getTargetExternalSymbol(argFrame, MVT::i8);
+
+       // Label for reading return value
+       char *retName = new char [strlen(Name.c_str()) +  8];
+       sprintf(retName, "%s.retval", Name.c_str());
+       RetLabel = DAG.getTargetExternalSymbol(retName, MVT::i8);
+    } else {
+       // if indirect call
+       SDValue CodeAddr_Lo = Callee.getOperand(0);
+       SDValue CodeAddr_Hi = Callee.getOperand(1);
+
+       CodeAddr_Lo = DAG.getNode(ISD::ADD, dl, MVT::i8, CodeAddr_Lo,
+                                 DAG.getConstant(2, MVT::i8));
+
+       // move Hi part in PCLATH
+       CodeAddr_Hi = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, CodeAddr_Hi);
+       Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, CodeAddr_Lo,
+                            CodeAddr_Hi);
+    } 
 
     // Pass the argument to function before making the call.
-    SDValue CallArgs = LowerCallArguments(Op, Chain, ArgLabel, OperFlag, DAG);
-    Chain = getChain(CallArgs);
-    OperFlag = getOutFlag(CallArgs);
+    SDValue CallArgs;
+    if (IsDirectCall) {
+      CallArgs = LowerDirectCallArguments(Op, Chain, ArgLabel, OperFlag, DAG);
+      Chain = getChain(CallArgs);
+      OperFlag = getOutFlag(CallArgs);
+    } else {
+      CallArgs = LowerIndirectCallArguments(Op, Chain, OperFlag, DataAddr_Lo, 
+                                            DataAddr_Hi, DAG);
+      Chain = getChain(CallArgs);
+      OperFlag = getOutFlag(CallArgs);
+    }
 
     SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
     SDValue PICCall = DAG.getNode(PIC16ISD::CALL, dl, Tys, Chain, Callee,
@@ -1116,7 +1298,11 @@
     OperFlag = getOutFlag(SeqEnd);
 
     // Lower the return value reading after the call.
-    return LowerCallReturn(Op, Chain, RetLabel, OperFlag, DAG);
+    if (IsDirectCall)
+      return LowerDirectCallReturn(Op, Chain, RetLabel, OperFlag, DAG);
+    else
+      return LowerIndirectCallReturn(Op, Chain, OperFlag, DataAddr_Lo,
+                                     DataAddr_Hi, DAG);
 }
 
 bool PIC16TargetLowering::isDirectLoad(const SDValue Op) {

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h?rev=68597&r1=68596&r2=68597&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h Wed Apr  8 00:38:48 2009
@@ -38,14 +38,17 @@
       PIC16Store,
       PIC16StWF,
       Banksel,
-      MTLO,
-      MTHI,
+      MTLO,          // Move to low part of FSR
+      MTHI,          // Move to high part of FSR
+      MTPCLATH,      // Move to PCLATCH
+      PIC16Connect,  // General connector for PIC16 nodes
       BCF,
       LSLF,          // PIC16 Logical shift left
       LRLF,          // PIC16 Logical shift right
       RLF,           // Rotate left through carry
       RRF,           // Rotate right through carry
       CALL,          // PIC16 Call instruction 
+      CALLW,         // PIC16 CALLW instruction 
       SUBCC,	     // Compare for equality or inequality.
       SELECT_ICC,    // Psuedo to be caught in schedular and expanded to brcond.
       BRCOND,        // Conditional branch.
@@ -87,10 +90,25 @@
     SDValue LowerBinOp(SDValue Op, SelectionDAG &DAG);
     SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
     SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
-    SDValue LowerCallReturn(SDValue Op, SDValue Chain, SDValue FrameAddress,
-                            SDValue InFlag, SelectionDAG &DAG);
-    SDValue LowerCallArguments(SDValue Op, SDValue Chain, SDValue FrameAddress,
-                               SDValue InFlag, SelectionDAG &DAG);
+    // Call returns
+    SDValue 
+    LowerDirectCallReturn(SDValue Op, SDValue Chain, SDValue FrameAddress, 
+                          SDValue InFlag, SelectionDAG &DAG);
+    SDValue 
+    LowerIndirectCallReturn(SDValue Op, SDValue Chain, SDValue InFlag,
+                            SDValue DataAddr_Lo, SDValue DataAddr_Hi,
+                            SelectionDAG &DAG);
+
+    // Call arguments
+    SDValue 
+    LowerDirectCallArguments(SDValue Op, SDValue Chain, SDValue FrameAddress, 
+                             SDValue InFlag, SelectionDAG &DAG);
+
+    SDValue 
+    LowerIndirectCallArguments(SDValue Op, SDValue Chain, SDValue InFlag, 
+                               SDValue DataAddr_Lo, SDValue DataAddr_Hi, 
+                               SelectionDAG &DAG);
+
     SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
     SDValue LowerStopPoint(SDValue Op, SelectionDAG &DAG);
@@ -152,6 +170,18 @@
     void LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG, SDValue &ES, 
                             int &Offset);
 
+    // CALL node should have all legal operands only. Legalize all non-legal
+    // operands of CALL node and then return the new call will all operands
+    // legal.
+    SDValue LegalizeCALL(SDValue Op, SelectionDAG &DAG);
+
+    // For indirect calls data address of the callee frame need to be
+    // extracted. This function fills the arguments DataAddr_Lo and 
+    // DataAddr_Hi with the address of the callee frame.
+    void GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain,
+                        SDValue &DataAddr_Lo, SDValue &DataAddr_Hi,
+                        SelectionDAG &DAG); 
+
     // We can not have both operands of a binary operation in W.
     // This function is used to put one operand on stack and generate a load.
     SDValue ConvertToMemOperand(SDValue Op, SelectionDAG &DAG, DebugLoc dl); 

Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td?rev=68597&r1=68596&r2=68597&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td Wed Apr  8 00:38:48 2009
@@ -42,8 +42,12 @@
 def SDT_PIC16Store : SDTypeProfile<0, 4, [SDTCisI8<0>, SDTCisI8<1>, 
                                           SDTCisI8<2>, SDTCisI8<3>]>;
 
+def SDT_PIC16Connect : SDTypeProfile<1, 2, [SDTCisI8<0>, SDTCisI8<1>,
+                                            SDTCisI8<2>]>;
+
 // PIC16ISD::CALL type prorile
 def SDT_PIC16call : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
+def SDT_PIC16callw : SDTypeProfile<1, -1, [SDTCisInt<0>]>;
 
 // PIC16ISD::BRCOND
 def SDT_PIC16Brcond: SDTypeProfile<0, 2, 
@@ -79,8 +83,9 @@
 // The MTHI and MTLO nodes are used only to match them in the incoming 
 // DAG for replacement by corresponding set_fsrhi, set_fsrlo insntructions.
 // These nodes are not used for defining any instructions.
-def MTLO : SDNode<"PIC16ISD::MTLO", SDTI8UnaryOp>;
-def MTHI : SDNode<"PIC16ISD::MTHI", SDTI8UnaryOp>;
+def MTLO     : SDNode<"PIC16ISD::MTLO", SDTI8UnaryOp>;
+def MTHI     : SDNode<"PIC16ISD::MTHI", SDTI8UnaryOp>;
+def MTPCLATH : SDNode<"PIC16ISD::MTPCLATH", SDTI8UnaryOp>;
 
 // Node to generate Bank Select for a GlobalAddress.
 def Banksel : SDNode<"PIC16ISD::Banksel", SDTI8UnaryOp>;
@@ -95,10 +100,13 @@
 def PIC16LdArg  : SDNode<"PIC16ISD::PIC16LdArg", SDT_PIC16Load, [SDNPHasChain]>;
 def PIC16LdWF  : SDNode<"PIC16ISD::PIC16LdWF", SDT_PIC16Load, 
                        [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
+def PIC16Connect: SDNode<"PIC16ISD::PIC16Connect", SDT_PIC16Connect, []>;
 
 // Node to match PIC16 call
 def PIC16call : SDNode<"PIC16ISD::CALL", SDT_PIC16call,
                               [SDNPHasChain , SDNPOptInFlag, SDNPOutFlag]>;
+def PIC16callw : SDNode<"PIC16ISD::CALLW", SDT_PIC16callw,
+                              [SDNPHasChain , SDNPOptInFlag, SDNPOutFlag]>;
 
 // Node to match a comparison instruction.
 def PIC16Subcc : SDNode<"PIC16ISD::SUBCC", SDTI8BinOp, [SDNPOutFlag]>;
@@ -213,6 +221,12 @@
              "movwf ${dst}H",
              []>;
 
+def set_pclath:
+  ByteFormat<0, (outs PCLATHR:$dst), 
+             (ins GPR:$val),
+             "movwf ${dst}",
+             [(set PCLATHR:$dst , (MTPCLATH GPR:$val))]>;
+
 //----------------------------
 // copyRegToReg 
 // copyRegToReg insns. These are dummy. They should always be deleted
@@ -392,10 +406,23 @@
 // Call instruction.
 let isCall = 1 in {
     def CALL: LiteralFormat<0x1, (outs), (ins i8imm:$func),
-            "call ${func}",
+            "call ${func} + 2",
             [(PIC16call diraddr:$func)]>;
 }
 
+let isCall = 1 in {
+    def CALL_1: LiteralFormat<0x1, (outs), (ins GPR:$func, PCLATHR:$pc),
+            "callw",
+            [(PIC16call (PIC16Connect GPR:$func, PCLATHR:$pc))]>;
+}
+
+let isCall = 1  in {
+    def CALLW: LiteralFormat<0x1, (outs GPR:$dest), 
+                                  (ins GPR:$func, PCLATHR:$pc),
+            "callw",
+            [(set GPR:$dest, (PIC16callw (PIC16Connect GPR:$func, PCLATHR:$pc)))]>;
+}
+
 let Uses = [STATUS] in
 def pic16brcond: ControlFormat<0x0, (outs), (ins brtarget:$dst, CCOp:$cc),
                           "b$cc $dst",
@@ -429,7 +456,7 @@
 // Return insn.
 def Return : 
   ControlFormat<0, (outs), (ins), "return", [(ret)]>;
-                      
+
 //===----------------------------------------------------------------------===//
 // PIC16 Replacment Patterns.
 //===----------------------------------------------------------------------===//
@@ -441,9 +468,20 @@
            (set_fsrhi (set_fsrlo GPR:$loaddr), GPR:$hiaddr),
            imm:$offset)>;
 
+def : Pat<(PIC16StWF GPR:$val, (MTLO GPR:$loaddr), (MTHI GPR:$hiaddr), 
+           imm:$offset),
+          (store_indirect GPR:$val, 
+           (set_fsrhi (set_fsrlo GPR:$loaddr), GPR:$hiaddr),
+           imm:$offset)>;
+
 // Identify an indirect load and select insns for it.
 def : Pat<(PIC16Load (MTLO GPR:$loaddr), (MTHI GPR:$hiaddr), 
            imm:$offset),
           (load_indirect  (set_fsrhi (set_fsrlo GPR:$loaddr), GPR:$hiaddr),
            imm:$offset)>;
 
+def : Pat<(PIC16LdWF (MTLO GPR:$loaddr), (MTHI GPR:$hiaddr), 
+           imm:$offset),
+          (load_indirect  (set_fsrhi (set_fsrlo GPR:$loaddr), GPR:$hiaddr),
+           imm:$offset)>;
+

Modified: llvm/trunk/lib/Target/PIC16/PIC16RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16RegisterInfo.td?rev=68597&r1=68596&r2=68597&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16RegisterInfo.td Wed Apr  8 00:38:48 2009
@@ -20,13 +20,14 @@
 def FSR0   : PIC16Reg<"FSR0">;
 def FSR1   : PIC16Reg<"FSR1">;
 def BS     : PIC16Reg<"BS">;
+def PCLATH : PIC16Reg<"PCLATH">;
 
 def STATUS : PIC16Reg<"STATUS">;
 
 // PIC16 Register classes.
-def GPR    : RegisterClass<"PIC16", [i8], 8, [W]>;
-def FSR16  : RegisterClass<"PIC16", [i16], 8, [FSR0, FSR1]>;
-def BSR  : RegisterClass<"PIC16", [i8], 8, [BS]>;
-
-def STATUSR: RegisterClass<"PIC16", [i8], 8, [STATUS]>;
+def GPR     : RegisterClass<"PIC16", [i8],  8, [W]>;
+def FSR16   : RegisterClass<"PIC16", [i16], 8, [FSR0, FSR1]>;
+def BSR     : RegisterClass<"PIC16", [i8],  8, [BS]>;
+def PCLATHR : RegisterClass<"PIC16", [i8],  8, [PCLATH]>;
+def STATUSR : RegisterClass<"PIC16", [i8],  8, [STATUS]>;
 




From sabre at nondot.org  Wed Apr  8 00:41:03 2009
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 08 Apr 2009 05:41:03 -0000
Subject: [llvm-commits] [llvm] r68598 - in /llvm/trunk:
 lib/Transforms/Scalar/InstructionCombining.cpp
 test/Transforms/InstCombine/2009-04-07-MulPromoteToI96.ll
Message-ID: <200904080541.n385f4qg015536@zion.cs.uiuc.edu>

Author: lattner
Date: Wed Apr  8 00:41:03 2009
New Revision: 68598

URL: http://llvm.org/viewvc/llvm-project?rev=68598&view=rev
Log:
Instcombine should not promote whole computation trees to "strange"
integer types, unless they are already strange.  This prevents it from
turning the code produced by SROA into crazy libcalls and stuff that 
the code generator can't handle.  In the attached example, the result
was an i96 multiply that caused the x86 backend to assert.

Note that if TargetData had an idea of what the legal types are for
a target that this could be used to stop instcombine from introducing
i64 muls, as Scott wanted.


Added:
    llvm/trunk/test/Transforms/InstCombine/2009-04-07-MulPromoteToI96.ll
Modified:
    llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=68598&r1=68597&r2=68598&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Wed Apr  8 00:41:03 2009
@@ -7927,6 +7927,22 @@
   return commonCastTransforms(CI);
 }
 
+/// isSafeIntegerType - Return true if this is a basic integer type, not a crazy
+/// type like i42.  We don't want to introduce operations on random non-legal
+/// integer types where they don't already exist in the code.  In the future,
+/// we should consider making this based off target-data, so that 32-bit targets
+/// won't get i64 operations etc.
+static bool isSafeIntegerType(const Type *Ty) {
+  switch (Ty->getPrimitiveSizeInBits()) {
+  case 8:
+  case 16:
+  case 32:
+  case 64:
+    return true;
+  default: 
+    return false;
+  }
+}
 
 /// Only the TRUNC, ZEXT, SEXT, and BITCAST can both operand and result as
 /// integer types. This function implements the common transforms for all those
@@ -7956,6 +7972,10 @@
   // Attempt to propagate the cast into the instruction for int->int casts.
   int NumCastsRemoved = 0;
   if (!isa<BitCastInst>(CI) &&
+      // Only do this if the dest type is a simple type, don't convert the
+      // expression tree to something weird like i93 unless the source is also
+      // strange.
+      (isSafeIntegerType(DestTy) || !isSafeIntegerType(SrcI->getType())) &&
       CanEvaluateInDifferentType(SrcI, cast<IntegerType>(DestTy),
                                  CI.getOpcode(), NumCastsRemoved)) {
     // If this cast is a truncate, evaluting in a different type always

Added: llvm/trunk/test/Transforms/InstCombine/2009-04-07-MulPromoteToI96.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2009-04-07-MulPromoteToI96.ll?rev=68598&view=auto

==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/2009-04-07-MulPromoteToI96.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/2009-04-07-MulPromoteToI96.ll Wed Apr  8 00:41:03 2009
@@ -0,0 +1,13 @@
+; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep {mul i64}
+; rdar://6762288
+
+; Instcombine should not promote the mul to i96 because it is definitely
+; not a legal type for the target, and we don't want a libcall.
+
+define i96 @test(i96 %a.4, i96 %b.2) {
+	%tmp1086 = trunc i96 %a.4 to i64		; <i64> [#uses=1]
+	%tmp836 = trunc i96 %b.2 to i64		; <i64> [#uses=1]
+	%mul185 = mul i64 %tmp1086, %tmp836		; <i64> [#uses=1]
+	%tmp544 = zext i64 %mul185 to i96		; <i96> [#uses=1]
+	ret i96 %tmp544
+}




From sanjiv.gupta at microchip.com  Wed Apr  8 01:24:04 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Wed, 08 Apr 2009 06:24:04 -0000
Subject: [llvm-commits] [llvm] r68602 - in /llvm/trunk/lib/Target/PIC16:
 PIC16AsmPrinter.cpp PIC16ISelLowering.cpp PIC16ISelLowering.h
 PIC16InstrInfo.td PIC16TargetAsmInfo.cpp
Message-ID: <200904080624.n386O5qe017241@zion.cs.uiuc.edu>

Author: sgupta
Date: Wed Apr  8 01:24:04 2009
New Revision: 68602

URL: http://llvm.org/viewvc/llvm-project?rev=68602&view=rev
Log:
Emit .line debug directives for stoppoints. The debug location is retrieved by the MachineInstr itself, rather than by custom handling the DBG_STOPPOINT nodes.

Modified:
    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h
    llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td
    llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.cpp

Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=68602&r1=68601&r2=68602&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Wed Apr  8 01:24:04 2009
@@ -113,6 +113,8 @@
                                                SectionFlags::Code);
   O <<  "\n";
   SwitchToSection (fCodeSection);
+
+  // Emit the frame address of the function at the beginning of code.
   O << CurrentFnName << ":\n";
   O << "    retlw  low(" << CurrentFnName << ".frame)\n";
   O << "    retlw  high(" << CurrentFnName << ".frame)\n"; 
@@ -127,10 +129,23 @@
       O << '\n';
     }
     CurBank = "";
+    
+    // For emitting line directives, we need to keep track of the current
+    // source line. When it changes then only emit the line directive.
+    unsigned CurLine = 0;
     for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
          II != E; ++II) {
+      // Emit the line directive if source line changed.
+      const DebugLoc DL = II->getDebugLoc();
+      if (!DL.isUnknown()) {
+        unsigned line = MF.getDebugLocTuple(DL).Line;
+        if (line != CurLine) {
+          O << "\t.line " << line << "\n";
+          CurLine = line;
+        }
+      }
       // Print the assembly for the instruction.
-        printMachineInstruction(II);
+      printMachineInstruction(II);
     }
   }
   return false;  // we didn't modify anything.

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=68602&r1=68601&r2=68602&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Wed Apr  8 01:24:04 2009
@@ -137,8 +137,6 @@
   //setOperationAction(ISD::TRUNCATE, MVT::i16, Custom);
   setTruncStoreAction(MVT::i16,   MVT::i8,  Custom);
 
-  setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Custom);
-
   // Now deduce the information based on the above mentioned 
   // actions
   computeRegisterProperties();
@@ -274,7 +272,6 @@
   case PIC16ISD::SELECT_ICC:       return "PIC16ISD::SELECT_ICC";
   case PIC16ISD::BRCOND:           return "PIC16ISD::BRCOND";
   case PIC16ISD::Dummy:            return "PIC16ISD::Dummy";
-  case PIC16ISD::PIC16StopPoint:   return "PIC16ISD::PIC16StopPoint";
   }
 }
 
@@ -825,21 +822,10 @@
       return LowerBR_CC(Op, DAG);
     case ISD::SELECT_CC:
       return LowerSELECT_CC(Op, DAG);
-    case ISD::DBG_STOPPOINT:
-      return LowerStopPoint(Op, DAG);
   }
   return SDValue();
 }
 
-SDValue PIC16TargetLowering::LowerStopPoint(SDValue Op, SelectionDAG &DAG) {
-  DbgStopPointSDNode *SP = dyn_cast<DbgStopPointSDNode>(Op);
-  unsigned line = SP->getLine();
-  SDValue LineNode = DAG.getConstant(line, MVT::i8);
-  DebugLoc dl = Op.getDebugLoc();
-  return DAG.getNode(PIC16ISD::PIC16StopPoint, dl, MVT::Other, 
-                     Op.getOperand(0), LineNode);
-}
-
 SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op,
                                                  SelectionDAG &DAG,
                                                  DebugLoc dl) {

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h?rev=68602&r1=68601&r2=68602&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h Wed Apr  8 01:24:04 2009
@@ -52,7 +52,6 @@
       SUBCC,	     // Compare for equality or inequality.
       SELECT_ICC,    // Psuedo to be caught in schedular and expanded to brcond.
       BRCOND,        // Conditional branch.
-      PIC16StopPoint,
       Dummy
     };
 
@@ -111,7 +110,6 @@
 
     SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
-    SDValue LowerStopPoint(SDValue Op, SelectionDAG &DAG);
     SDValue getPIC16Cmp(SDValue LHS, SDValue RHS, unsigned OrigCC, SDValue &CC,
                         SelectionDAG &DAG, DebugLoc dl);
     virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,

Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td?rev=68602&r1=68601&r2=68602&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td Wed Apr  8 01:24:04 2009
@@ -71,9 +71,6 @@
 def PIC16callseq_end   : SDNode<"ISD::CALLSEQ_END", SDTI8VoidOp, 
                                 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
 
-def PIC16StopPoint : SDNode<"PIC16ISD::PIC16StopPoint", SDTI8VoidOp,
-                             [SDNPHasChain]>;
-
 // Low 8-bits of GlobalAddress.
 def PIC16Lo : SDNode<"PIC16ISD::Lo", SDTI8UnaryOp>;  
 
@@ -171,10 +168,6 @@
 // PIC16 Instructions.
 //===----------------------------------------------------------------------===//
 
-def line_directive : ByteFormat<0, (outs), (ins i8imm:$src),
-                               ".line $src",
-                               [(PIC16StopPoint (i8 imm:$src))]>;
-
 // Pseudo-instructions.
 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i8imm:$amt),
                        "!ADJCALLSTACKDOWN $amt",

Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.cpp?rev=68602&r1=68601&r2=68602&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16TargetAsmInfo.cpp Wed Apr  8 01:24:04 2009
@@ -35,6 +35,9 @@
   ReadOnlySection = getNamedSection("romdata.# ROMDATA", SectionFlags::None);
   DataSection = getNamedSection("idata.# IDATA", SectionFlags::Writeable);
   SwitchToSectionDirective = "";
+  // Need because otherwise a .text symbol is emitted by DwarfWriter
+  // in BeginModule, and gpasm cribbs for that .text symbol.
+  TextSection = getUnnamedSection("", SectionFlags::Code);
 }
 
 const char *PIC16TargetAsmInfo::getRomDirective(unsigned size) const




From sanjiv.gupta at microchip.com  Wed Apr  8 01:50:37 2009
From: sanjiv.gupta at microchip.com (sanjiv gupta)
Date: Wed, 08 Apr 2009 12:20:37 +0530
Subject: [llvm-commits] [llvm] r68576 - in
	/llvm/trunk:	include/llvm/Target/ lib/CodeGen/
	lib/CodeGen/SelectionDAG/ lib/Target/X86/	test/CodeGen/X86/
In-Reply-To: <200904080015.n380FVD1002889@zion.cs.uiuc.edu>
References: <200904080015.n380FVD1002889@zion.cs.uiuc.edu>
Message-ID: <1239173437.9086.5.camel@idc-lt-i00171.microchip.com>

On Wed, 2009-04-08 at 00:15 +0000, Dan Gohman wrote:

> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=68576&r1=68575&r2=68576&view=diff
> 
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Apr  7 19:15:30 2009
> @@ -777,6 +777,48 @@
>    return false;
>  }
>  
> +/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
> +/// casts are free.  This uses isZExtFree and ZERO_EXTEND for the widening
> +/// cast, but it could be generalized for targets with other types of
> +/// implicit widening casts.
> +bool
> +TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
> +                                                    unsigned BitWidth,
> +                                                    const APInt &Demanded,
> +                                                    DebugLoc dl) {
> +  assert(Op.getNumOperands() == 2 &&
> +         "ShrinkDemandedOp only supports binary operators!");

> +  assert(Op.getNode()->getNumValues() == 1 &&
> +         "ShrinkDemandedOp only supports nodes with one result!");
> +
This assert breaks via visitADD, when the ADD operation also produces a
carry, so Op.getNode()->getNumValues() is 2 there.

-Sanjiv




From baldrick at free.fr  Wed Apr  8 02:47:30 2009
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 8 Apr 2009 09:47:30 +0200
Subject: [llvm-commits] Type::getPointerTo()
In-Reply-To: <5be2d90904070700n6709afd7t1a6e8c08c3ef7361@mail.gmail.com>
References: <5be2d90904070700n6709afd7t1a6e8c08c3ef7361@mail.gmail.com>
Message-ID: <200904080947.30755.baldrick@free.fr>

Hi Anders,

> I'd like to suggest this patch which adds a getPointerTo() method to llvm::Type.
> 
> This will allow the following code:
> 
> myType->getPointerTo(0);  (1)
> 
> that is 100% identical to
> 
> llvm::PointerType::get(myType, 0);   (2)
> 
> My motivation for the patch is that my code is full of (2) and it's
> getting somewhat ugly.

this looks good to me.  If Chris doesn't complain in the
next 24 hours, I suggest you apply it :)

Ciao,

Duncan.


From rafael.espindola at gmail.com  Wed Apr  8 03:09:43 2009
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 08 Apr 2009 08:09:43 -0000
Subject: [llvm-commits] [llvm] r68603 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <200904080809.n3889jlj028409@zion.cs.uiuc.edu>

Author: rafael
Date: Wed Apr  8 03:09:33 2009
New Revision: 68603

URL: http://llvm.org/viewvc/llvm-project?rev=68603&view=rev
Log:
Avoid a hard coded constant.


Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=68603&r1=68602&r2=68603&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Apr  8 03:09:33 2009
@@ -7800,7 +7800,7 @@
       AM.Disp = Op.getImm();
     }
     addFullAddress(BuildMI(BB, dl, TII->get(Opc)), AM)
-                      .addReg(MI->getOperand(4).getReg());
+                      .addReg(MI->getOperand(X86AddrNumOperands).getReg());
 
     // Reload the original control word now.
     addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);




From espindola at google.com  Wed Apr  8 03:13:35 2009
From: espindola at google.com (Rafael Espindola)
Date: Wed, 8 Apr 2009 09:13:35 +0100
Subject: [llvm-commits] [llvm] r68552 - in /llvm/trunk: lib/Target/X86/
	lib/Target/X86/AsmPrinter/ test/CodeGen/X86/
In-Reply-To: <16e5fdf90904071517r30afc273o26a0f3ffa1662194@mail.gmail.com>
References: <200904072137.n37Lbll0029223@zion.cs.uiuc.edu>
	<16e5fdf90904071517r30afc273o26a0f3ffa1662194@mail.gmail.com>
Message-ID: <38a0d8450904080113v2f63dcd6g9bf1fbb01f96219f@mail.gmail.com>

2009/4/7 Bill Wendling <isanbard at gmail.com>:
> Rafael,
>
> This is causing a self-hosting LLVM to fail to build:

Sorry about that. I just fixed a problem (revision 68603) that might
be related to that.

How do you build self-hosting? Just bootstrap llvm-gcc and use that to
bulid llvm?

Cheers,
-- 
Rafael Avila de Espindola

Google | Gordon House | Barrow Street | Dublin 4 | Ireland
Registered in Dublin, Ireland | Registration Number: 368047


From baldrick at free.fr  Wed Apr  8 03:18:56 2009
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 8 Apr 2009 10:18:56 +0200
Subject: [llvm-commits] [llvm] r68455 - /llvm/trunk/Makefile.rules
In-Reply-To: <45AFC928-ABB7-4CF5-890C-DB614B8E0604@apple.com>
References: <200904061958.n36JwC1F016795@zion.cs.uiuc.edu>
	<200904070959.00884.baldrick@free.fr>
	<45AFC928-ABB7-4CF5-890C-DB614B8E0604@apple.com>
Message-ID: <200904081018.57042.baldrick@free.fr>

Hi Chris,

> >> Avoid -O3 on Darwin for now.
> >
> > is this really a Darwin issue?  If it's not clear,
> > how about using -O2 on all platforms?  People using
> > FC8 have regularly been reporting miscompilations of
> > llvm-2.5 when building with optimization for example.
> > So perhaps this is a more general problem.
> 
> I would be supportive of using -O2 everywhere, but this will  
> significantly impact our compile times (llvm will compile slower).

did you measure this?  Since Darwin just switched from -O3
to -O2 I guess the impact should now be clear for Darwin users.
Is it really significant?

Ciao,

Duncan.


From baldrick at free.fr  Wed Apr  8 08:33:42 2009
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 08 Apr 2009 13:33:42 -0000
Subject: [llvm-commits] [llvm] r68607 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
 lib/CodeGen/SelectionDAG/LegalizeTypes.h
 test/CodeGen/ARM/2009-04-08-FloatUndef.ll
Message-ID: <200904081333.n38DXhAQ012453@zion.cs.uiuc.edu>

Author: baldrick
Date: Wed Apr  8 08:33:37 2009
New Revision: 68607

URL: http://llvm.org/viewvc/llvm-project?rev=68607&view=rev
Log:
Soft float support for undef.  Reported by Xerxes R?nby.

Added:
    llvm/trunk/test/CodeGen/ARM/2009-04-08-FloatUndef.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=68607&r1=68606&r2=68607&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Wed Apr  8 08:33:37 2009
@@ -90,6 +90,7 @@
     case ISD::SELECT_CC:   R = SoftenFloatRes_SELECT_CC(N); break;
     case ISD::SINT_TO_FP:
     case ISD::UINT_TO_FP:  R = SoftenFloatRes_XINT_TO_FP(N); break;
+    case ISD::UNDEF:       R = SoftenFloatRes_UNDEF(N); break;
     case ISD::VAARG:       R = SoftenFloatRes_VAARG(N); break;
   }
 
@@ -464,6 +465,10 @@
                      N->getOperand(1), LHS, RHS, N->getOperand(4));
 }
 
+SDValue DAGTypeLegalizer::SoftenFloatRes_UNDEF(SDNode *N) {
+  return DAG.getUNDEF(TLI.getTypeToTransformTo(N->getValueType(0)));
+}
+
 SDValue DAGTypeLegalizer::SoftenFloatRes_VAARG(SDNode *N) {
   SDValue Chain = N->getOperand(0); // Get the chain.
   SDValue Ptr = N->getOperand(1); // Get the pointer.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=68607&r1=68606&r2=68607&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Wed Apr  8 08:33:37 2009
@@ -422,6 +422,7 @@
   SDValue SoftenFloatRes_LOAD(SDNode *N);
   SDValue SoftenFloatRes_SELECT(SDNode *N);
   SDValue SoftenFloatRes_SELECT_CC(SDNode *N);
+  SDValue SoftenFloatRes_UNDEF(SDNode *N);
   SDValue SoftenFloatRes_VAARG(SDNode *N);
   SDValue SoftenFloatRes_XINT_TO_FP(SDNode *N);
 

Added: llvm/trunk/test/CodeGen/ARM/2009-04-08-FloatUndef.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-04-08-FloatUndef.ll?rev=68607&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-04-08-FloatUndef.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2009-04-08-FloatUndef.ll Wed Apr  8 08:33:37 2009
@@ -0,0 +1,11 @@
+; RUN: llvm-as < %s | llc -march=arm
+
+define void @execute_shader(<4 x float>* %OUT, <4 x float>* %IN, <4 x float>* %CONST) {
+entry:
+	%input2 = load <4 x float>* null, align 16		; <<4 x float>> [#uses=2]
+	%shuffle7 = shufflevector <4 x float> %input2, <4 x float> <float 0.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00>, <4 x i32> <i32 2, i32 2, i32 2, i32 2>		; <<4 x float>> [#uses=1]
+	%mul1 = mul <4 x float> %shuffle7, zeroinitializer		; <<4 x float>> [#uses=1]
+	%add2 = add <4 x float> %mul1, %input2		; <<4 x float>> [#uses=1]
+	store <4 x float> %add2, <4 x float>* null, align 16
+	ret void
+}




From dgregor at apple.com  Wed Apr  8 10:18:22 2009
From: dgregor at apple.com (Douglas Gregor)
Date: Wed, 08 Apr 2009 15:18:22 -0000
Subject: [llvm-commits] [llvm] r68610 -
	/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
Message-ID: <200904081518.n38FIMr8016539@zion.cs.uiuc.edu>

Author: dgregor
Date: Wed Apr  8 10:18:21 2009
New Revision: 68610

URL: http://llvm.org/viewvc/llvm-project?rev=68610&view=rev
Log:
Add BitstreamWriter::GetCurrentBitNo, to report where we are in the output bitstream

Modified:
    llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h

Modified: llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h?rev=68610&r1=68609&r2=68610&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h (original)
+++ llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h Wed Apr  8 10:18:21 2009
@@ -79,6 +79,9 @@
 
   std::vector<unsigned char> &getBuffer() { return Out; }
 
+  /// \brief Retrieve the current position in the stream, in bits.
+  uint64_t GetCurrentBitNo() const { return Out.size() * CHAR_BIT + CurBit; }
+
   //===--------------------------------------------------------------------===//
   // Basic Primitives for emitting bits to the stream.
   //===--------------------------------------------------------------------===//




From stoklund at 2pi.dk  Wed Apr  8 10:47:21 2009
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 8 Apr 2009 17:47:21 +0200
Subject: [llvm-commits] [PATCH] Fix simple crashing bug in
	MachineInstr::getNumExplicitOperands
Message-ID: <C091F0DE-9445-42D1-A412-E89B3DEC574B@2pi.dk>

MachineInstr::getNumExplicitOperands was tripping asserts in  
getOperand. Looking at the code, it it obvious why.

Note: The attached fix assumes that all implicit machine instruction  
operands follow the explicit operands. Is that always true?

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From brukman+llvm at gmail.com  Wed Apr  8 11:17:24 2009
From: brukman+llvm at gmail.com (Misha Brukman)
Date: Wed, 08 Apr 2009 16:17:24 -0000
Subject: [llvm-commits] [llvm] r68613 -
	/llvm/trunk/unittests/ADT/APIntTest.cpp
Message-ID: <200904081617.n38GHOLh018846@zion.cs.uiuc.edu>

Author: brukman
Date: Wed Apr  8 11:17:23 2009
New Revision: 68613

URL: http://llvm.org/viewvc/llvm-project?rev=68613&view=rev
Log:
* Fixed calls to APInt ctor to work for negative values on Darwin/x86
* Converted C-style casts to C++-style casts


Modified:
    llvm/trunk/unittests/ADT/APIntTest.cpp

Modified: llvm/trunk/unittests/ADT/APIntTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/APIntTest.cpp?rev=68613&r1=68612&r2=68613&view=diff

==============================================================================
--- llvm/trunk/unittests/ADT/APIntTest.cpp (original)
+++ llvm/trunk/unittests/ADT/APIntTest.cpp Wed Apr  8 11:17:23 2009
@@ -39,11 +39,11 @@
 }
 
 TEST(APIntTest, i128_NegativeCount) {
-  APInt Minus3(128, (uint64_t)-3, true);
+  APInt Minus3(128, static_cast<uint64_t>(-3), true);
   EXPECT_EQ(126u, Minus3.countLeadingOnes());
   EXPECT_EQ(-3, Minus3.getSExtValue());
 
-  APInt Minus1(128, (uint64_t)-1, true);
+  APInt Minus1(128, static_cast<uint64_t>(-1), true);
   EXPECT_EQ(0u, Minus1.countLeadingZeros());
   EXPECT_EQ(128u, Minus1.countLeadingOnes());
   EXPECT_EQ(128u, Minus1.getActiveBits());
@@ -54,7 +54,7 @@
 }
 
 TEST(APIntTest, i33_Count) {
-  APInt i33minus2(33, -2, true);
+  APInt i33minus2(33, static_cast<uint64_t>(-2), true);
   EXPECT_EQ(0u, i33minus2.countLeadingZeros());
   EXPECT_EQ(32u, i33minus2.countLeadingOnes());
   EXPECT_EQ(33u, i33minus2.getActiveBits());
@@ -83,7 +83,7 @@
   EXPECT_EQ(128u, u128max.countTrailingOnes());
   EXPECT_EQ(128u, u128max.countPopulation());
 
-  APInt u64max(128, (uint64_t)-1, false);
+  APInt u64max(128, static_cast<uint64_t>(-1), false);
   EXPECT_EQ(64u, u64max.countLeadingZeros());
   EXPECT_EQ(0u, u64max.countLeadingOnes());
   EXPECT_EQ(64u, u64max.getActiveBits());
@@ -114,8 +114,8 @@
 }
 
 TEST(APIntTest, i1) {
-  const APInt neg_two(1, -2, true);
-  const APInt neg_one(1, -1, true);
+  const APInt neg_two(1, static_cast<uint64_t>(-2), true);
+  const APInt neg_one(1, static_cast<uint64_t>(-1), true);
   const APInt zero(1, 0);
   const APInt one(1, 1);
   const APInt two(1, 2);




From baldrick at free.fr  Wed Apr  8 11:20:57 2009
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 08 Apr 2009 16:20:57 -0000
Subject: [llvm-commits] [llvm] r68614 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
 lib/CodeGen/SelectionDAG/LegalizeTypes.h
 test/CodeGen/ARM/2009-04-08-FREM.ll
Message-ID: <200904081620.n38GKvqe019004@zion.cs.uiuc.edu>

Author: baldrick
Date: Wed Apr  8 11:20:57 2009
New Revision: 68614

URL: http://llvm.org/viewvc/llvm-project?rev=68614&view=rev
Log:
Soft float support for FREM.

Added:
    llvm/trunk/test/CodeGen/ARM/2009-04-08-FREM.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=68614&r1=68613&r2=68614&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Wed Apr  8 11:20:57 2009
@@ -80,6 +80,7 @@
     case ISD::FP_ROUND:    R = SoftenFloatRes_FP_ROUND(N); break;
     case ISD::FPOW:        R = SoftenFloatRes_FPOW(N); break;
     case ISD::FPOWI:       R = SoftenFloatRes_FPOWI(N); break;
+    case ISD::FREM:        R = SoftenFloatRes_FREM(N); break;
     case ISD::FRINT:       R = SoftenFloatRes_FRINT(N); break;
     case ISD::FSIN:        R = SoftenFloatRes_FSIN(N); break;
     case ISD::FSQRT:       R = SoftenFloatRes_FSQRT(N); break;
@@ -363,6 +364,18 @@
                      NVT, Ops, 2, false, N->getDebugLoc());
 }
 
+SDValue DAGTypeLegalizer::SoftenFloatRes_FREM(SDNode *N) {
+  MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
+                     GetSoftenedFloat(N->getOperand(1)) };
+  return MakeLibCall(GetFPLibCall(N->getValueType(0),
+                                  RTLIB::REM_F32,
+                                  RTLIB::REM_F64,
+                                  RTLIB::REM_F80,
+                                  RTLIB::REM_PPCF128),
+                     NVT, Ops, 2, false, N->getDebugLoc());
+}
+
 SDValue DAGTypeLegalizer::SoftenFloatRes_FRINT(SDNode *N) {
   MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
   SDValue Op = GetSoftenedFloat(N->getOperand(0));

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=68614&r1=68613&r2=68614&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Wed Apr  8 11:20:57 2009
@@ -414,6 +414,7 @@
   SDValue SoftenFloatRes_FP_ROUND(SDNode *N);
   SDValue SoftenFloatRes_FPOW(SDNode *N);
   SDValue SoftenFloatRes_FPOWI(SDNode *N);
+  SDValue SoftenFloatRes_FREM(SDNode *N);
   SDValue SoftenFloatRes_FRINT(SDNode *N);
   SDValue SoftenFloatRes_FSIN(SDNode *N);
   SDValue SoftenFloatRes_FSQRT(SDNode *N);

Added: llvm/trunk/test/CodeGen/ARM/2009-04-08-FREM.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-04-08-FREM.ll?rev=68614&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-04-08-FREM.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2009-04-08-FREM.ll Wed Apr  8 11:20:57 2009
@@ -0,0 +1,9 @@
+; RUN: llvm-as < %s | llc -march=arm
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main() {
+	%rem_r = frem double 0.000000e+00, 0.000000e+00		; <double> [#uses=1]
+	%1 = call i32 (i8*, ...)* @printf(i8* null, double %rem_r)		; <i32> [#uses=0]
+	ret i32 0
+}




From gohman at apple.com  Wed Apr  8 11:22:38 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 8 Apr 2009 09:22:38 -0700
Subject: [llvm-commits] [llvm] r68576 - in /llvm/trunk:
	include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/
	lib/Target/X86/ test/CodeGen/X86/
In-Reply-To: <1239173437.9086.5.camel@idc-lt-i00171.microchip.com>
References: <200904080015.n380FVD1002889@zion.cs.uiuc.edu>
	<1239173437.9086.5.camel@idc-lt-i00171.microchip.com>
Message-ID: <3394DD7B-46BB-42D1-9D1A-BFCEBD22DC4D@apple.com>


On Apr 7, 2009, at 11:50 PM, sanjiv gupta wrote:

> On Wed, 2009-04-08 at 00:15 +0000, Dan Gohman wrote:
>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=68576&r1=68575&r2=68576&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Apr   
>> 7 19:15:30 2009
>> @@ -777,6 +777,48 @@
>>   return false;
>> }
>>
>> +/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y)  
>> if the
>> +/// casts are free.  This uses isZExtFree and ZERO_EXTEND for the  
>> widening
>> +/// cast, but it could be generalized for targets with other types  
>> of
>> +/// implicit widening casts.
>> +bool
>> +TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
>> +                                                    unsigned  
>> BitWidth,
>> +                                                    const APInt  
>> &Demanded,
>> +                                                    DebugLoc dl) {
>> +  assert(Op.getNumOperands() == 2 &&
>> +         "ShrinkDemandedOp only supports binary operators!");
>
>> +  assert(Op.getNode()->getNumValues() == 1 &&
>> +         "ShrinkDemandedOp only supports nodes with one result!");
>> +
> This assert breaks via visitADD, when the ADD operation also  
> produces a
> carry, so Op.getNode()->getNumValues() is 2 there.

ADD always has one result. ADDC and UADDO are used to represent an add
with a carry result.

Dan



From brukman at gmail.com  Wed Apr  8 11:31:26 2009
From: brukman at gmail.com (Misha Brukman)
Date: Wed, 8 Apr 2009 12:31:26 -0400
Subject: [llvm-commits] [PATCH] Correctly specify dependencies for "make
	check" and "make unittests"
Message-ID: <f88b89a50904080931t3c51e1aby11d858b314e648fe@mail.gmail.com>

Currently, out of the box, if one were to do:

% mkdir build; cd build
% ~/llvm/configure [...]
% make check

This would break (or rather, the tests would all fail) because none of the
tools have been built.  Similarly, even if you change some code, and then
re-run "make check" the tools will not be rebuilt, so unless you always
remember to run "make tools-only; make check", you might be testing an older
version of your code.

Same thing happens for unittests, except they just need the libraries, so
unless "make unittests" is preceded by "make libs-only", the same errors as
above will occur.

The attached patch fixes that, and was tested on both Linux/x86_64 and
Darwin/x86.  I'm not sure why this wasn't already done previously, so I'm
asking the Makefile gurus if it's safe to commit this, or if there are any
known issues that this patch will trigger.

Misha
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From pgurd at rapidmind.com  Wed Apr  8 11:42:11 2009
From: pgurd at rapidmind.com (Preston Gurd)
Date: Wed, 8 Apr 2009 12:42:11 -0400
Subject: [llvm-commits] [llvm] r68610 -
 /llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
In-Reply-To: <200904081518.n38FIMr8016539@zion.cs.uiuc.edu>
References: <200904081518.n38FIMr8016539@zion.cs.uiuc.edu>
Message-ID: <1239208931.6077.19.camel@remington>

This patch breaks my build, because CHAR_BIT is undefined.

Surely the patch must also add an include of <limits.h> to obtain the
definition of CHAR_BIT?



On Wed, 2009-04-08 at 11:18 -0400, Douglas Gregor wrote:
> Author: dgregor
> Date: Wed Apr  8 10:18:21 2009
> New Revision: 68610
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=68610&view=rev
> Log:
> Add BitstreamWriter::GetCurrentBitNo, to report where we are in the output bitstream
> 
> Modified:
>     llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
> 
> Modified: llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h?rev=68610&r1=68609&r2=68610&view=diff
> 
> ==============================================================================
> --- llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h (original)
> +++ llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h Wed Apr  8 10:18:21 2009
> @@ -79,6 +79,9 @@
> 
>    std::vector<unsigned char> &getBuffer() { return Out; }
> 
> +  /// \brief Retrieve the current position in the stream, in bits.
> +  uint64_t GetCurrentBitNo() const { return Out.size() * CHAR_BIT + CurBit; }
> +
>    //===--------------------------------------------------------------------===//
>    // Basic Primitives for emitting bits to the stream.
>    //===--------------------------------------------------------------------===//
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From clattner at apple.com  Wed Apr  8 11:51:07 2009
From: clattner at apple.com (Chris Lattner)
Date: Wed, 8 Apr 2009 09:51:07 -0700
Subject: [llvm-commits] [llvm] r68455 - /llvm/trunk/Makefile.rules
In-Reply-To: <200904081018.57042.baldrick@free.fr>
References: <200904061958.n36JwC1F016795@zion.cs.uiuc.edu>
	<200904070959.00884.baldrick@free.fr>
	<45AFC928-ABB7-4CF5-890C-DB614B8E0604@apple.com>
	<200904081018.57042.baldrick@free.fr>
Message-ID: <B1D83E08-8B4D-43E9-9FDF-620BD0C09D04@apple.com>

On Apr 8, 2009, at 1:18 AM, Duncan Sands wrote:
> Hi Chris,
>>>> Avoid -O3 on Darwin for now.
>>>
>>> is this really a Darwin issue?  If it's not clear,
>>> how about using -O2 on all platforms?  People using
>>> FC8 have regularly been reporting miscompilations of
>>> llvm-2.5 when building with optimization for example.
>>> So perhaps this is a more general problem.
>>
>> I would be supportive of using -O2 everywhere, but this will
>> significantly impact our compile times (llvm will compile slower).
>
> did you measure this?  Since Darwin just switched from -O3
> to -O2 I guess the impact should now be clear for Darwin users.
> Is it really significant?

No.  We plan/hope to switch back to -O3 after we shake the bugs out of  
our GCC.

-Chris


From clattner at apple.com  Wed Apr  8 11:52:45 2009
From: clattner at apple.com (Chris Lattner)
Date: Wed, 8 Apr 2009 09:52:45 -0700
Subject: [llvm-commits] [llvm] r68610 -
	/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
In-Reply-To: <1239208931.6077.19.camel@remington>
References: <200904081518.n38FIMr8016539@zion.cs.uiuc.edu>
	<1239208931.6077.19.camel@remington>
Message-ID: <30AD0ED4-B2BB-4864-99A8-950CF009A559@apple.com>

Doug, can you just use 8 instead of CHAR_BIT?

On Apr 8, 2009, at 9:42 AM, Preston Gurd wrote:

> This patch breaks my build, because CHAR_BIT is undefined.
>
> Surely the patch must also add an include of <limits.h> to obtain the
> definition of CHAR_BIT?
>
>
>
> On Wed, 2009-04-08 at 11:18 -0400, Douglas Gregor wrote:
>> Author: dgregor
>> Date: Wed Apr  8 10:18:21 2009
>> New Revision: 68610
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=68610&view=rev
>> Log:
>> Add BitstreamWriter::GetCurrentBitNo, to report where we are in the  
>> output bitstream
>>
>> Modified:
>>    llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
>>
>> Modified: llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h?rev=68610&r1=68609&r2=68610&view=diff
>>
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> =====================================================================
>> --- llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h (original)
>> +++ llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h Wed Apr  8  
>> 10:18:21 2009
>> @@ -79,6 +79,9 @@
>>
>>   std::vector<unsigned char> &getBuffer() { return Out; }
>>
>> +  /// \brief Retrieve the current position in the stream, in bits.
>> +  uint64_t GetCurrentBitNo() const { return Out.size() * CHAR_BIT  
>> + CurBit; }
>> +
>>   // 
>> = 
>> = 
>> = 
>> -------------------------------------------------------------------- 
>> ===//
>>   // Basic Primitives for emitting bits to the stream.
>>   // 
>> = 
>> = 
>> = 
>> -------------------------------------------------------------------- 
>> ===//
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From dgregor at apple.com  Wed Apr  8 11:57:40 2009
From: dgregor at apple.com (Douglas Gregor)
Date: Wed, 08 Apr 2009 16:57:40 -0000
Subject: [llvm-commits] [llvm] r68616 -
	/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
Message-ID: <200904081657.n38Gvei6020444@zion.cs.uiuc.edu>

Author: dgregor
Date: Wed Apr  8 11:57:40 2009
New Revision: 68616

URL: http://llvm.org/viewvc/llvm-project?rev=68616&view=rev
Log:
Use 8 instead of CHAR_BIT

Modified:
    llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h

Modified: llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h?rev=68616&r1=68615&r2=68616&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h (original)
+++ llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h Wed Apr  8 11:57:40 2009
@@ -80,7 +80,7 @@
   std::vector<unsigned char> &getBuffer() { return Out; }
 
   /// \brief Retrieve the current position in the stream, in bits.
-  uint64_t GetCurrentBitNo() const { return Out.size() * CHAR_BIT + CurBit; }
+  uint64_t GetCurrentBitNo() const { return Out.size() * 8 + CurBit; }
 
   //===--------------------------------------------------------------------===//
   // Basic Primitives for emitting bits to the stream.




From dgregor at apple.com  Wed Apr  8 11:57:49 2009
From: dgregor at apple.com (Douglas Gregor)
Date: Wed, 8 Apr 2009 09:57:49 -0700
Subject: [llvm-commits] [llvm] r68610 -
	/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
In-Reply-To: <30AD0ED4-B2BB-4864-99A8-950CF009A559@apple.com>
References: <200904081518.n38FIMr8016539@zion.cs.uiuc.edu>
	<1239208931.6077.19.camel@remington>
	<30AD0ED4-B2BB-4864-99A8-950CF009A559@apple.com>
Message-ID: <68ABCD0B-7898-44D8-8220-A030D8E34298@apple.com>


On Apr 8, 2009, at 9:52 AM, Chris Lattner wrote:

> Doug, can you just use 8 instead of CHAR_BIT?

Done, sorry 'bout that.

> On Apr 8, 2009, at 9:42 AM, Preston Gurd wrote:
>
>> This patch breaks my build, because CHAR_BIT is undefined.
>>
>> Surely the patch must also add an include of <limits.h> to obtain the
>> definition of CHAR_BIT?
>>
>>
>>
>> On Wed, 2009-04-08 at 11:18 -0400, Douglas Gregor wrote:
>>> Author: dgregor
>>> Date: Wed Apr  8 10:18:21 2009
>>> New Revision: 68610
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=68610&view=rev
>>> Log:
>>> Add BitstreamWriter::GetCurrentBitNo, to report where we are in  
>>> the output bitstream
>>>
>>> Modified:
>>>   llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
>>>
>>> Modified: llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h?rev=68610&r1=68609&r2=68610&view=diff
>>>
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> ====================================================================
>>> --- llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h (original)
>>> +++ llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h Wed Apr  8  
>>> 10:18:21 2009
>>> @@ -79,6 +79,9 @@
>>>
>>>  std::vector<unsigned char> &getBuffer() { return Out; }
>>>
>>> +  /// \brief Retrieve the current position in the stream, in bits.
>>> +  uint64_t GetCurrentBitNo() const { return Out.size() * CHAR_BIT  
>>> + CurBit; }
>>> +
>>>  // 
>>> = 
>>> = 
>>> = 
>>> --------------------------------------------------------------------= 
>>> ==//
>>>  // Basic Primitives for emitting bits to the stream.
>>>  // 
>>> = 
>>> = 
>>> = 
>>> --------------------------------------------------------------------= 
>>> ==//
>>>
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



From kremenek at apple.com  Wed Apr  8 12:28:16 2009
From: kremenek at apple.com (Ted Kremenek)
Date: Wed, 08 Apr 2009 17:28:16 -0000
Subject: [llvm-commits] [llvm] r68618 -
	/llvm/trunk/tools/llvm-config/CMakeLists.txt
Message-ID: <200904081728.n38HSGWe021584@zion.cs.uiuc.edu>

Author: kremenek
Date: Wed Apr  8 12:28:16 2009
New Revision: 68618

URL: http://llvm.org/viewvc/llvm-project?rev=68618&view=rev
Log:
Accommodate empty string for build type. This was previously causing an error
when generating an Xcode project using the CMake files (thanks to Doug Gregor
for identifying the issue).

Modified:
    llvm/trunk/tools/llvm-config/CMakeLists.txt

Modified: llvm/trunk/tools/llvm-config/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-config/CMakeLists.txt?rev=68618&r1=68617&r2=68618&view=diff

==============================================================================
--- llvm/trunk/tools/llvm-config/CMakeLists.txt (original)
+++ llvm/trunk/tools/llvm-config/CMakeLists.txt Wed Apr  8 12:28:16 2009
@@ -82,7 +82,7 @@
   DEPENDS ${LIBDEPS}
   COMMENT "Checking for cyclic dependencies between LLVM libraries.")
 
-string(TOUPPER ${CMAKE_BUILD_TYPE} uppercase_CMAKE_BUILD_TYPE)
+string(TOUPPER "${CMAKE_BUILD_TYPE}" uppercase_CMAKE_BUILD_TYPE)
 set(C_FLGS "${CMAKE_C_FLAGS_${uppercase_CMAKE_BUILD_TYPE}} ${LLVM_DEFINITIONS}")
 set(CXX_FLGS "${CMAKE_CXX_FLAGS_${uppercase_CMAKE_BUILD_TYPE}} ${LLVM_DEFINITIONS}")
 set(CPP_FLGS "${CMAKE_CPP_FLAGS_${uppercase_CMAKE_BUILD_TYPE}} ${LLVM_DEFINITIONS}")




From bob.wilson at apple.com  Wed Apr  8 12:55:28 2009
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 08 Apr 2009 17:55:28 -0000
Subject: [llvm-commits] [llvm] r68619 -
	/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Message-ID: <200904081755.n38HtSxE022564@zion.cs.uiuc.edu>

Author: bwilson
Date: Wed Apr  8 12:55:28 2009
New Revision: 68619

URL: http://llvm.org/viewvc/llvm-project?rev=68619&view=rev
Log:
Fix PR3795: Apply Dan's suggested fix for
ARMTargetLowering::isLegalAddressingMode.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=68619&r1=68618&r2=68619&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Apr  8 12:55:28 2009
@@ -1759,7 +1759,8 @@
 /// by AM is legal for this target, for a load/store of the specified type.
 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
                                               const Type *Ty) const {
-  if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty, true), Subtarget))
+  MVT VT = getValueType(Ty, true);
+  if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
     return false;
 
   // Can never fold addr of global into load/store.
@@ -1778,8 +1779,11 @@
     if (AM.BaseOffs)
       return false;
 
+    if (!VT.isSimple())
+      return false;
+
     int Scale = AM.Scale;
-    switch (getValueType(Ty).getSimpleVT()) {
+    switch (VT.getSimpleVT()) {
     default: return false;
     case MVT::i1:
     case MVT::i8:




From bob.wilson at apple.com  Wed Apr  8 13:00:56 2009
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 08 Apr 2009 18:00:56 -0000
Subject: [llvm-commits] [llvm] r68620 -
	/llvm/trunk/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll
Message-ID: <200904081800.n38I0usv022851@zion.cs.uiuc.edu>

Author: bwilson
Date: Wed Apr  8 13:00:55 2009
New Revision: 68620

URL: http://llvm.org/viewvc/llvm-project?rev=68620&view=rev
Log:
Add testcase for PR3795.

Added:
    llvm/trunk/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll

Added: llvm/trunk/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll?rev=68620&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll Wed Apr  8 13:00:55 2009
@@ -0,0 +1,18 @@
+; RUN: llvm-as < %s | llc -march=arm
+; PR3795
+
+define fastcc void @_D3foo3fooFAriZv({ i32, { double, double }* } %d_arg, i32 %x_arg) {
+entry:
+	%d = alloca { i32, { double, double }* }		; <{ i32, { double, double }* }*> [#uses=2]
+	%x = alloca i32		; <i32*> [#uses=2]
+	%b = alloca { double, double }		; <{ double, double }*> [#uses=1]
+	store { i32, { double, double }* } %d_arg, { i32, { double, double }* }* %d
+	store i32 %x_arg, i32* %x
+	%tmp = load i32* %x		; <i32> [#uses=1]
+	%tmp1 = getelementptr { i32, { double, double }* }* %d, i32 0, i32 1		; <{ double, double }**> [#uses=1]
+	%.ptr = load { double, double }** %tmp1		; <{ double, double }*> [#uses=1]
+	%tmp2 = getelementptr { double, double }* %.ptr, i32 %tmp		; <{ double, double }*> [#uses=1]
+	%tmp3 = load { double, double }* %tmp2		; <{ double, double }> [#uses=1]
+	store { double, double } %tmp3, { double, double }* %b
+	ret void
+}




From gohman at apple.com  Wed Apr  8 13:46:28 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 8 Apr 2009 11:46:28 -0700
Subject: [llvm-commits] [llvm] r68610 -
	/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
In-Reply-To: <30AD0ED4-B2BB-4864-99A8-950CF009A559@apple.com>
References: <200904081518.n38FIMr8016539@zion.cs.uiuc.edu>
	<1239208931.6077.19.camel@remington>
	<30AD0ED4-B2BB-4864-99A8-950CF009A559@apple.com>
Message-ID: <641F4820-48CF-42B6-A5B0-802ADB65A7E3@apple.com>

Has someone spent too much time micro-optimizing C front-end code? ;-)
CHAR_BIT just requires <limits.h>, and it makes it more obvious
that the code is talking about a byte on the host.

Dan

On Apr 8, 2009, at 9:52 AM, Chris Lattner wrote:

> Doug, can you just use 8 instead of CHAR_BIT?
>
> On Apr 8, 2009, at 9:42 AM, Preston Gurd wrote:
>
>> This patch breaks my build, because CHAR_BIT is undefined.
>>
>> Surely the patch must also add an include of <limits.h> to obtain the
>> definition of CHAR_BIT?
>>
>>
>>


From isanbard at gmail.com  Wed Apr  8 13:49:21 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 8 Apr 2009 11:49:21 -0700
Subject: [llvm-commits] [llvm] r68552 - in /llvm/trunk: lib/Target/X86/
	lib/Target/X86/AsmPrinter/ test/CodeGen/X86/
In-Reply-To: <38a0d8450904080113v2f63dcd6g9bf1fbb01f96219f@mail.gmail.com>
References: <200904072137.n37Lbll0029223@zion.cs.uiuc.edu>
	<16e5fdf90904071517r30afc273o26a0f3ffa1662194@mail.gmail.com>
	<38a0d8450904080113v2f63dcd6g9bf1fbb01f96219f@mail.gmail.com>
Message-ID: <16e5fdf90904081149v60db7b91ncb3d512e439d4e18@mail.gmail.com>

On Wed, Apr 8, 2009 at 1:13 AM, Rafael Espindola <espindola at google.com> wrote:
> 2009/4/7 Bill Wendling <isanbard at gmail.com>:
>> Rafael,
>>
>> This is causing a self-hosting LLVM to fail to build:
>
> Sorry about that. I just fixed a problem (revision 68603) that might
> be related to that.
>
> How do you build self-hosting? Just bootstrap llvm-gcc and use that to
> bulid llvm?
>
Yup! Nothing fancy. :-)

I also build it in release mode, because most developers only build
and test in debug mode. That also catches a lot of errors that would
otherwise go unnoticed for a long time.

-bw


From clattner at apple.com  Wed Apr  8 13:53:49 2009
From: clattner at apple.com (Chris Lattner)
Date: Wed, 8 Apr 2009 11:53:49 -0700
Subject: [llvm-commits] [llvm] r68610 -
	/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
In-Reply-To: <641F4820-48CF-42B6-A5B0-802ADB65A7E3@apple.com>
References: <200904081518.n38FIMr8016539@zion.cs.uiuc.edu>
	<1239208931.6077.19.camel@remington>
	<30AD0ED4-B2BB-4864-99A8-950CF009A559@apple.com>
	<641F4820-48CF-42B6-A5B0-802ADB65A7E3@apple.com>
Message-ID: <7B9B0762-DF7F-40AD-A581-61816B6F7255@apple.com>

On Apr 8, 2009, at 11:46 AM, Dan Gohman wrote:
> Has someone spent too much time micro-optimizing C front-end code? ;-)
> CHAR_BIT just requires <limits.h>, and it makes it more obvious
> that the code is talking about a byte on the host.

Bitstream stuff (as well as llvm in general) already makes many many  
assumptions that there are 8 bits in a host byte.

-Chris

>
>
> Dan
>
> On Apr 8, 2009, at 9:52 AM, Chris Lattner wrote:
>
>> Doug, can you just use 8 instead of CHAR_BIT?
>>
>> On Apr 8, 2009, at 9:42 AM, Preston Gurd wrote:
>>
>>> This patch breaks my build, because CHAR_BIT is undefined.
>>>
>>> Surely the patch must also add an include of <limits.h> to obtain  
>>> the
>>> definition of CHAR_BIT?
>>>
>>>
>>>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From gohman at apple.com  Wed Apr  8 14:04:59 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 8 Apr 2009 12:04:59 -0700
Subject: [llvm-commits] [PATCH] Fix simple crashing bug in
	MachineInstr::getNumExplicitOperands
In-Reply-To: <C091F0DE-9445-42D1-A412-E89B3DEC574B@2pi.dk>
References: <C091F0DE-9445-42D1-A412-E89B3DEC574B@2pi.dk>
Message-ID: <3E2DBEA3-EBCC-4153-9F80-F0E57642645E@apple.com>


On Apr 8, 2009, at 8:47 AM, Jakob Stoklund Olesen wrote:

> MachineInstr::getNumExplicitOperands was tripping asserts in  
> getOperand. Looking at the code, it it obvious why.

>
> Note: The attached fix assumes that all implicit machine instruction  
> operands follow the explicit operands. Is that always true?


I agree that the code in MachineInstr::getNumExplicitOperands
looks wrong. According to ARMInstrThumb.td, tPOP_RET has variable_ops
though, and IIRC the way things currently work is that these
extra operands get added after the implicit operands, so I think
this patch isn't the right fix.

Dan



From stoklund at 2pi.dk  Wed Apr  8 14:30:35 2009
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 8 Apr 2009 21:30:35 +0200
Subject: [llvm-commits] [PATCH] Fix simple crashing bug in
	MachineInstr::getNumExplicitOperands
In-Reply-To: <3E2DBEA3-EBCC-4153-9F80-F0E57642645E@apple.com>
References: <C091F0DE-9445-42D1-A412-E89B3DEC574B@2pi.dk>
	<3E2DBEA3-EBCC-4153-9F80-F0E57642645E@apple.com>
Message-ID: <77A1FA74-6457-4D3C-B367-55264D745054@2pi.dk>


On 08/04/2009, at 21.04, Dan Gohman wrote:
>
> I agree that the code in MachineInstr::getNumExplicitOperands
> looks wrong. According to ARMInstrThumb.td, tPOP_RET has variable_ops
> though, and IIRC the way things currently work is that these
> extra operands get added after the implicit operands, so I think
> this patch isn't the right fix.

In that case, maybe this was the intention?
Tested with "make check".

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From brukman at gmail.com  Wed Apr  8 14:39:11 2009
From: brukman at gmail.com (Misha Brukman)
Date: Wed, 8 Apr 2009 15:39:11 -0400
Subject: [llvm-commits] [PATCH] Fix simple crashing bug in
	MachineInstr::getNumExplicitOperands
In-Reply-To: <77A1FA74-6457-4D3C-B367-55264D745054@2pi.dk>
References: <C091F0DE-9445-42D1-A412-E89B3DEC574B@2pi.dk>
	<3E2DBEA3-EBCC-4153-9F80-F0E57642645E@apple.com>
	<77A1FA74-6457-4D3C-B367-55264D745054@2pi.dk>
Message-ID: <f88b89a50904081239p115ab460kd487baa20110dc0@mail.gmail.com>

On Wed, Apr 8, 2009 at 3:30 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote:

> On 08/04/2009, at 21.04, Dan Gohman wrote:
>
>>
>> I agree that the code in MachineInstr::getNumExplicitOperands
>> looks wrong. According to ARMInstrThumb.td, tPOP_RET has variable_ops
>> though, and IIRC the way things currently work is that these
>> extra operands get added after the implicit operands, so I think
>> this patch isn't the right fix.
>>
>
> In that case, maybe this was the intention?
> Tested with "make check".


Note that "make check" does not automatically rebuild the tools used in
testing; you have to "make tools-only" first to make sure you're running the
code you modified, rather than the binaries from a previous build.

I sent a patch to llvm-commits to solicit feedback as to whether it's safe
-- see the archives if you want to try it out.
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From rafael.espindola at gmail.com  Wed Apr  8 16:14:40 2009
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 08 Apr 2009 21:14:40 -0000
Subject: [llvm-commits] [llvm] r68645 - in /llvm/trunk: lib/Target/X86/
 lib/Target/X86/AsmPrinter/ test/CodeGen/X86/
Message-ID: <200904082114.n38LEheG000901@zion.cs.uiuc.edu>

Author: rafael
Date: Wed Apr  8 16:14:34 2009
New Revision: 68645

URL: http://llvm.org/viewvc/llvm-project?rev=68645&view=rev
Log:
Re-apply 68552.
Tested by bootstrapping llvm-gcc and using that to build llvm.


Modified:
    llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
    llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
    llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
    llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
    llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
    llvm/trunk/lib/Target/X86/X86FastISel.cpp
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86Instr64bit.td
    llvm/trunk/lib/Target/X86/X86InstrBuilder.h
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.h
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
    llvm/trunk/lib/Target/X86/X86RegisterInfo.td
    llvm/trunk/test/CodeGen/X86/tls10.ll
    llvm/trunk/test/CodeGen/X86/tls2.ll
    llvm/trunk/test/CodeGen/X86/tls6.ll
    llvm/trunk/test/CodeGen/X86/tls8.ll

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Wed Apr  8 16:14:34 2009
@@ -566,9 +566,8 @@
   }
 }
 
-void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
-                                         const char *Modifier){
-  assert(isMem(MI, Op) && "Invalid memory reference!");
+void X86ATTAsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op,
+                                            const char *Modifier){
   MachineOperand BaseReg  = MI->getOperand(Op);
   MachineOperand IndexReg = MI->getOperand(Op+2);
   const MachineOperand &DispSpec = MI->getOperand(Op+3);
@@ -611,6 +610,17 @@
   }
 }
 
+void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
+                                         const char *Modifier){
+  assert(isMem(MI, Op) && "Invalid memory reference!");
+  MachineOperand Segment = MI->getOperand(Op+4);
+  if (Segment.getReg()) {
+      printOperand(MI, Op+4, Modifier);
+      O << ':';
+    }
+  printLeaMemReference(MI, Op, Modifier);
+}
+
 void X86ATTAsmPrinter::printPICJumpTableSetLabel(unsigned uid,
                                            const MachineBasicBlock *MBB) const {
   if (!TAI->getSetDirective())

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Wed Apr  8 16:14:34 2009
@@ -93,8 +93,14 @@
   void printf128mem(const MachineInstr *MI, unsigned OpNo) {
     printMemReference(MI, OpNo);
   }
+  void printlea32mem(const MachineInstr *MI, unsigned OpNo) {
+    printLeaMemReference(MI, OpNo);
+  }
+  void printlea64mem(const MachineInstr *MI, unsigned OpNo) {
+    printLeaMemReference(MI, OpNo);
+  }
   void printlea64_32mem(const MachineInstr *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo, "subreg64");
+    printLeaMemReference(MI, OpNo, "subreg64");
   }
 
   bool printAsmMRegister(const MachineOperand &MO, const char Mode);
@@ -107,6 +113,8 @@
   void printSSECC(const MachineInstr *MI, unsigned Op);
   void printMemReference(const MachineInstr *MI, unsigned Op,
                          const char *Modifier=NULL);
+  void printLeaMemReference(const MachineInstr *MI, unsigned Op,
+                            const char *Modifier=NULL);
   void printPICJumpTableSetLabel(unsigned uid,
                                  const MachineBasicBlock *MBB) const;
   void printPICJumpTableSetLabel(unsigned uid, unsigned uid2,

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp Wed Apr  8 16:14:34 2009
@@ -271,10 +271,9 @@
   }
 }
 
-void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
-                                           const char *Modifier) {
-  assert(isMem(MI, Op) && "Invalid memory reference!");
-
+void X86IntelAsmPrinter::printLeaMemReference(const MachineInstr *MI,
+                                              unsigned Op,
+                                              const char *Modifier) {
   const MachineOperand &BaseReg  = MI->getOperand(Op);
   int ScaleVal                   = MI->getOperand(Op+1).getImm();
   const MachineOperand &IndexReg = MI->getOperand(Op+2);
@@ -317,6 +316,17 @@
   O << "]";
 }
 
+void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
+                                           const char *Modifier) {
+  assert(isMem(MI, Op) && "Invalid memory reference!");
+  MachineOperand Segment = MI->getOperand(Op+4);
+  if (Segment.getReg()) {
+      printOperand(MI, Op+4, Modifier);
+      O << ':';
+    }
+  printLeaMemReference(MI, Op, Modifier);
+}
+
 void X86IntelAsmPrinter::printPICJumpTableSetLabel(unsigned uid,
                                            const MachineBasicBlock *MBB) const {
   if (!TAI->getSetDirective())

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h Wed Apr  8 16:14:34 2009
@@ -88,9 +88,17 @@
     O << "XMMWORD PTR ";
     printMemReference(MI, OpNo);
   }
+  void printlea32mem(const MachineInstr *MI, unsigned OpNo) {
+    O << "DWORD PTR ";
+    printLeaMemReference(MI, OpNo);
+  }
+  void printlea64mem(const MachineInstr *MI, unsigned OpNo) {
+    O << "QWORD PTR ";
+    printLeaMemReference(MI, OpNo);
+  }
   void printlea64_32mem(const MachineInstr *MI, unsigned OpNo) {
     O << "QWORD PTR ";
-    printMemReference(MI, OpNo, "subreg64");
+    printLeaMemReference(MI, OpNo, "subreg64");
   }
 
   bool printAsmMRegister(const MachineOperand &MO, const char Mode);
@@ -103,6 +111,8 @@
   void printSSECC(const MachineInstr *MI, unsigned Op);
   void printMemReference(const MachineInstr *MI, unsigned Op,
                          const char *Modifier=NULL);
+  void printLeaMemReference(const MachineInstr *MI, unsigned Op,
+                            const char *Modifier=NULL);
   void printPICJumpTableSetLabel(unsigned uid,
                                  const MachineBasicBlock *MBB) const;
   void printPICJumpTableSetLabel(unsigned uid, unsigned uid2,

Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Wed Apr  8 16:14:34 2009
@@ -533,23 +533,6 @@
     case X86::DWARF_LOC:
     case X86::FP_REG_KILL:
       break;
-    case X86::TLS_tp: {
-      MCE.emitByte(BaseOpcode);
-      unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg());
-      MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
-      emitConstant(0, 4);
-      break;
-    }
-    case X86::TLS_gs_ri: {
-      MCE.emitByte(BaseOpcode);
-      unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg());
-      MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
-      GlobalValue* GV = MI.getOperand(1).getGlobal();
-      unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
-        : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
-      emitGlobalAddress(GV, rt);
-      break;
-    }
     case X86::MOVPC32r: {
       // This emits the "call" portion of this pseudo instruction.
       MCE.emitByte(BaseOpcode);
@@ -661,13 +644,21 @@
     break;
 
   case X86II::MRMSrcMem: {
-    intptr_t PCAdj = (CurOp + X86AddrNumOperands + 1 != NumOps) ?
+    // FIXME: Maybe lea should have its own form?
+    int AddrOperands;
+    if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
+        Opcode == X86::LEA16r || Opcode == X86::LEA32r)
+      AddrOperands = X86AddrNumOperands - 1; // No segment register
+    else
+      AddrOperands = X86AddrNumOperands;
+
+    intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
       X86InstrInfo::sizeOfImm(Desc) : 0;
 
     MCE.emitByte(BaseOpcode);
     emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
                      PCAdj);
-    CurOp += X86AddrNumOperands + 1;
+    CurOp += AddrOperands + 1;
     if (CurOp != NumOps)
       emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
     break;

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Wed Apr  8 16:14:34 2009
@@ -1490,7 +1490,7 @@
       else
         Opc = X86::LEA64r;
       unsigned ResultReg = createResultReg(RC);
-      addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
+      addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
       return ResultReg;
     }
     return 0;
@@ -1535,7 +1535,7 @@
   unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
   TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
   unsigned ResultReg = createResultReg(RC);
-  addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
+  addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
   return ResultReg;
 }
 

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Apr  8 16:14:34 2009
@@ -69,6 +69,7 @@
     unsigned Scale;
     SDValue IndexReg; 
     int32_t Disp;
+    SDValue Segment;
     GlobalValue *GV;
     Constant *CP;
     const char *ES;
@@ -77,7 +78,7 @@
 
     X86ISelAddressMode()
       : BaseType(RegBase), isRIPRel(false), Scale(1), IndexReg(), Disp(0),
-        GV(0), CP(0), ES(0), JT(-1), Align(0) {
+        Segment(), GV(0), CP(0), ES(0), JT(-1), Align(0) {
     }
 
     bool hasSymbolicDisplacement() const {
@@ -159,20 +160,25 @@
     SDNode *Select(SDValue N);
     SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
 
+    bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM);
+    bool MatchLoad(SDValue N, X86ISelAddressMode &AM);
     bool MatchAddress(SDValue N, X86ISelAddressMode &AM,
                       unsigned Depth = 0);
     bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
     bool SelectAddr(SDValue Op, SDValue N, SDValue &Base,
-                    SDValue &Scale, SDValue &Index, SDValue &Disp);
+                    SDValue &Scale, SDValue &Index, SDValue &Disp,
+                    SDValue &Segment);
     bool SelectLEAAddr(SDValue Op, SDValue N, SDValue &Base,
                        SDValue &Scale, SDValue &Index, SDValue &Disp);
     bool SelectScalarSSELoad(SDValue Op, SDValue Pred,
                              SDValue N, SDValue &Base, SDValue &Scale,
                              SDValue &Index, SDValue &Disp,
+                             SDValue &Segment,
                              SDValue &InChain, SDValue &OutChain);
     bool TryFoldLoad(SDValue P, SDValue N,
                      SDValue &Base, SDValue &Scale,
-                     SDValue &Index, SDValue &Disp);
+                     SDValue &Index, SDValue &Disp,
+                     SDValue &Segment);
     void PreprocessForRMW();
     void PreprocessForFPConvert();
 
@@ -186,7 +192,7 @@
 
     inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base, 
                                    SDValue &Scale, SDValue &Index,
-                                   SDValue &Disp) {
+                                   SDValue &Disp, SDValue &Segment) {
       Base  = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
         CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
         AM.Base.Reg;
@@ -205,6 +211,11 @@
         Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32);
       else
         Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
+
+      if (AM.Segment.getNode())
+        Segment = AM.Segment;
+      else
+        Segment = CurDAG->getRegister(0, MVT::i32);
     }
 
     /// getI8Imm - Return a target constant with the specified value, of type
@@ -726,6 +737,33 @@
     EmitSpecialCodeForMain(BB, MF.getFrameInfo());
 }
 
+
+bool X86DAGToDAGISel::MatchSegmentBaseAddress(SDValue N,
+                                              X86ISelAddressMode &AM) {
+  assert(N.getOpcode() == X86ISD::SegmentBaseAddress);
+  SDValue Segment = N.getOperand(0);
+
+  if (AM.Segment.getNode() == 0) {
+    AM.Segment = Segment;
+    return false;
+  }
+
+  return true;
+}
+
+bool X86DAGToDAGISel::MatchLoad(SDValue N, X86ISelAddressMode &AM) {
+  // This optimization is valid because the GNU TLS model defines that
+  // gs:0 (or fs:0 on X86-64) contains its own address.
+  // For more information see http://people.redhat.com/drepper/tls.pdf
+
+  SDValue Address = N.getOperand(1);
+  if (Address.getOpcode() == X86ISD::SegmentBaseAddress &&
+      !MatchSegmentBaseAddress (Address, AM))
+    return false;
+
+  return true;
+}
+
 /// MatchAddress - Add the specified node to the specified addressing mode,
 /// returning true if it cannot be done.  This just pattern matches for the
 /// addressing mode.
@@ -761,6 +799,11 @@
     break;
   }
 
+  case X86ISD::SegmentBaseAddress:
+    if (!MatchSegmentBaseAddress(N, AM))
+      return false;
+    break;
+
   case X86ISD::Wrapper: {
     DOUT << "Wrapper: 64bit " << is64Bit;
     DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n";
@@ -807,6 +850,11 @@
     break;
   }
 
+  case ISD::LOAD:
+    if (!MatchLoad(N, AM))
+      return false;
+    break;
+
   case ISD::FrameIndex:
     if (AM.BaseType == X86ISelAddressMode::RegBase
         && AM.Base.Reg.getNode() == 0) {
@@ -1034,7 +1082,7 @@
 /// match by reference.
 bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base,
                                  SDValue &Scale, SDValue &Index,
-                                 SDValue &Disp) {
+                                 SDValue &Disp, SDValue &Segment) {
   X86ISelAddressMode AM;
   bool Done = false;
   if (AvoidDupAddrCompute && !N.hasOneUse()) {
@@ -1069,7 +1117,7 @@
   if (!AM.IndexReg.getNode())
     AM.IndexReg = CurDAG->getRegister(0, VT);
 
-  getAddressOperands(AM, Base, Scale, Index, Disp);
+  getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
   return true;
 }
 
@@ -1079,7 +1127,8 @@
 bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred,
                                           SDValue N, SDValue &Base,
                                           SDValue &Scale, SDValue &Index,
-                                          SDValue &Disp, SDValue &InChain,
+                                          SDValue &Disp, SDValue &Segment,
+                                          SDValue &InChain,
                                           SDValue &OutChain) {
   if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
     InChain = N.getOperand(0).getValue(1);
@@ -1088,7 +1137,7 @@
         N.hasOneUse() &&
         IsLegalAndProfitableToFold(N.getNode(), Pred.getNode(), Op.getNode())) {
       LoadSDNode *LD = cast<LoadSDNode>(InChain);
-      if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
+      if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
         return false;
       OutChain = LD->getChain();
       return true;
@@ -1105,7 +1154,7 @@
       N.getOperand(0).getOperand(0).hasOneUse()) {
     // Okay, this is a zero extending load.  Fold it.
     LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
-    if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
+    if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
       return false;
     OutChain = LD->getChain();
     InChain = SDValue(LD, 1);
@@ -1124,6 +1173,11 @@
   if (MatchAddress(N, AM))
     return false;
 
+  //Is it better to set AM.Segment before calling MatchAddress to
+  //prevent it from adding a segment?
+  if (AM.Segment.getNode())
+    return false;
+
   MVT VT = N.getValueType();
   unsigned Complexity = 0;
   if (AM.BaseType == X86ISelAddressMode::RegBase)
@@ -1162,7 +1216,8 @@
     Complexity++;
 
   if (Complexity > 2) {
-    getAddressOperands(AM, Base, Scale, Index, Disp);
+    SDValue Segment;
+    getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
     return true;
   }
   return false;
@@ -1170,11 +1225,12 @@
 
 bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
                                   SDValue &Base, SDValue &Scale,
-                                  SDValue &Index, SDValue &Disp) {
+                                  SDValue &Index, SDValue &Disp,
+                                  SDValue &Segment) {
   if (ISD::isNON_EXTLoad(N.getNode()) &&
       N.hasOneUse() &&
       IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
-    return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp);
+    return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp, Segment);
   return false;
 }
 
@@ -1230,11 +1286,11 @@
   SDValue In1 = Node->getOperand(1);
   SDValue In2L = Node->getOperand(2);
   SDValue In2H = Node->getOperand(3);
-  SDValue Tmp0, Tmp1, Tmp2, Tmp3;
-  if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3))
+  SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
+  if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
     return NULL;
   SDValue LSI = Node->getOperand(4);    // MemOperand
-  const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, In2L, In2H, LSI, Chain };
+  const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, LSI, Chain};
   return CurDAG->getTargetNode(Opc, Node->getDebugLoc(),
                                MVT::i32, MVT::i32, MVT::Other, Ops,
                                array_lengthof(Ops));
@@ -1316,11 +1372,11 @@
       case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
       }
 
-      SDValue Tmp0, Tmp1, Tmp2, Tmp3;
-      bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
+      SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
+      bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
       // multiplty is commmutative
       if (!foldedLoad) {
-        foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
+        foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
         if (foldedLoad)
           std::swap(N0, N1);
       }
@@ -1329,7 +1385,8 @@
                                               N0, SDValue()).getValue(1);
 
       if (foldedLoad) {
-        SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
+        SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
+                          InFlag };
         SDNode *CNode =
           CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
                                 array_lengthof(Ops));
@@ -1438,17 +1495,17 @@
         break;
       }
 
-      SDValue Tmp0, Tmp1, Tmp2, Tmp3;
-      bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
+      SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
+      bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
       bool signBitIsZero = CurDAG->SignBitIsZero(N0);
 
       SDValue InFlag;
       if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
         // Special case for div8, just use a move with zero extension to AX to
         // clear the upper 8 bits (AH).
-        SDValue Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
-        if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) {
-          SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
+        SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
+        if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
+          SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
           Move =
             SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, MVT::i16, 
                                           MVT::Other, Ops,
@@ -1480,7 +1537,8 @@
       }
 
       if (foldedLoad) {
-        SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
+        SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
+                          InFlag };
         SDNode *CNode =
           CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
                                 array_lengthof(Ops));
@@ -1649,13 +1707,13 @@
 bool X86DAGToDAGISel::
 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
                              std::vector<SDValue> &OutOps) {
-  SDValue Op0, Op1, Op2, Op3;
+  SDValue Op0, Op1, Op2, Op3, Op4;
   switch (ConstraintCode) {
   case 'o':   // offsetable        ??
   case 'v':   // not offsetable    ??
   default: return true;
   case 'm':   // memory
-    if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3))
+    if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3, Op4))
       return true;
     break;
   }
@@ -1664,6 +1722,7 @@
   OutOps.push_back(Op1);
   OutOps.push_back(Op2);
   OutOps.push_back(Op3);
+  OutOps.push_back(Op4);
   return false;
 }
 

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Apr  8 16:14:34 2009
@@ -4834,8 +4834,13 @@
                                    const MVT PtrVT, TLSModel::Model model) {
   DebugLoc dl = GA->getDebugLoc();
   // Get the Thread Pointer
-  SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER,
-                                      DebugLoc::getUnknownLoc(), PtrVT);
+  SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
+                             DebugLoc::getUnknownLoc(), PtrVT,
+                             DAG.getRegister(X86::GS, MVT::i32));
+
+  SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
+                                      NULL, 0);
+
   // emit "addl x at ntpoff,%eax" (local exec) or "addl x at indntpoff,%eax" (initial
   // exec)
   SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
@@ -7149,7 +7154,7 @@
   case X86ISD::FRSQRT:             return "X86ISD::FRSQRT";
   case X86ISD::FRCP:               return "X86ISD::FRCP";
   case X86ISD::TLSADDR:            return "X86ISD::TLSADDR";
-  case X86ISD::THREAD_POINTER:     return "X86ISD::THREAD_POINTER";
+  case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
   case X86ISD::EH_RETURN:          return "X86ISD::EH_RETURN";
   case X86ISD::TC_RETURN:          return "X86ISD::TC_RETURN";
   case X86ISD::FNSTCW16m:          return "X86ISD::FNSTCW16m";
@@ -7483,7 +7488,7 @@
   unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
   MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
   // add 4 to displacement.
-  for (int i=0; i <= lastAddrIndx-1; ++i)
+  for (int i=0; i <= lastAddrIndx-2; ++i)
     (*MIB).addOperand(*argOpers[i]);
   MachineOperand newOp3 = *(argOpers[3]);
   if (newOp3.isImm())
@@ -7491,6 +7496,7 @@
   else
     newOp3.setOffset(newOp3.getOffset()+4);
   (*MIB).addOperand(newOp3);
+  (*MIB).addOperand(*argOpers[lastAddrIndx]);
 
   // t3/4 are defined later, at the bottom of the loop
   unsigned t3 = F->getRegInfo().createVirtualRegister(RC);

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Apr  8 16:14:34 2009
@@ -188,8 +188,11 @@
       /// in order to obtain suitable precision.
       FRSQRT, FRCP,
 
-      // TLSADDR, THREAD_POINTER - Thread Local Storage.
-      TLSADDR, THREAD_POINTER,
+      // TLSADDR - Thread Local Storage.
+      TLSADDR,
+
+      // SegmentBaseAddress - The address segment:0
+      SegmentBaseAddress,
 
       // EH_RETURN - Exception Handling helpers.
       EH_RETURN,

Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Wed Apr  8 16:14:34 2009
@@ -23,7 +23,7 @@
 def i64i8imm   : Operand<i64>;
 
 def lea64mem : Operand<i64> {
-  let PrintMethod = "printi64mem";
+  let PrintMethod = "printlea64mem";
   let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
 }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrBuilder.h?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrBuilder.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrBuilder.h Wed Apr  8 16:14:34 2009
@@ -66,6 +66,15 @@
   return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0);
 }
 
+inline const MachineInstrBuilder &addLeaOffset(const MachineInstrBuilder &MIB,
+                                            int Offset) {
+  return MIB.addImm(1).addReg(0).addImm(Offset);
+}
+
+inline const MachineInstrBuilder &addOffset(const MachineInstrBuilder &MIB,
+                                            int Offset) {
+  return addLeaOffset(MIB, Offset).addReg(0);
+}
 
 /// addRegOffset - This function is used to add a memory reference of the form
 /// [Reg + Offset], i.e., one with no scale or index, but with a
@@ -74,8 +83,13 @@
 inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB,
                                                unsigned Reg, bool isKill,
                                                int Offset) {
-  return MIB.addReg(Reg, false, false, isKill)
-    .addImm(1).addReg(0).addImm(Offset);
+  return addOffset(MIB.addReg(Reg, false, false, isKill), Offset);
+}
+
+inline const MachineInstrBuilder &addLeaRegOffset(const MachineInstrBuilder &MIB,
+                                                  unsigned Reg, bool isKill,
+                                                  int Offset) {
+  return addLeaOffset(MIB.addReg(Reg, false, false, isKill), Offset);
 }
 
 /// addRegReg - This function is used to add a memory reference of the form:
@@ -87,8 +101,8 @@
     .addReg(Reg2, false, false, isKill2).addImm(0);
 }
 
-inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
-                                                 const X86AddressMode &AM) {
+inline const MachineInstrBuilder &addLeaAddress(const MachineInstrBuilder &MIB,
+                                                const X86AddressMode &AM) {
   assert (AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
 
   if (AM.BaseType == X86AddressMode::RegBase)
@@ -104,6 +118,11 @@
     return MIB.addImm(AM.Disp);
 }
 
+inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
+                                                 const X86AddressMode &AM) {
+  return addLeaAddress(MIB, AM).addReg(0);
+}
+
 /// addFrameReference - This function is used to add a reference to the base of
 /// an abstract object on the stack frame of the current function.  This
 /// reference has base register as the FrameIndex offset until it is resolved.
@@ -125,7 +144,7 @@
                         MFI.getObjectOffset(FI) + Offset,
                         MFI.getObjectSize(FI),
                         MFI.getObjectAlignment(FI));
-  return MIB.addFrameIndex(FI).addImm(1).addReg(0).addImm(Offset)
+  return addOffset(MIB.addFrameIndex(FI), Offset)
             .addMemOperand(MMO);
 }
 
@@ -139,7 +158,9 @@
 inline const MachineInstrBuilder &
 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
                          unsigned GlobalBaseReg = 0) {
-  return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0).addConstantPoolIndex(CPI);
+  //FIXME: factor this
+  return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
+    .addConstantPoolIndex(CPI).addReg(0);
 }
 
 } // End llvm namespace

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed Apr  8 16:14:34 2009
@@ -1138,9 +1138,9 @@
       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
       unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
-      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
-                           .addReg(Dest, true, false, false, isDead),
-                           Src, isKill, 1);
+      NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
+                              .addReg(Dest, true, false, false, isDead),
+                              Src, isKill, 1);
       break;
     }
     case X86::INC16r:
@@ -1157,9 +1157,9 @@
       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
       unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
-      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
-                           .addReg(Dest, true, false, false, isDead),
-                           Src, isKill, -1);
+      NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
+                              .addReg(Dest, true, false, false, isDead),
+                              Src, isKill, -1);
       break;
     }
     case X86::DEC16r:
@@ -1200,18 +1200,18 @@
     case X86::ADD64ri8:
       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
       if (MI->getOperand(2).isImm())
-        NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
-                             .addReg(Dest, true, false, false, isDead),
-                             Src, isKill, MI->getOperand(2).getImm());
+        NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
+                                .addReg(Dest, true, false, false, isDead),
+                                Src, isKill, MI->getOperand(2).getImm());
       break;
     case X86::ADD32ri:
     case X86::ADD32ri8:
       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
       if (MI->getOperand(2).isImm()) {
         unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
-        NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
-                             .addReg(Dest, true, false, false, isDead),
-                             Src, isKill, MI->getOperand(2).getImm());
+        NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
+                                .addReg(Dest, true, false, false, isDead),
+                                Src, isKill, MI->getOperand(2).getImm());
       }
       break;
     case X86::ADD16ri:
@@ -1959,7 +1959,7 @@
   for (unsigned i = 0; i != NumAddrOps; ++i)
     MIB.addOperand(MOs[i]);
   if (NumAddrOps < 4)  // FrameIndex only
-    MIB.addImm(1).addReg(0).addImm(0);
+    addOffset(MIB, 0);
   
   // Loop over the rest of the ri operands, converting them over.
   unsigned NumOps = MI->getDesc().getNumOperands()-2;
@@ -1990,7 +1990,7 @@
       for (unsigned i = 0; i != NumAddrOps; ++i)
         MIB.addOperand(MOs[i]);
       if (NumAddrOps < 4)  // FrameIndex only
-        MIB.addImm(1).addReg(0).addImm(0);
+        addOffset(MIB, 0);
     } else {
       MIB.addOperand(MO);
     }
@@ -2008,7 +2008,7 @@
   for (unsigned i = 0; i != NumAddrOps; ++i)
     MIB.addOperand(MOs[i]);
   if (NumAddrOps < 4)  // FrameIndex only
-    MIB.addImm(1).addReg(0).addImm(0);
+    addOffset(MIB, 0);
   return MIB.addImm(0);
 }
 
@@ -2164,7 +2164,7 @@
   } else if (Ops.size() != 1)
     return NULL;
 
-  SmallVector<MachineOperand,4> MOs;
+  SmallVector<MachineOperand,X86AddrNumOperands> MOs;
   if (LoadMI->getOpcode() == X86::V_SET0 ||
       LoadMI->getOpcode() == X86::V_SETALLONES) {
     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
@@ -2193,6 +2193,7 @@
     MOs.push_back(MachineOperand::CreateImm(1));
     MOs.push_back(MachineOperand::CreateReg(0, false));
     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
+    MOs.push_back(MachineOperand::CreateReg(0, false));
   } else {
     // Folding a normal load. Just copy the load's address operands.
     unsigned NumOps = LoadMI->getDesc().getNumOperands();
@@ -2882,11 +2883,6 @@
       FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
       break;
     }
-    case X86::TLS_tp:
-    case X86::TLS_gs_ri:
-      FinalSize += 2;
-      FinalSize += sizeGlobalAddress(false);
-      break;
     }
     CurOp = NumOps;
     break;

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Wed Apr  8 16:14:34 2009
@@ -243,7 +243,7 @@
   };
 }
 
-const int X86AddrNumOperands = 4;
+const int X86AddrNumOperands = 5;
 
 inline static bool isScale(const MachineOperand &MO) {
   return MO.isImm() &&
@@ -251,7 +251,7 @@
      MO.getImm() == 4 || MO.getImm() == 8);
 }
 
-inline static bool isMem(const MachineInstr *MI, unsigned Op) {
+inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
   if (MI->getOperand(Op).isFI()) return true;
   return Op+4 <= MI->getNumOperands() &&
     MI->getOperand(Op  ).isReg() && isScale(MI->getOperand(Op+1)) &&
@@ -262,6 +262,13 @@
      MI->getOperand(Op+3).isJTI());
 }
 
+inline static bool isMem(const MachineInstr *MI, unsigned Op) {
+  if (MI->getOperand(Op).isFI()) return true;
+  return Op+5 <= MI->getNumOperands() &&
+    MI->getOperand(Op+4).isReg() &&
+    isLeaMem(MI, Op);
+}
+
 class X86InstrInfo : public TargetInstrInfoImpl {
   X86TargetMachine &TM;
   const X86RegisterInfo RI;

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Apr  8 16:14:34 2009
@@ -65,7 +65,7 @@
 
 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
 
-def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
+def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
 
 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 
@@ -142,7 +142,8 @@
 
 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
                         [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
-def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
+def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
+                                 SDT_X86SegmentBaseAddress, []>;
 
 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
                         [SDNPHasChain]>;
@@ -167,7 +168,7 @@
 //
 class X86MemOperand<string printMethod> : Operand<iPTR> {
   let PrintMethod = printMethod;
-  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
+  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
 }
 
 def i8mem   : X86MemOperand<"printi8mem">;
@@ -181,7 +182,7 @@
 def f128mem : X86MemOperand<"printf128mem">;
 
 def lea32mem : Operand<i32> {
-  let PrintMethod = "printi32mem";
+  let PrintMethod = "printlea32mem";
   let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
 }
 
@@ -207,7 +208,7 @@
 //
 
 // Define X86 specific addressing mode.
-def addr      : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
+def addr      : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
                                [add, mul, shl, or, frameindex], []>;
 
@@ -2922,101 +2923,11 @@
 // Thread Local Storage Instructions
 //
 
-// FIXME: there is duplication with the non-TLS case.
-// There is a suggestion on how to fix this at
-// http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090309/075212.html
-
 let Uses = [EBX] in
 def TLS_addr32 : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
                   "leal\t${sym:mem}(,%ebx,1), $dst",
                   [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
 
-let AddedComplexity = 10 in
-def TLS_gs_rr  : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
-                  "movl\t%gs:($src), $dst",
-                  [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
-
-let AddedComplexity = 15 in
-def TLS_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
-                  "movl\t%gs:${src:mem}, $dst",
-                  [(set GR32:$dst,
-                    (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>,
-                  SegGS;
-
-let AddedComplexity = 15 in
-def TLS16_gs_ri : I<0x8B, Pseudo, (outs GR16:$dst), (ins i32imm:$src),
-                    "movw\t%gs:${src:mem}, $dst",
-                    [(set GR16:$dst,
-                      (load (add X86TLStp,
-                        (X86Wrapper tglobaltlsaddr:$src))))]>,
-                    SegGS;
-
-let AddedComplexity = 15 in
-def TLS8_gs_ri : I<0x8B, Pseudo, (outs GR8:$dst), (ins i32imm:$src),
-                   "movb\t%gs:${src:mem}, $dst",
-                   [(set GR8:$dst,
-                     (load (add X86TLStp,
-                       (X86Wrapper tglobaltlsaddr:$src))))]>,
-                   SegGS;
-
-let AddedComplexity = 15 in
-def TLS_ext16_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
-                        "movzwl\t%gs:${src:mem}, $dst",
-                        [(set GR32:$dst,
-                          (extloadi32i16
-                            (add X86TLStp,
-                              (X86Wrapper tglobaltlsaddr:$src))))]>,
-                        SegGS;
-
-let AddedComplexity = 15 in
-def TLS_sext16_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
-                         "movswl\t%gs:${src:mem}, $dst",
-                         [(set GR32:$dst,
-                           (sextloadi32i16
-                             (add X86TLStp,
-                               (X86Wrapper tglobaltlsaddr:$src))))]>,
-                         SegGS;
-
-let AddedComplexity = 15 in
-def TLS_zext16_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
-                         "movzwl\t%gs:${src:mem}, $dst",
-                         [(set GR32:$dst,
-                           (zextloadi32i16
-                             (add X86TLStp,
-                               (X86Wrapper tglobaltlsaddr:$src))))]>,
-                         SegGS;
-
-let AddedComplexity = 15 in
-def TLS_ext8_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
-                        "movzbl\t%gs:${src:mem}, $dst",
-                        [(set GR32:$dst,
-                          (extloadi32i8
-                            (add X86TLStp,
-                              (X86Wrapper tglobaltlsaddr:$src))))]>,
-                        SegGS;
-
-let AddedComplexity = 15 in
-def TLS_sext8_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
-                         "movsbl\t%gs:${src:mem}, $dst",
-                         [(set GR32:$dst,
-                           (sextloadi32i8
-                             (add X86TLStp,
-                               (X86Wrapper tglobaltlsaddr:$src))))]>,
-                         SegGS;
-
-let AddedComplexity = 15 in
-def TLS_zext8_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
-                         "movzbl\t%gs:${src:mem}, $dst",
-                         [(set GR32:$dst,
-                           (zextloadi32i8
-                             (add X86TLStp,
-                              (X86Wrapper tglobaltlsaddr:$src))))]>,
-                         SegGS;
-
-def TLS_tp : I<0x8B, Pseudo, (outs GR32:$dst), (ins),
-               "movl\t%gs:0, $dst",
-               [(set GR32:$dst, X86TLStp)]>, SegGS;
-
 let AddedComplexity = 5 in
 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
                    "movl\t%gs:$src, $dst",

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Apr  8 16:14:34 2009
@@ -76,18 +76,18 @@
 // These are 'extloads' from a scalar to the low element of a vector, zeroing
 // the top elements.  These are used for the SSE 'ss' and 'sd' instruction
 // forms.
-def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
+def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
                                   [SDNPHasChain, SDNPMayLoad]>;
-def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
+def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
                                   [SDNPHasChain, SDNPMayLoad]>;
 
 def ssmem : Operand<v4f32> {
   let PrintMethod = "printf32mem";
-  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
+  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
 }
 def sdmem : Operand<v2f64> {
   let PrintMethod = "printf64mem";
-  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
+  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Wed Apr  8 16:14:34 2009
@@ -971,8 +971,8 @@
   } else if (MFI->hasVarSizedObjects()) {
     if (CSSize) {
       unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
-      MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
-                                      FramePtr, false, -CSSize);
+      MachineInstr *MI = addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
+                                         FramePtr, false, -CSSize);
       MBB.insert(MBBI, MI);
     } else
       BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Wed Apr  8 16:14:34 2009
@@ -168,6 +168,14 @@
 
   // Status flags register
   def EFLAGS : Register<"flags">;
+
+  // Segment registers
+  def CS : Register<"cs">;
+  def DS : Register<"ds">;
+  def SS : Register<"ss">;
+  def ES : Register<"es">;
+  def FS : Register<"fs">;
+  def GS : Register<"gs">;
 }
 
 

Modified: llvm/trunk/test/CodeGen/X86/tls10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls10.ll?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls10.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls10.ll Wed Apr  8 16:14:34 2009
@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movl	%gs:0, %eax} %t
-; RUN: grep {leal	i at NTPOFF(%eax), %eax} %t
+; RUN: grep {movl	\$i at NTPOFF, %eax} %t
+; RUN: grep {addl	%gs:0, %eax} %t
 
 @i = external hidden thread_local global i32
 

Modified: llvm/trunk/test/CodeGen/X86/tls2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls2.ll?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls2.ll Wed Apr  8 16:14:34 2009
@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movl	%gs:0, %eax} %t
-; RUN: grep {leal	i at NTPOFF(%eax), %eax} %t
+; RUN: grep {movl	\$i at NTPOFF, %eax} %t
+; RUN: grep {addl	%gs:0, %eax} %t
 
 @i = thread_local global i32 15
 

Modified: llvm/trunk/test/CodeGen/X86/tls6.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls6.ll?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls6.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls6.ll Wed Apr  8 16:14:34 2009
@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movl	%gs:0, %eax} %t
-; RUN: grep {leal	i at NTPOFF(%eax), %eax} %t
+; RUN: grep {movl	\$i at NTPOFF, %eax} %t
+; RUN: grep {addl	%gs:0, %eax} %t
 
 @i = internal thread_local global i32 15
 

Modified: llvm/trunk/test/CodeGen/X86/tls8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls8.ll?rev=68645&r1=68644&r2=68645&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls8.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls8.ll Wed Apr  8 16:14:34 2009
@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movl	%gs:0, %eax} %t
-; RUN: grep {leal	i at NTPOFF(%eax), %eax} %t
+; RUN: grep {movl	\$i at NTPOFF, %eax} %t
+; RUN: grep {addl	%gs:0, %eax} %t
 
 @i = hidden thread_local global i32 15
 




From dpatel at apple.com  Wed Apr  8 17:18:46 2009
From: dpatel at apple.com (Devang Patel)
Date: Wed, 08 Apr 2009 22:18:46 -0000
Subject: [llvm-commits] [llvm] r68647 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
Message-ID: <200904082218.n38MIkCW006691@zion.cs.uiuc.edu>

Author: dpatel
Date: Wed Apr  8 17:18:45 2009
New Revision: 68647

URL: http://llvm.org/viewvc/llvm-project?rev=68647&view=rev
Log:
If subprogram type is not tagged as DW_TAG_subroutine_type then use it directly as a return value type.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=68647&r1=68646&r2=68647&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Wed Apr  8 17:18:45 2009
@@ -1900,8 +1900,9 @@
     DIArray Args = SPTy.getTypeArray();
     
     // Add Return Type.
+    unsigned SPTag = SPTy.getTag();
     if (!IsConstructor) {
-      if (Args.isNull()) 
+      if (Args.isNull() || SPTag != DW_TAG_subroutine_type)
         AddType(DW_Unit, SPDie, SPTy);
       else
         AddType(DW_Unit, SPDie, DIType(Args.getElement(0).getGV()));
@@ -1912,7 +1913,7 @@
       // Add arguments.
       // Do not add arguments for subprogram definition. They will be
       // handled through RecordVariable.
-      if (!Args.isNull())
+      if (SPTag == DW_TAG_subroutine_type)
         for (unsigned i = 1, N =  Args.getNumElements(); i < N; ++i) {
           DIE *Arg = new DIE(DW_TAG_formal_parameter);
           AddType(DW_Unit, Arg, DIType(Args.getElement(i).getGV()));




From dgregor at apple.com  Wed Apr  8 17:26:47 2009
From: dgregor at apple.com (Douglas Gregor)
Date: Wed, 08 Apr 2009 22:26:47 -0000
Subject: [llvm-commits] [llvm] r68648 -
	/llvm/trunk/include/llvm/Bitcode/BitstreamReader.h
Message-ID: <200904082226.n38MQlnA007351@zion.cs.uiuc.edu>

Author: dgregor
Date: Wed Apr  8 17:26:47 2009
New Revision: 68648

URL: http://llvm.org/viewvc/llvm-project?rev=68648&view=rev
Log:
Fix BitstreamReader's GetCurrentBitNo to return the correct bit number, and stop JumpToBit from covering up its mistakes

Modified:
    llvm/trunk/include/llvm/Bitcode/BitstreamReader.h

Modified: llvm/trunk/include/llvm/Bitcode/BitstreamReader.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitstreamReader.h?rev=68648&r1=68647&r2=68648&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Bitcode/BitstreamReader.h (original)
+++ llvm/trunk/include/llvm/Bitcode/BitstreamReader.h Wed Apr  8 17:26:47 2009
@@ -115,7 +115,7 @@
 
   /// GetCurrentBitNo - Return the bit # of the bit we are reading.
   uint64_t GetCurrentBitNo() const {
-    return (NextChar-FirstChar)*CHAR_BIT + ((32-BitsInCurWord) & 31);
+    return (NextChar-FirstChar)*CHAR_BIT - BitsInCurWord;
   }
 
   /// JumpToBit - Reset the stream to the specified bit number.
@@ -131,7 +131,6 @@
 
     // Skip over any bits that are already consumed.
     if (WordBitNo) {
-      NextChar -= 4;
       Read(static_cast<unsigned>(WordBitNo));
     }
   }




From bob.wilson at apple.com  Wed Apr  8 18:46:12 2009
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 08 Apr 2009 23:46:12 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r68658 -
	/llvm-gcc-4.2/trunk/GNUmakefile
Message-ID: <200904082346.n38NkCLe010463@zion.cs.uiuc.edu>

Author: bwilson
Date: Wed Apr  8 18:46:12 2009
New Revision: 68658

URL: http://llvm.org/viewvc/llvm-project?rev=68658&view=rev
Log:
Add a default target to complain when someone attempts a srcdir==objdir build.

Modified:
    llvm-gcc-4.2/trunk/GNUmakefile

Modified: llvm-gcc-4.2/trunk/GNUmakefile
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/GNUmakefile?rev=68658&r1=68657&r2=68658&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/GNUmakefile (original)
+++ llvm-gcc-4.2/trunk/GNUmakefile Wed Apr  8 18:46:12 2009
@@ -9,6 +9,18 @@
 # The compiler targetted at this host gets built anyway, but not installed
 # unless it's listed in TARGETS.
 
+# The following default target is for the benefit of those who try to
+# build llvm-gcc in the source directory.  GNU make will prefer to use
+# this GNUmakefile instead of the Makefile generated by configure.  Since
+# builtit always invokes this makefile with an explicit target, report an
+# error for the default target and some other common gcc targets.
+.PHONY: all all-gcc all-host all-target bootstrap
+all all-gcc all-host all-target bootstrap:
+	@echo
+	@echo "Error: llvm-gcc cannot be built in the source directory."
+	@echo "Please follow the instructions in the README.LLVM file."
+	@exit 1
+
 # Include the set of standard Apple makefile definitions.
 ifndef CoreOSMakefiles
 CoreOSMakefiles = $(MAKEFILEPATH)/CoreOS




From isanbard at gmail.com  Wed Apr  8 19:10:49 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 8 Apr 2009 17:10:49 -0700
Subject: [llvm-commits] [llvm-gcc-4.2] r68658 -
	/llvm-gcc-4.2/trunk/GNUmakefile
In-Reply-To: <200904082346.n38NkCLe010463@zion.cs.uiuc.edu>
References: <200904082346.n38NkCLe010463@zion.cs.uiuc.edu>
Message-ID: <16e5fdf90904081710p2652d04dx102efa3933401956@mail.gmail.com>

On Wed, Apr 8, 2009 at 4:46 PM, Bob Wilson <bob.wilson at apple.com> wrote:
> Author: bwilson
> Date: Wed Apr ?8 18:46:12 2009
> New Revision: 68658
>
> URL: http://llvm.org/viewvc/llvm-project?rev=68658&view=rev
> Log:
> Add a default target to complain when someone attempts a srcdir==objdir build.
>
Awesome! Thanks. :-)

-bw



From bob.wilson at apple.com  Wed Apr  8 19:12:09 2009
From: bob.wilson at apple.com (Bob Wilson)
Date: Thu, 09 Apr 2009 00:12:09 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r68662 -
	/llvm-gcc-4.2/trunk/GNUmakefile
Message-ID: <200904090012.n390CA2H011593@zion.cs.uiuc.edu>

Author: bwilson
Date: Wed Apr  8 19:12:07 2009
New Revision: 68662

URL: http://llvm.org/viewvc/llvm-project?rev=68662&view=rev
Log:
Fix a typo.

Modified:
    llvm-gcc-4.2/trunk/GNUmakefile

Modified: llvm-gcc-4.2/trunk/GNUmakefile
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/GNUmakefile?rev=68662&r1=68661&r2=68662&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/GNUmakefile (original)
+++ llvm-gcc-4.2/trunk/GNUmakefile Wed Apr  8 19:12:07 2009
@@ -12,7 +12,7 @@
 # The following default target is for the benefit of those who try to
 # build llvm-gcc in the source directory.  GNU make will prefer to use
 # this GNUmakefile instead of the Makefile generated by configure.  Since
-# builtit always invokes this makefile with an explicit target, report an
+# buildit always invokes this makefile with an explicit target, report an
 # error for the default target and some other common gcc targets.
 .PHONY: all all-gcc all-host all-target bootstrap
 all all-gcc all-host all-target bootstrap:




From dalej at apple.com  Wed Apr  8 19:18:45 2009
From: dalej at apple.com (Dale Johannesen)
Date: Wed, 8 Apr 2009 17:18:45 -0700
Subject: [llvm-commits] [llvm] r68398 - in /llvm/trunk:
	lib/CodeGen/SelectionDAG/TargetLowering.cpp
	test/CodeGen/X86/and-su.ll
In-Reply-To: <200904032011.n33KBUd3005005@zion.cs.uiuc.edu>
References: <200904032011.n33KBUd3005005@zion.cs.uiuc.edu>
Message-ID: <0EC58062-36DC-420C-A5D9-056E689BC649@apple.com>

This is better than what it was doing before, but it would be valid  
and useful to shorten that load.
Perhaps when looking at the AND?

On Apr 3, 2009, at 1:11 PMPDT, Dan Gohman wrote:
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Fri Apr   
> 3 15:11:30 2009
> @@ -1464,6 +1464,7 @@
>       // in the same partial word, see if we can shorten the load.
>       if (DCI.isBeforeLegalize() &&
>           N0.getOpcode() == ISD::AND && C1 == 0 &&
> +          N0.getNode()->hasOneUse() &&
>           isa<LoadSDNode>(N0.getOperand(0)) &&
>           N0.getOperand(0).getNode()->hasOneUse() &&
>           isa<ConstantSDNode>(N0.getOperand(1))) {
>
> Added: llvm/trunk/test/CodeGen/X86/and-su.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/and-su.ll?rev=68398&view=auto
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/and-su.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/and-su.ll Fri Apr  3 15:11:30 2009
> @@ -0,0 +1,16 @@
> +; RUN: llvm-as < %s | llc -march=x86 | grep {(%} | count 1
> +
> +; Don't duplicate the load.
> +
> +define fastcc i32 @foo(i32* %p) nounwind {
> +	%t0 = load i32* %p
> +	%t2 = and i32 %t0, 10
> +	%t3 = icmp ne i32 %t2, 0
> +	br i1 %t3, label %bb63, label %bb76
> +
> +bb63:
> +	ret i32 %t2
> +
> +bb76:
> +	ret i32 0
> +}



From daniel at zuster.org  Wed Apr  8 19:33:09 2009
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 09 Apr 2009 00:33:09 -0000
Subject: [llvm-commits] [llvm] r68663 - in /llvm/trunk:
 include/llvm/System/Path.h lib/System/Path.cpp
Message-ID: <200904090033.n390X99E012363@zion.cs.uiuc.edu>

Author: ddunbar
Date: Wed Apr  8 19:33:08 2009
New Revision: 68663

URL: http://llvm.org/viewvc/llvm-project?rev=68663&view=rev
Log:
Add sys::Path::makeAbsolute().

Modified:
    llvm/trunk/include/llvm/System/Path.h
    llvm/trunk/lib/System/Path.cpp

Modified: llvm/trunk/include/llvm/System/Path.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Path.h?rev=68663&r1=68662&r2=68663&view=diff

==============================================================================
--- llvm/trunk/include/llvm/System/Path.h (original)
+++ llvm/trunk/include/llvm/System/Path.h Wed Apr  8 19:33:08 2009
@@ -459,6 +459,10 @@
       /// @brief Make the current path name unique in the file system.
       bool makeUnique( bool reuse_current /*= true*/, std::string* ErrMsg );
 
+      /// The current Path name is made absolute by prepending the
+      /// current working directory if necessary.
+      void makeAbsolute();
+
     /// @}
     /// @name Disk Mutators
     /// @{

Modified: llvm/trunk/lib/System/Path.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Path.cpp?rev=68663&r1=68662&r2=68663&view=diff

==============================================================================
--- llvm/trunk/lib/System/Path.cpp (original)
+++ llvm/trunk/lib/System/Path.cpp Wed Apr  8 19:33:08 2009
@@ -207,6 +207,18 @@
   return false;
 }
 
+void Path::makeAbsolute() {
+  if (isAbsolute())
+    return;
+
+  Path CWD = Path::GetCurrentDirectory();
+  assert(CWD.isAbsolute() && "GetCurrentDirectory returned relative path!");
+
+  CWD.appendComponent(path);
+
+  path = CWD.toString();
+}
+
 static void getPathList(const char*path, std::vector<Path>& Paths) {
   const char* at = path;
   const char* delim = strchr(at, PathSeparator);




From brukman+llvm at gmail.com  Wed Apr  8 19:42:39 2009
From: brukman+llvm at gmail.com (Misha Brukman)
Date: Thu, 09 Apr 2009 00:42:39 -0000
Subject: [llvm-commits] [llvm] r68664 -
	/llvm/trunk/unittests/VMCore/ConstantsTest.cpp
Message-ID: <200904090042.n390geOC012670@zion.cs.uiuc.edu>

Author: brukman
Date: Wed Apr  8 19:42:37 2009
New Revision: 68664

URL: http://llvm.org/viewvc/llvm-project?rev=68664&view=rev
Log:
Fixed compiler warning.

Modified:
    llvm/trunk/unittests/VMCore/ConstantsTest.cpp

Modified: llvm/trunk/unittests/VMCore/ConstantsTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/VMCore/ConstantsTest.cpp?rev=68664&r1=68663&r2=68664&view=diff

==============================================================================
--- llvm/trunk/unittests/VMCore/ConstantsTest.cpp (original)
+++ llvm/trunk/unittests/VMCore/ConstantsTest.cpp Wed Apr  8 19:42:37 2009
@@ -18,7 +18,7 @@
   const IntegerType* Int1 = IntegerType::get(1);
   Constant* One = ConstantInt::get(Int1, 1, true);
   Constant* Zero = ConstantInt::get(Int1, 0);
-  Constant* NegOne = ConstantInt::get(Int1, -1, true);
+  Constant* NegOne = ConstantInt::get(Int1, static_cast<uint64_t>(-1), true);
   Constant* Undef = UndefValue::get(Int1);
 
   // Input:  @b = constant i1 add(i1 1 , i1 1)




From gohman at apple.com  Wed Apr  8 21:06:10 2009
From: gohman at apple.com (Dan Gohman)
Date: Thu, 09 Apr 2009 02:06:10 -0000
Subject: [llvm-commits] [llvm] r68666 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <200904090206.n3926Bw8015392@zion.cs.uiuc.edu>

Author: djg
Date: Wed Apr  8 21:06:09 2009
New Revision: 68666

URL: http://llvm.org/viewvc/llvm-project?rev=68666&view=rev
Log:
Fix grammaros in comments.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=68666&r1=68665&r2=68666&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Apr  8 21:06:09 2009
@@ -7264,12 +7264,12 @@
 }
 
 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
-  // x86-64 has implicitly zero-extends 32-bit results in 64-bit registers.
+  // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
   return Ty1 == Type::Int32Ty && Ty2 == Type::Int64Ty && Subtarget->is64Bit();
 }
 
 bool X86TargetLowering::isZExtFree(MVT VT1, MVT VT2) const {
-  // x86-64 has implicitly zero-extends 32-bit results in 64-bit registers.
+  // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
   return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
 }
 




From gohman at apple.com  Wed Apr  8 21:33:36 2009
From: gohman at apple.com (Dan Gohman)
Date: Thu, 09 Apr 2009 02:33:36 -0000
Subject: [llvm-commits] [llvm] r68667 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
Message-ID: <200904090233.n392XaQ1016369@zion.cs.uiuc.edu>

Author: djg
Date: Wed Apr  8 21:33:36 2009
New Revision: 68667

URL: http://llvm.org/viewvc/llvm-project?rev=68667&view=rev
Log:
Don't copy the operand of a SwitchInst into virtual registers as
eagerly. This helps avoid CopyToReg nodes in some cases where they
aren't needed, and also helps subsequent optimizer heuristics
in cases where the extra nodes would cause the node to appear
to have multiple results. This doesn't have a significant impact
currently; it'll help an upcoming change.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=68667&r1=68666&r2=68667&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Wed Apr  8 21:33:36 2009
@@ -243,9 +243,7 @@
   if (isa<PHINode>(I)) return true;
   BasicBlock *BB = I->getParent();
   for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
-    if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
-        // FIXME: Remove switchinst special case.
-        isa<SwitchInst>(*UI))
+    if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
       return true;
   return false;
 }
@@ -1640,6 +1638,9 @@
     if (I != E-1) {
       FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
       CurMF->insert(BBI, FallThrough);
+
+      // Put SV in a virtual register to make it available from the new blocks.
+      ExportFromCurrentBlock(SV);
     } else {
       // If the last case doesn't match, go to the default block.
       FallThrough = Default;
@@ -1874,6 +1875,9 @@
     TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
     CurMF->insert(BBI, TrueBB);
     WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
+
+    // Put SV in a virtual register to make it available from the new blocks.
+    ExportFromCurrentBlock(SV);
   }
 
   // Similar to the optimization above, if the Value being switched on is
@@ -1888,6 +1892,9 @@
     FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
     CurMF->insert(BBI, FalseBB);
     WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
+
+    // Put SV in a virtual register to make it available from the new blocks.
+    ExportFromCurrentBlock(SV);
   }
 
   // Create a CaseBlock record representing a conditional branch to
@@ -2013,6 +2020,9 @@
     BTC.push_back(BitTestCase(CasesBits[i].Mask,
                               CaseBB,
                               CasesBits[i].BB));
+
+    // Put SV in a virtual register to make it available from the new blocks.
+    ExportFromCurrentBlock(SV);
   }
 
   BitTestBlock BTB(lowBound, cmpRange, SV,




From nicholas at mxc.ca  Wed Apr  8 22:10:04 2009
From: nicholas at mxc.ca (Nick Lewycky)
Date: Thu, 09 Apr 2009 03:10:04 -0000
Subject: [llvm-commits] [llvm] r68668 -
	/llvm/trunk/unittests/VMCore/MetadataTest.cpp
Message-ID: <200904090310.n393A4gb017720@zion.cs.uiuc.edu>

Author: nicholas
Date: Wed Apr  8 22:10:03 2009
New Revision: 68668

URL: http://llvm.org/viewvc/llvm-project?rev=68668&view=rev
Log:
Fix pointer casting problem.

Modified:
    llvm/trunk/unittests/VMCore/MetadataTest.cpp

Modified: llvm/trunk/unittests/VMCore/MetadataTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/VMCore/MetadataTest.cpp?rev=68668&r1=68667&r2=68668&view=diff

==============================================================================
--- llvm/trunk/unittests/VMCore/MetadataTest.cpp (original)
+++ llvm/trunk/unittests/VMCore/MetadataTest.cpp Wed Apr  8 22:10:03 2009
@@ -73,7 +73,8 @@
   V.push_back(s2);
 
   MDNode *n1 = MDNode::get(&V[0], 3);
-  MDNode *n2 = MDNode::get((Constant**)&n1, 1);
+  Constant *const c1 = n1;
+  MDNode *n2 = MDNode::get(&c1, 1);
   MDNode *n3 = MDNode::get(&V[0], 3);
   EXPECT_NE(n1, n2);
   EXPECT_EQ(n1, n3);




From resistor at mac.com  Wed Apr  8 22:50:18 2009
From: resistor at mac.com (Owen Anderson)
Date: Thu, 09 Apr 2009 03:50:18 -0000
Subject: [llvm-commits] [llvm] r68669 - in /llvm/trunk:
 include/llvm/Target/TargetRegisterInfo.h lib/Target/TargetRegisterInfo.cpp
 utils/TableGen/RegisterInfoEmitter.cpp
Message-ID: <200904090350.n393oIku018939@zion.cs.uiuc.edu>

Author: resistor
Date: Wed Apr  8 22:50:16 2009
New Revision: 68669

URL: http://llvm.org/viewvc/llvm-project?rev=68669&view=rev
Log:
Convert TargetRegisterInfo's super-register checking to use a pre-computed hash table just like subregister checking does.

Modified:
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
    llvm/trunk/lib/Target/TargetRegisterInfo.cpp
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=68669&r1=68668&r2=68669&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Wed Apr  8 22:50:16 2009
@@ -224,6 +224,8 @@
 protected:
   const unsigned* SubregHash;
   const unsigned SubregHashSize;
+  const unsigned* SuperregHash;
+  const unsigned SuperregHashSize;
 public:
   typedef const TargetRegisterClass * const * regclass_iterator;
 private:
@@ -240,7 +242,9 @@
                      int CallFrameSetupOpcode = -1,
                      int CallFrameDestroyOpcode = -1,
                      const unsigned* subregs = 0,
-                     const unsigned subregsize = 0);
+                     const unsigned subregsize = 0,
+		     const unsigned* superregs = 0,
+		     const unsigned superregsize = 0);
   virtual ~TargetRegisterInfo();
 public:
 
@@ -379,8 +383,18 @@
   /// isSuperRegister - Returns true if regB is a super-register of regA.
   ///
   bool isSuperRegister(unsigned regA, unsigned regB) const {
-    for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
-      if (*SR == regB) return true;
+    // SuperregHash is a simple quadratically probed hash table.
+    size_t index = (regA + regB * 37) & (SuperregHashSize-1);
+    unsigned ProbeAmt = 2;
+    while (SuperregHash[index*2] != 0 &&
+           SuperregHash[index*2+1] != 0) {
+      if (SuperregHash[index*2] == regA && SuperregHash[index*2+1] == regB)
+        return true;
+      
+      index = (index + ProbeAmt) & (SuperregHashSize-1);
+      ProbeAmt += 2;
+    }
+    
     return false;
   }
 

Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegisterInfo.cpp?rev=68669&r1=68668&r2=68669&view=diff

==============================================================================
--- llvm/trunk/lib/Target/TargetRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetRegisterInfo.cpp Wed Apr  8 22:50:16 2009
@@ -23,9 +23,11 @@
 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
                              regclass_iterator RCB, regclass_iterator RCE,
                              int CFSO, int CFDO,
-                             const unsigned* subregs, const unsigned subregsize)
-  : SubregHash(subregs), SubregHashSize(subregsize), Desc(D), NumRegs(NR),
-    RegClassBegin(RCB), RegClassEnd(RCE) {
+			     const unsigned* subregs, const unsigned subregsize,
+			 const unsigned* superregs, const unsigned superregsize)
+  : SubregHash(subregs), SubregHashSize(subregsize),
+    SuperregHash(superregs), SuperregHashSize(superregsize),
+    Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) {
   assert(NumRegs < FirstVirtualRegister &&
          "Target has too many physical registers!");
 

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=68669&r1=68668&r2=68669&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Wed Apr  8 22:50:16 2009
@@ -463,6 +463,83 @@
   
   delete [] SubregHashTable;
 
+
+  // Print the SuperregHashTable, a simple quadratically probed
+  // hash table for determining if a register is a super-register
+  // of another register.
+  unsigned NumSupRegs = 0;
+  RegNo.clear();
+  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+    RegNo[Regs[i].TheDef] = i;
+    NumSupRegs += RegisterSuperRegs[Regs[i].TheDef].size();
+  }
+  
+  unsigned SuperregHashTableSize = 2 * NextPowerOf2(2 * NumSupRegs);
+  unsigned* SuperregHashTable = new unsigned[2 * SuperregHashTableSize];
+  std::fill(SuperregHashTable, SuperregHashTable + 2 * SuperregHashTableSize, ~0U);
+  
+  hashMisses = 0;
+  
+  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+    Record* R = Regs[i].TheDef;
+    for (std::set<Record*>::iterator I = RegisterSuperRegs[R].begin(),
+         E = RegisterSuperRegs[R].end(); I != E; ++I) {
+      Record* RJ = *I;
+      // We have to increase the indices of both registers by one when
+      // computing the hash because, in the generated code, there
+      // will be an extra empty slot at register 0.
+      size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SuperregHashTableSize-1);
+      unsigned ProbeAmt = 2;
+      while (SuperregHashTable[index*2] != ~0U &&
+             SuperregHashTable[index*2+1] != ~0U) {
+        index = (index + ProbeAmt) & (SuperregHashTableSize-1);
+        ProbeAmt += 2;
+        
+        hashMisses++;
+      }
+      
+      SuperregHashTable[index*2] = i;
+      SuperregHashTable[index*2+1] = RegNo[RJ];
+    }
+  }
+  
+  OS << "\n\n  // Number of hash collisions: " << hashMisses << "\n";
+  
+  if (SuperregHashTableSize) {
+    std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
+    
+    OS << "  const unsigned SuperregHashTable[] = { ";
+    for (unsigned i = 0; i < SuperregHashTableSize - 1; ++i) {
+      if (i != 0)
+        // Insert spaces for nice formatting.
+        OS << "                                       ";
+      
+      if (SuperregHashTable[2*i] != ~0U) {
+        OS << getQualifiedName(Regs[SuperregHashTable[2*i]].TheDef) << ", "
+           << getQualifiedName(Regs[SuperregHashTable[2*i+1]].TheDef) << ", \n";
+      } else {
+        OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
+      }
+    }
+    
+    unsigned Idx = SuperregHashTableSize*2-2;
+    if (SuperregHashTable[Idx] != ~0U) {
+      OS << "                                       "
+         << getQualifiedName(Regs[SuperregHashTable[Idx]].TheDef) << ", "
+         << getQualifiedName(Regs[SuperregHashTable[Idx+1]].TheDef) << " };\n";
+    } else {
+      OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
+    }
+    
+    OS << "  const unsigned SuperregHashTableSize = "
+       << SuperregHashTableSize << ";\n";
+  } else {
+    OS << "  const unsigned SuperregHashTable[] = { ~0U, ~0U };\n"
+       << "  const unsigned SuperregHashTableSize = 1;\n";
+  }
+  
+  delete [] SuperregHashTable;
+
   if (!RegisterAliases.empty())
     OS << "\n\n  // Register Alias Sets...\n";
 
@@ -599,7 +676,8 @@
      << "  : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1
      << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
      << "                 CallFrameSetupOpcode, CallFrameDestroyOpcode,\n"
-     << "                 SubregHashTable, SubregHashTableSize) {\n"
+     << "                 SubregHashTable, SubregHashTableSize,\n"
+     << "                 SuperregHashTable, SuperregHashTableSize) {\n"
      << "}\n\n";
 
   // Collect all information about dwarf register numbers




From gohman at apple.com  Wed Apr  8 22:51:29 2009
From: gohman at apple.com (Dan Gohman)
Date: Thu, 09 Apr 2009 03:51:29 -0000
Subject: [llvm-commits] [llvm] r68670 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
 test/CodeGen/X86/2008-09-10-SpillerBug2.ll test/CodeGen/X86/anyext-uses.ll
 test/CodeGen/X86/switch-zextload.ll
Message-ID: <200904090351.n393pTWH019017@zion.cs.uiuc.edu>

Author: djg
Date: Wed Apr  8 22:51:29 2009
New Revision: 68670

URL: http://llvm.org/viewvc/llvm-project?rev=68670&view=rev
Log:
Generalize ExtendUsesToFormExtLoad to be usable for ANY_EXTEND,
in addition to ZERO_EXTEND and SIGN_EXTEND. Fix a bug in the
way it checked for live-out values, and simplify the way it
find users by using SDNode::use_iterator's (relatively) new
features. Also, make it slightly more permissive on targets
with free truncates.

In SelectionDAGBuild, avoid creating ANY_EXTEND nodes that are
larger than necessary. If the target's SwitchAmountTy has
enough bits, use it. This exposes the truncate to optimization
early, enabling more optimizations.

Added:
    llvm/trunk/test/CodeGen/X86/anyext-uses.ll
    llvm/trunk/test/CodeGen/X86/switch-zextload.ll
Removed:
    llvm/trunk/test/CodeGen/X86/2008-09-10-SpillerBug2.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=68670&r1=68669&r2=68670&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Apr  8 22:51:29 2009
@@ -2874,7 +2874,7 @@
 }
 
 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
-// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))"
+// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
 // transformation. Returns true if extension are possible and the above
 // mentioned transformation is profitable.
 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
@@ -2889,8 +2889,10 @@
     SDNode *User = *UI;
     if (User == N)
       continue;
+    if (UI.getUse().getResNo() != N0.getResNo())
+      continue;
     // FIXME: Only extend SETCC N, N and SETCC N, c for now.
-    if (User->getOpcode() == ISD::SETCC) {
+    if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
       ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
       if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
         // Sign bits will be lost after a zext.
@@ -2906,32 +2908,25 @@
       }
       if (Add)
         ExtendNodes.push_back(User);
-    } else {
-      for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
-        SDValue UseOp = User->getOperand(i);
-        if (UseOp == N0) {
-          // If truncate from extended type to original load type is free
-          // on this target, then it's ok to extend a CopyToReg.
-          if (isTruncFree && User->getOpcode() == ISD::CopyToReg)
-            HasCopyToRegUses = true;
-          else
-            return false;
-        }
-      }
+      continue;
     }
+    // If truncates aren't free and there are users we can't
+    // extend, it isn't worthwhile.
+    if (!isTruncFree)
+      return false;
+    // Remember if this value is live-out.
+    if (User->getOpcode() == ISD::CopyToReg)
+      HasCopyToRegUses = true;
   }
 
   if (HasCopyToRegUses) {
     bool BothLiveOut = false;
     for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
          UI != UE; ++UI) {
-      SDNode *User = *UI;
-      for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
-        SDValue UseOp = User->getOperand(i);
-        if (UseOp.getNode() == N && UseOp.getResNo() == 0) {
-          BothLiveOut = true;
-          break;
-        }
+      SDUse &Use = UI.getUse();
+      if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
+        BothLiveOut = true;
+        break;
       }
     }
     if (BothLiveOut)
@@ -3013,8 +3008,8 @@
       DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
     if (DoXform) {
       LoadSDNode *LN0 = cast<LoadSDNode>(N0);
-      SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(),
-                                       VT, LN0->getChain(),
+      SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
+                                       LN0->getChain(),
                                        LN0->getBasePtr(), LN0->getSrcValue(),
                                        LN0->getSrcValueOffset(),
                                        N0.getValueType(),
@@ -3034,8 +3029,8 @@
           if (SOp == Trunc)
             Ops.push_back(ExtLoad);
           else
-            Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
-                                      VT, SOp));
+            Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND,
+                                      N->getDebugLoc(), VT, SOp));
         }
 
         Ops.push_back(SetCC->getOperand(2));
@@ -3278,26 +3273,48 @@
   }
 
   // fold (aext (load x)) -> (aext (truncate (extload x)))
-  if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
+  if (ISD::isNON_EXTLoad(N0.getNode()) &&
       ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
        TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
-    LoadSDNode *LN0 = cast<LoadSDNode>(N0);
-    SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
-                                     LN0->getChain(),
-                                     LN0->getBasePtr(), LN0->getSrcValue(),
-                                     LN0->getSrcValueOffset(),
-                                     N0.getValueType(),
-                                     LN0->isVolatile(), LN0->getAlignment());
-    CombineTo(N, ExtLoad);
-    // Redirect any chain users to the new load.
-    DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1),
-                                  SDValue(ExtLoad.getNode(), 1));
-    // If any node needs the original loaded value, recompute it.
-    if (!LN0->use_empty())
-      CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
-                                 N0.getValueType(), ExtLoad),
-                ExtLoad.getValue(1));
-    return SDValue(N, 0);   // Return N so it doesn't get rechecked!
+    bool DoXform = true;
+    SmallVector<SDNode*, 4> SetCCs;
+    if (!N0.hasOneUse())
+      DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
+    if (DoXform) {
+      LoadSDNode *LN0 = cast<LoadSDNode>(N0);
+      SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
+                                       LN0->getChain(),
+                                       LN0->getBasePtr(), LN0->getSrcValue(),
+                                       LN0->getSrcValueOffset(),
+                                       N0.getValueType(),
+                                       LN0->isVolatile(), LN0->getAlignment());
+      CombineTo(N, ExtLoad);
+      SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
+                                  N0.getValueType(), ExtLoad);
+      CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
+
+      // Extend SetCC uses if necessary.
+      for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
+        SDNode *SetCC = SetCCs[i];
+        SmallVector<SDValue, 4> Ops;
+
+        for (unsigned j = 0; j != 2; ++j) {
+          SDValue SOp = SetCC->getOperand(j);
+          if (SOp == Trunc)
+            Ops.push_back(ExtLoad);
+          else
+            Ops.push_back(DAG.getNode(ISD::ANY_EXTEND,
+                                      N->getDebugLoc(), VT, SOp));
+        }
+
+        Ops.push_back(SetCC->getOperand(2));
+        CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
+                                     SetCC->getValueType(0),
+                                     &Ops[0], Ops.size()));
+      }
+
+      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
+    }
   }
 
   // fold (aext (zextload x)) -> (aext (truncate (zextload x)))

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=68670&r1=68669&r2=68670&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Wed Apr  8 22:51:29 2009
@@ -2190,8 +2190,24 @@
 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
   SDValue Op1 = getValue(I.getOperand(0));
   SDValue Op2 = getValue(I.getOperand(1));
-  if (!isa<VectorType>(I.getType())) {
-    if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
+  if (!isa<VectorType>(I.getType()) &&
+      Op2.getValueType() != TLI.getShiftAmountTy()) {
+    // If the operand is smaller than the shift count type, promote it.
+    if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
+      Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
+                        TLI.getShiftAmountTy(), Op2);
+    // If the operand is larger than the shift count type but the shift
+    // count type has enough bits to represent any shift value, truncate
+    // it now. This is a common case and it exposes the truncate to
+    // optimization early.
+    else if (TLI.getShiftAmountTy().getSizeInBits() >=
+             Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
+      Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
+                        TLI.getShiftAmountTy(), Op2);
+    // Otherwise we'll need to temporarily settle for some other
+    // convenient type; type legalization will make adjustments as
+    // needed.
+    else if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
       Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
                         TLI.getPointerTy(), Op2);
     else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))

Removed: llvm/trunk/test/CodeGen/X86/2008-09-10-SpillerBug2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-09-10-SpillerBug2.ll?rev=68669&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-09-10-SpillerBug2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-09-10-SpillerBug2.ll (removed)
@@ -1,40 +0,0 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep movw | not grep %e.x
-; PR2681
-
- at g_491 = external global i32		; <i32*> [#uses=1]
- at g_897 = external global i16		; <i16*> [#uses=1]
-
-define i32 @func_7(i16 signext %p_9) nounwind {
-entry:
-	%p_9.addr = alloca i16		; <i16*> [#uses=2]
-	%l_1122 = alloca i16, align 2		; <i16*> [#uses=1]
-	%l_1128 = alloca i32, align 4		; <i32*> [#uses=1]
-	%l_1129 = alloca i32, align 4		; <i32*> [#uses=1]
-	%l_1130 = alloca i32, align 4		; <i32*> [#uses=1]
-	%tmp14 = load i16* %l_1122		; <i16> [#uses=1]
-	%conv15 = sext i16 %tmp14 to i32		; <i32> [#uses=1]
-	%tmp16 = load i16* %p_9.addr		; <i16> [#uses=1]
-	%conv17 = sext i16 %tmp16 to i32		; <i32> [#uses=1]
-	%xor = xor i32 %conv15, %conv17		; <i32> [#uses=1]
-	%tmp18 = load i32* null		; <i32> [#uses=1]
-	%or = or i32 %xor, %tmp18		; <i32> [#uses=1]
-	%conv19 = trunc i32 %or to i16		; <i16> [#uses=1]
-	%tmp28 = load i16* %p_9.addr		; <i16> [#uses=1]
-	%tmp33 = load i16* @g_897		; <i16> [#uses=1]
-	%tmp34 = load i32* @g_491		; <i32> [#uses=1]
-	%conv35 = trunc i32 %tmp34 to i16		; <i16> [#uses=1]
-	%tmp36 = load i16* null		; <i16> [#uses=1]
-	%conv37 = trunc i16 %tmp36 to i8		; <i8> [#uses=1]
-	%tmp38 = load i32* %l_1128		; <i32> [#uses=1]
-	%conv39 = sext i32 %tmp38 to i64		; <i64> [#uses=1]
-	%tmp42 = load i32* %l_1129		; <i32> [#uses=1]
-	%conv43 = trunc i32 %tmp42 to i16		; <i16> [#uses=1]
-	%tmp44 = load i32* %l_1130		; <i32> [#uses=1]
-	%conv45 = sext i32 %tmp44 to i64		; <i64> [#uses=1]
-	%call46 = call i32 @func_18( i16 zeroext 0, i16 zeroext 0, i16 zeroext %tmp33, i16 zeroext %conv35, i8 zeroext %conv37, i64 %conv39, i32 0, i16 zeroext %conv43, i64 %conv45, i8 zeroext 1 )		; <i32> [#uses=0]
-	%call48 = call i32 @func_18( i16 zeroext 0, i16 zeroext 0, i16 zeroext 0, i16 zeroext 1, i8 zeroext 0, i64 0, i32 1, i16 zeroext %tmp28, i64 0, i8 zeroext 1 )		; <i32> [#uses=0]
-	%call50 = call i32 @func_18( i16 zeroext 1, i16 zeroext 0, i16 zeroext 0, i16 zeroext 1, i8 zeroext 0, i64 0, i32 1, i16 zeroext %conv19, i64 0, i8 zeroext 1 )		; <i32> [#uses=0]
-	ret i32 undef
-}
-
-declare i32 @func_18(i16 zeroext, i16 zeroext, i16 zeroext, i16 zeroext, i8 zeroext, i64, i32, i16 zeroext, i64, i8 zeroext)

Added: llvm/trunk/test/CodeGen/X86/anyext-uses.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/anyext-uses.ll?rev=68670&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/anyext-uses.ll (added)
+++ llvm/trunk/test/CodeGen/X86/anyext-uses.ll Wed Apr  8 22:51:29 2009
@@ -0,0 +1,47 @@
+; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: grep mov %t | count 8
+; RUN: not grep implicit %t
+
+; Avoid partial register updates; don't define an i8 register and read
+; the i32 super-register.
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin9.6"
+	%struct.RC4_KEY = type { i8, i8, [256 x i8] }
+
+define void @foo(%struct.RC4_KEY* nocapture %key, i64 %len, i8* %indata, i8* %outdata) nounwind {
+entry:
+	br label %bb24
+
+bb24:		; preds = %bb24, %entry
+	%0 = load i8* null, align 1		; <i8> [#uses=1]
+	%1 = zext i8 %0 to i64		; <i64> [#uses=1]
+	%2 = shl i64 %1, 32		; <i64> [#uses=1]
+	%3 = getelementptr %struct.RC4_KEY* %key, i64 0, i32 2, i64 0		; <i8*> [#uses=1]
+	%4 = load i8* %3, align 1		; <i8> [#uses=2]
+	%5 = add i8 %4, 0		; <i8> [#uses=2]
+	%6 = zext i8 %5 to i64		; <i64> [#uses=0]
+	%7 = load i8* null, align 1		; <i8> [#uses=1]
+	%8 = zext i8 %4 to i32		; <i32> [#uses=1]
+	%9 = zext i8 %7 to i32		; <i32> [#uses=1]
+	%10 = add i32 %9, %8		; <i32> [#uses=1]
+	%11 = and i32 %10, 255		; <i32> [#uses=1]
+	%12 = zext i32 %11 to i64		; <i64> [#uses=1]
+	%13 = getelementptr %struct.RC4_KEY* %key, i64 0, i32 2, i64 %12		; <i8*> [#uses=1]
+	%14 = load i8* %13, align 1		; <i8> [#uses=1]
+	%15 = zext i8 %14 to i64		; <i64> [#uses=1]
+	%16 = shl i64 %15, 48		; <i64> [#uses=1]
+	%17 = getelementptr %struct.RC4_KEY* %key, i64 0, i32 2, i64 0		; <i8*> [#uses=1]
+	%18 = load i8* %17, align 1		; <i8> [#uses=2]
+	%19 = add i8 %18, %5		; <i8> [#uses=1]
+	%20 = zext i8 %19 to i64		; <i64> [#uses=1]
+	%21 = getelementptr %struct.RC4_KEY* %key, i64 0, i32 2, i64 %20		; <i8*> [#uses=1]
+	store i8 %18, i8* %21, align 1
+	%22 = or i64 0, %2		; <i64> [#uses=1]
+	%23 = or i64 %22, 0		; <i64> [#uses=1]
+	%24 = or i64 %23, %16		; <i64> [#uses=1]
+	%25 = or i64 %24, 0		; <i64> [#uses=1]
+	%26 = xor i64 %25, 0		; <i64> [#uses=1]
+	store i64 %26, i64* null, align 8
+	br label %bb24
+}

Added: llvm/trunk/test/CodeGen/X86/switch-zextload.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/switch-zextload.ll?rev=68670&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/switch-zextload.ll (added)
+++ llvm/trunk/test/CodeGen/X86/switch-zextload.ll Wed Apr  8 22:51:29 2009
@@ -0,0 +1,34 @@
+; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 1
+
+; Do zextload, instead of a load and a separate zext.
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.6"
+	%struct.move_s = type { i32, i32, i32, i32, i32, i32 }
+	%struct.node_t = type { i8, i8, i8, i8, i32, i32, %struct.node_t**, %struct.node_t*, %struct.move_s }
+
+define fastcc void @set_proof_and_disproof_numbers(%struct.node_t* nocapture %node) nounwind {
+entry:
+	%0 = load i8* null, align 1		; <i8> [#uses=1]
+	switch i8 %0, label %return [
+		i8 2, label %bb31
+		i8 0, label %bb80
+		i8 1, label %bb82
+		i8 3, label %bb84
+	]
+
+bb31:		; preds = %entry
+	unreachable
+
+bb80:		; preds = %entry
+	ret void
+
+bb82:		; preds = %entry
+	ret void
+
+bb84:		; preds = %entry
+	ret void
+
+return:		; preds = %entry
+	ret void
+}




From sanjiv.gupta at microchip.com  Wed Apr  8 23:03:44 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Thu, 09 Apr 2009 04:03:44 -0000
Subject: [llvm-commits] [llvm] r68671 -
	/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
Message-ID: <200904090403.n3943iG5019472@zion.cs.uiuc.edu>

Author: sgupta
Date: Wed Apr  8 23:03:43 2009
New Revision: 68671

URL: http://llvm.org/viewvc/llvm-project?rev=68671&view=rev
Log:
r68576 unconverd a bug in PIC16 port (Thanks to Dan Gohman) where we were custom lowering an ADD to ADDC.

Modified:
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=68671&r1=68670&r2=68671&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Wed Apr  8 23:03:43 2009
@@ -1359,21 +1359,26 @@
     // Put one value on stack.
     SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
     
+    // ADDC and ADDE produces two results.
     SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
 
+    // ADDE has three operands, the last one is a flag.
     if (Op.getOpcode() == ISD::ADDE)
       return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
                          NewVal, Op.getOperand(2));
-    else
+    // ADDC has two operands.
+    else if (Op.getOpcode() == ISD::ADDC)
       return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
                          NewVal);
+    // ADD it is. It produces only one result.
+    else
+      return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
+                         NewVal);
   }
-  else if (Op.getOpcode() == ISD::ADD) {
+  else if (Op.getOpcode() == ISD::ADD)
     return Op;
-  }
-  else {
+  else
     return SDValue();
-  }
 }
 
 SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) {




From kremenek at apple.com  Wed Apr  8 23:34:18 2009
From: kremenek at apple.com (Ted Kremenek)
Date: Thu, 09 Apr 2009 04:34:18 -0000
Subject: [llvm-commits] [llvm] r68673 - /llvm/tags/checker/checker-0.184/
Message-ID: <200904090434.n394YIqL020624@zion.cs.uiuc.edu>

Author: kremenek
Date: Wed Apr  8 23:34:17 2009
New Revision: 68673

URL: http://llvm.org/viewvc/llvm-project?rev=68673&view=rev
Log:
Tagging checker-0.184.

Added:
    llvm/tags/checker/checker-0.184/
      - copied from r68672, llvm/trunk/



From kremenek at apple.com  Thu Apr  9 00:35:03 2009
From: kremenek at apple.com (Ted Kremenek)
Date: Thu, 09 Apr 2009 05:35:03 -0000
Subject: [llvm-commits] [llvm] r68681 - /llvm/tags/checker/checker-0.184/
Message-ID: <200904090535.n395Z4Sn022625@zion.cs.uiuc.edu>

Author: kremenek
Date: Thu Apr  9 00:35:03 2009
New Revision: 68681

URL: http://llvm.org/viewvc/llvm-project?rev=68681&view=rev
Log:
Removing checker-0.184.

Removed:
    llvm/tags/checker/checker-0.184/



From sabre at nondot.org  Thu Apr  9 00:56:58 2009
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 09 Apr 2009 05:56:58 -0000
Subject: [llvm-commits] [llvm] r68684 -
	/llvm/trunk/include/llvm/Analysis/SparsePropagation.h
Message-ID: <200904090556.n395uxix023434@zion.cs.uiuc.edu>

Author: lattner
Date: Thu Apr  9 00:56:58 2009
New Revision: 68684

URL: http://llvm.org/viewvc/llvm-project?rev=68684&view=rev
Log:
add an accessor method, patch by John McCall!

Modified:
    llvm/trunk/include/llvm/Analysis/SparsePropagation.h

Modified: llvm/trunk/include/llvm/Analysis/SparsePropagation.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/SparsePropagation.h?rev=68684&r1=68683&r2=68684&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Analysis/SparsePropagation.h (original)
+++ llvm/trunk/include/llvm/Analysis/SparsePropagation.h Thu Apr  9 00:56:58 2009
@@ -163,6 +163,13 @@
   /// lattice, not when querying it.
   bool isEdgeFeasible(BasicBlock *From, BasicBlock *To,
                       bool AggressiveUndef = false);
+
+  /// isBlockExecutable - Return true if there are any known feasible
+  /// edges into the basic block.  This is generally only useful when
+  /// querying the lattice.
+  bool isBlockExecutable(BasicBlock *BB) const {
+    return BBExecutable.count(BB);
+  }
   
 private:
   /// UpdateState - When the state for some instruction is potentially updated,




From kremenek at apple.com  Thu Apr  9 01:07:52 2009
From: kremenek at apple.com (Ted Kremenek)
Date: Thu, 09 Apr 2009 06:07:52 -0000
Subject: [llvm-commits] [llvm] r68688 - /llvm/tags/checker/checker-0.184/
Message-ID: <200904090607.n3967q03023887@zion.cs.uiuc.edu>

Author: kremenek
Date: Thu Apr  9 01:07:52 2009
New Revision: 68688

URL: http://llvm.org/viewvc/llvm-project?rev=68688&view=rev
Log:
Tagging checker-0.184.

Added:
    llvm/tags/checker/checker-0.184/
      - copied from r68687, llvm/trunk/



From sabre at nondot.org  Thu Apr  9 01:10:52 2009
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 09 Apr 2009 06:10:52 -0000
Subject: [llvm-commits] [llvm] r68690 -
	/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Message-ID: <200904090610.n396AsLw024013@zion.cs.uiuc.edu>

Author: lattner
Date: Thu Apr  9 01:10:51 2009
New Revision: 68690

URL: http://llvm.org/viewvc/llvm-project?rev=68690&view=rev
Log:
Fix code size computation on x86-64, patch by Zoltan Varga!

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=68690&r1=68689&r2=68690&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Apr  9 01:10:51 2009
@@ -2732,7 +2732,7 @@
   unsigned BaseReg = Base.getReg();
 
   // Is a SIB byte needed?
-  if (IndexReg.getReg() == 0 &&
+  if ((!Is64BitMode || DispForReloc) && IndexReg.getReg() == 0 &&
       (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
     if (BaseReg == 0) {  // Just a displacement?
       // Emit special case [disp32] encoding




From sanjiv.gupta at microchip.com  Thu Apr  9 05:29:42 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Thu, 09 Apr 2009 10:29:42 -0000
Subject: [llvm-commits] [llvm] r68705 -
	/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
Message-ID: <200904091029.n39ATjFX012356@zion.cs.uiuc.edu>

Author: sgupta
Date: Thu Apr  9 05:29:32 2009
New Revision: 68705

URL: http://llvm.org/viewvc/llvm-project?rev=68705&view=rev
Log:
Arguments to indirect calls were being passed incorrectly. They are not fixed to start after return value.

Modified:
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=68705&r1=68704&r2=68705&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Thu Apr  9 05:29:32 2009
@@ -877,7 +877,10 @@
   std::vector<SDValue> Ops;
   SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
   SDValue Arg, StoreRet;
-  for (unsigned i=0; i<NumOps; i++) {
+
+  // For PIC16 ABI the arguments come after the return value. 
+  unsigned RetVals = TheCall->getNumRetVals();
+  for (unsigned i = 0, ArgOffset = RetVals; i < NumOps; i++) {
     // Get the arguments
     Arg = TheCall->getArg(i);
     Ops.clear();
@@ -885,13 +888,14 @@
     Ops.push_back(Arg);
     Ops.push_back(DataAddr_Lo);
     Ops.push_back(DataAddr_Hi);
-    Ops.push_back(DAG.getConstant(i, MVT::i8));
+    Ops.push_back(DAG.getConstant(ArgOffset, MVT::i8));
     Ops.push_back(InFlag);
 
     StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
 
     Chain = getChain(StoreRet);
     InFlag = getOutFlag(StoreRet);
+    ArgOffset++;
   }
   return Chain;
 }




From brukman+llvm at gmail.com  Thu Apr  9 09:57:04 2009
From: brukman+llvm at gmail.com (Misha Brukman)
Date: Thu, 09 Apr 2009 14:57:04 -0000
Subject: [llvm-commits] [llvm] r68708 - /llvm/trunk/Makefile.rules
Message-ID: <200904091457.n39Ev5PC021643@zion.cs.uiuc.edu>

Author: brukman
Date: Thu Apr  9 09:57:00 2009
New Revision: 68708

URL: http://llvm.org/viewvc/llvm-project?rev=68708&view=rev
Log:
Make sure to rebuild dependencies for the `check' and `unittests' targets so
we're not testing out-of-date code.  This also makes "make check" and
"make unittests" work out-of-the box right after the configure step, without
requiring the user to run "make tools-only" or "make libs-only".

Tested on Linux/x86_64 and Darwin/x86.

Modified:
    llvm/trunk/Makefile.rules

Modified: llvm/trunk/Makefile.rules
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=68708&r1=68707&r2=68708&view=diff

==============================================================================
--- llvm/trunk/Makefile.rules (original)
+++ llvm/trunk/Makefile.rules Thu Apr  9 09:57:00 2009
@@ -1547,7 +1547,7 @@
 # CHECK: Running the test suite
 ###############################################################################
 
-check::
+check:: tools-only
 	$(Verb) if test -d "$(PROJ_OBJ_ROOT)/test" ; then \
 	  if test -f "$(PROJ_OBJ_ROOT)/test/Makefile" ; then \
 	    $(EchoCmd) Running test suite ; \
@@ -1564,7 +1564,7 @@
 # UNITTESTS: Running the unittests test suite
 ###############################################################################
 
-unittests::
+unittests:: libs-only
 	$(Verb) if test -d "$(PROJ_OBJ_ROOT)/unittests" ; then \
 	  if test -f "$(PROJ_OBJ_ROOT)/unittests/Makefile" ; then \
 	    $(EchoCmd) Running unittests test suite ; \




From sabre at nondot.org  Thu Apr  9 11:50:43 2009
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 09 Apr 2009 16:50:43 -0000
Subject: [llvm-commits] [llvm] r68712 - in /llvm/trunk:
 lib/CodeGen/MachineInstr.cpp test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll
Message-ID: <200904091650.n39Goh27026011@zion.cs.uiuc.edu>

Author: lattner
Date: Thu Apr  9 11:50:43 2009
New Revision: 68712

URL: http://llvm.org/viewvc/llvm-project?rev=68712&view=rev
Log:
reg0 references are not real registers.  This fixes a crash on the 
attached testcase.

Added:
    llvm/trunk/test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll
Modified:
    llvm/trunk/lib/CodeGen/MachineInstr.cpp

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=68712&r1=68711&r2=68712&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Thu Apr  9 11:50:43 2009
@@ -739,7 +739,7 @@
 bool MachineInstr::isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx){
   if (getOpcode() == TargetInstrInfo::INLINEASM) {
     const MachineOperand &MO = getOperand(UseOpIdx);
-    if (!MO.isReg() || !MO.isUse())
+    if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
       return false;
     assert(UseOpIdx > 0);
     const MachineOperand &UFMO = getOperand(UseOpIdx-1);

Added: llvm/trunk/test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll?rev=68712&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll Thu Apr  9 11:50:43 2009
@@ -0,0 +1,165 @@
+; RUN: llvm-as < %s | llc 
+; rdar://6774324
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin10.0"
+	type <{ i32, %1 }>		; type %0
+	type <{ [216 x i8] }>		; type %1
+	type <{ %3, %4*, %28*, i64, i32, %6, %6, i32, i32, i32, i32, void (i8*, i32)*, i8*, %29*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [2 x i8*], i32, %30, i32, %24, %4*, %4*, i64, i64, i32, i32, void (i32, %2*)*, i32, i32, i32, i32, i32, i32, i32, i32, %24, i64, i64, i64, i64, i64, %21, i32, i32, %21, i32, %31*, %3, %33, %34, %9*, i32, i32, %3, %3, %35, %41*, %42*, %11, i32, i32, i32, i8, i8, i8, i8, %69*, %69, %9*, %9*, [11 x %61], %3, i8*, i32, i64, i64, i32, i32, i32, i64 }>		; type %2
+	type <{ %3*, %3* }>		; type %3
+	type <{ %3, i32, %2*, %2*, %2*, %5*, i32, i32, %21, i64, i64, i64, i32, %22, %9*, %6, %4*, %23 }>		; type %4
+	type <{ %3, %3, %4*, %4*, i32, %6, %9*, %9*, %5*, %20* }>		; type %5
+	type <{ %7, i16, i8, i8, %8 }>		; type %6
+	type <{ i32 }>		; type %7
+	type <{ i8*, i8*, [2 x i32], i16, i8, i8, i8*, i8, i8, i8, i8, i8* }>		; type %8
+	type <{ %10, %13, %15, i32, i32, i32, i32, %9*, %9*, %16*, i32, %17*, i64, i32 }>		; type %9
+	type <{ i32, i32, %11 }>		; type %10
+	type <{ %12 }>		; type %11
+	type <{ [12 x i8] }>		; type %12
+	type <{ %14 }>		; type %13
+	type <{ [40 x i8] }>		; type %14
+	type <{ [4 x i8] }>		; type %15
+	type <{ %15, %15 }>		; type %16
+	type <{ %17*, %17*, %9*, i32, %18*, %19* }>		; type %17
+	type opaque		; type %18
+	type <{ i32, i32, %9*, %9*, i32, i32 }>		; type %19
+	type <{ %5*, %20*, %20*, %20* }>		; type %20
+	type <{ %3, %3*, void (i8*, i8*)*, i8*, i8*, i64 }>		; type %21
+	type <{ i32, [4 x i32], i32, i32, [128 x %3] }>		; type %22
+	type <{ %24, %24, %24, %24*, %24*, %24*, %25, %26, %27, i32, i32, i8* }>		; type %23
+	type <{ i64, i32, i32, i32 }>		; type %24
+	type <{ i32, i32 }>		; type %25
+	type <{ i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32 }>		; type %26
+	type <{ [16 x %17*], i32 }>		; type %27
+	type <{ i8, i8, i8, i8, %7, %3 }>		; type %28
+	type <{ i32, %11*, i8*, i8*, %11* }>		; type %29
+	type <{ i32, i32, i32, i32, i64 }>		; type %30
+	type <{ %32*, %3, %3, i32, i32, i32, %5* }>		; type %31
+	type opaque		; type %32
+	type <{ [44 x i8] }>		; type %33
+	type <{ %17* }>		; type %34
+	type <{ %36, %36*, i32, [4 x %40], i32, i32, i64, i32 }>		; type %35
+	type <{ i8*, %0*, %37*, i64, %39, i32, %39, %6, i64, i64, i8*, i32 }>		; type %36
+	type <{ i32, i32, i8, i8, i8, i8, i8, i8, i8, i8, %38 }>		; type %37
+	type <{ i16, i16, i8, i8, i16, i32, i16, i16, i32, i16, i16, i32, i32, [8 x [8 x i16]], [8 x [16 x i16]], [96 x i8] }>		; type %38
+	type <{ i8, i8, i8, i8, i8, i8, i8, i8 }>		; type %39
+	type <{ i64 }>		; type %40
+	type <{ %11, i32, i32, i32, %42*, %3, i8*, %3, %5*, %32*, i32, i32, i32, i32, i32, i32, i32, %59, %60, i64, i64, i32, %11, %9*, %9*, %9*, [11 x %61], %9*, %9*, %9*, %9*, %9*, [3 x %9*], %62*, %3, %3, i32, i32, %9*, %9*, i32, %67*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, %68*, [2 x i32], i64, i64, i32 }>		; type %41
+	type <{ %43, %44, %47*, i64, i64, i64, i32, %11, %54, %46*, %46*, i32, i32, i32, i32, i32, i32, i32 }>		; type %42
+	type <{ i16, i8, i8, i32, i32 }>		; type %43
+	type <{ %45, i32, i32 }>		; type %44
+	type <{ %46*, %46*, i64, i64 }>		; type %45
+	type <{ %45, %15, i64, i8, i8, i8, i8, i16, i16 }>		; type %46
+	type <{ i64*, i64, %48*, i32, i32, i32, %6, %53, i32, i64, i64*, i64*, %48*, %48*, %48*, i32 }>		; type %47
+	type <{ %3, %43, i64, %49*, i32, i32, i32, i32, %48*, %48*, i64, %50*, i64, %52*, i32, i16, i16, i8, i8, i8, i8, %3, %3, i64, i32, i32, i32, i8*, i32, i8, i8, i8, i8, %3 }>		; type %48
+	type <{ %3, %3, %49*, %48*, i64, i8, i8, i8, i8, i32, i8, i8, i8, i8 }>		; type %49
+	type <{ i32, %51* }>		; type %50
+	type <{ void (%50*)*, void (%50*)*, i32 (%50*, %52*, i32)*, i32 (%50*)*, i32 (%50*, i64, i32, i32, i32*)*, i32 (%50*, i64, i32, i64*, i32*, i32, i32, i32)*, i32 (%50*, i64, i32)*, i32 (%50*, i64, i64, i32)*, i32 (%50*, i64, i64, i32)*, i32 (%50*, i32)*, i32 (%50*)*, i8* }>		; type %51
+	type <{ i32, %48* }>		; type %52
+	type <{ i32, i32, i32 }>		; type %53
+	type <{ %11, %55*, i32, %53, i64 }>		; type %54
+	type <{ %3, i32, i32, i32, i32, i32, [64 x i8], %56 }>		; type %55
+	type <{ %57, %58, %58 }>		; type %56
+	type <{ i64, i64, i64, i64, i64 }>		; type %57
+	type <{ i64, i64, i64, i64, i64, i64, i64, i64 }>		; type %58
+	type <{ [2 x i32] }>		; type %59
+	type <{ [8 x i32] }>		; type %60
+	type <{ %9*, i32, i32, i32 }>		; type %61
+	type <{ %11, i32, %11, i32, i32, %63*, i32, %64*, %65, i32, i32, i32, i32, %41* }>		; type %62
+	type <{ %10*, i32, %15, %15 }>		; type %63
+	type opaque		; type %64
+	type <{ i32, %66*, %66*, %66**, %66*, %66** }>		; type %65
+	type <{ %63, i32, %62*, %66*, %66* }>		; type %66
+	type <{ i32, i32, [0 x %39] }>		; type %67
+	type opaque		; type %68
+	type <{ %69*, void (%69*, %2*)* }>		; type %69
+	type <{ %70*, %2*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i32, i32, i32, i32, i32, i32, i32, %71, i32, i32, i64, i64, i64, %72, i8*, i8*, %73, %4*, %79*, %81*, %39*, %84, i32, i32, i32, i8*, i32, i32, i32, i32, i32, i32, i32, i64*, i32, i64*, i8*, i32, [256 x i32], i64, i64, %86, %77*, i64, i64, %88*, %2*, %2* }>		; type %70
+	type <{ %3, i64, i32, i32 }>		; type %71
+	type <{ i64, i64, i64 }>		; type %72
+	type <{ %73*, %73*, %73*, %73*, %74*, %75*, %76*, %70*, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, [3 x %78*], i8*, i8* }>		; type %73
+	type <{ %74*, %74*, %75*, %76*, %73*, i32, i32, i32, i32, i32, i8*, i8* }>		; type %74
+	type <{ %75*, %73*, %74*, %76*, i32, i32, i32, i32, %78*, i8*, i8* }>		; type %75
+	type <{ %76*, %73*, %74*, %75*, i32, i32, i32, i32, i8*, i8*, %77* }>		; type %76
+	type opaque		; type %77
+	type <{ %78*, %75*, i8, i8, i8, i8, i16, i16, i16, i8, i8, i32, [0 x %73*] }>		; type %78
+	type <{ i32, i32, i32, [20 x %80] }>		; type %79
+	type <{ i64*, i8* }>		; type %80
+	type <{ [256 x %39], [19 x %39], i8, i8, i8, i8, i8, i8, i8, i8, %82, i8, i8, i8, i8, i8, i8, i8, i8, %82, %83 }>		; type %81
+	type <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, i16 }>		; type %82
+	type <{ [16 x i64], i64 }>		; type %83
+	type <{ %82*, %85, %85, %39*, i32 }>		; type %84
+	type <{ i16, %39* }>		; type %85
+	type <{ %87, i8* }>		; type %86
+	type <{ i32, i32, i32, i8, i8, i16, i32, i32, i32, i32, i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }>		; type %87
+	type <{ i64, i64, i32, i32, i32, i32 }>		; type %88
+	type <{ i32, i32, i32, i32, i32, i32, i32 }>		; type %89
+ at kernel_stack_size = external global i32		; <i32*> [#uses=1]
+
+define void @test(%0*) nounwind {
+	%2 = tail call %2* asm sideeffect "mov %gs:${1:P},$0", "=r,i,~{dirflag},~{fpsr},~{flags}"(i32 ptrtoint (%2** getelementptr (%70* null, i32 0, i32 1) to i32)) nounwind		; <%2*> [#uses=1]
+	%3 = getelementptr %2* %2, i32 0, i32 15		; <i32*> [#uses=1]
+	%4 = load i32* %3		; <i32> [#uses=2]
+	%5 = icmp eq i32 %4, 0		; <i1> [#uses=1]
+	br i1 %5, label %47, label %6
+
+; <label>:6		; preds = %1
+	%7 = load i32* @kernel_stack_size		; <i32> [#uses=1]
+	%8 = add i32 %7, %4		; <i32> [#uses=1]
+	%9 = inttoptr i32 %8 to %89*		; <%89*> [#uses=12]
+	%10 = tail call %2* asm sideeffect "mov %gs:${1:P},$0", "=r,i,~{dirflag},~{fpsr},~{flags}"(i32 ptrtoint (%2** getelementptr (%70* null, i32 0, i32 1) to i32)) nounwind		; <%2*> [#uses=1]
+	%11 = getelementptr %2* %10, i32 0, i32 65, i32 1		; <%36**> [#uses=1]
+	%12 = load %36** %11		; <%36*> [#uses=1]
+	%13 = getelementptr %36* %12, i32 0, i32 1		; <%0**> [#uses=1]
+	%14 = load %0** %13		; <%0*> [#uses=1]
+	%15 = icmp eq %0* %14, %0		; <i1> [#uses=1]
+	br i1 %15, label %40, label %16
+
+; <label>:16		; preds = %6
+	%17 = getelementptr %0* %0, i32 0, i32 1		; <%1*> [#uses=1]
+	%18 = getelementptr %89* %9, i32 -1, i32 0		; <i32*> [#uses=1]
+	%19 = getelementptr %0* %0, i32 0, i32 1, i32 0, i32 32		; <i8*> [#uses=1]
+	%20 = bitcast i8* %19 to i32*		; <i32*> [#uses=1]
+	%21 = load i32* %20		; <i32> [#uses=1]
+	store i32 %21, i32* %18
+	%22 = getelementptr %89* %9, i32 -1, i32 1		; <i32*> [#uses=1]
+	%23 = ptrtoint %1* %17 to i32		; <i32> [#uses=1]
+	store i32 %23, i32* %22
+	%24 = getelementptr %89* %9, i32 -1, i32 2		; <i32*> [#uses=1]
+	%25 = getelementptr %0* %0, i32 0, i32 1, i32 0, i32 24		; <i8*> [#uses=1]
+	%26 = bitcast i8* %25 to i32*		; <i32*> [#uses=1]
+	%27 = load i32* %26		; <i32> [#uses=1]
+	store i32 %27, i32* %24
+	%28 = getelementptr %89* %9, i32 -1, i32 3		; <i32*> [#uses=1]
+	%29 = getelementptr %0* %0, i32 0, i32 1, i32 0, i32 16		; <i8*> [#uses=1]
+	%30 = bitcast i8* %29 to i32*		; <i32*> [#uses=1]
+	%31 = load i32* %30		; <i32> [#uses=1]
+	store i32 %31, i32* %28
+	%32 = getelementptr %89* %9, i32 -1, i32 4		; <i32*> [#uses=1]
+	%33 = getelementptr %0* %0, i32 0, i32 1, i32 0, i32 20		; <i8*> [#uses=1]
+	%34 = bitcast i8* %33 to i32*		; <i32*> [#uses=1]
+	%35 = load i32* %34		; <i32> [#uses=1]
+	store i32 %35, i32* %32
+	%36 = getelementptr %89* %9, i32 -1, i32 5		; <i32*> [#uses=1]
+	%37 = getelementptr %0* %0, i32 0, i32 1, i32 0, i32 56		; <i8*> [#uses=1]
+	%38 = bitcast i8* %37 to i32*		; <i32*> [#uses=1]
+	%39 = load i32* %38		; <i32> [#uses=1]
+	store i32 %39, i32* %36
+	ret void
+
+; <label>:40		; preds = %6
+	%41 = getelementptr %89* %9, i32 -1, i32 0		; <i32*> [#uses=1]
+	tail call void asm sideeffect "movl %ebx, $0", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %41) nounwind
+	%42 = getelementptr %89* %9, i32 -1, i32 1		; <i32*> [#uses=1]
+	tail call void asm sideeffect "movl %esp, $0", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %42) nounwind
+	%43 = getelementptr %89* %9, i32 -1, i32 2		; <i32*> [#uses=1]
+	tail call void asm sideeffect "movl %ebp, $0", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %43) nounwind
+	%44 = getelementptr %89* %9, i32 -1, i32 3		; <i32*> [#uses=1]
+	tail call void asm sideeffect "movl %edi, $0", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %44) nounwind
+	%45 = getelementptr %89* %9, i32 -1, i32 4		; <i32*> [#uses=1]
+	tail call void asm sideeffect "movl %esi, $0", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %45) nounwind
+	%46 = getelementptr %89* %9, i32 -1, i32 5		; <i32*> [#uses=1]
+	tail call void asm sideeffect "movl $$1f, $0\0A1:", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %46) nounwind
+	ret void
+
+; <label>:47		; preds = %1
+	ret void
+}




From sanjiv.gupta at microchip.com  Thu Apr  9 12:06:24 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Thu, 09 Apr 2009 17:06:24 -0000
Subject: [llvm-commits] [llvm] r68713 -
	/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
Message-ID: <200904091706.n39H6PQ0026962@zion.cs.uiuc.edu>

Author: sgupta
Date: Thu Apr  9 12:06:24 2009
New Revision: 68713

URL: http://llvm.org/viewvc/llvm-project?rev=68713&view=rev
Log:
The way we are trying to figure out banksel immediate operand may yield different results for different type of insns. This will eventually need to be changed but currently let us prevent the crash in cases of incorrect detection of banksel operand.

Modified:
    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp

Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=68713&r1=68712&r2=68713&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Thu Apr  9 12:06:24 2009
@@ -77,8 +77,9 @@
       // This is not true for external variables as section names for global
       // variables in all files are same at this time. For eg. initialized 
       // data in put in idata.# section in all files. 
-      if (((int)BS.getImm() == 1) &&
-          ((Op.isGlobal() && Op.getGlobal()->hasExternalLinkage()) ||
+      if ((BS.getType() == MachineOperand::MO_Immediate 
+           && (int)BS.getImm() == 1) 
+          && ((Op.isGlobal() && Op.getGlobal()->hasExternalLinkage()) ||
            (NewBank.compare(CurBank) != 0))) { 
         O << "\tbanksel ";
         printOperand(MI, BankSelVar);




From bob.wilson at apple.com  Thu Apr  9 12:16:44 2009
From: bob.wilson at apple.com (Bob Wilson)
Date: Thu, 09 Apr 2009 17:16:44 -0000
Subject: [llvm-commits] [llvm] r68714 - in /llvm/trunk:
 include/llvm/CodeGen/MachineInstr.h include/llvm/Target/TargetInstrDesc.h
 lib/CodeGen/LiveIntervalAnalysis.cpp lib/CodeGen/MachineInstr.cpp
 lib/CodeGen/PostRASchedulerList.cpp lib/CodeGen/PreAllocSplitting.cpp
 lib/CodeGen/RegAllocLocal.cpp lib/CodeGen/RegAllocSimple.cpp
 lib/CodeGen/RegisterScavenging.cpp lib/CodeGen/Spiller.cpp
 lib/Target/TargetInstrInfo.cpp
 test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll
Message-ID: <200904091716.n39HGiHJ027496@zion.cs.uiuc.edu>

Author: bwilson
Date: Thu Apr  9 12:16:43 2009
New Revision: 68714

URL: http://llvm.org/viewvc/llvm-project?rev=68714&view=rev
Log:
Fix pr3954.  The register scavenger asserts for inline assembly with
register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).

Added:
    llvm/trunk/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll
Modified:
    llvm/trunk/include/llvm/CodeGen/MachineInstr.h
    llvm/trunk/include/llvm/Target/TargetInstrDesc.h
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
    llvm/trunk/lib/CodeGen/MachineInstr.cpp
    llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
    llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
    llvm/trunk/lib/CodeGen/RegAllocLocal.cpp
    llvm/trunk/lib/CodeGen/RegAllocSimple.cpp
    llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
    llvm/trunk/lib/CodeGen/Spiller.cpp
    llvm/trunk/lib/Target/TargetInstrInfo.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=68714&r1=68713&r2=68714&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Thu Apr  9 12:16:43 2009
@@ -241,9 +241,11 @@
   /// none is found.
   int findFirstPredOperandIdx() const;
   
-  /// isRegReDefinedByTwoAddr - Given the index of a register def operand,
-  /// check if the register def is a re-definition due to two addr elimination.
-  bool isRegReDefinedByTwoAddr(unsigned DefIdx) const;
+  /// isRegTiedToUseOperand - Given the index of a register def operand,
+  /// check if the register def is tied to a source operand, due to either
+  /// two-address elimination or inline assembly constraints. Returns the
+  /// first tied use operand index by reference is UseOpIdx is not null.
+  bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0);
 
   /// isRegTiedToDefOperand - Return true if the use operand of the specified
   /// index is tied to an def operand. It also returns the def operand index by

Modified: llvm/trunk/include/llvm/Target/TargetInstrDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrDesc.h?rev=68714&r1=68713&r2=68714&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrDesc.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrDesc.h Thu Apr  9 12:16:43 2009
@@ -131,10 +131,6 @@
     return -1;
   }
 
-  /// findTiedToSrcOperand - Returns the operand that is tied to the specified
-  /// dest operand. Returns -1 if there isn't one.
-  int findTiedToSrcOperand(unsigned OpNum) const;
-  
   /// getOpcode - Return the opcode number for this descriptor.
   unsigned getOpcode() const {
     return Opcode;

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=68714&r1=68713&r2=68714&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Thu Apr  9 12:16:43 2009
@@ -469,7 +469,7 @@
     // must be due to phi elimination or two addr elimination.  If this is
     // the result of two address elimination, then the vreg is one of the
     // def-and-use register operand.
-    if (mi->isRegReDefinedByTwoAddr(MOIdx)) {
+    if (mi->isRegTiedToUseOperand(MOIdx)) {
       // If this is a two-address definition, then we have already processed
       // the live range.  The only problem is that we didn't realize there
       // are actually two values in the live interval.  Because of this we

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=68714&r1=68713&r2=68714&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Thu Apr  9 12:16:43 2009
@@ -690,12 +690,14 @@
   return -1;
 }
   
-/// isRegReDefinedByTwoAddr - Given the index of a register operand,
-/// check if the register def is a re-definition due to two addr elimination.
-bool MachineInstr::isRegReDefinedByTwoAddr(unsigned DefIdx) const{
+/// isRegTiedToUseOperand - Given the index of a register def operand,
+/// check if the register def is tied to a source operand, due to either
+/// two-address elimination or inline assembly constraints. Returns the
+/// first tied use operand index by reference is UseOpIdx is not null.
+bool MachineInstr::isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx){
   if (getOpcode() == TargetInstrInfo::INLINEASM) {
-    assert(DefIdx >= 2);
-    const MachineOperand &MO = getOperand(DefIdx);
+    assert(DefOpIdx >= 2);
+    const MachineOperand &MO = getOperand(DefOpIdx);
     if (!MO.isReg() || !MO.isDef())
       return false;
     // Determine the actual operand no corresponding to this index.
@@ -705,7 +707,7 @@
       assert(FMO.isImm());
       // Skip over this def.
       i += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
-      if (i > DefIdx)
+      if (i > DefOpIdx)
         break;
       ++DefNo;
     }
@@ -717,18 +719,24 @@
         continue;
       unsigned Idx;
       if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) && 
-          Idx == DefNo)
+          Idx == DefNo) {
+        if (UseOpIdx)
+          *UseOpIdx = (unsigned)i + 1;
         return true;
+      }
     }
   }
 
-  assert(getOperand(DefIdx).isDef() && "DefIdx is not a def!");
+  assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
   const TargetInstrDesc &TID = getDesc();
   for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = getOperand(i);
     if (MO.isReg() && MO.isUse() &&
-        TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx)
+        TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
+      if (UseOpIdx)
+        *UseOpIdx = (unsigned)i;
       return true;
+    }
   }
   return false;
 }

Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=68714&r1=68713&r2=68714&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Thu Apr  9 12:16:43 2009
@@ -500,7 +500,7 @@
     if (Reg == 0) continue;
     if (!MO.isDef()) continue;
     // Ignore two-addr defs.
-    if (MI->isRegReDefinedByTwoAddr(i)) continue;
+    if (MI->isRegTiedToUseOperand(i)) continue;
 
     DefIndices[Reg] = Count;
     KillIndices[Reg] = ~0u;

Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=68714&r1=68713&r2=68714&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original)
+++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Thu Apr  9 12:16:43 2009
@@ -803,7 +803,7 @@
       MachineInstr* MI = LIs->getInstructionFromIndex(*KI);
       unsigned DefIdx = MI->findRegisterDefOperandIdx(CurrLI->reg);
       if (DefIdx == ~0U) continue;
-      if (MI->isRegReDefinedByTwoAddr(DefIdx)) {
+      if (MI->isRegTiedToUseOperand(DefIdx)) {
         VNInfo* NextVN =
                      CurrLI->findDefinedVNInfo(LiveIntervals::getDefIndex(*KI));
         if (NextVN == OldVN) continue;
@@ -1214,7 +1214,7 @@
       NonSpills++;
     
     int DefIdx = (*UI)->findRegisterDefOperandIdx(Reg);
-    if (DefIdx != -1 && (*UI)->isRegReDefinedByTwoAddr(DefIdx))
+    if (DefIdx != -1 && (*UI)->isRegTiedToUseOperand(DefIdx))
       FeedsTwoAddr = true;
   }
   

Modified: llvm/trunk/lib/CodeGen/RegAllocLocal.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLocal.cpp?rev=68714&r1=68713&r2=68714&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLocal.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLocal.cpp Thu Apr  9 12:16:43 2009
@@ -633,7 +633,7 @@
           // Check if this is a two address instruction.  If so, then
           // the def does not kill the use.
           if (last->second.first == I &&
-              I->isRegReDefinedByTwoAddr(i))
+              I->isRegTiedToUseOperand(i))
             continue;
           
           MachineOperand& lastUD =

Modified: llvm/trunk/lib/CodeGen/RegAllocSimple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocSimple.cpp?rev=68714&r1=68713&r2=68714&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocSimple.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocSimple.cpp Thu Apr  9 12:16:43 2009
@@ -204,8 +204,8 @@
         unsigned physReg = Virt2PhysRegMap[virtualReg];
         if (physReg == 0) {
           if (MO.isDef()) {
-            int TiedOp = Desc.findTiedToSrcOperand(i);
-            if (TiedOp == -1) {
+            unsigned TiedOp;
+            if (!MI->isRegTiedToUseOperand(i, &TiedOp)) {
               physReg = getFreeReg(virtualReg);
             } else {
               // must be same register number as the source operand that is 

Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=68714&r1=68713&r2=68714&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Thu Apr  9 12:16:43 2009
@@ -188,7 +188,6 @@
 
   MachineInstr *MI = MBBI;
   DistanceMap.insert(std::make_pair(MI, CurrDist++));
-  const TargetInstrDesc &TID = MI->getDesc();
 
   if (MI == ScavengeRestore) {
     ScavengedReg = 0;
@@ -256,7 +255,7 @@
     }
 
     // Skip two-address destination operand.
-    if (TID.findTiedToSrcOperand(Idx) != -1) {
+    if (MI->isRegTiedToUseOperand(Idx)) {
       assert(isUsed(Reg) && "Using an undefined register!");
       continue;
     }
@@ -284,7 +283,6 @@
   MachineInstr *MI = MBBI;
   DistanceMap.erase(MI);
   --CurrDist;
-  const TargetInstrDesc &TID = MI->getDesc();
 
   // Separate register operands into 3 classes: uses, defs, earlyclobbers.
   SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
@@ -313,7 +311,7 @@
       ? DefMOs[i].second : EarlyClobberMOs[i-NumDefs].second;
 
     // Skip two-address destination operand.
-    if (TID.findTiedToSrcOperand(Idx) != -1)
+    if (MI->isRegTiedToUseOperand(Idx))
       continue;
 
     unsigned Reg = MO.getReg();

Modified: llvm/trunk/lib/CodeGen/Spiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.cpp?rev=68714&r1=68713&r2=68714&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/Spiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/Spiller.cpp Thu Apr  9 12:16:43 2009
@@ -1589,8 +1589,8 @@
       // If this def is part of a two-address operand, make sure to execute
       // the store from the correct physical register.
       unsigned PhysReg;
-      int TiedOp = MI.getDesc().findTiedToSrcOperand(i);
-      if (TiedOp != -1) {
+      unsigned TiedOp;
+      if (MI.isRegTiedToUseOperand(i, &TiedOp)) {
         PhysReg = MI.getOperand(TiedOp).getReg();
         if (SubIdx) {
           unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI);

Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetInstrInfo.cpp?rev=68714&r1=68713&r2=68714&view=diff

==============================================================================
--- llvm/trunk/lib/Target/TargetInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetInstrInfo.cpp Thu Apr  9 12:16:43 2009
@@ -16,19 +16,6 @@
 #include "llvm/DerivedTypes.h"
 using namespace llvm;
 
-/// findTiedToSrcOperand - Returns the operand that is tied to the specified
-/// dest operand. Returns -1 if there isn't one.
-int TargetInstrDesc::findTiedToSrcOperand(unsigned OpNum) const {
-  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
-    if (i == OpNum)
-      continue;
-    if (getOperandConstraint(i, TOI::TIED_TO) == (int)OpNum)
-      return i;
-  }
-  return -1;
-}
-
-
 TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
                                  unsigned numOpcodes)
   : Descriptors(Desc), NumOpcodes(numOpcodes) {

Added: llvm/trunk/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll?rev=68714&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll Thu Apr  9 12:16:43 2009
@@ -0,0 +1,14 @@
+; RUN: llvm-as < %s | llc -march=arm
+; PR3954
+
+define void @foo(...) nounwind {
+entry:
+	%rr = alloca i32		; <i32*> [#uses=2]
+	%0 = load i32* %rr		; <i32> [#uses=1]
+	%1 = call i32 asm "nop", "=r,0"(i32 %0) nounwind		; <i32> [#uses=1]
+	store i32 %1, i32* %rr
+	br label %return
+
+return:		; preds = %entry
+	ret void
+}




From bob.wilson at apple.com  Thu Apr  9 12:20:33 2009
From: bob.wilson at apple.com (Bob Wilson)
Date: Thu, 9 Apr 2009 10:20:33 -0700
Subject: [llvm-commits] [llvm] r68712 - in /llvm/trunk:
	lib/CodeGen/MachineInstr.cpp
	test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll
In-Reply-To: <200904091650.n39Goh27026011@zion.cs.uiuc.edu>
References: <200904091650.n39Goh27026011@zion.cs.uiuc.edu>
Message-ID: <1B96DBD2-4BD0-4153-985E-EAD486785235@apple.com>

This change is probably also needed in the preceding  
"isRegTiedToUseOperand" method (formerly "isRegReDefinedByTwoAddr" --  
I just renamed it).  Do you agree?

On Apr 9, 2009, at 9:50 AM, Chris Lattner wrote:

> Author: lattner
> Date: Thu Apr  9 11:50:43 2009
> New Revision: 68712
>
> URL: http://llvm.org/viewvc/llvm-project?rev=68712&view=rev
> Log:
> reg0 references are not real registers.  This fixes a crash on the
> attached testcase.
>
> Added:
>    llvm/trunk/test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll
> Modified:
>    llvm/trunk/lib/CodeGen/MachineInstr.cpp
>
> Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=68712&r1=68711&r2=68712&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Thu Apr  9 11:50:43 2009
> @@ -739,7 +739,7 @@
> bool MachineInstr::isRegTiedToDefOperand(unsigned UseOpIdx, unsigned  
> *DefOpIdx){
>   if (getOpcode() == TargetInstrInfo::INLINEASM) {
>     const MachineOperand &MO = getOperand(UseOpIdx);
> -    if (!MO.isReg() || !MO.isUse())
> +    if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
>       return false;
>     assert(UseOpIdx > 0);
>     const MachineOperand &UFMO = getOperand(UseOpIdx-1);
>
> Added: llvm/trunk/test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll?rev=68712&view=auto
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll Thu  
> Apr  9 11:50:43 2009
> @@ -0,0 +1,165 @@
> +; RUN: llvm-as < %s | llc
> +; rdar://6774324
> +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32- 
> i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64- 
> f80:128:128"
> +target triple = "i386-apple-darwin10.0"
> +	type <{ i32, %1 }>		; type %0
> +	type <{ [216 x i8] }>		; type %1
> +	type <{ %3, %4*, %28*, i64, i32, %6, %6, i32, i32, i32, i32, void  
> (i8*, i32)*, i8*, %29*, i32, i32, i32, i32, i32, i32, i32, i32, i32,  
> i32, i32, [2 x i8*], i32, %30, i32, %24, %4*, %4*, i64, i64, i32,  
> i32, void (i32, %2*)*, i32, i32, i32, i32, i32, i32, i32, i32, %24,  
> i64, i64, i64, i64, i64, %21, i32, i32, %21, i32, %31*, %3, %33,  
> %34, %9*, i32, i32, %3, %3, %35, %41*, %42*, %11, i32, i32, i32, i8,  
> i8, i8, i8, %69*, %69, %9*, %9*, [11 x %61], %3, i8*, i32, i64, i64,  
> i32, i32, i32, i64 }>		; type %2
> +	type <{ %3*, %3* }>		; type %3
> +	type <{ %3, i32, %2*, %2*, %2*, %5*, i32, i32, %21, i64, i64, i64,  
> i32, %22, %9*, %6, %4*, %23 }>		; type %4
> +	type <{ %3, %3, %4*, %4*, i32, %6, %9*, %9*, %5*, %20* }>		; type %5
> +	type <{ %7, i16, i8, i8, %8 }>		; type %6
> +	type <{ i32 }>		; type %7
> +	type <{ i8*, i8*, [2 x i32], i16, i8, i8, i8*, i8, i8, i8, i8,  
> i8* }>		; type %8
> +	type <{ %10, %13, %15, i32, i32, i32, i32, %9*, %9*, %16*, i32,  
> %17*, i64, i32 }>		; type %9
> +	type <{ i32, i32, %11 }>		; type %10
> +	type <{ %12 }>		; type %11
> +	type <{ [12 x i8] }>		; type %12
> +	type <{ %14 }>		; type %13
> +	type <{ [40 x i8] }>		; type %14
> +	type <{ [4 x i8] }>		; type %15
> +	type <{ %15, %15 }>		; type %16
> +	type <{ %17*, %17*, %9*, i32, %18*, %19* }>		; type %17
> +	type opaque		; type %18
> +	type <{ i32, i32, %9*, %9*, i32, i32 }>		; type %19
> +	type <{ %5*, %20*, %20*, %20* }>		; type %20
> +	type <{ %3, %3*, void (i8*, i8*)*, i8*, i8*, i64 }>		; type %21
> +	type <{ i32, [4 x i32], i32, i32, [128 x %3] }>		; type %22
> +	type <{ %24, %24, %24, %24*, %24*, %24*, %25, %26, %27, i32, i32,  
> i8* }>		; type %23
> +	type <{ i64, i32, i32, i32 }>		; type %24
> +	type <{ i32, i32 }>		; type %25
> +	type <{ i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i64,  
> i64, i64, i32, i32 }>		; type %26
> +	type <{ [16 x %17*], i32 }>		; type %27
> +	type <{ i8, i8, i8, i8, %7, %3 }>		; type %28
> +	type <{ i32, %11*, i8*, i8*, %11* }>		; type %29
> +	type <{ i32, i32, i32, i32, i64 }>		; type %30
> +	type <{ %32*, %3, %3, i32, i32, i32, %5* }>		; type %31
> +	type opaque		; type %32
> +	type <{ [44 x i8] }>		; type %33
> +	type <{ %17* }>		; type %34
> +	type <{ %36, %36*, i32, [4 x %40], i32, i32, i64, i32 }>		; type %35
> +	type <{ i8*, %0*, %37*, i64, %39, i32, %39, %6, i64, i64, i8*,  
> i32 }>		; type %36
> +	type <{ i32, i32, i8, i8, i8, i8, i8, i8, i8, i8, %38 }>		; type %37
> +	type <{ i16, i16, i8, i8, i16, i32, i16, i16, i32, i16, i16, i32,  
> i32, [8 x [8 x i16]], [8 x [16 x i16]], [96 x i8] }>		; type %38
> +	type <{ i8, i8, i8, i8, i8, i8, i8, i8 }>		; type %39
> +	type <{ i64 }>		; type %40
> +	type <{ %11, i32, i32, i32, %42*, %3, i8*, %3, %5*, %32*, i32,  
> i32, i32, i32, i32, i32, i32, %59, %60, i64, i64, i32, %11, %9*,  
> %9*, %9*, [11 x %61], %9*, %9*, %9*, %9*, %9*, [3 x %9*], %62*, %3,  
> %3, i32, i32, %9*, %9*, i32, %67*, i8*, i32, i32, i32, i32, i32,  
> i32, i32, i32, i32, i32, i8*, %68*, [2 x i32], i64, i64, i32 }>		;  
> type %41
> +	type <{ %43, %44, %47*, i64, i64, i64, i32, %11, %54, %46*, %46*,  
> i32, i32, i32, i32, i32, i32, i32 }>		; type %42
> +	type <{ i16, i8, i8, i32, i32 }>		; type %43
> +	type <{ %45, i32, i32 }>		; type %44
> +	type <{ %46*, %46*, i64, i64 }>		; type %45
> +	type <{ %45, %15, i64, i8, i8, i8, i8, i16, i16 }>		; type %46
> +	type <{ i64*, i64, %48*, i32, i32, i32, %6, %53, i32, i64, i64*,  
> i64*, %48*, %48*, %48*, i32 }>		; type %47
> +	type <{ %3, %43, i64, %49*, i32, i32, i32, i32, %48*, %48*, i64,  
> %50*, i64, %52*, i32, i16, i16, i8, i8, i8, i8, %3, %3, i64, i32,  
> i32, i32, i8*, i32, i8, i8, i8, i8, %3 }>		; type %48
> +	type <{ %3, %3, %49*, %48*, i64, i8, i8, i8, i8, i32, i8, i8, i8,  
> i8 }>		; type %49
> +	type <{ i32, %51* }>		; type %50
> +	type <{ void (%50*)*, void (%50*)*, i32 (%50*, %52*, i32)*, i32  
> (%50*)*, i32 (%50*, i64, i32, i32, i32*)*, i32 (%50*, i64, i32,  
> i64*, i32*, i32, i32, i32)*, i32 (%50*, i64, i32)*, i32 (%50*, i64,  
> i64, i32)*, i32 (%50*, i64, i64, i32)*, i32 (%50*, i32)*, i32  
> (%50*)*, i8* }>		; type %51
> +	type <{ i32, %48* }>		; type %52
> +	type <{ i32, i32, i32 }>		; type %53
> +	type <{ %11, %55*, i32, %53, i64 }>		; type %54
> +	type <{ %3, i32, i32, i32, i32, i32, [64 x i8], %56 }>		; type %55
> +	type <{ %57, %58, %58 }>		; type %56
> +	type <{ i64, i64, i64, i64, i64 }>		; type %57
> +	type <{ i64, i64, i64, i64, i64, i64, i64, i64 }>		; type %58
> +	type <{ [2 x i32] }>		; type %59
> +	type <{ [8 x i32] }>		; type %60
> +	type <{ %9*, i32, i32, i32 }>		; type %61
> +	type <{ %11, i32, %11, i32, i32, %63*, i32, %64*, %65, i32, i32,  
> i32, i32, %41* }>		; type %62
> +	type <{ %10*, i32, %15, %15 }>		; type %63
> +	type opaque		; type %64
> +	type <{ i32, %66*, %66*, %66**, %66*, %66** }>		; type %65
> +	type <{ %63, i32, %62*, %66*, %66* }>		; type %66
> +	type <{ i32, i32, [0 x %39] }>		; type %67
> +	type opaque		; type %68
> +	type <{ %69*, void (%69*, %2*)* }>		; type %69
> +	type <{ %70*, %2*, i8*, i32, i32, i32, i32, i32, i32, i32, i32,  
> i8*, i32, i32, i32, i32, i32, i32, i32, %71, i32, i32, i64, i64,  
> i64, %72, i8*, i8*, %73, %4*, %79*, %81*, %39*, %84, i32, i32, i32,  
> i8*, i32, i32, i32, i32, i32, i32, i32, i64*, i32, i64*, i8*, i32,  
> [256 x i32], i64, i64, %86, %77*, i64, i64, %88*, %2*, %2* }>		;  
> type %70
> +	type <{ %3, i64, i32, i32 }>		; type %71
> +	type <{ i64, i64, i64 }>		; type %72
> +	type <{ %73*, %73*, %73*, %73*, %74*, %75*, %76*, %70*, i32, i32,  
> i32, i32, i32, i32, i32, i32, i64, i64, [3 x %78*], i8*, i8* }>		;  
> type %73
> +	type <{ %74*, %74*, %75*, %76*, %73*, i32, i32, i32, i32, i32,  
> i8*, i8* }>		; type %74
> +	type <{ %75*, %73*, %74*, %76*, i32, i32, i32, i32, %78*, i8*,  
> i8* }>		; type %75
> +	type <{ %76*, %73*, %74*, %75*, i32, i32, i32, i32, i8*, i8*,  
> %77* }>		; type %76
> +	type opaque		; type %77
> +	type <{ %78*, %75*, i8, i8, i8, i8, i16, i16, i16, i8, i8, i32, [0  
> x %73*] }>		; type %78
> +	type <{ i32, i32, i32, [20 x %80] }>		; type %79
> +	type <{ i64*, i8* }>		; type %80
> +	type <{ [256 x %39], [19 x %39], i8, i8, i8, i8, i8, i8, i8, i8,  
> %82, i8, i8, i8, i8, i8, i8, i8, i8, %82, %83 }>		; type %81
> +	type <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,  
> i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,  
> i32, i16, i16 }>		; type %82
> +	type <{ [16 x i64], i64 }>		; type %83
> +	type <{ %82*, %85, %85, %39*, i32 }>		; type %84
> +	type <{ i16, %39* }>		; type %85
> +	type <{ %87, i8* }>		; type %86
> +	type <{ i32, i32, i32, i8, i8, i16, i32, i32, i32, i32, i8, i8,  
> i8, i8, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,  
> i32, i32, i32, i32 }>		; type %87
> +	type <{ i64, i64, i32, i32, i32, i32 }>		; type %88
> +	type <{ i32, i32, i32, i32, i32, i32, i32 }>		; type %89
> + at kernel_stack_size = external global i32		; <i32*> [#uses=1]
> +
> +define void @test(%0*) nounwind {
> +	%2 = tail call %2* asm sideeffect "mov %gs:${1:P},$0",  
> "=r,i,~{dirflag},~{fpsr},~{flags}"(i32 ptrtoint (%2** getelementptr  
> (%70* null, i32 0, i32 1) to i32)) nounwind		; <%2*> [#uses=1]
> +	%3 = getelementptr %2* %2, i32 0, i32 15		; <i32*> [#uses=1]
> +	%4 = load i32* %3		; <i32> [#uses=2]
> +	%5 = icmp eq i32 %4, 0		; <i1> [#uses=1]
> +	br i1 %5, label %47, label %6
> +
> +; <label>:6		; preds = %1
> +	%7 = load i32* @kernel_stack_size		; <i32> [#uses=1]
> +	%8 = add i32 %7, %4		; <i32> [#uses=1]
> +	%9 = inttoptr i32 %8 to %89*		; <%89*> [#uses=12]
> +	%10 = tail call %2* asm sideeffect "mov %gs:${1:P},$0",  
> "=r,i,~{dirflag},~{fpsr},~{flags}"(i32 ptrtoint (%2** getelementptr  
> (%70* null, i32 0, i32 1) to i32)) nounwind		; <%2*> [#uses=1]
> +	%11 = getelementptr %2* %10, i32 0, i32 65, i32 1		; <%36**>  
> [#uses=1]
> +	%12 = load %36** %11		; <%36*> [#uses=1]
> +	%13 = getelementptr %36* %12, i32 0, i32 1		; <%0**> [#uses=1]
> +	%14 = load %0** %13		; <%0*> [#uses=1]
> +	%15 = icmp eq %0* %14, %0		; <i1> [#uses=1]
> +	br i1 %15, label %40, label %16
> +
> +; <label>:16		; preds = %6
> +	%17 = getelementptr %0* %0, i32 0, i32 1		; <%1*> [#uses=1]
> +	%18 = getelementptr %89* %9, i32 -1, i32 0		; <i32*> [#uses=1]
> +	%19 = getelementptr %0* %0, i32 0, i32 1, i32 0, i32 32		; <i8*>  
> [#uses=1]
> +	%20 = bitcast i8* %19 to i32*		; <i32*> [#uses=1]
> +	%21 = load i32* %20		; <i32> [#uses=1]
> +	store i32 %21, i32* %18
> +	%22 = getelementptr %89* %9, i32 -1, i32 1		; <i32*> [#uses=1]
> +	%23 = ptrtoint %1* %17 to i32		; <i32> [#uses=1]
> +	store i32 %23, i32* %22
> +	%24 = getelementptr %89* %9, i32 -1, i32 2		; <i32*> [#uses=1]
> +	%25 = getelementptr %0* %0, i32 0, i32 1, i32 0, i32 24		; <i8*>  
> [#uses=1]
> +	%26 = bitcast i8* %25 to i32*		; <i32*> [#uses=1]
> +	%27 = load i32* %26		; <i32> [#uses=1]
> +	store i32 %27, i32* %24
> +	%28 = getelementptr %89* %9, i32 -1, i32 3		; <i32*> [#uses=1]
> +	%29 = getelementptr %0* %0, i32 0, i32 1, i32 0, i32 16		; <i8*>  
> [#uses=1]
> +	%30 = bitcast i8* %29 to i32*		; <i32*> [#uses=1]
> +	%31 = load i32* %30		; <i32> [#uses=1]
> +	store i32 %31, i32* %28
> +	%32 = getelementptr %89* %9, i32 -1, i32 4		; <i32*> [#uses=1]
> +	%33 = getelementptr %0* %0, i32 0, i32 1, i32 0, i32 20		; <i8*>  
> [#uses=1]
> +	%34 = bitcast i8* %33 to i32*		; <i32*> [#uses=1]
> +	%35 = load i32* %34		; <i32> [#uses=1]
> +	store i32 %35, i32* %32
> +	%36 = getelementptr %89* %9, i32 -1, i32 5		; <i32*> [#uses=1]
> +	%37 = getelementptr %0* %0, i32 0, i32 1, i32 0, i32 56		; <i8*>  
> [#uses=1]
> +	%38 = bitcast i8* %37 to i32*		; <i32*> [#uses=1]
> +	%39 = load i32* %38		; <i32> [#uses=1]
> +	store i32 %39, i32* %36
> +	ret void
> +
> +; <label>:40		; preds = %6
> +	%41 = getelementptr %89* %9, i32 -1, i32 0		; <i32*> [#uses=1]
> +	tail call void asm sideeffect "movl %ebx, $0",  
> "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %41) nounwind
> +	%42 = getelementptr %89* %9, i32 -1, i32 1		; <i32*> [#uses=1]
> +	tail call void asm sideeffect "movl %esp, $0",  
> "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %42) nounwind
> +	%43 = getelementptr %89* %9, i32 -1, i32 2		; <i32*> [#uses=1]
> +	tail call void asm sideeffect "movl %ebp, $0",  
> "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %43) nounwind
> +	%44 = getelementptr %89* %9, i32 -1, i32 3		; <i32*> [#uses=1]
> +	tail call void asm sideeffect "movl %edi, $0",  
> "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %44) nounwind
> +	%45 = getelementptr %89* %9, i32 -1, i32 4		; <i32*> [#uses=1]
> +	tail call void asm sideeffect "movl %esi, $0",  
> "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %45) nounwind
> +	%46 = getelementptr %89* %9, i32 -1, i32 5		; <i32*> [#uses=1]
> +	tail call void asm sideeffect "movl $$1f, $0\0A1:",  
> "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %46) nounwind
> +	ret void
> +
> +; <label>:47		; preds = %1
> +	ret void
> +}
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From isanbard at gmail.com  Thu Apr  9 13:26:57 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 09 Apr 2009 18:26:57 -0000
Subject: [llvm-commits] [llvm] r68721 - /llvm/trunk/Makefile.rules
Message-ID: <200904091826.n39IQwbj030163@zion.cs.uiuc.edu>

Author: void
Date: Thu Apr  9 13:26:57 2009
New Revision: 68721

URL: http://llvm.org/viewvc/llvm-project?rev=68721&view=rev
Log:
Revert r68708. It was causing this failure in the self-hosting buildbot:

llvm[2]: Compiling lto.cpp for Debug build  (PIC)
make[2]: *** No rule to make target `/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/Debug/lib/libLLVMBitWriter.a', needed by `/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/Release/lib/libLTO.dylib'.  Stop.
make[1]: *** [all] Error 1
make: *** [all] Error 1

Modified:
    llvm/trunk/Makefile.rules

Modified: llvm/trunk/Makefile.rules
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=68721&r1=68720&r2=68721&view=diff

==============================================================================
--- llvm/trunk/Makefile.rules (original)
+++ llvm/trunk/Makefile.rules Thu Apr  9 13:26:57 2009
@@ -1547,7 +1547,7 @@
 # CHECK: Running the test suite
 ###############################################################################
 
-check:: tools-only
+check::
 	$(Verb) if test -d "$(PROJ_OBJ_ROOT)/test" ; then \
 	  if test -f "$(PROJ_OBJ_ROOT)/test/Makefile" ; then \
 	    $(EchoCmd) Running test suite ; \
@@ -1564,7 +1564,7 @@
 # UNITTESTS: Running the unittests test suite
 ###############################################################################
 
-unittests:: libs-only
+unittests::
 	$(Verb) if test -d "$(PROJ_OBJ_ROOT)/unittests" ; then \
 	  if test -f "$(PROJ_OBJ_ROOT)/unittests/Makefile" ; then \
 	    $(EchoCmd) Running unittests test suite ; \




From isanbard at gmail.com  Thu Apr  9 13:27:28 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 9 Apr 2009 11:27:28 -0700
Subject: [llvm-commits] [llvm] r68708 - /llvm/trunk/Makefile.rules
In-Reply-To: <200904091457.n39Ev5PC021643@zion.cs.uiuc.edu>
References: <200904091457.n39Ev5PC021643@zion.cs.uiuc.edu>
Message-ID: <16e5fdf90904091127v1727b63bxb44220b28f5c866d@mail.gmail.com>

Misha,

This was causing this failure in the self-hosting buildbot:

llvm[2]: Compiling lto.cpp for Debug build  (PIC)
make[2]: *** No rule to make target
`/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/Debug/lib/libLLVMBitWriter.a',
needed by `/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/Release/lib/libLTO.dylib'.
 Stop.
make[1]: *** [all] Error 1
make: *** [all] Error 1

Could you investigate please?

-bw

On Thu, Apr 9, 2009 at 7:57 AM, Misha Brukman <brukman+llvm at gmail.com> wrote:
> Author: brukman
> Date: Thu Apr ?9 09:57:00 2009
> New Revision: 68708
>
> URL: http://llvm.org/viewvc/llvm-project?rev=68708&view=rev
> Log:
> Make sure to rebuild dependencies for the `check' and `unittests' targets so
> we're not testing out-of-date code. ?This also makes "make check" and
> "make unittests" work out-of-the box right after the configure step, without
> requiring the user to run "make tools-only" or "make libs-only".
>
> Tested on Linux/x86_64 and Darwin/x86.
>
> Modified:
> ? ?llvm/trunk/Makefile.rules
>
> Modified: llvm/trunk/Makefile.rules
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=68708&r1=68707&r2=68708&view=diff
>
> ==============================================================================
> --- llvm/trunk/Makefile.rules (original)
> +++ llvm/trunk/Makefile.rules Thu Apr ?9 09:57:00 2009
> @@ -1547,7 +1547,7 @@
> ?# CHECK: Running the test suite
> ?###############################################################################
>
> -check::
> +check:: tools-only
> ? ? ? ?$(Verb) if test -d "$(PROJ_OBJ_ROOT)/test" ; then \
> ? ? ? ? ?if test -f "$(PROJ_OBJ_ROOT)/test/Makefile" ; then \
> ? ? ? ? ? ?$(EchoCmd) Running test suite ; \
> @@ -1564,7 +1564,7 @@
> ?# UNITTESTS: Running the unittests test suite
> ?###############################################################################
>
> -unittests::
> +unittests:: libs-only
> ? ? ? ?$(Verb) if test -d "$(PROJ_OBJ_ROOT)/unittests" ; then \
> ? ? ? ? ?if test -f "$(PROJ_OBJ_ROOT)/unittests/Makefile" ; then \
> ? ? ? ? ? ?$(EchoCmd) Running unittests test suite ; \
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



From brukman at gmail.com  Thu Apr  9 15:25:18 2009
From: brukman at gmail.com (Misha Brukman)
Date: Thu, 9 Apr 2009 16:25:18 -0400
Subject: [llvm-commits] [llvm] r68708 - /llvm/trunk/Makefile.rules
In-Reply-To: <16e5fdf90904091127v1727b63bxb44220b28f5c866d@mail.gmail.com>
References: <200904091457.n39Ev5PC021643@zion.cs.uiuc.edu>
	<16e5fdf90904091127v1727b63bxb44220b28f5c866d@mail.gmail.com>
Message-ID: <f88b89a50904091325m32185f02l506bbcec3072e0b2@mail.gmail.com>

On Thu, Apr 9, 2009 at 2:27 PM, Bill Wendling <isanbard at gmail.com> wrote:

> This was causing this failure in the self-hosting buildbot:
>
> llvm[2]: Compiling lto.cpp for Debug build  (PIC)
> make[2]: *** No rule to make target
>
> `/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/Debug/lib/libLLVMBitWriter.a',
> needed by
> `/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/Release/lib/libLTO.dylib'.
>  Stop.
> make[1]: *** [all] Error 1
> make: *** [all] Error 1
>
> Could you investigate please?


Bill,

To help me reproduce this, can you tell me what configure and make command
lines were used that cause the failure?
Or, even better, can you post the buildbot config so I can run the same
configuration?

Thanks,
Misha
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From isanbard at gmail.com  Thu Apr  9 15:58:31 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 9 Apr 2009 13:58:31 -0700
Subject: [llvm-commits] [llvm] r68708 - /llvm/trunk/Makefile.rules
In-Reply-To: <f88b89a50904091325m32185f02l506bbcec3072e0b2@mail.gmail.com>
References: <200904091457.n39Ev5PC021643@zion.cs.uiuc.edu>
	<16e5fdf90904091127v1727b63bxb44220b28f5c866d@mail.gmail.com>
	<f88b89a50904091325m32185f02l506bbcec3072e0b2@mail.gmail.com>
Message-ID: <16e5fdf90904091358l66d3b3f8me0c29dd088c6b370@mail.gmail.com>

I attached the build.sh script I use to self-host LLVM. It uses the
"buildit" command, which does an Apple-style build. You can replace
that with whatever command you use to build llvm and llvm-gcc.

-bw

On Thu, Apr 9, 2009 at 1:25 PM, Misha Brukman <brukman at gmail.com> wrote:
> On Thu, Apr 9, 2009 at 2:27 PM, Bill Wendling <isanbard at gmail.com> wrote:
>>
>> This was causing this failure in the self-hosting buildbot:
>>
>> llvm[2]: Compiling lto.cpp for Debug build ?(PIC)
>> make[2]: *** No rule to make target
>>
>> `/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/Debug/lib/libLLVMBitWriter.a',
>> needed by
>> `/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/Release/lib/libLTO.dylib'.
>> ?Stop.
>> make[1]: *** [all] Error 1
>> make: *** [all] Error 1
>>
>> Could you investigate please?
>
> Bill,
>
> To help me reproduce this, can you tell me what configure and make command
> lines were used that cause the failure?
> Or, even better, can you post the buildbot config so I can run the same
> configuration?
>
> Thanks,
> Misha
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
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From dpatel at apple.com  Thu Apr  9 16:42:11 2009
From: dpatel at apple.com (Devang Patel)
Date: Thu, 09 Apr 2009 21:42:11 -0000
Subject: [llvm-commits] [llvm] r68727 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200904092142.n39LgBb3005630@zion.cs.uiuc.edu>

Author: dpatel
Date: Thu Apr  9 16:42:11 2009
New Revision: 68727

URL: http://llvm.org/viewvc/llvm-project?rev=68727&view=rev
Log:
llvm.dbg.func_start also defines beginning of function scope.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=68727&r1=68726&r2=68727&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Apr  9 16:42:11 2009
@@ -370,17 +370,13 @@
       unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir),
                                                  CompileUnit.getFilename(FN));
 
-      // Record the source line but does not create a label for the normal
-      // function start. It will be emitted at asm emission time. However,
-      // create a label if this is a beginning of inlined function.
+      // Record the source line.
       unsigned Line = Subprogram.getLineNumber();
       unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
       setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
 
-      if (DW->getRecordSourceLineCount() != 1) {
-        const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
-        BuildMI(MBB, DL, II).addImm(LabelID);
-      }
+      // llvm.dbg.func_start also defines beginning of function scope.
+      DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram()));
     }
 
     return true;




From isanbard at gmail.com  Thu Apr  9 16:49:15 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 09 Apr 2009 21:49:15 -0000
Subject: [llvm-commits] [llvm] r68728 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
Message-ID: <200904092149.n39LnFVO005899@zion.cs.uiuc.edu>

Author: void
Date: Thu Apr  9 16:49:15 2009
New Revision: 68728

URL: http://llvm.org/viewvc/llvm-project?rev=68728&view=rev
Log:
Use a StringMap instead of std::map for storing std::string->DIE* maps. This
gives a micro speedup in the Dwarf writer.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=68728&r1=68727&r2=68728&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Thu Apr  9 16:49:15 2009
@@ -727,7 +727,7 @@
 
   /// Globals - A map of globally visible named entities for this unit.
   ///
-  std::map<std::string, DIE *> Globals;
+  StringMap<DIE*> Globals;
 
   /// DiesSet - Used to uniquely define dies within the compile unit.
   ///
@@ -745,7 +745,7 @@
   // Accessors.
   unsigned getID()           const { return ID; }
   DIE* getDie()              const { return Die; }
-  std::map<std::string, DIE *> &getGlobals() { return Globals; }
+  StringMap<DIE*> &getGlobals() { return Globals; }
 
   /// hasContent - Return true if this compile unit has something to write out.
   ///
@@ -2103,8 +2103,8 @@
   void ConstructDefaultDbgScope(MachineFunction *MF) {
     const char *FnName = MF->getFunction()->getNameStart();
     if (MainCU) {
-      std::map<std::string, DIE*> &Globals = MainCU->getGlobals();
-      std::map<std::string, DIE*>::iterator GI = Globals.find(FnName);
+      StringMap<DIE*> &Globals = MainCU->getGlobals();
+      StringMap<DIE*>::iterator GI = Globals.find(FnName);
       if (GI != Globals.end()) {
         DIE *SPDie = GI->second;
 
@@ -2121,8 +2121,8 @@
     } else {
       for (unsigned i = 0, e = CompileUnits.size(); i != e; ++i) {
         CompileUnit *Unit = CompileUnits[i];
-        std::map<std::string, DIE*> &Globals = Unit->getGlobals();
-        std::map<std::string, DIE*>::iterator GI = Globals.find(FnName);
+        StringMap<DIE*> &Globals = Unit->getGlobals();
+        StringMap<DIE*>::iterator GI = Globals.find(FnName);
         if (GI != Globals.end()) {
           DIE *SPDie = GI->second;
 
@@ -2663,10 +2663,10 @@
                    true);
     Asm->EOL("Compilation Unit Length");
       
-    std::map<std::string, DIE *> &Globals = Unit->getGlobals();
-    for (std::map<std::string, DIE *>::iterator GI = Globals.begin(),
-           GE = Globals.end(); GI != GE; ++GI) {
-      const std::string &Name = GI->first;
+    StringMap<DIE*> &Globals = Unit->getGlobals();
+    for (StringMap<DIE*>::iterator
+           GI = Globals.begin(), GE = Globals.end(); GI != GE; ++GI) {
+      const std::string &Name = GI->first();
       DIE * Entity = GI->second;
         
       Asm->EmitInt32(Entity->getOffset()); Asm->EOL("DIE offset");




From resistor at mac.com  Thu Apr  9 17:19:30 2009
From: resistor at mac.com (Owen Anderson)
Date: Thu, 09 Apr 2009 22:19:30 -0000
Subject: [llvm-commits] [llvm] r68730 - in /llvm/trunk:
 include/llvm/Target/TargetRegisterInfo.h lib/Target/TargetRegisterInfo.cpp
 utils/TableGen/RegisterInfoEmitter.cpp
Message-ID: <200904092219.n39MJUmv006907@zion.cs.uiuc.edu>

Author: resistor
Date: Thu Apr  9 17:19:30 2009
New Revision: 68730

URL: http://llvm.org/viewvc/llvm-project?rev=68730&view=rev
Log:
Give register alias checking the hash table treatment too.

Modified:
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
    llvm/trunk/lib/Target/TargetRegisterInfo.cpp
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=68730&r1=68729&r2=68730&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Thu Apr  9 17:19:30 2009
@@ -226,6 +226,8 @@
   const unsigned SubregHashSize;
   const unsigned* SuperregHash;
   const unsigned SuperregHashSize;
+  const unsigned* AliasesHash;
+  const unsigned AliasesHashSize;
 public:
   typedef const TargetRegisterClass * const * regclass_iterator;
 private:
@@ -244,7 +246,9 @@
                      const unsigned* subregs = 0,
                      const unsigned subregsize = 0,
 		     const unsigned* superregs = 0,
-		     const unsigned superregsize = 0);
+		     const unsigned superregsize = 0,
+		     const unsigned* aliases = 0,
+		     const unsigned aliasessize = 0);
   virtual ~TargetRegisterInfo();
 public:
 
@@ -346,8 +350,17 @@
   /// areAliases - Returns true if the two registers alias each other, false
   /// otherwise
   bool areAliases(unsigned regA, unsigned regB) const {
-    for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
-      if (*Alias == regB) return true;
+    size_t index = (regA + regB * 37) & (AliasesHashSize-1);
+    unsigned ProbeAmt = 0;
+    while (AliasesHash[index*2] != 0 &&
+	   AliasesHash[index*2+1] != 0) {
+      if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB)
+	return true;
+
+      index = (index + ProbeAmt) & (AliasesHashSize-1);
+      ProbeAmt += 2;
+    }
+
     return false;
   }
 

Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegisterInfo.cpp?rev=68730&r1=68729&r2=68730&view=diff

==============================================================================
--- llvm/trunk/lib/Target/TargetRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetRegisterInfo.cpp Thu Apr  9 17:19:30 2009
@@ -24,9 +24,11 @@
                              regclass_iterator RCB, regclass_iterator RCE,
                              int CFSO, int CFDO,
 			     const unsigned* subregs, const unsigned subregsize,
-			 const unsigned* superregs, const unsigned superregsize)
+                         const unsigned* superregs, const unsigned superregsize,
+			 const unsigned* aliases, const unsigned aliasessize)
   : SubregHash(subregs), SubregHashSize(subregsize),
     SuperregHash(superregs), SuperregHashSize(superregsize),
+    AliasesHash(aliases), AliasesHashSize(aliasessize),
     Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) {
   assert(NumRegs < FirstVirtualRegister &&
          "Target has too many physical registers!");

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=68730&r1=68729&r2=68730&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Thu Apr  9 17:19:30 2009
@@ -540,6 +540,82 @@
   
   delete [] SuperregHashTable;
 
+
+  // Print the AliasHashTable, a simple quadratically probed
+  // hash table for determining if a register aliases another register.
+  unsigned NumAliases = 0;
+  RegNo.clear();
+  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+    RegNo[Regs[i].TheDef] = i;
+    NumAliases += RegisterAliases[Regs[i].TheDef].size();
+  }
+  
+  unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases);
+  unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize];
+  std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U);
+  
+  hashMisses = 0;
+  
+  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+    Record* R = Regs[i].TheDef;
+    for (std::set<Record*>::iterator I = RegisterAliases[R].begin(),
+         E = RegisterAliases[R].end(); I != E; ++I) {
+      Record* RJ = *I;
+      // We have to increase the indices of both registers by one when
+      // computing the hash because, in the generated code, there
+      // will be an extra empty slot at register 0.
+      size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (AliasesHashTableSize-1);
+      unsigned ProbeAmt = 2;
+      while (AliasesHashTable[index*2] != ~0U &&
+             AliasesHashTable[index*2+1] != ~0U) {
+        index = (index + ProbeAmt) & (AliasesHashTableSize-1);
+        ProbeAmt += 2;
+        
+        hashMisses++;
+      }
+      
+      AliasesHashTable[index*2] = i;
+      AliasesHashTable[index*2+1] = RegNo[RJ];
+    }
+  }
+  
+  OS << "\n\n  // Number of hash collisions: " << hashMisses << "\n";
+  
+  if (AliasesHashTableSize) {
+    std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
+    
+    OS << "  const unsigned AliasesHashTable[] = { ";
+    for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) {
+      if (i != 0)
+        // Insert spaces for nice formatting.
+        OS << "                                       ";
+      
+      if (AliasesHashTable[2*i] != ~0U) {
+        OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", "
+           << getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n";
+      } else {
+        OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
+      }
+    }
+    
+    unsigned Idx = AliasesHashTableSize*2-2;
+    if (AliasesHashTable[Idx] != ~0U) {
+      OS << "                                       "
+         << getQualifiedName(Regs[AliasesHashTable[Idx]].TheDef) << ", "
+         << getQualifiedName(Regs[AliasesHashTable[Idx+1]].TheDef) << " };\n";
+    } else {
+      OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
+    }
+    
+    OS << "  const unsigned AliasesHashTableSize = "
+       << AliasesHashTableSize << ";\n";
+  } else {
+    OS << "  const unsigned AliasesHashTable[] = { ~0U, ~0U };\n"
+       << "  const unsigned AliasesHashTableSize = 1;\n";
+  }
+  
+  delete [] AliasesHashTable;
+
   if (!RegisterAliases.empty())
     OS << "\n\n  // Register Alias Sets...\n";
 
@@ -677,7 +753,8 @@
      << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
      << "                 CallFrameSetupOpcode, CallFrameDestroyOpcode,\n"
      << "                 SubregHashTable, SubregHashTableSize,\n"
-     << "                 SuperregHashTable, SuperregHashTableSize) {\n"
+     << "                 SuperregHashTable, SuperregHashTableSize,\n"
+     << "                 AliasesHashTable, AliasesHashTableSize) {\n"
      << "}\n\n";
 
   // Collect all information about dwarf register numbers




From jyasskin at google.com  Thu Apr  9 11:40:46 2009
From: jyasskin at google.com (Jeffrey Yasskin)
Date: Thu, 9 Apr 2009 09:40:46 -0700
Subject: [llvm-commits] TypeBuilder helper class
In-Reply-To: <bb55930e0904021137i3199acb6j3108bc4c2819d9c5@mail.gmail.com>
References: <bb55930e0904021137i3199acb6j3108bc4c2819d9c5@mail.gmail.com>
Message-ID: <bb55930e0904090940o5686c16er9f8f87e9ca302ed5@mail.gmail.com>

Sorry for taking so long to reply and for replying to myself -- I
wasn't subscribed to llvm-commits when you replied.

Dan Gohman objected that an in-tree type builder should support
cross-compilation. This library _does_ support cross compilation as
long as you only use types like int32_t as template arguments, but I
can definitely see that one might want a way to constrain a use to
only allow cross-compilable types. That is, something like
CrossCompilableTypeBuilder<size_t> would fail to compile, but
HostTypeBuilder<size_t> would succeed (with better names).

I like Chris's suggestion to use sometype<64> as the TypeBuilder<>
argument when you want to be able to cross compile, but for my use,
it's also very useful to be able to say TypeBuilder<readbufferproc> (a
typedef defined in Python which involves a use of ssize_t).

I think I see how to define TypeBuilder<typename T, bool
restrict_to_cross_compilable_types> so that TypeBuilder<size_t, true>
fails to compile but TypeBuilder<sometype<64>, false> succeeds,
without duplicating code. Could you confirm that that's along the
lines of what you want implemented before I waste time implementing
it? Also, what's the right spelling for "sometype"? I'd vote for
llvm::types::i<N> or something similar.

Jeffrey

On Thu, Apr 2, 2009 at 11:37 AM, Jeffrey Yasskin <jyasskin at google.com> wrote:
> When declaring global variables and functions that are defined in the
> Python C libraries, I've found the attached class helpful.
> TypeBuilder<void(int*, size_t*)>::get() will return an LLVM Type*
> corresponding to that function type, which is otherwise quite verbose
> to build up. Let me know what you think.
>
> Jeffrey
>


From jyasskin at google.com  Thu Apr  9 16:08:32 2009
From: jyasskin at google.com (Jeffrey Yasskin)
Date: Thu, 9 Apr 2009 14:08:32 -0700
Subject: [llvm-commits] Pointer subtraction for IRBuilder
Message-ID: <bb55930e0904091408w6a4036d0obc4aabef57d8d783@mail.gmail.com>

The attached file implements IRBuilder::CreatePSub(), which performs a
C-style pointer difference on its arguments. The included test passes,
but it involves a warning that "ISO C++ forbids casting between
pointer-to-function and pointer-to-object", which I don't know how to
get rid of given the ExecutionEngine interface. I was also hoping to
assert that constant folding could produce a constant integer, but I
couldn't figure that out.

Let me know what you think. (And I'm now subscribed, so I'll get your answer.)
Jeffrey
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From stoklund at 2pi.dk  Thu Apr  9 17:45:56 2009
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 10 Apr 2009 00:45:56 +0200
Subject: [llvm-commits] [llvm] r68730 - in /llvm/trunk:
	include/llvm/Target/TargetRegisterInfo.h
	lib/Target/TargetRegisterInfo.cpp
	utils/TableGen/RegisterInfoEmitter.cpp
In-Reply-To: <200904092219.n39MJUmv006907@zion.cs.uiuc.edu>
References: <200904092219.n39MJUmv006907@zion.cs.uiuc.edu>
Message-ID: <35B16157-47A4-4555-9C30-BF7ED3D86D4E@2pi.dk>


On 10/04/2009, at 00.19, Owen Anderson wrote:

> Author: resistor
> Date: Thu Apr  9 17:19:30 2009
> New Revision: 68730
>
> URL: http://llvm.org/viewvc/llvm-project?rev=68730&view=rev
> Log:
> Give register alias checking the hash table treatment too.
>
> Modified:
>    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
>    llvm/trunk/lib/Target/TargetRegisterInfo.cpp

Owen, these two files contain tabs from this commit and from r68669.

/jakob



From eli.friedman at gmail.com  Thu Apr  9 17:49:20 2009
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 9 Apr 2009 15:49:20 -0700
Subject: [llvm-commits] Pointer subtraction for IRBuilder
In-Reply-To: <bb55930e0904091408w6a4036d0obc4aabef57d8d783@mail.gmail.com>
References: <bb55930e0904091408w6a4036d0obc4aabef57d8d783@mail.gmail.com>
Message-ID: <f5aa3e9b0904091549t19b7bb6ycb098e322ea647a7@mail.gmail.com>

On Thu, Apr 9, 2009 at 2:08 PM, Jeffrey Yasskin <jyasskin at google.com> wrote:
> The included test passes,
> but it involves a warning that "ISO C++ forbids casting between
> pointer-to-function and pointer-to-object", which I don't know how to
> get rid of given the ExecutionEngine interface.

A unittest of core IR interfaces shouldn't depend on the JIT.  I'd
suggest manually checking that the expected instructions are
generated.

-Eli


From sabre at nondot.org  Thu Apr  9 18:33:35 2009
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 09 Apr 2009 23:33:35 -0000
Subject: [llvm-commits] [llvm] r68734 -
	/llvm/trunk/lib/CodeGen/MachineInstr.cpp
Message-ID: <200904092333.n39NXZdL009515@zion.cs.uiuc.edu>

Author: lattner
Date: Thu Apr  9 18:33:34 2009
New Revision: 68734

URL: http://llvm.org/viewvc/llvm-project?rev=68734&view=rev
Log:
ignore register zero in isRegTiedToUseOperand, following the example of
isRegTiedToDefOperand.  Thanks to Bob for pointing this out!


Modified:
    llvm/trunk/lib/CodeGen/MachineInstr.cpp

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=68734&r1=68733&r2=68734&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Thu Apr  9 18:33:34 2009
@@ -698,7 +698,7 @@
   if (getOpcode() == TargetInstrInfo::INLINEASM) {
     assert(DefOpIdx >= 2);
     const MachineOperand &MO = getOperand(DefOpIdx);
-    if (!MO.isReg() || !MO.isDef())
+    if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
       return false;
     // Determine the actual operand no corresponding to this index.
     unsigned DefNo = 0;




From clattner at apple.com  Thu Apr  9 18:33:46 2009
From: clattner at apple.com (Chris Lattner)
Date: Thu, 9 Apr 2009 16:33:46 -0700
Subject: [llvm-commits] [llvm] r68712 - in /llvm/trunk:
	lib/CodeGen/MachineInstr.cpp	test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll
In-Reply-To: <1B96DBD2-4BD0-4153-985E-EAD486785235@apple.com>
References: <200904091650.n39Goh27026011@zion.cs.uiuc.edu>
	<1B96DBD2-4BD0-4153-985E-EAD486785235@apple.com>
Message-ID: <68057540-322C-4877-82D1-192A4A0C769B@apple.com>

On Apr 9, 2009, at 10:20 AM, Bob Wilson wrote:

> This change is probably also needed in the preceding
> "isRegTiedToUseOperand" method (formerly "isRegReDefinedByTwoAddr" --
> I just renamed it).  Do you agree?

Yep, agreed, thanks!




From clattner at apple.com  Thu Apr  9 18:35:55 2009
From: clattner at apple.com (Chris Lattner)
Date: Thu, 9 Apr 2009 16:35:55 -0700
Subject: [llvm-commits] [llvm] r68728 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
In-Reply-To: <200904092149.n39LnFVO005899@zion.cs.uiuc.edu>
References: <200904092149.n39LnFVO005899@zion.cs.uiuc.edu>
Message-ID: <D2A7B527-E8FB-4411-9ECD-51BDD03EEFA1@apple.com>

On Apr 9, 2009, at 2:49 PM, Bill Wendling wrote:
> URL: http://llvm.org/viewvc/llvm-project?rev=68728&view=rev
> Log:
> Use a StringMap instead of std::map for storing std::string->DIE*  
> maps. This
> gives a micro speedup in the Dwarf writer.

Hi Bill,

> +    StringMap<DIE*> &Globals = Unit->getGlobals();
> +    for (StringMap<DIE*>::iterator
> +           GI = Globals.begin(), GE = Globals.end(); GI != GE; + 
> +GI) {
> +      const std::string &Name = GI->first();
>       DIE * Entity = GI->second;

Note that GI->first() returns a const char*, not an std::string.  This  
means that you're creating a temporary string object every time you  
iterate over this.  Please update this (and other places that poke the  
map) to use better APIs.

Thanks,

-Chris



From dpatel at apple.com  Thu Apr  9 18:45:17 2009
From: dpatel at apple.com (Devang Patel)
Date: Thu, 09 Apr 2009 23:45:17 -0000
Subject: [llvm-commits] [llvm] r68735 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200904092345.n39NjHBN009878@zion.cs.uiuc.edu>

Author: dpatel
Date: Thu Apr  9 18:45:17 2009
New Revision: 68735

URL: http://llvm.org/viewvc/llvm-project?rev=68735&view=rev
Log:
Silence unused variable warning.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=68735&r1=68734&r2=68735&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Apr  9 18:45:17 2009
@@ -372,7 +372,7 @@
 
       // Record the source line.
       unsigned Line = Subprogram.getLineNumber();
-      unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
+      DW->RecordSourceLine(Line, 0, SrcFile);
       setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
 
       // llvm.dbg.func_start also defines beginning of function scope.




From isanbard at gmail.com  Thu Apr  9 18:51:31 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 09 Apr 2009 23:51:31 -0000
Subject: [llvm-commits] [llvm] r68741 - in /llvm/trunk:
 include/llvm/CodeGen/AsmPrinter.h lib/CodeGen/AsmPrinter/AsmPrinter.cpp
 lib/CodeGen/AsmPrinter/DwarfWriter.cpp
Message-ID: <200904092351.n39NpV2c010161@zion.cs.uiuc.edu>

Author: void
Date: Thu Apr  9 18:51:31 2009
New Revision: 68741

URL: http://llvm.org/viewvc/llvm-project?rev=68741&view=rev
Log:
StringMap<DIE*>::iterator::first() returns a pointer to the first character of
the key. This will cause it to create a new std::string, which isn't
wanted. Instead, pass back the "const char*". Modify the EmitString() method to
take a "const char*".

Modified:
    llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=68741&r1=68740&r2=68741&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Thu Apr  9 18:51:31 2009
@@ -285,7 +285,8 @@
     /// Special characters are emitted properly.
     /// @verbatim (Eg. '\t') @endverbatim
     void EmitString(const std::string &String) const;
-    
+    void EmitString(const char *String, unsigned Size) const;
+
     /// EmitFile - Emit a .file directive.
     void EmitFile(unsigned Number, const std::string &Name) const;
 

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=68741&r1=68740&r2=68741&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Apr  9 18:51:31 2009
@@ -727,13 +727,17 @@
 /// Special characters are emitted properly.
 /// \literal (Eg. '\t') \endliteral
 void AsmPrinter::EmitString(const std::string &String) const {
+  EmitString(String.c_str(), String.size());
+}
+
+void AsmPrinter::EmitString(const char *String, unsigned Size) const {
   const char* AscizDirective = TAI->getAscizDirective();
   if (AscizDirective)
     O << AscizDirective;
   else
     O << TAI->getAsciiDirective();
   O << '\"';
-  for (unsigned i = 0, N = String.size(); i < N; ++i)
+  for (unsigned i = 0; i < Size; ++i)
     printStringChar(O, String[i]);
   if (AscizDirective)
     O << '\"';

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=68741&r1=68740&r2=68741&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Thu Apr  9 18:51:31 2009
@@ -2664,13 +2664,13 @@
     Asm->EOL("Compilation Unit Length");
       
     StringMap<DIE*> &Globals = Unit->getGlobals();
-    for (StringMap<DIE*>::iterator
+    for (StringMap<DIE*>::const_iterator
            GI = Globals.begin(), GE = Globals.end(); GI != GE; ++GI) {
-      const std::string &Name = GI->first();
+      const char *Name = GI->getKeyData();
       DIE * Entity = GI->second;
         
       Asm->EmitInt32(Entity->getOffset()); Asm->EOL("DIE offset");
-      Asm->EmitString(Name); Asm->EOL("External Name");
+      Asm->EmitString(Name, strlen(Name)); Asm->EOL("External Name");
     }
       
     Asm->EmitInt32(0); Asm->EOL("End Mark");




From isanbard at gmail.com  Thu Apr  9 18:52:09 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 9 Apr 2009 16:52:09 -0700
Subject: [llvm-commits] [llvm] r68728 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
In-Reply-To: <D2A7B527-E8FB-4411-9ECD-51BDD03EEFA1@apple.com>
References: <200904092149.n39LnFVO005899@zion.cs.uiuc.edu>
	<D2A7B527-E8FB-4411-9ECD-51BDD03EEFA1@apple.com>
Message-ID: <16e5fdf90904091652j4063993dmd492b96179948ba@mail.gmail.com>

On Thu, Apr 9, 2009 at 4:35 PM, Chris Lattner <clattner at apple.com> wrote:
> On Apr 9, 2009, at 2:49 PM, Bill Wendling wrote:
>> + ? ?StringMap<DIE*> &Globals = Unit->getGlobals();
>> + ? ?for (StringMap<DIE*>::iterator
>> + ? ? ? ? ? GI = Globals.begin(), GE = Globals.end(); GI != GE; +
>> +GI) {
>> + ? ? ?const std::string &Name = GI->first();
>> ? ? ? DIE * Entity = GI->second;
>
> Note that GI->first() returns a const char*, not an std::string. ?This
> means that you're creating a temporary string object every time you
> iterate over this. ?Please update this (and other places that poke the
> map) to use better APIs.
>
Ah! Okay. I modified it now. Thanks for catching this!

-bw



From gohman at apple.com  Thu Apr  9 18:53:32 2009
From: gohman at apple.com (Dan Gohman)
Date: Thu, 09 Apr 2009 23:53:32 -0000
Subject: [llvm-commits] [llvm] r68742 -
	/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
Message-ID: <200904092353.n39NrWEl010240@zion.cs.uiuc.edu>

Author: djg
Date: Thu Apr  9 18:53:31 2009
New Revision: 68742

URL: http://llvm.org/viewvc/llvm-project?rev=68742&view=rev
Log:
Change the NumVTs field from short to int, since there's no
real need for it to be short.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=68742&r1=68741&r2=68742&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Apr  9 18:53:31 2009
@@ -52,7 +52,7 @@
 ///
 struct SDVTList {
   const MVT *VTs;
-  unsigned short NumVTs;
+  unsigned int NumVTs;
 };
 
 /// ISD namespace - This namespace contains an enum which represents all of the




From gohman at apple.com  Thu Apr  9 18:54:41 2009
From: gohman at apple.com (Dan Gohman)
Date: Thu, 09 Apr 2009 23:54:41 -0000
Subject: [llvm-commits] [llvm] r68744 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAG.h
 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
 lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
 lib/Target/Mips/MipsISelLowering.cpp lib/Target/X86/X86ISelLowering.cpp
Message-ID: <200904092354.n39NsgpS010311@zion.cs.uiuc.edu>

Author: djg
Date: Thu Apr  9 18:54:40 2009
New Revision: 68744

URL: http://llvm.org/viewvc/llvm-project?rev=68744&view=rev
Log:
Remove the obsolete SelectionDAG::getNodeValueTypes and simplify
code that uses it by using SelectionDAG::getVTList instead.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=68744&r1=68743&r2=68744&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Thu Apr  9 18:54:40 2009
@@ -236,24 +236,6 @@
   SDVTList getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4);
   SDVTList getVTList(const MVT *VTs, unsigned NumVTs);
 
-  /// getNodeValueTypes - These are obsolete, use getVTList instead.
-  const MVT *getNodeValueTypes(MVT VT) {
-    return getVTList(VT).VTs;
-  }
-  const MVT *getNodeValueTypes(MVT VT1, MVT VT2) {
-    return getVTList(VT1, VT2).VTs;
-  }
-  const MVT *getNodeValueTypes(MVT VT1, MVT VT2, MVT VT3) {
-    return getVTList(VT1, VT2, VT3).VTs;
-  }
-  const MVT *getNodeValueTypes(MVT VT1, MVT VT2, MVT VT3, MVT VT4) {
-    return getVTList(VT1, VT2, VT3, VT4).VTs;
-  }
-  const MVT *getNodeValueTypes(const std::vector<MVT> &vtList) {
-    return getVTList(&vtList[0], (unsigned)vtList.size()).VTs;
-  }
-
-
   //===--------------------------------------------------------------------===//
   // Node creation methods.
   //
@@ -335,23 +317,23 @@
   // null) and that there should be a flag result.
   SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N,
                          SDValue Flag) {
-    const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
+    SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
     SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag };
-    return getNode(ISD::CopyToReg, dl, VTs, 2, Ops, Flag.getNode() ? 4 : 3);
+    return getNode(ISD::CopyToReg, dl, VTs, Ops, Flag.getNode() ? 4 : 3);
   }
 
   // Similar to last getCopyToReg() except parameter Reg is a SDValue
   SDValue getCopyToReg(SDValue Chain, DebugLoc dl, SDValue Reg, SDValue N,
                          SDValue Flag) {
-    const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
+    SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
     SDValue Ops[] = { Chain, Reg, N, Flag };
-    return getNode(ISD::CopyToReg, dl, VTs, 2, Ops, Flag.getNode() ? 4 : 3);
+    return getNode(ISD::CopyToReg, dl, VTs, Ops, Flag.getNode() ? 4 : 3);
   }
 
   SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, MVT VT) {
-    const MVT *VTs = getNodeValueTypes(VT, MVT::Other);
+    SDVTList VTs = getVTList(VT, MVT::Other);
     SDValue Ops[] = { Chain, getRegister(Reg, VT) };
-    return getNode(ISD::CopyFromReg, dl, VTs, 2, Ops, 2);
+    return getNode(ISD::CopyFromReg, dl, VTs, Ops, 2);
   }
 
   // This version of the getCopyFromReg method takes an extra operand, which
@@ -359,9 +341,9 @@
   // null) and that there should be a flag result.
   SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, MVT VT,
                            SDValue Flag) {
-    const MVT *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag);
+    SDVTList VTs = getVTList(VT, MVT::Other, MVT::Flag);
     SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag };
-    return getNode(ISD::CopyFromReg, dl, VTs, 3, Ops, Flag.getNode() ? 3 : 2);
+    return getNode(ISD::CopyFromReg, dl, VTs, Ops, Flag.getNode() ? 3 : 2);
   }
 
   SDValue getCondCode(ISD::CondCode Cond);
@@ -383,10 +365,10 @@
   /// a flag result (to ensure it's not CSE'd).  CALLSEQ_START does not have a
   /// useful DebugLoc.
   SDValue getCALLSEQ_START(SDValue Chain, SDValue Op) {
-    const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
+    SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
     SDValue Ops[] = { Chain,  Op };
     return getNode(ISD::CALLSEQ_START, DebugLoc::getUnknownLoc(),
-                   VTs, 2, Ops, 2);
+                   VTs, Ops, 2);
   }
 
   /// getCALLSEQ_END - Return a new CALLSEQ_END node, which always must have a

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=68744&r1=68743&r2=68744&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Apr  9 18:54:40 2009
@@ -5662,7 +5662,7 @@
 
   SDValue Ops[] = { LHSL, LHSH, Amt };
   MVT VT = LHSL.getValueType();
-  Lo = DAG.getNode(NodeOp, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
+  Lo = DAG.getNode(NodeOp, dl, DAG.getVTList(VT, VT), Ops, 3);
   Hi = Lo.getValue(1);
 }
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=68744&r1=68743&r2=68744&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Thu Apr  9 18:54:40 2009
@@ -1824,7 +1824,7 @@
 
     SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
     MVT VT = LHSL.getValueType();
-    Lo = DAG.getNode(PartsOpc, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
+    Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
     Hi = Lo.getValue(1);
     return;
   }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=68744&r1=68743&r2=68744&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Apr  9 18:54:40 2009
@@ -2131,7 +2131,7 @@
   if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
     return SDValue(E, 0);
   SDNode *N = NodeAllocator.Allocate<SDNode>();
-  new (N) SDNode(Opcode, DL, SDNode::getSDVTList(VT));
+  new (N) SDNode(Opcode, DL, getVTList(VT));
   CSEMap.InsertNode(N, IP);
 
   AllNodes.push_back(N);
@@ -3724,7 +3724,7 @@
 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
                               const std::vector<MVT> &ResultTys,
                               const SDValue *Ops, unsigned NumOps) {
-  return getNode(Opcode, DL, getNodeValueTypes(ResultTys), ResultTys.size(),
+  return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()),
                  Ops, NumOps);
 }
 
@@ -4360,82 +4360,75 @@
 
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
                                     MVT VT1, MVT VT2) {
-  const MVT *VTs = getNodeValueTypes(VT1, VT2);
+  SDVTList VTs = getVTList(VT1, VT2);
   SDValue Op;
-  return getNode(~Opcode, dl, VTs, 2, &Op, 0).getNode();
+  return getNode(~Opcode, dl, VTs, &Op, 0).getNode();
 }
 
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
                                     MVT VT2, SDValue Op1) {
-  const MVT *VTs = getNodeValueTypes(VT1, VT2);
-  return getNode(~Opcode, dl, VTs, 2, &Op1, 1).getNode();
+  SDVTList VTs = getVTList(VT1, VT2);
+  return getNode(~Opcode, dl, VTs, &Op1, 1).getNode();
 }
 
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
                                     MVT VT2, SDValue Op1,
                                     SDValue Op2) {
-  const MVT *VTs = getNodeValueTypes(VT1, VT2);
+  SDVTList VTs = getVTList(VT1, VT2);
   SDValue Ops[] = { Op1, Op2 };
-  return getNode(~Opcode, dl, VTs, 2, Ops, 2).getNode();
+  return getNode(~Opcode, dl, VTs, Ops, 2).getNode();
 }
 
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
                                     MVT VT2, SDValue Op1,
                                     SDValue Op2, SDValue Op3) {
-  const MVT *VTs = getNodeValueTypes(VT1, VT2);
+  SDVTList VTs = getVTList(VT1, VT2);
   SDValue Ops[] = { Op1, Op2, Op3 };
-  return getNode(~Opcode, dl, VTs, 2, Ops, 3).getNode();
+  return getNode(~Opcode, dl, VTs, Ops, 3).getNode();
 }
 
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
                                     MVT VT1, MVT VT2,
                                     const SDValue *Ops, unsigned NumOps) {
-  const MVT *VTs = getNodeValueTypes(VT1, VT2);
-  return getNode(~Opcode, dl, VTs, 2, Ops, NumOps).getNode();
+  SDVTList VTs = getVTList(VT1, VT2);
+  return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
 }
 
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
                                     MVT VT1, MVT VT2, MVT VT3,
                                     SDValue Op1, SDValue Op2) {
-  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
+  SDVTList VTs = getVTList(VT1, VT2, VT3);
   SDValue Ops[] = { Op1, Op2 };
-  return getNode(~Opcode, dl, VTs, 3, Ops, 2).getNode();
+  return getNode(~Opcode, dl, VTs, Ops, 2).getNode();
 }
 
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
                                     MVT VT1, MVT VT2, MVT VT3,
                                     SDValue Op1, SDValue Op2,
                                     SDValue Op3) {
-  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
+  SDVTList VTs = getVTList(VT1, VT2, VT3);
   SDValue Ops[] = { Op1, Op2, Op3 };
-  return getNode(~Opcode, dl, VTs, 3, Ops, 3).getNode();
+  return getNode(~Opcode, dl, VTs, Ops, 3).getNode();
 }
 
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
                                     MVT VT1, MVT VT2, MVT VT3,
                                     const SDValue *Ops, unsigned NumOps) {
-  const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
-  return getNode(~Opcode, dl, VTs, 3, Ops, NumOps).getNode();
+  SDVTList VTs = getVTList(VT1, VT2, VT3);
+  return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
 }
 
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
                                     MVT VT2, MVT VT3, MVT VT4,
                                     const SDValue *Ops, unsigned NumOps) {
-  std::vector<MVT> VTList;
-  VTList.push_back(VT1);
-  VTList.push_back(VT2);
-  VTList.push_back(VT3);
-  VTList.push_back(VT4);
-  const MVT *VTs = getNodeValueTypes(VTList);
-  return getNode(~Opcode, dl, VTs, 4, Ops, NumOps).getNode();
+  SDVTList VTs = getVTList(VT1, VT2, VT3, VT4);
+  return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
 }
 
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
                                     const std::vector<MVT> &ResultTys,
                                     const SDValue *Ops, unsigned NumOps) {
-  const MVT *VTs = getNodeValueTypes(ResultTys);
-  return getNode(~Opcode, dl, VTs, ResultTys.size(),
-                 Ops, NumOps).getNode();
+  return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode();
 }
 
 /// getNodeIfExists - Get the specified node if it's already available, or

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=68744&r1=68743&r2=68744&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Thu Apr  9 18:54:40 2009
@@ -2825,10 +2825,9 @@
                           DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
 
   SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
-  const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
-                                                    MVT::Other);
+  SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
   SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
-                            VTs, 2, Ops, 3);
+                            VTs, Ops, 3);
   setValue(&I, DSA);
   DAG.setRoot(DSA.getValue(1));
 
@@ -2965,7 +2964,7 @@
     Ops.push_back(Op);
   }
 
-  std::vector<MVT> VTs;
+  std::vector<MVT> VTArray;
   if (I.getType() != Type::VoidTy) {
     MVT VT = TLI.getValueType(I.getType());
     if (VT.isVector()) {
@@ -2977,36 +2976,32 @@
     }
 
     assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
-    VTs.push_back(VT);
+    VTArray.push_back(VT);
   }
   if (HasChain)
-    VTs.push_back(MVT::Other);
+    VTArray.push_back(MVT::Other);
 
-  const MVT *VTList = DAG.getNodeValueTypes(VTs);
+  SDVTList VTs = DAG.getVTList(&VTArray[0], VTArray.size());
 
   // Create the node.
   SDValue Result;
   if (IsTgtIntrinsic) {
     // This is target intrinsic that touches memory
     Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
-                                     VTList, VTs.size(),
-                                     &Ops[0], Ops.size(),
+                                     VTs, &Ops[0], Ops.size(),
                                      Info.memVT, Info.ptrVal, Info.offset,
                                      Info.align, Info.vol,
                                      Info.readMem, Info.writeMem);
   }
   else if (!HasChain)
     Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
-                         VTList, VTs.size(),
-                         &Ops[0], Ops.size());
+                         VTs, &Ops[0], Ops.size());
   else if (I.getType() != Type::VoidTy)
     Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
-                         VTList, VTs.size(),
-                         &Ops[0], Ops.size());
+                         VTs, &Ops[0], Ops.size());
   else
     Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
-                         VTList, VTs.size(),
-                         &Ops[0], Ops.size());
+                         VTs, &Ops[0], Ops.size());
 
   if (HasChain) {
     SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
@@ -3153,11 +3148,8 @@
   SDValue Op1 = getValue(I.getOperand(1));
   SDValue Op2 = getValue(I.getOperand(2));
 
-  MVT ValueVTs[] = { Op1.getValueType(), MVT::i1 };
-  SDValue Ops[] = { Op1, Op2 };
-
-  SDValue Result = DAG.getNode(Op, getCurDebugLoc(),
-                               DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
+  SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
+  SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
 
   setValue(&I, Result);
   return 0;
@@ -4211,8 +4203,8 @@
   case Intrinsic::readcyclecounter: {
     SDValue Op = getRoot();
     SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
-                                DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
-                                &Op, 1);
+                              DAG.getVTList(MVT::i64, MVT::Other),
+                              &Op, 1);
     setValue(&I, Tmp);
     DAG.setRoot(Tmp.getValue(1));
     return 0;
@@ -4256,7 +4248,7 @@
   case Intrinsic::stacksave: {
     SDValue Op = getRoot();
     SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
-              DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
+              DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
     setValue(&I, Tmp);
     DAG.setRoot(Tmp.getValue(1));
     return 0;
@@ -4304,9 +4296,8 @@
     Ops[5] = DAG.getSrcValue(F);
 
     SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
-                                DAG.getNodeValueTypes(TLI.getPointerTy(),
-                                                      MVT::Other), 2,
-                                Ops, 6);
+                              DAG.getVTList(TLI.getPointerTy(), MVT::Other),
+                              Ops, 6);
 
     setValue(&I, Tmp);
     DAG.setRoot(Tmp.getValue(1));
@@ -5393,7 +5384,7 @@
   if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
 
   Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
-                      DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
+                      DAG.getVTList(MVT::Other, MVT::Flag),
                       &AsmNodeOperands[0], AsmNodeOperands.size());
   Flag = Chain.getValue(1);
 

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=68744&r1=68743&r2=68744&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Apr  9 18:54:40 2009
@@ -475,16 +475,16 @@
   SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
 
   if (!Subtarget->hasABICall()) {
-    const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
+    SDVTList VTs = DAG.getVTList(MVT::i32);
     SDValue Ops[] = { GA };
     // %gp_rel relocation
     if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) { 
-      SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, 1, Ops, 1);
+      SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, Ops, 1);
       SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
       return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); 
     }
     // %hi/%lo relocation
-    SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, 1, Ops, 1);
+    SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1);
     SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
     return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
 
@@ -523,9 +523,9 @@
   SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
 
   if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
-    const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
+    SDVTList VTs = DAG.getVTList(MVT::i32);
     SDValue Ops[] = { JTI };
-    HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, 1, Ops, 1);
+    HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1);
   } else // Emit Load from Global Pointer
     HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
 

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=68744&r1=68743&r2=68744&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Apr  9 18:54:40 2009
@@ -5481,11 +5481,11 @@
       break;
     }
     if (Opcode != 0) {
-      const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::i32);
+      SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
       SmallVector<SDValue, 4> Ops;
       for (unsigned i = 0; i != NumOperands; ++i)
         Ops.push_back(Op.getOperand(i));
-      SDValue New = DAG.getNode(Opcode, dl, VTs, 2, &Ops[0], NumOperands);
+      SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
       DAG.ReplaceAllUsesWith(Op, New);
       return SDValue(New.getNode(), 1);
     }
@@ -5740,8 +5740,7 @@
     Cond = EmitTest(Cond, X86::COND_NE, DAG);
   }
 
-  const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
-                                                    MVT::Flag);
+  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
   SmallVector<SDValue, 4> Ops;
   // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
   // condition is true.
@@ -5749,7 +5748,7 @@
   Ops.push_back(Op.getOperand(1));
   Ops.push_back(CC);
   Ops.push_back(Cond);
-  return DAG.getNode(X86ISD::CMOV, dl, VTs, 2, &Ops[0], Ops.size());
+  return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size());
 }
 
 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or




From jyasskin at google.com  Thu Apr  9 18:56:59 2009
From: jyasskin at google.com (Jeffrey Yasskin)
Date: Thu, 9 Apr 2009 16:56:59 -0700
Subject: [llvm-commits] Pointer subtraction for IRBuilder
In-Reply-To: <f5aa3e9b0904091549t19b7bb6ycb098e322ea647a7@mail.gmail.com>
References: <bb55930e0904091408w6a4036d0obc4aabef57d8d783@mail.gmail.com>
	<f5aa3e9b0904091549t19b7bb6ycb098e322ea647a7@mail.gmail.com>
Message-ID: <bb55930e0904091656v1d094ab6s4af98430cc1d6a60@mail.gmail.com>

On Thu, Apr 9, 2009 at 3:49 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Thu, Apr 9, 2009 at 2:08 PM, Jeffrey Yasskin <jyasskin at google.com> wrote:
>> The included test passes,
>> but it involves a warning that "ISO C++ forbids casting between
>> pointer-to-function and pointer-to-object", which I don't know how to
>> get rid of given the ExecutionEngine interface.
>
> A unittest of core IR interfaces shouldn't depend on the JIT. ?I'd
> suggest manually checking that the expected instructions are
> generated.

I'm happy to do that if you want, but is it really a useful test?
i.e., does having a test that asserts that an sdiv was inserted add
anything to code that says, "CreateSDiv"? Another option would be to
add to the regression test suite instead of the unittest suite.

If you want me to assert against the instructions, is there any more
concise way to do it than a series of isa tests and operand
retrievals?

Thanks,
Jeffrey



From isanbard at gmail.com  Thu Apr  9 19:00:25 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 10 Apr 2009 00:00:25 -0000
Subject: [llvm-commits] [llvm] r68745 - in /llvm/trunk:
 include/llvm/CodeGen/AsmPrinter.h lib/CodeGen/AsmPrinter/AsmPrinter.cpp
 lib/CodeGen/AsmPrinter/DwarfWriter.cpp
Message-ID: <200904100000.n3A00P9k010473@zion.cs.uiuc.edu>

Author: void
Date: Thu Apr  9 19:00:25 2009
New Revision: 68745

URL: http://llvm.org/viewvc/llvm-project?rev=68745&view=rev
Log:
Constify getter methods.

Modified:
    llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=68745&r1=68744&r2=68745&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Thu Apr  9 19:00:25 2009
@@ -162,7 +162,7 @@
     /// getCurrentFunctionEHName - Called to return (and cache) the
     /// CurrentFnEHName.
     /// 
-    std::string getCurrentFunctionEHName(const MachineFunction *MF);
+    std::string getCurrentFunctionEHName(const MachineFunction *MF) const;
 
   protected:
     /// getAnalysisUsage - Record analysis usage.

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=68745&r1=68744&r2=68745&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Apr  9 19:00:25 2009
@@ -236,7 +236,8 @@
   return false;
 }
 
-std::string AsmPrinter::getCurrentFunctionEHName(const MachineFunction *MF) {
+std::string
+AsmPrinter::getCurrentFunctionEHName(const MachineFunction *MF) const {
   assert(MF && "No machine function?");
   std::string Name = MF->getFunction()->getName();
   if (Name.empty())

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=68745&r1=68744&r2=68745&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Thu Apr  9 19:00:25 2009
@@ -858,7 +858,7 @@
   //===--------------------------------------------------------------------===//
   // Accessors.
   //
-  AsmPrinter *getAsm() const { return Asm; }
+  const AsmPrinter *getAsm() const { return Asm; }
   MachineModuleInfo *getMMI() const { return MMI; }
   const TargetAsmInfo *getTargetAsmInfo() const { return TAI; }
   const TargetData *getTargetData() const { return TD; }




From isanbard at gmail.com  Thu Apr  9 19:12:50 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 10 Apr 2009 00:12:50 -0000
Subject: [llvm-commits] [llvm] r68747 - in /llvm/trunk:
 include/llvm/CodeGen/AsmPrinter.h lib/CodeGen/AsmPrinter/AsmPrinter.cpp
 lib/CodeGen/AsmPrinter/DwarfWriter.cpp
 lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
Message-ID: <200904100012.n3A0CqEB010909@zion.cs.uiuc.edu>

Author: void
Date: Thu Apr  9 19:12:49 2009
New Revision: 68747

URL: http://llvm.org/viewvc/llvm-project?rev=68747&view=rev
Log:
Pass in the std::string parameter instead of returning it by value.

Modified:
    llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
    llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=68747&r1=68746&r2=68747&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Thu Apr  9 19:12:49 2009
@@ -153,7 +153,8 @@
     /// getGlobalLinkName - Returns the asm/link name of of the specified
     /// global variable.  Should be overridden by each target asm printer to
     /// generate the appropriate value.
-    virtual const std::string getGlobalLinkName(const GlobalVariable *GV) const;
+    virtual const std::string &getGlobalLinkName(const GlobalVariable *GV,
+                                                 std::string &LinkName) const;
 
     /// EmitExternalGlobal - Emit the external reference to a global variable.
     /// Should be overridden if an indirect reference should be used.
@@ -162,7 +163,8 @@
     /// getCurrentFunctionEHName - Called to return (and cache) the
     /// CurrentFnEHName.
     /// 
-    std::string getCurrentFunctionEHName(const MachineFunction *MF) const;
+    const std::string &getCurrentFunctionEHName(const MachineFunction *MF,
+                                                std::string &FuncEHName) const;
 
   protected:
     /// getAnalysisUsage - Record analysis usage.

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=68747&r1=68746&r2=68747&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Apr  9 19:12:49 2009
@@ -186,11 +186,8 @@
       SwitchToDataSection("");
 
     for (std::set<const GlobalValue*>::iterator i = ExtWeakSymbols.begin(),
-         e = ExtWeakSymbols.end(); i != e; ++i) {
-      const GlobalValue *GV = *i;
-      std::string Name = Mang->getValueName(GV);
-      O << TAI->getWeakRefDirective() << Name << '\n';
-    }
+         e = ExtWeakSymbols.end(); i != e; ++i)
+      O << TAI->getWeakRefDirective() << Mang->getValueName(*i) << '\n';
   }
 
   if (TAI->getSetDirective()) {
@@ -236,14 +233,16 @@
   return false;
 }
 
-std::string
-AsmPrinter::getCurrentFunctionEHName(const MachineFunction *MF) const {
+const std::string &
+AsmPrinter::getCurrentFunctionEHName(const MachineFunction *MF,
+                                     std::string &Name) const {
   assert(MF && "No machine function?");
-  std::string Name = MF->getFunction()->getName();
+  Name = MF->getFunction()->getName();
   if (Name.empty())
     Name = Mang->getValueName(MF->getFunction());
-  return Mang->makeNameProper(TAI->getEHGlobalPrefix() +
+  Name = Mang->makeNameProper(TAI->getEHGlobalPrefix() +
                               Name + ".eh", TAI->getGlobalPrefix());
+  return Name;
 }
 
 void AsmPrinter::SetupMachineFunction(MachineFunction &MF) {
@@ -536,9 +535,8 @@
 /// getGlobalLinkName - Returns the asm/link name of of the specified
 /// global variable.  Should be overridden by each target asm printer to
 /// generate the appropriate value.
-const std::string AsmPrinter::getGlobalLinkName(const GlobalVariable *GV) const{
-  std::string LinkName;
-  
+const std::string &AsmPrinter::getGlobalLinkName(const GlobalVariable *GV,
+                                                 std::string &LinkName) const {
   if (isa<Function>(GV)) {
     LinkName += TAI->getFunctionAddrPrefix();
     LinkName += Mang->getValueName(GV);
@@ -555,7 +553,8 @@
 /// EmitExternalGlobal - Emit the external reference to a global variable.
 /// Should be overridden if an indirect reference should be used.
 void AsmPrinter::EmitExternalGlobal(const GlobalVariable *GV) {
-  O << getGlobalLinkName(GV);
+  std::string GLN;
+  O << getGlobalLinkName(GV, GLN);
 }
 
 

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=68747&r1=68746&r2=68747&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Thu Apr  9 19:12:49 2009
@@ -2888,8 +2888,9 @@
     // Add address.
     DIEBlock *Block = new DIEBlock();
     AddUInt(Block, 0, DW_FORM_data1, DW_OP_addr);
+    std::string GLN;
     AddObjectLabel(Block, 0, DW_FORM_udata,
-                   Asm->getGlobalLinkName(DI_GV.getGlobal()));
+                   Asm->getGlobalLinkName(DI_GV.getGlobal(), GLN));
     AddBlock(VariableDie, DW_AT_location, 0, Block);
 
     // Add to map.
@@ -4009,10 +4010,12 @@
 
       PrintRelDirective();
 
-      if (GV)
-        O << Asm->getGlobalLinkName(GV);
-      else
+      if (GV) {
+        std::string GLN;
+        O << Asm->getGlobalLinkName(GV, GLN);
+      } else {
         O << "0";
+      }
 
       Asm->EOL("TypeInfo");
     }
@@ -4120,14 +4123,15 @@
       EmitExceptionTable();
 
       // Save EH frame information
-      EHFrames.
-        push_back(FunctionEHFrameInfo(getAsm()->getCurrentFunctionEHName(MF),
-                                      SubprogramCount,
-                                      MMI->getPersonalityIndex(),
-                                      MF->getFrameInfo()->hasCalls(),
-                                      !MMI->getLandingPads().empty(),
-                                      MMI->getFrameMoves(),
-                                      MF->getFunction()));
+      std::string Name;
+      EHFrames.push_back(
+        FunctionEHFrameInfo(getAsm()->getCurrentFunctionEHName(MF, Name),
+                            SubprogramCount,
+                            MMI->getPersonalityIndex(),
+                            MF->getFrameInfo()->hasCalls(),
+                            !MMI->getLandingPads().empty(),
+                            MMI->getFrameMoves(),
+                            MF->getFunction()));
     }
 
     if (TimePassesIsEnabled) 

Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=68747&r1=68746&r2=68747&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Thu Apr  9 19:12:49 2009
@@ -423,7 +423,8 @@
 /// EmitExternalGlobal - In this case we need to use the indirect symbol.
 ///
 void PPCAsmPrinter::EmitExternalGlobal(const GlobalVariable *GV) {
-  std::string Name = getGlobalLinkName(GV);
+  std::string Name;
+  getGlobalLinkName(GV, Name);
   if (TM.getRelocationModel() != Reloc::Static) {
     if (GV->hasHiddenVisibility())
       HiddenGVStubs.insert(Name);




From sabre at nondot.org  Thu Apr  9 19:16:23 2009
From: sabre at nondot.org (Chris Lattner)
Date: Fri, 10 Apr 2009 00:16:23 -0000
Subject: [llvm-commits] [llvm] r68749 -
	/llvm/trunk/lib/Target/X86/X86InstrInfo.td
Message-ID: <200904100016.n3A0GP1G011041@zion.cs.uiuc.edu>

Author: lattner
Date: Thu Apr  9 19:16:23 2009
New Revision: 68749

URL: http://llvm.org/viewvc/llvm-project?rev=68749&view=rev
Log:
a few fixes to "addrspace(256) is reference offset of GS segment register".

It turns out that there are still several problems with this, will file a bugzilla.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=68749&r1=68748&r2=68749&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Apr  9 19:16:23 2009
@@ -277,6 +277,10 @@
 // known to be 32-bit aligned or better. Ditto for i8 to i16.
 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
   LoadSDNode *LD = cast<LoadSDNode>(N);
+  if (const Value *Src = LD->getSrcValue())
+    if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+      if (PT->getAddressSpace() != 0)
+        return false;
   ISD::LoadExtType ExtType = LD->getExtensionType();
   if (ExtType == ISD::NON_EXTLOAD)
     return true;
@@ -287,6 +291,10 @@
 
 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
   LoadSDNode *LD = cast<LoadSDNode>(N);
+  if (const Value *Src = LD->getSrcValue())
+    if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+      if (PT->getAddressSpace() != 0)
+        return false;
   ISD::LoadExtType ExtType = LD->getExtensionType();
   if (ExtType == ISD::EXTLOAD)
     return LD->getAlignment() >= 2 && !LD->isVolatile();
@@ -295,6 +303,10 @@
 
 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
   LoadSDNode *LD = cast<LoadSDNode>(N);
+  if (const Value *Src = LD->getSrcValue())
+    if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+      if (PT->getAddressSpace() != 0)
+        return false;
   ISD::LoadExtType ExtType = LD->getExtensionType();
   if (ExtType == ISD::NON_EXTLOAD)
     return true;
@@ -305,6 +317,10 @@
 
 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
   LoadSDNode *LD = cast<LoadSDNode>(N);
+  if (const Value *Src = LD->getSrcValue())
+    if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+      if (PT->getAddressSpace() != 0)
+        return false;
   if (LD->isVolatile())
     return false;
   ISD::LoadExtType ExtType = LD->getExtensionType();
@@ -316,21 +332,48 @@
 }]>;
 
 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
-  LoadSDNode *LD = cast<LoadSDNode>(N);
-  const Value *Src = LD->getSrcValue();
-  if (!Src)
-    return false;
-  if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
-    return PT->getAddressSpace() == 256;
+  if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
+    if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+      return PT->getAddressSpace() == 256;
   return false;
 }]>;
 
-def loadi8  : PatFrag<(ops node:$ptr), (i8  (load node:$ptr))>;
-def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
+def loadi8  : PatFrag<(ops node:$ptr), (i8  (load node:$ptr)), [{
+  if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
+    if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+      if (PT->getAddressSpace() != 0)
+        return false;
+  return true;
+}]>;
+def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
+  if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
+    if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+      if (PT->getAddressSpace() != 0)
+        return false;
+  return true;
+}]>;
 
-def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
-def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
-def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
+def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
+  if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
+    if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+      if (PT->getAddressSpace() != 0)
+        return false;
+  return true;
+}]>;
+def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
+  if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
+    if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+      if (PT->getAddressSpace() != 0)
+        return false;
+  return true;
+}]>;
+def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
+  if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
+    if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+      if (PT->getAddressSpace() != 0)
+        return false;
+  return true;
+}]>;
 
 def sextloadi16i8  : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
 def sextloadi32i8  : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
@@ -706,13 +749,13 @@
 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
 def MOV8rm  : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
                 "mov{b}\t{$src, $dst|$dst, $src}",
-                [(set GR8:$dst, (load addr:$src))]>;
+                [(set GR8:$dst, (loadi8 addr:$src))]>;
 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
                 "mov{w}\t{$src, $dst|$dst, $src}",
-                [(set GR16:$dst, (load addr:$src))]>, OpSize;
+                [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
                 "mov{l}\t{$src, $dst|$dst, $src}",
-                [(set GR32:$dst, (load addr:$src))]>;
+                [(set GR32:$dst, (loadi32 addr:$src))]>;
 }
 
 def MOV8mr  : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
@@ -1358,17 +1401,17 @@
 def AND8rm   : I<0x22, MRMSrcMem, 
                  (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
                  "and{b}\t{$src2, $dst|$dst, $src2}",
-                [(set GR8:$dst, (and GR8:$src1, (load addr:$src2))),
+                [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
                  (implicit EFLAGS)]>;
 def AND16rm  : I<0x23, MRMSrcMem, 
                  (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
                  "and{w}\t{$src2, $dst|$dst, $src2}",
-                [(set GR16:$dst, (and GR16:$src1, (load addr:$src2))),
+                [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
                  (implicit EFLAGS)]>, OpSize;
 def AND32rm  : I<0x23, MRMSrcMem,
                  (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
                  "and{l}\t{$src2, $dst|$dst, $src2}",
-                [(set GR32:$dst, (and GR32:$src1, (load addr:$src2))),
+                [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
                  (implicit EFLAGS)]>;
 
 def AND8ri   : Ii8<0x80, MRM4r, 




From nicholas at mxc.ca  Thu Apr  9 23:46:52 2009
From: nicholas at mxc.ca (Nick Lewycky)
Date: Thu, 09 Apr 2009 21:46:52 -0700
Subject: [llvm-commits] Pointer subtraction for IRBuilder
In-Reply-To: <bb55930e0904091408w6a4036d0obc4aabef57d8d783@mail.gmail.com>
References: <bb55930e0904091408w6a4036d0obc4aabef57d8d783@mail.gmail.com>
Message-ID: <49DECF3C.2050104@mxc.ca>

Jeffrey Yasskin wrote:
> The attached file implements IRBuilder::CreatePSub(), which performs a
> C-style pointer difference on its arguments. The included test passes,
> but it involves a warning that "ISO C++ forbids casting between
> pointer-to-function and pointer-to-object", which I don't know how to
> get rid of given the ExecutionEngine interface. I was also hoping to
> assert that constant folding could produce a constant integer, but I
> couldn't figure that out.

Instead, construct the IRBuilder with a TargetData with known pointer 
size and use Constants of pointer type (ie. "gep ptrtotint null, i32 1") 
as the Values when calling CreatePSub. That way, you'll get a simple 
Constant value back which must be a ConstantInt you can easily check.

Whatever you do, don't submit a 46 line test for a 7 line function. :)

> Let me know what you think. (And I'm now subscribed, so I'll get your answer.)

--- include/llvm/Support/IRBuilder.h	(revision 68715)
+++ include/llvm/Support/IRBuilder.h	(working copy)
@@ -681,8 +681,26 @@
                          Name);
    }
+  /// CreatePSub - Return the i64 difference between two pointer 
values, taking

The name CreatePSub is too ambiguous. Either CreatePtrSub or 
CreatePtrDiff. I prefer the latter.

+  /// the size of the pointed-to objects into account.  This is intended to
+  /// implement C's pointer subtraction.

"implement C-style pointer subtraction."

+  Value *CreatePSub(Value *LHS, Value *RHS, const char *Name = "");
  };

+template <bool preserveNames, typename T>
+Value *IRBuilder<preserveNames, T>::CreatePSub(
+    Value *LHS, Value *RHS, const char *Name) {
+  assert(LHS->getType() == RHS->getType() &&
+         "Pointer subtraction operand types must match!");
+  const PointerType *ArgType = cast<PointerType>(LHS->getType());

+  Value *LHS_int = CreatePtrToInt(LHS, Type::Int64Ty);
+  Value *RHS_int = CreatePtrToInt(RHS, Type::Int64Ty);

I'm don't think this is safe. With TargetData, you could use 
TD->getIntPtrType(). Without it, I'm not convinced it's safe even if you 
were to assume that pointer size is <= 64 bits...

+  Value *Difference = CreateSub(LHS_int, RHS_int);
+  return CreateSDiv(Difference,
+                    ConstantExpr::getSizeOf(ArgType->getElementType()),
+                    Name);

...and here's where it would matter. Consider i32* inttoptr(i32 -1 to 
i32*). CreatePtrToInt zero-extends to produce the i64 LHS_int or RHS_int.

On a 32-bit system:
   int32_t *a = -1;
   int32_t *b = -13;
   a - b
you would expand the -1 to 0x00000000ffffffff and the -13 to 
0x00000000fffffff3. b - a = 0xfffffffffffffff4, not 0x00000000fffffff4

0xff...f4 sdiv 4 = i64 -3, while 0x00...0f...f4 sdiv 4 = 1073741821.

So the fix is for this method to use TargetData.

Unless you want it to also work without TargetData -- now, this is 
hideous but functional -- you could fix it by truncating off the high 
bits of the subtraction result before the sdiv.

But how do you know how many bits to clear? You don't. The way to do it 
is to run it Different through an inttoptr/ptrtoint pair, because a 
pointer magically has the right number of bits.

Nick


From nicholas at mxc.ca  Thu Apr  9 23:54:30 2009
From: nicholas at mxc.ca (Nick Lewycky)
Date: Thu, 09 Apr 2009 21:54:30 -0700
Subject: [llvm-commits] Pointer subtraction for IRBuilder
In-Reply-To: <49DECF3C.2050104@mxc.ca>
References: <bb55930e0904091408w6a4036d0obc4aabef57d8d783@mail.gmail.com>
	<49DECF3C.2050104@mxc.ca>
Message-ID: <49DED106.7020502@mxc.ca>

Nick Lewycky wrote:
> Jeffrey Yasskin wrote:
>> The attached file implements IRBuilder::CreatePSub(), which performs a
>> C-style pointer difference on its arguments. The included test passes,
>> but it involves a warning that "ISO C++ forbids casting between
>> pointer-to-function and pointer-to-object", which I don't know how to
>> get rid of given the ExecutionEngine interface. I was also hoping to
>> assert that constant folding could produce a constant integer, but I
>> couldn't figure that out.
> 
> Instead, construct the IRBuilder with a TargetData with known pointer 
> size and use Constants of pointer type (ie. "gep ptrtotint null, i32 1") 
> as the Values when calling CreatePSub. That way, you'll get a simple 
> Constant value back which must be a ConstantInt you can easily check.
> 
> Whatever you do, don't submit a 46 line test for a 7 line function. :)
> 
>> Let me know what you think. (And I'm now subscribed, so I'll get your answer.)
> 
> --- include/llvm/Support/IRBuilder.h	(revision 68715)
> +++ include/llvm/Support/IRBuilder.h	(working copy)
> @@ -681,8 +681,26 @@
>                           Name);
>     }
> +  /// CreatePSub - Return the i64 difference between two pointer 
> values, taking
> 
> The name CreatePSub is too ambiguous. Either CreatePtrSub or 
> CreatePtrDiff. I prefer the latter.
> 
> +  /// the size of the pointed-to objects into account.  This is intended to
> +  /// implement C's pointer subtraction.
> 
> "implement C-style pointer subtraction."
> 
> +  Value *CreatePSub(Value *LHS, Value *RHS, const char *Name = "");
>   };
> 
> +template <bool preserveNames, typename T>
> +Value *IRBuilder<preserveNames, T>::CreatePSub(
> +    Value *LHS, Value *RHS, const char *Name) {
> +  assert(LHS->getType() == RHS->getType() &&
> +         "Pointer subtraction operand types must match!");
> +  const PointerType *ArgType = cast<PointerType>(LHS->getType());
> 
> +  Value *LHS_int = CreatePtrToInt(LHS, Type::Int64Ty);
> +  Value *RHS_int = CreatePtrToInt(RHS, Type::Int64Ty);
> 
> I'm don't think this is safe. With TargetData, you could use 
> TD->getIntPtrType(). Without it, I'm not convinced it's safe even if you 
> were to assume that pointer size is <= 64 bits...
> 
> +  Value *Difference = CreateSub(LHS_int, RHS_int);
> +  return CreateSDiv(Difference,
> +                    ConstantExpr::getSizeOf(ArgType->getElementType()),
> +                    Name);
> 
> ...and here's where it would matter. Consider i32* inttoptr(i32 -1 to 
> i32*). CreatePtrToInt zero-extends to produce the i64 LHS_int or RHS_int.
> 
> On a 32-bit system:
>    int32_t *a = -1;
>    int32_t *b = -13;
>    a - b
> you would expand the -1 to 0x00000000ffffffff and the -13 to 
> 0x00000000fffffff3. b - a = 0xfffffffffffffff4, not 0x00000000fffffff4
> 
> 0xff...f4 sdiv 4 = i64 -3, while 0x00...0f...f4 sdiv 4 = 1073741821.

*Erbl.*

Which means of course that your method produces the correct answer, 
because you chose sdiv instead of udiv.

I got confused because inttoptr does zero-extension (implying that it's 
unsigned) but the division is signed.

Anyways, please discard the above misanalysis. I'm still suspicious of 
this code but I don't have example values of it misbehaving.

Sorry for the confusion!

Nick


From nicholas at mxc.ca  Fri Apr 10 00:18:29 2009
From: nicholas at mxc.ca (Nick Lewycky)
Date: Fri, 10 Apr 2009 05:18:29 -0000
Subject: [llvm-commits] [llvm] r68767 - /llvm/trunk/configure
Message-ID: <200904100518.n3A5IUSU021247@zion.cs.uiuc.edu>

Author: nicholas
Date: Fri Apr 10 00:18:27 2009
New Revision: 68767

URL: http://llvm.org/viewvc/llvm-project?rev=68767&view=rev
Log:
Regenerate.

Modified:
    llvm/trunk/configure

Modified: llvm/trunk/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=68767&r1=68766&r2=68767&view=diff

==============================================================================
--- llvm/trunk/configure (original)
+++ llvm/trunk/configure Fri Apr 10 00:18:27 2009
@@ -4698,7 +4698,7 @@
 
 fi
 
-if test -d "CVS" -o -d "${srcdir}/CVS" -o -d ".svn" -o -d "${srcdir}/.svn"; then
+if test -d "CVS" -o -d "${srcdir}/CVS" -o -d ".svn" -o -d "${srcdir}/.svn" -o -d ".git" -o -d "${srcdir}/.git"; then
   cvsbuild="yes"
   optimize="no"
   CVSBUILD=CVSBUILD=1




From nicholas at mxc.ca  Fri Apr 10 00:20:27 2009
From: nicholas at mxc.ca (Nick Lewycky)
Date: Thu, 09 Apr 2009 22:20:27 -0700
Subject: [llvm-commits] [llvm] r68187 - /llvm/trunk/autoconf/configure.ac
In-Reply-To: <1BBB1B35-3F44-4021-B115-258C3D8814B1@apple.com>
References: <200904010439.n314dP2p010541@zion.cs.uiuc.edu>
	<1BBB1B35-3F44-4021-B115-258C3D8814B1@apple.com>
Message-ID: <49DED71B.2050405@mxc.ca>

Tanya Lattner wrote:
> Regenerate configure?

Right! Done.

Nick

> On Mar 31, 2009, at 9:39 PM, Nick Lewycky wrote:
> 
>> Author: nicholas
>> Date: Tue Mar 31 23:39:25 2009
>> New Revision: 68187
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=68187&view=rev 
>> <http://llvm.org/viewvc/llvm-project?rev=68187&view=rev>
>> Log:
>> Detect that we're building from a git checkout like we do for cvs and svn.
>> Based on a patch by Nicolas Trangez on the unladen-swallow mailing list!
>>
>> Modified:
>>    llvm/trunk/autoconf/configure.ac
>>
>> Modified: llvm/trunk/autoconf/configure.ac
>> URL: 
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=68187&r1=68186&r2=68187&view=diff 
>> <http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=68187&r1=68186&r2=68187&view=diff>
>>
>> ==============================================================================
>> --- llvm/trunk/autoconf/configure.ac (original)
>> +++ llvm/trunk/autoconf/configure.ac Tue Mar 31 23:39:25 2009
>> @@ -255,13 +255,13 @@
>>   AC_SUBST(LLVM_CROSS_COMPILING, [0])
>> fi
>>
>> -dnl Check to see if there's a "CVS" (or .svn) directory indicating 
>> that this
>> -dnl build is being done from a checkout. This sets up several 
>> defaults for the
>> -dnl command line switches. When we build with a CVS directory, we get a
>> -dnl debug with assertions turned on. Without, we assume a source 
>> release and we
>> -dnl get an optimized build without assertions. See --enable-optimized and
>> -dnl --enable-assertions below
>> -if test -d "CVS" -o -d "${srcdir}/CVS" -o -d ".svn" -o -d 
>> "${srcdir}/.svn"; then
>> +dnl Check to see if there's a "CVS" (or .svn or .git) directory 
>> indicating
>> +dnl that this build is being done from a checkout. This sets up several
>> +dnl defaults for the command line switches. When we build with a CVS 
>> directory,
>> +dnl we get a debug with assertions turned on. Without, we assume a source
>> +dnl release and we get an optimized build without assertions.
>> +dnl See --enable-optimized and --enable-assertions below
>> +if test -d "CVS" -o -d "${srcdir}/CVS" -o -d ".svn" -o -d 
>> "${srcdir}/.svn" -o -d ".git" -o -d "${srcdir}/.git"; then
>>   cvsbuild="yes"
>>   optimize="no"
>>   AC_SUBST(CVSBUILD,[[CVSBUILD=1]])
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu <mailto:llvm-commits at cs.uiuc.edu>
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> 
> ------------------------------------------------------------------------
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From nicholas at mxc.ca  Fri Apr 10 00:30:48 2009
From: nicholas at mxc.ca (Nick Lewycky)
Date: Fri, 10 Apr 2009 05:30:48 -0000
Subject: [llvm-commits] [llvm] r68768 -
	/llvm/trunk/include/llvm/Support/IRBuilder.h
Message-ID: <200904100530.n3A5UmP3021661@zion.cs.uiuc.edu>

Author: nicholas
Date: Fri Apr 10 00:30:48 2009
New Revision: 68768

URL: http://llvm.org/viewvc/llvm-project?rev=68768&view=rev
Log:
Add utility function to IRBuilder that takes the difference between two
pointers, taking into account the size of the pointed-to object.
Patch by Jeffrey Yasskin!

Modified:
    llvm/trunk/include/llvm/Support/IRBuilder.h

Modified: llvm/trunk/include/llvm/Support/IRBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=68768&r1=68767&r2=68768&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Support/IRBuilder.h (original)
+++ llvm/trunk/include/llvm/Support/IRBuilder.h Fri Apr 10 00:30:48 2009
@@ -681,6 +681,20 @@
                         Name);
   }
 
+  /// CreatePtrDiff - Return the i64 difference between two pointer values,
+  /// dividing out the size of the pointed-to objects.  This is intended to
+  /// implement C-style pointer subtraction.
+  Value *CreatePtrDiff(Value *LHS, Value *RHS, const char *Name = "") {
+    assert(LHS->getType() == RHS->getType() &&
+           "Pointer subtraction operand types must match!");
+    const PointerType *ArgType = cast<PointerType>(LHS->getType());
+    Value *LHS_int = CreatePtrToInt(LHS, Type::Int64Ty);
+    Value *RHS_int = CreatePtrToInt(RHS, Type::Int64Ty);
+    Value *Difference = CreateSub(LHS_int, RHS_int);
+    return CreateSDiv(Difference,
+                      ConstantExpr::getSizeOf(ArgType->getElementType()),
+                      Name);
+  }
 };
 
 }




From clattner at apple.com  Fri Apr 10 00:35:04 2009
From: clattner at apple.com (Chris Lattner)
Date: Thu, 9 Apr 2009 22:35:04 -0700
Subject: [llvm-commits] [llvm] r68768 -
	/llvm/trunk/include/llvm/Support/IRBuilder.h
In-Reply-To: <200904100530.n3A5UmP3021661@zion.cs.uiuc.edu>
References: <200904100530.n3A5UmP3021661@zion.cs.uiuc.edu>
Message-ID: <79DD037B-8A75-491A-8300-A57A4C630D17@apple.com>

On Apr 9, 2009, at 10:30 PM, Nick Lewycky wrote:
> URL: http://llvm.org/viewvc/llvm-project?rev=68768&view=rev
> Log:
> Add utility function to IRBuilder that takes the difference between  
> two
> pointers, taking into account the size of the pointed-to object.
> Patch by Jeffrey Yasskin!

looks good to me.  Incidentally, clang and llvm-gcc specialize the  
case when the element size is a power of two into a signed right  
shift.  This is legal because C only allows pointer subtraction  
between elements in the same array, which means the division must be  
"exact".  In this case, SRA x, c is the same as sdiv x, 2^c.  I don't  
know if you care about this case though.

-Chris

>
>
> Modified:
>    llvm/trunk/include/llvm/Support/IRBuilder.h
>
> Modified: llvm/trunk/include/llvm/Support/IRBuilder.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=68768&r1=68767&r2=68768&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/Support/IRBuilder.h (original)
> +++ llvm/trunk/include/llvm/Support/IRBuilder.h Fri Apr 10 00:30:48  
> 2009
> @@ -681,6 +681,20 @@
>                         Name);
>   }
>
> +  /// CreatePtrDiff - Return the i64 difference between two pointer  
> values,
> +  /// dividing out the size of the pointed-to objects.  This is  
> intended to
> +  /// implement C-style pointer subtraction.
> +  Value *CreatePtrDiff(Value *LHS, Value *RHS, const char *Name =  
> "") {
> +    assert(LHS->getType() == RHS->getType() &&
> +           "Pointer subtraction operand types must match!");
> +    const PointerType *ArgType = cast<PointerType>(LHS->getType());
> +    Value *LHS_int = CreatePtrToInt(LHS, Type::Int64Ty);
> +    Value *RHS_int = CreatePtrToInt(RHS, Type::Int64Ty);
> +    Value *Difference = CreateSub(LHS_int, RHS_int);
> +    return CreateSDiv(Difference,
> +                      ConstantExpr::getSizeOf(ArgType- 
> >getElementType()),
> +                      Name);
> +  }
> };
>
> }
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From jyasskin at google.com  Fri Apr 10 01:08:49 2009
From: jyasskin at google.com (Jeffrey Yasskin)
Date: Thu, 9 Apr 2009 23:08:49 -0700
Subject: [llvm-commits] [llvm] r68768 -
	/llvm/trunk/include/llvm/Support/IRBuilder.h
In-Reply-To: <79DD037B-8A75-491A-8300-A57A4C630D17@apple.com>
References: <200904100530.n3A5UmP3021661@zion.cs.uiuc.edu>
	<79DD037B-8A75-491A-8300-A57A4C630D17@apple.com>
Message-ID: <bb55930e0904092308i23d79b51x67fca9d551992a82@mail.gmail.com>

On Thu, Apr 9, 2009 at 10:35 PM, Chris Lattner <clattner at apple.com> wrote:
> On Apr 9, 2009, at 10:30 PM, Nick Lewycky wrote:
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=68768&view=rev
>> Log:
>> Add utility function to IRBuilder that takes the difference between two
>> pointers, taking into account the size of the pointed-to object.
>> Patch by Jeffrey Yasskin!
>
> looks good to me. ?Incidentally, clang and llvm-gcc specialize the case when
> the element size is a power of two into a signed right shift. ?This is legal
> because C only allows pointer subtraction between elements in the same
> array, which means the division must be "exact". ?In this case, SRA x, c is
> the same as sdiv x, 2^c. ?I don't know if you care about this case though.

It would be nice to optimize that, or provide enough information to
let a downstream pass optimize it, but I don't know a reliable way to
do it in the IRBuilder, which doesn't have target data. Is there a
way?



From clattner at apple.com  Fri Apr 10 01:33:37 2009
From: clattner at apple.com (Chris Lattner)
Date: Thu, 9 Apr 2009 23:33:37 -0700
Subject: [llvm-commits] [llvm] r68768 -
	/llvm/trunk/include/llvm/Support/IRBuilder.h
In-Reply-To: <bb55930e0904092308i23d79b51x67fca9d551992a82@mail.gmail.com>
References: <200904100530.n3A5UmP3021661@zion.cs.uiuc.edu>
	<79DD037B-8A75-491A-8300-A57A4C630D17@apple.com>
	<bb55930e0904092308i23d79b51x67fca9d551992a82@mail.gmail.com>
Message-ID: <B4E755C2-7FB8-4241-83F6-F7AD9E6D23B7@apple.com>


On Apr 9, 2009, at 11:08 PM, Jeffrey Yasskin wrote:

> On Thu, Apr 9, 2009 at 10:35 PM, Chris Lattner <clattner at apple.com>  
> wrote:
>> On Apr 9, 2009, at 10:30 PM, Nick Lewycky wrote:
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=68768&view=rev
>>> Log:
>>> Add utility function to IRBuilder that takes the difference  
>>> between two
>>> pointers, taking into account the size of the pointed-to object.
>>> Patch by Jeffrey Yasskin!
>>
>> looks good to me.  Incidentally, clang and llvm-gcc specialize the  
>> case when
>> the element size is a power of two into a signed right shift.  This  
>> is legal
>> because C only allows pointer subtraction between elements in the  
>> same
>> array, which means the division must be "exact".  In this case, SRA  
>> x, c is
>> the same as sdiv x, 2^c.  I don't know if you care about this case  
>> though.
>
> It would be nice to optimize that, or provide enough information to
> let a downstream pass optimize it, but I don't know a reliable way to
> do it in the IRBuilder, which doesn't have target data. Is there a
> way?


Ok, I didn't realize that IRBuilder didn't have TargetData directly.   
This is probably implementable in TargetFolder, which can be used as a  
template parameter to IRBuilder.

The ideal way to handle this is to just mark the sdiv as being exact,  
and letting instcombine do it later.  We don't have direct support for  
that in LLVM IR yet though.  This is the subject of:
http://llvm.org/bugs/show_bug.cgi?id=2247

The right way to handle this is to parameterize sdiv/udiv on a general  
integer rounding mode, one of which is "this divide is known to be  
exact".

-Chris


From clattner at apple.com  Fri Apr 10 01:38:43 2009
From: clattner at apple.com (Chris Lattner)
Date: Thu, 9 Apr 2009 23:38:43 -0700
Subject: [llvm-commits] TypeBuilder helper class
In-Reply-To: <bb55930e0904090940o5686c16er9f8f87e9ca302ed5@mail.gmail.com>
References: <bb55930e0904021137i3199acb6j3108bc4c2819d9c5@mail.gmail.com>
	<bb55930e0904090940o5686c16er9f8f87e9ca302ed5@mail.gmail.com>
Message-ID: <5F5A9B7F-1967-4D07-9D74-20466088C123@apple.com>


On Apr 9, 2009, at 9:40 AM, Jeffrey Yasskin wrote:

>
> I think I see how to define TypeBuilder<typename T, bool
> restrict_to_cross_compilable_types> so that TypeBuilder<size_t, true>
> fails to compile but TypeBuilder<sometype<64>, false> succeeds,
> without duplicating code. Could you confirm that that's along the
> lines of what you want implemented before I waste time implementing
> it? Also, what's the right spelling for "sometype"? I'd vote for
> llvm::types::i<N> or something similar.
>

Sounds great to me!

-Chris


From sabre at nondot.org  Fri Apr 10 01:42:10 2009
From: sabre at nondot.org (Chris Lattner)
Date: Fri, 10 Apr 2009 06:42:10 -0000
Subject: [llvm-commits] [llvm] r68772 - in /llvm/trunk: include/llvm/Type.h
	lib/VMCore/Type.cpp
Message-ID: <200904100642.n3A6gAWX024135@zion.cs.uiuc.edu>

Author: lattner
Date: Fri Apr 10 01:42:02 2009
New Revision: 68772

URL: http://llvm.org/viewvc/llvm-project?rev=68772&view=rev
Log:
Add a new Type::getPointerTo method, which is shorthand for
llvm::PointerType::get().  Patch by Anders Johnsen!

Modified:
    llvm/trunk/include/llvm/Type.h
    llvm/trunk/lib/VMCore/Type.cpp

Modified: llvm/trunk/include/llvm/Type.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Type.h?rev=68772&r1=68771&r2=68772&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Type.h (original)
+++ llvm/trunk/include/llvm/Type.h Fri Apr 10 01:42:02 2009
@@ -364,6 +364,10 @@
   ///
   void removeAbstractTypeUser(AbstractTypeUser *U) const;
 
+  /// getPointerTo - Return a pointer to the current type.  This is equivalent
+  /// to PointerType::get(Foo, AddrSpace).
+  PointerType *getPointerTo(unsigned AddrSpace = 0) const;
+
 private:
   /// isSizedDerivedType - Derived types like structures and arrays are sized
   /// iff all of the members of the type are sized as well.  Since asking for

Modified: llvm/trunk/lib/VMCore/Type.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Type.cpp?rev=68772&r1=68771&r2=68772&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/Type.cpp (original)
+++ llvm/trunk/lib/VMCore/Type.cpp Fri Apr 10 01:42:02 2009
@@ -1214,6 +1214,10 @@
   return PT;
 }
 
+PointerType *Type::getPointerTo(unsigned addrs) const {
+  return PointerType::get(this, addrs);
+}
+
 //===----------------------------------------------------------------------===//
 //                     Derived Type Refinement Functions
 //===----------------------------------------------------------------------===//




From clattner at apple.com  Fri Apr 10 01:42:31 2009
From: clattner at apple.com (Chris Lattner)
Date: Thu, 9 Apr 2009 23:42:31 -0700
Subject: [llvm-commits] Type::getPointerTo()
In-Reply-To: <5be2d90904070700n6709afd7t1a6e8c08c3ef7361@mail.gmail.com>
References: <5be2d90904070700n6709afd7t1a6e8c08c3ef7361@mail.gmail.com>
Message-ID: <11F16316-C5D2-431C-B6A3-821BDA5E4534@apple.com>


On Apr 7, 2009, at 7:00 AM, Anders Johnsen wrote:

> Hi,
>
> I'd like to suggest this patch which adds a getPointerTo() method to  
> llvm::Type.
>
> This will allow the following code:
>
> myType->getPointerTo(0);  (1)
>
> that is 100% identical to
>
> llvm::PointerType::get(myType, 0);   (2)
>
> My motivation for the patch is that my code is full of (2) and it's
> getting somewhat ugly.

Hi Anders,

I committed a tweaked version of your patch here, thanks!
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090406/076193.html

-Chris


From nicholas at mxc.ca  Fri Apr 10 01:54:06 2009
From: nicholas at mxc.ca (Nick Lewycky)
Date: Fri, 10 Apr 2009 06:54:06 -0000
Subject: [llvm-commits] [llvm] r68774 -
	/llvm/trunk/include/llvm/Support/IRBuilder.h
Message-ID: <200904100654.n3A6s6jD024592@zion.cs.uiuc.edu>

Author: nicholas
Date: Fri Apr 10 01:54:06 2009
New Revision: 68774

URL: http://llvm.org/viewvc/llvm-project?rev=68774&view=rev
Log:
Cleanup. Remove redundant llvm:: , we don't need them since we're inside
namespace llvm already.

Modified:
    llvm/trunk/include/llvm/Support/IRBuilder.h

Modified: llvm/trunk/include/llvm/Support/IRBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=68774&r1=68773&r2=68774&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Support/IRBuilder.h (original)
+++ llvm/trunk/include/llvm/Support/IRBuilder.h Fri Apr 10 01:54:06 2009
@@ -323,7 +323,7 @@
     return Insert(GetElementPtrInst::Create(Ptr, Idx), Name);
   }
   Value *CreateConstGEP1_32(Value *Ptr, unsigned Idx0, const char *Name = "") {
-    llvm::Value *Idx = ConstantInt::get(llvm::Type::Int32Ty, Idx0);
+    Value *Idx = ConstantInt::get(Type::Int32Ty, Idx0);
 
     if (Constant *PC = dyn_cast<Constant>(Ptr))
       return Folder.CreateGetElementPtr(PC, &Idx, 1);
@@ -332,9 +332,9 @@
   }
   Value *CreateConstGEP2_32(Value *Ptr, unsigned Idx0, unsigned Idx1, 
                     const char *Name = "") {
-    llvm::Value *Idxs[] = {
-      ConstantInt::get(llvm::Type::Int32Ty, Idx0),
-      ConstantInt::get(llvm::Type::Int32Ty, Idx1)
+    Value *Idxs[] = {
+      ConstantInt::get(Type::Int32Ty, Idx0),
+      ConstantInt::get(Type::Int32Ty, Idx1)
     };
 
     if (Constant *PC = dyn_cast<Constant>(Ptr))
@@ -343,7 +343,7 @@
     return Insert(GetElementPtrInst::Create(Ptr, Idxs, Idxs+2), Name);    
   }
   Value *CreateConstGEP1_64(Value *Ptr, uint64_t Idx0, const char *Name = "") {
-    llvm::Value *Idx = ConstantInt::get(llvm::Type::Int64Ty, Idx0);
+    Value *Idx = ConstantInt::get(Type::Int64Ty, Idx0);
 
     if (Constant *PC = dyn_cast<Constant>(Ptr))
       return Folder.CreateGetElementPtr(PC, &Idx, 1);
@@ -352,9 +352,9 @@
   }
   Value *CreateConstGEP2_64(Value *Ptr, uint64_t Idx0, uint64_t Idx1, 
                     const char *Name = "") {
-    llvm::Value *Idxs[] = {
-      ConstantInt::get(llvm::Type::Int64Ty, Idx0),
-      ConstantInt::get(llvm::Type::Int64Ty, Idx1)
+    Value *Idxs[] = {
+      ConstantInt::get(Type::Int64Ty, Idx0),
+      ConstantInt::get(Type::Int64Ty, Idx1)
     };
 
     if (Constant *PC = dyn_cast<Constant>(Ptr))
@@ -367,19 +367,19 @@
   }
   Value *CreateGlobalString(const char *Str = "", const char *Name = "") {
     Constant *StrConstant = ConstantArray::get(Str, true);
-    GlobalVariable *gv = new llvm::GlobalVariable(StrConstant->getType(),
-                                                  true,
-                                                  GlobalValue::InternalLinkage,
-                                                  StrConstant,
-                                                  "",
-                                                  BB->getParent()->getParent(),
-                                                  false);
+    GlobalVariable *gv = new GlobalVariable(StrConstant->getType(),
+                                            true,
+                                            GlobalValue::InternalLinkage,
+                                            StrConstant,
+                                            "",
+                                            BB->getParent()->getParent(),
+                                            false);
     gv->setName(Name);
     return gv;
   }
   Value *CreateGlobalStringPtr(const char *Str = "", const char *Name = "") {
     Value *gv = CreateGlobalString(Str, Name);
-    Value *zero = llvm::ConstantInt::get(llvm::Type::Int32Ty, 0);
+    Value *zero = ConstantInt::get(Type::Int32Ty, 0);
     Value *Args[] = { zero, zero };
     return CreateGEP(gv, Args, Args+2, Name);
   }
@@ -671,13 +671,13 @@
 
   /// CreateIsNull - Return an i1 value testing if \arg Arg is null.
   Value *CreateIsNull(Value *Arg, const char *Name = "") {
-    return CreateICmpEQ(Arg, llvm::Constant::getNullValue(Arg->getType()),
+    return CreateICmpEQ(Arg, Constant::getNullValue(Arg->getType()),
                         Name);
   }
 
   /// CreateIsNotNull - Return an i1 value testing if \arg Arg is not null.
   Value *CreateIsNotNull(Value *Arg, const char *Name = "") {
-    return CreateICmpNE(Arg, llvm::Constant::getNullValue(Arg->getType()),
+    return CreateICmpNE(Arg, Constant::getNullValue(Arg->getType()),
                         Name);
   }
 




From kremenek at apple.com  Fri Apr 10 02:09:35 2009
From: kremenek at apple.com (Ted Kremenek)
Date: Fri, 10 Apr 2009 07:09:35 -0000
Subject: [llvm-commits] [llvm] r68775 - /llvm/tags/checker/checker-0.185/
Message-ID: <200904100709.n3A79ZlD025105@zion.cs.uiuc.edu>

Author: kremenek
Date: Fri Apr 10 02:09:32 2009
New Revision: 68775

URL: http://llvm.org/viewvc/llvm-project?rev=68775&view=rev
Log:
Tagging checker-0.185.

Added:
    llvm/tags/checker/checker-0.185/
      - copied from r68774, llvm/trunk/



From rafael.espindola at gmail.com  Fri Apr 10 05:09:40 2009
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 10 Apr 2009 10:09:40 -0000
Subject: [llvm-commits] [llvm] r68778 - in /llvm/trunk:
 lib/Target/X86/X86ISelDAGToDAG.cpp test/CodeGen/X86/tls10.ll
 test/CodeGen/X86/tls15.ll test/CodeGen/X86/tls2.ll test/CodeGen/X86/tls6.ll
 test/CodeGen/X86/tls8.ll
Message-ID: <200904101009.n3AA9faZ010267@zion.cs.uiuc.edu>

Author: rafael
Date: Fri Apr 10 05:09:34 2009
New Revision: 68778

URL: http://llvm.org/viewvc/llvm-project?rev=68778&view=rev
Log:
Don't fold a load if the other operand is a TLS address.

With this we generate

movl    %gs:0, %eax
leal    i at NTPOFF(%eax), %eax

instead of

movl    $i at NTPOFF, %eax
addl    %gs:0, %eax


Added:
    llvm/trunk/test/CodeGen/X86/tls15.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/X86/tls10.ll
    llvm/trunk/test/CodeGen/X86/tls2.ll
    llvm/trunk/test/CodeGen/X86/tls6.ll
    llvm/trunk/test/CodeGen/X86/tls8.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=68778&r1=68777&r2=68778&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Apr 10 05:09:34 2009
@@ -322,6 +322,8 @@
     case ISD::AND:
     case ISD::OR:
     case ISD::XOR: {
+      SDValue Op1 = U->getOperand(1);
+
       // If the other operand is a 8-bit immediate we should fold the immediate
       // instead. This reduces code size.
       // e.g.
@@ -332,9 +334,25 @@
       // addl 4(%esp), %eax
       // The former is 2 bytes shorter. In case where the increment is 1, then
       // the saving can be 4 bytes (by using incl %eax).
-      if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(U->getOperand(1)))
+      if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
         if (Imm->getAPIntValue().isSignedIntN(8))
           return false;
+
+      // If the other operand is a TLS address, we should fold it instead.
+      // This produces
+      // movl    %gs:0, %eax
+      // leal    i at NTPOFF(%eax), %eax
+      // instead of
+      // movl    $i at NTPOFF, %eax
+      // addl    %gs:0, %eax
+      // if the block also has an access to a second TLS address this will save
+      // a load.
+      // FIXME: This is probably also true for non TLS addresses.
+      if (Op1.getOpcode() == X86ISD::Wrapper) {
+        SDValue Val = Op1.getOperand(0);
+        if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
+          return false;
+      }
     }
     }
 
@@ -1170,13 +1188,16 @@
                                     SDValue &Base, SDValue &Scale,
                                     SDValue &Index, SDValue &Disp) {
   X86ISelAddressMode AM;
-  if (MatchAddress(N, AM))
-    return false;
 
-  //Is it better to set AM.Segment before calling MatchAddress to
-  //prevent it from adding a segment?
-  if (AM.Segment.getNode())
+  // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
+  // segments.
+  SDValue Copy = AM.Segment;
+  SDValue T = CurDAG->getRegister(0, MVT::i32);
+  AM.Segment = T;
+  if (MatchAddress(N, AM))
     return false;
+  assert (T == AM.Segment);
+  AM.Segment = Copy;
 
   MVT VT = N.getValueType();
   unsigned Complexity = 0;

Modified: llvm/trunk/test/CodeGen/X86/tls10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls10.ll?rev=68778&r1=68777&r2=68778&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls10.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls10.ll Fri Apr 10 05:09:34 2009
@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movl	\$i at NTPOFF, %eax} %t
-; RUN: grep {addl	%gs:0, %eax} %t
+; RUN: grep {movl	%gs:0, %eax} %t
+; RUN: grep {leal	i at NTPOFF(%eax), %eax} %t
 
 @i = external hidden thread_local global i32
 

Added: llvm/trunk/test/CodeGen/X86/tls15.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls15.ll?rev=68778&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls15.ll (added)
+++ llvm/trunk/test/CodeGen/X86/tls15.ll Fri Apr 10 05:09:34 2009
@@ -0,0 +1,14 @@
+; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: grep {movl	%gs:0, %eax} %t | count 1
+; RUN: grep {leal	i at NTPOFF(%eax), %ecx} %t
+; RUN: grep {leal	j at NTPOFF(%eax), %eax} %t
+
+ at i = thread_local global i32 0
+ at j = thread_local global i32 0
+
+define void @f(i32** %a, i32** %b) {
+entry:
+	store i32* @i, i32** %a, align 8
+	store i32* @j, i32** %b, align 8
+	ret void
+}

Modified: llvm/trunk/test/CodeGen/X86/tls2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls2.ll?rev=68778&r1=68777&r2=68778&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls2.ll Fri Apr 10 05:09:34 2009
@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movl	\$i at NTPOFF, %eax} %t
-; RUN: grep {addl	%gs:0, %eax} %t
+; RUN: grep {movl	%gs:0, %eax} %t
+; RUN: grep {leal	i at NTPOFF(%eax), %eax} %t
 
 @i = thread_local global i32 15
 

Modified: llvm/trunk/test/CodeGen/X86/tls6.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls6.ll?rev=68778&r1=68777&r2=68778&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls6.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls6.ll Fri Apr 10 05:09:34 2009
@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movl	\$i at NTPOFF, %eax} %t
-; RUN: grep {addl	%gs:0, %eax} %t
+; RUN: grep {movl	%gs:0, %eax} %t
+; RUN: grep {leal	i at NTPOFF(%eax), %eax} %t
 
 @i = internal thread_local global i32 15
 

Modified: llvm/trunk/test/CodeGen/X86/tls8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls8.ll?rev=68778&r1=68777&r2=68778&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls8.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls8.ll Fri Apr 10 05:09:34 2009
@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movl	\$i at NTPOFF, %eax} %t
-; RUN: grep {addl	%gs:0, %eax} %t
+; RUN: grep {movl	%gs:0, %eax} %t
+; RUN: grep {leal	i at NTPOFF(%eax), %eax} %t
 
 @i = hidden thread_local global i32 15
 




From sanjiv.gupta at microchip.com  Fri Apr 10 10:10:15 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Fri, 10 Apr 2009 15:10:15 -0000
Subject: [llvm-commits] [llvm] r68783 - in /llvm/trunk/lib/Target/PIC16:
 PIC16ISelLowering.cpp PIC16ISelLowering.h PIC16InstrInfo.cpp
 PIC16InstrInfo.td
Message-ID: <200904101510.n3AFAFMR020714@zion.cs.uiuc.edu>

Author: sgupta
Date: Fri Apr 10 10:10:14 2009
New Revision: 68783

URL: http://llvm.org/viewvc/llvm-project?rev=68783&view=rev
Log:
Added code to handle spilling and reloading of FSRs.

Modified:
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h
    llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp
    llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=68783&r1=68782&r2=68783&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Fri Apr 10 10:10:14 2009
@@ -153,7 +153,7 @@
   return Flag;
 }
 // Get the TmpOffset for FrameIndex
-unsigned PIC16TargetLowering::GetTmpOffsetForFI(unsigned FI) {
+unsigned PIC16TargetLowering::GetTmpOffsetForFI(unsigned FI, unsigned size) {
   std::map<unsigned, unsigned>::iterator 
             MapIt = FiTmpOffsetMap.find(FI);
   if (MapIt != FiTmpOffsetMap.end())
@@ -161,7 +161,8 @@
 
   // This FI (FrameIndex) is not yet mapped, so map it
   FiTmpOffsetMap[FI] = TmpSize; 
-  return TmpSize++;
+  TmpSize += size;
+  return FiTmpOffsetMap[FI];
 }
 
 // To extract chain value from the SDValue Nodes
@@ -849,14 +850,14 @@
                                DAG.getEntryNode(),
                                Op, ES, 
                                DAG.getConstant (1, MVT::i8), // Banksel.
-                               DAG.getConstant (GetTmpOffsetForFI(FI), 
+                               DAG.getConstant (GetTmpOffsetForFI(FI, 1), 
                                                 MVT::i8));
 
   // Load the value from ES.
   SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other);
   SDValue Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Store,
                              ES, DAG.getConstant (1, MVT::i8),
-                             DAG.getConstant (GetTmpOffsetForFI(FI), 
+                             DAG.getConstant (GetTmpOffsetForFI(FI, 1), 
                              MVT::i8));
     
   return Load.getValue(0);

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h?rev=68783&r1=68782&r2=68783&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h Fri Apr 10 10:10:14 2009
@@ -137,7 +137,7 @@
     // This function returns the Tmp Offset for FrameIndex. If any TmpOffset 
     // already exists for the FI then it returns the same else it creates the 
     // new offset and returns.
-    unsigned GetTmpOffsetForFI(unsigned FI); 
+    unsigned GetTmpOffsetForFI(unsigned FI, unsigned slot_size); 
     void ResetTmpOffsetMap() { FiTmpOffsetMap.clear(); SetTmpSize(0); }
 
     // Return the size of Tmp variable 

Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp?rev=68783&r1=68782&r2=68783&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp Fri Apr 10 10:10:14 2009
@@ -85,12 +85,25 @@
     //MachineRegisterInfo &RI = MF.getRegInfo();
     BuildMI(MBB, I, DL, get(PIC16::movwf))
       .addReg(SrcReg, false, false, isKill)
-      .addImm(PTLI->GetTmpOffsetForFI(FI))
+      .addImm(PTLI->GetTmpOffsetForFI(FI, 1))
+      .addExternalSymbol(tmpName)
+      .addImm(1); // Emit banksel for it.
+  }
+  else if (RC == PIC16::FSR16RegisterClass) {
+    // This is a 16-bit register and the frameindex given by llvm is of
+    // size two here. Break this index N into two zero based indexes and 
+    // put one into the map. The second one is always obtained by adding 1
+    // to the first zero based index. In fact it is going to use 3 slots
+    // as saving FSRs corrupts W also and hence we need to save/restore W also.
+
+    unsigned opcode = (SrcReg == PIC16::FSR0) ? PIC16::save_fsr0 
+                                                 : PIC16::save_fsr1;
+    BuildMI(MBB, I, DL, get(opcode))
+      .addReg(SrcReg, false, false, isKill)
+      .addImm(PTLI->GetTmpOffsetForFI(FI, 3))
       .addExternalSymbol(tmpName)
       .addImm(1); // Emit banksel for it.
   }
-  else if (RC == PIC16::FSR16RegisterClass)
-    assert(0 && "Don't know yet how to store a FSR16 to stack slot");
   else
     assert(0 && "Can't store this register to stack slot");
 }
@@ -114,12 +127,24 @@
     //MachineFunction &MF = *MBB.getParent();
     //MachineRegisterInfo &RI = MF.getRegInfo();
     BuildMI(MBB, I, DL, get(PIC16::movf), DestReg)
-      .addImm(PTLI->GetTmpOffsetForFI(FI))
+      .addImm(PTLI->GetTmpOffsetForFI(FI, 1))
+      .addExternalSymbol(tmpName)
+      .addImm(1); // Emit banksel for it.
+  }
+  else if (RC == PIC16::FSR16RegisterClass) {
+    // This is a 16-bit register and the frameindex given by llvm is of
+    // size two here. Break this index N into two zero based indexes and 
+    // put one into the map. The second one is always obtained by adding 1
+    // to the first zero based index. In fact it is going to use 3 slots
+    // as saving FSRs corrupts W also and hence we need to save/restore W also.
+
+    unsigned opcode = (DestReg == PIC16::FSR0) ? PIC16::restore_fsr0 
+                                                 : PIC16::restore_fsr1;
+    BuildMI(MBB, I, DL, get(opcode), DestReg)
+      .addImm(PTLI->GetTmpOffsetForFI(FI, 3))
       .addExternalSymbol(tmpName)
       .addImm(1); // Emit banksel for it.
   }
-  else if (RC == PIC16::FSR16RegisterClass)
-    assert(0 && "Don't know yet how to load an FSR16 from stack slot");
   else
     assert(0 && "Can't load this register from stack slot");
 }

Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td?rev=68783&r1=68782&r2=68783&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td Fri Apr 10 10:10:14 2009
@@ -232,6 +232,24 @@
 def copy_w:
   Pseudo<(outs GPR:$dst), (ins GPR:$src), "copy_w $dst, $src", []>;
 
+class SAVE_FSR<string OpcStr>:
+  Pseudo<(outs), 
+         (ins FSR16:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi), 
+         !strconcat(OpcStr, " $ptrlo, $offset"),
+         []>; 
+ 
+def save_fsr0: SAVE_FSR<"save_fsr0">;
+def save_fsr1: SAVE_FSR<"save_fsr1">;
+
+class RESTORE_FSR<string OpcStr>:
+  Pseudo<(outs FSR16:$dst), 
+         (ins i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi), 
+         !strconcat(OpcStr, " $ptrlo, $offset"),
+         []>; 
+
+def restore_fsr0: RESTORE_FSR<"restore_fsr0">;
+def restore_fsr1: RESTORE_FSR<"restore_fsr1">;
+
 //--------------------------
 // Store to memory
 //-------------------------
@@ -397,19 +415,22 @@
 }
 
 // Call instruction.
-let isCall = 1 in {
+let isCall = 1,
+    Defs = [W, FSR0, FSR1] in {
     def CALL: LiteralFormat<0x1, (outs), (ins i8imm:$func),
             "call ${func} + 2",
             [(PIC16call diraddr:$func)]>;
 }
 
-let isCall = 1 in {
+let isCall = 1,
+    Defs = [W, FSR0, FSR1] in {
     def CALL_1: LiteralFormat<0x1, (outs), (ins GPR:$func, PCLATHR:$pc),
             "callw",
             [(PIC16call (PIC16Connect GPR:$func, PCLATHR:$pc))]>;
 }
 
-let isCall = 1  in {
+let isCall = 1,
+    Defs = [FSR0, FSR1] in {
     def CALLW: LiteralFormat<0x1, (outs GPR:$dest), 
                                   (ins GPR:$func, PCLATHR:$pc),
             "callw",




From sabre at nondot.org  Fri Apr 10 10:38:51 2009
From: sabre at nondot.org (Chris Lattner)
Date: Fri, 10 Apr 2009 15:38:51 -0000
Subject: [llvm-commits] [llvm] r68784 - /llvm/trunk/docs/GettingStarted.html
Message-ID: <200904101538.n3AFcpAF021722@zion.cs.uiuc.edu>

Author: lattner
Date: Fri Apr 10 10:38:51 2009
New Revision: 68784

URL: http://llvm.org/viewvc/llvm-project?rev=68784&view=rev
Log:
fix typo, patch by Shlomi Fish!

Modified:
    llvm/trunk/docs/GettingStarted.html

Modified: llvm/trunk/docs/GettingStarted.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GettingStarted.html?rev=68784&r1=68783&r2=68784&view=diff

==============================================================================
--- llvm/trunk/docs/GettingStarted.html (original)
+++ llvm/trunk/docs/GettingStarted.html Fri Apr 10 10:38:51 2009
@@ -1489,7 +1489,7 @@
 
 <div class="doc_text">
 <p>This section gives an example of using LLVM.  llvm-gcc3 is now obsolete,
-so we only include instructiosn for llvm-gcc4.
+so we only include instructions for llvm-gcc4.
 </p>
 
 <p><b>Note:</b> The <i>gcc4</i> frontend's invocation is <b><i>considerably different</i></b>




From sabre at nondot.org  Fri Apr 10 10:47:18 2009
From: sabre at nondot.org (Chris Lattner)
Date: Fri, 10 Apr 2009 15:47:18 -0000
Subject: [llvm-commits] [llvm] r68785 - /llvm/trunk/include/llvm/ADT/ilist.h
Message-ID: <200904101547.n3AFlIGH022130@zion.cs.uiuc.edu>

Author: lattner
Date: Fri Apr 10 10:47:17 2009
New Revision: 68785

URL: http://llvm.org/viewvc/llvm-project?rev=68785&view=rev
Log:
fix a broken assertion in ilist_iterator, which caused it to crash in the
bad case instead of actually assert.  Bug pointed out by Jakob Stoklund 
Olesen!


Modified:
    llvm/trunk/include/llvm/ADT/ilist.h

Modified: llvm/trunk/include/llvm/ADT/ilist.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/ilist.h?rev=68785&r1=68784&r2=68785&view=diff

==============================================================================
--- llvm/trunk/include/llvm/ADT/ilist.h (original)
+++ llvm/trunk/include/llvm/ADT/ilist.h Fri Apr 10 10:47:17 2009
@@ -210,7 +210,7 @@
   // Increment and decrement operators...
   ilist_iterator &operator--() {      // predecrement - Back up
     NodePtr = Traits::getPrev(NodePtr);
-    assert(Traits::getNext(NodePtr) && "--'d off the beginning of an ilist!");
+    assert(NodePtr && "--'d off the beginning of an ilist!");
     return *this;
   }
   ilist_iterator &operator++() {      // preincrement - Advance




From gohman at apple.com  Fri Apr 10 10:59:39 2009
From: gohman at apple.com (Dan Gohman)
Date: Fri, 10 Apr 2009 15:59:39 -0000
Subject: [llvm-commits] [llvm] r68786 -
 /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
Message-ID: <200904101559.n3AFxdJn022632@zion.cs.uiuc.edu>

Author: djg
Date: Fri Apr 10 10:59:38 2009
New Revision: 68786

URL: http://llvm.org/viewvc/llvm-project?rev=68786&view=rev
Log:
Now that register classes have names, include the name in debug output.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp?rev=68786&r1=68785&r2=68786&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp Fri Apr 10 10:59:38 2009
@@ -268,9 +268,11 @@
         cerr << "Op->Val = "; Op.getNode()->dump(DAG); cerr << "\n";
         cerr << "MI = "; MI->print(cerr);
         cerr << "VReg = " << VReg << "\n";
-        cerr << "VReg RegClass     size = " << VRC->getSize()
+        cerr << "VReg RegClass " << VRC->getName()
+             << "     size = " << VRC->getSize()
              << ", align = " << VRC->getAlignment() << "\n";
-        cerr << "Expected RegClass size = " << RC->getSize()
+        cerr << "Expected RegClass " << RC->getName()
+             << " size = " << RC->getSize()
              << ", align = " << RC->getAlignment() << "\n";
         cerr << "Fatal error, aborting.\n";
         abort();




From Sanjiv.Gupta at microchip.com  Fri Apr 10 11:20:43 2009
From: Sanjiv.Gupta at microchip.com (Sanjiv.Gupta at microchip.com)
Date: Fri, 10 Apr 2009 09:20:43 -0700
Subject: [llvm-commits] [llvm] r68576 - in /llvm/trunk:
	include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/
	lib/Target/X86/ test/CodeGen/X86/
References: <200904080015.n380FVD1002889@zion.cs.uiuc.edu>
	<1239173437.9086.5.camel@idc-lt-i00171.microchip.com>
	<3394DD7B-46BB-42D1-9D1A-BFCEBD22DC4D@apple.com>
Message-ID: <F536B7C316F9474E9F7091239725AC9A4E9096@CHN-CL-MAIL01.mchp-main.com>

>>> +  assert(Op.getNode()->getNumValues() == 1 &&
>>> +         "ShrinkDemandedOp only supports nodes with one result!");
>>> +
>> This assert breaks via visitADD, when the ADD operation also  
>> produces a
>> carry, so Op.getNode()->getNumValues() is 2 there.

>ADD always has one result. ADDC and UADDO are used to represent an add
>with a carry result.

>Dan

Thanks Dan,
This helped us figure out a mistake where we were lowering an ADD to ADDC in PIC16 port.


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From sabre at nondot.org  Fri Apr 10 11:38:37 2009
From: sabre at nondot.org (Chris Lattner)
Date: Fri, 10 Apr 2009 16:38:37 -0000
Subject: [llvm-commits] [llvm] r68787 - in /llvm/trunk:
 lib/CodeGen/MachineSink.cpp test/CodeGen/Generic/2009-04-10-SinkCrash.ll
Message-ID: <200904101638.n3AGcbKT024110@zion.cs.uiuc.edu>

Author: lattner
Date: Fri Apr 10 11:38:36 2009
New Revision: 68787

URL: http://llvm.org/viewvc/llvm-project?rev=68787&view=rev
Log:
fix two problems with machine sinking:
1. Sinking would crash when the first instruction of a block was
   sunk due to iterator problems.
2. Instructions could be sunk to their current block, causing an
   infinite loop.

This fixes PR3968

Added:
    llvm/trunk/test/CodeGen/Generic/2009-04-10-SinkCrash.ll
Modified:
    llvm/trunk/lib/CodeGen/MachineSink.cpp

Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=68787&r1=68786&r2=68787&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/MachineSink.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineSink.cpp Fri Apr 10 11:38:36 2009
@@ -111,20 +111,29 @@
 }
 
 bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) {
-  bool MadeChange = false;
-  
   // Can't sink anything out of a block that has less than two successors.
-  if (MBB.succ_size() <= 1) return false;
-  
+  if (MBB.succ_size() <= 1 || MBB.empty()) return false;
+
+  bool MadeChange = false;
+
   // Walk the basic block bottom-up.  Remember if we saw a store.
-  bool SawStore = false;
-  for (MachineBasicBlock::iterator I = MBB.end(); I != MBB.begin(); ){
-    MachineBasicBlock::iterator LastIt = I;
-    if (SinkInstruction(--I, SawStore)) {
-      I = LastIt;
-      ++NumSunk;
-    }
-  }
+  MachineBasicBlock::iterator I = MBB.end();
+  --I;
+  bool ProcessedBegin, SawStore = false;
+  do {
+    MachineInstr *MI = I;  // The instruction to sink.
+    
+    // Predecrement I (if it's not begin) so that it isn't invalidated by
+    // sinking.
+    ProcessedBegin = I == MBB.begin();
+    if (!ProcessedBegin)
+      --I;
+    
+    if (SinkInstruction(MI, SawStore))
+      ++NumSunk, MadeChange = true;
+    
+    // If we just processed the first instruction in the block, we're done.
+  } while (!ProcessedBegin);
   
   return MadeChange;
 }
@@ -218,6 +227,11 @@
   if (SuccToSinkTo->isLandingPad())
     return false;
   
+  // If is not possible to sink an instruction into its own block.  This can
+  // happen with loops.
+  if (MI->getParent() == SuccToSinkTo)
+    return false;
+  
   DEBUG(cerr << "Sink instr " << *MI);
   DEBUG(cerr << "to block " << *SuccToSinkTo);
   

Added: llvm/trunk/test/CodeGen/Generic/2009-04-10-SinkCrash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2009-04-10-SinkCrash.ll?rev=68787&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2009-04-10-SinkCrash.ll (added)
+++ llvm/trunk/test/CodeGen/Generic/2009-04-10-SinkCrash.ll Fri Apr 10 11:38:36 2009
@@ -0,0 +1,16 @@
+; RUN: llvm-as < %s | llc
+
+define void @QRiterate(i32 %p.1, double %tmp.212) nounwind {
+entry:
+	br i1 false, label %shortcirc_next.1, label %exit.1.critedge
+
+shortcirc_next.1:		; preds = %shortcirc_next.1, %entry
+	%tmp.213 = fcmp une double %tmp.212, 0.000000e+00		; <i1> [#uses=1]
+	br i1 %tmp.213, label %shortcirc_next.1, label %exit.1
+
+exit.1.critedge:		; preds = %entry
+	ret void
+
+exit.1:		; preds = %shortcirc_next.1
+	ret void
+}




From isanbard at gmail.com  Fri Apr 10 12:45:16 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 10 Apr 2009 17:45:16 -0000
Subject: [llvm-commits] [llvm] r68795 - /llvm/trunk/utils/buildit/build_llvm
Message-ID: <200904101745.n3AHjGQF026649@zion.cs.uiuc.edu>

Author: void
Date: Fri Apr 10 12:45:16 2009
New Revision: 68795

URL: http://llvm.org/viewvc/llvm-project?rev=68795&view=rev
Log:
Don't run "dsymutils" on .a files.

Modified:
    llvm/trunk/utils/buildit/build_llvm

Modified: llvm/trunk/utils/buildit/build_llvm
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=68795&r1=68794&r2=68795&view=diff

==============================================================================
--- llvm/trunk/utils/buildit/build_llvm (original)
+++ llvm/trunk/utils/buildit/build_llvm Fri Apr 10 12:45:16 2009
@@ -235,8 +235,9 @@
 rm -rf * || exit 1
 
 # Generate .dSYM files
-find $DEST_DIR -perm -0111 -type f ! \( -name '*.la' -o -name gccas -o -name gccld -o -name llvm-config \) -print \
-    | xargs -n 1 -P ${SYSCTL} dsymutil
+find $DEST_DIR -perm -0111 -type f \
+    ! \( -name '*.la' -o -name gccas -o -name gccld -o -name llvm-config -o -name '*.a' \) \
+    -print | xargs -n 1 -P ${SYSCTL} dsymutil
 
 # Save .dSYM files and .a archives
 cd $DEST_DIR || exit 1




From isanbard at gmail.com  Fri Apr 10 13:20:41 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 10 Apr 2009 18:20:41 -0000
Subject: [llvm-commits] [llvm] r68801 - /llvm/trunk/Makefile.rules
Message-ID: <200904101820.n3AIKf7t027948@zion.cs.uiuc.edu>

Author: void
Date: Fri Apr 10 13:20:41 2009
New Revision: 68801

URL: http://llvm.org/viewvc/llvm-project?rev=68801&view=rev
Log:
Add compatibility_version and current_version flags when creating dylibs.

Modified:
    llvm/trunk/Makefile.rules

Modified: llvm/trunk/Makefile.rules
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=68801&r1=68800&r2=68801&view=diff

==============================================================================
--- llvm/trunk/Makefile.rules (original)
+++ llvm/trunk/Makefile.rules Fri Apr 10 13:20:41 2009
@@ -439,6 +439,7 @@
   DARWIN_MAJVERS := $(shell echo $(DARWIN_VERSION)| sed -E 's/10.([0-9]).*/\1/')
 
   SharedLinkOptions=-Wl,-flat_namespace -Wl,-undefined -Wl,suppress \
+                    -compatibility_version 1 -current_version 1 \
                     -dynamiclib -mmacosx-version-min=$(DARWIN_VERSION)
   TargetCommonOpts += -mmacosx-version-min=$(DARWIN_VERSION)
 else




From isanbard at gmail.com  Fri Apr 10 13:48:38 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 10 Apr 2009 18:48:38 -0000
Subject: [llvm-commits] [llvm] r68807 - in /llvm/trunk: Makefile.rules
	utils/buildit/build_llvm
Message-ID: <200904101848.n3AImc03028907@zion.cs.uiuc.edu>

Author: void
Date: Fri Apr 10 13:48:38 2009
New Revision: 68807

URL: http://llvm.org/viewvc/llvm-project?rev=68807&view=rev
Log:
Don't install the libLLVMHello.dylib example.

Modified:
    llvm/trunk/Makefile.rules
    llvm/trunk/utils/buildit/build_llvm

Modified: llvm/trunk/Makefile.rules
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=68807&r1=68806&r2=68807&view=diff

==============================================================================
--- llvm/trunk/Makefile.rules (original)
+++ llvm/trunk/Makefile.rules Fri Apr 10 13:48:38 2009
@@ -439,7 +439,6 @@
   DARWIN_MAJVERS := $(shell echo $(DARWIN_VERSION)| sed -E 's/10.([0-9]).*/\1/')
 
   SharedLinkOptions=-Wl,-flat_namespace -Wl,-undefined -Wl,suppress \
-                    -compatibility_version 1 -current_version 1 \
                     -dynamiclib -mmacosx-version-min=$(DARWIN_VERSION)
   TargetCommonOpts += -mmacosx-version-min=$(DARWIN_VERSION)
 else

Modified: llvm/trunk/utils/buildit/build_llvm
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=68807&r1=68806&r2=68807&view=diff

==============================================================================
--- llvm/trunk/utils/buildit/build_llvm (original)
+++ llvm/trunk/utils/buildit/build_llvm Fri Apr 10 13:48:38 2009
@@ -207,6 +207,9 @@
 strip -S $DT_HOME/lib/libLTO.dylib
 rm -f lib/libLTO.a lib/libLTO.la
 
+# The Hello dylib is an example of how to build a pass. No need to install it.
+rm lib/libLLVMHello.dylib
+
 # Compress manpages
 MDIR=$DEST_DIR$DEST_ROOT/share/man/man1
 gzip -f $MDIR/*




From bob.wilson at apple.com  Fri Apr 10 13:48:47 2009
From: bob.wilson at apple.com (Bob Wilson)
Date: Fri, 10 Apr 2009 18:48:47 -0000
Subject: [llvm-commits] [llvm] r68808 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Message-ID: <200904101848.n3AImmH0028924@zion.cs.uiuc.edu>

Author: bwilson
Date: Fri Apr 10 13:48:47 2009
New Revision: 68808

URL: http://llvm.org/viewvc/llvm-project?rev=68808&view=rev
Log:
Clean up a bunch of whitespace issues and fix a comment typo.
No functional changes.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=68808&r1=68807&r2=68808&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Apr 10 13:48:47 2009
@@ -685,7 +685,7 @@
 
       // Perform the original store, only redirected to the stack slot.
       SDValue Store = DAG.getTruncStore(Chain, dl,
-                                        Val, StackPtr, NULL, 0,StoredVT);
+                                        Val, StackPtr, NULL, 0, StoredVT);
       SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
       SmallVector<SDValue, 8> Stores;
       unsigned Offset = 0;
@@ -864,7 +864,7 @@
                         MinAlign(Alignment, IncrementSize));
   } else {
     Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
-                        SVOffset, NewLoadedVT,LD->isVolatile(), Alignment);
+                        SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
     Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
                       DAG.getConstant(IncrementSize, TLI.getPointerTy()));
     Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
@@ -1316,7 +1316,7 @@
     }
    case TargetLowering::Custom:
       Result = TLI.LowerOperation(Op, DAG);
-      if (Result.getNode()) 
+      if (Result.getNode())
         break;
     case TargetLowering::Legal: {
       LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
@@ -1647,7 +1647,7 @@
         if (Tmp2.getValueType() ==
             Op.getValueType().getVectorElementType()) {
           SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
-                                        Tmp1.getValueType(), Tmp2);
+                                      Tmp1.getValueType(), Tmp2);
 
           unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
           MVT ShufMaskVT =
@@ -1665,7 +1665,7 @@
               ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
           }
           SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, ShufMaskVT,
-                                           &ShufOps[0], ShufOps.size());
+                                         &ShufOps[0], ShufOps.size());
 
           Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Tmp1.getValueType(),
                                Tmp1, ScVec, ShufMask);
@@ -1709,7 +1709,7 @@
     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
 
     // Allow targets to custom lower the SHUFFLEs they support.
-    switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
+    switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, Result.getValueType())){
     default: assert(0 && "Unknown operation action!");
     case TargetLowering::Legal:
       assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
@@ -1728,7 +1728,7 @@
       MVT PtrVT = TLI.getPointerTy();
       SDValue Mask = Node->getOperand(2);
       unsigned NumElems = Mask.getNumOperands();
-      SmallVector<SDValue,8> Ops;
+      SmallVector<SDValue, 8> Ops;
       for (unsigned i = 0; i != NumElems; ++i) {
         SDValue Arg = Mask.getOperand(i);
         if (Arg.getOpcode() == ISD::UNDEF) {
@@ -2475,7 +2475,7 @@
 
           if (Hi.getNode())
             Result = DAG.getNode(ISD::RET, dl, MVT::Other,
-                                 Tmp1, Lo, Tmp3, Hi,Tmp3);
+                                 Tmp1, Lo, Tmp3, Hi, Tmp3);
           else
             Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3);
           Result = LegalizeOp(Result);
@@ -2510,7 +2510,7 @@
             SDValue Lo, Hi;
             SplitVectorOp(Tmp2, Lo, Hi);
             Result = DAG.getNode(ISD::RET, dl, MVT::Other,
-                                 Tmp1, Lo, Tmp3, Hi,Tmp3);
+                                 Tmp1, Lo, Tmp3, Hi, Tmp3);
             Result = LegalizeOp(Result);
           }
         }
@@ -3009,7 +3009,7 @@
       Tmp2 = DAG.getNode(ExtOp, dl, NVT, Tmp2);
       Tmp3 = DAG.getNode(ExtOp, dl, NVT, Tmp3);
       // Perform the larger operation, then round down.
-      Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2,Tmp3);
+      Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
       if (TruncOp != ISD::FP_ROUND)
         Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result);
       else
@@ -3147,9 +3147,10 @@
                                               TmpEltVT, Tmp2,
                                               DAG.getIntPtrConstant(i)),
                              CC);
-        Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i], DAG.getConstant(
-                                  APInt::getAllOnesValue(EltVT.getSizeInBits()),
-                                  EltVT), DAG.getConstant(0, EltVT));
+        Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i],
+                             DAG.getConstant(APInt::getAllOnesValue
+                                             (EltVT.getSizeInBits()), EltVT),
+                             DAG.getConstant(0, EltVT));
       }
       Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems);
       break;
@@ -4361,7 +4362,7 @@
       // If this operation is not supported, lower it to 'abort()' call
       Tmp1 = LegalizeOp(Node->getOperand(0));
       TargetLowering::ArgListTy Args;
-      std::pair<SDValue,SDValue> CallResult =
+      std::pair<SDValue, SDValue> CallResult =
         TLI.LowerCallTo(Tmp1, Type::VoidTy,
                         false, false, false, false, CallingConv::C, false,
                         DAG.getExternalSymbol("abort", TLI.getPointerTy()),
@@ -5329,7 +5330,7 @@
       if (!Tmp2.getNode())
         Tmp2 = DAG.getNode(ISD::SETCC, dl,
                            TLI.getSetCCResultType(LHSHi.getValueType()),
-                           LHSHi, RHSHi,CC);
+                           LHSHi, RHSHi, CC);
 
       ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
       ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
@@ -5418,8 +5419,9 @@
                                                MVT DestVT,
                                                DebugLoc dl) {
   // Create the stack frame object.
-  unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
-                                          SrcOp.getValueType().getTypeForMVT());
+  unsigned SrcAlign =
+    TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
+                                              getTypeForMVT());
   SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
 
   FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
@@ -5429,8 +5431,8 @@
   unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
   unsigned SlotSize = SlotVT.getSizeInBits();
   unsigned DestSize = DestVT.getSizeInBits();
-  unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
-                                                        DestVT.getTypeForMVT());
+  unsigned DestAlign =
+    TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT());
 
   // Emit a store to the stack slot.  Use a truncstore if the input value is
   // later than DestVT.
@@ -5464,8 +5466,8 @@
   int SPFI = StackPtrFI->getIndex();
 
   SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(0),
-                              StackPtr,
-                              PseudoSourceValue::getFixedStack(SPFI), 0);
+                            StackPtr,
+                            PseudoSourceValue::getFixedStack(SPFI), 0);
   return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
                      PseudoSourceValue::getFixedStack(SPFI), 0);
 }
@@ -5497,7 +5499,7 @@
     if (V.getOpcode() != ISD::UNDEF)
       isOnlyLowElement = false;
     if (SplatValue != V)
-      SplatValue = SDValue(0,0);
+      SplatValue = SDValue(0, 0);
 
     // If this isn't a constant element or an undef, we can't use a constant
     // pool load.
@@ -5524,7 +5526,7 @@
           dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
         CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
       } else if (ConstantSDNode *V =
-                   dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
+                 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
         CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
       } else {
         assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
@@ -5547,7 +5549,7 @@
     SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
     std::vector<SDValue> ZeroVec(NumElems, Zero);
     SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                                      &ZeroVec[0], ZeroVec.size());
+                                    &ZeroVec[0], ZeroVec.size());
 
     // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
     if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
@@ -5576,7 +5578,7 @@
     else
       Val2 = (++MI)->first;
 
-    // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
+    // If Val1 is an undef, make sure it ends up as Val2, to ensure that our
     // vector shuffle has the undef vector on the RHS.
     if (Val1.getOpcode() == ISD::UNDEF)
       std::swap(Val1, Val2);
@@ -5600,7 +5602,7 @@
         MaskVec[Val2Elts[i]] = DAG.getUNDEF(MaskEltVT);
 
     SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                                        &MaskVec[0], MaskVec.size());
+                                      &MaskVec[0], MaskVec.size());
 
     // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
     if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR,
@@ -5671,7 +5673,7 @@
 /// smaller elements.  If we can't find a way that is more efficient than a
 /// libcall on this target, return false.  Otherwise, return true with the
 /// low-parts expanded into Lo and Hi.
-bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
+bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
                                        SDValue &Lo, SDValue &Hi,
                                        DebugLoc dl) {
   assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
@@ -5698,7 +5700,7 @@
       } else if (Cst > NVTBits) {
         Lo = DAG.getConstant(0, NVT);
         Hi = DAG.getNode(ISD::SHL, dl,
-                         NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
+                         NVT, InL, DAG.getConstant(Cst-NVTBits, ShTy));
       } else if (Cst == NVTBits) {
         Lo = DAG.getConstant(0, NVT);
         Hi = InL;
@@ -5716,7 +5718,7 @@
         Hi = DAG.getConstant(0, NVT);
       } else if (Cst > NVTBits) {
         Lo = DAG.getNode(ISD::SRL, dl, NVT,
-                         InH, DAG.getConstant(Cst-NVTBits,ShTy));
+                         InH, DAG.getConstant(Cst-NVTBits, ShTy));
         Hi = DAG.getConstant(0, NVT);
       } else if (Cst == NVTBits) {
         Lo = InH;
@@ -5850,7 +5852,7 @@
 
   // Splice the libcall in wherever FindInputOutputChains tells us to.
   const Type *RetTy = Node->getValueType(0).getTypeForMVT();
-  std::pair<SDValue,SDValue> CallInfo =
+  std::pair<SDValue, SDValue> CallInfo =
     TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
                     CallingConv::C, false, Callee, Args, DAG,
                     Node->getDebugLoc());
@@ -5914,10 +5916,9 @@
     Tmp1 = PromoteOp(Op);
     if (isSigned) {
       Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(),
-               Tmp1, DAG.getValueType(Op.getValueType()));
+                         Tmp1, DAG.getValueType(Op.getValueType()));
     } else {
-      Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl,
-                                    Op.getValueType());
+      Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, Op.getValueType());
     }
     if (Result.getNode())
       Result = DAG.UpdateNodeOperands(Result, Tmp1);
@@ -5984,7 +5985,7 @@
       break;   // This case is handled below.
     case TargetLowering::Custom: {
       SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, dl, DestTy,
-                                                    Source), DAG);
+                                                  Source), DAG);
       if (NV.getNode())
         return LegalizeOp(NV);
       break;   // The target decided this was legal after all
@@ -6046,7 +6047,7 @@
     break;   // This case is handled below.
   case TargetLowering::Custom: {
     SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, dl, DestTy,
-                                                  Source), DAG);
+                                                Source), DAG);
     if (NV.getNode())
       return LegalizeOp(NV);
     break;   // The target decided this was legal after all
@@ -6093,7 +6094,7 @@
     // set up Hi and Lo (into buffer) address based on endian
     SDValue Hi = StackSlot;
     SDValue Lo = DAG.getNode(ISD::ADD, dl,
-                             TLI.getPointerTy(), StackSlot,WordOff);
+                             TLI.getPointerTy(), StackSlot, WordOff);
     if (TLI.isLittleEndian())
       std::swap(Hi, Lo);
 
@@ -6108,7 +6109,7 @@
     }
     // store the lo of the constructed double - based on integer input
     SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
-                                    Op0Mapped, Lo, NULL, 0);
+                                  Op0Mapped, Lo, NULL, 0);
     // initial hi portion of constructed double
     SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
     // store the hi of the constructed double - biased exponent
@@ -6117,8 +6118,8 @@
     SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
     // FP constant to bias correct the final result
     SDValue Bias = DAG.getConstantFP(isSigned ?
-                                            BitsToDouble(0x4330000080000000ULL)
-                                          : BitsToDouble(0x4330000000000000ULL),
+                                     BitsToDouble(0x4330000080000000ULL) :
+                                     BitsToDouble(0x4330000000000000ULL),
                                      MVT::f64);
     // subtract the bias
     SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
@@ -6454,8 +6455,9 @@
       SDValue SrcLo, SrcHi, Src;
       ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
       Src = DAG.getNode(ISD::BUILD_PAIR, dl, VT, SrcLo, SrcHi);
-      SDValue Result = TLI.LowerOperation(
-        DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src, Op.getOperand(1)), DAG);
+      SDValue Result =
+        TLI.LowerOperation(DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src,
+                                       Op.getOperand(1)), DAG);
       assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
       Lo = Result.getNode()->getOperand(0);
       Hi = Result.getNode()->getOperand(1);
@@ -6630,7 +6632,7 @@
       // Build a factor node to remember that this load is independent of the
       // other one.
       SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
-                                 Hi.getValue(1));
+                               Hi.getValue(1));
 
       // Remember that we legalized the chain.
       AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
@@ -6643,7 +6645,7 @@
           (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
         // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
         SDValue Load = DAG.getLoad(EVT, dl, Ch, Ptr, SV,
-                                     SVOffset, isVolatile, Alignment);
+                                   SVOffset, isVolatile, Alignment);
         // Remember that we legalized the chain.
         AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
         ExpandOp(DAG.getNode(ISD::FP_EXTEND, dl, VT, Load), Lo, Hi);
@@ -6829,7 +6831,7 @@
     SDValue Result = TLI.LowerOperation(Replace, DAG);
     ExpandOp(Result.getValue(0), Lo, Hi);
     // Remember that we legalized the chain.
-    AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
+    AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Result.getValue(1)));
     break;
   }
 
@@ -7352,8 +7354,8 @@
       Hi = DAG.getNode(ISD::FABS, dl, NVT, Tmp);
       // lo = hi==fabs(hi) ? lo : -lo;
       Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Hi, Tmp,
-                    Lo, DAG.getNode(ISD::FNEG, dl, NVT, Lo),
-                    DAG.getCondCode(ISD::SETEQ));
+                       Lo, DAG.getNode(ISD::FNEG, dl, NVT, Lo),
+                       DAG.getCondCode(ISD::SETEQ));
       break;
     }
     SDValue Mask = (VT == MVT::f64)
@@ -7423,9 +7425,9 @@
                              MVT::ppcf128, Node->getOperand(0),
                              DAG.getConstant(0, MVT::i32),
                              DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
-                                         DAG.getConstantFP(
-                                            APFloat(APInt(128, 2, TwoE32)),
-                                            MVT::ppcf128)),
+                                         DAG.getConstantFP
+                                         (APFloat(APInt(128, 2, TwoE32)),
+                                          MVT::ppcf128)),
                              Hi,
                              DAG.getCondCode(ISD::SETLT)),
                  Lo, Hi);
@@ -7443,9 +7445,9 @@
                            Node->getOperand(0),
                            DAG.getConstant(0, MVT::i64),
                            DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
-                                       DAG.getConstantFP(
-                                          APFloat(APInt(128, 2, TwoE64)),
-                                          MVT::ppcf128)),
+                                       DAG.getConstantFP
+                                       (APFloat(APInt(128, 2, TwoE64)),
+                                        MVT::ppcf128)),
                            Hi,
                            DAG.getCondCode(ISD::SETLT)),
                Lo, Hi);
@@ -7532,8 +7534,8 @@
       break;
     }
     SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
-                                                   Node->getOperand(1),
-                                                   Node->getOperand(2), dl);
+                                                 Node->getOperand(1),
+                                                 Node->getOperand(2), dl);
     SplitVectorOp(Tmp, Lo, Hi);
     break;
   }
@@ -7584,11 +7586,11 @@
   }
   case ISD::BUILD_VECTOR: {
     SmallVector<SDValue, 8> LoOps(Node->op_begin(),
-                                    Node->op_begin()+NewNumElts_Lo);
+                                  Node->op_begin()+NewNumElts_Lo);
     Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &LoOps[0], LoOps.size());
 
     SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
-                                    Node->op_end());
+                                  Node->op_end());
     Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &HiOps[0], HiOps.size());
     break;
   }
@@ -7605,7 +7607,7 @@
                        &LoOps[0], LoOps.size());
 
       SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
-                                      Node->op_end());
+                                    Node->op_end());
       Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Hi,
                        &HiOps[0], HiOps.size());
     }
@@ -7742,10 +7744,10 @@
     ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
     SDValue L, H;
     SplitVectorOp(Node->getOperand(0), L, H);
-    SDValue DTyOpL =  DAG.getValueType(NewVT_Lo);
-    SDValue DTyOpH =  DAG.getValueType(NewVT_Hi);
-    SDValue STyOpL =  DAG.getValueType(L.getValueType());
-    SDValue STyOpH =  DAG.getValueType(H.getValueType());
+    SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
+    SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
+    SDValue STyOpL = DAG.getValueType(L.getValueType());
+    SDValue STyOpH = DAG.getValueType(H.getValueType());
 
     SDValue RndOp = Node->getOperand(3);
     SDValue SatOp = Node->getOperand(4);
@@ -7789,7 +7791,7 @@
     // Build a factor node to remember that this load is independent of the
     // other one.
     SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
-                               Hi.getValue(1));
+                             Hi.getValue(1));
 
     // Remember that we legalized the chain.
     AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
@@ -7804,14 +7806,14 @@
       // The input is a scalar or single-element vector.
       // Lower to a store/load so that it can be split.
       // FIXME: this could be improved probably.
-      unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
-                                            Op.getValueType().getTypeForMVT());
+      unsigned LdAlign = TLI.getTargetData()->
+        getPrefTypeAlignment(Op.getValueType().getTypeForMVT());
       SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
       int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
 
       SDValue St = DAG.getStore(DAG.getEntryNode(), dl,
-                                  InOp, Ptr,
-                                  PseudoSourceValue::getFixedStack(FI), 0);
+                                InOp, Ptr,
+                                PseudoSourceValue::getFixedStack(FI), 0);
       InOp = DAG.getLoad(Op.getValueType(), dl, St, Ptr,
                          PseudoSourceValue::getFixedStack(FI), 0);
     }
@@ -8441,7 +8443,7 @@
   EVTWidth = EVT.getSizeInBits();
 
   SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, SVOffset,
-                               isVolatile, Alignment);
+                             isVolatile, Alignment);
   SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecEVT, LdOp);
   LdChain.push_back(LdOp.getValue(1));
 
@@ -8473,8 +8475,8 @@
     }
 
     SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV,
-                                 SVOffset+Offset, isVolatile,
-                                 MinAlign(Alignment, Offset));
+                               SVOffset+Offset, isVolatile,
+                               MinAlign(Alignment, Offset));
     LdChain.push_back(LdOp.getValue(1));
     VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecEVT, VecOp, LdOp,
                         DAG.getIntPtrConstant(Idx++));
@@ -8553,7 +8555,7 @@
   SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
                             DAG.getIntPtrConstant(0));
   SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset,
-                               isVolatile, Alignment);
+                              isVolatile, Alignment);
   StChain.push_back(StOp);
 
   // Check if we are done
@@ -8593,8 +8595,8 @@
 
 
 SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
-                                                   SDValue Chain,
-                                                   SDValue BasePtr) {
+                                                 SDValue Chain,
+                                                 SDValue BasePtr) {
   // TODO: It might be cleaner if we can use SplitVector and have more legal
   //        vector types that can be stored into memory (e.g., v4xi8 can
   //        be stored as a word). This will not work when a vector register




From isanbard at gmail.com  Fri Apr 10 13:51:36 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 10 Apr 2009 18:51:36 -0000
Subject: [llvm-commits] [llvm] r68810 - in /llvm/tags/Apple/llvmCore-2105.1:
 ./ utils/buildit/build_llvm
Message-ID: <200904101851.n3AIpawx029050@zion.cs.uiuc.edu>

Author: void
Date: Fri Apr 10 13:51:36 2009
New Revision: 68810

URL: http://llvm.org/viewvc/llvm-project?rev=68810&view=rev
Log:
Tag 2105 with subversion 1. It fixes some build verification failures:

- Running dsymutils on archive files.
- Don't install libLLVMHello.dylib, because it's an example dylib.

Added:
    llvm/tags/Apple/llvmCore-2105.1/
      - copied from r68798, llvm/tags/Apple/llvmCore-2105/
Modified:
    llvm/tags/Apple/llvmCore-2105.1/utils/buildit/build_llvm

Modified: llvm/tags/Apple/llvmCore-2105.1/utils/buildit/build_llvm
URL: http://llvm.org/viewvc/llvm-project/llvm/tags/Apple/llvmCore-2105.1/utils/buildit/build_llvm?rev=68810&r1=68798&r2=68810&view=diff

==============================================================================
--- llvm/tags/Apple/llvmCore-2105.1/utils/buildit/build_llvm (original)
+++ llvm/tags/Apple/llvmCore-2105.1/utils/buildit/build_llvm Fri Apr 10 13:51:36 2009
@@ -207,6 +207,9 @@
 strip -S $DT_HOME/lib/libLTO.dylib
 rm -f lib/libLTO.a lib/libLTO.la
 
+# The Hello dylib is an example of how to build a pass. No need to install it.
+rm lib/libLLVMHello.dylib
+
 # Compress manpages
 MDIR=$DEST_DIR$DEST_ROOT/share/man/man1
 gzip -f $MDIR/*
@@ -235,8 +238,9 @@
 rm -rf * || exit 1
 
 # Generate .dSYM files
-find $DEST_DIR -perm -0111 -type f ! \( -name '*.la' -o -name gccas -o -name gccld -o -name llvm-config \) -print \
-    | xargs -n 1 -P ${SYSCTL} dsymutil
+find $DEST_DIR -perm -0111 -type f \
+    ! \( -name '*.la' -o -name gccas -o -name gccld -o -name llvm-config -o -name '*.a' \) \
+    -print | xargs -n 1 -P ${SYSCTL} dsymutil
 
 # Save .dSYM files and .a archives
 cd $DEST_DIR || exit 1




From isanbard at gmail.com  Fri Apr 10 13:52:49 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 10 Apr 2009 18:52:49 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r68812 -
	/llvm-gcc-4.2/tags/Apple/llvmgcc42-2105.1/
Message-ID: <200904101852.n3AIqnjO029113@zion.cs.uiuc.edu>

Author: void
Date: Fri Apr 10 13:52:48 2009
New Revision: 68812

URL: http://llvm.org/viewvc/llvm-project?rev=68812&view=rev
Log:
Create llvmgcc42-2105.1 from llvmgcc42-2105. No changes, just bumping up the
subversion number.

Added:
    llvm-gcc-4.2/tags/Apple/llvmgcc42-2105.1/
      - copied from r68810, llvm-gcc-4.2/tags/Apple/llvmgcc42-2105/



From dpatel at apple.com  Fri Apr 10 13:59:00 2009
From: dpatel at apple.com (Devang Patel)
Date: Fri, 10 Apr 2009 18:59:00 -0000
Subject: [llvm-commits] [llvm] r68813 - in /llvm/trunk:
 include/llvm/CodeGen/MachineModuleInfo.h lib/CodeGen/MachineModuleInfo.cpp
Message-ID: <200904101859.n3AIx0Zv029350@zion.cs.uiuc.edu>

Author: dpatel
Date: Fri Apr 10 13:58:59 2009
New Revision: 68813

URL: http://llvm.org/viewvc/llvm-project?rev=68813&view=rev
Log:
DebugLabelFolder ruthlessly deletes redundant labels. However, sometimes the redundant labels is referenced by debug info somewhere else. This patch provies a way so that dwarf writer can mark labels as used.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h
    llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h?rev=68813&r1=68812&r2=68813&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h Fri Apr 10 13:58:59 2009
@@ -37,6 +37,7 @@
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/UniqueVector.h"
 #include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/CodeGen/MachineLocation.h"
 #include "llvm/GlobalValue.h"
@@ -115,6 +116,9 @@
   // searchable format.
   SmallPtrSet<const Function *, 32> UsedFunctions;
 
+  /// UsedDbgLabels - labels are used by debug info entries.
+  SmallSet<unsigned, 8> UsedDbgLabels;
+
   bool CallsEHReturn;
   bool CallsUnwindInit;
  
@@ -195,6 +199,19 @@
     return LabelID ? LabelIDList[LabelID - 1] : 0;
   }
 
+  /// isDbgLabelUsed - Return true if label with LabelID is used by
+  /// DwarfWriter.
+  bool isDbgLabelUsed(unsigned LabelID) {
+    return UsedDbgLabels.count(LabelID);
+  }
+  
+  /// RecordUsedDbgLabel - Mark label with LabelID as used. This is used
+  /// by DwarfWriter to inform DebugLabelFolder that certain labels are
+  /// not to be deleted.
+  void RecordUsedDbgLabel(unsigned LabelID) {
+    UsedDbgLabels.insert(LabelID);
+  }
+
   /// getFrameMoves - Returns a reference to a list of moves done in the current
   /// function's prologue.  Used to construct frame maps for debug and exception
   /// handling comsumers.

Modified: llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp?rev=68813&r1=68812&r2=68813&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp Fri Apr 10 13:58:59 2009
@@ -333,7 +333,7 @@
     // Iterate through instructions.
     for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ) {
       // Is it a label.
-      if (I->isDebugLabel()) {
+      if (I->isDebugLabel() && !MMI->isDbgLabelUsed(I->getOperand(0).getImm())){
         // The label ID # is always operand #0, an immediate.
         unsigned NextLabel = I->getOperand(0).getImm();
         




From brukman+llvm at gmail.com  Fri Apr 10 15:48:27 2009
From: brukman+llvm at gmail.com (Misha Brukman)
Date: Fri, 10 Apr 2009 20:48:27 -0000
Subject: [llvm-commits] [llvm] r68821 - /llvm/trunk/docs/FAQ.html
Message-ID: <200904102048.n3AKmRod001317@zion.cs.uiuc.edu>

Author: brukman
Date: Fri Apr 10 15:48:27 2009
New Revision: 68821

URL: http://llvm.org/viewvc/llvm-project?rev=68821&view=rev
Log:
Fixed spelling.

Modified:
    llvm/trunk/docs/FAQ.html

Modified: llvm/trunk/docs/FAQ.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/FAQ.html?rev=68821&r1=68820&r2=68821&view=diff

==============================================================================
--- llvm/trunk/docs/FAQ.html (original)
+++ llvm/trunk/docs/FAQ.html Fri Apr 10 15:48:27 2009
@@ -700,7 +700,7 @@
 
 <p>Another example is <tt>sizeof</tt>. It's common for <tt>sizeof(long)</tt> to
    vary between platforms. In most C front-ends, <tt>sizeof</tt> is expanded to
-   a constant immediately, thus hardwaring a platform-specific detail.</p>
+   a constant immediately, thus hard-wiring a platform-specific detail.</p>
 
 <p>Also, since many platforms define their ABIs in terms of C, and since LLVM is
    lower-level than C, front-ends currently must emit platform-specific IR in




From sabre at nondot.org  Fri Apr 10 18:58:38 2009
From: sabre at nondot.org (Chris Lattner)
Date: Fri, 10 Apr 2009 23:58:38 -0000
Subject: [llvm-commits] [llvm] r68843 - in /llvm/trunk/test/CodeGen:
 ARM/2009-02-22-SoftenFloatVaArg.ll Generic/2009-02-22-SoftenFloatVaArg.ll
Message-ID: <200904102358.n3ANwcuf008448@zion.cs.uiuc.edu>

Author: lattner
Date: Fri Apr 10 18:58:38 2009
New Revision: 68843

URL: http://llvm.org/viewvc/llvm-project?rev=68843&view=rev
Log:
move a target-specific test into its directory so it isn't run if you
don't configure the ARM target in.

Added:
    llvm/trunk/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll
      - copied unchanged from r68784, llvm/trunk/test/CodeGen/Generic/2009-02-22-SoftenFloatVaArg.ll
Removed:
    llvm/trunk/test/CodeGen/Generic/2009-02-22-SoftenFloatVaArg.ll

Removed: llvm/trunk/test/CodeGen/Generic/2009-02-22-SoftenFloatVaArg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2009-02-22-SoftenFloatVaArg.ll?rev=68842&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2009-02-22-SoftenFloatVaArg.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/2009-02-22-SoftenFloatVaArg.ll (removed)
@@ -1,20 +0,0 @@
-; RUN: llvm-as < %s | llc
-; PR3610
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-s0:0:64-f80:32:32"
-target triple = "arm-elf"
-
-define i32 @main(i8*) nounwind {
-entry:
-	%ap = alloca i8*		; <i8**> [#uses=2]
-	store i8* %0, i8** %ap
-	%retval = alloca i32		; <i32*> [#uses=2]
-	store i32 0, i32* %retval
-	%tmp = alloca float		; <float*> [#uses=1]
-	%1 = va_arg i8** %ap, float		; <float> [#uses=1]
-	store float %1, float* %tmp
-	br label %return
-
-return:		; preds = %entry
-	%2 = load i32* %retval		; <i32> [#uses=1]
-	ret i32 %2
-}




From dpatel at apple.com  Fri Apr 10 19:16:47 2009
From: dpatel at apple.com (Devang Patel)
Date: Sat, 11 Apr 2009 00:16:47 -0000
Subject: [llvm-commits] [llvm] r68847 - in /llvm/trunk:
 include/llvm/CodeGen/DwarfWriter.h include/llvm/Target/TargetAsmInfo.h
 lib/CodeGen/AsmPrinter/DwarfWriter.cpp
 lib/CodeGen/SelectionDAG/FastISel.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp lib/Target/TargetAsmInfo.cpp
 lib/Target/X86/X86TargetAsmInfo.cpp
Message-ID: <200904110016.n3B0GmYs009165@zion.cs.uiuc.edu>

Author: dpatel
Date: Fri Apr 10 19:16:47 2009
New Revision: 68847

URL: http://llvm.org/viewvc/llvm-project?rev=68847&view=rev
Log:
Keep track of inlined functions and their locations. This information is collected when nested llvm.dbg.func.start intrinsics are seen. (Right now, inliner removes nested llvm.dbg.func.start intrinisics during inlining.) 

Create debug_inlined dwarf section using these information. This info is used by gdb, at least on Darwin, to enable better experience debugging inlined functions. See DwarfWriter.cpp for more information on structure of debug_inlined section.


Modified:
    llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
    llvm/trunk/include/llvm/Target/TargetAsmInfo.h
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
    llvm/trunk/lib/Target/TargetAsmInfo.cpp
    llvm/trunk/lib/Target/X86/X86TargetAsmInfo.cpp

Modified: llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DwarfWriter.h?rev=68847&r1=68846&r2=68847&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/DwarfWriter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/DwarfWriter.h Fri Apr 10 19:16:47 2009
@@ -94,6 +94,9 @@
   /// RecordRegionStart - Indicate the start of a region.
   unsigned RecordRegionStart(GlobalVariable *V);
 
+  /// RecordRegionStart - Indicate the start of a region.
+  unsigned RecordRegionStart(GlobalVariable *V, unsigned ID);
+
   /// RecordRegionEnd - Indicate the end of a region.
   unsigned RecordRegionEnd(GlobalVariable *V);
 
@@ -107,6 +110,10 @@
   /// ShouldEmitDwarfDebug - Returns true if Dwarf debugging declarations should
   /// be emitted.
   bool ShouldEmitDwarfDebug() const;
+
+  //// RecordInlineInfo - Global variable GV is inlined at the location marked
+  //// by LabelID label.
+  void RecordInlineInfo(GlobalVariable *GV, unsigned LabelID);
 };
 
 

Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=68847&r1=68846&r2=68847&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Fri Apr 10 19:16:47 2009
@@ -506,7 +506,11 @@
     /// DwarfPubTypesSection - Section directive for Dwarf info.
     ///
     const char *DwarfPubTypesSection; // Defaults to ".debug_pubtypes".
-    
+
+    /// DwarfDebugInlineSection - Section directive for inline info.
+    ///
+    const char *DwarfDebugInlineSection; // Defaults to ".debug_inlined"
+
     /// DwarfStrSection - Section directive for Dwarf info.
     ///
     const char *DwarfStrSection; // Defaults to ".debug_str".
@@ -880,6 +884,9 @@
     const char *getDwarfPubTypesSection() const {
       return DwarfPubTypesSection;
     }
+    const char *getDwarfDebugInlineSection() const {
+      return DwarfDebugInlineSection;
+    }
     const char *getDwarfStrSection() const {
       return DwarfStrSection;
     }

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=68847&r1=68846&r2=68847&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Fri Apr 10 19:16:47 2009
@@ -1252,6 +1252,10 @@
   /// DbgScopeMap - Tracks the scopes in the current function.
   DenseMap<GlobalVariable *, DbgScope *> DbgScopeMap;
 
+  /// InlineInfo - Keep track of inlined functions and their location.
+  /// This information is used to populate debug_inlined section.
+  DenseMap<GlobalVariable *, SmallVector<unsigned, 4> > InlineInfo;
+
   /// DebugTimer - Timer for the Dwarf debug writer.
   Timer *DebugTimer;
   
@@ -2027,15 +2031,18 @@
     for (unsigned j = 0, M = Scopes.size(); j < M; ++j) {
       // Define the Scope debug information entry.
       DbgScope *Scope = Scopes[j];
-      // FIXME - Ignore inlined functions for the time being.
-      if (!Scope->getParent()) continue;
 
       unsigned StartID = MMI->MappedLabel(Scope->getStartLabelID());
       unsigned EndID = MMI->MappedLabel(Scope->getEndLabelID());
 
       // Ignore empty scopes.
       if (StartID == EndID && StartID != 0) continue;
-      if (Scope->getScopes().empty() && Scope->getVariables().empty()) continue;
+
+      // Do not ignore inlined scope even if it is empty. Inlined scope 
+      // does not have any parent.
+      if (Scope->getParent() 
+          && Scope->getScopes().empty() && Scope->getVariables().empty()) 
+        continue;
 
       if (StartID == ParentStartID && EndID == ParentEndID) {
         // Just add stuff to the parent scope.
@@ -2781,6 +2788,74 @@
     }
   }
 
+  /// EmitDebugInlineInfo - Emit inline info using following format.
+  /// Section Header:
+  /// 1. length of section
+  /// 2. Dwarf version number
+  /// 3. address size.
+  ///
+  /// Entries (one "entry" for each function that was inlined):
+  ///
+  /// 1. offset into __debug_str section for MIPS linkage name, if exists; 
+  ///   otherwise offset into __debug_str for regular function name.
+  /// 2. offset into __debug_str section for regular function name.
+  /// 3. an unsigned LEB128 number indicating the number of distinct inlining 
+  /// instances for the function.
+  /// 
+  /// The rest of the entry consists of a {die_offset, low_pc}  pair for each 
+  /// inlined instance; the die_offset points to the inlined_subroutine die in
+  /// the __debug_info section, and the low_pc is the starting address  for the
+  ///  inlining instance.
+  void EmitDebugInlineInfo() {
+    if (!MainCU)
+      return;
+
+    Asm->SwitchToDataSection(TAI->getDwarfDebugInlineSection());
+    Asm->EOL();
+    EmitDifference("debug_inlined_end", 1,
+                   "debug_inlined_begin", 1, true);
+    Asm->EOL("Length of Debug Inlined Information Entry");
+
+    EmitLabel("debug_inlined_begin", 1);
+
+    Asm->EmitInt16(DWARF_VERSION); Asm->EOL("Dwarf Version");
+    Asm->EmitInt8(TD->getPointerSize()); Asm->EOL("Address Size (in bytes)");
+
+    for (DenseMap<GlobalVariable *, SmallVector<unsigned, 4> >::iterator 
+           I = InlineInfo.begin(), E = InlineInfo.end(); I != E; ++I) {
+      GlobalVariable *GV = I->first;
+      SmallVector<unsigned, 4> &Labels = I->second;
+      DISubprogram SP(GV);
+      std::string Name;
+      std::string LName;
+
+      SP.getLinkageName(LName);
+      SP.getName(Name);
+
+      Asm->EmitString(LName.empty() ? Name : LName);
+      Asm->EOL("MIPS linkage name");
+
+      Asm->EmitString(Name); Asm->EOL("Function name");
+
+      Asm->EmitULEB128Bytes(Labels.size()); Asm->EOL("Inline count");
+
+      for (SmallVector<unsigned, 4>::iterator LI = Labels.begin(),
+             LE = Labels.end(); LI != LE; ++LI) {
+        DIE *SP = MainCU->getDieMapSlotFor(GV);
+        Asm->EmitInt32(SP->getOffset()); Asm->EOL("DIE offset");
+
+        if (TD->getPointerSize() == sizeof(int32_t))
+          O << TAI->getData32bitsDirective();
+        else
+          O << TAI->getData64bitsDirective();
+        PrintLabelName("label", *LI); Asm->EOL("low_pc");
+      }
+    }
+
+    EmitLabel("debug_inlined_end", 1);
+    Asm->EOL();
+  }
+
   /// GetOrCreateSourceID - Look up the source id with the given directory and
   /// source file names. If none currently exists, create a new id and insert it
   /// in the SourceIds map. This can update DirectoryNames and SourceFileNames maps
@@ -3131,6 +3206,9 @@
     // Emit info into a debug macinfo section.
     EmitDebugMacInfo();
 
+    // Emit inline info.
+    EmitDebugInlineInfo();
+
     if (TimePassesIsEnabled)
       DebugTimer->stopTimer();
   }
@@ -3337,6 +3415,20 @@
     return ID;
   }
 
+  /// RecordRegionStart - Indicate the start of a region.
+  unsigned RecordRegionStart(GlobalVariable *V, unsigned ID) {
+    if (TimePassesIsEnabled)
+      DebugTimer->startTimer();
+
+    DbgScope *Scope = getOrCreateScope(V);
+    if (!Scope->getStartLabelID()) Scope->setStartLabelID(ID);
+
+    if (TimePassesIsEnabled)
+      DebugTimer->stopTimer();
+
+    return ID;
+  }
+
   /// RecordRegionEnd - Indicate the end of a region.
   unsigned RecordRegionEnd(GlobalVariable *V) {
     if (TimePassesIsEnabled)
@@ -3377,6 +3469,23 @@
     if (TimePassesIsEnabled)
       DebugTimer->stopTimer();
   }
+
+  //// RecordInlineInfo - Global variable GV is inlined at the location marked
+  //// by LabelID label.
+  void RecordInlineInfo(GlobalVariable *GV, unsigned LabelID) {
+    MMI->RecordUsedDbgLabel(LabelID);
+    DenseMap<GlobalVariable *, SmallVector<unsigned, 4> >::iterator
+      I = InlineInfo.find(GV);
+    if (I == InlineInfo.end()) {
+      SmallVector<unsigned, 4> Labels;
+      Labels.push_back(LabelID);
+      InlineInfo[GV] = Labels;
+      return;
+    }
+
+    SmallVector<unsigned, 4> &Labels = I->second;
+    Labels.push_back(LabelID);
+  }
 };
 
 //===----------------------------------------------------------------------===//
@@ -4532,6 +4641,11 @@
   return DD->RecordRegionStart(V);
 }
 
+/// RecordRegionStart - Indicate the start of a region.
+unsigned DwarfWriter::RecordRegionStart(GlobalVariable *V, unsigned ID) {
+  return DD->RecordRegionStart(V, ID);
+}
+
 /// RecordRegionEnd - Indicate the end of a region.
 unsigned DwarfWriter::RecordRegionEnd(GlobalVariable *V) {
   return DD->RecordRegionEnd(V);
@@ -4553,3 +4667,10 @@
 bool DwarfWriter::ShouldEmitDwarfDebug() const {
   return DD->ShouldEmitDwarfDebug();
 }
+
+//// RecordInlineInfo - Global variable GV is inlined at the location marked
+//// by LabelID label.
+void DwarfWriter::RecordInlineInfo(GlobalVariable *GV, unsigned LabelID) {
+  DD->RecordInlineInfo(GV, LabelID);
+}
+

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=68847&r1=68846&r2=68847&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Fri Apr 10 19:16:47 2009
@@ -372,11 +372,23 @@
 
       // Record the source line.
       unsigned Line = Subprogram.getLineNumber();
-      DW->RecordSourceLine(Line, 0, SrcFile);
+      unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
       setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
 
-      // llvm.dbg.func_start also defines beginning of function scope.
-      DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram()));
+      std::string SPName;
+      Subprogram.getLinkageName(SPName);
+      if (!SPName.empty() 
+          && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
+        // This is a beginning of inlined function.
+        DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram()), 
+                              LabelID);
+        const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
+        BuildMI(MBB, DL, II).addImm(LabelID);
+        DW->RecordInlineInfo(Subprogram.getGV(), LabelID);
+      } else {
+        // llvm.dbg.func_start also defines beginning of function scope.
+        DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram()));
+      }
     }
 
     return true;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=68847&r1=68846&r2=68847&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Fri Apr 10 19:16:47 2009
@@ -3955,6 +3955,18 @@
     DwarfWriter *DW = DAG.getDwarfWriter();
     DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
     if (DW && DW->ValidDebugInfo(REI.getContext())) {
+
+      MachineFunction &MF = DAG.getMachineFunction();
+      DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
+      std::string SPName;
+      Subprogram.getLinkageName(SPName);
+      if (!SPName.empty() 
+          && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
+        // This is end of inlined function. Debugging information for
+        // inlined function is not handled yet (only supported by FastISel).
+        return 0;
+      }
+
       unsigned LabelID =
         DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
       if (Fast)
@@ -3974,6 +3986,16 @@
       // what (most?) gdb expects.
       MachineFunction &MF = DAG.getMachineFunction();
       DISubprogram Subprogram(cast<GlobalVariable>(SP));
+
+      std::string SPName;
+      Subprogram.getLinkageName(SPName);
+      if (!SPName.empty() 
+          && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
+        // This is beginning of inlined function. Debugging information for
+        // inlined function is not handled yet (only supported by FastISel).
+        return 0;
+      }
+
       DICompileUnit CompileUnit = Subprogram.getCompileUnit();
       std::string Dir, FN;
       unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir),

Modified: llvm/trunk/lib/Target/TargetAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetAsmInfo.cpp?rev=68847&r1=68846&r2=68847&view=diff

==============================================================================
--- llvm/trunk/lib/Target/TargetAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetAsmInfo.cpp Fri Apr 10 19:16:47 2009
@@ -112,6 +112,7 @@
   DwarfFrameSection = ".debug_frame";
   DwarfPubNamesSection = ".debug_pubnames";
   DwarfPubTypesSection = ".debug_pubtypes";
+  DwarfDebugInlineSection = ".debug_inlined";
   DwarfStrSection = ".debug_str";
   DwarfLocSection = ".debug_loc";
   DwarfARangesSection = ".debug_aranges";

Modified: llvm/trunk/lib/Target/X86/X86TargetAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetAsmInfo.cpp?rev=68847&r1=68846&r2=68847&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetAsmInfo.cpp Fri Apr 10 19:16:47 2009
@@ -112,6 +112,7 @@
   DwarfFrameSection = ".section __DWARF,__debug_frame,regular,debug";
   DwarfPubNamesSection = ".section __DWARF,__debug_pubnames,regular,debug";
   DwarfPubTypesSection = ".section __DWARF,__debug_pubtypes,regular,debug";
+  DwarfDebugInlineSection = ".section __DWARF,__debug_inlined,regular,debug";
   DwarfStrSection = ".section __DWARF,__debug_str,regular,debug";
   DwarfLocSection = ".section __DWARF,__debug_loc,regular,debug";
   DwarfARangesSection = ".section __DWARF,__debug_aranges,regular,debug";




From dpatel at apple.com  Fri Apr 10 19:17:54 2009
From: dpatel at apple.com (Devang Patel)
Date: Sat, 11 Apr 2009 00:17:54 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r68848 -
	/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp
Message-ID: <200904110017.n3B0HseT009219@zion.cs.uiuc.edu>

Author: dpatel
Date: Fri Apr 10 19:17:54 2009
New Revision: 68848

URL: http://llvm.org/viewvc/llvm-project?rev=68848&view=rev
Log:
If linkage name is not available then use function display name as linkage name.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp?rev=68848&r1=68847&r2=68848&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Fri Apr 10 19:17:54 2009
@@ -190,7 +190,7 @@
       return IDENTIFIER_POINTER(DECL_ASSEMBLER_NAME(Node));
     } 
   }
-  return "";
+  return NULL;
 }
 
 DebugInfo::DebugInfo(Module *m)
@@ -211,12 +211,11 @@
   // Gather location information.
   expanded_location Loc = GetNodeLocation(FnDecl, false);
   const char *LinkageName = getLinkageName(FnDecl);
-
+  const char *FnName = lang_hooks.dwarf_name(FnDecl, 0);
   DISubprogram SP = 
     DebugFactory.CreateSubprogram(findRegion(FnDecl),
-                                  lang_hooks.dwarf_name(FnDecl, 0),
-                                  lang_hooks.dwarf_name(FnDecl, 0),
-                                  LinkageName,
+                                  FnName, FnName,
+                                  LinkageName ? LinkageName : FnName,
                                   getOrCreateCompileUnit(Loc.file), CurLineNo,
                                   getOrCreateType(TREE_TYPE(FnDecl)),
                                   Fn->hasInternalLinkage(),
@@ -345,11 +344,11 @@
     if (IDENTIFIER_POINTER(DECL_NAME(decl)))
       DispName = IDENTIFIER_POINTER(DECL_NAME(decl));
   }
-    
+  const char *LinkageName = getLinkageName(decl);
   DebugFactory.CreateGlobalVariable(getOrCreateCompileUnit(Loc.file), 
                                     GV->getNameStr(), 
                                     DispName,
-                                    getLinkageName(decl), 
+                                    LinkageName ? LinkageName : DispName,
                                     getOrCreateCompileUnit(Loc.file), Loc.line,
                                     TyD, GV->hasInternalLinkage(),
                                     true/*definition*/, GV);
@@ -668,7 +667,7 @@
     DIType SPTy = getOrCreateType(TREE_TYPE(Member));
     DISubprogram SP = 
       DebugFactory.CreateSubprogram(findRegion(Member), MemberName, MemberName,
-                                    LinkageName, 
+                                    LinkageName ? LinkageName : MemberName, 
                                     getOrCreateCompileUnit(MemLoc.file),
                                     MemLoc.line, SPTy, false, false);
     EltTys.push_back(SP);




From kremenek at apple.com  Fri Apr 10 19:56:00 2009
From: kremenek at apple.com (Ted Kremenek)
Date: Sat, 11 Apr 2009 00:56:00 -0000
Subject: [llvm-commits] [llvm] r68850 - /llvm/tags/checker/checker-0.186/
Message-ID: <200904110056.n3B0u0mp010461@zion.cs.uiuc.edu>

Author: kremenek
Date: Fri Apr 10 19:55:59 2009
New Revision: 68850

URL: http://llvm.org/viewvc/llvm-project?rev=68850&view=rev
Log:
Tagging checker-0.186.

Added:
    llvm/tags/checker/checker-0.186/
      - copied from r68849, llvm/trunk/



From kremenek at apple.com  Fri Apr 10 21:27:58 2009
From: kremenek at apple.com (Ted Kremenek)
Date: Sat, 11 Apr 2009 02:27:58 -0000
Subject: [llvm-commits] [llvm] r68855 - /llvm/tags/checker/checker-0.186/
Message-ID: <200904110227.n3B2RwdM013307@zion.cs.uiuc.edu>

Author: kremenek
Date: Fri Apr 10 21:27:58 2009
New Revision: 68855

URL: http://llvm.org/viewvc/llvm-project?rev=68855&view=rev
Log:
Removing checker-0.186.

Removed:
    llvm/tags/checker/checker-0.186/



From kremenek at apple.com  Fri Apr 10 21:35:33 2009
From: kremenek at apple.com (Ted Kremenek)
Date: Sat, 11 Apr 2009 02:35:33 -0000
Subject: [llvm-commits] [llvm] r68858 - /llvm/tags/checker/checker-0.186/
Message-ID: <200904110235.n3B2ZXpX013601@zion.cs.uiuc.edu>

Author: kremenek
Date: Fri Apr 10 21:35:32 2009
New Revision: 68858

URL: http://llvm.org/viewvc/llvm-project?rev=68858&view=rev
Log:
Tagging checker-0.186.

Added:
    llvm/tags/checker/checker-0.186/
      - copied from r68857, llvm/trunk/



From gohman at apple.com  Sat Apr 11 10:57:04 2009
From: gohman at apple.com (Dan Gohman)
Date: Sat, 11 Apr 2009 15:57:04 -0000
Subject: [llvm-commits] [llvm] r68863 - in /llvm/trunk:
 include/llvm/CodeGen/DwarfWriter.h include/llvm/Target/TargetAsmInfo.h
 lib/CodeGen/AsmPrinter/DwarfWriter.cpp
 lib/CodeGen/SelectionDAG/FastISel.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp lib/Target/TargetAsmInfo.cpp
 lib/Target/X86/X86TargetAsmInfo.cpp
Message-ID: <200904111557.n3BFv5sQ019240@zion.cs.uiuc.edu>

Author: djg
Date: Sat Apr 11 10:57:04 2009
New Revision: 68863

URL: http://llvm.org/viewvc/llvm-project?rev=68863&view=rev
Log:
Revert r68847. It breaks the build on non-Darwin targets, with this message
from the assembler:

Error: unknown pseudo-op: `.debug_inlined'

Modified:
    llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
    llvm/trunk/include/llvm/Target/TargetAsmInfo.h
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
    llvm/trunk/lib/Target/TargetAsmInfo.cpp
    llvm/trunk/lib/Target/X86/X86TargetAsmInfo.cpp

Modified: llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DwarfWriter.h?rev=68863&r1=68862&r2=68863&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/DwarfWriter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/DwarfWriter.h Sat Apr 11 10:57:04 2009
@@ -94,9 +94,6 @@
   /// RecordRegionStart - Indicate the start of a region.
   unsigned RecordRegionStart(GlobalVariable *V);
 
-  /// RecordRegionStart - Indicate the start of a region.
-  unsigned RecordRegionStart(GlobalVariable *V, unsigned ID);
-
   /// RecordRegionEnd - Indicate the end of a region.
   unsigned RecordRegionEnd(GlobalVariable *V);
 
@@ -110,10 +107,6 @@
   /// ShouldEmitDwarfDebug - Returns true if Dwarf debugging declarations should
   /// be emitted.
   bool ShouldEmitDwarfDebug() const;
-
-  //// RecordInlineInfo - Global variable GV is inlined at the location marked
-  //// by LabelID label.
-  void RecordInlineInfo(GlobalVariable *GV, unsigned LabelID);
 };
 
 

Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=68863&r1=68862&r2=68863&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Sat Apr 11 10:57:04 2009
@@ -506,11 +506,7 @@
     /// DwarfPubTypesSection - Section directive for Dwarf info.
     ///
     const char *DwarfPubTypesSection; // Defaults to ".debug_pubtypes".
-
-    /// DwarfDebugInlineSection - Section directive for inline info.
-    ///
-    const char *DwarfDebugInlineSection; // Defaults to ".debug_inlined"
-
+    
     /// DwarfStrSection - Section directive for Dwarf info.
     ///
     const char *DwarfStrSection; // Defaults to ".debug_str".
@@ -884,9 +880,6 @@
     const char *getDwarfPubTypesSection() const {
       return DwarfPubTypesSection;
     }
-    const char *getDwarfDebugInlineSection() const {
-      return DwarfDebugInlineSection;
-    }
     const char *getDwarfStrSection() const {
       return DwarfStrSection;
     }

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=68863&r1=68862&r2=68863&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Sat Apr 11 10:57:04 2009
@@ -1252,10 +1252,6 @@
   /// DbgScopeMap - Tracks the scopes in the current function.
   DenseMap<GlobalVariable *, DbgScope *> DbgScopeMap;
 
-  /// InlineInfo - Keep track of inlined functions and their location.
-  /// This information is used to populate debug_inlined section.
-  DenseMap<GlobalVariable *, SmallVector<unsigned, 4> > InlineInfo;
-
   /// DebugTimer - Timer for the Dwarf debug writer.
   Timer *DebugTimer;
   
@@ -2031,18 +2027,15 @@
     for (unsigned j = 0, M = Scopes.size(); j < M; ++j) {
       // Define the Scope debug information entry.
       DbgScope *Scope = Scopes[j];
+      // FIXME - Ignore inlined functions for the time being.
+      if (!Scope->getParent()) continue;
 
       unsigned StartID = MMI->MappedLabel(Scope->getStartLabelID());
       unsigned EndID = MMI->MappedLabel(Scope->getEndLabelID());
 
       // Ignore empty scopes.
       if (StartID == EndID && StartID != 0) continue;
-
-      // Do not ignore inlined scope even if it is empty. Inlined scope 
-      // does not have any parent.
-      if (Scope->getParent() 
-          && Scope->getScopes().empty() && Scope->getVariables().empty()) 
-        continue;
+      if (Scope->getScopes().empty() && Scope->getVariables().empty()) continue;
 
       if (StartID == ParentStartID && EndID == ParentEndID) {
         // Just add stuff to the parent scope.
@@ -2788,74 +2781,6 @@
     }
   }
 
-  /// EmitDebugInlineInfo - Emit inline info using following format.
-  /// Section Header:
-  /// 1. length of section
-  /// 2. Dwarf version number
-  /// 3. address size.
-  ///
-  /// Entries (one "entry" for each function that was inlined):
-  ///
-  /// 1. offset into __debug_str section for MIPS linkage name, if exists; 
-  ///   otherwise offset into __debug_str for regular function name.
-  /// 2. offset into __debug_str section for regular function name.
-  /// 3. an unsigned LEB128 number indicating the number of distinct inlining 
-  /// instances for the function.
-  /// 
-  /// The rest of the entry consists of a {die_offset, low_pc}  pair for each 
-  /// inlined instance; the die_offset points to the inlined_subroutine die in
-  /// the __debug_info section, and the low_pc is the starting address  for the
-  ///  inlining instance.
-  void EmitDebugInlineInfo() {
-    if (!MainCU)
-      return;
-
-    Asm->SwitchToDataSection(TAI->getDwarfDebugInlineSection());
-    Asm->EOL();
-    EmitDifference("debug_inlined_end", 1,
-                   "debug_inlined_begin", 1, true);
-    Asm->EOL("Length of Debug Inlined Information Entry");
-
-    EmitLabel("debug_inlined_begin", 1);
-
-    Asm->EmitInt16(DWARF_VERSION); Asm->EOL("Dwarf Version");
-    Asm->EmitInt8(TD->getPointerSize()); Asm->EOL("Address Size (in bytes)");
-
-    for (DenseMap<GlobalVariable *, SmallVector<unsigned, 4> >::iterator 
-           I = InlineInfo.begin(), E = InlineInfo.end(); I != E; ++I) {
-      GlobalVariable *GV = I->first;
-      SmallVector<unsigned, 4> &Labels = I->second;
-      DISubprogram SP(GV);
-      std::string Name;
-      std::string LName;
-
-      SP.getLinkageName(LName);
-      SP.getName(Name);
-
-      Asm->EmitString(LName.empty() ? Name : LName);
-      Asm->EOL("MIPS linkage name");
-
-      Asm->EmitString(Name); Asm->EOL("Function name");
-
-      Asm->EmitULEB128Bytes(Labels.size()); Asm->EOL("Inline count");
-
-      for (SmallVector<unsigned, 4>::iterator LI = Labels.begin(),
-             LE = Labels.end(); LI != LE; ++LI) {
-        DIE *SP = MainCU->getDieMapSlotFor(GV);
-        Asm->EmitInt32(SP->getOffset()); Asm->EOL("DIE offset");
-
-        if (TD->getPointerSize() == sizeof(int32_t))
-          O << TAI->getData32bitsDirective();
-        else
-          O << TAI->getData64bitsDirective();
-        PrintLabelName("label", *LI); Asm->EOL("low_pc");
-      }
-    }
-
-    EmitLabel("debug_inlined_end", 1);
-    Asm->EOL();
-  }
-
   /// GetOrCreateSourceID - Look up the source id with the given directory and
   /// source file names. If none currently exists, create a new id and insert it
   /// in the SourceIds map. This can update DirectoryNames and SourceFileNames maps
@@ -3206,9 +3131,6 @@
     // Emit info into a debug macinfo section.
     EmitDebugMacInfo();
 
-    // Emit inline info.
-    EmitDebugInlineInfo();
-
     if (TimePassesIsEnabled)
       DebugTimer->stopTimer();
   }
@@ -3415,20 +3337,6 @@
     return ID;
   }
 
-  /// RecordRegionStart - Indicate the start of a region.
-  unsigned RecordRegionStart(GlobalVariable *V, unsigned ID) {
-    if (TimePassesIsEnabled)
-      DebugTimer->startTimer();
-
-    DbgScope *Scope = getOrCreateScope(V);
-    if (!Scope->getStartLabelID()) Scope->setStartLabelID(ID);
-
-    if (TimePassesIsEnabled)
-      DebugTimer->stopTimer();
-
-    return ID;
-  }
-
   /// RecordRegionEnd - Indicate the end of a region.
   unsigned RecordRegionEnd(GlobalVariable *V) {
     if (TimePassesIsEnabled)
@@ -3469,23 +3377,6 @@
     if (TimePassesIsEnabled)
       DebugTimer->stopTimer();
   }
-
-  //// RecordInlineInfo - Global variable GV is inlined at the location marked
-  //// by LabelID label.
-  void RecordInlineInfo(GlobalVariable *GV, unsigned LabelID) {
-    MMI->RecordUsedDbgLabel(LabelID);
-    DenseMap<GlobalVariable *, SmallVector<unsigned, 4> >::iterator
-      I = InlineInfo.find(GV);
-    if (I == InlineInfo.end()) {
-      SmallVector<unsigned, 4> Labels;
-      Labels.push_back(LabelID);
-      InlineInfo[GV] = Labels;
-      return;
-    }
-
-    SmallVector<unsigned, 4> &Labels = I->second;
-    Labels.push_back(LabelID);
-  }
 };
 
 //===----------------------------------------------------------------------===//
@@ -4641,11 +4532,6 @@
   return DD->RecordRegionStart(V);
 }
 
-/// RecordRegionStart - Indicate the start of a region.
-unsigned DwarfWriter::RecordRegionStart(GlobalVariable *V, unsigned ID) {
-  return DD->RecordRegionStart(V, ID);
-}
-
 /// RecordRegionEnd - Indicate the end of a region.
 unsigned DwarfWriter::RecordRegionEnd(GlobalVariable *V) {
   return DD->RecordRegionEnd(V);
@@ -4667,10 +4553,3 @@
 bool DwarfWriter::ShouldEmitDwarfDebug() const {
   return DD->ShouldEmitDwarfDebug();
 }
-
-//// RecordInlineInfo - Global variable GV is inlined at the location marked
-//// by LabelID label.
-void DwarfWriter::RecordInlineInfo(GlobalVariable *GV, unsigned LabelID) {
-  DD->RecordInlineInfo(GV, LabelID);
-}
-

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=68863&r1=68862&r2=68863&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Sat Apr 11 10:57:04 2009
@@ -372,23 +372,11 @@
 
       // Record the source line.
       unsigned Line = Subprogram.getLineNumber();
-      unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
+      DW->RecordSourceLine(Line, 0, SrcFile);
       setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
 
-      std::string SPName;
-      Subprogram.getLinkageName(SPName);
-      if (!SPName.empty() 
-          && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
-        // This is a beginning of inlined function.
-        DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram()), 
-                              LabelID);
-        const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
-        BuildMI(MBB, DL, II).addImm(LabelID);
-        DW->RecordInlineInfo(Subprogram.getGV(), LabelID);
-      } else {
-        // llvm.dbg.func_start also defines beginning of function scope.
-        DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram()));
-      }
+      // llvm.dbg.func_start also defines beginning of function scope.
+      DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram()));
     }
 
     return true;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=68863&r1=68862&r2=68863&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Sat Apr 11 10:57:04 2009
@@ -3955,18 +3955,6 @@
     DwarfWriter *DW = DAG.getDwarfWriter();
     DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
     if (DW && DW->ValidDebugInfo(REI.getContext())) {
-
-      MachineFunction &MF = DAG.getMachineFunction();
-      DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
-      std::string SPName;
-      Subprogram.getLinkageName(SPName);
-      if (!SPName.empty() 
-          && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
-        // This is end of inlined function. Debugging information for
-        // inlined function is not handled yet (only supported by FastISel).
-        return 0;
-      }
-
       unsigned LabelID =
         DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
       if (Fast)
@@ -3986,16 +3974,6 @@
       // what (most?) gdb expects.
       MachineFunction &MF = DAG.getMachineFunction();
       DISubprogram Subprogram(cast<GlobalVariable>(SP));
-
-      std::string SPName;
-      Subprogram.getLinkageName(SPName);
-      if (!SPName.empty() 
-          && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
-        // This is beginning of inlined function. Debugging information for
-        // inlined function is not handled yet (only supported by FastISel).
-        return 0;
-      }
-
       DICompileUnit CompileUnit = Subprogram.getCompileUnit();
       std::string Dir, FN;
       unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir),

Modified: llvm/trunk/lib/Target/TargetAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetAsmInfo.cpp?rev=68863&r1=68862&r2=68863&view=diff

==============================================================================
--- llvm/trunk/lib/Target/TargetAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetAsmInfo.cpp Sat Apr 11 10:57:04 2009
@@ -112,7 +112,6 @@
   DwarfFrameSection = ".debug_frame";
   DwarfPubNamesSection = ".debug_pubnames";
   DwarfPubTypesSection = ".debug_pubtypes";
-  DwarfDebugInlineSection = ".debug_inlined";
   DwarfStrSection = ".debug_str";
   DwarfLocSection = ".debug_loc";
   DwarfARangesSection = ".debug_aranges";

Modified: llvm/trunk/lib/Target/X86/X86TargetAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetAsmInfo.cpp?rev=68863&r1=68862&r2=68863&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetAsmInfo.cpp Sat Apr 11 10:57:04 2009
@@ -112,7 +112,6 @@
   DwarfFrameSection = ".section __DWARF,__debug_frame,regular,debug";
   DwarfPubNamesSection = ".section __DWARF,__debug_pubnames,regular,debug";
   DwarfPubTypesSection = ".section __DWARF,__debug_pubtypes,regular,debug";
-  DwarfDebugInlineSection = ".section __DWARF,__debug_inlined,regular,debug";
   DwarfStrSection = ".section __DWARF,__debug_str,regular,debug";
   DwarfLocSection = ".section __DWARF,__debug_loc,regular,debug";
   DwarfARangesSection = ".section __DWARF,__debug_aranges,regular,debug";




From benny.kra at googlemail.com  Sat Apr 11 09:17:11 2009
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Sat, 11 Apr 2009 16:17:11 +0200
Subject: [llvm-commits] [PATCH] implement strncat and strncpy optimizations
Message-ID: <4A593B86-7D53-4BD5-A126-3FD0BDEB5265@gmail.com>

This patch adds optimizations for the library functions strncpy and  
strncat to the simplify-libcalls pass.

The strcat and strncat opts share some code. I've implemented this by  
putting the common code in a method of StrCatOpt and made StrNCatOpt a  
subclass of StrCatOpt.

I've also factored out EmitMemSet from MemSetOpt so it can be reused  
by the strncpy opt.

  lib/Transforms/Scalar/SimplifyLibCalls.cpp  |  136 ++++++++++++++++++ 
+++++-----
  test/Transforms/SimplifyLibCalls/StrNCat.ll |   27 +++++
  test/Transforms/SimplifyLibCalls/StrNCpy.ll |   25 +++++
  3 files changed, 166 insertions(+), 22 deletions(-)

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From sabre at nondot.org  Sun Apr 12 00:06:41 2009
From: sabre at nondot.org (Chris Lattner)
Date: Sun, 12 Apr 2009 05:06:41 -0000
Subject: [llvm-commits] [llvm] r68885 - in /llvm/trunk:
 lib/Transforms/Scalar/SimplifyLibCalls.cpp
 test/Transforms/SimplifyLibCalls/StrNCat.ll
 test/Transforms/SimplifyLibCalls/StrNCpy.ll
Message-ID: <200904120506.n3C56f3X013493@zion.cs.uiuc.edu>

Author: lattner
Date: Sun Apr 12 00:06:39 2009
New Revision: 68885

URL: http://llvm.org/viewvc/llvm-project?rev=68885&view=rev
Log:
add some optimizations for strncpy/strncat and factor some
code.  Patch by Benjamin Kramer!


Added:
    llvm/trunk/test/Transforms/SimplifyLibCalls/StrNCat.ll
    llvm/trunk/test/Transforms/SimplifyLibCalls/StrNCpy.ll
Modified:
    llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=68885&r1=68884&r2=68885&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Sun Apr 12 00:06:39 2009
@@ -85,6 +85,9 @@
   /// EmitMemCmp - Emit a call to the memcmp function.
   Value *EmitMemCmp(Value *Ptr1, Value *Ptr2, Value *Len, IRBuilder<> &B);
 
+  /// EmitMemSet - Emit a call to the memset function
+  Value *EmitMemSet(Value *Dst, Value *Val, Value *Len, IRBuilder<> &B);
+
   /// EmitUnaryFloatFnCall - Emit a call to the unary function named 'Name' (e.g.
   /// 'floor').  This function is known to take a single of type matching 'Op'
   /// and returns one value with the same type.  If 'Op' is a long double, 'l'
@@ -183,6 +186,18 @@
                        Len, "memcmp");
 }
 
+/// EmitMemSet - Emit a call to the memset function
+Value *LibCallOptimization::EmitMemSet(Value *Dst, Value *Val,
+                                       Value *Len, IRBuilder<> &B) {
+ Module *M = Caller->getParent();
+ Intrinsic::ID IID = Intrinsic::memset;
+ const Type *Tys[1];
+ Tys[0] = Len->getType();
+ Value *MemSet = Intrinsic::getDeclaration(M, IID, Tys, 1);
+ Value *Align = ConstantInt::get(Type::Int32Ty, 1);
+ return B.CreateCall4(MemSet, CastToCStr(Dst, B), Val, Len, Align);
+}
+
 /// EmitUnaryFloatFnCall - Emit a call to the unary function named 'Name' (e.g.
 /// 'floor').  This function is known to take a single of type matching 'Op' and
 /// returns one value with the same type.  If 'Op' is a long double, 'l' is
@@ -507,6 +522,11 @@
     if (Len == 0)
       return Dst;
     
+    EmitStrLenMemCpy(Src, Dst, Len, B);
+    return Dst;
+  }
+
+  void EmitStrLenMemCpy(Value *Src, Value *Dst, uint64_t Len, IRBuilder<> &B) {
     // We need to find the end of the destination string.  That's where the
     // memory is to be moved to. We just generate a call to strlen.
     Value *DstLen = EmitStrLen(Dst, B);
@@ -519,6 +539,50 @@
     // We have enough information to now generate the memcpy call to do the
     // concatenation for us.  Make a memcpy to copy the nul byte with align = 1.
     EmitMemCpy(CpyDst, Src, ConstantInt::get(TD->getIntPtrType(), Len+1), 1, B);
+  }
+};
+
+//===---------------------------------------===//
+// 'strncat' Optimizations
+
+struct VISIBILITY_HIDDEN StrNCatOpt : public StrCatOpt {
+  virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
+    // Verify the "strncat" function prototype.
+    const FunctionType *FT = Callee->getFunctionType();
+    if (FT->getNumParams() != 3 ||
+        FT->getReturnType() != PointerType::getUnqual(Type::Int8Ty) ||
+        FT->getParamType(0) != FT->getReturnType() ||
+        FT->getParamType(1) != FT->getReturnType() ||
+        !isa<IntegerType>(FT->getParamType(2)))
+      return 0;
+
+    // Extract some information from the instruction
+    Value *Dst = CI->getOperand(1);
+    Value *Src = CI->getOperand(2);
+    uint64_t Len;
+
+    // We don't do anything if length is not constant
+    if (ConstantInt *LengthArg = dyn_cast<ConstantInt>(CI->getOperand(3)))
+      Len = LengthArg->getZExtValue();
+    else
+      return 0;
+
+    // See if we can get the length of the input string.
+    uint64_t SrcLen = GetStringLength(Src);
+    if (SrcLen == 0) return 0;
+    --SrcLen;  // Unbias length.
+
+    // Handle the simple, do-nothing cases:
+    // strncat(x, "", c) -> x
+    // strncat(x,  c, 0) -> x
+    if (SrcLen == 0 || Len == 0) return Dst;
+
+    // We don't optimize this case
+    if (Len < SrcLen) return 0;
+
+    // strncat(x, s, c) -> strcat(x, s)
+    // s is constant so the strcat can be optimized further
+    EmitStrLenMemCpy(Src, Dst, Len, B);
     return Dst;
   }
 };
@@ -694,7 +758,50 @@
   }
 };
 
+//===---------------------------------------===//
+// 'strncpy' Optimizations
+
+struct VISIBILITY_HIDDEN StrNCpyOpt : public LibCallOptimization {
+  virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
+    const FunctionType *FT = Callee->getFunctionType();
+    if (FT->getNumParams() != 3 || FT->getReturnType() != FT->getParamType(0) ||
+        FT->getParamType(0) != FT->getParamType(1) ||
+        FT->getParamType(0) != PointerType::getUnqual(Type::Int8Ty) ||
+        !isa<IntegerType>(FT->getParamType(2)))
+      return 0;
+
+    Value *Dst = CI->getOperand(1);
+    Value *Src = CI->getOperand(2);
+    Value *LenOp = CI->getOperand(3);
+
+    // See if we can get the length of the input string.
+    uint64_t SrcLen = GetStringLength(Src);
+    if (SrcLen == 0) return 0;
+    --SrcLen;
+
+    if (SrcLen == 0) {
+      // strncpy(x, "", y) -> memset(x, '\0', y, 1)
+      EmitMemSet(Dst, ConstantInt::get(Type::Int8Ty, '\0'), LenOp, B);
+      return Dst;
+    }
+
+    uint64_t Len;
+    if (ConstantInt *LengthArg = dyn_cast<ConstantInt>(LenOp))
+      Len = LengthArg->getZExtValue();
+    else
+      return 0;
 
+    if (Len == 0) return Dst; // strncpy(x, y, 0) -> x
+
+    // Let strncpy handle the zero padding
+    if (Len > SrcLen+1) return 0;
+
+    // strncpy(x, s, c) -> memcpy(x, s, c, 1) [s and c are constant]
+    EmitMemCpy(Dst, Src, ConstantInt::get(TD->getIntPtrType(), Len), 1, B);
+
+    return Dst;
+  }
+};
 
 //===---------------------------------------===//
 // 'strlen' Optimizations
@@ -849,16 +956,8 @@
       return 0;
 
     // memset(p, v, n) -> llvm.memset(p, v, n, 1)
-    Module *M = Caller->getParent();
-    Intrinsic::ID IID = Intrinsic::memset;
-    const Type *Tys[1];
-    Tys[0] = TD->getIntPtrType();
-    Value *MemSet = Intrinsic::getDeclaration(M, IID, Tys, 1);
-    Value *Dst = CastToCStr(CI->getOperand(1), B);
     Value *Val = B.CreateTrunc(CI->getOperand(2), Type::Int8Ty);
-    Value *Size = CI->getOperand(3);
-    Value *Align = ConstantInt::get(Type::Int32Ty, 1);
-    B.CreateCall4(MemSet, Dst, Val, Size, Align);
+    EmitMemSet(CI->getOperand(1), Val,  CI->getOperand(3), B);
     return CI->getOperand(1);
   }
 };
@@ -1351,9 +1450,10 @@
     // Miscellaneous LibCall Optimizations
     ExitOpt Exit; 
     // String and Memory LibCall Optimizations
-    StrCatOpt StrCat; StrChrOpt StrChr; StrCmpOpt StrCmp; StrNCmpOpt StrNCmp;
-    StrCpyOpt StrCpy; StrLenOpt StrLen; StrToOpt StrTo; MemCmpOpt MemCmp;
-    MemCpyOpt MemCpy; MemMoveOpt MemMove; MemSetOpt MemSet;
+    StrCatOpt StrCat; StrNCatOpt StrNCat; StrChrOpt StrChr; StrCmpOpt StrCmp;
+    StrNCmpOpt StrNCmp; StrCpyOpt StrCpy; StrNCpyOpt StrNCpy; StrLenOpt StrLen;
+    StrToOpt StrTo; MemCmpOpt MemCmp; MemCpyOpt MemCpy; MemMoveOpt MemMove;
+    MemSetOpt MemSet;
     // Math Library Optimizations
     PowOpt Pow; Exp2Opt Exp2; UnaryDoubleFPOpt UnaryDoubleFP;
     // Integer Optimizations
@@ -1401,10 +1501,12 @@
   
   // String and Memory LibCall Optimizations
   Optimizations["strcat"] = &StrCat;
+  Optimizations["strncat"] = &StrNCat;
   Optimizations["strchr"] = &StrChr;
   Optimizations["strcmp"] = &StrCmp;
   Optimizations["strncmp"] = &StrNCmp;
   Optimizations["strcpy"] = &StrCpy;
+  Optimizations["strncpy"] = &StrNCpy;
   Optimizations["strlen"] = &StrLen;
   Optimizations["strtol"] = &StrTo;
   Optimizations["strtod"] = &StrTo;
@@ -2299,16 +2401,6 @@
 //      (if c is a constant integer and s is a constant string)
 //   * strrchr(s1,0) -> strchr(s1,0)
 //
-// strncat:
-//   * strncat(x,y,0) -> x
-//   * strncat(x,y,0) -> x (if strlen(y) = 0)
-//   * strncat(x,y,l) -> strcat(x,y) (if y and l are constants an l > strlen(y))
-//
-// strncpy:
-//   * strncpy(d,s,0) -> d
-//   * strncpy(d,s,l) -> memcpy(d,s,l,1)
-//      (if s and l are constants)
-//
 // strpbrk:
 //   * strpbrk(s,a) -> offset_in_for(s,a)
 //      (if s and a are both constant strings)

Added: llvm/trunk/test/Transforms/SimplifyLibCalls/StrNCat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/StrNCat.ll?rev=68885&view=auto

==============================================================================
--- llvm/trunk/test/Transforms/SimplifyLibCalls/StrNCat.ll (added)
+++ llvm/trunk/test/Transforms/SimplifyLibCalls/StrNCat.ll Sun Apr 12 00:06:39 2009
@@ -0,0 +1,27 @@
+; Test that the StrNCatOptimizer works correctly
+; RUN: llvm-as < %s | opt -simplify-libcalls | llvm-dis | \
+; RUN:   not grep {call.*strncat}
+; RUN: llvm-as < %s | opt -simplify-libcalls | llvm-dis | \
+; RUN:   grep {puts.*%arg1}
+
+ at hello = constant [6 x i8] c"hello\00"		; <[6 x i8]*> [#uses=1]
+ at null = constant [1 x i8] zeroinitializer		; <[1 x i8]*> [#uses=1]
+ at null_hello = constant [7 x i8] c"\00hello\00"		; <[7 x i8]*> [#uses=1]
+
+declare i8* @strncat(i8*, i8*, i32)
+
+declare i32 @puts(i8*)
+
+define i32 @main() {
+	%target = alloca [1024 x i8]		; <[1024 x i8]*> [#uses=1]
+	%arg1 = getelementptr [1024 x i8]* %target, i32 0, i32 0		; <i8*> [#uses=2]
+	store i8 0, i8* %arg1
+	%arg2 = getelementptr [6 x i8]* @hello, i32 0, i32 0		; <i8*> [#uses=1]
+	%rslt1 = call i8* @strncat( i8* %arg1, i8* %arg2, i32 6 )		; <i8*> [#uses=1]
+	%arg3 = getelementptr [1 x i8]* @null, i32 0, i32 0		; <i8*> [#uses=1]
+	%rslt2 = call i8* @strncat( i8* %rslt1, i8* %arg3, i32 42 )		; <i8*> [#uses=1]
+	%arg4 = getelementptr [7 x i8]* @null_hello, i32 0, i32 0		; <i8*> [#uses=1]
+	%rslt3 = call i8* @strncat( i8* %rslt2, i8* %arg4, i32 42 )		; <i8*> [#uses=1]
+	call i32 @puts( i8* %rslt3 )		; <i32>:1 [#uses=0]
+	ret i32 0
+}

Added: llvm/trunk/test/Transforms/SimplifyLibCalls/StrNCpy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/StrNCpy.ll?rev=68885&view=auto

==============================================================================
--- llvm/trunk/test/Transforms/SimplifyLibCalls/StrNCpy.ll (added)
+++ llvm/trunk/test/Transforms/SimplifyLibCalls/StrNCpy.ll Sun Apr 12 00:06:39 2009
@@ -0,0 +1,25 @@
+; Test that the StrNCpyOptimizer works correctly
+; RUN: llvm-as < %s | opt -simplify-libcalls | llvm-dis | \
+; RUN:   not grep {call.*strncpy}
+
+ at hello = constant [6 x i8] c"hello\00"		; <[6 x i8]*> [#uses=1]
+ at null = constant [1 x i8] zeroinitializer		; <[1 x i8]*> [#uses=1]
+ at null_hello = constant [7 x i8] c"\00hello\00"		; <[7 x i8]*> [#uses=1]
+
+declare i8* @strncpy(i8*, i8*, i32)
+
+declare i32 @puts(i8*)
+
+define i32 @main() {
+	%target = alloca [1024 x i8]		; <[1024 x i8]*> [#uses=1]
+	%arg1 = getelementptr [1024 x i8]* %target, i32 0, i32 0		; <i8*> [#uses=2]
+	store i8 0, i8* %arg1
+	%arg2 = getelementptr [6 x i8]* @hello, i32 0, i32 0		; <i8*> [#uses=1]
+	%rslt1 = call i8* @strncpy( i8* %arg1, i8* %arg2, i32 6 )		; <i8*> [#uses=1]
+	%arg3 = getelementptr [1 x i8]* @null, i32 0, i32 0		; <i8*> [#uses=1]
+	%rslt2 = call i8* @strncpy( i8* %rslt1, i8* %arg3, i32 42 )		; <i8*> [#uses=1]
+	%arg4 = getelementptr [7 x i8]* @null_hello, i32 0, i32 0		; <i8*> [#uses=1]
+	%rslt3 = call i8* @strncpy( i8* %rslt2, i8* %arg4, i32 42 )		; <i8*> [#uses=1]
+	call i32 @puts( i8* %rslt3 )		; <i32>:1 [#uses=0]
+	ret i32 0
+}




From clattner at apple.com  Sun Apr 12 00:07:32 2009
From: clattner at apple.com (Chris Lattner)
Date: Sat, 11 Apr 2009 22:07:32 -0700
Subject: [llvm-commits] [PATCH] implement strncat and strncpy
	optimizations
In-Reply-To: <4A593B86-7D53-4BD5-A126-3FD0BDEB5265@gmail.com>
References: <4A593B86-7D53-4BD5-A126-3FD0BDEB5265@gmail.com>
Message-ID: <F050600E-9346-4B10-B065-015E1367340A@apple.com>


On Apr 11, 2009, at 7:17 AM, Benjamin Kramer wrote:

> This patch adds optimizations for the library functions strncpy and  
> strncat to the simplify-libcalls pass.
>
> The strcat and strncat opts share some code. I've implemented this  
> by putting the common code in a method of StrCatOpt and made  
> StrNCatOpt a subclass of StrCatOpt.
>
> I've also factored out EmitMemSet from MemSetOpt so it can be reused  
> by the strncpy opt.

Beautiful!  Applied here:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090406/076220.html

-Chris


From sabre at nondot.org  Sun Apr 12 02:26:53 2009
From: sabre at nondot.org (Chris Lattner)
Date: Sun, 12 Apr 2009 07:26:53 -0000
Subject: [llvm-commits] [llvm] r68886 - in /llvm/trunk:
 include/llvm/Target/TargetInstrDesc.h lib/Target/X86/X86FastISel.cpp
Message-ID: <200904120726.n3C7QrdV017743@zion.cs.uiuc.edu>

Author: lattner
Date: Sun Apr 12 02:26:51 2009
New Revision: 68886

URL: http://llvm.org/viewvc/llvm-project?rev=68886&view=rev
Log:
Add new TargetInstrDesc::hasImplicitUseOfPhysReg and
hasImplicitDefOfPhysReg methods.  Use them to remove a 
look in X86 fast isel.

Modified:
    llvm/trunk/include/llvm/Target/TargetInstrDesc.h
    llvm/trunk/lib/Target/X86/X86FastISel.cpp

Modified: llvm/trunk/include/llvm/Target/TargetInstrDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrDesc.h?rev=68886&r1=68885&r2=68886&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrDesc.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrDesc.h Sun Apr 12 02:26:51 2009
@@ -199,6 +199,24 @@
   const unsigned *getImplicitDefs() const {
     return ImplicitDefs;
   }
+  
+  /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
+  /// uses the specified physical register.
+  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
+    if (const unsigned *ImpUses = ImplicitUses)
+      for (; *ImpUses; ++ImpUses)
+        if (*ImpUses == Reg) return true;
+    return false;
+  }
+  
+  /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
+  /// defines the specified physical register.
+  bool hasImplicitDefOfPhysReg(unsigned Reg) const {
+    if (const unsigned *ImpDefs = ImplicitDefs)
+      for (; *ImpDefs; ++ImpDefs)
+        if (*ImpDefs == Reg) return true;
+    return false;
+  }
 
   /// getRegClassBarriers - Return a list of register classes that are
   /// completely clobbered by this machine instruction. For example, on X86

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=68886&r1=68885&r2=68886&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Sun Apr 12 02:26:51 2009
@@ -808,21 +808,9 @@
             }
 
             const TargetInstrDesc &TID = MI.getDesc();
-            const unsigned *ImpDefs = TID.getImplicitDefs();
-
-            if (TID.hasUnmodeledSideEffects()) break;
-
-            bool ModifiesEFlags = false;
-
-            if (ImpDefs) {
-              for (unsigned u = 0; ImpDefs[u]; ++u)
-                if (ImpDefs[u] == X86::EFLAGS) {
-                  ModifiesEFlags = true;
-                  break;
-                }
-            }
-
-            if (ModifiesEFlags) break;
+            if (TID.hasUnmodeledSideEffects() ||
+                TID.hasImplicitDefOfPhysReg(X86::EFLAGS))
+              break;
           }
 
           if (SetMI) {




From sabre at nondot.org  Sun Apr 12 02:36:02 2009
From: sabre at nondot.org (Chris Lattner)
Date: Sun, 12 Apr 2009 07:36:02 -0000
Subject: [llvm-commits] [llvm] r68887 -
	/llvm/trunk/lib/Target/X86/X86FastISel.cpp
Message-ID: <200904120736.n3C7a2nJ018169@zion.cs.uiuc.edu>

Author: lattner
Date: Sun Apr 12 02:36:01 2009
New Revision: 68887

URL: http://llvm.org/viewvc/llvm-project?rev=68887&view=rev
Log:
simplify code by using IntrinsicInst.

Modified:
    llvm/trunk/lib/Target/X86/X86FastISel.cpp

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=68887&r1=68886&r2=68887&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Sun Apr 12 02:36:01 2009
@@ -23,7 +23,7 @@
 #include "llvm/DerivedTypes.h"
 #include "llvm/GlobalVariable.h"
 #include "llvm/Instructions.h"
-#include "llvm/Intrinsics.h"
+#include "llvm/IntrinsicInst.h"
 #include "llvm/CodeGen/FastISel.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
@@ -112,7 +112,7 @@
 
   bool X86SelectExtractValue(Instruction *I);
 
-  bool X86VisitIntrinsicCall(CallInst &I, unsigned Intrinsic);
+  bool X86VisitIntrinsicCall(IntrinsicInst &I);
   bool X86SelectCall(Instruction *I);
 
   CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false);
@@ -777,55 +777,45 @@
     // looking for the SETO/SETB instruction. If an instruction modifies the
     // EFLAGS register before we reach the SETO/SETB instruction, then we can't
     // convert the branch into a JO/JB instruction.
-
-    Value *Agg = EI->getAggregateOperand();
-
-    if (CallInst *CI = dyn_cast<CallInst>(Agg)) {
-      Function *F = CI->getCalledFunction();
-
-      if (F && F->isDeclaration()) {
-        switch (F->getIntrinsicID()) {
-        default: break;
-        case Intrinsic::sadd_with_overflow:
-        case Intrinsic::uadd_with_overflow: {
-          const MachineInstr *SetMI = 0;
-          unsigned Reg = lookUpRegForValue(EI);
-
-          for (MachineBasicBlock::const_reverse_iterator
-                 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
-            const MachineInstr &MI = *RI;
-
-            if (MI.modifiesRegister(Reg)) {
-              unsigned Src, Dst, SrcSR, DstSR;
-
-              if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) {
-                Reg = Src;
-                continue;
-              }
-
-              SetMI = &MI;
-              break;
+    if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){
+      if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow ||
+          CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) {
+        const MachineInstr *SetMI = 0;
+        unsigned Reg = lookUpRegForValue(EI);
+
+        for (MachineBasicBlock::const_reverse_iterator
+               RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
+          const MachineInstr &MI = *RI;
+
+          if (MI.modifiesRegister(Reg)) {
+            unsigned Src, Dst, SrcSR, DstSR;
+
+            if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) {
+              Reg = Src;
+              continue;
             }
 
-            const TargetInstrDesc &TID = MI.getDesc();
-            if (TID.hasUnmodeledSideEffects() ||
-                TID.hasImplicitDefOfPhysReg(X86::EFLAGS))
-              break;
+            SetMI = &MI;
+            break;
           }
 
-          if (SetMI) {
-            unsigned OpCode = SetMI->getOpcode();
+          const TargetInstrDesc &TID = MI.getDesc();
+          if (TID.hasUnmodeledSideEffects() ||
+              TID.hasImplicitDefOfPhysReg(X86::EFLAGS))
+            break;
+        }
 
-            if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
-              BuildMI(MBB, DL, TII.get((OpCode == X86::SETOr) ? 
-                                   X86::JO : X86::JB)).addMBB(TrueMBB);
-              FastEmitBranch(FalseMBB);
-              MBB->addSuccessor(TrueMBB);
-              return true;
-            }
+        if (SetMI) {
+          unsigned OpCode = SetMI->getOpcode();
+
+          if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
+            BuildMI(MBB, DL, TII.get((OpCode == X86::SETOr) ? 
+                                 X86::JO : X86::JB)).addMBB(TrueMBB);
+            FastEmitBranch(FalseMBB);
+            MBB->addSuccessor(TrueMBB);
+            return true;
           }
         }
-        }
       }
     }
   }
@@ -1027,30 +1017,26 @@
   ExtractValueInst *EI = cast<ExtractValueInst>(I);
   Value *Agg = EI->getAggregateOperand();
 
-  if (CallInst *CI = dyn_cast<CallInst>(Agg)) {
-    Function *F = CI->getCalledFunction();
-
-    if (F && F->isDeclaration()) {
-      switch (F->getIntrinsicID()) {
-      default: break;
-      case Intrinsic::sadd_with_overflow:
-      case Intrinsic::uadd_with_overflow:
-        // Cheat a little. We know that the registers for "add" and "seto" are
-        // allocated sequentially. However, we only keep track of the register
-        // for "add" in the value map. Use extractvalue's index to get the
-        // correct register for "seto".
-        UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
-        return true;
-      }
+  if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) {
+    switch (CI->getIntrinsicID()) {
+    default: break;
+    case Intrinsic::sadd_with_overflow:
+    case Intrinsic::uadd_with_overflow:
+      // Cheat a little. We know that the registers for "add" and "seto" are
+      // allocated sequentially. However, we only keep track of the register
+      // for "add" in the value map. Use extractvalue's index to get the
+      // correct register for "seto".
+      UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
+      return true;
     }
   }
 
   return false;
 }
 
-bool X86FastISel::X86VisitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
+bool X86FastISel::X86VisitIntrinsicCall(IntrinsicInst &I) {
   // FIXME: Handle more intrinsics.
-  switch (Intrinsic) {
+  switch (I.getIntrinsicID()) {
   default: return false;
   case Intrinsic::sadd_with_overflow:
   case Intrinsic::uadd_with_overflow: {
@@ -1059,11 +1045,11 @@
     // instructions are encountered, we use the fact that two registers were
     // created sequentially to get the correct registers for the "sum" and the
     // "overflow bit".
-    MVT VT;
     const Function *Callee = I.getCalledFunction();
     const Type *RetTy =
       cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
 
+    MVT VT;
     if (!isTypeLegal(RetTy, VT))
       return false;
 
@@ -1077,7 +1063,6 @@
       return false;
 
     unsigned OpC = 0;
-
     if (VT == MVT::i32)
       OpC = X86::ADD32rr;
     else if (VT == MVT::i64)
@@ -1090,8 +1075,10 @@
     UpdateValueMap(&I, ResultReg);
 
     ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
-    BuildMI(MBB, DL, TII.get((Intrinsic == Intrinsic::sadd_with_overflow) ?
-                         X86::SETOr : X86::SETBr), ResultReg);
+    unsigned Opc = X86::SETBr;
+    if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
+      Opc = X86::SETOr;
+    BuildMI(MBB, DL, TII.get(Opc), ResultReg);
     return true;
   }
   }
@@ -1106,10 +1093,8 @@
     return false;
 
   // Handle intrinsic calls.
-  if (Function *F = CI->getCalledFunction())
-    if (F->isDeclaration())
-      if (unsigned IID = F->getIntrinsicID())
-        return X86VisitIntrinsicCall(*CI, IID);
+  if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI))
+    return X86VisitIntrinsicCall(*II);
 
   // Handle only C and fastcc calling conventions for now.
   CallSite CS(CI);




From sabre at nondot.org  Sun Apr 12 02:45:02 2009
From: sabre at nondot.org (Chris Lattner)
Date: Sun, 12 Apr 2009 07:45:02 -0000
Subject: [llvm-commits] [llvm] r68888 - in /llvm/trunk:
 include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200904120745.n3C7j3kZ019569@zion.cs.uiuc.edu>

Author: lattner
Date: Sun Apr 12 02:45:01 2009
New Revision: 68888

URL: http://llvm.org/viewvc/llvm-project?rev=68888&view=rev
Log:
optimize FastISel::UpdateValueMap to avoid duplicate map lookups,
and make it return the assigned register.

Modified:
    llvm/trunk/include/llvm/CodeGen/FastISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=68888&r1=68887&r2=68888&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Sun Apr 12 02:45:01 2009
@@ -279,7 +279,7 @@
   /// the CFG.
   void FastEmitBranch(MachineBasicBlock *MBB);
 
-  void UpdateValueMap(Value* I, unsigned Reg);
+  unsigned UpdateValueMap(Value* I, unsigned Reg);
 
   unsigned createResultReg(const TargetRegisterClass *RC);
   

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=68888&r1=68887&r2=68888&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Sun Apr 12 02:45:01 2009
@@ -149,16 +149,21 @@
 /// NOTE: This is only necessary because we might select a block that uses
 /// a value before we select the block that defines the value.  It might be
 /// possible to fix this by selecting blocks in reverse postorder.
-void FastISel::UpdateValueMap(Value* I, unsigned Reg) {
+unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
   if (!isa<Instruction>(I)) {
     LocalValueMap[I] = Reg;
-    return;
+    return Reg;
   }
-  if (!ValueMap.count(I))
-    ValueMap[I] = Reg;
-  else
-    TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I],
-                     Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
+  
+  unsigned &AssignedReg = ValueMap[I];
+  if (AssignedReg == 0)
+    AssignedReg = Reg;
+  else {
+    const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
+    TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
+                     Reg, RegClass, RegClass);
+  }
+  return AssignedReg;
 }
 
 unsigned FastISel::getRegForGEPIndex(Value *Idx) {




From sabre at nondot.org  Sun Apr 12 02:46:30 2009
From: sabre at nondot.org (Chris Lattner)
Date: Sun, 12 Apr 2009 07:46:30 -0000
Subject: [llvm-commits] [llvm] r68889 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <200904120746.n3C7kVQh019838@zion.cs.uiuc.edu>

Author: lattner
Date: Sun Apr 12 02:46:30 2009
New Revision: 68889

URL: http://llvm.org/viewvc/llvm-project?rev=68889&view=rev
Log:
make UpdateValueMap handle the possiblity that we could be
copying into the right register, avoiding a copy.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=68889&r1=68888&r2=68889&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Sun Apr 12 02:46:30 2009
@@ -158,7 +158,7 @@
   unsigned &AssignedReg = ValueMap[I];
   if (AssignedReg == 0)
     AssignedReg = Reg;
-  else {
+  else if (Reg != AssignedReg) {
     const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
     TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
                      Reg, RegClass, RegClass);




From sabre at nondot.org  Sun Apr 12 02:51:15 2009
From: sabre at nondot.org (Chris Lattner)
Date: Sun, 12 Apr 2009 07:51:15 -0000
Subject: [llvm-commits] [llvm] r68890 - in /llvm/trunk:
 lib/Target/X86/X86FastISel.cpp
 test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
Message-ID: <200904120751.n3C7pFS8021112@zion.cs.uiuc.edu>

Author: lattner
Date: Sun Apr 12 02:51:14 2009
New Revision: 68890

URL: http://llvm.org/viewvc/llvm-project?rev=68890&view=rev
Log:
fix a cross-block fastisel crash handling overflow intrinsics.
See comment for details.  This fixes rdar://6772169

Added:
    llvm/trunk/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
Modified:
    llvm/trunk/lib/Target/X86/X86FastISel.cpp

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=68890&r1=68889&r2=68890&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Sun Apr 12 02:51:14 2009
@@ -809,8 +809,8 @@
           unsigned OpCode = SetMI->getOpcode();
 
           if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
-            BuildMI(MBB, DL, TII.get((OpCode == X86::SETOr) ? 
-                                 X86::JO : X86::JB)).addMBB(TrueMBB);
+            BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ? X86::JO : X86::JB))
+              .addMBB(TrueMBB);
             FastEmitBranch(FalseMBB);
             MBB->addSuccessor(TrueMBB);
             return true;
@@ -1072,9 +1072,20 @@
 
     unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
     BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
-    UpdateValueMap(&I, ResultReg);
+    unsigned DestReg1 = UpdateValueMap(&I, ResultReg);
 
-    ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
+    // If the add with overflow is an intra-block value then we just want to
+    // create temporaries for it like normal.  If it is a cross-block value then
+    // UpdateValueMap will return the cross-block register used.  Since we
+    // *really* want the value to be live in the register pair known by
+    // UpdateValueMap, we have to use DestReg1+1 as the destination register in
+    // the cross block case.  In the non-cross-block case, we should just make
+    // another register for the value.
+    if (DestReg1 != ResultReg)
+      ResultReg = DestReg1+1;
+    else
+      ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
+    
     unsigned Opc = X86::SETBr;
     if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
       Opc = X86::SETOr;

Added: llvm/trunk/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll?rev=68890&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll Sun Apr 12 02:51:14 2009
@@ -0,0 +1,21 @@
+; RUN: llvm-as < %s | llc -fast-isel
+; radr://6772169
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin10"
+	type { i32, i1 }		; type %0
+
+declare %0 @llvm.sadd.with.overflow.i32(i32, i32) nounwind
+
+define fastcc i32 @test() nounwind {
+entry:
+	%tmp1 = call %0 @llvm.sadd.with.overflow.i32(i32 1, i32 0)
+	%tmp2 = extractvalue %0 %tmp1, 1
+	br i1 %tmp2, label %.backedge, label %BB3
+
+BB3:
+	%tmp4 = extractvalue %0 %tmp1, 0
+	br label %.backedge
+
+.backedge:
+	ret i32 0
+}




From rafael.espindola at gmail.com  Sun Apr 12 05:43:49 2009
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Sun, 12 Apr 2009 10:43:49 -0000
Subject: [llvm-commits] [llvm] r68901 - in /llvm/trunk/test/CodeGen/X86:
 tls1-pic.ll tls2-pic.ll tls3-pic.ll tls4-pic.ll
Message-ID: <200904121043.n3CAhoVj027137@zion.cs.uiuc.edu>

Author: rafael
Date: Sun Apr 12 05:43:41 2009
New Revision: 68901

URL: http://llvm.org/viewvc/llvm-project?rev=68901&view=rev
Log:
Add tests for the parts of X86-64 TLS that are already implemented.


Modified:
    llvm/trunk/test/CodeGen/X86/tls1-pic.ll
    llvm/trunk/test/CodeGen/X86/tls2-pic.ll
    llvm/trunk/test/CodeGen/X86/tls3-pic.ll
    llvm/trunk/test/CodeGen/X86/tls4-pic.ll

Modified: llvm/trunk/test/CodeGen/X86/tls1-pic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls1-pic.ll?rev=68901&r1=68900&r2=68901&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls1-pic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls1-pic.ll Sun Apr 12 05:43:41 2009
@@ -1,6 +1,9 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu -relocation-model=pic > %t
 ; RUN: grep {leal	i at TLSGD(,%ebx,1), %eax} %t
 ; RUN: grep {call	___tls_get_addr at PLT} %t
+; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu -relocation-model=pic > %t2
+; RUN: grep {leaq	i at TLSGD(%rip), %rdi} %t2
+; RUN: grep {call	__tls_get_addr at PLT} %t2
 
 @i = thread_local global i32 15
 

Modified: llvm/trunk/test/CodeGen/X86/tls2-pic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls2-pic.ll?rev=68901&r1=68900&r2=68901&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls2-pic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls2-pic.ll Sun Apr 12 05:43:41 2009
@@ -1,6 +1,9 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu -relocation-model=pic > %t
 ; RUN: grep {leal	i at TLSGD(,%ebx,1), %eax} %t
 ; RUN: grep {call	___tls_get_addr at PLT} %t
+; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu -relocation-model=pic > %t2
+; RUN: grep {leaq	i at TLSGD(%rip), %rdi} %t2
+; RUN: grep {call	__tls_get_addr at PLT} %t2
 
 @i = thread_local global i32 15
 

Modified: llvm/trunk/test/CodeGen/X86/tls3-pic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls3-pic.ll?rev=68901&r1=68900&r2=68901&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls3-pic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls3-pic.ll Sun Apr 12 05:43:41 2009
@@ -1,6 +1,9 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu -relocation-model=pic  > %t
 ; RUN: grep {leal	i at TLSGD(,%ebx,1), %eax} %t
 ; RUN: grep {call	___tls_get_addr at PLT} %t
+; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu -relocation-model=pic > %t2
+; RUN: grep {leaq	i at TLSGD(%rip), %rdi} %t2
+; RUN: grep {call	__tls_get_addr at PLT} %t2
 
 @i = external thread_local global i32		; <i32*> [#uses=2]
 

Modified: llvm/trunk/test/CodeGen/X86/tls4-pic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls4-pic.ll?rev=68901&r1=68900&r2=68901&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls4-pic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls4-pic.ll Sun Apr 12 05:43:41 2009
@@ -1,6 +1,9 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu -relocation-model=pic > %t
 ; RUN: grep {leal	i at TLSGD(,%ebx,1), %eax} %t
 ; RUN: grep {call	___tls_get_addr at PLT} %t
+; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu -relocation-model=pic > %t2
+; RUN: grep {leaq	i at TLSGD(%rip), %rdi} %t2
+; RUN: grep {call	__tls_get_addr at PLT} %t2
 
 @i = external thread_local global i32		; <i32*> [#uses=2]
 




From benny.kra at googlemail.com  Sun Apr 12 06:04:23 2009
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Sun, 12 Apr 2009 13:04:23 +0200
Subject: [llvm-commits] [PATCH] Fix strncat optimization
In-Reply-To: <F050600E-9346-4B10-B065-015E1367340A@apple.com>
References: <4A593B86-7D53-4BD5-A126-3FD0BDEB5265@gmail.com>
	<F050600E-9346-4B10-B065-015E1367340A@apple.com>
Message-ID: <82AD8062-86BE-4CE6-8BBE-1D072143133E@gmail.com>

There was a typo in my previous patch which leads to miscompilation of
strncat :(

strncat(foo, "bar", 99)
would be optimized to
memcpy(foo+strlen(foo), "bar", 100, 1)
instead of
memcpy(foo+strlen(foo), "bar", 4, 1)

The attached patch corrects this.

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From sabre at nondot.org  Sun Apr 12 13:22:33 2009
From: sabre at nondot.org (Chris Lattner)
Date: Sun, 12 Apr 2009 18:22:33 -0000
Subject: [llvm-commits] [llvm] r68905 -
	/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
Message-ID: <200904121822.n3CIMXmv009775@zion.cs.uiuc.edu>

Author: lattner
Date: Sun Apr 12 13:22:33 2009
New Revision: 68905

URL: http://llvm.org/viewvc/llvm-project?rev=68905&view=rev
Log:
"There was a typo in my previous patch which leads to miscompilation of
strncat :(

strncat(foo, "bar", 99)
would be optimized to
memcpy(foo+strlen(foo), "bar", 100, 1)
instead of
memcpy(foo+strlen(foo), "bar", 4, 1)"

Patch by Benjamin Kramer!


Modified:
    llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=68905&r1=68904&r2=68905&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Sun Apr 12 13:22:33 2009
@@ -582,7 +582,7 @@
 
     // strncat(x, s, c) -> strcat(x, s)
     // s is constant so the strcat can be optimized further
-    EmitStrLenMemCpy(Src, Dst, Len, B);
+    EmitStrLenMemCpy(Src, Dst, SrcLen, B);
     return Dst;
   }
 };




From clattner at apple.com  Sun Apr 12 13:22:55 2009
From: clattner at apple.com (Chris Lattner)
Date: Sun, 12 Apr 2009 11:22:55 -0700
Subject: [llvm-commits] [PATCH] Fix strncat optimization
In-Reply-To: <82AD8062-86BE-4CE6-8BBE-1D072143133E@gmail.com>
References: <4A593B86-7D53-4BD5-A126-3FD0BDEB5265@gmail.com>
	<F050600E-9346-4B10-B065-015E1367340A@apple.com>
	<82AD8062-86BE-4CE6-8BBE-1D072143133E@gmail.com>
Message-ID: <5E31F661-8A6F-4A88-803C-010654BE90AF@apple.com>


On Apr 12, 2009, at 4:04 AM, Benjamin Kramer wrote:

> There was a typo in my previous patch which leads to miscompilation of
> strncat :(
>
> strncat(foo, "bar", 99)
> would be optimized to
> memcpy(foo+strlen(foo), "bar", 100, 1)
> instead of
> memcpy(foo+strlen(foo), "bar", 4, 1)

Nice catch, I'm sorry I missed this in the review.  Applied here:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090406/076229.html


From nicholas at mxc.ca  Sun Apr 12 15:15:45 2009
From: nicholas at mxc.ca (Nick Lewycky)
Date: Sun, 12 Apr 2009 20:15:45 -0000
Subject: [llvm-commits] [llvm] r68910 - in /llvm/trunk/docs/tutorial:
 JITTutorial1.html JITTutorial2.html
Message-ID: <200904122015.n3CKFjYH013527@zion.cs.uiuc.edu>

Author: nicholas
Date: Sun Apr 12 15:15:44 2009
New Revision: 68910

URL: http://llvm.org/viewvc/llvm-project?rev=68910&view=rev
Log:
Fix compile error. Pointed out by mait on #llvm IRC!

Modified:
    llvm/trunk/docs/tutorial/JITTutorial1.html
    llvm/trunk/docs/tutorial/JITTutorial2.html

Modified: llvm/trunk/docs/tutorial/JITTutorial1.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/JITTutorial1.html?rev=68910&r1=68909&r2=68910&view=diff

==============================================================================
--- llvm/trunk/docs/tutorial/JITTutorial1.html (original)
+++ llvm/trunk/docs/tutorial/JITTutorial1.html Sun Apr 12 15:15:44 2009
@@ -78,7 +78,7 @@
   verifyModule(*Mod, PrintMessageAction);
 
   PassManager PM;
-  PM.add(new PrintModulePass(&amp;llvm::cout));
+  PM.add(createPrintModulePass(&amp;llvm::cout));
   PM.run(*Mod);
 
   delete Mod;

Modified: llvm/trunk/docs/tutorial/JITTutorial2.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/JITTutorial2.html?rev=68910&r1=68909&r2=68910&view=diff

==============================================================================
--- llvm/trunk/docs/tutorial/JITTutorial2.html (original)
+++ llvm/trunk/docs/tutorial/JITTutorial2.html Sun Apr 12 15:15:44 2009
@@ -68,7 +68,7 @@
   verifyModule(*Mod, PrintMessageAction);
   
   PassManager PM;
-  PM.add(new PrintModulePass(&amp;llvm::cout));
+  PM.add(createPrintModulePass(&amp;llvm::cout));
   PM.run(*Mod);
 
   delete Mod;  




From nicholas at mxc.ca  Sun Apr 12 15:47:24 2009
From: nicholas at mxc.ca (Nick Lewycky)
Date: Sun, 12 Apr 2009 20:47:24 -0000
Subject: [llvm-commits] [llvm] r68912 - in /llvm/trunk/examples:
 CMakeLists.txt Kaleidoscope/ Kaleidoscope/CMakeLists.txt
 Kaleidoscope/Makefile Kaleidoscope/toy.cpp Makefile
Message-ID: <200904122047.n3CKlOGL014503@zion.cs.uiuc.edu>

Author: nicholas
Date: Sun Apr 12 15:47:23 2009
New Revision: 68912

URL: http://llvm.org/viewvc/llvm-project?rev=68912&view=rev
Log:
Add Kaleidoscope to examples/ so that it gets built regularly and we'll notice
if an API change causes it to be out of date. The code is copied out of
LangImpl7.html.

Added:
    llvm/trunk/examples/Kaleidoscope/   (with props)
    llvm/trunk/examples/Kaleidoscope/CMakeLists.txt
    llvm/trunk/examples/Kaleidoscope/Makefile
    llvm/trunk/examples/Kaleidoscope/toy.cpp
Modified:
    llvm/trunk/examples/CMakeLists.txt
    llvm/trunk/examples/Makefile

Modified: llvm/trunk/examples/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/CMakeLists.txt?rev=68912&r1=68911&r2=68912&view=diff

==============================================================================
--- llvm/trunk/examples/CMakeLists.txt (original)
+++ llvm/trunk/examples/CMakeLists.txt Sun Apr 12 15:47:23 2009
@@ -1,6 +1,7 @@
 add_subdirectory(BrainF)
 add_subdirectory(Fibonacci)
 add_subdirectory(HowToUseJIT)
+add_subdirectory(Kaleidoscope)
 add_subdirectory(ModuleMaker)
 
 include(CheckIncludeFile)

Propchange: llvm/trunk/examples/Kaleidoscope/

------------------------------------------------------------------------------
--- svn:ignore (added)
+++ svn:ignore Sun Apr 12 15:47:23 2009
@@ -0,0 +1,4 @@
+Debug
+Release
+Release-Asserts
+

Added: llvm/trunk/examples/Kaleidoscope/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/CMakeLists.txt?rev=68912&view=auto

==============================================================================
--- llvm/trunk/examples/Kaleidoscope/CMakeLists.txt (added)
+++ llvm/trunk/examples/Kaleidoscope/CMakeLists.txt Sun Apr 12 15:47:23 2009
@@ -0,0 +1,5 @@
+set(LLVM_LINK_COMPONENTS core jit native)
+
+add_llvm_example(Kaleidoscope
+  toy.cpp
+  )

Added: llvm/trunk/examples/Kaleidoscope/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Makefile?rev=68912&view=auto

==============================================================================
--- llvm/trunk/examples/Kaleidoscope/Makefile (added)
+++ llvm/trunk/examples/Kaleidoscope/Makefile Sun Apr 12 15:47:23 2009
@@ -0,0 +1,15 @@
+##===- examples/Kaleidoscope/Makefile ----------------------*- Makefile -*-===##
+# 
+#                     The LLVM Compiler Infrastructure
+#
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+# 
+##===----------------------------------------------------------------------===##
+LEVEL = ../..
+TOOLNAME = Kaleidoscope
+EXAMPLE_TOOL = 1
+
+LINK_COMPONENTS := core jit native
+
+include $(LEVEL)/Makefile.common

Added: llvm/trunk/examples/Kaleidoscope/toy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/toy.cpp?rev=68912&view=auto

==============================================================================
--- llvm/trunk/examples/Kaleidoscope/toy.cpp (added)
+++ llvm/trunk/examples/Kaleidoscope/toy.cpp Sun Apr 12 15:47:23 2009
@@ -0,0 +1,1137 @@
+#include "llvm/DerivedTypes.h"
+#include "llvm/ExecutionEngine/ExecutionEngine.h"
+#include "llvm/Module.h"
+#include "llvm/ModuleProvider.h"
+#include "llvm/PassManager.h"
+#include "llvm/Analysis/Verifier.h"
+#include "llvm/Target/TargetData.h"
+#include "llvm/Transforms/Scalar.h"
+#include "llvm/Support/IRBuilder.h"
+#include <cstdio>
+#include <string>
+#include <map>
+#include <vector>
+using namespace llvm;
+
+//===----------------------------------------------------------------------===//
+// Lexer
+//===----------------------------------------------------------------------===//
+
+// The lexer returns tokens [0-255] if it is an unknown character, otherwise one
+// of these for known things.
+enum Token {
+  tok_eof = -1,
+
+  // commands
+  tok_def = -2, tok_extern = -3,
+
+  // primary
+  tok_identifier = -4, tok_number = -5,
+  
+  // control
+  tok_if = -6, tok_then = -7, tok_else = -8,
+  tok_for = -9, tok_in = -10,
+  
+  // operators
+  tok_binary = -11, tok_unary = -12,
+  
+  // var definition
+  tok_var = -13
+};
+
+static std::string IdentifierStr;  // Filled in if tok_identifier
+static double NumVal;              // Filled in if tok_number
+
+/// gettok - Return the next token from standard input.
+static int gettok() {
+  static int LastChar = ' ';
+
+  // Skip any whitespace.
+  while (isspace(LastChar))
+    LastChar = getchar();
+
+  if (isalpha(LastChar)) { // identifier: [a-zA-Z][a-zA-Z0-9]*
+    IdentifierStr = LastChar;
+    while (isalnum((LastChar = getchar())))
+      IdentifierStr += LastChar;
+
+    if (IdentifierStr == "def") return tok_def;
+    if (IdentifierStr == "extern") return tok_extern;
+    if (IdentifierStr == "if") return tok_if;
+    if (IdentifierStr == "then") return tok_then;
+    if (IdentifierStr == "else") return tok_else;
+    if (IdentifierStr == "for") return tok_for;
+    if (IdentifierStr == "in") return tok_in;
+    if (IdentifierStr == "binary") return tok_binary;
+    if (IdentifierStr == "unary") return tok_unary;
+    if (IdentifierStr == "var") return tok_var;
+    return tok_identifier;
+  }
+
+  if (isdigit(LastChar) || LastChar == '.') {   // Number: [0-9.]+
+    std::string NumStr;
+    do {
+      NumStr += LastChar;
+      LastChar = getchar();
+    } while (isdigit(LastChar) || LastChar == '.');
+
+    NumVal = strtod(NumStr.c_str(), 0);
+    return tok_number;
+  }
+
+  if (LastChar == '#') {
+    // Comment until end of line.
+    do LastChar = getchar();
+    while (LastChar != EOF && LastChar != '\n' && LastChar != '\r');
+    
+    if (LastChar != EOF)
+      return gettok();
+  }
+  
+  // Check for end of file.  Don't eat the EOF.
+  if (LastChar == EOF)
+    return tok_eof;
+
+  // Otherwise, just return the character as its ascii value.
+  int ThisChar = LastChar;
+  LastChar = getchar();
+  return ThisChar;
+}
+
+//===----------------------------------------------------------------------===//
+// Abstract Syntax Tree (aka Parse Tree)
+//===----------------------------------------------------------------------===//
+
+/// ExprAST - Base class for all expression nodes.
+class ExprAST {
+public:
+  virtual ~ExprAST() {}
+  virtual Value *Codegen() = 0;
+};
+
+/// NumberExprAST - Expression class for numeric literals like "1.0".
+class NumberExprAST : public ExprAST {
+  double Val;
+public:
+  NumberExprAST(double val) : Val(val) {}
+  virtual Value *Codegen();
+};
+
+/// VariableExprAST - Expression class for referencing a variable, like "a".
+class VariableExprAST : public ExprAST {
+  std::string Name;
+public:
+  VariableExprAST(const std::string &name) : Name(name) {}
+  const std::string &getName() const { return Name; }
+  virtual Value *Codegen();
+};
+
+/// UnaryExprAST - Expression class for a unary operator.
+class UnaryExprAST : public ExprAST {
+  char Opcode;
+  ExprAST *Operand;
+public:
+  UnaryExprAST(char opcode, ExprAST *operand) 
+    : Opcode(opcode), Operand(operand) {}
+  virtual Value *Codegen();
+};
+
+/// BinaryExprAST - Expression class for a binary operator.
+class BinaryExprAST : public ExprAST {
+  char Op;
+  ExprAST *LHS, *RHS;
+public:
+  BinaryExprAST(char op, ExprAST *lhs, ExprAST *rhs) 
+    : Op(op), LHS(lhs), RHS(rhs) {}
+  virtual Value *Codegen();
+};
+
+/// CallExprAST - Expression class for function calls.
+class CallExprAST : public ExprAST {
+  std::string Callee;
+  std::vector<ExprAST*> Args;
+public:
+  CallExprAST(const std::string &callee, std::vector<ExprAST*> &args)
+    : Callee(callee), Args(args) {}
+  virtual Value *Codegen();
+};
+
+/// IfExprAST - Expression class for if/then/else.
+class IfExprAST : public ExprAST {
+  ExprAST *Cond, *Then, *Else;
+public:
+  IfExprAST(ExprAST *cond, ExprAST *then, ExprAST *_else)
+  : Cond(cond), Then(then), Else(_else) {}
+  virtual Value *Codegen();
+};
+
+/// ForExprAST - Expression class for for/in.
+class ForExprAST : public ExprAST {
+  std::string VarName;
+  ExprAST *Start, *End, *Step, *Body;
+public:
+  ForExprAST(const std::string &varname, ExprAST *start, ExprAST *end,
+             ExprAST *step, ExprAST *body)
+    : VarName(varname), Start(start), End(end), Step(step), Body(body) {}
+  virtual Value *Codegen();
+};
+
+/// VarExprAST - Expression class for var/in
+class VarExprAST : public ExprAST {
+  std::vector<std::pair<std::string, ExprAST*> > VarNames;
+  ExprAST *Body;
+public:
+  VarExprAST(const std::vector<std::pair<std::string, ExprAST*> > &varnames,
+             ExprAST *body)
+  : VarNames(varnames), Body(body) {}
+  
+  virtual Value *Codegen();
+};
+
+/// PrototypeAST - This class represents the "prototype" for a function,
+/// which captures its argument names as well as if it is an operator.
+class PrototypeAST {
+  std::string Name;
+  std::vector<std::string> Args;
+  bool isOperator;
+  unsigned Precedence;  // Precedence if a binary op.
+public:
+  PrototypeAST(const std::string &name, const std::vector<std::string> &args,
+               bool isoperator = false, unsigned prec = 0)
+  : Name(name), Args(args), isOperator(isoperator), Precedence(prec) {}
+  
+  bool isUnaryOp() const { return isOperator && Args.size() == 1; }
+  bool isBinaryOp() const { return isOperator && Args.size() == 2; }
+  
+  char getOperatorName() const {
+    assert(isUnaryOp() || isBinaryOp());
+    return Name[Name.size()-1];
+  }
+  
+  unsigned getBinaryPrecedence() const { return Precedence; }
+  
+  Function *Codegen();
+  
+  void CreateArgumentAllocas(Function *F);
+};
+
+/// FunctionAST - This class represents a function definition itself.
+class FunctionAST {
+  PrototypeAST *Proto;
+  ExprAST *Body;
+public:
+  FunctionAST(PrototypeAST *proto, ExprAST *body)
+    : Proto(proto), Body(body) {}
+  
+  Function *Codegen();
+};
+
+//===----------------------------------------------------------------------===//
+// Parser
+//===----------------------------------------------------------------------===//
+
+/// CurTok/getNextToken - Provide a simple token buffer.  CurTok is the current
+/// token the parser it looking at.  getNextToken reads another token from the
+/// lexer and updates CurTok with its results.
+static int CurTok;
+static int getNextToken() {
+  return CurTok = gettok();
+}
+
+/// BinopPrecedence - This holds the precedence for each binary operator that is
+/// defined.
+static std::map<char, int> BinopPrecedence;
+
+/// GetTokPrecedence - Get the precedence of the pending binary operator token.
+static int GetTokPrecedence() {
+  if (!isascii(CurTok))
+    return -1;
+  
+  // Make sure it's a declared binop.
+  int TokPrec = BinopPrecedence[CurTok];
+  if (TokPrec <= 0) return -1;
+  return TokPrec;
+}
+
+/// Error* - These are little helper functions for error handling.
+ExprAST *Error(const char *Str) { fprintf(stderr, "Error: %s\n", Str);return 0;}
+PrototypeAST *ErrorP(const char *Str) { Error(Str); return 0; }
+FunctionAST *ErrorF(const char *Str) { Error(Str); return 0; }
+
+static ExprAST *ParseExpression();
+
+/// identifierexpr
+///   ::= identifier
+///   ::= identifier '(' expression* ')'
+static ExprAST *ParseIdentifierExpr() {
+  std::string IdName = IdentifierStr;
+  
+  getNextToken();  // eat identifier.
+  
+  if (CurTok != '(') // Simple variable ref.
+    return new VariableExprAST(IdName);
+  
+  // Call.
+  getNextToken();  // eat (
+  std::vector<ExprAST*> Args;
+  if (CurTok != ')') {
+    while (1) {
+      ExprAST *Arg = ParseExpression();
+      if (!Arg) return 0;
+      Args.push_back(Arg);
+      
+      if (CurTok == ')') break;
+      
+      if (CurTok != ',')
+        return Error("Expected ')' or ',' in argument list");
+      getNextToken();
+    }
+  }
+
+  // Eat the ')'.
+  getNextToken();
+  
+  return new CallExprAST(IdName, Args);
+}
+
+/// numberexpr ::= number
+static ExprAST *ParseNumberExpr() {
+  ExprAST *Result = new NumberExprAST(NumVal);
+  getNextToken(); // consume the number
+  return Result;
+}
+
+/// parenexpr ::= '(' expression ')'
+static ExprAST *ParseParenExpr() {
+  getNextToken();  // eat (.
+  ExprAST *V = ParseExpression();
+  if (!V) return 0;
+  
+  if (CurTok != ')')
+    return Error("expected ')'");
+  getNextToken();  // eat ).
+  return V;
+}
+
+/// ifexpr ::= 'if' expression 'then' expression 'else' expression
+static ExprAST *ParseIfExpr() {
+  getNextToken();  // eat the if.
+  
+  // condition.
+  ExprAST *Cond = ParseExpression();
+  if (!Cond) return 0;
+  
+  if (CurTok != tok_then)
+    return Error("expected then");
+  getNextToken();  // eat the then
+  
+  ExprAST *Then = ParseExpression();
+  if (Then == 0) return 0;
+  
+  if (CurTok != tok_else)
+    return Error("expected else");
+  
+  getNextToken();
+  
+  ExprAST *Else = ParseExpression();
+  if (!Else) return 0;
+  
+  return new IfExprAST(Cond, Then, Else);
+}
+
+/// forexpr ::= 'for' identifier '=' expr ',' expr (',' expr)? 'in' expression
+static ExprAST *ParseForExpr() {
+  getNextToken();  // eat the for.
+
+  if (CurTok != tok_identifier)
+    return Error("expected identifier after for");
+  
+  std::string IdName = IdentifierStr;
+  getNextToken();  // eat identifier.
+  
+  if (CurTok != '=')
+    return Error("expected '=' after for");
+  getNextToken();  // eat '='.
+  
+  
+  ExprAST *Start = ParseExpression();
+  if (Start == 0) return 0;
+  if (CurTok != ',')
+    return Error("expected ',' after for start value");
+  getNextToken();
+  
+  ExprAST *End = ParseExpression();
+  if (End == 0) return 0;
+  
+  // The step value is optional.
+  ExprAST *Step = 0;
+  if (CurTok == ',') {
+    getNextToken();
+    Step = ParseExpression();
+    if (Step == 0) return 0;
+  }
+  
+  if (CurTok != tok_in)
+    return Error("expected 'in' after for");
+  getNextToken();  // eat 'in'.
+  
+  ExprAST *Body = ParseExpression();
+  if (Body == 0) return 0;
+
+  return new ForExprAST(IdName, Start, End, Step, Body);
+}
+
+/// varexpr ::= 'var' identifier ('=' expression)? 
+//                    (',' identifier ('=' expression)?)* 'in' expression
+static ExprAST *ParseVarExpr() {
+  getNextToken();  // eat the var.
+
+  std::vector<std::pair<std::string, ExprAST*> > VarNames;
+
+  // At least one variable name is required.
+  if (CurTok != tok_identifier)
+    return Error("expected identifier after var");
+  
+  while (1) {
+    std::string Name = IdentifierStr;
+    getNextToken();  // eat identifier.
+
+    // Read the optional initializer.
+    ExprAST *Init = 0;
+    if (CurTok == '=') {
+      getNextToken(); // eat the '='.
+      
+      Init = ParseExpression();
+      if (Init == 0) return 0;
+    }
+    
+    VarNames.push_back(std::make_pair(Name, Init));
+    
+    // End of var list, exit loop.
+    if (CurTok != ',') break;
+    getNextToken(); // eat the ','.
+    
+    if (CurTok != tok_identifier)
+      return Error("expected identifier list after var");
+  }
+  
+  // At this point, we have to have 'in'.
+  if (CurTok != tok_in)
+    return Error("expected 'in' keyword after 'var'");
+  getNextToken();  // eat 'in'.
+  
+  ExprAST *Body = ParseExpression();
+  if (Body == 0) return 0;
+  
+  return new VarExprAST(VarNames, Body);
+}
+
+
+/// primary
+///   ::= identifierexpr
+///   ::= numberexpr
+///   ::= parenexpr
+///   ::= ifexpr
+///   ::= forexpr
+///   ::= varexpr
+static ExprAST *ParsePrimary() {
+  switch (CurTok) {
+  default: return Error("unknown token when expecting an expression");
+  case tok_identifier: return ParseIdentifierExpr();
+  case tok_number:     return ParseNumberExpr();
+  case '(':            return ParseParenExpr();
+  case tok_if:         return ParseIfExpr();
+  case tok_for:        return ParseForExpr();
+  case tok_var:        return ParseVarExpr();
+  }
+}
+
+/// unary
+///   ::= primary
+///   ::= '!' unary
+static ExprAST *ParseUnary() {
+  // If the current token is not an operator, it must be a primary expr.
+  if (!isascii(CurTok) || CurTok == '(' || CurTok == ',')
+    return ParsePrimary();
+  
+  // If this is a unary operator, read it.
+  int Opc = CurTok;
+  getNextToken();
+  if (ExprAST *Operand = ParseUnary())
+    return new UnaryExprAST(Opc, Operand);
+  return 0;
+}
+
+/// binoprhs
+///   ::= ('+' unary)*
+static ExprAST *ParseBinOpRHS(int ExprPrec, ExprAST *LHS) {
+  // If this is a binop, find its precedence.
+  while (1) {
+    int TokPrec = GetTokPrecedence();
+    
+    // If this is a binop that binds at least as tightly as the current binop,
+    // consume it, otherwise we are done.
+    if (TokPrec < ExprPrec)
+      return LHS;
+    
+    // Okay, we know this is a binop.
+    int BinOp = CurTok;
+    getNextToken();  // eat binop
+    
+    // Parse the unary expression after the binary operator.
+    ExprAST *RHS = ParseUnary();
+    if (!RHS) return 0;
+    
+    // If BinOp binds less tightly with RHS than the operator after RHS, let
+    // the pending operator take RHS as its LHS.
+    int NextPrec = GetTokPrecedence();
+    if (TokPrec < NextPrec) {
+      RHS = ParseBinOpRHS(TokPrec+1, RHS);
+      if (RHS == 0) return 0;
+    }
+    
+    // Merge LHS/RHS.
+    LHS = new BinaryExprAST(BinOp, LHS, RHS);
+  }
+}
+
+/// expression
+///   ::= unary binoprhs
+///
+static ExprAST *ParseExpression() {
+  ExprAST *LHS = ParseUnary();
+  if (!LHS) return 0;
+  
+  return ParseBinOpRHS(0, LHS);
+}
+
+/// prototype
+///   ::= id '(' id* ')'
+///   ::= binary LETTER number? (id, id)
+///   ::= unary LETTER (id)
+static PrototypeAST *ParsePrototype() {
+  std::string FnName;
+  
+  int Kind = 0;  // 0 = identifier, 1 = unary, 2 = binary.
+  unsigned BinaryPrecedence = 30;
+  
+  switch (CurTok) {
+  default:
+    return ErrorP("Expected function name in prototype");
+  case tok_identifier:
+    FnName = IdentifierStr;
+    Kind = 0;
+    getNextToken();
+    break;
+  case tok_unary:
+    getNextToken();
+    if (!isascii(CurTok))
+      return ErrorP("Expected unary operator");
+    FnName = "unary";
+    FnName += (char)CurTok;
+    Kind = 1;
+    getNextToken();
+    break;
+  case tok_binary:
+    getNextToken();
+    if (!isascii(CurTok))
+      return ErrorP("Expected binary operator");
+    FnName = "binary";
+    FnName += (char)CurTok;
+    Kind = 2;
+    getNextToken();
+    
+    // Read the precedence if present.
+    if (CurTok == tok_number) {
+      if (NumVal < 1 || NumVal > 100)
+        return ErrorP("Invalid precedecnce: must be 1..100");
+      BinaryPrecedence = (unsigned)NumVal;
+      getNextToken();
+    }
+    break;
+  }
+  
+  if (CurTok != '(')
+    return ErrorP("Expected '(' in prototype");
+  
+  std::vector<std::string> ArgNames;
+  while (getNextToken() == tok_identifier)
+    ArgNames.push_back(IdentifierStr);
+  if (CurTok != ')')
+    return ErrorP("Expected ')' in prototype");
+  
+  // success.
+  getNextToken();  // eat ')'.
+  
+  // Verify right number of names for operator.
+  if (Kind && ArgNames.size() != Kind)
+    return ErrorP("Invalid number of operands for operator");
+  
+  return new PrototypeAST(FnName, ArgNames, Kind != 0, BinaryPrecedence);
+}
+
+/// definition ::= 'def' prototype expression
+static FunctionAST *ParseDefinition() {
+  getNextToken();  // eat def.
+  PrototypeAST *Proto = ParsePrototype();
+  if (Proto == 0) return 0;
+
+  if (ExprAST *E = ParseExpression())
+    return new FunctionAST(Proto, E);
+  return 0;
+}
+
+/// toplevelexpr ::= expression
+static FunctionAST *ParseTopLevelExpr() {
+  if (ExprAST *E = ParseExpression()) {
+    // Make an anonymous proto.
+    PrototypeAST *Proto = new PrototypeAST("", std::vector<std::string>());
+    return new FunctionAST(Proto, E);
+  }
+  return 0;
+}
+
+/// external ::= 'extern' prototype
+static PrototypeAST *ParseExtern() {
+  getNextToken();  // eat extern.
+  return ParsePrototype();
+}
+
+//===----------------------------------------------------------------------===//
+// Code Generation
+//===----------------------------------------------------------------------===//
+
+static Module *TheModule;
+static IRBuilder<> Builder;
+static std::map<std::string, AllocaInst*> NamedValues;
+static FunctionPassManager *TheFPM;
+
+Value *ErrorV(const char *Str) { Error(Str); return 0; }
+
+/// CreateEntryBlockAlloca - Create an alloca instruction in the entry block of
+/// the function.  This is used for mutable variables etc.
+static AllocaInst *CreateEntryBlockAlloca(Function *TheFunction,
+                                          const std::string &VarName) {
+  IRBuilder<> TmpB(&TheFunction->getEntryBlock(),
+                 TheFunction->getEntryBlock().begin());
+  return TmpB.CreateAlloca(Type::DoubleTy, 0, VarName.c_str());
+}
+
+
+Value *NumberExprAST::Codegen() {
+  return ConstantFP::get(APFloat(Val));
+}
+
+Value *VariableExprAST::Codegen() {
+  // Look this variable up in the function.
+  Value *V = NamedValues[Name];
+  if (V == 0) return ErrorV("Unknown variable name");
+
+  // Load the value.
+  return Builder.CreateLoad(V, Name.c_str());
+}
+
+Value *UnaryExprAST::Codegen() {
+  Value *OperandV = Operand->Codegen();
+  if (OperandV == 0) return 0;
+  
+  Function *F = TheModule->getFunction(std::string("unary")+Opcode);
+  if (F == 0)
+    return ErrorV("Unknown unary operator");
+  
+  return Builder.CreateCall(F, OperandV, "unop");
+}
+
+
+Value *BinaryExprAST::Codegen() {
+  // Special case '=' because we don't want to emit the LHS as an expression.
+  if (Op == '=') {
+    // Assignment requires the LHS to be an identifier.
+    VariableExprAST *LHSE = dynamic_cast<VariableExprAST*>(LHS);
+    if (!LHSE)
+      return ErrorV("destination of '=' must be a variable");
+    // Codegen the RHS.
+    Value *Val = RHS->Codegen();
+    if (Val == 0) return 0;
+
+    // Look up the name.
+    Value *Variable = NamedValues[LHSE->getName()];
+    if (Variable == 0) return ErrorV("Unknown variable name");
+
+    Builder.CreateStore(Val, Variable);
+    return Val;
+  }
+  
+  
+  Value *L = LHS->Codegen();
+  Value *R = RHS->Codegen();
+  if (L == 0 || R == 0) return 0;
+  
+  switch (Op) {
+  case '+': return Builder.CreateAdd(L, R, "addtmp");
+  case '-': return Builder.CreateSub(L, R, "subtmp");
+  case '*': return Builder.CreateMul(L, R, "multmp");
+  case '<':
+    L = Builder.CreateFCmpULT(L, R, "cmptmp");
+    // Convert bool 0/1 to double 0.0 or 1.0
+    return Builder.CreateUIToFP(L, Type::DoubleTy, "booltmp");
+  default: break;
+  }
+  
+  // If it wasn't a builtin binary operator, it must be a user defined one. Emit
+  // a call to it.
+  Function *F = TheModule->getFunction(std::string("binary")+Op);
+  assert(F && "binary operator not found!");
+  
+  Value *Ops[] = { L, R };
+  return Builder.CreateCall(F, Ops, Ops+2, "binop");
+}
+
+Value *CallExprAST::Codegen() {
+  // Look up the name in the global module table.
+  Function *CalleeF = TheModule->getFunction(Callee);
+  if (CalleeF == 0)
+    return ErrorV("Unknown function referenced");
+  
+  // If argument mismatch error.
+  if (CalleeF->arg_size() != Args.size())
+    return ErrorV("Incorrect # arguments passed");
+
+  std::vector<Value*> ArgsV;
+  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
+    ArgsV.push_back(Args[i]->Codegen());
+    if (ArgsV.back() == 0) return 0;
+  }
+  
+  return Builder.CreateCall(CalleeF, ArgsV.begin(), ArgsV.end(), "calltmp");
+}
+
+Value *IfExprAST::Codegen() {
+  Value *CondV = Cond->Codegen();
+  if (CondV == 0) return 0;
+  
+  // Convert condition to a bool by comparing equal to 0.0.
+  CondV = Builder.CreateFCmpONE(CondV, 
+                                ConstantFP::get(APFloat(0.0)),
+                                "ifcond");
+  
+  Function *TheFunction = Builder.GetInsertBlock()->getParent();
+  
+  // Create blocks for the then and else cases.  Insert the 'then' block at the
+  // end of the function.
+  BasicBlock *ThenBB = BasicBlock::Create("then", TheFunction);
+  BasicBlock *ElseBB = BasicBlock::Create("else");
+  BasicBlock *MergeBB = BasicBlock::Create("ifcont");
+  
+  Builder.CreateCondBr(CondV, ThenBB, ElseBB);
+  
+  // Emit then value.
+  Builder.SetInsertPoint(ThenBB);
+  
+  Value *ThenV = Then->Codegen();
+  if (ThenV == 0) return 0;
+  
+  Builder.CreateBr(MergeBB);
+  // Codegen of 'Then' can change the current block, update ThenBB for the PHI.
+  ThenBB = Builder.GetInsertBlock();
+  
+  // Emit else block.
+  TheFunction->getBasicBlockList().push_back(ElseBB);
+  Builder.SetInsertPoint(ElseBB);
+  
+  Value *ElseV = Else->Codegen();
+  if (ElseV == 0) return 0;
+  
+  Builder.CreateBr(MergeBB);
+  // Codegen of 'Else' can change the current block, update ElseBB for the PHI.
+  ElseBB = Builder.GetInsertBlock();
+  
+  // Emit merge block.
+  TheFunction->getBasicBlockList().push_back(MergeBB);
+  Builder.SetInsertPoint(MergeBB);
+  PHINode *PN = Builder.CreatePHI(Type::DoubleTy, "iftmp");
+  
+  PN->addIncoming(ThenV, ThenBB);
+  PN->addIncoming(ElseV, ElseBB);
+  return PN;
+}
+
+Value *ForExprAST::Codegen() {
+  // Output this as:
+  //   var = alloca double
+  //   ...
+  //   start = startexpr
+  //   store start -> var
+  //   goto loop
+  // loop: 
+  //   ...
+  //   bodyexpr
+  //   ...
+  // loopend:
+  //   step = stepexpr
+  //   endcond = endexpr
+  //
+  //   curvar = load var
+  //   nextvar = curvar + step
+  //   store nextvar -> var
+  //   br endcond, loop, endloop
+  // outloop:
+  
+  Function *TheFunction = Builder.GetInsertBlock()->getParent();
+
+  // Create an alloca for the variable in the entry block.
+  AllocaInst *Alloca = CreateEntryBlockAlloca(TheFunction, VarName);
+  
+  // Emit the start code first, without 'variable' in scope.
+  Value *StartVal = Start->Codegen();
+  if (StartVal == 0) return 0;
+  
+  // Store the value into the alloca.
+  Builder.CreateStore(StartVal, Alloca);
+  
+  // Make the new basic block for the loop header, inserting after current
+  // block.
+  BasicBlock *PreheaderBB = Builder.GetInsertBlock();
+  BasicBlock *LoopBB = BasicBlock::Create("loop", TheFunction);
+  
+  // Insert an explicit fall through from the current block to the LoopBB.
+  Builder.CreateBr(LoopBB);
+
+  // Start insertion in LoopBB.
+  Builder.SetInsertPoint(LoopBB);
+  
+  // Within the loop, the variable is defined equal to the PHI node.  If it
+  // shadows an existing variable, we have to restore it, so save it now.
+  AllocaInst *OldVal = NamedValues[VarName];
+  NamedValues[VarName] = Alloca;
+  
+  // Emit the body of the loop.  This, like any other expr, can change the
+  // current BB.  Note that we ignore the value computed by the body, but don't
+  // allow an error.
+  if (Body->Codegen() == 0)
+    return 0;
+  
+  // Emit the step value.
+  Value *StepVal;
+  if (Step) {
+    StepVal = Step->Codegen();
+    if (StepVal == 0) return 0;
+  } else {
+    // If not specified, use 1.0.
+    StepVal = ConstantFP::get(APFloat(1.0));
+  }
+  
+  // Compute the end condition.
+  Value *EndCond = End->Codegen();
+  if (EndCond == 0) return EndCond;
+  
+  // Reload, increment, and restore the alloca.  This handles the case where
+  // the body of the loop mutates the variable.
+  Value *CurVar = Builder.CreateLoad(Alloca, VarName.c_str());
+  Value *NextVar = Builder.CreateAdd(CurVar, StepVal, "nextvar");
+  Builder.CreateStore(NextVar, Alloca);
+  
+  // Convert condition to a bool by comparing equal to 0.0.
+  EndCond = Builder.CreateFCmpONE(EndCond, 
+                                  ConstantFP::get(APFloat(0.0)),
+                                  "loopcond");
+  
+  // Create the "after loop" block and insert it.
+  BasicBlock *LoopEndBB = Builder.GetInsertBlock();
+  BasicBlock *AfterBB = BasicBlock::Create("afterloop", TheFunction);
+  
+  // Insert the conditional branch into the end of LoopEndBB.
+  Builder.CreateCondBr(EndCond, LoopBB, AfterBB);
+  
+  // Any new code will be inserted in AfterBB.
+  Builder.SetInsertPoint(AfterBB);
+  
+  // Restore the unshadowed variable.
+  if (OldVal)
+    NamedValues[VarName] = OldVal;
+  else
+    NamedValues.erase(VarName);
+
+  
+  // for expr always returns 0.0.
+  return Constant::getNullValue(Type::DoubleTy);
+}
+
+Value *VarExprAST::Codegen() {
+  std::vector<AllocaInst *> OldBindings;
+  
+  Function *TheFunction = Builder.GetInsertBlock()->getParent();
+
+  // Register all variables and emit their initializer.
+  for (unsigned i = 0, e = VarNames.size(); i != e; ++i) {
+    const std::string &VarName = VarNames[i].first;
+    ExprAST *Init = VarNames[i].second;
+    
+    // Emit the initializer before adding the variable to scope, this prevents
+    // the initializer from referencing the variable itself, and permits stuff
+    // like this:
+    //  var a = 1 in
+    //    var a = a in ...   # refers to outer 'a'.
+    Value *InitVal;
+    if (Init) {
+      InitVal = Init->Codegen();
+      if (InitVal == 0) return 0;
+    } else { // If not specified, use 0.0.
+      InitVal = ConstantFP::get(APFloat(0.0));
+    }
+    
+    AllocaInst *Alloca = CreateEntryBlockAlloca(TheFunction, VarName);
+    Builder.CreateStore(InitVal, Alloca);
+
+    // Remember the old variable binding so that we can restore the binding when
+    // we unrecurse.
+    OldBindings.push_back(NamedValues[VarName]);
+    
+    // Remember this binding.
+    NamedValues[VarName] = Alloca;
+  }
+  
+  // Codegen the body, now that all vars are in scope.
+  Value *BodyVal = Body->Codegen();
+  if (BodyVal == 0) return 0;
+  
+  // Pop all our variables from scope.
+  for (unsigned i = 0, e = VarNames.size(); i != e; ++i)
+    NamedValues[VarNames[i].first] = OldBindings[i];
+
+  // Return the body computation.
+  return BodyVal;
+}
+
+
+Function *PrototypeAST::Codegen() {
+  // Make the function type:  double(double,double) etc.
+  std::vector<const Type*> Doubles(Args.size(), Type::DoubleTy);
+  FunctionType *FT = FunctionType::get(Type::DoubleTy, Doubles, false);
+  
+  Function *F = Function::Create(FT, Function::ExternalLinkage, Name, TheModule);
+  
+  // If F conflicted, there was already something named 'Name'.  If it has a
+  // body, don't allow redefinition or reextern.
+  if (F->getName() != Name) {
+    // Delete the one we just made and get the existing one.
+    F->eraseFromParent();
+    F = TheModule->getFunction(Name);
+    
+    // If F already has a body, reject this.
+    if (!F->empty()) {
+      ErrorF("redefinition of function");
+      return 0;
+    }
+    
+    // If F took a different number of args, reject.
+    if (F->arg_size() != Args.size()) {
+      ErrorF("redefinition of function with different # args");
+      return 0;
+    }
+  }
+  
+  // Set names for all arguments.
+  unsigned Idx = 0;
+  for (Function::arg_iterator AI = F->arg_begin(); Idx != Args.size();
+       ++AI, ++Idx)
+    AI->setName(Args[Idx]);
+    
+  return F;
+}
+
+/// CreateArgumentAllocas - Create an alloca for each argument and register the
+/// argument in the symbol table so that references to it will succeed.
+void PrototypeAST::CreateArgumentAllocas(Function *F) {
+  Function::arg_iterator AI = F->arg_begin();
+  for (unsigned Idx = 0, e = Args.size(); Idx != e; ++Idx, ++AI) {
+    // Create an alloca for this variable.
+    AllocaInst *Alloca = CreateEntryBlockAlloca(F, Args[Idx]);
+
+    // Store the initial value into the alloca.
+    Builder.CreateStore(AI, Alloca);
+
+    // Add arguments to variable symbol table.
+    NamedValues[Args[Idx]] = Alloca;
+  }
+}
+
+
+Function *FunctionAST::Codegen() {
+  NamedValues.clear();
+  
+  Function *TheFunction = Proto->Codegen();
+  if (TheFunction == 0)
+    return 0;
+  
+  // If this is an operator, install it.
+  if (Proto->isBinaryOp())
+    BinopPrecedence[Proto->getOperatorName()] = Proto->getBinaryPrecedence();
+  
+  // Create a new basic block to start insertion into.
+  BasicBlock *BB = BasicBlock::Create("entry", TheFunction);
+  Builder.SetInsertPoint(BB);
+  
+  // Add all arguments to the symbol table and create their allocas.
+  Proto->CreateArgumentAllocas(TheFunction);
+  
+  if (Value *RetVal = Body->Codegen()) {
+    // Finish off the function.
+    Builder.CreateRet(RetVal);
+
+    // Validate the generated code, checking for consistency.
+    verifyFunction(*TheFunction);
+
+    // Optimize the function.
+    TheFPM->run(*TheFunction);
+    
+    return TheFunction;
+  }
+  
+  // Error reading body, remove function.
+  TheFunction->eraseFromParent();
+
+  if (Proto->isBinaryOp())
+    BinopPrecedence.erase(Proto->getOperatorName());
+  return 0;
+}
+
+//===----------------------------------------------------------------------===//
+// Top-Level parsing and JIT Driver
+//===----------------------------------------------------------------------===//
+
+static ExecutionEngine *TheExecutionEngine;
+
+static void HandleDefinition() {
+  if (FunctionAST *F = ParseDefinition()) {
+    if (Function *LF = F->Codegen()) {
+      fprintf(stderr, "Read function definition:");
+      LF->dump();
+    }
+  } else {
+    // Skip token for error recovery.
+    getNextToken();
+  }
+}
+
+static void HandleExtern() {
+  if (PrototypeAST *P = ParseExtern()) {
+    if (Function *F = P->Codegen()) {
+      fprintf(stderr, "Read extern: ");
+      F->dump();
+    }
+  } else {
+    // Skip token for error recovery.
+    getNextToken();
+  }
+}
+
+static void HandleTopLevelExpression() {
+  // Evaluate a top level expression into an anonymous function.
+  if (FunctionAST *F = ParseTopLevelExpr()) {
+    if (Function *LF = F->Codegen()) {
+      // JIT the function, returning a function pointer.
+      void *FPtr = TheExecutionEngine->getPointerToFunction(LF);
+      
+      // Cast it to the right type (takes no arguments, returns a double) so we
+      // can call it as a native function.
+      double (*FP)() = (double (*)())FPtr;
+      fprintf(stderr, "Evaluated to %f\n", FP());
+    }
+  } else {
+    // Skip token for error recovery.
+    getNextToken();
+  }
+}
+
+/// top ::= definition | external | expression | ';'
+static void MainLoop() {
+  while (1) {
+    fprintf(stderr, "ready> ");
+    switch (CurTok) {
+    case tok_eof:    return;
+    case ';':        getNextToken(); break;  // ignore top level semicolons.
+    case tok_def:    HandleDefinition(); break;
+    case tok_extern: HandleExtern(); break;
+    default:         HandleTopLevelExpression(); break;
+    }
+  }
+}
+
+
+
+//===----------------------------------------------------------------------===//
+// "Library" functions that can be "extern'd" from user code.
+//===----------------------------------------------------------------------===//
+
+/// putchard - putchar that takes a double and returns 0.
+extern "C" 
+double putchard(double X) {
+  putchar((char)X);
+  return 0;
+}
+
+/// printd - printf that takes a double prints it as "%f\n", returning 0.
+extern "C" 
+double printd(double X) {
+  printf("%f\n", X);
+  return 0;
+}
+
+//===----------------------------------------------------------------------===//
+// Main driver code.
+//===----------------------------------------------------------------------===//
+
+int main() {
+  // Install standard binary operators.
+  // 1 is lowest precedence.
+  BinopPrecedence['='] = 2;
+  BinopPrecedence['<'] = 10;
+  BinopPrecedence['+'] = 20;
+  BinopPrecedence['-'] = 20;
+  BinopPrecedence['*'] = 40;  // highest.
+
+  // Prime the first token.
+  fprintf(stderr, "ready> ");
+  getNextToken();
+
+  // Make the module, which holds all the code.
+  TheModule = new Module("my cool jit");
+  
+  // Create the JIT.
+  TheExecutionEngine = ExecutionEngine::create(TheModule);
+
+  {
+    ExistingModuleProvider OurModuleProvider(TheModule);
+    FunctionPassManager OurFPM(&OurModuleProvider);
+      
+    // Set up the optimizer pipeline.  Start with registering info about how the
+    // target lays out data structures.
+    OurFPM.add(new TargetData(*TheExecutionEngine->getTargetData()));
+    // Promote allocas to registers.
+    OurFPM.add(createPromoteMemoryToRegisterPass());
+    // Do simple "peephole" optimizations and bit-twiddling optzns.
+    OurFPM.add(createInstructionCombiningPass());
+    // Reassociate expressions.
+    OurFPM.add(createReassociatePass());
+    // Eliminate Common SubExpressions.
+    OurFPM.add(createGVNPass());
+    // Simplify the control flow graph (deleting unreachable blocks, etc).
+    OurFPM.add(createCFGSimplificationPass());
+
+    // Set the global so the code gen can use this.
+    TheFPM = &OurFPM;
+
+    // Run the main "interpreter loop" now.
+    MainLoop();
+    
+    TheFPM = 0;
+    
+    // Print out all of the generated code.
+    TheModule->dump();
+    
+  }  // Free module provider (and thus the module) and pass manager.
+  
+  return 0;
+}
+

Modified: llvm/trunk/examples/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Makefile?rev=68912&r1=68911&r2=68912&view=diff

==============================================================================
--- llvm/trunk/examples/Makefile (original)
+++ llvm/trunk/examples/Makefile Sun Apr 12 15:47:23 2009
@@ -10,7 +10,7 @@
 
 include $(LEVEL)/Makefile.config
 
-PARALLEL_DIRS:= BrainF Fibonacci HowToUseJIT ModuleMaker
+PARALLEL_DIRS:= BrainF Fibonacci HowToUseJIT Kaleidoscope ModuleMaker
 
 ifeq ($(HAVE_PTHREAD),1)
 PARALLEL_DIRS += ParallelJIT 




From rafael.espindola at gmail.com  Sun Apr 12 16:55:04 2009
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Sun, 12 Apr 2009 21:55:04 -0000
Subject: [llvm-commits] [llvm] r68915 -
	/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Message-ID: <200904122155.n3CLt4CN016730@zion.cs.uiuc.edu>

Author: rafael
Date: Sun Apr 12 16:55:03 2009
New Revision: 68915

URL: http://llvm.org/viewvc/llvm-project?rev=68915&view=rev
Log:
refactor some code into X86DAGToDAGISel::MatchWrapper

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=68915&r1=68914&r2=68915&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Sun Apr 12 16:55:03 2009
@@ -162,6 +162,7 @@
 
     bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM);
     bool MatchLoad(SDValue N, X86ISelAddressMode &AM);
+    bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
     bool MatchAddress(SDValue N, X86ISelAddressMode &AM,
                       unsigned Depth = 0);
     bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
@@ -782,6 +783,53 @@
   return true;
 }
 
+bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
+  bool is64Bit = Subtarget->is64Bit();
+  DOUT << "Wrapper: 64bit " << is64Bit;
+  DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n";
+  // Under X86-64 non-small code model, GV (and friends) are 64-bits.
+  // Also, base and index reg must be 0 in order to use rip as base.
+  if (is64Bit && (TM.getCodeModel() != CodeModel::Small ||
+                  AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
+    return true;
+  if (AM.hasSymbolicDisplacement())
+    return true;
+  // If value is available in a register both base and index components have
+  // been picked, we can't fit the result available in the register in the
+  // addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
+
+  SDValue N0 = N.getOperand(0);
+  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
+    uint64_t Offset = G->getOffset();
+    if (!is64Bit || isInt32(AM.Disp + Offset)) {
+      GlobalValue *GV = G->getGlobal();
+      AM.GV = GV;
+      AM.Disp += Offset;
+      AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
+      return false;
+    }
+  } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
+    uint64_t Offset = CP->getOffset();
+    if (!is64Bit || isInt32(AM.Disp + Offset)) {
+      AM.CP = CP->getConstVal();
+      AM.Align = CP->getAlignment();
+      AM.Disp += Offset;
+      AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
+      return false;
+    }
+  } else if (ExternalSymbolSDNode *S =dyn_cast<ExternalSymbolSDNode>(N0)) {
+    AM.ES = S->getSymbol();
+    AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
+    return false;
+  } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
+    AM.JT = J->getIndex();
+    AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
+    return false;
+  }
+
+  return true;
+}
+
 /// MatchAddress - Add the specified node to the specified addressing mode,
 /// returning true if it cannot be done.  This just pattern matches for the
 /// addressing mode.
@@ -822,51 +870,10 @@
       return false;
     break;
 
-  case X86ISD::Wrapper: {
-    DOUT << "Wrapper: 64bit " << is64Bit;
-    DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n";
-    // Under X86-64 non-small code model, GV (and friends) are 64-bits.
-    // Also, base and index reg must be 0 in order to use rip as base.
-    if (is64Bit && (TM.getCodeModel() != CodeModel::Small ||
-                    AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
-      break;
-    if (AM.hasSymbolicDisplacement())
-      break;
-    // If value is available in a register both base and index components have
-    // been picked, we can't fit the result available in the register in the
-    // addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
-    {
-      SDValue N0 = N.getOperand(0);
-      if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
-        uint64_t Offset = G->getOffset();
-        if (!is64Bit || isInt32(AM.Disp + Offset)) {
-          GlobalValue *GV = G->getGlobal();
-          AM.GV = GV;
-          AM.Disp += Offset;
-          AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
-          return false;
-        }
-      } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
-        uint64_t Offset = CP->getOffset();
-        if (!is64Bit || isInt32(AM.Disp + Offset)) {
-          AM.CP = CP->getConstVal();
-          AM.Align = CP->getAlignment();
-          AM.Disp += Offset;
-          AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
-          return false;
-        }
-      } else if (ExternalSymbolSDNode *S =dyn_cast<ExternalSymbolSDNode>(N0)) {
-        AM.ES = S->getSymbol();
-        AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
-        return false;
-      } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
-        AM.JT = J->getIndex();
-        AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
-        return false;
-      }
-    }
+  case X86ISD::Wrapper:
+    if (!MatchWrapper(N, AM))
+      return false;
     break;
-  }
 
   case ISD::LOAD:
     if (!MatchLoad(N, AM))




From resistor at mac.com  Sun Apr 12 17:31:17 2009
From: resistor at mac.com (Owen Anderson)
Date: Sun, 12 Apr 2009 22:31:17 -0000
Subject: [llvm-commits] [llvm] r68922 -
	/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
Message-ID: <200904122231.n3CMVHho018078@zion.cs.uiuc.edu>

Author: resistor
Date: Sun Apr 12 17:31:17 2009
New Revision: 68922

URL: http://llvm.org/viewvc/llvm-project?rev=68922&view=rev
Log:
Use a hashtable for TargetRegisterClass::contains.

Modified:
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=68922&r1=68921&r2=68922&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Sun Apr 12 17:31:17 2009
@@ -18,6 +18,7 @@
 
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/ValueTypes.h"
+#include "llvm/ADT/DenseSet.h"
 #include <cassert>
 #include <functional>
 
@@ -64,6 +65,7 @@
   const unsigned RegSize, Alignment;    // Size & Alignment of register in bytes
   const int CopyCost;
   const iterator RegsBegin, RegsEnd;
+  DenseSet<unsigned> RegSet;
 public:
   TargetRegisterClass(unsigned id,
                       const char *name,
@@ -73,7 +75,10 @@
                       unsigned RS, unsigned Al, int CC,
                       iterator RB, iterator RE)
     : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
-    RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {}
+    RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {
+      for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
+        RegSet.insert(*I);
+    }
   virtual ~TargetRegisterClass() {}     // Allow subclasses
   
   /// getID() - Return the register class ID number.
@@ -103,9 +108,7 @@
   /// contains - Return true if the specified register is included in this
   /// register class.
   bool contains(unsigned Reg) const {
-    for (iterator I = begin(), E = end(); I != E; ++I)
-      if (*I == Reg) return true;
-    return false;
+    return RegSet.count(Reg);
   }
 
   /// hasType - return true if this TargetRegisterClass has the ValueType vt.




From rafael.espindola at gmail.com  Sun Apr 12 18:00:40 2009
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Sun, 12 Apr 2009 23:00:40 -0000
Subject: [llvm-commits] [llvm] r68924 - in /llvm/trunk:
 lib/Target/X86/X86ISelDAGToDAG.cpp test/CodeGen/X86/2009-04-12-picrel.ll
 test/CodeGen/X86/abi-isel.ll
Message-ID: <200904122300.n3CN0emJ019212@zion.cs.uiuc.edu>

Author: rafael
Date: Sun Apr 12 18:00:38 2009
New Revision: 68924

URL: http://llvm.org/viewvc/llvm-project?rev=68924&view=rev
Log:
In X86DAGToDAGISel::MatchWrapper, if base or index are set, avoid matching
only if symbolic addresses are RIP relatives.


Added:
    llvm/trunk/test/CodeGen/X86/2009-04-12-picrel.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/X86/abi-isel.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=68924&r1=68923&r2=68924&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Sun Apr 12 18:00:38 2009
@@ -787,11 +787,16 @@
   bool is64Bit = Subtarget->is64Bit();
   DOUT << "Wrapper: 64bit " << is64Bit;
   DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n";
+
   // Under X86-64 non-small code model, GV (and friends) are 64-bits.
-  // Also, base and index reg must be 0 in order to use rip as base.
-  if (is64Bit && (TM.getCodeModel() != CodeModel::Small ||
-                  AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
+  if (is64Bit && (TM.getCodeModel() != CodeModel::Small))
+    return true;
+
+  // Base and index reg must be 0 in order to use rip as base.
+  bool canUsePICRel = !AM.Base.Reg.getNode() && !AM.IndexReg.getNode();
+  if (is64Bit && !canUsePICRel && TM.symbolicAddressesAreRIPRel())
     return true;
+
   if (AM.hasSymbolicDisplacement())
     return true;
   // If value is available in a register both base and index components have

Added: llvm/trunk/test/CodeGen/X86/2009-04-12-picrel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-12-picrel.ll?rev=68924&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-04-12-picrel.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2009-04-12-picrel.ll Sun Apr 12 18:00:38 2009
@@ -0,0 +1,13 @@
+; RUN: llvm-as < %s | llc -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=static -code-model=small > %t
+; RUN: grep leaq %t | count 1
+
+ at dst = external global [131072 x i32]
+ at ptr = external global i32*
+
+define void @off01(i64 %i) nounwind {
+entry:
+	%.sum = add i64 %i, 16
+	%0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %.sum
+	store i32* %0, i32** @ptr, align 8
+	ret void
+}

Modified: llvm/trunk/test/CodeGen/X86/abi-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/abi-isel.ll?rev=68924&r1=68923&r2=68924&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/abi-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/abi-isel.ll Sun Apr 12 18:00:38 2009
@@ -43,7 +43,7 @@
 ; RUN: grep movl %t | count 91
 ; RUN: not grep addl %t
 ; RUN: not grep subl %t
-; RUN: grep leaq %t | count 93
+; RUN: grep leaq %t | count 70
 ; RUN: grep movq %t | count 56
 ; RUN: grep addq %t | count 20
 ; RUN: grep subq %t | count 14
@@ -57,7 +57,7 @@
 ; RUN: not grep @PLT %t
 ; RUN: not grep @PLTOFF %t
 ; RUN: grep {call	\\\*} %t | count 10
-; RUN: grep {%rip} %t | count 162
+; RUN: grep {%rip} %t | count 139
 ; RUN: llvm-as < %s | llc -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=pic -code-model=small > %t
 ; RUN: not grep leal %t
 ; RUN: grep movl %t | count 98
@@ -146,7 +146,7 @@
 ; RUN: grep movl %t | count 91
 ; RUN: not grep addl %t
 ; RUN: not grep subl %t
-; RUN: grep leaq %t | count 93
+; RUN: grep leaq %t | count 70
 ; RUN: grep movq %t | count 56
 ; RUN: grep addq %t | count 20
 ; RUN: grep subq %t | count 14
@@ -160,7 +160,7 @@
 ; RUN: not grep @PLT %t
 ; RUN: not grep @PLTOFF %t
 ; RUN: grep {call	\\\*} %t | count 10
-; RUN: grep {%rip} %t | count 162
+; RUN: grep {%rip} %t | count 139
 ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small > %t
 ; RUN: not grep leal %t
 ; RUN: grep movl %t | count 95




From sabre at nondot.org  Sun Apr 12 18:33:14 2009
From: sabre at nondot.org (Chris Lattner)
Date: Sun, 12 Apr 2009 23:33:14 -0000
Subject: [llvm-commits] [llvm] r68929 -
	/llvm/trunk/lib/System/Unix/Signals.inc
Message-ID: <200904122333.n3CNXEtF020442@zion.cs.uiuc.edu>

Author: lattner
Date: Sun Apr 12 18:33:13 2009
New Revision: 68929

URL: http://llvm.org/viewvc/llvm-project?rev=68929&view=rev
Log:
fix PR3965:SIGINT handler not restored after calling ParseAST(),
patch by Alexei Svitkine!

Modified:
    llvm/trunk/lib/System/Unix/Signals.inc

Modified: llvm/trunk/lib/System/Unix/Signals.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Signals.inc?rev=68929&r1=68928&r2=68929&view=diff

==============================================================================
--- llvm/trunk/lib/System/Unix/Signals.inc (original)
+++ llvm/trunk/lib/System/Unix/Signals.inc Sun Apr 12 18:33:13 2009
@@ -126,7 +126,8 @@
       IF();        // run the interrupt function.
       return;
     }
-    exit(1);   // If this is an interrupt signal, exit the program
+    raise(Sig);   // Execute the default handler.
+    return;
   }
 
   // Otherwise if it is a fault (like SEGV) run any handler.




From jyasskin at google.com  Sun Apr 12 19:16:49 2009
From: jyasskin at google.com (Jeffrey Yasskin)
Date: Sun, 12 Apr 2009 17:16:49 -0700
Subject: [llvm-commits] TypeBuilder helper class
In-Reply-To: <5F5A9B7F-1967-4D07-9D74-20466088C123@apple.com>
References: <bb55930e0904021137i3199acb6j3108bc4c2819d9c5@mail.gmail.com>
	<bb55930e0904090940o5686c16er9f8f87e9ca302ed5@mail.gmail.com>
	<5F5A9B7F-1967-4D07-9D74-20466088C123@apple.com>
Message-ID: <bb55930e0904121716j19c85efdxbadff2f727315df4@mail.gmail.com>

On Thu, Apr 9, 2009 at 11:38 PM, Chris Lattner <clattner at apple.com> wrote:
>
> On Apr 9, 2009, at 9:40 AM, Jeffrey Yasskin wrote:
>
>>
>> I think I see how to define TypeBuilder<typename T, bool
>> restrict_to_cross_compilable_types> so that TypeBuilder<size_t, true>
>> fails to compile but TypeBuilder<sometype<64>, false> succeeds,
>> without duplicating code. Could you confirm that that's along the
>> lines of what you want implemented before I waste time implementing
>> it? Also, what's the right spelling for "sometype"? I'd vote for
>> llvm::types::i<N> or something similar.
>>
>
> Sounds great to me!

Ok, here's the new version. I'm not entirely happy with using a bool
for this decision since it makes user code harder to read. I could use
an enum or distinct subtypes, but then I'd need names. "Host" seems to
work for the version that accepts types like 'size_t', but
"CrossCompilable" seems too long for the version that doesn't.
Thoughts?

I also don't have any tests that TypeBuilder<size_t, true> correctly
fails to compile. dejagnu could do it in theory, but Nick tells me
that it doesn't work for code that calls into LLVM.

Jeffrey
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From nicholas at mxc.ca  Sun Apr 12 21:03:40 2009
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 13 Apr 2009 02:03:40 -0000
Subject: [llvm-commits] [llvm] r68934 - /llvm/trunk/docs/GoldPlugin.html
Message-ID: <200904130203.n3D23eCU025900@zion.cs.uiuc.edu>

Author: nicholas
Date: Sun Apr 12 21:03:40 2009
New Revision: 68934

URL: http://llvm.org/viewvc/llvm-project?rev=68934&view=rev
Log:
Add paragraph tags.

Modified:
    llvm/trunk/docs/GoldPlugin.html

Modified: llvm/trunk/docs/GoldPlugin.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GoldPlugin.html?rev=68934&r1=68933&r2=68934&view=diff

==============================================================================
--- llvm/trunk/docs/GoldPlugin.html (original)
+++ llvm/trunk/docs/GoldPlugin.html Sun Apr 12 21:03:40 2009
@@ -139,10 +139,10 @@
 <div class="doc_section"><a name="licensing">Licensing</a></div>
 <!--=========================================================================-->
 <div class="doc_text">
-Gold is licensed under the GPLv3. LLVMgold uses the interface file
+  <p>Gold is licensed under the GPLv3. LLVMgold uses the interface file
 <tt>plugin-api.h</tt> from gold which means that the resulting LLVMgold.so
 binary is also GPLv3. This can still be used to link non-GPLv3 programs just
-as much as gold could without the plugin.
+as much as gold could without the plugin.</p>
 </div>
 
 <!-- *********************************************************************** -->




From nicholas at mxc.ca  Sun Apr 12 23:26:06 2009
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 13 Apr 2009 04:26:06 -0000
Subject: [llvm-commits] [llvm] r68937 - in /llvm/trunk: Makefile.config.in
 autoconf/configure.ac lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp
Message-ID: <200904130426.n3D4Q6IO030280@zion.cs.uiuc.edu>

Author: nicholas
Date: Sun Apr 12 23:26:06 2009
New Revision: 68937

URL: http://llvm.org/viewvc/llvm-project?rev=68937&view=rev
Log:
Link against libffi if available, fall back to "no external calls from
interpreter mode" when it's not.

Modified:
    llvm/trunk/Makefile.config.in
    llvm/trunk/autoconf/configure.ac
    llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp

Modified: llvm/trunk/Makefile.config.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.config.in?rev=68937&r1=68936&r2=68937&view=diff

==============================================================================
--- llvm/trunk/Makefile.config.in (original)
+++ llvm/trunk/Makefile.config.in Sun Apr 12 23:26:06 2009
@@ -289,6 +289,3 @@
 
 # Location of the plugin header file for gold.
 BINUTILS_INCDIR := @BINUTILS_INCDIR@
-
-# Can we use libFFI for the interpreter?
-HAVE_FFI := @HAVE_FFI@

Modified: llvm/trunk/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=68937&r1=68936&r2=68937&view=diff

==============================================================================
--- llvm/trunk/autoconf/configure.ac (original)
+++ llvm/trunk/autoconf/configure.ac Sun Apr 12 23:26:06 2009
@@ -737,8 +737,9 @@
                AC_MSG_WARN([dlopen() not found - disabling plugin support]))
 
 dnl libffi is optional; used to call external functions from the interpreter
-AC_CHECK_LIB(ffi,ffi_call,[have_libffi=1],
-             AC_MSG_WARN([libffi not found - disabling external calls from interpreter]))
+AC_SEARCH_LIBS(ffi_call,ffi,AC_DEFINE([HAVE_FFI_CALL],[1],
+               [Define if libffi is available on this platform.]),
+               AC_MSG_WARN([libffi not found - disabling external calls from interpreter]))
 
 dnl mallinfo is optional; the code can compile (minus features) without it
 AC_SEARCH_LIBS(mallinfo,malloc,AC_DEFINE([HAVE_MALLINFO],[1],
@@ -802,10 +803,8 @@
   AC_SUBST(HAVE_PTHREAD, 0)
 fi
 
-dnl Once we know we have libffi, try to find ffi.h.
-if test -n "$have_libffi" ; then
-  AC_CHECK_HEADERS([ffi.h ffi/ffi.h], [AC_SUBST(HAVE_FFI, 1)])
-fi  
+dnl Try to find ffi.h.
+AC_CHECK_HEADERS([ffi.h ffi/ffi.h])
 
 dnl===-----------------------------------------------------------------------===
 dnl===

Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp?rev=68937&r1=68936&r2=68937&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp Sun Apr 12 23:26:06 2009
@@ -33,13 +33,13 @@
 #include <cmath>
 #include <cstring>
 
-#ifdef HAVE_FFI
+#ifdef HAVE_FFI_CALL
 #ifdef HAVE_FFI_H
 #include <ffi.h>
+#define USE_LIBFFI
 #elif HAVE_FFI_FFI_H
 #include <ffi/ffi.h>
-#else
-#error "Not sure where configure found ffi.h!"
+#define USE_LIBFFI
 #endif
 #endif
 
@@ -50,7 +50,7 @@
 static ManagedStatic<std::map<const Function *, ExFunc> > ExportedFunctions;
 static std::map<std::string, ExFunc> FuncNames;
 
-#ifdef HAVE_FFI
+#ifdef USE_LIBFFI
 typedef void (*RawFunc)(void);
 static ManagedStatic<std::map<const Function *, RawFunc> > RawFunctions;
 #endif
@@ -105,7 +105,7 @@
   return FnPtr;
 }
 
-#ifdef HAVE_FFI
+#ifdef USE_LIBFFI
 static ffi_type *ffiTypeFor(const Type *Ty) {
   switch (Ty->getTypeID()) {
     case Type::VoidTyID: return &ffi_type_void;
@@ -240,7 +240,7 @@
 
   return false;
 }
-#endif // HAVE_FFI
+#endif // USE_LIBFFI
 
 GenericValue Interpreter::callExternalFunction(Function *F,
                                      const std::vector<GenericValue> &ArgVals) {
@@ -253,7 +253,7 @@
                                                    : FI->second)
     return Fn(F->getFunctionType(), ArgVals);
 
-#ifdef HAVE_FFI
+#ifdef USE_LIBFFI
   std::map<const Function *, RawFunc>::iterator RF = RawFunctions->find(F);
   RawFunc RawFn;
   if (RF == RawFunctions->end()) {
@@ -268,7 +268,7 @@
   GenericValue Result;
   if (RawFn != 0 && ffiInvoke(RawFn, F, ArgVals, getTargetData(), Result))
     return Result;
-#endif // HAVE_FFI
+#endif // USE_LIBFFI
 
   cerr << "Tried to execute an unknown external function: "
        << F->getType()->getDescription() << " " << F->getName() << "\n";




From nicholas at mxc.ca  Sun Apr 12 23:26:27 2009
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 13 Apr 2009 04:26:27 -0000
Subject: [llvm-commits] [llvm] r68938 - in /llvm/trunk: configure
	include/llvm/Config/config.h.in
Message-ID: <200904130426.n3D4QSx0030302@zion.cs.uiuc.edu>

Author: nicholas
Date: Sun Apr 12 23:26:27 2009
New Revision: 68938

URL: http://llvm.org/viewvc/llvm-project?rev=68938&view=rev
Log:
Regenerate.

Modified:
    llvm/trunk/configure
    llvm/trunk/include/llvm/Config/config.h.in

Modified: llvm/trunk/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=68938&r1=68937&r2=68938&view=diff

==============================================================================
--- llvm/trunk/configure (original)
+++ llvm/trunk/configure Sun Apr 12 23:26:27 2009
@@ -900,7 +900,6 @@
 LLVMGXX
 USE_UDIS86
 HAVE_PTHREAD
-HAVE_FFI
 HUGE_VAL_SANITY
 ALLOCA
 MMAP_FILE
@@ -10544,7 +10543,7 @@
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<EOF
-#line 10547 "configure"
+#line 10546 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -12688,7 +12687,7 @@
   ;;
 *-*-irix6*)
   # Find out which ABI we are using.
-  echo '#line 12691 "configure"' > conftest.$ac_ext
+  echo '#line 12690 "configure"' > conftest.$ac_ext
   if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   (eval $ac_compile) 2>&5
   ac_status=$?
@@ -14406,11 +14405,11 @@
    -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
    -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
    -e 's:$: $lt_compiler_flag:'`
-   (eval echo "\"\$as_me:14409: $lt_compile\"" >&5)
+   (eval echo "\"\$as_me:14408: $lt_compile\"" >&5)
    (eval "$lt_compile" 2>conftest.err)
    ac_status=$?
    cat conftest.err >&5
-   echo "$as_me:14413: \$? = $ac_status" >&5
+   echo "$as_me:14412: \$? = $ac_status" >&5
    if (exit $ac_status) && test -s "$ac_outfile"; then
      # The compiler can only warn and ignore the option if not recognized
      # So say no if there are warnings other than the usual output.
@@ -14674,11 +14673,11 @@
    -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
    -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
    -e 's:$: $lt_compiler_flag:'`
-   (eval echo "\"\$as_me:14677: $lt_compile\"" >&5)
+   (eval echo "\"\$as_me:14676: $lt_compile\"" >&5)
    (eval "$lt_compile" 2>conftest.err)
    ac_status=$?
    cat conftest.err >&5
-   echo "$as_me:14681: \$? = $ac_status" >&5
+   echo "$as_me:14680: \$? = $ac_status" >&5
    if (exit $ac_status) && test -s "$ac_outfile"; then
      # The compiler can only warn and ignore the option if not recognized
      # So say no if there are warnings other than the usual output.
@@ -14778,11 +14777,11 @@
    -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
    -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
    -e 's:$: $lt_compiler_flag:'`
-   (eval echo "\"\$as_me:14781: $lt_compile\"" >&5)
+   (eval echo "\"\$as_me:14780: $lt_compile\"" >&5)
    (eval "$lt_compile" 2>out/conftest.err)
    ac_status=$?
    cat out/conftest.err >&5
-   echo "$as_me:14785: \$? = $ac_status" >&5
+   echo "$as_me:14784: \$? = $ac_status" >&5
    if (exit $ac_status) && test -s out/conftest2.$ac_objext
    then
      # The compiler can only warn and ignore the option if not recognized
@@ -17230,7 +17229,7 @@
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<EOF
-#line 17233 "configure"
+#line 17232 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -17330,7 +17329,7 @@
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<EOF
-#line 17333 "configure"
+#line 17332 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -19698,11 +19697,11 @@
    -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
    -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
    -e 's:$: $lt_compiler_flag:'`
-   (eval echo "\"\$as_me:19701: $lt_compile\"" >&5)
+   (eval echo "\"\$as_me:19700: $lt_compile\"" >&5)
    (eval "$lt_compile" 2>conftest.err)
    ac_status=$?
    cat conftest.err >&5
-   echo "$as_me:19705: \$? = $ac_status" >&5
+   echo "$as_me:19704: \$? = $ac_status" >&5
    if (exit $ac_status) && test -s "$ac_outfile"; then
      # The compiler can only warn and ignore the option if not recognized
      # So say no if there are warnings other than the usual output.
@@ -19802,11 +19801,11 @@
    -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
    -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
    -e 's:$: $lt_compiler_flag:'`
-   (eval echo "\"\$as_me:19805: $lt_compile\"" >&5)
+   (eval echo "\"\$as_me:19804: $lt_compile\"" >&5)
    (eval "$lt_compile" 2>out/conftest.err)
    ac_status=$?
    cat out/conftest.err >&5
-   echo "$as_me:19809: \$? = $ac_status" >&5
+   echo "$as_me:19808: \$? = $ac_status" >&5
    if (exit $ac_status) && test -s out/conftest2.$ac_objext
    then
      # The compiler can only warn and ignore the option if not recognized
@@ -21372,11 +21371,11 @@
    -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
    -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
    -e 's:$: $lt_compiler_flag:'`
-   (eval echo "\"\$as_me:21375: $lt_compile\"" >&5)
+   (eval echo "\"\$as_me:21374: $lt_compile\"" >&5)
    (eval "$lt_compile" 2>conftest.err)
    ac_status=$?
    cat conftest.err >&5
-   echo "$as_me:21379: \$? = $ac_status" >&5
+   echo "$as_me:21378: \$? = $ac_status" >&5
    if (exit $ac_status) && test -s "$ac_outfile"; then
      # The compiler can only warn and ignore the option if not recognized
      # So say no if there are warnings other than the usual output.
@@ -21476,11 +21475,11 @@
    -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
    -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
    -e 's:$: $lt_compiler_flag:'`
-   (eval echo "\"\$as_me:21479: $lt_compile\"" >&5)
+   (eval echo "\"\$as_me:21478: $lt_compile\"" >&5)
    (eval "$lt_compile" 2>out/conftest.err)
    ac_status=$?
    cat out/conftest.err >&5
-   echo "$as_me:21483: \$? = $ac_status" >&5
+   echo "$as_me:21482: \$? = $ac_status" >&5
    if (exit $ac_status) && test -s out/conftest2.$ac_objext
    then
      # The compiler can only warn and ignore the option if not recognized
@@ -23711,11 +23710,11 @@
    -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
    -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
    -e 's:$: $lt_compiler_flag:'`
-   (eval echo "\"\$as_me:23714: $lt_compile\"" >&5)
+   (eval echo "\"\$as_me:23713: $lt_compile\"" >&5)
    (eval "$lt_compile" 2>conftest.err)
    ac_status=$?
    cat conftest.err >&5
-   echo "$as_me:23718: \$? = $ac_status" >&5
+   echo "$as_me:23717: \$? = $ac_status" >&5
    if (exit $ac_status) && test -s "$ac_outfile"; then
      # The compiler can only warn and ignore the option if not recognized
      # So say no if there are warnings other than the usual output.
@@ -23979,11 +23978,11 @@
    -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
    -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
    -e 's:$: $lt_compiler_flag:'`
-   (eval echo "\"\$as_me:23982: $lt_compile\"" >&5)
+   (eval echo "\"\$as_me:23981: $lt_compile\"" >&5)
    (eval "$lt_compile" 2>conftest.err)
    ac_status=$?
    cat conftest.err >&5
-   echo "$as_me:23986: \$? = $ac_status" >&5
+   echo "$as_me:23985: \$? = $ac_status" >&5
    if (exit $ac_status) && test -s "$ac_outfile"; then
      # The compiler can only warn and ignore the option if not recognized
      # So say no if there are warnings other than the usual output.
@@ -24083,11 +24082,11 @@
    -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
    -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
    -e 's:$: $lt_compiler_flag:'`
-   (eval echo "\"\$as_me:24086: $lt_compile\"" >&5)
+   (eval echo "\"\$as_me:24085: $lt_compile\"" >&5)
    (eval "$lt_compile" 2>out/conftest.err)
    ac_status=$?
    cat out/conftest.err >&5
-   echo "$as_me:24090: \$? = $ac_status" >&5
+   echo "$as_me:24089: \$? = $ac_status" >&5
    if (exit $ac_status) && test -s out/conftest2.$ac_objext
    then
      # The compiler can only warn and ignore the option if not recognized
@@ -27427,13 +27426,12 @@
 fi
 
 
-{ echo "$as_me:$LINENO: checking for ffi_call in -lffi" >&5
-echo $ECHO_N "checking for ffi_call in -lffi... $ECHO_C" >&6; }
-if test "${ac_cv_lib_ffi_ffi_call+set}" = set; then
+{ echo "$as_me:$LINENO: checking for library containing ffi_call" >&5
+echo $ECHO_N "checking for library containing ffi_call... $ECHO_C" >&6; }
+if test "${ac_cv_search_ffi_call+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
-  ac_check_lib_save_LIBS=$LIBS
-LIBS="-lffi  $LIBS"
+  ac_func_search_save_LIBS=$LIBS
 cat >conftest.$ac_ext <<_ACEOF
 /* confdefs.h.  */
 _ACEOF
@@ -27456,7 +27454,14 @@
   return 0;
 }
 _ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
+for ac_lib in '' ffi; do
+  if test -z "$ac_lib"; then
+    ac_res="none required"
+  else
+    ac_res=-l$ac_lib
+    LIBS="-l$ac_lib  $ac_func_search_save_LIBS"
+  fi
+  rm -f conftest.$ac_objext conftest$ac_exeext
 if { (ac_try="$ac_link"
 case "(($ac_try" in
   *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
@@ -27490,22 +27495,38 @@
   ac_status=$?
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); }; }; then
-  ac_cv_lib_ffi_ffi_call=yes
+  ac_cv_search_ffi_call=$ac_res
 else
   echo "$as_me: failed program was:" >&5
 sed 's/^/| /' conftest.$ac_ext >&5
 
-	ac_cv_lib_ffi_ffi_call=no
+
 fi
 
 rm -f core conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-LIBS=$ac_check_lib_save_LIBS
+      conftest$ac_exeext
+  if test "${ac_cv_search_ffi_call+set}" = set; then
+  break
 fi
-{ echo "$as_me:$LINENO: result: $ac_cv_lib_ffi_ffi_call" >&5
-echo "${ECHO_T}$ac_cv_lib_ffi_ffi_call" >&6; }
-if test $ac_cv_lib_ffi_ffi_call = yes; then
-  have_libffi=1
+done
+if test "${ac_cv_search_ffi_call+set}" = set; then
+  :
+else
+  ac_cv_search_ffi_call=no
+fi
+rm conftest.$ac_ext
+LIBS=$ac_func_search_save_LIBS
+fi
+{ echo "$as_me:$LINENO: result: $ac_cv_search_ffi_call" >&5
+echo "${ECHO_T}$ac_cv_search_ffi_call" >&6; }
+ac_res=$ac_cv_search_ffi_call
+if test "$ac_res" != no; then
+  test "$ac_res" = "none required" || LIBS="$ac_res $LIBS"
+
+cat >>confdefs.h <<\_ACEOF
+#define HAVE_FFI_CALL 1
+_ACEOF
+
 else
   { echo "$as_me:$LINENO: WARNING: libffi not found - disabling external calls from interpreter" >&5
 echo "$as_me: WARNING: libffi not found - disabling external calls from interpreter" >&2;}
@@ -29754,7 +29775,6 @@
 
 fi
 
-if test -n "$have_libffi" ; then
 
 
 for ac_header in ffi.h ffi/ffi.h
@@ -29920,13 +29940,11 @@
   cat >>confdefs.h <<_ACEOF
 #define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
 _ACEOF
- HAVE_FFI=1
 
 fi
 
 done
 
-fi
 
 
 
@@ -34844,7 +34862,6 @@
 LLVMGXX!$LLVMGXX$ac_delim
 USE_UDIS86!$USE_UDIS86$ac_delim
 HAVE_PTHREAD!$HAVE_PTHREAD$ac_delim
-HAVE_FFI!$HAVE_FFI$ac_delim
 HUGE_VAL_SANITY!$HUGE_VAL_SANITY$ac_delim
 ALLOCA!$ALLOCA$ac_delim
 MMAP_FILE!$MMAP_FILE$ac_delim
@@ -34876,7 +34893,7 @@
 LTLIBOBJS!$LTLIBOBJS$ac_delim
 _ACEOF
 
-  if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 77; then
+  if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 76; then
     break
   elif $ac_last_try; then
     { { echo "$as_me:$LINENO: error: could not make $CONFIG_STATUS" >&5

Modified: llvm/trunk/include/llvm/Config/config.h.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.in?rev=68938&r1=68937&r2=68938&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Config/config.h.in (original)
+++ llvm/trunk/include/llvm/Config/config.h.in Sun Apr 12 23:26:27 2009
@@ -109,6 +109,9 @@
 /* Define to 1 if you have the <fcntl.h> header file. */
 #undef HAVE_FCNTL_H
 
+/* Define if libffi is available on this platform. */
+#undef HAVE_FFI_CALL
+
 /* Define to 1 if you have the <ffi/ffi.h> header file. */
 #undef HAVE_FFI_FFI_H